--- intel-gpu-tools-1.3.orig/Android.mk +++ intel-gpu-tools-1.3/Android.mk @@ -0,0 +1,531 @@ +LOCAL_PATH := $(call my-dir) +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_reg_write.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_reg_map.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + +LOCAL_MODULE := intel_reg_write +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_reg_read.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_reg_map.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_reg_read +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_disable_clock_gating.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_disable_clock_gating +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_audio_dump.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_audio_dump +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_backlight.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_backlight +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_bios_dumper.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_bios_dumper +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_bios_reader.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_bios_reader +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +# Disabling intel_error_decode tool, since Android still does not have libdrm2.4.30 +#================ +#include $(CLEAR_VARS) +# +#LOCAL_SRC_FILES := \ +# tools/intel_error_decode.c \ +# lib/intel_pci.c \ +# lib/intel_gpu_tools.h \ +# tools/intel_reg.h \ +# lib/intel_batchbuffer.h \ +# lib/intel_batchbuffer.c \ +# lib/intel_mmio.c \ +# tools/intel_chipset.h \ +# lib/instdone.h \ +# lib/instdone.c \ +# tools/intel_decode.h \ +# lib/intel_drm.c +# +# +#LOCAL_C_INCLUDES += \ +# $(LOCAL_PATH)/lib \ +# $(TOPDIR)hardware/intel/libdrm/include/drm \ +# $(TOPDIR)hardware/intel/libdrm/intel \ +# $(LOCAL_PATH)/../libpciaccess/include/ +# +#LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +#LOCAL_CFLAGS += -DANDROID +#LOCAL_CFLAGS += -std=c99 +# +# +#LOCAL_MODULE := intel_error_decode +#LOCAL_MODULE_TAGS := optional +# +#LOCAL_SHARED_LIBRARIES := libpciaccess \ +# libdrm \ +# libdrm_intel +# +#include $(BUILD_EXECUTABLE) +# +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_gpu_top.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h \ + lib/instdone.h \ + lib/instdone.c \ + lib/intel_reg_map.c + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_gpu_top +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_gpu_time.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_gpu_time +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_gtt.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 + +LOCAL_MODULE := intel_gtt +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_stepping.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_stepping +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_reg_dumper.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_reg_dumper +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/intel_reg_snapshot.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 + +LOCAL_MODULE := intel_reg_snapshot +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + tools/forcewaked.c \ + lib/intel_pci.c \ + lib/intel_gpu_tools.h \ + tools/intel_reg.h \ + lib/intel_batchbuffer.h \ + lib/intel_batchbuffer.c \ + lib/intel_mmio.c \ + tools/intel_chipset.h \ + lib/intel_reg_map.c \ + lib/intel_drm.c + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := forcewaked +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess \ + libdrm \ + libdrm_intel + +include $(BUILD_EXECUTABLE) + +#================ +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := \ + lib/intel_gpu_tools.h \ + tools/intel_reg_checker.c \ + lib/intel_pci.c \ + lib/intel_mmio.c + + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/lib \ + $(TOPDIR)hardware/intel/libdrm/include/drm \ + $(TOPDIR)hardware/intel/libdrm/intel \ + $(LOCAL_PATH)/../libpciaccess/include/ + +LOCAL_CFLAGS += -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 +LOCAL_CFLAGS += -DANDROID + + +LOCAL_MODULE := intel_reg_checker +LOCAL_MODULE_TAGS := optional + +LOCAL_SHARED_LIBRARIES := libpciaccess + +include $(BUILD_EXECUTABLE) + --- intel-gpu-tools-1.3.orig/autogen.sh +++ intel-gpu-tools-1.3/autogen.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +srcdir=`dirname $0` +test -z "$srcdir" && srcdir=. + +ORIGDIR=`pwd` +cd $srcdir + +autoreconf -v --install || exit 1 +cd $ORIGDIR || exit $? + +$srcdir/configure --enable-maintainer-mode "$@" --- intel-gpu-tools-1.3.orig/man/intel_reg_snapshot.man +++ intel-gpu-tools-1.3/man/intel_reg_snapshot.man @@ -0,0 +1,15 @@ +.\" shorthand for double quote that works everywhere. +.ds q \N'34' +.TH intel_reg_snapshot __appmansuffix__ __xorgversion__ +.SH NAME +intel_reg_snapshot \- Take a GPU register snapshot +.SH SYNOPSIS +.B intel_reg_snapshot +.SH DESCRIPTION +.B intel_reg_snapshot +takes a snapshot of the registers of an Intel GPU, and writes it to standard +output. These files can be inspected later with the +.B intel_reg_dumper +tool. +.SH SEE ALSO +.BR intel_reg_dumper(1) --- intel-gpu-tools-1.3.orig/debian/copyright +++ intel-gpu-tools-1.3/debian/copyright @@ -0,0 +1,70 @@ +This package was debianized by Eric Anholt on +Tue, 19 May 2009 15:00:52 -0700. + +It was downloaded from http://xorg.freedesktop.org/archive/individual/app/ + +Upstream Authors: + + Eric Anholt + Jesse Barnes + Keith Whitwell + Carl Worth + +Copyright: + + Copyright © 2005 Adam Jackson + Copyright © 2007-2009 Intel Corporation + Copyright 1998-1999, 2006 Tungsten Graphics, Inc., Cedar Park, Texas. + +License: +The code is covered by the MIT license. Most of it is under the common form +that just says "authors and copyright holders": + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice (including the next + paragraph) shall be included in all copies or substantial portions of the + Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + IN THE SOFTWARE. + +Some of the code is also under the MIT license but specifically mentions +Tungsten Graphics: + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sub license, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice (including the + next paragraph) shall be included in all copies or substantial portions + of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +The Debian packaging is: + + Copyright (C) 2009 Eric Anholt + +and is licensed under the GPL version 3, +see `/usr/share/common-licenses/GPL-3'. --- intel-gpu-tools-1.3.orig/debian/docs +++ intel-gpu-tools-1.3/debian/docs @@ -0,0 +1 @@ +README --- intel-gpu-tools-1.3.orig/debian/intel-gpu-tools.install +++ intel-gpu-tools-1.3/debian/intel-gpu-tools.install @@ -0,0 +1,2 @@ +usr/bin +usr/share/man --- intel-gpu-tools-1.3.orig/debian/compat +++ intel-gpu-tools-1.3/debian/compat @@ -0,0 +1 @@ +8 --- intel-gpu-tools-1.3.orig/debian/rules +++ intel-gpu-tools-1.3/debian/rules @@ -0,0 +1,21 @@ +#!/usr/bin/make -f + +# Disable test suite: +override_dh_auto_test: + echo 'Test suite disabled (does not perform a build check).' + +# Install in debian/tmp to retain control through dh_install: +override_dh_auto_install: + dh_auto_install --destdir=debian/tmp + +# Forget no-one: +override_dh_install: + dh_install --fail-missing + +%: + dh $@ --with quilt,autoreconf --builddirectory=build/ + +# For maintainer use only, generate a tarball: +gentarball: UV=$(shell dpkg-parsechangelog|awk '/^Version:/ {print $$2}'|sed 's/-.*$$//') +gentarball: + git archive --format=tar upstream-unstable --prefix=$(SOURCE)-$(UV)/ | gzip -9 > ../$(SOURCE)_$(UV).orig.tar.gz --- intel-gpu-tools-1.3.orig/debian/control +++ intel-gpu-tools-1.3/debian/control @@ -0,0 +1,32 @@ +Source: intel-gpu-tools +Section: x11 +Priority: optional +Maintainer: Ubuntu X-SWAT +XSBC-Original-Maintainer: Debian X Strike Force +Uploaders: Eric Anholt , Tormod Volden , Cyril Brulebois +Build-Depends: + debhelper (>= 8), + dh-autoreconf, + quilt, + pkg-config, + libpciaccess-dev (>= 0.10), + libdrm-dev, + libdrm-intel1 (>= 2.4.38), + libudev-dev, + libcairo2-dev, + xutils-dev (>= 1:7.6+6), +Standards-Version: 3.9.3 +Homepage: http://www.intellinuxgraphics.org/ +Vcs-Git: git://git.debian.org/git/pkg-xorg/app/intel-gpu-tools.git +Vcs-Browser: http://git.debian.org/?p=pkg-xorg/app/intel-gpu-tools.git + +Package: intel-gpu-tools +Architecture: amd64 i386 +Depends: + ${shlibs:Depends}, + ${misc:Depends}, +Conflicts: xserver-xorg-video-intel (<< 2.9.1) +Description: tools for debugging the Intel graphics driver + intel-gpu-tools is a package of tools for debugging the Intel graphics driver, + including a GPU hang dumping program, performance monitor, and performance + microbenchmarks for regression testing the DRM. --- intel-gpu-tools-1.3.orig/debian/watch +++ intel-gpu-tools-1.3/debian/watch @@ -0,0 +1,3 @@ +#git=git://anongit.freedesktop.org/app/intel-gpu-tools +version=3 +http://xorg.freedesktop.org/archive/individual/app/intel-gpu-tools-(.*)\.tar\.gz --- intel-gpu-tools-1.3.orig/debian/changelog +++ intel-gpu-tools-1.3/debian/changelog @@ -0,0 +1,117 @@ +intel-gpu-tools (1.3-0ubuntu2) quantal; urgency=low + + * Merge from debian git: + - control: Limit the architectures to amd64, i386. + + -- Timo Aaltonen Wed, 12 Sep 2012 18:50:55 +0300 + +intel-gpu-tools (1.3-0ubuntu1) quantal; urgency=low + + * Sync from unreleased debian git. + + -- Timo Aaltonen Fri, 07 Sep 2012 09:30:07 +0300 + +intel-gpu-tools (1.3-1) UNRELEASED; urgency=low + + * New upstream release. + * Drop patches + - 100_drmtest_exit_not_abort.patch - upstream + - 10-Revert-tests-make-testdisplay-non-optional.patch - build testdisplay + now. + - 20-Revert-Fix-pthread-compiler-flags-to-work-on-Solaris.patch + xorg-macros is new enough. + - 30-Revert-add-sprite-demo-from-Armin-Reese.patch - libdrm is new enough. + * control: Bump libdrm-dev build-dep + * control: Add libudev-dev to build-depends. + * control: Add libcairo2-dev to build-depends. + * rules: Stop renaming forcewaked. + * control: Bump standards-version to 3.9.3, no changes. + * control: Limit the architectures to amd64, i386. + + -- Timo Aaltonen Mon, 27 Aug 2012 11:55:43 +0300 + +intel-gpu-tools (1.2-1) unstable; urgency=low + + * New upstream release + * Add 10-Revert-tests-make-testdisplay-non-optional.patch to + avoid unnecessary build deps for the unshipped testdisplay + * Add 20-Revert-Fix-pthread-compiler-flags-to-work-on-Solaris.patch + to build on current xorg-macros + * Add 30-Revert-add-sprite-demo-from-Armin-Reese.patch because + it requires newer libdrm than ours + * Rename forcewaked to intel_forcewaked (upstream post-release fix) + + -- Tormod Volden Tue, 28 Feb 2012 23:13:05 +0100 + +intel-gpu-tools (1.1-1) unstable; urgency=low + + [ Cyril Brulebois ] + * New upstream release. (Closes: #621721) + - Fixes intel_gpu_top MMIO issue. (Closes: #655672) + * Make the Debian X Strike Force maintain the package; keeping Eric, + Tormod, and myself as Uploaders. + * Wrap Build-Depends/Depends. + * Bump libdrm-intel1 build-dep. + * Update watch file: + - Add a reference to upstream git repository. + - Switch from tar.bz2 to tar.gz, the former isn't supported by the 1.0 + source format. + * Switch to dh: + - Switch debhelper build-dep and compat to 8. + - Use dh-autoreconf and quilt as in other X packages. + - Use --fail-missing and .install accordingly. + * Disable test suite, "make test" checks GPU/drm, not the build + + [ Bryce Harrington ] + * control: Add Conflicts with xserver-xorg-video-intel < 2.9.1 due to + intel_reg_dumper. (LP: #591203) + * Add build dependency on xutils-dev to fix FTBFS. + * rules: Add gentarball target to make it easier to update to new git + snapshots when needed. + * Add 100_drmtest_exit_not_abort.patch to avoid SIGABRT when running + benchmarks as non-root. + + [ Tormod Volden ] + * control: Add Vcs links + * Bump Standards-Version to 3.9.2 (no changes needed) + + -- Cyril Brulebois Sat, 11 Feb 2012 18:09:34 +0100 + +intel-gpu-tools (1.1-0ubuntu2) precise; urgency=low + + * Add 100_drmtest_exit_not_abort.patch + + Fix SEGV when running benchmarks as non-root. + (LP: #657529) + + -- Bryce Harrington Tue, 24 Jan 2012 22:38:04 -0800 + +intel-gpu-tools (1.1-0ubuntu1) precise; urgency=low + + * Pre-release merge of Debian's packaging of new upstream release. + + Adds GPU test suite, GPU debugger, intel_backlight, + intel_disable_clock_gating, intel_gpu_abrt, intel_reg_checker, + intel_reg_snapshot, forcewaked. + + Many bug fixes (LP: #752967, #740252, #758437) + * control: + + Add dependency on xutils-dev. Fixes FTBS. + + Add Conflicts with -intel<2.9.1 due to intel_reg_dumper. + (LP: #591203) + * rules: Add gentarball target to make it easier to update to new git + snapshots when needed. + + -- Bryce Harrington Tue, 24 Jan 2012 07:44:13 -0800 + +intel-gpu-tools (1.0.2-1) unstable; urgency=low + + * New upstream version 1.0.2 + * debian/control: Bump to Standards-Version 3.8.3 (no changes needed) + * debian/control: Build-dep on libdrm-intel1 >= 2.4.6 + * debian/control: Add myself as uploader + + -- Tormod Volden Thu, 19 Nov 2009 19:03:26 +0100 + +intel-gpu-tools (1.0.1-1) unstable; urgency=low + + * Initial release (Closes: #529553) + + -- Eric Anholt Fri, 04 Sep 2009 11:51:02 -0700 --- intel-gpu-tools-1.3.orig/debian/README.Debian +++ intel-gpu-tools-1.3/debian/README.Debian @@ -0,0 +1,7 @@ +intel-gpu-tools for Debian +-------------------------- + +The upstream code includes regression tests for the DRM using automake's +make check system. Those are not included in this package. + + -- Eric Anholt Tue, 19 May 2009 18:23:16 -0700 --- intel-gpu-tools-1.3.orig/debian/patches/series +++ intel-gpu-tools-1.3/debian/patches/series @@ -0,0 +1 @@ +#placeholder --- intel-gpu-tools-1.3.orig/scripts/display_debug.sh +++ intel-gpu-tools-1.3/scripts/display_debug.sh @@ -0,0 +1,172 @@ +#!/bin/bash + +# FBC_CFB_BASE 0x43200 +../tools/intel_reg_read 0x43200 +# FBC_CTL 0x43208 +../tools/intel_reg_read 0x43208 +# ERR_INT 0x44040 +../tools/intel_reg_read 0x44040 +# DE_RRMR 0x44050 +../tools/intel_reg_read 0x44050 +# ARB_CTL 0x45000 +../tools/intel_reg_read 0x45000 +# ARB_CTL2 0x45004 +../tools/intel_reg_read 0x45004 +# MSG_CTL 0x45010 +../tools/intel_reg_read 0x45010 +# Watermarks +../tools/intel_reg_read 0x45100 +../tools/intel_reg_read 0x45104 +../tools/intel_reg_read 0x45200 +../tools/intel_reg_read 0x45108 +../tools/intel_reg_read 0x4510C +../tools/intel_reg_read 0x45110 +../tools/intel_reg_read 0x45120 +../tools/intel_reg_read 0x45124 +../tools/intel_reg_read 0x45128 +# Pipe A timing 0x60000-0x6004C +../tools/intel_reg_read 0x60000 -c 0x13; +# Pipe B timing 0x61000-0x6104C +../tools/intel_reg_read 0x61000 -c 0x13; +# Pipe C timing 0x62000-0x6204C +../tools/intel_reg_read 0x62000 -c 0x13; +# FDI A 0x60100 +# FDI B 0x61100 +# FDI C 0x62100 +# EDP 0x64000 +../tools/intel_reg_read 0x60100 +../tools/intel_reg_read 0x61100 +../tools/intel_reg_read 0x62100 +../tools/intel_reg_read 0x64000 +# Panel fitter A window size 0x68074 +# Panel fitter A control 0x68080 +../tools/intel_reg_read 0x68074 +../tools/intel_reg_read 0x68080 +# Panel fitter B window size 0x68874 +# Panel fitter B control 0x68880 +../tools/intel_reg_read 0x68874 +../tools/intel_reg_read 0x68880 +# Panel fitter C window size 0x69074 +# Panel fitter C control 0x69080 +../tools/intel_reg_read 0x69074 +../tools/intel_reg_read 0x69080 +# Pipe A config 0x70008 +# Pipe B config 0x71008 +# Pipe C config 0x72008 +../tools/intel_reg_read 0x70008 +../tools/intel_reg_read 0x71008 +../tools/intel_reg_read 0x72008 +# Cursor A control 0x70080 +# Cursor B control 0x71080 +# Cursor C control 0x72080 +../tools/intel_reg_read 0x70080 +../tools/intel_reg_read 0x71080 +../tools/intel_reg_read 0x72080 +# Primary A control 0x70180 +# Primary B control 0x71180 +# Primary C control 0x72180 +../tools/intel_reg_read 0x70180 +../tools/intel_reg_read 0x71180 +../tools/intel_reg_read 0x72180 +# Sprite A control 0x70280 +# Sprite B control 0x71280 +# Sprite C control 0x72280 +../tools/intel_reg_read 0x70280 +../tools/intel_reg_read 0x71280 +../tools/intel_reg_read 0x72280 +# Sprite A size 0x70290 +# Sprite B size 0x71290 +# Sprite C size 0x72290 +../tools/intel_reg_read 0x70290 +../tools/intel_reg_read 0x71290 +../tools/intel_reg_read 0x72290 +# Sprite A scaling 0x70304 +# Sprite B scaling 0x71304 +# Sprite C scaling 0x72304 +../tools/intel_reg_read 0x70304 +../tools/intel_reg_read 0x71304 +../tools/intel_reg_read 0x72304 +# PCH DE Interrupt enable 0xC400C +../tools/intel_reg_read 0xC400C +# PCH DE Interrupt IIR 0xC4008 +../tools/intel_reg_read 0xC4008 +# PCH DE hotplug 0xC4030 +../tools/intel_reg_read 0xC4030 +# SERR_INT 0xC4040 +../tools/intel_reg_read 0xC4040 +# PCH DPLL A CTL 0xC6014 +# PCH DPLL A Divisor 0 0xC6040 +# PCH DPLL A Divisor 1 0xC6044 +../tools/intel_reg_read 0xC6014 +../tools/intel_reg_read 0xC6040 +../tools/intel_reg_read 0xC6044 +# PCH DPLL B CTL 0xC6018 +# PCH DPLL B Divisor 0 0xC6048 +# PCH DPLL B Divisor 1 0xC604C +../tools/intel_reg_read 0xC6018 +../tools/intel_reg_read 0xC6048 +../tools/intel_reg_read 0xC604C +# PCH DPLL DREF CTL 0xC6200 +../tools/intel_reg_read 0xC6200 +# PCH DPLL SEL 0xC7000 +../tools/intel_reg_read 0xC7000 +# PCH Panel Status 0xC7200 +../tools/intel_reg_read 0xC7200 +# PCH Panel Control 0xC7204 +../tools/intel_reg_read 0xC7204 +# Transcoder A timing 0xE0000-0xE004F +# Transcoder B timing 0xE1000-0xE104F +# Transcoder C timing 0xE2000-0xE204F +../tools/intel_reg_read 0xE0000 -c 0x14; +../tools/intel_reg_read 0xE1000 -c 0x14; +../tools/intel_reg_read 0xE2000 -c 0x14; +# Transcoder A DP CTL 0xE0300 +# Transcoder B DP CTL 0xE1300 +# Transcoder C DP CTL 0xE2300 +../tools/intel_reg_read 0xE0300 +../tools/intel_reg_read 0xE1300 +../tools/intel_reg_read 0xE2300 +# CRT DAC CTL 0xE1100 +../tools/intel_reg_read 0xE1100 +# HDMI/DVI B CTL 0xE1140 +# HDMI/DVI C CTL 0xE1150 +# HDMI/DVI D CTL 0xE1160 +../tools/intel_reg_read 0xE1140 +../tools/intel_reg_read 0xE1150 +../tools/intel_reg_read 0xE1160 +# LVDS 0xE1180 +../tools/intel_reg_read 0xE1180 +# DP B CTL 0xE4100 +# DP C CTL 0xE4200 +# DP D CTL 0xE4300 +../tools/intel_reg_read 0xE4100 +../tools/intel_reg_read 0xE4200 +../tools/intel_reg_read 0xE4300 +# Transcoder A config 0xF0008 +# FDI RX A CTL 0xF000C +# FDI RX A MISC 0xF0010 +# FDI RX A IIR 0xF0014 +# FDI RX A IMR 0xF0018 +../tools/intel_reg_read 0xF0008 -c 5; +# Transcoder B config 0xF1008 +# FDI RX B CTL 0xF100C +# FDI RX B MISC 0xF1010 +# FDI RX B IIR 0xF1014 +# FDI RX B IMR 0xF1018 +../tools/intel_reg_read 0xF1008 -c 5; +# Transcoder C config 0xF2008 +# FDI RX C CTL 0xF200C +# FDI RX C MISC 0xF2010 +# FDI RX C IIR 0xF2014 +# FDI RX C IMR 0xF2018 +../tools/intel_reg_read 0xF2008 -c 5; +#Check if frame and line counters are running +../tools/intel_reg_read 0x44070 +../tools/intel_reg_read 0x70050 +../tools/intel_reg_read 0x71050 +../tools/intel_reg_read 0x72050 +sleep 2; +../tools/intel_reg_read 0x44070 +../tools/intel_reg_read 0x70050 +../tools/intel_reg_read 0x71050 +../tools/intel_reg_read 0x72050 --- intel-gpu-tools-1.3.orig/scripts/convert_itp.py +++ intel-gpu-tools-1.3/scripts/convert_itp.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 + +#this script helps to convert internal debugger scripts given to us into our tools + +import sys +import fileinput + +def replace_with_dict(text, dicto): + for key, val in dicto.items(): + text = text.replace(key, val) + return text + +for lines in fileinput.input([sys.argv[1]], inplace=True): + lines = lines.strip() + if lines == '': continue # strip empty lines + replace_dict = {'dword(' : '../tools/intel_reg_read ', 'MMADDR + ' : '', '//' : '#', ')p;' : '', ')p ' : ' -c '} + print(replace_with_dict(lines, replace_dict)) --- intel-gpu-tools-1.3.orig/shaders/ps/neg1_test.g7a +++ intel-gpu-tools-1.3/shaders/ps/neg1_test.g7a @@ -0,0 +1,9 @@ +mov(8) g112:UD 0x3f800000:UD { align1 }; +mov(8) g113:UD 0x3f800000:UD { align1 }; +mov(8) g114:UD 0x3f800000:UD { align1 }; +mov(8) g115:UD 0x3f800000:UD { align1 }; +mov(8) g116:UD 0x3f800000:UD { align1 }; +mov(8) g117:UD 0x3f800000:UD { align1 }; +mov(8) g118:UD 0x3f800000:UD { align1 }; +mov(8) g119:UD 0x3f800000:UD { align1 }; +send(16) null g112 0x25 0x10031000 { align1, EOT }; --- intel-gpu-tools-1.3.orig/shaders/ps/README +++ intel-gpu-tools-1.3/shaders/ps/README @@ -0,0 +1 @@ +These files are here for reference only. --- intel-gpu-tools-1.3.orig/shaders/ps/blit.g7a +++ intel-gpu-tools-1.3/shaders/ps/blit.g7a @@ -0,0 +1,66 @@ +/* Assemble with ".../intel-gen4asm/src/intel-gen4asm -g 7" */ + + +/* Move pixels into g10-g13. The pixel shaader does not load what you want. It + * loads the input data for a plane function to calculate what you want. The + * following is boiler plate code to move our normalized texture coordinates + * (u,v) into g10-g13. It does this 4 subspans (16 pixels) at a time. + * + * This should do the same thing, but it doesn't work for some reason. + * pln(16) g10 g6<0,1,0>F g2<8,8,1>F { align1 }; + * pln(16) g12 g6.16<1>F g2<8,8,1>F { align1 }; + */ +/* U */ +pln (8) g10<1>F g6.0<0,1,0>F g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ +pln (8) g11<1>F g6.0<0,1,0>F g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ +/* V */ +pln (8) g12<1>F g6.16<0,1,0> g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ +pln (8) g13<1>F g6.16<0,1,0> g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ + + +/* Next the we want the sampler to fetch the src texture (ie. src buffer). This + * is done with a pretty simple send message. The output goes to g112, which is + * exactly what we're supposed to use in our final send message. + * In intel-gen4asm, we should end up parsed by the following rule: + * predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions + * + * Send message descriptor: + * 28:25 = message len = 4 // our 4 registers have 16 pixels + * 24:20 = response len = 8 // Each pixel is RGBA32, so we need 8 registers + * 19:19 = header present = 0 + * 18:17 = SIMD16 = 2 + * 16:12 = TYPE = 0 (regular sample) + * 11:08 = Sampler index = ignored/0 + * 7:0 = binding table index = src = 1 + * 0x8840001 + * + * Send message extra descriptor + * 5:5 = End of Thread = 0 + * 3:0 = Target Function ID = SFID_SAMPLER (2) + * 0x2 + */ + +send(16) g112 g10 0x2 0x8840001 { align1 }; + +/* g112-g119 now contains the sample source input, and all we must do is write + * it out to the destination render target. This is done with the send message + * as well. The only extra bits are to terminate the pixel shader. + * + * Send message descriptor: + * 28:25 = message len = 8 // 16 pixels RGBA32 + * 24:20 = response len = 0 + * 19:19 = header present = 0 + * 17:14 = message type = Render Target Write (12) + * 12:12 = Last Render Target Select = 1 + * 10:08 = Message Type = SIMD16 (0) + * 07:00 = Binding Table Index = dest = 0 + * 0x10031000 + * + * Send message extra descriptor + * 5:5 = End of Thread = 1 + * 3:0 = Target Function ID = SFID_DP_RC (5) + * 0x25 + */ +send(16) null g112 0x25 0x10031000 { align1, EOT }; + +/* vim: set ft=c ts=4 sw=2 tw=80 et: */ --- intel-gpu-tools-1.3.orig/tests/gem_hangcheck_forcewake.c +++ intel-gpu-tools-1.3/tests/gem_hangcheck_forcewake.c @@ -0,0 +1,127 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Daniel Vetter + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "i915_drm.h" +#include "drmtest.h" +#include "intel_bufmgr.h" +#include "intel_batchbuffer.h" +#include "intel_gpu_tools.h" + +/* + * Testcase: Provoke the hangcheck timer on an otherwise idle system + * + * This tries to hit forcewake locking bugs when the hangcheck runs. Somehow we + * often luck out and the hangcheck runs while someone else is already holding + * the dev->struct_mutex. + * + * It's imperative that nothing else runs while this test runs, i.e. kill your X + * session, please. + */ + +static drm_intel_bufmgr *bufmgr; +struct intel_batchbuffer *batch; + +uint32_t blob[2048*2048]; + +#define MAX_BLT_SIZE 128 +int main(int argc, char **argv) +{ + drm_intel_bo *bo = NULL; + uint32_t tiling_mode = I915_TILING_X; + unsigned long pitch, act_size; + int fd, i, devid; + + memset(blob, 'A', sizeof(blob)); + + fd = drm_open_any(); + + bufmgr = drm_intel_bufmgr_gem_init(fd, 4096); + drm_intel_bufmgr_gem_enable_reuse(bufmgr); + devid = intel_get_drm_devid(fd); + batch = intel_batchbuffer_alloc(bufmgr, devid); + + act_size = 2048; + printf("filling ring\n"); + drm_intel_bo_unreference(bo); + bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled bo", act_size, act_size, + 4, &tiling_mode, &pitch, 0); + + drm_intel_bo_subdata(bo, 0, act_size*act_size*4, blob); + + if (IS_965(devid)) + pitch /= 4; + + for (i = 0; i < 10000; i++) { + BEGIN_BATCH(8); + OUT_BATCH(XY_SRC_COPY_BLT_CMD | + XY_SRC_COPY_BLT_WRITE_ALPHA | + XY_SRC_COPY_BLT_WRITE_RGB | + XY_SRC_COPY_BLT_SRC_TILED | + XY_SRC_COPY_BLT_DST_TILED); + OUT_BATCH((3 << 24) | /* 32 bits */ + (0xcc << 16) | /* copy ROP */ + pitch); + OUT_BATCH(0 << 16 | 1024); + OUT_BATCH((2048) << 16 | (2048)); + OUT_RELOC_FENCED(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); + OUT_BATCH(0 << 16 | 0); + OUT_BATCH(pitch); + OUT_RELOC_FENCED(bo, I915_GEM_DOMAIN_RENDER, 0, 0); + ADVANCE_BATCH(); + + if (IS_GEN6(devid) || IS_GEN7(devid)) { + BEGIN_BATCH(3); + OUT_BATCH(XY_SETUP_CLIP_BLT_CMD); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } + } + + printf("waiting\n"); + sleep(10); + + printf("done waiting, check dmesg\n"); + drm_intel_bo_unreference(bo); + + intel_batchbuffer_free(batch); + drm_intel_bufmgr_destroy(bufmgr); + + close(fd); + + return 0; +}