--- redboot-imx-200952.orig/debian/copyright +++ redboot-imx-200952/debian/copyright @@ -0,0 +1,797 @@ +This package was debianized by: + + Michael Casadevall on Fri, 13 Mar 2009 04:51:13 -0400 + +The source code for this package was provided by Freescale Semiconductors, Inc. + +Upstream Authors: + + Red Hat, Inc + eCosCentric Limited + Freescale Semiconductors, Inc. + +Copyright: + + Copyright (C) 1984, 1989, 1990, 2000-2003 Free Software Foundation, Inc + Copyright (C) 1982-1993 Regents of the University of California + Copyright (C) 1987-1988 by Digital Equipment Corporation + Copyright (C) 1987-1988 X Consortium + Copyright (C) 1988-1992 by Richard Outerbridge + Copyright (C) 1989 Carnegie Mellon University + Copyright (C) 1991 David I. Bell + Copyright (C) 1991-1992, RSA Data Security + Copyright (C) 1991-1998, Thomas G. Lane + Copyright (C) 1993 Sun Microsystems, Inc + Copyright (C) 1993-1995 Alexandre Julliard + Copyright (C) 1994 The Australian National University + Copyright (C) 1995-1998 WIDE Project + Copyright (C) 1996 Theo de Raadt + Copyright (C) 1996,1999 by Internet Software Consortium + Copyright (C) 1997 Dan Malek + Copyright (C) 1997-1998 Olivetti & Oracle Research Laboratory + Copyright (C) 1998 Huw Davies + Copyright (C) 1999 ConnectTel, Inc. + Copyright (C) 1999 Alistair Riddoch + Copyright (C) 1999 darran@rimron.co.uk + Copyright (C) 1999-2001 Greg Haerr + Copyright (C) 1999 Bradley D. LaRonde + Copyright (C) 1999-2000 Wei Yongming + Copyright (C) 2000 by VTech Informations LTD + Copyright (C) 2000 Alex Holden + Copyright (C) 2000 Compaq Computer Corporation + Copyright (C) 2000 Rosimildo da Silva + Copyright (C) 2000 Victor Larionov + Copyright (C) 2000 Victor Rogachev + Copyright (C) 2000 Century Software Embedded Technologies + Copyright (C) 2002-2003 Bart Veer + Copyright (C) 2000-2004 Red Hat, Inc. + Copyright (C) 2002-2003 Nick Garnett + Copyright (C) 2002-2004 Gary Thomas + Copyright (C) 2003 MLB Associates + Copyright (C) 2003 Jonathan Larmour + Copyright (C) 2003 Sweeney Design Ltd + Copyright (C) 2003-2007 eCosCentric Limited + Copyright (C) 2004 Andrew Lunn + Copyright (C) 2004 Ferenc Havasi + Copyright (C) 2005 Salvatore Sanfilippo + Copyright (C) 2006-2009 Freescale Semiconductors, Inc. + Copyright (C) Andrea Michelotti + Copyright (C) Chris Johns + +License: + +eCos and Redboot are distributed under the GPLv2: + + This package is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This package is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + As a special exception, if other files instantiate templates or + use macros or inline functions from this file, or you compile this + file and link it with other works to produce a work based on this file, + this file does not by itself cause the resulting work to be covered by the + GNU General Public License. However the source code for this file must + still be made available in accordance with section (3) of the GNU General + Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + You should have received a copy of the GNU General Public License + along with this package; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +On Debian and Ubuntu systems, the complete text of the GNU General +Public License can be found in `/usr/share/common-licenses/GPL'. + +zlib is distributed as part of ecos's source code, its license follows: + + Copyright (C) 1995-1998 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + +The Microwindows, Nano-X, and BOGL software included with eCos +are licensed under the MPL, as specified below. Alternatively, +the software can be converted to the GNU General Public License, Version 2. + + The contents of this file are subject to the Mozilla Public License + Version 1.1 (the "License"); you may not use this file except in + compliance with the License. You may obtain a copy of the License at + http://www.mozilla.org/MPL/ + + Software distributed under the License is distributed on an "AS IS" + basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the + License for the specific language governing rights and limitations + under the License. + + The Original Code is MicroWindows. + + The Initial Developer of the Original Code is Greg Haerr. + Portions created by Greg Haerr are Copyright (C) 1999 + Greg Haerr . All Rights Reserved. + + Contributor(s): + + Alternatively, the contents of this file may be used under the terms + of the GNU General Public license (the "[GNU] License"), in which case the + provisions of [GNU] License are applicable instead of those + above. If you wish to allow use of your version of this file only + under the terms of the [GNU] License and not to allow others to use + your version of this file under the MPL, indicate your decision by + deleting the provisions above and replace them with the notice and + other provisions required by the [GNU] License. If you do not delete + the provisions above, a recipient may use your version of this file + under either the MPL or the [GNU] License. + +The full text of the Mozilla Public License 1.1 follows: + + MOZILLA PUBLIC LICENSE + Version 1.1 + + --------------- + +1. Definitions. + + 1.0.1. "Commercial Use" means distribution or otherwise making the + Covered Code available to a third party. + + 1.1. "Contributor" means each entity that creates or contributes to + the creation of Modifications. + + 1.2. "Contributor Version" means the combination of the Original + Code, prior Modifications used by a Contributor, and the Modifications + made by that particular Contributor. + + 1.3. "Covered Code" means the Original Code or Modifications or the + combination of the Original Code and Modifications, in each case + including portions thereof. + + 1.4. "Electronic Distribution Mechanism" means a mechanism generally + accepted in the software development community for the electronic + transfer of data. + + 1.5. "Executable" means Covered Code in any form other than Source + Code. + + 1.6. "Initial Developer" means the individual or entity identified + as the Initial Developer in the Source Code notice required by Exhibit + A. + + 1.7. "Larger Work" means a work which combines Covered Code or + portions thereof with code not governed by the terms of this License. + + 1.8. "License" means this document. + + 1.8.1. "Licensable" means having the right to grant, to the maximum + extent possible, whether at the time of the initial grant or + subsequently acquired, any and all of the rights conveyed herein. + + 1.9. "Modifications" means any addition to or deletion from the + substance or structure of either the Original Code or any previous + Modifications. When Covered Code is released as a series of files, a + Modification is: + A. Any addition to or deletion from the contents of a file + containing Original Code or previous Modifications. + + B. Any new file that contains any part of the Original Code or + previous Modifications. + + 1.10. "Original Code" means Source Code of computer software code + which is described in the Source Code notice required by Exhibit A as + Original Code, and which, at the time of its release under this + License is not already Covered Code governed by this License. + + 1.10.1. "Patent Claims" means any patent claim(s), now owned or + hereafter acquired, including without limitation, method, process, + and apparatus claims, in any patent Licensable by grantor. + + 1.11. "Source Code" means the preferred form of the Covered Code for + making modifications to it, including all modules it contains, plus + any associated interface definition files, scripts used to control + compilation and installation of an Executable, or source code + differential comparisons against either the Original Code or another + well known, available Covered Code of the Contributor's choice. The + Source Code can be in a compressed or archival form, provided the + appropriate decompression or de-archiving software is widely available + for no charge. + + 1.12. "You" (or "Your") means an individual or a legal entity + exercising rights under, and complying with all of the terms of, this + License or a future version of this License issued under Section 6.1. + For legal entities, "You" includes any entity which controls, is + controlled by, or is under common control with You. For purposes of + this definition, "control" means (a) the power, direct or indirect, + to cause the direction or management of such entity, whether by + contract or otherwise, or (b) ownership of more than fifty percent + (50%) of the outstanding shares or beneficial ownership of such + entity. + +2. Source Code License. + + 2.1. The Initial Developer Grant. + The Initial Developer hereby grants You a world-wide, royalty-free, + non-exclusive license, subject to third party intellectual property + claims: + (a) under intellectual property rights (other than patent or + trademark) Licensable by Initial Developer to use, reproduce, + modify, display, perform, sublicense and distribute the Original + Code (or portions thereof) with or without Modifications, and/or + as part of a Larger Work; and + + (b) under Patents Claims infringed by the making, using or + selling of Original Code, to make, have made, use, practice, + sell, and offer for sale, and/or otherwise dispose of the + Original Code (or portions thereof). + + (c) the licenses granted in this Section 2.1(a) and (b) are + effective on the date Initial Developer first distributes + Original Code under the terms of this License. + + (d) Notwithstanding Section 2.1(b) above, no patent license is + granted: 1) for code that You delete from the Original Code; 2) + separate from the Original Code; or 3) for infringements caused + by: i) the modification of the Original Code or ii) the + combination of the Original Code with other software or devices. + + 2.2. Contributor Grant. + Subject to third party intellectual property claims, each Contributor + hereby grants You a world-wide, royalty-free, non-exclusive license + + (a) under intellectual property rights (other than patent or + trademark) Licensable by Contributor, to use, reproduce, modify, + display, perform, sublicense and distribute the Modifications + created by such Contributor (or portions thereof) either on an + unmodified basis, with other Modifications, as Covered Code + and/or as part of a Larger Work; and + + (b) under Patent Claims infringed by the making, using, or + selling of Modifications made by that Contributor either alone + and/or in combination with its Contributor Version (or portions + of such combination), to make, use, sell, offer for sale, have + made, and/or otherwise dispose of: 1) Modifications made by that + Contributor (or portions thereof); and 2) the combination of + Modifications made by that Contributor with its Contributor + Version (or portions of such combination). + + (c) the licenses granted in Sections 2.2(a) and 2.2(b) are + effective on the date Contributor first makes Commercial Use of + the Covered Code. + + (d) Notwithstanding Section 2.2(b) above, no patent license is + granted: 1) for any code that Contributor has deleted from the + Contributor Version; 2) separate from the Contributor Version; + 3) for infringements caused by: i) third party modifications of + Contributor Version or ii) the combination of Modifications made + by that Contributor with other software (except as part of the + Contributor Version) or other devices; or 4) under Patent Claims + infringed by Covered Code in the absence of Modifications made by + that Contributor. + +3. Distribution Obligations. + + 3.1. Application of License. + The Modifications which You create or to which You contribute are + governed by the terms of this License, including without limitation + Section 2.2. The Source Code version of Covered Code may be + distributed only under the terms of this License or a future version + of this License released under Section 6.1, and You must include a + copy of this License with every copy of the Source Code You + distribute. You may not offer or impose any terms on any Source Code + version that alters or restricts the applicable version of this + License or the recipients' rights hereunder. However, You may include + an additional document offering the additional rights described in + Section 3.5. + + 3.2. Availability of Source Code. + Any Modification which You create or to which You contribute must be + made available in Source Code form under the terms of this License + either on the same media as an Executable version or via an accepted + Electronic Distribution Mechanism to anyone to whom you made an + Executable version available; and if made available via Electronic + Distribution Mechanism, must remain available for at least twelve (12) + months after the date it initially became available, or at least six + (6) months after a subsequent version of that particular Modification + has been made available to such recipients. You are responsible for + ensuring that the Source Code version remains available even if the + Electronic Distribution Mechanism is maintained by a third party. + + 3.3. Description of Modifications. + You must cause all Covered Code to which You contribute to contain a + file documenting the changes You made to create that Covered Code and + the date of any change. You must include a prominent statement that + the Modification is derived, directly or indirectly, from Original + Code provided by the Initial Developer and including the name of the + Initial Developer in (a) the Source Code, and (b) in any notice in an + Executable version or related documentation in which You describe the + origin or ownership of the Covered Code. + + 3.4. Intellectual Property Matters + (a) Third Party Claims. + If Contributor has knowledge that a license under a third party's + intellectual property rights is required to exercise the rights + granted by such Contributor under Sections 2.1 or 2.2, + Contributor must include a text file with the Source Code + distribution titled "LEGAL" which describes the claim and the + party making the claim in sufficient detail that a recipient will + know whom to contact. If Contributor obtains such knowledge after + the Modification is made available as described in Section 3.2, + Contributor shall promptly modify the LEGAL file in all copies + Contributor makes available thereafter and shall take other steps + (such as notifying appropriate mailing lists or newsgroups) + reasonably calculated to inform those who received the Covered + Code that new knowledge has been obtained. + + (b) Contributor APIs. + If Contributor's Modifications include an application programming + interface and Contributor has knowledge of patent licenses which + are reasonably necessary to implement that API, Contributor must + also include this information in the LEGAL file. + + (c) Representations. + Contributor represents that, except as disclosed pursuant to + Section 3.4(a) above, Contributor believes that Contributor's + Modifications are Contributor's original creation(s) and/or + Contributor has sufficient rights to grant the rights conveyed by + this License. + + 3.5. Required Notices. + You must duplicate the notice in Exhibit A in each file of the Source + Code. If it is not possible to put such notice in a particular Source + Code file due to its structure, then You must include such notice in a + location (such as a relevant directory) where a user would be likely + to look for such a notice. If You created one or more Modification(s) + You may add your name as a Contributor to the notice described in + Exhibit A. You must also duplicate this License in any documentation + for the Source Code where You describe recipients' rights or ownership + rights relating to Covered Code. You may choose to offer, and to + charge a fee for, warranty, support, indemnity or liability + obligations to one or more recipients of Covered Code. However, You + may do so only on Your own behalf, and not on behalf of the Initial + Developer or any Contributor. You must make it absolutely clear than + any such warranty, support, indemnity or liability obligation is + offered by You alone, and You hereby agree to indemnify the Initial + Developer and every Contributor for any liability incurred by the + Initial Developer or such Contributor as a result of warranty, + support, indemnity or liability terms You offer. + + 3.6. Distribution of Executable Versions. + You may distribute Covered Code in Executable form only if the + requirements of Section 3.1-3.5 have been met for that Covered Code, + and if You include a notice stating that the Source Code version of + the Covered Code is available under the terms of this License, + including a description of how and where You have fulfilled the + obligations of Section 3.2. The notice must be conspicuously included + in any notice in an Executable version, related documentation or + collateral in which You describe recipients' rights relating to the + Covered Code. You may distribute the Executable version of Covered + Code or ownership rights under a license of Your choice, which may + contain terms different from this License, provided that You are in + compliance with the terms of this License and that the license for the + Executable version does not attempt to limit or alter the recipient's + rights in the Source Code version from the rights set forth in this + License. If You distribute the Executable version under a different + license You must make it absolutely clear that any terms which differ + from this License are offered by You alone, not by the Initial + Developer or any Contributor. You hereby agree to indemnify the + Initial Developer and every Contributor for any liability incurred by + the Initial Developer or such Contributor as a result of any such + terms You offer. + + 3.7. Larger Works. + You may create a Larger Work by combining Covered Code with other code + not governed by the terms of this License and distribute the Larger + Work as a single product. In such a case, You must make sure the + requirements of this License are fulfilled for the Covered Code. + +4. Inability to Comply Due to Statute or Regulation. + + If it is impossible for You to comply with any of the terms of this + License with respect to some or all of the Covered Code due to + statute, judicial order, or regulation then You must: (a) comply with + the terms of this License to the maximum extent possible; and (b) + describe the limitations and the code they affect. Such description + must be included in the LEGAL file described in Section 3.4 and must + be included with all distributions of the Source Code. Except to the + extent prohibited by statute or regulation, such description must be + sufficiently detailed for a recipient of ordinary skill to be able to + understand it. + +5. Application of this License. + + This License applies to code to which the Initial Developer has + attached the notice in Exhibit A and to related Covered Code. + +6. Versions of the License. + + 6.1. New Versions. + Netscape Communications Corporation ("Netscape") may publish revised + and/or new versions of the License from time to time. Each version + will be given a distinguishing version number. + + 6.2. Effect of New Versions. + Once Covered Code has been published under a particular version of the + License, You may always continue to use it under the terms of that + version. You may also choose to use such Covered Code under the terms + of any subsequent version of the License published by Netscape. No one + other than Netscape has the right to modify the terms applicable to + Covered Code created under this License. + + 6.3. Derivative Works. + If You create or use a modified version of this License (which you may + only do in order to apply it to code which is not already Covered Code + governed by this License), You must (a) rename Your license so that + the phrases "Mozilla", "MOZILLAPL", "MOZPL", "Netscape", + "MPL", "NPL" or any confusingly similar phrase do not appear in your + license (except to note that your license differs from this License) + and (b) otherwise make it clear that Your version of the license + contains terms which differ from the Mozilla Public License and + Netscape Public License. (Filling in the name of the Initial + Developer, Original Code or Contributor in the notice described in + Exhibit A shall not of themselves be deemed to be modifications of + this License.) + +7. DISCLAIMER OF WARRANTY. + + COVERED CODE IS PROVIDED UNDER THIS LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, + WITHOUT LIMITATION, WARRANTIES THAT THE COVERED CODE IS FREE OF + DEFECTS, MERCHANTABLE, FIT FOR A PARTICULAR PURPOSE OR NON-INFRINGING. + THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE COVERED CODE + IS WITH YOU. SHOULD ANY COVERED CODE PROVE DEFECTIVE IN ANY RESPECT, + YOU (NOT THE INITIAL DEVELOPER OR ANY OTHER CONTRIBUTOR) ASSUME THE + COST OF ANY NECESSARY SERVICING, REPAIR OR CORRECTION. THIS DISCLAIMER + OF WARRANTY CONSTITUTES AN ESSENTIAL PART OF THIS LICENSE. NO USE OF + ANY COVERED CODE IS AUTHORIZED HEREUNDER EXCEPT UNDER THIS DISCLAIMER. + +8. TERMINATION. + + 8.1. This License and the rights granted hereunder will terminate + automatically if You fail to comply with terms herein and fail to cure + such breach within 30 days of becoming aware of the breach. All + sublicenses to the Covered Code which are properly granted shall + survive any termination of this License. Provisions which, by their + nature, must remain in effect beyond the termination of this License + shall survive. + + 8.2. If You initiate litigation by asserting a patent infringement + claim (excluding declatory judgment actions) against Initial Developer + or a Contributor (the Initial Developer or Contributor against whom + You file such action is referred to as "Participant") alleging that: + + (a) such Participant's Contributor Version directly or indirectly + infringes any patent, then any and all rights granted by such + Participant to You under Sections 2.1 and/or 2.2 of this License + shall, upon 60 days notice from Participant terminate prospectively, + unless if within 60 days after receipt of notice You either: (i) + agree in writing to pay Participant a mutually agreeable reasonable + royalty for Your past and future use of Modifications made by such + Participant, or (ii) withdraw Your litigation claim with respect to + the Contributor Version against such Participant. If within 60 days + of notice, a reasonable royalty and payment arrangement are not + mutually agreed upon in writing by the parties or the litigation claim + is not withdrawn, the rights granted by Participant to You under + Sections 2.1 and/or 2.2 automatically terminate at the expiration of + the 60 day notice period specified above. + + (b) any software, hardware, or device, other than such Participant's + Contributor Version, directly or indirectly infringes any patent, then + any rights granted to You by such Participant under Sections 2.1(b) + and 2.2(b) are revoked effective as of the date You first made, used, + sold, distributed, or had made, Modifications made by that + Participant. + + 8.3. If You assert a patent infringement claim against Participant + alleging that such Participant's Contributor Version directly or + indirectly infringes any patent where such claim is resolved (such as + by license or settlement) prior to the initiation of patent + infringement litigation, then the reasonable value of the licenses + granted by such Participant under Sections 2.1 or 2.2 shall be taken + into account in determining the amount or value of any payment or + license. + + 8.4. In the event of termination under Sections 8.1 or 8.2 above, + all end user license agreements (excluding distributors and resellers) + which have been validly granted by You or any distributor hereunder + prior to termination shall survive termination. + +9. LIMITATION OF LIABILITY. + + UNDER NO CIRCUMSTANCES AND UNDER NO LEGAL THEORY, WHETHER TORT + (INCLUDING NEGLIGENCE), CONTRACT, OR OTHERWISE, SHALL YOU, THE INITIAL + DEVELOPER, ANY OTHER CONTRIBUTOR, OR ANY DISTRIBUTOR OF COVERED CODE, + OR ANY SUPPLIER OF ANY OF SUCH PARTIES, BE LIABLE TO ANY PERSON FOR + ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OF ANY + CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF GOODWILL, + WORK STOPPAGE, COMPUTER FAILURE OR MALFUNCTION, OR ANY AND ALL OTHER + COMMERCIAL DAMAGES OR LOSSES, EVEN IF SUCH PARTY SHALL HAVE BEEN + INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. THIS LIMITATION OF + LIABILITY SHALL NOT APPLY TO LIABILITY FOR DEATH OR PERSONAL INJURY + RESULTING FROM SUCH PARTY'S NEGLIGENCE TO THE EXTENT APPLICABLE LAW + PROHIBITS SUCH LIMITATION. SOME JURISDICTIONS DO NOT ALLOW THE + EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO + THIS EXCLUSION AND LIMITATION MAY NOT APPLY TO YOU. + +10. U.S. GOVERNMENT END USERS. + + The Covered Code is a "commercial item," as that term is defined in + 48 C.F.R. 2.101 (Oct. 1995), consisting of "commercial computer + software" and "commercial computer software documentation," as such + terms are used in 48 C.F.R. 12.212 (Sept. 1995). Consistent with 48 + C.F.R. 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (June 1995), + all U.S. Government End Users acquire Covered Code with only those + rights set forth herein. + +11. MISCELLANEOUS. + + This License represents the complete agreement concerning subject + matter hereof. If any provision of this License is held to be + unenforceable, such provision shall be reformed only to the extent + necessary to make it enforceable. This License shall be governed by + California law provisions (except to the extent applicable law, if + any, provides otherwise), excluding its conflict-of-law provisions. + With respect to disputes in which at least one party is a citizen of, + or an entity chartered or registered to do business in the United + States of America, any litigation relating to this License shall be + subject to the jurisdiction of the Federal Courts of the Northern + District of California, with venue lying in Santa Clara County, + California, with the losing party responsible for costs, including + without limitation, court costs and reasonable attorneys' fees and + expenses. The application of the United Nations Convention on + Contracts for the International Sale of Goods is expressly excluded. + Any law or regulation which provides that the language of a contract + shall be construed against the drafter shall not apply to this + License. + +12. RESPONSIBILITY FOR CLAIMS. + + As between Initial Developer and the Contributors, each party is + responsible for claims and damages arising, directly or indirectly, + out of its utilization of rights under this License and You agree to + work with Initial Developer and Contributors to distribute such + responsibility on an equitable basis. Nothing herein is intended or + shall be deemed to constitute any admission of liability. + +13. MULTIPLE-LICENSED CODE. + + Initial Developer may designate portions of the Covered Code as + "Multiple-Licensed". "Multiple-Licensed" means that the Initial + Developer permits you to utilize portions of the Covered Code under + Your choice of the NPL or the alternative licenses, if any, specified + by the Initial Developer in the file described in Exhibit A. + +EXHIBIT A -Mozilla Public License. + + ``The contents of this file are subject to the Mozilla Public License + Version 1.1 (the "License"); you may not use this file except in + compliance with the License. You may obtain a copy of the License at + http://www.mozilla.org/MPL/ + + Software distributed under the License is distributed on an "AS IS" + basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the + License for the specific language governing rights and limitations + under the License. + + The Original Code is ______________________________________. + + The Initial Developer of the Original Code is ________________________. + Portions created by ______________________ are Copyright (C) ______ + _______________________. All Rights Reserved. + + Contributor(s): ______________________________________. + + Alternatively, the contents of this file may be used under the terms + of the _____ license (the "[___] License"), in which case the + provisions of [______] License are applicable instead of those + above. If you wish to allow use of your version of this file only + under the terms of the [____] License and not to allow others to use + your version of this file under the MPL, indicate your decision by + deleting the provisions above and replace them with the notice and + other provisions required by the [___] License. If you do not delete + the provisions above, a recipient may use your version of this file + under either the MPL or the [___] License." + + [NOTE: The text of this Exhibit A may differ slightly from the text of + the notices in the Source Code files of the Original Code. You should + use the text of this Exhibit A rather than the text found in the + Original Code Source Code for Your Modifications.] + + +The jpeg library by the Independent JPEG Group is included, this package license is as follows: + +LEGAL ISSUES +============ + +In plain English: + +1. We don't promise that this software works. (But if you find any bugs, + please let us know!) +2. You can use this software for whatever you want. You don't have to pay us. +3. You may not pretend that you wrote this software. If you use it in a + program, you must acknowledge somewhere in your documentation that + you've used the IJG code. + +In legalese: + +The authors make NO WARRANTY or representation, either express or implied, +with respect to this software, its quality, accuracy, merchantability, or +fitness for a particular purpose. This software is provided "AS IS", and you, +its user, assume the entire risk as to its quality and accuracy. + +This software is copyright (C) 1991-1998, Thomas G. Lane. +All Rights Reserved except as specified below. + +Permission is hereby granted to use, copy, modify, and distribute this +software (or portions thereof) for any purpose, without fee, subject to these +conditions: +(1) If any part of the source code for this software is distributed, then this +README file must be included, with this copyright and no-warranty notice +unaltered; and any additions, deletions, or changes to the original files +must be clearly indicated in accompanying documentation. +(2) If only executable code is distributed, then the accompanying +documentation must state that "this software is based in part on the work of +the Independent JPEG Group". +(3) Permission for use of this software is granted only if the user accepts +full responsibility for any undesirable consequences; the authors accept +NO LIABILITY for damages of any kind. + +These conditions apply to any software derived from or based on the IJG code, +not just to the unmodified library. If you use our work, you ought to +acknowledge us. + +Permission is NOT granted for the use of any IJG author's name or company name +in advertising or publicity relating to this software or products derived from +it. This software may be referred to only as "the Independent JPEG Group's +software". + +We specifically permit and encourage the use of this software as the basis of +commercial products, provided that all warranty or liability claims are +assumed by the product vendor. + + +ansi2knr.c is included in this distribution by permission of L. Peter Deutsch, +sole proprietor of its copyright holder, Aladdin Enterprises of Menlo Park, CA. +ansi2knr.c is NOT covered by the above copyright and conditions, but instead +by the usual distribution terms of the Free Software Foundation; principally, +that you must include source code if you redistribute it. (See the file +ansi2knr.c for full details.) However, since ansi2knr.c is not needed as part +of any program generated from the IJG code, this does not limit you more than +the foregoing paragraphs do. + +The Unix configuration script "configure" was produced with GNU Autoconf. +It is copyright by the Free Software Foundation but is freely distributable. +The same holds for its supporting scripts (config.guess, config.sub, +ltconfig, ltmain.sh). Another support script, install-sh, is copyright +by M.I.T. but is also freely distributable. + +It appears that the arithmetic coding option of the JPEG spec is covered by +patents owned by IBM, AT&T, and Mitsubishi. Hence arithmetic coding cannot +legally be used without obtaining one or more licenses. For this reason, +support for arithmetic coding has been removed from the free JPEG software. +(Since arithmetic coding provides only a marginal gain over the unpatented +Huffman mode, it is unlikely that very many implementations will support it.) +So far as we are aware, there are no patent restrictions on the remaining +code. + +The IJG distribution formerly included code to read and write GIF files. +To avoid entanglement with the Unisys LZW patent, GIF reading support has +been removed altogether, and the GIF writer has been simplified to produce +"uncompressed GIFs". This technique does not use the LZW algorithm; the +resulting GIF files are larger than usual, but are readable by all standard +GIF decoders. + +We are required to state that + "The Graphics Interchange Format(c) is the Copyright property of + CompuServe Incorporated. GIF(sm) is a Service Mark property of + CompuServe Incorporated." + +Some files in this project are licensed under the four-clause BSD license as +denoted by the copyright headers in their files. The full four-clause BSD licnese +follows: + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. + 4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +Some files in this project are licensed under the three clause BSD license as +denoted by the copyright headers in their files. The full three-clause BSD licnese +follows: + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +Some files in this project are licensed under the Apache 2.0 license as deno +ted by the copyright headers in each file. The full text of the Apache 2.0 +license follows: + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +On Debian and Ubuntu systems, the complete text of the Apache 2.0 license +can be found in `/usr/share/common-licenses/Apache-2.0'. + + +The Debian packaging is: + + Copyright (C) 2009, Michael Casadevall , Canonical Ltd. + +and is licensed under the GPL, see above. + +debian/fconfig-imx51-babbage.bin.uue was created by running "fconfig -i" from +a running imx51-babbage redboot and copying the resulting flash data (in +uuencoded form). + --- redboot-imx-200952.orig/debian/redboot-imx51-babbage.install +++ redboot-imx-200952/debian/redboot-imx51-babbage.install @@ -0,0 +1,2 @@ +build/install/bin/imx51-babbage_fconfig.bin usr/lib/redboot/ +build/install/bin/imx51-babbage-TO2_redboot.bin usr/lib/redboot/ --- redboot-imx-200952.orig/debian/fconfig-imx51-babbage.bin.uue +++ redboot-imx-200952/debian/fconfig-imx51-babbage.bin.uue @@ -0,0 +1,95 @@ +begin 644 fconfig-imx51-babbage.bin +M`!```,[ZK0L!#`$`8F]O=%]S8W)I<'0```````01`0QB;V]T7W-C5]I +M<`!B;V]T<```````!1$`!F)O;W1P7VUY7VEP7VUA\Q:X +!%0`` +` +end --- redboot-imx-200952.orig/debian/changelog +++ redboot-imx-200952/debian/changelog @@ -0,0 +1,140 @@ +redboot-imx (200952-0ubuntu3) precise; urgency=low + + * Build for armhf. + + -- Matthias Klose Mon, 05 Dec 2011 16:46:32 +0100 + +redboot-imx (200952-0ubuntu1) lucid; urgency=low + + * New upstream release + + MX25/35 3-stack - support Samsung K9LBG08UxD NAND flash + + Update MX51 Babbage DDR2 init with new ESDCFG parameter + + [MX25_BSP] Redboot : There are CRC error and system halted + when load kernel with fec port connected + + Update the IDE Driver to the latest from the Public ECOS Repository + + Restructure the iMX ATA driver to use the Redboot IDE Framework + + Add FAT32 support + * Update patch 01_freescale_imx_base + * Update patch 02_freescale_imx51 + + -- Oliver Grawert Tue, 26 Jan 2010 18:36:51 +0100 + +redboot-imx (200938-0ubuntu1) lucid; urgency=low + + * New upstream bugfix release + + Update the DDR setup for MX51 TO 3.0 on 3-stack platform + + Drop support for MX51 Babbage 1.0 & MX51 Rocky + + Fix the I2C driver + + Update the DDR setup for MX51 Babbage Platform + * Update patch 01_freescale_imx_base + * Update patch 02_freescale_imx51 + * debian/rules: Switch off building of the babbage1 redboot + + -- Oliver Grawert Wed, 14 Oct 2009 15:40:35 +0200 + +redboot-imx (200933-0ubuntu1) karmic; urgency=low + + * New upstream bugfix release + + Change MX51 core voltage settings based on the latest datasheet + + Add support for MX51 TO 3.0 + + Add display support on MX51 & MX37 3-stack platforms + + i.MX51 3-stack - add image header for HAB + + i.MX51 BB2.5 - "fac spi" reports "Unknown error" when cold boot from MMC + + Fix the MX51 NAND driver to reset RBA to Buf 0 before program + + Fix the FIS erase implementation for NAND media + + [MX51] SD card boot failure + * Update patch 01_freescale_imx_base + * Update patch 02_freescale_imx51 + + -- Oliver Grawert Wed, 23 Sep 2009 12:55:47 +0200 + +redboot-imx (200929-0ubuntu1) karmic; urgency=low + + * New Upstream Release: + + Update Redboot for Babbage 2.5 + + Fix the NAND driver to increase flexibility in configuring NAND + parameters + + Update MX37 & MX51 clocking code to Gate off Peripheral clocks + during clock setup + + Implement workaround for hardware Erratum ENGcm09121 - NFC 8bit + ECC corrects wrongly on slow NAND devices + * Update patch 01_freescale_imx_base + * Update patch 02_freescale_imx51 + * re-enable babbage1 binary again, build failures are fixed in this + version (installs to /usr/lib/redboot/imx51-babbage_redboot.bin) + + -- Oliver Grawert Thu, 20 Aug 2009 12:20:05 +0200 + +redboot-imx (200925-0ubuntu1) karmic; urgency=low + + * New Upstream Release: + + Add support for the new 4MB Atmel SPI-NOR + + Fix MX51 Clock code to make sure IPG PERCLK divider is set correctly + + Add a Redboot command to read/write to different MMC/SD + + MX51 Babbage2.5 - pass new system rev to Linux kernel + + Update the MX51 ARM Platform clock divider + + Fix NAND driver to read the NAND ID without relying on the dip switch + settings + + Fix the MX51 NAND Driver Programming code + + Support Huashan (STMP3780) in RedBoot + + Update the mcpu flag + + Request to remove Watchdog disable codes MX51 + * Update patch 01_freescale_imx_base + * Update patch 02_freescale_imx51 + * Update patch 03_build_fixups + * do not build babbage1 redboot binary since there are build failures + + -- Oliver Grawert Wed, 19 Aug 2009 11:32:50 +0200 + +redboot-imx (200918-0ubuntu2) karmic; urgency=low + + * build babbage1 abd TO2 targets, install both to /usr/lib/redboot + as imx51-babbage_redboot.bin and imx51-babbage-TO2_redboot.bin + + -- Oliver Grawert Sun, 02 Aug 2009 08:58:10 +0200 + +redboot-imx (200918-0ubuntu1) karmic; urgency=low + + * new upstream version for TO2 hardware + * 01_freescale_imx_base.dpatch, 02_freescale_imx51.dpatch updated to + TO2 architecture + * newly added 03_build_fixups.dpatch to fix build issues + + -- Oliver Grawert Sat, 01 Aug 2009 15:42:50 +0200 + +redboot-imx (200910-0ubuntu2) jaunty; urgency=low + + * Use debian/*.install files and dh_install for installation. + * Install the RedBoot binary in usr/lib/redboot/imx51-babbage_redboot.bin; + LP: #356257. Also drop the now unneeded lintian override for this file. + * Cleanup rules. + * get-orig-source is .PHONY. + * Drop unused udeb for now. + * Priority is optional. + * Cleanup control. + * Drop bogus watch file. + * Generate and install a non-padded version of the RedBoot binary. + * Drop install target. + * Add debian/fconfig-imx51-babbage.bin.uue containing the uuencoded default + values for the flash config; install the uudecoded binary along redboot; + build-dep on sharutils for uuencoding/decoding; add a note in copyright + about this. + + -- Loic Minier Tue, 07 Apr 2009 15:40:07 +0200 + +redboot-imx (200910-0ubuntu1) jaunty; urgency=low + + * Initial Release (LP: #343866) + * Included patches: + - 01_freescale_imx_base.dpatch + + Provided by Freescale - Adds base code for the iMX and adds the + Freescale variants to the build system + - 02_freescale_imx51.dpatch + + Provided by Freescale, adds iMX51 support + - 03_correct_machine_id.dpatch + + Corrects the RedBoot machine id to allow RedBoot to successfully boot + a 2.6.28 kernel using the assigned machine ID + - 04_allow_compliation_with_native_arm_toolchain.dpatch + + Allows RedBoot to be built and run with an arm-linux-gnueabi toolchain + + -- Michael Casadevall Mon, 16 Mar 2009 06:16:25 -0400 --- redboot-imx-200952.orig/debian/rules +++ redboot-imx-200952/debian/rules @@ -0,0 +1,67 @@ +#!/usr/bin/make -f + +include /usr/share/dpatch/dpatch.make + +export ECOS_REPOSITORY=$(CURDIR)/packages + +DEB_HOST_GNU_TYPE := $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) + +build: build-stamp +build-stamp: patch-stamp + dh_testdir + mkdir build + cd build && \ + ecosconfig-imx new mx51_babbage redboot && \ + ecosconfig-imx import $(CURDIR)/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM.ecm && \ + ecosconfig-imx tree && \ + $(MAKE) COMMAND_PREFIX=$(DEB_HOST_GNU_TYPE)- AR=ar OBJCOPY=objcopy + # generate a binary without the first 0x400 bytes of padding + #dd if=build/install/bin/redboot.bin of=build/install/bin/imx51-babbage_redboot.bin bs=1024 skip=1 + #mkdir build-TO2 + #cd build-TO2 && \ + # ecosconfig-imx new mx51_babbage redboot && \ + # ecosconfig-imx import $(CURDIR)/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM_TO2.ecm && \ + # ecosconfig-imx tree && \ + # $(MAKE) COMMAND_PREFIX=$(DEB_HOST_GNU_TYPE)- AR=ar OBJCOPY=objcopy + # generate a binary without the first 0x400 bytes of padding + dd if=build/install/bin/redboot.bin of=build/install/bin/imx51-babbage-TO2_redboot.bin bs=1024 skip=1 + + # unpack binary fconfig data for iMX51 Babbage + uudecode -o build/install/bin/imx51-babbage_fconfig.bin debian/fconfig-imx51-babbage.bin.uue + touch $@ + +clean: unpatch + dh_testdir + dh_testroot + rm -rf build-stamp build + dh_clean + +get-orig-source: clean + # Remove all the CVS files + find . -name CVS | xargs rm -rf + cd .. && sh -c "/bin/tar czf redboot-imx_200918.orig.tar.gz --exclude=debian --exclude=.bzr --exclude=.bzr-builddeb `basename $(CURDIR)`" + +binary-indep: + +binary-arch: build + dh_testdir + dh_testroot + dh_prep + dh_installchangelogs -s ChangeLog + dh_installdocs -s + dh_installexamples -s + dh_install -s + dh_installman -s + dh_link -s + dh_strip -s + dh_compress -s + dh_fixperms -s + dh_lintian -s + dh_installdeb -s + dh_shlibdeps -s + dh_gencontrol -s + dh_md5sums -s + dh_builddeb -s + +binary: binary-indep binary-arch +.PHONY: build clean binary-indep binary-arch binary get-orig-source --- redboot-imx-200952.orig/debian/README.Ubuntu +++ redboot-imx-200952/debian/README.Ubuntu @@ -0,0 +1,8 @@ +Notes on redboot-imx +--- + +Freescale ships this package as one base tarball (which is the orig.tar.gz +for this package), one base patch file (which extends the build system), and then +one patch for each processor series (imx51, etc.). To sanely package this, we take +the base tarball, then take each of Freescale's patches, strip out the cruft (aka CVS +folders using filterdiff), and apply them as a dpatch, then apply our patches ontop. --- redboot-imx-200952.orig/debian/compat +++ redboot-imx-200952/debian/compat @@ -0,0 +1 @@ +7 --- redboot-imx-200952.orig/debian/control +++ redboot-imx-200952/debian/control @@ -0,0 +1,20 @@ +Source: redboot-imx +Maintainer: Ubuntu Mobile Team +XSBC-Original-Maintainer: Michael Casadevall +Section: misc +Priority: optional +Standards-Version: 3.8.0 +Vcs-Bzr: lp:~ubuntu-mobile/redboot-imx/ubuntu/ +Vcs-Browser: http://bazaar.launchpad.net/~ubuntu-mobile/redboot-imx/ubuntu/ +Build-Depends: debhelper (>= 7), dpatch, ecosconfig-imx, sharutils + +Package: redboot-imx51-babbage +Architecture: armel armhf +Depends: ${shlibs:Depends}, ${misc:Depends} +Description: Bootloader for Freescale iMX51 boards + RedBoot is a complete bootstrap environment for embedded systems. + Based on the eCos Hardware Abstraction Layer, RedBoot inherits the + eCos qualities of reliability, compactness, configurability, and portability. + . + This package has been configured for Freescale's iMX51 Babbage board, and will + not work on any other imx51 based board. --- redboot-imx-200952.orig/debian/source.lintian-overrides +++ redboot-imx-200952/debian/source.lintian-overrides @@ -0,0 +1,4 @@ +# we are only using the ecos source to build redboot +# we don't use the autoconf tools within this package +# since they are only used in ecos builds AFAIK. +redboot-imx source: ancient-libtool --- redboot-imx-200952.orig/debian/patches/02_freescale_imx51.dpatch +++ redboot-imx-200952/debian/patches/02_freescale_imx51.dpatch @@ -0,0 +1,10320 @@ +#! /bin/sh /usr/share/dpatch/dpatch-run +## 02_freescale_imx51.dpatch by +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: No description. + +@DPATCH@ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/cdl/hal_arm_board.cdl redboot-imx-200952/packages/hal/arm/mx51/3stack/current/cdl/hal_arm_board.cdl +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/cdl/hal_arm_board.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/cdl/hal_arm_board.cdl 2010-01-26 17:35:49.952964753 +0000 +@@ -0,0 +1,350 @@ ++# ==================================================================== ++# ++# hal_arm_board.cdl ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++ ++cdl_package CYGPKG_HAL_ARM_MX51_3STACK { ++ display "Freescale board" ++ parent CYGPKG_HAL_ARM_MX51 ++ hardware ++ include_dir cyg/hal ++ define_header hal_arm_board.h ++ description " ++ This HAL platform package provides generic ++ support for the Freescale MX51 3-Stack Board." ++ ++ compile board_misc.c mx51_fastlogo.c epson_lcd.c ++ implements CYGINT_HAL_DEBUG_GDB_STUBS ++ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK ++ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT ++ ++ implements CYGHWR_IMX_UART1 ++ #implements CYGHWR_IMX_UART2 ++ #implements CYGHWR_IMX_UART3 ++ ++ define_proc { ++ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " ++ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " ++ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " ++ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\"" ++ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 3-Stack\"" ++ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1696" ++ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack" ++ } ++ ++ cdl_component CYG_HAL_STARTUP { ++ display "Startup type" ++ flavor data ++ default_value {"ROM"} ++ legal_values {"RAM" "ROM" "ROMRAM"} ++ no_define ++ define -file system.h CYG_HAL_STARTUP ++ description " ++ When targetting the eval board it is possible to build ++ the system for either RAM bootstrap or ROM bootstrap(s). Select ++ 'ram' when building programs to load into RAM using eCos GDB ++ stubs. Select 'rom' when building a stand-alone application ++ which will be put into ROM, or for the special case of ++ building the eCos GDB stubs themselves. Using ROMRAM will allow ++ the program to exist in ROM, but be copied to RAM during startup." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { ++ display "Diagnostic serial port baud rate" ++ flavor data ++ legal_values 9600 19200 38400 57600 115200 ++ default_value 115200 ++ description " ++ This option selects the baud rate used for the console port. ++ Note: this should match the value chosen for the GDB port if the ++ console and GDB port are the same." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { ++ display "GDB serial port baud rate" ++ flavor data ++ legal_values 9600 19200 38400 57600 115200 ++ default_value 115200 ++ description " ++ This option selects the baud rate used for the GDB port. ++ Note: this should match the value chosen for the console port if the ++ console and GDB port are the same." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { ++ display "Number of communication channels on the board" ++ flavor data ++ calculated 6 ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { ++ display "Debug serial port" ++ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ default_value 0 ++ description " ++ The board has three serial ports. This option ++ chooses which port will be used to connect to a host ++ running GDB." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { ++ display "Default console channel." ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ calculated 0 ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { ++ display "Console serial port" ++ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT ++ description " ++ The board has only three serial ports. This option ++ chooses which port will be used for console output." ++ } ++ ++ cdl_component CYGBLD_GLOBAL_OPTIONS { ++ display "Global build options" ++ flavor none ++ no_define ++ description " ++ Global build options including control over ++ compiler flags, linker flags and choice of toolchain." ++ ++ ++ parent CYGPKG_NONE ++ ++ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { ++ display "Global command prefix" ++ flavor data ++ no_define ++ default_value { "arm-none-eabi" } ++ description " ++ This option specifies the command prefix used when ++ invoking the build tools." ++ } ++ ++ cdl_option CYGBLD_GLOBAL_CFLAGS { ++ display "Global compiler flags" ++ flavor data ++ no_define ++ default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } ++ description " ++ This option controls the global compiler flags which are used to ++ compile all packages by default. Individual packages may define ++ options which override these global flags." ++ } ++ ++ cdl_option CYGBLD_GLOBAL_LDFLAGS { ++ display "Global linker flags" ++ flavor data ++ no_define ++ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } ++ description " ++ This option controls the global linker flags. Individual ++ packages may define options which override these global flags." ++ } ++ ++ cdl_option CYGBLD_BUILD_GDB_STUBS { ++ display "Build GDB stub ROM image" ++ default_value 0 ++ requires { CYG_HAL_STARTUP == "ROM" } ++ requires CYGSEM_HAL_ROM_MONITOR ++ requires CYGBLD_BUILD_COMMON_GDB_STUBS ++ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT ++ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT ++ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++ no_define ++ description " ++ This option enables the building of the GDB stubs for the ++ board. The common HAL controls takes care of most of the ++ build process, but the final conversion from ELF image to ++ binary data is handled by the platform CDL, allowing ++ relocation of the data if necessary." ++ ++ make -priority 320 { ++ /bin/gdb_module.bin : /bin/gdb_module.img ++ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ ++ } ++ } ++ } ++ ++ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS { ++ display "Freescale MXC Board build options" ++ flavor none ++ no_define ++ description " ++ Package specific build options including control over ++ compiler flags used only in building this package, ++ and details of which tests are built." ++ ++ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building the board HAL. These flags are used in addition ++ to the set of global flags." ++ } ++ ++ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE { ++ display "Suppressed compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building the board HAL. These flags are removed from ++ the set of global flags if present." ++ } ++ ++ } ++ ++ cdl_component CYGHWR_MEMORY_LAYOUT { ++ display "Memory layout" ++ flavor data ++ no_define ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" : ++ "arm_board_rom" } ++ ++ cdl_option CYGHWR_MEMORY_LAYOUT_LDI { ++ display "Memory layout linker script fragment" ++ flavor data ++ no_define ++ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "" : ++ "" } ++ } ++ ++ cdl_option CYGHWR_MEMORY_LAYOUT_H { ++ display "Memory layout header file" ++ flavor data ++ no_define ++ define -file system.h CYGHWR_MEMORY_LAYOUT_H ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "" : ++ "" } ++ } ++ } ++ ++ cdl_option CYGSEM_HAL_ROM_MONITOR { ++ display "Behave as a ROM monitor" ++ flavor bool ++ default_value 0 ++ parent CYGPKG_HAL_ROM_MONITOR ++ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } ++ description " ++ Enable this option if this program is to be used as a ROM monitor, ++ i.e. applications will be loaded into RAM on the board, and this ++ ROM monitor may process exceptions or interrupts generated from the ++ application. This enables features such as utilizing a separate ++ interrupt stack when exceptions are generated." ++ } ++ ++ cdl_option CYGSEM_HAL_USE_ROM_MONITOR { ++ display "Work with a ROM monitor" ++ flavor booldata ++ legal_values { "Generic" "GDB_stubs" } ++ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } ++ parent CYGPKG_HAL_ROM_MONITOR ++ requires { CYG_HAL_STARTUP == "RAM" } ++ description " ++ Support can be enabled for different varieties of ROM monitor. ++ This support changes various eCos semantics such as the encoding ++ of diagnostic output, or the overriding of hardware interrupt ++ vectors. ++ Firstly there is \"Generic\" support which prevents the HAL ++ from overriding the hardware vectors that it does not use, to ++ instead allow an installed ROM monitor to handle them. This is ++ the most basic support which is likely to be common to most ++ implementations of ROM monitor. ++ \"GDB_stubs\" provides support when GDB stubs are included in ++ the ROM monitor or boot ROM." ++ } ++ ++ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { ++ display "Redboot HAL options" ++ flavor none ++ no_define ++ parent CYGPKG_REDBOOT ++ active_if CYGPKG_REDBOOT ++ description " ++ This option lists the target's requirements for a valid Redboot ++ configuration." ++ ++ compile -library=libextras.a redboot_cmds.c ++ ++ cdl_option CYGBLD_BUILD_REDBOOT_BIN { ++ display "Build Redboot ROM binary image" ++ active_if CYGBLD_BUILD_REDBOOT ++ default_value 1 ++ no_define ++ description "This option enables the conversion of the Redboot ELF ++ image to a binary image suitable for ROM programming." ++ ++ make -priority 325 { ++ /bin/redboot.bin : /bin/redboot.elf ++ $(OBJCOPY) --strip-debug $< $(@:.bin=.img) ++ $(OBJCOPY) -O srec $< $(@:.bin=.srec) ++ $(OBJCOPY) -O binary $< $@ ++ } ++ } ++ } ++ ++ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS { ++ display "Redboot HAL variant options" ++ flavor none ++ no_define ++ parent CYGPKG_REDBOOT ++ active_if CYGPKG_REDBOOT ++ ++ # RedBoot details ++ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 } ++ define_proc { ++ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/fsl_board.h redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/fsl_board.h +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/fsl_board.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/fsl_board.h 2010-01-26 17:35:49.952964753 +0000 +@@ -0,0 +1,79 @@ ++#ifndef CYGONCE_FSL_BOARD_H ++#define CYGONCE_FSL_BOARD_H ++ ++//============================================================================= ++// ++// Platform specific support (register layout, etc) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include // Hardware definitions ++ ++/* CPLD offsets */ ++#define PBC_LED_CTRL (0x20000) ++#define PBC_SB_STAT (0x20008) ++#define PBC_ID_AAAA (0x20040) ++#define PBC_ID_5555 (0x20048) ++#define PBC_VERSION (0x20050) ++#define PBC_ID_CAFE (0x20058) ++#define PBC_INT_STAT (0x20010) ++#define PBC_INT_MASK (0x20038) ++#define PBC_INT_REST (0x20020) ++#define PBC_SW_RESET (0x20060) ++#define BOARD_CS_UART_BASE (0x8000) ++ ++#define FEC_PHY_ADDR 0x06 ++#define REDBOOT_IMAGE_SIZE 0x40000 ++ ++#define EXT_UART_x16 ++/* MX51 3-Stack SDRAM is from 0x40000000, 128M */ ++#define SDRAM_BASE_ADDR CSD0_BASE_ADDR ++#define SDRAM_SIZE 0x08000000 ++#define RAM_BANK0_BASE SDRAM_BASE_ADDR ++ ++#define LED_MAX_NUM 8 ++ ++#define LCD_HEIGHT 640 // physical display height in pixel ++#define LCD_WIDTH 480 // physical display width in pixel ++#define DISPLAY_CHANNEL 28 ++#define DISPLAY_BUFFER_ADDR (SDRAM_BASE_ADDR + CYGMEM_REGION_ram_SIZE - 0x400000) ++ ++//#define ROTATE_NONE ++#define ROTATE_90 ++#define FONT_STRETCH_X 1 ++#define FONT_STRETCH_Y 2 ++ ++#endif /* CYGONCE_FSL_BOARD_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/hal_platform_setup.h redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/hal_platform_setup.h +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/hal_platform_setup.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/hal_platform_setup.h 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,625 @@ ++#ifndef CYGONCE_HAL_PLATFORM_SETUP_H ++#define CYGONCE_HAL_PLATFORM_SETUP_H ++ ++//============================================================================= ++// ++// hal_platform_setup.h ++// ++// Platform specific support for HAL (assembly code) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include // System-wide configuration info ++#include CYGBLD_HAL_VARIANT_H // Variant specific configuration ++#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration ++#include // Variant specific hardware definitions ++#include // MMU definitions ++#include // Platform specific hardware definitions ++ ++#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) ++#define PLATFORM_SETUP1 _platform_setup1 ++#define CYGHWR_HAL_ARM_HAS_MMU ++ ++#ifdef CYG_HAL_STARTUP_ROMRAM ++#define CYGSEM_HAL_ROM_RESET_USES_JUMP ++#endif ++ ++//#define NFC_2K_BI_SWAP ++#define SDRAM_FULL_PAGE_BIT 0x100 ++#define SDRAM_FULL_PAGE_MODE 0x37 ++#define SDRAM_BURST_MODE 0x33 ++ ++#define CYGHWR_HAL_ROM_VADDR 0x0 ++ ++#if 0 ++#define UNALIGNED_ACCESS_ENABLE ++#define SET_T_BIT_DISABLE ++#define BRANCH_PREDICTION_ENABLE ++#endif ++ ++#define DCDGEN(i,type, addr, data) \ ++dcd_##i: ;\ ++ .long type ;\ ++ .long addr ;\ ++ .long data ++ ++#define PLATFORM_PREAMBLE flash_header ++//flash header & DCD @ 0x400 ++.macro flash_header ++ b reset_vector ++ .org 0x400 ++app_code_jump_v: .long reset_vector ++app_code_barker: .long 0xB1 // barker code ++app_code_csf: .long (0x97f40000 - 0x1000) // reserve 4K for csf ++dcd_ptr_ptr: .long dcd_ptr ++super_root_key: .long hab_super_root_key ++dcd_ptr: .long dcd_data ++app_dest_ptr: .long 0x97f00000 ++ ++dcd_data: .long 0xB17219E9 // Fixed. can't change. ++ ++#ifdef IMX51_MDDR ++// DCD ++dcd_len: .long (38*12) ++// DDR IOMUX configuration ++// Control, Data, Address pads are in their default state: HIGH DS, FAST SR. ++DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x4b8, 0x000000e7) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS ++DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x4d4, 0x000000e4) // DQM0 DS high, slew rate slow ++DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x4d8, 0x000000e4) // DQM1 DS high, slew rate slow ++DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x4dc, 0x000000e4) // DQM2 DS high, slew rate slow ++DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x4e0, 0x000000e4) // DQM3 DS high, slew rate slow ++DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x000000c4) // SDQS0 DS high, slew rate slow ++DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x000000c4) // SDQS1 DS high, slew rate slow ++DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x000000c4) // SDQS2 DS high, slew rate slow ++DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x000000c4) // SDQS3 DS high, slew rate slow ++DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000004) // DRAM_B0 ++DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000004) // DRAM_B1 ++DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000004) // DRAM_B2 ++DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x82c, 0x00000004) // DRAM_B3 ++DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x878, 0x00000000) // DRAM_B0_SR ++DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x880, 0x00000000) // DRAM_B1_SR ++DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x88c, 0x00000000) // DRAM_B2_SR ++DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x89c, 0x00000000) // DRAM_B3_SR ++// Configure CS0 ++DCDGEN(18, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x83220000) // ESDCTL0: Enable controller ++DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) // ESDSCR: Precharge command ++DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command ++DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command ++DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) ++DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801a) // ESDSCR: EMR with Half Drive strength ++DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) // ESDSCR ++DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000) // ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 ++// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks ++// tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks ++DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xC33574AA) ++DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000a1700) // ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 ++// Configure CS1 ++DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x83220000) // ESDCTL1: Enable controller ++DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) // ESDSCR: Precharge command ++DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command ++DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command ++DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0033801c) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) ++DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801e) // ESDSCR: EMR with Half Drive strength ++DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) // ESDSCR ++DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xC3220000) // ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 ++// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks ++// tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks ++DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0xC33574AA) ++DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) // ESDSCR - clear "configuration request" bit ++DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00f58000) //Delay line write - -11 ++ ++#else ++dcd_len: .long (57*12) ++ ++//DCD ++//DDR2 IOMUX configuration ++DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) ++DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) ++DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) ++DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) ++DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) ++DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) ++DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) ++DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) ++DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) ++DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) ++DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) ++DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) ++DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) ++DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) ++DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) ++DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) ++DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) ++DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) ++//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model ++//CAS=3, BL=4 ++DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) ++DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) ++DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) ++DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) ++DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) ++// Init DRAM on CS0 ++DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) ++DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) ++DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) ++DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019) ++DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) ++DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) ++DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) ++DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) ++DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) ++DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) ++DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019) ++DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) ++ ++// Init DRAM on CS1 ++DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) ++DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) ++DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) ++DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) ++DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) ++DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) ++DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) ++DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) ++DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) ++DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) ++DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d) ++DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) ++ ++DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) ++DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) ++DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) ++DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) ++DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) ++ ++// Delay settings ++DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000) ++DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000) ++DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000) ++DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000) ++DCDGEN(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000) ++#endif ++image_len: .long 256 * 1024 // 256K for Redboot and csf ++ ++.endm ++ ++//#define ENABLE_IMPRECISE_ABORT ++ ++// This macro represents the initial startup code for the platform ++ .macro _platform_setup1 ++FSL_BOARD_SETUP_START: ++ ldr r1, =ROM_BASE_ADDRESS ++ ldr r3, [r1, #ROM_SI_REV_OFFSET] ++ ++ setup_sdram ++ ++ ldr r0, =GPC_BASE_ADDR ++ cmp r3, #0x10 // r3 contains the silicon rev ++ ldrls r1, =0x1FC00000 ++ ldrhi r1, =0x1A800000 ++ str r1, [r0, #4] ++ ++#ifdef ENABLE_IMPRECISE_ABORT ++ mrs r1, spsr // save old spsr ++ mrs r0, cpsr // read out the cpsr ++ bic r0, r0, #0x100 // clear the A bit ++ msr spsr, r0 // update spsr ++ add lr, pc, #0x8 // update lr ++ movs pc, lr // update cpsr ++ nop ++ nop ++ nop ++ nop ++ msr spsr, r1 // restore old spsr ++#endif ++ ++ // explicitly disable L2 cache ++ mrc 15, 0, r0, c1, c0, 1 ++ bic r0, r0, #0x2 ++ mcr 15, 0, r0, c1, c0, 1 ++ ++ // reconfigure L2 cache aux control reg ++ mov r0, #0xC0 // tag RAM ++ add r0, r0, #0x4 // data RAM ++ orr r0, r0, #(1 << 24) // disable write allocate delay ++ orr r0, r0, #(1 << 23) // disable write allocate combine ++ orr r0, r0, #(1 << 22) // disable write allocate ++ ++ cmp r3, #0x10 // r3 contains the silicon rev ++ orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs ++ ++ mcr 15, 1, r0, c9, c0, 2 ++ ++init_aips_start: ++ init_aips ++init_m4if_start: ++ init_m4if ++ ++#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */ ++ /* Check if need to copy image to Redboot ROM space */ ++ ldr r0, =0xFFFFF000 ++ and r0, r0, pc ++ ldr r1, MXC_REDBOOT_ROM_START ++ cmp r0, r1 ++ beq skip_copy_to_ddr ++ ++ add r2, r0, #REDBOOT_IMAGE_SIZE ++ ++1: ldmia r0!, {r3-r10} ++ stmia r1!, {r3-r10} ++ cmp r0, r2 ++ ble 1b ++ /* Jump to SDRAM */ ++ ldr r1, =0xFFFF ++ and r0, pc, r1 /* offset of pc */ ++ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8) ++ add pc, r0, r1 ++ nop ++ nop ++ nop ++ nop ++#endif /* CYG_HAL_STARTUP_ROMRAM */ ++ ++skip_copy_to_ddr: ++ /* Skip clock setup if already booted up */ ++ ldr r0, =IRAM_BASE_ADDR ++ ldr r0, [r0] ++ ldr r1, =FROM_SPI_NOR_FLASH ++ cmp r0, r1 ++ beq Normal_Boot_Continue ++ ldr r1, =FROM_MMC_FLASH ++ cmp r0, r1 ++ beq Normal_Boot_Continue ++ ldr r1, =FROM_NAND_FLASH ++ cmp r0, r1 ++ beq Normal_Boot_Continue ++ ++init_clock_start: ++ init_clock ++ ++Normal_Boot_Continue: ++ ++/* ++ * Note: ++ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity ++ */ ++STACK_Setup: ++ // Set up a stack [for calling C code] ++ ldr r1, =__startup_stack ++ ldr r2, =RAM_BANK0_BASE ++ orr sp, r1, r2 ++ ++ // Create MMU tables ++ bl hal_mmu_init ++ ++ /* Workaround for arm errata #709718 */ ++ //Setup PRRR so device is always mapped to non-shared ++ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register ++ bic r1, #(3 << 16) ++ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register ++ ++ // Enable MMU ++ ldr r2, =10f ++ mrc MMU_CP, 0, r1, MMU_Control, c0 ++ orr r1, r1, #7 // enable MMU bit ++ orr r1, r1, #0x800 // enable z bit ++ orr r1, r1, #(1 << 28) // Enable TEX remap ++ mcr MMU_CP, 0, r1, MMU_Control, c0 ++ ++ /* Workaround for arm errata #621766 */ ++ mrc MMU_CP, 0, r1, MMU_Control, c0, 1 ++ orr r1, r1, #(1 << 5) // enable L1NEON bit ++ mcr MMU_CP, 0, r1, MMU_Control, c0, 1 ++ ++ mov pc,r2 /* Change address spaces */ ++ nop ++ nop ++ nop ++10: ++ ++ // Save shadow copy of BCR, also hardware configuration ++ ldr r1, =_board_BCR ++ str r2, [r1] ++ ldr r1, =_board_CFG ++ str r9, [r1] // Saved far above... ++ ++ .endm // _platform_setup1 ++ ++#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) ++#define PLATFORM_SETUP1 ++#endif ++ ++ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ ++ .macro init_aips ++ /* ++ * Set all MPROTx to be non-bufferable, trusted for R/W, ++ * not forced to user-mode. ++ */ ++ ldr r0, AIPS1_CTRL_BASE_ADDR_W ++ ldr r1, AIPS1_PARAM_W ++ str r1, [r0, #0x00] ++ str r1, [r0, #0x04] ++ ldr r0, AIPS2_CTRL_BASE_ADDR_W ++ str r1, [r0, #0x00] ++ str r1, [r0, #0x04] ++ ++ .endm /* init_aips */ ++ ++ .macro init_clock ++ ldr r0, CCM_BASE_ADDR_W ++ ++ /* Gate of clocks to the peripherals first */ ++ ldr r1, =0x3FFFFFFF ++ str r1, [r0, #CLKCTL_CCGR0] ++ ldr r1, =0x0 ++ str r1, [r0, #CLKCTL_CCGR1] ++ str r1, [r0, #CLKCTL_CCGR2] ++ str r1, [r0, #CLKCTL_CCGR3] ++ ++ ldr r1, =0x00030000 ++ str r1, [r0, #CLKCTL_CCGR4] ++ ldr r1, =0x00FFF030 ++ str r1, [r0, #CLKCTL_CCGR5] ++ ldr r1, =0x00000300 ++ str r1, [r0, #CLKCTL_CCGR6] ++ ++ /* Disable IPU and HSC dividers */ ++ mov r1, #0x60000 ++ str r1, [r0, #CLKCTL_CCDR] ++ ++ /* Make sure to switch the DDR away from PLL 1 */ ++ ldr r1, CCM_VAL_0x19239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ /* make sure divider effective */ ++ 1: ldr r1, [r0, #CLKCTL_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++ ++ /* Switch ARM to step clock */ ++ mov r1, #0x4 ++ str r1, [r0, #CLKCTL_CCSR] ++ setup_pll PLL1, 800 ++ ++ setup_pll PLL3, 665 ++ /* Switch peripheral to PLL 3 */ ++ ldr r0, CCM_BASE_ADDR_W ++ ldr r1, CCM_VAL_0x000010C0 ++ str r1, [r0, #CLKCTL_CBCMR] ++ ldr r1, CCM_VAL_0x13239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ setup_pll PLL2, 665 ++ /* Switch peripheral to PLL 2 */ ++ ldr r0, CCM_BASE_ADDR_W ++ ldr r1, CCM_VAL_0x19239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ ldr r1, CCM_VAL_0x000020C0 ++ str r1, [r0, #CLKCTL_CBCMR] ++ ++ setup_pll PLL3, 216 ++ ++ /* Set the platform clock dividers */ ++ ldr r0, PLATFORM_BASE_ADDR_W ++ ldr r1, PLATFORM_CLOCK_DIV_W ++ str r1, [r0, #PLATFORM_ICGC] ++ ++ ldr r0, CCM_BASE_ADDR_W ++ /* Run at slower speed we increase VDDGP */ ++ mov r1, #0x1 ++ str r1, [r0, #CLKCTL_CACRR] ++ ++ /* Switch ARM back to PLL 1. */ ++ mov r1, #0x0 ++ str r1, [r0, #CLKCTL_CCSR] ++ ++ /* setup the rest */ ++ /* Use lp_apm (24MHz) source for perclk */ ++ ldr r1, CCM_VAL_0x000020C2 ++ str r1, [r0, #CLKCTL_CBCMR] ++ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz ++#ifdef IMX51_MDDR ++ ldr r1, CCM_VAL_0x61E35100 ++#else ++ ldr r1, CCM_VAL_0x59E35100 ++#endif ++ str r1, [r0, #CLKCTL_CBCDR] ++ ++ /* Restore the default values in the Gate registers */ ++ ldr r1, =0xFFFFFFFF ++ str r1, [r0, #CLKCTL_CCGR0] ++ str r1, [r0, #CLKCTL_CCGR1] ++ str r1, [r0, #CLKCTL_CCGR2] ++ str r1, [r0, #CLKCTL_CCGR3] ++ str r1, [r0, #CLKCTL_CCGR4] ++ str r1, [r0, #CLKCTL_CCGR5] ++ str r1, [r0, #CLKCTL_CCGR6] ++ ++ /* Use PLL 2 for UART's, get 66.5MHz from it */ ++ ldr r1, CCM_VAL_0xA5A2A020 ++ str r1, [r0, #CLKCTL_CSCMR1] ++ ldr r1, CCM_VAL_0x00C30321 ++ str r1, [r0, #CLKCTL_CSCDR1] ++ ++ /* make sure divider effective */ ++ 1: ldr r1, [r0, #CLKCTL_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++ ++ mov r1, #0x00000 ++ str r1, [r0, #CLKCTL_CCDR] ++ ++ // for cko - for ARM div by 8 ++ mov r1, #0x000A0000 ++ add r1, r1, #0x00000F0 ++ str r1, [r0, #CLKCTL_CCOSR] ++ .endm /* init_clock */ ++ ++ .macro setup_pll pll_nr, mhz ++ ldr r0, BASE_ADDR_W_\pll_nr ++ ldr r1, PLL_VAL_0x1232 ++ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ ++ ldr r1, =0x2 ++ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ ++ ++ ldr r1, W_DP_OP_\mhz ++ str r1, [r0, #PLL_DP_OP] ++ str r1, [r0, #PLL_DP_HFS_OP] ++ ++ ldr r1, W_DP_MFD_\mhz ++ str r1, [r0, #PLL_DP_MFD] ++ str r1, [r0, #PLL_DP_HFS_MFD] ++ ++ ldr r1, W_DP_MFN_\mhz ++ str r1, [r0, #PLL_DP_MFN] ++ str r1, [r0, #PLL_DP_HFS_MFN] ++ ++ /* Now restart PLL */ ++ ldr r1, PLL_VAL_0x1232 ++ str r1, [r0, #PLL_DP_CTL] ++wait_pll_lock\pll_nr\mhz: ++ ldr r1, [r0, #PLL_DP_CTL] ++ ands r1, r1, #0x1 ++ beq wait_pll_lock\pll_nr\mhz ++ .endm ++ ++ /* M3IF setup */ ++ .macro init_m4if ++ ldr r1, M4IF_BASE_W ++ ldr r0, M4IF_0x00000203 ++ str r0, [r1, #M4IF_FBPM0] ++ ++ ldr r0, =0x0 ++ str r0, [r1, #M4IF_FBPM1] ++ ++ ldr r0, M4IF_0x00120125 ++ str r0, [r1, #M4IF_FPWC] ++ ++ ldr r0, M4IF_0x001901A3 ++ str r0, [r1, #M4IF_MIF4] ++ ++ .endm /* init_m4if */ ++ ++ .macro setup_sdram ++ cmp r3, #0x10 // r3 contains the silicon rev ++ bls skip_setup ++ /* Decrease the DRAM SDCLK to HIGH Drive strength */ ++ ldr r0, IOMUXC_BASE_ADDR_W ++ ldr r1, =0x000000e5 ++ str r1, [r0, #0x4b8] ++ /* Change the delay line configuration */ ++ ldr r0, ESDCTL_BASE_W ++ ldr r1, =0x00f49400 ++ str r1, [r0, #ESDCTL_ESDCDLY1] ++ ldr r1, =0x00f49a00 ++ str r1, [r0, #ESDCTL_ESDCDLY2] ++ ldr r1, =0x00f49100 ++ str r1, [r0, #ESDCTL_ESDCDLY3] ++ ldr r1, =0x00f48900 ++ str r1, [r0, #ESDCTL_ESDCDLY4] ++ ldr r1, =0x00f49400 ++ str r1, [r0, #ESDCTL_ESDCDLY5] ++skip_setup: ++ .endm ++ ++#define PLATFORM_VECTORS _platform_vectors ++ .macro _platform_vectors ++ .globl _board_BCR, _board_CFG ++_board_BCR: .long 0 // Board Control register shadow ++_board_CFG: .long 0 // Board Configuration (read at RESET) ++ .endm ++ ++IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF ++AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR ++AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR ++AIPS1_PARAM_W: .word 0x77777777 ++MAX_BASE_ADDR_W: .word MAX_BASE_ADDR ++MAX_PARAM1: .word 0x00302154 ++ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR ++M4IF_BASE_W: .word M4IF_BASE_ADDR ++M4IF_0x00120125: .word 0x00120125 ++M4IF_0x001901A3: .word 0x001901A3 ++M4IF_0x00000203: .word 0x00000203 ++SDRAM_0x04008008: .word 0x04008008 ++SDRAM_0x00008010: .word 0x00008010 ++SDRAM_0x00338018: .word 0x00338018 ++SDRAM_0xB2220000: .word 0xB2220000 ++SDRAM_0x899F6BBA: .word 0x899F6BBA ++SDRAM_0xB02567A9: .word 0xB02567A9 ++SDRAM_0x000A0104: .word 0x000A0104 ++IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR ++MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 ++CONST_0x0FFF: .word 0x0FFF ++CCM_BASE_ADDR_W: .word CCM_BASE_ADDR ++CCM_VAL_0x0000E3C2: .word 0x0000E3C2 ++CCM_VAL_0x000020C2: .word 0x000020C2 ++CCM_VAL_0x013B9100: .word 0x013B9100 ++CCM_VAL_0x59E35100: .word 0x59E35100 ++CCM_VAL_0x61E35100: .word 0x61E35100 ++CCM_VAL_0x19239145: .word 0x19239145 ++CCM_VAL_0xA5A2A020: .word 0xA5A2A020 ++CCM_VAL_0x00C30321: .word 0x00C30321 ++CCM_VAL_0x000010C0: .word 0x000010C0 ++CCM_VAL_0x13239145: .word 0x13239145 ++CCM_VAL_0x000020C0: .word 0x000020C0 ++PLL_VAL_0x222: .word 0x222 ++PLL_VAL_0x232: .word 0x232 ++BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR ++BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR ++BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR ++PLL_VAL_0x1232: .word 0x1232 ++W_DP_OP_800: .word DP_OP_800 ++W_DP_MFD_800: .word DP_MFD_800 ++W_DP_MFN_800: .word DP_MFN_800 ++W_DP_OP_700: .word DP_OP_700 ++W_DP_MFD_700: .word DP_MFD_700 ++W_DP_MFN_700: .word DP_MFN_700 ++W_DP_OP_400: .word DP_OP_400 ++W_DP_MFD_400: .word DP_MFD_400 ++W_DP_MFN_400: .word DP_MFN_400 ++W_DP_OP_532: .word DP_OP_532 ++W_DP_MFD_532: .word DP_MFD_532 ++W_DP_MFN_532: .word DP_MFN_532 ++W_DP_OP_665: .word DP_OP_665 ++W_DP_MFD_665: .word DP_MFD_665 ++W_DP_MFN_665: .word DP_MFN_665 ++W_DP_OP_216: .word DP_OP_216 ++W_DP_MFD_216: .word DP_MFD_216 ++W_DP_MFN_216: .word DP_MFN_216 ++PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR ++PLATFORM_CLOCK_DIV_W: .word 0x00000124 ++ ++/*---------------------------------------------------------------------------*/ ++/* end of hal_platform_setup.h */ ++#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.h redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.h +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.h 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,20 @@ ++// eCos memory layout - Fri Oct 20 05:56:55 2000 ++ ++// This is a generated file - do not edit ++ ++#ifndef __ASSEMBLER__ ++#include ++#include ++ ++#endif ++#define CYGMEM_REGION_ram (0x00000000) ++#define CYGMEM_REGION_ram_SIZE (0x7F00000) ++#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) ++#define CYGMEM_REGION_rom (0x97F00000) ++#define CYGMEM_REGION_rom_SIZE (0x100000) ++#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) ++#ifndef __ASSEMBLER__ ++extern char CYG_LABEL_NAME (__heap1) []; ++#endif ++#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) ++#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.ldi redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.ldi +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.ldi 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.ldi 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,31 @@ ++// eCos memory layout - Fri Oct 20 05:56:55 2000 ++ ++// This is a generated file - do not edit ++ ++#include ++ ++MEMORY ++{ ++ ram : ORIGIN = 0, LENGTH = 0x7F00000 ++ rom : ORIGIN = 0x97F00000, LENGTH = 0x100000 ++} ++ ++SECTIONS ++{ ++ SECTIONS_BEGIN ++ SECTION_rom_vectors (rom, 0x97F00000, LMA_EQ_VMA) ++ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) ++ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) ++ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) ++ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); ++ SECTIONS_END ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.mlt redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.mlt +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.mlt 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/pkgconf/mlt_arm_board_romram.mlt 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,14 @@ ++version 0 ++region ram 0 7F00000 0 ! ++region rom 97F00000 100000 1 ! ++section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! ++section data 0 1 1 1 1 1 0 0 8000 bss ! ++section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! ++section heap1 0 8 0 0 0 0 0 0 ! ++section rom_vectors 0 1 0 1 1 1 1 1 97F00000 97F00000 text text ! ++section text 0 4 0 1 0 1 0 1 fini fini ! ++section fini 0 4 0 1 0 1 0 1 rodata rodata ! ++section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! ++section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! ++section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! ++section gcc_except_table 0 4 0 1 0 0 0 1 data ! +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/plf_io.h redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/plf_io.h +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/plf_io.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/plf_io.h 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,128 @@ ++#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H ++#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H ++ ++//============================================================================= ++// ++// plf_io.h ++// ++// Platform specific support (register layout, etc) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++ ++#include ++#include ++ ++extern unsigned int cpld_base_addr; ++ ++#define LAN92XX_REG_READ(reg_offset) \ ++ (*(volatile unsigned int *)(cpld_base_addr + reg_offset)) ++ ++#define LAN92XX_REG_WRITE(reg_offset, val) \ ++ (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val)) ++ ++#define LED_IS_ON(n) ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0) ++#define TURN_LED_ON(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) | (1 << (n))), cpld_base_addr + PBC_LED_CTRL) ++#define TURN_LED_OFF(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) & (~(1<<(n)))), cpld_base_addr + PBC_LED_CTRL) ++ ++#define BOARD_DEBUG_LED(n) 0 ++/* ++#define BOARD_DEBUG_LED(n) \ ++ CYG_MACRO_START \ ++ if (n >= 0 && n < LED_MAX_NUM) { \ ++ if (LED_IS_ON(n)) \ ++ TURN_LED_OFF(n); \ ++ else \ ++ TURN_LED_ON(n); \ ++ } \ ++ CYG_MACRO_END ++*/ ++ ++extern unsigned int system_rev; ++ ++#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \ ++ CYG_MACRO_START \ ++ { \ ++ extern unsigned int system_rev; \ ++ /* Next ATAG_MEM. */ \ ++ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \ ++ _p_->hdr.tag = ATAG_MEM; \ ++ /* Round up so there's only one bit set in the memory size. \ ++ * Don't double it if it's already a power of two, though. \ ++ */ \ ++ _p_->u.mem.size = 1<u.mem.size < CYGMEM_REGION_ram_SIZE) \ ++ _p_->u.mem.size <<= 1; \ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) \ ++ _p_->u.mem.size = 512 * 0x100000; \ ++ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \ ++ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \ ++ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \ ++ _p_->hdr.tag = ATAG_REVISION; \ ++ _p_->u.revision.rev = system_rev; \ ++ } \ ++ CYG_MACRO_END ++//----------------------------------------------------------------------------- ++// IDE interface macros ++// ++// Special I/O access functions ++externC int imx_ide_hwr_init(void); ++externC cyg_uint8 imx_ide_read_uint8(int ctlr, cyg_uint32 reg); ++externC void imx_ide_write_uint8(int ctlr, cyg_uint32 reg, cyg_uint8 val); ++externC cyg_uint16 imx_ide_read_uint16(int ctlr, cyg_uint32 reg); ++externC void imx_ide_write_uint16(int ctlr, cyg_uint32 reg, cyg_uint16 val); ++externC void imx_ide_write_control(int ctlr, cyg_uint8 val); ++ ++#define HAL_IDE_NUM_CONTROLLERS 1 ++ ++#define HAL_IDE_READ_UINT8( __ctlr, __reg, __val) \ ++ __val = imx_ide_read_uint8((__ctlr), (__reg)) ++ ++#define HAL_IDE_READ_UINT16( __ctlr, __reg, __val) \ ++ __val = imx_ide_read_uint16((__ctlr), (__reg)) ++ ++#define HAL_IDE_WRITE_UINT8( __ctlr, __reg, __val) \ ++ imx_ide_write_uint8((__ctlr), (__reg), (__val)) ++ ++#define HAL_IDE_WRITE_UINT16( __ctlr, __reg, __val) \ ++ imx_ide_write_uint16((__ctlr), (__reg), (__val)) ++ ++ ++#define HAL_IDE_WRITE_CONTROL( __ctlr, __val) \ ++ imx_ide_write_control((__ctlr), (__val)) ++ ++#define HAL_IDE_INIT() imx_ide_hwr_init() ++ ++#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/plf_mmap.h redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/plf_mmap.h +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/include/plf_mmap.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/include/plf_mmap.h 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,94 @@ ++#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H ++#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H ++//============================================================================= ++// ++// plf_mmap.h ++// ++// Platform specific memory map support ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include ++ ++// Get the pagesize for a particular virtual address: ++ ++// This does not depend on the vaddr. ++#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \ ++ (pagesize) = SZ_1M; \ ++CYG_MACRO_END ++ ++// Get the physical address from a virtual address: ++ ++#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \ ++ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \ ++ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \ ++ _v_ += SDRAM_BASE_ADDR; \ ++ else /* Rest of it */ \ ++ /* no change */ ; \ ++ (paddr) = _v_; \ ++CYG_MACRO_END ++ ++//--------------------------------------------------------------------------- ++ ++/* ++ * translate the virtual address of ram space to physical address ++ * It is dependent on the implementation of hal_mmu_init ++ */ ++static unsigned long __inline__ hal_virt_to_phy(unsigned long virt) ++{ ++ if(virt < 0x08000000) { ++ return virt|0x90000000; ++ } ++ if((virt & 0xF0000000) == 0x90000000) { ++ return virt&(~0x08000000); ++ } ++ return virt; ++} ++ ++/* ++ * remap the physical address of ram space to uncacheable virtual address space ++ * It is dependent on the implementation of hal_mmu_init ++ */ ++static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy) ++{ ++ /* 0x98000000~0x9FFFFFFF is uncacheable meory space which is mapped to SDRAM*/ ++ if((phy & 0xF0000000) == 0x90000000) { ++ phy |= 0x08000000; ++ } ++ return phy; ++} ++ ++#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM.ecm redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM.ecm +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM.ecm 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM.ecm 2010-01-26 17:35:49.972960878 +0000 +@@ -0,0 +1,158 @@ ++cdl_savefile_version 1; ++cdl_savefile_command cdl_savefile_version {}; ++cdl_savefile_command cdl_savefile_command {}; ++cdl_savefile_command cdl_configuration { description hardware template package }; ++cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; ++ ++cdl_configuration eCos { ++ description "" ; ++ hardware mx51_3stack ; ++ template redboot ; ++ package -hardware CYGPKG_HAL_ARM current ; ++ package -hardware CYGPKG_HAL_ARM_MX51 current ; ++ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ; ++ package -hardware CYGPKG_IMX_COMMON current ; ++ package -hardware CYGPKG_IO_SERIAL_ARM_IMX ; ++ package -hardware CYGPKG_IO_ETH_DRIVERS current ; ++ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ; ++ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ; ++ #package -hardware CYGPKG_DEVS_ETH_FEC current ; ++ package -hardware CYGPKG_COMPRESS_ZLIB current ; ++ package -hardware CYGPKG_DIAGNOSIS current ; ++ package -hardware CYGPKG_IO_FLASH current ; ++ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ; ++ package -hardware CYGPKG_DEVS_IMX_SPI current ; ++ package -hardware CYGPKG_DEVS_MXC_I2C current ; ++ package -hardware CYGPKG_DEVS_IMX_IPU current ; ++ package -template CYGPKG_HAL current ; ++ package -template CYGPKG_INFRA current ; ++ package -template CYGPKG_REDBOOT current ; ++ package -template CYGPKG_ISOINFRA current ; ++ package -template CYGPKG_LIBC_STRING current ; ++ package -template CYGPKG_CRC current ; ++ package CYGPKG_MEMALLOC current ; ++ package -hardware CYGPKG_IO_DISK current; ++}; ++ ++cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MMC { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IMX_ECSPI { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IPU_3_EX { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_IMX_DISPLAY { ++ inferred_value 1 ++}; ++ ++cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { ++ inferred_value 0 ++}; ++ ++cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { ++ user_value 4096 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { ++ user_value 0 ++}; ++ ++cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { ++ user_value 50 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { ++ inferred_value 0 ++}; ++ ++cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { ++ inferred_value 1 ++}; ++ ++cdl_option CYGSEM_HAL_ROM_MONITOR { ++ inferred_value 1 ++}; ++ ++cdl_component CYGBLD_BUILD_REDBOOT { ++ user_value 1 ++}; ++ ++cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { ++ inferred_value 0x00040000 ++}; ++ ++cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { ++ inferred_value 0x90008000 ++}; ++ ++cdl_option CYGBLD_ISO_STRTOK_R_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_component CYG_HAL_STARTUP { ++ user_value ROMRAM ++}; ++ ++cdl_component CYGPKG_MEMORY_DIAGNOSIS { ++ user_value 1 ++}; ++ ++cdl_option CYGSEM_RAM_PM_DIAGNOSIS { ++ user_value 0 ++}; ++ ++#cdl_component CYGPKG_WDT_DIAGNOSIS { ++# user_value 1 ++#}; ++ ++cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { ++ inferred_value 1 ++}; ++ ++cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { ++ inferred_value 4 ++}; ++ ++cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { ++ user_value 1 "FSL 200952" ++}; +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_ata.ecm redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_ata.ecm +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_ata.ecm 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_ata.ecm 2010-01-26 17:35:49.962963878 +0000 +@@ -0,0 +1,187 @@ ++cdl_savefile_version 1; ++cdl_savefile_command cdl_savefile_version {}; ++cdl_savefile_command cdl_savefile_command {}; ++cdl_savefile_command cdl_configuration { description hardware template package }; ++cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; ++ ++cdl_configuration eCos { ++ description "" ; ++ hardware mx51_3stack ; ++ template redboot ; ++ package -hardware CYGPKG_HAL_ARM current ; ++ package -hardware CYGPKG_HAL_ARM_MX51 current ; ++ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ; ++ package -hardware CYGPKG_IMX_COMMON current ; ++ package -hardware CYGPKG_IO_SERIAL_ARM_IMX ; ++ package -hardware CYGPKG_IO_ETH_DRIVERS current ; ++ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ; ++ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ; ++ #package -hardware CYGPKG_DEVS_ETH_FEC current ; ++ package -hardware CYGPKG_COMPRESS_ZLIB current ; ++ package -hardware CYGPKG_DIAGNOSIS current ; ++ package -hardware CYGPKG_IO_FLASH current ; ++ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ; ++ package -hardware CYGPKG_DEVS_IMX_SPI current ; ++ package -hardware CYGPKG_DEVS_MXC_I2C current ; ++ package -hardware CYGPKG_DEVS_IMX_IPU current ; ++ package -hardware CYGPKG_ERROR current ; ++ package -hardware CYGPKG_IO current ; ++ package -hardware CYGPKG_IO_FILEIO current ; ++ package -template CYGPKG_HAL current ; ++ package -template CYGPKG_INFRA current ; ++ package -template CYGPKG_REDBOOT current ; ++ package -template CYGPKG_ISOINFRA current ; ++ package -template CYGPKG_LIBC_STRING current ; ++ package -template CYGPKG_CRC current ; ++ package CYGPKG_MEMALLOC current ; ++ package -hardware CYGPKG_IO_DISK current; ++ package -hardware CYGPKG_DEVS_DISK_IDE current; ++ package CYGPKG_BLOCK_LIB current ; # needed by CYGPKG_FS_FAT ++ package CYGPKG_LINUX_COMPAT current ; ++ package CYGPKG_FS_FAT current ; ++# package CYGPKG_FS_JFFS2 current ; ++}; ++ ++cdl_component CYGPKG_REDBOOT_DISK { ++ user_value 1 ++}; ++ ++cdl_option CYGPKG_IO_FILEIO_DEVFS_SUPPORT { ++ user_value 1 ++}; ++ ++cdl_option CYGCFG_FS_FAT_USE_ATTRIBUTES { ++ user_value 1 ++}; ++ ++cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { ++ inferred_value 0 ++}; ++ ++# Pin Conflict with NAND, enable only when NAND is disabled ++cdl_option CYGHWR_IMX_IDE { ++ inferred_value 1 ++} ++ ++cdl_option CYGHWR_DEVS_FLASH_MMC { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IMX_ECSPI { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IPU_3_EX { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_IMX_DISPLAY { ++ inferred_value 1 ++}; ++ ++cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { ++ inferred_value 0 ++}; ++ ++cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { ++ user_value 4096 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { ++ user_value 0 ++}; ++ ++cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { ++ user_value 50 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { ++ inferred_value 0 ++}; ++ ++cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { ++ inferred_value 1 ++}; ++ ++cdl_option CYGSEM_HAL_ROM_MONITOR { ++ inferred_value 1 ++}; ++ ++cdl_component CYGBLD_BUILD_REDBOOT { ++ user_value 1 ++}; ++ ++cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { ++ inferred_value 0x00040000 ++}; ++ ++cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { ++ inferred_value 0x90008000 ++}; ++ ++cdl_option CYGBLD_ISO_STRTOK_R_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_component CYG_HAL_STARTUP { ++ user_value ROMRAM ++}; ++ ++cdl_component CYGPKG_MEMORY_DIAGNOSIS { ++ user_value 1 ++}; ++ ++cdl_option CYGSEM_RAM_PM_DIAGNOSIS { ++ user_value 0 ++}; ++ ++#cdl_component CYGPKG_WDT_DIAGNOSIS { ++# user_value 1 ++#}; ++ ++cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { ++ inferred_value 1 ++}; ++ ++cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { ++ inferred_value 4 ++}; ++ ++cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE { ++ user_value 1 ++}; ++ ++cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { ++ user_value 1 "FSL 200952" ++}; +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_mddr.ecm redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_mddr.ecm +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_mddr.ecm 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/misc/redboot_ROMRAM_mddr.ecm 2010-01-26 17:35:49.972960878 +0000 +@@ -0,0 +1,162 @@ ++cdl_savefile_version 1; ++cdl_savefile_command cdl_savefile_version {}; ++cdl_savefile_command cdl_savefile_command {}; ++cdl_savefile_command cdl_configuration { description hardware template package }; ++cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; ++ ++cdl_configuration eCos { ++ description "" ; ++ hardware mx51_3stack ; ++ template redboot ; ++ package -hardware CYGPKG_HAL_ARM current ; ++ package -hardware CYGPKG_HAL_ARM_MX51 current ; ++ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ; ++ package -hardware CYGPKG_IMX_COMMON current ; ++ package -hardware CYGPKG_IO_SERIAL_ARM_IMX ; ++ package -hardware CYGPKG_IO_ETH_DRIVERS current ; ++ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ; ++ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ; ++ #package -hardware CYGPKG_DEVS_ETH_FEC current ; ++ package -hardware CYGPKG_COMPRESS_ZLIB current ; ++ package -hardware CYGPKG_DIAGNOSIS current ; ++ package -hardware CYGPKG_IO_FLASH current ; ++ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ; ++ package -hardware CYGPKG_DEVS_IMX_SPI current ; ++ package -hardware CYGPKG_DEVS_MXC_I2C current ; ++ package -hardware CYGPKG_DEVS_IMX_IPU current ; ++ package -template CYGPKG_HAL current ; ++ package -template CYGPKG_INFRA current ; ++ package -template CYGPKG_REDBOOT current ; ++ package -template CYGPKG_ISOINFRA current ; ++ package -template CYGPKG_LIBC_STRING current ; ++ package -template CYGPKG_CRC current ; ++ package CYGPKG_MEMALLOC current ; ++ package -hardware CYGPKG_IO_DISK current; ++}; ++ ++cdl_option CYGHWR_MX51_MDDR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MMC { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IMX_ECSPI { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IPU_3_EX { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_IMX_DISPLAY { ++ inferred_value 1 ++}; ++ ++cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { ++ inferred_value 0 ++}; ++ ++cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { ++ user_value 4096 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { ++ user_value 0 ++}; ++ ++cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { ++ user_value 50 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { ++ inferred_value 0 ++}; ++ ++cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { ++ inferred_value 1 ++}; ++ ++cdl_option CYGSEM_HAL_ROM_MONITOR { ++ inferred_value 1 ++}; ++ ++cdl_component CYGBLD_BUILD_REDBOOT { ++ user_value 1 ++}; ++ ++cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { ++ inferred_value 0x00040000 ++}; ++ ++cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { ++ inferred_value 0x90008000 ++}; ++ ++cdl_option CYGBLD_ISO_STRTOK_R_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_component CYG_HAL_STARTUP { ++ user_value ROMRAM ++}; ++ ++cdl_component CYGPKG_MEMORY_DIAGNOSIS { ++ user_value 1 ++}; ++ ++cdl_option CYGSEM_RAM_PM_DIAGNOSIS { ++ user_value 0 ++}; ++ ++#cdl_component CYGPKG_WDT_DIAGNOSIS { ++# user_value 1 ++#}; ++ ++cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { ++ inferred_value 1 ++}; ++ ++cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { ++ inferred_value 4 ++}; ++ ++cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { ++ user_value 1 "FSL 200952" ++}; +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/board_misc.c redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/board_misc.c +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/board_misc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/board_misc.c 2010-01-26 17:35:49.972960878 +0000 +@@ -0,0 +1,821 @@ ++//========================================================================== ++// ++// board_misc.c ++// ++// HAL misc board support code for the board ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================*/ ++ ++#include ++#include ++#include ++#include CYGBLD_HAL_PLATFORM_H ++ ++#include // base types ++#include // tracing macros ++#include // assertion macros ++ ++#include // IO macros ++#include // Register state info ++#include ++#include // Interrupt names ++#include ++#include // Hardware definitions ++#include // Platform specifics ++#include ++#include ++#include ++#include // diag_printf ++ ++// All the MM table layout is here: ++#include ++#include ++ ++externC void* memset(void *, int, size_t); ++extern nfc_iomuxsetup_func_t *nfc_iomux_setup; ++ ++unsigned int cpld_base_addr; ++ ++struct spi_v2_3_reg spi_nor_reg; ++struct imx_spi_dev imx_spi_nor = { ++ base : CSPI2_BASE_ADDR, ++ freq : 25000000, ++ ss_pol : IMX_SPI_ACTIVE_LOW, ++ ss : 1, ++ fifo_sz : 32, ++ us_delay: 0, ++ reg : &spi_nor_reg, ++}; ++ ++imx_spi_init_func_t *spi_nor_init; ++imx_spi_xfer_func_t *spi_nor_xfer; ++ ++void hal_mmu_init(void) ++{ ++ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000; ++ unsigned long i; ++ ++ /* ++ * Set the TTB register ++ */ ++ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); ++ ++ /* ++ * Set the Domain Access Control Register ++ */ ++ i = ARM_ACCESS_DACR_DEFAULT; ++ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); ++ ++ /* ++ * First clear all TT entries - ie Set them to Faulting ++ */ ++ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); ++ ++ /* Actual Virtual Size Attributes Function */ ++ /* Base Base MB cached? buffered? access permissions */ ++ /* xxx00000 xxx00000 */ ++ X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */ ++ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */ ++ X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */ ++ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */ ++ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */ ++ X_ARM_MMU_SECTION(0x900, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ ++ X_ARM_MMU_SECTION(0x900, 0x900, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ ++ X_ARM_MMU_SECTION(0x900, 0x980, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ ++ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ ++ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ ++ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */ ++} ++ ++void mxc_i2c_init(unsigned int module_base) ++{ ++ unsigned int reg; ++ ++ switch (module_base) { ++ case I2C_BASE_ADDR: ++ reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA ++ writel(0x11, reg); ++ reg = IOMUXC_BASE_ADDR + 0x600; ++ writel(0x1ad, reg); ++ reg = IOMUXC_BASE_ADDR + 0x9B4; ++ writel(0x1, reg); ++ ++ reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL ++ writel(0x11, reg); ++ reg = IOMUXC_BASE_ADDR + 0x614; ++ writel(0x1ad, reg); ++ reg = IOMUXC_BASE_ADDR + 0x9B0; ++ writel(0x1, reg); ++ break; ++ case I2C2_BASE_ADDR: ++ /* Workaround for Atlas Lite */ ++ writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL ++ writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA ++ reg = readl(GPIO1_BASE_ADDR + 0x0); ++ reg |= 0xC; // write a 1 on the SCL and SDA lines ++ writel(reg, GPIO1_BASE_ADDR + 0x0); ++ reg = readl(GPIO1_BASE_ADDR + 0x4); ++ reg |= 0xC; // configure GPIO lines as output ++ writel(reg, GPIO1_BASE_ADDR + 0x4); ++ reg = readl(GPIO1_BASE_ADDR + 0x0); ++ reg &= ~0x4 ; // set SCL low for a few milliseconds ++ writel(reg, GPIO1_BASE_ADDR + 0x0); ++ hal_delay_us(20000); ++ reg |= 0x4; ++ writel(reg, GPIO1_BASE_ADDR + 0x0); ++ hal_delay_us(10); ++ reg = readl(GPIO1_BASE_ADDR + 0x4); ++ reg &= ~0xC; // configure GPIO lines back as input ++ writel(reg, GPIO1_BASE_ADDR + 0x4); ++ writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL ++ writel(0x3, IOMUXC_BASE_ADDR + 0x9B8); ++ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4); ++ ++ writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA ++ writel(0x3, IOMUXC_BASE_ADDR + 0x9BC); ++ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8); ++ break; ++ default: ++ diag_printf("Invalid I2C base: 0x%x\n", module_base); ++ return; ++ } ++} ++ ++void mxc_ata_iomux_setup(void) ++{ ++ // config NANDF_WE_B pad for pata instance DIOW port ++ // config_pad_mode(NANDF_WE_B, ALT1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B); ++ ++ // config NANDF_RE_B pad for pata instance DIOR port ++ // config_pad_mode(NANDF_RE_B, ALT1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B); ++ ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE); ++ ++ // config NANDF_CLE pad for pata instance PATA_RESET_B port ++ // config_pad_mode(NANDF_CLE, ALT1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE); ++ ++ // config NANDF_WP_B pad for pata instance DMACK port ++ // config_pad_mode(NANDF_WP_B, ALT1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B); ++ ++ // config NANDF_RB0 pad for pata instance DMARQ port ++ // config_pad_mode(NANDF_RB0, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0); ++ ++ // config NANDF_RB1 pad for pata instance IORDY port ++ // config_pad_mode(NANDF_RB1, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1); ++ ++ // config NANDF_RB5 pad for pata instance INTRQ port ++ // config_pad_mode(NANDF_RB5, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND); ++ ++ // config NANDF_CS2 pad for pata instance CS_0 port ++ // config_pad_mode(NANDF_CS2, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2); ++ ++ // config NANDF_CS3 pad for pata instance CS_1 port ++ // config_pad_mode(NANDF_CS3, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3); ++ ++ // config NANDF_CS4 pad for pata instance DA_0 port ++ // config_pad_mode(NANDF_CS4, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4); ++ ++ // config NANDF_CS5 pad for pata instance DA_1 port ++ // config_pad_mode(NANDF_CS5, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5); ++ ++ // config NANDF_CS6 pad for pata instance DA_2 port ++ // config_pad_mode(NANDF_CS6, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6); ++ ++ // config NANDF_D15 pad for pata instance PATA_DATA[15] port ++ // config_pad_mode(NANDF_D15, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15); ++ ++ // config NANDF_D14 pad for pata instance PATA_DATA[14] port ++ // config_pad_mode(NANDF_D14, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14); ++ ++ // config NANDF_D13 pad for pata instance PATA_DATA[13] port ++ // config_pad_mode(NANDF_D13, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13); ++ ++ // config NANDF_D12 pad for pata instance PATA_DATA[12] port ++ // config_pad_mode(NANDF_D12, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12); ++ ++ // config NANDF_D11 pad for pata instance PATA_DATA[11] port ++ // config_pad_mode(NANDF_D11, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11); ++ ++ // config NANDF_D10 pad for pata instance PATA_DATA[10] port ++ // config_pad_mode(NANDF_D10, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10); ++ ++ // config NANDF_D9 pad for pata instance PATA_DATA[9] port ++ // config_pad_mode(NANDF_D9, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9); ++ ++ // config NANDF_D8 pad for pata instance PATA_DATA[8] port ++ // config_pad_mode(NANDF_D8, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8); ++ ++ // config NANDF_D7 pad for pata instance PATA_DATA[7] port ++ // config_pad_mode(NANDF_D7, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7); ++ ++ // config NANDF_D6 pad for pata instance PATA_DATA[6] port ++ // config_pad_mode(NANDF_D6, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6); ++ ++ // config NANDF_D5 pad for pata instance PATA_DATA[5] port ++ // config_pad_mode(NANDF_D5, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5); ++ ++ // config NANDF_D4 pad for pata instance PATA_DATA[4] port ++ // config_pad_mode(NANDF_D4, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4); ++ ++ // config NANDF_D3 pad for pata instance PATA_DATA[3] port ++ // config_pad_mode(NANDF_D3, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3); ++ ++ // config NANDF_D2 pad for pata instance PATA_DATA[2] port ++ // config_pad_mode(NANDF_D2, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2); ++ ++ // config NANDF_D1 pad for pata instance PATA_DATA[1] port ++ // config_pad_mode(NANDF_D1, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1); ++ ++ // config NANDF_D0 pad for pata instance PATA_DATA[0] port ++ // config_pad_mode(NANDF_D0, 0x1); ++ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0); ++ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0); ++} ++ ++static void mxc_fec_setup(void) ++{ ++ volatile unsigned int reg; ++ ++ /* No FEC support for TO 2.0 and higher yet */ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) ++ return; ++ /*FEC_TX_CLK*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0390); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x085C); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09D0); ++ ++ /*FEC_RX_CLK*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0388); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0854); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09C4); ++ ++ /*FEC_RX_DV*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x038c); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0858); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09C8); ++ ++ /*FEC_COL*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0384); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0850); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x9A8); ++ ++ /*FEC_RDATA0*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0394); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0860); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09B4); ++ ++ /*FEC_TDATA0*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0398); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x864); ++ ++ /*FEC_TX_EN*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0380); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x084C); ++ ++ /*FEC_MDC*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x034C); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x0818); ++ ++ /*FEC_MDIO*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0350); ++ writel(0x1CD, IOMUXC_BASE_ADDR + 0x081C); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09B0); ++ ++ /*FEC_TX_ERR*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0344); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x0810); ++ ++ /*FEC_RX_ERR*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0360); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x082C); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09CC); ++ ++ /*FEC_CRS*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0348); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0814); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09AC); ++ ++ /*FEC_RDATA1*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0354); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0820); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09B8); ++ ++ /*FEC_TDATA1*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0374); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x0840); ++ ++ /*FEC_RDATA2*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0358); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0824); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09BC); ++ ++ /*FEC_TDATA2*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0378); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x0844); ++ ++ /*FEC_RDATA3*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x035C); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0828); ++ writel(0x1, IOMUXC_BASE_ADDR + 0x09C0); ++ ++ /*FEC_TDATA3*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x037C); ++ writel(0x5, IOMUXC_BASE_ADDR + 0x0848); ++ ++ reg = readl(GPIO3_BASE_ADDR + 0x0); ++ reg &= ~0x40; // Lower reset line ++ writel(reg, GPIO3_BASE_ADDR + 0x0); ++ ++ reg = readl(GPIO3_BASE_ADDR + 0x4); ++ reg |= 0x40; // configure GPIO lines as output ++ writel(reg, GPIO3_BASE_ADDR + 0x4); ++ ++ /* Reset the ethernet controller over GPIO */ ++ writel(0x4, IOMUXC_BASE_ADDR + 0x02CC); ++ writel(0xC5, IOMUXC_BASE_ADDR + 0x078C); ++ ++ hal_delay_us(200); ++ ++ reg = readl(GPIO3_BASE_ADDR + 0x0); ++ reg |= 0x40; ++ writel(reg, GPIO3_BASE_ADDR + 0x0); ++} ++ ++static void mxc_nfc_iomux_setup(void) ++{ ++ writel(0x0, IOMUXC_BASE_ADDR + 0x108); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x10C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x110); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x114); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x118); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x11C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x120); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x124); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x128); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x12C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x130); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x134); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x138); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x13C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x140); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x144); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x148); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x14C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x150); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x154); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x158); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x15C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x160); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x164); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x168); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x16C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x170); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x174); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x178); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x17C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x180); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x184); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x188); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x18C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x190); ++} ++ ++void setup_core_voltages(void) ++{ ++ struct mxc_i2c_request rq; ++ unsigned char buf[4]; ++ ++ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) { ++ rq.dev_addr = 0x8; ++ rq.reg_addr_sz = 1; ++ rq.buffer_sz = 3; ++ rq.buffer = buf; ++ ++ /* Set core voltage to 1.1V */ ++ rq.reg_addr = 24; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0x1F)) | 0x14; ++ i2c_xfer(1, &rq, 0); ++ hal_delay_us(50); ++ /* Raise the core frequency */ ++ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); ++ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) { ++ /* Setup VCC (SW2) to 1.25 */ ++ rq.reg_addr = 25; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0x1F)) | 0x1A; ++ i2c_xfer(1, &rq, 0); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ rq.reg_addr = 26; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0x1F)) | 0x1A; ++ i2c_xfer(1, &rq, 0); ++ } else { ++ /* TO 3.0 */ ++ /* Setup VCC (SW2) to 1.225 */ ++ rq.reg_addr = 25; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0x1F)) | 0x19; ++ i2c_xfer(1, &rq, 0); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ rq.reg_addr = 26; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0x1F)) | 0x18; ++ i2c_xfer(1, &rq, 0); ++ } ++ ++ rq.reg_addr = 7; ++ i2c_xfer(1, &rq, 1); ++ ++ if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) { ++ /* Set switchers in PWM mode for Atlas 2.0 and lower */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ rq.reg_addr = 28; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0xF)) | 0x5; ++ buf[1] = (buf[1] & (~0x3C)) | 0x14; ++ i2c_xfer(1, &rq, 0); ++ ++ /* Setup the switcher mode for SW3 & SW4*/ ++ rq.reg_addr = 29; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0xF)) | 0x5; ++ buf[1] = (buf[1] & (~0xF)) | 0x5; ++ i2c_xfer(1, &rq, 0); ++ } else { ++ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ rq.reg_addr = 28; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0xF)) | 0x8; ++ buf[1] = (buf[1] & (~0x3C)) | 0x20; ++ i2c_xfer(1, &rq, 0); ++ ++ /* Setup the switcher mode for SW3 & SW4*/ ++ rq.reg_addr = 29; ++ i2c_xfer(1, &rq, 1); ++ buf[2] = (buf[2] & (~0xF)) | 0x8; ++ buf[1] = (buf[1] & (~0xF)) | 0x8; ++ i2c_xfer(1, &rq, 0); ++ } ++ } ++} ++ ++// ++// Platform specific initialization ++// ++ ++void plf_hardware_init(void) ++{ ++ unsigned long sw_rest_reg, weim_base; ++ unsigned int reg; ++ ++ setup_core_voltages(); ++ // CS5 setup ++ writel(0, IOMUXC_BASE_ADDR + 0xF4); ++ weim_base = WEIM_BASE_ADDR + 0x78; ++ writel(0x00410089, weim_base + CSGCR1); ++ writel(0x00000002, weim_base + CSGCR2); ++ // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 ++ writel(0x32260000, weim_base + CSRCR1); ++ // APR=0 ++ writel(0x00000000, weim_base + CSRCR2); ++ // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0 ++ writel(0x72080F00, weim_base + CSWCR1); ++ cpld_base_addr = CS5_BASE_ADDR; ++ ++ /* Reset interrupt status reg */ ++ writew(0x1F, cpld_base_addr + PBC_INT_REST); ++ writew(0x00, cpld_base_addr + PBC_INT_REST); ++ writew(0xFFFF, cpld_base_addr + PBC_INT_MASK); ++ ++ /* Reset the XUART and Ethernet controllers */ ++ sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET); ++ sw_rest_reg |= 0x9; ++ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET); ++ sw_rest_reg &= ~0x9; ++ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET); ++ ++ // UART1 ++ //RXD ++ writel(0x0, IOMUXC_BASE_ADDR + 0x228); ++ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618); ++ //TXD ++ writel(0x0, IOMUXC_BASE_ADDR + 0x22c); ++ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c); ++ //RTS ++ writel(0x0, IOMUXC_BASE_ADDR + 0x230); ++ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620); ++ //CTS ++ writel(0x0, IOMUXC_BASE_ADDR + 0x234); ++ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624); ++ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2 ++ writel(0x00000004, 0x73fa83E8); ++ writel(0x00000004, 0x73fa83Ec); ++ ++ // enable ARM clock div by 8 ++ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR); ++#ifdef MXCFLASH_SELECT_NAND ++ nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup; ++#endif ++ mxc_fec_setup(); ++ ++ spi_nor_init = (imx_spi_init_func_t *)imx_ecspi_init; ++ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_ecspi_xfer; ++} ++ ++ ++void mxc_ipu_iomux_config(void) ++{ ++ // configure display data0~17 for Epson panel ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2,0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10, 0x5); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16, 0x5); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17, 0x5); ++ ++ // DI1_PIN2 and DI1_PIN3, configured to be HSYNC and VSYNC of Epson LCD ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ ++ // PCLK - DISP_CLK ++ // No IOMUX configuration required, as there is no IOMUXing for this pin ++ ++ // DRDY - PIN15 ++ // No IOMUX configuration required, as there is no IOMUXing for this pin ++ ++ // configure this pin to be the SER_DISP_CS ++ ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT4); ++ CONFIG_PIN(IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS,0x85); ++ ++ // configure to be DISPB1_SER_RS ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP1, 0x85); ++ // configure to be SER_DISP1_CLK ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP2, 0x85); ++ // configure to be DISPB1_SER_DIO ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP3, 0xC5); ++ // configure to be DISPB1_SER_DIN ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP4, 0xC4); ++ //CS0 ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS, 0x85); ++ // WR ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11, 0x85); ++ // RD ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12, 0x85); ++ // RS ++ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1); ++ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13, 0x85); ++ ++} ++ ++void mxc_mmc_init(unsigned int base_address) ++{ ++ switch(base_address) { ++ case MMC_SDHC1_BASE_ADDR: ++ /* SD1 CMD, SION bit */ ++ writel(0x10, IOMUXC_BASE_ADDR + 0x394); ++ /* Configure SW PAD */ ++ /* SD1 CMD */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x79C); ++ /* SD1 CLK */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0); ++ /* SD1 DAT0 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4); ++ /* SD1 DAT1 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8); ++ /* SD1 DAT2 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC); ++ /* SD1 DAT3 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void increase_core_voltage(bool i) ++{ ++ unsigned char buf[4]; ++ struct mxc_i2c_request rq; ++ ++ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) { ++ rq.dev_addr = 0x8; ++ rq.reg_addr = 24; ++ rq.reg_addr_sz = 1; ++ rq.buffer_sz = 3; ++ rq.buffer = buf; ++ ++ i2c_xfer(1, &rq, 1); ++ ++ if (i) { ++ //buf[2] = (buf[2] & (~0x1F)) | 0x17; //1.175 ++ buf[2] = (buf[2] & (~0x1F)) | 0x18; //1.2 ++ } else { ++ buf[2] = (buf[2] & (~0x1F)) | 0x14; ++ } ++ i2c_xfer(1, &rq, 0); ++ ++ ++ rq.reg_addr = 26; ++ i2c_xfer(1, &rq, 1); ++ if (i) { ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ buf[2] = (buf[2] & (~0x1F)) | 0x1A; ++ } else { ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ buf[2] = (buf[2] & (~0x1F)) | 0x18; ++ } ++ i2c_xfer(1, &rq, 0); ++ } else { ++ diag_printf("Cannot increase core voltage, failed to initialize I2C2\n"); ++ } ++} ++ ++void io_cfg_spi(struct imx_spi_dev *dev) ++{ ++ unsigned int reg; ++ ++ switch (dev->base) { ++ case CSPI1_BASE_ADDR: ++ break; ++ case CSPI2_BASE_ADDR: ++ // Select mux mode: ALT2 mux port: MOSI of instance: ecspi2 ++ writel(0x2, IOMUXC_BASE_ADDR + 0x154); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x53C); ++ ++ // Select mux mode: ALT2 mux port: MISO of instance: ecspi2. ++ writel(0x2, IOMUXC_BASE_ADDR + 0x128); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x504); ++ ++ // de-select SS0 of instance: ecspi1. ++ writel(0x2, IOMUXC_BASE_ADDR + 0x298); ++ writel(0x85, IOMUXC_BASE_ADDR + 0x698); ++ // Select mux mode: ALT2 mux port: SS1 of instance: ecspi2. ++ writel(0x2, IOMUXC_BASE_ADDR + 0x160); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x548); ++ ++ // Select mux mode: ALT3 mux port: GPIO mode ++ writel(0x3, IOMUXC_BASE_ADDR + 0x150); ++ writel(0xE0, IOMUXC_BASE_ADDR + 0x538); ++ reg = readl(GPIO3_BASE_ADDR + 0x0); ++ reg |= 0x1000000; // write a 1 ++ writel(reg, GPIO3_BASE_ADDR + 0x0); ++ reg = readl(GPIO3_BASE_ADDR + 0x4); ++ reg |= 0x1000000; // configure GPIO lines as output ++ writel(reg, GPIO3_BASE_ADDR + 0x4); ++ ++ // Select mux mode: ALT2 mux port: SCLK of instance: ecspi2. ++ writel(0x2, IOMUXC_BASE_ADDR + 0x124); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x500); ++ break; ++ default: ++ break; ++ } ++} ++ ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++typedef void code_fun(void); ++ ++void board_program_new_stack(void *func) ++{ ++ register CYG_ADDRESS stack_ptr asm("sp"); ++ register CYG_ADDRESS old_stack asm("r4"); ++ register code_fun *new_func asm("r0"); ++ old_stack = stack_ptr; ++ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS); ++ new_func = (code_fun*)func; ++ new_func(); ++ stack_ptr = old_stack; ++} ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/epson_lcd.c redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/epson_lcd.c +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/epson_lcd.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/epson_lcd.c 2010-01-26 17:35:49.982961503 +0000 +@@ -0,0 +1,223 @@ ++//========================================================================== ++// ++// epson_lcd.c ++// ++// LCD Display Implementation ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++ ++#define MX51_ATLAS_PMIC_ADDRESS 0x8 ++ ++static int pmic_read_reg(unsigned int reg_addr, unsigned char *data, unsigned int count) ++{ ++ struct mxc_i2c_request rq; ++ ++ rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS; // dev_addr of Atlas PMIC ++ rq.reg_addr = reg_addr; // addr of LEC Control0 Reg ++ rq.reg_addr_sz = 1; ++ rq.buffer_sz = count; // send 3 data in a series ++ rq.buffer = data; ++ i2c_xfer(1, &rq, 1); ++ ++ return 1; ++} ++ ++static int pmic_write_reg(unsigned int reg_addr, unsigned char *data, unsigned int count) ++{ ++ struct mxc_i2c_request rq; ++ ++ rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS; // dev_addr of Atlas PMIC ++ rq.reg_addr = reg_addr; // addr of LEC Control0 Reg ++ rq.reg_addr_sz = 1; ++ rq.buffer_sz = count; // send 3 data in a series ++ rq.buffer = data; ++ i2c_xfer(1, &rq, 0); ++ ++ return 1; ++} ++ ++/*this function use common pins of IPU to simulate a cspi interface*/ ++static void epson_lcd_spi_simulate(void) ++{ ++ dc_microcode_t microcode = { 0 }; ++ microcode.addr = 0x24; ++ microcode.stop = 1; ++ microcode.opcode = "WROD"; ++ microcode.lf = 0; ++ microcode.af = 0; ++ microcode.operand = 0; ++ microcode.mapping = 5; ++ microcode.waveform = 7; ++ microcode.gluelogic = 0; ++ microcode.sync = 0; ++ ipu_dc_microcode_config(microcode); ++ ++ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1, 0x24); //address of second region ++ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0, 0x24); //address of first region ++ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8, 1); //MEDIUM PRIORITY FOR DATA ++ ++ /* Data Mapping of 24-bit new data ++ |23..16|15..8|7..0| ==>> bit[15..0]&(0x1FF), just keep the last 17bit for LCD configuration */ ++ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4, 3); ++ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4, 4); ++ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4, 5); ++ ipu_write_field(IPU_DC_MAP_CONF_16__MD_OFFSET_3, 0); ++ ipu_write_field(IPU_DC_MAP_CONF_16__MD_MASK_3, 0x00); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_4, 15); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_4, 0x01); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_5, 7); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_5, 0xFF); ++ ++ /*set clock and cs signal for command. ++ sclk should be more than 90ns interval, derived from base clock. */ ++ ipu_di_waveform_config(0, 6, 0, 0, 11); ++ ipu_di_waveform_config(0, 6, 1, 1, 2); ++ ipu_di_waveform_config(0, 6, 2, 0, 0); ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6, 3); //base clock, 133MHz/div ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6, 0); //start immediatly ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_CST_6, 0); //pointer for CS ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6, 8); //8+1 bit, should be more than or equal with 9 ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6, 2); //RS=0 ++ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6, 1); //SCLK for command, should be less than 11MHz ++ ipu_write_field(IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY, 1); ++ ipu_write_field(IPU_IPU_DISP_GEN__MCU_DI_ID_8, 0); //MCU accesses DC's channel #8 via DI0. ++ ++ /* T VALUE, seperate into two parts */ ++ ipu_write_field(IPU_IPU_DISP_GEN__MCU_T, T_VALUE); //diffrenciate ++ ++ ipu_write_field(IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8, 1); //display 1 ++ ipu_write_field(IPU_DC_WR_CH_CONF1_8__W_SIZE_8, 3); //32 bits are used (RGB) ++ ++ ipu_write_field(IPU_DC_DISP_CONF1_1__DISP_TYP_1, 0); //serial display ++ ++ ipu_write_field(IPU_IPU_CONF__DI0_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DP_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DC_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 1); ++} ++ ++static void epson_lcd_rst(void) ++{ ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 1); ++ hal_delay_us(1000); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 0); ++} ++ ++void lcd_backlit_on(void) ++{ ++ struct mxc_i2c_request rq; ++ unsigned char data[3]; ++ unsigned char dataCheck[3]; ++ int timeout = 0; ++ int ret = 0xFF; ++ /*duty cycle = (mainDispDutyCycle % 32) / 32; */ ++ unsigned char mainDispDutyCycle = 0x20; ++ /*current = mainDispCurrentSet * 3 * 2^mainDispHiCurMode ++ current should be no more than 15 */ ++ unsigned char mainDispCurrentSet = 3; ++ unsigned char mainDispHiCurMode = 0; ++ ++#ifndef CYGPKG_REDBOOT ++ mxc_i2c2_clock_gate(1); ++#endif ++ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) { ++ while (timeout < 5) { ++ data[0] = 0x0; ++ data[1] = ((mainDispCurrentSet << 1) & 0xE) | ((mainDispDutyCycle >> 5) & 0x1); ++ data[2] = ((mainDispHiCurMode << 1) & 0x2) | ((mainDispDutyCycle << 3) & 0xF8); ++ pmic_write_reg(0x33, data, 3); ++ dataCheck[0] = 0x0; ++ dataCheck[1] = 0x0; ++ dataCheck[2] = 0x0; ++ pmic_read_reg(0x33, dataCheck, 3); ++ ++ if ((dataCheck[0] == data[0]) && (dataCheck[1] == data[1]) && (dataCheck[2] == data[2])) { ++ break; ++ } ++ timeout++; ++ hal_delay_us(20); ++ } ++ } else { ++ diag_printf("ERROR:I2C initialization failed\n"); ++ } ++#ifndef CYGPKG_REDBOOT ++ mxc_i2c2_clock_gate(0); ++#endif ++} ++ ++void lcd_config(void) ++{ ++ /* set these regs to conpensate color. */ ++ writel((readl(MIPI_HSC_BASE_ADDR + 0x800) | (1<<16)), MIPI_HSC_BASE_ADDR + 0x800); ++ writel((readl(MIPI_HSC_BASE_ADDR + 0x0) | (1<<10)), MIPI_HSC_BASE_ADDR + 0x0); ++ ++ /* simulate spi interface to access LCD regs */ ++ epson_lcd_spi_simulate(); ++ epson_lcd_rst(); ++ ++ /* enable chip select */ ++ gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT); ++ gpio_write_data(GPIO_PORT3, 4, 0); ++ hal_delay_us(300); ++ ++ writel(MADCTL, IPU_CTRL_BASE_ADDR); ++ writel(0x0100, IPU_CTRL_BASE_ADDR); ++ ++ writel(GAMSET, IPU_CTRL_BASE_ADDR); ++ writel(0x0101, IPU_CTRL_BASE_ADDR); ++ ++ writel(COLMOD, IPU_CTRL_BASE_ADDR); ++ writel(0x0160, IPU_CTRL_BASE_ADDR); ++ ++ writel(SLPOUT, IPU_CTRL_BASE_ADDR); // SLEEP OUT ++ hal_delay_us(300); ++ ++ writel(DISON, IPU_CTRL_BASE_ADDR); // Display ON ++ hal_delay_us(300); ++ ++ /* disable chip select */ ++ gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT); ++ gpio_write_data(GPIO_PORT3, 4, 1); ++ ++ ipu_write_field(IPU_IPU_CONF__DI0_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DP_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DC_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 0); ++ hal_delay_us(300); ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/mx51_fastlogo.c redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/mx51_fastlogo.c +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/mx51_fastlogo.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/mx51_fastlogo.c 2010-01-26 17:35:49.982961503 +0000 +@@ -0,0 +1,295 @@ ++//========================================================================== ++// ++// mx51_fastlogo.c ++// ++// MX51 Fast Logo Implementation ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++ ++// DI counter definitions ++#define DI_COUNTER_BASECLK 0 ++#define DI_COUNTER_IHSYNC 1 ++#define DI_COUNTER_OHSYNC 2 ++#define DI_COUNTER_OVSYNC 3 ++#define DI_COUNTER_ALINE 4 ++#define DI_COUNTER_ACLOCK 5 ++ ++extern display_buffer_info_t display_buffer; ++ ++void fastlogo_dma(void) ++{ ++ ipu_channel_parameter_t ipu_channel_params; ++ ipu_idmac_channel_enable(DISPLAY_CHANNEL, 0); ++ ++ ipu_idmac_params_init(&ipu_channel_params); ++ ipu_channel_params.channel = DISPLAY_CHANNEL; ++ ipu_channel_params.eba0 = (unsigned int)(display_buffer.startAddr) / 8; ++ ipu_channel_params.fw = display_buffer.width - 1; //frame width ++ ipu_channel_params.fh = display_buffer.height - 1; //frame height ++ ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1; ++ ipu_channel_params.npb = 31; //16 pixels per burst ++ ipu_channel_params.pfs = 7; //1->4:2:2 non-interleaved, 7->rgb ++ ++ switch(display_buffer.bpp) { ++ case 32: ++ ipu_channel_params.bpp = 0; ++ break; ++ case 24: ++ ipu_channel_params.bpp = 1; ++ break; ++ case 18: ++ ipu_channel_params.bpp = 2; ++ break; ++ case 16: ++ ipu_channel_params.bpp = 3; ++ break; ++ default: ++ diag_printf("data bpp format not supported!\n"); ++ } ++ ++ switch(display_buffer.dataFormat) { ++ case RGB565: ++ ipu_channel_params.wid0 = 5 - 1; //bits ++ ipu_channel_params.wid1 = 6 - 1; //bits; ++ ipu_channel_params.wid2 = 5 - 1; //bits; ++ ipu_channel_params.wid3 = 0; //bits; ++ ipu_channel_params.ofs0 = 0; ++ ipu_channel_params.ofs1 = 5; ++ ipu_channel_params.ofs2 = 11; ++ ipu_channel_params.ofs3 = 16; ++ break; ++ ++ case RGB666: ++ ipu_channel_params.wid0 = 6 - 1; //bits ++ ipu_channel_params.wid1 = 6 - 1; //bits; ++ ipu_channel_params.wid2 = 6 - 1; //bits; ++ ipu_channel_params.wid3 = 0; //bits; ++ ipu_channel_params.ofs0 = 0; ++ ipu_channel_params.ofs1 = 6; ++ ipu_channel_params.ofs2 = 12; ++ ipu_channel_params.ofs3 = 18; ++ break; ++ case RGB888: ++ ipu_channel_params.wid0 = 8 - 1; //bits ++ ipu_channel_params.wid1 = 8 - 1; //bits; ++ ipu_channel_params.wid2 = 8 - 1; //bits; ++ ipu_channel_params.wid3 = 0; //bits; ++ ipu_channel_params.ofs0 = 0; ++ ipu_channel_params.ofs1 = 8; ++ ipu_channel_params.ofs2 = 16; ++ ipu_channel_params.ofs3 = 24; ++ break; ++ case RGBA8888: ++ ipu_channel_params.wid0 = 8 - 1; //bits ++ ipu_channel_params.wid1 = 8 - 1; //bits; ++ ipu_channel_params.wid2 = 8 - 1; //bits; ++ ipu_channel_params.wid3 = 8 - 1; //bits; ++ ipu_channel_params.ofs0 = 0; ++ ipu_channel_params.ofs1 = 8; ++ ipu_channel_params.ofs2 = 16; ++ ipu_channel_params.ofs3 = 24; ++ break; ++ default: ++ diag_printf("data format not supported!\n"); ++ } ++ ipu_channel_params.bm = 0; ++ ipu_channel_params.hf = 0; ++ ipu_channel_params.vf = 1; ++ ipu_channel_params.id = 0; ++ ipu_idmac_interleaved_channel_config(ipu_channel_params); ++ ++ ipu_idmac_channel_mode_sel(DISPLAY_CHANNEL, 0); ++ ipu_idmac_channel_enable(DISPLAY_CHANNEL, 1); ++} ++ ++void fastlogo_dmfc(void) ++{ ++ ipu_dmfc_fifo_allocate(DISPLAY_CHANNEL, 1, 0, 4); ++} ++ ++void fastlogo_dc(void) ++{ ++ //***************************************************/ ++ //DI CONFIGURATION ++ //****************************************************/ ++ //MICROCODE ++ dc_microcode_t microcode; ++ microcode.addr = 4; ++ microcode.stop = 1; ++ microcode.opcode = "WROD"; ++ microcode.lf = 0; ++ microcode.af = 0; ++ microcode.operand = 0; ++ microcode.mapping = 2; ++ microcode.waveform = 1; ++ microcode.gluelogic = 0; ++ microcode.sync = 5; ++ ipu_dc_microcode_config(microcode); ++ ++ ipu_dc_microcode_event(1, "NEW_DATA", 1, 4); ++ ++ //WRITE_CHAN ++ ipu_dc_write_channel_config(DISPLAY_CHANNEL, 2, 0, 0); ++ ++ //DISP_CONF ++ ipu_dc_display_config(2, 2 /*paralell */ , 0, display_buffer.width); ++ ++ //DC_MAP ++ ipu_dc_map(1, RGB666); ++} ++ ++void fastlogo_di(void) ++{ ++ di_sync_wave_gen_t syncWaveformGen = { 0 }; ++ int clkUp, clkDown; ++ int hSyncStartWidth = 80; ++ int hSyncWidth = 20; ++ int hSyncEndWidth = 41; ++ int delayH2V = 480; ++ int hDisp = 480; ++ int vSyncStartWidth = 20; ++ int vSyncWidth = 10; ++ int vSyncEndWidth = 5;; ++ int vDisp = 640; ++ int ipuClk = 133000000; // ipu clk is 133M ++ int typPixClk = 24000000; // typical value of pixel clock ++ int div = (int)((float)ipuClk / (float)typPixClk + 0.5); // get the nearest value of typical pixel clock ++ int pixClk = 133000000 / div; ++ ++ //DI0_SCR, set the screen height ++ ipu_di_screen_set(0, vDisp + vSyncStartWidth + vSyncEndWidth - 1); ++ ++ /* set DI_PIN15 to be waveform according to DI data wave set 3 */ ++ ipu_di_pointer_config(0, 0, div - 1, div - 1, 0, 0, 0, 0, 0, 2, 0, 0); ++ ++ /*set the up & down of data wave set 3. */ ++ ipu_di_waveform_config(0, 0, 2, 0, div * 2); // one bit for fraction part ++ ++ /* set clk for DI0, generate the base clock of DI0. */ ++ clkUp = div - 2; ++ clkDown = clkUp * 2; ++ ipu_di_bsclk_gen(0, div << 4, clkUp, clkDown); ++ ++ /* ++ DI0 configuration: ++ hsync - DI0 pin 3 ++ vsync - DI0 pin 2 ++ data_en - DI0 pin 15 ++ clk - DI0 disp clk ++ COUNTER 2 for VSYNC ++ COUNTER 3 for HSYNC ++ */ ++ /*internal HSYNC */ ++ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1; ++ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1; ++ syncWaveformGen.offsetValue = 0; ++ syncWaveformGen.offsetResolution = 0; ++ syncWaveformGen.cntAutoReload = 1; ++ syncWaveformGen.stepRepeat = 0; ++ syncWaveformGen.cntClrSel = 0; ++ syncWaveformGen.cntPolarityGenEn = 0; ++ syncWaveformGen.cntPolarityTrigSel = 0; ++ syncWaveformGen.cntPolarityClrSel = 0; ++ syncWaveformGen.cntUp = 0; ++ syncWaveformGen.cntDown = 1; ++ ipu_di_sync_config(0, DI_COUNTER_IHSYNC, syncWaveformGen); ++ ++ /*OUTPUT HSYNC */ ++ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1; ++ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1; ++ syncWaveformGen.offsetValue = delayH2V; ++ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1; ++ syncWaveformGen.cntAutoReload = 1; ++ syncWaveformGen.stepRepeat = 0; ++ syncWaveformGen.cntClrSel = 0; ++ syncWaveformGen.cntPolarityGenEn = 0; ++ syncWaveformGen.cntPolarityTrigSel = 0; ++ syncWaveformGen.cntPolarityClrSel = 0; ++ syncWaveformGen.cntUp = 0; ++ syncWaveformGen.cntDown = div * hSyncWidth; ++ ipu_di_sync_config(0, DI_COUNTER_OHSYNC, syncWaveformGen); ++ ++ /*Output Vsync */ ++ syncWaveformGen.runValue = vDisp + vSyncStartWidth + vSyncEndWidth - 1; ++ syncWaveformGen.runResolution = DI_COUNTER_IHSYNC + 1; ++ syncWaveformGen.offsetValue = 0; ++ syncWaveformGen.offsetResolution = 0; ++ syncWaveformGen.cntAutoReload = 1; ++ syncWaveformGen.stepRepeat = 0; ++ syncWaveformGen.cntClrSel = 0; ++ syncWaveformGen.cntPolarityGenEn = 1; ++ syncWaveformGen.cntPolarityTrigSel = 2; ++ syncWaveformGen.cntPolarityClrSel = 0; ++ syncWaveformGen.cntUp = 0; ++ syncWaveformGen.cntDown = vSyncWidth; ++ ipu_di_sync_config(0, DI_COUNTER_OVSYNC, syncWaveformGen); ++ ++ /*Active Lines start points */ ++ syncWaveformGen.runValue = 0; ++ syncWaveformGen.runResolution = DI_COUNTER_OHSYNC + 1; ++ syncWaveformGen.offsetValue = vSyncWidth; ++ syncWaveformGen.offsetResolution = DI_COUNTER_OHSYNC + 1; ++ syncWaveformGen.cntAutoReload = 0; ++ syncWaveformGen.stepRepeat = vDisp; ++ syncWaveformGen.cntClrSel = DI_COUNTER_OVSYNC + 1; ++ syncWaveformGen.cntPolarityGenEn = 0; ++ syncWaveformGen.cntPolarityTrigSel = 0; ++ syncWaveformGen.cntPolarityClrSel = 0; ++ syncWaveformGen.cntUp = 0; ++ syncWaveformGen.cntDown = 0; ++ ipu_di_sync_config(0, DI_COUNTER_ALINE, syncWaveformGen); ++ ++ /*Active clock start points */ ++ syncWaveformGen.runValue = 0; ++ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1; ++ syncWaveformGen.offsetValue = hSyncWidth; ++ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1; ++ syncWaveformGen.cntAutoReload = 0; ++ syncWaveformGen.stepRepeat = hDisp; ++ syncWaveformGen.cntClrSel = DI_COUNTER_ALINE + 1; ++ syncWaveformGen.cntPolarityGenEn = 0; ++ syncWaveformGen.cntPolarityTrigSel = 0; ++ syncWaveformGen.cntPolarityClrSel = 0; ++ syncWaveformGen.cntUp = 0; ++ syncWaveformGen.cntDown = 0; ++ ipu_di_sync_config(0, DI_COUNTER_ACLOCK, syncWaveformGen); ++ ++ ipu_di_general_set(0, 1, 2, 1, 0); ++ ++} ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/redboot_cmds.c redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/redboot_cmds.c +--- redboot-imx-200952~/packages/hal/arm/mx51/3stack/current/src/redboot_cmds.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/3stack/current/src/redboot_cmds.c 2010-01-26 17:35:49.982961503 +0000 +@@ -0,0 +1,189 @@ ++//========================================================================== ++// ++// redboot_cmds.c ++// ++// Board [platform] specific RedBoot commands ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++#include ++#include ++#include ++#include ++#include // Platform specific hardware definitions ++ ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++#include ++ ++#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE) ++#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE ++#endif ++ ++RedBoot_config_option("Board specifics", ++ brd_specs, ++ ALWAYS_ENABLED, ++ true, ++ CONFIG_INT, ++ 0 ++ ); ++#endif //CYGSEM_REDBOOT_FLASH_CONFIG ++ ++char HAL_PLATFORM_EXTRA[40] = "PASS x.x [x32 DDR]"; ++ ++#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM) ++ ++RedBoot_cmd("romupdate", ++ "Update Redboot with currently running image", ++ "", ++ romupdate ++ ); ++ ++extern int flash_program(void *_addr, void *_data, int len, void **err_addr); ++extern int flash_erase(void *addr, int len, void **err_addr); ++extern char *flash_errmsg(int err); ++extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value ++ ++#ifdef CYGPKG_IO_FLASH ++void romupdate(int argc, char *argv[]) ++{ ++ void *err_addr, *base_addr; ++ int stat; ++ unsigned int nfc_config3_reg, temp; ++ ++ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) { ++ diag_printf("Updating ROM in MMC/SD flash\n"); ++ /* eMMC 4.3 and eSD 2.1 supported only on TO 2.0 and higher */ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) { ++ if(!emmc_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) { ++ /* eMMC 4.3 */ ++ diag_printf("Card supports MMC-4.3, programming for boot operation.\n"); ++ return; ++ } else if(!esd_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) { ++ /* eSD 2.1 */ ++ diag_printf("Card supports SD-2.1, programming for boot operation.\n"); ++ return; ++ } ++ } ++ base_addr = (void*)0; ++ /* Read the first 1K from the card */ ++ mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr); ++ diag_printf("Programming Redboot to MMC/SD flash\n"); ++ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr); ++ ++ return; ++ } else if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) { ++ diag_printf("Updating ROM in NAND flash\n"); ++ base_addr = (void*)0; ++ nfc_config3_reg = readl(NFC_FLASH_CONFIG3_REG); ++ temp = nfc_config3_reg & (~ 0x7003); ++ writel(temp, NFC_FLASH_CONFIG3_REG); ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()) { ++ diag_printf("Updating ROM in SPI-NOR flash\n"); ++ base_addr = (void*)0; ++ } else { ++ diag_printf("romupdate not supported\n"); ++ diag_printf("Use \"factive [NAND|MMC|SPI]\" to select either NAND, MMC or SPI flash\n"); ++ } ++ ++ // Erase area to be programmed ++ if ((stat = flash_erase((void *)base_addr, ++ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, ++ (void **)&err_addr)) != 0) { ++ diag_printf("Can't erase region at %p: %s\n", ++ err_addr, flash_errmsg(stat)); ++ return; ++ } ++ // Now program it ++ if ((stat = flash_program((void *)base_addr, (void *)ram_end, ++ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, ++ (void **)&err_addr)) != 0) { ++ diag_printf("Can't program region at %p: %s\n", ++ err_addr, flash_errmsg(stat)); ++ } ++ if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) ++ writel(nfc_config3_reg, NFC_FLASH_CONFIG3_REG); ++} ++RedBoot_cmd("factive", ++ "Enable one flash media for Redboot", ++ "[NAND | MMC | SPI]", ++ factive ++ ); ++ ++typedef void reset_func_t(void); ++ ++extern reset_func_t reset_vector; ++ ++void factive(int argc, char *argv[]) ++{ ++ unsigned int *fis_addr = IRAM_BASE_ADDR; ++ ++ if (argc != 2) { ++ diag_printf("Invalid factive cmd\n"); ++ return; ++ } ++ ++ if (strcasecmp(argv[1], "NOR") == 0) { ++ diag_printf("Not supported\n"); ++ return; ++ } else if (strcasecmp(argv[1], "NAND") == 0) { ++#ifndef MXCFLASH_SELECT_NAND ++ diag_printf("Not supported\n"); ++ return; ++#endif ++ *fis_addr = FROM_NAND_FLASH; ++ } else if (strcasecmp(argv[1], "MMC") == 0) { ++#ifndef MXCFLASH_SELECT_MMC ++ diag_printf("Not supported\n"); ++ return; ++#else ++ *fis_addr = FROM_MMC_FLASH; ++#endif ++ } else if (strcasecmp(argv[1], "SPI") == 0) { ++#ifndef IMXFLASH_SELECT_SPI_NOR ++ diag_printf("Not supported\n"); ++ return; ++#else ++ *fis_addr = FROM_SPI_NOR_FLASH; ++#endif ++ } else { ++ diag_printf("Invalid command: %s\n", argv[1]); ++ return; ++ } ++ ++ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr); ++ launchRunImg(reset_vector); ++} ++#endif //CYGPKG_IO_FLASH ++#endif /* CYG_HAL_STARTUP_ROMRAM */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl redboot-imx-200952/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,350 @@ ++# ==================================================================== ++# ++# hal_arm_board.cdl ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++ ++cdl_package CYGPKG_HAL_ARM_MX51_BABBAGE { ++ display "Freescale board" ++ parent CYGPKG_HAL_ARM_MX51 ++ hardware ++ include_dir cyg/hal ++ define_header hal_arm_board.h ++ description " ++ This HAL platform package provides generic ++ support for the Freescale MX51 Babbage Board." ++ ++ compile board_misc.c ++ implements CYGINT_HAL_DEBUG_GDB_STUBS ++ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK ++ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT ++ ++ implements CYGHWR_IMX_UART1 ++ #implements CYGHWR_IMX_UART2 ++ #implements CYGHWR_IMX_UART3 ++ ++ define_proc { ++ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " ++ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " ++ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " ++ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\"" ++ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 Babbage\"" ++ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2125" ++ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack" ++ } ++ ++ cdl_component CYG_HAL_STARTUP { ++ display "Startup type" ++ flavor data ++ default_value {"ROM"} ++ legal_values {"RAM" "ROM" "ROMRAM"} ++ no_define ++ define -file system.h CYG_HAL_STARTUP ++ description " ++ When targetting the eval board it is possible to build ++ the system for either RAM bootstrap or ROM bootstrap(s). Select ++ 'ram' when building programs to load into RAM using eCos GDB ++ stubs. Select 'rom' when building a stand-alone application ++ which will be put into ROM, or for the special case of ++ building the eCos GDB stubs themselves. Using ROMRAM will allow ++ the program to exist in ROM, but be copied to RAM during startup." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { ++ display "Diagnostic serial port baud rate" ++ flavor data ++ legal_values 9600 19200 38400 57600 115200 ++ default_value 115200 ++ description " ++ This option selects the baud rate used for the console port. ++ Note: this should match the value chosen for the GDB port if the ++ console and GDB port are the same." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { ++ display "GDB serial port baud rate" ++ flavor data ++ legal_values 9600 19200 38400 57600 115200 ++ default_value 115200 ++ description " ++ This option selects the baud rate used for the GDB port. ++ Note: this should match the value chosen for the console port if the ++ console and GDB port are the same." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { ++ display "Number of communication channels on the board" ++ flavor data ++ calculated 6 ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { ++ display "Debug serial port" ++ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ default_value 0 ++ description " ++ The board has three serial ports. This option ++ chooses which port will be used to connect to a host ++ running GDB." ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { ++ display "Default console channel." ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ calculated 0 ++ } ++ ++ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { ++ display "Console serial port" ++ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE ++ flavor data ++ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 ++ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT ++ description " ++ The board has only three serial ports. This option ++ chooses which port will be used for console output." ++ } ++ ++ cdl_component CYGBLD_GLOBAL_OPTIONS { ++ display "Global build options" ++ flavor none ++ no_define ++ description " ++ Global build options including control over ++ compiler flags, linker flags and choice of toolchain." ++ ++ ++ parent CYGPKG_NONE ++ ++ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { ++ display "Global command prefix" ++ flavor data ++ no_define ++ default_value { "arm-none-eabi" } ++ description " ++ This option specifies the command prefix used when ++ invoking the build tools." ++ } ++ ++ cdl_option CYGBLD_GLOBAL_CFLAGS { ++ display "Global compiler flags" ++ flavor data ++ no_define ++ default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } ++ description " ++ This option controls the global compiler flags which are used to ++ compile all packages by default. Individual packages may define ++ options which override these global flags." ++ } ++ ++ cdl_option CYGBLD_GLOBAL_LDFLAGS { ++ display "Global linker flags" ++ flavor data ++ no_define ++ default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } ++ description " ++ This option controls the global linker flags. Individual ++ packages may define options which override these global flags." ++ } ++ ++ cdl_option CYGBLD_BUILD_GDB_STUBS { ++ display "Build GDB stub ROM image" ++ default_value 0 ++ requires { CYG_HAL_STARTUP == "ROM" } ++ requires CYGSEM_HAL_ROM_MONITOR ++ requires CYGBLD_BUILD_COMMON_GDB_STUBS ++ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT ++ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT ++ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ++ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM ++ no_define ++ description " ++ This option enables the building of the GDB stubs for the ++ board. The common HAL controls takes care of most of the ++ build process, but the final conversion from ELF image to ++ binary data is handled by the platform CDL, allowing ++ relocation of the data if necessary." ++ ++ make -priority 320 { ++ /bin/gdb_module.bin : /bin/gdb_module.img ++ $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ ++ } ++ } ++ } ++ ++ cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS { ++ display "Freescale MXC Board build options" ++ flavor none ++ no_define ++ description " ++ Package specific build options including control over ++ compiler flags used only in building this package, ++ and details of which tests are built." ++ ++ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building the board HAL. These flags are used in addition ++ to the set of global flags." ++ } ++ ++ cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE { ++ display "Suppressed compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building the board HAL. These flags are removed from ++ the set of global flags if present." ++ } ++ ++ } ++ ++ cdl_component CYGHWR_MEMORY_LAYOUT { ++ display "Memory layout" ++ flavor data ++ no_define ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" : ++ "arm_board_rom" } ++ ++ cdl_option CYGHWR_MEMORY_LAYOUT_LDI { ++ display "Memory layout linker script fragment" ++ flavor data ++ no_define ++ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "" : ++ "" } ++ } ++ ++ cdl_option CYGHWR_MEMORY_LAYOUT_H { ++ display "Memory layout header file" ++ flavor data ++ no_define ++ define -file system.h CYGHWR_MEMORY_LAYOUT_H ++ calculated { (CYG_HAL_STARTUP == "RAM") ? "" : ++ (CYG_HAL_STARTUP == "ROMRAM") ? "" : ++ "" } ++ } ++ } ++ ++ cdl_option CYGSEM_HAL_ROM_MONITOR { ++ display "Behave as a ROM monitor" ++ flavor bool ++ default_value 0 ++ parent CYGPKG_HAL_ROM_MONITOR ++ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } ++ description " ++ Enable this option if this program is to be used as a ROM monitor, ++ i.e. applications will be loaded into RAM on the board, and this ++ ROM monitor may process exceptions or interrupts generated from the ++ application. This enables features such as utilizing a separate ++ interrupt stack when exceptions are generated." ++ } ++ ++ cdl_option CYGSEM_HAL_USE_ROM_MONITOR { ++ display "Work with a ROM monitor" ++ flavor booldata ++ legal_values { "Generic" "GDB_stubs" } ++ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } ++ parent CYGPKG_HAL_ROM_MONITOR ++ requires { CYG_HAL_STARTUP == "RAM" } ++ description " ++ Support can be enabled for different varieties of ROM monitor. ++ This support changes various eCos semantics such as the encoding ++ of diagnostic output, or the overriding of hardware interrupt ++ vectors. ++ Firstly there is \"Generic\" support which prevents the HAL ++ from overriding the hardware vectors that it does not use, to ++ instead allow an installed ROM monitor to handle them. This is ++ the most basic support which is likely to be common to most ++ implementations of ROM monitor. ++ \"GDB_stubs\" provides support when GDB stubs are included in ++ the ROM monitor or boot ROM." ++ } ++ ++ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { ++ display "Redboot HAL options" ++ flavor none ++ no_define ++ parent CYGPKG_REDBOOT ++ active_if CYGPKG_REDBOOT ++ description " ++ This option lists the target's requirements for a valid Redboot ++ configuration." ++ ++ compile -library=libextras.a redboot_cmds.c ++ ++ cdl_option CYGBLD_BUILD_REDBOOT_BIN { ++ display "Build Redboot ROM binary image" ++ active_if CYGBLD_BUILD_REDBOOT ++ default_value 1 ++ no_define ++ description "This option enables the conversion of the Redboot ELF ++ image to a binary image suitable for ROM programming." ++ ++ make -priority 325 { ++ /bin/redboot.bin : /bin/redboot.elf ++ $(OBJCOPY) --strip-debug $< $(@:.bin=.img) ++ $(OBJCOPY) -O srec $< $(@:.bin=.srec) ++ $(OBJCOPY) -O binary $< $@ ++ } ++ } ++ } ++ ++ cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS { ++ display "Redboot HAL variant options" ++ flavor none ++ no_define ++ parent CYGPKG_REDBOOT ++ active_if CYGPKG_REDBOOT ++ ++ # RedBoot details ++ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90008000 } ++ define_proc { ++ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/fsl_board.h redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/fsl_board.h +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/fsl_board.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/fsl_board.h 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,60 @@ ++#ifndef CYGONCE_FSL_BOARD_H ++#define CYGONCE_FSL_BOARD_H ++ ++//============================================================================= ++// ++// Platform specific support (register layout, etc) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include // Hardware definitions ++ ++#define BOARD_CS_UART_BASE (0x8000) ++ ++#define REDBOOT_IMAGE_SIZE 0x40000 ++ ++#define PMIC_SPI_BASE CSPI1_BASE_ADDR ++#define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0 ++#define PMIC_SPI_SS_POL SPI_CFG_SS0_POL_HIGH ++ ++#define FEC_PHY_ADDR 0 ++ ++/* MX51 3-Stack SDRAM is from 0x40000000, 128M */ ++#define SDRAM_BASE_ADDR CSD0_BASE_ADDR ++#define SDRAM_SIZE 0x20000000 ++#define RAM_BANK0_BASE SDRAM_BASE_ADDR ++ ++#endif /* CYGONCE_FSL_BOARD_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/hal_platform_setup.h redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/hal_platform_setup.h +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/hal_platform_setup.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/hal_platform_setup.h 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,517 @@ ++#ifndef CYGONCE_HAL_PLATFORM_SETUP_H ++#define CYGONCE_HAL_PLATFORM_SETUP_H ++ ++//============================================================================= ++// ++// hal_platform_setup.h ++// ++// Platform specific support for HAL (assembly code) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include // System-wide configuration info ++#include CYGBLD_HAL_VARIANT_H // Variant specific configuration ++#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration ++#include // Variant specific hardware definitions ++#include // MMU definitions ++#include // Platform specific hardware definitions ++ ++#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) ++#define PLATFORM_SETUP1 _platform_setup1 ++#define CYGHWR_HAL_ARM_HAS_MMU ++ ++#ifdef CYG_HAL_STARTUP_ROMRAM ++#define CYGSEM_HAL_ROM_RESET_USES_JUMP ++#endif ++ ++//#define NFC_2K_BI_SWAP ++#define SDRAM_FULL_PAGE_BIT 0x100 ++#define SDRAM_FULL_PAGE_MODE 0x37 ++#define SDRAM_BURST_MODE 0x33 ++ ++#define CYGHWR_HAL_ROM_VADDR 0x0 ++ ++#if 0 ++#define UNALIGNED_ACCESS_ENABLE ++#define SET_T_BIT_DISABLE ++#define BRANCH_PREDICTION_ENABLE ++#endif ++ ++#define DCDGEN(i,type, addr, data) \ ++dcd_##i: ;\ ++ .long type ;\ ++ .long addr ;\ ++ .long data ++ ++#define PLATFORM_PREAMBLE flash_header ++//flash header & DCD @ 0x400 ++.macro flash_header ++ b reset_vector ++ .org 0x400 ++app_code_jump_v: .long reset_vector ++app_code_barker: .long 0xB1 ++app_code_csf: .long 0 ++dcd_ptr_ptr: .long dcd_ptr ++super_root_key: .long 0 ++dcd_ptr: .long dcd_data ++app_dest_ptr: .long 0xAFF00000 ++ ++dcd_data: .long 0xB17219E9 // Fixed. can't change. ++dcd_len: .long (56*12) ++ ++//DCD ++//DDR2 IOMUX configuration ++DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) ++DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) ++DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) ++DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) ++DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) ++DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) ++DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) ++DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) ++DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) ++DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) ++DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) ++DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) ++DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) ++DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) ++DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) ++DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) ++DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) ++DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) ++//Set drive strength to HIGH ++DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4) ++DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4) ++DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4) ++DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4) ++//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model ++//CAS=3, BL=4 ++DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) ++DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) ++DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) ++DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333584AB) ++DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333584AB) ++// Init DRAM on CS0 ++DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) ++DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) ++DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) ++DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019) ++DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) ++DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) ++DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) ++DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) ++DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) ++DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) ++DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019) ++DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) ++ ++// Init DRAM on CS1 ++DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) ++DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) ++DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) ++DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) ++DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) ++DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) ++DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) ++DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) ++DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) ++DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) ++DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d) ++DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) ++ ++DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) ++DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) ++DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) ++DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) ++DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) ++ ++image_len: .long 256*1024 ++ ++.endm ++ ++//#define ENABLE_IMPRECISE_ABORT ++ ++// This macro represents the initial startup code for the platform ++ .macro _platform_setup1 ++FSL_BOARD_SETUP_START: ++ // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work??? ++ // mcr p15, 0, , c1, c1, 0 ; Write Secure Configuration Register data ++ ++ ldr r0, GPIO1_BASE_ADDR_W ++ ldr r1, [r0, #0x0] ++ orr r1, r1, #(1 << 23) ++ str r1, [r0, #0x0] ++ ldr r1, [r0, #0x4] ++ orr r1, r1, #(1 << 23) ++ str r1, [r0, #0x4] ++ ++#ifdef ENABLE_IMPRECISE_ABORT ++ mrs r1, spsr // save old spsr ++ mrs r0, cpsr // read out the cpsr ++ bic r0, r0, #0x100 // clear the A bit ++ msr spsr, r0 // update spsr ++ add lr, pc, #0x8 // update lr ++ movs pc, lr // update cpsr ++ nop ++ nop ++ nop ++ nop ++ msr spsr, r1 // restore old spsr ++#endif ++ // explicitly disable L2 cache ++ mrc 15, 0, r0, c1, c0, 1 ++ bic r0, r0, #0x2 ++ mcr 15, 0, r0, c1, c0, 1 ++ ++ // reconfigure L2 cache aux control reg ++ mov r0, #0xC0 // tag RAM ++ add r0, r0, #0x4 // data RAM ++ orr r0, r0, #(1 << 24) // disable write allocate delay ++ orr r0, r0, #(1 << 23) // disable write allocate combine ++ orr r0, r0, #(1 << 22) // disable write allocate ++ ++ ldr r1, =ROM_BASE_ADDRESS ++ ldr r3, [r1, #ROM_SI_REV_OFFSET] ++ cmp r3, #0x10 ++ orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs ++ ++ mcr 15, 1, r0, c9, c0, 2 ++ ++init_aips_start: ++ init_aips ++init_m4if_start: ++ init_m4if ++#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */ ++ /* Check if need to copy image to Redboot ROM space */ ++ ldr r0, =0xFFFFF000 ++ and r0, r0, pc ++ ldr r1, MXC_REDBOOT_ROM_START ++ cmp r0, r1 ++ beq HWInitialise_skip_SDRAM_copy ++ ++ add r2, r0, #REDBOOT_IMAGE_SIZE ++ ++1: ldmia r0!, {r3-r10} ++ stmia r1!, {r3-r10} ++ cmp r0, r2 ++ ble 1b ++ /* Jump to SDRAM */ ++ ldr r1, =0xFFFF ++ and r0, pc, r1 /* offset of pc */ ++ ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8) ++ add pc, r0, r1 ++ nop ++ nop ++ nop ++ nop ++#endif /* CYG_HAL_STARTUP_ROMRAM */ ++ ++HWInitialise_skip_SDRAM_copy: ++ /* Skip clock setup if already booted up */ ++ ldr r0, =IRAM_BASE_ADDR ++ ldr r0, [r0] ++ ldr r1, =FROM_SPI_NOR_FLASH ++ cmp r0, r1 ++ beq Normal_Boot_Continue ++ ldr r1, =FROM_MMC_FLASH ++ cmp r0, r1 ++ beq Normal_Boot_Continue ++ ++init_clock_start: ++ init_clock ++ ++Normal_Boot_Continue: ++ ++/* ++ * Note: ++ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity ++ */ ++STACK_Setup: ++ // Set up a stack [for calling C code] ++ ldr r1, =__startup_stack ++ ldr r2, =RAM_BANK0_BASE ++ orr sp, r1, r2 ++ ++ // Create MMU tables ++ bl hal_mmu_init ++ ++ /* Workaround for arm errata #709718 */ ++ //Setup PRRR so device is always mapped to non-shared ++ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register ++ bic r1, #(3 << 16) ++ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register ++ ++ // Enable MMU ++ ldr r2, =10f ++ mrc MMU_CP, 0, r1, MMU_Control, c0 ++ orr r1, r1, #7 // enable MMU bit ++ orr r1, r1, #0x800 // enable z bit ++ orr r1, r1, #(1 << 28) // Enable TEX remap ++ mcr MMU_CP, 0, r1, MMU_Control, c0 ++ ++ /* Workaround for arm errata #621766 */ ++ mrc MMU_CP, 0, r1, MMU_Control, c0, 1 ++ orr r1, r1, #(1 << 5) // enable L1NEON bit ++ mcr MMU_CP, 0, r1, MMU_Control, c0, 1 ++ ++ mov pc,r2 /* Change address spaces */ ++ nop ++ nop ++ nop ++10: ++ ++ // Save shadow copy of BCR, also hardware configuration ++ ldr r1, =_board_BCR ++ str r2, [r1] ++ ldr r1, =_board_CFG ++ str r9, [r1] // Saved far above... ++ ++ .endm // _platform_setup1 ++ ++#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) ++#define PLATFORM_SETUP1 ++#endif ++ ++ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ ++ .macro init_aips ++ /* ++ * Set all MPROTx to be non-bufferable, trusted for R/W, ++ * not forced to user-mode. ++ */ ++ ldr r0, AIPS1_CTRL_BASE_ADDR_W ++ ldr r1, AIPS1_PARAM_W ++ str r1, [r0, #0x00] ++ str r1, [r0, #0x04] ++ ldr r0, AIPS2_CTRL_BASE_ADDR_W ++ str r1, [r0, #0x00] ++ str r1, [r0, #0x04] ++ ++ .endm /* init_aips */ ++ ++ .macro init_clock ++ ldr r0, CCM_BASE_ADDR_W ++ ++ /* Gate of clocks to the peripherals first */ ++ ldr r1, =0x3FFFFFFF ++ str r1, [r0, #CLKCTL_CCGR0] ++ ldr r1, =0x0 ++ str r1, [r0, #CLKCTL_CCGR1] ++ str r1, [r0, #CLKCTL_CCGR2] ++ str r1, [r0, #CLKCTL_CCGR3] ++ ++ ldr r1, =0x00030000 ++ str r1, [r0, #CLKCTL_CCGR4] ++ ldr r1, =0x00FFF030 ++ str r1, [r0, #CLKCTL_CCGR5] ++ ldr r1, =0x00000300 ++ str r1, [r0, #CLKCTL_CCGR6] ++ ++ /* Disable IPU and HSC dividers */ ++ mov r1, #0x60000 ++ str r1, [r0, #CLKCTL_CCDR] ++ ++ /* Make sure to switch the DDR away from PLL 1 */ ++ ldr r1, CCM_VAL_0x19239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ /* make sure divider effective */ ++ 1: ldr r1, [r0, #CLKCTL_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++ ++ /* Switch ARM to step clock */ ++ mov r1, #0x4 ++ str r1, [r0, #CLKCTL_CCSR] ++ setup_pll PLL1, 800 ++ ++ setup_pll PLL3, 665 ++ /* Switch peripheral to PLL 3 */ ++ ldr r0, CCM_BASE_ADDR_W ++ ldr r1, CCM_VAL_0x000010C0 ++ str r1, [r0, #CLKCTL_CBCMR] ++ ldr r1, CCM_VAL_0x13239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ setup_pll PLL2, 665 ++ /* Switch peripheral to PLL 2 */ ++ ldr r0, CCM_BASE_ADDR_W ++ ldr r1, CCM_VAL_0x19239145 ++ str r1, [r0, #CLKCTL_CBCDR] ++ ldr r1, CCM_VAL_0x000020C0 ++ str r1, [r0, #CLKCTL_CBCMR] ++ ++ setup_pll PLL3, 216 ++ ++ /* Set the platform clock dividers */ ++ ldr r0, PLATFORM_BASE_ADDR_W ++ ldr r1, PLATFORM_CLOCK_DIV_W ++ str r1, [r0, #PLATFORM_ICGC] ++ ++ ldr r0, CCM_BASE_ADDR_W ++ /* Run at slower speed till we increase VDDGP */ ++ mov r1, #0x1 ++ str r1, [r0, #CLKCTL_CACRR] ++ ++ /* Switch ARM back to PLL 1. */ ++ mov r1, #0x0 ++ str r1, [r0, #CLKCTL_CCSR] ++ ++ /* setup the rest */ ++ /* Use lp_apm (24MHz) source for perclk */ ++ ldr r1, CCM_VAL_0x000020C2 ++ str r1, [r0, #CLKCTL_CBCMR] ++ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz ++ ldr r1, CCM_VAL_0x59239100 ++ str r1, [r0, #CLKCTL_CBCDR] ++ ++ /* Restore the default values in the Gate registers */ ++ ldr r1, =0xFFFFFFFF ++ str r1, [r0, #CLKCTL_CCGR0] ++ str r1, [r0, #CLKCTL_CCGR1] ++ str r1, [r0, #CLKCTL_CCGR2] ++ str r1, [r0, #CLKCTL_CCGR3] ++ str r1, [r0, #CLKCTL_CCGR4] ++ str r1, [r0, #CLKCTL_CCGR5] ++ str r1, [r0, #CLKCTL_CCGR6] ++ ++ /* Use PLL 2 for UART's, get 66.5MHz from it */ ++ ldr r1, CCM_VAL_0xA5A2A020 ++ str r1, [r0, #CLKCTL_CSCMR1] ++ ldr r1, CCM_VAL_0x00C30321 ++ str r1, [r0, #CLKCTL_CSCDR1] ++ ++ /* make sure divider effective */ ++ 1: ldr r1, [r0, #CLKCTL_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++ ++ mov r1, #0x00000 ++ str r1, [r0, #CLKCTL_CCDR] ++ ++ // for cko - for ARM div by 8 ++ mov r1, #0x000A0000 ++ add r1, r1, #0x00000F0 ++ str r1, [r0, #CLKCTL_CCOSR] ++ .endm /* init_clock */ ++ ++ .macro setup_pll pll_nr, mhz ++ ldr r0, BASE_ADDR_W_\pll_nr ++ ldr r1, PLL_VAL_0x1232 ++ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ ++ ldr r1, =0x2 ++ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ ++ ++ ldr r1, W_DP_OP_\mhz ++ str r1, [r0, #PLL_DP_OP] ++ str r1, [r0, #PLL_DP_HFS_OP] ++ ++ ldr r1, W_DP_MFD_\mhz ++ str r1, [r0, #PLL_DP_MFD] ++ str r1, [r0, #PLL_DP_HFS_MFD] ++ ++ ldr r1, W_DP_MFN_\mhz ++ str r1, [r0, #PLL_DP_MFN] ++ str r1, [r0, #PLL_DP_HFS_MFN] ++ ++ /* Now restart PLL */ ++ ldr r1, PLL_VAL_0x1232 ++ str r1, [r0, #PLL_DP_CTL] ++wait_pll_lock\pll_nr\mhz: ++ ldr r1, [r0, #PLL_DP_CTL] ++ ands r1, r1, #0x1 ++ beq wait_pll_lock\pll_nr\mhz ++ .endm ++ ++ /* M4IF setup */ ++ .macro init_m4if ++ ldr r1, M4IF_BASE_W ++ ldr r0, M4IF_0x00000203 ++ str r0, [r1, #M4IF_FBPM0] ++ ++ ldr r0, =0x0 ++ str r0, [r1, #M4IF_FBPM1] ++ ++ ldr r0, M4IF_0x00120125 ++ str r0, [r1, #M4IF_FPWC] ++ ++ ldr r0, M4IF_0x001901A3 ++ str r0, [r1, #M4IF_MIF4] ++ .endm /* init_m4if */ ++ ++#define PLATFORM_VECTORS _platform_vectors ++ .macro _platform_vectors ++ .globl _board_BCR, _board_CFG ++_board_BCR: .long 0 // Board Control register shadow ++_board_CFG: .long 0 // Board Configuration (read at RESET) ++ .endm ++ ++AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR ++AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR ++AIPS1_PARAM_W: .word 0x77777777 ++M4IF_BASE_W: .word M4IF_BASE_ADDR ++M4IF_0x00120125: .word 0x00120125 ++M4IF_0x001901A3: .word 0x001901A3 ++M4IF_0x00000203: .word 0x00000203 ++MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 ++GPIO1_BASE_ADDR_W: .word GPIO1_BASE_ADDR ++CCM_BASE_ADDR_W: .word CCM_BASE_ADDR ++CCM_VAL_0x000020C2: .word 0x000020C2 ++CCM_VAL_0x59239100: .word 0x59239100 ++CCM_VAL_0x19239145: .word 0x19239145 ++CCM_VAL_0xA5A2A020: .word 0xA5A2A020 ++CCM_VAL_0x00C30321: .word 0x00C30321 ++CCM_VAL_0x000010C0: .word 0x000010C0 ++CCM_VAL_0x13239145: .word 0x13239145 ++CCM_VAL_0x000020C0: .word 0x000020C0 ++PLL_VAL_0x222: .word 0x222 ++PLL_VAL_0x232: .word 0x232 ++BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR ++BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR ++BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR ++PLL_VAL_0x1232: .word 0x1232 ++W_DP_OP_800: .word DP_OP_800 ++W_DP_MFD_800: .word DP_MFD_800 ++W_DP_MFN_800: .word DP_MFN_800 ++W_DP_OP_665: .word DP_OP_665 ++W_DP_MFD_665: .word DP_MFD_665 ++W_DP_MFN_665: .word DP_MFN_665 ++W_DP_OP_216: .word DP_OP_216 ++W_DP_MFD_216: .word DP_MFD_216 ++W_DP_MFN_216: .word DP_MFN_216 ++PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR ++PLATFORM_CLOCK_DIV_W: .word 0x00000124 ++ ++/*---------------------------------------------------------------------------*/ ++/* end of hal_platform_setup.h */ ++#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.h redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.h +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.h 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,20 @@ ++// eCos memory layout - Fri Oct 20 05:56:55 2000 ++ ++// This is a generated file - do not edit ++ ++#ifndef __ASSEMBLER__ ++#include ++#include ++ ++#endif ++#define CYGMEM_REGION_ram (0x00000000) ++#define CYGMEM_REGION_ram_SIZE (0x1FF00000) ++#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) ++#define CYGMEM_REGION_rom (0xAFF00000) ++#define CYGMEM_REGION_rom_SIZE (0x100000) ++#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) ++#ifndef __ASSEMBLER__ ++extern char CYG_LABEL_NAME (__heap1) []; ++#endif ++#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) ++#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,31 @@ ++// eCos memory layout - Fri Oct 20 05:56:55 2000 ++ ++// This is a generated file - do not edit ++ ++#include ++ ++MEMORY ++{ ++ ram : ORIGIN = 0, LENGTH = 0x1FF00000 ++ rom : ORIGIN = 0xAFF00000, LENGTH = 0x100000 ++} ++ ++SECTIONS ++{ ++ SECTIONS_BEGIN ++ SECTION_rom_vectors (rom, 0xAFF00000, LMA_EQ_VMA) ++ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) ++ SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) ++ SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) ++ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) ++ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); ++ SECTIONS_END ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.mlt redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.mlt +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.mlt 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.mlt 2010-01-26 17:35:49.992961003 +0000 +@@ -0,0 +1,14 @@ ++version 0 ++region ram 0 1FF00000 0 ! ++region rom AFF00000 100000 1 ! ++section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! ++section data 0 1 1 1 1 1 0 0 8000 bss ! ++section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! ++section heap1 0 8 0 0 0 0 0 0 ! ++section rom_vectors 0 1 0 1 1 1 1 1 AFF00000 AFF00000 text text ! ++section text 0 4 0 1 0 1 0 1 fini fini ! ++section fini 0 4 0 1 0 1 0 1 rodata rodata ! ++section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! ++section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! ++section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! ++section gcc_except_table 0 4 0 1 0 0 0 1 data ! +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/plf_io.h redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/plf_io.h +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/plf_io.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/plf_io.h 2010-01-26 17:35:50.002962878 +0000 +@@ -0,0 +1,69 @@ ++#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H ++#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H ++ ++//============================================================================= ++// ++// plf_io.h ++// ++// Platform specific support (register layout, etc) ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++ ++#include ++#include ++ ++#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \ ++ CYG_MACRO_START \ ++ { \ ++ extern unsigned int system_rev; \ ++ /* Next ATAG_MEM. */ \ ++ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \ ++ _p_->hdr.tag = ATAG_MEM; \ ++ /* Round up so there's only one bit set in the memory size. \ ++ * Don't double it if it's already a power of two, though. \ ++ */ \ ++ _p_->u.mem.size = 1<u.mem.size < CYGMEM_REGION_ram_SIZE) \ ++ _p_->u.mem.size <<= 1; \ ++ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \ ++ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \ ++ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \ ++ _p_->hdr.tag = ATAG_REVISION; \ ++ _p_->u.revision.rev = system_rev; \ ++ } \ ++ CYG_MACRO_END ++ ++#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/plf_mmap.h redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/plf_mmap.h +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/plf_mmap.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/plf_mmap.h 2010-01-26 17:35:50.002962878 +0000 +@@ -0,0 +1,94 @@ ++#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H ++#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H ++//============================================================================= ++// ++// plf_mmap.h ++// ++// Platform specific memory map support ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include ++#include // Platform specific hardware definitions ++ ++// Get the pagesize for a particular virtual address: ++ ++// This does not depend on the vaddr. ++#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \ ++ (pagesize) = SZ_1M; \ ++CYG_MACRO_END ++ ++// Get the physical address from a virtual address: ++ ++#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \ ++ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \ ++ if ( _v_ < SDRAM_SIZE - 0x100000) /* SDRAM */ \ ++ _v_ += SDRAM_BASE_ADDR; \ ++ else /* Rest of it */ \ ++ /* no change */ ; \ ++ (paddr) = _v_; \ ++CYG_MACRO_END ++ ++/* ++ * translate the virtual address of ram space to physical address ++ * It is dependent on the implementation of hal_mmu_init ++ */ ++static unsigned long __inline__ hal_virt_to_phy(unsigned long virt) ++{ ++ if(virt < (SDRAM_SIZE - 0x100000)) { ++ return (virt + SDRAM_BASE_ADDR); ++ } ++ if(virt >= 0xE0000000) { ++ return ((virt - 0xE0000000) + SDRAM_BASE_ADDR); ++ } ++ return virt; ++} ++ ++/* ++ * remap the physical address of ram space to uncacheable virtual address space ++ * It is dependent on the implementation of hal_mmu_init ++ */ ++static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy) ++{ ++ /* 0xE0000000~0xFFFFFFFF is uncacheable meory space which is mapped to SDRAM*/ ++ if(phy >= SDRAM_BASE_ADDR && phy < (SDRAM_BASE_ADDR + SDRAM_SIZE)) { ++ phy = (phy - SDRAM_BASE_ADDR) + 0xE0000000; ++ } ++ return phy; ++} ++ ++//--------------------------------------------------------------------------- ++#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM.ecm redboot-imx-200952/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM.ecm +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM.ecm 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/misc/redboot_ROMRAM.ecm 2010-01-26 17:35:50.002962878 +0000 +@@ -0,0 +1,132 @@ ++cdl_savefile_version 1; ++cdl_savefile_command cdl_savefile_version {}; ++cdl_savefile_command cdl_savefile_command {}; ++cdl_savefile_command cdl_configuration { description hardware template package }; ++cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; ++cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; ++ ++cdl_configuration eCos { ++ description "" ; ++ hardware mx51_babbage ; ++ template redboot ; ++ package -hardware CYGPKG_HAL_ARM current ; ++ package -hardware CYGPKG_HAL_ARM_MX51 current ; ++ package -hardware CYGPKG_HAL_ARM_MX51_BABBAGE current ; ++ package -hardware CYGPKG_IMX_COMMON current ; ++ package -hardware CYGPKG_IO_SERIAL_ARM_IMX ; ++ package -hardware CYGPKG_IO_ETH_DRIVERS current ; ++ package -hardware CYGPKG_DEVS_ETH_FEC current ; ++ package -hardware CYGPKG_COMPRESS_ZLIB current ; ++ package -hardware CYGPKG_IO_FLASH current ; ++ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ; ++ package -hardware CYGPKG_DEVS_IMX_SPI current ; ++ package -template CYGPKG_HAL current ; ++ package -template CYGPKG_INFRA current ; ++ package -template CYGPKG_REDBOOT current ; ++ package -template CYGPKG_ISOINFRA current ; ++ package -template CYGPKG_LIBC_STRING current ; ++ package -template CYGPKG_CRC current ; ++ package CYGPKG_MEMALLOC current ; ++}; ++ ++cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { ++ inferred_value 0 ++}; ++ ++cdl_option CYGHWR_DEVS_FLASH_MMC { ++ inferred_value 1 ++}; ++ ++cdl_option CYGHWR_DEVS_IMX_ECSPI { ++ inferred_value 1 ++}; ++ ++cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { ++ inferred_value 0 ++}; ++ ++cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { ++ user_value 4096 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { ++ user_value 0 ++}; ++ ++cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { ++ user_value 50 ++}; ++ ++cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { ++ inferred_value 0 ++}; ++ ++cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { ++ inferred_value 1 ++}; ++ ++cdl_option CYGSEM_HAL_ROM_MONITOR { ++ inferred_value 1 ++}; ++ ++cdl_component CYGBLD_BUILD_REDBOOT { ++ user_value 1 ++}; ++ ++cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { ++ inferred_value 0x00040000 ++}; ++ ++cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { ++ inferred_value 0x90008000 ++}; ++ ++cdl_option CYGBLD_ISO_STRTOK_R_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { ++ inferred_value 1 ++}; ++ ++cdl_component CYG_HAL_STARTUP { ++ user_value ROMRAM ++}; ++ ++cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { ++ inferred_value 1 ++}; ++ ++cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { ++ inferred_value 4 ++}; ++ ++cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { ++ user_value 1 "FSL 200952" ++}; +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/src/board_misc.c redboot-imx-200952/packages/hal/arm/mx51/babbage/current/src/board_misc.c +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/src/board_misc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/src/board_misc.c 2010-01-26 17:35:50.002962878 +0000 +@@ -0,0 +1,504 @@ ++//========================================================================== ++// ++// board_misc.c ++// ++// HAL misc board support code for the board ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================*/ ++ ++#include ++#include ++#include ++#include CYGBLD_HAL_PLATFORM_H ++ ++#include // base types ++#include // tracing macros ++#include // assertion macros ++ ++#include // IO macros ++#include // Register state info ++#include ++#include // Interrupt names ++#include ++#include // Hardware definitions ++#include // Platform specifics ++#include // diag_printf ++ ++// All the MM table layout is here: ++#include ++ ++externC void* memset(void *, int, size_t); ++unsigned int cpld_base_addr; ++extern char HAL_PLATFORM_EXTRA[40]; ++ ++void hal_mmu_init(void) ++{ ++ unsigned long ttb_base = RAM_BANK0_BASE + 0x4000; ++ unsigned long i; ++ ++ /* ++ * Set the TTB register ++ */ ++ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); ++ ++ /* ++ * Set the Domain Access Control Register ++ */ ++ i = ARM_ACCESS_DACR_DEFAULT; ++ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); ++ ++ /* ++ * First clear all TT entries - ie Set them to Faulting ++ */ ++ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); ++ ++ /* Actual Virtual Size Attributes Function */ ++ /* Base Base MB cached? buffered? access permissions */ ++ /* xxx00000 xxx00000 */ ++ X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */ ++ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */ ++ X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */ ++ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */ ++ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */ ++ X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ ++ X_ARM_MMU_SECTION(0x900, 0x900, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ ++ X_ARM_MMU_SECTION(0x900, 0xE00, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/ ++ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ ++ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */ ++} ++ ++static void mxc_fec_setup(void) ++{ ++ volatile unsigned int reg; ++ ++ /*FEC_MDIO*/ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0D4); ++ writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0954); ++ ++ /*FEC_MDC*/ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x13C); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0524); ++ ++ /* FEC RDATA[3] */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0EC); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0480); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0964); ++ ++ /* FEC RDATA[2] */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0E8); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x047C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0960); ++ ++ /* FEC RDATA[1] */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0d8); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x046C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x095C); ++ ++ /* FEC RDATA[0] */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x016C); ++ writel(0x2180, IOMUXC_BASE_ADDR + 0x0554); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0958); ++ ++ /* FEC TDATA[3] */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x148); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0530); ++ ++ /* FEC TDATA[2] */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x144); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x052C); ++ ++ /* FEC TDATA[1] */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x140); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0528); ++ ++ /* FEC TDATA[0] */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0170); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0558); ++ ++ /* FEC TX_EN */ ++ writel(0x1, IOMUXC_BASE_ADDR + 0x014C); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0534); ++ ++ /* FEC TX_ER */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x0138); ++ writel(0x2004, IOMUXC_BASE_ADDR + 0x0520); ++ ++ /* FEC TX_CLK */ ++ writel(0x1, IOMUXC_BASE_ADDR + 0x0150); ++ writel(0x2180, IOMUXC_BASE_ADDR + 0x0538); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0974); ++ ++ /* FEC COL */ ++ writel(0x1, IOMUXC_BASE_ADDR + 0x0124); ++ writel(0x2180, IOMUXC_BASE_ADDR + 0x0500); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x094c); ++ ++ /* FEC RX_CLK */ ++ writel(0x1, IOMUXC_BASE_ADDR + 0x0128); ++ writel(0x2180, IOMUXC_BASE_ADDR + 0x0504); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0968); ++ ++ /* FEC CRS */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0f4); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0488); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0950); ++ ++ /* FEC RX_ER */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x0f0); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x0484); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x0970); ++ ++ /* FEC RX_DV */ ++ writel(0x2, IOMUXC_BASE_ADDR + 0x164); ++ writel(0x2180, IOMUXC_BASE_ADDR + 0x054C); ++ writel(0x0, IOMUXC_BASE_ADDR + 0x096C); ++} ++ ++#include ++struct spi_v2_3_reg spi_pmic_reg; ++ ++struct imx_spi_dev imx_spi_pmic = { ++ base : CSPI1_BASE_ADDR, ++ freq : 25000000, ++ ss_pol : IMX_SPI_ACTIVE_HIGH, ++ ss : 0, // slave select 0 ++ fifo_sz : 32, ++ reg : &spi_pmic_reg, ++}; ++ ++struct spi_v2_3_reg spi_nor_reg; ++ ++struct imx_spi_dev imx_spi_nor = { ++ base : CSPI1_BASE_ADDR, ++ freq : 25000000, ++ ss_pol : IMX_SPI_ACTIVE_LOW, ++ ss : 1, // slave select 1 ++ fifo_sz : 32, ++ us_delay: 0, ++ reg : &spi_nor_reg, ++}; ++ ++imx_spi_init_func_t *spi_nor_init; ++imx_spi_xfer_func_t *spi_nor_xfer; ++ ++imx_spi_init_func_t *spi_pmic_init; ++imx_spi_xfer_func_t *spi_pmic_xfer; ++ ++// ++// Platform specific initialization ++// ++static void babbage_power_init(void); ++ ++void plf_hardware_init(void) ++{ ++ unsigned int reg; ++ ++ spi_nor_init = (imx_spi_init_func_t *)imx_ecspi_init; ++ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_ecspi_xfer; ++ ++ spi_pmic_init = (imx_spi_init_func_t *)imx_ecspi_init; ++ spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_ecspi_xfer; ++ spi_pmic_init(&imx_spi_pmic); ++ ++ babbage_power_init(); ++ ++ // UART1 ++ //RXD ++ writel(0x0, IOMUXC_BASE_ADDR + 0x228); ++ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618); ++ //TXD ++ writel(0x0, IOMUXC_BASE_ADDR + 0x22c); ++ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c); ++ //RTS ++ writel(0x0, IOMUXC_BASE_ADDR + 0x230); ++ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620); ++ //CTS ++ writel(0x0, IOMUXC_BASE_ADDR + 0x234); ++ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624); ++ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2 ++ writel(0x00000004, 0x73fa83E8); ++ writel(0x00000004, 0x73fa83Ec); ++ ++ // enable ARM clock div by 8 ++ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR); ++ ++ /* Configure UART3_RXD pin for GPIO */ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x240); ++ reg = readl(GPIO1_BASE_ADDR + 0x4); ++ reg &= ~0x400000; // configure GPIO lines as input ++ writel(reg, GPIO1_BASE_ADDR + 0x4); ++ ++ if ((readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) { ++ /* Babbage 2.5 */ ++ system_rev |= 0x1 << BOARD_VER_OFFSET; ++ HAL_PLATFORM_EXTRA[32] = '5'; ++ } ++} ++ ++void mxc_mmc_init(unsigned int base_address) ++{ ++ switch(base_address) { ++ case MMC_SDHC1_BASE_ADDR: ++ /* SD1 CMD, SION bit */ ++ writel(0x10, IOMUXC_BASE_ADDR + 0x394); ++ /* Configure SW PAD */ ++ /* SD1 CMD */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x79C); ++ /* SD1 CLK */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0); ++ /* SD1 DAT0 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4); ++ /* SD1 DAT1 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8); ++ /* SD1 DAT2 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC); ++ /* SD1 DAT3 */ ++ writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0); ++ break; ++ case MMC_SDHC2_BASE_ADDR: ++ /* SD2 CMD, SION bit */ ++ writel(0x10, IOMUXC_BASE_ADDR + 0x3b4); ++ /* Configure SW PAD */ ++ /* SD2 CMD */ ++ writel(0x20f4, IOMUXC_BASE_ADDR + 0x7bc); ++ /* SD2 CLK */ ++ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7c0); ++ /* SD2 DAT0 */ ++ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7c4); ++ /* SD2 DAT1 */ ++ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7c8); ++ /* SD2 DAT2 */ ++ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7cc); ++ /* SD2 DAT3 */ ++ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7d0); ++ default: ++ break; ++ } ++} ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++typedef void code_fun(void); ++ ++void board_program_new_stack(void *func) ++{ ++ register CYG_ADDRESS stack_ptr asm("sp"); ++ register CYG_ADDRESS old_stack asm("r4"); ++ register code_fun *new_func asm("r0"); ++ old_stack = stack_ptr; ++ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS); ++ new_func = (code_fun*)func; ++ new_func(); ++ stack_ptr = old_stack; ++} ++ ++void increase_core_voltage(bool i) ++{ ++ unsigned int val; ++ ++ val = pmic_reg(24, 0, 0); ++ if (i) { ++ /* Set core voltage to 1.2V */ ++ val = val & (~0x1F) | 0x18; ++ } else { ++ /* Set core voltage to 1.1V */ ++ val = val & (~0x1F) | 0x14; ++ } ++ pmic_reg(24, val, 1); ++ ++ val = pmic_reg(26, 0, 0); ++ if (i) { ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ val = val & (~0x1F) | 0x1A; ++ } else { ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ val = val & (~0x1F) | 0x18; ++ } ++ pmic_reg(26, val, 1); ++} ++ ++extern unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write); ++static void babbage_power_init(void) ++{ ++ unsigned int val; ++ volatile unsigned int reg; ++ ++ /* Write needed to Power Gate 2 register */ ++ val = pmic_reg(34, 0, 0); ++ val &= ~0x10000; ++ pmic_reg(34, val, 1); ++ ++ /* Write needed to update Charger 0 */ ++ pmic_reg(48, 0x0023807F, 1); ++ ++ /* Set core voltage to 1.1V */ ++ val = pmic_reg(24, 0, 0); ++ val = val & (~0x1F) | 0x14; ++ pmic_reg(24, val, 1); ++ hal_delay_us(50); ++ /* Raise the core frequency */ ++ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); ++ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) { ++ /* Setup VCC (SW2) to 1.25 */ ++ val = pmic_reg(25, 0, 0); ++ val = val & (~0x1F) | 0x1A; ++ pmic_reg(25, val, 1); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ val = pmic_reg(26, 0, 0); ++ val = val & (~0x1F) | 0x1A; ++ pmic_reg(26, val, 1); ++ ++ } else { ++ /* TO 3.0 */ ++ /* Setup VCC (SW2) to 1.225 */ ++ val = pmic_reg(25, 0, 0); ++ val = val & (~0x1F) | 0x19; ++ pmic_reg(25, val, 1); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ val = pmic_reg(26, 0, 0); ++ val = val & (~0x1F) | 0x18; ++ pmic_reg(26, val, 1); ++ } ++ ++ if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) { ++ /* Set switchers in PWM mode for Atlas 2.0 and lower */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ val = pmic_reg(28, 0, 0); ++ val = val & (~0x3C0F) | 0x1405; ++ pmic_reg(28, val, 1); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ val = pmic_reg(29, 0, 0); ++ val = val & (~0xF0F) | 0x505; ++ pmic_reg(29, val, 1); ++ } else { ++ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ val = pmic_reg(28, 0, 0); ++ val = val & (~0x3C0F) | 0x2008; ++ pmic_reg(28, val, 1); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ val = pmic_reg(29, 0, 0); ++ val = val & (~0xF0F) | 0x808; ++ pmic_reg(29, val, 1); ++ } ++ ++ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ ++ val = pmic_reg(30, 0, 0); ++ val &= ~0x34030; ++ val |= 0x10020; ++ pmic_reg(30, val, 1); ++ ++ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ ++ val = pmic_reg(31, 0, 0); ++ val &= ~0x1FC; ++ val |= 0x1F4; ++ pmic_reg(31, val, 1); ++ ++ /* Configure VGEN3 and VCAM regulators to use external PNP */ ++ val = 0x208; ++ pmic_reg(33, val, 1); ++ hal_delay_us(200); ++ ++ reg = readl(GPIO2_BASE_ADDR + 0x0); ++ reg &= ~0x4000; // Lower reset line ++ writel(reg, GPIO2_BASE_ADDR + 0x0); ++ ++ reg = readl(GPIO2_BASE_ADDR + 0x4); ++ reg |= 0x4000; // configure GPIO lines as output ++ writel(reg, GPIO2_BASE_ADDR + 0x4); ++ ++ /* Reset the ethernet controller over GPIO */ ++ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); ++ ++ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ ++ val = 0x49249; ++ pmic_reg(33, val, 1); ++ ++ hal_delay_us(500); ++ ++ reg = readl(GPIO2_BASE_ADDR + 0x0); ++ reg |= 0x4000; ++ writel(reg, GPIO2_BASE_ADDR + 0x0); ++ ++ /* Setup the FEC after enabling the regulators */ ++ mxc_fec_setup(); ++} ++ ++void io_cfg_spi(struct imx_spi_dev *dev) ++{ ++ switch (dev->base) { ++ case CSPI1_BASE_ADDR: ++ // 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 ++ writel(0x0, IOMUXC_BASE_ADDR + 0x210); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x600); ++ ++ // 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. ++ writel(0x0, IOMUXC_BASE_ADDR + 0x214); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x604); ++ if (dev->ss == 0) { ++ // de-select SS1 of instance: ecspi1. ++ writel(0x3, IOMUXC_BASE_ADDR + 0x21C); ++ writel(0x85, IOMUXC_BASE_ADDR + 0x60C); ++ // 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. ++ writel(0x0, IOMUXC_BASE_ADDR + 0x218); ++ writel(0x185, IOMUXC_BASE_ADDR + 0x608); ++ } else if (dev->ss == 1) { ++ // de-select SS0 of instance: ecspi1. ++ writel(0x3, IOMUXC_BASE_ADDR + 0x218); ++ writel(0x85, IOMUXC_BASE_ADDR + 0x608); ++ // 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1. ++ writel(0x0, IOMUXC_BASE_ADDR + 0x21C); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x60C); ++ } ++ // 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. ++ writel(0x0, IOMUXC_BASE_ADDR + 0x220); ++ writel(0x180, IOMUXC_BASE_ADDR + 0x610); ++ ++ // 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. ++ writel(0x0, IOMUXC_BASE_ADDR + 0x224); ++ writel(0x105, IOMUXC_BASE_ADDR + 0x614); ++ break; ++ case CSPI2_BASE_ADDR: ++ default: ++ break; ++ } ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/src/redboot_cmds.c redboot-imx-200952/packages/hal/arm/mx51/babbage/current/src/redboot_cmds.c +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/src/redboot_cmds.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/src/redboot_cmds.c 2010-01-26 17:35:50.012962254 +0000 +@@ -0,0 +1,200 @@ ++//========================================================================== ++// ++// redboot_cmds.c ++// ++// Board [platform] specific RedBoot commands ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++#include ++#include ++#include ++#include ++#include // Platform specific hardware definitions ++ ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++#include ++ ++#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE) ++#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE ++#endif ++ ++RedBoot_config_option("Board specifics", ++ brd_specs, ++ ALWAYS_ENABLED, ++ true, ++ CONFIG_INT, ++ 0 ++ ); ++#endif //CYGSEM_REDBOOT_FLASH_CONFIG ++ ++char HAL_PLATFORM_EXTRA[40] = "PASS x.x [x32 DDR]. Board Rev 2.0"; ++ ++#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM) ++ ++RedBoot_cmd("romupdate", ++ "Update Redboot with currently running image", ++ "", ++ romupdate ++ ); ++ ++extern int flash_program(void *_addr, void *_data, int len, void **err_addr); ++extern int flash_erase(void *addr, int len, void **err_addr); ++extern char *flash_errmsg(int err); ++extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value ++extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32); ++extern int spi_nor_erase_block(void* block_addr, unsigned int block_size); ++extern int spi_nor_program_buf(void *addr, void *data, int len); ++extern void __attribute__((__noinline__)) launchRunImg(unsigned long addr); ++ ++#ifdef CYGPKG_IO_FLASH ++void romupdate(int argc, char *argv[]) ++{ ++ void *err_addr, *base_addr; ++ int stat; ++ unsigned int nfc_config3_reg, temp; ++ ++ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) { ++ diag_printf("Updating ROM in MMC/SD flash\n"); ++ /* eMMC 4.3 and eSD 2.1 supported on TO 2.0 and higher */ ++ if(!emmc_set_boot_partition((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) { ++ /* eMMC 4.3 */ ++ diag_printf("Card supports MMC-4.3, programming for boot operation.\n"); ++ return; ++ } else if(!esd_set_boot_partition((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) { ++ /* eSD 2.1 */ ++ diag_printf("Card supports SD-2.1, programming for boot operation.\n"); ++ return; ++ } ++ ++ base_addr = (void*)0; ++ /* Read the first 1K from the card */ ++ mmc_data_read((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), ++ 0x400, base_addr); ++ diag_printf("Programming Redboot to MMC/SD flash\n"); ++ mmc_data_write((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), ++ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr); ++ return; ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()) { ++ diag_printf("Updating ROM in SPI-NOR flash\n"); ++ base_addr = (void*)0; ++ } else { ++ diag_printf("romupdate not supported\n"); ++ diag_printf("Use \"factive [SPI|MMC]\" to select either NAND or MMC flash\n"); ++ } ++ ++ // Erase area to be programmed ++ if ((stat = flash_erase((void *)base_addr, ++ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, ++ (void **)&err_addr)) != 0) { ++ diag_printf("Can't erase region at %p: %s\n", ++ err_addr, flash_errmsg(stat)); ++ return; ++ } ++ // Now program it ++ if ((stat = flash_program((void *)base_addr, ++ (void *)SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000, ++ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, ++ (void **)&err_addr)) != 0) { ++ diag_printf("Can't program region at %p: %s\n", ++ err_addr, flash_errmsg(stat)); ++ } ++} ++RedBoot_cmd("factive", ++ "Enable one flash media for Redboot", ++ "[MMC|SPI]", ++ factive ++ ); ++ ++typedef void reset_func_t(void); ++ ++extern reset_func_t reset_vector; ++ ++void factive(int argc, char *argv[]) ++{ ++ unsigned int *fis_addr = IRAM_BASE_ADDR; ++ ++ if (argc != 2) { ++ diag_printf("Invalid factive cmd\n"); ++ return; ++ } ++ ++ if (strcasecmp(argv[1], "MMC") == 0) { ++ *fis_addr = FROM_MMC_FLASH; ++ } else if (strcasecmp(argv[1], "SPI") == 0) { ++ *fis_addr = FROM_SPI_NOR_FLASH; ++ } ++ else { ++ diag_printf("Invalid command: %s\n", argv[1]); ++ return; ++ } ++ ++ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr); ++ launchRunImg(reset_vector); ++} ++#endif //CYGPKG_IO_FLASH ++ ++#define POST_SDRAM_START_OFFSET 0x800000 ++#define POST_MMC_OFFSET 0x100000 ++#define POST_SIZE 0x100000 ++#define POST_MAGIC_MARKER 0x43 ++ ++void imx_launch_post(void) ++{ ++ mmc_data_read(0x100000, // ram location ++ 0x40000, // length ++ 0x100000); // from MMC/SD offset 0x100000 ++ /* Need this to recognize the SPI-NOR part */ ++ if (spi_norflash_hwr_init() != 0) ++ return; ++ ++ spi_nor_erase_block(0, 0x10000); ++ spi_nor_erase_block(0x10000, 0x10000); ++ spi_nor_erase_block(0x20000, 0x10000); ++ spi_nor_erase_block(0x30000, 0x10000); ++ // save the redboot to SPI-NOR ++ if (spi_nor_program_buf(0, 0x100000, 0x40000) != 0) ++ return; ++ ++ diag_printf("Reading POST from MMC to SDRAM...\n"); ++ mmc_data_read(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET, // ram location ++ 0x200000, // length ++ 0x200000); // from MMC offset ++ diag_printf("Launching POST\n"); ++ launchRunImg(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET); ++} ++//RedBoot_init(imx_launch_post, RedBoot_INIT_BEFORE_NET); ++ ++#endif /* CYG_HAL_STARTUP_ROMRAM */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/cdl/hal_arm_soc.cdl redboot-imx-200952/packages/hal/arm/mx51/var/current/cdl/hal_arm_soc.cdl +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/cdl/hal_arm_soc.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/cdl/hal_arm_soc.cdl 2010-01-26 17:35:50.012962254 +0000 +@@ -0,0 +1,144 @@ ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): gthomas ++# Original data: gthomas ++# Contributors: ++# Date: 2000-05-08 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++cdl_package CYGPKG_HAL_ARM_MX51 { ++ display "Freescale SoC architecture" ++ parent CYGPKG_HAL_ARM ++ hardware ++ include_dir cyg/hal ++ define_header hal_arm_soc.h ++ description " ++ This HAL variant package provides generic ++ support for the Freescale SoC. It is also ++ necessary to select a specific target platform HAL ++ package." ++ ++ implements CYGINT_HAL_ARM_ARCH_ARM9 ++ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT ++ ++ # Let the architectural HAL see this variant's interrupts file - ++ # the SoC has no variation between targets here. ++ define_proc { ++ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H " ++ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" ++ ++ puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000" ++ } ++ ++ compile soc_misc.c ++ compile -library=libextras.a cmds.c ++ ++ cdl_option CYGHWR_MX51_TO2 { ++ display "MX51 Tapeout 2.0 support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates support for ++ MX51 Tapeout 2.0" ++ define_proc { ++ puts $::cdl_system_header "#define IMX51_TO_2" ++ } ++ } ++ ++ cdl_option CYGHWR_MX51_MDDR { ++ display "MX51 mDDR memory support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates support for ++ mDDR memory on MX51" ++ define_proc { ++ puts $::cdl_system_header "#define IMX51_MDDR" ++ } ++ } ++ ++ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK { ++ display "Processor clock rate" ++ active_if { CYG_HAL_STARTUP == "ROM" } ++ flavor data ++ legal_values 150000 200000 ++ default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ? ++ CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000} ++ description " ++ The processor can run at various frequencies. ++ These values are expressed in KHz. Note that there are ++ several steppings of the rated to run at different ++ maximum frequencies. Check the specs to make sure that your ++ particular processor can run at the rate you select here." ++ } ++ ++ # Real-time clock/counter specifics ++ cdl_component CYGNUM_HAL_RTC_CONSTANTS { ++ display "Real-time clock constants" ++ flavor none ++ no_define ++ ++ cdl_option CYGNUM_HAL_RTC_NUMERATOR { ++ display "Real-time clock numerator" ++ flavor data ++ calculated 1000000000 ++ } ++ cdl_option CYGNUM_HAL_RTC_DENOMINATOR { ++ display "Real-time clock denominator" ++ flavor data ++ default_value 100 ++ description " ++ This option selects the heartbeat rate for the real-time clock. ++ The rate is specified in ticks per second. Change this value ++ with caution - too high and your system will become saturated ++ just handling clock interrupts, too low and some operations ++ such as thread scheduling may become sluggish." ++ } ++ cdl_option CYGNUM_HAL_RTC_PERIOD { ++ display "Real-time clock period" ++ flavor data ++ calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz ++ } ++ } ++ ++ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED { ++ display "FEC ethernet driver required" ++ } ++ ++ implements CYGINT_DEVS_ETH_FEC_REQUIRED ++ ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_cache.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_cache.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_cache.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_cache.h 2010-01-26 17:35:50.012962254 +0000 +@@ -0,0 +1,323 @@ ++#ifndef CYGONCE_HAL_CACHE_H ++#define CYGONCE_HAL_CACHE_H ++ ++//============================================================================= ++// ++// hal_cache.h ++// ++// HAL cache control API ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++ ++#include ++#include // Variant specific hardware definitions ++ ++//----------------------------------------------------------------------------- ++// Global control of data cache ++ ++// Enable the data cache ++#define HAL_DCACHE_ENABLE_L1() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ "mrc p15, 0, r1, c1, c0, 0;" \ ++ "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \ ++ /* the MMU, alignment faults, and */ \ ++ "mcr p15, 0, r1, c1, c0, 0" \ ++ : \ ++ : \ ++ : "r1" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++ ++// Clean+invalidate the both D+I caches at L1 and L2 levels ++#define HAL_CACHE_FLUSH_ALL() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ "stmfd sp!, {r0-r5, r7, r9-r11};" \ ++ "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \ ++ "ands r3, r0, #0x7000000;" /*@ extract loc from clidr */ \ ++ "mov r3, r3, lsr #23;" /*@ left align loc bit field*/ \ ++ "beq 555f;" /* finished;" */ /*@ if loc is 0, then no need to clean*/ \ ++ "mov r10, #0;" /*@ start clean at cache level 0*/ \ ++ "111:" /*"loop1: */ \ ++ "add r2, r10, r10, lsr #1;" /*@ work out 3x current cache level*/ \ ++ "mov r1, r0, lsr r2;" /*@ extract cache type bits from clidr*/ \ ++ "and r1, r1, #7;" /*@ mask of the bits for current cache only*/ \ ++ "cmp r1, #2;" /*@ see what cache we have at this level*/ \ ++ "blt 444f;" /* skip;" */ /*@ skip if no cache, or just i-cache*/ \ ++ "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr*/ \ ++ "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \ ++ "mrc p15, 1, r1, c0, c0, 0;" /*@ read the new csidr*/ \ ++ "and r2, r1, #7;" /*@ extract the length of the cache lines*/ \ ++ "add r2, r2, #4;" /*@ add 4 (line length offset) */ \ ++ "ldr r4, =0x3ff;" \ ++ "ands r4, r4, r1, lsr #3;" /*@ find maximum number on the way size*/ \ ++ ".word 0xE16F5F14;" /*"clz r5, r4;" @ find bit position of way size increment*/ \ ++ "ldr r7, =0x7fff;" \ ++ "ands r7, r7, r1, lsr #13;" /*@ extract max number of the index size*/ \ ++ "222:" /* loop2:" */ \ ++ "mov r9, r4;" /*@ create working copy of max way size*/ \ ++ "333:" /* loop3:" */ \ ++ "orr r11, r10, r9, lsl r5;" /*@ factor way and cache number into r11*/ \ ++ "orr r11, r11, r7, lsl r2;" /*@ factor index number into r11*/ \ ++ "mcr p15, 0, r11, c7, c14, 2;" /*@ clean & invalidate by set/way */ \ ++ "subs r9, r9, #1;" /*@ decrement the way */ \ ++ "bge 333b;" /* loop3;" */ \ ++ "subs r7, r7, #1;" /*@ decrement the index */ \ ++ "bge 222b;" /* loop2;" */ \ ++ "444:" /* skip:" */ \ ++ "add r10, r10, #2;" /*@ increment cache number */ \ ++ "cmp r3, r10;" \ ++ "bgt 111b;" /*loop1;" */ \ ++ "555:" /* "finished:" */ \ ++ "mov r10, #0;" /*@ swith back to cache level 0 */ \ ++ "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr */ \ ++ "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \ ++ "ldmfd sp!, {r0-r5, r7, r9-r11};" \ ++ "666:" /* iflush:" */ \ ++ "mov r0, #0x0;" \ ++ "mcr p15, 0, r0, c7, c5, 0;" /* @ invalidate I+BTB */ \ ++ "mcr p15, 0, r0, c7, c10, 4;" /* @ drain WB */ \ ++ : \ ++ : \ ++ : "r0" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++ ++// Disable the data cache ++#define HAL_DCACHE_DISABLE_C1() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ "mrc p15, 0, r1, c1, c0, 0;" \ ++ "bic r1, r1, #0x0004;" /* disable DCache by clearing C bit */ \ ++ /* but not MMU and alignment faults */ \ ++ "mcr p15, 0, r1, c1, c0, 0" \ ++ : \ ++ : \ ++ : "r1" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++ ++// Query the state of the data cache ++#define HAL_DCACHE_IS_ENABLED(_state_) \ ++CYG_MACRO_START \ ++ register int reg; \ ++ asm volatile ( \ ++ "nop; " \ ++ "nop; " \ ++ "nop; " \ ++ "nop; " \ ++ "nop; " \ ++ "mrc p15, 0, %0, c1, c0, 0;" \ ++ : "=r"(reg) \ ++ : \ ++ ); \ ++ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \ ++CYG_MACRO_END ++ ++//----------------------------------------------------------------------------- ++// Global control of Instruction cache ++ ++// Enable the instruction cache ++#define HAL_ICACHE_ENABLE_L1() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ "mrc p15, 0, r1, c1, c0, 0;" \ ++ "orr r1, r1, #0x1000;" \ ++ "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \ ++ /* that MMU and alignment faults */ \ ++ /* are enabled) */ \ ++ "mcr p15, 0, r1, c1, c0, 0" \ ++ : \ ++ : \ ++ : "r1" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++ ++// Query the state of the instruction cache ++#define HAL_ICACHE_IS_ENABLED(_state_) \ ++CYG_MACRO_START \ ++ register cyg_uint32 reg; \ ++ asm volatile ( \ ++ "mrc p15, 0, %0, c1, c0, 0" \ ++ : "=r"(reg) \ ++ : \ ++ ); \ ++ \ ++ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \ ++CYG_MACRO_END ++ ++// Disable the instruction cache ++#define HAL_ICACHE_DISABLE_L1() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ "mrc p15, 0, r1, c1, c0, 0;" \ ++ "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \ ++ "mcr p15, 0, r1, c1, c0, 0;" \ ++ "mov r1, #0;" \ ++ "nop;" /* next few instructions may be via cache */ \ ++ "nop;" \ ++ "nop;" \ ++ "nop;" \ ++ "nop;" \ ++ "nop" \ ++ : \ ++ : \ ++ : "r1" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++ ++// Invalidate the entire cache ++#define HAL_ICACHE_INVALIDATE_ALL_L1() ++#ifdef TODO ++#define HAL_ICACHE_INVALIDATE_ALL_L1() \ ++CYG_MACRO_START \ ++ /* this macro can discard dirty cache lines (N/A for ICache) */ \ ++ asm volatile ( \ ++ "mov r1, #0;" \ ++ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \ ++ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \ ++ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \ ++ "nop;" /* next few instructions may be via cache */ \ ++ "nop;" \ ++ "nop;" \ ++ "nop;" \ ++ "nop;" \ ++ "nop;" \ ++ : \ ++ : \ ++ : "r1" /* Clobber list */ \ ++ ); \ ++CYG_MACRO_END ++#endif ++ ++// Synchronize the contents of the cache with memory. ++// (which includes flushing out pending writes) ++#define HAL_ICACHE_SYNC() ++#ifdef TODO ++#define HAL_ICACHE_SYNC() \ ++CYG_MACRO_START \ ++ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \ ++ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \ ++CYG_MACRO_END ++#endif ++ ++#ifdef L2CC_ENABLED ++// Query the state of the L2 cache ++#define HAL_L2CACHE_IS_ENABLED(_state_) \ ++CYG_MACRO_START \ ++ register int reg; \ ++ asm volatile ( \ ++ "nop; " \ ++ "nop; " \ ++ "nop; " \ ++ "nop; " \ ++ "mrc p15, 0, %0, c1, c0, 1;" \ ++ : "=r"(reg) \ ++ : \ ++ ); \ ++ (_state_) = (0 != (2 & reg)); /* Bit 1 is L2 Cache enable */ \ ++CYG_MACRO_END ++ ++#define HAL_ENABLE_L2() \ ++{ \ ++ asm("mrc 15, 0, r0, c1, c0, 1"); \ ++ asm("orr r0, r0, #0x2"); \ ++ asm("mcr 15, 0, r0, c1, c0, 1"); \ ++} ++ ++#define HAL_DISABLE_L2() \ ++{ \ ++ asm("mrc 15, 0, r0, c1, c0, 1"); \ ++ asm("bic r0, r0, #0x2"); \ ++ asm("mcr 15, 0, r0, c1, c0, 1"); \ ++} ++ ++#else //L2CC_ENABLED ++ ++#define HAL_ENABLE_L2() ++#define HAL_DISABLE_L2() ++#endif //L2CC_ENABLED ++ ++/*********************** Exported macros *******************/ ++ ++#define HAL_DCACHE_ENABLE() { \ ++ HAL_ENABLE_L2(); \ ++ HAL_DCACHE_ENABLE_L1(); \ ++} ++ ++#define HAL_DCACHE_DISABLE() { \ ++ HAL_CACHE_FLUSH_ALL(); \ ++ HAL_DCACHE_DISABLE_C1(); \ ++} ++ ++#define HAL_DCACHE_INVALIDATE_ALL() { \ ++ HAL_CACHE_FLUSH_ALL(); \ ++} ++ ++// not needed ++#define HAL_DCACHE_SYNC() ++ ++#define HAL_ICACHE_INVALIDATE_ALL() { \ ++ HAL_CACHE_FLUSH_ALL(); \ ++} ++ ++#define HAL_ICACHE_DISABLE() { \ ++ HAL_ICACHE_DISABLE_L1(); \ ++} ++ ++#define HAL_ICACHE_ENABLE() { \ ++ HAL_ICACHE_ENABLE_L1(); \ ++} ++ ++#define CYGARC_HAL_MMU_OFF(__paddr__) \ ++ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \ ++ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \ ++ "bic r0, r0, #0x1000;" /* disable ICache */ \ ++ "mcr p15, 0, r0, c1, c0, 0;" /* */ \ ++ "nop;" /* flush i+d-TLBs */ \ ++ "nop;" /* flush i+d-TLBs */ \ ++ "nop;" /* flush i+d-TLBs */ ++ ++#define HAL_MMU_OFF() \ ++CYG_MACRO_START \ ++ asm volatile ( \ ++ CYGARC_HAL_MMU_OFF() \ ++ ); \ ++CYG_MACRO_END ++ ++#endif // ifndef CYGONCE_HAL_CACHE_H ++// End of hal_cache.h +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_diag.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_diag.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_diag.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_diag.h 2010-01-26 17:35:50.012962254 +0000 +@@ -0,0 +1,83 @@ ++#ifndef CYGONCE_HAL_DIAG_H ++#define CYGONCE_HAL_DIAG_H ++ ++/*============================================================================= ++// ++// hal_diag.h ++// ++// HAL Support for Kernel Diagnostic Routines ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//===========================================================================*/ ++ ++#include ++ ++#include ++ ++#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) ++ ++#include ++ ++#define HAL_DIAG_INIT() hal_if_diag_init() ++#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) ++#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) ++ ++#else // everything by steam ++ ++/*---------------------------------------------------------------------------*/ ++/* functions implemented in hal_diag.c */ ++ ++externC void hal_diag_init(void); ++externC void hal_diag_write_char(char c); ++externC void hal_diag_read_char(char *c); ++ ++/*---------------------------------------------------------------------------*/ ++ ++#define HAL_DIAG_INIT() hal_diag_init() ++ ++#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) ++ ++#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) ++ ++#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG ++ ++/*---------------------------------------------------------------------------*/ ++// LED ++ ++externC void hal_diag_led(int n); ++ ++/*---------------------------------------------------------------------------*/ ++/* end of hal_diag.h */ ++#endif /* CYGONCE_HAL_DIAG_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_mm.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_mm.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_mm.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_mm.h 2010-01-26 17:35:50.022963254 +0000 +@@ -0,0 +1,176 @@ ++#ifndef CYGONCE_HAL_MM_H ++#define CYGONCE_HAL_MM_H ++ ++//============================================================================= ++// ++// hal_mm.h ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++// ------------------------------------------------------------------------- ++// MMU initialization: ++// ++// These structures are laid down in memory to define the translation ++// table. ++// ++ ++/* ++ * Translation Table Base Bit Masks ++ */ ++#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 ++ ++/* ++ * Domain Access Control Bit Masks ++ */ ++#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) ++#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) ++#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) ++ ++struct ARM_MMU_FIRST_LEVEL_FAULT { ++ unsigned int id : 2; ++ unsigned int sbz : 30; ++}; ++ ++#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 ++ ++struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { ++ unsigned int id : 2; ++ unsigned int imp : 2; ++ unsigned int domain : 4; ++ unsigned int sbz : 1; ++ unsigned int base_address : 23; ++}; ++ ++#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 ++ ++struct ARM_MMU_FIRST_LEVEL_SECTION { ++ unsigned int id : 2; ++ unsigned int b : 1; ++ unsigned int c : 1; ++ unsigned int imp : 1; ++ unsigned int domain : 4; ++ unsigned int sbz0 : 1; ++ unsigned int ap : 2; ++ unsigned int sbz1 : 8; ++ unsigned int base_address : 12; ++}; ++ ++#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 ++ ++struct ARM_MMU_FIRST_LEVEL_RESERVED { ++ unsigned int id : 2; ++ unsigned int sbz : 30; ++}; ++ ++#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 ++ ++#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ ++ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) ++ ++#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 ++ ++#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ ++ cacheable, bufferable, perm) \ ++ CYG_MACRO_START \ ++ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ ++ \ ++ desc.word = 0; \ ++ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ ++ desc.section.domain = 0; \ ++ desc.section.c = (cacheable); \ ++ desc.section.b = (bufferable); \ ++ desc.section.ap = (perm); \ ++ desc.section.base_address = (actual_base); \ ++ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ ++ = desc.word; \ ++ CYG_MACRO_END ++ ++#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \ ++ { \ ++ int i; int j = abase; int k = vbase; \ ++ for (i = size; i > 0 ; i--,j++,k++) { \ ++ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ ++ } \ ++ } ++ ++union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { ++ unsigned long word; ++ struct ARM_MMU_FIRST_LEVEL_FAULT fault; ++ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; ++ struct ARM_MMU_FIRST_LEVEL_SECTION section; ++ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; ++}; ++ ++#define ARM_UNCACHEABLE 0 ++#define ARM_CACHEABLE 1 ++#define ARM_UNBUFFERABLE 0 ++#define ARM_BUFFERABLE 1 ++ ++#define ARM_ACCESS_PERM_NONE_NONE 0 ++#define ARM_ACCESS_PERM_RO_NONE 0 ++#define ARM_ACCESS_PERM_RO_RO 0 ++#define ARM_ACCESS_PERM_RW_NONE 1 ++#define ARM_ACCESS_PERM_RW_RO 2 ++#define ARM_ACCESS_PERM_RW_RW 3 ++ ++/* ++ * Initialization for the Domain Access Control Register ++ */ ++#define ARM_ACCESS_DACR_DEFAULT ( \ ++ ARM_ACCESS_TYPE_MANAGER(0) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(1) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(2) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(3) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(4) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(5) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(6) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(7) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(8) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(9) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(10) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(11) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(12) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(13) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(14) | \ ++ ARM_ACCESS_TYPE_NO_ACCESS(15) ) ++ ++// ------------------------------------------------------------------------ ++#endif // ifndef CYGONCE_HAL_MM_H ++// End of hal_mm.h ++ ++ ++ ++ ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_soc.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_soc.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_soc.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_soc.h 2010-01-26 17:35:50.022963254 +0000 +@@ -0,0 +1,834 @@ ++//========================================================================== ++// ++// hal_soc.h ++// ++// SoC chip definitions ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// Copyright (C) 2002 Gary Thomas ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================*/ ++ ++#ifndef __HAL_SOC_H__ ++#define __HAL_SOC_H__ ++ ++#ifdef __ASSEMBLER__ ++ ++#define REG8_VAL(a) (a) ++#define REG16_VAL(a) (a) ++#define REG32_VAL(a) (a) ++ ++#define REG8_PTR(a) (a) ++#define REG16_PTR(a) (a) ++#define REG32_PTR(a) (a) ++ ++#else /* __ASSEMBLER__ */ ++ ++extern char HAL_PLATFORM_EXTRA[]; ++#define REG8_VAL(a) ((unsigned char)(a)) ++#define REG16_VAL(a) ((unsigned short)(a)) ++#define REG32_VAL(a) ((unsigned int)(a)) ++ ++#define REG8_PTR(a) ((volatile unsigned char *)(a)) ++#define REG16_PTR(a) ((volatile unsigned short *)(a)) ++#define REG32_PTR(a) ((volatile unsigned int *)(a)) ++#define readb(a) (*(volatile unsigned char *)(a)) ++#define readw(a) (*(volatile unsigned short *)(a)) ++#define readl(a) (*(volatile unsigned int *)(a)) ++#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) ++#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) ++#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) ++ ++#endif /* __ASSEMBLER__ */ ++ ++/* ++ * Default Memory Layout Definitions ++ */ ++ ++/* ++ * UART Chip level Configuration that a user may not have to edit. These ++ * configuration vary depending on how the UART module is integrated with ++ * the ARM core ++ */ ++#define MXC_UART_NR 3 ++/*! ++ * This option is used to set or clear the RXDMUXSEL bit in control reg 3. ++ * Certain platforms need this bit to be set in order to receive Irda data. ++ */ ++#define MXC_UART_IR_RXDMUX 0x0004 ++/*! ++ * This option is used to set or clear the RXDMUXSEL bit in control reg 3. ++ * Certain platforms need this bit to be set in order to receive UART data. ++ */ ++#define MXC_UART_RXDMUX 0x0004 ++ ++/* ++ * IRAM ++ */ ++#define IRAM_BASE_ADDR 0x1FFE2000 /* 96K internal ram */ ++ ++/* ++ * ROM address ++ */ ++#define ROM_BASE_ADDRESS 0x0 ++#define ROM_BASE_ADDRESS_VIRT 0x20000000 ++ ++#define ROM_SI_REV_OFFSET 0x48 ++ ++/* ++ * NFC internal RAM ++ */ ++#define NFC_BASE_ADDR_AXI 0xCFFF0000 ++#define NFC_BASE NFC_BASE_ADDR_AXI ++ ++#define PLATFORM_BASE_ADDR 0x83FA0000 ++#define PLATFORM_ICGC 0x14 ++/* ++ * Graphics Memory of GPU ++ */ ++#define GPU_BASE_ADDR 0x20000000 ++ ++#define TZIC_BASE_ADDR 0x8FFFC000 ++ ++#define DEBUG_BASE_ADDR 0x60000000 ++#define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0) ++#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) ++#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) ++#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) ++#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) ++#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) ++#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) ++#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) ++#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) ++ ++/* ++ * SPBA global module enabled #0 ++ */ ++#define SPBA0_BASE_ADDR 0x70000000 ++ ++#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) ++#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR ++#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) ++#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) ++//eCSPI1 ++#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) ++#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) ++#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) ++#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) ++#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) ++#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) ++#define SLIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) ++#define HSI2C_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) ++#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) ++ ++/*! ++ * defines for SPBA modules ++ */ ++#define SPBA_SDHC1 0x04 ++#define SPBA_SDHC2 0x08 ++#define SPBA_UART3 0x0C ++#define SPBA_CSPI1 0x10 ++#define SPBA_SSI2 0x14 ++#define SPBA_SDHC3 0x20 ++#define SPBA_SDHC4 0x24 ++#define SPBA_SPDIF 0x28 ++#define SPBA_ATA 0x30 ++#define SPBA_SLIM 0x34 ++#define SPBA_HSI2C 0x38 ++#define SPBA_CTRL 0x3C ++ ++ ++/* ++ * AIPS 1 ++ */ ++#define AIPS1_BASE_ADDR 0x73F00000 ++#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR ++#define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) ++#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) ++#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) ++#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) ++#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) ++#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) ++#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) ++#define WDOG_BASE_ADDR WDOG1_BASE_ADDR ++#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) ++#define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) ++#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) ++#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) ++#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) ++#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) ++#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) ++#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) ++#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) ++#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) ++#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) ++#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) ++#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) ++ ++/* ++ * AIPS 2 ++ */ ++#define AIPS2_BASE_ADDR 0x83F00000 ++#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR ++#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) ++#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) ++#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) ++#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) ++#define MAX_BASE_ADDR AHBMAX_BASE_ADDR ++#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) ++#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) ++#define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) ++#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) ++#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) ++// eCSPI2 ++#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) ++#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) ++#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) ++#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) ++#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) ++// actually cspi1 ++#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) ++#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) ++#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) ++#define I2C_BASE_ADDR I2C1_BASE_ADDR ++#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) ++#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) ++#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) ++#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) ++#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) ++#define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000) ++#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) ++#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) ++#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) ++#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) ++#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) ++#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) ++#define SOC_FEC_BASE FEC_BASE_ADDR ++#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) ++#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) ++#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) ++ ++/* ++ * Memory regions and CS ++ */ ++#define GPU_CTRL_BASE_ADDR 0x30000000 ++#define IPU_CTRL_BASE_ADDR 0x40000000 ++#define CSD0_BASE_ADDR 0x90000000 ++#define CSD1_BASE_ADDR 0xA0000000 ++#define CS0_BASE_ADDR 0xB0000000 ++#define CS1_BASE_ADDR 0xB8000000 ++#define CS2_BASE_ADDR 0xC0000000 ++#define CS3_BASE_ADDR 0xC8000000 ++#define CS4_BASE_ADDR 0xCC000000 ++#define CS5_BASE_ADDR 0xCE000000 ++ ++/* ++ * DMA request assignments ++ */ ++#define DMA_REQ_SSI3_TX1 47 ++#define DMA_REQ_SSI3_RX1 46 ++#define DMA_REQ_SPDIF 45 ++#define DMA_REQ_UART3_TX 44 ++#define DMA_REQ_UART3_RX 43 ++#define DMA_REQ_SLIM_B_TX 42 ++#define DMA_REQ_SDHC4 41 ++#define DMA_REQ_SDHC3 40 ++#define DMA_REQ_CSPI_TX 39 ++#define DMA_REQ_CSPI_RX 38 ++#define DMA_REQ_SSI3_TX2 37 ++#define DMA_REQ_IPU 36 ++#define DMA_REQ_SSI3_RX2 35 ++#define DMA_REQ_EPIT2 34 ++#define DMA_REQ_CTI2_1 33 ++#define DMA_REQ_EMI_WR 32 ++#define DMA_REQ_CTI2_0 31 ++#define DMA_REQ_EMI_RD 30 ++#define DMA_REQ_SSI1_TX1 29 ++#define DMA_REQ_SSI1_RX1 28 ++#define DMA_REQ_SSI1_TX2 27 ++#define DMA_REQ_SSI1_RX2 26 ++#define DMA_REQ_SSI2_TX1 25 ++#define DMA_REQ_SSI2_RX1 24 ++#define DMA_REQ_SSI2_TX2 23 ++#define DMA_REQ_SSI2_RX2 22 ++#define DMA_REQ_SDHC2_I2C2 21 ++#define DMA_REQ_SDHC1_I2C1 20 ++#define DMA_REQ_UART1_TX 19 ++#define DMA_REQ_UART1_RX 18 ++#define DMA_REQ_UART2_TX 17 ++#define DMA_REQ_UART2_RX 16 ++#define DMA_REQ_GPU_GPIO1_0 15 ++#define DMA_REQ_GPIO1_1 14 ++#define DMA_REQ_FIRI_TX 13 ++#define DMA_REQ_FIRI_RX 12 ++#define DMA_REQ_HS_I2C_RX 11 ++#define DMA_REQ_HS_I2C_TX 10 ++#define DMA_REQ_CSPI2_TX 9 ++#define DMA_REQ_CSPI2_RX 8 ++#define DMA_REQ_CSPI1_TX 7 ++#define DMA_REQ_CSPI1_RX 6 ++#define DMA_REQ_SLIM_B 5 ++#define DMA_REQ_ATA_TX_END 4 ++#define DMA_REQ_ATA_TX 3 ++#define DMA_REQ_ATA_RX 2 ++#define DMA_REQ_GPC 1 ++#define DMA_REQ_VPU 0 ++ ++/* ++ * Interrupt numbers ++ */ ++#define MXC_INT_BASE 0 ++#define MXC_INT_RESV0 0 ++#define MXC_INT_MMC_SDHC1 1 ++#define MXC_INT_MMC_SDHC2 2 ++#define MXC_INT_MMC_SDHC3 3 ++#define MXC_INT_MMC_SDHC4 4 ++#define MXC_INT_RESV5 5 ++#define MXC_INT_SDMA 6 ++#define MXC_INT_IOMUX 7 ++#define MXC_INT_NFC 8 ++#define MXC_INT_VPU 9 ++#define MXC_INT_IPU_ERR 10 ++#define MXC_INT_IPU_SYN 11 ++#define MXC_INT_GPU 12 ++#define MXC_INT_RESV13 13 ++#define MXC_INT_USB_H1 14 ++#define MXC_INT_EMI 15 ++#define MXC_INT_USB_H2 16 ++#define MXC_INT_USB_H3 17 ++#define MXC_INT_USB_OTG 18 ++#define MXC_INT_SAHARA_H0 19 ++#define MXC_INT_SAHARA_H1 20 ++#define MXC_INT_SCC_SMN 21 ++#define MXC_INT_SCC_STZ 22 ++#define MXC_INT_SCC_SCM 23 ++#define MXC_INT_SRTC_NTZ 24 ++#define MXC_INT_SRTC_TZ 25 ++#define MXC_INT_RTIC 26 ++#define MXC_INT_CSU 27 ++#define MXC_INT_SLIM_B 28 ++#define MXC_INT_SSI1 29 ++#define MXC_INT_SSI2 30 ++#define MXC_INT_UART1 31 ++#define MXC_INT_UART2 32 ++#define MXC_INT_UART3 33 ++#define MXC_INT_RESV34 34 ++#define MXC_INT_RESV35 35 ++#define MXC_INT_CSPI1 36 ++#define MXC_INT_CSPI2 37 ++#define MXC_INT_CSPI 38 ++#define MXC_INT_GPT 39 ++#define MXC_INT_EPIT1 40 ++#define MXC_INT_EPIT2 41 ++#define MXC_INT_GPIO1_INT7 42 ++#define MXC_INT_GPIO1_INT6 43 ++#define MXC_INT_GPIO1_INT5 44 ++#define MXC_INT_GPIO1_INT4 45 ++#define MXC_INT_GPIO1_INT3 46 ++#define MXC_INT_GPIO1_INT2 47 ++#define MXC_INT_GPIO1_INT1 48 ++#define MXC_INT_GPIO1_INT0 49 ++#define MXC_INT_GPIO1_LOW 50 ++#define MXC_INT_GPIO1_HIGH 51 ++#define MXC_INT_GPIO2_LOW 52 ++#define MXC_INT_GPIO2_HIGH 53 ++#define MXC_INT_GPIO3_LOW 54 ++#define MXC_INT_GPIO3_HIGH 55 ++#define MXC_INT_GPIO4_LOW 56 ++#define MXC_INT_GPIO4_HIGH 57 ++#define MXC_INT_WDOG1 58 ++#define MXC_INT_WDOG2 59 ++#define MXC_INT_KPP 60 ++#define MXC_INT_PWM1 61 ++#define MXC_INT_I2C1 62 ++#define MXC_INT_I2C2 63 ++#define MXC_INT_HS_I2C 64 ++#define MXC_INT_RESV65 65 ++#define MXC_INT_RESV66 66 ++#define MXC_INT_SIM_IPB 67 ++#define MXC_INT_SIM_DAT 68 ++#define MXC_INT_IIM 69 ++#define MXC_INT_ATA 70 ++#define MXC_INT_CCM1 71 ++#define MXC_INT_CCM2 72 ++#define MXC_INT_GPC1 73 ++#define MXC_INT_GPC2 74 ++#define MXC_INT_SRC 75 ++#define MXC_INT_NM 76 ++#define MXC_INT_PMU 77 ++#define MXC_INT_CTI_IRQ 78 ++#define MXC_INT_CTI1_TG0 79 ++#define MXC_INT_CTI1_TG1 80 ++#define MXC_INT_MCG_ERR 81 ++#define MXC_INT_MCG_TMR 82 ++#define MXC_INT_MCG_FUNC 83 ++#define MXC_INT_RESV84 84 ++#define MXC_INT_RESV85 85 ++#define MXC_INT_RESV86 86 ++#define MXC_INT_FEC 87 ++#define MXC_INT_OWIRE 88 ++#define MXC_INT_CTI1_TG2 89 ++#define MXC_INT_SJC 90 ++#define MXC_INT_SPDIF 91 ++#define MXC_INT_TVE 92 ++#define MXC_INT_FIFI 93 ++#define MXC_INT_PWM2 94 ++#define MXC_INT_SLIM_EXP 95 ++#define MXC_INT_SSI3 96 ++#define MXC_INT_RESV97 97 ++#define MXC_INT_CTI1_TG3 98 ++#define MXC_INT_SMC_RX 99 ++#define MXC_INT_VPU_IDLE 100 ++#define MXC_INT_RESV101 101 ++#define MXC_INT_GPU_IDLE 102 ++ ++/*! ++ * Number of GPIO port as defined in the IC Spec ++ */ ++#define GPIO_PORT_NUM 4 ++/*! ++ * Number of GPIO pins per port ++ */ ++#define GPIO_NUM_PIN 32 ++ ++/* CCM */ ++#define CLKCTL_CCR 0x00 ++#define CLKCTL_CCDR 0x04 ++#define CLKCTL_CSR 0x08 ++#define CLKCTL_CCSR 0x0C ++#define CLKCTL_CACRR 0x10 ++#define CLKCTL_CBCDR 0x14 ++#define CLKCTL_CBCMR 0x18 ++#define CLKCTL_CSCMR1 0x1C ++#define CLKCTL_CSCMR2 0x20 ++#define CLKCTL_CSCDR1 0x24 ++#define CLKCTL_CS1CDR 0x28 ++#define CLKCTL_CS2CDR 0x2C ++#define CLKCTL_CDCDR 0x30 ++#define CLKCTL_CHSCCDR 0x34 ++#define CLKCTL_CSCDR2 0x38 ++#define CLKCTL_CSCDR3 0x3C ++#define CLKCTL_CSCDR4 0x40 ++#define CLKCTL_CWDR 0x44 ++#define CLKCTL_CDHIPR 0x48 ++#define CLKCTL_CDCR 0x4C ++#define CLKCTL_CTOR 0x50 ++#define CLKCTL_CLPCR 0x54 ++#define CLKCTL_CISR 0x58 ++#define CLKCTL_CIMR 0x5C ++#define CLKCTL_CCOSR 0x60 ++#define CLKCTL_CGPR 0x64 ++#define CLKCTL_CCGR0 0x68 ++#define CLKCTL_CCGR1 0x6C ++#define CLKCTL_CCGR2 0x70 ++#define CLKCTL_CCGR3 0x74 ++#define CLKCTL_CCGR4 0x78 ++#define CLKCTL_CCGR5 0x7C ++#define CLKCTL_CCGR6 0x80 ++#define CLKCTL_CMEOR 0x84 ++ ++#define FREQ_24MHZ 24000000 ++#define FREQ_32768HZ (32768 * 1024) ++#define FREQ_38400HZ (38400 * 1024) ++#define FREQ_32000HZ (32000 * 1024) ++#define PLL_REF_CLK FREQ_24MHZ ++#define CKIH 22579200 ++//#define PLL_REF_CLK FREQ_32768HZ ++//#define PLL_REF_CLK FREQ_32000HZ ++ ++/* WEIM registers */ ++#define CSGCR1 0x00 ++#define CSGCR2 0x04 ++#define CSRCR1 0x08 ++#define CSRCR2 0x0C ++#define CSWCR1 0x10 ++ ++/* M4IF */ ++#define M4IF_FBPM0 0x40 ++#define M4IF_FBPM1 0x44 ++#define M4IF_FIDBP 0x48 ++#define M4IF_MIF4 0x48 ++#define M4IF_FPWC 0x9C ++ ++/* ESDCTL */ ++#define ESDCTL_ESDCTL0 0x00 ++#define ESDCTL_ESDCFG0 0x04 ++#define ESDCTL_ESDCTL1 0x08 ++#define ESDCTL_ESDCFG1 0x0C ++#define ESDCTL_ESDMISC 0x10 ++#define ESDCTL_ESDSCR 0x14 ++#define ESDCTL_ESDCDLY1 0x20 ++#define ESDCTL_ESDCDLY2 0x24 ++#define ESDCTL_ESDCDLY3 0x28 ++#define ESDCTL_ESDCDLY4 0x2C ++#define ESDCTL_ESDCDLY5 0x30 ++#define ESDCTL_ESDCDLYGD 0x34 ++ ++/* DPLL */ ++#define PLL_DP_CTL 0x00 ++#define PLL_DP_CONFIG 0x04 ++#define PLL_DP_OP 0x08 ++#define PLL_DP_MFD 0x0C ++#define PLL_DP_MFN 0x10 ++#define PLL_DP_MFNMINUS 0x14 ++#define PLL_DP_MFNPLUS 0x18 ++#define PLL_DP_HFS_OP 0x1C ++#define PLL_DP_HFS_MFD 0x20 ++#define PLL_DP_HFS_MFN 0x24 ++#define PLL_DP_TOGC 0x28 ++#define PLL_DP_DESTAT 0x2C ++ ++#define CHIP_REV_1_0 0x0 /* PASS 1.0 */ ++#define CHIP_REV_1_1 0x1 /* PASS 1.1 */ ++#define CHIP_REV_2_0 0x2 /* PASS 2.0 */ ++#define CHIP_LATEST CHIP_REV_1_1 ++ ++#define IIM_STAT_OFF 0x00 ++#define IIM_STAT_BUSY (1 << 7) ++#define IIM_STAT_PRGD (1 << 1) ++#define IIM_STAT_SNSD (1 << 0) ++#define IIM_STATM_OFF 0x04 ++#define IIM_ERR_OFF 0x08 ++#define IIM_ERR_PRGE (1 << 7) ++#define IIM_ERR_WPE (1 << 6) ++#define IIM_ERR_OPE (1 << 5) ++#define IIM_ERR_RPE (1 << 4) ++#define IIM_ERR_WLRE (1 << 3) ++#define IIM_ERR_SNSE (1 << 2) ++#define IIM_ERR_PARITYE (1 << 1) ++#define IIM_EMASK_OFF 0x0C ++#define IIM_FCTL_OFF 0x10 ++#define IIM_UA_OFF 0x14 ++#define IIM_LA_OFF 0x18 ++#define IIM_SDAT_OFF 0x1C ++#define IIM_PREV_OFF 0x20 ++#define IIM_SREV_OFF 0x24 ++#define IIM_PREG_P_OFF 0x28 ++#define IIM_SCS0_OFF 0x2C ++#define IIM_SCS1_P_OFF 0x30 ++#define IIM_SCS2_OFF 0x34 ++#define IIM_SCS3_P_OFF 0x38 ++ ++#define IIM_PROD_REV_SH 3 ++#define IIM_PROD_REV_LEN 5 ++#define IIM_SREV_REV_SH 4 ++#define IIM_SREV_REV_LEN 4 ++#define PROD_SIGNATURE_MX51 0x1 ++ ++#define EPIT_BASE_ADDR EPIT1_BASE_ADDR ++#define EPITCR 0x00 ++#define EPITSR 0x04 ++#define EPITLR 0x08 ++#define EPITCMPR 0x0C ++#define EPITCNR 0x10 ++ ++#define GPTCR 0x00 ++#define GPTPR 0x04 ++#define GPTSR 0x08 ++#define GPTIR 0x0C ++#define GPTOCR1 0x10 ++#define GPTOCR2 0x14 ++#define GPTOCR3 0x18 ++#define GPTICR1 0x1C ++#define GPTICR2 0x20 ++#define GPTCNT 0x24 ++ ++/* Assuming 24MHz input clock with doubler ON */ ++/* MFI PDF */ ++#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) ++#define DP_MFD_850 (48 - 1) ++#define DP_MFN_850 41 ++ ++#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) ++#define DP_MFD_800 (3 - 1) ++#define DP_MFN_800 1 ++ ++#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) ++#define DP_MFD_700 (24 - 1) ++#define DP_MFN_700 7 ++ ++#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) ++#define DP_MFD_400 (3 - 1) ++#define DP_MFN_400 1 ++ ++#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) ++#define DP_MFD_532 (24 - 1) ++#define DP_MFN_532 13 ++ ++#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) ++#define DP_MFD_665 (96 - 1) ++#define DP_MFN_665 89 ++ ++#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) ++#define DP_MFD_216 (4 - 1) ++#define DP_MFN_216 3 ++ ++#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51 ++ ++#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID ++#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev ++ ++#define PART_NUMBER_OFFSET (12) ++#define BOARD_VER_OFFSET (8) ++#define MAJOR_NUMBER_OFFSET (4) ++#define MINOR_NUMBER_OFFSET (0) ++ ++/* IOMUX defines used only for Rocky which is using TO 1.0 */ ++#ifndef IMX51_TO_2 ++ ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND (IOMUXC_BASE_ADDR + 0x130) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x144) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x148) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x14C) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x150) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x154) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x158) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x15C) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x160) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x164) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x168) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x16C) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x170) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x174) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x178) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x17C) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x180) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x184) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x188) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x18C) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x190) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x194) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x198) ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x19C) ++ ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x5B0) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x5B4) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x5B8) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x5BC) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x5C0) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x5C4) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x5C8) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x5CC) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x5D0) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x5D4) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x5D8) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x5DC) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x5E0) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x5E4) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x5E8) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x5EC) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x5F0) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x5F4) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x5F8) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x5FC) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x600) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x604) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x608) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x60C) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x610) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x614) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x618) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x61C) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x620) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x624) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x628) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x62C) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x630) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x634) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x638) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x63C) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x640) ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x644) ++ ++#endif ++ ++//#define BARKER_CODE_SWAP_LOC 0x404 ++#define BARKER_CODE_VAL 0xB1 ++#define NFC_V3_0 0x30 ++// This defines the register base for the NAND AXI registers ++#define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00) ++ ++#define NAND_CMD_REG (NAND_REG_BASE + 0x00) ++#define NAND_ADD0_REG (NAND_REG_BASE + 0x04) ++#define NAND_ADD1_REG (NAND_REG_BASE + 0x08) ++#define NAND_ADD2_REG (NAND_REG_BASE + 0x0C) ++#define NAND_ADD3_REG (NAND_REG_BASE + 0x10) ++#define NAND_ADD4_REG (NAND_REG_BASE + 0x14) ++#define NAND_ADD5_REG (NAND_REG_BASE + 0x18) ++#define NAND_ADD6_REG (NAND_REG_BASE + 0x1C) ++#define NAND_ADD7_REG (NAND_REG_BASE + 0x20) ++#define NAND_ADD8_REG (NAND_REG_BASE + 0x24) ++#define NAND_ADD9_REG (NAND_REG_BASE + 0x28) ++#define NAND_ADD10_REG (NAND_REG_BASE + 0x2C) ++#define NAND_ADD11_REG (NAND_REG_BASE + 0x30) ++ ++#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34) ++#define NAND_CONFIGURATION1_NFC_RST (1 << 2) ++#define NAND_CONFIGURATION1_NF_CE (1 << 1) ++#define NAND_CONFIGURATION1_SP_EN (1 << 0) ++ ++#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38) ++ ++#define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C) ++ ++#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40) ++#define NAND_LAUNCH_FCMD (1 << 0) ++#define NAND_LAUNCH_FADD (1 << 1) ++#define NAND_LAUNCH_FDI (1 << 2) ++#define NAND_LAUNCH_AUTO_PROG (1 << 6) ++#define NAND_LAUNCH_AUTO_READ (1 << 7) ++#define NAND_LAUNCH_AUTO_READ_CONT (1 << 8) ++#define NAND_LAUNCH_AUTO_ERASE (1 << 9) ++#define NAND_LAUNCH_COPY_BACK0 (1 << 10) ++#define NAND_LAUNCH_COPY_BACK1 (1 << 11) ++#define NAND_LAUNCH_AUTO_STAT (1 << 12) ++ ++#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00) ++#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04) ++#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08) ++#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C) ++#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10) ++#define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14) ++#define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18) ++#define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C) ++#define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20) ++ ++#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24) ++#define NFC_FLASH_CONFIG2_ECC_EN (1 << 3) ++ ++#define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28) ++ ++#define NFC_IPC_REG (NFC_IP_BASE + 0x2C) ++#define NFC_IPC_INT (1 << 31) ++#define NFC_IPC_AUTO_DONE (1 << 30) ++#define NFC_IPC_LPS (1 << 29) ++#define NFC_IPC_RB_B (1 << 28) ++#define NFC_IPC_CACK (1 << 1) ++#define NFC_IPC_CREQ (1 << 0) ++#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30) ++ ++#define MXC_MMC_BASE_DUMMY 0x00000000 ++ ++#define NAND_FLASH_BOOT 0x10000000 ++#define FROM_NAND_FLASH NAND_FLASH_BOOT ++ ++#define SDRAM_NON_FLASH_BOOT 0x20000000 ++ ++#define MMC_FLASH_BOOT 0x40000000 ++#define FROM_MMC_FLASH MMC_FLASH_BOOT ++ ++#define SPI_NOR_FLASH_BOOT 0x80000000 ++#define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT ++ ++#define IS_BOOTING_FROM_NAND() (0) ++#define IS_BOOTING_FROM_SPI_NOR() (0) ++#define IS_BOOTING_FROM_NOR() (0) ++#define IS_BOOTING_FROM_SDRAM() (0) ++#define IS_BOOTING_FROM_MMC() (0) ++ ++#ifndef MXCFLASH_SELECT_NAND ++#define IS_FIS_FROM_NAND() 0 ++#else ++#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH) ++#endif ++ ++#ifndef MXCFLASH_SELECT_MMC ++#define IS_FIS_FROM_MMC() 0 ++#else ++#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH) ++#endif ++ ++#define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH) ++ ++#define IS_FIS_FROM_NOR() 0 ++ ++/* ++ * This macro is used to get certain bit field from a number ++ */ ++#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1)) ++ ++/* ++ * This macro is used to set certain bit field inside a number ++ */ ++#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh)) ++ ++#define L2CC_ENABLED ++#define UART_WIDTH_32 /* internal UART is 32bit access only */ ++ ++#if !defined(__ASSEMBLER__) ++void cyg_hal_plf_serial_init(void); ++void cyg_hal_plf_serial_stop(void); ++void hal_delay_us(unsigned int usecs); ++#define HAL_DELAY_US(n) hal_delay_us(n) ++extern int _mxc_fis; ++extern unsigned int system_rev; ++ ++enum plls { ++ PLL1, ++ PLL2, ++ PLL3, ++}; ++ ++enum main_clocks { ++ CPU_CLK, ++ AHB_CLK, ++ IPG_CLK, ++ IPG_PER_CLK, ++ DDR_CLK, ++ NFC_CLK, ++ USB_CLK, ++}; ++ ++enum peri_clocks { ++ UART1_BAUD, ++ UART2_BAUD, ++ UART3_BAUD, ++ SSI1_BAUD, ++ SSI2_BAUD, ++ CSI_BAUD, ++ MSTICK1_CLK, ++ MSTICK2_CLK, ++ SPI1_CLK = CSPI1_BASE_ADDR, ++ SPI2_CLK = CSPI2_BASE_ADDR, ++}; ++ ++unsigned int pll_clock(enum plls pll); ++ ++unsigned int get_main_clock(enum main_clocks clk); ++ ++unsigned int get_peri_clock(enum peri_clocks clk); ++ ++#endif //#if !defined(__ASSEMBLER__) ++ ++#endif /* __HAL_SOC_H__ */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_var_ints.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_var_ints.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/hal_var_ints.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/hal_var_ints.h 2010-01-26 17:35:50.022963254 +0000 +@@ -0,0 +1,136 @@ ++#ifndef CYGONCE_HAL_VAR_INTS_H ++#define CYGONCE_HAL_VAR_INTS_H ++//========================================================================== ++// ++// hal_var_ints.h ++// ++// HAL Interrupt and clock support ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include // registers ++ ++#define CYGNUM_HAL_INTERRUPT_GPIO0 0 ++#define CYGNUM_HAL_INTERRUPT_GPIO1 1 ++#define CYGNUM_HAL_INTERRUPT_GPIO2 2 ++#define CYGNUM_HAL_INTERRUPT_GPIO3 3 ++#define CYGNUM_HAL_INTERRUPT_GPIO4 4 ++#define CYGNUM_HAL_INTERRUPT_GPIO5 5 ++#define CYGNUM_HAL_INTERRUPT_GPIO6 6 ++#define CYGNUM_HAL_INTERRUPT_GPIO7 7 ++#define CYGNUM_HAL_INTERRUPT_GPIO8 8 ++#define CYGNUM_HAL_INTERRUPT_GPIO9 9 ++#define CYGNUM_HAL_INTERRUPT_GPIO10 10 ++#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly! ++#define CYGNUM_HAL_INTERRUPT_LCD 12 ++#define CYGNUM_HAL_INTERRUPT_UDC 13 ++#define CYGNUM_HAL_INTERRUPT_UART1 15 ++#define CYGNUM_HAL_INTERRUPT_UART2 16 ++#define CYGNUM_HAL_INTERRUPT_UART3 17 ++#define CYGNUM_HAL_INTERRUPT_UART4 17 ++#define CYGNUM_HAL_INTERRUPT_MCP 18 ++#define CYGNUM_HAL_INTERRUPT_SSP 19 ++#define CYGNUM_HAL_INTERRUPT_TIMER0 26 ++#define CYGNUM_HAL_INTERRUPT_TIMER1 27 ++#define CYGNUM_HAL_INTERRUPT_TIMER2 28 ++#define CYGNUM_HAL_INTERRUPT_TIMER3 29 ++#define CYGNUM_HAL_INTERRUPT_HZ 30 ++#define CYGNUM_HAL_INTERRUPT_ALARM 31 ++ ++// GPIO bits 31..11 can generate interrupts as well, but they all ++// end up clumped into interrupt signal #11. Using the symbols ++// below allow for detection of these separately. ++ ++#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11) ++#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12) ++#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13) ++#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14) ++#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15) ++#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16) ++#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17) ++#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18) ++#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19) ++#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20) ++#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21) ++#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22) ++#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23) ++#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24) ++#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25) ++#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26) ++#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27) ++ ++#define CYGNUM_HAL_INTERRUPT_NONE -1 ++ ++#define CYGNUM_HAL_ISR_MIN 0 ++#define CYGNUM_HAL_ISR_MAX (27+32) ++ ++#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) ++ ++// The vector used by the Real time clock ++#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 ++ ++// The vector used by the Ethernet ++#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0 ++ ++// method for reading clock interrupt latency ++#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY ++externC void hal_clock_latency(cyg_uint32 *); ++# define HAL_CLOCK_LATENCY( _pvalue_ ) \ ++ hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) ++#endif ++ ++//---------------------------------------------------------------------------- ++// Reset. ++#define HAL_PLATFORM_RESET() \ ++ CYG_MACRO_START \ ++ writel(readl(NFC_FLASH_CONFIG3_REG) & ~0x73, NFC_FLASH_CONFIG3_REG); \ ++ *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) { \ ++ /* de-select SS0 of instance: ecspi1. */ \ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x218); \ ++ writel(0x85, IOMUXC_BASE_ADDR + 0x608); \ ++ /* de-select SS1 of instance: ecspi1 */ \ ++ writel(0x3, IOMUXC_BASE_ADDR + 0x21C); \ ++ writel(0x85, IOMUXC_BASE_ADDR + 0x60C); \ ++ } \ ++ /* hang here forever if reset fails */ \ ++ while (1){} \ ++ CYG_MACRO_END ++ ++// Fallback (never really used) ++#define HAL_PLATFORM_RESET_ENTRY 0x00000000 ++ ++#endif // CYGONCE_HAL_VAR_INTS_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/mx51_iomux.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/mx51_iomux.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/mx51_iomux.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/mx51_iomux.h 2010-01-26 17:35:50.042958254 +0000 +@@ -0,0 +1,871 @@ ++/*************************************************************************** ++* ++* MX51_IOMUX.H ++* ++* Macros definations for MX51 IPUv3e IOMUX. ++* ++*************************************************************************** ++* ++* Author(s) : Ray Sun-B17777 ++* Create Date: 2008-11-10 ++* Description : i.MX51 IOMUX defines ++* ++***************************************************************************/ ++ ++#ifndef _MX51_IOMUX_H_ ++#define _MX51_IOMUX_H_ ++ ++#include ++ ++#define GPR_BASE_ADDR (IOMUXC_BASE_ADDR + 0x0) // 0x0 ++#define OBSRV_BASE_ADDR (GPR_BASE_ADDR + 0x8) // 0x8 ++#define SW_MUX_BASE_ADDR (OBSRV_BASE_ADDR + 0x14) // 0x1c ++#define SW_PAD_BASE_ADDR (SW_MUX_BASE_ADDR + 0x3d4) // 0x3f0 ++#define SW_GRP_BASE_ADDR (SW_PAD_BASE_ADDR + 0x42c) // 0x81c ++#define SW_INPUT_PORT_BASE_ADDR (SW_GRP_BASE_ADDR + 0xa8) // 0x8c4 ++#define SELECT_INPUT_BASE_ADDR (SW_INPUT_PORT_BASE_ADDR + 0x0) // 0x8c4 ++ ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 (SW_MUX_BASE_ADDR + 0x0) // 0x1c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 (SW_MUX_BASE_ADDR + 0x4) // 0x20 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 (SW_MUX_BASE_ADDR + 0x8) // 0x24 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 (SW_MUX_BASE_ADDR + 0xc) // 0x28 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 (SW_MUX_BASE_ADDR + 0x10) // 0x2c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 (SW_MUX_BASE_ADDR + 0x14) // 0x30 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 (SW_MUX_BASE_ADDR + 0x18) // 0x34 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 (SW_MUX_BASE_ADDR + 0x1c) // 0x38 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 (SW_MUX_BASE_ADDR + 0x20) // 0x3c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 (SW_MUX_BASE_ADDR + 0x24) // 0x40 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 (SW_MUX_BASE_ADDR + 0x28) // 0x44 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 (SW_MUX_BASE_ADDR + 0x2c) // 0x48 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 (SW_MUX_BASE_ADDR + 0x30) // 0x4c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 (SW_MUX_BASE_ADDR + 0x34) // 0x50 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 (SW_MUX_BASE_ADDR + 0x38) // 0x54 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 (SW_MUX_BASE_ADDR + 0x3c) // 0x58 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 (SW_MUX_BASE_ADDR + 0x40) // 0x5c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 (SW_MUX_BASE_ADDR + 0x44) // 0x60 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 (SW_MUX_BASE_ADDR + 0x48) // 0x64 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 (SW_MUX_BASE_ADDR + 0x4c) // 0x68 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 (SW_MUX_BASE_ADDR + 0x50) // 0x6c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 (SW_MUX_BASE_ADDR + 0x54) // 0x70 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 (SW_MUX_BASE_ADDR + 0x58) // 0x74 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 (SW_MUX_BASE_ADDR + 0x5c) // 0x78 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 (SW_MUX_BASE_ADDR + 0x60) // 0x7c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 (SW_MUX_BASE_ADDR + 0x64) // 0x80 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 (SW_MUX_BASE_ADDR + 0x68) // 0x84 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 (SW_MUX_BASE_ADDR + 0x6c) // 0x88 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 (SW_MUX_BASE_ADDR + 0x70) // 0x8c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 (SW_MUX_BASE_ADDR + 0x74) // 0x90 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 (SW_MUX_BASE_ADDR + 0x78) // 0x94 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 (SW_MUX_BASE_ADDR + 0x7c) // 0x98 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 (SW_MUX_BASE_ADDR + 0x80) // 0x9c ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 (SW_MUX_BASE_ADDR + 0x84) // 0xa0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 (SW_MUX_BASE_ADDR + 0x88) // 0xa4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 (SW_MUX_BASE_ADDR + 0x8c) // 0xa8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 (SW_MUX_BASE_ADDR + 0x90) // 0xac ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 (SW_MUX_BASE_ADDR + 0x94) // 0xb0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 (SW_MUX_BASE_ADDR + 0x98) // 0xb4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 (SW_MUX_BASE_ADDR + 0x9c) // 0xb8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 (SW_MUX_BASE_ADDR + 0xa0) // 0xbc ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 (SW_MUX_BASE_ADDR + 0xa4) // 0xc0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 (SW_MUX_BASE_ADDR + 0xa8) // 0xc4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 (SW_MUX_BASE_ADDR + 0xac) // 0xc8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 (SW_MUX_BASE_ADDR + 0xb0) // 0xcc ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 (SW_MUX_BASE_ADDR + 0xb4) // 0xd0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 (SW_MUX_BASE_ADDR + 0xb8) // 0xd4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 (SW_MUX_BASE_ADDR + 0xbc) // 0xd8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE (SW_MUX_BASE_ADDR + 0xc0) // 0xdc ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 (SW_MUX_BASE_ADDR + 0xc4) // 0xe0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 (SW_MUX_BASE_ADDR + 0xc8) // 0xe4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 (SW_MUX_BASE_ADDR + 0xcc) // 0xe8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 (SW_MUX_BASE_ADDR + 0xd0) // 0xec ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 (SW_MUX_BASE_ADDR + 0xd4) // 0xf0 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 (SW_MUX_BASE_ADDR + 0xd8) // 0xf4 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK (SW_MUX_BASE_ADDR + 0xdc) // 0xf8 ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA (SW_MUX_BASE_ADDR + 0xe0) // 0xfc ++#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE (SW_MUX_BASE_ADDR + 0xe4) // 0x100 ++#define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 (SW_MUX_BASE_ADDR + 0xe8) // 0x104 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (SW_MUX_BASE_ADDR + 0xec) // 0x108 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (SW_MUX_BASE_ADDR + 0xf0) // 0x10c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (SW_MUX_BASE_ADDR + 0xf4) // 0x110 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (SW_MUX_BASE_ADDR + 0xf8) // 0x114 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (SW_MUX_BASE_ADDR + 0xfc) // 0x118 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (SW_MUX_BASE_ADDR + 0x100) // 0x11c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (SW_MUX_BASE_ADDR + 0x104) // 0x120 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (SW_MUX_BASE_ADDR + 0x108) // 0x124 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (SW_MUX_BASE_ADDR + 0x10c) // 0x128 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND (SW_MUX_BASE_ADDR + 0x110) // 0x12c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (SW_MUX_BASE_ADDR + 0x114) // 0x130 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (SW_MUX_BASE_ADDR + 0x118) // 0x134 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (SW_MUX_BASE_ADDR + 0x11c) // 0x138 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (SW_MUX_BASE_ADDR + 0x120) // 0x13c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (SW_MUX_BASE_ADDR + 0x124) // 0x140 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (SW_MUX_BASE_ADDR + 0x128) // 0x144 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (SW_MUX_BASE_ADDR + 0x12c) // 0x148 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (SW_MUX_BASE_ADDR + 0x130) // 0x14c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (SW_MUX_BASE_ADDR + 0x134) // 0x150 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (SW_MUX_BASE_ADDR + 0x138) // 0x154 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (SW_MUX_BASE_ADDR + 0x13c) // 0x158 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (SW_MUX_BASE_ADDR + 0x140) // 0x15c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (SW_MUX_BASE_ADDR + 0x144) // 0x160 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (SW_MUX_BASE_ADDR + 0x148) // 0x164 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (SW_MUX_BASE_ADDR + 0x14c) // 0x168 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (SW_MUX_BASE_ADDR + 0x150) // 0x16c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (SW_MUX_BASE_ADDR + 0x154) // 0x170 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (SW_MUX_BASE_ADDR + 0x158) // 0x174 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (SW_MUX_BASE_ADDR + 0x15c) // 0x178 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (SW_MUX_BASE_ADDR + 0x160) // 0x17c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (SW_MUX_BASE_ADDR + 0x164) // 0x180 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (SW_MUX_BASE_ADDR + 0x168) // 0x184 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (SW_MUX_BASE_ADDR + 0x16c) // 0x188 ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (SW_MUX_BASE_ADDR + 0x170) // 0x18c ++#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (SW_MUX_BASE_ADDR + 0x174) // 0x190 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 (SW_MUX_BASE_ADDR + 0x178) // 0x194 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 (SW_MUX_BASE_ADDR + 0x17c) // 0x198 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 (SW_MUX_BASE_ADDR + 0x180) // 0x19c ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 (SW_MUX_BASE_ADDR + 0x184) // 0x1a0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 (SW_MUX_BASE_ADDR + 0x188) // 0x1a4 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 (SW_MUX_BASE_ADDR + 0x18c) // 0x1a8 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 (SW_MUX_BASE_ADDR + 0x190) // 0x1ac ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 (SW_MUX_BASE_ADDR + 0x194) // 0x1b0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 (SW_MUX_BASE_ADDR + 0x198) // 0x1b4 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 (SW_MUX_BASE_ADDR + 0x19c) // 0x1b8 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 (SW_MUX_BASE_ADDR + 0x1a0) // 0x1bc ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 (SW_MUX_BASE_ADDR + 0x1a4) // 0x1c0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC (SW_MUX_BASE_ADDR + 0x1a8) // 0x1c4 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC (SW_MUX_BASE_ADDR + 0x1ac) // 0x1c8 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 (SW_MUX_BASE_ADDR + 0x1b0) // 0x1cc ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 (SW_MUX_BASE_ADDR + 0x1b4) // 0x1d0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 (SW_MUX_BASE_ADDR + 0x1b8) // 0x1d4 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 (SW_MUX_BASE_ADDR + 0x1bc) // 0x1d8 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 (SW_MUX_BASE_ADDR + 0x1c0) // 0x1dc ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 (SW_MUX_BASE_ADDR + 0x1c4) // 0x1e0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 (SW_MUX_BASE_ADDR + 0x1c8) // 0x1e4 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 (SW_MUX_BASE_ADDR + 0x1cc) // 0x1e8 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC (SW_MUX_BASE_ADDR + 0x1d0) // 0x1ec ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC (SW_MUX_BASE_ADDR + 0x1d4) // 0x1f0 ++#define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK (SW_MUX_BASE_ADDR + 0x1d8) // 0x1f4 ++#define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK (SW_MUX_BASE_ADDR + 0x1dc) // 0x1f8 ++#define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT (SW_MUX_BASE_ADDR + 0x1e0) // 0x1fc ++#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD (SW_MUX_BASE_ADDR + 0x1e4) // 0x200 ++#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD (SW_MUX_BASE_ADDR + 0x1e8) // 0x204 ++#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK (SW_MUX_BASE_ADDR + 0x1ec) // 0x208 ++#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS (SW_MUX_BASE_ADDR + 0x1f0) // 0x20c ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI (SW_MUX_BASE_ADDR + 0x1f4) // 0x210 ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO (SW_MUX_BASE_ADDR + 0x1f8) // 0x214 ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 (SW_MUX_BASE_ADDR + 0x1fc) // 0x218 ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 (SW_MUX_BASE_ADDR + 0x200) // 0x21c ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY (SW_MUX_BASE_ADDR + 0x204) // 0x220 ++#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK (SW_MUX_BASE_ADDR + 0x208) // 0x224 ++#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD (SW_MUX_BASE_ADDR + 0x20c) // 0x228 ++#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD (SW_MUX_BASE_ADDR + 0x210) // 0x22c ++#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS (SW_MUX_BASE_ADDR + 0x214) // 0x230 ++#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS (SW_MUX_BASE_ADDR + 0x218) // 0x234 ++#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD (SW_MUX_BASE_ADDR + 0x21c) // 0x238 ++#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD (SW_MUX_BASE_ADDR + 0x220) // 0x23c ++#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD (SW_MUX_BASE_ADDR + 0x224) // 0x240 ++#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD (SW_MUX_BASE_ADDR + 0x228) // 0x244 ++#define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE (SW_MUX_BASE_ADDR + 0x22c) // 0x248 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 (SW_MUX_BASE_ADDR + 0x230) // 0x24c ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 (SW_MUX_BASE_ADDR + 0x234) // 0x250 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 (SW_MUX_BASE_ADDR + 0x238) // 0x254 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 (SW_MUX_BASE_ADDR + 0x23c) // 0x258 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 (SW_MUX_BASE_ADDR + 0x240) // 0x25c ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 (SW_MUX_BASE_ADDR + 0x244) // 0x260 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 (SW_MUX_BASE_ADDR + 0x248) // 0x264 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 (SW_MUX_BASE_ADDR + 0x24c) // 0x268 ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 (SW_MUX_BASE_ADDR + 0x250) // 0x26c ++#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 (SW_MUX_BASE_ADDR + 0x254) // 0x270 ++#define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B (SW_MUX_BASE_ADDR + 0x258) // 0x274 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK (SW_MUX_BASE_ADDR + 0x25c) // 0x278 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR (SW_MUX_BASE_ADDR + 0x260) // 0x27c ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP (SW_MUX_BASE_ADDR + 0x264) // 0x280 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT (SW_MUX_BASE_ADDR + 0x268) // 0x284 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 (SW_MUX_BASE_ADDR + 0x26c) // 0x288 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 (SW_MUX_BASE_ADDR + 0x270) // 0x28c ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 (SW_MUX_BASE_ADDR + 0x274) // 0x290 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 (SW_MUX_BASE_ADDR + 0x278) // 0x294 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 (SW_MUX_BASE_ADDR + 0x27c) // 0x298 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 (SW_MUX_BASE_ADDR + 0x280) // 0x29c ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 (SW_MUX_BASE_ADDR + 0x284) // 0x2a0 ++#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 (SW_MUX_BASE_ADDR + 0x288) // 0x2a4 ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 (SW_MUX_BASE_ADDR + 0x28c) // 0x2a8 ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 (SW_MUX_BASE_ADDR + 0x290) // 0x2ac ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 (SW_MUX_BASE_ADDR + 0x294) // 0x2b0 ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS (SW_MUX_BASE_ADDR + 0x298) // 0x2b4 ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS (SW_MUX_BASE_ADDR + 0x29c) // 0x2b8 ++#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN (SW_MUX_BASE_ADDR + 0x2a0) // 0x2bc ++#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO (SW_MUX_BASE_ADDR + 0x2a4) // 0x2c0 ++#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK (SW_MUX_BASE_ADDR + 0x2a8) // 0x2c4 ++#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS (SW_MUX_BASE_ADDR + 0x2ac) // 0x2c8 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 (SW_MUX_BASE_ADDR + 0x2b0) // 0x2cc ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 (SW_MUX_BASE_ADDR + 0x2b4) // 0x2d0 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 (SW_MUX_BASE_ADDR + 0x2b8) // 0x2d4 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 (SW_MUX_BASE_ADDR + 0x2bc) // 0x2d8 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 (SW_MUX_BASE_ADDR + 0x2c0) // 0x2dc ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 (SW_MUX_BASE_ADDR + 0x2c4) // 0x2e0 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 (SW_MUX_BASE_ADDR + 0x2c8) // 0x2e4 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 (SW_MUX_BASE_ADDR + 0x2cc) // 0x2e8 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 (SW_MUX_BASE_ADDR + 0x2d0) // 0x2ec ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 (SW_MUX_BASE_ADDR + 0x2d4) // 0x2f0 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 (SW_MUX_BASE_ADDR + 0x2d8) // 0x2f4 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 (SW_MUX_BASE_ADDR + 0x2dc) // 0x2f8 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 (SW_MUX_BASE_ADDR + 0x2e0) // 0x2fc ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 (SW_MUX_BASE_ADDR + 0x2e4) // 0x300 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 (SW_MUX_BASE_ADDR + 0x2e8) // 0x304 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 (SW_MUX_BASE_ADDR + 0x2ec) // 0x308 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 (SW_MUX_BASE_ADDR + 0x2f0) // 0x30c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 (SW_MUX_BASE_ADDR + 0x2f4) // 0x310 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 (SW_MUX_BASE_ADDR + 0x2f8) // 0x314 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 (SW_MUX_BASE_ADDR + 0x2fc) // 0x318 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 (SW_MUX_BASE_ADDR + 0x300) // 0x31c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 (SW_MUX_BASE_ADDR + 0x304) // 0x320 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 (SW_MUX_BASE_ADDR + 0x308) // 0x324 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 (SW_MUX_BASE_ADDR + 0x30c) // 0x328 ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 (SW_MUX_BASE_ADDR + 0x310) // 0x32c ++#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 (SW_MUX_BASE_ADDR + 0x314) // 0x330 ++#define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 (SW_MUX_BASE_ADDR + 0x318) // 0x334 ++#define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 (SW_MUX_BASE_ADDR + 0x31c) // 0x338 ++#define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 (SW_MUX_BASE_ADDR + 0x320) // 0x33c ++#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 (SW_MUX_BASE_ADDR + 0x324) // 0x340 ++#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 (SW_MUX_BASE_ADDR + 0x328) // 0x344 ++#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 (SW_MUX_BASE_ADDR + 0x32c) // 0x348 ++#define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK (SW_MUX_BASE_ADDR + 0x330) // 0x34c ++#define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 (SW_MUX_BASE_ADDR + 0x334) // 0x350 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 (SW_MUX_BASE_ADDR + 0x338) // 0x354 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 (SW_MUX_BASE_ADDR + 0x33c) // 0x358 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 (SW_MUX_BASE_ADDR + 0x340) // 0x35c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 (SW_MUX_BASE_ADDR + 0x344) // 0x360 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 (SW_MUX_BASE_ADDR + 0x348) // 0x364 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 (SW_MUX_BASE_ADDR + 0x34c) // 0x368 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 (SW_MUX_BASE_ADDR + 0x350) // 0x36c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 (SW_MUX_BASE_ADDR + 0x354) // 0x370 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 (SW_MUX_BASE_ADDR + 0x358) // 0x374 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 (SW_MUX_BASE_ADDR + 0x35c) // 0x378 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 (SW_MUX_BASE_ADDR + 0x360) // 0x37c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 (SW_MUX_BASE_ADDR + 0x364) // 0x380 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 (SW_MUX_BASE_ADDR + 0x368) // 0x384 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 (SW_MUX_BASE_ADDR + 0x36c) // 0x388 ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 (SW_MUX_BASE_ADDR + 0x370) // 0x38c ++#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 (SW_MUX_BASE_ADDR + 0x374) // 0x390 ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD (SW_MUX_BASE_ADDR + 0x378) // 0x394 ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK (SW_MUX_BASE_ADDR + 0x37c) // 0x398 ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 (SW_MUX_BASE_ADDR + 0x380) // 0x39c ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 (SW_MUX_BASE_ADDR + 0x384) // 0x3a0 ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 (SW_MUX_BASE_ADDR + 0x388) // 0x3a4 ++#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 (SW_MUX_BASE_ADDR + 0x38c) // 0x3a8 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 (SW_MUX_BASE_ADDR + 0x390) // 0x3ac ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 (SW_MUX_BASE_ADDR + 0x394) // 0x3b0 ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD (SW_MUX_BASE_ADDR + 0x398) // 0x3b4 ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK (SW_MUX_BASE_ADDR + 0x39c) // 0x3b8 ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 (SW_MUX_BASE_ADDR + 0x3a0) // 0x3bc ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 (SW_MUX_BASE_ADDR + 0x3a4) // 0x3c0 ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 (SW_MUX_BASE_ADDR + 0x3a8) // 0x3c4 ++#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 (SW_MUX_BASE_ADDR + 0x3ac) // 0x3c8 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 (SW_MUX_BASE_ADDR + 0x3b0) // 0x3cc ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 (SW_MUX_BASE_ADDR + 0x3b4) // 0x3d0 ++#define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ (SW_MUX_BASE_ADDR + 0x3b8) // 0x3d4 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 (SW_MUX_BASE_ADDR + 0x3bc) // 0x3d8 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 (SW_MUX_BASE_ADDR + 0x3c0) // 0x3dc ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 (SW_MUX_BASE_ADDR + 0x3c4) // 0x3e0 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 (SW_MUX_BASE_ADDR + 0x3c8) // 0x3e4 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 (SW_MUX_BASE_ADDR + 0x3cc) // 0x3e8 ++#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 (SW_MUX_BASE_ADDR + 0x3d0) // 0x3ec ++ ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 (SW_PAD_BASE_ADDR + 0x0) // 0x3f0 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 (SW_PAD_BASE_ADDR + 0x4) // 0x3f4 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 (SW_PAD_BASE_ADDR + 0x8) // 0x3f8 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 (SW_PAD_BASE_ADDR + 0xc) // 0x3fc ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 (SW_PAD_BASE_ADDR + 0x10) // 0x400 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 (SW_PAD_BASE_ADDR + 0x14) // 0x404 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 (SW_PAD_BASE_ADDR + 0x18) // 0x408 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 (SW_PAD_BASE_ADDR + 0x1c) // 0x40c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 (SW_PAD_BASE_ADDR + 0x20) // 0x410 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 (SW_PAD_BASE_ADDR + 0x24) // 0x414 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 (SW_PAD_BASE_ADDR + 0x28) // 0x418 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 (SW_PAD_BASE_ADDR + 0x2c) // 0x41c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 (SW_PAD_BASE_ADDR + 0x30) // 0x420 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 (SW_PAD_BASE_ADDR + 0x34) // 0x424 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 (SW_PAD_BASE_ADDR + 0x38) // 0x428 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 (SW_PAD_BASE_ADDR + 0x3c) // 0x42c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 (SW_PAD_BASE_ADDR + 0x40) // 0x430 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 (SW_PAD_BASE_ADDR + 0x44) // 0x434 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 (SW_PAD_BASE_ADDR + 0x48) // 0x438 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 (SW_PAD_BASE_ADDR + 0x4c) // 0x43c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 (SW_PAD_BASE_ADDR + 0x50) // 0x440 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 (SW_PAD_BASE_ADDR + 0x54) // 0x444 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 (SW_PAD_BASE_ADDR + 0x58) // 0x448 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 (SW_PAD_BASE_ADDR + 0x5c) // 0x44c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 (SW_PAD_BASE_ADDR + 0x60) // 0x450 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 (SW_PAD_BASE_ADDR + 0x64) // 0x454 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 (SW_PAD_BASE_ADDR + 0x68) // 0x458 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 (SW_PAD_BASE_ADDR + 0x6c) // 0x45c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 (SW_PAD_BASE_ADDR + 0x70) // 0x460 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 (SW_PAD_BASE_ADDR + 0x74) // 0x464 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 (SW_PAD_BASE_ADDR + 0x78) // 0x468 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 (SW_PAD_BASE_ADDR + 0x7c) // 0x46c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE (SW_PAD_BASE_ADDR + 0x80) // 0x470 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 (SW_PAD_BASE_ADDR + 0x84) // 0x474 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 (SW_PAD_BASE_ADDR + 0x88) // 0x478 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 (SW_PAD_BASE_ADDR + 0x8c) // 0x47c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 (SW_PAD_BASE_ADDR + 0x90) // 0x480 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 (SW_PAD_BASE_ADDR + 0x94) // 0x484 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 (SW_PAD_BASE_ADDR + 0x98) // 0x488 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK (SW_PAD_BASE_ADDR + 0x9c) // 0x48c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT (SW_PAD_BASE_ADDR + 0xa0) // 0x490 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA (SW_PAD_BASE_ADDR + 0xa4) // 0x494 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK (SW_PAD_BASE_ADDR + 0xa8) // 0x498 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW (SW_PAD_BASE_ADDR + 0xac) // 0x49c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE (SW_PAD_BASE_ADDR + 0xb0) // 0x4a0 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS (SW_PAD_BASE_ADDR + 0xb4) // 0x4a4 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS (SW_PAD_BASE_ADDR + 0xb8) // 0x4a8 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE (SW_PAD_BASE_ADDR + 0xbc) // 0x4ac ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 (SW_PAD_BASE_ADDR + 0xc0) // 0x4b0 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 (SW_PAD_BASE_ADDR + 0xc4) // 0x4b4 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK (SW_PAD_BASE_ADDR + 0xc8) // 0x4b8 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 (SW_PAD_BASE_ADDR + 0xcc) // 0x4bc ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 (SW_PAD_BASE_ADDR + 0xd0) // 0x4c0 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 (SW_PAD_BASE_ADDR + 0xd4) // 0x4c4 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 (SW_PAD_BASE_ADDR + 0xd8) // 0x4c8 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 (SW_PAD_BASE_ADDR + 0xdc) // 0x4cc ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 (SW_PAD_BASE_ADDR + 0xe0) // 0x4d0 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 (SW_PAD_BASE_ADDR + 0xe4) // 0x4d4 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 (SW_PAD_BASE_ADDR + 0xe8) // 0x4d8 ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 (SW_PAD_BASE_ADDR + 0xec) // 0x4dc ++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 (SW_PAD_BASE_ADDR + 0xf0) // 0x4e0 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (SW_PAD_BASE_ADDR + 0xf4) // 0x4e4 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (SW_PAD_BASE_ADDR + 0xf8) // 0x4e8 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (SW_PAD_BASE_ADDR + 0xfc) // 0x4ec ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (SW_PAD_BASE_ADDR + 0x100) // 0x4f0 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (SW_PAD_BASE_ADDR + 0x104) // 0x4f4 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (SW_PAD_BASE_ADDR + 0x108) // 0x4f8 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (SW_PAD_BASE_ADDR + 0x10c) // 0x4fc ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (SW_PAD_BASE_ADDR + 0x110) // 0x500 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (SW_PAD_BASE_ADDR + 0x114) // 0x504 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 (SW_PAD_BASE_ADDR + 0x118) // 0x508 ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 (SW_PAD_BASE_ADDR + 0x11c) // 0x50c ++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 (SW_PAD_BASE_ADDR + 0x120) // 0x510 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND (SW_PAD_BASE_ADDR + 0x124) // 0x514 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (SW_PAD_BASE_ADDR + 0x128) // 0x518 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (SW_PAD_BASE_ADDR + 0x12c) // 0x51c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (SW_PAD_BASE_ADDR + 0x130) // 0x520 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (SW_PAD_BASE_ADDR + 0x134) // 0x524 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (SW_PAD_BASE_ADDR + 0x138) // 0x528 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (SW_PAD_BASE_ADDR + 0x13c) // 0x52c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (SW_PAD_BASE_ADDR + 0x140) // 0x530 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (SW_PAD_BASE_ADDR + 0x144) // 0x534 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (SW_PAD_BASE_ADDR + 0x148) // 0x538 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (SW_PAD_BASE_ADDR + 0x14c) // 0x53c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (SW_PAD_BASE_ADDR + 0x150) // 0x540 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (SW_PAD_BASE_ADDR + 0x154) // 0x544 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (SW_PAD_BASE_ADDR + 0x158) // 0x548 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (SW_PAD_BASE_ADDR + 0x15c) // 0x54c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (SW_PAD_BASE_ADDR + 0x160) // 0x550 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (SW_PAD_BASE_ADDR + 0x164) // 0x554 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (SW_PAD_BASE_ADDR + 0x168) // 0x558 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (SW_PAD_BASE_ADDR + 0x16c) // 0x55c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (SW_PAD_BASE_ADDR + 0x170) // 0x560 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (SW_PAD_BASE_ADDR + 0x174) // 0x564 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (SW_PAD_BASE_ADDR + 0x178) // 0x568 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (SW_PAD_BASE_ADDR + 0x17c) // 0x56c ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (SW_PAD_BASE_ADDR + 0x180) // 0x570 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (SW_PAD_BASE_ADDR + 0x184) // 0x574 ++#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (SW_PAD_BASE_ADDR + 0x188) // 0x578 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 (SW_PAD_BASE_ADDR + 0x18c) // 0x57c ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 (SW_PAD_BASE_ADDR + 0x190) // 0x580 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 (SW_PAD_BASE_ADDR + 0x194) // 0x584 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 (SW_PAD_BASE_ADDR + 0x198) // 0x588 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 (SW_PAD_BASE_ADDR + 0x19c) // 0x58c ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 (SW_PAD_BASE_ADDR + 0x1a0) // 0x590 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 (SW_PAD_BASE_ADDR + 0x1a4) // 0x594 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 (SW_PAD_BASE_ADDR + 0x1a8) // 0x598 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 (SW_PAD_BASE_ADDR + 0x1ac) // 0x59c ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 (SW_PAD_BASE_ADDR + 0x1b0) // 0x5a0 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 (SW_PAD_BASE_ADDR + 0x1b4) // 0x5a4 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 (SW_PAD_BASE_ADDR + 0x1b8) // 0x5a8 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC (SW_PAD_BASE_ADDR + 0x1bc) // 0x5ac ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC (SW_PAD_BASE_ADDR + 0x1c0) // 0x5b0 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK (SW_PAD_BASE_ADDR + 0x1c4) // 0x5b4 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK (SW_PAD_BASE_ADDR + 0x1c8) // 0x5b8 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 (SW_PAD_BASE_ADDR + 0x1cc) // 0x5bc ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 (SW_PAD_BASE_ADDR + 0x1d0) // 0x5c0 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 (SW_PAD_BASE_ADDR + 0x1d4) // 0x5c4 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 (SW_PAD_BASE_ADDR + 0x1d8) // 0x5c8 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 (SW_PAD_BASE_ADDR + 0x1dc) // 0x5cc ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 (SW_PAD_BASE_ADDR + 0x1e0) // 0x5d0 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 (SW_PAD_BASE_ADDR + 0x1e4) // 0x5d4 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 (SW_PAD_BASE_ADDR + 0x1e8) // 0x5d8 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC (SW_PAD_BASE_ADDR + 0x1ec) // 0x5dc ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC (SW_PAD_BASE_ADDR + 0x1f0) // 0x5e0 ++#define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK (SW_PAD_BASE_ADDR + 0x1f4) // 0x5e4 ++#define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK (SW_PAD_BASE_ADDR + 0x1f8) // 0x5e8 ++#define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT (SW_PAD_BASE_ADDR + 0x1fc) // 0x5ec ++#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD (SW_PAD_BASE_ADDR + 0x200) // 0x5f0 ++#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD (SW_PAD_BASE_ADDR + 0x204) // 0x5f4 ++#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK (SW_PAD_BASE_ADDR + 0x208) // 0x5f8 ++#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS (SW_PAD_BASE_ADDR + 0x20c) // 0x5fc ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI (SW_PAD_BASE_ADDR + 0x210) // 0x600 ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO (SW_PAD_BASE_ADDR + 0x214) // 0x604 ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 (SW_PAD_BASE_ADDR + 0x218) // 0x608 ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 (SW_PAD_BASE_ADDR + 0x21c) // 0x60c ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY (SW_PAD_BASE_ADDR + 0x220) // 0x610 ++#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK (SW_PAD_BASE_ADDR + 0x224) // 0x614 ++#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD (SW_PAD_BASE_ADDR + 0x228) // 0x618 ++#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD (SW_PAD_BASE_ADDR + 0x22c) // 0x61c ++#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS (SW_PAD_BASE_ADDR + 0x230) // 0x620 ++#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS (SW_PAD_BASE_ADDR + 0x234) // 0x624 ++#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD (SW_PAD_BASE_ADDR + 0x238) // 0x628 ++#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD (SW_PAD_BASE_ADDR + 0x23c) // 0x62c ++#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD (SW_PAD_BASE_ADDR + 0x240) // 0x630 ++#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD (SW_PAD_BASE_ADDR + 0x244) // 0x634 ++#define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE (SW_PAD_BASE_ADDR + 0x248) // 0x638 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 (SW_PAD_BASE_ADDR + 0x24c) // 0x63c ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 (SW_PAD_BASE_ADDR + 0x250) // 0x640 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 (SW_PAD_BASE_ADDR + 0x254) // 0x644 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 (SW_PAD_BASE_ADDR + 0x258) // 0x648 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 (SW_PAD_BASE_ADDR + 0x25c) // 0x64c ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 (SW_PAD_BASE_ADDR + 0x260) // 0x650 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 (SW_PAD_BASE_ADDR + 0x264) // 0x654 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 (SW_PAD_BASE_ADDR + 0x268) // 0x658 ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 (SW_PAD_BASE_ADDR + 0x26c) // 0x65c ++#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 (SW_PAD_BASE_ADDR + 0x270) // 0x660 ++#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK (SW_PAD_BASE_ADDR + 0x274) // 0x664 ++#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS (SW_PAD_BASE_ADDR + 0x278) // 0x668 ++#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI (SW_PAD_BASE_ADDR + 0x27c) // 0x66c ++#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB (SW_PAD_BASE_ADDR + 0x280) // 0x670 ++#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD (SW_PAD_BASE_ADDR + 0x284) // 0x674 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK (SW_PAD_BASE_ADDR + 0x288) // 0x678 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR (SW_PAD_BASE_ADDR + 0x28c) // 0x67c ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP (SW_PAD_BASE_ADDR + 0x290) // 0x680 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT (SW_PAD_BASE_ADDR + 0x294) // 0x684 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 (SW_PAD_BASE_ADDR + 0x298) // 0x688 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 (SW_PAD_BASE_ADDR + 0x29c) // 0x68c ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 (SW_PAD_BASE_ADDR + 0x2a0) // 0x690 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 (SW_PAD_BASE_ADDR + 0x2a4) // 0x694 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 (SW_PAD_BASE_ADDR + 0x2a8) // 0x698 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 (SW_PAD_BASE_ADDR + 0x2ac) // 0x69c ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 (SW_PAD_BASE_ADDR + 0x2b0) // 0x6a0 ++#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 (SW_PAD_BASE_ADDR + 0x2b4) // 0x6a4 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 (SW_PAD_BASE_ADDR + 0x2b8) // 0x6a8 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 (SW_PAD_BASE_ADDR + 0x2bc) // 0x6ac ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 (SW_PAD_BASE_ADDR + 0x2c0) // 0x6b0 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS (SW_PAD_BASE_ADDR + 0x2c4) // 0x6b4 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS (SW_PAD_BASE_ADDR + 0x2c8) // 0x6b8 ++#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN (SW_PAD_BASE_ADDR + 0x2cc) // 0x6bc ++#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO (SW_PAD_BASE_ADDR + 0x2d0) // 0x6c0 ++#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK (SW_PAD_BASE_ADDR + 0x2d4) // 0x6c4 ++#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS (SW_PAD_BASE_ADDR + 0x2d8) // 0x6c8 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 (SW_PAD_BASE_ADDR + 0x2dc) // 0x6cc ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 (SW_PAD_BASE_ADDR + 0x2e0) // 0x6d0 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 (SW_PAD_BASE_ADDR + 0x2e4) // 0x6d4 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 (SW_PAD_BASE_ADDR + 0x2e8) // 0x6d8 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 (SW_PAD_BASE_ADDR + 0x2ec) // 0x6dc ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 (SW_PAD_BASE_ADDR + 0x2f0) // 0x6e0 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 (SW_PAD_BASE_ADDR + 0x2f4) // 0x6e4 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 (SW_PAD_BASE_ADDR + 0x2f8) // 0x6e8 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 (SW_PAD_BASE_ADDR + 0x2fc) // 0x6ec ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 (SW_PAD_BASE_ADDR + 0x300) // 0x6f0 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 (SW_PAD_BASE_ADDR + 0x304) // 0x6f4 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 (SW_PAD_BASE_ADDR + 0x308) // 0x6f8 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 (SW_PAD_BASE_ADDR + 0x30c) // 0x6fc ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 (SW_PAD_BASE_ADDR + 0x310) // 0x700 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 (SW_PAD_BASE_ADDR + 0x314) // 0x704 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 (SW_PAD_BASE_ADDR + 0x318) // 0x708 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 (SW_PAD_BASE_ADDR + 0x31c) // 0x70c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 (SW_PAD_BASE_ADDR + 0x320) // 0x710 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 (SW_PAD_BASE_ADDR + 0x324) // 0x714 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 (SW_PAD_BASE_ADDR + 0x328) // 0x718 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 (SW_PAD_BASE_ADDR + 0x32c) // 0x71c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 (SW_PAD_BASE_ADDR + 0x330) // 0x720 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 (SW_PAD_BASE_ADDR + 0x334) // 0x724 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 (SW_PAD_BASE_ADDR + 0x338) // 0x728 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 (SW_PAD_BASE_ADDR + 0x33c) // 0x72c ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK (SW_PAD_BASE_ADDR + 0x340) // 0x730 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 (SW_PAD_BASE_ADDR + 0x344) // 0x734 ++#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 (SW_PAD_BASE_ADDR + 0x348) // 0x738 ++#define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 (SW_PAD_BASE_ADDR + 0x34c) // 0x73c ++#define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 (SW_PAD_BASE_ADDR + 0x350) // 0x740 ++#define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 (SW_PAD_BASE_ADDR + 0x354) // 0x744 ++#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 (SW_PAD_BASE_ADDR + 0x358) // 0x748 ++#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 (SW_PAD_BASE_ADDR + 0x35c) // 0x74c ++#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 (SW_PAD_BASE_ADDR + 0x360) // 0x750 ++#define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK (SW_PAD_BASE_ADDR + 0x364) // 0x754 ++#define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 (SW_PAD_BASE_ADDR + 0x368) // 0x758 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 (SW_PAD_BASE_ADDR + 0x36c) // 0x75c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 (SW_PAD_BASE_ADDR + 0x370) // 0x760 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 (SW_PAD_BASE_ADDR + 0x374) // 0x764 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 (SW_PAD_BASE_ADDR + 0x378) // 0x768 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 (SW_PAD_BASE_ADDR + 0x37c) // 0x76c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 (SW_PAD_BASE_ADDR + 0x380) // 0x770 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 (SW_PAD_BASE_ADDR + 0x384) // 0x774 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 (SW_PAD_BASE_ADDR + 0x388) // 0x778 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 (SW_PAD_BASE_ADDR + 0x38c) // 0x77c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 (SW_PAD_BASE_ADDR + 0x390) // 0x780 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 (SW_PAD_BASE_ADDR + 0x394) // 0x784 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 (SW_PAD_BASE_ADDR + 0x398) // 0x788 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 (SW_PAD_BASE_ADDR + 0x39c) // 0x78c ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 (SW_PAD_BASE_ADDR + 0x3a0) // 0x790 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 (SW_PAD_BASE_ADDR + 0x3a4) // 0x794 ++#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 (SW_PAD_BASE_ADDR + 0x3a8) // 0x798 ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD (SW_PAD_BASE_ADDR + 0x3ac) // 0x79c ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK (SW_PAD_BASE_ADDR + 0x3b0) // 0x7a0 ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 (SW_PAD_BASE_ADDR + 0x3b4) // 0x7a4 ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 (SW_PAD_BASE_ADDR + 0x3b8) // 0x7a8 ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 (SW_PAD_BASE_ADDR + 0x3bc) // 0x7ac ++#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 (SW_PAD_BASE_ADDR + 0x3c0) // 0x7b0 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 (SW_PAD_BASE_ADDR + 0x3c4) // 0x7b4 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 (SW_PAD_BASE_ADDR + 0x3c8) // 0x7b8 ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD (SW_PAD_BASE_ADDR + 0x3cc) // 0x7bc ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK (SW_PAD_BASE_ADDR + 0x3d0) // 0x7c0 ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 (SW_PAD_BASE_ADDR + 0x3d4) // 0x7c4 ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 (SW_PAD_BASE_ADDR + 0x3d8) // 0x7c8 ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 (SW_PAD_BASE_ADDR + 0x3dc) // 0x7cc ++#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 (SW_PAD_BASE_ADDR + 0x3e0) // 0x7d0 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 (SW_PAD_BASE_ADDR + 0x3e4) // 0x7d4 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 (SW_PAD_BASE_ADDR + 0x3e8) // 0x7d8 ++#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B (SW_PAD_BASE_ADDR + 0x3ec) // 0x7dc ++#define IOMUXC_SW_PAD_CTL_PAD_POR_B (SW_PAD_BASE_ADDR + 0x3f0) // 0x7e0 ++#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 (SW_PAD_BASE_ADDR + 0x3f4) // 0x7e4 ++#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 (SW_PAD_BASE_ADDR + 0x3f8) // 0x7e8 ++#define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY (SW_PAD_BASE_ADDR + 0x3fc) // 0x7ec ++#define IOMUXC_SW_PAD_CTL_PAD_CKIL (SW_PAD_BASE_ADDR + 0x400) // 0x7f0 ++#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ (SW_PAD_BASE_ADDR + 0x404) // 0x7f4 ++#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ (SW_PAD_BASE_ADDR + 0x408) // 0x7f8 ++#define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ (SW_PAD_BASE_ADDR + 0x40c) // 0x7fc ++#define IOMUXC_SW_PAD_CTL_PAD_CLK_SS (SW_PAD_BASE_ADDR + 0x410) // 0x800 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 (SW_PAD_BASE_ADDR + 0x414) // 0x804 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 (SW_PAD_BASE_ADDR + 0x418) // 0x808 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 (SW_PAD_BASE_ADDR + 0x41c) // 0x80c ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 (SW_PAD_BASE_ADDR + 0x420) // 0x810 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 (SW_PAD_BASE_ADDR + 0x424) // 0x814 ++#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 (SW_PAD_BASE_ADDR + 0x428) // 0x818 ++ ++#define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 (SW_GRP_BASE_ADDR + 0x0) // 0x81c ++#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS (SW_GRP_BASE_ADDR + 0x4) // 0x820 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 (SW_GRP_BASE_ADDR + 0x8) // 0x824 ++#define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 (SW_GRP_BASE_ADDR + 0xc) // 0x828 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 (SW_GRP_BASE_ADDR + 0x10) // 0x82c ++#define IOMUXC_SW_PAD_CTL_GRP_INDDR (SW_GRP_BASE_ADDR + 0x14) // 0x830 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 (SW_GRP_BASE_ADDR + 0x18) // 0x834 ++#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR (SW_GRP_BASE_ADDR + 0x1c) // 0x838 ++#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 (SW_GRP_BASE_ADDR + 0x20) // 0x83c ++#define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 (SW_GRP_BASE_ADDR + 0x24) // 0x840 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 (SW_GRP_BASE_ADDR + 0x28) // 0x844 ++#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 (SW_GRP_BASE_ADDR + 0x2c) // 0x848 ++#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS (SW_GRP_BASE_ADDR + 0x30) // 0x84c ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 (SW_GRP_BASE_ADDR + 0x34) // 0x850 ++#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 (SW_GRP_BASE_ADDR + 0x38) // 0x854 ++#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 (SW_GRP_BASE_ADDR + 0x3c) // 0x858 ++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 (SW_GRP_BASE_ADDR + 0x40) // 0x85c ++#define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 (SW_GRP_BASE_ADDR + 0x44) // 0x860 ++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 (SW_GRP_BASE_ADDR + 0x48) // 0x864 ++#define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 (SW_GRP_BASE_ADDR + 0x4c) // 0x868 ++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 (SW_GRP_BASE_ADDR + 0x50) // 0x86c ++#define IOMUXC_SW_PAD_CTL_GRP_HVDDR (SW_GRP_BASE_ADDR + 0x54) // 0x870 ++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 (SW_GRP_BASE_ADDR + 0x58) // 0x874 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 (SW_GRP_BASE_ADDR + 0x5c) // 0x878 ++#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS (SW_GRP_BASE_ADDR + 0x60) // 0x87c ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 (SW_GRP_BASE_ADDR + 0x64) // 0x880 ++#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS (SW_GRP_BASE_ADDR + 0x68) // 0x884 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 (SW_GRP_BASE_ADDR + 0x6c) // 0x888 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 (SW_GRP_BASE_ADDR + 0x70) // 0x88c ++#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR (SW_GRP_BASE_ADDR + 0x74) // 0x890 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 (SW_GRP_BASE_ADDR + 0x78) // 0x894 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 (SW_GRP_BASE_ADDR + 0x7c) // 0x898 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 (SW_GRP_BASE_ADDR + 0x80) // 0x89c ++#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 (SW_GRP_BASE_ADDR + 0x84) // 0x8a0 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 (SW_GRP_BASE_ADDR + 0x88) // 0x8a4 ++#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 (SW_GRP_BASE_ADDR + 0x8c) // 0x8a8 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 (SW_GRP_BASE_ADDR + 0x90) // 0x8ac ++#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 (SW_GRP_BASE_ADDR + 0x94) // 0x8b0 ++#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 (SW_GRP_BASE_ADDR + 0x98) // 0x8b4 ++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 (SW_GRP_BASE_ADDR + 0x9c) // 0x8b8 ++#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 (SW_GRP_BASE_ADDR + 0xa0) // 0x8bc ++#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 (SW_GRP_BASE_ADDR + 0xa4) // 0x8c0 ++ ++#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x0) // 0x8c4 ++#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4) // 0x8c8 ++#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8) // 0x8cc ++#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc) // 0x8d0 ++#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10) // 0x8d4 ++#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14) // 0x8d8 ++#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x18) // 0x8dc ++#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x1c) // 0x8e0 ++#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x20) // 0x8e4 ++#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x24) // 0x8e8 ++#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x28) // 0x8ec ++#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x2c) // 0x8f0 ++#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x30) // 0x8f4 ++#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x34) // 0x8f8 ++#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x38) // 0x8fc ++#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x3c) // 0x900 ++#define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x40) // 0x904 ++#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x44) // 0x908 ++#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x48) // 0x90c ++#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4c) // 0x910 ++#define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x50) // 0x914 ++#define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x54) // 0x918 ++#define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x58) // 0x91c ++#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x5c) // 0x920 ++#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x60) // 0x924 ++#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x64) // 0x928 ++#define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x68) // 0x92c ++#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x6c) // 0x930 ++#define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x70) // 0x934 ++#define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x74) // 0x938 ++#define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x78) // 0x93c ++#define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x7c) // 0x940 ++#define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x80) // 0x944 ++#define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x84) // 0x948 ++#define IOMUXC_FEC_FEC_COL_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x88) // 0x94c ++#define IOMUXC_FEC_FEC_CRS_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8c) // 0x950 ++#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x90) // 0x954 ++#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x94) // 0x958 ++#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x98) // 0x95c ++#define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x9c) // 0x960 ++#define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa0) // 0x964 ++#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa4) // 0x968 ++#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa8) // 0x96c ++#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xac) // 0x970 ++#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb0) // 0x974 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb4) // 0x978 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb8) // 0x97c ++#define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xbc) // 0x980 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc0) // 0x984 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc4) // 0x988 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc8) // 0x98c ++#define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xcc) // 0x990 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd0) // 0x994 ++#define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd4) // 0x998 ++#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd8) // 0x99c ++#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xdc) // 0x9a0 ++#define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe0) // 0x9a4 ++#define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe4) // 0x9a8 ++#define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe8) // 0x9ac ++#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xec) // 0x9b0 ++#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf0) // 0x9b4 ++#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf4) // 0x9b8 ++#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf8) // 0x9bc ++#define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xfc) // 0x9c0 ++#define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x100) // 0x9c4 ++#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x104) // 0x9c8 ++#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x108) // 0x9cc ++#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10c) // 0x9d0 ++#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x110) // 0x9d4 ++#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x114) // 0x9d8 ++#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x118) // 0x9dc ++#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x11c) // 0x9e0 ++#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x120) // 0x9e4 ++#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x124) // 0x9e8 ++#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x128) // 0x9ec ++#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x12c) // 0x9f0 ++#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x130) // 0x9f4 ++#define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x134) // 0x9f8 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x138) // 0x9fc ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x13c) // 0xa00 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x140) // 0xa04 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x144) // 0xa08 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x148) // 0xa0c ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14c) // 0xa10 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x150) // 0xa14 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x154) // 0xa18 ++#define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x158) // 0xa1c ++#define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x15c) // 0xa20 ++#define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x160) // 0xa24 ++ ++#define IOMUX_SW_MUX_CTL_SION 0x4 ++ ++#define IOMUX_PAD_SRC_LSH 0 ++#define IOMUX_PAD_DSE_LSH 1 ++#define IOMUX_PAD_PUE_LSH 6 ++#define IOMUX_PAD_HYS_LSH 8 ++ ++// IOMUXC_SW_PAD_CTL, value of each field ++#define IOMUX_SW_PAD_CTL_SRE_SLOW 0 // Slow slew rate ++#define IOMUX_SW_PAD_CTL_SRE_FAST 1 // Fast slew rate ++ ++#define IOMUX_SW_PAD_CTL_DSE_NORMAL 0 // Normal drive strength ++#define IOMUX_SW_PAD_CTL_DSE_MEDIUM 1 // Medium drive strength ++#define IOMUX_SW_PAD_CTL_DSE_HIGH 2 // High drive strength ++#define IOMUX_SW_PAD_CTL_DSE_MAX 3 // Maximum drive strength ++ ++#define IOMUX_SW_PAD_CTL_ODE_DISABLE 0 // Disable open drain ++#define IOMUX_SW_PAD_CTL_ODE_ENABLE 1 // Enable open drain ++ ++#define IOMUX_SW_PAD_CTL_PUS_100K_DOWN 0 // 100K Ohm pull down ++#define IOMUX_SW_PAD_CTL_PUS_47K_UP 1 // 47K Ohm pull up ++#define IOMUX_SW_PAD_CTL_PUS_100K_UP 2 // 100K Ohm pull up ++#define IOMUX_SW_PAD_CTL_PUS_22K_UP 3 // 22K Ohm pull up ++ ++#define IOMUX_SW_PAD_CTL_PUE_KEEPER 0 // Keeper enable ++#define IOMUX_SW_PAD_CTL_PUE_PULL 1 // Pull up/down enable ++ ++#define IOMUX_SW_PAD_CTL_PKE_DISABLE 0 // Pull up/down/keeper disabled ++#define IOMUX_SW_PAD_CTL_PKE_ENABLE 1 // Pull up/down/keeper enabled ++ ++#define IOMUX_SW_PAD_CTL_HYS_DISABLE 0 // Disable hysteresis ++#define IOMUX_SW_PAD_CTL_HYS_ENABLE 1 // Enable hysteresis ++ ++#define IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS 0 // CMOS input ++#define IOMUX_SW_PAD_CTL_DDR_INPUT_DDR 1 // DDR input ++ ++#define IOMUX_SW_PAD_CTL_HVE_LOW 0 // Low output voltage ++#define IOMUX_SW_PAD_CTL_HVE_HIGH 1 // High output voltage ++// offset ++#define IOMUX_SW_PAD_CTL_SRE_LSH 0 ++#define IOMUX_SW_PAD_CTL_DSE_LSH 1 ++#define IOMUX_SW_PAD_CTL_ODE_LSH 3 ++#define IOMUX_SW_PAD_CTL_PUS_LSH 4 ++#define IOMUX_SW_PAD_CTL_PUE_LSH 6 ++#define IOMUX_SW_PAD_CTL_PKE_LSH 7 ++#define IOMUX_SW_PAD_CTL_HYS_LSH 8 ++#define IOMUX_SW_PAD_CTL_DDR_INPUT_LSH 9 ++#define IOMUX_SW_PAD_CTL_HVE_LSH 13 ++// end of pad control configuration ++ ++// Mode define ++typedef enum{ ++ IOMUX_SW_MUX_CTL_ALT0 = 0, ++ IOMUX_SW_MUX_CTL_ALT1 = 1, ++ IOMUX_SW_MUX_CTL_ALT2 = 2, ++ IOMUX_SW_MUX_CTL_ALT3 = 3, ++ IOMUX_SW_MUX_CTL_ALT4 = 4, ++ IOMUX_SW_MUX_CTL_ALT5 = 5, ++ IOMUX_SW_MUX_CTL_ALT6 = 6, ++ IOMUX_SW_MUX_CTL_ALT7 = 7 ++}IOMUX_PIN_MODE; ++ ++typedef enum ++{ ++ IOMUX_PIN_SION_REGULAR = (0 << IOMUX_SW_MUX_CTL_SION), ++ IOMUX_PIN_SION_FORCE = (1 << IOMUX_SW_MUX_CTL_SION) ++} IOMUX_PIN_SION; ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_SLEW ++// ++// Specifies the slew rate for a pad. ++// ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_SLEW_SLOW = (IOMUX_SW_PAD_CTL_SRE_SLOW << IOMUX_SW_PAD_CTL_SRE_LSH), ++ IOMUX_PAD_SLEW_FAST = (IOMUX_SW_PAD_CTL_SRE_FAST << IOMUX_SW_PAD_CTL_SRE_LSH), ++} IOMUX_PAD_SLEW; ++ ++#define IOMUX_PAD_SLEW_NULL ((IOMUX_PAD_SLEW)0) ++ ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_DRIVE ++// ++// Specifies the drive strength for a pad. ++// ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_DRIVE_NORMAL = (IOMUX_SW_PAD_CTL_DSE_NORMAL << IOMUX_SW_PAD_CTL_DSE_LSH), ++ IOMUX_PAD_DRIVE_MEDIUM = (IOMUX_SW_PAD_CTL_DSE_MEDIUM << IOMUX_SW_PAD_CTL_DSE_LSH), ++ IOMUX_PAD_DRIVE_HIGH = (IOMUX_SW_PAD_CTL_DSE_HIGH << IOMUX_SW_PAD_CTL_DSE_LSH), ++ IOMUX_PAD_DRIVE_MAX = (IOMUX_SW_PAD_CTL_DSE_MAX << IOMUX_SW_PAD_CTL_DSE_LSH) ++} IOMUX_PAD_DRIVE; ++ ++#define IOMUX_PAD_DRIVE_NULL ((IOMUX_PAD_DRIVE)0) ++ ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_OPENDRAIN ++// ++// Specifies the open drain for a pad. ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_OPENDRAIN_DISABLE = (IOMUX_SW_PAD_CTL_ODE_DISABLE << IOMUX_SW_PAD_CTL_ODE_LSH), ++ IOMUX_PAD_OPENDRAIN_ENABLE = (IOMUX_SW_PAD_CTL_ODE_ENABLE << IOMUX_SW_PAD_CTL_ODE_LSH) ++} IOMUX_PAD_OPENDRAIN; ++ ++#define IOMUX_PAD_OPENDRAIN_NULL ((IOMUX_PAD_OPENDRAIN)0) ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_PULL ++// ++// Specifies the pull-up/pull-down/keeper configuration for a pad. ++// ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_PULL_NONE = (IOMUX_SW_PAD_CTL_PKE_DISABLE << IOMUX_SW_PAD_CTL_PKE_LSH), ++ ++ IOMUX_PAD_PULL_KEEPER = (IOMUX_SW_PAD_CTL_PUE_KEEPER << IOMUX_SW_PAD_CTL_PUE_LSH) | ++ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH), ++ ++ IOMUX_PAD_PULL_DOWN_100K = (IOMUX_SW_PAD_CTL_PUS_100K_DOWN << IOMUX_SW_PAD_CTL_PUS_LSH) | ++ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) | ++ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH), ++ ++ IOMUX_PAD_PULL_UP_100K = (IOMUX_SW_PAD_CTL_PUS_100K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) | ++ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) | ++ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH), ++ ++ IOMUX_PAD_PULL_UP_47K = (IOMUX_SW_PAD_CTL_PUS_47K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) | ++ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) | ++ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH), ++ ++ IOMUX_PAD_PULL_UP_22K = (IOMUX_SW_PAD_CTL_PUS_22K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) | ++ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) | ++ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH) ++ ++} IOMUX_PAD_PULL; ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_HYSTERESIS ++// ++// Specifies the hysteresis for a pad. ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_HYSTERESIS_DISABLE = (IOMUX_SW_PAD_CTL_HYS_DISABLE << IOMUX_SW_PAD_CTL_HYS_LSH), ++ IOMUX_PAD_HYSTERESIS_ENABLE = (IOMUX_SW_PAD_CTL_HYS_ENABLE << IOMUX_SW_PAD_CTL_HYS_LSH) ++} IOMUX_PAD_HYSTERESIS; ++ ++#define IOMUX_PAD_HYSTERESIS_NULL ((IOMUX_PAD_HYSTERESIS)0) ++ ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_INMODE ++// ++// Specifies the input mode (DDR/CMOS) for a pad. ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_INMODE_CMOS = (IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH), ++ IOMUX_PAD_INMODE_DDR = (IOMUX_SW_PAD_CTL_DDR_INPUT_DDR << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH) ++} IOMUX_PAD_INMODE; ++ ++#define IOMUX_PAD_INMODE_NULL ((IOMUX_PAD_INMODE)0) ++ ++//----------------------------------------------------------------------------- ++// ++// Type: IOMUX_PAD_OUTVOLT ++// ++// Specifies the output voltage for a pad. ++// ++//----------------------------------------------------------------------------- ++typedef enum ++{ ++ IOMUX_PAD_OUTVOLT_LOW = (IOMUX_SW_PAD_CTL_HVE_LOW << IOMUX_SW_PAD_CTL_HVE_LSH), ++ IOMUX_PAD_OUTVOLT_HIGH = (IOMUX_SW_PAD_CTL_HVE_HIGH << IOMUX_SW_PAD_CTL_HVE_LSH) ++} IOMUX_PAD_OUTVOLT; ++ ++#define IOMUX_PAD_OUTVOLT_NULL ((IOMUX_PAD_OUTVOLT)0) ++ ++#define CONFIG_PIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val ++#define CONFIG_DAISY_CHAIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val ++#define CONFIG_PAD(Reg_Addr,Val) *(volatile unsigned int *)Reg_Addr=Val ++ ++#endif +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/plf_stub.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/plf_stub.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/plf_stub.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/plf_stub.h 2010-01-26 17:35:50.042958254 +0000 +@@ -0,0 +1,72 @@ ++#ifndef CYGONCE_HAL_PLF_STUB_H ++#define CYGONCE_HAL_PLF_STUB_H ++ ++//============================================================================= ++// ++// plf_stub.h ++// ++// Platform header for GDB stub support. ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++ ++#include ++#include // CYG_UNUSED_PARAM ++ ++#include // registers ++#include // IO macros ++#include // Interrupt macros ++#include // architecture stub support ++ ++#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++//---------------------------------------------------------------------------- ++// Define some platform specific communication details. This is mostly ++// handled by hal_if now, but we need to make sure the comms tables are ++// properly initialized. ++ ++externC void cyg_hal_plf_comms_init(void); ++ ++#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() ++#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) ++#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 ++ ++//---------------------------------------------------------------------------- ++// Stub initializer. ++#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT ++ ++#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++//----------------------------------------------------------------------------- ++#endif // CYGONCE_HAL_PLF_STUB_H ++// End of plf_stub.h +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/var_io.h redboot-imx-200952/packages/hal/arm/mx51/var/current/include/var_io.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/include/var_io.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/include/var_io.h 2010-01-26 17:35:50.042958254 +0000 +@@ -0,0 +1,56 @@ ++#ifndef CYGONCE_VAR_IO_H ++#define CYGONCE_VAR_IO_H ++ ++//============================================================================= ++// ++// var_io.h ++// ++// Variant specific IO support ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//============================================================================= ++ ++#include // Platform specifics ++ ++//----------------------------------------------------------------------------- ++ ++// Memory mapping details ++#ifndef CYGARC_PHYSICAL_ADDRESS ++#define CYGARC_PHYSICAL_ADDRESS(x) (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE) ++#endif ++ ++//----------------------------------------------------------------------------- ++// end of var_io.h ++#endif // CYGONCE_VAR_IO_H +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/cmds.c redboot-imx-200952/packages/hal/arm/mx51/var/current/src/cmds.c +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/cmds.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/src/cmds.c 2010-01-26 17:35:50.052962253 +0000 +@@ -0,0 +1,1202 @@ ++//========================================================================== ++// ++// cmds.c ++// ++// SoC [platform] specific RedBoot commands ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++#include ++#include ++#include ++#include // Hardware definitions ++#include ++ ++int gcd(int m, int n); ++extern void increase_core_voltage(bool i); ++ ++typedef unsigned long long u64; ++typedef unsigned int u32; ++typedef unsigned short u16; ++typedef unsigned char u8; ++ ++#define SZ_DEC_1M 1000000 ++#define PLL_PD_MAX 16 //actual pd+1 ++#define PLL_MFI_MAX 15 ++#define PLL_MFI_MIN 5 ++#define ARM_DIV_MAX 8 ++#define IPG_DIV_MAX 4 ++#define AHB_DIV_MAX 8 ++#define EMI_DIV_MAX 8 ++#define NFC_DIV_MAX 8 ++ ++#define REF_IN_CLK_NUM 4 ++struct fixed_pll_mfd { ++ u32 ref_clk_hz; ++ u32 mfd; ++}; ++const struct fixed_pll_mfd fixed_mfd[REF_IN_CLK_NUM] = { ++ {0, 0}, // reserved ++ {0, 0}, // reserved ++ {FREQ_24MHZ, 24 * 16}, // 384 ++ {0, 0}, // reserved ++}; ++ ++struct pll_param { ++ u32 pd; ++ u32 mfi; ++ u32 mfn; ++ u32 mfd; ++}; ++ ++#define PLL_FREQ_MAX(_ref_clk_) (4 * _ref_clk_ * PLL_MFI_MAX) ++#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) ++#define MAX_DDR_CLK 420000000 ++#define AHB_CLK_MAX 133333333 ++#define IPG_CLK_MAX (AHB_CLK_MAX / 2) ++#define NFC_CLK_MAX 25000000 ++// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires ++// higher voltage support. For simplicity, limit it to 133MHz ++#define HSP_CLK_MAX 133333333 ++ ++#define ERR_WRONG_CLK -1 ++#define ERR_NO_MFI -2 ++#define ERR_NO_MFN -3 ++#define ERR_NO_PD -4 ++#define ERR_NO_PRESC -5 ++#define ERR_NO_AHB_DIV -6 ++ ++u32 pll_clock(enum plls pll); ++u32 get_main_clock(enum main_clocks clk); ++u32 get_peri_clock(enum peri_clocks clk); ++ ++static volatile u32 *pll_base[] = ++{ ++ REG32_PTR(PLL1_BASE_ADDR), ++ REG32_PTR(PLL2_BASE_ADDR), ++ REG32_PTR(PLL3_BASE_ADDR), ++}; ++ ++#define NOT_ON_VAL 0xDEADBEEF ++ ++static void clock_setup(int argc, char *argv[]); ++ ++RedBoot_cmd("clock", ++ "Setup/Display clock\nSyntax:", ++ "[ :] \n\n\ ++ Examples:\n\ ++ [clock] -> Show various clocks\n\ ++ [clock 665] -> Core=665 \n\ ++ [clock 800:133] -> Core=800 DDR=133 \n\ ++ [clock :166] -> Core=no change DDR=166 \n", ++ clock_setup ++ ); ++ ++/*! ++ * This is to calculate various parameters based on reference clock and ++ * targeted clock based on the equation: ++ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) ++ * This calculation is based on a fixed MFD value for simplicity. ++ * ++ * @param ref reference clock freq in Hz ++ * @param target targeted clock in Hz ++ * @param p_pd calculated pd value (pd value from register + 1) upon return ++ * @param p_mfi calculated actual mfi value upon return ++ * @param p_mfn calculated actual mfn value upon return ++ * @param p_mfd fixed mfd value (mfd value from register + 1) upon return ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) ++{ ++ u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i; ++ ++ // make sure targeted freq is in the valid range. Otherwise the ++ // following calculation might be wrong!!! ++ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref)) ++ return ERR_WRONG_CLK; ++ for (i = 0; ; i++) { ++ if (i == REF_IN_CLK_NUM) ++ return ERR_WRONG_CLK; ++ if (fixed_mfd[i].ref_clk_hz == ref) { ++ mfd = fixed_mfd[i].mfd; ++ break; ++ } ++ } ++ ++ // Use n_target and n_ref to avoid overflow ++ for (pd = 1; pd <= PLL_PD_MAX; pd++) { ++ mfi = (n_target * pd) / (4 * n_ref); ++ if (mfi > PLL_MFI_MAX) { ++ return ERR_NO_MFI; ++ } else if (mfi < 5) { ++ continue; ++ } ++ break; ++ } ++ // Now got pd and mfi already ++ mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; ++#ifdef CMD_CLOCK_DEBUG ++ diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n", ++ __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); ++#endif ++ i = 1; ++ if (mfn != 0) ++ i = gcd(mfd, mfn); ++ pll->pd = (u32)pd; ++ pll->mfi = (u32)mfi; ++ pll->mfn = (u32)(mfn / i); ++ pll->mfd = (u32)(mfd / i); ++ return 0; ++} ++ ++/*! ++ * This function returns the low power audio clock. ++ */ ++u32 get_lp_apm(void) ++{ ++ u32 ret_val = 0; ++ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR); ++ ++ if (((ccsr >> 9) & 1) == 0) { ++ ret_val = FREQ_24MHZ; ++ } else { ++ ret_val = FREQ_32768HZ; ++ } ++ return ret_val; ++} ++ ++/*! ++ * This function returns the periph_clk. ++ */ ++u32 get_periph_clk(void) ++{ ++ u32 ret_val = 0, clk_sel; ++ ++ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); ++ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); ++ ++ if (((cbcdr >> 25) & 1) == 0) { ++ ret_val = pll_clock(PLL2); ++ } else { ++ clk_sel = (cbcmr >> 12) & 3; ++ if (clk_sel == 0) { ++ ret_val = pll_clock(PLL1); ++ } else if (clk_sel == 1) { ++ ret_val = pll_clock(PLL3); ++ } else if (clk_sel == 2) { ++ ret_val = get_lp_apm(); ++ } ++ } ++ return ret_val; ++} ++ ++/*! ++ * This function assumes the expected core clock has to be changed by ++ * modifying the PLL. This is NOT true always but for most of the times, ++ * it is. So it assumes the PLL output freq is the same as the expected ++ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. ++ * In the latter case, it will try to increase the presc value until ++ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to ++ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based ++ * on the targeted PLL and reference input clock to the PLL. Lastly, ++ * it sets the register based on these values along with the dividers. ++ * Note 1) There is no value checking for the passed-in divider values ++ * so the caller has to make sure those values are sensible. ++ * 2) Also adjust the NFC divider such that the NFC clock doesn't ++ * exceed NFC_CLK_MAX. ++ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to ++ * 177MHz for higher voltage, this function fixes the max to 133MHz. ++ * 4) This function should not have allowed diag_printf() calls since ++ * the serial driver has been stoped. But leave then here to allow ++ * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). ++ * ++ * @param ref pll input reference clock (24MHz) ++ * @param core_clk core clock in Hz ++ * @param emi_clk emi clock in Hz ++ # @return 0 if successful; non-zero otherwise ++ */ ++int configure_clock(u32 ref, u32 core_clk, u32 emi_clk) ++{ ++ ++ u32 pll, clk_src; ++ struct pll_param pll_param; ++ int ret, clk_sel, div = 1, shift = 0; ++ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); ++ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); ++ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR); ++ ++ if (core_clk != 0) { ++ // assume pll default to core clock first ++ pll = core_clk; ++ if ((ret = calc_pll_params(ref, pll, &pll_param)) != 0) { ++ diag_printf("can't find pll parameters: %d\n", ret); ++ return ret; ++ } ++#ifdef CMD_CLOCK_DEBUG ++ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n", ++ ref, pll, pll_param.pd, pll_param.mfi, pll_param.mfn, pll_param.mfd); ++#endif ++ ++ /* Applies for TO 2 only */ ++ if (((cbcdr >> 30) & 0x1) == 0x1) { ++ /* Disable IPU and HSC dividers */ ++ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR); ++ /* Switch DDR to different source */ ++ writel(cbcdr & ~0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR); ++ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0); ++ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); ++ } ++ ++ /* Switch ARM to PLL2 clock */ ++ writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR); ++ ++ if (core_clk > 800000000) { ++ increase_core_voltage(true); ++ } else { ++ increase_core_voltage(false); ++ } ++ ++ // adjust pll settings ++ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4), ++ PLL1_BASE_ADDR + PLL_DP_OP); ++ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_MFN); ++ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_MFD); ++ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4), ++ PLL1_BASE_ADDR + PLL_DP_HFS_OP); ++ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_HFS_MFN); ++ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_HFS_MFD); ++ ++ /* Switch ARM back to PLL1 */ ++ writel((ccsr & ~0x4), CCM_BASE_ADDR + CLKCTL_CCSR); ++ /* Applies for TO 2 only */ ++ if (((cbcdr >> 30) & 0x1) == 0x1) { ++ /* Disable IPU and HSC dividers */ ++ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR); ++ /* Switch DDR back to PLL1 */ ++ writel(cbcdr | 0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR); ++ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0); ++ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); ++ if (emi_clk == 0) { ++ /* Keep EMI clock to the max if not specified */ ++ emi_clk = 200000000; ++ } ++ } ++ } ++ ++ if (emi_clk != 0) { ++ /* Applies for TO 2 only */ ++ if (((cbcdr >> 30) & 0x1) == 0x1) { ++ clk_src = pll_clock(PLL1); ++ shift = 27; ++ } else { ++ clk_src = get_periph_clk(); ++ /* Find DDR clock input */ ++ clk_sel = (cbcmr >> 10) & 0x3; ++ if (clk_sel == 0) { ++ shift = 16; ++ } else if (clk_sel == 1) { ++ shift = 19; ++ } else if (clk_sel == 2) { ++ shift = 22; ++ } else if (clk_sel == 3) { ++ shift = 10; ++ } ++ } ++ if ((clk_src % emi_clk) == 0) ++ div = clk_src / emi_clk; ++ else ++ div = (clk_src / emi_clk) + 1; ++ if (div > 8) ++ div = 8; ++ ++ cbcdr = cbcdr & ~(0x7 << shift); ++ cbcdr |= ((div - 1) << shift); ++ /* Disable IPU and HSC dividers */ ++ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR); ++ writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR); ++ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0); ++ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); ++ } ++ return 0; ++} ++ ++static void clock_setup(int argc,char *argv[]) ++{ ++ ++ u32 i, core_clk, ddr_clk, data[3]; ++ unsigned long temp; ++ int ret; ++ ++ if (argc == 1) ++ goto print_clock; ++ ++ for (i = 0; i < 2; i++) { ++ if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ data[i] = temp; ++ } ++ ++ core_clk = data[0] * SZ_DEC_1M; ++ ddr_clk = data[1] * SZ_DEC_1M; ++ ++ if (core_clk != 0) { ++ if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) { ++ diag_printf("Targeted core clock should be within [%d - %d]\n", ++ PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK)); ++ return; ++ } ++ } ++ ++ if (ddr_clk != 0) { ++ if (ddr_clk > MAX_DDR_CLK) { ++ diag_printf("DDR clock should be less than %d MHz, assuming max value \n", (MAX_DDR_CLK / SZ_DEC_1M)); ++ ddr_clk = MAX_DDR_CLK; ++ } ++ } ++ ++ // stop the serial to be ready to adjust the clock ++ hal_delay_us(100000); ++// cyg_hal_plf_serial_stop(); ++ // adjust the clock ++ ret = configure_clock(PLL_REF_CLK, core_clk, ddr_clk); ++ // restart the serial driver ++// cyg_hal_plf_serial_init(); ++ hal_delay_us(100000); ++ ++ if (ret != 0) { ++ diag_printf("Failed to setup clock: %d\n", ret); ++ return; ++ } ++ diag_printf("\n<<>>\n"); ++ ++ // Now printing clocks ++print_clock: ++ ++ diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n"); ++ diag_printf("========================================\n"); ++ diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2), ++ pll_clock(PLL3)); ++ diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n"); ++ diag_printf("========================================================\n"); ++ diag_printf("%-16d%-16d%-16d%-16d\n\n", ++ get_main_clock(CPU_CLK), ++ get_main_clock(AHB_CLK), ++ get_main_clock(IPG_CLK), ++ get_main_clock(DDR_CLK)); ++ ++ diag_printf("NFC\t\tUSB\t\tIPG_PER_CLK\n"); ++ diag_printf("========================================\n"); ++ diag_printf("%-16d%-16d%-16d\n\n", ++ get_main_clock(NFC_CLK), ++ get_main_clock(USB_CLK), ++ get_main_clock(IPG_PER_CLK)); ++ ++ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tSPI\n"); ++ diag_printf("==========================================="); ++ diag_printf("=============\n"); ++ ++ diag_printf("%-16d%-16d%-16d%-16d\n\n", ++ get_peri_clock(UART1_BAUD), ++ get_peri_clock(SSI1_BAUD), ++ get_peri_clock(SSI2_BAUD), ++ get_peri_clock(SPI1_CLK)); ++ ++#if 0 ++ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC"); ++ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) { ++ diag_printf(", EPIT"); ++ } ++ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) { ++ diag_printf("GPT,"); ++ } ++#endif ++ diag_printf("\n"); ++ ++} ++ ++/*! ++ * This function returns the PLL output value in Hz based on pll. ++ */ ++u32 pll_clock(enum plls pll) ++{ ++ u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign; ++ u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel; ++ u8 dbl = 0; ++ ++ dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2]; ++ clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8); ++ ref_clk = fixed_mfd[clk_sel].ref_clk_hz; ++ ++ if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) { ++ dp_op = pll_base[pll][PLL_DP_OP >> 2]; ++ dp_mfd = pll_base[pll][PLL_DP_MFD >> 2]; ++ dp_mfn = pll_base[pll][PLL_DP_MFN >> 2]; ++ } else { ++ dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2]; ++ dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2]; ++ dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2]; ++ } ++ pdf = dp_op & 0xF; ++ mfi = (dp_op >> 4) & 0xF; ++ mfi = (mfi <= 5) ? 5: mfi; ++ mfd = dp_mfd & 0x07FFFFFF; ++ mfn = dp_mfn & 0x07FFFFFF; ++ ++ sign = (mfn < 0x4000000) ? 0: 1; ++ mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn); ++ ++ dbl = ((dp_ctrl >> 12) & 0x1) + 1; ++ ++ dbl = dbl * 2; ++ if (sign == 0) { ++ pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) / ++ (pdf + 1); ++ } else { ++ pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) / ++ (pdf + 1); ++ } ++ ++ return (u32)pll_out; ++} ++ ++/*! ++ * This function returns the emi_core_clk_root clock. ++ */ ++u32 get_emi_core_clk(void) ++{ ++ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); ++ u32 clk_sel = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0; ++ u32 ret_val = 0; ++ ++ max_pdf = (cbcdr >> 10) & 0x7; ++ peri_clk = get_periph_clk(); ++ ahb_clk = peri_clk / (max_pdf + 1); ++ ++ clk_sel = (cbcdr >> 26) & 1; ++ if (clk_sel == 0) { ++ ret_val = peri_clk; ++ } else { ++ ret_val = ahb_clk ; ++ } ++ return ret_val; ++} ++ ++/*! ++ * This function returns the main clock value in Hz. ++ */ ++u32 get_main_clock(enum main_clocks clk) ++{ ++ u32 pdf, max_pdf, ipg_pdf, nfc_pdf, clk_sel; ++ u32 pll, ret_val = 0; ++ u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR); ++ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); ++ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); ++ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1); ++ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1); ++ ++ switch (clk) { ++ case CPU_CLK: ++ pdf = cacrr & 0x7; ++ pll = pll_clock(PLL1); ++ ret_val = pll / (pdf + 1); ++ break; ++ case AHB_CLK: ++ max_pdf = (cbcdr >> 10) & 0x7; ++ pll = get_periph_clk(); ++ ret_val = pll / (max_pdf + 1); ++ break; ++ case IPG_CLK: ++ max_pdf = (cbcdr >> 10) & 0x7; ++ ipg_pdf = (cbcdr >> 8) & 0x3; ++ pll = get_periph_clk(); ++ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1)); ++ break; ++ case IPG_PER_CLK: ++ clk_sel = cbcmr & 1; ++ if (clk_sel == 0) { ++ clk_sel = (cbcmr >> 1) & 1; ++ pdf = (((cbcdr >> 6) & 3) + 1) * (((cbcdr >> 3) & 7) + 1) * ((cbcdr & 7) + 1); ++ if (clk_sel == 0) { ++ ret_val = get_periph_clk() / pdf; ++ } else { ++ ret_val = get_lp_apm(); ++ } ++ } else { ++ /* Same as IPG_CLK */ ++ max_pdf = (cbcdr >> 10) & 0x7; ++ ipg_pdf = (cbcdr >> 8) & 0x3; ++ pll = get_periph_clk(); ++ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1)); ++ } ++ break; ++ case DDR_CLK: ++ if (((cbcdr >> 30) & 0x1) == 0x1) { ++ pll = pll_clock(PLL1); ++ pdf = (cbcdr >> 27) & 0x7; ++ } else { ++ clk_sel = (cbcmr >> 10) & 3; ++ pll = get_periph_clk(); ++ if (clk_sel == 0) { ++ /* AXI A */ ++ pdf = (cbcdr >> 16) & 0x7; ++ } else if (clk_sel == 1) { ++ /* AXI B */ ++ pdf = (cbcdr >> 19) & 0x7; ++ } else if (clk_sel == 2) { ++ /* EMI SLOW CLOCK ROOT */ ++ pll = get_emi_core_clk(); ++ pdf = (cbcdr >> 22) & 0x7; ++ } else if (clk_sel == 3) { ++ /* AHB CLOCK */ ++ pdf = (cbcdr >> 10) & 0x7; ++ } ++ } ++ ++ ret_val = pll / (pdf + 1); ++ break; ++ case NFC_CLK: ++ pdf = (cbcdr >> 22) & 0x7; ++ nfc_pdf = (cbcdr >> 13) & 0x7; ++ pll = get_emi_core_clk(); ++ ret_val = pll / ((pdf + 1) * (nfc_pdf + 1)); ++ break; ++ case USB_CLK: ++ clk_sel = (cscmr1 >> 22) & 3; ++ if (clk_sel == 0) { ++ pll = pll_clock(PLL1); ++ } else if (clk_sel == 1) { ++ pll = pll_clock(PLL2); ++ } else if (clk_sel == 2) { ++ pll = pll_clock(PLL3); ++ } else if (clk_sel == 3) { ++ pll = get_lp_apm(); ++ } ++ pdf = (cscdr1 >> 8) & 0x7; ++ max_pdf = (cscdr1 >> 6) & 0x3; ++ ret_val = pll / ((pdf + 1) * (max_pdf + 1)); ++ break; ++ default: ++ diag_printf("Unknown clock: %d\n", clk); ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/*! ++ * This function returns the peripheral clock value in Hz. ++ */ ++u32 get_peri_clock(enum peri_clocks clk) ++{ ++ u32 ret_val = 0, pdf, pre_pdf, clk_sel; ++ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1); ++ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1); ++ u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2); ++ u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR); ++ u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR); ++ ++ switch (clk) { ++ case UART1_BAUD: ++ case UART2_BAUD: ++ case UART3_BAUD: ++ pre_pdf = (cscdr1 >> 3) & 0x7; ++ pdf = cscdr1 & 0x7; ++ clk_sel = (cscmr1 >> 24) & 3; ++ if (clk_sel == 0) { ++ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 1) { ++ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 2) { ++ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1)); ++ } else { ++ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); ++ } ++ break; ++ case SSI1_BAUD: ++ pre_pdf = (cs1cdr >> 6) & 0x7; ++ pdf = cs1cdr & 0x3F; ++ clk_sel = (cscmr1 >> 14) & 3; ++ if (clk_sel == 0) { ++ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 0x1) { ++ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 0x2) { ++ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1)); ++ } else { ++ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1)); ++ } ++ break; ++ case SSI2_BAUD: ++ pre_pdf = (cs2cdr >> 6) & 0x7; ++ pdf = cs2cdr & 0x3F; ++ clk_sel = (cscmr1 >> 12) & 3; ++ if (clk_sel == 0) { ++ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 0x1) { ++ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 0x2) { ++ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1)); ++ } else { ++ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1)); ++ } ++ break; ++ case SPI1_CLK: ++ case SPI2_CLK: ++ pre_pdf = (cscdr2 >> 25) & 0x7; ++ pdf = (cscdr2 >> 19) & 0x3F; ++ clk_sel = (cscmr1 >> 4) & 3; ++ if (clk_sel == 0) { ++ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 1) { ++ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1)); ++ } else if (clk_sel == 2) { ++ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1)); ++ } else { ++ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); ++ } ++ break; ++ default: ++ diag_printf("%s(): This clock: %d not supported yet \n", ++ __FUNCTION__, clk); ++ break; ++ } ++ ++ return ret_val; ++} ++ ++#ifdef L2CC_ENABLED ++/* ++ * This command is added for some simple testing only. It turns on/off ++ * L2 cache regardless of L1 cache state. The side effect of this is ++ * when doing any flash operations such as "fis init", the L2 ++ * will be turned back on along with L1 caches even though it is off ++ * by using this command. ++ */ ++RedBoot_cmd("L2", ++ "L2 cache", ++ "[ON | OFF]", ++ do_L2_caches ++ ); ++ ++void do_L2_caches(int argc, char *argv[]) ++{ ++ u32 oldints; ++ int L2cache_on=0; ++ ++ if (argc == 2) { ++ if (strcasecmp(argv[1], "on") == 0) { ++ HAL_DISABLE_INTERRUPTS(oldints); ++ HAL_ENABLE_L2(); ++ HAL_RESTORE_INTERRUPTS(oldints); ++ } else if (strcasecmp(argv[1], "off") == 0) { ++ HAL_DISABLE_INTERRUPTS(oldints); ++ HAL_DCACHE_DISABLE_C1(); ++ HAL_CACHE_FLUSH_ALL(); ++ HAL_DISABLE_L2(); ++ HAL_DCACHE_ENABLE_L1(); ++ HAL_RESTORE_INTERRUPTS(oldints); ++ } else { ++ diag_printf("Invalid L2 cache mode: %s\n", argv[1]); ++ } ++ } else { ++ HAL_L2CACHE_IS_ENABLED(L2cache_on); ++ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off"); ++ } ++} ++#endif //L2CC_ENABLED ++ ++#define IIM_ERR_SHIFT 8 ++#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT)) ++#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT)) ++ ++static void fuse_op_start(void) ++{ ++ /* Do not generate interrupt */ ++ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF); ++ // clear the status bits and error bits ++ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF); ++ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF); ++} ++ ++/* ++ * The action should be either: ++ * POLL_FUSE_PRGD ++ * or: ++ * POLL_FUSE_SNSD ++ */ ++static int poll_fuse_op_done(int action) ++{ ++ ++ u32 status, error; ++ ++ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) { ++ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action); ++ return -1; ++ } ++ ++ /* Poll busy bit till it is NOT set */ ++ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) { ++ } ++ ++ /* Test for successful write */ ++ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF); ++ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF); ++ ++ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) { ++ if (error) { ++ diag_printf("Even though the operation seems successful...\n"); ++ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n", ++ (IIM_BASE_ADDR + IIM_ERR_OFF), error); ++ } ++ return 0; ++ } ++ diag_printf("%s(%d) failed\n", __FUNCTION__, action); ++ diag_printf("status address=0x%x, value=0x%x\n", ++ (IIM_BASE_ADDR + IIM_STAT_OFF), status); ++ diag_printf("There are some error(s) at addr=0x%x: 0x%x\n", ++ (IIM_BASE_ADDR + IIM_ERR_OFF), error); ++ return -1; ++} ++ ++static unsigned int sense_fuse(int bank, int row, int bit) ++{ ++ int addr, addr_l, addr_h, reg_addr; ++ ++ fuse_op_start(); ++ ++ addr = ((bank << 11) | (row << 3) | (bit & 0x7)); ++ /* Set IIM Program Upper Address */ ++ addr_h = (addr >> 8) & 0x000000FF; ++ /* Set IIM Program Lower Address */ ++ addr_l = (addr & 0x000000FF); ++ ++#ifdef IIM_FUSE_DEBUG ++ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n", ++ __FUNCTION__, addr_h, addr_l); ++#endif ++ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF); ++ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF); ++ /* Start sensing */ ++ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF); ++ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) { ++ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n", ++ __FUNCTION__, bank, row, bit); ++ } ++ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF; ++ return readl(reg_addr); ++} ++ ++void do_fuse_read(int argc, char *argv[]) ++{ ++ unsigned long bank, row; ++ unsigned long fuse_val; ++ ++ if (argc == 1) { ++ diag_printf("Useage: fuse_read \n"); ++ return; ++ } else if (argc == 3) { ++ if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row); ++ fuse_val = sense_fuse(bank, row, 0); ++ diag_printf("fuses at (bank:%ld, row:%ld) = 0x%lx\n", bank, row, fuse_val); ++ } else { ++ diag_printf("Passing in wrong arguments: %d\n", argc); ++ diag_printf("Useage: fuse_read \n"); ++ } ++} ++ ++/* Blow fuses based on the bank, row and bit positions (all 0-based) ++*/ ++int fuse_blow(int bank,int row,int bit) ++{ ++ int addr, addr_l, addr_h, ret = -1; ++ ++ fuse_op_start(); ++ ++ /* Disable IIM Program Protect */ ++ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF); ++ ++ addr = ((bank << 11) | (row << 3) | (bit & 0x7)); ++ /* Set IIM Program Upper Address */ ++ addr_h = (addr >> 8) & 0x000000FF; ++ /* Set IIM Program Lower Address */ ++ addr_l = (addr & 0x000000FF); ++ ++#ifdef IIM_FUSE_DEBUG ++ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l); ++#endif ++ ++ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF); ++ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF); ++ /* Start Programming */ ++ writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF); ++ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) { ++ ret = 0; ++ } ++ ++ /* Enable IIM Program Protect */ ++ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF); ++ return ret; ++} ++ ++/* ++ * This command is added for burning IIM fuses ++ */ ++RedBoot_cmd("fuse_read", ++ "read some fuses", ++ " ", ++ do_fuse_read ++ ); ++ ++RedBoot_cmd("fuse_blow", ++ "blow some fuses", ++ " ", ++ do_fuse_blow ++ ); ++ ++void quick_itoa(u32 num, char *a) ++{ ++ int i, j, k; ++ for (i = 0; i <= 7; i++) { ++ j = (num >> (4 * i)) & 0xF; ++ k = (j < 10) ? '0' : ('a' - 0xa); ++ a[i] = j + k; ++ } ++} ++ ++// slen - streng length, e.g.: 23 -> slen=2; abcd -> slen=4 ++// only convert hex value as string input. so "12" is 0x12. ++u32 quick_atoi(char *a, u32 slen) ++{ ++ u32 i, num = 0, digit; ++ ++ for (i = 0; i < slen; i++) { ++ if (a[i] >= '0' && a[i] <= '9') { ++ digit = a[i] - '0'; ++ } else if (a[i] >= 'a' && a[i] <= 'f') { ++ digit = a[i] - 'a' + 10; ++ } else if (a[i] >= 'A' && a[i] <= 'F') { ++ digit = a[i] - 'A' + 10; ++ } else { ++ diag_printf("ERROR: %c\n", a[i]); ++ return -1; ++ } ++ num = (num * 16) + digit; ++ } ++ return num; ++} ++ ++static void fuse_blow_row(int bank, int row, int value) ++{ ++ unsigned int reg, i; ++ ++ // enable fuse blown ++ reg = readl(CCM_BASE_ADDR + 0x64); ++ reg |= 0x10; ++ writel(reg, CCM_BASE_ADDR + 0x64); ++ ++ for (i = 0; i < 8; i++) { ++ if (((value >> i) & 0x1) == 0) { ++ continue; ++ } ++ if (fuse_blow(bank, row, i) != 0) { ++ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n", ++ bank, row, i); ++ } ++ } ++ reg &= ~0x10; ++ writel(reg, CCM_BASE_ADDR + 0x64); ++} ++ ++void do_fuse_blow(int argc, char *argv[]) ++{ ++ unsigned long bank, row, value, i; ++ unsigned int fuse_val; ++ char *s; ++ char val[3]; ++ ++ if (argc == 1) { ++ diag_printf("It is too dangeous for you to use this command.\n"); ++ return; ++ } ++ ++ if (argc == 3) { ++ if (strcasecmp(argv[1], "scc") == 0) { ++ // fuse_blow scc C3D153EDFD2EA9982226EF5047D3B9A0B9C7138EA87C028401D28C2C2C0B9AA2 ++ diag_printf("Ready to burn SCC fuses\n"); ++ s=argv[2]; ++ for (i = 0; ;i++) { ++ memcpy(val, s, 2); ++ val[2]='\0'; ++ value = quick_atoi(val, 2); ++ // diag_printf("fuse_blow_row(2, %d, value=0x%x)\n", i, value); ++ fuse_blow_row(2, i, value); ++ ++ if ((++s)[0] == '\0') { ++ diag_printf("ERROR: Odd string input\n"); ++ break; ++ } ++ if ((++s)[0] == '\0') { ++ diag_printf("Successful\n"); ++ break; ++ } ++ } ++ } else if (strcasecmp(argv[1], "srk") == 0) { ++ // fuse_blow srk 418bccd09b53bee1ab59e2662b3c7877bc0094caee201052add49be8780dff95 ++ diag_printf("Ready to burn SRK key fuses\n"); ++ s=argv[2]; ++ for (i = 0; ;i++) { ++ memcpy(val, s, 2); ++ val[2]='\0'; ++ value = quick_atoi(val, 2); ++ if (i == 0) { ++ fuse_blow_row(1, 1, value); // 0x41 goes to SRK_HASH[255:248], bank 1, row 1 ++ } else ++ fuse_blow_row(3, i, value); // 0x8b in SRK_HASH[247:240] bank 3, row 1 ++ // 0xcc in SRK_HASH[239:232] bank 3, row 2 ++ // ... ++ if ((++s)[0] == '\0') { ++ diag_printf("ERROR: Odd string input\n"); ++ break; ++ } ++ if ((++s)[0] == '\0') { ++ diag_printf("Successful\n"); ++ break; ++ } ++ } ++ } else ++ diag_printf("This command is not supported\n"); ++ ++ return; ++ } else if (argc == 4) { ++ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ if (!parse_num(*(&argv[3]), &value, &argv[3], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n", ++ bank, row, value); ++ fuse_blow_row(bank, row, value); ++ fuse_val = sense_fuse(bank, row, 0); ++ diag_printf("fuses at (bank:%ld, row:%ld) = 0x%x\n", bank, row, fuse_val); ++ ++ } else { ++ diag_printf("Passing in wrong arguments: %d\n", argc); ++ } ++} ++ ++/* precondition: m>0 and n>0. Let g=gcd(m,n). */ ++int gcd(int m, int n) ++{ ++ int t; ++ while(m > 0) { ++ if(n > m) {t = m; m = n; n = t;} /* swap */ ++ m -= n; ++ } ++ return n; ++} ++ ++int read_mac_addr_from_fuse(unsigned char* data) ++{ ++ data[0] = sense_fuse(1, 9, 0) ; ++ data[1] = sense_fuse(1, 10, 0) ; ++ data[2] = sense_fuse(1, 11, 0) ; ++ data[3] = sense_fuse(1, 12, 0) ; ++ data[4] = sense_fuse(1, 13, 0) ; ++ data[5] = sense_fuse(1, 14, 0) ; ++ ++ if ((data[0] == 0) && (data[1] == 0) && (data[2] == 0) && ++ (data[3] == 0) && (data[4] == 0) && (data[5] == 0)) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static void set_fecmac(int argc,char *argv[]) ++{ ++ unsigned long temp; ++ unsigned char data[6]; ++ int ret, i; ++ ++ if (argc == 1) { ++ goto print_mac_info; ++ } ++ ++ if (argc != 2) { ++ ret = -1; ++ goto error; ++ } ++ for (i = 0; i < 6; i++) { ++ if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) { ++ ret = -2; ++ goto error; ++ } ++ if (temp > 0xFF) { ++ ret = -3; ++ goto error; ++ } ++ data[i] = temp & 0xFF; ++ } ++ ++ for (i = 0; i < 6; i++) { ++ fuse_blow_row(1, i + 9, data[i]); ++ } ++ ++print_mac_info: ++ /* Read the Mac address and print it */ ++ ret = read_mac_addr_from_fuse(data); ++ ++ diag_printf("FEC MAC address: "); ++ diag_printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n", ++ data[0], data[1], data[2], data[3], data[4], data[5]); ++ ++ return; ++ ++ error: ++ diag_printf("Wrong value for set_fecmac. Error=%d\n\n", ret); ++} ++ ++RedBoot_cmd("set_fecmac", ++ "Set FEC MAC address in Fuse registers", ++ "[0x##:0x##:0x##:0x##:0x##:0x##]", ++ set_fecmac ++ ); ++ ++#if 0 ++void imx_power_mode(int mode) ++{ ++ volatile unsigned int val; ++ switch (mode) { ++ case 2: ++ writel(0x0000030f, GPC_PGR); ++ writel(0x1, SRPGCR_EMI); ++ writel(0x1, SRPGCR_ARM); ++ writel(0x1, PGC_PGCR_VPU); ++ writel(0x1, PGC_PGCR_IPU); ++ ++ ++ case 1: ++ // stop mode - from validation code ++ // Set DSM_INT_HOLDOFF bit in TZIC ++ // If the TZIC didn't write the bit then there was interrupt pending ++ // It will be serviced while we're in the loop ++ // So we write to this bit again ++ while (readl(INTC_BASE_ADDR + 0x14) == 0) { ++ writel(1, INTC_BASE_ADDR + 0x14); ++ // Wait few cycles ++ __asm("nop"); ++ __asm("nop"); ++ __asm("nop"); ++ __asm("nop"); ++ __asm("nop"); ++ __asm("nop"); ++ __asm("nop"); ++ } ++ diag_printf("Entering stop mode\n"); ++ val = readl(CCM_BASE_ADDR + 0x74); ++ val = (val & 0xfffffffc) | 0x2; // set STOP mode ++ writel(val, CCM_BASE_ADDR + 0x74); ++ val = readl(PLATFORM_LPC_REG); ++ writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform ++ writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform ++ break; ++ default: ++ break; ++ } ++ ++ hal_delay_us(50); ++ ++ asm("mov r1, #0"); ++ asm("mcr p15, 0, r1, c7, c0, 4"); ++} ++ ++void do_power_mode(int argc, char *argv[]) ++{ ++ int mode; ++ ++ if (argc == 1) { ++ diag_printf("Useage: power_mode \n"); ++ return; ++ } else if (argc == 2) { ++ if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ diag_printf("Entering power mode: %d\n", mode); ++ imx_power_mode(mode); ++ ++ } else { ++ diag_printf("Passing in wrong arguments: %d\n", argc); ++ diag_printf("Useage: power_mode \n"); ++ } ++} ++ ++/* ++ * This command is added for burning IIM fuses ++ */ ++RedBoot_cmd("power_mode", ++ "Enter various power modes:", ++ "\n\ ++ <0> - WAIT\n\ ++ <1> - SRPG\n\ ++ <2> - STOP\n\ ++ <3> - STOP with Power-Gating\n\ ++ -- need reset after issuing the command", ++ do_power_mode ++ ); ++#endif ++ ++#include "hab_super_root.h" ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/hab_super_root.h redboot-imx-200952/packages/hal/arm/mx51/var/current/src/hab_super_root.h +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/hab_super_root.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/src/hab_super_root.h 2010-01-26 17:35:50.052962253 +0000 +@@ -0,0 +1,209 @@ ++//========================================================================== ++// ++// hab_super_root.h ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++#ifndef HAB_SUPER_ROOT_H ++#define HAB_SUPER_ROOT_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/*================================================================================================== ++ ++ Header Name: hab_super_root.h ++ ++ General Description: This module contains the HAB Super Root public keys. ++ ++====================================================================================================*/ ++ ++/* Generic type definitions */ ++typedef signed char INT8; ++typedef unsigned char UINT8; ++typedef short int INT16; ++typedef unsigned short int UINT16; ++typedef int INT32; ++typedef unsigned int UINT32; ++typedef unsigned char BOOLEAN; ++ ++ ++/* HAB specific type definitions */ ++typedef UINT8 *hab_bytestring; ++typedef UINT16 hab_algorithm; ++typedef UINT8 hab_index; ++typedef UINT32 hab_address; ++typedef UINT8 hab_certificate; ++typedef UINT32 hab_data_length; ++typedef UINT16 hab_int_length; ++typedef UINT8 hab_error; ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++/* HAB specific definitions */ ++#define HAB_MAX_EXP_SIZE ((hab_int_length)4) /* Maximum size of RSA ++ * public key exponent ++ * - in bytes ++ */ ++ ++/*================================================================================================== ++ MACROS ++==================================================================================================*/ ++ ++/*================================================================================================== ++ ENUMS ++==================================================================================================*/ ++ ++/*================================================================================================== ++ STRUCTURES AND OTHER TYPEDEFS ++==================================================================================================*/ ++ ++/* RSA public key structure */ ++typedef struct ++{ ++ UINT8 rsa_exponent[HAB_MAX_EXP_SIZE]; /* RSA public exponent */ ++ UINT8 *rsa_modulus; /* RSA modulus pointer */ ++ hab_int_length exponent_size; /* Exponent size in bytes */ ++ hab_int_length modulus_size; /* Modulus size in bytes */ ++ BOOLEAN init_flag; /* Indicates if key initialised */ ++} hab_rsa_public_key; ++ ++/*================================================================================================== ++ GLOBAL VARIABLE DECLARATIONS ++==================================================================================================*/ ++/* Super Root keys */ ++extern const hab_rsa_public_key hab_super_root_key[]; ++ ++/*================================================================================================== ++ FUNCTION PROTOTYPES ++==================================================================================================*/ ++ ++/*================================================================================================*/ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/*================================================================================================== ++ LOCAL FUNCTION PROTOTYPES ++ =================================================================================================*/ ++ ++/*================================================================================================== ++ LOCAL CONSTANTS ++ =================================================================================================*/ ++ ++/*================================================================================================== ++ LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) ++ =================================================================================================*/ ++ ++/*================================================================================================== ++ LOCAL MACROS ++ =================================================================================================*/ ++ ++/*================================================================================================== ++ LOCAL VARIABLES ++ =================================================================================================*/ ++ ++/*================================================================================================== ++ GLOBAL VARIABLES ++ =================================================================================================*/ ++ ++/* Super Root key moduli */ ++const UINT8 hab_super_root_moduli[] = { ++ ++ ++ /* modulus data */ ++ 0xb9, 0x84, 0xc8, 0x8a, 0xd3, 0x7e, 0xcc, 0xc0, 0xe7, 0x3e, 0x11, 0x53, ++ 0x6b, 0x5e, 0xea, 0xf4, 0xd9, 0xac, 0x5a, 0x63, 0x8a, 0x79, 0x96, 0x83, ++ 0xb1, 0x39, 0xb2, 0x6f, 0x9c, 0x54, 0x87, 0xf4, 0x3b, 0x9e, 0xd8, 0x0f, ++ 0x89, 0xf5, 0x01, 0x53, 0xb8, 0xe2, 0xcc, 0x75, 0x0d, 0xe1, 0x13, 0xfa, ++ 0xa7, 0xb9, 0x1e, 0xff, 0x6a, 0x05, 0xdb, 0x58, 0x10, 0xbf, 0x2b, 0xf4, ++ 0xe7, 0x0a, 0x63, 0x82, 0x2c, 0xa3, 0xb5, 0x0a, 0x72, 0x1c, 0xdc, 0x29, ++ 0xc1, 0x81, 0xb5, 0x9a, 0xf0, 0x25, 0x7d, 0xd6, 0xee, 0x01, 0x64, 0xc7, ++ 0x07, 0x2d, 0xcb, 0x31, 0x4c, 0x8d, 0x82, 0xf6, 0x44, 0x95, 0x4a, 0xbc, ++ 0xae, 0xe8, 0x2a, 0x89, 0xd4, 0xf2, 0x66, 0x72, 0x2b, 0x09, 0x4e, 0x56, ++ 0xe9, 0xbf, 0x5e, 0x38, 0x5c, 0xd5, 0x7e, 0x15, 0x55, 0x86, 0x0f, 0x19, ++ 0xf6, 0x00, 0xee, 0xa1, 0x92, 0x78, 0xef, 0x93, 0xcb, 0xfa, 0xb4, 0x98, ++ 0x19, 0xef, 0x10, 0x70, 0xde, 0x36, 0x1c, 0x12, 0x2e, 0xd2, 0x09, 0xc7, ++ 0x7b, 0xd1, 0xaa, 0xd3, 0x46, 0x65, 0xa1, 0x5b, 0xee, 0xa5, 0x96, 0x97, ++ 0x98, 0x3e, 0xfc, 0xf8, 0x74, 0x22, 0x51, 0xe7, 0xf1, 0x2f, 0x30, 0x79, ++ 0x13, 0xe5, 0x42, 0xc6, 0x7c, 0x18, 0x76, 0xd3, 0x7f, 0x5a, 0x13, 0xde, ++ 0x2f, 0x51, 0x07, 0xfa, 0x93, 0xfe, 0x10, 0x8a, 0x0c, 0x18, 0x60, 0x3c, ++ 0xff, 0x6a, 0x9b, 0xe7, 0x10, 0x2d, 0x71, 0xd2, 0x34, 0xc0, 0xdf, 0xbe, ++ 0x17, 0x4e, 0x75, 0x40, 0x83, 0xaa, 0x90, 0xd1, 0xed, 0xbd, 0xbf, 0xac, ++ 0x9a, 0x30, 0xbd, 0x69, 0x4d, 0xd8, 0x00, 0x63, 0x92, 0x69, 0x98, 0xf8, ++ 0x89, 0xdc, 0x7b, 0xe3, 0x66, 0x7e, 0xdd, 0xfa, 0x8c, 0x74, 0xe2, 0xb1, ++ 0xeb, 0x94, 0xf7, 0xab, 0x0e, 0x92, 0x06, 0xab, 0x60, 0xe5, 0x00, 0x43, ++ 0xb2, 0x5e, 0x6e, 0xeb ++ ++ ++}; ++ ++ ++/* Super Root key */ ++const hab_rsa_public_key hab_super_root_key[] = { ++ ++{ ++ { /* RSA public exponent, right-padded */ ++ 0x01, 0x00, 0x01, 0x00}, ++ /* pointer to modulus data */ ++ (UINT8 *)&hab_super_root_moduli[0], ++ /* Exponent size in bytes */ ++ 0x03, ++ /* Modulus size in bytes */ ++ 0x100, ++ /* Key data valid */ ++ TRUE ++} ++ ++}; ++ ++/*================================================================================================== ++ LOCAL FUNCTIONS ++==================================================================================================*/ ++ ++/*================================================================================================== ++ GLOBAL FUNCTIONS ++==================================================================================================*/ ++ ++/*================================================================================================*/ ++#endif /* HAB_SUPER_ROOT_H */ +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/soc_misc.c redboot-imx-200952/packages/hal/arm/mx51/var/current/src/soc_misc.c +--- redboot-imx-200952~/packages/hal/arm/mx51/var/current/src/soc_misc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/var/current/src/soc_misc.c 2010-01-26 17:35:50.062962128 +0000 +@@ -0,0 +1,688 @@ ++//========================================================================== ++// ++// soc_misc.c ++// ++// HAL misc board support code ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================*/ ++ ++#include ++#include ++#include ++#include CYGBLD_HAL_PLATFORM_H ++ ++#include // base types ++#include // tracing macros ++#include // assertion macros ++ ++#include // Size constants ++#include // IO macros ++#include // Register state info ++#include ++#include // Interrupt names ++#include // Cache control ++#include // Hardware definitions ++#include // MMap table definitions ++#ifdef MXCFLASH_SELECT_MMC ++#include ++#endif ++#include // diag_printf ++#ifdef CYGPKG_DEVS_ETH_FEC ++#include ++#endif ++#ifdef MXCFLASH_SELECT_NAND ++#include ++#endif ++ ++// Most initialization has already been done before we get here. ++// All we do here is set up the interrupt environment. ++// FIXME: some of the stuff in hal_platform_setup could be moved here. ++ ++externC void plf_hardware_init(void); ++int _mxc_fis; ++ ++/* ++ * System_rev will have the following format ++ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc) ++ * 11-8 = unused ++ * 7-4 = major (1.y) ++ * 3-0 = minor (x.0) ++ */ ++unsigned int system_rev = CHIP_REV_1_0; ++static int find_correct_chip; ++extern char HAL_PLATFORM_EXTRA[40]; ++ ++static int _reset_reason; ++ ++struct soc_sbmr { ++ unsigned int bt_mem_ctl:2, ++ bt_bus_width:1, ++ bt_page_size:2, ++ rsv2:1, ++ bt_spare_size:1, ++ bt_mem_type:2, ++ rsv1:1, ++ bt_ecc_sel:1, ++ bt_usb_src_0:1, ++ bt_eeprom_cfg:1, ++ dir_bt_dis:1, ++ bmod:2, ++ bt_weim_muxed:2, ++ bt_spare:1, ++ bt_sdmmc_src:2, ++ bt_chih_freq_sel:2, ++ bt_i2c_src:2, ++ bt_uart_src:2, ++ bt_cspi_src:2, ++ rsv0:3; ++} __attribute__ ((packed)); ++struct soc_sbmr *soc_sbmr = (struct soc_sbmr *) (SRC_BASE_ADDR + 0x4); ++/* ++ * This functions reads the IIM module and returns the system revision number. ++ * It returns the IIM silicon revision reg value if valid product rev is found. ++ . Otherwise, it returns -1. ++ */ ++static int read_system_rev(void) ++{ ++ int val; ++ int *rom_id_address; ++ ++ rom_id_address = ROM_BASE_ADDRESS_VIRT + ROM_SI_REV_OFFSET; ++ ++ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF); ++ ++ system_rev = 0x51 << PART_NUMBER_OFFSET; /* For MX51 Platform*/ ++ ++ /* Now trying to retrieve the silicon rev from IIM's SREV register */ ++ return *rom_id_address; ++} ++ ++#ifdef MXCFLASH_SELECT_NAND ++unsigned int mxc_nfc_soc_setup(flash_dev_info_t* flash_params, unsigned int num_of_chips); ++extern nfc_setup_func_t *nfc_setup; ++#endif ++ ++#ifdef CYGPKG_DEVS_ETH_FEC ++extern int read_mac_addr_from_fuse(unsigned char* data); ++extern mxc_fec_read_mac_from_fuse *get_mac_addr; ++#endif ++ ++#ifdef MXCFLASH_SELECT_MMC ++extern mxc_mmc_check_sdhc_boot_slot *check_sdhc_slot; ++#endif ++ ++int mxc_check_sdhc_boot_slot(unsigned int port, unsigned int *sdhc_addr); ++ ++void hal_hardware_init(void) ++{ ++ int ver = read_system_rev(); ++ unsigned int i; ++ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR; ++ ++ _reset_reason = readl(SRC_BASE_ADDR + 0x8); ++ switch (*fis_addr) { ++ case FROM_MMC_FLASH: ++ _mxc_fis = FROM_MMC_FLASH; ++ break; ++ case FROM_NAND_FLASH: ++ _mxc_fis = FROM_NAND_FLASH; ++ break; ++ case FROM_SPI_NOR_FLASH: ++ _mxc_fis = FROM_SPI_NOR_FLASH; ++ break; ++ default: ++ if (soc_sbmr->bt_mem_ctl == 0x3) { ++ if (soc_sbmr->bt_mem_type == 0) { ++ _mxc_fis = MMC_FLASH_BOOT; ++ *fis_addr = FROM_MMC_FLASH; ++ } else if (soc_sbmr->bt_mem_type == 3) { ++ _mxc_fis = SPI_NOR_FLASH_BOOT; ++ *fis_addr = FROM_SPI_NOR_FLASH; ++ } ++ } else if (soc_sbmr->bt_mem_ctl == 1) { ++ _mxc_fis = NAND_FLASH_BOOT; ++ *fis_addr = FROM_NAND_FLASH; ++ } ++ } ++ ++ find_correct_chip = ver; ++ ++ if (ver != CHIP_VERSION_NONE) { ++ /* Valid product revision found. Check actual silicon rev from the ROM code. */ ++ if (ver == 0x1) { ++ HAL_PLATFORM_EXTRA[5] = '1'; ++ HAL_PLATFORM_EXTRA[7] = '0'; ++ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/ ++ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ ++ } else if (ver == 0x2) { ++ HAL_PLATFORM_EXTRA[5] = '1'; ++ HAL_PLATFORM_EXTRA[7] = '1'; ++ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/ ++ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/ ++ } else if (ver == 0x10) { ++ HAL_PLATFORM_EXTRA[5] = '2'; ++ HAL_PLATFORM_EXTRA[7] = '0'; ++ system_rev |= 2 << MAJOR_NUMBER_OFFSET; /*Major Number*/ ++ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ ++ } else if (ver == 0x20) { ++ HAL_PLATFORM_EXTRA[5] = '3'; ++ HAL_PLATFORM_EXTRA[7] = '0'; ++ system_rev |= 3 << MAJOR_NUMBER_OFFSET; /*Major Number*/ ++ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ ++ } else { ++ HAL_PLATFORM_EXTRA[5] = 'x'; ++ HAL_PLATFORM_EXTRA[7] = 'x'; ++ system_rev |= 3 << MAJOR_NUMBER_OFFSET; /*Major Number*/ ++ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ ++ find_correct_chip = CHIP_VERSION_UNKNOWN; ++ } ++ ++ } ++ // Enable caches ++ HAL_ICACHE_ENABLE(); ++ HAL_DCACHE_ENABLE(); ++ ++ // enable EPIT and start it with 32KHz input clock ++ writel(0x00010000, EPIT_BASE_ADDR + EPITCR); ++ ++ // make sure reset is complete ++ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) { ++ } ++ ++ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR); ++ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR); ++ ++ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0 ++ ++ if ((readw(WDOG_BASE_ADDR) & 4) != 0) { ++ // increase the WDOG timeout value to the max ++ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR); ++ } ++ ++ // Perform any platform specific initializations ++ plf_hardware_init(); ++ ++ // Set up eCos/ROM interfaces ++ hal_if_init(); ++ ++ // initial NAND setup ++ writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD4_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD5_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD6_REG); ++ writel(0xFFFF0000, UNLOCK_BLK_ADD7_REG); ++ ++ // unlock all the CS's ++ for (i = 0; i < 8; i++) { ++ writel(0x84 | (i << 3), NFC_WR_PROT_REG); ++ } ++ writel(0, NFC_IPC_REG); ++#ifdef MXCFLASH_SELECT_NAND ++ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup; ++#endif ++ ++#ifdef CYGPKG_DEVS_ETH_FEC ++ get_mac_addr = (mxc_fec_read_mac_from_fuse *)read_mac_addr_from_fuse; ++#endif ++ ++#ifdef MXCFLASH_SELECT_MMC ++ check_sdhc_slot = (mxc_mmc_check_sdhc_boot_slot *)mxc_check_sdhc_boot_slot; ++#endif ++} ++ ++// ------------------------------------------------------------------------- ++void hal_clock_initialize(cyg_uint32 period) ++{ ++} ++ ++// This routine is called during a clock interrupt. ++ ++// Define this if you want to ensure that the clock is perfect (i.e. does ++// not drift). One reason to leave it turned off is that it costs some ++// us per system clock interrupt for this maintenance. ++#undef COMPENSATE_FOR_CLOCK_DRIFT ++ ++void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) ++{ ++} ++ ++// Read the current value of the clock, returning the number of hardware ++// "ticks" that have occurred (i.e. how far away the current value is from ++// the start) ++ ++// Note: The "contract" for this function is that the value is the number ++// of hardware clocks that have happened since the last interrupt (i.e. ++// when it was reset). This value is used to measure interrupt latencies. ++// However, since the hardware counter runs freely, this routine computes ++// the difference between the current clock period and the number of hardware ++// ticks left before the next timer interrupt. ++void hal_clock_read(cyg_uint32 *pvalue) ++{ ++} ++ ++// This is to cope with the test read used by tm_basic with ++// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP ++// in the ISR, *before* resetting the clock. Which returns 1tick + ++// latency if we just use plain hal_clock_read(). ++void hal_clock_latency(cyg_uint32 *pvalue) ++{ ++} ++ ++unsigned int hal_timer_count(void) ++{ ++ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR)); ++} ++ ++#define WDT_MAGIC_1 0x5555 ++#define WDT_MAGIC_2 0xAAAA ++#define MXC_WDT_WSR 0x2 ++ ++unsigned int i2c_base_addr[] = { ++ I2C_BASE_ADDR, ++ I2C2_BASE_ADDR, ++}; ++unsigned int i2c_num = 2; ++ ++// ++// Delay for some number of micro-seconds ++// ++void hal_delay_us(unsigned int usecs) ++{ ++ /* ++ * This causes overflow. ++ * unsigned int delayCount = (usecs * 32768) / 1000000; ++ * So use the following one instead ++ */ ++ unsigned int delayCount = (usecs * 512) / 15625; ++ ++ if (delayCount == 0) { ++ return; ++ } ++ ++ // issue the service sequence instructions ++ if ((readw(WDOG_BASE_ADDR) & 4) != 0) { ++ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR); ++ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR); ++ } ++ ++ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit ++ ++ writel(delayCount, EPIT_BASE_ADDR + EPITLR); ++ ++ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set ++} ++ ++// ------------------------------------------------------------------------- ++ ++// This routine is called to respond to a hardware interrupt (IRQ). It ++// should interrogate the hardware and return the IRQ vector number. ++int hal_IRQ_handler(void) ++{ ++#ifdef HAL_EXTENDED_IRQ_HANDLER ++ cyg_uint32 index; ++ ++ // Use platform specific IRQ handler, if defined ++ // Note: this macro should do a 'return' with the appropriate ++ // interrupt number if such an extended interrupt exists. The ++ // assumption is that the line after the macro starts 'normal' processing. ++ HAL_EXTENDED_IRQ_HANDLER(index); ++#endif ++ ++ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen! ++} ++ ++// ++// Interrupt control ++// ++ ++void hal_interrupt_mask(int vector) ++{ ++// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector); ++#ifdef HAL_EXTENDED_INTERRUPT_MASK ++ // Use platform specific handling, if defined ++ // Note: this macro should do a 'return' for "extended" values of 'vector' ++ // Normal vectors are handled by code subsequent to the macro call. ++ HAL_EXTENDED_INTERRUPT_MASK(vector); ++#endif ++} ++ ++void hal_interrupt_unmask(int vector) ++{ ++// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector); ++ ++#ifdef HAL_EXTENDED_INTERRUPT_UNMASK ++ // Use platform specific handling, if defined ++ // Note: this macro should do a 'return' for "extended" values of 'vector' ++ // Normal vectors are handled by code subsequent to the macro call. ++ HAL_EXTENDED_INTERRUPT_UNMASK(vector); ++#endif ++} ++ ++void hal_interrupt_acknowledge(int vector) ++{ ++ ++// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector); ++#ifdef HAL_EXTENDED_INTERRUPT_UNMASK ++ // Use platform specific handling, if defined ++ // Note: this macro should do a 'return' for "extended" values of 'vector' ++ // Normal vectors are handled by code subsequent to the macro call. ++ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector); ++#endif ++} ++ ++void hal_interrupt_configure(int vector, int level, int up) ++{ ++ ++#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE ++ // Use platform specific handling, if defined ++ // Note: this macro should do a 'return' for "extended" values of 'vector' ++ // Normal vectors are handled by code subsequent to the macro call. ++ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up); ++#endif ++} ++ ++void hal_interrupt_set_level(int vector, int level) ++{ ++ ++#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL ++ // Use platform specific handling, if defined ++ // Note: this macro should do a 'return' for "extended" values of 'vector' ++ // Normal vectors are handled by code subsequent to the macro call. ++ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level); ++#endif ++ ++ // Interrupt priorities are not configurable. ++} ++ ++#ifdef MXCFLASH_SELECT_NAND ++unsigned int mxc_nfc_soc_setup(flash_dev_info_t *flash_params, unsigned int num_of_chips) ++{ ++ unsigned int src_scr_reg; ++ unsigned int tmp; ++ ++ tmp = readl(NFC_FLASH_CONFIG2_REG); ++ /* Set the ST_CMD to be 0x70 for all NAND devices */ ++ tmp &= ~(0xFF << 24); ++ tmp |= (0x70 << 24); ++ /* Set the Spare size */ ++ tmp &= ~(0xFF << 16); ++ tmp |= (((flash_params->spare_size & 0xFF) / 2) << 16); ++ /* Set the Page Size */ ++ tmp &= ~(0x3); ++ switch(flash_params->page_size) { ++ case 512: ++ tmp |= 0x0; ++ break; ++ case 2048: ++ tmp |= 0x1; ++ break; ++ case 4096: ++ default: ++ tmp |= 0x2; ++ break; ++ } ++ /* Set ECC mode */ ++ if (flash_params->spare_size >= 218) { ++ /* Use 8-bit ECC */ ++ tmp |= (0x1 << 6); ++ } else { ++ tmp &= ~(0x1 << 6); ++ } ++ /* Pages per block */ ++ tmp &= ~(0x3 << 7); ++ switch(flash_params->pages_per_block) { ++ case 32: ++ tmp |= 0x0; ++ break; ++ case 64: ++ tmp |= (0x1 << 7); ++ break; ++ case 128: ++ tmp |= (0x2 << 7); ++ break; ++ case 256: ++ default: ++ tmp |= (0x3 << 7); ++ break; ++ } ++ /* Set the number of phase bits & ECC enable bit to default value */ ++ tmp &= ~(0x3 << 12); ++ tmp |= 0x2038; ++ writel(tmp, NFC_FLASH_CONFIG2_REG); ++ ++ tmp = readl(NFC_FLASH_CONFIG3_REG); ++ /* Set the No SDMA bit */ ++ tmp |= (0x1 << 20); ++ /* Set the Status Busy Bit to 0x6 (default) */ ++ tmp &= ~(0x7 << 8); ++ tmp |= (0x6 << 8); ++ /* Set the Flash Width */ ++ if (flash_params->port_size == MXC_NAND_16_BIT) { ++ tmp &= (~(1 << 3)); ++ } else { ++ tmp |= (1 << 3); ++ } ++ /* Set the Number of Nand Chips */ ++ tmp &= ~(0x7 << 12); ++ tmp |= ((num_of_chips -1) << 12); ++ if (num_of_chips > 1) ++ tmp |= 0x1; ++ writel(tmp, NFC_FLASH_CONFIG3_REG); ++ ++ ++ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) { ++ /* This issue is fixed in MX51 TO 3.0 */ ++ /* Workaround to disable WARM RESET when booting from interleaved NAND devices */ ++ if ((num_of_chips > 1) && (soc_sbmr->bt_mem_ctl == 1)) { ++ src_scr_reg = readl(SRC_BASE_ADDR); ++ src_scr_reg &= ~0x1; ++ writel(src_scr_reg, SRC_BASE_ADDR); ++ } ++ } ++ ++ return 0x30; ++} ++#endif ++ ++int mxc_check_sdhc_boot_slot(unsigned int port, unsigned int *sdhc_addr) ++{ ++ unsigned int bt_sdmmc_src = 0; ++ int ret = 1; ++ ++ if (port != READ_PORT_FROM_FUSE) { ++ bt_sdmmc_src = port; ++ } else { ++ bt_sdmmc_src = soc_sbmr->bt_sdmmc_src; ++ } ++ ++ switch(bt_sdmmc_src){ ++ case 0x0: ++ *sdhc_addr = MMC_SDHC1_BASE_ADDR; ++ break; ++ case 0x1: ++ *sdhc_addr = MMC_SDHC2_BASE_ADDR; ++ break; ++ case 0x2: ++ *sdhc_addr = MMC_SDHC3_BASE_ADDR; ++ break; ++ case 0x3: ++ *sdhc_addr = MMC_SDHC4_BASE_ADDR; ++ break; ++ default: ++ ret = 0; ++ } ++ ++ if ((ret == 1) && (port == READ_PORT_FROM_FUSE)) { ++ diag_printf("Booting from SDHC%d\n", bt_sdmmc_src); ++ } else if (ret == 0) { ++ diag_printf("Invalid SD port number %d\n", port); ++ } ++ ++ return ret; ++} ++ ++static void show_sys_info(void) ++{ ++ if (find_correct_chip == CHIP_VERSION_UNKNOWN) { ++ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev()); ++ diag_printf("Assuming chip version=0x%x\n", system_rev); ++ } else if (find_correct_chip == CHIP_VERSION_NONE) { ++ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF)); ++ } ++ ++ diag_printf("Reset reason: "); ++ switch (_reset_reason) { ++ case 0x09: ++ diag_printf("User reset\n"); ++ break; ++ case 0x01: ++ diag_printf("Power-on reset\n"); ++ break; ++ case 0x10: ++ case 0x11: ++ diag_printf("WDOG reset\n"); ++ break; ++ default: ++ diag_printf("Unknown: 0x%x\n", _reset_reason); ++ } ++ ++ if (_mxc_fis == MMC_FLASH_BOOT) { ++ diag_printf("fis/fconfig from MMC\n"); ++ } else if (_mxc_fis == SPI_NOR_FLASH_BOOT) { ++ diag_printf("fis/fconfig from SPI-NOR\n"); ++ } else if (_mxc_fis == NAND_FLASH_BOOT) { ++ diag_printf("fis/fconfig from NAND\n"); ++ } else { ++ diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n"); ++ } ++ ++ //diag_printf("SBMR = 0x%x\n", readl(SRC_BASE_ADDR + 0x4)); ++ diag_printf("Boot switch: "); ++ if (soc_sbmr->bmod == 0) { ++ diag_printf("INTERNAL\n"); ++ } else if (soc_sbmr->bmod == 3){ ++ diag_printf("BOOTSTRAP\n"); ++ } else if (soc_sbmr->bmod == 0x1 && soc_sbmr->dir_bt_dis == 0) { ++ diag_printf("TEST EXEC\n"); ++ } else { ++ diag_printf("UNKNOWN\n"); ++ } ++ diag_printf("\t"); ++ if (soc_sbmr->bt_mem_ctl == 0) { ++ diag_printf("WEIM: "); ++ if (soc_sbmr->bt_mem_type == 0) { ++ diag_printf("NOR"); ++ } else if (soc_sbmr->bt_mem_type == 2) { ++ diag_printf("ONE NAND"); ++ } else { ++ diag_printf("UNKNOWN"); ++ } ++ } else if (soc_sbmr->bt_mem_ctl == 1) { ++ diag_printf("NAND: ADDR CYCLES:"); ++ if (soc_sbmr->bt_mem_type == 0) { ++ diag_printf("3: "); ++ } else if (soc_sbmr->bt_mem_type == 1) { ++ diag_printf("4: "); ++ } else if (soc_sbmr->bt_mem_type == 2) { ++ diag_printf("5: "); ++ } else { ++ diag_printf("UNKNOWN: "); ++ } ++ if (soc_sbmr->bt_ecc_sel == 0) { ++ diag_printf("SLC: "); ++ } else { ++ diag_printf("MLC: "); ++ } ++ if (soc_sbmr->bt_spare_size == 0) { ++ diag_printf("128B spare (4-bit ECC): "); ++ } else { ++ diag_printf("218B spare (8-bit ECC): "); ++ } ++ diag_printf("PAGE SIZE: "); ++ if (soc_sbmr->bt_page_size == 0) { ++ diag_printf("512: "); ++ } else if (soc_sbmr->bt_page_size == 1) { ++ diag_printf("2K: "); ++ } else if (soc_sbmr->bt_page_size == 2) { ++ diag_printf("4K: "); ++ } else { ++ diag_printf("UNKNOWN: "); ++ } ++ diag_printf("BUS WIDTH: "); ++ if (soc_sbmr->bt_bus_width == 0) { ++ diag_printf("8"); ++ } else { ++ diag_printf("16"); ++ } ++ } else if (soc_sbmr->bt_mem_ctl == 3) { ++ diag_printf("EXPANSION: "); ++ if (soc_sbmr->bt_mem_type == 0) { ++ diag_printf("SD/MMC-%d", soc_sbmr->bt_sdmmc_src); ++ } else if (soc_sbmr->bt_mem_type == 2) { ++ diag_printf("I2C-NOR: "); ++ if (soc_sbmr->bt_sdmmc_src == 0) { ++ diag_printf("I2C-1"); ++ } else if (soc_sbmr->bt_sdmmc_src == 1) { ++ diag_printf("I2C-2"); ++ } else if (soc_sbmr->bt_sdmmc_src == 2) { ++ diag_printf("HS-I2C"); ++ } else { ++ diag_printf("UNKNOWN"); ++ } ++ } else if (soc_sbmr->bt_mem_type == 3) { ++ diag_printf("SPI-NOR: "); ++ if (soc_sbmr->bt_sdmmc_src == 0) { ++ diag_printf("eCSPI1"); ++ } else if (soc_sbmr->bt_sdmmc_src == 1) { ++ diag_printf("eCSPI2"); ++ } else if (soc_sbmr->bt_sdmmc_src == 2) { ++ diag_printf("CSPI"); ++ } else { ++ diag_printf("UNKNOWN"); ++ } ++ } else { ++ diag_printf("UNKNOWN"); ++ } ++ } else { ++ diag_printf("UNKNOWN"); ++ } ++ diag_printf("\n"); ++} ++ ++RedBoot_init(show_sys_info, RedBoot_INIT_LAST); --- redboot-imx-200952.orig/debian/patches/00list +++ redboot-imx-200952/debian/patches/00list @@ -0,0 +1,3 @@ +01_freescale_imx_base +02_freescale_imx51 +03_build_fixups --- redboot-imx-200952.orig/debian/patches/03_build_fixups.dpatch +++ redboot-imx-200952/debian/patches/03_build_fixups.dpatch @@ -0,0 +1,65 @@ +#! /bin/sh /usr/share/dpatch/dpatch-run +## 03_build_fixups.dpatch by +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: No description. + +@DPATCH@ +diff -urNad redboot-imx-200952~/packages/hal/arm/arch/current/src/arm.ld redboot-imx-200952/packages/hal/arm/arch/current/src/arm.ld +--- redboot-imx-200952~/packages/hal/arm/arch/current/src/arm.ld 2010-01-26 17:58:08.682964376 +0000 ++++ redboot-imx-200952/packages/hal/arm/arch/current/src/arm.ld 2010-01-26 17:58:18.232993505 +0000 +@@ -42,11 +42,7 @@ + STARTUP(vectors.o) + ENTRY(reset_vector) + INPUT(extras.o) +-#if (__GNUC__ >= 3) +-GROUP(libtarget.a libgcc.a libsupc++.a) +-#else +-GROUP(libtarget.a libgcc.a) +-#endif ++GROUP(libtarget.a libgcc.a libsupc++.a libc.a libgcc_eh.a) + + #if defined(__ARMEB__) + OUTPUT_FORMAT(elf32-bigarm) +@@ -109,7 +105,7 @@ + { _stext = ABSOLUTE(.); \ + PROVIDE (__stext = ABSOLUTE(.)); \ + *(.text*) *(i.*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \ +- *(.glue_7) *(.glue_7t) \ ++ *(.glue_7) *(.glue_7t) *(.note.gnu.build-id) \ + } > _region_ \ + _etext = .; PROVIDE (__etext = .); + +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl redboot-imx-200952/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl 2010-01-26 17:58:08.972961886 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/cdl/hal_arm_board.cdl 2010-01-26 17:58:43.232979872 +0000 +@@ -165,7 +165,7 @@ + display "Global compiler flags" + flavor data + no_define +- default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } ++ default_value { "-mcpu=cortex-a8 -marm -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -fno-stack-protector" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define +@@ -327,8 +327,6 @@ + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf +- $(OBJCOPY) --strip-debug $< $(@:.bin=.img) +- $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } +diff -urNad redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi +--- redboot-imx-200952~/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi 2010-01-26 17:58:08.972961886 +0000 ++++ redboot-imx-200952/packages/hal/arm/mx51/babbage/current/include/pkgconf/mlt_arm_board_romram.ldi 2010-01-26 17:58:18.242997755 +0000 +@@ -27,5 +27,8 @@ + SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + SECTIONS_END + } --- redboot-imx-200952.orig/debian/patches/01_freescale_imx_base.dpatch +++ redboot-imx-200952/debian/patches/01_freescale_imx_base.dpatch @@ -0,0 +1,137261 @@ +#! /bin/sh /usr/share/dpatch/dpatch-run +## 01_freescale_imx_base.dpatch by +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: No description. + +@DPATCH@ +diff -urNad redboot-imx-200952~/packages/compat/posix/current/tests/mqueue1.c redboot-imx-200952/packages/compat/posix/current/tests/mqueue1.c +--- redboot-imx-200952~/packages/compat/posix/current/tests/mqueue1.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/compat/posix/current/tests/mqueue1.c 2010-01-26 17:33:11.892955130 +0000 +@@ -0,0 +1,359 @@ ++/*======================================================================== ++// ++// mqueue1.c ++// ++// POSIX Message queues tests ++// ++//======================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//======================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): jlarmour ++// Contributors: ++// Date: 2000-05-18 ++// Purpose: This file provides tests for POSIX mqueues ++// Description: ++// Usage: ++// ++//####DESCRIPTIONEND#### ++// ++//====================================================================== ++*/ ++ ++/* CONFIGURATION */ ++ ++#include ++ ++#ifndef CYGPKG_POSIX_MQUEUES ++# define NA_MSG "Message queues not configured" ++#endif ++ ++#ifdef NA_MSG ++#include // test API ++void ++cyg_user_start(void) ++{ ++ CYG_TEST_NA( NA_MSG ); ++} ++ ++#else ++ ++/* INCLUDES */ ++ ++#include // O_* ++#include // errno ++#include // file modes ++#include // Mqueue Header ++#include // test API ++ ++/* FUNCTIONS */ ++ ++static int ++my_memcmp(const void *m1, const void *m2, size_t n) ++{ ++ char *s1 = (char *)m1; ++ char *s2 = (char *)m2; ++ ++ while (n--) { ++ if (*s1 != *s2) ++ return *s1 - *s2; ++ s1++; ++ s2++; ++ } ++ return 0; ++} // my_memcmp() ++ ++//************************************************************************ ++ ++int ++main(void) ++{ ++ mqd_t q1, q2; ++ char buf[20]; ++ ssize_t recvlen; ++ unsigned int prio; ++ struct mq_attr attr, oattr; ++ mode_t mode; ++ int err; ++ ++ CYG_TEST_INIT(); ++ CYG_TEST_INFO( "Starting POSIX message test 1" ); ++ ++ q1 = mq_open( "/mq1", O_RDWR ); ++ CYG_TEST_PASS_FAIL( q1 == (mqd_t)-1, "error for non-existent queue" ); ++ CYG_TEST_PASS_FAIL( ENOENT == errno, ++ "errno correct for non-existent queue" ); ++ ++ attr.mq_flags = 0; ++ attr.mq_maxmsg = 4; ++ attr.mq_msgsize = 20; ++ mode = S_IRWXU|S_IRWXG|S_IRWXO; // rwx for all ++ ++ q1 = mq_open( "/mq1", O_CREAT|O_NONBLOCK|O_WRONLY, mode, &attr ); ++ CYG_TEST_PASS_FAIL( q1 != (mqd_t)-1, "simple mq_open (write only)" ); ++ ++ err = mq_getattr( q1, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY != (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY == (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (0 == attr.mq_curmsgs ), "getattr attributes correct" ); ++ ++ err = mq_send( q1, "Vik is brill", sizeof("Vik is brill"), 10 ); ++ ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_send" ); ++ ++ err = mq_getattr( q1, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr after send" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY != (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY == (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (1 == attr.mq_curmsgs ), ++ "getattr attributes correct #2" ); ++ ++ q2 = mq_open( "/mq1", O_RDONLY|O_CREAT|O_EXCL ); ++ CYG_TEST_PASS_FAIL( q2 == (mqd_t)-1, ++ "error for exclusive open of existing queue" ); ++ CYG_TEST_PASS_FAIL( EEXIST == errno, ++ "errno correct for exclusive open of existing queue" ); ++ ++ q2 = mq_open( "/mq1", O_RDONLY ); ++ CYG_TEST_PASS_FAIL( q2 != (mqd_t)-1, "simple mq_open (read only)" ); ++ ++ err = mq_getattr( q2, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr, different mqd_t" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK != (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY == (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY != (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (1 == attr.mq_curmsgs ), ++ "getattr attributes correct #3" ); ++ ++ err = mq_close( q2 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_close" ); ++ ++ q2 = mq_open( "/mq1", O_RDONLY ); ++ CYG_TEST_PASS_FAIL( q2 != (mqd_t)-1, "mq_open reopen (read only)" ); ++ ++ err = mq_getattr( q2, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr, different mqd_t" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK != (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY == (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY != (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (1 == attr.mq_curmsgs ), ++ "getattr attributes correct #4" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == sizeof("Vik is brill"), ++ "receive message length" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "Vik is brill", ++ sizeof("Vik is brill")), ++ "received message data intact" ); ++ CYG_TEST_PASS_FAIL( 10 == prio, "received at correct priority" ); ++ ++ err = mq_getattr( q1, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr after send" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY != (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY == (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (0 == attr.mq_curmsgs ), ++ "getattr attributes correct #5" ); ++ ++ attr.mq_flags |= O_NONBLOCK; ++ err = mq_setattr( q2, &attr, &oattr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_setattr O_NONBLOCK" ); ++ CYG_TEST_PASS_FAIL( (4 == oattr.mq_maxmsg) && ++ (20 == oattr.mq_msgsize) && ++ (O_NONBLOCK != (oattr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY == (oattr.mq_flags & O_RDONLY)) && ++ (O_WRONLY != (oattr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (oattr.mq_flags & O_RDWR)) && ++ (0 == oattr.mq_curmsgs ), ++ "old attribute correct" ); ++ err = mq_getattr( q2, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_getattr after O_NONBLOCK" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY == (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY != (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (0 == attr.mq_curmsgs ), ++ "new attribute correct" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == (ssize_t)-1, ++ "mq_receive, empty buffer, non-blocking" ); ++ CYG_TEST_PASS_FAIL( EAGAIN == errno, ++ "errno correct for non-blocking" ); ++ ++ err = mq_send( q2, "foo", sizeof("foo"), 1 ); ++ CYG_TEST_PASS_FAIL( -1 == err, "error on mq_send on read-only descriptor" ); ++ CYG_TEST_PASS_FAIL( EBADF == errno, ++ "errno correct for mq_send on r/o descriptor" ); ++ ++ err = mq_send( q2, "supercalifragilisticexpealidocious", 21, 2 ); ++ CYG_TEST_PASS_FAIL( -1 == err, "error on mq_send (message too long)" ); ++ CYG_TEST_PASS_FAIL( EMSGSIZE == errno, ++ "errno correct for mq_send (message too long)" ); ++ ++ err = mq_send( q1, "", sizeof(""), 5 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send \"\"" ); ++ ++ err = mq_send( q1, "I love Vik", sizeof("I love Vik"), 7 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send (different priority)" ); ++ ++ err = mq_send( q1, "a lot!", sizeof("a lot!"), 7 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send (same priority)" ); ++ ++ err = mq_send( q1, "Vik is a babe", sizeof("Vik is a babe"), 6 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send (middle priority)" ); ++ ++ err = mq_send( q1, "wibble", sizeof("wibble"), 6 ); ++ CYG_TEST_PASS_FAIL( -1 == err, "error on mq_send with full queue" ); ++ CYG_TEST_PASS_FAIL( EAGAIN == errno, ++ "errno correct for mq_send full queue" ); ++ ++ err = mq_getattr( q2, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_getattr after sends" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDONLY == (attr.mq_flags & O_RDONLY)) && ++ (O_WRONLY != (attr.mq_flags & O_WRONLY)) && ++ (O_RDWR != (attr.mq_flags & O_RDWR)) && ++ (4 == attr.mq_curmsgs ), ++ "getattr attributes correct #5" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == sizeof("I love Vik"), ++ "receive message length (prioritized) #1" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "I love Vik", ++ sizeof("I love Vik")), ++ "received message data intact (prioritized) #1" ); ++ CYG_TEST_PASS_FAIL( 7 == prio, ++ "received at correct priority (prioritized) #1" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == sizeof("a lot!"), ++ "receive message length (prioritized) #2" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "a lot!", ++ sizeof("a lot!")), ++ "received message data intact (prioritized) #2" ); ++ CYG_TEST_PASS_FAIL( 7 == prio, ++ "received at correct priority (prioritized) #2" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == sizeof("Vik is a babe"), ++ "receive message length (prioritized) #3" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "Vik is a babe", ++ sizeof("Vik is a babe")), ++ "received message data intact (prioritized) #3" ); ++ CYG_TEST_PASS_FAIL( 6 == prio, ++ "received at correct priority (prioritized) #3" ); ++ ++ recvlen = mq_receive( q2, buf, 0, &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == (ssize_t)-1, ++ "mq_receive, zero-sized buffer" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == sizeof(""), ++ "receive message length (prioritized) #4" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "", ++ sizeof("")), ++ "received message data intact (prioritized) #4" ); ++ CYG_TEST_PASS_FAIL( 5 == prio, ++ "received at correct priority (prioritzed) #4" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == (ssize_t)-1, ++ "mq_receive, empty buffer, non-blocking #2" ); ++ CYG_TEST_PASS_FAIL( EAGAIN == errno, ++ "errno correct for non-blocking #2" ); ++ ++ err = mq_send( q1, "12345678901234567890", 20, 15 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send (before closing)" ); ++ ++ err = mq_unlink( "/foo" ); ++ CYG_TEST_PASS_FAIL( -1 == err, "mq_unlink (wrong name)" ); ++ CYG_TEST_PASS_FAIL( ENOENT == errno, ++ "errno correct for mq_unlink (wrong name)" ); ++ ++ err = mq_unlink( "/mq1" ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_unlink (before closing)" ); ++ ++ err = mq_close( q1 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_close (send descriptor)" ); ++ ++ recvlen = mq_receive( q2, buf, sizeof(buf), &prio ); ++ CYG_TEST_PASS_FAIL( recvlen == 20, ++ "receive message length (mid close)" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, "12345678901234567890", 20 ), ++ "received message data intact (mid close)" ); ++ CYG_TEST_PASS_FAIL( 15 == prio, ++ "received at correct priority (mid close)" ); ++ ++ err = mq_close( q2 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_close (receive descriptor)" ); ++ ++ q1 = mq_open( "/mq1", O_RDONLY ); ++ CYG_TEST_PASS_FAIL( q1 == (mqd_t)-1, "error for non-existent queue" ); ++ CYG_TEST_PASS_FAIL( ENOENT == errno, ++ "errno correct for non-existent queue" ); ++ ++ CYG_TEST_EXIT("POSIX message test 1"); ++ ++ return 0; ++} // main() ++ ++//------------------------------------------------------------------------ ++ ++#endif ++ ++/* EOF mqueue1.c */ +diff -urNad redboot-imx-200952~/packages/compat/posix/current/tests/mqueue2.c redboot-imx-200952/packages/compat/posix/current/tests/mqueue2.c +--- redboot-imx-200952~/packages/compat/posix/current/tests/mqueue2.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/compat/posix/current/tests/mqueue2.c 2010-01-26 17:33:11.892955130 +0000 +@@ -0,0 +1,276 @@ ++/*======================================================================== ++// ++// mqueue2.c ++// ++// POSIX Message queues tests - mq_notify ++// ++//======================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//======================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): jlarmour ++// Contributors: ++// Date: 2000-05-18 ++// Purpose: This file provides tests for POSIX mqueue mq_notify ++// Description: ++// Usage: ++// ++//####DESCRIPTIONEND#### ++// ++//====================================================================== ++*/ ++ ++/* CONFIGURATION */ ++ ++#include ++ ++#ifndef CYGPKG_POSIX_MQUEUES ++# define NA_MSG "Message queues not configured" ++#elif !defined(CYGPKG_POSIX_SIGNALS) ++# define NA_MSG "No POSIX signals configured" ++#endif ++ ++#ifdef NA_MSG ++#include // test API ++void ++cyg_user_start(void) ++{ ++ CYG_TEST_INIT(); ++ CYG_TEST_NA( NA_MSG ); ++} ++ ++#else ++ ++/* INCLUDES */ ++ ++#include // O_* ++#include // errno ++#include // file modes ++#include // Mqueue Header ++#include // test API ++#include // signals ++ ++/* GLOBALS */ ++sig_atomic_t signals=0; ++char buf[20]; ++unsigned int prio; ++ ++ ++/* FUNCTIONS */ ++ ++static int ++my_memcmp(const void *m1, const void *m2, size_t n) ++{ ++ char *s1 = (char *)m1; ++ char *s2 = (char *)m2; ++ ++ while (n--) { ++ if (*s1 != *s2) ++ return *s1 - *s2; ++ s1++; ++ s2++; ++ } ++ return 0; ++} // my_memcmp() ++ ++static char * ++my_strcpy(char *s1, const char *s2) ++{ ++ char *s = s1; ++ while (*s2) { ++ *s1++ = *s2++; ++ } ++ return s; ++} // my_strcpy() ++ ++static size_t ++my_strlen(const char *s) ++{ ++ const char *start = s; ++ while (*s) ++ s++; ++ return (s - start); ++} // my_strcpy() ++ ++ ++ ++//************************************************************************ ++ ++static void ++sigusr1_handler( int signo, siginfo_t *info, void *context ) ++{ ++ ssize_t recvlen; ++ char mybuf[20]; ++ unsigned int myprio; ++ mqd_t *q = (mqd_t *)info->si_value.sival_ptr; ++ ++ CYG_TEST_PASS_FAIL( SIGUSR1 == signo, "correct signal number #1" ); ++ CYG_TEST_PASS_FAIL( SIGUSR1 == info->si_signo, "correct signal number #2" ); ++ CYG_TEST_PASS_FAIL( SI_MESGQ == info->si_code, "correct signal code" ); ++ ++ signals++; ++ ++ // retrieve message and compare with buf ++ recvlen = mq_receive( *q, mybuf, sizeof(mybuf), &myprio ); ++ CYG_TEST_PASS_FAIL( recvlen == my_strlen(buf), ++ "receive message length" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, mybuf, my_strlen(buf)), ++ "received message data intact" ); ++ CYG_TEST_PASS_FAIL( prio == myprio, ++ "received at correct priority" ); ++} ++ ++//************************************************************************ ++ ++int ++main(void) ++{ ++ mqd_t q1; ++ struct mq_attr attr; ++ mode_t mode; ++ int err; ++ ssize_t recvlen; ++ char mybuf[20]; ++ unsigned int myprio; ++ struct sigevent ev; ++ struct sigaction act; ++ ++ CYG_TEST_INIT(); ++ CYG_TEST_INFO( "Starting POSIX message test 2" ); ++ ++#if 0 ++ if ( 0 != pthread_create( &thr, NULL, &thread, NULL ) ) { ++ CYG_TEST_FAIL_FINISH( "Couldn't create a helper thread" ); ++ } ++#endif ++ ++ attr.mq_flags = 0; ++ attr.mq_maxmsg = 4; ++ attr.mq_msgsize = 20; ++ mode = S_IRWXU|S_IRWXG|S_IRWXO; // rwx for all ++ ++ q1 = mq_open( "/mq1", O_CREAT|O_NONBLOCK|O_RDWR, mode, &attr ); ++ CYG_TEST_PASS_FAIL( q1 != (mqd_t)-1, "simple mq_open (write only)" ); ++ ++ err = mq_getattr( q1, &attr ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_getattr" ); ++ CYG_TEST_PASS_FAIL( (4 == attr.mq_maxmsg) && ++ (20 == attr.mq_msgsize) && ++ (O_NONBLOCK == (attr.mq_flags & O_NONBLOCK)) && ++ (O_RDWR == (attr.mq_flags & O_RDWR)) && ++ (0 == attr.mq_curmsgs ), "getattr attributes correct" ); ++ ++ ++ act.sa_sigaction = &sigusr1_handler; ++ sigfillset( &act.sa_mask ); // enable all signals ++ act.sa_flags = SA_SIGINFO; ++ ++ if ( 0 != sigaction( SIGUSR1, &act, NULL ) ) { ++ CYG_TEST_FAIL_FINISH( "Couldn't register signal handler" ); ++ } ++ ++ ev.sigev_notify = SIGEV_SIGNAL; ++ ev.sigev_signo = SIGUSR1; ++ ev.sigev_value.sival_ptr = (void *)&q1; ++ ++ err = mq_notify( q1, &ev ); ++ CYG_TEST_PASS_FAIL( 0 == err, "simple mq_notify" ); ++ ++ my_strcpy( buf, "Vik is the best" ); ++ prio = 7; ++ err = mq_send( q1, buf, my_strlen(buf), prio ); ++ ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send #1" ); ++ ++ CYG_TEST_PASS_FAIL( 1 == signals, "got notification" ); ++ ++ my_strcpy( buf, "Scrummy Vik" ); ++ prio = 6; ++ err = mq_send( q1, buf, my_strlen(buf), prio ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send #2" ); ++ ++ CYG_TEST_PASS_FAIL( 1 == signals, "correctly didn't get notification" ); ++ ++ recvlen = mq_receive( q1, mybuf, sizeof(mybuf), &myprio ); ++ CYG_TEST_PASS_FAIL( recvlen == my_strlen(buf), ++ "receive message length" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, mybuf, my_strlen(buf)), ++ "received message data intact" ); ++ CYG_TEST_PASS_FAIL( prio == myprio, ++ "received at correct priority" ); ++ ++ err = mq_notify( q1, &ev ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_notify #2" ); ++ ++ err = mq_notify( q1, &ev ); ++ CYG_TEST_PASS_FAIL( -1 == err, "second mq_notify returns error" ); ++ CYG_TEST_PASS_FAIL( EBUSY == errno, ++ "errno correct for second mq_notify error" ); ++ ++ err = mq_notify( q1, NULL ); ++ CYG_TEST_PASS_FAIL( 0 == err, "clear notification" ); ++ ++ my_strcpy( buf, "Vik is k3wl" ); ++ prio = 8; ++ err = mq_send( q1, buf, my_strlen(buf), prio ); ++ ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_send #2" ); ++ ++ CYG_TEST_PASS_FAIL( 1 == signals, "correctly didn't get notification #2" ); ++ ++ recvlen = mq_receive( q1, mybuf, sizeof(mybuf), &myprio ); ++ CYG_TEST_PASS_FAIL( recvlen == my_strlen(buf), ++ "receive message length" ); ++ CYG_TEST_PASS_FAIL( 0 == my_memcmp( buf, mybuf, my_strlen(buf)), ++ "received message data intact" ); ++ CYG_TEST_PASS_FAIL( prio == myprio, ++ "received at correct priority" ); ++ ++ err = mq_close( q1 ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_close" ); ++ ++ err = mq_unlink( "/mq1" ); ++ CYG_TEST_PASS_FAIL( 0 == err, "mq_unlink" ); ++ ++ CYG_TEST_EXIT("POSIX message test 2"); ++ ++ return 0; ++} // main() ++ ++//------------------------------------------------------------------------ ++ ++#endif ++ ++/* EOF mqueue2.c */ +diff -urNad redboot-imx-200952~/packages/compat/posix/current/tests/mutex3.c redboot-imx-200952/packages/compat/posix/current/tests/mutex3.c +--- redboot-imx-200952~/packages/compat/posix/current/tests/mutex3.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/compat/posix/current/tests/mutex3.c 2010-01-26 17:33:11.902961755 +0000 +@@ -0,0 +1,672 @@ ++//========================================================================== ++// ++// mutex3.cxx ++// ++// Mutex test 3 - priority inheritance ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): hmt ++// Contributors: hmt, nickg, jlarmour ++// Date: 2000-01-06 ++// Description: Tests mutex priority inheritance. This is simply a translation ++// of the similarly named kernel test to the POSIX API ++//####DESCRIPTIONEND#### ++ ++// ------------------------------------------------------------------------ ++ ++#include ++#include ++#include ++#ifdef CYGPKG_KERNEL ++#include ++#endif ++ ++#ifdef CYGPKG_ISOINFRA ++# include ++# include ++# include ++# include ++# include ++#endif ++ ++#if !defined(CYGPKG_POSIX_PTHREAD) ++#define NA_MSG "POSIX threads not enabled" ++ ++// ------------------------------------------------------------------------ ++// ++// These checks should be enough; any other scheduler which has priorities ++// should manifest as having no priority inheritance, but otherwise fine, ++// so the test should work correctly. ++ ++#elif !defined(_POSIX_THREAD_PRIORITY_SCHEDULING) ++#define NA_MSG "No POSIX thread priority scheduling enabled" ++#elif !defined(_POSIX_THREAD_PRIO_INHERIT) ++#define NA_MSG "No POSIX thread priority inheritance enabled" ++#elif !defined(_POSIX_SEMAPHORES) ++#define NA_MSG "No POSIX sempaphore support enabled enabled" ++#elif !defined(CYGFUN_KERNEL_API_C) ++#define NA_MSG "Kernel C API not enabled" ++#elif defined(CYGPKG_KERNEL_SMP_SUPPORT) ++#define NA_MSG "Test cannot run with SMP support" ++#endif ++ ++#ifdef NA_MSG ++void ++cyg_start(void) ++{ ++ CYG_TEST_INIT(); ++ CYG_TEST_NA(NA_MSG); ++} ++#else ++ ++#include ++#include ++#include // diag_printf ++ ++#include // Some extras ++ ++// ------------------------------------------------------------------------ ++// Management functions ++// ++// Stolen from testaux.hxx and copied in here because I want to be able to ++// reset the world also. ++// ... and subsequently POSIXized out of all similarly with its progenitors. ++ ++#define NTHREADS 7 ++ ++#define STACKSIZE (PTHREAD_STACK_MIN*2) ++ ++static pthread_t thread[NTHREADS] = { 0 }; ++ ++typedef CYG_WORD64 CYG_ALIGNMENT_TYPE; ++ ++static CYG_ALIGNMENT_TYPE stack[NTHREADS] [ ++ (STACKSIZE+sizeof(CYG_ALIGNMENT_TYPE)-1) ++ / sizeof(CYG_ALIGNMENT_TYPE) ]; ++ ++// Semaphores to halt execution of threads ++static sem_t hold[NTHREADS]; ++ ++// Flag to tell all threads to exit ++static int all_exit; ++ ++// Application thread data is passed here, the thread ++// argument is ++static CYG_ADDRWORD thread_data[NTHREADS]; ++ ++static volatile int nthreads = 0; ++ ++// Sleep for 1 tick... ++static struct timespec sleeptime; ++ ++ ++static pthread_t new_thread( void *(*entry)(void *), ++ CYG_ADDRWORD data, ++ int priority, ++ int do_resume) ++{ ++ pthread_attr_t attr; ++ int _nthreads = nthreads++; ++ ++ struct sched_param schedparam; ++ schedparam.sched_priority = priority; ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setstackaddr( &attr, (void *)((char *)(&stack[_nthreads])+STACKSIZE) ); ++ pthread_attr_setstacksize( &attr, STACKSIZE ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ CYG_ASSERT(_nthreads < NTHREADS, ++ "Attempt to create more than NTHREADS threads"); ++ ++ thread_data[_nthreads] = data; ++ ++ sem_init( &hold[_nthreads], 0, do_resume ? 1 : 0 ); ++ all_exit = 0; ++ ++ pthread_create( &thread[_nthreads], ++ &attr, ++ entry, ++ (void *)_nthreads); ++ ++ return thread[_nthreads]; ++} ++ ++ ++static void kill_threads( void ) ++{ ++ CYG_ASSERT(nthreads <= NTHREADS, ++ "More than NTHREADS threads"); ++ CYG_ASSERT( pthread_equal(pthread_self(),thread[0]), ++ "kill_threads() not called from thread 0"); ++ all_exit = 1; ++ while ( nthreads > 1 ) { ++ nthreads--; ++ if ( 0 != thread[nthreads] ) { ++ sem_post( &hold[nthreads] ); ++ pthread_cancel( thread[nthreads] ); ++ pthread_join( thread[nthreads], NULL ); ++ thread[nthreads] = 0; ++ sem_destroy( &hold[nthreads] ); ++ } ++ } ++ CYG_ASSERT(nthreads == 1, ++ "No threads left"); ++} ++ ++// ------------------------------------------------------------------------ ++ ++#define DELAYFACTOR 1 // for debugging ++ ++// ------------------------------------------------------------------------ ++ ++pthread_mutex_t mutex; ++ ++// These are for reporting back to the master thread ++volatile int got_it = 0; ++volatile int t3ran = 0; ++volatile int t3ended = 0; ++volatile int extras[4] = {0,0,0,0}; ++ ++volatile int go_flag = 0; // but this one controls thread 3 from thread 2 ++ ++// ------------------------------------------------------------------------ ++// 0 to 3 of these run generally to interfere with the other processing, ++// to cause multiple prio inheritances, and clashes in any orders. ++ ++static void *extra_thread( void *arg ) ++{ ++#define XINFO( z ) \ ++ do { z[13] = '0' + data; CYG_TEST_INFO( z ); } while ( 0 ) ++ ++ static char running[] = "Extra thread Xa running"; ++ static char exiting[] = "Extra thread Xa exiting"; ++ static char resumed[] = "Extra thread Xa resumed"; ++ static char locked[] = "Extra thread Xa locked"; ++ static char unlocked[] = "Extra thread Xa unlocked"; ++ ++ int id = (int)arg; ++ CYG_ADDRWORD data = thread_data[id]; ++ ++ CYG_ASSERT( (id >= 4 && id <= 6), "extra_thread invalid id" ); ++ ++ // Emulate resume behaviour ++ sem_wait( &hold[id] ); ++ if( all_exit ) return 0; ++ ++ XINFO( running ); ++ ++ sem_wait( &hold[id] ); ++ ++ XINFO( resumed ); ++ ++ pthread_mutex_lock( &mutex ); ++ ++ XINFO( locked ); ++ ++ pthread_mutex_unlock( &mutex ); ++ ++ XINFO( unlocked ); ++ ++ extras[ data ] ++; ++ ++ XINFO( exiting ); ++ ++ return NULL; ++} ++ ++// ------------------------------------------------------------------------ ++ ++static void *t1( void *arg ) ++{ ++ int id = (int)arg; ++ //CYG_ADDRWORD data = thread_data[id]; ++ ++ // Emulate resume behaviour ++ sem_wait( &hold[id] ); ++ if( all_exit ) return 0; ++ ++ CYG_TEST_INFO( "Thread 1 running" ); ++ ++ sem_wait( &hold[id] ); ++ ++ pthread_mutex_lock( &mutex ); ++ ++ got_it++; ++ ++ CYG_TEST_CHECK( 0 == t3ended, "T3 ended prematurely [T1,1]" ); ++ ++ pthread_mutex_unlock( &mutex ); ++ ++ CYG_TEST_CHECK( 0 == t3ended, "T3 ended prematurely [T1,2]" ); ++ ++ // That's all. ++ ++ CYG_TEST_INFO( "Thread 1 exit" ); ++ ++ return 0; ++} ++ ++// ------------------------------------------------------------------------ ++ ++static void *t2( void *arg ) ++{ ++ int i; ++ int id = (int)arg; ++ CYG_ADDRWORD data = thread_data[id]; ++ cyg_tick_count_t now, then; ++ ++ // Emulate resume behaviour ++ sem_wait( &hold[id] ); ++ if( all_exit ) return 0; ++ ++ CYG_TEST_INFO( "Thread 2 running" ); ++ ++ CYG_TEST_CHECK( 0 == (data & ~0x77), "Bad T2 arg: extra bits" ); ++ CYG_TEST_CHECK( 0 == (data & (data >> 4)), "Bad T2 arg: overlap" ); ++ ++ sem_wait( &hold[id] ); ++ ++ // depending on our config argument, optionally restart some of the ++ // extra threads to throw noise into the scheduler: ++ for ( i = 0; i < 3; i++ ) ++ if ( (1 << i) & data ) // bits 0-2 control ++ sem_post( &hold[i+4] ); // made sure extras are thread[4-6] ++ ++ // let those threads run ++ for( i = 0; i < DELAYFACTOR * 10; i++ ) ++ nanosleep( &sleeptime, NULL ); ++ ++ cyg_scheduler_lock(); // do this next lot atomically ++ ++ go_flag = 1; // unleash thread 3 ++ sem_post( &hold[1] ); // resume thread 1 ++ ++ // depending on our config argument, optionally restart some of the ++ // extra threads to throw noise into the scheduler at this later point: ++ for ( i = 4; i < 7; i++ ) ++ if ( (1 << i) & data ) // bits 4-6 control ++ sem_post( &hold[i] ); // made sure extras are thread[4-6] ++ ++ cyg_scheduler_unlock(); // let scheduling proceed ++ ++ // Need a delay (but not a CPU yield) to allow t3 to awaken and act on ++ // the go_flag, otherwise we check these details below too soon. ++ // Actually, waiting for the clock to tick a couple of times would be ++ // better, so that is what we will do. Must be a busy-wait. ++ then = cyg_current_time(); ++ do { ++ now = cyg_current_time(); ++ // Wait longer than the delay in t3 waiting on go_flag ++ } while ( now < (then + 3) ); ++ ++#ifdef _POSIX_THREAD_PRIO_INHERIT ++ CYG_TEST_INFO( "Checking for mutex priority inheritance" ); ++ CYG_TEST_CHECK( 1 == t3ran, "Thread 3 did not run" ); ++ CYG_TEST_CHECK( 1 == got_it, "Thread 1 did not get the mutex" ); ++#else ++ CYG_TEST_INFO( "Checking for NO mutex priority inheritance" ); ++ CYG_TEST_CHECK( 0 == t3ran, "Thread 3 DID run" ); ++ CYG_TEST_CHECK( 0 == got_it, "Thread 1 DID get the mutex" ); ++#endif ++ ++ CYG_TEST_CHECK( 0 == t3ended, "Thread 3 ended prematurely [T2,1]" ); ++ ++ for( i = 0; i < DELAYFACTOR * 20; i++ ) ++ nanosleep( &sleeptime, NULL ); // let those threads run ++ ++ CYG_TEST_CHECK( 1 == t3ran, "Thread 3 did not run" ); ++ CYG_TEST_CHECK( 1 == got_it, "Thread 1 did not get the mutex" ); ++ CYG_TEST_CHECK( 1 == t3ended, "Thread 3 has not ended" ); ++ ++ for ( i = 0; i < 3; i++ ) ++ if ( (1 << i) & (data | data >> 4) ) // bits 0-2 and 4-6 control ++ CYG_TEST_CHECK( 1 == extras[i+1], "Extra thread did not run" ); ++ else ++ CYG_TEST_CHECK( 0 == extras[i+1], "Extra thread ran" ); ++ ++ CYG_TEST_PASS( "Thread 2 exiting, AOK" ); ++ // That's all: restart the control thread. ++ sem_post( &hold[0] ); ++ ++ return 0; ++} ++ ++// ------------------------------------------------------------------------ ++ ++static void *t3( void *arg ) ++{ ++ int i; ++ int id = (int)arg; ++ //CYG_ADDRWORD data = thread_data[id]; ++ ++ // Emulate resume behaviour ++ sem_wait( &hold[id] ); ++ if( all_exit ) return 0; ++ ++ CYG_TEST_INFO( "Thread 3 running" ); ++ ++ pthread_mutex_lock( &mutex ); ++ ++ for( i = 0; i < DELAYFACTOR * 5; i++ ) ++ nanosleep( &sleeptime, NULL ); // let thread 3a run ++ ++ sem_post( &hold[2] ); // resume thread 2 ++ ++ while ( 0 == go_flag ) ++ nanosleep( &sleeptime, NULL ); // wait until we are told to go ++ ++ t3ran ++; // record the fact ++ ++ CYG_TEST_CHECK( 0 == got_it, "Thread 1 claims to have got my mutex" ); ++ ++ pthread_mutex_unlock( &mutex ); ++ ++ t3ended ++; // record that we came back ++ ++ CYG_TEST_CHECK( 1 == got_it, "Thread 1 did not get the mutex" ); ++ ++ CYG_TEST_INFO( "Thread 3 exit" ); ++ ++ return 0; ++} ++ ++// ------------------------------------------------------------------------ ++ ++static void *control_thread( void *arg ) ++{ ++ int i,z; ++ int id = (int)arg; ++ //CYG_ADDRWORD data = thread_data[id]; ++ ++ // Emulate resume behaviour ++ sem_wait( &hold[id] ); ++ if( all_exit ) return 0; ++ ++ // one tick sleep time ++ sleeptime.tv_nsec = 10000000; ++ sleeptime.tv_sec = 0; ++ ++ CYG_TEST_INIT(); ++ CYG_TEST_INFO( "Control Thread running" ); ++ ++ // Go through the 27 possibilitied of resuming the extra threads ++ // 0: not at all ++ // 1: early in the process ++ // 2: later on ++ // which are represented by bits 0-3 and 4-6 resp in the argument to ++ // thread 2 (none set means no resume at all). ++ for ( i = 0; i < 27; i++ ) { ++ static int xx[] = { 0, 1, 16 }; ++ int j = i % 3; ++ int k = (i / 3) % 3; ++ int l = (i / 9) % 3; ++ ++ int d = xx[j] | (xx[k]<<1) | (xx[l]<<2) ; ++ ++ if ( cyg_test_is_simulator && (0 != i && 13 != i && 26 != i) ) ++ continue; // 13 is 111 base 3, 26 is 222 base 3 ++ ++#ifdef _POSIX_THREAD_PRIO_INHERIT ++ // If the simple scheme plus relay enhancement, or any other ++ // *complete* scheme, we can run all three ancillary threads no ++ // problem, so no special action here. ++ ++#else ++ // If no priority inheritance at all, running threads 1a and 2a is ++ // OK, but not thread 3a; it blocks the world. ++ if ( l ) // Cannot run thread 3a if no ++ break; // priority inheritance at all. ++#endif ++ ++ // Reinitialize mutex to provide priority inheritance ++ { ++ pthread_mutexattr_t attr; ++ pthread_mutexattr_init( &attr ); ++ pthread_mutexattr_setprotocol( &attr, PTHREAD_PRIO_INHERIT ); ++ pthread_mutex_init( &mutex, &attr ); ++ } ++ ++ got_it = 0; ++ t3ran = 0; ++ t3ended = 0; ++ for ( z = 0; z < 4; z++ ) extras[z] = 0; ++ go_flag = 0; ++ ++ new_thread( t1, 0, 15, 1 ); // Slot 1 ++ new_thread( t2, d, 10, 1 ); // Slot 2 ++ new_thread( t3, 0, 5, 1 ); // Slot 3 ++ ++ new_thread( extra_thread, 1, 17, j ); // Slot 4 ++ new_thread( extra_thread, 2, 12, k ); // Slot 5 ++ new_thread( extra_thread, 3, 8, l ); // Slot 6 ++ ++ { ++ static char *a[] = { "inactive", "run early", "run late" }; ++ diag_printf( "\n----- [%2d] New Cycle: 0x%02x, Threads 1a %s, 2a %s, 3a %s -----\n", ++ i, d, a[j], a[k], a[l] ); ++ } ++ ++ sem_wait( &hold[0] ); ++ ++ kill_threads(); ++ pthread_mutex_destroy( &mutex ); ++ } ++ CYG_TEST_EXIT( "Control Thread exit" ); ++ ++ return 0; ++} ++ ++// ------------------------------------------------------------------------ ++ ++static sem_t main_sem; ++ ++externC int ++main( int argc, char **argv ) ++{ ++ new_thread( control_thread, 0, 20, 1 ); ++ ++ // We have nothing for main to do here, so put it to sleep on ++ // its own semaphore. We cannot let it just exit since that ++ // will end the whole program. ++ ++ sem_init( &main_sem, 0, 0 ); ++ ++ for(;;) sem_wait( &main_sem ); ++} ++ ++// ------------------------------------------------------------------------ ++// Documentation: enclosed is the design of this test. ++// ++// It has been carefully constructed so that it does NOT use other kernel ++// facilities (aside from delay-task) to test that priority inheritance is ++// working, or not, as intended by the configuration. ++// ++// These notes describe the flow of control in one run of the test with the ++// ancillary tasks optionally interspersed. The details of how those extra ++// tasks are or are not allowed to run are not described. ++// ++// ++// ++// The only change in the test that depends on whether there is inheritance or ++// not is the check in thread 2 on "3-ran" and "got it" flags marked **** ++// ++// ++// volatile &c booleans: ++// "got it" = FALSE ++// "3-ran" = FALSE ++// "3-ended" = FALSE ++// "extras"[3] = FALSE ++// ++// thread 1. prio 5, self-suspend. ++// ++// thread 1a, prio 8, self-suspend. ++// ++// thread 2. prio 10, self-suspend. ++// ++// thread 2a, prio 12, self-suspend. ++// ++// thread 3. prio 15, runs, lock mutex, resume(2) ++// ++// thread 3a, prio 17, self-suspend. ++// ++// 2. runs, ++// 2. resume(3a) +++OPTIONAL ++// 2. resume(2a) +++OPTIONAL ++// 2. resume(1a) +++OPTIONAL ++// [1a lock-fail] thread 3->prio := 8 ++// ++// [3. runs maybe, does the looping thing] ++// ++// 2. sleep a while... ++// ++// [2a lock-fail] thread 3->prio := 12 ++// ++// [3. runs maybe, does the looping thing] ++// ++// [3a lock-fail] thread 3->prio unchanged ++// ++// [3. runs maybe, does the looping thing] ++// ++// 2. lock scheduler ++// 2. set "go-flag" ++// 2. resume(1) ++// 2. resume(1a) +++OPTIONAL ++// 2. resume(2a) +++OPTIONAL ++// 2. resume(3a) +++OPTIONAL ++// 2. unlock scheduler ++// ++// 1. runs, lock mutex - thread 3 has it locked ++// ++// 2. busy-waits a bit for thread 3 to come out of its delay() loop. ++// This must be a *busy*wait so that 3 can only run via the ++// inherited raised priority. ++// ++// [xa. all do the same: lock mutex, ] ++// [xa. unlock mutex ] ++// [xa. set a flag "extras"[x] to say we are done. ] ++// [xa. exit ] ++// ++// ++// ++// INHERIT ++// ------- ++// ++// thread 3->prio := 5 ++// ++// 3. runs, ++// 3. set a flag to say "3-ran", ++// 3. loop with a sleep(1) until "go-flag" is set. ++// 3. check "got it" is false, ++// 3. then unlock mutex, ++// ++// thread 3->prio := 15 ++// ++// 1. runs, set a flag to say "got it", ++// 1. check "3-ended" flag is false ++// 1. unlock mutex, ++// 1. check "3-ended" flag is still false ++// 1. exit. ++// ++// [1a locks, unlocks, exits] ++// ++// 2. runs, check "3-ran" and "got it" flags are TRUE **** ++// 2. check "3-ended" flag is false ++// 2. sleeps for a while so that... ++// ++// [2a locks, unlocks, exits] ++// ++// 3. runs, set "3-ended" flag, ++// 3. check "3-ran" and "got it" flags ++// 3. exit ++// ++// [3a locks, unlocks, exits] ++// ++// 2. awakens, checks all flags true, ++// 2. check that all "extra" threads that we started have indeed run ++// 2. end of test. ++// ++// ++// ++// ++// NO-INHERIT ++// ---------- ++// thread 1 is waiting on the mutex ++// ++// [1a lock-fail] ++// ++// 2. runs, checks that "3-ran" and "got it" flags are FALSE **** ++// 2. check "3-ended" flag is false ++// 2. sleeps for a while so that... ++// ++// [2a. lock-fail] ++// ++// 3. runs, set a flag to say "3-ran", ++// 3. check "got it" is false, ++// 3. then unlock mutex, ++// ++// 1. runs, set a flag to say "got it", ++// 1. check "3-ended" flag is false ++// 1. unlock mutex, ++// 1. check "3-ended" flag is still false ++// 1. exit. ++// ++// [1a locks, unlocks, exits] ++// [2a locks, unlocks, exits] ++// ++// 3. runs, set "3-ended" flag, ++// 3. check "3-ran" and "got it" flags ++// 3. exit ++// ++// [3a locks, unlocks, exits] ++// ++// 2. awakens, checks all flags true, ++// 2. check that all "extra" threads that we started have indeed run ++// 2. end of test. ++// ++// ++// (the end) ++// ++// ++// ------------------------------------------------------------------------ ++ ++#endif ++ ++// EOF mutex3.cxx +diff -urNad redboot-imx-200952~/packages/compat/posix/current/tests/tm_basic.cxx redboot-imx-200952/packages/compat/posix/current/tests/tm_basic.cxx +--- redboot-imx-200952~/packages/compat/posix/current/tests/tm_basic.cxx 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/compat/posix/current/tests/tm_basic.cxx 2010-01-26 17:33:11.912961131 +0000 +@@ -0,0 +1,1696 @@ ++//========================================================================== ++// ++// tm_basic.cxx ++// ++// Basic timing test / scaffolding ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// Copyright (C) 2002 Jonathan Larmour ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): gthomas,nickg ++// Contributors: jlarmour ++// Date: 1998-10-19 ++// Description: Very simple kernel timing test ++//####DESCRIPTIONEND#### ++//========================================================================== ++ ++ ++#include ++#include ++#include ++#include ++#ifdef CYGPKG_KERNEL ++#include ++#endif ++ ++#ifndef CYGPKG_POSIX_SIGNALS ++#define NA_MSG "No POSIX signals" ++#elif !defined(CYGPKG_POSIX_TIMERS) ++#define NA_MSG "No POSIX timers" ++#elif !defined(CYGPKG_POSIX_PTHREAD) ++#define NA_MSG "POSIX threads not enabled" ++#elif !defined(CYGFUN_KERNEL_API_C) ++#define NA_MSG "Kernel C API not enabled" ++#elif !defined(CYGSEM_KERNEL_SCHED_MLQUEUE) ++#define NA_MSG "Kernel mlqueue scheduler not enabled" ++#elif !defined(CYGVAR_KERNEL_COUNTERS_CLOCK) ++#define NA_MSG "Kernel clock not enabled" ++#elif CYGNUM_KERNEL_SCHED_PRIORITIES <= 12 ++#define NA_MSG "Kernel scheduler properties <= 12" ++#endif ++ ++//========================================================================== ++ ++#ifdef NA_MSG ++extern "C" void ++cyg_start(void) ++{ ++ CYG_TEST_INIT(); ++ CYG_TEST_NA(NA_MSG); ++} ++#else ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++ ++// POSIX headers ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//========================================================================== ++// Define this to see the statistics with the first sample datum removed. ++// This can expose the effects of caches on the speed of operations. ++ ++#undef STATS_WITHOUT_FIRST_SAMPLE ++ ++//========================================================================== ++ ++// Structure used to keep track of times ++typedef struct fun_times { ++ cyg_uint32 start; ++ cyg_uint32 end; ++} fun_times; ++ ++//========================================================================== ++ ++#define STACK_SIZE (PTHREAD_STACK_MIN*2) ++ ++// Defaults ++#define NTEST_THREADS 16 ++#define NMUTEXES 32 ++#define NMBOXES 32 ++#define NSEMAPHORES 32 ++#define NTIMERS 32 ++ ++ ++#define NSAMPLES 32 ++#define NTHREAD_SWITCHES 128 ++#define NSCHEDS 128 ++ ++#define NSAMPLES_SIM 2 ++#define NTEST_THREADS_SIM 2 ++#define NTHREAD_SWITCHES_SIM 4 ++#define NMUTEXES_SIM 2 ++#define NMBOXES_SIM 2 ++#define NSEMAPHORES_SIM 2 ++#define NSCHEDS_SIM 4 ++#define NTIMERS_SIM 2 ++ ++//========================================================================== ++ ++static int nsamples; ++static int ntest_threads; ++static int nthread_switches; ++static int nmutexes; ++static int nmboxes; ++static int nsemaphores; ++static int nscheds; ++static int ntimers; ++ ++static char stacks[NTEST_THREADS][STACK_SIZE]; ++static pthread_t threads[NTEST_THREADS]; ++static int overhead; ++static sem_t synchro; ++static fun_times thread_ft[NTEST_THREADS]; ++ ++static fun_times test2_ft[NTHREAD_SWITCHES]; ++ ++static pthread_mutex_t test_mutexes[NMUTEXES]; ++static fun_times mutex_ft[NMUTEXES]; ++static pthread_t mutex_test_thread_handle; ++ ++#if 0 ++static cyg_mbox test_mboxes[NMBOXES]; ++static cyg_handle_t test_mbox_handles[NMBOXES]; ++static fun_times mbox_ft[NMBOXES]; ++static cyg_thread mbox_test_thread; ++static cyg_handle_t mbox_test_thread_handle; ++#endif ++ ++static sem_t test_semaphores[NSEMAPHORES]; ++static fun_times semaphore_ft[NSEMAPHORES]; ++static pthread_t semaphore_test_thread_handle; ++ ++static fun_times sched_ft[NSCHEDS]; ++ ++static timer_t timers[NTIMERS]; ++static fun_times timer_ft[NTIMERS]; ++ ++static long rtc_resolution[] = CYGNUM_KERNEL_COUNTERS_RTC_RESOLUTION; ++static long ns_per_system_clock; ++ ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) ++// Data kept by kernel real time clock measuring clock interrupt latency ++extern cyg_tick_count total_clock_latency, total_clock_interrupts; ++extern cyg_int32 min_clock_latency, max_clock_latency; ++extern bool measure_clock_latency; ++#endif ++ ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY) ++extern cyg_tick_count total_clock_dsr_latency, total_clock_dsr_calls; ++extern cyg_int32 min_clock_dsr_latency, max_clock_dsr_latency; ++extern bool measure_clock_latency; ++#endif ++ ++//========================================================================== ++ ++void run_sched_tests(void); ++void run_thread_tests(void); ++void run_thread_switch_test(void); ++void run_mutex_tests(void); ++void run_mutex_circuit_test(void); ++void run_mbox_tests(void); ++void run_mbox_circuit_test(void); ++void run_semaphore_tests(void); ++void run_semaphore_circuit_test(void); ++void run_timer_tests(void); ++ ++//========================================================================== ++ ++#ifndef max ++#define max(n,m) (m > n ? n : m) ++#endif ++ ++//========================================================================== ++// Wait until a clock tick [real time clock] has passed. This should keep it ++// from happening again during a measurement, thus minimizing any fluctuations ++void ++wait_for_tick(void) ++{ ++ cyg_tick_count_t tv0, tv1; ++ tv0 = cyg_current_time(); ++ while (true) { ++ tv1 = cyg_current_time(); ++ if (tv1 != tv0) break; ++ } ++} ++ ++//-------------------------------------------------------------------------- ++// Display a number of ticks as microseconds ++// Note: for improved calculation significance, values are kept in ticks*1000 ++void ++show_ticks_in_us(cyg_uint32 ticks) ++{ ++ long long ns; ++ ns = (ns_per_system_clock * (long long)ticks) / CYGNUM_KERNEL_COUNTERS_RTC_PERIOD; ++ ns += 5; // for rounding to .01us ++ diag_printf("%5d.%02d", (int)(ns/1000), (int)((ns%1000)/10)); ++} ++ ++//-------------------------------------------------------------------------- ++// ++// If the kernel is instrumented to measure clock interrupt latency, these ++// measurements can be drastically perturbed by printing via "diag_printf()" ++// since that code may run with interrupts disabled for long periods. ++// ++// In order to get accurate/reasonable latency figures _for the kernel ++// primitive functions beint tested_, the kernel's latency measurements ++// are suspended while the printing actually takes place. ++// ++// The measurements are reenabled after the printing, thus allowing for ++// fair measurements of the kernel primitives, which are not distorted ++// by the printing mechanisms. ++ ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY) ++void ++disable_clock_latency_measurement(void) ++{ ++ wait_for_tick(); ++ measure_clock_latency = false; ++} ++ ++void ++enable_clock_latency_measurement(void) ++{ ++ wait_for_tick(); ++ measure_clock_latency = true; ++} ++ ++// Ensure that the measurements are reasonable (no startup anomalies) ++void ++reset_clock_latency_measurement(void) ++{ ++ disable_clock_latency_measurement(); ++ total_clock_latency = 0; ++ total_clock_interrupts = 0; ++ min_clock_latency = 0x7FFFFFFF; ++ max_clock_latency = 0; ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY) ++ total_clock_dsr_latency = 0; ++ total_clock_dsr_calls = 0; ++ min_clock_dsr_latency = 0x7FFFFFFF; ++ max_clock_dsr_latency = 0; ++#endif ++ enable_clock_latency_measurement(); ++ ++} ++#else ++#define disable_clock_latency_measurement() ++#define enable_clock_latency_measurement() ++#define reset_clock_latency_measurement() ++#endif ++ ++//-------------------------------------------------------------------------- ++ ++void ++show_times_hdr(void) ++{ ++ disable_clock_latency_measurement(); ++ diag_printf("\n"); ++ diag_printf(" Confidence\n"); ++ diag_printf(" Ave Min Max Var Ave Min Function\n"); ++ diag_printf(" ====== ====== ====== ====== ========== ========\n"); ++ enable_clock_latency_measurement(); ++} ++ ++void ++show_times_detail(fun_times ft[], int nsamples, char *title, bool ignore_first) ++{ ++ int i, delta, min, max, con_ave, con_min, ave_dev; ++ int start_sample, total_samples; ++ cyg_int32 total, ave; ++ ++ if (ignore_first) { ++ start_sample = 1; ++ total_samples = nsamples-1; ++ } else { ++ start_sample = 0; ++ total_samples = nsamples; ++ } ++ total = 0; ++ min = 0x7FFFFFFF; ++ max = 0; ++ for (i = start_sample; i < nsamples; i++) { ++ if (ft[i].end < ft[i].start) { ++ // Clock wrapped around (timer tick) ++ delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD) - ft[i].start; ++ } else { ++ delta = ft[i].end - ft[i].start; ++ } ++ delta -= overhead; ++ if (delta < 0) delta = 0; ++ delta *= 1000; ++ total += delta; ++ if (delta < min) min = delta; ++ if (delta > max) max = delta; ++ } ++ ave = total / total_samples; ++ total = 0; ++ ave_dev = 0; ++ for (i = start_sample; i < nsamples; i++) { ++ if (ft[i].end < ft[i].start) { ++ // Clock wrapped around (timer tick) ++ delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD) - ft[i].start; ++ } else { ++ delta = ft[i].end - ft[i].start; ++ } ++ delta -= overhead; ++ if (delta < 0) delta = 0; ++ delta *= 1000; ++ delta = delta - ave; ++ if (delta < 0) delta = -delta; ++ ave_dev += delta; ++ } ++ ave_dev /= total_samples; ++ con_ave = 0; ++ con_min = 0; ++ for (i = start_sample; i < nsamples; i++) { ++ if (ft[i].end < ft[i].start) { ++ // Clock wrapped around (timer tick) ++ delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD) - ft[i].start; ++ } else { ++ delta = ft[i].end - ft[i].start; ++ } ++ delta -= overhead; ++ if (delta < 0) delta = 0; ++ delta *= 1000; ++ if ((delta <= (ave+ave_dev)) && (delta >= (ave-ave_dev))) con_ave++; ++ if ((delta <= (min+ave_dev)) && (delta >= (min-ave_dev))) con_min++; ++ } ++ con_ave = (con_ave * 100) / total_samples; ++ con_min = (con_min * 100) / total_samples; ++ show_ticks_in_us(ave); ++ show_ticks_in_us(min); ++ show_ticks_in_us(max); ++ show_ticks_in_us(ave_dev); ++ disable_clock_latency_measurement(); ++ diag_printf(" %3d%% %3d%%", con_ave, con_min); ++ diag_printf(" %s\n", title); ++ enable_clock_latency_measurement(); ++} ++ ++void ++show_times(fun_times ft[], int nsamples, char *title) ++{ ++ show_times_detail(ft, nsamples, title, false); ++#ifdef STATS_WITHOUT_FIRST_SAMPLE ++ show_times_detail(ft, nsamples, "", true); ++#endif ++} ++ ++//-------------------------------------------------------------------------- ++ ++void ++show_test_parameters(void) ++{ ++ disable_clock_latency_measurement(); ++ diag_printf("\nTesting parameters:\n"); ++ diag_printf(" Clock samples: %5d\n", nsamples); ++ diag_printf(" Threads: %5d\n", ntest_threads); ++ diag_printf(" Thread switches: %5d\n", nthread_switches); ++ diag_printf(" Mutexes: %5d\n", nmutexes); ++ diag_printf(" Mailboxes: %5d\n", nmboxes); ++ diag_printf(" Semaphores: %5d\n", nsemaphores); ++ diag_printf(" Scheduler operations: %5d\n", nscheds); ++ diag_printf(" Timers: %5d\n", ntimers); ++ diag_printf("\n"); ++ enable_clock_latency_measurement(); ++} ++ ++void ++end_of_test_group(void) ++{ ++ disable_clock_latency_measurement(); ++ diag_printf("\n"); ++ enable_clock_latency_measurement(); ++} ++ ++//-------------------------------------------------------------------------- ++// Compute a name for a thread ++ ++char * ++thread_name(char *basename, int indx) { ++ return "<>"; // Not currently used ++} ++ ++//-------------------------------------------------------------------------- ++// test0 - null test, just return ++ ++void * ++test0(void *indx) ++{ ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// test3 - loop, yeilding repeatedly and checking for cancellation ++ ++void * ++test3(void *indx) ++{ ++ for(;;) ++ { ++ sched_yield(); ++ pthread_testcancel(); ++ } ++ ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// test1 - empty test, simply exit. Last thread signals parent. ++ ++void * ++test1( void *indx) ++{ ++ if ((cyg_uint32)indx == (cyg_uint32)(ntest_threads-1)) { ++ sem_post(&synchro); // Signal that last thread is dying ++ } ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// test2 - measure thread switch times ++ ++void * ++test2(void *indx) ++{ ++ int i; ++ for (i = 0; i < nthread_switches; i++) { ++ if ((int)indx == 0) { ++ HAL_CLOCK_READ(&test2_ft[i].start); ++ } else { ++ HAL_CLOCK_READ(&test2_ft[i].end); ++ } ++ sched_yield(); ++ } ++ if ((int)indx == 1) { ++ sem_post(&synchro); ++ } ++ ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// Full-circuit mutex unlock/lock test ++ ++void * ++mutex_test(void * indx) ++{ ++ int i; ++ pthread_mutex_lock(&test_mutexes[0]); ++ for (i = 0; i < nmutexes; i++) { ++ sem_wait(&synchro); ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_unlock(&test_mutexes[0]); ++ pthread_mutex_lock(&test_mutexes[0]); ++ sem_post(&synchro); ++ } ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// Full-circuit mbox put/get test ++ ++#if 0 ++void ++mbox_test(cyg_uint32 indx) ++{ ++ void *item; ++ do { ++ item = cyg_mbox_get(test_mbox_handles[0]); ++ HAL_CLOCK_READ(&mbox_ft[(int)item].end); ++ cyg_semaphore_post(&synchro); ++ } while ((int)item != (nmboxes-1)); ++ cyg_thread_exit(0); ++} ++#endif ++ ++//-------------------------------------------------------------------------- ++// Full-circuit semaphore post/wait test ++ ++void * ++semaphore_test(void * indx) ++{ ++ int i; ++ for (i = 0; i < nsemaphores; i++) { ++ sem_wait(&test_semaphores[0]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ sem_post(&synchro); ++ } ++ return indx; ++} ++ ++//-------------------------------------------------------------------------- ++// ++// This set of tests is used to measure kernel primitives that deal with threads ++// ++ ++void ++run_thread_tests(void) ++{ ++ ++ ++ int i; ++ struct sched_param schedparam; ++ pthread_attr_t attr; ++ int policy; ++ void *retval; ++ ++ // Set my priority higher than any I plan to create ++ schedparam.sched_priority = 30; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ // Initiaize thread creation attributes ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &threads[i], ++ &attr, ++ test0, ++ (void *)i ++ ); ++ ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Create thread"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ sched_yield(); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Yield thread [all lower priority]"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ ++ schedparam.sched_priority = 11; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ pthread_setschedparam(threads[i], SCHED_RR, &schedparam); ++ ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Set priority"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ pthread_getschedparam( threads[i], &policy, &schedparam ); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Get priority"); ++ ++ cyg_thread_delay(1); // Let the test threads run ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ pthread_join(threads[i], &retval); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Join exited thread"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ sched_yield(); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Yield [no other] thread"); ++ ++ ++ // Recreate the test set ++ ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ for (i = 0; i < ntest_threads; i++) { ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &threads[i], ++ &attr, ++ test3, ++ (void *)i ++ ); ++ } ++ ++ cyg_thread_delay(1); // Let the test threads run ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ pthread_cancel(threads[i]); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Cancel [running] thread"); ++ ++ cyg_thread_delay(1); // Let the test threads do their cancellations ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ pthread_join(threads[i], &retval); ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Join [cancelled] thread"); ++ ++ ++ // Set my priority lower than any I plan to create ++ schedparam.sched_priority = 5; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ // Set up the end-of-threads synchronizer ++ sem_init(&synchro, 0, 0); ++ ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntest_threads; i++) { ++ HAL_CLOCK_READ(&thread_ft[i].start); ++ ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &threads[i], ++ &attr, ++ test2, ++ (void *)i ++ ); ++ ++ HAL_CLOCK_READ(&thread_ft[i].end); ++ } ++ show_times(thread_ft, ntest_threads, "Create [high priority] thread"); ++ ++ sem_wait(&synchro); // Wait for all threads to finish ++ ++ // Make sure they are all dead ++ for (i = 0; i < ntest_threads; i++) { ++ pthread_join(threads[i], &retval); ++ } ++ ++ run_thread_switch_test(); ++ end_of_test_group(); ++ ++} ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_thread_switch_test(void) ++{ ++ ++ int i; ++ struct sched_param schedparam; ++ pthread_attr_t attr; ++ void *retval; ++ ++ // Set my priority higher than any I plan to create ++ schedparam.sched_priority = 30; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ // Initiaize thread creation attributes ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ // Set up the end-of-threads synchronizer ++ ++ sem_init(&synchro, 0, 0); ++ ++ // Set up for thread context switch ++ ++ for (i = 0; i < 2; i++) { ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &threads[i], ++ &attr, ++ test2, ++ (void *)i ++ ); ++ } ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ ++ sem_wait(&synchro); ++ ++ show_times(test2_ft, nthread_switches, "Thread switch"); ++ ++ // Clean up ++ for (i = 0; i < 2; i++) { ++ pthread_join(threads[i], &retval); ++ } ++ ++} ++ ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_mutex_tests(void) ++{ ++ ++ int i; ++ pthread_mutexattr_t attr; ++ ++ pthread_mutexattr_init( &attr ); ++ ++ // Mutex primitives ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_init(&test_mutexes[i], &attr); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Init mutex"); ++ ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_lock(&test_mutexes[i]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Lock [unlocked] mutex"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_unlock(&test_mutexes[i]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Unlock [locked] mutex"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_trylock(&test_mutexes[i]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Trylock [unlocked] mutex"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_trylock(&test_mutexes[i]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Trylock [locked] mutex"); ++ ++ // Must unlock mutices before destroying them. ++ for (i = 0; i < nmutexes; i++) { ++ pthread_mutex_unlock(&test_mutexes[i]); ++ } ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmutexes; i++) { ++ HAL_CLOCK_READ(&mutex_ft[i].start); ++ pthread_mutex_destroy(&test_mutexes[i]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ } ++ show_times(mutex_ft, nmutexes, "Destroy mutex"); ++ ++ ++ run_mutex_circuit_test(); ++ end_of_test_group(); ++} ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_mutex_circuit_test(void) ++{ ++ int i; ++ pthread_mutexattr_t mattr; ++ struct sched_param schedparam; ++ pthread_attr_t attr; ++ void *retval; ++ ++ // Set my priority lower than any I plan to create ++ schedparam.sched_priority = 5; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ // Initiaize thread creation attributes ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ // Set up for full mutex unlock/lock test ++ pthread_mutexattr_init( &mattr ); ++ pthread_mutex_init(&test_mutexes[0], &mattr); ++ sem_init(&synchro, 0, 0); ++ ++ pthread_attr_setstackaddr( &attr, &stacks[0][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &mutex_test_thread_handle, ++ &attr, ++ mutex_test, ++ (void *)0 ++ ); ++ ++ // Need to raise priority so that this thread will block on the "lock" ++ schedparam.sched_priority = 20; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ for (i = 0; i < nmutexes; i++) { ++ sem_post(&synchro); ++ pthread_mutex_lock(&test_mutexes[0]); ++ HAL_CLOCK_READ(&mutex_ft[i].end); ++ pthread_mutex_unlock(&test_mutexes[0]); ++ sem_wait(&synchro); ++ } ++ pthread_join(mutex_test_thread_handle, &retval); ++ show_times(mutex_ft, nmutexes, "Unlock/Lock mutex"); ++ ++} ++ ++ ++//-------------------------------------------------------------------------- ++// Message queue tests ++ ++// Currently disabled, pending implementation of POSIX message queues ++ ++#if 0 ++void ++run_mbox_tests(void) ++{ ++ int i, cnt; ++ void *item; ++ // Mailbox primitives ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_create(&test_mbox_handles[i], &test_mboxes[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Create mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cnt = cyg_mbox_peek(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Peek [empty] mbox"); ++ ++#ifdef CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_put(test_mbox_handles[i], (void *)i); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Put [first] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cnt = cyg_mbox_peek(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Peek [1 msg] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_put(test_mbox_handles[i], (void *)i); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Put [second] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cnt = cyg_mbox_peek(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Peek [2 msgs] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_get(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Get [first] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_get(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Get [second] mbox"); ++#endif // ifdef CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_tryput(test_mbox_handles[i], (void *)i); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Tryput [first] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_peek_item(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Peek item [non-empty] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_tryget(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Tryget [non-empty] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_peek_item(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Peek item [empty] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ item = cyg_mbox_tryget(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Tryget [empty] mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_waiting_to_get(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Waiting to get mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_waiting_to_put(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Waiting to put mbox"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nmboxes; i++) { ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_delete(test_mbox_handles[i]); ++ HAL_CLOCK_READ(&mbox_ft[i].end); ++ } ++ show_times(mbox_ft, nmboxes, "Delete mbox"); ++ ++ run_mbox_circuit_test(); ++ end_of_test_group(); ++} ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_mbox_circuit_test(void) ++{ ++#ifdef CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT ++ int i; ++ // Set my priority lower than any I plan to create ++ cyg_thread_set_priority(cyg_thread_self(), 3); ++ // Set up for full mbox put/get test ++ cyg_mbox_create(&test_mbox_handles[0], &test_mboxes[0]); ++ cyg_semaphore_init(&synchro, 0); ++ cyg_thread_create(2, // Priority - just a number ++ mbox_test, // entry ++ 0, // index ++ thread_name("thread", 0), // Name ++ &stacks[0][0], // Stack ++ STACK_SIZE, // Size ++ &mbox_test_thread_handle, // Handle ++ &mbox_test_thread // Thread data structure ++ ); ++ cyg_thread_resume(mbox_test_thread_handle); ++ for (i = 0; i < nmboxes; i++) { ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ HAL_CLOCK_READ(&mbox_ft[i].start); ++ cyg_mbox_put(test_mbox_handles[0], (void *)i); ++ cyg_semaphore_wait(&synchro); ++ } ++ cyg_thread_delete(mbox_test_thread_handle); ++ show_times(mbox_ft, nmboxes, "Put/Get mbox"); ++#endif ++} ++ ++#endif ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_semaphore_tests(void) ++{ ++ ++ int i; ++ int sem_val; ++ ++ // Semaphore primitives ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_init(&test_semaphores[i], 0, 0); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Init semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_post(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Post [0] semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_wait(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Wait [1] semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_trywait(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Trywait [0] semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ sem_post(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_trywait(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Trywait [1] semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_getvalue(&test_semaphores[i], &sem_val); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Get value of semaphore"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < nsemaphores; i++) { ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_destroy(&test_semaphores[i]); ++ HAL_CLOCK_READ(&semaphore_ft[i].end); ++ } ++ show_times(semaphore_ft, nsemaphores, "Destroy semaphore"); ++ ++ run_semaphore_circuit_test(); ++ end_of_test_group(); ++} ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_semaphore_circuit_test(void) ++{ ++ ++ int i; ++ struct sched_param schedparam; ++ pthread_attr_t attr; ++ void *retval; ++ ++ // Set my priority lower than any I plan to create ++ schedparam.sched_priority = 5; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ // Initiaize thread creation attributes ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ // Set up for full semaphore post/wait test ++ sem_init(&test_semaphores[0], 0, 0); ++ sem_init(&synchro, 0, 0); ++ ++ pthread_attr_setstackaddr( &attr, &stacks[0][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ pthread_create( &semaphore_test_thread_handle, ++ &attr, ++ semaphore_test, ++ (void *)0 ++ ); ++ ++ ++ for (i = 0; i < nsemaphores; i++) { ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ HAL_CLOCK_READ(&semaphore_ft[i].start); ++ sem_post(&test_semaphores[0]); ++ sem_wait(&synchro); ++ } ++ pthread_join(semaphore_test_thread_handle, &retval); ++ ++ show_times(semaphore_ft, nsemaphores, "Post/Wait semaphore"); ++ ++ ++} ++ ++//-------------------------------------------------------------------------- ++ ++// Timer callback function ++void ++sigrt0(int signo, siginfo_t *info, void *context) ++{ ++ diag_printf("sigrt0 called\n"); ++ // empty call back ++} ++ ++// Callback used to test determinancy ++static volatile int timer_cnt; ++void ++sigrt1(int signo, siginfo_t *info, void *context) ++{ ++ if (timer_cnt == nscheds) return; ++ sched_ft[timer_cnt].start = 0; ++ HAL_CLOCK_READ(&sched_ft[timer_cnt++].end); ++ if (timer_cnt == nscheds) { ++ sem_post(&synchro); ++ } ++} ++ ++static sem_t timer_sem; ++ ++static void ++sigrt2(int signo, siginfo_t *info, void *context) ++{ ++ if (timer_cnt == nscheds) { ++ sem_post(&synchro); ++ sem_post(&timer_sem); ++ } else { ++ sched_ft[timer_cnt].start = 0; ++ sem_post(&timer_sem); ++ } ++} ++ ++// Null thread, used to keep scheduler busy ++void * ++timer_test(void * id) ++{ ++ while (true) { ++ cyg_thread_yield(); ++ pthread_testcancel(); ++ } ++ ++ return id; ++} ++ ++// Thread that suspends itself at the first opportunity ++void * ++timer_test2(void *id) ++{ ++ while (timer_cnt != nscheds) { ++ HAL_CLOCK_READ(&sched_ft[timer_cnt++].end); ++ sem_wait(&timer_sem); ++ } ++ return id; ++} ++ ++void ++run_timer_tests(void) ++{ ++ int res; ++ int i; ++ struct sigaction sa; ++ struct sigevent sigev; ++ struct itimerspec tp; ++ ++ // Install signal handlers ++ sigemptyset( &sa.sa_mask ); ++ sa.sa_flags = SA_SIGINFO; ++ ++ sa.sa_sigaction = sigrt0; ++ sigaction( SIGRTMIN, &sa, NULL ); ++ ++ sa.sa_sigaction = sigrt1; ++ sigaction( SIGRTMIN+1, &sa, NULL ); ++ ++ sa.sa_sigaction = sigrt2; ++ sigaction( SIGRTMIN+2, &sa, NULL ); ++ ++ // Set up common bits of sigevent ++ ++ sigev.sigev_notify = SIGEV_SIGNAL; ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntimers; i++) { ++ HAL_CLOCK_READ(&timer_ft[i].start); ++ sigev.sigev_signo = SIGRTMIN; ++ sigev.sigev_value.sival_ptr = (void*)(&timers[i]); ++ res = timer_create( CLOCK_REALTIME, &sigev, &timers[i]); ++ HAL_CLOCK_READ(&timer_ft[i].end); ++ CYG_ASSERT( res == 0 , "timer_create() returned error"); ++ } ++ show_times(timer_ft, ntimers, "Create timer"); ++ ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 0; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 0; ++ for (i = 0; i < ntimers; i++) { ++ HAL_CLOCK_READ(&timer_ft[i].start); ++ res = timer_settime( timers[i], 0, &tp, NULL ); ++ HAL_CLOCK_READ(&timer_ft[i].end); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ } ++ show_times(timer_ft, ntimers, "Initialize timer to zero"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ tp.it_value.tv_sec = 1; ++ tp.it_value.tv_nsec = 250000000; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 0; ++ for (i = 0; i < ntimers; i++) { ++ HAL_CLOCK_READ(&timer_ft[i].start); ++ res = timer_settime( timers[i], 0, &tp, NULL ); ++ HAL_CLOCK_READ(&timer_ft[i].end); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ } ++ show_times(timer_ft, ntimers, "Initialize timer to 1.25 sec"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 0; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 0; ++ for (i = 0; i < ntimers; i++) { ++ HAL_CLOCK_READ(&timer_ft[i].start); ++ res = timer_settime( timers[i], 0, &tp, NULL ); ++ HAL_CLOCK_READ(&timer_ft[i].end); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ } ++ show_times(timer_ft, ntimers, "Disable timer"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ for (i = 0; i < ntimers; i++) { ++ HAL_CLOCK_READ(&timer_ft[i].start); ++ res = timer_delete( timers[i] ); ++ HAL_CLOCK_READ(&timer_ft[i].end); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ } ++ show_times(timer_ft, ntimers, "Delete timer"); ++ ++ ++ ++ sigev.sigev_signo = SIGRTMIN+1; ++ sigev.sigev_value.sival_ptr = (void*)(&timers[i]); ++ res = timer_create( CLOCK_REALTIME, &sigev, &timers[0]); ++ CYG_ASSERT( res == 0 , "timer_create() returned error"); ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 50000000; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 50000000;; ++ timer_cnt = 0; ++ res = timer_settime( timers[0], 0, &tp, NULL ); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ sem_init(&synchro, 0, 0); ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ do ++ { res = sem_wait(&synchro); ++ } while( res == -1 && errno == EINTR ); ++ CYG_ASSERT( res == 0 , "sem_wait() returned error"); ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 0; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 0; ++ res = timer_settime( timers[0], 0, &tp, NULL ); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ res = timer_delete( timers[0] ); ++ CYG_ASSERT( res == 0 , "timer_delete() returned error"); ++ show_times(sched_ft, nscheds, "Timer latency [0 threads]"); ++ ++ ++ ++ ++ struct sched_param schedparam; ++ pthread_attr_t attr; ++ void *retval; ++ ++ // Set my priority higher than any I plan to create ++ schedparam.sched_priority = 20; ++ pthread_setschedparam( pthread_self(), SCHED_RR, &schedparam ); ++ ++ ++ // Initiaize thread creation attributes ++ ++ pthread_attr_init( &attr ); ++ pthread_attr_setinheritsched( &attr, PTHREAD_EXPLICIT_SCHED ); ++ pthread_attr_setschedpolicy( &attr, SCHED_RR ); ++ schedparam.sched_priority = 10; ++ pthread_attr_setschedparam( &attr, &schedparam ); ++ ++ for (i = 0; i < 2; i++) { ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ res = pthread_create( &threads[i], ++ &attr, ++ timer_test, ++ (void *)i ++ ); ++ CYG_ASSERT( res == 0 , "pthread_create() returned error"); ++ } ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ ++ sigev.sigev_signo = SIGRTMIN+1; ++ sigev.sigev_value.sival_ptr = (void*)(&timers[i]); ++ res = timer_create( CLOCK_REALTIME, &sigev, &timers[0]); ++ CYG_ASSERT( res == 0 , "timer_create() returned error"); ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 50000000; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 50000000;; ++ timer_cnt = 0; ++ res = timer_settime( timers[0], 0, &tp, NULL ); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ ++ sem_init(&synchro, 0, 0); ++ do ++ { res = sem_wait(&synchro); ++ } while( res == -1 && errno == EINTR ); ++ CYG_ASSERT( res == 0 , "sem_wait() returned error"); ++ res = timer_delete(timers[0]); ++ CYG_ASSERT( res == 0 , "timerdelete() returned error"); ++ show_times(sched_ft, nscheds, "Timer latency [2 threads]"); ++ for (i = 0; i < 2; i++) { ++ pthread_cancel(threads[i]); ++ pthread_join(threads[i], &retval); ++ } ++ ++ ++ ++ for (i = 0; i < ntest_threads; i++) { ++ pthread_attr_setstackaddr( &attr, &stacks[i][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ res = pthread_create( &threads[i], ++ &attr, ++ timer_test, ++ (void *)i ++ ); ++ CYG_ASSERT( res == 0 , "pthread_create() returned error"); ++ } ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ sigev.sigev_signo = SIGRTMIN+1; ++ sigev.sigev_value.sival_ptr = (void*)(&timers[i]); ++ res = timer_create( CLOCK_REALTIME, &sigev, &timers[0]); ++ CYG_ASSERT( res == 0 , "timer_create() returned error"); ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 50000000; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 50000000;; ++ timer_cnt = 0; ++ res = timer_settime( timers[0], 0, &tp, NULL ); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ ++ sem_init(&synchro, 0, 0); ++ do ++ { res = sem_wait(&synchro); ++ } while( res == -1 && errno == EINTR ); ++ CYG_ASSERT( res == 0 , "sem_wait() returned error"); ++ res = timer_delete(timers[0]); ++ CYG_ASSERT( res == 0 , "timerdelete() returned error"); ++ show_times(sched_ft, nscheds, "Timer latency [many threads]"); ++ for (i = 0; i < ntest_threads; i++) { ++ pthread_cancel(threads[i]); ++ pthread_join(threads[i], &retval); ++ } ++ ++ sem_init(&synchro, 0, 0); ++ sem_init(&timer_sem, 0, 0); ++ pthread_attr_setstackaddr( &attr, &stacks[0][STACK_SIZE] ); ++ pthread_attr_setstacksize( &attr, STACK_SIZE ); ++ res = pthread_create( &threads[0], ++ &attr, ++ timer_test2, ++ (void *)0 ++ ); ++ CYG_ASSERT( res == 0 , "pthread_create() returned error"); ++ ++ wait_for_tick(); // Wait until the next clock tick to minimize aberations ++ sigev.sigev_signo = SIGRTMIN+2; ++ sigev.sigev_value.sival_ptr = (void*)(threads[0]); ++ res = timer_create( CLOCK_REALTIME, &sigev, &timers[0]); ++ CYG_ASSERT( res == 0 , "timer_create() returned error"); ++ tp.it_value.tv_sec = 0; ++ tp.it_value.tv_nsec = 50000000; ++ tp.it_interval.tv_sec = 0; ++ tp.it_interval.tv_nsec = 50000000;; ++ timer_cnt = 0; ++ res = timer_settime( timers[0], 0, &tp, NULL ); ++ CYG_ASSERT( res == 0 , "timer_settime() returned error"); ++ ++ do ++ { res = sem_wait(&synchro); ++ } while( res == -1 && errno == EINTR ); ++ CYG_ASSERT( res == 0 , "sem_wait() returned error"); ++ res = timer_delete(timers[0]); ++ CYG_ASSERT( res == 0 , "timerdelete() returned error"); ++ show_times(sched_ft, nscheds, "Timer -> thread post latency"); ++ sem_post(&timer_sem); ++// pthread_cancel(threads[0]); ++ pthread_join(threads[0], &retval); ++ ++ ++ end_of_test_group(); ++} ++ ++ ++//-------------------------------------------------------------------------- ++ ++void ++run_all_tests() ++{ ++ int i; ++ cyg_uint32 tv[nsamples], tv0, tv1; ++// cyg_uint32 min_stack, max_stack, total_stack, actual_stack, j; ++ cyg_tick_count_t ticks, tick0, tick1; ++#ifdef CYG_SCHEDULER_LOCK_TIMINGS ++ cyg_uint32 lock_ave, lock_max; ++#endif ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY) ++ cyg_int32 clock_ave; ++#endif ++ ++ disable_clock_latency_measurement(); ++ ++// cyg_test_dump_thread_stack_stats( "Startup, main stack", thread[0] ); ++ cyg_test_dump_interrupt_stack_stats( "Startup" ); ++ cyg_test_dump_idlethread_stack_stats( "Startup" ); ++ cyg_test_clear_interrupt_stack(); ++ ++ diag_printf("\neCos Kernel Timings\n"); ++ diag_printf("Notes: all times are in microseconds (.000001) unless otherwise stated\n"); ++#ifdef STATS_WITHOUT_FIRST_SAMPLE ++ diag_printf(" second line of results have first sample removed\n"); ++#endif ++ ++ cyg_thread_delay(2); // Make sure the clock is actually running ++ ++ ns_per_system_clock = 1000000/rtc_resolution[1]; ++ ++ for (i = 0; i < nsamples; i++) { ++ HAL_CLOCK_READ(&tv[i]); ++ } ++ tv0 = 0; ++ for (i = 1; i < nsamples; i++) { ++ tv0 += tv[i] - tv[i-1]; ++ } ++ end_of_test_group(); ++ ++ overhead = tv0 / (nsamples-1); ++ diag_printf("Reading the hardware clock takes %d 'ticks' overhead\n", overhead); ++ diag_printf("... this value will be factored out of all other measurements\n"); ++ ++ // Try and measure how long the clock interrupt handling takes ++ for (i = 0; i < nsamples; i++) { ++ tick0 = cyg_current_time(); ++ while (true) { ++ tick1 = cyg_current_time(); ++ if (tick0 != tick1) break; ++ } ++ HAL_CLOCK_READ(&tv[i]); ++ } ++ tv1 = 0; ++ for (i = 0; i < nsamples; i++) { ++ tv1 += tv[i] * 1000; ++ } ++ tv1 = tv1 / nsamples; ++ tv1 -= overhead; // Adjust out the cost of getting the timer value ++ diag_printf("Clock interrupt took"); ++ show_ticks_in_us(tv1); ++ diag_printf(" microseconds (%d raw clock ticks)\n", tv1/1000); ++ enable_clock_latency_measurement(); ++ ++ ticks = cyg_current_time(); ++ ++ show_test_parameters(); ++ show_times_hdr(); ++ ++ reset_clock_latency_measurement(); ++ ++ run_thread_tests(); ++ run_mutex_tests(); ++// run_mbox_tests(); ++ run_semaphore_tests(); ++ run_timer_tests(); ++ ++#ifdef CYG_SCHEDULER_LOCK_TIMINGS ++ Cyg_Scheduler::get_lock_times(&lock_ave, &lock_max); ++ diag_printf("\nMax lock:"); ++ show_ticks_in_us(lock_max); ++ diag_printf(", Ave lock:"); ++ show_ticks_in_us(lock_ave); ++ diag_printf("\n"); ++#endif ++ ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY) ++ // Display latency figures in same format as all other numbers ++ disable_clock_latency_measurement(); ++ clock_ave = (total_clock_latency*1000) / total_clock_interrupts; ++ show_ticks_in_us(clock_ave); ++ show_ticks_in_us(min_clock_latency*1000); ++ show_ticks_in_us(max_clock_latency*1000); ++ show_ticks_in_us(0); ++ diag_printf(" Clock/interrupt latency\n\n"); ++ enable_clock_latency_measurement(); ++#endif ++ ++#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY) ++ disable_clock_latency_measurement(); ++ clock_ave = (total_clock_dsr_latency*1000) / total_clock_dsr_calls; ++ show_ticks_in_us(clock_ave); ++ show_ticks_in_us(min_clock_dsr_latency*1000); ++ show_ticks_in_us(max_clock_dsr_latency*1000); ++ show_ticks_in_us(0); ++ diag_printf(" Clock DSR latency\n\n"); ++ enable_clock_latency_measurement(); ++#endif ++ ++#if 0 ++ disable_clock_latency_measurement(); ++ min_stack = STACK_SIZE; ++ max_stack = 0; ++ total_stack = 0; ++ for (i = 0; i < (int)NTEST_THREADS; i++) { ++ for (j = 0; j < STACK_SIZE; j++) { ++ if (stacks[i][j]) break; ++ } ++ actual_stack = STACK_SIZE-j; ++ if (actual_stack < min_stack) min_stack = actual_stack; ++ if (actual_stack > max_stack) max_stack = actual_stack; ++ total_stack += actual_stack; ++ } ++ for (j = 0; j < STACKSIZE; j++) { ++ if (((char *)stack[0])[j]) break; ++ } ++ diag_printf("%5d %5d %5d (main stack: %5d) Thread stack used (%d total)\n", ++ total_stack/NTEST_THREADS, min_stack, max_stack, ++ STACKSIZE - j, STACK_SIZE); ++#endif ++ ++// cyg_test_dump_thread_stack_stats( "All done, main stack", thread[0] ); ++ cyg_test_dump_interrupt_stack_stats( "All done" ); ++ cyg_test_dump_idlethread_stack_stats( "All done" ); ++ ++ enable_clock_latency_measurement(); ++ ++ ticks = cyg_current_time(); ++ diag_printf("\nTiming complete - %d ms total\n\n", (int)((ticks*ns_per_system_clock)/1000)); ++ ++ CYG_TEST_PASS_FINISH("Basic timing OK"); ++} ++ ++int main( int argc, char **argv ) ++{ ++ CYG_TEST_INIT(); ++ ++ if (cyg_test_is_simulator) { ++ nsamples = NSAMPLES_SIM; ++ ntest_threads = NTEST_THREADS_SIM; ++ nthread_switches = NTHREAD_SWITCHES_SIM; ++ nmutexes = NMUTEXES_SIM; ++ nmboxes = NMBOXES_SIM; ++ nsemaphores = NSEMAPHORES_SIM; ++ nscheds = NSCHEDS_SIM; ++ ntimers = NTIMERS_SIM; ++ } else { ++ nsamples = NSAMPLES; ++ ntest_threads = NTEST_THREADS; ++ nthread_switches = NTHREAD_SWITCHES; ++ nmutexes = NMUTEXES; ++ nmboxes = NMBOXES; ++ nsemaphores = NSEMAPHORES; ++ nscheds = NSCHEDS; ++ ntimers = NTIMERS; ++ } ++ ++ // Sanity ++#ifdef WORKHORSE_TEST ++ ntest_threads = max(512, ntest_threads); ++ nmutexes = max(1024, nmutexes); ++ nsemaphores = max(1024, nsemaphores); ++ nmboxes = max(1024, nmboxes); ++ ncounters = max(1024, ncounters); ++ ntimers = max(1024, ntimers); ++#else ++ ntest_threads = max(64, ntest_threads); ++ nmutexes = max(32, nmutexes); ++ nsemaphores = max(32, nsemaphores); ++ nmboxes = max(32, nmboxes); ++ ntimers = max(32, ntimers); ++#endif ++ ++ run_all_tests(); ++ ++} ++ ++#endif // CYGFUN_KERNEL_API_C, etc. ++ ++// EOF tm_basic.cxx +diff -urNad redboot-imx-200952~/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_load.c redboot-imx-200952/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_load.c +--- redboot-imx-200952~/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_load.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_load.c 2010-01-26 17:33:11.992955131 +0000 +@@ -0,0 +1,294 @@ ++//========================================================================== ++// ++// flexcan_load.c ++// ++// FlexCAN load test ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Uwe Kindler ++// Contributors: Uwe Kindler ++// Date: 2005-08-14 ++// Description: FlexCAN load test ++//####DESCRIPTIONEND#### ++ ++ ++//=========================================================================== ++// INCLUDES ++//=========================================================================== ++#include ++ ++#include // test macros ++#include // assertion macros ++#include ++ ++// Package requirements ++#if defined(CYGPKG_IO_CAN) && defined(CYGPKG_KERNEL) ++ ++#include ++#include ++#include ++ ++// Package option requirements ++#if defined(CYGFUN_KERNEL_API_C) ++ ++#include // CYGNUM_HAL_STACK_SIZE_TYPICAL ++#include ++ ++ ++//=========================================================================== ++// DATA TYPES ++//=========================================================================== ++typedef struct st_thread_data ++{ ++ cyg_thread obj; ++ long stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; ++ cyg_handle_t hdl; ++} thread_data_t; ++ ++ ++//=========================================================================== ++// LOCAL DATA ++//=========================================================================== ++cyg_thread_entry_t can0_thread; ++thread_data_t can0_thread_data; ++ ++cyg_thread_entry_t can1_thread; ++thread_data_t can1_thread_data; ++ ++cyg_io_handle_t hDrvFlexCAN; ++ ++ ++//=========================================================================== ++// LOCAL FUNCTIONS ++//=========================================================================== ++#include "can_test_aux.inl" // include CAN test auxiliary functions ++ ++ ++//=========================================================================== ++// READER THREAD ++//=========================================================================== ++void can0_thread(cyg_addrword_t data) ++{ ++ cyg_uint32 len; ++ cyg_can_event rx_event; ++ cyg_can_timeout_info_t timeouts; ++ ++#if defined(CYGOPT_IO_CAN_SUPPORT_TIMEOUTS) ++ // ++ // setup large timeout values because we do not need timeouts here ++ // ++ timeouts.rx_timeout = 100000; ++ timeouts.tx_timeout = 100000; ++ ++ len = sizeof(timeouts); ++ if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_TIMEOUT ,&timeouts, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0"); ++ } ++#endif // defined(CYGOPT_IO_CAN_SUPPORT_TIMEOUTS) ++ ++ // ++ // This thread simply receives all CAN events and prints the event flags and the ++ // CAN message if it was a TX or RX event. You can use this test in order to check ++ // when a RX overrun occurs ++ // ++ while (1) ++ { ++ len = sizeof(rx_event); ++ ++ if (ENOERR != cyg_io_read(hDrvFlexCAN, &rx_event, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error reading from /dev/can0"); ++ } ++ else ++ { ++ print_can_flags(rx_event.flags, ""); ++ ++ if ((rx_event.flags & CYGNUM_CAN_EVENT_RX) || (rx_event.flags & CYGNUM_CAN_EVENT_TX)) ++ { ++ print_can_msg(&rx_event.msg, ""); ++ } ++ } ++ } ++} ++ ++ ++//=========================================================================== ++// WRITER THREAD ++//=========================================================================== ++void can1_thread(cyg_addrword_t data) ++{ ++ cyg_uint16 i = 0; ++ cyg_uint32 len; ++ cyg_can_message tx_msg = ++ { ++ 0x000, // CAN identifier ++ {0x00, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7}, // 8 data bytes ++ CYGNUM_CAN_ID_STD, // standard frame ++ CYGNUM_CAN_FRAME_DATA, // data frame ++ 8, // data length code ++ }; ++ ++ // ++ // This thread simply sends CAN messages. It increments the ID for each new CAN messsage ++ // and sends a remote frame after seven data frames. In the first byte of each data frame ++ // the number (0 - 7) of the data frame is stored and the length of the data frame grows ++ // from 1 - 8 data bytes. ++ // ++ // The received pattern should look like this way: ++ // ID Length Data ++ // ---------------------------------------------- ++ // 000 1 00 ++ // 001 2 01 F1 ++ // 002 3 02 F1 F2 ++ // 003 4 03 F1 F2 F3 ++ // 004 5 04 F1 F2 F3 F4 ++ // 005 6 05 F1 F2 F3 F4 F5 ++ // 006 7 06 F1 F2 F3 F4 F5 F6 ++ // 007 8 Remote Request ++ // 008 1 00 ++ // 009 2 01 F1 ++ // 00A 3 02 F1 F2 ++ // ... ++ // ++ while (1) ++ { ++ tx_msg.id = i; ++ tx_msg.dlc = (i % 8) + 1; ++ tx_msg.data[0] = (i % 8); ++ i = (i + 1) % 0x7FF; ++ ++ // ++ // we send a remote frame after 7 data frames ++ // ++ if (!(i % 8)) ++ { ++ tx_msg.rtr = CYGNUM_CAN_FRAME_RTR; ++ } ++ else ++ { ++ tx_msg.rtr = CYGNUM_CAN_FRAME_DATA; ++ } ++ ++ len = sizeof(tx_msg); ++ if (ENOERR != cyg_io_write(hDrvFlexCAN, &tx_msg, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing to /dev/can0"); ++ } ++ else ++ { ++ print_can_msg(&tx_msg, "TX: "); ++ } ++ ++ cyg_thread_delay(100); ++ } // while (1) ++} ++ ++ ++ ++void ++cyg_start(void) ++{ ++ cyg_uint32 len; ++ cyg_can_info_t can_cfg; ++ ++ CYG_TEST_INIT(); ++ ++ // ++ // open flexcan device driver ++ // ++ if (ENOERR != cyg_io_lookup("/dev/can0", &hDrvFlexCAN)) ++ { ++ CYG_TEST_FAIL_FINISH("Error opening /dev/can0"); ++ } ++ ++ // ++ // setup CAN baudrate 250 KBaud ++ // ++ can_cfg.baud = CYGNUM_CAN_KBAUD_250; ++ len = sizeof(can_cfg); ++ if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_INFO ,&can_cfg, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0"); ++ } ++ ++ // ++ // create the two threads which access the CAN device driver ++ // a reader thread with a higher priority and a writer thread ++ // with a lower priority ++ // ++ cyg_thread_create(4, can0_thread, ++ (cyg_addrword_t) 0, ++ "can0_thread", ++ (void *) can0_thread_data.stack, ++ 1024 * sizeof(long), ++ &can0_thread_data.hdl, ++ &can0_thread_data.obj); ++ ++ cyg_thread_create(5, can1_thread, ++ (cyg_addrword_t) can0_thread_data.hdl, ++ "can1_thread", ++ (void *) can1_thread_data.stack, ++ 1024 * sizeof(long), ++ &can1_thread_data.hdl, ++ &can1_thread_data.obj); ++ ++ cyg_thread_resume(can0_thread_data.hdl); ++ cyg_thread_resume(can1_thread_data.hdl); ++ ++ cyg_scheduler_start(); ++} ++ ++#else // CYGFUN_KERNEL_API_C ++#define N_A_MSG "Needs kernel C API" ++#endif ++ ++#else // CYGPKG_IO_CAN && CYGPKG_KERNEL ++#define N_A_MSG "Needs IO/CAN and Kernel" ++#endif ++ ++#ifdef N_A_MSG ++void ++cyg_start( void ) ++{ ++ CYG_TEST_INIT(); ++ CYG_TEST_NA( N_A_MSG); ++} ++#endif // N_A_MSG ++ ++// EOF flexcan_load.c +diff -urNad redboot-imx-200952~/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_remote.c redboot-imx-200952/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_remote.c +--- redboot-imx-200952~/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_remote.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/can/m68k/mcf52xx/current/tests/flexcan_remote.c 2010-01-26 17:33:11.992955131 +0000 +@@ -0,0 +1,233 @@ ++//========================================================================== ++// ++// flexcan_remote.c ++// ++// FlexCAN remote response buffer test ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Uwe Kindler ++// Contributors: Uwe Kindler ++// Date: 2005-08-14 ++// Description: FlexCAN load test ++//####DESCRIPTIONEND#### ++ ++ ++//=========================================================================== ++// INCLUDES ++//=========================================================================== ++#include ++ ++#include // test macros ++#include // assertion macros ++#include ++ ++// Package requirements ++#if defined(CYGPKG_IO_CAN) && defined(CYGPKG_KERNEL) ++ ++#include ++#include ++#include ++ ++// Package option requirements ++#if defined(CYGFUN_KERNEL_API_C) ++ ++#include // CYGNUM_HAL_STACK_SIZE_TYPICAL ++#include ++ ++ ++//=========================================================================== ++// DATA TYPES ++//=========================================================================== ++typedef struct st_thread_data ++{ ++ cyg_thread obj; ++ long stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; ++ cyg_handle_t hdl; ++} thread_data_t; ++ ++ ++//=========================================================================== ++// LOCAL DATA ++//=========================================================================== ++cyg_thread_entry_t can0_thread; ++thread_data_t can0_thread_data; ++ ++ ++cyg_io_handle_t hDrvFlexCAN; ++ ++ ++//=========================================================================== ++// LOCAL FUNCTIONS ++//=========================================================================== ++#include "can_test_aux.inl" // include CAN test auxiliary functions ++ ++ ++//=========================================================================== ++// READER THREAD ++//=========================================================================== ++void can0_thread(cyg_addrword_t data) ++{ ++ cyg_uint32 len; ++ cyg_can_event rx_event; ++ cyg_can_rtr_buf_t rtr_buf; ++ cyg_can_rtr_buf_t rtr_buf2; ++ ++ ++ rtr_buf.handle = CYGNUM_CAN_RTR_BUF_INIT; ++ rtr_buf.msg.id = 0x7FF; ++ rtr_buf.msg.ext = CYGNUM_CAN_ID_STD; ++ rtr_buf.msg.rtr = CYGNUM_CAN_FRAME_DATA; ++ rtr_buf.msg.dlc = 1; ++ rtr_buf.msg.data[0] = 0xAB; ++ ++ len = sizeof(rtr_buf); ++ if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_RTR_BUF ,&rtr_buf, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0"); ++ } ++ ++ if (rtr_buf.handle == CYGNUM_CAN_RTR_BUF_NA) ++ { ++ CYG_TEST_FAIL_FINISH("No free message buffer available for /dev/can0"); ++ } ++ ++ rtr_buf2.handle = CYGNUM_CAN_RTR_BUF_INIT; ++ rtr_buf2.msg.id = 0x7FE; ++ rtr_buf2.msg.ext = CYGNUM_CAN_ID_STD; ++ rtr_buf2.msg.rtr = CYGNUM_CAN_FRAME_DATA; ++ rtr_buf2.msg.dlc = 4; ++ rtr_buf2.msg.data[0] = 0xAB; ++ ++ len = sizeof(rtr_buf2); ++ if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_RTR_BUF ,&rtr_buf2, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0"); ++ } ++ ++ if (rtr_buf.handle == CYGNUM_CAN_RTR_BUF_NA) ++ { ++ CYG_TEST_FAIL_FINISH("No free message buffer available for /dev/can0"); ++ } ++ ++ diag_printf("Test of FlexCAN remote response buffer configuration\n" ++ "If a CAN node sends a remote request with ID 0x7FE\n" ++ "or 0x7FF then the FlexCAN modul should respond with\n" ++ "data frames.\n"); ++ diag_printf("!!! This test can be stopped by sending a data frame with ID 0x100 !!!\n\n"); ++ ++ while (1) ++ { ++ len = sizeof(rx_event); ++ ++ if (ENOERR != cyg_io_read(hDrvFlexCAN, &rx_event, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error reading from /dev/can0"); ++ } ++ ++ if (0x100 == rx_event.msg.id) ++ { ++ CYG_TEST_PASS_FINISH("flexcan_remote test OK"); ++ } ++ } ++ ++ ++} ++ ++ ++void ++cyg_start(void) ++{ ++ cyg_uint32 len; ++ cyg_can_info_t can_cfg; ++ ++ CYG_TEST_INIT(); ++ ++ // ++ // open flexcan device driver ++ // ++ if (ENOERR != cyg_io_lookup("/dev/can0", &hDrvFlexCAN)) ++ { ++ CYG_TEST_FAIL_FINISH("Error opening /dev/can0"); ++ } ++ ++ // ++ // setup CAN baudrate 250 KBaud ++ // ++ can_cfg.baud = CYGNUM_CAN_KBAUD_250; ++ len = sizeof(can_cfg); ++ if (ENOERR != cyg_io_set_config(hDrvFlexCAN, CYG_IO_SET_CONFIG_CAN_INFO ,&can_cfg, &len)) ++ { ++ CYG_TEST_FAIL_FINISH("Error writing config of /dev/can0"); ++ } ++ ++ // ++ // create the two threads which access the CAN device driver ++ // a reader thread with a higher priority and a writer thread ++ // with a lower priority ++ // ++ cyg_thread_create(4, can0_thread, ++ (cyg_addrword_t) 0, ++ "can0_thread", ++ (void *) can0_thread_data.stack, ++ 1024 * sizeof(long), ++ &can0_thread_data.hdl, ++ &can0_thread_data.obj); ++ ++ cyg_thread_resume(can0_thread_data.hdl); ++ ++ cyg_scheduler_start(); ++} ++ ++#else // CYGFUN_KERNEL_API_C ++#define N_A_MSG "Needs kernel C API" ++#endif ++ ++#else // CYGPKG_IO_CAN && CYGPKG_KERNEL ++#define N_A_MSG "Needs IO/CAN and Kernel" ++#endif ++ ++#ifdef N_A_MSG ++void ++cyg_start( void ) ++{ ++ CYG_TEST_INIT(); ++ CYG_TEST_NA( N_A_MSG); ++} ++#endif // N_A_MSG ++ ++// EOF flexcan_remote.c +diff -urNad redboot-imx-200952~/packages/devs/disk/ide/current/cdl/ide_disk.cdl redboot-imx-200952/packages/devs/disk/ide/current/cdl/ide_disk.cdl +--- redboot-imx-200952~/packages/devs/disk/ide/current/cdl/ide_disk.cdl 2004-10-18 09:03:45.000000000 +0000 ++++ redboot-imx-200952/packages/devs/disk/ide/current/cdl/ide_disk.cdl 2010-01-26 17:33:12.022955381 +0000 +@@ -5,37 +5,37 @@ + # A generic IDE disk driver package. + # + # ==================================================================== +-#####ECOSGPLCOPYRIGHTBEGIN#### ++## ####ECOSGPLCOPYRIGHTBEGIN#### + ## ------------------------------------------- + ## This file is part of eCos, the Embedded Configurable Operating System. +-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. +-## Copyright (C) 2004 eCosCentric, Ltd ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. + ## + ## eCos is free software; you can redistribute it and/or modify it under + ## the terms of the GNU General Public License as published by the Free +-## Software Foundation; either version 2 or (at your option) any later version. ++## Software Foundation; either version 2 or (at your option) any later ++## version. + ## +-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## eCos is distributed in the hope that it will be useful, but WITHOUT ++## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + ## for more details. + ## +-## You should have received a copy of the GNU General Public License along +-## with eCos; if not, write to the Free Software Foundation, Inc., +-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-## +-## As a special exception, if other files instantiate templates or use macros +-## or inline functions from this file, or you compile this file and link it +-## with other works to produce a work based on this file, this file does not +-## by itself cause the resulting work to be covered by the GNU General Public +-## License. However the source code for this file must still be made available +-## in accordance with section (3) of the GNU General Public License. ++## You should have received a copy of the GNU General Public License ++## along with eCos; if not, write to the Free Software Foundation, Inc., ++## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + ## +-## This exception does not invalidate any other reasons why a work based on +-## this file might be covered by the GNU General Public License. ++## As a special exception, if other files instantiate templates or use ++## macros or inline functions from this file, or you compile this file ++## and link it with other works to produce a work based on this file, ++## this file does not by itself cause the resulting work to be covered by ++## the GNU General Public License. However the source code for this file ++## must still be made available in accordance with section (3) of the GNU ++## General Public License v2. + ## ++## This exception does not invalidate any other reasons why a work based ++## on this file might be covered by the GNU General Public License. + ## ------------------------------------------- +-#####ECOSGPLCOPYRIGHTEND#### ++## ####ECOSGPLCOPYRIGHTEND#### + # ==================================================================== + ######DESCRIPTIONBEGIN#### + # +@@ -63,7 +63,7 @@ + cdl_option CYGDAT_IO_DISK_IDE_DISK0_NAME { + display "Device name for disk 0 device" + flavor data +- default_value {"\"/dev/hda/\""} ++ default_value {"\"/dev/idedisk0/\""} + } + } + +@@ -76,7 +76,7 @@ + cdl_option CYGDAT_IO_DISK_IDE_DISK1_NAME { + display "Device name for disk 1 device" + flavor data +- default_value {"\"/dev/hdb/\""} ++ default_value {"\"/dev/idedisk1/\""} + } + } + +@@ -89,7 +89,7 @@ + cdl_option CYGDAT_IO_DISK_IDE_DISK2_NAME { + display "Device name for disk 2 device" + flavor data +- default_value {"\"/dev/hdc/\""} ++ default_value {"\"/dev/idedisk2/\""} + } + } + +@@ -102,7 +102,7 @@ + cdl_option CYGDAT_IO_DISK_IDE_DISK3_NAME { + display "Device name for disk 3 device" + flavor data +- default_value {"\"/dev/hdd/\""} ++ default_value {"\"/dev/idedisk3/\""} + } + } + +@@ -114,6 +114,34 @@ + This option controls the disk sector size (default=512)" + } + ++ cdl_option CYGDAT_DEVS_DISK_IDE_STARTUP_DELAY { ++ display "Startup delay (in ms)" ++ flavor data ++ default_value 0 ++ description " ++ The amount of time (in ms) to wait for the IDE drives to ++ initialize on startup. For hard drives, this can usually ++ be set to zero, but for Compact Flash and other solid ++ state media this could be up to 500ms. If drives are not ++ detected at power-up, try increasing this value. ++ " ++ } ++ ++ cdl_option CYGDAT_DEVS_DISK_IDE_8_BIT_DATA_PATH { ++ display "8-bit data path" ++ flavor bool ++ default_value false ++ description " ++ This allows the host to communicate with the IDE drives using an ++ 8-bit data, rather than 16-bits. It does so by requesting a \"Set ++ Feature\" on the drive for the 8-bit path. Note that this may ++ be ignored by most modern disk drives, but is supported by Compact ++ Flash drives. This is only used by proprietary boards, and should ++ be disabled for standard IDE controllers. ++ " ++ } ++ ++ + cdl_option CYGSEM_DEVS_DISK_IDE_VMWARE { + display "Work with VMware virtual disks" + flavor bool +@@ -121,7 +149,6 @@ + description " + This option controls the disk driver behaviour at ide-init" + } +- + } + + # EOF ide_disk.cdl +diff -urNad redboot-imx-200952~/packages/devs/disk/ide/current/src/ide_disk.c redboot-imx-200952/packages/devs/disk/ide/current/src/ide_disk.c +--- redboot-imx-200952~/packages/devs/disk/ide/current/src/ide_disk.c 2006-11-17 18:04:43.000000000 +0000 ++++ redboot-imx-200952/packages/devs/disk/ide/current/src/ide_disk.c 2010-01-26 17:33:12.032973506 +0000 +@@ -2,45 +2,45 @@ + // + // ide_disk.c + // +-// IDE polled mode disk driver ++// IDE polled mode disk driver + // + //========================================================================== + //####ECOSGPLCOPYRIGHTBEGIN#### + // ------------------------------------------- + // This file is part of eCos, the Embedded Configurable Operating System. +-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. +-// Copyright (C) 2004, 2006 eCosCentric, Ltd. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006 Free Software Foundation, Inc. + // + // eCos is free software; you can redistribute it and/or modify it under + // the terms of the GNU General Public License as published by the Free +-// Software Foundation; either version 2 or (at your option) any later version. ++// Software Foundation; either version 2 or (at your option) any later ++// version. + // +-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// eCos is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + // for more details. + // +-// You should have received a copy of the GNU General Public License along +-// with eCos; if not, write to the Free Software Foundation, Inc., +-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-// +-// As a special exception, if other files instantiate templates or use macros +-// or inline functions from this file, or you compile this file and link it +-// with other works to produce a work based on this file, this file does not +-// by itself cause the resulting work to be covered by the GNU General Public +-// License. However the source code for this file must still be made available +-// in accordance with section (3) of the GNU General Public License. ++// You should have received a copy of the GNU General Public License ++// along with eCos; if not, write to the Free Software Foundation, Inc., ++// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + // +-// This exception does not invalidate any other reasons why a work based on +-// this file might be covered by the GNU General Public License. ++// As a special exception, if other files instantiate templates or use ++// macros or inline functions from this file, or you compile this file ++// and link it with other works to produce a work based on this file, ++// this file does not by itself cause the resulting work to be covered by ++// the GNU General Public License. However the source code for this file ++// must still be made available in accordance with section (3) of the GNU ++// General Public License v2. + // ++// This exception does not invalidate any other reasons why a work based ++// on this file might be covered by the GNU General Public License. + // ------------------------------------------- + //####ECOSGPLCOPYRIGHTEND#### + //========================================================================== + //#####DESCRIPTIONBEGIN#### + // + // Author(s): iz +-// Contributors: ++// Contributors: + // Date: 2004-10-16 + // + //####DESCRIPTIONEND#### +@@ -48,6 +48,7 @@ + //========================================================================== + + #include ++#include + + #include + #include +@@ -64,7 +65,9 @@ + + // ---------------------------------------------------------------------------- + +-//#define DEBUG 1 ++#ifdef CYGDBG_IO_DISK_DEBUG ++#define DEBUG 1 ++#endif + + #ifdef DEBUG + # define D(fmt,args...) diag_printf(fmt, ## args) +@@ -94,6 +97,8 @@ + IDE_DISK_INSTANCE(3, 1, 1, true, CYGDAT_IO_DISK_IDE_DISK3_NAME); + #endif + ++#define MIN(a,b) (((a) < (b)) ? (a) : (b)) ++ + // ---------------------------------------------------------------------------- + + static void +@@ -101,8 +106,7 @@ + { + int i; + +- for (i = 0; i < size; i+=2) +- { ++ for (i=0; i> 8); + *dest++ = (char)(*src & 0x00FF); + src++; +@@ -121,22 +125,26 @@ + } while (status & (IDE_STAT_BSY | IDE_STAT_DRQ)); + } + ++// ---------------------------------------------------------------------------- + // Wait while the device is busy with the last command ++ + static inline int + __wait_busy(int ctlr) + { + cyg_uint8 status; + cyg_ucount32 tries; +- ++ + for (tries=0; tries < 1000000; tries++) { + CYGACC_CALL_IF_DELAY_US(10); + HAL_IDE_READ_UINT8(ctlr, IDE_REG_STATUS, status); + if ((status & IDE_STAT_BSY) == 0) + return 1; + } +- return 0; ++ return 0; + } + ++// ---------------------------------------------------------------------------- ++ + static inline int + __wait_for_drq(int ctlr) + { +@@ -156,18 +164,20 @@ + return 0; + } + ++// ---------------------------------------------------------------------------- + // Return true if any devices attached to controller ++ + static int + ide_presence_detect(int ctlr) + { + cyg_uint8 sel, val; + int i; + +- for (i = 0; i < 2; i++) { ++ for (i = 0; i < HAL_IDE_NUM_CONTROLLERS; i++) { + sel = (i << 4) | 0xA0; +- CYGACC_CALL_IF_DELAY_US((cyg_uint32)50000); ++ CYGACC_CALL_IF_DELAY_US(50000U); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_DEVICE, sel); +- CYGACC_CALL_IF_DELAY_US((cyg_uint32)50000); ++ CYGACC_CALL_IF_DELAY_US(50000U); + HAL_IDE_READ_UINT8(ctlr, IDE_REG_DEVICE, val); + if (val == sel) { + #ifndef CYGSEM_DEVS_DISK_IDE_VMWARE +@@ -180,6 +190,8 @@ + return 0; + } + ++// ---------------------------------------------------------------------------- ++ + static int + ide_reset(int ctlr) + { +@@ -193,14 +205,14 @@ + // + #ifndef CYGSEM_DEVS_DISK_IDE_VMWARE + HAL_IDE_WRITE_CONTROL(ctlr, 6); // polled mode, reset asserted +- CYGACC_CALL_IF_DELAY_US(5000); ++ CYGACC_CALL_IF_DELAY_US(5000U); + HAL_IDE_WRITE_CONTROL(ctlr, 2); // polled mode, reset cleared +- CYGACC_CALL_IF_DELAY_US((cyg_uint32)50000); ++ CYGACC_CALL_IF_DELAY_US(50000U); + #endif + + // wait 30 seconds max for not busy and drive ready + for (delay = 0; delay < 300; ++delay) { +- CYGACC_CALL_IF_DELAY_US((cyg_uint32)100000); ++ CYGACC_CALL_IF_DELAY_US(100000U); + HAL_IDE_READ_UINT8(ctlr, IDE_REG_STATUS, status); + if (!(status & IDE_STAT_BSY)) { + if (status & IDE_STAT_DRDY) { +@@ -211,43 +223,76 @@ + return 0; + } + ++// ---------------------------------------------------------------------------- ++ + static int + ide_ident(int ctlr, int dev, cyg_uint16 *buf) + { + int i; + +- if (!__wait_busy(ctlr)) { ++ if (!__wait_busy(ctlr)) + return 0; +- } +- ++ + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_DEVICE, dev << 4); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_COMMAND, 0xEC); +- CYGACC_CALL_IF_DELAY_US((cyg_uint32)50000); ++ CYGACC_CALL_IF_DELAY_US(50000U); + +- if (!__wait_for_drq(ctlr)) { ++ if (!__wait_for_drq(ctlr)) + return 0; +- } +- ++ + for (i = 0; i < (CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16)); +- i++, buf++) ++ i++, buf++) { + HAL_IDE_READ_UINT16(ctlr, IDE_REG_DATA, *buf); +- ++ } + return 1; + } + ++// ---------------------------------------------------------------------------- ++// Requests the disk to use an 8-bit data path. This is probably ignored by ++// most modern drives, but is supported by compact flash devices. ++ ++#ifdef CYGDAT_DEVS_DISK_IDE_8_BIT_DATA_PATH + static int +-ide_read_sector(int ctlr, int dev, cyg_uint32 start, +- cyg_uint8 *buf, cyg_uint32 len) ++ide_8bit_mode(int ctlr, int dev, cyg_bool on) + { +- int j, c; +- cyg_uint16 p; +- cyg_uint8 * b=buf; ++ cyg_uint8 stat; + +- if(!__wait_busy(ctlr)) { ++ if (!__wait_busy(ctlr)) + return 0; +- } + +- HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_COUNT, 1); // count =1 ++ HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_DEVICE, dev << 4); ++ HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_FEATURES, 0x01); ++ HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_COMMAND, 0xEF); ++ ++ if (!__wait_busy(ctlr)) ++ return 0; ++ ++ HAL_IDE_READ_UINT8(ctlr, IDE_REG_STATUS, stat); ++ return (stat & 1) ? 0 : 1; ++} ++#endif ++ ++// ---------------------------------------------------------------------------- ++// Reads a group of contiguous sectors from the drive. ++// It can read up to 256 sectors. ++ ++static int ++ide_read_sector(int ctlr, int dev, cyg_uint32 start, ++ cyg_uint8 *buf, cyg_uint32 len) ++{ ++ int i, nword; ++ cyg_uint8 lenb; ++ cyg_uint16 w; ++ ++ if (len==0 || !__wait_busy(ctlr)) ++ return 0; ++ ++ len = MIN(len, 256); ++ lenb = (len == 256) ? 0 : ((cyg_uint8) len); ++ ++ nword = len * CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16); ++ ++ HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_COUNT, lenb); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_LBALOW, start & 0xff); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_LBAMID, (start >> 8) & 0xff); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_LBAHI, (start >> 16) & 0xff); +@@ -257,32 +302,44 @@ + + if (!__wait_for_drq(ctlr)) + return 0; +- // +- // It would be fine if all buffers were word aligned, +- // but who knows +- // +- for (j = 0, c=0 ; j < (CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16)); +- j++) { +- HAL_IDE_READ_UINT16(ctlr, IDE_REG_DATA, p); +- if (c++<(len*512)) *b++=p&0xff; +- if (c++<(len*512)) *b++=(p>>8)&0xff; ++ ++ if ((int) buf & 1) { ++ // Unaligned buffer, so split each word manually ++ for (i=0; i>8) & 0xff; ++ } + } +- return 1; ++ else { ++ cyg_uint16* wbuf = (cyg_uint16*) buf; ++ for (i=0; i> 8) & 0xff); + HAL_IDE_WRITE_UINT8(ctlr, IDE_REG_LBAHI, (start >> 16) & 0xff); +@@ -292,22 +349,26 @@ + + if (!__wait_for_drq(ctlr)) + return 0; +- // +- // It would be fine if all buffers were word aligned, +- // but who knows +- // +- for (j = 0, c=0 ; j < (CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE / sizeof(cyg_uint16)); +- j++) { +- p = (c++<(len*512)) ? *b++ : 0; +- p |= (c++<(len*512)) ? (*b++<<8) : 0; +- HAL_IDE_WRITE_UINT16(ctlr, IDE_REG_DATA, p); ++ ++ if ((int) buf & 1) { ++ // Unaligned buffer, so assemble each word manually ++ for (i=0; ipriv; +@@ -317,17 +378,22 @@ + static int ide_present[4], ide_reset_done[4]; + cyg_disk_identify_t ident; + ide_identify_data_t *ide_idData=(ide_identify_data_t*)id_buf; +- +- if (chan->init) ++ ++ if (chan->init) + return true; + + D("IDE(%d:%d) hw init\n", info->port, info->chan); +- ++ + if (!num_controllers) num_controllers=HAL_IDE_INIT(); + if (info->chan>=num_controllers) { + D("No IDE controller for channel %d:%d\n", info->port, info->chan); + return false; + } ++ ++#if CYGDAT_DEVS_DISK_IDE_STARTUP_DELAY ++ CYGACC_CALL_IF_DELAY_US(CYGDAT_DEVS_DISK_IDE_STARTUP_DELAY*1000U); ++#endif ++ + if (!ide_present[info->port]) { + ide_present[info->port]=ide_presence_detect(info->port); + if (!ide_present[info->port]) { +@@ -342,9 +408,16 @@ + return false; + } + } ++ ++#ifdef CYGDAT_DEVS_DISK_IDE_8_BIT_DATA_PATH ++ if (!ide_8bit_mode(info->port, info->chan, true)) { ++ D("IDE disk %d:%d failed to enter 8-bit mode\n", ++ info->port, info->chan); ++ } ++#endif + + D("IDE %d:%d identify drive\n", info->port, info->chan); +- ++ + if (!ide_ident(info->port, info->chan, (cyg_uint16 *)id_buf)) { + diag_printf("IDE %d:%d ident DRQ error\n", info->port, info->chan); + return false; +@@ -353,27 +426,23 @@ + id_strcpy(ident.serial, ide_idData->serial, 20); + id_strcpy(ident.firmware_rev, ide_idData->firmware_rev, 8); + id_strcpy(ident.model_num, ide_idData->model_num, 40); +- ++ + ident.cylinders_num = ide_idData->num_cylinders; + ident.heads_num = ide_idData->num_heads; + ident.sectors_num = ide_idData->num_sectors; +- ident.lba_sectors_num = ide_idData->lba_total_sectors[1] << 16 | ++ ident.lba_sectors_num = ide_idData->lba_total_sectors[1] << 16 | + ide_idData->lba_total_sectors[0]; + ident.phys_block_size = 1; ++ ++ // TODO: Should this be CYGDAT_DEVS_DISK_IDE_SECTOR_SIZE? + ident.max_transfer = 512; +- ++ + D("\tSerial : %s\n", ident.serial); + D("\tFirmware rev. : %s\n", ident.firmware_rev); + D("\tModel : %s\n", ident.model_num); +- D("\tC/H/S : %d/%d/%d\n", ident.cylinders_num, ++ D("\tC/H/S : %d/%d/%d\n", ident.cylinders_num, + ident.heads_num, ident.sectors_num); +- D("\tKind : %x\n", (ide_idData->general_conf>>8)&0x1f); + +- if (((ide_idData->general_conf>>8)&0x1f)!=2) { +- diag_printf("IDE device %d:%d is not a hard disk!\n", +- info->port, info->chan); +- return false; +- } + if (!(chan->callbacks->disk_init)(tab)) + return false; + +@@ -385,8 +454,8 @@ + + // ---------------------------------------------------------------------------- + +-static Cyg_ErrNo +-ide_disk_lookup(struct cyg_devtab_entry **tab, ++static Cyg_ErrNo ++ide_disk_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) + { +@@ -396,20 +465,20 @@ + + // ---------------------------------------------------------------------------- + +-static Cyg_ErrNo +-ide_disk_read(disk_channel *chan, ++static Cyg_ErrNo ++ide_disk_read(disk_channel *chan, + void *buf, +- cyg_uint32 len, ++ cyg_uint32 len, + cyg_uint32 block_num) + { + ide_disk_info_t *info = (ide_disk_info_t *)chan->dev_priv; + + D("IDE %d:%d read block %d\n", info->port, info->chan, block_num); + +- if (!ide_read_sector(info->port, info->chan, block_num, ++ if (!ide_read_sector(info->port, info->chan, block_num, + (cyg_uint8 *)buf, len)) { + diag_printf("IDE %d:%d read DRQ error\n", info->port, info->chan); +- return -EIO; ++ return -EIO; + } + + return ENOERR; +@@ -417,31 +486,31 @@ + + // ---------------------------------------------------------------------------- + +-static Cyg_ErrNo +-ide_disk_write(disk_channel *chan, ++static Cyg_ErrNo ++ide_disk_write(disk_channel *chan, + const void *buf, +- cyg_uint32 len, ++ cyg_uint32 len, + cyg_uint32 block_num) + { + ide_disk_info_t *info = (ide_disk_info_t *)chan->dev_priv; + + D("IDE %d:%d write block %d\n", info->port, info->chan, block_num); + +- if (!ide_write_sector(info->port, info->chan, block_num, ++ if (!ide_write_sector(info->port, info->chan, block_num, + (cyg_uint8 *)buf, len)) { + diag_printf("IDE %d:%d read DRQ error\n", info->port, info->chan); +- return -EIO; ++ return -EIO; + } +- ++ + return ENOERR; + } + + // ---------------------------------------------------------------------------- + + static Cyg_ErrNo +-ide_disk_get_config(disk_channel *chan, ++ide_disk_get_config(disk_channel *chan, + cyg_uint32 key, +- const void *xbuf, ++ const void *xbuf, + cyg_uint32 *len) + { + return -EINVAL; +@@ -450,9 +519,9 @@ + // ---------------------------------------------------------------------------- + + static Cyg_ErrNo +-ide_disk_set_config(disk_channel *chan, ++ide_disk_set_config(disk_channel *chan, + cyg_uint32 key, +- const void *xbuf, ++ const void *xbuf, + cyg_uint32 *len) + { + return -EINVAL; +diff -urNad redboot-imx-200952~/packages/devs/disk/ide/current/src/ide_disk.h redboot-imx-200952/packages/devs/disk/ide/current/src/ide_disk.h +--- redboot-imx-200952~/packages/devs/disk/ide/current/src/ide_disk.h 2006-09-21 16:36:24.000000000 +0000 ++++ redboot-imx-200952/packages/devs/disk/ide/current/src/ide_disk.h 2010-01-26 17:33:12.042962756 +0000 +@@ -10,32 +10,32 @@ + //####ECOSGPLCOPYRIGHTBEGIN#### + // ------------------------------------------- + // This file is part of eCos, the Embedded Configurable Operating System. +-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. +-// Copyright (C) 2004 eCosCentric, Ltd. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. + // + // eCos is free software; you can redistribute it and/or modify it under + // the terms of the GNU General Public License as published by the Free +-// Software Foundation; either version 2 or (at your option) any later version. ++// Software Foundation; either version 2 or (at your option) any later ++// version. + // +-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// eCos is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + // for more details. + // +-// You should have received a copy of the GNU General Public License along +-// with eCos; if not, write to the Free Software Foundation, Inc., +-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-// +-// As a special exception, if other files instantiate templates or use macros +-// or inline functions from this file, or you compile this file and link it +-// with other works to produce a work based on this file, this file does not +-// by itself cause the resulting work to be covered by the GNU General Public +-// License. However the source code for this file must still be made available +-// in accordance with section (3) of the GNU General Public License. ++// You should have received a copy of the GNU General Public License ++// along with eCos; if not, write to the Free Software Foundation, Inc., ++// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + // +-// This exception does not invalidate any other reasons why a work based on +-// this file might be covered by the GNU General Public License. ++// As a special exception, if other files instantiate templates or use ++// macros or inline functions from this file, or you compile this file ++// and link it with other works to produce a work based on this file, ++// this file does not by itself cause the resulting work to be covered by ++// the GNU General Public License. However the source code for this file ++// must still be made available in accordance with section (3) of the GNU ++// General Public License v2. + // ++// This exception does not invalidate any other reasons why a work based ++// on this file might be covered by the GNU General Public License. + // ------------------------------------------- + //####ECOSGPLCOPYRIGHTEND#### + //========================================================================== +diff -urNad redboot-imx-200952~/packages/devs/eth/arm/imx_3stack/current/cdl/board_eth_drivers.cdl redboot-imx-200952/packages/devs/eth/arm/imx_3stack/current/cdl/board_eth_drivers.cdl +--- redboot-imx-200952~/packages/devs/eth/arm/imx_3stack/current/cdl/board_eth_drivers.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/arm/imx_3stack/current/cdl/board_eth_drivers.cdl 2010-01-26 17:33:12.142957750 +0000 +@@ -0,0 +1,95 @@ ++# ==================================================================== ++# ++# board_eth_drivers.cdl ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++ ++cdl_package CYGPKG_DEVS_ETH_ARM_IMX_3STACK { ++ display "Ethernet driver for Freescale MXC Board development board" ++ ++ parent CYGPKG_IO_ETH_DRIVERS ++ active_if CYGPKG_IO_ETH_DRIVERS ++ ++ include_dir cyg/io ++ ++ # FIXME: This really belongs in the SMSC LAN92xx package ++ cdl_interface CYGINT_DEVS_ETH_SMSC_LAN92XX_REQUIRED { ++ display "SMSC LAN92XX ethernet driver required" ++ } ++ ++ define_proc { ++ puts $::cdl_system_header "/***** ethernet driver proc output start *****/" ++ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN92XX_INL " ++ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN92XX_CFG " ++ puts $::cdl_system_header "/***** ethernet driver proc output end *****/" ++ } ++ ++ cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 { ++ display "MXC Board ethernet port driver" ++ flavor bool ++ default_value 1 ++ description " ++ This option includes the ethernet device driver for the ++ MXC Board port." ++ ++ implements CYGHWR_NET_DRIVER_ETH0 ++ implements CYGINT_DEVS_ETH_SMSC_LAN92XX_REQUIRED ++ ++ cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME { ++ display "Device name for the ETH0 ethernet driver" ++ flavor data ++ default_value {"\"eth0\""} ++ description " ++ This option sets the name of the ethernet device." ++ } ++ ++ cdl_component CYGSEM_DEVS_ETH_ARM_MXCBOARD_ETH0_SET_ESA { ++ display "Set the ethernet station address" ++ flavor bool ++ default_value 0 ++ description "Enabling this option will allow the ethernet ++ station address to be forced to the value set by the ++ configuration. This may be required if the hardware does ++ not include a serial EEPROM for the ESA." ++ ++ cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_ESA { ++ display "The ethernet station address" ++ flavor data ++ default_value {"{0x08, 0x88, 0x12, 0x34, 0x56, 0x78}"} ++ description "The ethernet station address" ++ } ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/eth/arm/imx_3stack/current/include/devs_eth_arm_board.inl redboot-imx-200952/packages/devs/eth/arm/imx_3stack/current/include/devs_eth_arm_board.inl +--- redboot-imx-200952~/packages/devs/eth/arm/imx_3stack/current/include/devs_eth_arm_board.inl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/arm/imx_3stack/current/include/devs_eth_arm_board.inl 2010-01-26 17:33:12.142957750 +0000 +@@ -0,0 +1,101 @@ ++//========================================================================== ++// ++// devs_eth_arm_board.inl ++// ++// Board ethernet I/O definitions. ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== ++ ++#include // CYGNUM_HAL_INTERRUPT_ETHR ++#include ++ ++#ifdef CYGPKG_REDBOOT ++#include ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++#include ++#include ++#endif ++#endif ++ ++extern unsigned int sys_ver; ++ ++#ifdef __WANT_DEVS ++ ++#ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 ++#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG) ++RedBoot_config_option("Set " CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]", ++ eth0_esa, ++ ALWAYS_ENABLED, true, ++ CONFIG_BOOL, false ++ ); ++RedBoot_config_option(CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]", ++ eth0_esa_data, ++ "eth0_esa", true, ++ CONFIG_ESA, 0 ++ ); ++#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG ++ ++#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT ++// Note that this section *is* active in an application, outside RedBoot, ++// where the above section is not included. ++ ++#include ++ ++#ifndef CONFIG_ESA ++#define CONFIG_ESA (6) ++#endif ++#ifndef CONFIG_BOOL ++#define CONFIG_BOOL (1) ++#endif ++ ++cyg_bool _board_provide_eth0_esa(unsigned char * mac) ++{ ++ cyg_bool set_esa; ++ int ok; ++ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "eth0_esa", &set_esa, CONFIG_BOOL); ++ if (ok && set_esa) { ++ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "eth0_esa_data", mac, CONFIG_ESA); ++ } ++ ++ return ok && set_esa; ++} ++#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT ++ ++#endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 ++ ++#endif // __WANT_DEVS +diff -urNad redboot-imx-200952~/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c redboot-imx-200952/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c +--- redboot-imx-200952~/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c 2007-09-11 17:37:23.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c 2010-01-26 17:33:12.252954008 +0000 +@@ -171,7 +171,9 @@ + cyg_addrword_t base = cpd->base; + cyg_uint16 chip_type, chip_rev, chip_status; + cyg_uint16 i; ++#ifndef CS8900A_RESET_BYPASS + long timeout = 500000; ++#endif + cyg_bool esa_configured = false; + + cpd->tab = tab; +@@ -222,6 +224,7 @@ + } + + CYGHWR_CL_CS8900A_PLF_RESET(base); ++#ifndef CS8900A_RESET_BYPASS + put_reg(base, PP_SelfCtl, PP_SelfCtl_Reset); // Reset chip + + CYGHWR_CL_CS8900A_PLF_POST_RESET(base); +@@ -234,6 +237,7 @@ + return false; + } + } ++#endif /* CS8900A_RESET_BYPASS */ + + chip_status = get_reg(base, PP_SelfStat); + #if DEBUG & 8 +@@ -520,6 +524,7 @@ + if( !timeout ) { + // we might as well just return, since if we write the data it will + // just get thrown away ++ diag_printf("if_cs8900a.c: PP_BusStat_TXRDY is not set. Cannot transmit packet\n"); + return; + } + } +@@ -698,6 +703,7 @@ + cyg_uint16 event; + cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private; + cyg_addrword_t base = cpd->base; ++ volatile int timeout=5000; + + HAL_READ_UINT16(base+CS8900A_ISQ, event); + while (event != 0) { +@@ -723,6 +729,8 @@ + #endif + break; + } ++ while(timeout--); ++ timeout=5000; + HAL_READ_UINT16(base+CS8900A_ISQ, event); + } + +diff -urNad redboot-imx-200952~/packages/devs/eth/fec/current/cdl/fec_eth_drivers.cdl redboot-imx-200952/packages/devs/eth/fec/current/cdl/fec_eth_drivers.cdl +--- redboot-imx-200952~/packages/devs/eth/fec/current/cdl/fec_eth_drivers.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/fec/current/cdl/fec_eth_drivers.cdl 2010-01-26 17:33:12.272957884 +0000 +@@ -0,0 +1,89 @@ ++# ==================================================================== ++# ++# cl_mxc_fec_eth_drivers.cdl ++# ++# Ethernet driver for i.MXx FEC controller ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Fred Fan ++# Contributors: Fred Fan ++# Date: 2006-08-23 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_ETH_FEC { ++ display "Driver for fast ethernet controller." ++ ++ parent CYGPKG_IO_ETH_DRIVERS ++ active_if CYGPKG_IO_ETH_DRIVERS ++ ++ implements CYGHWR_NET_DRIVERS ++ implements CYGINT_IO_ETH_MULTICAST ++ ++ active_if CYGINT_DEVS_ETH_FEC_REQUIRED ++ ++ include_dir cyg/io ++ description "Driver for fast ethernet controller." ++ compile -library=libextras.a if_fec.c ++ ++ define_proc { ++ puts $::cdl_header "#include "; ++ puts $::cdl_header "#include CYGDAT_DEVS_ETH_FEC_CFG"; ++ } ++ ++ cdl_component CYGPKG_DEVS_ETH_FEC_OPTIONS { ++ display "MXC FEC ethernet driver build options" ++ flavor none ++ no_define ++ ++ cdl_option CYGPKG_DEVS_ETH_FEC_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "-D_KERNEL -D__ECOS" } ++ description " ++ This option modifies the set of compiler flags for ++ building the Cirrus Logic ethernet driver package. ++ These flags are used in addition ++ to the set of global flags." ++ } ++ } ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/eth/fec/current/include/fec.h redboot-imx-200952/packages/devs/eth/fec/current/include/fec.h +--- redboot-imx-200952~/packages/devs/eth/fec/current/include/fec.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/fec/current/include/fec.h 2010-01-26 17:33:12.272957884 +0000 +@@ -0,0 +1,303 @@ ++#ifndef _CYGONCE_ETH_FEC_H_ ++#define _CYGONCE_ETH_FEC_H_ ++//========================================================================== ++// ++// dev/mxc_fec.h ++// ++// Fast Ethernet MAC controller in i.MXx ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//####BSDCOPYRIGHTBEGIN#### ++// ++// ++//####BSDCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Fred Fan ++// Contributors: ++// Date: 2006-08-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++ ++#include ++/* The defines of event bits */ ++#define FEC_EVENT_HBERR 0x80000000 ++#define FEC_EVENT_BABR 0x40000000 ++#define FEC_EVENT_BABT 0x20000000 ++#define FEC_EVENT_GRA 0x10000000 ++#define FEC_EVENT_TXF 0x08000000 ++#define FEC_EVENT_TXB 0x04000000 ++#define FEC_EVENT_RXF 0x02000000 ++#define FEC_EVENT_RXB 0x01000000 ++#define FEC_EVENT_MII 0x00800000 ++#define FEC_EVENT_EBERR 0x00400000 ++#define FEC_EVENT_LC 0x00200000 ++#define FEC_EVENT_RL 0x00100000 ++#define FEC_EVENT_UN 0x00080000 ++ ++#define FEC_EVENT_TX FEC_EVENT_TXF ++#define FEC_EVENT_TX_ERR (FEC_EVENT_BABT | FEC_EVENT_LC | FEC_EVENT_RL | FEC_EVENT_UN) ++#define FEC_EVENT_RX FEC_EVENT_RXF ++#define FEC_EVENT_ERR (FEC_EVENT_HBERR | FEC_EVENT_EBERR) ++ ++#define FEC_RX_FRAMES ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT/2)+1) ++#define FEC_FRAME_LEN (1540+4) ++ ++/* the defines to active transmit or receive frame */ ++#define FEC_RX_TX_ACTIVE 0x01000000 ++ ++/* the defines of Ethernet Control register */ ++#define FEC_RESET 0x00000001 ++#define FEC_ETHER_EN 0x00000002 ++ ++/* the defins of MII operation */ ++#define FEC_MII_ST 0x40000000 ++#define FEC_MII_OP_OFF 28 ++#define FEC_MII_OP_MASK 0x03 ++#define FEC_MII_OP_RD 0x02 ++#define FEC_MII_OP_WR 0x01 ++#define FEC_MII_PA_OFF 23 ++#define FEC_MII_PA_MASK 0xFF ++#define FEC_MII_RA_OFF 18 ++#define FEC_MII_RA_MASK 0xFF ++#define FEC_MII_TA 0x00020000 ++#define FEC_MII_DATA_OFF 0 ++#define FEC_MII_DATA_MASK 0x0000FFFF ++ ++#define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA ) ++#define FEC_MII_OP(x) ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF ) ++#define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF) ++#define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF) ++#define FEC_MII_SET_DATA(v) (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF) ++#define FEC_MII_GET_DATA(v) (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK ) ++#define FEC_MII_READ(pa, ra) ( ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD) )|\ ++ FEC_MII_PA(pa) | FEC_MII_RA(ra) ) ++#define FEC_MII_WRITE(pa, ra, v) ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR)|\ ++ FEC_MII_PA(pa) | FEC_MII_RA(ra) |FEC_MII_SET_DATA(v) ) ++ ++#define MII_SPEED_SHIFT 1 ++#define MII_SPEED_MASK 0x0000003F ++#define MII_SPEED(x) ( (((((x)+499999)/2500000)&(MII_SPEED_MASK))>>1)<<(MII_SPEED_SHIFT) ) ++ ++/*the defines of MIB control */ ++#define FEC_MIB_DISABLE 0x80000000 ++ ++/*the defines of Receive Control*/ ++#define FEC_RCR_FCE 0x00000020 ++#define FEC_RCR_BC_REJ 0x00000010 ++#define FEC_RCR_PROM 0x00000008 ++#define FEC_RCR_MII_MODE 0x00000004 ++ ++/*the defines of Transmit Control*/ ++#define FEC_TCR_RFC_PAUSE 0x00000010 ++#define FEC_TCR_FDEN 0x00000004 ++ ++/*the defines of buffer description*/ ++#define FEC_BD_RX_NUM 256 ++#define FEC_BD_TX_NUM 2 ++ ++#ifdef CYGPKG_HAL_ARM_MX25 ++/*the defines for MIIGSK */ ++ ++/* RMII frequency control: 0=50MHz, 1=5MHz */ ++#define MIIGSK_CFGR_FRCONT (1 << 6) ++ ++/* loopback mode */ ++#define MIIGSK_CFGR_LBMODE (1 << 4) ++ ++/* echo mode */ ++#define MIIGSK_CFGR_EMODE (1 << 3) ++ ++/* MII gasket mode field */ ++#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) ++ ++/* MMI/7-Wire mode */ ++#define MIIGSK_CFGR_IF_MODE_MII (0 << 0) ++ ++/* RMII mode */ ++#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) ++ ++/* reflects MIIGSK Enable bit (RO) */ ++#define MIIGSK_ENR_READY (1 << 2) ++ ++/* enable MIGSK (set by default) */ ++#define MIIGSK_ENR_EN (1 << 1) ++#endif ++ ++typedef struct mxc_fec_reg_s ++{ ++ unsigned long res1; ++/*0x004*/ unsigned long eir; /* Interrupt Event Register */ ++/*0x008*/ unsigned long eimr; /* Interrupt Mask Register */ ++ unsigned long res2; ++/*0x010*/ unsigned long rdar; /* Receive Descriptor Active Register*/ ++/*0x014*/ unsigned long tdar; /* Transmit Descriptor Active Register*/ ++ unsigned long res3[3]; ++/*0x024*/ unsigned long ecr; /*Receive Descriptor Active Register*/ ++ unsigned long res4[6]; ++/*0x040*/ unsigned long mmfr; /*MII Management Frame Register */ ++/*0x044*/ unsigned long mscr; /*MII Speed Control Register */ ++ unsigned long res5[7]; ++/*0x064*/ unsigned long mibc; /*MII Control/Status Register */ ++ unsigned long res6[7]; ++/*0x084*/ unsigned long rcr; /*Receive Control Register */ ++ unsigned long res7[15]; ++/*0x0C4*/ unsigned long tcr; /*Transmit Control register */ ++ unsigned long res8[7]; ++/*0x0E4*/ unsigned long palr; /*Physical Address Low Register*/ ++/*0x0E8*/ unsigned long paur; /*Physical Address High+Type Register*/ ++/*0x0EC*/ unsigned long opd; /*Opcode+Pause Duration */ ++ unsigned long res9[10]; ++/*0x118*/ unsigned long iaur; /*Upper 32bits Individual Hash Table*/ ++/*0x11c*/ unsigned long ialr; /*lower 32bits Individual Hash Table*/ ++/*0x120*/ unsigned long gaur; /*Upper 32bits Group Hash Table*/ ++/*0x124*/ unsigned long galr; /*lower 32bits Group Hash Table*/ ++ unsigned long res10[7]; ++/*0x144*/ unsigned long tfwr; /*Trasmit FIFO Watermark */ ++ unsigned long res11; ++/*0x14c*/ unsigned long frbr; /*FIFO Receive Bound Register*/ ++/*0x150*/ unsigned long frsr; /*FIFO Receive FIFO Start Registers*/ ++ unsigned long res12[11]; ++/*0x180*/ unsigned long erdsr; /*Pointer to Receive Descriptor Ring*/ ++/*0x184*/ unsigned long etdsr; /*Pointer to Transmit Descriptor Ring*/ ++/*0x188*/ unsigned long emrbr; /*Maximum Receive Buffer size*/ ++#ifdef CYGPKG_HAL_ARM_MX25 ++ unsigned long res13[93]; ++/*0x300*/ unsigned short miigsk_cfgr; /* MIIGSK Configuration Register */ ++ unsigned short res14[3]; ++/*0x308*/ unsigned short miigsk_enr; /* MIIGSK Enable Register */ ++#endif ++} mxc_fec_reg_t; ++ ++#define BD_RX_ST_EMPTY 0x8000 ++#define BD_RX_ST_WRAP 0x2000 ++#define BD_RX_ST_LAST 0x0800 ++#define BD_RX_ST_ERRS 0x0037 ++ ++#define BD_TX_ST_RDY 0x8000 ++#define BD_TX_ST_WRAP 0x2000 ++#define BD_TX_ST_LAST 0x0800 ++#define BD_TX_ST_TC 0x0400 ++#define BD_TX_ST_ABC 0x0200 ++ ++typedef struct mxc_fec_bd_t ++{ ++ unsigned short int length; /*packet size*/ ++ unsigned short int status; /*control & statue of this buffer description*/ ++ unsigned char * data; /*frame buffer address*/ ++} mxc_fec_bd_t; ++ ++typedef struct mxc_fec_priv_s ++{ ++ mxc_fec_reg_t * hw_reg; /*the reister base address of FEC*/ ++ unsigned char phy_addr; /*the address of PHY which associated with FEC controller*/ ++ unsigned char tx_busy; /*0:free, 1:transmitting frame*/ ++ unsigned char res[2]; ++ unsigned long status; /*the status of FEC device:link-status etc.*/ ++ unsigned long tx_key; /*save the key delivered from send function*/ ++ mxc_fec_bd_t * rx_bd; /*the receive buffer description ring*/ ++ mxc_fec_bd_t * rx_cur; /*the next recveive buffer description*/ ++ mxc_fec_bd_t * tx_bd; /*the transmit buffer description rign*/ ++ mxc_fec_bd_t * tx_cur; /*the next transmit buffer description*/ ++ /*TODO: Add interrupt about fields*/ ++ /*TODO: Add timer about fields*/ ++} mxc_fec_priv_t; ++ ++#define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private) ++ ++/*The defines of the status field of mxc_fec_priv_t */ ++#define FEC_STATUS_LINK_ON 0x80000000 ++#define FEC_STATUS_FULL_DPLX 0x40000000 ++#define FEC_STATUS_AUTO_NEG 0x20000000 ++#define FEC_STATUS_100M 0x10000000 ++ ++/*The defines about PHY */ ++#ifndef FEC_PHY_ADDR ++#define PHY_PORT_ADDR 0x01 ++#else ++#define PHY_PORT_ADDR FEC_PHY_ADDR ++#endif ++ ++#define PHY_CTRL_REG 0x00 ++#define PHY_CTRL_RESET 0x8000 ++#define PHY_CTRL_AUTO_NEG 0x1000 ++#define PHY_CTRL_FULL_DPLX 0x0100 ++ ++#define PHY_STATUS_REG 0x01 ++#define PHY_STATUS_LINK_ST 0x0004 ++ ++#define PHY_IDENTIFY_1 0x02 ++#define PHY_IDENTIFY_2 0x03 ++#define PHY_ID1_SHIFT 16 ++#define PHY_ID1_MASK 0xFFFF ++#define PHY_ID2_SHIFT 0 ++#define PHY_ID2_MASK 0xFFFF ++#define PHY_MODE_NUM 0x03F0 ++#define PHY_REV_NUM 0x000F ++ ++#define PHY_DIAG_REG 0x12 ++#define PHY_DIAG_DPLX 0x0800 ++#define PHY_DIAG_RATE 0x0400 ++ ++#define PHY_MODE_REG 0x15 ++#define PHY_LED_SEL 0x200 ++ ++#define PHY_AUTO_NEG_REG 0x5 ++#define PHY_AUTO_10BASET 0x20 ++#define PHY_AUTO_10BASET_DPLX 0x40 ++#define PHY_AUTO_100BASET 0x80 ++#define PHY_AUTO_100BASET_DPLX 0x100 ++ ++#define PHY_AUTO_NEG_EXP_REG 0x6 ++#define PHY_AUTO_NEG_NEW_PAGE 0x2 ++#define PHY_AUTO_NEG_CAP 0x1 ++ ++#define PHY_INT_SRC_REG 29 ++#define PHY_INT_AUTO_NEG 0x40 ++#define FEC_COMMON_TICK 2 ++#define FEC_COMMON_TIMEOUT (1000*1000) ++#define FEC_MII_TICK 2 ++#define FEC_MII_TIMEOUT (1000*1000) ++ ++typedef int mxc_fec_read_mac_from_fuse(unsigned char*); ++ ++#endif // _CYGONCE_ETH_FEC_H_ +diff -urNad redboot-imx-200952~/packages/devs/eth/fec/current/src/if_fec.c redboot-imx-200952/packages/devs/eth/fec/current/src/if_fec.c +--- redboot-imx-200952~/packages/devs/eth/fec/current/src/if_fec.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/fec/current/src/if_fec.c 2010-01-26 17:33:12.282961510 +0000 +@@ -0,0 +1,789 @@ ++//========================================================================== ++// ++// dev/if_fec.c ++// ++// Device driver for FEC ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//####BSDCOPYRIGHTBEGIN#### ++// ++// ------------------------------------------- ++// ++// Portions of this software may have been derived from OpenBSD or other sources, ++// and are covered by the appropriate copyright disclaimers included herein. ++// ++// ------------------------------------------- ++// ++//####BSDCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Fred Fan ++// Contributors: ++// Date: 2006-08-23 ++// Purpose: ++// Description: Driver for FEC ethernet controller ++// ++// Note: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#ifdef CYGPKG_KERNEL ++#include ++#endif ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#undef __ECOS ++#define __ECOS ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++#include ++#endif ++ ++/*! ++ * Global variable which contains the name of FEC driver and device. ++ */ ++static char mxc_fec_name[] = "mxc_fec"; ++ ++/*! ++ * Global variable which defines the private structure of FEC device. ++ */ ++static mxc_fec_priv_t mxc_fec_private ; ++ ++/*! ++ *Global variable which defines the buffer descriptions for receiving frame ++ * comment:: it must aligned by 128-bits. ++ */ ++static mxc_fec_bd_t mxc_fec_rx_bd[FEC_BD_RX_NUM] __attribute__ ( ( aligned(32) ) ) ; ++ ++/*! ++ *Global variable which defines the buffer descriptions for receiving frame ++ * comment:: it must aligned by 128-bits. ++ */ ++static mxc_fec_bd_t mxc_fec_tx_bd[FEC_BD_TX_NUM] __attribute__ ( ( aligned(32) ) ) ; ++ ++/*! ++ * Global variable which contains the frame buffers , ++ */ ++static unsigned char mxc_fec_rx_buf[FEC_BD_RX_NUM][2048] __attribute__ ( ( aligned(32) ) ) ; ++ ++/*! ++ * Global variable which contains the frame buffers , ++ */ ++static unsigned char mxc_fec_tx_buf[FEC_BD_TX_NUM][2048] __attribute__ ( ( aligned(32) ) ) ; ++ ++mxc_fec_read_mac_from_fuse *get_mac_addr = NULL; ++ ++/*! ++ * This function get the value of PHY registers by MII interface ++ */ ++static int ++mxc_fec_mii_read(volatile mxc_fec_reg_t * hw_reg, unsigned char phy_addr, unsigned char reg_addr, unsigned short int * value) ++{ ++ unsigned long waiting = FEC_MII_TIMEOUT; ++ ++ if(hw_reg->eir & FEC_EVENT_MII ) { ++ hw_reg->eir = FEC_EVENT_MII ; ++ } ++ hw_reg->mmfr = FEC_MII_READ(phy_addr, reg_addr);/*Write CMD*/ ++ while(1) { ++ if(hw_reg->eir & FEC_EVENT_MII ) { ++ hw_reg->eir = FEC_EVENT_MII ; ++ break; ++ } ++ if ( (--waiting) == 0 ) return -1; ++ hal_delay_us(FEC_MII_TICK); ++ } ++ *value = FEC_MII_GET_DATA(hw_reg->mmfr); ++ return 0; ++} ++ ++/*! ++ * This function set the value of PHY registers by MII interface ++ */ ++static int ++mxc_fec_mii_write(volatile mxc_fec_reg_t * hw_reg, unsigned char phy_addr, unsigned char reg_addr, unsigned short int value) ++{ ++ unsigned long waiting = FEC_MII_TIMEOUT; ++ ++ if(hw_reg->eir & FEC_EVENT_MII ) { ++ hw_reg->eir = FEC_EVENT_MII ; ++ } ++ hw_reg->mmfr = FEC_MII_WRITE(phy_addr, reg_addr, value);/*Write CMD*/ ++ while(1) { ++ if(hw_reg->eir & FEC_EVENT_MII ) { ++ hw_reg->eir = FEC_EVENT_MII ; ++ break; ++ } ++ if ( (--waiting) == 0 ) return -1; ++ hal_delay_us(FEC_MII_TICK); ++ } ++ return 0; ++} ++ ++static void ++mxc_fec_set_mac_address(volatile mxc_fec_reg_t * dev, unsigned char * enaddr) ++{ ++ unsigned long value; ++ ++ value = enaddr[0]; ++ value = (value << 8) + enaddr[1]; ++ value = (value << 8) + enaddr[2]; ++ value = (value << 8) + enaddr[3]; ++ dev->palr = value; ++ ++ value = enaddr[4]; ++ value = (value<<8)+enaddr[5]; ++ dev->paur = (value<<16); ++} ++ ++/*! ++ * This function set the value of PHY registers by MII interface ++ */ ++static void ++mxc_fec_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) ++{ ++ mxc_fec_priv_t * priv = sc?sc->driver_private:NULL; ++ volatile mxc_fec_reg_t * chip = priv?priv->hw_reg:NULL; ++ ++ if ( !(priv && chip) || enaddr == NULL ) { ++ diag_printf("BUG[start]: MAC address or some fields in driver is NULL\n"); ++ return; ++ } ++ mxc_fec_set_mac_address(chip, enaddr); ++ ++ priv->tx_busy = 0; ++ chip->ecr |= FEC_ETHER_EN; ++ chip->rdar |= FEC_RX_TX_ACTIVE; ++} ++ ++/*! ++ * This function pauses the FEC controller. ++ */ ++static void ++mxc_fec_stop(struct eth_drv_sc *sc) ++{ ++ mxc_fec_priv_t * priv = sc?sc->driver_private:NULL; ++ volatile mxc_fec_reg_t * chip = priv?priv->hw_reg:NULL; ++ if ( !(priv && chip) ) { ++ diag_printf("BUG[stop]: some fields in driver is NULL\n"); ++ return; ++ } ++ chip->ecr &= ~FEC_ETHER_EN; ++} ++ ++static int ++mxc_fec_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_length) ++{ ++ /*TODO:: Add support */ ++ diag_printf("mxc_fec_control: key=0x%x, data=0x%x, data_len=0x%x\n", ++ key, data, data_length); ++ return 0; ++} ++ ++/*! ++ * This function checks the status of FEC control. ++ */ ++static int ++mxc_fec_can_send(struct eth_drv_sc *sc) ++{ ++ mxc_fec_priv_t * priv = sc?sc->driver_private:NULL; ++ volatile mxc_fec_reg_t * hw_reg = priv?priv->hw_reg:NULL; ++ unsigned long value; ++ ++ if ( !( priv && hw_reg) ) { ++ diag_printf("BUG[can_send]:the private pointer and register pointer in MXC_FEC is NULL\n"); ++ return 0; ++ } ++ if ( priv->tx_busy ) { ++ diag_printf("WARNING[can_send]: MXC_FEC is busy for transmittinig\n"); ++ return 0; ++ } ++ ++ if(!(hw_reg->ecr & FEC_ETHER_EN)) { ++ diag_printf("WARNING[can_send]: MXC_FEC is not enabled\n"); ++ return 0; ++ } ++ ++ if(hw_reg->tcr & FEC_TCR_RFC_PAUSE) { ++ diag_printf("WARNING[can_send]: MXC_FEC is paused\n"); ++ return 0; ++ } ++ ++ mxc_fec_mii_read(hw_reg, priv->phy_addr, 1, &value); ++ if ( value & PHY_STATUS_LINK_ST) { ++ priv->status |= FEC_STATUS_LINK_ON; ++ } else { ++ priv->status &= ~FEC_STATUS_LINK_ON; ++ } ++ return (priv->status&FEC_STATUS_LINK_ON); ++} ++ ++/*! ++ * This function transmits a frame. ++ */ ++static void ++mxc_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total, unsigned long key) ++{ ++ mxc_fec_priv_t * dev = sc?sc->driver_private:NULL; ++ volatile mxc_fec_reg_t * hw_reg = dev?dev->hw_reg:NULL; ++ mxc_fec_bd_t * p; ++ int i, off; ++ ++ if ( dev == NULL || hw_reg == NULL) { ++ diag_printf("BUG[TX]: some fields in driver are NULL\n"); ++ return; ++ } ++ if ( total > (FEC_FRAME_LEN-4)) total = FEC_FRAME_LEN-4; ++ if ( sg_list == NULL || total <= 14 ) { ++ if(sc->funs->eth_drv && sc->funs->eth_drv->tx_done) { ++ sc->funs->eth_drv->tx_done(sc, key, -1); ++ } ++ return; ++ } ++ ++ for(i=0, off=0, p = dev->tx_cur; istatus & BD_TX_ST_RDY) { ++ diag_printf("BUG[TX]:MXC_FEC's status=%x\n", p->status); ++ break; ++ } ++ if (sg_list[i].buf == NULL ) { ++ diag_printf("WARNING[TX]: sg_list->buf is NULL\n"); ++ break; ++ } ++ memcpy(hal_ioremap_nocache(p->data)+off, sg_list[i].buf, sg_list[i].len ); ++ off += sg_list[i].len; ++ } ++ if ( off < 14 ) { ++ diag_printf("WARNING[TX]: data len is %d\n", off); ++ return; ++ } ++ p->length = off; ++ p->status &= ~(BD_TX_ST_LAST|BD_TX_ST_RDY|BD_TX_ST_TC|BD_TX_ST_ABC); ++ p->status |= BD_TX_ST_LAST| BD_TX_ST_RDY | BD_TX_ST_TC; ++ if(p->status & BD_TX_ST_WRAP ) { ++ p = dev->tx_bd; ++ } else p++; ++ dev->tx_cur = p; ++ dev->tx_busy = 1; ++ dev->tx_key = key; ++ hw_reg->tdar = FEC_RX_TX_ACTIVE; ++} ++ ++/*! ++ * This function receives ready Frame in DB. ++ */ ++static void ++mxc_fec_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) ++{ ++ mxc_fec_priv_t * priv = sc?sc->driver_private:NULL; ++ mxc_fec_bd_t * p; ++ ++ if(sg_list == NULL || priv == NULL || sg_len <= 0) { ++ diag_printf("BUG[RX]: driver's private field or argument of this calling is NULL \n"); ++ return; ++ } ++ ++ /*TODO: I think if buf pointer is NULL, this function ++ * should not be called ++ */ ++ if(sg_list->buf == NULL) { ++ return; ++ } ++ p = priv->rx_cur; ++ ++ if(p->status & BD_RX_ST_EMPTY) { ++ diag_printf("BUG[RX]: status =%x\n", p->status); ++ return; ++ } ++ ++ if(!(p->status & BD_RX_ST_LAST)) { ++ diag_printf("BUG[RX]: status =%x\n", p->status); ++ return; ++ } ++ /*TODO::D_CACHE invalid this data buffer*/ ++ memcpy(sg_list->buf, hal_ioremap_nocache(p->data), p->length -4); ++} ++ ++static void ++mxc_fec_deliver(struct eth_drv_sc *sc) ++{ ++ /*TODO::When redboot support thread , ++ * the polling function will be called at here ++ */ ++ return; ++} ++ ++/* This funtion just called by polling funtion*/ ++static void ++mxc_fec_check_rx_bd(struct eth_drv_sc * sc) ++{ ++ mxc_fec_priv_t * priv = sc->driver_private; ++ mxc_fec_bd_t * p, * prev; ++ volatile mxc_fec_reg_t * hw_reg = priv->hw_reg; ++ int i; ++ ++ for(i = 0, p = priv->rx_cur; i< FEC_RX_FRAMES; i++){ ++ /*TODO::D-CACHE invalid this BD. ++ *In WRITE_BACK mode: this maybe destroy the next BD ++ * when the CACHE_LINE write back. ++ */ ++ if(p->status & BD_RX_ST_EMPTY) { ++ break; ++ } ++ if(!(p->status & BD_RX_ST_LAST)) { ++ //diag_printf("BUG[RX]: status=%x, length=%x\n", p->status, p->length); ++ goto skip_next; ++ } ++ ++ if((p->status & BD_RX_ST_ERRS)|| (p->length > FEC_FRAME_LEN)) { ++ //diag_printf("BUG1[RX]: status=%x, length=%x\n", p->status, p->length); ++ } else { ++ sc->funs->eth_drv->recv(sc, p->length -4); ++ } ++skip_next: ++ p->status = (p->status & BD_RX_ST_WRAP) | BD_RX_ST_EMPTY; ++ ++ if ( p->status & BD_RX_ST_WRAP) { ++ p = priv->rx_bd; ++ } else { ++ p++; ++ } ++ priv->rx_cur = p; ++ hw_reg->ecr |= FEC_ETHER_EN; ++ hw_reg->rdar |= FEC_RX_TX_ACTIVE; ++ } ++} ++ ++/*! ++ * This function checks the event of FEC controller ++ */ ++static void ++mxc_fec_poll(struct eth_drv_sc * sc) ++{ ++ mxc_fec_priv_t * priv = sc?sc->driver_private:NULL; ++ volatile mxc_fec_reg_t * hw_reg = priv?priv->hw_reg:NULL; ++ unsigned long value; ++ ++ if ( priv == NULL || hw_reg == NULL) { ++ diag_printf("BUG[POLL]: some fields in driver are NULL\n"); ++ return; ++ } ++ value = hw_reg->eir; ++ hw_reg->eir = value&(~FEC_EVENT_MII); ++ ++ if(value&FEC_EVENT_TX_ERR) { ++ diag_printf("WARNING[POLL]: There are error(%x) for transmit\n", value&FEC_EVENT_TX_ERR); ++ sc->funs->eth_drv->tx_done(sc, priv->tx_key, -1); ++ priv->tx_busy = 0; ++ } else { ++ if(value&FEC_EVENT_TX) { ++ sc->funs->eth_drv->tx_done(sc, priv->tx_key, 0); ++ priv->tx_busy = 0; ++ } ++ } ++ ++ if(value&FEC_EVENT_RX) { ++ mxc_fec_check_rx_bd(sc); ++ } ++ ++ if(value & FEC_EVENT_HBERR) { ++ diag_printf("WARNGING[POLL]: Hearbeat error!\n"); ++ } ++ ++ if(value & FEC_EVENT_EBERR) { ++ diag_printf("WARNING[POLL]: Ethernet Bus Error!\n"); ++ } ++} ++ ++ ++static int ++mxc_fec_int_vector(struct eth_drv_sc *sc) ++{ ++ /*TODO:: ++ * get FEC interrupt number ++ */ ++ return -1; ++} ++ ++/*! ++ * The function initializes the description buffer for receiving or transmitting ++ */ ++static void ++mxc_fec_bd_init(mxc_fec_priv_t * dev) ++{ ++ int i; ++ mxc_fec_bd_t * p; ++ ++ p = dev->rx_bd = hal_ioremap_nocache(hal_virt_to_phy((unsigned long)mxc_fec_rx_bd)); ++ for(i=0; istatus = BD_RX_ST_EMPTY; ++ p->length = 0; ++ p->data = hal_virt_to_phy((unsigned long)mxc_fec_rx_buf[i]); ++ } ++ ++ dev->rx_bd[i-1].status |= BD_RX_ST_WRAP; ++ dev->rx_cur = dev->rx_bd; ++ ++ p = dev->tx_bd = hal_ioremap_nocache(hal_virt_to_phy((unsigned long)mxc_fec_tx_bd)); ++ for(i=0; istatus = 0; ++ p->length = 0; ++ p->data = hal_virt_to_phy((unsigned long)mxc_fec_tx_buf[i]); ++ } ++ ++ dev->tx_bd[i-1].status |= BD_TX_ST_WRAP; ++ dev->tx_cur = dev->tx_bd; ++ ++ /*TODO:: add the sync function for items*/ ++} ++ ++/*! ++ *This function initializes FEC controller. ++ */ ++static void ++mxc_fec_chip_init(mxc_fec_priv_t * dev) ++{ ++ volatile mxc_fec_reg_t * chip = dev->hw_reg; ++ unsigned long ipg_clk; ++ ++ chip->ecr = FEC_RESET; ++ while(chip->ecr & FEC_RESET) { ++ hal_delay_us(FEC_COMMON_TICK); ++ } ++ ++ chip->eimr = 0x00000000; ++ chip->eir = 0xFFFFFFFF; ++ ++ chip->rcr = (chip->rcr&~(0x0000003F))|FEC_RCR_FCE|FEC_RCR_MII_MODE; ++ chip->tcr |= FEC_TCR_FDEN; ++ chip->mibc |= FEC_MIB_DISABLE; ++ ++ chip->iaur = 0; ++ chip->ialr = 0; ++ chip->gaur = 0; ++ chip->galr = 0; ++ ++#ifdef CYGPKG_HAL_ARM_MX25 ++ /* ++ * setup the MII gasket for RMII mode ++ */ ++ ++ /* disable the gasket */ ++ chip->miigsk_enr = 0; ++ ++ /* wait for the gasket to be disabled */ ++ while (chip->miigsk_enr & MIIGSK_ENR_READY) ++ hal_delay_us(FEC_COMMON_TICK); ++ ++ /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ ++ chip->miigsk_cfgr = MIIGSK_CFGR_IF_MODE_RMII; ++ ++ /* re-enable the gasket */ ++ chip->miigsk_enr = MIIGSK_ENR_EN; ++ ++#if 0 // Spec says READY should reflect EN but doesn't seem to here ++ /* wait for the gasket to be ready */ ++ while ((chip->miigsk_enr & MIIGSK_ENR_READY) == 0) ++ hal_delay_us(FEC_COMMON_TICK); ++#endif ++#endif ++ ++ /*TODO:: Use MII_SPEED(IPG_CLK) to get the value*/ ++ ipg_clk = get_main_clock(IPG_CLK); ++ ++ chip->mscr = (chip->mscr&(~0x7e)) | (((ipg_clk+499999)/2500000/2)<<1); ++ ++ /*Enable ETHER_EN*/ ++ chip->emrbr = 2048-16; ++ chip->erdsr = hal_virt_to_phy((unsigned long)dev->rx_bd); ++ chip->etdsr = hal_virt_to_phy((unsigned long)dev->tx_bd); ++} ++ ++/*! ++ * This function initialize PHY ++ */ ++static bool ++mxc_fec_phy_init(mxc_fec_priv_t * dev) ++{ ++ unsigned long value = 0; ++ unsigned long id = 0, timeout = 50; ++ ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_IDENTIFY_1, &value); ++ id = (value & PHY_ID1_MASK) << PHY_ID1_SHIFT; ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_IDENTIFY_2, &value); ++ id |= (value & PHY_ID2_MASK) << PHY_ID2_SHIFT; ++ ++ switch(id & 0xfffffff0) { ++ case 0x00540088: ++ break; ++ case 0x0007c0c0: ++ diag_printf("FEC LAN8700 PHY: ID=%lx\n", id); ++ break; ++ default: ++ diag_printf("[Warning] FEC not connect right PHY: ID=%lx\n", id); ++ } ++ ++ mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG|PHY_CTRL_FULL_DPLX); ++ ++#ifdef CYGPKG_HAL_ARM_MX27ADS ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, &value); ++ value &= ~(PHY_LED_SEL); ++ mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, value); ++#endif ++ ++#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK) || defined (CYGPKG_HAL_ARM_MX27_3STACK) ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_EXP_REG, &value); ++ /* Wait for packet to arrive */ ++ while (((value & PHY_AUTO_NEG_NEW_PAGE) == 0) && (timeout != 0)) { ++ hal_delay_us(100); ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_EXP_REG, &value); ++ timeout--; ++ } ++ /* Check if link is capable of auto-negotiation */ ++ if ((value & PHY_AUTO_NEG_CAP) == 1) { ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_INT_SRC_REG, &value); ++ timeout = 50; ++ /* Wait for auto-negotiation to complete */ ++ while (((value & PHY_INT_AUTO_NEG) == 0) && (timeout != 0)) { ++ hal_delay_us(100); ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_INT_SRC_REG, &value); ++ timeout--; ++ } ++ } ++#endif ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_STATUS_REG, &value); ++ if ( value & PHY_STATUS_LINK_ST) { ++ dev->status |= FEC_STATUS_LINK_ON; ++ } else { ++ dev->status &= ~FEC_STATUS_LINK_ON; ++ } ++ ++#ifdef CYGPKG_HAL_ARM_MX27ADS ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_DIAG_REG, &value); ++ if ( value & PHY_DIAG_DPLX) { ++ dev->status |= FEC_STATUS_FULL_DPLX; ++ } else { ++ dev->status &= ~FEC_STATUS_FULL_DPLX; ++ } ++ if ( value & PHY_DIAG_DPLX) { ++ dev->status |= FEC_STATUS_100M; ++ } else { ++ dev->status &= ~FEC_STATUS_100M; ++ } ++#endif ++ ++#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK) ++ mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_REG, &value); ++ if (value & PHY_AUTO_10BASET) { ++ dev->status &= ~FEC_STATUS_100M; ++ if (value & PHY_AUTO_10BASET_DPLX) { ++ dev->status |= FEC_STATUS_FULL_DPLX; ++ } else { ++ dev->status &= ~FEC_STATUS_FULL_DPLX; ++ } ++ } ++ ++ if (value & PHY_AUTO_100BASET) { ++ dev->status |= FEC_STATUS_100M; ++ if (value & PHY_AUTO_100BASET_DPLX) { ++ dev->status |= FEC_STATUS_FULL_DPLX; ++ } else { ++ dev->status &= ~FEC_STATUS_FULL_DPLX; ++ } ++ } ++#endif ++ ++ diag_printf("FEC: [ %s ] [ %s ] [ %s ]:\n", ++ (dev->status&FEC_STATUS_FULL_DPLX)?"FULL_DUPLEX":"HALF_DUPLEX", ++ (dev->status&FEC_STATUS_LINK_ON)?"connected":"disconnected", ++ (dev->status&FEC_STATUS_100M)?"100M bps":"10M bps"); ++ return true; ++} ++ ++/*! This function initializes the FEC driver. ++ * It is called by net_init in net module of RedBoot during RedBoot init ++ */ ++static bool ++mxc_fec_init(struct cyg_netdevtab_entry *tab) ++{ ++ struct eth_drv_sc * sc = tab?tab->device_instance:NULL; ++ mxc_fec_priv_t * private; ++ unsigned char eth_add_local[6] = {0x00, 0x00, 0x45, 0x67, 0x89, 0xab}; ++ cyg_bool set_esa; ++ int ok; ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++ /* Get MAC address */ ++ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "fec_esa", &set_esa, CONFIG_BOOL); ++ if (ok && set_esa) { ++ CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "fec_esa_data", eth_add_local, CONFIG_ESA); ++ } ++#endif ++ /* See if a MAC address is specified in the fuse registers */ ++ if (!(ok && set_esa)) { ++ if (get_mac_addr) ++ ok = get_mac_addr(eth_add_local); ++ } ++ ++ if(sc == NULL ){ ++ diag_printf("FEC:: no driver attached\n"); ++ return false; ++ } ++ ++ private = MXC_FEC_PRIVATE(sc); ++ if ( private == NULL ) { ++ private = &mxc_fec_private; ++ } ++ ++ private->hw_reg = SOC_FEC_BASE; ++ private->tx_busy = 0; ++ private->status = 0; ++ private->phy_addr = PHY_PORT_ADDR; ++ ++ mxc_fec_bd_init(private); ++ ++ mxc_fec_chip_init(private); ++ ++ mxc_fec_phy_init(private); ++ ++ /*TODO:: initialize System Resource : irq, timer */ ++ ++ sc->funs->eth_drv->init(sc, eth_add_local); ++ ++ return true; ++} ++ ++/*! ++ * Global variable which defines the FEC driver, ++ */ ++ETH_DRV_SC(mxc_fec_sc, ++ &mxc_fec_private, // Driver specific data ++ mxc_fec_name, ++ mxc_fec_start, ++ mxc_fec_stop, ++ mxc_fec_control, ++ mxc_fec_can_send, ++ mxc_fec_send, ++ mxc_fec_recv, ++ mxc_fec_deliver, // "pseudoDSR" called from fast net thread ++ mxc_fec_poll, // poll function, encapsulates ISR and DSR ++ mxc_fec_int_vector); ++ ++/*! ++ * Global variable which defines the FEC device ++ */ ++NETDEVTAB_ENTRY(mxc_fec_netdev, ++ mxc_fec_name, ++ mxc_fec_init, ++ &mxc_fec_sc); ++ ++#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG) ++extern unsigned int sys_ver; ++ ++void _board_provide_fec_esa(void) ++{ ++ cyg_bool set_esa; ++ cyg_uint8 addr[6]; ++ int ok; ++ ++ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "fec_esa", &set_esa, CONFIG_BOOL); ++ if (ok && set_esa) { ++ CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "fec_esa_data", addr, CONFIG_ESA); ++#ifdef CYGPKG_HAL_ARM_MX27 ++ if(sys_ver == SOC_SILICONID_Rev1_0) { ++ writel(addr[5], SOC_FEC_MAC_BASE + 0x0); ++ writel(addr[4], SOC_FEC_MAC_BASE + 0x4); ++ writel(addr[3], SOC_FEC_MAC_BASE + 0x8); ++ writel(addr[2], SOC_FEC_MAC_BASE + 0xC); ++ writel(addr[1], SOC_FEC_MAC_BASE + 0x10); ++ writel(addr[0], SOC_FEC_MAC_BASE + 0x14); ++ addr[5] = readl(SOC_FEC_MAC_BASE + 0x0); ++ addr[4] = readl(SOC_FEC_MAC_BASE + 0x4); ++ addr[3] = readl(SOC_FEC_MAC_BASE + 0x8); ++ addr[2] = readl(SOC_FEC_MAC_BASE + 0xC); ++ addr[1] = readl(SOC_FEC_MAC_BASE + 0x10); ++ addr[0] = readl(SOC_FEC_MAC_BASE + 0x14); ++ } else { ++ writel(addr[5], SOC_FEC_MAC_BASE2 + 0x0); ++ writel(addr[4], SOC_FEC_MAC_BASE2 + 0x4); ++ writel(addr[3], SOC_FEC_MAC_BASE2 + 0x8); ++ writel(addr[2], SOC_FEC_MAC_BASE2 + 0xC); ++ writel(addr[1], SOC_FEC_MAC_BASE2 + 0x10); ++ writel(addr[0], SOC_FEC_MAC_BASE2 + 0x14); ++ addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x0); ++ addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x4); ++ addr[3] = readl(SOC_FEC_MAC_BASE2 + 0x8); ++ addr[2] = readl(SOC_FEC_MAC_BASE2 + 0xC); ++ addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x10); ++ addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x14); ++ } ++#endif ++ } ++} ++ ++RedBoot_init(_board_provide_fec_esa, RedBoot_INIT_LAST); ++ ++RedBoot_config_option("Set FEC network hardware address [MAC]", ++ fec_esa, ++ ALWAYS_ENABLED, true, ++ CONFIG_BOOL, false ++ ); ++RedBoot_config_option("FEC network hardware address [MAC]", ++ fec_esa_data, ++ "fec_esa", true, ++ CONFIG_ESA, 0 ++ ); ++#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG +diff -urNad redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/cdl/smsc_lan92xx_eth_drivers.cdl redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/cdl/smsc_lan92xx_eth_drivers.cdl +--- redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/cdl/smsc_lan92xx_eth_drivers.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/cdl/smsc_lan92xx_eth_drivers.cdl 2010-01-26 17:33:12.632952624 +0000 +@@ -0,0 +1,88 @@ ++# ==================================================================== ++# ++# smsc_lan92xx_eth_drivers.cdl ++# ++# Ethernet drivers - support for LAN92XX compatible ethernet controllers ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 2007 Fred Fan ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Fred Fan ++# Contributors: Fred Fan ++# Date: 2007-9-27 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_ETH_SMSC_LAN92XX { ++ display "SMSC LAN92XX compatible ethernet driver" ++ description "Ethernet driver for SMSC LAN92XX compatible controllers." ++ ++ parent CYGPKG_IO_ETH_DRIVERS ++ active_if CYGPKG_IO_ETH_DRIVERS ++ ++ implements CYGHWR_NET_DRIVERS ++ implements CYGINT_IO_ETH_MULTICAST ++ ++ active_if CYGINT_DEVS_ETH_SMSC_LAN92XX_REQUIRED ++ ++ include_dir cyg/io ++ compile -library=libextras.a if_lan92xx.c ++ ++ define_proc { ++ puts $::cdl_header "#include "; ++ puts $::cdl_header "#include CYGDAT_DEVS_ETH_SMSC_LAN92XX_CFG"; ++ } ++ ++ cdl_component CYGPKG_DEVS_ETH_SMSC_LAN92XX_OPTIONS { ++ display "LAN92XX ethernet driver build options" ++ flavor none ++ no_define ++ ++ cdl_option CYGPKG_DEVS_ETH_SMSC_LAN91CXX_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "-D_KERNEL -D__ECOS" } ++ description " ++ This option modifies the set of compiler flags for ++ building the LAN91CXX ethernet driver package. ++ These flags are used in addition ++ to the set of global flags." ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/include/smsc_lan92xx.h redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/include/smsc_lan92xx.h +--- redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/include/smsc_lan92xx.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/include/smsc_lan92xx.h 2010-01-26 17:33:12.632952624 +0000 +@@ -0,0 +1,187 @@ ++#ifndef CYGONCE_DEVS_ETH_SMSC_LAN92XX_LAN92XX_H ++#define CYGONCE_DEVS_ETH_SMSC_LAN92XX_LAN92XX_H ++//========================================================================== ++// ++// lan92xx.h ++// ++// SMCS LAN9217 (LAN92XX compatible) Ethernet chip ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// Copyright (C) 2003 Nick Garnett ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//####BSDCOPYRIGHTBEGIN#### ++// ++// ------------------------------------------- ++// ++// Portions of this software may have been derived from OpenBSD or other sources, ++// and are covered by the appropriate copyright disclaimers included herein. ++// ++// ------------------------------------------- ++// ++//####BSDCOPYRIGHTEND#### ++ ++#include ++#include ++ ++#define __WANT_CONFIG ++#include CYGDAT_DEVS_ETH_SMSC_LAN92XX_CFG ++#undef __WANT_CONFIG ++ ++typedef struct ++{ ++ unsigned short id; ++ unsigned short ver; ++ char *id_name; ++}smsc_lan92xx_id_t; ++ ++// LAN92xx register offset ++#define LAN92XX_RX_DATA 0x00 ++#define LAN92XX_TX_DATA 0x20 ++#define LAN92XX_RX_STATUS1 0x40 ++#define LAN92XX_RX_STATUS2 0x44 ++#define LAN92XX_TX_STATUS1 0x48 ++#define LAN92XX_TX_STATUS2 0x4C ++#define LAN92XX_ID_REV 0x50 ++#define LAN92XX_IRQ_CFG 0x54 ++#define LAN92XX_INT_STS 0x58 ++#define LAN92XX_INT_EN 0x5C ++#define LAN92XX_RESERVED1 0x60 ++#define LAN92XX_BYTE_TEST 0x64 ++#define LAN92XX_FIFO_INT 0x68 ++#define LAN92XX_RX_CFG 0x6C ++#define LAN92XX_TX_CFG 0x70 ++#define LAN92XX_HW_CFG 0x74 ++#define LAN92XX_RX_DP_CTRL 0x78 ++#define LAN92XX_RX_FIFO_INF 0x7C ++#define LAN92XX_TX_FIFO_INF 0x80 ++#define LAN92XX_PMT_CTRL 0x84 ++#define LAN92XX_GPIO_CFG 0x88 ++#define LAN92XX_GPT_CFG 0x8C ++#define LAN92XX_GPT_CNT 0x90 ++#define LAN92XX_RESERVED2 0x94 ++#define LAN92XX_WORD_SWAP 0x98 ++#define LAN92XX_FREE_RUN 0x9C ++#define LAN92XX_RX_DROP 0xA0 ++#define LAN92XX_MAC_CMD 0xA4 ++#define LAN92XX_MAC_DATA 0xA8 ++#define LAN92XX_AFC_CFG 0xAC ++#define LAN92XX_E2P_CMD 0xB0 ++#define LAN92XX_E2P_DATA 0xB4 ++ ++// Access these MAC registers indirectly through MAC_CMD and MAC_DATA ++// registers. ++#define MAC_MAC_CR 1 ++#define MAC_ADDRH 2 ++#define MAC_ADDRL 3 ++#define MAC_HASHH 4 ++#define MAC_HASHL 5 ++#define MAC_MII_ACC 6 ++#define MAC_MII_DATA 7 ++#define MAC_FLOW 8 ++#define MAC_VLAN1 9 ++#define MAC_VLAN2 10 ++#define MAC_WUFF 11 ++#define MAC_WUCSR 12 ++ ++// These PHY registers are accessed indirectly through the MAC via the ++// MII interface using the MII_ACC and MII_DATA registers. PHY controls ++// the 802.3 physical layer such as 10/100Mbps, full/half mode. ++#define PHY_BCR 0 ++#define PHY_BSR 1 ++#define PHY_ID1 2 ++#define PHY_ID2 3 ++#define PHY_ANAR 4 ++#define PHY_ANLPAR 5 ++#define PHY_ANER 6 ++#define PHY_MCSR 17 ++#define PHY_SMR 18 ++#define PHY_SCSI 27 ++#define PHY_ISR 29 ++#define PHY_IMR 30 ++#define PHY_SCSR 31 ++ ++#define PHY_100TX_FD 0x4000 ++#define PHY_100TX_HD 0x2000 ++#define PHY_10T_RD 0x1000 ++#define PHY_10T_HD 0x0800 ++#define PHY_LINK_ON 0x0004 ++ ++#define IS_DUPLEX(x) ((x) & (PHY_100TX_FD | PHY_10T_RD)) ++ ++#define MAC_TIMEOUT (1000 * 100) ++#define MAC_TICKET 2 ++ ++#define E2P_CMD_SHIFT 28 ++#define E2P_CMD_BUSY 0x80000000 ++#define E2P_CMD_TIMEOUT 0x00000200 ++#define E2P_CMD_LOADED 0x00000100 ++ ++enum epc_cmd { ++ E2P_CMD_READ = 0 << E2P_CMD_SHIFT, ++ E2P_CMD_EWDS = 1 << E2P_CMD_SHIFT, ++ E2P_CMD_EWEN = 2 << E2P_CMD_SHIFT, ++ E2P_CMD_WRITE = 3 << E2P_CMD_SHIFT, ++ E2P_CMD_WRAL = 4 << E2P_CMD_SHIFT, ++ E2P_CMD_ERASE = 5 << E2P_CMD_SHIFT, ++ E2P_CMD_ERAL = 6 << E2P_CMD_SHIFT, ++ E2P_CMD_Reload = 7 << E2P_CMD_SHIFT, ++}; ++#define E2P_CMD(cmd, addr) (E2P_CMD_BUSY | (cmd) | (addr)) ++ ++#define E2P_CONTEXT_ID 0xA5 ++ ++typedef struct ++{ ++ unsigned int base; ++ int status; ++ int tx_busy; ++ int tx_key; ++ unsigned char mac_addr[6]; ++} smsc_lan92xx_t; ++ ++#ifndef LAN92XX_REG_BASE ++#define LAN92XX_REG_BASE PBC_BASE ++#endif ++ ++#ifndef LAN92XX_REG_READ ++#define LAN92XX_REG_READ(reg_offset) \ ++ (*(volatile unsigned int *)(LAN92XX_REG_BASE + reg_offset)) ++#endif ++ ++#ifndef LAN92XX_REG_WRITE ++#define LAN92XX_REG_WRITE(reg_offset, val) \ ++ (*(volatile unsigned int *)(LAN92XX_REG_BASE + reg_offset) = (val)) ++#endif ++ ++#endif // CYGONCE_DEVS_ETH_SMSC_MAC_MAC_H +diff -urNad redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/src/if_lan92xx.c redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/src/if_lan92xx.c +--- redboot-imx-200952~/packages/devs/eth/smsc/lan92xx/current/src/if_lan92xx.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/eth/smsc/lan92xx/current/src/if_lan92xx.c 2010-01-26 17:33:12.642962249 +0000 +@@ -0,0 +1,702 @@ ++//========================================================================== ++// ++// dev/if_lan92xx.c ++// ++// Ethernet device driver for SMSC LAN92XX compatible controllers ++// ++//========================================================================== ++//========================================================================== ++ ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Fred Fan ++// Contributors: ++// Date: 2007-10-16 ++// Purpose: ++// Description: Driver for SMSC LAN92xx ethernet controller ++// ++// Note: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CYGPKG_NET ++#include ++#include ++#include /* Needed for struct ifnet */ ++#endif ++ ++//#define LAN92XX_DEBUG ++#ifdef LAN92XX_DEBUG ++#define PDEBUG(fmt, args...) diag_printf(fmt, ##args) ++#else ++#define PDEBUG(fmt, args...) ++#endif /*LAN92XX_DEBUG*/ ++ ++#define __WANT_DEVS ++#include CYGDAT_DEVS_ETH_SMSC_LAN92XX_INL ++#undef __WANT_DEVS ++ ++#define LAN_92XX_DRV_VER "1.1" ++ ++#define MAX_RX_NUM (CYGNUM_IO_ETH_DRIVERS_NUM_PKT - 1) ++static smsc_lan92xx_id_t smsc_lan92xx_id_table[] = ++{ ++ {0x117A, 0x0000, "SMSC LAN9217"}, ++ {0x9220, 0x0000, "SMSC LAN9220"}, ++ {0}, ++}; ++ ++static int lan92xx_eeprom_present = 1; ++ ++static smsc_lan92xx_t lan92xx_dev; ++static inline void ++lan92xx_set_mac_addr(struct eth_drv_sc *sc, unsigned char *enaddr); ++static void lan92xx_soft_reset(struct eth_drv_sc *sc); ++static inline unsigned int ++lan92xx_mac_read(struct eth_drv_sc *sc, unsigned char reg); ++static inline void ++lan92xx_mac_write(struct eth_drv_sc *sc, unsigned char reg, unsigned long val); ++static inline unsigned int ++lan92xx_mii_read(struct eth_drv_sc *sc, unsigned char addr); ++static inline void ++lan92xx_mii_write(struct eth_drv_sc *sc, unsigned char addr, unsigned int val); ++ ++/*! ++ * This function set the value of PHY registers by MII interface ++ */ ++static void ++lan92xx_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) ++{ ++ unsigned int val; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ lan92xx_set_mac_addr(sc, enaddr); ++ ++ pdev->tx_busy = 0; ++ ++ val = lan92xx_mac_read(sc, MAC_MAC_CR)& (~0x800); ++ val |= 0x0010080C; ++ lan92xx_mac_write(sc, MAC_MAC_CR, val); ++ val = lan92xx_mac_read(sc, MAC_MAC_CR); ++} ++ ++/*! ++ * This function pauses the FEC controller. ++ */ ++static void ++lan92xx_stop(struct eth_drv_sc *sc) ++{ ++ unsigned int val; ++ ++ val = lan92xx_mac_read(sc, MAC_MAC_CR); ++ val &= ~(0x0000000C); ++ lan92xx_mac_write(sc, MAC_MAC_CR, val); ++} ++ ++static int ++lan92xx_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_length) ++{ ++ /*TODO:: Add support */ ++ PDEBUG("%s: key=0x%x, data=0x%x, data_len=0x%x\n", ++ __FUNCTION__, key, (unsigned long)data, (unsigned long)data_length); ++ return 0; ++} ++ ++/*! ++ * This function checks the status of FEC control. ++ */ ++static int ++lan92xx_can_send(struct eth_drv_sc *sc) ++{ ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ if (!(pdev->status & PHY_LINK_ON)) return 0; ++ if (pdev->tx_busy) return 0; ++ ++ return 1; ++} ++ ++/*! ++ * This function transmits a frame. ++ */ ++static void ++lan92xx_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total, unsigned long key) ++{ ++ int i, j, len, freespace; ++ unsigned int tx_cmd1, tx_cmd2, data, *pdata; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ freespace = LAN92XX_REG_READ(LAN92XX_TX_FIFO_INF) & 0xFFFF; ++ ++ if (freespace < total + 16 ) { ++ sc->funs->eth_drv->tx_done(sc, key, -1); ++ return; ++ } ++ for (i = 0; i < sg_len; i++) { ++ len = (sg_list[i].len + 3) >> 2; ++ if (i == (sg_len - 1)) ++ tx_cmd1 = 0x1000; ++ else if (i) ++ tx_cmd1 = 0x0000; ++ else ++ tx_cmd1 = 0x2000; ++ ++ tx_cmd1 |= sg_list[i].len; ++ tx_cmd2 = (total << 16) + total; ++ LAN92XX_REG_WRITE(LAN92XX_TX_DATA, tx_cmd1); ++ ++ LAN92XX_REG_WRITE(LAN92XX_TX_DATA, tx_cmd2); ++ pdata = (unsigned int *)sg_list[i].buf; ++ ++ for (j=0; jtx_busy = 1; ++ pdev->tx_key = key; ++} ++ ++static void ++lan92xx_drop_packet(struct eth_drv_sc *sc, int count) ++{ ++ unsigned int data; ++ if (count >= 4) { ++ LAN92XX_REG_WRITE(LAN92XX_RX_DP_CTRL, 0x80000000); ++ while (LAN92XX_REG_READ(LAN92XX_RX_DP_CTRL) & 0x80000000) { ++ } ++ } else { ++ while (count--) ++ data = LAN92XX_REG_READ(LAN92XX_RX_DATA); ++ } ++} ++ ++/*! ++ * This function receives ready Frame in DB. ++ */ ++static void ++lan92xx_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) ++{ ++ unsigned int i, rlen; ++ unsigned int *pdata = (unsigned int *)(sg_list->buf); ++ ++ rlen = (sg_list->len + 3) >> 2; ++ if ((void *)(sg_list->buf) == NULL) { ++ goto Drop; ++ } ++ ++ for (i = 0; i < rlen; i++) { ++ *(pdata++) = LAN92XX_REG_READ(LAN92XX_RX_DATA); ++ } ++ return; ++Drop: ++ lan92xx_drop_packet(sc, rlen); ++} ++ ++static void ++lan92xx_deliver(struct eth_drv_sc *sc) ++{ ++ /*TODO::When redboot support thread , ++ * the polling function will be called at here ++ */ ++ return; ++} ++ ++static void ++lan92xx_link_status(struct eth_drv_sc *sc) ++{ ++ unsigned int val; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ val = lan92xx_mii_read(sc, PHY_ISR); ++ if (val&0x50) { ++ val = lan92xx_mii_read(sc, PHY_BSR); ++ if (val != pdev->status) { ++ pdev->status = val; ++ val = lan92xx_mac_read(sc, MAC_MAC_CR) & (~0x802F0800); ++ if ( IS_DUPLEX(pdev->status)) { ++ val |= 0x00100000; ++ } ++ lan92xx_mac_write(sc, MAC_MAC_CR, val); ++ } ++ } ++} ++/*! ++ * This function checks the event of FEC controller ++ */ ++static void ++lan92xx_poll(struct eth_drv_sc *sc) ++{ ++ unsigned int val, reg; ++ int rx_num = 0; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ reg = LAN92XX_REG_READ(LAN92XX_INT_STS); ++ LAN92XX_REG_WRITE(LAN92XX_INT_STS, reg); ++ ++ //diag_printf("INT_STS: %x\n", reg); ++ if (reg & 0x40000) { ++ lan92xx_link_status(sc); ++ } ++ ++ if (reg & 0xE000) { ++ diag_printf("%s:: TX or RX error [0x%x]\n", __FUNCTION__, reg); ++ lan92xx_soft_reset(sc); ++ return; ++ } ++ ++ while (1) { ++ reg = LAN92XX_REG_READ(LAN92XX_RX_FIFO_INF); ++ if (!(reg & 0xFF0000)) ++ break; ++ reg = LAN92XX_REG_READ(LAN92XX_RX_STATUS1); ++ ++ if (reg & 0x4000909A) { ++ val = (reg >> 16) & 0x3FFF; ++ val = (val + 3) >> 2; ++ lan92xx_drop_packet(sc, val); ++ } else { ++ val = (reg >> 16) & 0x3FFF; ++ sc->funs->eth_drv->recv(sc, val); ++ rx_num++; ++ } ++ ++ if ( rx_num >= MAX_RX_NUM) break; ++ } ++ ++ while (1) { ++ reg = LAN92XX_REG_READ(LAN92XX_TX_FIFO_INF); ++ if (!(reg & 0xFF0000)) break; ++ ++ if (!LAN92XX_REG_READ(LAN92XX_TX_STATUS2)) { ++ diag_printf("***FIFO %x, wrong status =%x: int_sts=%x\n", ++ reg, LAN92XX_REG_READ(LAN92XX_TX_STATUS2), ++ LAN92XX_REG_READ(LAN92XX_INT_STS)); ++ continue; ++ } ++ reg = LAN92XX_REG_READ(LAN92XX_TX_STATUS1); ++ if (reg & 0x8000) { ++ sc->funs->eth_drv->tx_done(sc, pdev->tx_key, -1); ++ } else { ++ sc->funs->eth_drv->tx_done(sc, pdev->tx_key, 0); ++ } ++ pdev->tx_busy = 0; ++ } ++} ++ ++static int ++lan92xx_int_vector(struct eth_drv_sc *sc) ++{ ++ PDEBUG("%s::\n", __FUNCTION__); ++ ++ /*TODO:: ++ * get FEC interrupt number ++ */ ++ return -1; ++} ++ ++static smsc_lan92xx_id_t *lan92xx_probe(unsigned long id) ++{ ++ smsc_lan92xx_id_t *p = smsc_lan92xx_id_table; ++ while (p->id) { ++ if (id == p->id) ++ return p; ++ p++; ++ } ++ return NULL; ++} ++ ++static inline unsigned int ++lan92xx_mac_read(struct eth_drv_sc *sc, unsigned char reg) ++{ ++ unsigned int cmd; ++ ++ if (LAN92XX_REG_READ(LAN92XX_MAC_CMD) & 0x80000000) { ++ diag_printf("Error: %d. MAC is busy\n", __LINE__); ++ return 0xFFFFFFFF; ++ } ++ ++ cmd = 0xC0000000 | (reg & 0xFF); ++ LAN92XX_REG_WRITE(LAN92XX_MAC_CMD, cmd); ++ ++ /* Workaround for hardware read-after-write */ ++ LAN92XX_REG_READ(LAN92XX_BYTE_TEST); ++ ++ while (LAN92XX_REG_READ(LAN92XX_MAC_CMD) & 0x80000000); ++ ++ return LAN92XX_REG_READ(LAN92XX_MAC_DATA); ++} ++ ++static inline void ++lan92xx_mac_write(struct eth_drv_sc *sc, unsigned char reg, unsigned long val) ++{ ++ unsigned int cmd; ++ ++ if (LAN92XX_REG_READ(LAN92XX_MAC_CMD) & 0x80000000) { ++ diag_printf("Error: %d. MAC is busy\n", __LINE__); ++ return; ++ } ++ ++ LAN92XX_REG_WRITE(LAN92XX_MAC_DATA, val); ++ cmd = 0x80000000 | (reg & 0xFF); ++ LAN92XX_REG_WRITE(LAN92XX_MAC_CMD, cmd); ++ ++ /* Workaround for hardware read-after-write */ ++ LAN92XX_REG_READ(LAN92XX_BYTE_TEST); ++ ++ while (LAN92XX_REG_READ(LAN92XX_MAC_CMD) & 0x80000000); ++} ++ ++static inline void ++lan92xx_set_mac_addr(struct eth_drv_sc *sc, unsigned char *enaddr) ++{ ++ unsigned int val; ++ val = enaddr[3]; ++ val = (val << 8) | enaddr[2]; ++ val = (val << 8) | enaddr[1]; ++ val = (val << 8) | enaddr[0]; ++ lan92xx_mac_write(sc, MAC_ADDRL, val); ++ ++ val = lan92xx_mac_read(sc, MAC_ADDRH) >> 16; ++ val = (val << 8) | enaddr[5]; ++ val = (val << 8) | enaddr[4]; ++ lan92xx_mac_write(sc, MAC_ADDRH, val); ++} ++ ++static inline unsigned int ++lan92xx_mii_read(struct eth_drv_sc *sc, unsigned char addr) ++{ ++ unsigned int cmd; ++ ++ cmd = (0x1 << 11 ) | (addr << 6) | 1; ++ lan92xx_mac_write(sc, MAC_MII_ACC, cmd); ++ while (lan92xx_mac_read(sc, MAC_MII_ACC) & 1); ++ ++ return lan92xx_mac_read(sc, MAC_MII_DATA)&0xFFFF; ++} ++ ++static inline void ++lan92xx_mii_write(struct eth_drv_sc *sc, unsigned char addr, unsigned int val) ++{ ++ unsigned int cmd; ++ ++ cmd = (0x1 << 11 ) | (addr << 6) | 3; ++ lan92xx_mac_write(sc, MAC_MII_DATA, val); ++ lan92xx_mac_read(sc, MAC_MII_DATA); ++ lan92xx_mac_write(sc, MAC_MII_ACC, cmd); ++ ++ while (lan92xx_mac_read(sc, MAC_MII_ACC) & 1); ++} ++ ++static int lan92xx_phy_init(struct eth_drv_sc *sc) ++{ ++ int val; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ lan92xx_mii_write(sc, PHY_BCR, 0x8000); ++ ++ while (lan92xx_mii_read(sc, PHY_BCR) & 0x8000); ++ ++ for (val = 0; val < 2500; val++) ++ hal_delay_us(4); ++ ++ val = lan92xx_mii_read(sc, PHY_ANAR); ++ val |= 0x01E1; ++ lan92xx_mii_write(sc, PHY_ANAR, val); ++ lan92xx_mii_write(sc, PHY_SMR, 0x00E1); ++ lan92xx_mii_write(sc, PHY_SCSI, 0x400B); ++ lan92xx_mii_write(sc, PHY_IMR, 0x00F0); ++ lan92xx_mii_write(sc, PHY_BCR, 0x1200); ++ ++ while ((lan92xx_mii_read(sc, PHY_BCR) & 0x200)); ++ ++ pdev->status = lan92xx_mii_read(sc, PHY_BSR); ++ ++ return 0; ++} ++ ++static int lan92xx_mac_init(struct eth_drv_sc *sc) ++{ ++ static int mac_init = 0; ++ unsigned int val; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ val = lan92xx_mac_read(sc, MAC_MAC_CR) & (~0x802F0800); ++ if (IS_DUPLEX(pdev->status)) { ++ val |= 0x00100000; ++ } ++ lan92xx_mac_write(sc, MAC_MAC_CR, val); ++ ++ lan92xx_mac_write(sc, MAC_HASHH, 0); ++ lan92xx_mac_write(sc, MAC_HASHL, 0); ++ ++ if (mac_init) ++ return 0; ++ ++ mac_init = 1; ++ ++#if CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT ++ if (!_board_provide_eth0_esa(pdev->mac_addr)) ++#endif ++ { ++ // make sure EPC not busy ++ while ((val = LAN92XX_REG_READ(LAN92XX_E2P_CMD)) & E2P_CMD_BUSY); ++ ++ if (val & E2P_CMD_TIMEOUT) { ++ lan92xx_eeprom_present = 0; ++ diag_printf("LAN9217: NO EEPROM\n"); ++ return -1; ++ } ++ ++ if (!(LAN92XX_REG_READ(LAN92XX_E2P_CMD) & E2P_CMD_LOADED)) { ++ diag_printf("LAN9217:EEPROM is empty\n"); ++ } ++ val = lan92xx_mac_read(sc, MAC_ADDRH); ++ pdev->mac_addr[5] = (val >> 8) & 0xFF; ++ pdev->mac_addr[4] = val&0xFF; ++ val = lan92xx_mac_read(sc, MAC_ADDRL); ++ pdev->mac_addr[3] = (val >> 24) & 0xFF; ++ pdev->mac_addr[2] = (val >> 16) & 0xFF; ++ pdev->mac_addr[1] = (val >> 8) & 0xFF; ++ pdev->mac_addr[0] = val & 0xFF; ++ } ++ return 0; ++} ++ ++/* ++ * This function reset LAN9219 . ++ */ ++static void ++lan92xx_soft_reset(struct eth_drv_sc *sc) ++{ ++ unsigned int timeout = MAC_TIMEOUT; ++ ++ LAN92XX_REG_WRITE(LAN92XX_HW_CFG, 1); ++ while ((LAN92XX_REG_READ(LAN92XX_HW_CFG) & 1) && (--timeout)) { ++ hal_delay_us(MAC_TICKET); ++ } ++ ++ if (!timeout) { ++ diag_printf("LAN92XX: Reset fail \n"); ++ return ; ++ } ++ ++ LAN92XX_REG_WRITE(LAN92XX_INT_EN, 0); ++ LAN92XX_REG_WRITE(LAN92XX_HW_CFG, 0x150000); ++ LAN92XX_REG_WRITE(LAN92XX_AFC_CFG, 0x6E3740); ++ LAN92XX_REG_WRITE(LAN92XX_TX_CFG, 0x2); ++ ++ timeout = MAC_TIMEOUT; ++ ++ while ((LAN92XX_REG_READ(LAN92XX_E2P_CMD) & 0x80000000) && (--timeout)) { ++ hal_delay_us(MAC_TICKET); ++ } ++ ++ LAN92XX_REG_WRITE(LAN92XX_GPIO_CFG, 0x70070000); ++ LAN92XX_REG_WRITE(LAN92XX_INT_STS, 0xFFFFFFFF); ++ lan92xx_mac_init(sc); ++} ++ ++/*! ++ * This function initializes the LAN92xx driver. ++ * It is called by net_init in net module of RedBoot during RedBoot init ++ */ ++static bool ++lan92xx_init(struct cyg_netdevtab_entry *tab) ++{ ++ unsigned int reg, timeout; ++ smsc_lan92xx_id_t *id; ++ struct eth_drv_sc *sc = tab ? tab->device_instance : NULL; ++ smsc_lan92xx_t *pdev = (smsc_lan92xx_t *)(sc->driver_private); ++ ++ diag_printf("\nLAN92xx Driver version %s\n", LAN_92XX_DRV_VER); ++ if (!pdev) { ++ diag_printf("LAN92xx:: Driver don't attach with device\n"); ++ return false; ++ } ++ reg = LAN92XX_REG_READ(LAN92XX_ID_REV); ++ id = lan92xx_probe(reg >> 16); ++ if (id) { ++ diag_printf("%s: ID = 0x%x REV = 0x%x\n", id->id_name, id->id, id->ver); ++ } else { ++ diag_printf("LAN92XX: unknow chip ID = %x\n", reg); ++ return false; ++ } ++ ++ timeout = MAC_TIMEOUT; ++ while ((!(LAN92XX_REG_READ(LAN92XX_PMT_CTRL) & 1)) && (--timeout)) { ++ hal_delay_us(MAC_TICKET); ++ } ++ if (timeout == 0) { ++ diag_printf("LAN92XX: is not ready to access\n"); ++ return false; ++ } ++ ++ lan92xx_phy_init(sc); ++ ++ lan92xx_soft_reset(sc); ++ (sc->funs->eth_drv->init)(sc, pdev->mac_addr); ++ return true; ++} ++ ++/*! ++ * Global variable which defines the LAN92xx driver, ++ */ ++ETH_DRV_SC(lan92xx_sc, ++ &lan92xx_dev, // Driver specific data ++ CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME, ++ lan92xx_start, ++ lan92xx_stop, ++ lan92xx_control, ++ lan92xx_can_send, ++ lan92xx_send, ++ lan92xx_recv, ++ lan92xx_deliver, // "pseudoDSR" called from fast net thread ++ lan92xx_poll, // poll function, encapsulates ISR and DSR ++ lan92xx_int_vector); ++ ++/*! ++ * Global variable which defines the FEC device ++ */ ++NETDEVTAB_ENTRY(lan92xx_netdev, ++ "lan92xx_" CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME, ++ lan92xx_init, ++ &lan92xx_sc); ++ ++// Low level function to issue a command to the eeprom controller. ++// return 0 on success and -1 on failure ++static inline int ++_lan92xx_e2p_do_cmd(unsigned int cmd) ++{ ++ unsigned int v; ++ LAN92XX_REG_WRITE(LAN92XX_E2P_CMD, cmd); ++ while ((v = LAN92XX_REG_READ(LAN92XX_E2P_CMD)) & E2P_CMD_BUSY); ++ if (v & E2P_CMD_TIMEOUT) { ++ diag_printf("%s:: EEPROM timeout\n", __FUNCTION__); ++ // clear the timeout status bit ++ LAN92XX_REG_WRITE(LAN92XX_E2P_CMD, E2P_CMD_TIMEOUT); ++ while ((v = LAN92XX_REG_READ(LAN92XX_E2P_CMD)) & E2P_CMD_BUSY); ++ return -1; ++ } ++ return 0; ++} ++ ++// for all the 7 EEPROM operations ++// return 0 on success and -1 on failure ++static int ++lan92xx_e2p_op(enum epc_cmd cmd, unsigned char addr, unsigned char *data) ++{ ++ switch (cmd) { ++ case E2P_CMD_READ: ++ if (_lan92xx_e2p_do_cmd(E2P_CMD(cmd, addr)) != 0) ++ return -1; ++ *data = (unsigned char)LAN92XX_REG_READ(LAN92XX_E2P_DATA); ++ return 0; ++ break; ++ case E2P_CMD_WRAL: ++ case E2P_CMD_WRITE: ++ LAN92XX_REG_WRITE(LAN92XX_E2P_DATA, *data); ++ break; ++ default: ++ break; ++ } ++ ++ if (_lan92xx_e2p_do_cmd(E2P_CMD(cmd, addr)) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++static void setMac(int argc, char *argv[]) ++{ ++ int i; ++ unsigned char data[7]; ++ unsigned long temp; ++ ++ if (!lan92xx_eeprom_present) { ++ diag_printf("NO EEPROM present\n\n"); ++ return; ++ } ++ ++ if (argc == 1) { ++ for (i = 0; i < 7 ; i++) { ++ if (lan92xx_e2p_op(E2P_CMD_READ, i, &data[i]) != 0) { ++ diag_printf("read MAC %d address fail\n\n", i); ++ return; ++ } ++ } ++ ++ if (data[0] != E2P_CONTEXT_ID) { ++ diag_printf("Warning: Unprogrammed MAC address: 0x%x\n", data[0]); ++ return; ++ } ++ ++ diag_printf("MAC address: "); ++ diag_printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n", ++ data[1], data[2], data[3], ++ data[4], data[5], data[6]); ++ return; ++ } ++ ++ if (argc != 2) { ++ diag_printf("Error: Wrong argument\n"); ++ return; ++ } ++ ++ data[0] = E2P_CONTEXT_ID; ++ for (i = 1; i < 7; i++) { ++ if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) { ++ diag_printf("Error: failed to parse command: %d\n", __LINE__); ++ return; ++ } ++ if (temp > 0xFF) { ++ diag_printf("Error: invalid valie: 0x%x\n", (unsigned int)temp); ++ return; ++ } ++ data[i] = temp; ++ } ++ ++ // enable erase/write ++ if (lan92xx_e2p_op(E2P_CMD_EWEN, 0, data) != 0) { ++ diag_printf("%s:: Enable write/erase fail\n", __FUNCTION__); ++ return; ++ } ++ for (i = 0; i < 7; i++) { ++ if (lan92xx_e2p_op(E2P_CMD_ERASE, i, &data[i]) != 0 || ++ lan92xx_e2p_op(E2P_CMD_WRITE, i, &data[i]) != 0) { ++ diag_printf("Error: failed to program eeprom at %d\n", i); ++ return; ++ } ++ } ++ ++ // disable erase/write ++ if (lan92xx_e2p_op(E2P_CMD_EWDS, 0, data) != 0) { ++ diag_printf("%s:: Enable write/erase fail\n", __FUNCTION__); ++ } ++} ++ ++RedBoot_cmd("setmac", ++ "Set Ethernet MAC address in EEPROM", ++ "[0x##:0x##:0x##:0x##:0x##:0x##]", ++ setMac ++ ); +diff -urNad redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl +--- redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 2006-08-29 19:19:06.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 2010-01-26 17:33:12.672959376 +0000 +@@ -327,74 +327,84 @@ + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL032J { +- display "Spansion S29PL032J flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128N { ++ display "AMD/SPANSION S29GL128N flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " +- When this option is enabled, the AMD flash driver will be +- able to recognize and handle the S29PL032J ++ When this option is enabled, the AMD/SPANSION flash driver will be ++ able to recognize and handle the S29GL128N + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL064J { +- display "Spansion S29PL064J flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL256N { ++ display "AMD/SPANSION S29GL256N flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " +- When this option is enabled, the AMD flash driver will be +- able to recognize and handle the S29PL064J ++ When this option is enabled, the AMD/SPANSION flash driver will be ++ able to recognize and handle the S29GL256N ++ part in the family." ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N { ++ display "AMD/SPANSION S29GL512N flash memory support" ++ default_value 0 ++ implements CYGINT_DEVS_FLASH_AMD_VARIANTS ++ description " ++ When this option is enabled, the AMD/SPANSION flash driver will be ++ able to recognize and handle the S29GL512N + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL127J { +- display "Spansion S29PL127J flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL032J { ++ display "Spansion S29PL032J flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " + When this option is enabled, the AMD flash driver will be +- able to recognize and handle the S29PL0127J ++ able to recognize and handle the S29PL032J + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128N { +- display "AMD/SPANSION S29GL128N flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL064J { ++ display "Spansion S29PL064J flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " +- When this option is enabled, the AMD/SPANSION flash driver will be +- able to recognize and handle the S29GL128N ++ When this option is enabled, the AMD flash driver will be ++ able to recognize and handle the S29PL064J + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL256N { +- display "AMD/SPANSION S29GL256N flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128M { ++ display "AMD/SPANSION S29GL128M flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " + When this option is enabled, the AMD/SPANSION flash driver will be +- able to recognize and handle the S29GL256N ++ able to recognize and handle the S29GL128M + part in the family." +- } ++ } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N { +- display "AMD/SPANSION S29GL512N flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_AMD_S29PL127J { ++ display "Spansion S29PL127J flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " +- When this option is enabled, the AMD/SPANSION flash driver will be +- able to recognize and handle the S29GL512N ++ When this option is enabled, the AMD flash driver will be ++ able to recognize and handle the S29PL0127J + part in the family." + } + +- cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL128M { +- display "AMD/SPANSION S29GL128M flash memory support" ++ cdl_option CYGHWR_DEVS_FLASH_S29WS256N { ++ display "SPANSION flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " +- When this option is enabled, the AMD/SPANSION flash driver will be +- able to recognize and handle the S29GL128M ++ When this option is enabled, the AMD flash driver will be ++ able to recognize and handle the S29WS256N + part in the family." + } + +-} ++} +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl +--- redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl 2006-08-11 15:28:21.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl 2010-01-26 17:33:12.672959376 +0000 +@@ -171,7 +171,7 @@ + cyg_bool bootblock; + cyg_uint32 bootblocks[64]; // 0 is bootblock offset, 1-11 sub-sector sizes (or 0) + cyg_bool banked; +- cyg_uint32 banks[8]; // bank offsets, highest to lowest (lowest should be 0) ++ cyg_uint32 banks[16]; // bank offsets, highest to lowest (lowest should be 0) + // (only one entry for now, increase to support devices + // with more banks). + cyg_uint32 bufsiz; // write buffer size in units of flash_data_t +@@ -186,6 +186,7 @@ + //---------------------------------------------------------------------------- + // Functions that put the flash device into non-read mode must reside + // in RAM. ++#ifndef MXCFLASH_SELECT_MULTI + void flash_query(void* data) __attribute__ ((section (".2ram.flash_query"))); + int flash_erase_block(void* block, unsigned int size) + __attribute__ ((section (".2ram.flash_erase_block"))); +@@ -199,6 +200,17 @@ + static flash_data_t * find_sector(volatile flash_data_t * addr, unsigned long *remain_size) + __attribute__ ((section (".2ram.find_sector"))); + ++#else ++void norflash_query(void* data); ++int norflash_erase_block(void* block, unsigned int size); ++int norflash_program_buf(void* addr, void* data, int len); ++ ++//---------------------------------------------------------------------------- ++// Auxiliary functions ++static volatile flash_data_t * find_bank(volatile flash_data_t * base, void * addr, CYG_ADDRWORD * bo); ++static flash_data_t * find_sector(volatile flash_data_t * addr, unsigned long *remain_size); ++#endif //MXCFLASH_SELECT_MULTI ++ + //---------------------------------------------------------------------------- + // Flash Query + // +@@ -207,7 +219,11 @@ + // will be of the same type. + + void ++#ifndef MXCFLASH_SELECT_MULTI + flash_query(void* data) ++#else ++norflash_query(void* data) ++#endif + { + volatile flash_data_t *ROM; + volatile flash_data_t *f_s1, *f_s2; +@@ -247,7 +263,11 @@ + //---------------------------------------------------------------------------- + // Initialize driver details + int ++#ifndef MXCFLASH_SELECT_MULTI + flash_hwr_init(void) ++#else ++norflash_hwr_init(void) ++#endif + { + flash_data_t id[4]; + int i; +@@ -283,7 +303,11 @@ + //---------------------------------------------------------------------------- + // Map a hardware status to a package error + int ++#ifndef MXCFLASH_SELECT_MULTI + flash_hwr_map_error(int e) ++#else ++norflash_hwr_map_error(int e) ++#endif + { + return e; + } +@@ -292,7 +316,11 @@ + //---------------------------------------------------------------------------- + // See if a range of FLASH addresses overlaps currently running code + bool ++#ifndef MXCFLASH_SELECT_MULTI + flash_code_overlaps(void *start, void *end) ++#else ++norflash_code_overlaps(void *start, void *end) ++#endif + { + extern unsigned char _stext[], _etext[]; + +@@ -306,7 +334,11 @@ + // Erase Block + + int ++#ifndef MXCFLASH_SELECT_MULTI + flash_erase_block(void* block, unsigned int size) ++#else ++norflash_erase_block(void* block, unsigned int size) ++#endif + { + volatile flash_data_t* ROM, *BANK; + volatile flash_data_t* b_p = (flash_data_t*) block; +@@ -346,6 +378,8 @@ + } + } + ++#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT ++ + while (size > 0) { + #ifndef CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT + // First check whether the block is protected +@@ -429,7 +463,11 @@ + //---------------------------------------------------------------------------- + // Program Buffer + int ++#ifndef MXCFLASH_SELECT_MULTI + flash_program_buf(void* addr, void* data, int len) ++#else ++norflash_program_buf(void* addr, void* data, int len) ++#endif + { + volatile flash_data_t* ROM; + volatile flash_data_t* BANK; +@@ -632,4 +670,4 @@ + return (flash_data_t *) res; + } + +-#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_INL ++#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_INL +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl +--- redboot-imx-200952~/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 2006-11-28 13:23:59.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 2010-01-26 17:33:12.682963001 +0000 +@@ -1176,6 +1176,7 @@ + bufsiz : 1 + }, + #endif ++ + #ifdef CYGHWR_DEVS_FLASH_AMD_AM29LV256 + { // AMD AM29LV256 + long_device_id: true, +@@ -1311,6 +1312,55 @@ + bufsiz : 1 + }, + #endif ++ ++#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL512N ++ { // AMD/SPANSION S29GL512N ++ long_device_id: true, ++ device_id : FLASHWORD(0x227e), ++ device_id2 : FLASHWORD(0x2223), ++ device_id3 : FLASHWORD(0x2201), ++ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 512, ++ device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ bootblock : false, ++ banked : false, ++ bufsiz : 16 ++ }, ++#endif ++ ++#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL256N ++ { // AMD/SPANSION S29GL256N ++ long_device_id: true, ++ device_id : FLASHWORD(0x227e), ++ device_id2 : FLASHWORD(0x2222), ++ device_id3 : FLASHWORD(0x2201), ++ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 256, ++ device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ bootblock : false, ++ banked : false, ++ bufsiz : 16 ++ }, ++#endif ++ ++#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL128N ++ { // AMD/SPANSION S29GL128N ++ long_device_id: true, ++ device_id : FLASHWORD(0x227e), ++ device_id2 : FLASHWORD(0x2221), ++ device_id3 : FLASHWORD(0x2201), ++ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 128, ++ device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ bootblock : false, ++ banked : false, ++ bufsiz : 16 ++ }, ++#endif ++ + #ifdef CYGHWR_DEVS_FLASH_AMD_S29GL064M + { // AMD/SPANSION S29GL064M + long_device_id: true, +@@ -1351,51 +1401,53 @@ + bufsiz : 1 + }, + #endif +-#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL128N +- { // AMD/SPANSION S29GL128N +- long_device_id: true, +- device_id : FLASHWORD(0x227e), +- device_id2 : FLASHWORD(0x2221), +- device_id3 : FLASHWORD(0x2201), +- block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, +- block_count: 128, +- device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE, +- base_mask : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1), +- bootblock : false, +- banked : false, +- bufsiz : 16, +- }, +-#endif +-#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL256N +- { // AMD/SPANSION S29GL256N ++ ++#ifdef CYGHWR_DEVS_FLASH_S29WS256N ++ { // SPANSION S29WS256N (compatible with AM29DL640D except for IDs.) + long_device_id: true, + device_id : FLASHWORD(0x227e), +- device_id2 : FLASHWORD(0x2222), +- device_id3 : FLASHWORD(0x2201), ++ device_id2 : FLASHWORD(0x2230), ++ device_id3 : FLASHWORD(0x2200), + block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, + block_count: 256, + device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE, + base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1), +- bootblock : false, +- banked : false, +- bufsiz : 16, +- }, +-#endif +-#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL512N +- { // AMD/SPANSION S29GL512N +- long_device_id: true, +- device_id : FLASHWORD(0x227e), +- device_id2 : FLASHWORD(0x2223), +- device_id3 : FLASHWORD(0x2201), +- block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, +- block_count: 512, +- device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE, +- base_mask : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1), +- bootblock : false, +- banked : false, +- bufsiz : 16, ++ bootblock : true, ++ bootblocks : { 0x00000000 * CYGNUM_FLASH_INTERLEAVE, /* offset not absolute */ ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x01FE0000 * CYGNUM_FLASH_INTERLEAVE, /* offset not absolute */ ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x8000 * CYGNUM_FLASH_INTERLEAVE, ++ _LAST_BOOTBLOCK ++ }, ++ banked : true, ++ banks : { ++ 0x1E00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1C00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1A00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1800000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1600000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1400000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1200000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x1000000 * CYGNUM_FLASH_INTERLEAVE, ++ 0xE00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0xC00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0xA00000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x800000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x600000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x400000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x200000 * CYGNUM_FLASH_INTERLEAVE, //starting of bank1 ++ 0 //starting of bank0 ++ }, ++ bufsiz : 1 + }, + #endif ++ + #ifdef CYGHWR_DEVS_FLASH_AMD_S29GL128M + { // AMD/SPANSION S29GL128M + long_device_id: true, +@@ -1414,4 +1466,4 @@ + + #endif // 16 bit devices + +-#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_PARTS_INL ++#endif // CYGONCE_DEVS_FLASH_AMD_AM29XXXXX_PARTS_INL +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/at91/current/ChangeLog redboot-imx-200952/packages/devs/flash/arm/at91/current/ChangeLog +--- redboot-imx-200952~/packages/devs/flash/arm/at91/current/ChangeLog 2006-06-02 18:50:34.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/at91/current/ChangeLog 1970-01-01 00:00:00.000000000 +0000 +@@ -1,50 +0,0 @@ +-2006-05-23 Andrew Lunn +- +- * src/at91_flash.c: Support for the AT91SAM7X devices. +- +-2006-02-19 Oliver Munz +- +- * src/at91_flash.c: Optimize the cyg_uint32 page. +- Make the lock/unlock functions work. +- +-2006-02-19 Oliver Munz +- Andrew Lunn +- +- * src/at91_flash.c: +- * cdl/flash_at91.cdl: . +- * ChangeLog: Flash driver for the AT91 Embedded Flash controller, +- e.g. the AT91SAM7S devices. +- +-//=========================================================================== +-//####ECOSGPLCOPYRIGHTBEGIN#### +-// ------------------------------------------- +-// This file is part of eCos, the Embedded Configurable Operating System. +-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +-// Copyright (C) 2006 eCosCentric Ltd +-// Copyright (C) 2006 Andrew Lunn +-// +-// eCos is free software; you can redistribute it and/or modify it under +-// the terms of the GNU General Public License as published by the Free +-// Software Foundation; either version 2 or (at your option) any later version. +-// +-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-// WARRANTY; without even the implied warranty of MERCHANTABILITY or +-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-// for more details. +-// +-// You should have received a copy of the GNU General Public License along +-// with eCos; if not, write to the Free Software Foundation, Inc., +-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-// +-// As a special exception, if other files instantiate templates or use macros +-// or inline functions from this file, or you compile this file and link it +-// with other works to produce a work based on this file, this file does not +-// by itself cause the resulting work to be covered by the GNU General Public +-// License. However the source code for this file must still be made available +-// in accordance with section (3) of the GNU General Public License. +-// +-// This exception does not invalidate any other reasons why a work based on +-// this file might be covered by the GNU General Public License. +-// ------------------------------------------- +-//####ECOSGPLCOPYRIGHTEND#### +-//=========================================================================== +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl redboot-imx-200952/packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl +--- redboot-imx-200952~/packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl 2006-02-19 19:43:01.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +-# ==================================================================== +-# +-# flash_at91.cdl +-# +-# FLASH programming for devices with the Embedded Flash Controller +-# +-# ==================================================================== +-#####ECOSGPLCOPYRIGHTBEGIN#### +-## ------------------------------------------- +-## This file is part of eCos, the Embedded Configurable Operating System. +-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +-## Copyright (C) 2006 eCosCentric LTD +-## Copyright (C) 2006 Andrew Lunn +-## +-## eCos is free software; you can redistribute it and/or modify it under +-## the terms of the GNU General Public License as published by the Free +-## Software Foundation; either version 2 or (at your option) any later version. +-## +-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-## WARRANTY; without even the implied warranty of MERCHANTABILITY or +-## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-## for more details. +-## +-## You should have received a copy of the GNU General Public License along +-## with eCos; if not, write to the Free Software Foundation, Inc., +-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-## +-## As a special exception, if other files instantiate templates or use macros +-## or inline functions from this file, or you compile this file and link it +-## with other works to produce a work based on this file, this file does not +-## by itself cause the resulting work to be covered by the GNU General Public +-## License. However the source code for this file must still be made available +-## in accordance with section (3) of the GNU General Public License. +-## +-## This exception does not invalidate any other reasons why a work based on +-## this file might be covered by the GNU General Public License. +-## ------------------------------------------- +-#####ECOSGPLCOPYRIGHTEND#### +-# ==================================================================== +-######DESCRIPTIONBEGIN#### +-# +-# Author(s): dmoseley +-# Original data: gthomas +-# Contributors: Andrew Lunn, Oliver Munz +-# Date: 2000-10-25 +-# +-#####DESCRIPTIONEND#### +-# +-# ==================================================================== +- +-cdl_package CYGPKG_DEVS_FLASH_AT91 { +- display "at91 FLASH memory support" +- +- parent CYGPKG_IO_FLASH +- active_if CYGPKG_IO_FLASH +- +- implements CYGHWR_IO_FLASH_DEVICE +- +- include_dir . +- description "FLASH memory device support for at91 EFC" +- compile at91_flash.c +- +- cdl_option CYGBLD_DEV_FLASH_AT91_LOCKING { +- display "Support block locking" +- default_value 1 +- implements CYGHWR_IO_FLASH_BLOCK_LOCKING +- description " +- The driver will implement flash block locking when this +- option is enabled. Note that the device implements sector +- locking, not block locking, where sectors are bigger than +- blocks. So the sector which contains the block will be +- locked/unlocked +- +- WARNING: The errata says that these lock bits only have +- a life of 100 cycles for the AT91SAM7S devices." +- } +-} +- +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/at91/current/src/at91_flash.c redboot-imx-200952/packages/devs/flash/arm/at91/current/src/at91_flash.c +--- redboot-imx-200952~/packages/devs/flash/arm/at91/current/src/at91_flash.c 2006-06-02 18:50:34.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/at91/current/src/at91_flash.c 1970-01-01 00:00:00.000000000 +0000 +@@ -1,394 +0,0 @@ +-//========================================================================== +-// +-// at91_flash.c +-// +-// Flash programming for the at91 devices which have the +-// Embedded Flash Controller. +-// +-//========================================================================== +-//####ECOSGPLCOPYRIGHTBEGIN#### +-// ------------------------------------------- +-// This file is part of eCos, the Embedded Configurable Operating System. +-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +-// Copyright (C) 2006 eCosCentric Ltd +-// Copyright (C) 2006 Andrew Lunn (andrew.lunn@ascom.ch) +-// +-// eCos is free software; you can redistribute it and/or modify it under +-// the terms of the GNU General Public License as published by the Free +-// Software Foundation; either version 2 or (at your option) any later version. +-// +-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +-// WARRANTY; without even the implied warranty of MERCHANTABILITY or +-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-// for more details. +-// +-// You should have received a copy of the GNU General Public License along +-// with eCos; if not, write to the Free Software Foundation, Inc., +-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +-// +-// As a special exception, if other files instantiate templates or use macros +-// or inline functions from this file, or you compile this file and link it +-// with other works to produce a work based on this file, this file does not +-// by itself cause the resulting work to be covered by the GNU General Public +-// License. However the source code for this file must still be made available +-// in accordance with section (3) of the GNU General Public License. +-// +-// This exception does not invalidate any other reasons why a work based on +-// this file might be covered by the GNU General Public License. +-// ------------------------------------------- +-//####ECOSGPLCOPYRIGHTEND#### +-//========================================================================== +-//#####DESCRIPTIONBEGIN#### +-// +-// Author(s): gthomas +-// Contributors: gthomas, dmoseley, Andrew Lunn, Oliver Munz +-// Date: 2000-07-26 +-// Purpose: +-// Description: +-// +-//####DESCRIPTIONEND#### +-// +-//========================================================================== +- +-#include +-#include +- +-#include +-#include +-#include +- +-#define _FLASH_PRIVATE_ +-#include +- +-#include +- +-#define FLASH_TIMEOUT 100000 +- +-#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING +-static cyg_uint32 sector_size; +-#endif +- +-// Disable the flash controller from erasing the page before +-// programming it +-static void +-flash_erase_before_write_disable (void) +-{ +- cyg_uint32 fmr; +- +- HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr); +- fmr = fmr | AT91_MC_FMR_NEBP; +- HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr); +-} +- +-// Enable the flash controller to erase the page before programming +-// it +-static void +-flash_erase_before_write_enable (void) +-{ +- +- cyg_uint32 fmr; +- +- HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr); +- fmr = fmr & ~((cyg_uint32) AT91_MC_FMR_NEBP); +- HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr); +-} +- +-// Is the flash controller ready to accept the next command? +-static __inline__ cyg_bool +-flash_controller_is_ready(void) +-CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command"); +- +-static __inline__ cyg_bool +-flash_controller_is_ready(void) +-{ +- cyg_uint32 fsr; +- +- HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr); +- return (fsr & AT91_MC_FSR_FRDY ? true : false); +-} +- +-// Busy loop waiting for the controller to finish the command. +-// Wait a maximum of timeout loops and then return an error. +-static __inline__ int +-flash_wait_for_controller (cyg_uint32 timeout) +-CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command"); +- +-static __inline__ int +-flash_wait_for_controller (cyg_uint32 timeout) +-{ +- while (!flash_controller_is_ready()){ +- timeout--; +- if (!timeout) { +- return FLASH_ERR_DRV_TIMEOUT; +- } +- } +- return FLASH_ERR_OK; +-} +- +-// Execute one command on the flash controller. This code should +-// probably not be in flash +- +-static int +-flash_run_command(cyg_uint32 address, +- cyg_uint32 command, +- cyg_uint32 timeout) +-CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command"); +- +-static int +-flash_run_command(cyg_uint32 address, +- cyg_uint32 command, +- cyg_uint32 timeout) +-{ +- cyg_uint32 retcode; +- cyg_uint32 fsr; +- cyg_uint32 mask; +- cyg_uint32 page; +- +- page = ((cyg_uint32) address - (cyg_uint32) flash_info.start) / +- flash_info.block_size; +- +- // Wait for the last command to finish +- retcode = flash_wait_for_controller(timeout); +- if (retcode != FLASH_ERR_OK){ +- return retcode; +- } +- +- HAL_DISABLE_INTERRUPTS(mask); +- +- HAL_WRITE_UINT32(AT91_MC+AT91_MC_FCR, +- command | +- ((page & AT91_MC_FCR_PAGE_MASK) << AT91_MC_FCR_PAGE_SHIFT) | +- AT91_MC_FCR_KEY); +- +- retcode = flash_wait_for_controller(timeout); +- +- HAL_RESTORE_INTERRUPTS(mask); +- +- if (retcode != FLASH_ERR_OK){ +- return retcode; +- } +- +- // Check for an error +- HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr); +- +- if ((fsr & AT91_MC_FSR_LOCKE) == AT91_MC_FSR_LOCKE) +- return FLASH_ERR_PROTECT; +- if ((fsr & AT91_MC_FSR_PROGE) == AT91_MC_FSR_PROGE) +- return FLASH_ERR_PROGRAM; +- +- return FLASH_ERR_OK; +-} +- +-// The flash is embedded in the CPU package. So return the chip +-// ID. This allows us to determine if the chip is one we support and +-// the size of the flash +-int flash_query(void *data) +-{ +- cyg_uint32 chipID1r; +- +- HAL_READ_UINT32(AT91_DBG+AT91_DBG_C1R, chipID1r); +- +- memcpy(data, &chipID1r, sizeof(chipID1r)); +- return FLASH_ERR_OK; +-} +- +-// Initialize the hardware. Make sure we have a flash device we know +-// how to program and determine its size, the size of the blocks, and +-// the number of blocks. The query function returns the chip ID 1 +-// register which tells us about the CPU we are running on, the flash +-// size etc. Use this information to determine we have a valid setup. +-int +-flash_hwr_init(void){ +- +- cyg_uint32 chipID1r; +- cyg_uint32 flash_mode; +- cyg_uint8 fmcn; +- cyg_uint32 lock_bits; +- +- flash_query (&chipID1r); +- +- if ((chipID1r & AT91_DBG_C1R_CPU_MASK) != AT91_DBG_C1R_ARM7TDMI) +- goto out; +- +- if (((chipID1r & AT91_DBG_C1R_ARCH_MASK) != AT91_DBG_C1R_ARCH_AT91SAM7Sxx) && +- ((chipID1r & AT91_DBG_C1R_ARCH_MASK) != AT91_DBG_C1R_ARCH_AT91SAM7Xxx)) +- goto out; +- +- if ((chipID1r & AT91_DBG_C1R_FLASH_MASK) == AT91_DBG_C1R_FLASH_0K) +- goto out; +- +- switch (chipID1r & AT91_DBG_C1R_FLASH_MASK) { +- case AT91_DBG_C1R_FLASH_32K: +- flash_info.block_size = 128; +- flash_info.blocks = 256; +- lock_bits = 8; +- break; +- case AT91_DBG_C1R_FLASH_64K: +- flash_info.block_size = 128; +- flash_info.blocks = 512; +- lock_bits = 16; +- break; +- case AT91_DBG_C1R_FLASH_128K: +- flash_info.block_size = 256; +- flash_info.blocks = 512; +- lock_bits = 8; +- break; +- case AT91_DBG_C1R_FLASH_256K: +- flash_info.block_size = 256; +- flash_info.blocks = 1024; +- lock_bits = 16; +- break; +- default: +- goto out; +- } +- flash_info.buffer_size = 0; +- flash_info.start = (void *) 0x00100000; +- flash_info.end = (void *)(((cyg_uint32) flash_info.start) + +- flash_info.block_size * flash_info.blocks); +-#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING +- sector_size = flash_info.block_size * flash_info.blocks / lock_bits; +-#endif +- // Set the FLASH clock to 1.5 microseconds based on the MCLK. This +- // assumes the CPU is still running from the PLL clock as defined in +- // the HAL CDL and the HAL startup code. +- fmcn = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / 1000000 * 1.5; +- HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, flash_mode); +- flash_mode = flash_mode & ~AT91_MC_FMR_FMCN_MASK; +- flash_mode = flash_mode | (fmcn << AT91_MC_FMR_FMCN_SHIFT); +- HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, flash_mode); +- +- return FLASH_ERR_OK; +- +- out: +- (*flash_info.pf)("Can't identify FLASH, sorry, ChipID1 %x\n", +- chipID1r ); +- return FLASH_ERR_HWR; +-} +- +-// Erase a block. The flash controller does not have a command to +-// erase a block. So instead we setup the controller to do a program +-// writing all 0xff with an erase operation first. +-int +-flash_erase_block (volatile unsigned long block) +-{ +- cyg_uint32 retcode; +- cyg_uint32 *buffer; +- cyg_uint32 *end; +- +- buffer = (cyg_uint32 *) block; +- end = (cyg_uint32 *) (block + flash_info.block_size); +- +- while (buffer < end){ +- *buffer = (cyg_uint32) 0xffffffff; +- buffer++; +- } +- +- flash_erase_before_write_enable(); +- retcode = flash_run_command(block, +- AT91_MC_FCR_START_PROG, +- FLASH_TIMEOUT); +- +- return retcode; +-} +- +-// Write into the flash. The datasheet says that performing 8 or 16bit +-// accesses results in unpredictable corruption. So the current code +-// checks that these conditions are upheld. It would be possible to +-// perform extra reads and masking operation to support writing to +-// none word assigned addresses or not multiple or a word length. +-int +-flash_program_buf (volatile unsigned long addr, unsigned long *data, int len) +-{ +- cyg_uint32 retcode; +- volatile unsigned long *target; +- +- CYG_ASSERT(len % 4 == 0, "Only word writes allowed by current code"); +- CYG_ASSERT(addr % 4 == 0, "Address must be word aligned for current code"); +- +- target = (volatile unsigned long *)addr; +- +- while (len > 0) { +- *target = *data; +- data++; +- target++; +- len = len - sizeof(unsigned long); +- } +- +- flash_erase_before_write_disable(); +- retcode = flash_run_command(addr, +- AT91_MC_FCR_START_PROG, +- FLASH_TIMEOUT); +- +- return retcode; +-} +- +-#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING +-// Unlock a block. This is not strictly possible, we can only lock and +-// unlock sectors. This will unlock the sector which contains the +-// block. +-int +-flash_unlock_block(volatile unsigned long block, int block_size, int blocks) +-{ +- cyg_uint32 sector; +- cyg_uint32 retcode; +- cyg_uint32 status; +- +- sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) / +- sector_size; +- +- HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status); +- +- if (status & (1 << (sector + 16))){ +- retcode = flash_run_command(block, +- AT91_MC_FCR_UNLOCK, +- FLASH_TIMEOUT); +- return retcode; +- } else { +- return FLASH_ERR_OK; +- } +-} +- +-// Lock a block. This is not strictly possible, we can only lock and +-// unlock sectors. This will lock the sector which contains the +-// block. +-int +-flash_lock_block(volatile unsigned long block, int block_size, int blocks) +-{ +- cyg_uint32 sector; +- cyg_uint32 retcode; +- cyg_uint32 status; +- +- sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) / +- sector_size; +- +- HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status); +- +- if (!(status & (1 << (sector + 16)))){ +- retcode = flash_run_command(block, +- AT91_MC_FCR_LOCK, +- FLASH_TIMEOUT); +- +- return retcode; +- } else { +- return FLASH_ERR_OK; +- } +-} +-#endif +- +-// Map a hardware status to a package error. NOP since the errors are +-// already mapped. +-int flash_hwr_map_error(int err){ +- +- return err; +-} +- +-// See if a range of FLASH addresses overlaps currently running code +-bool flash_code_overlaps(void *start, void *end){ +- +- extern char _stext[], _etext[]; +- +- return ((((unsigned long)&_stext >= (unsigned long)start) && +- ((unsigned long)&_stext < (unsigned long)end)) || +- (((unsigned long)&_etext >= (unsigned long)start) && +- ((unsigned long)&_etext < (unsigned long)end))); +-} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/imx_3stack/current/cdl/flash_board_spansion.cdl redboot-imx-200952/packages/devs/flash/arm/imx_3stack/current/cdl/flash_board_spansion.cdl +--- redboot-imx-200952~/packages/devs/flash/arm/imx_3stack/current/cdl/flash_board_spansion.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/imx_3stack/current/cdl/flash_board_spansion.cdl 2010-01-26 17:33:12.862958261 +0000 +@@ -0,0 +1,71 @@ ++# ==================================================================== ++# ++# flash_board_spansion.cdl ++# ++# FLASH memory - Hardware support ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): gthomas ++# Original data: gthomas ++# Contributors: ++# Date: 2000-07-26 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION { ++ display "Freescale Spansion FLASH memory support" ++ ++ parent CYGPKG_IO_FLASH ++ active_if CYGPKG_IO_FLASH ++ ++ implements CYGHWR_IO_FLASH_DEVICE ++ ++ compile board_spansionflash.c ++ ++ # Arguably this should do in the generic package ++ # but then there is a logic loop so you can never enable it. ++ cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED { ++ display "Generic AMD FlashFile driver required" ++ } ++ ++ implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED ++ ++ requires CYGHWR_DEVS_FLASH_AMD_S29GL512N ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/imx_3stack/current/src/board_spansionflash.c redboot-imx-200952/packages/devs/flash/arm/imx_3stack/current/src/board_spansionflash.c +--- redboot-imx-200952~/packages/devs/flash/arm/imx_3stack/current/src/board_spansionflash.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/imx_3stack/current/src/board_spansionflash.c 2010-01-26 17:33:12.872957386 +0000 +@@ -0,0 +1,73 @@ ++//========================================================================== ++// ++// board_spansionflash.c ++// ++// Flash programming for AMD Flash devices ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Patrick Doyle ++// Contributors: Patrick Doyle ++// Date: 2002-11-26 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++ ++//-------------------------------------------------------------------------- ++// Device properties ++ ++// We use the one SPANSION S29WS256N part on the EVB. ++#define CYGNUM_FLASH_INTERLEAVE (1) ++#define CYGNUM_FLASH_SERIES (1) ++#define CYGNUM_FLASH_WIDTH (16) ++#define CYGNUM_FLASH_BASE (CS0_BASE_ADDR) ++ ++#define CYGNUM_FLASH_TIMEOUT_QUERY 5000000 ++#define CYGNUM_FLASH_TIMEOUT_ERASE_TIMER 100000000 ++#define CYGNUM_FLASH_TIMEOUT_ERASE_COMPLETE 100000000 ++#define CYGNUM_FLASH_TIMEOUT_PROGRAM 100000000 ++//-------------------------------------------------------------------------- ++// Platform specific extras ++ ++//-------------------------------------------------------------------------- ++// Now include the driver code. ++#include "cyg/io/flash_am29xxxxx.inl" +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_spansion.cdl redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_spansion.cdl +--- redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_spansion.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_spansion.cdl 2010-01-26 17:33:12.932954762 +0000 +@@ -0,0 +1,71 @@ ++# ==================================================================== ++# ++# flash_board_spansion.cdl ++# ++# FLASH memory - Hardware support ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): gthomas ++# Original data: gthomas ++# Contributors: ++# Date: 2000-07-26 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_FLASH_MX35EVB_SPANSION { ++ display "Freescale Spansion FLASH memory support" ++ ++ parent CYGPKG_IO_FLASH ++ active_if CYGPKG_IO_FLASH ++ ++ implements CYGHWR_IO_FLASH_DEVICE ++ ++ compile board_spansionflash.c ++ ++ # Arguably this should do in the generic package ++ # but then there is a logic loop so you can never enable it. ++ cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED { ++ display "Generic AMD FlashFile driver required" ++ } ++ ++ implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED ++ ++ requires CYGHWR_DEVS_FLASH_S29WS256N ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_strata.cdl redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_strata.cdl +--- redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_strata.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/cdl/flash_board_strata.cdl 2010-01-26 17:33:12.942960887 +0000 +@@ -0,0 +1,80 @@ ++# ==================================================================== ++# ++# flash_board_strata.cdl ++# ++# FLASH memory - Hardware support ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): gthomas ++# Original data: gthomas ++# Contributors: ++# Date: 2000-07-26 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_FLASH_MX35EVB_STRATA { ++ display "Freescale FLASH memory support" ++ ++ parent CYGPKG_IO_FLASH ++ active_if CYGPKG_IO_FLASH ++ ++ requires CYGPKG_DEVS_FLASH_STRATA ++ requires CYGNUM_DEVS_FLASH_STRATA_MAX_BLOCKS == 256 ++ ++ implements CYGHWR_IO_FLASH_BLOCK_LOCKING ++ ++ include_dir cyg/io ++ ++ # Arguably this should do in the generic package ++ # but then there is a logic loop so you can never enable it. ++ cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED { ++ display "Generic StrataFLASH driver required" ++ } ++ ++ implements CYGINT_DEVS_FLASH_STRATA_REQUIRED ++ ++ define_proc { ++ puts $::cdl_system_header "/***** strataflash driver proc output start *****/" ++ puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL " ++ puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG " ++ puts $::cdl_system_header "/***** strataflash driver proc output end *****/" ++ } ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/include/board_strataflash.inl redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/include/board_strataflash.inl +--- redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/include/board_strataflash.inl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/include/board_strataflash.inl 2010-01-26 17:33:12.942960887 +0000 +@@ -0,0 +1,64 @@ ++#ifndef CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL ++#define CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL ++//========================================================================== ++// ++// board_strataflash.inl ++// ++// Flash programming - device constants, etc. ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): gthomas, hmt ++// Contributors: gthomas ++// Date: 2001-02-24 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++// The system has one 16-bit devices. ++// a StrataFlash 28F256L18. The 256 means 256Mbit, so 32Mbyte with 16bit width. ++ ++#define CYGNUM_FLASH_DEVICES (1) ++#define CYGNUM_FLASH_BASE (0xA0000000u) ++#define CYGNUM_FLASH_BASE_MASK (0xFE000000u) // 32MB devices (size=0x02000000 -> mask=0xFE000000) ++#define CYGNUM_FLASH_WIDTH (16) ++#define CYGNUM_FLASH_BLANK (1) ++ ++#endif // CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/src/board_spansionflash.c redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/src/board_spansionflash.c +--- redboot-imx-200952~/packages/devs/flash/arm/mx35evb/current/src/board_spansionflash.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mx35evb/current/src/board_spansionflash.c 2010-01-26 17:33:12.942960887 +0000 +@@ -0,0 +1,73 @@ ++//========================================================================== ++// ++// board_spansionflash.c ++// ++// Flash programming for AMD Flash devices ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Patrick Doyle ++// Contributors: Patrick Doyle ++// Date: 2002-11-26 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++ ++//-------------------------------------------------------------------------- ++// Device properties ++ ++// We use the one SPANSION S29WS256N part on the EVB. ++#define CYGNUM_FLASH_INTERLEAVE (1) ++#define CYGNUM_FLASH_SERIES (1) ++#define CYGNUM_FLASH_WIDTH (16) ++#define CYGNUM_FLASH_BASE (CS0_BASE_ADDR) ++ ++#define CYGNUM_FLASH_TIMEOUT_QUERY 5000000 ++#define CYGNUM_FLASH_TIMEOUT_ERASE_TIMER 100000000 ++#define CYGNUM_FLASH_TIMEOUT_ERASE_COMPLETE 100000000 ++#define CYGNUM_FLASH_TIMEOUT_PROGRAM 100000000 ++//-------------------------------------------------------------------------- ++// Platform specific extras ++ ++//-------------------------------------------------------------------------- ++// Now include the driver code. ++#include "cyg/io/flash_am29xxxxx.inl" +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/cdl/mxc_flash_select.cdl redboot-imx-200952/packages/devs/flash/arm/mxc/current/cdl/mxc_flash_select.cdl +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/cdl/mxc_flash_select.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/cdl/mxc_flash_select.cdl 2010-01-26 17:33:12.942960887 +0000 +@@ -0,0 +1,155 @@ ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): gthomas ++# Original data: gthomas ++# Contributors: ++# Date: 2000-07-26 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_FLASH_ONMXC { ++ display "Support FLASH memory on Freescale MXC platforms" ++ ++ implements CYGHWR_IO_FLASH_DEVICE ++ parent CYGPKG_IO_FLASH ++ active_if CYGPKG_IO_FLASH ++ ++ include_dir cyg/io ++ ++ cdl_component CYGHWR_DEVS_FLASH_MMC { ++ display "MXC platform MMC card support" ++ default_value 0 ++ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 } ++ description " ++ When this option is enabled, it indicates MMC card is ++ supported on the MXC platforms" ++ define_proc { ++ puts $::cdl_system_header "#define MXCFLASH_SELECT_MMC" ++ } ++ compile mxc_mmc.c ++ ++ cdl_option CYGHWR_DEVS_FLASH_MMC_ESDHC { ++ display "MXC platform MMC card for newer SDHC controllers" ++ active_if { CYGPKG_HAL_ARM_MX37_3STACK || CYGPKG_HAL_ARM_MX35_3STACK || CYGPKG_HAL_ARM_MX25_3STACK || CYGPKG_HAL_ARM_MX51} ++ default_value 1 ++ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 } ++ compile mxcmci_core.c mxcmci_host.c mxcmci_mmc.c mxcmci_sd.c mxcmci_sd.c ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_MMC_SD { ++ display "MXC platform MMC card for older MMC/SD controllers" ++ active_if { CYGPKG_HAL_ARM_MX31_3STACK || CYGPKG_HAL_ARM_MX31ADS } ++ default_value 1 ++ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 } ++ compile card_mx32.c ++ } ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_MXC_NOR { ++ display "MXC platform NOR flash memory support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates NOR flash is ++ supported on the MXC platforms" ++ define_proc { ++ puts $::cdl_system_header "#define MXCFLASH_SELECT_NOR" ++ } ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { ++ display "MXC platform NAND flash memory support" ++ default_value 0 ++ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 } ++ description " ++ When this option is enabled, it indicates NAND flash is ++ supported on the MXC platforms" ++ define_proc { ++ puts $::cdl_system_header "#define MXCFLASH_SELECT_NAND" ++ } ++ compile mxc_nfc.c ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_STMP_NAND { ++ display "STMP platform NAND flash memory support" ++ default_value 0 ++ requires { CYGSEM_IO_FLASH_READ_INDIRECT == 1 } ++ description " ++ When this option is enabled, it indicates NAND flash is ++ supported on the STMP platforms" ++ define_proc { ++ puts $::cdl_system_header "#define STMPFLASH_SELECT_NAND" ++ } ++ compile stmp_nand.c ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR { ++ display "i.MX platform SPI NOR flash memory support" ++ default_value 0 ++ requires { CYGHWR_DEVS_FLASH_MXC_NOR == 1 } ++ description " ++ When this option is enabled, it indicates SPI NOR flash is ++ supported on the i.MX platforms" ++ define_proc { ++ puts $::cdl_system_header "#define IMXFLASH_SELECT_SPI_NOR" ++ } ++ compile spi_nor.c spi_nor_sst.c spi_nor_atmel.c ++ } ++ ++ cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI { ++ display "MXC platform multi flash memory support" ++ default_value 1 ++ active_if {((CYGHWR_DEVS_FLASH_MXC_NAND || CYGHWR_DEVS_FLASH_STMP_NAND) && CYGHWR_DEVS_FLASH_MXC_NOR) || ++ ((CYGHWR_DEVS_FLASH_MXC_NAND || CYGHWR_DEVS_FLASH_STMP_NAND) && CYGHWR_DEVS_FLASH_MMC) || ++ (CYGHWR_DEVS_FLASH_MXC_NOR && CYGHWR_DEVS_FLASH_MMC)} ++ description " ++ When this option is enabled, it indicates multi flashes are ++ supported on the MXC platforms (like NAND and NOR)" ++ define_proc { ++ puts $::cdl_system_header "#define MXCFLASH_SELECT_MULTI" ++ } ++ compile mxcflash_wrapper.c ++ } ++ cdl_interface CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND { ++ display "MXC platform NAND flash reset workaround support" ++ active_if {CYGHWR_DEVS_FLASH_MXC_NAND} ++ description " ++ When this option is enabled, it indicates 0xFFFF is used for ++ the NAND reset command instead of 0xFF." ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/card_mx32.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/card_mx32.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/card_mx32.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/card_mx32.h 2010-01-26 17:33:12.942960887 +0000 +@@ -0,0 +1,242 @@ ++#ifndef CARD_MX32_H ++#define CARD_MX32_H ++ ++#include ++ ++/*sdhc memory map*/ ++typedef struct _sdhc ++{ ++ volatile cyg_uint32 sdhc_clk; ++ volatile cyg_uint32 sdhc_status; ++ volatile cyg_uint32 sdhc_clk_rate; ++ volatile cyg_uint32 sdhc_dat_cont; ++ volatile cyg_uint32 sdhc_response_to; ++ volatile cyg_uint32 sdhc_read_to; ++ volatile cyg_uint32 sdhc_blk_len; ++ volatile cyg_uint32 sdhc_nob; ++ volatile cyg_uint32 sdhc_rev_no; ++ volatile cyg_uint32 sdhc_int_cntr; ++ volatile cyg_uint32 sdhc_cmd; ++ volatile cyg_uint32 sdhc_arg; ++ volatile cyg_uint32 sdhc_reserved; ++ volatile cyg_uint32 sdhc_res_fifo; ++ volatile cyg_uint32 sdhc_buffer_access; ++}sdhc_t, *psdhc_t; ++ ++/* Defines for card types */ ++typedef enum ++{ ++ TYPE_NONE, ++ SD_CSD_1_0, ++ SD_CSD_2_0, ++ MMC_CSD_1_0, ++ MMC_CSD_1_1, ++ MMC_CSD_1_2, ++ MMC_UNKNOWN ++}card_type; ++ ++/* Defines for card types */ ++typedef struct _card_id ++{ ++ cyg_uint32 cid0; ++ cyg_uint32 cid1; ++ cyg_uint32 cid2; ++ cyg_uint32 cid3; ++}CARD_ID; ++ ++enum sdhc_clk_val ++{ ++ SDHC_CLK_START = 0x2, ++ SDHC_CLK_STOP = 0x1, ++ SDHC_CLK_RESET = 0x8 ++}; ++ ++typedef enum frequency_mode ++{ ++ iden_mode = 0x1, ++ trans_mode = 0x2 ++} frequency_mode_t; ++ ++typedef struct command ++{ ++ cyg_uint32 index; ++ cyg_uint32 data_control; ++ cyg_uint32 arg; ++}command_t; ++ ++ ++#define NO_ARG 0 ++#define ENABLE 1 ++#define DISABLE 0 ++#define PASS 0 ++#define SUCCESS 0 ++#define FAIL 1 ++ ++#define CARD_STATE 0x1E00 ++#define CARD_STATE_SHIFT 9 ++ ++/*Defines of CSD data*/ ++#define CSD_STRUCT_MSK 0xC0000000 ++#define CSD_STRUCT_SHIFT 30 ++ ++ ++/* Define the states of the card*/ ++enum states ++{ ++ IDLE, ++ READY, ++ IDENT, ++ STBY, ++ TRAN, ++ DATA, ++ RCV, ++ PRG, ++ DIS ++}; ++ ++ ++/* SDHC Response */ ++typedef struct _response ++{ ++ cyg_uint32 rsp0; ++ cyg_uint32 rsp1; ++ cyg_uint32 rsp2; ++ cyg_uint32 rsp3; ++}response_t; ++ ++ ++typedef enum card_mode ++{ ++ NONE = 0, ++ SD = 1, ++ MMC = 2 ++}card_mode_t; ++ ++enum RW ++{ ++ READ = 0, ++ WRITE = 1 ++}; ++ ++enum cmd_response ++{ ++ RESPONSE_NO = 0x0, ++ RESPONSE_48_CRC = 0x1, ++ RESPONSE_136 = 0x2, ++ RESPONSE_48_WITHOUT_CRC = 0x3 ++}; ++ ++enum status_bus_width ++{ ++ ONE = 0x0, ++ FOUR = 0x2 ++}; ++ ++ ++#define SDHC_INT 0xc015 ++ ++#define SD_OCR_VALUE_HV_LC 0x00ff8000 /* 3.3v, LC */ ++#define SD_OCR_VALUE_HV_HC 0x40ff8000 /* 3.3v, HC */ ++/* LV_LC not needed - 1.8v is only supported under eSD which supports HC by default (SD>2.00) */ ++#define SD_OCR_VALUE_LV_HC 0x40000080 /* 1.8v, HC */ ++#define SD_OCR_HC_RES 0x40000000 ++#define SD_OCR_LC_RES 0x00000000 ++#define SD_IF_HV_COND_ARG 0x000001AA ++#define SD_IF_LV_COND_ARG 0x000002AA ++ ++#define MMC_OCR_VALUE 0x40FF8000 ++#define MMC_OCR_VALUE_BAK 0x80FFC000 ++#define MMC_OCR_HC_RES 0xC0FF8000 ++#define MMC_OCR_LC_RES 0x80FF8000 ++#define MMC_OCR_VALUE_MASK 0x00FF8000 ++ ++#define CARD_BUSY 0x80000000 ++#define SD_R1_APP_CMD_MSK 0x20 ++ ++#define BLOCK_LEN 0x200 ++ ++ ++ ++/* Status regsiter Masks */ ++#define SDHC_STATUS_END_CMD_RESP_MSK 0x2000 ++#define SDHC_STATUS_WRITE_OP_DONE_MSK 0x1000 ++#define SDHC_STATUS_READ_OP_DONE_MSK 0x800 ++#define SDHC_STATUS_WR_CRC_ERR_CODE_MSK 0x600 ++#define SDHC_STATUS_CARD_BUS_CLK_RUN_MSK 0x100 ++#define SDHC_STATUS_RESP_CRC_ERR_MSK 0x20 ++#define SDHC_STATUS_BUF_READ_RDY_MSK 0x80 ++#define SDHC_STATUS_BUF_WRITE_RDY_MSK 0x40 ++#define SDHC_STATUS_READ_CRC_ERR_MSK 0x8 ++#define SDHC_STATUS_WRITE_CRC_ERR_MSK 0x4 ++#define SDHC_STATUS_TIME_OUT_RESP_MSK 0x2 ++#define SDHC_STATUS_TIME_OUT_READ 0x1 ++ ++#define SDHC_STATUS_CLEAR ((cyg_uint32)(0xC0007E2F)) ++ ++ ++ ++/* Command (data control) masks */ ++#define SDHC_CMD_FROMAT_OF_RESP 0x00000007 ++#define SDHC_CMD_DATA_ENABLE 0x00000008 ++#define SDHC_CMD_WRITE_READ 0x00000010 ++#define SDHC_CMD_INIT 0x00000080 ++#define SDHC_CMD_BUS_WIDTH 0x00000300 ++#define SDHC_CMD_START_READWAIT 0x00000400 ++#define SDHC_CMD_STOP_READWAIT 0x00000800 ++#define SDHC_CMD_DATA_CTRL_CMD_RESP_LONG_OFF 0x00001000 ++ ++/* Command (data control) shift */ ++#define SDHC_CMD_FROMAT_OF_RESP_SHIFT 0x0 ++#define SDHC_CMD_DATA_ENABLE_SHIFT 0x3 ++#define SDHC_CMD_BUS_WIDTH_SHIFT 0x8 ++#define SDHC_CMD_WRITE_READ_SHIFT 0x4 ++#define SDHC_CMD_INIT_SHIFT 0x7 ++ ++//#define SDHC_CMD_FROMAT_OF_RESP_NONE 0x0 ++//#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48 0x1 ++//#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_136 0x2 ++//#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48_N0_CRC 0x3 ++//#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_1_BIT 0x0 ++//#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_4_BIT 0x2 ++ ++/* Define each command */ ++enum commands ++{ ++ CMD0= 0, ++ CMD1= 1, ++ CMD2= 2, ++ CMD3= 3, ++ CMD5= 5, ++ CMD6=6, ++ ACMD6= 6, ++ CMD7= 7, ++ CMD8 = 8, ++ CMD9=9, ++ CMD12 = 12, ++ CMD13 = 13, ++ CMD16 = 16, ++ CMD17 = 17, ++ CMD18 = 18, ++ CMD24 = 24, ++ CMD25 = 25, ++ CMD26 = 26, ++ CMD32 = 32, ++ CMD33 = 33, ++ CMD35 = 35, ++ CMD36 = 36, ++ CMD38 = 38, ++ ACMD41 = 41, ++ ACMD51 = 51, ++ CMD55 = 55 ++}; ++ ++extern cyg_uint32 CCC; /* Card Command Class */ ++ ++extern cyg_uint32 mxcmci_init (cyg_uint32 bus_width, cyg_uint32 base_address); ++extern cyg_uint32 mmc_data_write (cyg_uint32 *src_ptr,cyg_uint32 length,cyg_uint32 offset); ++extern cyg_uint32 mmc_data_erase (cyg_uint32 offset, cyg_uint32 size); ++extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32); ++extern cyg_uint32 card_flash_query(void* data); ++extern cyg_uint32 card_get_capacity_size (void); ++ ++#endif +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/imx_nfc.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/imx_nfc.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/imx_nfc.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/imx_nfc.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,133 @@ ++#ifndef _IMX_NFC_H_ ++#define _IMX_NFC_H_ ++//========================================================================== ++// ++// imx_nfc.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2008-06-02 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#define NFC_DEBUG_MIN 1 ++#define NFC_DEBUG_MED 2 ++#define NFC_DEBUG_MAX 3 ++#define NFC_DEBUG_DEF NFC_DEBUG_MAX ++ ++extern int _mxc_boot; ++typedef unsigned short u16; ++typedef unsigned int u32; ++typedef unsigned char u8; ++ ++//---------------------------------------------------------------------------- ++// Common device details. ++#define FLASH_Read_ID (0x90) ++#ifdef CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND ++#define FLASH_Reset 0xFFFF ++#else ++#define FLASH_Reset (0xFF) ++#endif ++#define FLASH_Read_Mode1 (0x00) ++#define FLASH_Read_Mode1_LG (0x30) ++#define FLASH_Read_Mode2 (0x01) ++#define FLASH_Read_Mode3 (0x50) ++#define FLASH_Program (0x10) ++#define FLASH_Send_Data (0x80) ++#define FLASH_Status (0x70) ++#define FLASH_Block_Erase (0x60) ++#define FLASH_Start_Erase (0xD0) ++ ++/* Information about supported devices */ ++typedef struct flash_device_info { ++ cyg_uint16 device_id; ++ cyg_uint16 device_id2; ++ cyg_uint16 device_id3; ++ cyg_uint16 device_id4; ++ cyg_uint16 page_size; ++ cyg_uint16 spare_size; ++ cyg_uint32 pages_per_block; ++ cyg_uint32 block_size; ++ cyg_int32 block_count; ++ cyg_uint32 device_size; ++ cyg_uint32 port_size; // x8 or x16 IO ++ cyg_uint32 type; // SLC vs MLC ++ cyg_uint32 options; ++ cyg_uint32 fis_start_addr; ++ cyg_uint32 bi_off; ++ cyg_uint32 bbt_blk_max_nr; ++ cyg_uint8 vendor_info[96]; ++ cyg_uint32 col_cycle; // number of column address cycles ++ cyg_uint32 row_cycle; // number of row address cycles ++} flash_dev_info_t; ++ ++enum nfc_page_area { ++ NFC_SPARE_ONLY, ++ NFC_MAIN_ONLY, ++}; ++ ++enum { ++ MXC_NAND_8_BIT = 8, ++ MXC_NAND_16_BIT = 16, ++}; ++ ++enum { ++ NAND_SLC = 0, ++ NAND_MLC = 1, ++}; ++ ++// read column 464-465 byte but only 464 for bad block marker ++#define BAD_BLK_MARKER_464 (NAND_MAIN_BUF3 + 464) ++// read column 4-5 byte, but only 5 is used for swapped main area data ++#define BAD_BLK_MARKER_SP_5 (NAND_SPAR_BUF3 + 4) ++ ++typedef void nfc_iomuxsetup_func_t(void); ++typedef unsigned int nfc_setup_func_t(flash_dev_info_t*, unsigned int); ++ ++/* Mechanism to distinguish between programming Bad Block Table and norma data */ ++#define FILE_FORMAT_NORMAL 0x1 ++#define FILE_FORMAT_BBT 0x2 ++ ++#endif // _IMX_NFC_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/imx_spi_nor.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/imx_spi_nor.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/imx_spi_nor.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/imx_spi_nor.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,127 @@ ++#ifndef _IMX_SPI_NOR_H_ ++#define _IMX_SPI_NOR_H_ ++//========================================================================== ++// ++// imx_nfc.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2008-11-14 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++// dummy defines - not used ++#define CYGNUM_FLASH_INTERLEAVE 1 ++#define CYGNUM_FLASH_SERIES 1 ++#define CYGNUM_FLASH_WIDTH 8 ++#define CYGNUM_FLASH_BASE 0 ++#define CYGNUM_FLASH_BLANK 1 ++ ++#define READ 0x03 // tx: 1 byte cmd + 3 byte addr; rx: variable bytes ++#define READ_HS 0x0B // tx: 1 byte cmd + 3 byte addr + 1 byte dummy; rx: variable bytes ++#define RDSR 0x05 // read status register 1 byte tx cmd + 1 byte rx status ++ #define RDSR_BUSY (1 << 0) // 1=write-in-progress (default 0) ++ #define RDSR_WEL (1 << 1) // 1=write enable (default 0) ++ #define RDSR_BP0 (1 << 2) // block write prot level (default 1) ++ #define RDSR_BP1 (1 << 3) // block write prot level (default 1) ++ #define RDSR_BP2 (1 << 4) // block write prot level (default 1) ++ #define RDSR_BP3 (1 << 5) // block write prot level (default 1) ++ #define RDSR_AAI (1 << 6) // 1=AAI prog mode; 0=byte prog (default 0) ++ #define RDSR_BPL (1 << 7) // 1=BP3,BP2,BP1,BP0 RO; 0=R/W (default 0) ++#define WREN 0x06 // write enable. 1 byte tx cmd ++#define WRDI 0x04 // write disable. 1 byte tx cmd ++#define EWSR 0x50 // Enable write status. 1 byte tx cmd ++#define WRSR 0x01 // Write status register. 1 byte tx cmd + 1 byte tx value ++#define ERASE_4K 0x20 // sector erase. 1 byte cmd + 3 byte addr ++#define ERASE_32K 0x52 // 32K block erase. 1 byte cmd + 3 byte addr ++#define ERASE_64K 0xD8 // 64K block erase. 1 byte cmd + 3 byte addr ++#define ERASE_CHIP 0x60 // whole chip erase ++#define BYTE_PROG 0x02 // all tx: 1 cmd + 3 addr + 1 data ++#define AAI_PROG 0xAD // all tx: [1 cmd + 3 addr + 2 data] + RDSR ++ // + [1cmd + 2 data] + .. + [WRDI] + [RDSR] ++#define JEDEC_ID 0x9F // read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID ++ ++ ++/* Atmel SPI-NOR commands */ ++#define WR_2_MEM_DIR 0x82 ++#define BUF1_WR 0x84 ++#define BUF2_WR 0x87 ++#define BUF1_TO_MEM 0x83 ++#define BUF2_TO_MEM 0x86 ++#define STAT_READ 0xD7 ++ #define STAT_PG_SZ (1 << 0) // 1=Page size is 512, 0=Page size is 528 (default 0) ++ #define STAT_PROT (1 << 1) // 1=sector protection enabled (default 0) ++ #define STAT_COMP (1 << 6) ++ #define STAT_BUSY (1 << 7) // 1=Device not busy ++#define CONFIG_REG1 0x3D ++#define CONFIG_REG2 0x2A ++#define CONFIG_REG3 0x80 ++#define CONFIG_REG4 0xA6 ++ ++#define SZ_64K 0x10000 ++#define SZ_32K 0x8000 ++#define SZ_4K 0x1000 ++#define TRANS_FAIL -1 ++ ++extern imx_spi_init_func_t *spi_nor_init; ++extern imx_spi_xfer_func_t *spi_nor_xfer; ++extern struct imx_spi_dev imx_spi_nor; ++static int spi_nor_status(void); ++static int spi_nor_cmd_1byte(unsigned char cmd); ++int spi_nor_erase_block(void* block_addr, unsigned int block_size); ++int spi_nor_erase_64k(void* block_addr, unsigned int size); ++static int spi_nor_write_status(unsigned char val); ++int spi_nor_program_buf(void *addr, void *data, int len); ++ ++int spi_nor_program_buf_sst(void *addr, void *data, int len, unsigned int block_size); ++int spi_nor_erase_block_sst(void* block_addr, unsigned int block_size); ++ ++int spi_nor_program_buf_atm(void *addr, void *data, int len, unsigned int block_size); ++int spi_nor_erase_block_atm(void* block_addr, unsigned int block_size); ++ ++typedef int imx_spi_write_func_t(void *addr, void *data, int len, unsigned int block_size); ++typedef int imx_spi_erase_func_t(void* block_addr, unsigned int block_size); ++ ++#endif // _IMX_SPI_NOR_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_mmc.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_mmc.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_mmc.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_mmc.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,50 @@ ++/*================================================================================= ++ ++ Module Name: mxc_mmc.h ++ ++ General Description: Limited Bootloader eSDHC Driver. ++ ++=================================================================================== ++ Copyright: 2004,2005,2006,2007,2008 FREESCALE, INC. ++ All Rights Reserved. This file contains copyrighted material. ++ Use of this file is restricted by the provisions of a ++ Freescale Software License Agreement, which has either ++ accompanied the delivery of this software in shrink wrap ++ form or been expressly executed between the parties. ++ ++ ++Revision History: ++ Modification Tracking ++Author (core ID) Date Number Description of Changes ++------------------------- ------------ ---------- -------------------------- ++Lewis Liu 18-Feb-2008 ++ ++ ++Portability: Portable to other compilers or platforms. ++ ++====================================================================================================*/ ++ ++#ifndef __MXC_MMC_H__ ++#define __MXC_MMC_H__ ++ ++#include ++ ++#define FLASH_DEBUG_MIN 1 ++#define FLASH_DEBUG_MED 2 ++#define FLASH_DEBUG_MAX 3 ++#define FLASH_DEBUG_LEVEL FLASH_DEBUG_MED ++#define flash_dprintf(level, args...) \ ++ do { \ ++ if (FLASH_DEBUG_LEVEL >= level) \ ++ diag_printf(args); \ ++ } while(0) ++ ++#define CHECK_RUN_TIMES(n) { \ ++ static int count = 0;\ ++ if(++count > n){\ ++ diag_printf("%s: the loop gets the limitation, WRONG!\n", __FUNCTION__);break;} ++ ++typedef int mxc_mmc_check_sdhc_boot_slot(unsigned int port, unsigned int *sdhc_addr); ++ ++#define READ_PORT_FROM_FUSE 50 ++#endif //__MXC_MMC_H__ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nand_parts.inl redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nand_parts.inl +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nand_parts.inl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nand_parts.inl 2010-01-26 17:33:12.962959386 +0000 +@@ -0,0 +1,539 @@ ++#ifndef CYGONCE_DEVS_FLASH_MXC_NAND_PARTS_INL ++#define CYGONCE_DEVS_FLASH_MXC_NAND_PARTS_INL ++//========================================================================== ++// ++// mxc_nfc.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++ { ++ device_id : 0x35ec, // Samsung K9F5608x0C (on EVB SDR memory card) ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 1, ++ row_cycle: 2, ++ page_size : 512, ++ spare_size : 16, ++ pages_per_block : 32, ++ block_size : 0x4000, ++ block_count: 2048, ++ device_size: 0x2000000, ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is fixed at 5th byte in the spare area. This value is not used ++ bi_off : 0, ++ vendor_info: "Samsung K9F5608x0C 8-bit 512B page 32MB", ++ }, ++ { ++ device_id : 0x36ec, // Samsung K9F1208R0B ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 1, ++ row_cycle: 3, ++ page_size : 512, ++ spare_size : 16, ++ pages_per_block : 32, ++ block_size : 0x4000, ++ block_count: 4096, ++ device_size: 0x4000000, ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is fixed at 5th byte in the spare area. This value is not used ++ bi_off : 0, ++ vendor_info: "Samsung K9F1208R0B 8-bit 512B page 64MB", ++ }, ++ { ++ device_id : 0x76ec, // Samsung K9F1208x0B ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 1, ++ row_cycle: 3, ++ page_size : 512, ++ spare_size : 16, ++ pages_per_block : 32, ++ block_size : 0x4000, ++ block_count: 4096, ++ device_size: 0x4000000, ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is fixed at 5th byte in the spare area. This value is not used ++ bi_off : 0, ++ vendor_info: "Samsung K9F1208x0B 8-bit 512B page 64MB", ++ }, ++ { ++ device_id : 0x79ec, // Samsung K9K1G08x0B (MX31 ADS 512B page 8 bit) ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 1, ++ row_cycle: 3, ++ page_size : 512, ++ spare_size : 16, ++ pages_per_block : 32, ++ block_size : 0x4000, ++ block_count: 4096 * 2, ++ device_size: 0x4000000 * 2, ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is fixed at 5th byte in the spare area. This value is not used ++ bi_off : 0, ++ vendor_info: "Samsung K9K1G08x0B 8-bit 512B page 128MB", ++ }, ++ { ++ device_id : 0xf1ec, // Samsung K9F1G08U0A (MX31 ADS 2KB page 8 bit nand) ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 2, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 64, ++ block_size : 64*2*1024, ++ block_count: 1024, ++ device_size: 128*1024*1024, // 128MB device =0x08000000 ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 4096th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 P5 P6 P7 P8 ++ // |0-527|528-1055/1056-1583/1584-2111/2112-2639/2640-3167/3168-3695/3696-4223 | ++ // So the last subpage starts: 3696th byte. 4096th byte is at offset 400. ++ bi_off : 7 * 512 + 400, ++ vendor_info: "Samsung K9F1G08U0A 8-bit 2K page 128MB", ++ }, ++ { ++ device_id : 0xa1ec, // Samsung K9F1G08R0A (2KB page 8 bit nand) ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 2, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 64, ++ block_size : 64*2*1024, ++ block_count: 1024, ++ device_size: 0x08000000, // 128MB device =0x08000000 ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 ++ // 0-527|528-1055/1056-1583/1584-2111 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, // BUF3 offset + 464 ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ vendor_info: "Samsung K9F1G08R0A 8-bit 2K page 128MB", ++ }, ++ { ++ device_id : 0xaaec, // Samsung K9F2G08R0A (2KB page 8 bit nand) ++ device_id2 : 0xFFFF, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 64, ++ block_size : 64*2*1024, ++ block_count: 2048, ++ device_size: 0x10000000, // 256MB device =0x10000000 ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 ++ // 0-527|528-1055/1056-1583/1584-2111 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, // BUF3 offset + 464 ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ vendor_info: "Samsung K9F2G08R0A 8-bit 2K page 256MB", ++ }, ++ { ++ device_id : 0xd5ec, // Samsung K9LAG08U0M (2KB page 2G x 8 bit MLC nand) ++ device_id2 : 0x2555, // interleaved NAND used on MX51 TO 1.0 ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 128, ++ block_size : 128*2*1024, ++ block_count: 8192, ++ device_size: 0x80000000, // 2GB device =0x8000,0000 ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 ++ // 0-527|528-1055/1056-1583/1584-2111 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, // BUF3 offset + 464 ++ options : NAND_BBT_SCANLSTPAGE, ++ vendor_info: "Samsung K9LAG08U0M 8-bit 2K page 2GB MLC", ++ }, ++ { ++ device_id : 0xd3ec, // Samsung K9G8G08U0M (2KB page 1G x 8 bit MLC nand) ++ device_id2 : 0x2514, // default for MX51 ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 128, ++ block_size : 128*2*1024, ++ block_count: 4096, ++ device_size: 0x40000000, ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 ++ // 0-527|528-1055/1056-1583/1584-2111 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, // BUF3 offset + 464 ++ options : NAND_BBT_SCANLSTPAGE, ++ vendor_info: "Samsung K9G8G08U0M 8-bit 2K page 1GB MLC", ++ }, ++ { ++ device_id : 0xd5ec, ++ device_id2 : 0xb614, ++ device_id3 : 0xec74, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 128, ++ block_size : 128*2*1024, ++ block_count: 8192, ++ device_size: 0x80000000, // 2GB device =0x8000,0000 ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ vendor_info: "Samsung K9HCG08U5M 8-bit 2K page 8GB Quad MLC", ++ }, ++ { ++ device_id : 0xd7ec, // Samsung K9LBG08U0M 8-bit 4K page 4GB MLC. - used on MX37 ++ device_id2 : 0xb655, ++ device_id3 : 0xec78, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*8, ++ spare_size : 16*8, ++ pages_per_block : 128, ++ block_size : 128*4*1024, ++ block_count: 8192 / 2, // for now ++ device_size: 0x80000000, // only 2GB supported ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ options : NAND_BBT_SCANLSTPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 4096th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 | 528 | 528 | 528 | 528 | ++ // P1 P2 P3 P4 P5 P6 P7 P8 ++ // |0-527|528-1055/1056-1583/1584-2111/2112-2639/2640-3167/3168-3695/3696-4223 | ++ // So the last subpage starts: 3696th byte. 4096th byte is at offset 400. ++ bi_off : 7 * 512 + 400, ++ vendor_info: "Samsung K9LBG08U0M 8-bit 4K page 4GB MLC. Only 2GB supported.", ++ }, ++ { ++ device_id : 0xD5AD, // Hynix HY27UV08BG5M 8-bit 2K page ?? GB MLC nand ++ device_id2 : 0xA555, ++ device_id3 : 0xAD68, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 128, ++ block_size : 128*2*1024, ++ block_count: 2*2* 2048, ++ device_size: 0x80000000, // 2GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ vendor_info: "Hynix HY27UV08BG5M 8-bit 2K page ?? GB MLC nand", ++ }, ++ { ++ device_id : 0xAD, // Hynix HYD0SQH0MF3(P) 16-bit 2K page 128MB (1Gb) MLC nand ++ device_id2 : 0xB1, ++ device_id3 : 0x80, ++ device_id4 : 0x55, ++ col_cycle: 2, ++ row_cycle: 2, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 64, ++ block_size : 64*2*1024, ++ block_count: 1024, ++ device_size: 0x08000000, // 128MB device =0x0800,0000 ++ port_size : MXC_NAND_16_BIT, ++ type : NAND_MLC, ++ vendor_info: "Hynix HYD0SQH0MF3(P) 16-bit 2K page 128MB MLC nand", ++ }, ++ { ++ // Hynix HY27UG088G 8Gb NAND FLASH 8-bit 2K page 64-bits spare - 64 pages per block SLC nand ++ device_id : 0xDCAD, ++ device_id2 : 0x9510, ++ device_id3 : 0xFF54, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 2*1024, ++ spare_size : 64, ++ pages_per_block : 64, ++ block_size : 2*1024*64, ++ block_count: 8192, ++ device_size: 0x40000000, // 1GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 ++ // P1 P2 P3 P4 ++ // |0-527|528-1055|1056-1583|1584-2112 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, ++ vendor_info: "Hynix HY27UG088G 8Gb NAND FLASH 8-bit 2K page 64-bits spare - 64 pages per block SLC nand", ++ }, ++ { ++ // ST NAND08GW3C2B 8Gb NAND FLASH 8-bit 2K page 64-bits spare - 128 pages per block MLC nand ++ device_id : 0xD320, ++ device_id2 : 0xA514, ++ device_id3 : 0xFF34, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 2*1024, ++ spare_size : 64, ++ pages_per_block : 128, ++ block_size : 2*1024*128, ++ block_count: 4096, ++ device_size: 0x40000000, // 1GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ options : NAND_BBT_SCANLSTPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 2048th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 528 | 528 | 528 | 528 ++ // P1 P2 P3 P4 ++ // |0-527|528-1055|1056-1583|1584-2112 ++ // So the last subpage starts: 1584th byte. 2048th byte is at offset 464. ++ bi_off : 3 * 512 + 464, ++ vendor_info: "ST NAND08GW3C2B 8Gb NAND FLASH 8-bit 2K page 64-bits spare - 128 pages per block MLC nand", ++ }, ++ { ++ // Micron 29F32G08TAA 8-bit 2K page 4GB (32Gb) nand ++ // Even though it is 4GB device, so far we only use 2GB. Will work on it more ++ // once we have the schematic for this MX32 3DS board with Wolfson ++ // Note: this device doesn't work for NAND boot since it requires a ++ // "reset" command issued to the NAND flash which is missing ++ // from our NFC controller on i.MX31/32 and earlier. ++ device_id : 0xD52C, ++ device_id2 : 0xA5D5, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*4, ++ spare_size : 16*4, ++ pages_per_block : 128, ++ block_size : 128*2*1024, ++ block_count: 2 * 2 * 2048, ++ device_size: 0x80000000, // 2GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ vendor_info: "Micron 29F32G08TAA 16-bit 2K page 4GB (32Gb) nand", ++ }, ++ { ++ // Micron MT29F8G08AAA 8-bit 4K page 1GB (8Gb) nand, 218B spare ++ device_id : 0xD32C, ++ device_id2 : 0x2E90, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*8, ++ spare_size : 218, ++ pages_per_block : 64, ++ block_size : 128*2*1024, ++ block_count: 2 * 2048, ++ device_size: 0x40000000, // 2GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCANLSTPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 4096th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 538 | 538 | 538 | 538 | 538 | 538 | 538 | 538 | ++ // P1 P2 P3 P4 P5 P6 P7 P8 ++ // |0-537|538-1075|1076-1613|1614-2151|2152-2689|2690-3227|3228-3765|3766-4303 | ++ // So the last subpage starts: 3696th byte. 4096th byte is at offset 330. ++ bi_off : 7 * 512 + 330, ++ vendor_info: "Micron MT29F8G08AAA 8-bit 4K page 1GB (8Gb) nand, 218B spare", ++ }, ++ { ++ // Micron MT29F32G08QAA 8-bit 4K page 4GB (32Gb) nand, 218B spare ++ device_id : 0xD52C, ++ device_id2 : 0x3E94, ++ device_id3 : 0xFF74, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*8, ++ spare_size : 218, ++ pages_per_block : 128, ++ block_size : 128*8*512, ++ block_count: 4096, ++ device_size: 0x80000000, // 2GB device ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ options : NAND_BBT_SCANLSTPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 4096th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 538 | 538 | 538 | 538 | 538 | 538 | 538 | 538 | ++ // P1 P2 P3 P4 P5 P6 P7 P8 ++ // |0-537|538-1075|1076-1613|1614-2151|2152-2689|2690-3227|3228-3765|3766-4303 | ++ // So the last subpage starts: 3696th byte. 4096th byte is at offset 330. ++ bi_off : 7 * 512 + 330, ++ vendor_info: "Micron MT29F32G08QAA 8-bit 4K page 4GB (32Gb) nand, 218B spare", ++ }, ++ { ++ //ELPIDA EHD013111MA 16bit 2K page(2 plane) 256MB(2Gb) nand, 64b spare ++ device_id : 0xBA20, ++ device_id2 : 0x5510, ++ device_id3 : 0xFFFF, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 2048, ++ spare_size : 64, ++ pages_per_block : 64, ++ block_size : 64*2048, ++ block_count: 2048, ++ device_size: 0x10000000, // 2Gb device ++ port_size : MXC_NAND_16_BIT, ++ type : NAND_SLC, ++ options : NAND_BBT_SCAN1STPAGE | NAND_BBT_SCAN2NDPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ bi_off : 3 * 512 + 464, ++ vendor_info: "ELPIDA EHD013111MA 16bit 4K page(2 plane) 256MB(2Gb) nand, 64b spare", ++ }, ++ { ++ device_id : 0xd7ec, // Samsung K9LBG08UxD 8-bit 4K page 4GB MLC. - used on MX25/35 (newer ones) ++ device_id2 : 0x29d5, ++ device_id3 : 0x4138, ++ device_id4 : 0xFFFF, ++ col_cycle: 2, ++ row_cycle: 3, ++ page_size : 512*8, ++ spare_size : 218, ++ pages_per_block : 128, ++ block_size : 128*4*1024, ++ block_count: 8192 / 2, // for now ++ device_size: 0x80000000, // only 2GB supported ++ port_size : MXC_NAND_8_BIT, ++ type : NAND_MLC, ++ options : NAND_BBT_SCANLSTPAGE, ++ fis_start_addr: 0x100000, // first 1MB reserved for Redboot ++ bbt_blk_max_nr: 4, // reserve 4 blocks for the bad block tables ++ // BI is at 4096th byte out of factory (0-indexed) ++ // our NFC read out data like this: ++ // | 538 | 538 | 538 | 538 | 538 | 538 | 538 | 538 | ++ // P1 P2 P3 P4 P5 P6 P7 P8 ++ // |0-537|538-1075|1076-1613|1614-2151|2152-2689|2690-3227|3228-3765|3766-4303 | ++ // So the last subpage starts: 3696th byte. 4096th byte is at offset 330. ++ bi_off : 7 * 512 + 330, ++ vendor_info: "Samsung K9LBG08UxD 8-bit 4K page 4GB MLC. Only 2GB supported.", ++ }, ++#endif // CYGONCE_DEVS_FLASH_MXC_NAND_PARTS_INL +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nand_specifics.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nand_specifics.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nand_specifics.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nand_specifics.h 2010-01-26 17:33:12.962959386 +0000 +@@ -0,0 +1,61 @@ ++#ifndef CYGONCE_DEVS_FLASH_MXC_NAND_SPECIFICS_H ++#define CYGONCE_DEVS_FLASH_MXC_NAND_SPECIFICS_H ++//========================================================================== ++// ++// mxc_nand_specifics.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#define CYGNUM_FLASH_INTERLEAVE 1 ++#define CYGNUM_FLASH_SERIES 1 ++#define CYGNUM_FLASH_WIDTH 8 ++#define CYGNUM_FLASH_BASE 0 ++#define CYGNUM_FLASH_BLANK 1 ++ ++#endif // CYGONCE_DEVS_FLASH_MXC_NAND_SPECIFICS_H +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc.h 2010-01-26 17:33:12.962959386 +0000 +@@ -0,0 +1,295 @@ ++#ifndef _MXC_NFC_H_ ++#define _MXC_NFC_H_ ++//========================================================================== ++// ++// mxc_nfc.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include "mxc_nand_specifics.h" ++ ++ ++#if defined(NFC_V1_1) ++#define PG_2K_DATA_OP_MULTI_CYCLES() false ++#else ++#define PG_2K_DATA_OP_MULTI_CYCLES() true ++#endif ++ ++#define ADDR_INPUT_SIZE 8 ++#define NAND_MAIN_BUF0 (NFC_BASE + 0x000) ++#define NAND_MAIN_BUF1 (NFC_BASE + 0x200) ++#define NAND_MAIN_BUF2 (NFC_BASE + 0x400) ++#define NAND_MAIN_BUF3 (NFC_BASE + 0x600) ++#if defined(NFC_V1_1) ++#define NAND_MAIN_BUF4 (NFC_BASE + 0x800) ++#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00) ++#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00) ++#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00) ++#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000) ++#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040) ++#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080) ++#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0) ++#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100) ++#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140) ++#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180) ++#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0) ++#else ++#define NAND_SPAR_BUF0 (NFC_BASE + 0x800) ++#define NAND_SPAR_BUF1 (NFC_BASE + 0x810) ++#define NAND_SPAR_BUF2 (NFC_BASE + 0x820) ++#define NAND_SPAR_BUF3 (NFC_BASE + 0x830) ++#define NAND_RESERVED (NFC_BASE + 0x840) ++#endif ++ ++#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00) ++#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04) ++#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06) ++#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08) ++#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A) ++#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C) ++#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E) ++#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10) ++#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12) ++#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18) ++#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A) ++#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C) ++#if defined(NFC_V1_1) ++#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x20) ++#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x22) ++#define UNLOCK_START_BLK_ADD1_REG (NAND_REG_BASE + 0x24) ++#define UNLOCK_END_BLK_ADD1_REG (NAND_REG_BASE + 0x26) ++#define UNLOCK_START_BLK_ADD2_REG (NAND_REG_BASE + 0x28) ++#define UNLOCK_END_BLK_ADD2_REG (NAND_REG_BASE + 0x2A) ++#define UNLOCK_START_BLK_ADD3_REG (NAND_REG_BASE + 0x2C) ++#define UNLOCK_END_BLK_ADD3_REG (NAND_REG_BASE + 0x2E) ++#else ++#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14) ++#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16) ++#endif ++ ++#define NUM_OF_CS_LINES 1 ++#define NFC_BUFSIZE 0 ++ ++enum nfc_internal_buf { ++ RAM_BUF_0, ++ RAM_BUF_1, ++ RAM_BUF_2, ++ RAM_BUF_3, ++ RAM_BUF_4, ++ RAM_BUF_5, ++ RAM_BUF_6, ++ RAM_BUF_7, ++}; ++ ++enum nfc_output_mode { ++ FDO_PAGE_SPARE = 0x0008, ++ FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08 ++ FDO_FLASH_ID = 0x0010, ++ FDO_FLASH_STATUS = 0x0020, ++}; ++ ++#define wait_for_auto_prog_done() ++ ++// Polls the NANDFC to wait for an operation to complete ++#define wait_op_done() \ ++ do { \ ++ volatile int mxc_nfc_wait_loop; \ ++ while ((readw(NAND_FLASH_CONFIG2_REG) & NAND_FLASH_CONFIG2_INT_DONE) == 0) \ ++ {for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++);} \ ++ } while (0) ++ ++/*! ++ * NAND flash data output operation (reading data from NAND flash) ++ * @param buf_no internal ram buffer number that will contain data ++ * to be outputted from the NAND flash after operation done ++ * @param mode one of the mode defined in enum nfc_output_mode ++ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled ++ */ ++static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode, ++ int ecc_en) ++{ ++ u16 config1 = (ecc_en != 0) ? NAND_FLASH_CONFIG1_ECC_EN : 0; ++ ++ config1 |= readw(NAND_FLASH_CONFIG1_REG); ++ ++ if (mode == FDO_SPARE_ONLY) { ++ config1 |= NAND_FLASH_CONFIG1_SP_EN; ++ } ++ ++ writew(config1, NAND_FLASH_CONFIG1_REG); ++ writew(buf_no, RAM_BUFFER_ADDRESS_REG); ++ writew(mode & 0xFF, NAND_FLASH_CONFIG2_REG); ++ wait_op_done(); ++} ++ ++static void NFC_CMD_INPUT(u32 cmd) ++{ ++ writew(cmd, NAND_FLASH_CMD_REG); ++ writew(NAND_FLASH_CONFIG2_FCMD_EN, NAND_FLASH_CONFIG2_REG); ++ wait_op_done(); ++} ++ ++static u16 NFC_STATUS_READ(void) ++{ ++ u16 flash_status; ++ u16 saved = readw(NAND_MAIN_BUF0); ++ ++ NFC_CMD_INPUT(FLASH_Status); ++ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_STATUS, 1); ++ flash_status = readw(NAND_MAIN_BUF0) & 0x00FF; ++ ++ // restore ++ writew(saved, NAND_MAIN_BUF0); ++ ++ return flash_status; ++} ++ ++/*! ++ * NAND flash data input operation (writing data to NAND flash) ++ * @param buf_no internal ram buffer number containing data to be ++ * written into the NAND flash ++ * @param area NFC_SPARE_ONLY or NFC_MAIN_ONLY, ++ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled ++ */ ++static void NFC_DATA_INPUT(enum nfc_internal_buf buf_no, enum nfc_page_area area, ++ int ecc_en) ++{ ++ u16 config1 = (ecc_en != 0) ? NAND_FLASH_CONFIG1_ECC_EN : 0; ++ ++ config1 |= readw(NAND_FLASH_CONFIG1_REG); ++ ++ if (area == NFC_SPARE_ONLY) { ++ config1 |= NAND_FLASH_CONFIG1_SP_EN; ++ } ++ ++ writew(config1, NAND_FLASH_CONFIG1_REG); ++ writew(buf_no, RAM_BUFFER_ADDRESS_REG); ++ ++ // start operation ++ writew(NAND_FLASH_CONFIG2_FDI_EN, NAND_FLASH_CONFIG2_REG); ++ wait_op_done(); ++} ++ ++static void NFC_DATA_INPUT_2k(enum nfc_internal_buf buf_no) ++{ ++ writew(buf_no, RAM_BUFFER_ADDRESS_REG); ++ writew(NAND_FLASH_CONFIG2_FDI_EN, NAND_FLASH_CONFIG2_REG); ++ wait_op_done(); ++} ++ ++/*! ++ * The NFC has to be preset before performing any operation ++ */ ++static void NFC_PRESET(u32 max_block_count) ++{ ++ // Unlock the internal RAM buffer ++ writew(NFC_CONFIGURATION_UNLOCKED, NFC_CONFIGURATION_REG); ++ // First Block to be unlocked ++ writew(0, UNLOCK_START_BLK_ADD_REG); ++ // Last Unlock Block ++ writew(max_block_count, UNLOCK_END_BLK_ADD_REG); ++ // Unlock Block Command ++ writew(NF_WR_PROT_UNLOCK, NF_WR_PROT_REG); ++} ++ ++static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line) ++{ ++ // not needed. ++} ++ ++/*! ++ * Issue the address input operation ++ * @param addr the address for the address input operation ++ */ ++static void NFC_ADDR_INPUT(u32 addr) ++{ ++ if (nfc_debug) { ++ diag_printf("add = 0x%x, at 0x%x\n", ++ addr & ((1 << ADDR_INPUT_SIZE) - 1), NAND_FLASH_ADD_REG); ++ diag_printf("NAND_FLASH_CONFIG2_REG=%x\n", NAND_FLASH_CONFIG2_REG); ++ } ++ writew(addr & ((1 << ADDR_INPUT_SIZE) - 1), NAND_FLASH_ADD_REG); ++ writew(NAND_FLASH_CONFIG2_FADD_EN, NAND_FLASH_CONFIG2_REG); ++ wait_op_done(); ++} ++ ++#if defined(NFC_V1_1) ++#define NFC_ARCH_INIT() \ ++ { \ ++ unsigned int tmp, reg; \ ++ tmp = flash_dev_info->page_size / 512; \ ++ if(flash_dev_info->spare_size) {\ ++ writew((flash_dev_info->spare_size>>1), \ ++ ECC_RSLT_SPARE_AREA_REG);\ ++ } \ ++ writew(0x2, NFC_CONFIGURATION_REG);\ ++ reg = readw(NAND_FLASH_CONFIG1_REG)| 0x800; \ ++ if((flash_dev_info->spare_size / tmp) > 16) \ ++ reg &= ~1; \ ++ else \ ++ reg |= 1; \ ++ writew(reg, NAND_FLASH_CONFIG1_REG); \ ++ } ++#else ++#define NFC_ARCH_INIT() ++#endif /*NFC_V1_1*/ ++ ++#define NAND_ADD0_REG 0xDEADDAED ++#define NAND_ADD8_REG 0xDEADDAED ++#define NAND_CMD_REG 0xDEADDAED ++#define NAND_LAUNCH_AUTO_PROG 0xDEADDAED ++#define NAND_STATUS_SUM_REG 0xDEADDAED ++#define NAND_LAUNCH_AUTO_READ 0xDEADDAED ++#define NAND_LAUNCH_AUTO_ERASE 0xDEADDAED ++#define NFC_IPC_REG 0xDEADDAED ++#define NFC_IPC_INT 0xDEADDAED ++#define NFC_IPC_RB_B 0xDEADDAED ++ ++#endif // _MXC_NFC_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v2.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v2.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v2.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v2.h 2010-01-26 17:33:12.972961386 +0000 +@@ -0,0 +1,272 @@ ++#ifndef _MXC_NFC_V2_H_ ++#define _MXC_NFC_V2_H_ ++//========================================================================== ++// ++// mxc_nfc_v2.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include "mxc_nand_specifics.h" ++ ++#define PG_2K_DATA_OP_MULTI_CYCLES() false ++ ++//---------------------------------------------------------------------------- ++// Common device details. ++#define NAND_MAIN_BUF0 (NFC_BASE + 0x000) ++#define NAND_MAIN_BUF1 (NFC_BASE + 0x200) ++#define NAND_MAIN_BUF2 (NFC_BASE + 0x400) ++#define NAND_MAIN_BUF3 (NFC_BASE + 0x600) ++#if defined (NFC_V2_0) ++#define NAND_SPAR_BUF0 (NFC_BASE + 0x800) ++#define NAND_SPAR_BUF1 (NFC_BASE + 0x810) ++#define NAND_SPAR_BUF2 (NFC_BASE + 0x820) ++#define NAND_SPAR_BUF3 (NFC_BASE + 0x830) ++#define NAND_RESERVED (NFC_BASE + 0x840) ++#elif defined (NFC_V2_1) ++#define NAND_MAIN_BUF4 (NFC_BASE + 0x800) ++#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00) ++#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00) ++#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00) ++#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000) ++#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040) ++#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080) ++#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0) ++#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100) ++#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140) ++#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180) ++#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0) ++#else ++#error NOT supported ++#endif ++ ++#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08) ++#define NUM_OF_CS_LINES 1 ++#define NFC_BUFSIZE 0 ++ ++enum nfc_internal_buf { ++ RAM_BUF_0 = 0x0 << 4, ++ RAM_BUF_1 = 0x1 << 4, ++ RAM_BUF_2 = 0x2 << 4, ++ RAM_BUF_3 = 0x3 << 4, ++ RAM_BUF_4 = 0x4 << 4, ++ RAM_BUF_5 = 0x5 << 4, ++ RAM_BUF_6 = 0x6 << 4, ++ RAM_BUF_7 = 0x7 << 4, ++}; ++ ++enum nfc_output_mode { ++ FDO_PAGE_SPARE = 0x0008, ++ FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08 ++ FDO_FLASH_ID = 0x0010, ++ FDO_FLASH_STATUS = 0x0020, ++}; ++ ++#define wait_for_auto_prog_done() ++ ++// Polls the NANDFC to wait for an operation to complete ++#define wait_op_done() \ ++ do { \ ++ while ((readl(NFC_IPC_REG) & NFC_IPC_INT) == 0) \ ++ {} \ ++ write_nfc_ip_reg(0, NFC_IPC_REG); \ ++ } while (0) ++ ++static void write_nfc_ip_reg(u32 val, u32 reg) ++{ ++ writel(NFC_IPC_CREQ, NFC_IPC_REG); ++ while((readl(NFC_IPC_REG) & NFC_IPC_CACK) == 0); ++ ++ writel(val, reg); ++ writel(0, NFC_IPC_REG); ++} ++ ++/*! ++ * NAND flash data output operation (reading data from NAND flash) ++ * @param buf_no internal ram buffer number that will contain data ++ * to be outputted from the NAND flash after operation done ++ * @param mode one of the mode defined in enum nfc_output_mode ++ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled ++ */ ++static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode, ++ int ecc_en) ++{ ++ u32 v = readl(NFC_FLASH_CONFIG2_REG); ++ ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) { ++ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) { ++ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ ++ v = readl(NAND_CONFIGURATION1_REG); ++ ++ if (mode == FDO_SPARE_ONLY) { ++ v = (v & ~0x31) | buf_no | NAND_CONFIGURATION1_SP_EN; ++ } else { ++ v = (v & ~0x31) | buf_no; ++ } ++ ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ writel(mode & 0xFF, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++static void NFC_CMD_INPUT(u32 cmd) ++{ ++ writel(cmd & 0xFFFF, NAND_ADD_CMD_REG); ++ writel(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++static u16 NFC_STATUS_READ(void) ++{ ++ u16 flash_status; ++ u16 saved = readw(NAND_MAIN_BUF0); ++ ++ NFC_CMD_INPUT(FLASH_Status); ++ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_STATUS, 1); ++ flash_status = readw(NAND_MAIN_BUF0) & 0x00FF; ++ ++ // restore ++ writew(saved, NAND_MAIN_BUF0); ++ ++ return flash_status; ++} ++ ++/*! ++ * NAND flash data input operation (writing data to NAND flash) ++ * @param buf_no internal ram buffer number containing data to be ++ * written into the NAND flash ++ * @param area NFC_SPARE_ONLY or NFC_MAIN_ONLY, ++ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled ++ */ ++static void NFC_DATA_INPUT(enum nfc_internal_buf buf_no, enum nfc_page_area area, ++ int ecc_en) ++{ ++ u32 v = readl(NFC_FLASH_CONFIG2_REG); ++ ++ // setup config2 register for ECC enable or not ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) { ++ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) { ++ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ ++ // setup config1 register for ram buffer number, spare-only or not ++ v = readl(NAND_CONFIGURATION1_REG); ++ ++ if (area == NFC_SPARE_ONLY) { ++ v = (v & ~0x31) | buf_no | NAND_CONFIGURATION1_SP_EN; ++ } else { ++ v = (v & ~0x31) | buf_no; ++ } ++ ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ // start operation ++ writel(NAND_LAUNCH_FDI, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++static void NFC_DATA_INPUT_2k(enum nfc_internal_buf buf_no) ++{ ++ u32 v; ++ ++ // setup config1 register for ram buffer number, spare-only or not ++ v = readl(NAND_CONFIGURATION1_REG); ++ v = (v & ~0x30) | buf_no; ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ // start operation ++ writel(NAND_LAUNCH_FDI, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++/*! ++ * The NFC has to be preset before performing any operation ++ */ ++static void NFC_PRESET(u32 max_block_count) ++{ ++ // not needed. It is done in plf_hardware_init() ++} ++ ++static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line) ++{ ++ // not needed. ++} ++ ++/*! ++ * Issue the address input operation ++ * @param addr the address for the address input operation ++ */ ++static void NFC_ADDR_INPUT(u32 addr) ++{ ++ if (nfc_debug) { ++ diag_printf("add = 0x%x, at 0x%x\n", ++ (addr & 0xFF) << 16, NAND_ADD_CMD_REG); ++ diag_printf("NAND_LAUNCH_FADD=%x, NAND_LAUNCH_REG=%x\n", NAND_LAUNCH_FADD, NAND_LAUNCH_REG); ++ } ++ writel((addr & 0xFF) << 16, NAND_ADD_CMD_REG); ++ writel(NAND_LAUNCH_FADD, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++#define NFC_ARCH_INIT() ++#define NAND_ADD0_REG 0xDEADDAED ++#define NAND_ADD8_REG 0xDEADDAED ++#define NAND_CMD_REG 0xDEADDAED ++#define NAND_LAUNCH_AUTO_PROG 0xDEADDAED ++#define NAND_STATUS_SUM_REG 0xDEADDAED ++#define NAND_LAUNCH_AUTO_READ 0xDEADDAED ++#define NAND_LAUNCH_AUTO_ERASE 0xDEADDAED ++#endif // _MXC_NFC_V2_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v3.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v3.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v3.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxc_nfc_v3.h 2010-01-26 17:33:12.972961386 +0000 +@@ -0,0 +1,325 @@ ++#ifndef _MXC_NFC_V3_H_ ++#define _MXC_NFC_V3_H_ ++//========================================================================== ++// ++// mxc_nfc_v3.h ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2008-06-02 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include "mxc_nand_specifics.h" ++ ++#define PG_2K_DATA_OP_MULTI_CYCLES() false ++#define ADDR_INPUT_SIZE 8 ++ ++#define NAND_MAIN_BUF0 (NFC_BASE + 0x000) ++#define NAND_MAIN_BUF1 (NFC_BASE + 0x200) ++#define NAND_MAIN_BUF2 (NFC_BASE + 0x400) ++#define NAND_MAIN_BUF3 (NFC_BASE + 0x600) ++#define NAND_MAIN_BUF4 (NFC_BASE + 0x800) ++#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00) ++#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00) ++#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00) ++#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000) ++#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040) ++#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080) ++#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0) ++#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100) ++#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140) ++#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180) ++#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0) ++ ++// The following defines are not used. Just for compilation purpose ++#define ECC_STATUS_RESULT_REG 0xDEADFFFF ++#define NFC_DATA_INPUT(buf_no, earea, en) ++#define NFC_DATA_INPUT_2k(buf_no) ++// dummy function as it is not needed for automatic operations ++#define NFC_ADDR_INPUT(addr) ++#define NFC_ARCH_INIT() ++#define NUM_OF_CS_LINES 8 ++#define NFC_BUFSIZE 4096 ++ ++enum nfc_internal_buf { ++ RAM_BUF_0 = 0x0 << 4, ++ RAM_BUF_1 = 0x1 << 4, ++ RAM_BUF_2 = 0x2 << 4, ++ RAM_BUF_3 = 0x3 << 4, ++ RAM_BUF_4 = 0x4 << 4, ++ RAM_BUF_5 = 0x5 << 4, ++ RAM_BUF_6 = 0x6 << 4, ++ RAM_BUF_7 = 0x7 << 4, ++}; ++ ++enum nfc_output_mode { ++ FDO_PAGE_SPARE = 0x0008, ++ FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08 ++ FDO_FLASH_ID = 0x0010, ++ FDO_FLASH_STATUS = 0x0020, ++}; ++ ++#define wait_for_auto_prog_done() \ ++ do { \ ++ while ((readl(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) \ ++ {} \ ++ write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \ ++ } while (0) ++ ++// Polls the NANDFC to wait for an operation to complete ++#define wait_op_done() \ ++ do { \ ++ while ((readl(NFC_IPC_REG) & NFC_IPC_INT) == 0) \ ++ {} \ ++ write_nfc_ip_reg(0, NFC_IPC_REG); \ ++ } while (0) ++ ++static void write_nfc_ip_reg(u32 val, u32 reg) ++{ ++ writel(NFC_IPC_CREQ, NFC_IPC_REG); ++ while((readl(NFC_IPC_REG) & NFC_IPC_CACK) == 0); ++ ++ writel(val, reg); ++ writel((readl(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG); ++} ++ ++/*! ++ * NAND flash data output operation (reading data from NAND flash) ++ * @param buf_no internal ram buffer number that will contain data ++ * to be outputted from the NAND flash after operation done ++ * @param mode one of the mode defined in enum nfc_output_mode ++ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled ++ */ ++static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode, ++ int ecc_en) ++{ ++ u32 v = readl(NFC_FLASH_CONFIG2_REG); ++ ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) { ++ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) { ++ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG); ++ } ++ ++ v = readl(NAND_CONFIGURATION1_REG); ++ ++ if (mode == FDO_SPARE_ONLY) { ++ v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN; ++ } else { ++ v = (v & ~0x71) | buf_no; ++ } ++ ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ writel(mode & 0xFF, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++static void NFC_CMD_INPUT(u32 cmd) ++{ ++ writel(cmd & 0xFFFF, NAND_CMD_REG); ++ writel(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG); ++ wait_op_done(); ++} ++ ++static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line) ++{ ++ u32 v; ++ ++ v = readl(NAND_CONFIGURATION1_REG) & (~0x7071); ++ v |= (cs_line << 12); ++ writel(v, NAND_CONFIGURATION1_REG); ++} ++ ++static u16 NFC_STATUS_READ(void) ++{ ++ u32 status; ++ u16 status_sum = 0; ++ int i; ++ ++#ifdef IMX51_TO_2 ++ write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_INT), NFC_IPC_REG); ++ /* Wait till NAND is not busy */ ++ do { ++ writel(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG); ++ wait_op_done(); ++ status = (readl(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16; ++ } while ((status & 0x40) == 0); // make sure I/O 6 == 1 ++ return readl(NAND_STATUS_SUM_REG); ++#else ++ /* Cannot rely on STATUS_SUM register due to errata */ ++ for (i = 0; i < num_of_nand_chips; i++) { ++ NFC_SET_NFC_ACTIVE_CS(i); ++ do { ++ writel(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG); ++ status = (readl(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16; ++ } while ((status & 0x40) == 0); // make sure I/O 6 == 1 ++ /* Get Pass/Fail status */ ++ status = (readl(NAND_CONFIGURATION1_REG) >> 16) & 0x1; ++ status_sum |= (status << i); ++ } ++ return status_sum; ++#endif ++} ++ ++/* This function uses a global variable for the page size. It shouldn't be a big ++ * problem since we don't expect mixed page size nand flash parts on the same IC. ++ * Note for address 0, it will always be correct regardless the page size. So for ++ * ID read, it doesn't need to have the correct page size global variable first. ++ */ ++static void start_nfc_addr_ops(u32 ops, u32 pg_no, u16 pg_off, u32 is_erase, u32 cs_line, u32 num_of_chips) ++{ ++ u32 add0, add8, page_number; ++ int num_of_bits[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4}; ++ ++ if (ops == FLASH_Read_ID) { ++ // issue addr cycle ++ writel(0x0, NAND_ADD0_REG + (4 * cs_line)); ++ writel(NAND_LAUNCH_FADD, NAND_LAUNCH_REG); ++ wait_op_done(); ++ return; ++ } ++ ++ if (num_of_chips > 1) { ++ page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1)); ++ } else { ++ page_number = pg_no; ++ } ++ if (is_erase) { ++ add0 = page_number; ++ add8 = 0; ++ } else { ++ // for both read and write ++ if (g_is_2k_page || g_is_4k_page) { ++ // the first two addr cycles are for column addr. Page number starts ++ // from the 3rd addr cycle. ++ add0 = pg_off | (page_number << 16); ++ add8 = page_number >> 16; ++ } else { ++ diag_printf("too bad, die\n"); ++ asm("1: b 1b"); ++ // For 512B page, the first addr cycle is for column addr. Page number ++ // starts from the 2nd addr cycle. ++ add0 = (pg_off & 0xFF) | (page_number << 8); ++ add8 = page_number >> 24; ++ } ++ } ++ writel(add0, NAND_ADD0_REG); ++ writel(add8, NAND_ADD8_REG); ++} ++ ++/* ++ * Do a page read at random address ++ * ++ * @param pg_no page number offset from 0 ++ * @param pg_off byte offset within the page ++ * @param ecc_force can force ecc to be off. Otherwise, by default it is on ++ * unless the page offset is non-zero ++ * @param cs_line indicates which NAND of interleaved NAND devices is used ++ * ++ * @return 0 if successful; non-zero otherwise ++ */ ++static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line, u32 num_of_chips) ++{ ++ u32 ecc = NFC_FLASH_CONFIG2_ECC_EN; ++ u32 v, res = 0; ++ ++ // clear the NAND_STATUS_SUM_REG register ++ writel(0, NAND_STATUS_SUM_REG); ++ ++ // the 2nd condition is to test for unaligned page address -- ecc has to be off. ++ if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) { ++ ecc = 0; ++ } ++ ++ // Take care of config1 for RBA and SP_EN ++ v = readl(NAND_CONFIGURATION1_REG) & (~0x71); ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ // For ECC ++ v = readl(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN); ++ // setup config2 register for ECC enable or not ++ write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG); ++ ++ start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, cs_line, num_of_chips); ++ ++ if (g_is_2k_page || g_is_4k_page) { ++ // combine the two commands for 2k/4k page read ++ writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG); ++ } else { ++ // just one command is enough for 512 page ++ writel(FLASH_Read_Mode1, NAND_CMD_REG); ++ } ++ ++ // start auto-read ++ writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG); ++ wait_op_done(); ++ ++ v = readl(NAND_STATUS_SUM_REG); ++ // test for CS0 ECC error from the STATUS_SUM register ++ if ((v & (0x0100 << cs_line)) != 0) { ++ // clear the status ++ writel((0x0100 << cs_line), NAND_STATUS_SUM_REG); ++ diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n", ++ NAND_STATUS_SUM_REG, v); ++ diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG, ++ readl(NAND_ECC_STATUS_RESULT_REG)); ++ res = -1; ++ } ++ return res; ++} ++ ++/*! ++ * The NFC has to be preset before performing any operation ++ */ ++static void NFC_PRESET(u32 max_block_count) ++{ ++ // not needed. It is done in plf_hardware_init() ++} ++ ++#endif // _MXC_NFC_V3_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_core.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_core.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_core.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_core.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,154 @@ ++#ifndef _MXCMCI_CORE_H_ ++#define _MXCMCI_CORE_H_ ++ ++/*================================================================================= ++ ++ Module Name: mxcmci_core.h ++ ++ General Description: Limited Bootloader eSDHC Driver. ++ ++=================================================================================== ++ Copyright: 2004,2005,2006,2007,2008 FREESCALE, INC. ++ All Rights Reserved. This file contains copyrighted material. ++ Use of this file is restricted by the provisions of a ++ Freescale Software License Agreement, which has either ++ accompanied the delivery of this software in shrink wrap ++ form or been expressly executed between the parties. ++ ++ ++Revision History: ++ Modification Tracking ++Author (core ID) Date Number Description of Changes ++------------------------- ------------ ---------- -------------------------- ++Lewis Liu 18-June-2008 ++ ++ ++Portability: Portable to other compilers or platforms. ++ ++====================================================================================================*/ ++ ++#include "mxcmci_mmc.h" ++#include "mxcmci_host.h" ++ ++#define SUCCESS 0 ++#define FAIL 1 ++#define NO_ARG 0 ++#define RCA_SHIFT 16 ++#define ONE 1 ++#define FOUR 4 ++#define EIGHT 8 ++#define TWO_K_SIZE 2048 ++#define MMCSD_READY_TIMEOUT 3000 /* ~(3s / (2 * 48 * 10us)) */ ++#define ESDHC_ACMD41_TIMEOUT 48000 /* 1.5 sec =1500 msec delay for ACMD41 cmd */ ++#define MMCSD_SUPPORT ++ ++#define CURR_CARD_STATE(r) ((cyg_uint32) ((r) & 0x1E00) >> 9) ++ ++/*Defines of CSD data*/ ++#define CSD_STRUCT_MSK 0x00C00000 ++#define CSD_STRUCT_SHIFT 22 ++#define MMC_CSD_SPEC_VERS_MASK 0x003C0000 ++#define MMC_CSD_SPEC_VERS_SHIFT 18 ++ ++extern cyg_uint32 Card_rca; ++extern cyg_uint32 address_mode; ++extern cyg_uint32 MMC_Spec_vers; ++extern card_specific_data csd; /* Global variable for Card Specific Data */ ++extern cyg_uint32 Card_capacity_size; /* Capacity size (C_SIZE) for card*/ ++extern cyg_uint32 CCC; /* Card Command Class */ ++ ++ ++/* Defines the id for each command */ ++enum commands ++{ ++ CMD0= 0, ++ CMD1= 1, ++ CMD2= 2, ++ CMD3= 3, ++ CMD5= 5, ++ CMD6=6, ++ ACMD6= 6, ++ CMD7= 7, ++ CMD8=8, ++ CMD9=9, ++ CMD12 = 12, ++ CMD13 = 13, ++ CMD16 = 16, ++ CMD17 = 17, ++ CMD18 = 18, ++ CMD24 = 24, ++ CMD25 = 25, ++ CMD26 = 26, ++ CMD32 = 32, ++ CMD33 = 33, ++ CMD35 = 35, ++ CMD36 = 36, ++ CMD37 = 37, ++ CMD38 = 38, ++ CMD39 = 39, ++ ACMD41 = 41, ++ CMD43 = 43, ++ ACMD51 = 51, ++ CMD55 = 55, ++ CMD60 = 60, ++ CMD61 = 61, ++ CMD62 = 62, ++}; ++ ++/* Defines for the states of the card*/ ++enum states ++{ ++ IDLE, ++ READY, ++ IDENT, ++ STBY, ++ TRAN, ++ DATA, ++ RCV, ++ PRG, ++ DIS ++}; ++ ++/* Defines for card types */ ++typedef enum ++{ ++ TYPE_NONE, ++ SD_CSD_1_0, ++ SD_CSD_2_0, ++ MMC_CSD_1_0, ++ MMC_CSD_1_1, ++ MMC_CSD_1_2, ++ MMC_UNKNOWN ++}card_type; ++ ++typedef struct ++{ ++ cyg_uint32 cid0; ++ cyg_uint32 cid1; ++ cyg_uint32 cid2; ++ cyg_uint32 cid3; ++}card_ident; ++ ++ ++/* CARD Flash Configuration Parameters Structure */ ++typedef struct { ++ cyg_uint32 length; /* Length of Card data to read */ ++} CARD_FLASH_CFG_PARMS_T; ++ ++/*================================================================================================== ++ ENUMS ++==================================================================================================*/ ++ ++/*================================================================================================== ++ Global Function ++==================================================================================================*/ ++extern cyg_uint32 mxcmci_init (cyg_uint32 bus_width, cyg_uint32 base_address); ++extern cyg_uint32 mxcmci_data_read (cyg_uint32* dest_ptr,cyg_uint32 len,cyg_uint32 offset); ++extern cyg_uint32 mxcmci_software_reset (void); ++extern cyg_uint32 mxcmci_get_cid (void); ++extern cyg_uint32 mxcmci_trans_prepare(void); ++extern void mxcmci_cmd_config (command_t *cmd_config,cyg_uint32 index,cyg_uint32 argument,xfer_type_t transfer,response_format_t format, ++ data_present_select data,crc_check_enable crc,cmdindex_check_enable cmdindex); ++ ++ ++#endif //_MXCMCI_CORE_H_ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_host.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_host.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_host.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_host.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,257 @@ ++#ifndef _MXCMCI_HOST_H_ ++#define _MXCMCI_HOST_H_ ++ ++// ========================================================================== ++// ++// Module Name: mxcmci_host.h ++// ++// General Description: Limited Bootloader eSDHC Driver. ++// ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//==================================================================================================== ++ ++#include ++ ++ ++#define ESDHC_SOFTWARE_RESET 0x01000000 /* RSTA bit of ESDHC system control register*/ ++#define ESDHC_CMD_INHIBIT 0x00000003 /* Command inhibit bits*/ ++#define ESDHC_SOFTWARE_INIT 0x08000000 /* INITA bit of ESDHC system control register */ ++#define ESDHC_LITTLE_ENDIAN_MODE 0x00000020 /* Little Endian mode */ ++#define ESDHC_HW_BIG_ENDIAN_MODE 0x00000010 /* Half Word Big Endian mode */ ++#define ESDHC_BIG_ENDIAN_MODE 0x00000000 /* Big Endian mode */ ++#define ESDHC_ONE_BIT_SUPPORT 0x00000000 /* 1 Bit Mode support */ ++#define ESDHC_FOUR_BIT_SUPPORT 0x00000002 /* 4 Bit Mode support */ ++#define ESDHC_EIGHT_BIT_SUPPORT 0x00000004 /* 8 Bit Mode support */ ++#define ESDHC_CLOCK_ENABLE 0x00000007 /* Clock Enable */ ++#define ESDHC_ENABLE 0x00000008 /* Enable SD */ ++ ++#define ESDHC_FREQ_MASK 0xffff0007 ++#define ESDHC_IDENT_FREQ 0x0000800e /* SDCLKFS 0x08 ; DVS 0xe */ ++#define ESDHC_OPERT_FREQ 0x00000200 /* SDCLKFS 0x02 ; DVS 0x0 */ ++#define ESDHC_INTERRUPT_ENABLE 0x007f0123 /* Enable Interrupts */ ++#define ESDHC_CONFIG_BLOCK 0x00010200 /* 512 byte block size*/ ++#define ESDHC_CLEAR_INTERRUPT 0xffffffff ++ ++#define ESDHC_CONFIG_BLOCK_512 0x00000200 /* 512 byte block size*/ ++#define ESDHC_CONFIG_BLOCK_64 0x00000040 /* 64 byte block size*/ ++#define ESDHC_BLOCK_SHIFT 16 ++ ++#define ESDHC_CLEAR_INTERRUPT 0xffffffff ++#define ESDHC_OPER_TIMEOUT 96 /* 3 msec time out */ ++#define ESDHC_READ_TIMEOUT 3264 /* 102 msec read time out */ ++#define ESDHC_ACMD41_TIMEOUT 48000 /* 1.5 sec =1500 msec delay for ACMD41 cmd */ ++ ++#define ESDHCI_SPACE_AVAILABLE 0x00000400 ++#define ESDHCI_DATA_AVAILABLE 0x00000800 ++ ++/*================================================================================================== ++ DEFINES ++==================================================================================================*/ ++#define DATA_TRANSFER_SHIFT 4 ++#define RESPONSE_FORMAT_SHIFT 16 ++#define DATA_PRESENT_SHIFT 21 ++#define CRC_CHECK_SHIFT 19 ++#define CMD_INDEX_CHECK_SHIFT 20 ++#define CMD_INDEX_SHIFT 24 ++#define BLOCK_COUNT_ENABLE_SHIFT 1 ++#define MULTI_SINGLE_BLOCK_SELECT_SHIFT 5 ++#define BLK_LEN 512 ++#define SWITCH_BLK_LEN 64 ++#define FIFO_SIZE 128 ++#define WRITE_READ_WATER_MARK_LEVEL 0x00200020 ++#define ESDHC3 2 ++#define ESDHC2 1 ++#define ONE 1 ++#define ESDHC1 0 ++/*================================================================================================== ++ ENUS ++==================================================================================================*/ ++#define ESDHC_STATUS_END_CMD_RESP_MSK 0x1 ++#define ESDHC_STATUS_END_CMD_RESP_TIME_MSK 0x00010001 ++#define ESDHC_STATUS_TIME_OUT_RESP_MSK 0x10000 ++#define ESDHC_STATUS_RESP_CRC_ERR_MSK 0x20000 ++#define ESDHC_STATUS_RESP_INDEX_ERR_MSK 0x80000 ++#define ESDHC_STATUS_BUF_READ_RDY_MSK 0x20 ++#define ESDHC_STATUS_BUF_WRITE_RDY_MSK 0x10 ++#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK 0x2 ++#define ESDHC_STATUS_TIME_OUT_READ 0x100000 ++#define ESDHC_STATUS_READ_CRC_ERR_MSK 0x200000 ++ ++#define ESDHC_RESET_CMD_MSK 0x02000000 ++#define ESDHC_RESET_DAT_MSK 0x04000000 ++#define ESDHC_RESET_ALL_MSK 0x01000000 ++ ++typedef enum ++{ ++ WRITE = 0, ++ READ = 1, ++}xfer_type_t; ++ ++typedef enum ++{ ++ RESPONSE_NONE, ++ RESPONSE_136, ++ RESPONSE_48, ++ RESPONSE_48_CHECK_BUSY ++}response_format_t; ++ ++ ++typedef enum ++{ ++ DATA_PRESENT_NONE = 0, ++ DATA_PRESENT = 1 ++}data_present_select; ++ ++typedef enum ++{ ++ DISABLE = 0, ++ ENABLE = 1 ++}crc_check_enable,cmdindex_check_enable,block_count_enable; ++ ++typedef enum ++{ ++ SINGLE = 0, ++ MULTIPLE = 1 ++}multi_single_block_select; ++ ++typedef struct ++{ ++ cyg_uint32 command; ++ cyg_uint32 arg; ++ xfer_type_t data_transfer; ++ response_format_t response_format; ++ data_present_select data_present; ++ crc_check_enable crc_check; ++ cmdindex_check_enable cmdindex_check; ++ block_count_enable block_count_enable_check; ++ multi_single_block_select multi_single_block; ++}command_t; ++ ++typedef struct ++{ ++ response_format_t format; ++ cyg_uint32 cmd_rsp0; ++ cyg_uint32 cmd_rsp1; ++ cyg_uint32 cmd_rsp2; ++ cyg_uint32 cmd_rsp3; ++}command_response_t; ++ ++typedef enum ++{ ++ BIG_ENDIAN, ++ HALF_WORD_BIG_ENDIAN, ++ LITTLE_ENDIAN ++}endian_mode_t; ++ ++typedef enum ++{ ++ OPERATING_FREQ = 20000, /* in kHz */ ++ IDENTIFICATION_FREQ = 400 /* in kHz */ ++}sdhc_freq_t; ++ ++ ++enum esdhc_data_status ++{ ++ ESDHC_DATA_ERR = 3, ++ ESDHC_DATA_OK = 4 ++}; ++ ++enum esdhc_int_cntr_val ++{ ++ ESDHC_INT_CNTR_END_CD_RESP = 0x4, ++ ESDHC_INT_CNTR_BUF_WR_RDY = 0x8 ++}; ++ ++enum esdhc_reset_status ++{ ++ ESDHC_WRONG_RESET = 0, ++ ESDHC_CORRECT_RESET = 1 ++}; ++ ++typedef struct ++{ ++ volatile cyg_uint32 dma_system_address; ++ volatile cyg_uint32 block_attributes; ++ volatile cyg_uint32 command_argument; ++ volatile cyg_uint32 command_transfer_type; ++ volatile cyg_uint32 command_response0; ++ volatile cyg_uint32 command_response1; ++ volatile cyg_uint32 command_response2; ++ volatile cyg_uint32 command_response3; ++ volatile cyg_uint32 data_buffer_access; ++ volatile cyg_uint32 present_state; ++ volatile cyg_uint32 protocol_control; ++ volatile cyg_uint32 system_control; ++ volatile cyg_uint32 interrupt_status; ++ volatile cyg_uint32 interrupt_status_enable; ++ volatile cyg_uint32 interrupt_signal_enable; ++ volatile cyg_uint32 autocmd12_status; ++ volatile cyg_uint32 host_controller_capabilities; ++ volatile cyg_uint32 watermark_level; ++ cyg_uint32 reserved1[2]; ++ volatile cyg_uint32 force_event; ++ volatile cyg_uint32 adma_error_status_register; ++ volatile cyg_uint32 adma_system_address; ++ cyg_uint32 reserved[40]; ++ volatile cyg_uint32 host_controller_version; ++}host_register, *host_register_ptr; ++ ++ ++extern host_register_ptr esdhc_base_pointer; ++//extern cyg_uint32 available_mask; ++ ++extern void host_reset(cyg_uint32 data_transfer_width, cyg_uint32 endian_mode); ++extern void host_cfg_clock(sdhc_freq_t); ++extern void host_read_response(command_response_t *); ++extern cyg_uint32 host_send_cmd(command_t *cmd); ++extern cyg_uint32 host_data_read(cyg_uint32 *,cyg_uint32); ++extern cyg_uint32 host_data_write(cyg_uint32 *,cyg_uint32); ++extern void host_cfg_block(cyg_uint32 blk_len, cyg_uint32 nob); ++extern void host_init(cyg_uint32 base_address); ++extern void esdhc_softreset(cyg_uint32 mask); ++/*================================================================================================*/ ++#endif /* _MXCMCI_HOST_H_ */ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_mmc.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_mmc.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/mxcmci_mmc.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/mxcmci_mmc.h 2010-01-26 17:33:12.952960887 +0000 +@@ -0,0 +1,94 @@ ++#ifndef _MXCMCI_MMC_H_ ++#define _MXCMCI_MMC_H_ ++ ++// ========================================================================== ++// ++// Module Name: mxcmci_mmc.h ++// ++// General Description: Limited Bootloader eSDHC Driver. ++// ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//==================================================================================================== ++ ++ ++#define MMC_OCR_VALUE 0x40FF8000 ++#define MMC_OCR_VALUE_BAK 0x80FFC000 ++#define MMC_OCR_HC_RES 0xC0FF8000 ++#define MMC_OCR_LC_RES 0x80FF8000 ++#define MMC_OCR_VALUE_MASK 0x00FF8000 ++#define BYTE_MODE 0 ++#define SECT_MODE 1 ++#define CARD_BUSY_BIT 0x80000000 ++#define CURR_STATE_SHIFT 9 ++#define MMC_SPEC_VER 0x003C0000 ++#define MMC_SPEC_VER_SHIFT 18 ++#define MMC_R1_SWITCH_ERROR_MASK 0x80 ++#define SWITCH_ERROR_SHIFT 7 ++#define BUS_SIZE_SHIFT 2 ++#define BUS_WIDTH 0x3b700000 ++ ++ ++extern cyg_uint32 mmc_init(cyg_uint32); ++extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32); ++extern cyg_uint32 mmc_data_write (cyg_uint32 *src_ptr,cyg_uint32 length,cyg_uint32 offset); ++extern cyg_uint32 mmc_data_erase (cyg_uint32 offset, cyg_uint32 size); ++extern cyg_uint32 mmc_voltage_validation (void); ++extern cyg_uint32 mmc_get_spec_ver (void); ++extern cyg_uint32 sd_voltage_validation (void); ++extern cyg_uint32 sd_init(cyg_uint32); ++extern cyg_uint32 card_flash_query(void* data); ++ ++typedef struct ++{ ++ cyg_uint32 csd0; ++ cyg_uint32 csd1; ++ cyg_uint32 csd2; ++ cyg_uint32 csd3; ++}card_specific_data; ++ ++#endif /* _MXCMCI_MMC_H_ */ ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/nand_dma.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/nand_dma.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/nand_dma.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/nand_dma.h 2010-01-26 17:33:12.992957885 +0000 +@@ -0,0 +1,722 @@ ++#ifndef _NAND_DMA_H ++#define _NAND_DMA_H ++ ++#include ++ ++ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned COMMAND : 2; ++ unsigned CHAIN : 1; ++ unsigned IRQONCMPLT : 1; ++ unsigned NANDLOCK : 1; ++ unsigned NANDWAIT4READY : 1; ++ unsigned SEMAPHORE : 1; ++ unsigned WAIT4ENDCMD : 1; ++ unsigned HALTONTERMINATE : 1; ++ unsigned RSVD1 : 3; ++ unsigned CMDWORDS : 4; ++ unsigned XFER_COUNT : 16; ++ } B; ++} hw_apbh_chn_cmd_t; ++ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned XFER_COUNT : 16; ++ unsigned ADDRESS_INCREMENT : 1; ++ unsigned ADDRESS : 3; ++ unsigned CS : 2; ++ unsigned LOCK_CS : 1; ++ unsigned WORD_LENGTH : 1; ++ unsigned COMMAND_MODE : 2; ++ unsigned UDMA : 1; ++ unsigned TIMEOUT_IRQ_EN : 1; ++ unsigned DEV_IRQ_EN : 1; ++ unsigned RUN : 1; ++ unsigned CLKGATE : 1; ++ unsigned SFTRST : 1; ++ } B; ++} hw_gpmi_ctrl0_t; ++ ++ ++ ++//! This structure packs the ReadID result into 6 bytes. ++typedef struct _ReadIDCode{ ++ union{ ++ struct { ++ unsigned char btManufacturerCode; ++ unsigned char btDeviceCode; ++ }Device_Code; ++ unsigned short usDeviceID; ++ }DeviceID_Code; ++ // Read ID Byte 3 ++ unsigned int InternalChipNumber : 2; //!> Number of die = (1 << n) ++ unsigned int CellType : 2; //!> Number of bits per memory cell = ( 1 << (n+1) ) ++ unsigned int VendorSpecific0 : 3; ++ unsigned int CacheProgram : 1; //!> 0 == Not supported ++ // Read ID Byte 4 ++ unsigned int PageSize : 2; //!> Page size in bytes = (1 << n) * 1024 ++ unsigned int RedundantAreaSize : 1; //!> Redundant area bytes per 512 data bytes = 8 * (1 << n) ++ unsigned int Reserved0 : 1; ++ unsigned int BlockSize : 2; //!> Block size in bytes = 64 * 1024 * (1 << n) ++ unsigned int Organization : 1; //!> 0 == x8, 1 == x16 ++ unsigned int SamsungHSSerialAccess : 1; //!> 0 == 50/30ns, 1 == 25ns ++ // Read ID Byte 5 ++ unsigned int VendorSpecific1 : 2; ++ unsigned int PlaneNumber : 2; //!> # of planes total (see note below) = (1 << n) ++ unsigned int PlaneSize : 3; //!> # of bytes per plane = 64 * 1024 * 1024 * (1 << n) ++ unsigned int Reserved4 : 1; ++ // Read ID Byte 6 ++ unsigned int Reserved5 : 3; ++ unsigned int ToshibaHighSpeedMode : 1; //!> 0 == Not supported ++ unsigned int Reserved6 : 4; ++} ReadIDCode; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// APBH Definitions ++//////////////////////////////////////////////////////////////////////////////// ++typedef struct _dma_cmd ++{ ++ struct _dma_cmd *pNxt; ++ hw_apbh_chn_cmd_t cmd; ++ void *pBuf; ++ hw_gpmi_ctrl0_t ctrl; ++ hw_gpmi_compare_t cmp; ++} dma_cmd_t; ++ ++ ++/////////////////////////////////////////////////////////////////// ++//! \name APBH DMA Structure Definitions ++//@{ ++////////////////////////////////////////////////////////////////// ++ ++typedef struct _NAND_Timing ++{ ++ unsigned char m_u8DataSetup; ++ unsigned char m_u8DataHold; ++ unsigned char m_u8AddressSetup; ++ unsigned char m_u8DSAMPLE_TIME; ++} NAND_Timing_t; ++ ++ ++//! Define the APBH DMA structure without GPMI transfers. ++typedef struct _apbh_dma_t ++{ ++ struct _apbh_dma_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++} apbh_dma_t; ++ ++//! Define the APBH DMA structure with 1 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi1_t ++{ ++ struct _apbh_dma_gpmi1_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ }apbh_dma_gpmi1_ctrl; ++ unsigned int pio[1]; ++ }apbh_dma_gpmi1_u; ++} apbh_dma_gpmi1_t; ++ ++//! Define the APBH DMA structure with 2 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi2_t ++{ ++ struct _apbh_dma_gpmi2_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ hw_gpmi_compare_t gpmi_compare; ++ }; ++ unsigned int pio[2]; ++ }; ++} apbh_dma_gpmi2_t; ++ ++ ++//! Define the APBH DMA structure with 3 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi3_t ++{ ++ struct _apbh_dma_gpmi1_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ hw_gpmi_compare_t gpmi_compare; ++ hw_gpmi_eccctrl_t gpmi_eccctrl; ++ }apbh_dma_gpmi3_ctrl; ++ unsigned int pio[3]; ++ }apbh_dma_gpmi3_u; ++} apbh_dma_gpmi3_t; ++ ++//! Define the APBH DMA structure with 4 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi4_t ++{ ++ struct _apbh_dma_gpmi1_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ hw_gpmi_compare_t gpmi_compare; ++ hw_gpmi_eccctrl_t gpmi_eccctrl; ++ hw_gpmi_ecccount_t gpmi_ecccount; ++ }; ++ unsigned int pio[4]; ++ }; ++} apbh_dma_gpmi4_t; ++ ++//! Define the APBH DMA structure with 5 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi5_t ++{ ++ struct _apbh_dma_gpmi1_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ hw_gpmi_compare_t gpmi_compare; ++ hw_gpmi_eccctrl_t gpmi_eccctrl; ++ hw_gpmi_ecccount_t gpmi_ecccount; ++ hw_gpmi_payload_t gpmi_payload; ++ }; ++ unsigned int pio[5]; ++ }; ++} apbh_dma_gpmi5_t; ++ ++//! Define the APBH DMA structure with 6 GPMI Parameter word writes. ++typedef struct _apbh_dma_gpmi6_t ++{ ++ struct _apbh_dma_gpmi1_t* nxt; ++ hw_apbh_chn_cmd_t cmd; ++ void* bar; ++ union ++ { ++ struct ++ { ++ hw_gpmi_ctrl0_t gpmi_ctrl0; ++ hw_gpmi_compare_t gpmi_compare; ++ hw_gpmi_eccctrl_t gpmi_eccctrl; ++ hw_gpmi_ecccount_t gpmi_ecccount; ++ hw_gpmi_payload_t gpmi_payload; ++ hw_gpmi_auxiliary_t gpmi_auxiliary; ++ }apbh_dma_gpmi6_ctrl; ++ unsigned int pio[6]; ++ }apbh_dma_gpmi6_u; ++} apbh_dma_gpmi6_t; ++ ++//@} ++ ++//////////////////////////////////////////////////////////////////////////////// ++//! \name NAND Addressing Structures ++//////////////////////////////////////////////////////////////////////////////// ++#define MAX_COLUMNS 2 //!< Current NANDs only use 2 bytes for column. ++#define MAX_ROWS 3 //!< Current NANDs use a max of 3 bytes for row. ++ ++//! CLE command plus up to Max Columns and Max Rows. ++#define CLE1_MAX_SIZE MAX_COLUMNS+MAX_ROWS+1 ++ ++//! This structure defines the packed nature of NAND Column bytes. ++typedef struct _NAND_col_t ++{ ++ unsigned char byte1; ++ unsigned char byte2; ++} NAND_col_t; ++ ++//! This structure defines the packed nature of NAND Row bytes. ++typedef struct _NAND_row_t ++{ ++ unsigned char byte1; ++ unsigned char byte2; ++ unsigned char byte3; ++ unsigned char byte4; ++} NAND_row_t; ++ ++//! This structure defines the NAND Address bytes defined as Column and Row. ++typedef struct _NAND_address_t ++{ ++ NAND_col_t col; ++ NAND_row_t row; ++} NAND_address_t; ++ ++//@} ++ ++/////////////////////////////////////////////////////////////////// ++//! \name DMA Chain Structure Definitions ++////////////////////////////////////////////////////////////////// ++ ++//! Number of commands sent for a NAND Device Reset. ++#define NAND_RESET_DEVICE_SIZE 1 ++//! Number of commands sent for a NAND Device Read ID. ++#define NAND_READ_ID_SIZE 2 ++//! Number of commands read for a NAND Device Read ID. ++#define NAND_READ_ID_RESULT_SIZE 6 // Reading 6 bytes back. ++//! Number of commands sent to read NAND Device Status. ++#define NAND_READ_STATUS_SIZE 1 ++//! Number of commands read for a NAND Device Status result. ++#define NAND_READ_STATUS_RESULT_SIZE 1 ++ ++//! \brief DMA Descriptor structure for a NAND Reset transaction. ++//! ++//! This structure defines the DMA chains required to send a Device ++//! Reset command to the NAND. The following chains are required: ++//! Wait for Ready - waits for the device to enter the Ready state. ++//! Sense Ready - Sense if the device is ready, if not branch to error routine. ++//! Transmit Reset Command - Send reset command to the NAND. ++//! Wait for Ready - waits for the device to enter the Ready state. ++//! Sense Ready - Sense if the device is ready, if not branch to error routine. ++typedef struct _NAND_dma_reset_device_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi1_t wait4rdy_dma; ++ apbh_dma_gpmi1_t sense_rdy_dma; ++ apbh_dma_gpmi3_t tx_dma; ++ apbh_dma_gpmi1_t wait_dma; ++ apbh_dma_gpmi1_t sense_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t timeout_dma; ++ ++ // Buffer for Reset Command. ++ unsigned char tx_reset_command_buf[NAND_RESET_DEVICE_SIZE]; ++} NAND_dma_reset_device_t; ++ ++//! \brief DMA Descriptor structure for a NAND Read ID transaction. ++//! ++//! This structure defines the DMA chains required to send a Device ++//! Read ID command to the NAND. The following chains are required: ++//! Transmit Read ID Command - Send Read ID command to the NAND. ++//! Read ID Command - Read ID bytes out of the NAND. ++typedef struct _NAND_dma_read_id_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi1_t wait4rdy_dma; ++ apbh_dma_gpmi1_t sense_rdy_dma; ++ // now get data. ++ apbh_dma_gpmi3_t tx_dma; ++ apbh_dma_gpmi1_t rx_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t timeout_dma; ++ ++ union ++ { ++ // Buffer for Reset Command. ++ unsigned char tx_readid_command_buf[NAND_READ_ID_SIZE]; ++ struct ++ { ++ unsigned char txCLEByte; ++ unsigned char txALEByte; ++ }txCLE_txALE; ++ }dma_read_id_buffer; ++ ++} NAND_dma_read_id_t ; ++ ++typedef struct _NAND_ECC_Params_t ++{ ++ unsigned int u32ECCEngine; //!< ECC8 or BCH ++ unsigned int u32EccType; //!< Type of ECC - 4 or 8 ++ unsigned int m_u32EccBlock0Size; //!< Number of bytes for Block0 - BCH ++ unsigned int m_u32EccBlockNSize; //!< Block size in bytes for all blocks other than Block0 - BCH ++ unsigned int m_u32EccBlock0EccLevel; //!< Ecc level for Block 0 - BCH ++ unsigned int m_u32NumEccBlocksPerPage; //!< Number of blocks per page - BCH ++ unsigned int m_u32MetadataBytes; //!< Metadata size - BCH ++ unsigned int m_u32PageSize; //!< Size of page including redundant area ++ unsigned int m_u32EraseThreshold; //!< To set into BCH_MODE register. ++} NAND_ECC_Params_t; ++ ++//! \brief Seed structure with values required for proper read. ++//! ++//! Dma seed structure for Read Page ++//! Use data from this structure to fill in the DMA chain. ++typedef struct _NAND_read_seed_t ++{ ++ // Number of Column & Row bytes to be sent. ++ unsigned int uiAddressSize; ++ // How many bytes of data do we want to read back? ++ unsigned int uiReadSize; ++ // What is the word size 16 or 8 bits? ++ unsigned int uiWordSize; ++ // How many chunks of 512 bytes should be ECCed? ++ unsigned int uiECCMask; ++ // Enable or Disable ECC ++ bool bEnableHWECC; ++ // nand ecc parameters ++ //unsigned int uiNumChunks; ++ // What is the word size 16 or 8 bits? ++ NAND_ECC_Params_t zNANDEccParams; ++ // buffer for 'tx_cle1_addr_dma' ++ union ++ { ++ // 1 byte CLE, up to 5 bytes of Column & Row. ++ unsigned char tx_cle1_addr_buf[MAX_COLUMNS+MAX_ROWS+1]; ++ struct ++ { ++ unsigned char tx_cle1; ++ union ++ { ++ unsigned char tx_addr[MAX_COLUMNS+MAX_ROWS]; ++ // Type2 array has 2 Columns & 3 Rows. ++ struct ++ { ++ unsigned char bType2Columns[MAX_COLUMNS]; ++ unsigned char bType2Rows[MAX_ROWS]; ++ }tx_cle1_Type2; ++ // Type1 array has 1 Column & up to 3 Rows ++ struct ++ { ++ unsigned char bType1Columns[1]; ++ unsigned char bType1Rows[MAX_ROWS]; ++ }tx_cle1_Type1; ++ }tx_cle1_Columns_Rows; ++ }tx_cle1_addr_Columns_Rows; ++ }tx_cle1_addr_dma_buffer; ++ ++ // buffer for 'tx_cle2_dma' ++ union ++ { ++ unsigned char tx_cle2_buf[1]; ++ struct ++ { ++ unsigned char tx_cle2; ++ }tx_cle2_addr_dma; ++ }tx_cle2_addr_dma_buffer; ++ ++ // Buffer pointer for data ++ void * pDataBuffer; ++ // Buffer pointer for Auxiliary data (Redundant and ECC).. ++ void * pAuxBuffer; ++ ++} NAND_read_seed_t; ++ ++//! \brief DMA Descriptor structure for a NAND Read transaction. ++//! ++//! This structure defines the DMA chains required to send a Device ++//! Read sequence to the NAND. The following chains are required: ++//! Transmit Read Command and Address - Send primary command and address to the NAND. ++//! Transmit Read2 Command - Send second read command to the NAND. ++//! Wait for Ready - waits for the device to enter the Ready state. ++//! Sense Ready - Sense if the device is ready, if not branch to error routine. ++//! Receive Data - Read the data page from the NAND. ++//! Disable ECC - Disable the ECC DMA (flow-through DMA on Encore). ++typedef struct _NAND_dma_read_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi3_t tx_cle1_addr_dma; ++ apbh_dma_gpmi1_t tx_cle2_dma; ++ apbh_dma_gpmi1_t wait_dma; ++ apbh_dma_gpmi1_t sense_dma; ++ apbh_dma_gpmi1_t wait_dma1; ++ apbh_dma_gpmi1_t sense_dma1; ++ apbh_dma_gpmi6_t rx_data_dma; ++ apbh_dma_gpmi3_t rx_wait4done_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t timeout_dma; ++ ++ // Add the DMA Read Seed into the Read DMA structure. ++ NAND_read_seed_t NAND_DMA_Read_Seed; ++ ++} NAND_dma_read_t; ++ ++//! \brief Seed structure with values required for proper read. ++//! ++//! Dma seed structure for Read Page ++//! Use data from this structure to fill in the DMA chain above. ++typedef struct _NandDmaProgSize_t ++{ ++ // Number of Column & Row bytes to be sent. ++ unsigned int uiAddressSize; ++ // How many bytes do we want to write to NAND? ++ unsigned int uiWriteSize; ++ // What is the word size 16 or 8 bits? ++ unsigned int uiWordSize; ++ // buffer for 'tx_cle1_addr_dma' ++} NandDmaProgSize_t; ++ ++//! \brief Seed structure with values required for NAND writes. ++//! ++//! Dma seed structure for Write Page ++//! Use data from this structure to fill in the DMA chain. ++typedef struct _NandDmaProgSeed_t ++{ ++ // Command 1 along with address. ++ union ++ { ++ // 1 byte CLE, up to 4 bytes of Column & Row. ++ unsigned char tx_cle1_addr_buf[MAX_COLUMNS+MAX_ROWS+1]; ++ struct ++ { ++ unsigned char tx_cle1; ++ union ++ { ++ unsigned char tx_addr[MAX_COLUMNS+MAX_ROWS]; ++ // Type2 array has 2 Columns & 2 Rows. ++ struct ++ { ++ unsigned char bType2Columns[MAX_COLUMNS]; ++ unsigned char bType2Rows[MAX_ROWS]; ++ }; ++ // Type1 array has 1 Column & up to 3 Rows ++ struct ++ { ++ unsigned char bType1Columns[1]; ++ unsigned char bType1Rows[MAX_ROWS]; ++ }; ++ }; ++ }; ++ }; ++ ++ // buffer for 'tx_cle2_dma' ++ union ++ { ++ unsigned char tx_cle2_buf[1]; ++ struct ++ { ++ unsigned char tx_cle2; ++ }; ++ }; ++ ++ NandDmaProgSize_t NandSizeVars; ++ ++ // Status variables for testing success of program. ++ unsigned char u8StatusCmd; ++ unsigned short u16Status; ++ unsigned int u32StatusMaskRef; ++ bool bEnableHWECC; ++ NAND_ECC_Params_t zNANDEccParams; ++} NandDmaProgSeed_t; ++ ++//! \brief DMA Descriptor structure for a NAND Program transaction. ++//! ++//! This structure defines the DMA chains required to send a Device ++//! Program sequence to the NAND. The following chains are required: ++//! Transmit Program1 Command and Address - Send primary command and address to the NAND. ++//! Transmit Data - Send the data page to the NAND. ++//! Transmit Program2 Command - Send second program command to the NAND. ++//! Wait for Ready - waits for the device to enter the Ready state. ++//! Sense Ready - Sense if the device is ready, if not branch to error routine. ++//! \todo - It would be best to send a Read Status command and check the result but ++//! this is much lower priority because the ROM will not perform any writes. ++//! \todo - This does not support ECC and is only working on the dillo. ++typedef struct _NAND_dma_program_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi3_t tx_cle1_addr_dma; ++ apbh_dma_gpmi6_t tx_data_dma; ++// apbh_dma_t tx_auxdata_dma; ++ apbh_dma_gpmi3_t tx_cle2_dma; ++ apbh_dma_gpmi1_t wait_dma; ++ apbh_dma_t sense_dma; ++ // CheckStatus. ++ apbh_dma_gpmi3_t statustx_dma; ++ apbh_dma_gpmi2_t statusrx_dma; ++ //apbh_dma_gpmi2_t statcmp_dma; ++ apbh_dma_t statbranch_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t program_failed_dma; ++ ++ // The buffers needed by the DMA. ++ NandDmaProgSeed_t NandProgSeed; ++ ++} NAND_dma_program_t; ++ ++//! \brief Seed structure with values required for NAND writes. ++//! ++//! Dma seed structure for Write Page ++//! Use data from this structure to fill in the DMA chain. ++typedef struct _NAND_dma_block_erase_seed_t ++{ ++ // Number of Block bytes to be sent. ++ unsigned int uiBlockAddressBytes; ++ ++ // buffer for 'tx_cle1_row_dma' ++ union ++ { ++ // CLE + Maximum Block bytes to send. ++ unsigned char tx_cle1_block_buf[MAX_ROWS+1]; ++ struct ++ { ++ unsigned char tx_cle1; ++ unsigned char tx_block[MAX_ROWS]; ++ }; ++ }; ++ ++ // buffer for 'tx_cle2_dma' ++ union ++ { ++ unsigned char tx_cle2_buf[1]; ++ struct ++ { ++ unsigned char tx_cle2; ++ }; ++ }; ++ ++ // Status variables for testing success of erase. ++ unsigned char u8StatusCmd; ++ unsigned short u16Status; ++ unsigned int u32StatusMaskRef; ++} NAND_dma_block_erase_seed_t; ++ ++//! \brief DMA Descriptor structure for a NAND Erase Block transaction. ++//! ++//! This structure defines the DMA chains required to send a Device ++//! Erase sequence to the NAND. The following chains are required: ++//! Transmit Erase1 Command and Address - Send primary command and address to the NAND. ++//! Transmit Erase2 Command - Send second erase command to the NAND. ++//! Wait for Ready - waits for the device to enter the Ready state. ++//! Sense Ready - Sense if the device is ready, if not branch to error routine. ++//! \todo - It would be best to send a Read Status command and check the result but ++//! this is much lower priority because the ROM will not perform any writes. ++typedef struct _NAND_dma_block_erase_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi3_t tx_cle1_row_dma; ++ apbh_dma_gpmi1_t tx_cle2_dma; ++ apbh_dma_gpmi1_t wait_dma; ++ apbh_dma_gpmi1_t sense_dma; ++ ++ // CheckStatus. ++ apbh_dma_gpmi1_t statustx_dma; ++ apbh_dma_gpmi1_t statusrx_dma; ++ //apbh_dma_gpmi2_t statcmp_dma; ++ apbh_dma_t statbranch_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t program_failed_dma; ++ ++ NAND_dma_block_erase_seed_t NandEraseSeed; ++} NAND_dma_block_erase_t; ++ ++// dma chain structure for NAND Read Status. ++typedef struct _NAND_dma_read_status_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi3_t tx_dma; ++ apbh_dma_gpmi1_t rx_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ ++ // Read Status Size. ++ unsigned int uiReadStatusSize; ++ // Read Status Result Size. ++ unsigned int uiReadStatusResultSize; ++ // Command word for Read Status ++ unsigned char tx_cle1; ++ // buffer for resulting Status. ++ unsigned char rx_Result; ++ ++} NAND_dma_read_status_t; ++ ++// dma chain structure for NAND Check Status. ++typedef struct _NAND_dma_check_status_t ++{ ++ // descriptor sequence ++ apbh_dma_gpmi1_t tx_dma; ++ apbh_dma_gpmi2_t cmp_dma; ++ apbh_dma_t branch_dma; ++ ++ // terminator functions ++ apbh_dma_t success_dma; ++ apbh_dma_t timeout_dma; ++ ++ // Read Status Size. ++ unsigned int uiReadStatusSize; ++ // buffer for 'tx_cle1' ++ unsigned char tx_cle1[2]; ++} NAND_dma_check_status_t; ++ ++//@} ++ ++//////////////////////////////////////////////////////////////////////////////// ++// NAND Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Defines the number of microseconds to wait before declaring a timeout. This ++//! should equate to ~12msec. ++#define MAX_TRANSACTION_TIMEOUT 12000 //!< Maximum time for DMA is 12msec ++ ++//! Defines the bit offset of the NAND APBH Channel 0 in the APBH structure. This ++//! value is used to mask the correct NAND channels. ++#define NAND0_APBH_CH 4 //!< Define starting bit for NANDs in APBH. ++ ++//! Define size of metadata in redundant area for 4 bit ECC ++#define NAND_METADATA_SIZE_4BIT 19 ++//! Define size of metadata in redundant area for 8 bit ECC ++#define NAND_METADATA_SIZE_8BIT 65 ++ ++//////////////////////////////////////////////////////////////////////////////// ++// NAND GPMI CTRL0 Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Externs ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Prototypes ++//////////////////////////////////////////////////////////////////////////////// ++ ++void NAND_HAL_Delay(unsigned int usec); ++ ++void rom_nand_hal_BuildResetDma(NAND_dma_reset_device_t* pChain, ++ unsigned int u32NandDeviceNumber); ++ ++void rom_nand_hal_BuildReadIdDma(NAND_dma_read_id_t* pChain, ++ unsigned int u32NandDeviceNumber, void* pReadIDBuffer); ++ ++void rom_nand_hal_BuildReadDma(NAND_dma_read_t* pChain, unsigned int u32NandDeviceNumber, ++ NAND_read_seed_t * pReadSeed); ++ ++void rom_nand_hal_BuildQuickReadDma(NAND_dma_read_t* pChain, ++ unsigned int u32NandDeviceNumber, ++ NAND_read_seed_t * pReadSeed); ++ ++void rom_nand_hal_BuildProgramDma(NAND_dma_program_t* pChain, unsigned int u32NandDeviceNumber, ++ unsigned int u32AddressSize, unsigned int u32DataSize, ++ unsigned int u32EccSize, void* pWriteBuffer, ++ void* pAuxBuffer); ++ ++void rom_nand_hal_BuildEraseDma(NAND_dma_block_erase_t* pChain, ++ unsigned int u32BlockAddressBytes, unsigned int u32NandDeviceNumber); ++ ++void rom_nand_hal_BuildReadStatusDma(NAND_dma_read_status_t* pChain, ++ unsigned int u32NandDeviceNumber, void* pStatusBuffer); ++ ++void rom_nand_hal_BuildCheckStatusDma(NAND_dma_check_status_t* pChain, ++ unsigned int u32NandDeviceNumber, unsigned short u16Mask, unsigned short u16Match); ++ ++//RtStatus_t rom_nand_hal_GetDmaStatus(unsigned int u32NandDeviceNumber, ++// unsigned int u32StartTime, ++// unsigned int u32DmaTimeout); ++ ++ ++#endif // _NAND_DMA_H +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/nand_dma_descriptor.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/nand_dma_descriptor.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/nand_dma_descriptor.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/nand_dma_descriptor.h 2010-01-26 17:33:12.992957885 +0000 +@@ -0,0 +1,2341 @@ ++#ifndef _NAND_DMA_DESCRIPTOR_H ++#define _NAND_DMA_DESCRIPTOR_H ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define REGS_GPMI_BASE 0x8000C000 ++ ++/* ++ * constants & macros for individual HW_APBH_CHn_CMD multi-register bitfields ++ */ ++/* --- Register HW_APBH_CHn_CMD, field XFER_COUNT */ ++ ++#define BP_APBH_CHn_CMD_XFER_COUNT 16 ++#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_APBH_CHn_CMD_XFER_COUNT(v) ((((unsigned int) v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) ++#else ++#define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) ++#endif ++ ++/* --- Register HW_APBH_CHn_CMD, field CMDWORDS */ ++ ++#define BP_APBH_CHn_CMD_CMDWORDS 12 ++#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 ++ ++#define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) ++ ++/* --- Register HW_APBH_CHn_CMD, field HALTONTERMINATE */ ++ ++#define BP_APBH_CHn_CMD_HALTONTERMINATE 8 ++#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 ++ ++#define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & BM_APBH_CHn_CMD_HALTONTERMINATE) ++ ++/* --- Register HW_APBH_CHn_CMD, field WAIT4ENDCMD */ ++ ++#define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 ++#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 ++ ++#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & BM_APBH_CHn_CMD_WAIT4ENDCMD) ++ ++/* --- Register HW_APBH_CHn_CMD, field SEMAPHORE */ ++ ++#define BP_APBH_CHn_CMD_SEMAPHORE 6 ++#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 ++ ++#define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & BM_APBH_CHn_CMD_SEMAPHORE) ++ ++/* --- Register HW_APBH_CHn_CMD, field NANDWAIT4READY */ ++ ++#define BP_APBH_CHn_CMD_NANDWAIT4READY 5 ++#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 ++ ++#define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & BM_APBH_CHn_CMD_NANDWAIT4READY) ++ ++/* --- Register HW_APBH_CHn_CMD, field NANDLOCK */ ++ ++#define BP_APBH_CHn_CMD_NANDLOCK 4 ++#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 ++ ++#define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & BM_APBH_CHn_CMD_NANDLOCK) ++ ++/* --- Register HW_APBH_CHn_CMD, field IRQONCMPLT */ ++ ++#define BP_APBH_CHn_CMD_IRQONCMPLT 3 ++#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 ++ ++#define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & BM_APBH_CHn_CMD_IRQONCMPLT) ++ ++/* --- Register HW_APBH_CHn_CMD, field CHAIN */ ++ ++#define BP_APBH_CHn_CMD_CHAIN 2 ++#define BM_APBH_CHn_CMD_CHAIN 0x00000004 ++ ++#define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & BM_APBH_CHn_CMD_CHAIN) ++ ++/* --- Register HW_APBH_CHn_CMD, field COMMAND */ ++ ++#define BP_APBH_CHn_CMD_COMMAND 0 ++#define BM_APBH_CHn_CMD_COMMAND 0x00000003 ++ ++#define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) ++ ++ ++ ++/* --- Register HW_APBH_CHn_CMD, field CHAIN */ ++ ++#define BP_APBH_CHn_CMD_CHAIN 2 ++#define BM_APBH_CHn_CMD_CHAIN 0x00000004 ++ ++ ++/* --- Register HW_APBH_CHn_CMD, field COMMAND */ ++ ++#define BP_APBH_CHn_CMD_COMMAND 0 ++#define BM_APBH_CHn_CMD_COMMAND 0x00000003 ++ ++ ++// ++// macros for single instance registers ++// ++ ++#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) ++#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) ++#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) ++ ++#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) ++#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) ++#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) ++ ++#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) ++#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym ++ ++#define BF_RD(reg, field) HW_##reg.B.field ++#define BF_WR(reg, field, v) BW_##reg##_##field(v) ++ ++#define BF_CS1(reg, f1, v1) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1))) ++ ++#define BF_CS2(reg, f1, v1, f2, v2) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2))) ++ ++#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3))) ++ ++#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4))) ++ ++#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5))) ++ ++#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6))) ++ ++#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6 | \ ++ BM_##reg##_##f7), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6) | \ ++ BF_##reg##_##f7(v7))) ++ ++#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ ++ (HW_##reg##_CLR(BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6 | \ ++ BM_##reg##_##f7 | \ ++ BM_##reg##_##f8), \ ++ HW_##reg##_SET(BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6) | \ ++ BF_##reg##_##f7(v7) | \ ++ BF_##reg##_##f8(v8))) ++ ++ ++// ++// macros for multiple instance registers ++// ++ ++#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) ++#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) ++#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) ++ ++#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) ++#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) ++#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) ++ ++#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) ++#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym ++ ++#define BF_RDn(reg, n, field) HW_##reg(n).B.field ++#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) ++ ++#define BF_CS1n(reg, n, f1, v1) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) ++ ++#define BF_CS2n(reg, n, f1, v1, f2, v2) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2)))) ++ ++#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3)))) ++ ++#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4)))) ++ ++#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5)))) ++ ++#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6)))) ++ ++#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6 | \ ++ BM_##reg##_##f7)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6) | \ ++ BF_##reg##_##f7(v7)))) ++ ++#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ ++ (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ ++ BM_##reg##_##f2 | \ ++ BM_##reg##_##f3 | \ ++ BM_##reg##_##f4 | \ ++ BM_##reg##_##f5 | \ ++ BM_##reg##_##f6 | \ ++ BM_##reg##_##f7 | \ ++ BM_##reg##_##f8)), \ ++ HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ ++ BF_##reg##_##f2(v2) | \ ++ BF_##reg##_##f3(v3) | \ ++ BF_##reg##_##f4(v4) | \ ++ BF_##reg##_##f5(v5) | \ ++ BF_##reg##_##f6(v6) | \ ++ BF_##reg##_##f7(v7) | \ ++ BF_##reg##_##f8(v8)))) ++ ++#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 ++#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 ++#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 ++#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 ++ ++// Macro/Defines used to create a DMA command word in the chain. ++ ++//! \brief APBH DMA Macro for Wait4Ready command. ++//! ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Wait for Ready before starting next DMA descriptor in chain. ++//! Don't lock the nand while waiting for Ready to go high. ++//! Another descriptor follows this one in the chain. ++//! This DMA has no transfer. ++ ++#define NAND_DMA_WAIT4RDY_CMD \ ++ (BF_APBH_CHn_CMD_CMDWORDS(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_NANDWAIT4READY(1) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++//! \brief GPMI PIO DMA Macro for Wait4Ready command. ++//! ++//! Wait for Ready before sending IRQ interrupt. ++//! Use 8 bit word length (doesn't really matter since no transfer). ++//! Watch u32ChipSelect. ++#define NAND_DMA_WAIT4RDY_PIO(u32ChipSelect) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect)) ++ ++//! \brief APBH DMA Macro for Transmit Data command. ++//! ++//! Transfer TransferSize bytes with DMA. ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Lock the NAND while waiting for this DMA chain to complete. ++//! Decrement semaphore if this is the last part of the chain. ++//! Another descriptor follows this one in the chain. ++//! This DMA is a read from System Memory - write to device. ++ // TGT_3700, TGT_CHIP and others ++#define NAND_DMA_TXDATA_CMD(TransferSize,Semaphore,CommandWords,Wait4End) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(CommandWords) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(Wait4End) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++//! \brief GPMI PIO DMA Macro for Transmit Data command. ++//! ++//! Setup transfer as a write. ++//! Transfer NumBitsInWord bits per DMA cycle. ++//! Lock CS during this transaction. ++//! Select the appropriate chip. ++//! Address lines need to specify Data transfer (0b00) ++//! Transfer TransferSize - NumBitsInWord values. ++#define NAND_DMA_TXDATA_PIO(u32ChipSelect,NumBitsInWord,TransferSize) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(NumBitsInWord) | \ ++ BF_GPMI_CTRL0_LOCK_CS(1) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(TransferSize)) ++ ++//! \brief APBH DMA Macro for Sense command. ++//! ++//! Transfer no Bytes with DMA. ++//! Transfer no Words to PIO. ++//! Don't lock the NAND while waiting for Ready to go high. ++//! Decrement semaphore if this is the last part of the chain. ++//! Another descriptor follows this one in the chain. ++#define NAND_DMA_SENSE_CMD(SenseSemaphore) \ ++ (BF_APBH_CHn_CMD_CMDWORDS(0) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(SenseSemaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE)) ++ ++//! \brief APBH DMA Macro for Read Data command. ++//! ++//! Receive TransferSize bytes with DMA. ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Decrement semaphore if this is the last part of the chain. ++//! Unlock the NAND after this DMA chain completes. ++//! Another descriptor follows this one in the chain. ++//! This DMA is a write to System Memory - read from device. ++#ifdef TGT_DILLO ++#define NAND_DMA_RX_CMD(TransferSize,Semaphore) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, DMA_WRITE)) ++#else ++#define NAND_DMA_RX_CMD_NOECC(TransferSize,CmdWords,Semaphore) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(CmdWords) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, DMA_WRITE)) ++ ++//! \brief APBH DMA Macro for Read Data command with ECC. ++//! ++//! Receive TransferSize bytes with DMA. ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Decrement semaphore if this is the last part of the chain. ++//! Unlock the NAND after this DMA chain completes. ++//! Another descriptor follows this one in the chain. ++//! No DMA transfer here; the ECC8 block becomes the bus master and ++//! performs the memory writes itself instead of the DMA. ++#define NAND_DMA_RX_CMD_ECC(TransferSize,Semaphore) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(6) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(1) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++#endif ++ ++//! \brief APBH DMA Macro for Recieve Data with no ECC command. ++//! ++//! Receive TransferSize bytes with DMA but no ECC. ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Decrement semaphore if this is the last part of the chain. ++//! Unlock the NAND after this DMA chain completes. ++//! Another descriptor follows this one in the chain. ++//! This DMA is a write to System Memory - read from device. ++#define NAND_DMA_RX_NO_ECC_CMD(TransferSize,Semaphore) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, DMA_WRITE)) ++ ++//! \brief GPMI PIO DMA Macro for Receive command. ++//! ++//! Setup transfer as a READ. ++//! Transfer NumBitsInWord bits per DMA cycle. ++//! Select the appropriate chip. ++//! Address lines need to specify Data transfer (0b00) ++//! Transfer TransferSize - NumBitsInWord values. ++#define NAND_DMA_RX_PIO(u32ChipSelect,NumBitsInWord,TransferSize) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(NumBitsInWord) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BF_GPMI_CTRL0_LOCK_CS(0) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(TransferSize)) ++ ++//! \brief APBH DMA Macro for sending NAND Command sequence. ++//! ++//! Transmit TransferSize bytes to DMA. ++//! Transfer one Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Decrement semaphore if this is the last part of the chain. ++//! Lock the NAND until the next chain. ++//! Another descriptor follows this one in the chain. ++//! This DMA is a read from System Memory - write to device. ++#define NAND_DMA_COMMAND_CMD(TransferSize,Semaphore,NandLock,CmdWords) \ ++ (BF_APBH_CHn_CMD_XFER_COUNT(TransferSize) | \ ++ BF_APBH_CHn_CMD_CMDWORDS(CmdWords) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(Semaphore) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(NandLock) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ)) ++ ++//! \brief GPMI PIO DMA Macro when sending a command. ++//! ++//! Setup transfer as a WRITE. ++//! Transfer NumBitsInWord bits per DMA cycle. ++//! Lock CS during and after this transaction. ++//! Select the appropriate chip. ++//! Address lines need to specify Command transfer (0b01) ++//! Increment the Address lines if AddrIncr is set. ++//! Transfer TransferSize - NumBitsInWord values. ++#define NAND_DMA_COMMAND_PIO(u32ChipSelect,TransferSize,AddrInc,AssertCS) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) | \ ++ BF_GPMI_CTRL0_LOCK_CS(AssertCS) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | \ ++ BF_GPMI_CTRL0_ADDRESS_INCREMENT(AddrInc) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(TransferSize)) ++ ++//! \brief GPMI PIO DMA Macro for disabling ECC during this write. ++#define NAND_DMA_ECC_PIO(EnableDisable) \ ++ (BW_GPMI_ECCCTRL_ENABLE_ECC(EnableDisable)) ++ ++//! \brief APBH DMA Macro for Sending NAND Address sequence. ++//! ++//! Setup transfer as a WRITE. ++//! Transfer NumBitsInWord bits per DMA cycle. ++//! Lock CS during and after this transaction. ++//! Select the appropriate chip. ++//! Address lines need to specify Address transfer (0b10) ++//! Transfer TransferSize - NumBitsInWord values. ++#define NAND_DMA_ADDRESS_PIO(u32ChipSelect,TransferSize) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) | \ ++ BF_GPMI_CTRL0_LOCK_CS(1) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_ALE) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(TransferSize)) ++ ++//! \brief APBH DMA Macro for NAND Compare sequence ++//! ++//! Transfer TransferSize Word to PIO. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Lock the NAND until the next chain. ++//! Another descriptor follows this one in the chain. ++//! This DMA has no transfer. ++#define NAND_DMA_COMPARE_CMD(TransferSize) \ ++ (BF_APBH_CHn_CMD_CMDWORDS(TransferSize) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++//! \brief GPMI PIO DMA Macro for NAND Compare sequence ++//! ++//! Setup transfer as a Read and Compare. ++//! Transfer 8 bits per DMA cycle. ++//! Lock CS during and after this transaction. ++//! Select the appropriate chip. ++//! Address lines need to specify Data transfer (0b00) ++//! Transfer TransferSize - 8 Bit values. ++#define NAND_DMA_COMPARE_PIO(u32ChipSelect,TransferSize) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ_AND_COMPARE) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(TransferSize)) ++ ++//! \brief APBH DMA Macro for NAND Dummy transfer sequence ++//! ++//! Dummy Transfer. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Lock the NAND until the next chain. ++//! Another descriptor follows this one in the chain. ++//! This DMA has no transfer. ++#define NAND_DMA_DUMMY_TRANSFER \ ++ (BF_APBH_CHn_CMD_CMDWORDS(0) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++//! \brief GPMI PIO DMA Macro sequence for ECC decode. ++//! ++//! Setup READ transfer ECC Control register. ++//! Setup for ECC Decode, 4 Bit. ++//! Enable the ECC block ++//! The ECC Buffer Mask determines which fields are corrected. ++#define NAND_DMA_ECC_CTRL_PIO(EccBufferMask, decode_encode_size) \ ++ (BW_GPMI_ECCCTRL_ECC_CMD(decode_encode_size) | \ ++ BW_GPMI_ECCCTRL_ENABLE_ECC(BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE) | \ ++ BW_GPMI_ECCCTRL_BUFFER_MASK(EccBufferMask) ) ++ ++//! \brief APBH DMA Macro for Disabling the ECC block sequence ++//! ++//! Disable ECC Block Transfer. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Lock the NAND until the next chain. ++//! Another descriptor follows this one in the chain. ++//! This DMA has no transfer. ++#define NAND_DMA_DISABLE_ECC_TRANSFER \ ++ (BF_APBH_CHn_CMD_CMDWORDS(3) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_NANDWAIT4READY(1) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++//! \brief GPMI PIO DMA Macro sequence for disabling ECC block ++//! ++//! Setup transfer as a READ. ++//! Release CS during and after this transaction. ++//! Select the appropriate chip. ++//! Address lines need to specify Data transfer ++//! Transfer NO data. ++#define NAND_DMA_DISABLE_ECC_PIO(u32ChipSelect) \ ++ (BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | \ ++ BF_GPMI_CTRL0_WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) | \ ++ BF_GPMI_CTRL0_LOCK_CS(0) | \ ++ BF_GPMI_CTRL0_CS(u32ChipSelect) | \ ++ BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | \ ++ BF_GPMI_CTRL0_ADDRESS_INCREMENT(0) | \ ++ BF_GPMI_CTRL0_XFER_COUNT(0)) ++ ++//! \brief APBH DMA Macro for Removing the NAND Lock in APBH. ++//! ++//! Remove NAND Lock. ++//! Wait for DMA to complete before starting next DMA descriptor in chain. ++//! Unlock the NAND to allow another NAND to run. ++//! Another descriptor follows this one in the chain. ++//! This DMA has no transfer. ++#define NAND_DMA_REMOVE_NAND_LOCK \ ++ (BF_APBH_CHn_CMD_CMDWORDS(0) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_NANDWAIT4READY(0) | \ ++ BF_APBH_CHn_CMD_NANDLOCK(0) | \ ++ BF_APBH_CHn_CMD_CHAIN(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER)) ++ ++ ++#define DECR_SEMAPHORE 1 //!< Decrement DMA semaphore this time. ++#define NAND_LOCK 1 //!< Lock the NAND to prevent contention. ++#define ASSERT_CS 1 //!< Assert the Chip Select during this operation. ++#define ECC_ENCODE 1 //!< Perform an ECC Encode during this operation. ++#define ECC_DECODE 0 //!< Perform an ECC Decode during this operation. ++#define ECC_4_BIT 0 //!< Perform a 4 bit ECC operation. ++#define ECC_8_BIT 1 //!< Perform an 8 bit ECC operation. ++ ++ ++ ++/* ++ * constants & macros for entire HW_GPMI_CTRL0 register ++ */ ++#define HW_GPMI_CTRL0_ADDR (REGS_GPMI_BASE + 0x00000000) ++#define HW_GPMI_CTRL0_SET_ADDR (REGS_GPMI_BASE + 0x00000004) ++#define HW_GPMI_CTRL0_CLR_ADDR (REGS_GPMI_BASE + 0x00000008) ++#define HW_GPMI_CTRL0_TOG_ADDR (REGS_GPMI_BASE + 0x0000000C) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_CTRL0 (*(volatile hw_gpmi_ctrl0_t *) HW_GPMI_CTRL0_ADDR) ++#define HW_GPMI_CTRL0_RD() (HW_GPMI_CTRL0.U) ++#define HW_GPMI_CTRL0_WR(v) (HW_GPMI_CTRL0.U = (v)) ++#define HW_GPMI_CTRL0_SET(v) ((*(volatile unsigned int *) HW_GPMI_CTRL0_SET_ADDR) = (v)) ++#define HW_GPMI_CTRL0_CLR(v) ((*(volatile unsigned int *) HW_GPMI_CTRL0_CLR_ADDR) = (v)) ++#define HW_GPMI_CTRL0_TOG(v) ((*(volatile unsigned int *) HW_GPMI_CTRL0_TOG_ADDR) = (v)) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_CTRL0 bitfields ++ */ ++/* --- Register HW_GPMI_CTRL0, field SFTRST */ ++ ++#define BP_GPMI_CTRL0_SFTRST 31 ++#define BM_GPMI_CTRL0_SFTRST 0x80000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_CTRL0_SFTRST(v) ((((unsigned int) v) << 31) & BM_GPMI_CTRL0_SFTRST) ++#else ++#define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & BM_GPMI_CTRL0_SFTRST) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_SFTRST(v) BF_CS1(GPMI_CTRL0, SFTRST, v) ++#endif ++ ++#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 ++#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field CLKGATE */ ++ ++#define BP_GPMI_CTRL0_CLKGATE 30 ++#define BM_GPMI_CTRL0_CLKGATE 0x40000000 ++ ++#define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & BM_GPMI_CTRL0_CLKGATE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_CLKGATE(v) BF_CS1(GPMI_CTRL0, CLKGATE, v) ++#endif ++ ++#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 ++#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field RUN */ ++ ++#define BP_GPMI_CTRL0_RUN 29 ++#define BM_GPMI_CTRL0_RUN 0x20000000 ++ ++#define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & BM_GPMI_CTRL0_RUN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_RUN(v) BF_CS1(GPMI_CTRL0, RUN, v) ++#endif ++ ++#define BV_GPMI_CTRL0_RUN__IDLE 0x0 ++#define BV_GPMI_CTRL0_RUN__BUSY 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field DEV_IRQ_EN */ ++ ++#define BP_GPMI_CTRL0_DEV_IRQ_EN 28 ++#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 ++ ++#define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & BM_GPMI_CTRL0_DEV_IRQ_EN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_DEV_IRQ_EN(v) BF_CS1(GPMI_CTRL0, DEV_IRQ_EN, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL0, field TIMEOUT_IRQ_EN */ ++ ++#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 ++#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000 ++ ++#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & BM_GPMI_CTRL0_TIMEOUT_IRQ_EN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) BF_CS1(GPMI_CTRL0, TIMEOUT_IRQ_EN, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL0, field UDMA */ ++ ++#define BP_GPMI_CTRL0_UDMA 26 ++#define BM_GPMI_CTRL0_UDMA 0x04000000 ++ ++#define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & BM_GPMI_CTRL0_UDMA) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_UDMA(v) BF_CS1(GPMI_CTRL0, UDMA, v) ++#endif ++ ++#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 ++#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field COMMAND_MODE */ ++ ++#define BP_GPMI_CTRL0_COMMAND_MODE 24 ++#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 ++ ++#define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_COMMAND_MODE(v) BF_CS1(GPMI_CTRL0, COMMAND_MODE, v) ++#endif ++ ++#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 ++#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 ++#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 ++#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 ++ ++/* --- Register HW_GPMI_CTRL0, field WORD_LENGTH */ ++ ++#define BP_GPMI_CTRL0_WORD_LENGTH 23 ++#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 ++ ++#define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & BM_GPMI_CTRL0_WORD_LENGTH) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_WORD_LENGTH(v) BF_CS1(GPMI_CTRL0, WORD_LENGTH, v) ++#endif ++ ++#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 ++#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field LOCK_CS */ ++ ++#define BP_GPMI_CTRL0_LOCK_CS 22 ++#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 ++ ++#define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & BM_GPMI_CTRL0_LOCK_CS) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_LOCK_CS(v) BF_CS1(GPMI_CTRL0, LOCK_CS, v) ++#endif ++ ++#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 ++#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field CS */ ++ ++#define BP_GPMI_CTRL0_CS 20 ++#define BM_GPMI_CTRL0_CS 0x00300000 ++ ++#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_CS(v) BF_CS1(GPMI_CTRL0, CS, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL0, field ADDRESS */ ++ ++#define BP_GPMI_CTRL0_ADDRESS 17 ++#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 ++ ++#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_ADDRESS(v) BF_CS1(GPMI_CTRL0, ADDRESS, v) ++#endif ++ ++#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 ++#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 ++#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 ++ ++/* --- Register HW_GPMI_CTRL0, field ADDRESS_INCREMENT */ ++ ++#define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 ++#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 ++ ++#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & BM_GPMI_CTRL0_ADDRESS_INCREMENT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_ADDRESS_INCREMENT(v) BF_CS1(GPMI_CTRL0, ADDRESS_INCREMENT, v) ++#endif ++ ++#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 ++#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 ++ ++/* --- Register HW_GPMI_CTRL0, field XFER_COUNT */ ++ ++#define BP_GPMI_CTRL0_XFER_COUNT 0 ++#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF ++ ++#define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL0_XFER_COUNT(v) (HW_GPMI_CTRL0.B.XFER_COUNT = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_COMPARE - GPMI Compare Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned REFERENCE : 16; ++ unsigned MASK : 16; ++ } B; ++} hw_gpmi_compare_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_COMPARE register ++ */ ++#define HW_GPMI_COMPARE_ADDR (REGS_GPMI_BASE + 0x00000010) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_COMPARE (*(volatile hw_gpmi_compare_t *) HW_GPMI_COMPARE_ADDR) ++#define HW_GPMI_COMPARE_RD() (HW_GPMI_COMPARE.U) ++#define HW_GPMI_COMPARE_WR(v) (HW_GPMI_COMPARE.U = (v)) ++#define HW_GPMI_COMPARE_SET(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() | (v))) ++#define HW_GPMI_COMPARE_CLR(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() & ~(v))) ++#define HW_GPMI_COMPARE_TOG(v) (HW_GPMI_COMPARE_WR(HW_GPMI_COMPARE_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_COMPARE bitfields ++ */ ++/* --- Register HW_GPMI_COMPARE, field MASK */ ++ ++#define BP_GPMI_COMPARE_MASK 16 ++#define BM_GPMI_COMPARE_MASK 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_COMPARE_MASK(v) ((((unsigned int) v) << 16) & BM_GPMI_COMPARE_MASK) ++#else ++#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_COMPARE_MASK(v) (HW_GPMI_COMPARE.B.MASK = (v)) ++#endif ++ ++/* --- Register HW_GPMI_COMPARE, field REFERENCE */ ++ ++#define BP_GPMI_COMPARE_REFERENCE 0 ++#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF ++ ++#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_COMPARE_REFERENCE(v) (HW_GPMI_COMPARE.B.REFERENCE = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_ECCCTRL - GPMI Integrated ECC Control Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned BUFFER_MASK : 9; ++ unsigned RSVD1 : 3; ++ unsigned ENABLE_ECC : 1; ++ unsigned ECC_CMD : 2; ++ unsigned RSVD2 : 1; ++ unsigned HANDLE : 16; ++ } B; ++} hw_gpmi_eccctrl_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_ECCCTRL register ++ */ ++#define HW_GPMI_ECCCTRL_ADDR (REGS_GPMI_BASE + 0x00000020) ++#define HW_GPMI_ECCCTRL_SET_ADDR (REGS_GPMI_BASE + 0x00000024) ++#define HW_GPMI_ECCCTRL_CLR_ADDR (REGS_GPMI_BASE + 0x00000028) ++#define HW_GPMI_ECCCTRL_TOG_ADDR (REGS_GPMI_BASE + 0x0000002C) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_ECCCTRL (*(volatile hw_gpmi_eccctrl_t *) HW_GPMI_ECCCTRL_ADDR) ++#define HW_GPMI_ECCCTRL_RD() (HW_GPMI_ECCCTRL.U) ++#define HW_GPMI_ECCCTRL_WR(v) (HW_GPMI_ECCCTRL.U = (v)) ++#define HW_GPMI_ECCCTRL_SET(v) ((*(volatile unsigned int *) HW_GPMI_ECCCTRL_SET_ADDR) = (v)) ++#define HW_GPMI_ECCCTRL_CLR(v) ((*(volatile unsigned int *) HW_GPMI_ECCCTRL_CLR_ADDR) = (v)) ++#define HW_GPMI_ECCCTRL_TOG(v) ((*(volatile unsigned int *) HW_GPMI_ECCCTRL_TOG_ADDR) = (v)) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_ECCCTRL bitfields ++ */ ++/* --- Register HW_GPMI_ECCCTRL, field HANDLE */ ++ ++#define BP_GPMI_ECCCTRL_HANDLE 16 ++#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_ECCCTRL_HANDLE(v) ((((unsigned int) v) << 16) & BM_GPMI_ECCCTRL_HANDLE) ++#else ++#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_ECCCTRL_HANDLE(v) (HW_GPMI_ECCCTRL.B.HANDLE = (v)) ++#endif ++ ++/* --- Register HW_GPMI_ECCCTRL, field ECC_CMD */ ++ ++#define BP_GPMI_ECCCTRL_ECC_CMD 13 ++#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 ++ ++#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_ECCCTRL_ECC_CMD(v) BF_CS1(GPMI_ECCCTRL, ECC_CMD, v) ++#endif ++ ++#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 ++#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 ++#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 ++#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 ++ ++/* --- Register HW_GPMI_ECCCTRL, field ENABLE_ECC */ ++ ++#define BP_GPMI_ECCCTRL_ENABLE_ECC 12 ++#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 ++ ++#define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & BM_GPMI_ECCCTRL_ENABLE_ECC) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_ECCCTRL_ENABLE_ECC(v) BF_CS1(GPMI_ECCCTRL, ENABLE_ECC, v) ++#endif ++ ++#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 ++#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 ++ ++/* --- Register HW_GPMI_ECCCTRL, field BUFFER_MASK */ ++ ++#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 ++#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF ++ ++#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_ECCCTRL_BUFFER_MASK(v) BF_CS1(GPMI_ECCCTRL, BUFFER_MASK, v) ++#endif ++ ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002 ++#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001 ++ ++ ++ ++/* ++ * HW_GPMI_ECCCOUNT - GPMI Integrated ECC Transfer Count Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned COUNT : 16; ++ unsigned RSVD2 : 16; ++ } B; ++} hw_gpmi_ecccount_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_ECCCOUNT register ++ */ ++#define HW_GPMI_ECCCOUNT_ADDR (REGS_GPMI_BASE + 0x00000030) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_ECCCOUNT (*(volatile hw_gpmi_ecccount_t *) HW_GPMI_ECCCOUNT_ADDR) ++#define HW_GPMI_ECCCOUNT_RD() (HW_GPMI_ECCCOUNT.U) ++#define HW_GPMI_ECCCOUNT_WR(v) (HW_GPMI_ECCCOUNT.U = (v)) ++#define HW_GPMI_ECCCOUNT_SET(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() | (v))) ++#define HW_GPMI_ECCCOUNT_CLR(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() & ~(v))) ++#define HW_GPMI_ECCCOUNT_TOG(v) (HW_GPMI_ECCCOUNT_WR(HW_GPMI_ECCCOUNT_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_ECCCOUNT bitfields ++ */ ++/* --- Register HW_GPMI_ECCCOUNT, field COUNT */ ++ ++#define BP_GPMI_ECCCOUNT_COUNT 0 ++#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF ++ ++#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_ECCCOUNT_COUNT(v) (HW_GPMI_ECCCOUNT.B.COUNT = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_PAYLOAD - GPMI Payload Address Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned RSVD0 : 2; ++ unsigned ADDRESS : 30; ++ } B; ++} hw_gpmi_payload_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_PAYLOAD register ++ */ ++#define HW_GPMI_PAYLOAD_ADDR (REGS_GPMI_BASE + 0x00000040) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_PAYLOAD (*(volatile hw_gpmi_payload_t *) HW_GPMI_PAYLOAD_ADDR) ++#define HW_GPMI_PAYLOAD_RD() (HW_GPMI_PAYLOAD.U) ++#define HW_GPMI_PAYLOAD_WR(v) (HW_GPMI_PAYLOAD.U = (v)) ++#define HW_GPMI_PAYLOAD_SET(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() | (v))) ++#define HW_GPMI_PAYLOAD_CLR(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() & ~(v))) ++#define HW_GPMI_PAYLOAD_TOG(v) (HW_GPMI_PAYLOAD_WR(HW_GPMI_PAYLOAD_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_PAYLOAD bitfields ++ */ ++/* --- Register HW_GPMI_PAYLOAD, field ADDRESS */ ++ ++#define BP_GPMI_PAYLOAD_ADDRESS 2 ++#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_PAYLOAD_ADDRESS(v) ((((unsigned int) v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) ++#else ++#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_PAYLOAD_ADDRESS(v) BF_CS1(GPMI_PAYLOAD, ADDRESS, v) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_AUXILIARY - GPMI Auxiliary Address Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned RSVD0 : 2; ++ unsigned ADDRESS : 30; ++ } B; ++} hw_gpmi_auxiliary_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_AUXILIARY register ++ */ ++#define HW_GPMI_AUXILIARY_ADDR (REGS_GPMI_BASE + 0x00000050) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_AUXILIARY (*(volatile hw_gpmi_auxiliary_t *) HW_GPMI_AUXILIARY_ADDR) ++#define HW_GPMI_AUXILIARY_RD() (HW_GPMI_AUXILIARY.U) ++#define HW_GPMI_AUXILIARY_WR(v) (HW_GPMI_AUXILIARY.U = (v)) ++#define HW_GPMI_AUXILIARY_SET(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() | (v))) ++#define HW_GPMI_AUXILIARY_CLR(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() & ~(v))) ++#define HW_GPMI_AUXILIARY_TOG(v) (HW_GPMI_AUXILIARY_WR(HW_GPMI_AUXILIARY_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_AUXILIARY bitfields ++ */ ++/* --- Register HW_GPMI_AUXILIARY, field ADDRESS */ ++ ++#define BP_GPMI_AUXILIARY_ADDRESS 2 ++#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_AUXILIARY_ADDRESS(v) ((((unsigned int) v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) ++#else ++#define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_AUXILIARY_ADDRESS(v) BF_CS1(GPMI_AUXILIARY, ADDRESS, v) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_CTRL1 - GPMI Control Register 1 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned GPMI_MODE : 1; ++ unsigned CAMERA_MODE : 1; ++ unsigned ATA_IRQRDY_POLARITY : 1; ++ unsigned DEV_RESET : 1; ++ unsigned ABORT_WAIT_FOR_READY0 : 1; ++ unsigned ABORT_WAIT_FOR_READY1 : 1; ++ unsigned ABORT_WAIT_FOR_READY2 : 1; ++ unsigned ABORT_WAIT_FOR_READY3 : 1; ++ unsigned BURST_EN : 1; ++ unsigned TIMEOUT_IRQ : 1; ++ unsigned DEV_IRQ : 1; ++ unsigned DMA2ECC_MODE : 1; ++ unsigned RDN_DELAY : 4; ++ unsigned HALF_PERIOD : 1; ++ unsigned DLL_ENABLE : 1; ++ unsigned BCH_MODE : 1; ++ unsigned GANGED_RDYBUSY : 1; ++ unsigned CE0_SEL : 1; ++ unsigned CE1_SEL : 1; ++ unsigned CE2_SEL : 1; ++ unsigned CE3_SEL : 1; ++ unsigned RSVD2 : 8; ++ } B; ++} hw_gpmi_ctrl1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_CTRL1 register ++ */ ++#define HW_GPMI_CTRL1_ADDR (REGS_GPMI_BASE + 0x00000060) ++#define HW_GPMI_CTRL1_SET_ADDR (REGS_GPMI_BASE + 0x00000064) ++#define HW_GPMI_CTRL1_CLR_ADDR (REGS_GPMI_BASE + 0x00000068) ++#define HW_GPMI_CTRL1_TOG_ADDR (REGS_GPMI_BASE + 0x0000006C) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_CTRL1 (*(volatile hw_gpmi_ctrl1_t *) HW_GPMI_CTRL1_ADDR) ++#define HW_GPMI_CTRL1_RD() (HW_GPMI_CTRL1.U) ++#define HW_GPMI_CTRL1_WR(v) (HW_GPMI_CTRL1.U = (v)) ++#define HW_GPMI_CTRL1_SET(v) ((*(volatile unsigned int *) HW_GPMI_CTRL1_SET_ADDR) = (v)) ++#define HW_GPMI_CTRL1_CLR(v) ((*(volatile unsigned int *) HW_GPMI_CTRL1_CLR_ADDR) = (v)) ++#define HW_GPMI_CTRL1_TOG(v) ((*(volatile unsigned int *) HW_GPMI_CTRL1_TOG_ADDR) = (v)) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_CTRL1 bitfields ++ */ ++/* --- Register HW_GPMI_CTRL1, field CE3_SEL */ ++ ++#define BP_GPMI_CTRL1_CE3_SEL 23 ++#define BM_GPMI_CTRL1_CE3_SEL 0x00800000 ++ ++#define BF_GPMI_CTRL1_CE3_SEL(v) (((v) << 23) & BM_GPMI_CTRL1_CE3_SEL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_CE3_SEL(v) BF_CS1(GPMI_CTRL1, CE3_SEL, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field CE2_SEL */ ++ ++#define BP_GPMI_CTRL1_CE2_SEL 22 ++#define BM_GPMI_CTRL1_CE2_SEL 0x00400000 ++ ++#define BF_GPMI_CTRL1_CE2_SEL(v) (((v) << 22) & BM_GPMI_CTRL1_CE2_SEL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_CE2_SEL(v) BF_CS1(GPMI_CTRL1, CE2_SEL, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field CE1_SEL */ ++ ++#define BP_GPMI_CTRL1_CE1_SEL 21 ++#define BM_GPMI_CTRL1_CE1_SEL 0x00200000 ++ ++#define BF_GPMI_CTRL1_CE1_SEL(v) (((v) << 21) & BM_GPMI_CTRL1_CE1_SEL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_CE1_SEL(v) BF_CS1(GPMI_CTRL1, CE1_SEL, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field CE0_SEL */ ++ ++#define BP_GPMI_CTRL1_CE0_SEL 20 ++#define BM_GPMI_CTRL1_CE0_SEL 0x00100000 ++ ++#define BF_GPMI_CTRL1_CE0_SEL(v) (((v) << 20) & BM_GPMI_CTRL1_CE0_SEL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_CE0_SEL(v) BF_CS1(GPMI_CTRL1, CE0_SEL, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field GANGED_RDYBUSY */ ++ ++#define BP_GPMI_CTRL1_GANGED_RDYBUSY 19 ++#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 ++ ++#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v) (((v) << 19) & BM_GPMI_CTRL1_GANGED_RDYBUSY) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_GANGED_RDYBUSY(v) BF_CS1(GPMI_CTRL1, GANGED_RDYBUSY, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field BCH_MODE */ ++ ++#define BP_GPMI_CTRL1_BCH_MODE 18 ++#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 ++ ++#define BF_GPMI_CTRL1_BCH_MODE(v) (((v) << 18) & BM_GPMI_CTRL1_BCH_MODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_BCH_MODE(v) BF_CS1(GPMI_CTRL1, BCH_MODE, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field DLL_ENABLE */ ++ ++#define BP_GPMI_CTRL1_DLL_ENABLE 17 ++#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 ++ ++#define BF_GPMI_CTRL1_DLL_ENABLE(v) (((v) << 17) & BM_GPMI_CTRL1_DLL_ENABLE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_DLL_ENABLE(v) BF_CS1(GPMI_CTRL1, DLL_ENABLE, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field HALF_PERIOD */ ++ ++#define BP_GPMI_CTRL1_HALF_PERIOD 16 ++#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 ++ ++#define BF_GPMI_CTRL1_HALF_PERIOD(v) (((v) << 16) & BM_GPMI_CTRL1_HALF_PERIOD) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_HALF_PERIOD(v) BF_CS1(GPMI_CTRL1, HALF_PERIOD, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field RDN_DELAY */ ++ ++#define BP_GPMI_CTRL1_RDN_DELAY 12 ++#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 ++ ++#define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_RDN_DELAY(v) BF_CS1(GPMI_CTRL1, RDN_DELAY, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field DMA2ECC_MODE */ ++ ++#define BP_GPMI_CTRL1_DMA2ECC_MODE 11 ++#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 ++ ++#define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & BM_GPMI_CTRL1_DMA2ECC_MODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_DMA2ECC_MODE(v) BF_CS1(GPMI_CTRL1, DMA2ECC_MODE, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field DEV_IRQ */ ++ ++#define BP_GPMI_CTRL1_DEV_IRQ 10 ++#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 ++ ++#define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & BM_GPMI_CTRL1_DEV_IRQ) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_DEV_IRQ(v) BF_CS1(GPMI_CTRL1, DEV_IRQ, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field TIMEOUT_IRQ */ ++ ++#define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 ++#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 ++ ++#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & BM_GPMI_CTRL1_TIMEOUT_IRQ) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_TIMEOUT_IRQ(v) BF_CS1(GPMI_CTRL1, TIMEOUT_IRQ, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field BURST_EN */ ++ ++#define BP_GPMI_CTRL1_BURST_EN 8 ++#define BM_GPMI_CTRL1_BURST_EN 0x00000100 ++ ++#define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & BM_GPMI_CTRL1_BURST_EN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_BURST_EN(v) BF_CS1(GPMI_CTRL1, BURST_EN, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY3 */ ++ ++#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 ++#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080 ++ ++#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY3, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY2 */ ++ ++#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 ++#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040 ++ ++#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY2, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY1 */ ++ ++#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 ++#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020 ++ ++#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY1, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field ABORT_WAIT_FOR_READY0 */ ++ ++#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 ++#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010 ++ ++#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) BF_CS1(GPMI_CTRL1, ABORT_WAIT_FOR_READY0, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field DEV_RESET */ ++ ++#define BP_GPMI_CTRL1_DEV_RESET 3 ++#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 ++ ++#define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & BM_GPMI_CTRL1_DEV_RESET) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_DEV_RESET(v) BF_CS1(GPMI_CTRL1, DEV_RESET, v) ++#endif ++ ++#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 ++#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 ++ ++/* --- Register HW_GPMI_CTRL1, field ATA_IRQRDY_POLARITY */ ++ ++#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 ++#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 ++ ++#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) BF_CS1(GPMI_CTRL1, ATA_IRQRDY_POLARITY, v) ++#endif ++ ++#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 ++#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 ++ ++/* --- Register HW_GPMI_CTRL1, field CAMERA_MODE */ ++ ++#define BP_GPMI_CTRL1_CAMERA_MODE 1 ++#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 ++ ++#define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & BM_GPMI_CTRL1_CAMERA_MODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_CAMERA_MODE(v) BF_CS1(GPMI_CTRL1, CAMERA_MODE, v) ++#endif ++ ++/* --- Register HW_GPMI_CTRL1, field GPMI_MODE */ ++ ++#define BP_GPMI_CTRL1_GPMI_MODE 0 ++#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 ++ ++#define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & BM_GPMI_CTRL1_GPMI_MODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_CTRL1_GPMI_MODE(v) BF_CS1(GPMI_CTRL1, GPMI_MODE, v) ++#endif ++ ++#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 ++#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 ++ ++ ++ ++/* ++ * HW_GPMI_TIMING0 - GPMI Timing Register 0 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA_SETUP : 8; ++ unsigned DATA_HOLD : 8; ++ unsigned ADDRESS_SETUP : 8; ++ unsigned RSVD1 : 8; ++ } B; ++} hw_gpmi_timing0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_TIMING0 register ++ */ ++#define HW_GPMI_TIMING0_ADDR (REGS_GPMI_BASE + 0x00000070) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_TIMING0 (*(volatile hw_gpmi_timing0_t *) HW_GPMI_TIMING0_ADDR) ++#define HW_GPMI_TIMING0_RD() (HW_GPMI_TIMING0.U) ++#define HW_GPMI_TIMING0_WR(v) (HW_GPMI_TIMING0.U = (v)) ++#define HW_GPMI_TIMING0_SET(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() | (v))) ++#define HW_GPMI_TIMING0_CLR(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() & ~(v))) ++#define HW_GPMI_TIMING0_TOG(v) (HW_GPMI_TIMING0_WR(HW_GPMI_TIMING0_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_TIMING0 bitfields ++ */ ++/* --- Register HW_GPMI_TIMING0, field ADDRESS_SETUP */ ++ ++#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 ++#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 ++ ++#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING0_ADDRESS_SETUP(v) (HW_GPMI_TIMING0.B.ADDRESS_SETUP = (v)) ++#endif ++ ++/* --- Register HW_GPMI_TIMING0, field DATA_HOLD */ ++ ++#define BP_GPMI_TIMING0_DATA_HOLD 8 ++#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 ++ ++#define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING0_DATA_HOLD(v) (HW_GPMI_TIMING0.B.DATA_HOLD = (v)) ++#endif ++ ++/* --- Register HW_GPMI_TIMING0, field DATA_SETUP */ ++ ++#define BP_GPMI_TIMING0_DATA_SETUP 0 ++#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF ++ ++#define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING0_DATA_SETUP(v) (HW_GPMI_TIMING0.B.DATA_SETUP = (v)) ++#endif ++ ++#define NAND_GPMI_TIMING0(AddSetup, DataSetup, DataHold) \ ++ (BF_GPMI_TIMING0_ADDRESS_SETUP(AddSetup) | \ ++ BF_GPMI_TIMING0_DATA_HOLD(DataHold) | \ ++ BF_GPMI_TIMING0_DATA_SETUP(DataSetup)) ++ ++/* ++ * HW_GPMI_TIMING1 - GPMI Timing Register 1 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned RSVD1 : 16; ++ unsigned DEVICE_BUSY_TIMEOUT : 16; ++ } B; ++} hw_gpmi_timing1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_TIMING1 register ++ */ ++#define HW_GPMI_TIMING1_ADDR (REGS_GPMI_BASE + 0x00000080) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_TIMING1 (*(volatile hw_gpmi_timing1_t *) HW_GPMI_TIMING1_ADDR) ++#define HW_GPMI_TIMING1_RD() (HW_GPMI_TIMING1.U) ++#define HW_GPMI_TIMING1_WR(v) (HW_GPMI_TIMING1.U = (v)) ++#define HW_GPMI_TIMING1_SET(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() | (v))) ++#define HW_GPMI_TIMING1_CLR(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() & ~(v))) ++#define HW_GPMI_TIMING1_TOG(v) (HW_GPMI_TIMING1_WR(HW_GPMI_TIMING1_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_TIMING1 bitfields ++ */ ++/* --- Register HW_GPMI_TIMING1, field DEVICE_BUSY_TIMEOUT */ ++ ++#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 ++#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) ((((unsigned int) v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) ++#else ++#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (HW_GPMI_TIMING1.B.DEVICE_BUSY_TIMEOUT = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_TIMING2 - GPMI Timing Register 2 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned UDMA_SETUP : 8; ++ unsigned UDMA_HOLD : 8; ++ unsigned UDMA_ENV : 8; ++ unsigned UDMA_TRP : 8; ++ } B; ++} hw_gpmi_timing2_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_TIMING2 register ++ */ ++#define HW_GPMI_TIMING2_ADDR (REGS_GPMI_BASE + 0x00000090) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_TIMING2 (*(volatile hw_gpmi_timing2_t *) HW_GPMI_TIMING2_ADDR) ++#define HW_GPMI_TIMING2_RD() (HW_GPMI_TIMING2.U) ++#define HW_GPMI_TIMING2_WR(v) (HW_GPMI_TIMING2.U = (v)) ++#define HW_GPMI_TIMING2_SET(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() | (v))) ++#define HW_GPMI_TIMING2_CLR(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() & ~(v))) ++#define HW_GPMI_TIMING2_TOG(v) (HW_GPMI_TIMING2_WR(HW_GPMI_TIMING2_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_TIMING2 bitfields ++ */ ++/* --- Register HW_GPMI_TIMING2, field UDMA_TRP */ ++ ++#define BP_GPMI_TIMING2_UDMA_TRP 24 ++#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_TIMING2_UDMA_TRP(v) ((((unsigned int) v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) ++#else ++#define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING2_UDMA_TRP(v) (HW_GPMI_TIMING2.B.UDMA_TRP = (v)) ++#endif ++ ++/* --- Register HW_GPMI_TIMING2, field UDMA_ENV */ ++ ++#define BP_GPMI_TIMING2_UDMA_ENV 16 ++#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 ++ ++#define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING2_UDMA_ENV(v) (HW_GPMI_TIMING2.B.UDMA_ENV = (v)) ++#endif ++ ++/* --- Register HW_GPMI_TIMING2, field UDMA_HOLD */ ++ ++#define BP_GPMI_TIMING2_UDMA_HOLD 8 ++#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 ++ ++#define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING2_UDMA_HOLD(v) (HW_GPMI_TIMING2.B.UDMA_HOLD = (v)) ++#endif ++ ++/* --- Register HW_GPMI_TIMING2, field UDMA_SETUP */ ++ ++#define BP_GPMI_TIMING2_UDMA_SETUP 0 ++#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF ++ ++#define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_TIMING2_UDMA_SETUP(v) (HW_GPMI_TIMING2.B.UDMA_SETUP = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_DATA - GPMI DMA Data Transfer Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA : 32; ++ } B; ++} hw_gpmi_data_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_DATA register ++ */ ++#define HW_GPMI_DATA_ADDR (REGS_GPMI_BASE + 0x000000A0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_DATA (*(volatile hw_gpmi_data_t *) HW_GPMI_DATA_ADDR) ++#define HW_GPMI_DATA_RD() (HW_GPMI_DATA.U) ++#define HW_GPMI_DATA_WR(v) (HW_GPMI_DATA.U = (v)) ++#define HW_GPMI_DATA_SET(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() | (v))) ++#define HW_GPMI_DATA_CLR(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() & ~(v))) ++#define HW_GPMI_DATA_TOG(v) (HW_GPMI_DATA_WR(HW_GPMI_DATA_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_DATA bitfields ++ */ ++/* --- Register HW_GPMI_DATA, field DATA */ ++ ++#define BP_GPMI_DATA_DATA 0 ++#define BM_GPMI_DATA_DATA 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_DATA_DATA(v) ((unsigned int) v) ++#else ++#define BF_GPMI_DATA_DATA(v) (v) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_GPMI_DATA_DATA(v) (HW_GPMI_DATA.B.DATA = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_GPMI_STAT - GPMI Status Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DEV0_ERROR : 1; ++ unsigned DEV1_ERROR : 1; ++ unsigned DEV2_ERROR : 1; ++ unsigned DEV3_ERROR : 1; ++ unsigned FIFO_FULL : 1; ++ unsigned FIFO_EMPTY : 1; ++ unsigned INVALID_BUFFER_MASK : 1; ++ unsigned ATA_IRQ : 1; ++ unsigned RDY_TIMEOUT : 4; ++ unsigned RSVD1 : 19; ++ unsigned PRESENT : 1; ++ } B; ++} hw_gpmi_stat_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_STAT register ++ */ ++#define HW_GPMI_STAT_ADDR (REGS_GPMI_BASE + 0x000000B0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_STAT (*(volatile hw_gpmi_stat_t *) HW_GPMI_STAT_ADDR) ++#define HW_GPMI_STAT_RD() (HW_GPMI_STAT.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_STAT bitfields ++ */ ++/* --- Register HW_GPMI_STAT, field PRESENT */ ++ ++#define BP_GPMI_STAT_PRESENT 31 ++#define BM_GPMI_STAT_PRESENT 0x80000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_STAT_PRESENT(v) ((((unsigned int) v) << 31) & BM_GPMI_STAT_PRESENT) ++#else ++#define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & BM_GPMI_STAT_PRESENT) ++#endif ++ ++#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 ++#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 ++ ++/* --- Register HW_GPMI_STAT, field RDY_TIMEOUT */ ++ ++#define BP_GPMI_STAT_RDY_TIMEOUT 8 ++#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00 ++ ++#define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT) ++ ++/* --- Register HW_GPMI_STAT, field ATA_IRQ */ ++ ++#define BP_GPMI_STAT_ATA_IRQ 7 ++#define BM_GPMI_STAT_ATA_IRQ 0x00000080 ++ ++#define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & BM_GPMI_STAT_ATA_IRQ) ++ ++/* --- Register HW_GPMI_STAT, field INVALID_BUFFER_MASK */ ++ ++#define BP_GPMI_STAT_INVALID_BUFFER_MASK 6 ++#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040 ++ ++#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & BM_GPMI_STAT_INVALID_BUFFER_MASK) ++ ++/* --- Register HW_GPMI_STAT, field FIFO_EMPTY */ ++ ++#define BP_GPMI_STAT_FIFO_EMPTY 5 ++#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020 ++ ++#define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & BM_GPMI_STAT_FIFO_EMPTY) ++ ++#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 ++#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 ++ ++/* --- Register HW_GPMI_STAT, field FIFO_FULL */ ++ ++#define BP_GPMI_STAT_FIFO_FULL 4 ++#define BM_GPMI_STAT_FIFO_FULL 0x00000010 ++ ++#define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & BM_GPMI_STAT_FIFO_FULL) ++ ++#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 ++#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 ++ ++/* --- Register HW_GPMI_STAT, field DEV3_ERROR */ ++ ++#define BP_GPMI_STAT_DEV3_ERROR 3 ++#define BM_GPMI_STAT_DEV3_ERROR 0x00000008 ++ ++#define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & BM_GPMI_STAT_DEV3_ERROR) ++ ++/* --- Register HW_GPMI_STAT, field DEV2_ERROR */ ++ ++#define BP_GPMI_STAT_DEV2_ERROR 2 ++#define BM_GPMI_STAT_DEV2_ERROR 0x00000004 ++ ++#define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & BM_GPMI_STAT_DEV2_ERROR) ++ ++/* --- Register HW_GPMI_STAT, field DEV1_ERROR */ ++ ++#define BP_GPMI_STAT_DEV1_ERROR 1 ++#define BM_GPMI_STAT_DEV1_ERROR 0x00000002 ++ ++#define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & BM_GPMI_STAT_DEV1_ERROR) ++ ++/* --- Register HW_GPMI_STAT, field DEV0_ERROR */ ++ ++#define BP_GPMI_STAT_DEV0_ERROR 0 ++#define BM_GPMI_STAT_DEV0_ERROR 0x00000001 ++ ++#define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & BM_GPMI_STAT_DEV0_ERROR) ++ ++ ++ ++/* ++ * HW_GPMI_DEBUG - GPMI Debug Information Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned MAIN_STATE : 4; ++ unsigned PIN_STATE : 3; ++ unsigned BUSY : 1; ++ unsigned UDMA_STATE : 4; ++ unsigned CMD_END : 4; ++ unsigned DMAREQ0 : 1; ++ unsigned DMAREQ1 : 1; ++ unsigned DMAREQ2 : 1; ++ unsigned DMAREQ3 : 1; ++ unsigned SENSE0 : 1; ++ unsigned SENSE1 : 1; ++ unsigned SENSE2 : 1; ++ unsigned SENSE3 : 1; ++ unsigned WAIT_FOR_READY_END0 : 1; ++ unsigned WAIT_FOR_READY_END1 : 1; ++ unsigned WAIT_FOR_READY_END2 : 1; ++ unsigned WAIT_FOR_READY_END3 : 1; ++ unsigned READY0 : 1; ++ unsigned READY1 : 1; ++ unsigned READY2 : 1; ++ unsigned READY3 : 1; ++ } B; ++} hw_gpmi_debug_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_DEBUG register ++ */ ++#define HW_GPMI_DEBUG_ADDR (0x8000c000 + 0x000000C0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_DEBUG (*(volatile hw_gpmi_debug_t *) HW_GPMI_DEBUG_ADDR) ++#define HW_GPMI_DEBUG_RD() (HW_GPMI_DEBUG.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_DEBUG bitfields ++ */ ++/* --- Register HW_GPMI_DEBUG, field READY3 */ ++ ++#define BP_GPMI_DEBUG_READY3 31 ++#define BM_GPMI_DEBUG_READY3 0x80000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_DEBUG_READY3(v) ((((unsigned int) v) << 31) & BM_GPMI_DEBUG_READY3) ++#else ++#define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & BM_GPMI_DEBUG_READY3) ++#endif ++ ++/* --- Register HW_GPMI_DEBUG, field READY2 */ ++ ++#define BP_GPMI_DEBUG_READY2 30 ++#define BM_GPMI_DEBUG_READY2 0x40000000 ++ ++#define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & BM_GPMI_DEBUG_READY2) ++ ++/* --- Register HW_GPMI_DEBUG, field READY1 */ ++ ++#define BP_GPMI_DEBUG_READY1 29 ++#define BM_GPMI_DEBUG_READY1 0x20000000 ++ ++#define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & BM_GPMI_DEBUG_READY1) ++ ++/* --- Register HW_GPMI_DEBUG, field READY0 */ ++ ++#define BP_GPMI_DEBUG_READY0 28 ++#define BM_GPMI_DEBUG_READY0 0x10000000 ++ ++#define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & BM_GPMI_DEBUG_READY0) ++ ++/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END3 */ ++ ++#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 ++#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000 ++ ++#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & BM_GPMI_DEBUG_WAIT_FOR_READY_END3) ++ ++/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END2 */ ++ ++#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 ++#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000 ++ ++#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & BM_GPMI_DEBUG_WAIT_FOR_READY_END2) ++ ++/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END1 */ ++ ++#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 ++#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000 ++ ++#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & BM_GPMI_DEBUG_WAIT_FOR_READY_END1) ++ ++/* --- Register HW_GPMI_DEBUG, field WAIT_FOR_READY_END0 */ ++ ++#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 ++#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000 ++ ++#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END0) ++ ++/* --- Register HW_GPMI_DEBUG, field SENSE3 */ ++ ++#define BP_GPMI_DEBUG_SENSE3 23 ++#define BM_GPMI_DEBUG_SENSE3 0x00800000 ++ ++#define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & BM_GPMI_DEBUG_SENSE3) ++ ++/* --- Register HW_GPMI_DEBUG, field SENSE2 */ ++ ++#define BP_GPMI_DEBUG_SENSE2 22 ++#define BM_GPMI_DEBUG_SENSE2 0x00400000 ++ ++#define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & BM_GPMI_DEBUG_SENSE2) ++ ++/* --- Register HW_GPMI_DEBUG, field SENSE1 */ ++ ++#define BP_GPMI_DEBUG_SENSE1 21 ++#define BM_GPMI_DEBUG_SENSE1 0x00200000 ++ ++#define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & BM_GPMI_DEBUG_SENSE1) ++ ++/* --- Register HW_GPMI_DEBUG, field SENSE0 */ ++ ++#define BP_GPMI_DEBUG_SENSE0 20 ++#define BM_GPMI_DEBUG_SENSE0 0x00100000 ++ ++#define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & BM_GPMI_DEBUG_SENSE0) ++ ++/* --- Register HW_GPMI_DEBUG, field DMAREQ3 */ ++ ++#define BP_GPMI_DEBUG_DMAREQ3 19 ++#define BM_GPMI_DEBUG_DMAREQ3 0x00080000 ++ ++#define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & BM_GPMI_DEBUG_DMAREQ3) ++ ++/* --- Register HW_GPMI_DEBUG, field DMAREQ2 */ ++ ++#define BP_GPMI_DEBUG_DMAREQ2 18 ++#define BM_GPMI_DEBUG_DMAREQ2 0x00040000 ++ ++#define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & BM_GPMI_DEBUG_DMAREQ2) ++ ++/* --- Register HW_GPMI_DEBUG, field DMAREQ1 */ ++ ++#define BP_GPMI_DEBUG_DMAREQ1 17 ++#define BM_GPMI_DEBUG_DMAREQ1 0x00020000 ++ ++#define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & BM_GPMI_DEBUG_DMAREQ1) ++ ++/* --- Register HW_GPMI_DEBUG, field DMAREQ0 */ ++ ++#define BP_GPMI_DEBUG_DMAREQ0 16 ++#define BM_GPMI_DEBUG_DMAREQ0 0x00010000 ++ ++#define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & BM_GPMI_DEBUG_DMAREQ0) ++ ++/* --- Register HW_GPMI_DEBUG, field CMD_END */ ++ ++#define BP_GPMI_DEBUG_CMD_END 12 ++#define BM_GPMI_DEBUG_CMD_END 0x0000F000 ++ ++#define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & BM_GPMI_DEBUG_CMD_END) ++ ++/* --- Register HW_GPMI_DEBUG, field UDMA_STATE */ ++ ++#define BP_GPMI_DEBUG_UDMA_STATE 8 ++#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00 ++ ++#define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE) ++ ++/* --- Register HW_GPMI_DEBUG, field BUSY */ ++ ++#define BP_GPMI_DEBUG_BUSY 7 ++#define BM_GPMI_DEBUG_BUSY 0x00000080 ++ ++#define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & BM_GPMI_DEBUG_BUSY) ++ ++#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 ++#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 ++ ++/* --- Register HW_GPMI_DEBUG, field PIN_STATE */ ++ ++#define BP_GPMI_DEBUG_PIN_STATE 4 ++#define BM_GPMI_DEBUG_PIN_STATE 0x00000070 ++ ++#define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE) ++ ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 ++#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 ++ ++/* --- Register HW_GPMI_DEBUG, field MAIN_STATE */ ++ ++#define BP_GPMI_DEBUG_MAIN_STATE 0 ++#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F ++ ++#define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE) ++ ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 ++#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA ++ ++ ++ ++/* ++ * HW_GPMI_VERSION - GPMI Version Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned STEP : 16; ++ unsigned MINOR : 8; ++ unsigned MAJOR : 8; ++ } B; ++} hw_gpmi_version_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_VERSION register ++ */ ++#define HW_GPMI_VERSION_ADDR (REGS_GPMI_BASE + 0x000000D0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_VERSION (*(volatile hw_gpmi_version_t *) HW_GPMI_VERSION_ADDR) ++#define HW_GPMI_VERSION_RD() (HW_GPMI_VERSION.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_VERSION bitfields ++ */ ++/* --- Register HW_GPMI_VERSION, field MAJOR */ ++ ++#define BP_GPMI_VERSION_MAJOR 24 ++#define BM_GPMI_VERSION_MAJOR 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_VERSION_MAJOR(v) ((((unsigned int) v) << 24) & BM_GPMI_VERSION_MAJOR) ++#else ++#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR) ++#endif ++ ++/* --- Register HW_GPMI_VERSION, field MINOR */ ++ ++#define BP_GPMI_VERSION_MINOR 16 ++#define BM_GPMI_VERSION_MINOR 0x00FF0000 ++ ++#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR) ++ ++/* --- Register HW_GPMI_VERSION, field STEP */ ++ ++#define BP_GPMI_VERSION_STEP 0 ++#define BM_GPMI_VERSION_STEP 0x0000FFFF ++ ++#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP) ++ ++ ++ ++/* ++ * HW_GPMI_DEBUG2 - GPMI Debug2 Information Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned RDN_TAP : 6; ++ unsigned UPDATE_WINDOW : 1; ++ unsigned VIEW_DELAYED_RDN : 1; ++ unsigned SYND2GPMI_READY : 1; ++ unsigned SYND2GPMI_VALID : 1; ++ unsigned GPMI2SYND_READY : 1; ++ unsigned GPMI2SYND_VALID : 1; ++ unsigned SYND2GPMI_BE : 4; ++ unsigned RSVD1 : 16; ++ } B; ++} hw_gpmi_debug2_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_DEBUG2 register ++ */ ++#define HW_GPMI_DEBUG2_ADDR (0x8000c000 + 0x000000E0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_DEBUG2 (*(volatile hw_gpmi_debug2_t *) HW_GPMI_DEBUG2_ADDR) ++#define HW_GPMI_DEBUG2_RD() (HW_GPMI_DEBUG2.U) ++#define HW_GPMI_DEBUG2_WR(v) (HW_GPMI_DEBUG2.U = (v)) ++#define HW_GPMI_DEBUG2_SET(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() | (v))) ++#define HW_GPMI_DEBUG2_CLR(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() & ~(v))) ++#define HW_GPMI_DEBUG2_TOG(v) (HW_GPMI_DEBUG2_WR(HW_GPMI_DEBUG2_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_DEBUG2 bitfields ++ */ ++/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_BE */ ++ ++#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 ++#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 ++ ++#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) ++ ++/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_VALID */ ++ ++#define BP_GPMI_DEBUG2_GPMI2SYND_VALID 11 ++#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 ++ ++#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v) (((v) << 11) & BM_GPMI_DEBUG2_GPMI2SYND_VALID) ++ ++/* --- Register HW_GPMI_DEBUG2, field GPMI2SYND_READY */ ++ ++#define BP_GPMI_DEBUG2_GPMI2SYND_READY 10 ++#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 ++ ++#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v) (((v) << 10) & BM_GPMI_DEBUG2_GPMI2SYND_READY) ++ ++/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_VALID */ ++ ++#define BP_GPMI_DEBUG2_SYND2GPMI_VALID 9 ++#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 ++ ++#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v) (((v) << 9) & BM_GPMI_DEBUG2_SYND2GPMI_VALID) ++ ++/* --- Register HW_GPMI_DEBUG2, field SYND2GPMI_READY */ ++ ++#define BP_GPMI_DEBUG2_SYND2GPMI_READY 8 ++#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 ++ ++#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v) (((v) << 8) & BM_GPMI_DEBUG2_SYND2GPMI_READY) ++ ++/* --- Register HW_GPMI_DEBUG2, field VIEW_DELAYED_RDN */ ++ ++#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN 7 ++#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 ++ ++#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) (((v) << 7) & BM_GPMI_DEBUG2_VIEW_DELAYED_RDN) ++ ++#ifndef __LANGUAGE_ASM__ ++//#define BW_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) BF_CS1(GPMI_DEBUG2, VIEW_DELAYED_RDN, v) ++#endif ++ ++/* --- Register HW_GPMI_DEBUG2, field UPDATE_WINDOW */ ++ ++#define BP_GPMI_DEBUG2_UPDATE_WINDOW 6 ++#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 ++ ++#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v) (((v) << 6) & BM_GPMI_DEBUG2_UPDATE_WINDOW) ++ ++/* --- Register HW_GPMI_DEBUG2, field RDN_TAP */ ++ ++#define BP_GPMI_DEBUG2_RDN_TAP 0 ++#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F ++ ++#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) ++ ++ ++ ++/* ++ * HW_GPMI_DEBUG3 - GPMI Debug3 Information Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DEV_WORD_CNTR : 16; ++ unsigned APB_WORD_CNTR : 16; ++ } B; ++} hw_gpmi_debug3_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_GPMI_DEBUG3 register ++ */ ++#define HW_GPMI_DEBUG3_ADDR (0x8000c000 + 0x000000F0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_GPMI_DEBUG3 (*(volatile hw_gpmi_debug3_t *) HW_GPMI_DEBUG3_ADDR) ++#define HW_GPMI_DEBUG3_RD() (HW_GPMI_DEBUG3.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_GPMI_DEBUG3 bitfields ++ */ ++/* --- Register HW_GPMI_DEBUG3, field APB_WORD_CNTR */ ++ ++#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 ++#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) ((((unsigned int) v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) ++#else ++#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) ++#endif ++ ++/* --- Register HW_GPMI_DEBUG3, field DEV_WORD_CNTR */ ++ ++#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 ++#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF ++ ++#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) ++ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned CMD_ADDR : 32; ++ } B; ++} hw_apbh_chn_nxtcmdar_t; ++ ++ ++#define HW_APBH_CHn_NXTCMDAR_COUNT 8 ++#define HW_APBH_CHn_NXTCMDAR_ADDR(n) (0x80004000 + 0x00000050 + ((n) * 0x70)) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_APBH_CHn_NXTCMDAR(n) (*(volatile hw_apbh_chn_nxtcmdar_t *) HW_APBH_CHn_NXTCMDAR_ADDR(n)) ++#define HW_APBH_CHn_NXTCMDAR_RD(n) (HW_APBH_CHn_NXTCMDAR(n).U) ++#define HW_APBH_CHn_NXTCMDAR_WR(n, v) (HW_APBH_CHn_NXTCMDAR(n).U = (v)) ++#define HW_APBH_CHn_NXTCMDAR_SET(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) | (v))) ++#define HW_APBH_CHn_NXTCMDAR_CLR(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) & ~(v))) ++#define HW_APBH_CHn_NXTCMDAR_TOG(n, v) (HW_APBH_CHn_NXTCMDAR_WR(n, HW_APBH_CHn_NXTCMDAR_RD(n) ^ (v))) ++#endif ++ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned INCREMENT_SEMA : 8; ++ unsigned RSVD1 : 8; ++ unsigned PHORE : 8; ++ unsigned RSVD2 : 8; ++ } B; ++} hw_apbh_chn_sema_t; ++ ++#define HW_APBH_CHn_SEMA_COUNT 8 ++#define HW_APBH_CHn_SEMA_ADDR(n) (0x80004000 + 0x00000080 + ((n) * 0x70)) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_APBH_CHn_SEMA(n) (*(volatile hw_apbh_chn_sema_t *) HW_APBH_CHn_SEMA_ADDR(n)) ++#define HW_APBH_CHn_SEMA_RD(n) (HW_APBH_CHn_SEMA(n).U) ++#define HW_APBH_CHn_SEMA_WR(n, v) (HW_APBH_CHn_SEMA(n).U = (v)) ++#define HW_APBH_CHn_SEMA_SET(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) | (v))) ++#define HW_APBH_CHn_SEMA_CLR(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) & ~(v))) ++#define HW_APBH_CHn_SEMA_TOG(n, v) (HW_APBH_CHn_SEMA_WR(n, HW_APBH_CHn_SEMA_RD(n) ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_APBH_CHn_SEMA multi-register bitfields ++ */ ++/* --- Register HW_APBH_CHn_SEMA, field PHORE */ ++ ++#define BP_APBH_CHn_SEMA_PHORE 16 ++#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 ++ ++#define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) ++ ++/* --- Register HW_APBH_CHn_SEMA, field INCREMENT_SEMA */ ++ ++#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 ++#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF ++ ++#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_APBH_CHn_SEMA_INCREMENT_SEMA(n, v) (HW_APBH_CHn_SEMA(n).B.INCREMENT_SEMA = (v)) ++#endif ++ ++#endif //_NAND_DMA_DESCRIPTOR_H ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/spi_nor_parts.inl redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/spi_nor_parts.inl +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/spi_nor_parts.inl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/spi_nor_parts.inl 2010-01-26 17:33:12.992957885 +0000 +@@ -0,0 +1,71 @@ ++#ifndef CYGONCE_DEVS_FLASH_SPI_NOR_PARTS_INL ++#define CYGONCE_DEVS_FLASH_SPI_NOR_PARTS_INL ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2008-11-14 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++ { ++ device_id : 0xbf, // SST SST25VF016B (on MX51 Babbage 1.0 & 2.0) ++ device_id2 : 0x25, ++ device_id3 : 0x41, ++ device_id4 : 0xFF, ++ block_size : SZ_64K, ++ block_count: 32, ++ device_size: SZ_64K * 32, ++ fis_start_addr: 0x80000, // first 0.5MB reserved for Redboot ++ vendor_info: "SST25VF016B - 2MB ", ++ }, ++ { ++ device_id : 0x1f, // Atmel AT45DB321D (on MX51 Babbage 2.5) ++ device_id2 : 0x27, ++ device_id3 : 0x01, ++ device_id4 : 0x00, ++ block_size : SZ_64K, ++ block_count: 64, ++ device_size: SZ_64K * 64, ++ fis_start_addr: 0x84000, // first 0.5MB reserved for Redboot ++ vendor_info: "AT45DB321D - 4MB ", ++ }, ++#endif // CYGONCE_DEVS_FLASH_SPI_NOR_PARTS_INL +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/stmp_bch.h redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/stmp_bch.h +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/include/stmp_bch.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/include/stmp_bch.h 2010-01-26 17:33:13.012959635 +0000 +@@ -0,0 +1,1898 @@ ++#ifndef _STMP_BCH_H ++#define _STMP_BCH_H 1 ++ ++//#include "regs.h" ++ ++#ifndef REGS_BCH_BASE ++#define REGS_BCH_BASE (0x80000000 + 0x0000A000) ++#endif ++ ++/* ++ * HW_BCH_CTRL - Hardware BCH ECC Accelerator Control Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned COMPLETE_IRQ : 1; ++ unsigned RSVD0 : 1; ++ unsigned DEBUG_STALL_IRQ : 1; ++ unsigned BM_ERROR_IRQ : 1; ++ unsigned RSVD1 : 4; ++ unsigned COMPLETE_IRQ_EN : 1; ++ unsigned RSVD2 : 1; ++ unsigned DEBUG_STALL_IRQ_EN : 1; ++ unsigned RSVD3 : 5; ++ unsigned M2M_ENABLE : 1; ++ unsigned M2M_ENCODE : 1; ++ unsigned M2M_LAYOUT : 2; ++ unsigned RSVD4 : 2; ++ unsigned DEBUGSYNDROME : 1; ++ unsigned RSVD5 : 7; ++ unsigned CLKGATE : 1; ++ unsigned SFTRST : 1; ++ } B; ++} hw_bch_ctrl_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_CTRL register ++ */ ++#define HW_BCH_CTRL_ADDR (REGS_BCH_BASE + 0x00000000) ++#define HW_BCH_CTRL_SET_ADDR (REGS_BCH_BASE + 0x00000004) ++#define HW_BCH_CTRL_CLR_ADDR (REGS_BCH_BASE + 0x00000008) ++#define HW_BCH_CTRL_TOG_ADDR (REGS_BCH_BASE + 0x0000000C) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_CTRL (*(volatile hw_bch_ctrl_t *) HW_BCH_CTRL_ADDR) ++#define HW_BCH_CTRL_RD() (HW_BCH_CTRL.U) ++#define HW_BCH_CTRL_WR(v) (HW_BCH_CTRL.U = (v)) ++#define HW_BCH_CTRL_SET(v) ((*(volatile unsigned int *) HW_BCH_CTRL_SET_ADDR) = (v)) ++#define HW_BCH_CTRL_CLR(v) ((*(volatile unsigned int *) HW_BCH_CTRL_CLR_ADDR) = (v)) ++#define HW_BCH_CTRL_TOG(v) ((*(volatile unsigned int *) HW_BCH_CTRL_TOG_ADDR) = (v)) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_CTRL bitfields ++ */ ++/* --- Register HW_BCH_CTRL, field SFTRST */ ++ ++#define BP_BCH_CTRL_SFTRST 31 ++#define BM_BCH_CTRL_SFTRST 0x80000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_CTRL_SFTRST(v) ((((unsigned int) v) << 31) & BM_BCH_CTRL_SFTRST) ++#else ++#define BF_BCH_CTRL_SFTRST(v) (((v) << 31) & BM_BCH_CTRL_SFTRST) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_SFTRST(v) BF_CS1(BCH_CTRL, SFTRST, v) ++#endif ++ ++#define BV_BCH_CTRL_SFTRST__RUN 0x0 ++#define BV_BCH_CTRL_SFTRST__RESET 0x1 ++ ++/* --- Register HW_BCH_CTRL, field CLKGATE */ ++ ++#define BP_BCH_CTRL_CLKGATE 30 ++#define BM_BCH_CTRL_CLKGATE 0x40000000 ++ ++#define BF_BCH_CTRL_CLKGATE(v) (((v) << 30) & BM_BCH_CTRL_CLKGATE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_CLKGATE(v) BF_CS1(BCH_CTRL, CLKGATE, v) ++#endif ++ ++#define BV_BCH_CTRL_CLKGATE__RUN 0x0 ++#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 ++ ++/* --- Register HW_BCH_CTRL, field DEBUGSYNDROME */ ++ ++#define BP_BCH_CTRL_DEBUGSYNDROME 22 ++#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 ++ ++#define BF_BCH_CTRL_DEBUGSYNDROME(v) (((v) << 22) & BM_BCH_CTRL_DEBUGSYNDROME) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_DEBUGSYNDROME(v) BF_CS1(BCH_CTRL, DEBUGSYNDROME, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field M2M_LAYOUT */ ++ ++#define BP_BCH_CTRL_M2M_LAYOUT 18 ++#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 ++ ++#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_M2M_LAYOUT(v) BF_CS1(BCH_CTRL, M2M_LAYOUT, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field M2M_ENCODE */ ++ ++#define BP_BCH_CTRL_M2M_ENCODE 17 ++#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 ++ ++#define BF_BCH_CTRL_M2M_ENCODE(v) (((v) << 17) & BM_BCH_CTRL_M2M_ENCODE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_M2M_ENCODE(v) BF_CS1(BCH_CTRL, M2M_ENCODE, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field M2M_ENABLE */ ++ ++#define BP_BCH_CTRL_M2M_ENABLE 16 ++#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 ++ ++#define BF_BCH_CTRL_M2M_ENABLE(v) (((v) << 16) & BM_BCH_CTRL_M2M_ENABLE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_M2M_ENABLE(v) BF_CS1(BCH_CTRL, M2M_ENABLE, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field DEBUG_STALL_IRQ_EN */ ++ ++#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN 10 ++#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 ++ ++#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & BM_BCH_CTRL_DEBUG_STALL_IRQ_EN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) BF_CS1(BCH_CTRL, DEBUG_STALL_IRQ_EN, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field COMPLETE_IRQ_EN */ ++ ++#define BP_BCH_CTRL_COMPLETE_IRQ_EN 8 ++#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 ++ ++#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & BM_BCH_CTRL_COMPLETE_IRQ_EN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_COMPLETE_IRQ_EN(v) BF_CS1(BCH_CTRL, COMPLETE_IRQ_EN, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field BM_ERROR_IRQ */ ++ ++#define BP_BCH_CTRL_BM_ERROR_IRQ 3 ++#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 ++ ++#define BF_BCH_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & BM_BCH_CTRL_BM_ERROR_IRQ) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_BM_ERROR_IRQ(v) BF_CS1(BCH_CTRL, BM_ERROR_IRQ, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field DEBUG_STALL_IRQ */ ++ ++#define BP_BCH_CTRL_DEBUG_STALL_IRQ 2 ++#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 ++ ++#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & BM_BCH_CTRL_DEBUG_STALL_IRQ) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_DEBUG_STALL_IRQ(v) BF_CS1(BCH_CTRL, DEBUG_STALL_IRQ, v) ++#endif ++ ++/* --- Register HW_BCH_CTRL, field COMPLETE_IRQ */ ++ ++#define BP_BCH_CTRL_COMPLETE_IRQ 0 ++#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 ++ ++#define BF_BCH_CTRL_COMPLETE_IRQ(v) (((v) << 0) & BM_BCH_CTRL_COMPLETE_IRQ) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_CTRL_COMPLETE_IRQ(v) BF_CS1(BCH_CTRL, COMPLETE_IRQ, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_STATUS0 - Hardware ECC Accelerator Status Register 0 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned RSVD0 : 2; ++ unsigned UNCORRECTABLE : 1; ++ unsigned CORRECTED : 1; ++ unsigned ALLONES : 1; ++ unsigned RSVD1 : 3; ++ unsigned STATUS_BLK0 : 8; ++ unsigned COMPLETED_CE : 4; ++ unsigned HANDLE : 12; ++ } B; ++} hw_bch_status0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_STATUS0 register ++ */ ++#define HW_BCH_STATUS0_ADDR (REGS_BCH_BASE + 0x00000010) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_STATUS0 (*(volatile hw_bch_status0_t *) HW_BCH_STATUS0_ADDR) ++#define HW_BCH_STATUS0_RD() (HW_BCH_STATUS0.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_STATUS0 bitfields ++ */ ++/* --- Register HW_BCH_STATUS0, field HANDLE */ ++ ++#define BP_BCH_STATUS0_HANDLE 20 ++#define BM_BCH_STATUS0_HANDLE 0xFFF00000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_STATUS0_HANDLE(v) ((((unsigned int) v) << 20) & BM_BCH_STATUS0_HANDLE) ++#else ++#define BF_BCH_STATUS0_HANDLE(v) (((v) << 20) & BM_BCH_STATUS0_HANDLE) ++#endif ++ ++/* --- Register HW_BCH_STATUS0, field COMPLETED_CE */ ++ ++#define BP_BCH_STATUS0_COMPLETED_CE 16 ++#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 ++ ++#define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) ++ ++/* --- Register HW_BCH_STATUS0, field STATUS_BLK0 */ ++ ++#define BP_BCH_STATUS0_STATUS_BLK0 8 ++#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 ++ ++#define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) ++ ++#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 ++#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 ++#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 ++#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 ++#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 ++#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE ++#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF ++ ++/* --- Register HW_BCH_STATUS0, field ALLONES */ ++ ++#define BP_BCH_STATUS0_ALLONES 4 ++#define BM_BCH_STATUS0_ALLONES 0x00000010 ++ ++#define BF_BCH_STATUS0_ALLONES(v) (((v) << 4) & BM_BCH_STATUS0_ALLONES) ++ ++/* --- Register HW_BCH_STATUS0, field CORRECTED */ ++ ++#define BP_BCH_STATUS0_CORRECTED 3 ++#define BM_BCH_STATUS0_CORRECTED 0x00000008 ++ ++#define BF_BCH_STATUS0_CORRECTED(v) (((v) << 3) & BM_BCH_STATUS0_CORRECTED) ++ ++/* --- Register HW_BCH_STATUS0, field UNCORRECTABLE */ ++ ++#define BP_BCH_STATUS0_UNCORRECTABLE 2 ++#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 ++ ++#define BF_BCH_STATUS0_UNCORRECTABLE(v) (((v) << 2) & BM_BCH_STATUS0_UNCORRECTABLE) ++ ++ ++ ++/* ++ * HW_BCH_MODE - Hardware ECC Accelerator Mode Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned ERASE_THRESHOLD : 8; ++ unsigned RSVD : 24; ++ } B; ++} hw_bch_mode_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_MODE register ++ */ ++#define HW_BCH_MODE_ADDR (REGS_BCH_BASE + 0x00000020) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_MODE (*(volatile hw_bch_mode_t *) HW_BCH_MODE_ADDR) ++#define HW_BCH_MODE_RD() (HW_BCH_MODE.U) ++#define HW_BCH_MODE_WR(v) (HW_BCH_MODE.U = (v)) ++#define HW_BCH_MODE_SET(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() | (v))) ++#define HW_BCH_MODE_CLR(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() & ~(v))) ++#define HW_BCH_MODE_TOG(v) (HW_BCH_MODE_WR(HW_BCH_MODE_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_MODE bitfields ++ */ ++/* --- Register HW_BCH_MODE, field ERASE_THRESHOLD */ ++ ++#define BP_BCH_MODE_ERASE_THRESHOLD 0 ++#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF ++ ++#define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_MODE_ERASE_THRESHOLD(v) (HW_BCH_MODE.B.ERASE_THRESHOLD = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned ADDR : 32; ++ } B; ++} hw_bch_encodeptr_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_ENCODEPTR register ++ */ ++#define HW_BCH_ENCODEPTR_ADDR (REGS_BCH_BASE + 0x00000030) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_ENCODEPTR (*(volatile hw_bch_encodeptr_t *) HW_BCH_ENCODEPTR_ADDR) ++#define HW_BCH_ENCODEPTR_RD() (HW_BCH_ENCODEPTR.U) ++#define HW_BCH_ENCODEPTR_WR(v) (HW_BCH_ENCODEPTR.U = (v)) ++#define HW_BCH_ENCODEPTR_SET(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() | (v))) ++#define HW_BCH_ENCODEPTR_CLR(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() & ~(v))) ++#define HW_BCH_ENCODEPTR_TOG(v) (HW_BCH_ENCODEPTR_WR(HW_BCH_ENCODEPTR_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_ENCODEPTR bitfields ++ */ ++/* --- Register HW_BCH_ENCODEPTR, field ADDR */ ++ ++#define BP_BCH_ENCODEPTR_ADDR 0 ++#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_ENCODEPTR_ADDR(v) ((unsigned int) v) ++#else ++#define BF_BCH_ENCODEPTR_ADDR(v) (v) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_ENCODEPTR_ADDR(v) (HW_BCH_ENCODEPTR.B.ADDR = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DATAPTR - Hardware BCH ECC Loopback Data Buffer Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned ADDR : 32; ++ } B; ++} hw_bch_dataptr_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DATAPTR register ++ */ ++#define HW_BCH_DATAPTR_ADDR (REGS_BCH_BASE + 0x00000040) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DATAPTR (*(volatile hw_bch_dataptr_t *) HW_BCH_DATAPTR_ADDR) ++#define HW_BCH_DATAPTR_RD() (HW_BCH_DATAPTR.U) ++#define HW_BCH_DATAPTR_WR(v) (HW_BCH_DATAPTR.U = (v)) ++#define HW_BCH_DATAPTR_SET(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() | (v))) ++#define HW_BCH_DATAPTR_CLR(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() & ~(v))) ++#define HW_BCH_DATAPTR_TOG(v) (HW_BCH_DATAPTR_WR(HW_BCH_DATAPTR_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DATAPTR bitfields ++ */ ++/* --- Register HW_BCH_DATAPTR, field ADDR */ ++ ++#define BP_BCH_DATAPTR_ADDR 0 ++#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_DATAPTR_ADDR(v) ((unsigned int) v) ++#else ++#define BF_BCH_DATAPTR_ADDR(v) (v) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DATAPTR_ADDR(v) (HW_BCH_DATAPTR.B.ADDR = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned ADDR : 32; ++ } B; ++} hw_bch_metaptr_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_METAPTR register ++ */ ++#define HW_BCH_METAPTR_ADDR (REGS_BCH_BASE + 0x00000050) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_METAPTR (*(volatile hw_bch_metaptr_t *) HW_BCH_METAPTR_ADDR) ++#define HW_BCH_METAPTR_RD() (HW_BCH_METAPTR.U) ++#define HW_BCH_METAPTR_WR(v) (HW_BCH_METAPTR.U = (v)) ++#define HW_BCH_METAPTR_SET(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() | (v))) ++#define HW_BCH_METAPTR_CLR(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() & ~(v))) ++#define HW_BCH_METAPTR_TOG(v) (HW_BCH_METAPTR_WR(HW_BCH_METAPTR_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_METAPTR bitfields ++ */ ++/* --- Register HW_BCH_METAPTR, field ADDR */ ++ ++#define BP_BCH_METAPTR_ADDR 0 ++#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_METAPTR_ADDR(v) ((unsigned int) v) ++#else ++#define BF_BCH_METAPTR_ADDR(v) (v) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_METAPTR_ADDR(v) (HW_BCH_METAPTR.B.ADDR = (v)) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned CS0_SELECT : 2; ++ unsigned CS1_SELECT : 2; ++ unsigned CS2_SELECT : 2; ++ unsigned CS3_SELECT : 2; ++ unsigned CS4_SELECT : 2; ++ unsigned CS5_SELECT : 2; ++ unsigned CS6_SELECT : 2; ++ unsigned CS7_SELECT : 2; ++ unsigned CS8_SELECT : 2; ++ unsigned CS9_SELECT : 2; ++ unsigned CS10_SELECT : 2; ++ unsigned CS11_SELECT : 2; ++ unsigned CS12_SELECT : 2; ++ unsigned CS13_SELECT : 2; ++ unsigned CS14_SELECT : 2; ++ unsigned CS15_SELECT : 2; ++ } B; ++} hw_bch_layoutselect_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_LAYOUTSELECT register ++ */ ++#define HW_BCH_LAYOUTSELECT_ADDR (REGS_BCH_BASE + 0x00000070) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_LAYOUTSELECT (*(volatile hw_bch_layoutselect_t *) HW_BCH_LAYOUTSELECT_ADDR) ++#define HW_BCH_LAYOUTSELECT_RD() (HW_BCH_LAYOUTSELECT.U) ++#define HW_BCH_LAYOUTSELECT_WR(v) (HW_BCH_LAYOUTSELECT.U = (v)) ++#define HW_BCH_LAYOUTSELECT_SET(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() | (v))) ++#define HW_BCH_LAYOUTSELECT_CLR(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() & ~(v))) ++#define HW_BCH_LAYOUTSELECT_TOG(v) (HW_BCH_LAYOUTSELECT_WR(HW_BCH_LAYOUTSELECT_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_LAYOUTSELECT bitfields ++ */ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS15_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 ++#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) ((((unsigned int) v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) ++#else ++#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS15_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS15_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS14_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 ++#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 ++ ++#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS14_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS14_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS13_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 ++#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 ++ ++#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS13_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS13_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS12_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 ++#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 ++ ++#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS12_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS12_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS11_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 ++#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 ++ ++#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS11_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS11_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS10_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 ++#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 ++ ++#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS10_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS10_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS9_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 ++#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 ++ ++#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS9_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS9_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS8_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 ++#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 ++ ++#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS8_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS8_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS7_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 ++#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 ++ ++#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS7_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS7_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS6_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 ++#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 ++ ++#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS6_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS6_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS5_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 ++#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 ++ ++#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS5_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS5_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS4_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 ++#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 ++ ++#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS4_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS4_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS3_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 ++#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 ++ ++#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS3_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS3_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS2_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 ++#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 ++ ++#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS2_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS2_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS1_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 ++#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C ++ ++#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS1_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS1_SELECT, v) ++#endif ++ ++/* --- Register HW_BCH_LAYOUTSELECT, field CS0_SELECT */ ++ ++#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 ++#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 ++ ++#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_LAYOUTSELECT_CS0_SELECT(v) BF_CS1(BCH_LAYOUTSELECT, CS0_SELECT, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA0_SIZE : 12; ++ unsigned ECC0 : 4; ++ unsigned META_SIZE : 8; ++ unsigned NBLOCKS : 8; ++ } B; ++} hw_bch_flash0layout0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH0LAYOUT0 register ++ */ ++#define HW_BCH_FLASH0LAYOUT0_ADDR (REGS_BCH_BASE + 0x00000080) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH0LAYOUT0 (*(volatile hw_bch_flash0layout0_t *) HW_BCH_FLASH0LAYOUT0_ADDR) ++#define HW_BCH_FLASH0LAYOUT0_RD() (HW_BCH_FLASH0LAYOUT0.U) ++#define HW_BCH_FLASH0LAYOUT0_WR(v) (HW_BCH_FLASH0LAYOUT0.U = (v)) ++#define HW_BCH_FLASH0LAYOUT0_SET(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() | (v))) ++#define HW_BCH_FLASH0LAYOUT0_CLR(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() & ~(v))) ++#define HW_BCH_FLASH0LAYOUT0_TOG(v) (HW_BCH_FLASH0LAYOUT0_WR(HW_BCH_FLASH0LAYOUT0_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH0LAYOUT0 bitfields ++ */ ++/* --- Register HW_BCH_FLASH0LAYOUT0, field NBLOCKS */ ++ ++#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 ++#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) ((((unsigned int) v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) ++#else ++#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH0LAYOUT0.B.NBLOCKS = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH0LAYOUT0, field META_SIZE */ ++ ++#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 ++#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 ++ ++#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT0_META_SIZE(v) (HW_BCH_FLASH0LAYOUT0.B.META_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH0LAYOUT0, field ECC0 */ ++ ++#define BP_BCH_FLASH0LAYOUT0_ECC0 12 ++#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 ++ ++#define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH0LAYOUT0, ECC0, v) ++#endif ++ ++#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 ++#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH0LAYOUT0, field DATA0_SIZE */ ++ ++#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 ++#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH0LAYOUT0, DATA0_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATAN_SIZE : 12; ++ unsigned ECCN : 4; ++ unsigned PAGE_SIZE : 16; ++ } B; ++} hw_bch_flash0layout1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH0LAYOUT1 register ++ */ ++#define HW_BCH_FLASH0LAYOUT1_ADDR (REGS_BCH_BASE + 0x00000090) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH0LAYOUT1 (*(volatile hw_bch_flash0layout1_t *) HW_BCH_FLASH0LAYOUT1_ADDR) ++#define HW_BCH_FLASH0LAYOUT1_RD() (HW_BCH_FLASH0LAYOUT1.U) ++#define HW_BCH_FLASH0LAYOUT1_WR(v) (HW_BCH_FLASH0LAYOUT1.U = (v)) ++#define HW_BCH_FLASH0LAYOUT1_SET(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() | (v))) ++#define HW_BCH_FLASH0LAYOUT1_CLR(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() & ~(v))) ++#define HW_BCH_FLASH0LAYOUT1_TOG(v) (HW_BCH_FLASH0LAYOUT1_WR(HW_BCH_FLASH0LAYOUT1_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH0LAYOUT1 bitfields ++ */ ++/* --- Register HW_BCH_FLASH0LAYOUT1, field PAGE_SIZE */ ++ ++#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 ++#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) ((((unsigned int) v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) ++#else ++#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH0LAYOUT1.B.PAGE_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH0LAYOUT1, field ECCN */ ++ ++#define BP_BCH_FLASH0LAYOUT1_ECCN 12 ++#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 ++ ++#define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH0LAYOUT1, ECCN, v) ++#endif ++ ++#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 ++#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH0LAYOUT1, field DATAN_SIZE */ ++ ++#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 ++#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH0LAYOUT1, DATAN_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA0_SIZE : 12; ++ unsigned ECC0 : 4; ++ unsigned META_SIZE : 8; ++ unsigned NBLOCKS : 8; ++ } B; ++} hw_bch_flash1layout0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH1LAYOUT0 register ++ */ ++#define HW_BCH_FLASH1LAYOUT0_ADDR (REGS_BCH_BASE + 0x000000A0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH1LAYOUT0 (*(volatile hw_bch_flash1layout0_t *) HW_BCH_FLASH1LAYOUT0_ADDR) ++#define HW_BCH_FLASH1LAYOUT0_RD() (HW_BCH_FLASH1LAYOUT0.U) ++#define HW_BCH_FLASH1LAYOUT0_WR(v) (HW_BCH_FLASH1LAYOUT0.U = (v)) ++#define HW_BCH_FLASH1LAYOUT0_SET(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() | (v))) ++#define HW_BCH_FLASH1LAYOUT0_CLR(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() & ~(v))) ++#define HW_BCH_FLASH1LAYOUT0_TOG(v) (HW_BCH_FLASH1LAYOUT0_WR(HW_BCH_FLASH1LAYOUT0_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH1LAYOUT0 bitfields ++ */ ++/* --- Register HW_BCH_FLASH1LAYOUT0, field NBLOCKS */ ++ ++#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 ++#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) ((((unsigned int) v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) ++#else ++#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH1LAYOUT0.B.NBLOCKS = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH1LAYOUT0, field META_SIZE */ ++ ++#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 ++#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 ++ ++#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT0_META_SIZE(v) (HW_BCH_FLASH1LAYOUT0.B.META_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH1LAYOUT0, field ECC0 */ ++ ++#define BP_BCH_FLASH1LAYOUT0_ECC0 12 ++#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 ++ ++#define BF_BCH_FLASH1LAYOUT0_ECC0(v) (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH1LAYOUT0, ECC0, v) ++#endif ++ ++#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 ++#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH1LAYOUT0, field DATA0_SIZE */ ++ ++#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 ++#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH1LAYOUT0, DATA0_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATAN_SIZE : 12; ++ unsigned ECCN : 4; ++ unsigned PAGE_SIZE : 16; ++ } B; ++} hw_bch_flash1layout1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH1LAYOUT1 register ++ */ ++#define HW_BCH_FLASH1LAYOUT1_ADDR (REGS_BCH_BASE + 0x000000B0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH1LAYOUT1 (*(volatile hw_bch_flash1layout1_t *) HW_BCH_FLASH1LAYOUT1_ADDR) ++#define HW_BCH_FLASH1LAYOUT1_RD() (HW_BCH_FLASH1LAYOUT1.U) ++#define HW_BCH_FLASH1LAYOUT1_WR(v) (HW_BCH_FLASH1LAYOUT1.U = (v)) ++#define HW_BCH_FLASH1LAYOUT1_SET(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() | (v))) ++#define HW_BCH_FLASH1LAYOUT1_CLR(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() & ~(v))) ++#define HW_BCH_FLASH1LAYOUT1_TOG(v) (HW_BCH_FLASH1LAYOUT1_WR(HW_BCH_FLASH1LAYOUT1_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH1LAYOUT1 bitfields ++ */ ++/* --- Register HW_BCH_FLASH1LAYOUT1, field PAGE_SIZE */ ++ ++#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 ++#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) ((((unsigned int) v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) ++#else ++#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH1LAYOUT1.B.PAGE_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH1LAYOUT1, field ECCN */ ++ ++#define BP_BCH_FLASH1LAYOUT1_ECCN 12 ++#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 ++ ++#define BF_BCH_FLASH1LAYOUT1_ECCN(v) (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH1LAYOUT1, ECCN, v) ++#endif ++ ++#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 ++#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH1LAYOUT1, field DATAN_SIZE */ ++ ++#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 ++#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH1LAYOUT1, DATAN_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA0_SIZE : 12; ++ unsigned ECC0 : 4; ++ unsigned META_SIZE : 8; ++ unsigned NBLOCKS : 8; ++ } B; ++} hw_bch_flash2layout0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH2LAYOUT0 register ++ */ ++#define HW_BCH_FLASH2LAYOUT0_ADDR (REGS_BCH_BASE + 0x000000C0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH2LAYOUT0 (*(volatile hw_bch_flash2layout0_t *) HW_BCH_FLASH2LAYOUT0_ADDR) ++#define HW_BCH_FLASH2LAYOUT0_RD() (HW_BCH_FLASH2LAYOUT0.U) ++#define HW_BCH_FLASH2LAYOUT0_WR(v) (HW_BCH_FLASH2LAYOUT0.U = (v)) ++#define HW_BCH_FLASH2LAYOUT0_SET(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() | (v))) ++#define HW_BCH_FLASH2LAYOUT0_CLR(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() & ~(v))) ++#define HW_BCH_FLASH2LAYOUT0_TOG(v) (HW_BCH_FLASH2LAYOUT0_WR(HW_BCH_FLASH2LAYOUT0_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH2LAYOUT0 bitfields ++ */ ++/* --- Register HW_BCH_FLASH2LAYOUT0, field NBLOCKS */ ++ ++#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 ++#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) ((((unsigned int) v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) ++#else ++#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH2LAYOUT0.B.NBLOCKS = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH2LAYOUT0, field META_SIZE */ ++ ++#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 ++#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 ++ ++#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT0_META_SIZE(v) (HW_BCH_FLASH2LAYOUT0.B.META_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH2LAYOUT0, field ECC0 */ ++ ++#define BP_BCH_FLASH2LAYOUT0_ECC0 12 ++#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 ++ ++#define BF_BCH_FLASH2LAYOUT0_ECC0(v) (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH2LAYOUT0, ECC0, v) ++#endif ++ ++#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 ++#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH2LAYOUT0, field DATA0_SIZE */ ++ ++#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 ++#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH2LAYOUT0, DATA0_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATAN_SIZE : 12; ++ unsigned ECCN : 4; ++ unsigned PAGE_SIZE : 16; ++ } B; ++} hw_bch_flash2layout1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH2LAYOUT1 register ++ */ ++#define HW_BCH_FLASH2LAYOUT1_ADDR (REGS_BCH_BASE + 0x000000D0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH2LAYOUT1 (*(volatile hw_bch_flash2layout1_t *) HW_BCH_FLASH2LAYOUT1_ADDR) ++#define HW_BCH_FLASH2LAYOUT1_RD() (HW_BCH_FLASH2LAYOUT1.U) ++#define HW_BCH_FLASH2LAYOUT1_WR(v) (HW_BCH_FLASH2LAYOUT1.U = (v)) ++#define HW_BCH_FLASH2LAYOUT1_SET(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() | (v))) ++#define HW_BCH_FLASH2LAYOUT1_CLR(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() & ~(v))) ++#define HW_BCH_FLASH2LAYOUT1_TOG(v) (HW_BCH_FLASH2LAYOUT1_WR(HW_BCH_FLASH2LAYOUT1_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH2LAYOUT1 bitfields ++ */ ++/* --- Register HW_BCH_FLASH2LAYOUT1, field PAGE_SIZE */ ++ ++#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 ++#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) ((((unsigned int) v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) ++#else ++#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH2LAYOUT1.B.PAGE_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH2LAYOUT1, field ECCN */ ++ ++#define BP_BCH_FLASH2LAYOUT1_ECCN 12 ++#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 ++ ++#define BF_BCH_FLASH2LAYOUT1_ECCN(v) (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH2LAYOUT1, ECCN, v) ++#endif ++ ++#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 ++#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH2LAYOUT1, field DATAN_SIZE */ ++ ++#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 ++#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH2LAYOUT1, DATAN_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATA0_SIZE : 12; ++ unsigned ECC0 : 4; ++ unsigned META_SIZE : 8; ++ unsigned NBLOCKS : 8; ++ } B; ++} hw_bch_flash3layout0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH3LAYOUT0 register ++ */ ++#define HW_BCH_FLASH3LAYOUT0_ADDR (REGS_BCH_BASE + 0x000000E0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH3LAYOUT0 (*(volatile hw_bch_flash3layout0_t *) HW_BCH_FLASH3LAYOUT0_ADDR) ++#define HW_BCH_FLASH3LAYOUT0_RD() (HW_BCH_FLASH3LAYOUT0.U) ++#define HW_BCH_FLASH3LAYOUT0_WR(v) (HW_BCH_FLASH3LAYOUT0.U = (v)) ++#define HW_BCH_FLASH3LAYOUT0_SET(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() | (v))) ++#define HW_BCH_FLASH3LAYOUT0_CLR(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() & ~(v))) ++#define HW_BCH_FLASH3LAYOUT0_TOG(v) (HW_BCH_FLASH3LAYOUT0_WR(HW_BCH_FLASH3LAYOUT0_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH3LAYOUT0 bitfields ++ */ ++/* --- Register HW_BCH_FLASH3LAYOUT0, field NBLOCKS */ ++ ++#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 ++#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) ((((unsigned int) v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) ++#else ++#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT0_NBLOCKS(v) (HW_BCH_FLASH3LAYOUT0.B.NBLOCKS = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH3LAYOUT0, field META_SIZE */ ++ ++#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 ++#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 ++ ++#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT0_META_SIZE(v) (HW_BCH_FLASH3LAYOUT0.B.META_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH3LAYOUT0, field ECC0 */ ++ ++#define BP_BCH_FLASH3LAYOUT0_ECC0 12 ++#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 ++ ++#define BF_BCH_FLASH3LAYOUT0_ECC0(v) (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT0_ECC0(v) BF_CS1(BCH_FLASH3LAYOUT0, ECC0, v) ++#endif ++ ++#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 ++#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH3LAYOUT0, field DATA0_SIZE */ ++ ++#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 ++#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) BF_CS1(BCH_FLASH3LAYOUT0, DATA0_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DATAN_SIZE : 12; ++ unsigned ECCN : 4; ++ unsigned PAGE_SIZE : 16; ++ } B; ++} hw_bch_flash3layout1_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_FLASH3LAYOUT1 register ++ */ ++#define HW_BCH_FLASH3LAYOUT1_ADDR (REGS_BCH_BASE + 0x000000F0) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_FLASH3LAYOUT1 (*(volatile hw_bch_flash3layout1_t *) HW_BCH_FLASH3LAYOUT1_ADDR) ++#define HW_BCH_FLASH3LAYOUT1_RD() (HW_BCH_FLASH3LAYOUT1.U) ++#define HW_BCH_FLASH3LAYOUT1_WR(v) (HW_BCH_FLASH3LAYOUT1.U = (v)) ++#define HW_BCH_FLASH3LAYOUT1_SET(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() | (v))) ++#define HW_BCH_FLASH3LAYOUT1_CLR(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() & ~(v))) ++#define HW_BCH_FLASH3LAYOUT1_TOG(v) (HW_BCH_FLASH3LAYOUT1_WR(HW_BCH_FLASH3LAYOUT1_RD() ^ (v))) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_FLASH3LAYOUT1 bitfields ++ */ ++/* --- Register HW_BCH_FLASH3LAYOUT1, field PAGE_SIZE */ ++ ++#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 ++#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) ((((unsigned int) v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) ++#else ++#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) ++#endif ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (HW_BCH_FLASH3LAYOUT1.B.PAGE_SIZE = (v)) ++#endif ++ ++/* --- Register HW_BCH_FLASH3LAYOUT1, field ECCN */ ++ ++#define BP_BCH_FLASH3LAYOUT1_ECCN 12 ++#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 ++ ++#define BF_BCH_FLASH3LAYOUT1_ECCN(v) (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT1_ECCN(v) BF_CS1(BCH_FLASH3LAYOUT1, ECCN, v) ++#endif ++ ++#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 ++#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA ++ ++/* --- Register HW_BCH_FLASH3LAYOUT1, field DATAN_SIZE */ ++ ++#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 ++#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF ++ ++#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) BF_CS1(BCH_FLASH3LAYOUT1, DATAN_SIZE, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DEBUG0 - Hardware ECC 8 Debug Register0 ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned DEBUG_REG_SELECT : 6; ++ unsigned RSVD0 : 2; ++ unsigned BM_KES_TEST_BYPASS : 1; ++ unsigned KES_DEBUG_STALL : 1; ++ unsigned KES_DEBUG_STEP : 1; ++ unsigned KES_STANDALONE : 1; ++ unsigned KES_DEBUG_KICK : 1; ++ unsigned KES_DEBUG_MODE4K : 1; ++ unsigned KES_DEBUG_PAYLOAD_FLAG : 1; ++ unsigned KES_DEBUG_SHIFT_SYND : 1; ++ unsigned KES_DEBUG_SYNDROME_SYMBOL : 9; ++ unsigned ROM_BIST_COMPLETE : 1; ++ unsigned ROM_BIST_ENABLE : 1; ++ unsigned RSVD1 : 5; ++ } B; ++} hw_bch_debug0_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DEBUG0 register ++ */ ++#define HW_BCH_DEBUG0_ADDR (REGS_BCH_BASE + 0x00000100) ++#define HW_BCH_DEBUG0_SET_ADDR (REGS_BCH_BASE + 0x00000104) ++#define HW_BCH_DEBUG0_CLR_ADDR (REGS_BCH_BASE + 0x00000108) ++#define HW_BCH_DEBUG0_TOG_ADDR (REGS_BCH_BASE + 0x0000010C) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DEBUG0 (*(volatile hw_bch_debug0_t *) HW_BCH_DEBUG0_ADDR) ++#define HW_BCH_DEBUG0_RD() (HW_BCH_DEBUG0.U) ++#define HW_BCH_DEBUG0_WR(v) (HW_BCH_DEBUG0.U = (v)) ++#define HW_BCH_DEBUG0_SET(v) ((*(volatile unsigned int *) HW_BCH_DEBUG0_SET_ADDR) = (v)) ++#define HW_BCH_DEBUG0_CLR(v) ((*(volatile unsigned int *) HW_BCH_DEBUG0_CLR_ADDR) = (v)) ++#define HW_BCH_DEBUG0_TOG(v) ((*(volatile unsigned int *) HW_BCH_DEBUG0_TOG_ADDR) = (v)) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DEBUG0 bitfields ++ */ ++/* --- Register HW_BCH_DEBUG0, field ROM_BIST_ENABLE */ ++ ++#define BP_BCH_DEBUG0_ROM_BIST_ENABLE 26 ++#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 ++ ++#define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v) (((v) << 26) & BM_BCH_DEBUG0_ROM_BIST_ENABLE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_ROM_BIST_ENABLE(v) BF_CS1(BCH_DEBUG0, ROM_BIST_ENABLE, v) ++#endif ++ ++/* --- Register HW_BCH_DEBUG0, field ROM_BIST_COMPLETE */ ++ ++#define BP_BCH_DEBUG0_ROM_BIST_COMPLETE 25 ++#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 ++ ++#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v) (((v) << 25) & BM_BCH_DEBUG0_ROM_BIST_COMPLETE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_ROM_BIST_COMPLETE(v) BF_CS1(BCH_DEBUG0, ROM_BIST_COMPLETE, v) ++#endif ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_SYNDROME_SYMBOL */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 ++#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_SYNDROME_SYMBOL, v) ++#endif ++ ++#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 ++#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_SHIFT_SYND */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 15 ++#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_SHIFT_SYND, v) ++#endif ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_PAYLOAD_FLAG */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 ++#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_PAYLOAD_FLAG, v) ++#endif ++ ++#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 ++#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_MODE4K */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K 13 ++#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & BM_BCH_DEBUG0_KES_DEBUG_MODE4K) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_MODE4K(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_MODE4K, v) ++#endif ++ ++#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 ++#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_KICK */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_KICK 12 ++#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & BM_BCH_DEBUG0_KES_DEBUG_KICK) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_KICK(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_KICK, v) ++#endif ++ ++/* --- Register HW_BCH_DEBUG0, field KES_STANDALONE */ ++ ++#define BP_BCH_DEBUG0_KES_STANDALONE 11 ++#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 ++ ++#define BF_BCH_DEBUG0_KES_STANDALONE(v) (((v) << 11) & BM_BCH_DEBUG0_KES_STANDALONE) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_STANDALONE(v) BF_CS1(BCH_DEBUG0, KES_STANDALONE, v) ++#endif ++ ++#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 ++#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_STEP */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_STEP 10 ++#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & BM_BCH_DEBUG0_KES_DEBUG_STEP) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_STEP(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_STEP, v) ++#endif ++ ++/* --- Register HW_BCH_DEBUG0, field KES_DEBUG_STALL */ ++ ++#define BP_BCH_DEBUG0_KES_DEBUG_STALL 9 ++#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 ++ ++#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & BM_BCH_DEBUG0_KES_DEBUG_STALL) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_KES_DEBUG_STALL(v) BF_CS1(BCH_DEBUG0, KES_DEBUG_STALL, v) ++#endif ++ ++#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 ++#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field BM_KES_TEST_BYPASS */ ++ ++#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS 8 ++#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 ++ ++#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & BM_BCH_DEBUG0_BM_KES_TEST_BYPASS) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) BF_CS1(BCH_DEBUG0, BM_KES_TEST_BYPASS, v) ++#endif ++ ++#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 ++#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 ++ ++/* --- Register HW_BCH_DEBUG0, field DEBUG_REG_SELECT */ ++ ++#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 ++#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F ++ ++#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) ++ ++#ifndef __LANGUAGE_ASM__ ++#define BW_BCH_DEBUG0_DEBUG_REG_SELECT(v) BF_CS1(BCH_DEBUG0, DEBUG_REG_SELECT, v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DBGKESREAD - KES Debug Read Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned VALUES : 32; ++ } B; ++} hw_bch_dbgkesread_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DBGKESREAD register ++ */ ++#define HW_BCH_DBGKESREAD_ADDR (REGS_BCH_BASE + 0x00000110) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DBGKESREAD (*(volatile hw_bch_dbgkesread_t *) HW_BCH_DBGKESREAD_ADDR) ++#define HW_BCH_DBGKESREAD_RD() (HW_BCH_DBGKESREAD.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DBGKESREAD bitfields ++ */ ++/* --- Register HW_BCH_DBGKESREAD, field VALUES */ ++ ++#define BP_BCH_DBGKESREAD_VALUES 0 ++#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_DBGKESREAD_VALUES(v) ((unsigned int) v) ++#else ++#define BF_BCH_DBGKESREAD_VALUES(v) (v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DBGCSFEREAD - Chien Search Debug Read Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned VALUES : 32; ++ } B; ++} hw_bch_dbgcsferead_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DBGCSFEREAD register ++ */ ++#define HW_BCH_DBGCSFEREAD_ADDR (REGS_BCH_BASE + 0x00000120) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DBGCSFEREAD (*(volatile hw_bch_dbgcsferead_t *) HW_BCH_DBGCSFEREAD_ADDR) ++#define HW_BCH_DBGCSFEREAD_RD() (HW_BCH_DBGCSFEREAD.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DBGCSFEREAD bitfields ++ */ ++/* --- Register HW_BCH_DBGCSFEREAD, field VALUES */ ++ ++#define BP_BCH_DBGCSFEREAD_VALUES 0 ++#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_DBGCSFEREAD_VALUES(v) ((unsigned int) v) ++#else ++#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DBGSYNDGENREAD - Syndrome Generator Debug Read Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned VALUES : 32; ++ } B; ++} hw_bch_dbgsyndgenread_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DBGSYNDGENREAD register ++ */ ++#define HW_BCH_DBGSYNDGENREAD_ADDR (REGS_BCH_BASE + 0x00000130) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DBGSYNDGENREAD (*(volatile hw_bch_dbgsyndgenread_t *) HW_BCH_DBGSYNDGENREAD_ADDR) ++#define HW_BCH_DBGSYNDGENREAD_RD() (HW_BCH_DBGSYNDGENREAD.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DBGSYNDGENREAD bitfields ++ */ ++/* --- Register HW_BCH_DBGSYNDGENREAD, field VALUES */ ++ ++#define BP_BCH_DBGSYNDGENREAD_VALUES 0 ++#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_DBGSYNDGENREAD_VALUES(v) ((unsigned int) v) ++#else ++#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_DBGAHBMREAD - AHB Master and ecc8 controller Debug Read Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned VALUES : 32; ++ } B; ++} hw_bch_dbgahbmread_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_DBGAHBMREAD register ++ */ ++#define HW_BCH_DBGAHBMREAD_ADDR (REGS_BCH_BASE + 0x00000140) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_DBGAHBMREAD (*(volatile hw_bch_dbgahbmread_t *) HW_BCH_DBGAHBMREAD_ADDR) ++#define HW_BCH_DBGAHBMREAD_RD() (HW_BCH_DBGAHBMREAD.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_DBGAHBMREAD bitfields ++ */ ++/* --- Register HW_BCH_DBGAHBMREAD, field VALUES */ ++ ++#define BP_BCH_DBGAHBMREAD_VALUES 0 ++#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_DBGAHBMREAD_VALUES(v) ((unsigned int) v) ++#else ++#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_BLOCKNAME - Block Name Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned NAME : 32; ++ } B; ++} hw_bch_blockname_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_BLOCKNAME register ++ */ ++#define HW_BCH_BLOCKNAME_ADDR (REGS_BCH_BASE + 0x00000150) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_BLOCKNAME (*(volatile hw_bch_blockname_t *) HW_BCH_BLOCKNAME_ADDR) ++#define HW_BCH_BLOCKNAME_RD() (HW_BCH_BLOCKNAME.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_BLOCKNAME bitfields ++ */ ++/* --- Register HW_BCH_BLOCKNAME, field NAME */ ++ ++#define BP_BCH_BLOCKNAME_NAME 0 ++#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_BLOCKNAME_NAME(v) ((unsigned int) v) ++#else ++#define BF_BCH_BLOCKNAME_NAME(v) (v) ++#endif ++ ++ ++ ++/* ++ * HW_BCH_VERSION - BCH Version Register ++ */ ++#ifndef __LANGUAGE_ASM__ ++typedef union ++{ ++ unsigned int U; ++ struct ++ { ++ unsigned STEP : 16; ++ unsigned MINOR : 8; ++ unsigned MAJOR : 8; ++ } B; ++} hw_bch_version_t; ++#endif ++ ++/* ++ * constants & macros for entire HW_BCH_VERSION register ++ */ ++#define HW_BCH_VERSION_ADDR (REGS_BCH_BASE + 0x00000160) ++ ++#ifndef __LANGUAGE_ASM__ ++#define HW_BCH_VERSION (*(volatile hw_bch_version_t *) HW_BCH_VERSION_ADDR) ++#define HW_BCH_VERSION_RD() (HW_BCH_VERSION.U) ++#endif ++ ++ ++/* ++ * constants & macros for individual HW_BCH_VERSION bitfields ++ */ ++/* --- Register HW_BCH_VERSION, field MAJOR */ ++ ++#define BP_BCH_VERSION_MAJOR 24 ++#define BM_BCH_VERSION_MAJOR 0xFF000000 ++ ++#ifndef __LANGUAGE_ASM__ ++#define BF_BCH_VERSION_MAJOR(v) ((((unsigned int) v) << 24) & BM_BCH_VERSION_MAJOR) ++#else ++#define BF_BCH_VERSION_MAJOR(v) (((v) << 24) & BM_BCH_VERSION_MAJOR) ++#endif ++ ++/* --- Register HW_BCH_VERSION, field MINOR */ ++ ++#define BP_BCH_VERSION_MINOR 16 ++#define BM_BCH_VERSION_MINOR 0x00FF0000 ++ ++#define BF_BCH_VERSION_MINOR(v) (((v) << 16) & BM_BCH_VERSION_MINOR) ++ ++/* --- Register HW_BCH_VERSION, field STEP */ ++ ++#define BP_BCH_VERSION_STEP 0 ++#define BM_BCH_VERSION_STEP 0x0000FFFF ++ ++#define BF_BCH_VERSION_STEP(v) (((v) << 0) & BM_BCH_VERSION_STEP) ++ ++ ++#endif /* _STMP_BCH_H */ ++ ++//////////////////////////////////////////////////////////////////////////////// +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/card_mx32.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/card_mx32.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/card_mx32.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/card_mx32.c 2010-01-26 17:33:13.022965134 +0000 +@@ -0,0 +1,1129 @@ ++// ========================================================================== ++// ++// card_mx32.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ivan Xu ++// Contributors: Ivan Xu ++// Date: 2008-06-13 Initial version ++// Purpose: ++// Description: ++// Support SD/MMC cards based on SDHC controller. ++// only base functionality is implemented: Card init, read, write and erase. ++// Write protection are not supported so far. ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++ ++//#define diag_printf1 diag_printf ++#define diag_printf1(fmt,args...) ++ ++volatile psdhc_t pSDHC; ++card_mode_t Card_Mode; ++cyg_uint32 HighCapacityCard = 0; ++cyg_uint32 card_address; ++card_type Card_type; /* Card Type*/ ++CARD_ID card_id; ++cyg_uint32 card_specific_data[4]; ++cyg_uint32 CCC = 0; /* Card Command Class */ ++ ++static void configure_cmd (command_t *cmd,cyg_uint32 index, cyg_uint32 argument, ++ cyg_uint32 transfer,cyg_uint32 response_format, cyg_uint32 data_enable, ++ cyg_uint32 bus_width ) ++{ ++ /* Configure Command index */ ++ cmd->index = index; ++ ++ /* Configure Command argument */ ++ cmd->arg = argument; ++ /* workaround for CMD0, send 80 clock cycles before CMD0 */ ++ if (cmd->index == 0) ++ { ++ cmd->data_control = (((transfer) << SDHC_CMD_WRITE_READ_SHIFT) | ++ ((response_format) << SDHC_CMD_FROMAT_OF_RESP_SHIFT) | ++ ((data_enable) << SDHC_CMD_DATA_ENABLE_SHIFT) | ++ ((bus_width) << SDHC_CMD_BUS_WIDTH_SHIFT)) | ++ (0x1 << SDHC_CMD_INIT_SHIFT ); ++ } else { ++ cmd->data_control = (((transfer) << SDHC_CMD_WRITE_READ_SHIFT) | ++ ((response_format) << SDHC_CMD_FROMAT_OF_RESP_SHIFT) | ++ ((data_enable) << SDHC_CMD_DATA_ENABLE_SHIFT) | ++ ((bus_width) << SDHC_CMD_BUS_WIDTH_SHIFT)); ++ } ++} ++ ++static void stop_clk(void) ++{ ++ /* Stop the clock */ ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ ++ /* Wait till the clock has stopped */ ++ while((pSDHC->sdhc_status & SDHC_STATUS_CARD_BUS_CLK_RUN_MSK)); ++ return; ++} ++ ++static void start_clk(void) ++{ ++ /* Start the clock */ ++ pSDHC->sdhc_clk = SDHC_CLK_START; ++ ++ /* Wait till the clock has started */ ++ while(!(pSDHC->sdhc_status & SDHC_STATUS_CARD_BUS_CLK_RUN_MSK)); ++ return; ++} ++ ++static void configure_clk(frequency_mode_t mode) ++{ ++ if(mode == iden_mode) ++ { ++ /* Below 400 kHz */ ++ pSDHC->sdhc_clk_rate = 0x207; ++ start_clk(); ++ } ++ else if(mode == trans_mode) ++ { ++ /* Below 20 MHz */ ++ pSDHC->sdhc_clk_rate = 0x3; ++ } ++ ++ diag_printf1("pSDHC->sdhc_clk_rate=0x%x\n", pSDHC->sdhc_clk_rate); ++} ++ ++static void read_response(cyg_uint32 response_mode, response_t*response) ++{ ++ cyg_uint32 resp1=0; ++ cyg_uint32 resp2=0; ++ cyg_uint32 resp3=0; ++ cyg_uint32 count; ++ ++ if(response_mode != 0) ++ { ++ /* Stop the clock */ ++ stop_clk(); ++ if((response_mode == RESPONSE_48_CRC) || (response_mode == RESPONSE_48_WITHOUT_CRC)) ++ { ++ resp1 = readl(0x50004000 + 0x34) & 0xffff; ++ resp2 = readl(0x50004000 + 0x34) & 0xffff; ++ resp3 = readl(0x50004000 + 0x34) & 0xffff; ++ ++ response->rsp0 = (resp1 << 24) | (resp2 << 8) | (resp3 >> 8); ++ } ++ else if(response_mode == RESPONSE_136) ++ { ++ resp1 = pSDHC->sdhc_res_fifo & 0xffff; ++ resp2 = pSDHC->sdhc_res_fifo & 0xffff; ++ response->rsp3 = (resp1 << 16) | resp2; ++ resp1 = pSDHC->sdhc_res_fifo & 0xffff; ++ resp2 = pSDHC->sdhc_res_fifo & 0xffff; ++ response->rsp2 = (resp1 << 16) | resp2; ++ ++ resp1 = pSDHC->sdhc_res_fifo & 0xffff; ++ resp2 = pSDHC->sdhc_res_fifo & 0xffff; ++ response->rsp1 = (resp1 << 16) | resp2; ++ ++ resp1 = pSDHC->sdhc_res_fifo & 0xffff; ++ resp2= pSDHC->sdhc_res_fifo & 0xffff; ++ response->rsp0 = (resp1 << 16) | resp2; ++ } ++ ++ /* Clear w1c bits from STATUS register */ ++ pSDHC->sdhc_status |= SDHC_STATUS_CLEAR; ++ } ++ ++ //return status; ++} ++ ++static cyg_uint32 check_response(void) ++{ ++ cyg_uint32 status = PASS; ++ ++ if((pSDHC->sdhc_status & SDHC_STATUS_END_CMD_RESP_MSK) && ++ !(pSDHC->sdhc_status & SDHC_STATUS_TIME_OUT_RESP_MSK) && ++ !(pSDHC->sdhc_status & SDHC_STATUS_RESP_CRC_ERR_MSK)) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ diag_printf("response status: %x Fail!\n", pSDHC->sdhc_status); ++ } ++ return status; ++} ++ ++static cyg_uint32 send_cmd_and_wait_resp(command_t *cmd) ++{ ++ /* Start clock */ ++ start_clk(); ++ ++ /* Clear Interrupt status Register and enable int*/ ++ pSDHC->sdhc_status = 0xFFFFFFFF; ++ pSDHC->sdhc_int_cntr = SDHC_INT; ++ ++ /* Write command index */ ++ pSDHC->sdhc_cmd = cmd->index; ++ ++ /* Write command arg */ ++ pSDHC->sdhc_arg = cmd->arg; ++ ++ /* Write command data control */ ++ pSDHC->sdhc_dat_cont = cmd->data_control; ++ ++ /* Wait for the response of command end */ ++ while(!(pSDHC->sdhc_status & SDHC_STATUS_END_CMD_RESP_MSK) ); ++ ++ /* Mask all interrupts */ ++ pSDHC->sdhc_int_cntr = 0; ++ ++ /* Check if an error occured */ ++ return check_response(); ++} ++ ++static cyg_uint32 card_get_csd (void) ++{ ++ command_t cmd; ++ response_t response; ++ cyg_uint32 status = FAIL; ++ //cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD9 for MMC/SD card */ ++ /* 16bit card address is expected as Argument */ ++ configure_cmd(&cmd,CMD9,card_address,READ,RESPONSE_136, DISABLE, ONE); ++ ++ /* Send Command CMD9 to Extrace CSD register contents */ ++ if(send_cmd_and_wait_resp(&cmd) != FAIL) ++ { ++ /* Read Command response */ ++ read_response (RESPONSE_136, &response); ++ /* Assign Response to CSD Strcuture */ ++ card_specific_data[0] = response.rsp0; ++ card_specific_data[1] = response.rsp1; ++ card_specific_data[2] = response.rsp2; ++ card_specific_data[3] = response.rsp3; ++ diag_printf1("CSD:%x:%x:%x:%x\n", card_specific_data[0], card_specific_data[1], ++ card_specific_data[2], card_specific_data[3]); ++ status = SUCCESS; ++ } ++ ++ return status; ++} ++ ++static cyg_uint32 csd_get_value(cyg_uint32* pcsd, cyg_uint32 start_bit, cyg_uint32 end_bit) ++{ ++ cyg_uint32 index = (start_bit / 32); ++ cyg_uint32 end_index = (end_bit / 32); ++ cyg_uint32 offset = (start_bit) % 32; ++ cyg_uint32 end_offset = (end_bit) % 32; ++ cyg_uint32 value; ++ cyg_uint32 temp; ++ ++ if (index == end_index) { ++ value = pcsd[index] & ((1 << (end_offset + 1)) - (1 << offset)); ++ value = (value >> offset); ++ } else { ++ value = pcsd[index] & (0xFFFFFFFF - (1 << offset) + 1); ++ value = (value >> offset); ++ temp = (1 << (offset + end_bit - start_bit - 31)) - 1; ++ temp = pcsd[index + 1] & temp; ++ value += temp << (32 - offset); ++ } ++ ++ return value; ++} ++ ++static cyg_uint32 mmc_init(void) ++{ ++ cyg_uint32 status = FAIL; ++ command_t cmd; ++ response_t resp; ++ ++ cyg_uint32 card_status = 0; ++ ++ ++ card_address = 0x1<<16; ++ /* get cid of MMC */ ++ /* Configure CMD2 for card */ ++ configure_cmd(&cmd,CMD2,NO_ARG,READ,RESPONSE_136,DISABLE,ONE); ++ ++ /* Send CMD2 to card to determine CID contents */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response(RESPONSE_136, &resp); ++ /* Assign CID values to mmc_cid structures */ ++ card_id.cid0 = resp.rsp0; ++ card_id.cid1 = resp.rsp1; ++ card_id.cid2 = resp.rsp2; ++ card_id.cid3 = resp.rsp3; ++ ++ //status = PASS; ++ } ++ ++ /* get rca of MMC */ ++ /* Configure CMD3 for MMC card */ ++ configure_cmd(&cmd,CMD3,card_address,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ /* Assigns relative address to the card */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response(RESPONSE_48_CRC, &resp); ++ card_status = resp.rsp0; ++ card_status = (((cyg_uint32) (card_status & CARD_STATE)) >> CARD_STATE_SHIFT); ++ if(card_status == IDENT) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ return status; ++ } ++ } ++ ++ card_get_csd(); ++ ++ configure_clk(trans_mode); ++ ++ /*Send MMC to Transfer State */ ++ /* Configure CMD7 for MMC card */ ++ configure_cmd(&cmd,CMD7,card_address,READ,RESPONSE_48_CRC, DISABLE,ONE); ++ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Configure CMD13 to read status of the card becuase CMD7 has R1b response */ ++ configure_cmd(&cmd,CMD13,card_address,READ,RESPONSE_48_CRC,DISABLE,ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response (RESPONSE_48_CRC, &resp); ++ card_status = resp.rsp0; ++ card_status = (((cyg_uint32) (card_status & CARD_STATE)) >> CARD_STATE_SHIFT); ++ ++ if(card_status == TRAN) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status= FAIL; ++ } ++ } ++ } ++ ++ return status; ++} ++ ++static cyg_uint32 check_sd(void) ++{ ++ command_t cmd; ++ //command_response_t response; ++ cyg_uint32 count =0; ++ cyg_uint32 default_rca = 0; ++ cyg_uint32 ocr_value = SD_OCR_VALUE_HV_LC; ++ cyg_uint32 interface_value = 0; ++ cyg_uint32 status = FAIL; ++ response_t resp; ++ ++ configure_cmd(&cmd,CMD8,SD_IF_HV_COND_ARG,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ status = send_cmd_and_wait_resp(&cmd); ++ ++ if (status == PASS) { ++ /* Read Response from CMDRSP0 Register */ ++ read_response(RESPONSE_48_WITHOUT_CRC, &resp); ++ interface_value = resp.rsp0; ++ /* Check if volatge lies in range or not */ ++ if ((interface_value & SD_IF_HV_COND_ARG) == SD_IF_HV_COND_ARG) { ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_HV_HC) & 0xFFFFFFFF); ++ } ++ /* start timer for a delay of 1.5sec, for ACMD41 */ ++ hal_delay_us(1500); ++ status = FAIL; ++ while((count < 3000) && (status != PASS)) { ++ /* Configure CMD55 for SD card */ ++ configure_cmd(&cmd,CMD55,default_rca,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ /* Send CMD55 to SD Memory card*/ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf1("CMD55 FAIL!\n"); ++ break; ++ } else { ++ /* Configure ACMD41 for SD card */ ++ configure_cmd(&cmd,ACMD41,ocr_value,READ,RESPONSE_48_WITHOUT_CRC,DISABLE, ONE); ++ /* SEND ACMD41 to SD Memory card to determine OCR value */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf1("ACMD41 FAIL!\n"); ++ break; ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ read_response(RESPONSE_48_WITHOUT_CRC, &resp); ++ ocr_value = resp.rsp0; ++ diag_printf1("response.cmd_rsp0: 0x%x\n", ocr_value); ++ /* Check if card busy bit is cleared or not */ ++ if(ocr_value & CARD_BUSY) { ++ status = PASS; ++ if((ocr_value & SD_OCR_HC_RES) == SD_OCR_HC_RES) { ++ HighCapacityCard = 1; ++ } else { ++ HighCapacityCard = 0; ++ } ++ } else { ++ count++; ++ diag_printf1("SD: Busy! \n"); ++ } ++ } ++ } ++ hal_delay_us(1000); ++ } ++ } else { ++ /*3.3v test failed, try to test 1.8v mode! */ ++ configure_cmd(&cmd,CMD8,SD_IF_LV_COND_ARG,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ status = send_cmd_and_wait_resp(&cmd); ++ ++ if (status == FAIL) { ++ /* CMD8 failed both in 3.3 & 1.8v, try SD 1.x case - no CMD8, LC, 3.3v only */ ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_HV_LC) & 0xFFFFFFFF); ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ read_response(RESPONSE_48_WITHOUT_CRC, &resp); ++ interface_value = resp.rsp0; ++ /* Check if volatge lies in range or not */ ++ if ((interface_value & SD_IF_LV_COND_ARG) == SD_IF_LV_COND_ARG) { ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_LV_HC) & 0xFFFFFFFF); ++ } ++ } ++ /* start timer for a delay of 1.5sec, for ACMD41 */ ++ hal_delay_us(1500); ++ status = FAIL; ++ while((count < 3000) && (status != PASS)) { ++ /* Configure CMD55 for SD card */ ++ configure_cmd(&cmd,CMD55,default_rca,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ /* Send CMD55 to SD Memory card*/ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf1("CMD55 FAIL!\n"); ++ break; ++ } else { ++ /* Configure ACMD41 for SD card */ ++ configure_cmd(&cmd,ACMD41,ocr_value,READ,RESPONSE_48_WITHOUT_CRC,DISABLE, ONE); ++ /* SEND ACMD41 to SD Memory card to determine OCR value */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf1("ACMD41 FAIL!\n"); ++ break; ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ read_response(RESPONSE_48_WITHOUT_CRC, &resp); ++ ocr_value = resp.rsp0; ++ diag_printf1("response.cmd_rsp0: 0x%x\n", ocr_value); ++ /* Check if card busy bit is cleared or not */ ++ if(ocr_value & CARD_BUSY) { ++ if((ocr_value & SD_OCR_HC_RES) == SD_OCR_HC_RES) { ++ HighCapacityCard = 1; ++ } else { ++ HighCapacityCard = 0; ++ } ++ status = PASS; ++ } else { ++ count++; ++ diag_printf1("SD: Busy! \n"); ++ } ++ } ++ } ++ hal_delay_us(1000); ++ } ++ } ++ ++ return status; ++} ++ ++ ++static cyg_uint32 sd_init(cyg_uint32 bus_width) ++{ ++ cyg_uint32 status = FAIL; ++ command_t cmd; ++ response_t resp; ++ cyg_uint32 card_status = 0; ++ cyg_uint32 read_resp = 0; ++ ++ card_address = 0; ++ ++ /* get cid of MMC */ ++ /* Configure CMD2 for card */ ++ configure_cmd(&cmd,CMD2,NO_ARG,READ,RESPONSE_136,DISABLE,ONE); ++ ++ /* Send CMD2 to card to determine CID contents */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response(RESPONSE_136, &resp); ++ /* Assign CID values to mmc_cid structures */ ++ card_id.cid0 = resp.rsp0; ++ card_id.cid1 = resp.rsp1; ++ card_id.cid2 = resp.rsp2; ++ card_id.cid3 = resp.rsp3; ++ ++ //status = PASS; ++ } ++ ++ /* get rca of card */ ++ /* Configure CMD3 for card */ ++ configure_cmd(&cmd,CMD3,NO_ARG,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ /* Assigns relative address to the card */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response(RESPONSE_48_CRC, &resp); ++ card_status = resp.rsp0; ++ card_address = ((cyg_uint32) (card_status & (0xffff0000))); ++ card_status = (((cyg_uint32) (card_status & CARD_STATE)) >> CARD_STATE_SHIFT); ++ if(card_status == IDENT) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ return status; ++ } ++ } ++ ++ card_get_csd(); ++ configure_clk(trans_mode); ++ ++ /*Send card to Transfer State */ ++ /* Configure CMD7 for card */ ++ configure_cmd(&cmd,CMD7,card_address,READ,RESPONSE_48_CRC, DISABLE,ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Configure CMD13 to read status of the card becuase CMD7 has R1b response */ ++ configure_cmd(&cmd,CMD13,card_address,READ,RESPONSE_48_CRC, ++ DISABLE,ONE); ++ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response (RESPONSE_48_CRC, &resp); ++ card_status = resp.rsp0; ++ card_status = (((cyg_uint32) (card_status & CARD_STATE)) >> CARD_STATE_SHIFT); ++ if(card_status == TRAN) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ } ++ } ++ } ++ ++ ++ /* set bus width */ ++ if ((bus_width == 4 ) || (bus_width == 1)) ++ { ++ /* Configure CMD55 for SD card */ ++ configure_cmd(&cmd,CMD55,card_address,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ /* Issue CMD55 to SD Memory card*/ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response(RESPONSE_48_CRC, &resp); ++ read_resp = resp.rsp0; ++ if(read_resp & SD_R1_APP_CMD_MSK) ++ { ++ bus_width = (bus_width>>1); ++ ++ /* Configure ACMD6 for SD card */ ++ configure_cmd(&cmd,ACMD6,bus_width,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ /* Send ACMD6 to SD Memory card*/ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ return status; ++ } ++ else ++ { ++ status = PASS; ++ } ++ } ++ } ++ } ++ ++ return status; ++} ++ ++static cyg_uint32 check_mmc(void) ++{ ++ command_t cmd; ++ response_t resp; ++ //cyg_uint32 response; ++ cyg_uint32 count=0; ++ cyg_uint32 ocr_value=0; ++ cyg_uint32 status = FAIL; ++ ++ ocr_value = (cyg_uint32) ((MMC_OCR_VALUE) & 0xFFFFFFFF); ++ while((count < 3000) && (status != PASS)) { ++ /* Configure CMD1 for MMC card */ ++ configure_cmd(&cmd, CMD1, ocr_value, READ, RESPONSE_48_WITHOUT_CRC,DISABLE, ONE); ++ ++ /* Issue CMD1 to MMC card to determine OCR value */ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) { ++ status = FAIL; ++ count++; ++ diag_printf1("CMD1 FAIL!\n"); ++ break; ++ //continue; ++ } else { ++ read_response(RESPONSE_48_WITHOUT_CRC, &resp); ++ ocr_value = resp.rsp0; ++ ++ /* Check if card busy bit is cleared or not */ ++ if(ocr_value & CARD_BUSY) { ++ status = PASS; ++ if((ocr_value & MMC_OCR_HC_RES) == MMC_OCR_HC_RES) { ++ HighCapacityCard = 1; ++ } else if((ocr_value & MMC_OCR_LC_RES) == MMC_OCR_LC_RES) { ++ HighCapacityCard = 0; ++ } ++ } else { ++ count++; ++ } ++ } ++ } ++ ++ return status; ++} ++ ++static cyg_uint32 check_card(cyg_uint32 bus_width) ++{ ++ ++ cyg_uint32 status = FAIL; ++ Card_Mode = NONE; ++ ++ //wait ++ hal_delay_us(2000); ++ diag_printf1("check SD\n"); ++ if(check_sd() == PASS){ ++ Card_Mode = SD; ++ diag_printf1("SD init\n"); ++ status = sd_init(bus_width); ++ Card_type = ((card_specific_data[3] & CSD_STRUCT_MSK)? SD_CSD_2_0: SD_CSD_1_0); ++ ++ /* Card Command Class */ ++ CCC = csd_get_value(card_specific_data, 84, 95); ++ } else { ++ //wait ++ hal_delay_us(2000); ++ diag_printf1("check MMC\n"); ++ if(check_mmc() == PASS){ ++ Card_Mode = MMC; ++ ++ status = mmc_init(); ++ Card_type = ((card_specific_data[3] & CSD_STRUCT_MSK) >> CSD_STRUCT_SHIFT) + SD_CSD_2_0; ++ /* Card Command Class */ ++ CCC = csd_get_value(card_specific_data, 84, 95); ++ } ++ } ++ return status; ++} ++ ++static void sdhc_init(cyg_uint32 base_address) ++{ ++ cyg_uint32 iomux_base = 0x43FAC000; ++ cyg_uint32 gpio_base = 0x53FA4000; ++ cyg_uint32 iomux_sw_mux_ctl1 = readl(iomux_base + 0x18); ++ cyg_uint32 iomux_sw_mux_ctl2 = readl(iomux_base + 0x1C); ++ unsigned long reg; ++ ++ iomux_sw_mux_ctl1 &= 0x000000FF; ++ iomux_sw_mux_ctl1 |= 0x12121200; ++ writel(iomux_sw_mux_ctl1, iomux_base + 0x18); ++ ++ iomux_sw_mux_ctl2 &= 0xFF000000; ++ iomux_sw_mux_ctl2 |= 0x00121012; ++ writel(iomux_sw_mux_ctl2, iomux_base + 0x1C); ++ ++ writel(0x0A529485, iomux_base + 0x168); ++ writel(0x0A5294A5, iomux_base + 0x16c); ++ ++ /* Initialize base address */ ++ pSDHC = (psdhc_t)base_address; ++} ++ ++static void sdhc_reset(void) ++{ ++ pSDHC->sdhc_clk = SDHC_CLK_RESET; ++ pSDHC->sdhc_clk = SDHC_CLK_RESET | SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++ pSDHC->sdhc_clk = SDHC_CLK_STOP; ++} ++ ++static cyg_uint32 card_reset(void) ++{ ++ command_t cmd; ++ ++ configure_clk(iden_mode); ++ ++ /*set size of read and response fifo */ ++ //pSDHC->sdhc_read_to = 0xffff; ++ pSDHC->sdhc_read_to = 0x2DB4; ++ pSDHC->sdhc_response_to = 0xff; ++ hal_delay_us(20000); ++ ++ /* CMD0 to reset SD/MMC cards */ ++ configure_cmd(&cmd,CMD0,NO_ARG,READ, RESPONSE_NO, DISABLE, ONE); ++ ++ return send_cmd_and_wait_resp(&cmd); ++} ++ ++static void wait_transfer_done(cyg_uint32 mask) ++{ ++ /* Wait interrupt (WRITE_OP_DONE/READ_OP_DONE) */ ++ while(!(pSDHC->sdhc_status & mask)); ++} ++ ++static cyg_uint32 check_data(cyg_uint32 done_mask, cyg_uint32 crc_err_code_mask, cyg_uint32 crc_err_mask) ++{ ++ cyg_uint32 status = FAIL; ++ /* Check whether the interrupt is an OP_DONE or a data time out or a CRC error */ ++ if((pSDHC->sdhc_status & done_mask) && ++ !(pSDHC->sdhc_status & crc_err_code_mask) && ++ !(pSDHC->sdhc_status & crc_err_mask)) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ } ++ return status; ++} ++ ++static cyg_uint32 check_card_status(void) ++{ ++ command_t cmd; ++ cyg_uint32 status = PASS; ++ cyg_uint32 card_state; ++ cyg_uint32 read_resp; ++ response_t resp; ++ //cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ configure_cmd(&cmd,CMD13,card_address,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ } ++ else ++ { ++ /* Read Command response */ ++ read_response (RESPONSE_48_CRC, &resp); ++ read_resp = resp.rsp0; ++ card_state = ((cyg_uint32) (read_resp & CARD_STATE) >> CARD_STATE_SHIFT); ++ ++ if(card_state == TRAN) ++ { ++ status = PASS; ++ } ++ else ++ { ++ status = FAIL; ++ } ++ } ++ return status; ++} ++ ++ ++ ++/*========================================================================== ++FUNCTION: static cyg_uint32 card_get_capacity_size(void) ++DESCRIPTION: ++ this function will analize MMC/SD CSD register and return the capacity size (in unit of KB) ++ ++ARGUMENTS PASSED: ++ None ++ ++RETURN VALUE: ++ cyg_uint32 ++ ++PRE-CONDITIONS: ++ None ++ ++POST-CONDITIONS: ++ None ++ ++Detailed Description: ++==============================================================================*/ ++cyg_uint32 card_get_capacity_size (void) ++{ ++ cyg_uint32 capacity = 0; ++ cyg_uint32 c_size, c_size_mult, blk_len; ++ ++ if(!card_specific_data[0] && !card_specific_data[1] && !card_specific_data[2] && !card_specific_data[3]) ++ diag_printf("WARNINGS:card_init should be done first!\n"); ++ ++ switch(Card_type) ++ { ++ case SD_CSD_1_0: ++ case MMC_CSD_1_0: ++ case MMC_CSD_1_1: ++ case MMC_CSD_1_2: ++ c_size_mult = csd_get_value(card_specific_data, 47, 49); ++ c_size = csd_get_value(card_specific_data, 62, 73); ++ blk_len = csd_get_value(card_specific_data, 80, 83); ++ capacity = (c_size + 1) << (c_size_mult + 2 + blk_len - 10); ++ diag_printf1("c_size=0x%x, c_size_mult=0x%x, blk_len=0x%x, capacity(KB)=0x%x\n", ++ c_size, c_size_mult, blk_len, capacity); ++ break; ++ case SD_CSD_2_0: ++ c_size = csd_get_value(card_specific_data, 48, 69); ++ capacity = (c_size + 1) * 512; ++ diag_printf1("card capacity2=0x%x\n", capacity); ++ break; ++ default: ++ break; ++ } ++ ++ return capacity; ++} ++ ++cyg_uint32 mxcmci_init (cyg_uint32 bus_width, cyg_uint32 base_address) ++{ ++ sdhc_init(base_address); ++ ++ /* Software Reset to SDHC */ ++ sdhc_reset(); ++ ++ /* Software Reset to card */ ++ card_reset(); ++ ++ return check_card(bus_width); ++} ++ ++cyg_uint32 mmc_data_read (cyg_uint32 *ram_ptr, cyg_uint32 length, cyg_uint32 offset) ++{ ++ command_t cmd; ++ cyg_uint32 len; ++ cyg_uint32 status = PASS; ++ cyg_uint32 i, j; ++ cyg_uint32 blk_len = BLOCK_LEN; ++ ++ diag_printf1("\ncard_data_read !-- offset: %x, length: %x \n", offset, length); ++ ++ len = (length + BLOCK_LEN - 1) & (~(BLOCK_LEN - 1)); ++ ++ if (HighCapacityCard) { ++ offset = offset / 512; ++ blk_len = BLOCK_LEN / 512; ++ } ++ ++ /* Configure SDHC block and number of blocks */ ++ pSDHC->sdhc_blk_len = BLOCK_LEN; ++ pSDHC->sdhc_nob = 0x1; ++ ++ /* Configure CMD16 to set block length as 512 bytes.*/ ++ configure_cmd(&cmd,CMD16,BLOCK_LEN,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ diag_printf1("CMD16 Fail!\n"); ++ } ++ else ++ { ++ while(len != 0 && !status) ++ { ++ //check card status whether it is in transfer mode, so as to start next transfer ++ while((status = check_card_status())!=PASS); ++ ++ diag_printf1("length left: %x \n", len); ++ ++ /* Send CMD17 for single block read */ ++ configure_cmd(&cmd,CMD17,offset,READ,RESPONSE_48_CRC, ENABLE, ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status= FAIL; ++ diag_printf1("CMD17 Fail!\n"); ++ } ++ else ++ { ++ /* Enable int */ ++ pSDHC->sdhc_int_cntr = SDHC_INT; ++ for(i = 0; i < BLOCK_LEN/16; i++) ++ { ++ /* Wait for BRR bit to be set */ ++ while(!(pSDHC->sdhc_status & SDHC_STATUS_BUF_READ_RDY_MSK)) { ++ hal_delay_us(10); ++ } ++ for(j=0;j<4;j++) ++ { ++ /* Read 32 bit data from buffer access fifo */ ++ *ram_ptr = pSDHC->sdhc_buffer_access; ++ ram_ptr++; ++ } ++ } ++ /* Wait for transfer complete */ ++ wait_transfer_done(SDHC_STATUS_READ_OP_DONE_MSK); ++ ++ /* Check for status errors (crc or timeout)*/ ++ status = check_data(SDHC_STATUS_READ_OP_DONE_MSK, SDHC_STATUS_TIME_OUT_READ, SDHC_STATUS_READ_CRC_ERR_MSK); ++ ++ offset = offset + blk_len; ++ len = len - BLOCK_LEN; ++ diag_printf1("length left3: %x \n", len); ++ } ++ } ++ } ++ diag_printf1("End of card data read!\n"); ++ return status; ++} ++ ++cyg_uint32 mmc_data_write (cyg_uint32 *ram_ptr, cyg_uint32 length, cyg_uint32 offset) ++{ ++ command_t cmd; ++ cyg_uint32 len; ++ cyg_uint32 status = PASS; ++ cyg_uint32 i = 0; ++ cyg_uint32 blk_len = BLOCK_LEN; ++ ++ len = (length + BLOCK_LEN - 1) & (~(BLOCK_LEN - 1)); ++ ++ /* Configure SDHC block and number of blocks */ ++ pSDHC->sdhc_blk_len = BLOCK_LEN; ++ pSDHC->sdhc_nob = 0x1; ++ ++ /* high capacity card uses sector mode */ ++ if (HighCapacityCard) { ++ offset = offset / 512; ++ blk_len = BLOCK_LEN / 512; ++ } ++ ++ /* Send CMD16 to set block length as 512 bytes.*/ ++ configure_cmd(&cmd,CMD16,BLOCK_LEN,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ } ++ else ++ { ++ while(len != 0 && !status) ++ { ++ //check card status whether it is in transfer mode, so as to start next transfer ++ while((status = check_card_status())!=PASS); ++ /* Comfigure command CMD24 for block write--write address */ ++ configure_cmd(&cmd,CMD24,offset,WRITE,RESPONSE_48_CRC, ENABLE, ONE); ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ } ++ else ++ { ++ /* Enable int */ ++ pSDHC->sdhc_int_cntr = SDHC_INT; ++ ++ for(i = 0; i < (BLOCK_LEN)/4; i++) ++ { ++ /* Wait for BWR bit to be set */ ++ while(!(pSDHC->sdhc_status & SDHC_STATUS_BUF_WRITE_RDY_MSK)); ++ //copy data from ram to sdhc buffer access fifo ++ pSDHC->sdhc_buffer_access = *ram_ptr; ++ ram_ptr++; ++ } ++ ++ /* Wait for transfer done */ ++ wait_transfer_done(SDHC_STATUS_WRITE_OP_DONE_MSK); ++ ++ /* Check for status errors (crc or timeout)*/ ++ status = check_data(SDHC_STATUS_WRITE_OP_DONE_MSK, 0, SDHC_STATUS_WRITE_CRC_ERR_MSK); ++ ++ len = len - BLOCK_LEN; ++ offset += blk_len; ++ } ++ } ++ } ++ return status; ++} ++ ++cyg_uint32 mmc_data_erase (cyg_uint32 offset, cyg_uint32 size) ++{ ++ command_t cmd; ++ cyg_uint32 startEraseBlockCmd; ++ cyg_uint32 endEraseBlockCmd; ++ cyg_uint32 startBlock = offset/BLOCK_LEN; ++ cyg_uint32 endBlock = (offset+size)/BLOCK_LEN; ++ cyg_uint32 status = FAIL; ++ ++ /* Fix erase operation on MX31/32 */ ++ return 0; ++ if(Card_Mode == MMC) { ++ startBlock *=BLOCK_LEN; ++ endBlock *= BLOCK_LEN; ++ startEraseBlockCmd = CMD35; ++ endEraseBlockCmd = CMD36; ++ } ++ else if(Card_Mode == SD) { ++ startBlock *=BLOCK_LEN; ++ endBlock *= BLOCK_LEN; ++ startEraseBlockCmd = CMD32; ++ endEraseBlockCmd = CMD33; ++ } ++ if (HighCapacityCard) { ++ startBlock /= BLOCK_LEN; ++ endBlock /= BLOCK_LEN; ++ } ++ ++ /* Configure start erase command to set first block*/ ++ configure_cmd(&cmd,startEraseBlockCmd,startBlock,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ if((status = send_cmd_and_wait_resp(&cmd)) == PASS){ ++ ++ /* Configure end erase command to set end block*/ ++ configure_cmd(&cmd,endEraseBlockCmd,endBlock,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ if((status = send_cmd_and_wait_resp(&cmd)) == PASS){ ++ /* Comfigure command to start erase*/ ++ configure_cmd(&cmd,CMD38,0,READ,RESPONSE_48_CRC, DISABLE, ONE); ++ if((status = send_cmd_and_wait_resp(&cmd)) == PASS){ ++ //wait for completion ++ return status; ++ } ++ } ++ } ++ ++ return status; ++} ++ ++cyg_uint32 card_flash_query(void* data) ++{ ++ command_t cmd; ++ cyg_uint32 status = PASS; ++ response_t response; ++ ++ // Configure CMD2 for card No Argument is expected for CMD2 ++ configure_cmd(&cmd,CMD2,NO_ARG,READ,RESPONSE_136, DISABLE, ONE); ++ ++ // Send CMD2 to card to determine CID contents ++ if(send_cmd_and_wait_resp(&cmd) == FAIL) ++ { ++ status = FAIL; ++ diag_printf("%s: can't send query command\n", __FUNCTION__); ++ } ++ else ++ { ++ cyg_uint32* d = (cyg_uint32*)data; ++ // Read Command response ++ read_response (RESPONSE_136, &response); ++ ++ // Assign CID values to mmc_cid structures ++ *d++ = response.rsp0; ++ *d++ = response.rsp1; ++ *d++= response.rsp2; ++ *d= response.rsp3; ++ ++ // Assign cid_request as SUCCESS ++ status = PASS; ++ } ++ diag_printf( "%s(PASS?=%d):(ID=0x%x: 0x%x, 0x%x, 0x%x)\n", ++ __FUNCTION__, status,*(cyg_uint32*)(data), *(cyg_uint32*)((cyg_uint32)data+4), ++ *(cyg_uint8*)((cyg_uint32)data+8), *(cyg_uint8*)((cyg_uint32)data+12)); ++ return status; ++} ++ ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxc_mmc.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxc_mmc.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxc_mmc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxc_mmc.c 2010-01-26 17:33:13.042961508 +0000 +@@ -0,0 +1,350 @@ ++// ========================================================================== ++// ++// mxc_mmc.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// Support SD/MMC cards based on eSDHC controller. ++// only base functionality is implemented: Card init, read and write. ++// Erase and write protection are not supported so far. ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++#define _FLASH_PRIVATE_ ++#include ++#include ++ ++#if defined(CYGPKG_HAL_ARM_MX31ADS) || defined(CYGPKG_HAL_ARM_MX31_3STACK) ++ #include ++#endif ++ ++#if defined(CYGPKG_HAL_ARM_MX25_3STACK) || defined(CYGPKG_HAL_ARM_MX35_3STACK) || defined(CYGPKG_HAL_ARM_MX37_3STACK) || defined(CYGPKG_HAL_ARM_MX51) ++ #include ++#endif ++ ++mxc_mmc_check_sdhc_boot_slot *check_sdhc_slot = NULL; ++ ++//hardware init for MMC card ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_init(void) ++#else ++int mmcflash_hwr_init(void) ++#endif ++{ ++ cyg_uint32 status = FAIL; ++ cyg_uint32 capacity = 0; ++ int i = 5; ++ int SDHCbootslot = 0; ++ unsigned int EsdhcRegBase = 0; ++ ++ if (check_sdhc_slot) { ++ SDHCbootslot = check_sdhc_slot(READ_PORT_FROM_FUSE, &EsdhcRegBase); ++ if(!SDHCbootslot){ ++ return FAIL; ++ } ++ } else { ++ /* Default to MMC 1 */ ++ EsdhcRegBase = MMC_SDHC1_BASE_ADDR; ++ } ++ ++ while (status != SUCCESS && i--) { ++ hal_delay_us(100000); ++ status = mxcmci_init(1, EsdhcRegBase); ++ } ++ ++ if (FAIL == status) { ++ diag_printf("Error: Card initialization failed!\n"); ++ return status; ++ } ++ diag_printf("Card initialization successful!\n"); ++ //set flash_info structure ++ externC struct flash_info flash_info; ++ flash_dprintf(FLASH_DEBUG_MAX,"%s: status=%d\n", __FUNCTION__, status); ++ capacity = card_get_capacity_size(); // in unit of KB ++ diag_printf("Actual capacity of the card is %dKB\n", capacity); ++ //if the capacity size is larger than 2G or equals zero, force to be 2G ++ if (capacity > 0x200000 || capacity == 0) { ++ capacity = 0x200000; ++ } ++ diag_printf("Redboot uses %dKB\n", capacity); ++ ++ flash_info.block_size = 0x20000; // = 128KB ++ flash_info.blocks = capacity / 128; ++ flash_info.start = (void *)MXC_MMC_BASE_DUMMY; ++ flash_info.end = (void *)(MXC_MMC_BASE_DUMMY + flash_info.block_size * flash_info.blocks); ++ ++ return status; ++} ++ ++ ++// Read data into buffer ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_read_buf(void* addr, void* data, int len) ++#else ++int mmcflash_read_buf(void* addr, void* data, int len) ++#endif ++{ ++ flash_dprintf(FLASH_DEBUG_MAX,"%s:Debug:1:addr=%X, data=%X, len=%d\n", __FUNCTION__, (cyg_uint32)addr, (cyg_uint32)data, len); ++ return mmc_data_read(data, len, (cyg_uint32)addr); ++} ++ ++ ++// Get CID to pointer data (should hold 4*4 byte space) ++#ifndef MXCFLASH_SELECT_MULTI ++void flash_query(void* data) ++#else ++void mmcflash_query(void* data) ++#endif ++{ ++ return card_flash_query(data); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_map_error(int e) ++#else ++int mmcflash_hwr_map_error(int e) ++#endif ++{ ++ return e; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++bool flash_code_overlaps(void *start, void *end) ++#else ++bool mmcflash_code_overlaps(void *start, void *end) ++#endif ++{ ++ extern char _stext[], _etext[]; ++ ++ bool ret = ((((unsigned long)&_stext >= (unsigned long)start) && ++ ((unsigned long)&_stext < (unsigned long)end)) || ++ (((unsigned long)&_etext >= (unsigned long)start) && ++ ((unsigned long)&_etext < (unsigned long)end))); ++ flash_dprintf(FLASH_DEBUG_MAX,"%s: flash code overlap::%d\n", __FUNCTION__, ret); ++ return ret; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_erase_block(void* block, unsigned int size) ++#else ++int mmcflash_erase_block(void* block, unsigned int size) ++#endif ++{ ++ flash_dprintf(FLASH_DEBUG_MAX,"%s:Debug:1:block=0x%X, size=%d\n", __FUNCTION__, (cyg_uint32)block, size); ++ // No need to erase for MMC/SD. Skipping ... ++ return 0; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_program_buf(void* addr, void* data, int len) ++#else ++int mmcflash_program_buf(void* addr, void* data, int len) ++#endif ++{ ++ flash_dprintf(FLASH_DEBUG_MAX,"%s:Debug:1:addr=0x%X, data=0x%X, len=%d\n", __FUNCTION__, (cyg_uint32)addr, (cyg_uint32)data, len); ++ return mmc_data_write((cyg_uint32*)data, len, (cyg_uint32)addr); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_lock_block(void* block) ++#else ++int mmcflash_lock_block(void* block) ++#endif ++{ ++ //not support yet ++ return 0; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_unlock_block(void* block, int block_size, int blocks) ++#else ++int mmcflash_unlock_block(void* block, int block_size, int blocks) ++#endif ++{ ++ //not support yet ++ return 0; ++} ++ ++void mxc_mmc_print_info(void) ++{ ++ extern card_type Card_type; ++ cyg_uint32 i = 0; ++ cyg_uint8* cmd_class[] = { ++ "basic", //class 0 ++ "reserved", //class 1 ++ "block-read", //class 2 ++ "reserved", //class 3 ++ "block-write", //class 4 ++ "erase", //class 5 ++ "write-protect", //class 6 ++ "lock", //class 7 ++ "app-command", //class 8 ++ "IO-mode", //class 9 ++ "switch", //class 10 ++ "reserved" //class 11 ++ }; ++ ++ switch (Card_type) { ++ case SD_CSD_1_0: ++ diag_printf("\nBooting from [SD card, CSD Version 1.0]\n"); ++ break; ++ case SD_CSD_2_0: ++ diag_printf("\nBooting from [SD card, CSD Version 2.0]\n"); ++ break; ++ case MMC_CSD_1_0: ++ diag_printf("\nBooting from [MMC card, CSD Version 1.0]\n"); ++ break; ++ case MMC_CSD_1_1: ++ diag_printf("\nBooting from [MMC card, CSD Version 1.1]\n"); ++ break; ++ case MMC_CSD_1_2: ++ diag_printf("\nBooting from [MMC card, CSD Version 1.2]\n"); ++ break; ++ case MMC_UNKNOWN: ++ diag_printf("\nBooting from [MMC card (?) ]\n"); ++ break; ++ default: ++ diag_printf("\nBooting from [unknown version card ]\n"); ++ break; ++ } ++ diag_printf("Supporting Card Command Class: "); ++ for (;i<12;i++) { ++ if (CCC & (1 << i)) ++ diag_printf("%s, ", cmd_class[i]); ++ } ++ ++ diag_printf("\n\n"); ++} ++ ++static void do_mmc_op(int argc, char *argv[]); ++RedBoot_cmd("sdhc", ++ "Read/Write MMC/SD card", ++ " ", ++ do_mmc_op ++ ); ++ ++static void do_mmc_op(int argc, char *argv[]) ++{ ++ unsigned int ram, port, flash, len; ++ unsigned char op; ++ int stat = -1, ret; ++ int i = 5; ++ unsigned int EsdhcRegBase = 0; ++ cyg_uint32 status = FAIL; ++ ++ if (argc != 6) { ++ diag_printf("\tRead: sdhc \n"); ++ diag_printf("\tWrite: sdhc \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)&port, &argv[1], ":")) { ++ diag_printf("Error: Invalid Port number\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[2]), (unsigned long *)&ram, &argv[2], ":")) { ++ diag_printf("Error: Invalid ram parameter\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[3]), (unsigned long *)&flash, &argv[3], ":")) { ++ diag_printf("Error: Invalid flash parameter\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[4]), (unsigned long *)&len, &argv[4], ":")) { ++ diag_printf("Error: Invalid length parameter\n"); ++ return; ++ } ++ ++ op = argv[5][0]; ++ ++ if (check_sdhc_slot) { ++ ret = check_sdhc_slot(port, &EsdhcRegBase); ++ if(!ret){ ++ return; ++ } ++ } else { ++ diag_printf("This command is not implemented on this platform!\n"); ++ return; ++ } ++ while (status != SUCCESS && i--) { ++ hal_delay_us(100000); ++ status = mxcmci_init(1, EsdhcRegBase); ++ } ++ ++ if (FAIL == status) { ++ diag_printf("Error: Card initialization failed!\n"); ++ return; ++ } ++ ++ switch (op) { ++ case 'r': ++ case 'R': ++ diag_printf("Reading SDHC%d 0x%x [0x%x bytes] -> ram 0x%x\n", port, flash, len, ram); ++ //stat = spi_nor_read((void *)flash, (void *)ram, len); ++ stat = mmcflash_read_buf((void *)flash, (void *)ram, len); ++ break; ++ case 'w': ++ case 'W': ++ diag_printf("Writing SDHC%d 0x%x [0x%x bytes] <- ram 0x%x\n", port, flash, len, ram); ++ //stat = spi_nor_program_buf((void *)flash, (void *)ram, len); ++ stat = mmcflash_program_buf((void *)flash, (void *)ram, len); ++ break; ++ default: ++ diag_printf("Error: unknown operation: 0x%02x\n", op); ++ } ++ diag_printf("%s\n\n", (stat == 0)? "SUCCESS": "FAILED"); ++ return; ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxc_nfc.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxc_nfc.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxc_nfc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxc_nfc.c 2010-01-26 17:33:13.052960382 +0000 +@@ -0,0 +1,1867 @@ ++//========================================================================== ++// ++// mxc_nfc.c ++// ++// Flash programming to support NAND flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 Initial version ++// Date: 2007-12-20 Update to support 4K page and bbt management. ++// Purpose: ++// Description: ++// -- Add bad block management according to Linux NAND MTD implementation. ++// Reference linux/drivers/mtd/nand/nand_bbt.c by Thomas Gleixner ++// Summary: ++// 1. Last 4 blocks are reserved for one main BBT and one ++// mirror BBT (2 spare ones just in case a block turns bad.) ++// 2. The main BBT block's spare area starts with "Bbt0" followed ++// by a version number starting from 1. ++// 3. The mirror BBT block's spare area starts with "1tbB" followed ++// by a version number also starting from 1. ++// 4. The actual main area, starting from first page in the BBT block, ++// is used to indicate if a block is bad or not through 2bit/block: ++// * The table uses 2 bits per block ++// * 11b: block is good ++// * 00b: block is factory marked bad ++// * 01b, 10b: block is marked bad due to wear ++// Redboot operations: During boot, it searches for the marker for ++// either main BBT or mirror BBT based on the marker: ++// case 1: Neither table is found: ++// Do the bad block scan of the whole flash with ECC off. Use ++// manufactor marked BI field to decide if a block is bad and ++// then build the BBT in RAM. Then write this table to both ++// main BBT block and mirror BBT block. ++// case 2: Only one table is found: ++// Load the BBT table from the flash and stored in the RAM. ++// Then build the 2nd BBT table in the flash. ++// case 3: If both tables found, load the one with higher version in the ++// RAM and then update the block with older BBT info with the ++// newer one. If same version, just then read out the table in ++// RAM. ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++static int nfc_debug = 0; ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++#include ++#define _FLASH_PRIVATE_ ++#include ++ ++#include ++ ++/* Search good / bad pattern on the first page only */ ++#define NAND_BBT_SCAN1STPAGE 0x00000001 ++/* Search good / bad pattern on the first and the second page */ ++#define NAND_BBT_SCAN2NDPAGE 0x00000002 ++/* Search good / bad pattern on the last page only */ ++#define NAND_BBT_SCANLSTPAGE 0x00000004 ++// todo: move to top ++#define ECC_FORCE_ON 1 ++#define ECC_FORCE_OFF 2 ++ ++enum blk_bad_type ++{ ++ BLK_BAD_FACTORY = 0, ++ BLK_BAD_RUNTIME = 1, ++}; ++ ++//#define diag_printf1 diag_printf ++#define diag_printf1(fmt,args...) ++#define MXC_UNLOCK_BLK_END 0xFFFF ++ ++extern unsigned int hal_timer_count(void); ++int nfc_program_region(u32 addr, u32 buf, u32 len); ++int nfc_erase_region(u32 addr, u32 len, u32 skip_bad, bool verbose); ++ ++static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u32 buf, u32 ecc_force, u8 format); ++static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line, u32 num_of_chips); ++static int nfc_erase_blk(u32 ra); ++static void print_page (u32 addr, bool spare_only); ++static int nfc_read_page(u32 pg_no, u32 pg_off, u32 cs_line); ++static int mxc_nfc_scan(bool lowlevel); ++static void read_nflash_id(void* id, u32 cs_line); ++static int nfc_program_blk(u32 ra, u32 buf, u32 len, u8 file_format); ++ ++// globals ++static int nand_flash_index = -1; ++static int g_ecc_enable = true; ++static int g_spare_only_read_ok = true; ++static int g_nfc_debug_level = NFC_DEBUG_MIN; ++static bool g_nfc_debug_measure = false; ++static bool g_is_2k_page = false; ++static bool g_is_4k_page = false; ++static unsigned int g_nfc_version = 0x10; // version 1.0 ++static int num_of_nand_chips = 1; ++static int num_of_nand_chips_for_nandsize = 1; ++static int scale_block_cnt = 1; ++ ++#if defined(NFC_V2_0) || defined(NFC_V2_1) ++#include ++#elif defined(NFC_V3_0) ++#include ++#else ++#include ++#endif ++ ++#ifndef NAND_LAUNCH_REG ++#define NAND_LAUNCH_REG 0xDEADEEEE ++#define NAND_CONFIGURATION1_REG 0xDEADEEEE ++#define NFC_FLASH_CONFIG2_REG 0xDEADEEEE ++#define NFC_FLASH_CONFIG2_ECC_EN 0xDEADEEEE ++#define write_nfc_ip_reg(a, b) ++#endif ++ ++#define nfc_printf(level, args...) \ ++ do { \ ++ if (g_nfc_debug_level >= level) \ ++ diag_printf(args); \ ++ } while(0) ++ ++#ifndef MXCFLASH_SELECT_MULTI ++void flash_query(void* data) ++#else ++void nandflash_query(void* data) ++#endif ++{ ++ read_nflash_id(data, 0); ++ nfc_printf(NFC_DEBUG_MAX, "%s(ID=0x%x: 0x%x, 0x%x, 0x%x)\n", ++ __FUNCTION__, *(u8*)(data), *(u8*)((u32)data+1), ++ *(u8*)((u32)data+2), *(u8*)((u32)data+3)); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_program_buf(void* addr, void* data, int len) ++#else ++int nandflash_program_buf(void* addr, void* data, int len) ++#endif ++{ ++ return nfc_program_region((u32) addr, (u32) data, (u32) len); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_erase_block(void* block, unsigned int size) ++#else ++int nandflash_erase_block(void* block, unsigned int size) ++#endif ++{ ++ return nfc_erase_region((u32) block, size, 1, 0); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++bool flash_code_overlaps(void *start, void *end) ++#else ++bool nandflash_code_overlaps(void *start, void *end) ++#endif ++{ ++ extern unsigned char _stext[], _etext[]; ++ ++ return ((((unsigned long)&_stext >= (unsigned long)start) && ++ ((unsigned long)&_stext < (unsigned long)end)) || ++ (((unsigned long)&_etext >= (unsigned long)start) && ++ ((unsigned long)&_etext < (unsigned long)end))); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_map_error(int e) ++#else ++int nandflash_hwr_map_error(int e) ++#endif ++{ ++ return e; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_lock_block(void* block) ++#else ++int nandflash_lock_block(void* block) ++#endif ++{ ++ // Not supported yet ++ return 0; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_unlock_block(void* block, int block_size, int blocks) ++#else ++int nandflash_unlock_block(void* block, int block_size, int blocks) ++#endif ++{ ++ // Not supported yet ++ return 0; ++} ++ ++//---------------------------------------------------------------------------- ++// Now that device properties are defined, include magic for defining ++// accessor type and constants. ++#include ++ ++static flash_dev_info_t *flash_dev_info; ++static const flash_dev_info_t supported_devices[] = { ++#include ++}; ++#define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t)) ++ ++#define COL_CYCLE flash_dev_info->col_cycle ++#define ROW_CYCLE flash_dev_info->row_cycle ++#define NF_PG_SZ ((flash_dev_info->page_size) * num_of_nand_chips) ++#define NF_PG_PER_BLK flash_dev_info->pages_per_block ++#define NF_DEV_SZ ((flash_dev_info->device_size) * num_of_nand_chips_for_nandsize) ++#define NF_BLK_SZ ((flash_dev_info->block_size) * num_of_nand_chips) ++#define NF_BLK_CNT ((flash_dev_info->block_count) / (scale_block_cnt)) ++#define NF_VEND_INFO flash_dev_info->vendor_info ++#define NF_OPTIONS flash_dev_info->options ++#define NF_BBT_MAX_NR flash_dev_info->bbt_blk_max_nr ++#define NF_OPTIONS flash_dev_info->options ++#define NF_BI_OFF flash_dev_info->bi_off ++ ++#define BLOCK_TO_OFFSET(blk) (blk * NF_PG_PER_BLK * NF_PG_SZ) ++#define BLOCK_TO_PAGE(blk) (blk * NF_PG_PER_BLK) ++#define BLOCK_PAGE_TO_OFFSET(blk, pge) ((blk * NF_PG_PER_BLK + pge) * NF_PG_SZ) ++#define OFFSET_TO_BLOCK(offset) ((offset / NF_PG_SZ) / NF_PG_PER_BLK) ++#define OFFSET_TO_PAGE(offset) ((offset / NF_PG_SZ) % NF_PG_PER_BLK) ++ ++static u8 *g_bbt, *g_page_buf; ++static u32 g_bbt_sz; ++static u32 g_main_bbt_addr = 0, g_mirror_bbt_page = 0; ++static u8 g_main_bbt_ver; ++//static u8 g_mirror_bbt_ver; ++static u8 g_main_bbt_des[] = "Bbt0"; ++//static u8 g_mirror_bbt_des[] = "1tbB"; ++static bool mxcnfc_init_ok = false; ++ ++// this callback allows the platform specific function to be called right ++// after flash_dev_query() ++nfc_setup_func_t *nfc_setup = NULL; ++ ++// this callback allows the platform specific iomux setup ++nfc_iomuxsetup_func_t *nfc_iomux_setup = NULL; ++ ++int ++#ifndef MXCFLASH_SELECT_MULTI ++flash_hwr_init(void) ++#else ++nandflash_hwr_init(void) ++#endif ++{ ++ cyg_uint16 id[4], id_tmp[4]; ++ int i, flash_width = 0; ++ nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__); ++ ++ if (nfc_iomux_setup) ++ nfc_iomux_setup(); ++ ++ ++ if (nfc_setup) { ++ /* If not booting from NAND, set the width to x8 to read the NAND ID */ ++ if (!(IS_BOOTING_FROM_NAND())) { ++ flash_dev_info = supported_devices; ++ flash_dev_info->port_size = MXC_NAND_8_BIT; ++ flash_width = MXC_NAND_8_BIT; ++ g_nfc_version = nfc_setup(flash_dev_info, num_of_nand_chips); ++ } ++ } ++ ++try_reading_id_again: ++ NFC_SET_NFC_ACTIVE_CS(0); ++ NFC_CMD_INPUT(FLASH_Reset); ++ ++ // Look through table for device data ++ flash_dev_query(id); ++ flash_dev_info = supported_devices; ++ for (i = 0; i < NUM_DEVICES; i++) { ++ if ((flash_dev_info->device_id == id[0]) && ++ (flash_dev_info->device_id2 == 0xFFFF || flash_dev_info->device_id2 == id[1])) ++ break; ++ flash_dev_info++; ++ } ++ ++ // Do we find the device? If not, return error. ++ if (NUM_DEVICES == i) { ++ if ((!(IS_BOOTING_FROM_NAND())) && (flash_width == MXC_NAND_8_BIT)) { ++ /* Set in x16 mode and try reading id again */ ++ flash_dev_info = supported_devices; ++ flash_dev_info->port_size = MXC_NAND_16_BIT; ++ flash_width = MXC_NAND_16_BIT; ++ g_nfc_version = nfc_setup(flash_dev_info, num_of_nand_chips); ++ goto try_reading_id_again; ++ } ++ diag_printf("Unrecognized NAND part: 0x%04x, 0x%04x, 0x%04x, 0x%04x\n", ++ id[0], id[1], id[2], id[3]); ++ return FLASH_ERR_DRV_WRONG_PART; ++ } ++ ++ nand_flash_index = i; ++ mxcnfc_init_ok = true; ++ ++ if (NF_PG_SZ == 2048) { ++ g_is_2k_page = true; ++ g_spare_only_read_ok = false; ++ } ++ if (NF_PG_SZ == 4096) { ++ g_is_4k_page = true; ++ g_spare_only_read_ok = false; ++ } ++ ++ nfc_printf(NFC_DEBUG_MED, "%s(): %d out of NUM_DEVICES=%d, id=0x%x\n", ++ __FUNCTION__, i, (u32)NUM_DEVICES, flash_dev_info->device_id); ++ ++ for (i = 2; i <= NUM_OF_CS_LINES; i++) { ++ id_tmp[0] = 0; ++ id_tmp[1] = 0; ++ read_nflash_id(id_tmp, i -1); ++ if ((id[0] != id_tmp[0]) || (id[1] != id_tmp[1])) { ++ break; ++ } ++ /* Support interleave with 1, 2, 4, 8 chips */ ++ if (i == (num_of_nand_chips * 2)) { ++ num_of_nand_chips = i; ++ } ++ NFC_CMD_INPUT(FLASH_Reset); ++ } ++ ++ num_of_nand_chips = 1; ++ if (nfc_setup) { ++ g_nfc_version = nfc_setup(flash_dev_info, num_of_nand_chips); ++ } ++ ++ NFC_ARCH_INIT(); ++ ++ g_bbt_sz = NF_BLK_CNT / 4; ++ g_bbt = (u8*)malloc(g_bbt_sz); // two bit for each block ++ if (g_bbt == NULL) { ++ diag_printf("%s(): malloc failed (%d)\n", __FUNCTION__, __LINE__); ++ return FLASH_ERR_PROTOCOL; ++ } ++ ++ g_page_buf = (u8*)malloc(NF_PG_SZ); // for programming less than one page size buffer ++ if (g_page_buf == NULL) { ++ diag_printf("%s(): malloc failed (%d)\n", __FUNCTION__, __LINE__); ++ return FLASH_ERR_PROTOCOL; ++ } ++ memset(g_bbt, -1, g_bbt_sz); ++ ++ /* For now cap off the Device size to 2GB */ ++ i = 1; ++ while ((i <= num_of_nand_chips) && ((NF_DEV_SZ * i) < 0x80000000)) { ++ num_of_nand_chips_for_nandsize = i ; ++ i *= 2; ++ } ++ ++ scale_block_cnt = num_of_nand_chips / num_of_nand_chips_for_nandsize; ++ // Hard wired for now ++ flash_info.block_size = NF_BLK_SZ; ++ flash_info.blocks = NF_BLK_CNT; ++ flash_info.start = (void *)0; ++ flash_info.end = (void *)NF_DEV_SZ; ++ ++ diag_printf1("%s(g_bbt=%p)\n", __FUNCTION__, g_bbt); ++ mxc_nfc_scan(false); // look for table ++ ++ diag_printf1("%s(): block_size=0x%x, blocks=0x%x, start=%p, end=%p\n", ++ __FUNCTION__, flash_info.block_size, flash_info.blocks, ++ flash_info.start, flash_info.end); ++ ++ return FLASH_ERR_OK; ++} ++ ++// used by redboot/current/src/flash.c ++int mxc_nand_fis_start(void) ++{ ++ return (flash_dev_info->fis_start_addr * num_of_nand_chips); ++} ++ ++// used by redboot/current/src/fconfig.c ++int mxc_nand_get_page_size(void) ++{ ++ return NF_PG_SZ; ++} ++ ++#define nfc_buf_mem_cpy memcpy ++ ++#ifndef NFC_V3_0 ++/*! ++ * Starts the address input cycles for different operations as defined in ops. ++ * ++ * @param ops operations as defined in enum nfc_addr_ops ++ * @param pg_no page number offset from 0 ++ * @param pg_off byte offset within the page ++ * @param is_erase don't care for earlier NFC ++ * @param cs_line don't care for earlier NFC ++ */ ++static void start_nfc_addr_ops(u32 ops, u32 pg_no, u32 pg_off, u32 is_erase, u32 cs_line, u32 num_of_chips) ++{ ++ int i; ++ ++ switch (ops) { ++ case FLASH_Read_ID: ++ /* Only support one NAND chip (CS0) */ ++ if (cs_line != 0) ++ return; ++ NFC_ADDR_INPUT(0); ++ return; ++ case FLASH_Read_Mode1: ++ case FLASH_Program: ++ for (i = 0; i < COL_CYCLE; i++, pg_off >>= 8) { ++ NFC_ADDR_INPUT(pg_off & 0xFF); ++ } ++ // don't break on purpose ++ case FLASH_Block_Erase: ++ for (i = 0; i < ROW_CYCLE; i++, pg_no >>= 8) { ++ NFC_ADDR_INPUT(pg_no & 0xFF); ++ } ++ break; ++ default: ++ diag_printf("!!!!!! %s(): wrong ops: %d !!!!!\n", __FUNCTION__, ops); ++ return; ++ } ++} ++#endif // #ifndef NFC_V3_0 ++ ++static void read_nflash_id(void* id, u32 cs_line) ++{ ++ volatile u32 *ptr = (u32*)NAND_MAIN_BUF0; ++ volatile u32 *id_32 = (u32*)id; ++ ++ nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__); ++ NFC_PRESET(MXC_UNLOCK_BLK_END); ++ NFC_SET_NFC_ACTIVE_CS(cs_line); ++ NFC_CMD_INPUT(FLASH_Read_ID); ++ ++ start_nfc_addr_ops(FLASH_Read_ID, 0, 0, 0, cs_line, num_of_nand_chips); ++ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_ID, g_ecc_enable); ++ ++ *id_32++ = *ptr++; ++ *id_32++ = *ptr++; ++} ++ ++/*! ++ * Checks to see if a block is bad. If buf is not NULL, it indicates a valid ++ * BBT in the RAM. In this case, it assumes to have 2-bit to represent each ++ * block for good or bad ++ * * 11b: block is good ++ * * 00b: block is factory marked bad ++ * * 01b, 10b: block is marked bad due to wear ++ * If buf is NULL, then it indicates a low level scan based on the certain ++ * offset value in certain pages and certain offset to be non-0xFF. In this ++ * case, the HW ECC will be turned off. ++ * ++ * @param block 0-based block number ++ * @param buf BBT buffer. Could be NULL (see above explanation) ++ * ++ * @return 1 if bad block; 0 otherwise ++ */ ++static bool nfc_is_badblock(u32 block, u8 *buf) ++{ ++ u32 off; // byte offset ++ u32 sft; // bit shift 0, 2, 4, 6 ++ u32 addr; ++ u16 temp, i; ++ bool res = false; ++ u32 pg_no, pg_off; ++ ++ if (g_main_bbt_addr) { ++ // use BBT ++ off = block >> 2; // byte offset ++ sft = (block & 3) << 1; // bit shift 0, 2, 4, 6 ++ if (((buf[off] >> sft) & 0x3) != 0x3) { ++ res = true; ++ } ++ goto out; ++ } ++ ++ // need to do low level scan with ECC off ++ if (NF_OPTIONS & NAND_BBT_SCAN1STPAGE) { ++ addr = block * NF_BLK_SZ; // TODO: overflow for over 4GB nand ++ pg_no = addr / NF_PG_SZ; ++ pg_off = addr % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc ++ if (g_is_2k_page || g_is_4k_page) { ++ temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF); ++ } else { ++ temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area ++ } ++ if ((temp & 0xFF) != 0xFF) { ++ res = true; ++ return res; ++ } ++ pg_off = 0; ++ } ++ } ++ if (NF_OPTIONS & NAND_BBT_SCAN2NDPAGE) { ++ addr = block * NF_BLK_SZ + NF_PG_SZ; // TODO: overflow for over 4GB nand ++ pg_no = addr / NF_PG_SZ; ++ pg_off = addr % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc ++ if (g_is_2k_page || g_is_4k_page) { ++ temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF); ++ } else { ++ temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area ++ } ++ if ((temp & 0xFF) != 0xFF) { ++ res = true; ++ return res; ++ } ++ pg_off = 0; ++ } ++ } ++ if (NF_OPTIONS & NAND_BBT_SCANLSTPAGE) { ++ if (g_is_4k_page || g_is_2k_page) { ++ // TODO: overflow for over 4GB nand ++ addr = (block + 1) * NF_BLK_SZ - NF_PG_SZ; ++ pg_no = addr / NF_PG_SZ; ++ pg_off = addr % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ // we don't do partial page read here. No ecc either ++ nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_OFF, i, num_of_nand_chips); ++ temp = readw((u32)NAND_MAIN_BUF0 + NF_BI_OFF); ++ if ((temp & 0xFF) != 0xFF) { ++ res = true; ++ return res; ++ } ++ pg_off = 0; ++ } ++ } else { ++ diag_printf("only 2K/4K page is supported\n"); ++ // die here -- need to fix the SW ++ while (1); ++ } ++ } ++out: ++ return res; ++} ++ ++/* ++ * Program g_bbt into the NAND block with offset at g_main_bbt_addr. ++ * This assumes that the g_bbt has been built already. ++ * ++ * If g_main_bbt_addr is 0, search for a free block from the bottom 4 blocks (but make ++ * sure not re-using the mirror block). If g_mirror_bbt_page is 0, do the same thing. ++ * Otherwise, just use g_main_bbt_addr, g_mirror_bbt_page numbers to prgram the ++ * g_bbt into those two blocks. ++ * todo: need to do the version to see which one is newer. ++ * ++ * @return 0 if successful; -1 otherwise. ++ */ ++static int program_bbt_to_flash(void) ++{ ++ int i = 0; ++ u32 addr, blk; ++ ++ if (g_main_bbt_addr) { ++ // update the spare area before writing and version number ++ g_main_bbt_ver++; ++ } else { ++ // no existing main bbt table in flash, build one. ++ g_main_bbt_ver = 1; // first BBT version ++ for (i = 0; i < NF_BBT_MAX_NR; i++) { ++ blk = NF_BLK_CNT - i - 1; ++ addr = blk * NF_BLK_SZ; ++ if (g_mirror_bbt_page == addr || nfc_is_badblock(blk, g_bbt)) ++ continue; ++ g_main_bbt_addr = addr; ++ break; ++ } ++ } ++ // todo: take care of bad block here if programming error? ++ if (i < NF_BBT_MAX_NR) { ++ nfc_erase_blk(g_main_bbt_addr); ++ writel(*(u32*)g_main_bbt_des, NAND_SPAR_BUF0); ++ writew(g_main_bbt_ver | 0xFF00, NAND_SPAR_BUF0 + 4); ++ ++ nfc_program_blk(g_main_bbt_addr, (u32)g_bbt, g_bbt_sz, FILE_FORMAT_BBT); ++ ++ diag_printf("\nWriting BBT at offset 0x%x size=%d\n", g_main_bbt_addr, g_bbt_sz); ++ } else { ++ diag_printf("Error: %s() failed to build main BBT in flash\n", __FUNCTION__); ++ return -1; ++ } ++ return 0; ++} ++ ++/*! ++ * Unconditionally erase a block without checking the BI field. ++ * Note that there is NO error checking for passed-in ra. ++ * ++ * @param ra starting address in the raw address space (offset) ++ * Must be block-aligned ++ * @return 0 if successful; -1 otherwise ++ */ ++static int nfc_erase_blk(u32 ra) ++{ ++ u16 flash_status, i; ++ u32 pg_no, pg_off; ++ ++ if (g_nfc_version == 0x30) { ++ pg_no = ra / NF_PG_SZ; ++ pg_off = ra % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ start_nfc_addr_ops(FLASH_Block_Erase, pg_no, pg_off, 1, i, num_of_nand_chips); ++ // combine the two commands for erase ++ writel(FLASH_Block_Erase, NAND_CMD_REG); ++ writel((FLASH_Start_Erase << 8) | FLASH_Block_Erase, NAND_CMD_REG); ++ write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_INT), NFC_IPC_REG); ++ // start auto-erase ++ writel(NAND_LAUNCH_AUTO_ERASE, NAND_LAUNCH_REG); ++ wait_op_done(); ++ pg_off = 0; ++ } ++ flash_status = NFC_STATUS_READ(); ++ // check I/O bit 0 to see if it is 0 for success ++ if((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) { ++ diag_printf("Error: %s() status=0x%x\n", __FUNCTION__, flash_status); ++ return -1; ++ } ++ } else { ++ NFC_CMD_INPUT(FLASH_Block_Erase); ++ start_nfc_addr_ops(FLASH_Block_Erase, ra / NF_PG_SZ, ra % NF_PG_SZ, 1, 0, num_of_nand_chips); ++ NFC_CMD_INPUT(FLASH_Start_Erase); ++ ++ flash_status = NFC_STATUS_READ(); ++ ++ // check I/O bit 0 to see if it is 0 for success ++ if((flash_status & 0x1) != 0) { ++ diag_printf("Error: %s() status=0x%x\n", __FUNCTION__, flash_status); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/*! ++ * Program a block of data in the flash. This function doesn't do ++ * bad block checking. But if program fails, it return error. ++ * Note: If "len" is less than a block it will program up to a page's ++ * boundary. If not within a page boundary, then it fills the ++ * rest of the page with 0xFF. ++ * ++ * @param ra destination raw flash address ++ * @param buf source address in the RAM ++ * @param len len to be programmed ++ * @param file_format used to distinguish if this a write to the BBT are or normal data write ++ * ++ * @return 0 if successful; -1 otherwise ++ */ ++static int nfc_program_blk(u32 ra, u32 buf, u32 len, u8 file_format) ++{ ++ u32 temp = num_of_nand_chips; ++ ++ /* Needed when romupdate is called */ ++ if (ra == 0) ++ num_of_nand_chips = 1; ++ ++ for (; len >= NF_PG_SZ; len -= NF_PG_SZ) { ++ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, buf, 0, file_format) != 0) { ++ return -1; ++ } ++ ra += NF_PG_SZ; ++ buf += NF_PG_SZ; ++ } ++ if (len != 0) { ++ memset(g_page_buf, 0xFF, NF_PG_SZ); ++ memcpy(g_page_buf, (void *)buf, len); ++ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, (u32)g_page_buf, 0, file_format) != 0) { ++ num_of_nand_chips = temp; ++ return -1; ++ } ++ } ++ num_of_nand_chips = temp; ++ return 0; ++} ++ ++static void mark_blk_bad(unsigned int block, unsigned char *buf, ++ enum blk_bad_type bad_type) ++{ ++ unsigned int off = block >> 2; // byte offset - each byte can hold status for 4 blocks ++ unsigned int sft = (block & 3) << 1; // bit shift 0, 2, 4, 6 ++ unsigned char val = buf[off]; ++ diag_printf1("buf[%d]=0x%x\n", off, buf[off]); ++ ++ val &= ~(3 << sft) | (bad_type << sft); ++ buf[off] = val; ++ diag_printf1("buf[%d]=0x%x\n", off, val); ++} ++ ++/*! ++ * Erase a range of NAND flash good blocks only. ++ * It skips bad blocks and update the BBT once it sees new bad block due to erase. ++ * @param addr raw NAND flash address. it has to be block size aligned ++ * @param len number of bytes ++ * @param skip_bad if 1, don't erase bad block; otherwise, always erase ++ * @param verbose use true to print more messages ++ * ++ * @return FLASH_ERR_OK (0) if successful; non-zero otherwise ++ */ ++int nfc_erase_region(u32 addr, u32 len, u32 skip_bad, bool verbose) ++{ ++ u32 sz, blk, update = 0, skip = 0, j = 0; ++ ++ nfc_printf(NFC_DEBUG_MED, "%s(addr=0x%x, len=0x%x)\n", ++ __FUNCTION__, addr, len); ++ ++ if ((addr % NF_BLK_SZ) != 0 || len == 0) { ++ diag_printf("%s(): invalid value or not aligned with block boundry\n", __FUNCTION__); ++ diag_printf("addr=0x%x, len=%d\n", addr, len); ++ return FLASH_ERR_INVALID; ++ } ++ ++ // now addr has to be block aligned ++ for (sz = 0; sz < len; addr += NF_BLK_SZ, j++) { ++ blk = OFFSET_TO_BLOCK(addr); ++ if (skip_bad && nfc_is_badblock(blk, g_bbt)) { ++ diag_printf("\nWarning: %s(addr=0x%x, block=%d): skipping bad\n", ++ __FUNCTION__, addr, blk); ++ skip++; ++ continue; ++ } ++ if (nfc_erase_blk(addr) != 0) { ++ diag_printf("\nError: %s2(addr=0x%x, block=%d): run-time erase error!\n", ++ __FUNCTION__, addr, blk); ++ mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME); ++ if (!skip_bad) { ++ sz += NF_BLK_SZ; ++ } ++ // we don't need to update the table immediately here since even ++ // with power loss now, we should see the same erase error again. ++ update++; ++ continue; ++ } ++ ++ if ((j % 0x20) == 0) ++ diag_printf("\n%s 0x%08x: ", skip_bad ? "Erase" : "FORCE erase", addr); ++ diag_printf("."); ++ ++ sz += NF_BLK_SZ; ++ } ++ if (update) { ++ if (program_bbt_to_flash() != 0) { ++ diag_printf("ERROR: TOO BAD! What can I do?\n"); ++ return -1; ++ } ++ diag_printf("\n%s(new bad blocks=%d)\n\n", __FUNCTION__, update); ++ } ++ if (skip) { ++ diag_printf("\n%s(skip bad blocks=%d\n\n", __FUNCTION__, skip); ++ } ++ return FLASH_ERR_OK; ++} ++ ++/*! ++ * Program a range of NAND flash in blocks only. ++ * It skips bad blocks and update the BBT once it sees new bad block due to program. ++ * @param addr raw NAND flash address. it has to be block size aligned ++ * @param len number of bytes ++ * @return FLASH_ERR_OK (0) if successful; non-zero otherwise ++ */ ++int nfc_program_region(u32 addr, u32 buf, u32 len) ++{ ++ u32 sz = 0, blk, update = 0, skip = 0, partial_block_size = NF_BLK_SZ; ++ u32 buf_addr_st = 0; ++ ++ diag_printf1("%s(addr=0x%x, len=0x%x)\n", __FUNCTION__, addr, len); ++ ++ if (((addr % NF_PG_SZ) != 0) || (len == 0)) { ++ diag_printf("%s(): invalid value or not aligned with page boundry\n", __FUNCTION__); ++ diag_printf("addr=0x%x, len=%d\n", addr, len); ++ return FLASH_ERR_INVALID; ++ } ++ ++ if ((addr % NF_BLK_SZ) != 0) { ++ partial_block_size = (((OFFSET_TO_BLOCK(addr) + 1) * NF_BLK_SZ) - addr); ++ } ++ ++ // now addr has to be block aligned ++ while (1) { ++ blk = OFFSET_TO_BLOCK(addr); ++ if (nfc_is_badblock(blk, g_bbt)) { ++ diag_printf("\nWarning: %s(addr=0x%x, block=%d): skipping bad\n", ++ __FUNCTION__, addr, blk); ++ skip++; ++ goto incr_address; ++ } ++ ++ sz = (len >= partial_block_size) ? partial_block_size : len; ++ buf_addr_st = buf; ++ ++ if (nfc_program_blk(addr, buf, sz, FILE_FORMAT_NORMAL) != 0) { ++ diag_printf("\nError: %s2(addr=0x%x, block=%d): run-time program error!\n", ++ __FUNCTION__, addr, blk); ++ mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME); ++ // we don't need to update the table immediately here since even ++ // with power loss now, we should see the same program error again. ++ update++; ++ buf = buf_addr_st; ++ goto incr_address; ++ } ++ diag_printf("."); ++ ++ len -= sz; ++ buf += sz; ++ if (len == 0) ++ break; ++ ++incr_address: ++ addr += partial_block_size; ++ partial_block_size = NF_BLK_SZ; ++ } ++ if (update) { ++ if (program_bbt_to_flash() != 0) { ++ diag_printf("ERROR: TOO BAD! What can I do?\n"); ++ return -1; ++ } ++ diag_printf("\n%s(new bad blocks=%d\n", __FUNCTION__, update); ++ } ++ if (skip) ++ diag_printf("\n%s(skip bad blocks=%d\n", __FUNCTION__, skip); ++ ++ return FLASH_ERR_OK; ++} ++ ++/*! ++ * Read data from raw NAND flash address to memory. The MSB of the passed- ++ * in flash address will be masked off inside the function. ++ * It skips bad blocks and read good blocks of data for "len" bytes. ++ * ++ * @param addr NAND flash address. it has to be page aligned ++ * @param buf memory buf where data will be copied to ++ * @param len number of bytes ++ * @return FLASH_ERR_OK (0) if successful; non-zero otherwise ++ */ ++int nfc_read_region(u32 addr, u32 buf, u32 len) ++{ ++ u32 sz, blk = 0, bad, i, pg_no, pg_off = 0; ++ ++ // make sure 32-bit aligned ++ len = (len + 3) & (~0x3); ++ ++ diag_printf1("\n%s(addr=0x%x, buf=0x%x, len=0x%x)\n", ++ __FUNCTION__, addr, buf, len); ++ ++ if (addr < (u32)(flash_info.start) || (addr + len) > (u32)(flash_info.end) || len == 0) { ++ diag_printf("\n%s(): Error: invalid address=0x%x, len=%d\n", ++ __FUNCTION__, addr, len); ++ diag_printf("flash_info.start=%p, flash_info.end=%p\n", flash_info.start, flash_info.end); ++ return FLASH_ERR_INVALID; ++ } ++ ++ if ((addr % (NF_PG_SZ)) != 0) { ++ diag_printf("\n%s(): invalid value or not aligned with page boundry\n", __FUNCTION__); ++ diag_printf("addr=0x%x, len=%d\n", addr, len); ++ return FLASH_ERR_INVALID; ++ } ++ ++ for (sz = 0, bad = 0; sz < len;) { ++ if ((addr % NF_BLK_SZ) == 0) { ++ diag_printf("."); ++ // only need to test block aligned page address ++ blk = OFFSET_TO_BLOCK(addr); ++ if (nfc_is_badblock(blk, g_bbt)) { ++ diag_printf("\nWarning: %s(addr=0x%x, block=%d): skipping bad\n", ++ __FUNCTION__, addr, blk); ++ addr += NF_BLK_SZ; ++ if (bad++ >= (NF_BLK_CNT / 10)) { ++ diag_printf("Found too many bad blocks (%d). Abort\n", bad); ++ return FLASH_ERR_PROTOCOL; ++ } ++ continue; ++ } ++ } ++ ++ pg_no = addr / NF_PG_SZ; ++ ++ for (i = 0; i < num_of_nand_chips; i++) { ++ if (nfc_read_page(i, pg_no, pg_off) != 0) { ++ diag_printf("\nError: %s() can't handle read error at (addr=0x%x, block=%d)\n", ++ __FUNCTION__, addr, blk); ++ return FLASH_ERR_INVALID; ++ } ++ // now do the copying ++ nfc_buf_mem_cpy((void*)buf, (void*)(NAND_MAIN_BUF0), NF_PG_SZ / num_of_nand_chips); ++ ++ buf += (NF_PG_SZ / num_of_nand_chips); ++ sz += (NF_PG_SZ / num_of_nand_chips); ++ addr += (NF_PG_SZ / num_of_nand_chips); ++ } ++ } ++ ++ return FLASH_ERR_OK; ++} ++ ++/* ++ * Support only either program for main area only. Or spare-area only for 512B. ++ * If one wants to write to the spare-area, then before calling this function, ++ * the spare area NFC RAM buffer has to be setup already. This function doesn't touch ++ * the spare area NFC RAM buffer. ++ * ++ * @param pg_no page number offset from 0 ++ * @param pg_off byte offset within the page ++ * @param buf data buffer in the RAM to be written to NAND flash ++ * @param ecc_force can force ecc to be off. Otherwise, by default it is on ++ * unless the page offset is non-zero ++ * @param format used to distinguish if this a write to the BBT are or normal data write ++ * ++ * @return 0 if successful; non-zero otherwise ++ */ ++// SP-only opearation is not supported anymore !!! ++static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u32 buf, u32 ecc_force, u8 format) ++{ ++ u16 flash_status; ++ u32 ecc = NFC_FLASH_CONFIG2_ECC_EN, v, i = 0; ++ u32 write_count = NF_PG_SZ, start_point = 0, rba = 0, rba_count = 0; ++ int need_write = 0; ++ ++ /* check for linux ubifs support */ ++ if (format == FILE_FORMAT_NORMAL) { ++ for (; i < write_count; i += 4) { ++ if (*(u32 *)(buf + i) != 0xFFFFFFFF) { ++ need_write = 1; ++ break; ++ } ++ } ++ } else { ++ need_write = 1; ++ } ++ ++ if (!need_write) ++ return 0; ++ ++ // the 2nd condition is to test for unaligned page address -- ecc has to be off. ++ if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) { ++ ecc = 0; ++ } ++ ++ diag_printf1("%s(0x%x, 0x%x, %d)\n", __FUNCTION__, pg_no, pg_off, ecc_force); ++ ++ if (g_nfc_version == 0x30) { ++ /* Set the RBA to use the first 1/2k buffer (Main area Buffer 0) */ ++ v = readl(NAND_CONFIGURATION1_REG) & (~0x71); ++ writel(v, NAND_CONFIGURATION1_REG); ++ ++ /* Check if Page size is greater than NFC buffer */ ++ do { ++ if (write_count <= NFC_BUFSIZE) { ++ // No need to worry about the spare area ++ nfc_buf_mem_cpy((void *)NAND_MAIN_BUF0, (void *)buf, write_count); ++ write_count = 0; ++ } else { ++ // No need to worry about the spare area ++ nfc_buf_mem_cpy((void *)NAND_MAIN_BUF0, (void *)buf, NFC_BUFSIZE); ++ write_count -= NFC_BUFSIZE; ++ buf += NFC_BUFSIZE; ++ } ++ ++ for (i = start_point; i < num_of_nand_chips; i++) { ++ rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512); ++ /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */ ++ if (rba > 7) { ++ rba_count = 0; ++ break; ++ } ++ ++ // For ECC ++ v = readl(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN); ++ // setup config2 register for ECC enable or not ++ write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG); ++ ++ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips); ++ // combine the two commands for program ++ writel(FLASH_Send_Data, NAND_CMD_REG); ++ writel((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG); ++ write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_INT), NFC_IPC_REG); ++ // start auto-program ++ writel(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG); ++ if (i < (num_of_nand_chips - i)) ++ wait_for_auto_prog_done(); ++ else { ++ wait_op_done(); ++ /* Wait till NAND is idle */ ++ while (!(readl(NFC_IPC_REG) & NFC_IPC_RB_B)); ++ } ++ pg_off = 0; ++ rba_count++; ++ } ++ start_point = i; ++ } while (write_count > 0); ++ flash_status = NFC_STATUS_READ(); ++ // check I/O bit 0 to see if it is 0 for success ++ if((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) { ++ diag_printf("Error: %s() status=0x%x\n", __FUNCTION__, flash_status); ++ return -1; ++ } ++ } else { ++ // No need to worry about the spare area ++ nfc_buf_mem_cpy((void *)NAND_MAIN_BUF0, (void *)buf, NF_PG_SZ); ++#ifdef BARKER_CODE_SWAP_LOC ++ // To replace the data at offset MXC_NAND_BOOT_LOAD_BARKER with ++ // the address of the NFC base. This is needed for certain platforms. ++ if (pg_no == 0) { ++ diag_printf("\n[INFO]: copy data at 0x%x to spare area and set it to 0x%x\n", ++ BARKER_CODE_SWAP_LOC, BARKER_CODE_VAL); ++ writel(readl(NFC_BASE + BARKER_CODE_SWAP_LOC), NAND_SPAR_BUF0); ++ // todo: set BARKER_CODE_VAL and BARKER_CODE_SWAP_LOC for skye, etc. ++ writel(BARKER_CODE_VAL, NFC_BASE + BARKER_CODE_SWAP_LOC); ++ } ++#endif ++ ++ NFC_CMD_INPUT(FLASH_Send_Data); ++ start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips); ++ ++ NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc); ++ if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) { ++ diag_printf("4K page with multi cycle write is not supported\n"); ++ // die here -- need to fix the SW ++ while (1); ++ } ++ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) { ++ NFC_DATA_INPUT_2k(RAM_BUF_1); ++ NFC_DATA_INPUT_2k(RAM_BUF_2); ++ NFC_DATA_INPUT_2k(RAM_BUF_3); ++ } ++ NFC_CMD_INPUT(FLASH_Program); ++ ++ flash_status = NFC_STATUS_READ(); ++ // check I/O bit 0 to see if it is 0 for success ++ if((flash_status & 0x1) != 0) { ++ diag_printf("Error: %s() status=0x%x\n", __FUNCTION__, flash_status); ++ return -1; ++ } ++ } ++ return 0; ++} ++#ifndef NFC_V3_0 ++// for version V1 and V2 of NFC ++static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line, u32 num_of_chips) ++{ ++ u32 t1, ecc = 1; ++ u8 t2 = 0, t3 = 0, t4 = 0, t5 = 0, t6 = 0, t7 = 0, t8 = 0; ++ int res = 0; ++ ++ if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) ++ ecc = 0; ++ ++ NFC_CMD_INPUT(FLASH_Read_Mode1); ++ start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, 0, num_of_chips); ++ ++ if (g_is_2k_page || g_is_4k_page) { ++ NFC_CMD_INPUT(FLASH_Read_Mode1_LG); ++ } ++ ++ NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, ecc); ++ if (g_nfc_version == 0x10) { ++ t1 = readw(ECC_STATUS_RESULT_REG); ++ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) { ++ NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc); ++ t2 = readw(ECC_STATUS_RESULT_REG); ++ NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc); ++ t3 = readw(ECC_STATUS_RESULT_REG); ++ NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc); ++ t4 = readw(ECC_STATUS_RESULT_REG); ++ } ++ ++ if (ecc && ((t1 & 0xA) != 0x0 || (t2 & 0xA) != 0x0 || (t3 & 0xA) != 0x0 ++ || (t4 & 0xA) != 0x0)) { ++ diag_printf("\nError %d: %s(page=%d, col=%d): ECC status=0x%x:0x%x:0x%x:0x%x\n", ++ __LINE__, __FUNCTION__, pg_no, pg_off, t1, t2, t3, t4); ++ res = -1; ++ goto out; ++ } ++ } else if (g_nfc_version == 0x20) { ++ if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) { ++ NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc); ++ NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc); ++ NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc); ++ } ++ if (ecc) { ++ t1 = readl(ECC_STATUS_RESULT_REG); ++ if (g_is_2k_page || g_is_4k_page) { ++ t2 = (t1 >> 4) & 0xF; ++ t3 = (t1 >> 8) & 0xF; ++ t4 = (t1 >> 12) & 0xF; ++ if (g_is_4k_page) { ++ t5 = (t1 >> 16) & 0xF; ++ t6 = (t1 >> 20) & 0xF; ++ t7 = (t1 >> 24) & 0xF; ++ t8 = (t1 >> 28) & 0xF; ++ } ++ } ++ if ((t1 = (t1 & 0xF)) > 4 || t2 > 4 || t3 > 4 || t4 > 4 || t5 > 4 || t6 > 4 || t7 > 4 || t8 > 4) { ++ diag_printf("\nError %d: %s(page=%d, col=%d)\n", ++ __LINE__, __FUNCTION__, pg_no, pg_off); ++ diag_printf(" ECC status=%x:%x:%x:%x:%x:%x:%x:%x\n", t1, t2, t3, t4, t5, t6, t7, t8); ++ res = -1; ++ goto out; ++ } ++ } ++ } else { ++ diag_printf("Unknown NFC version: %d\n", g_nfc_version); ++ while (1); ++ } ++#ifdef BARKER_CODE_SWAP_LOC ++ // To replace the data at offset BARKER_CODE_SWAP_LOC with the address of the NFC base ++ // This is needed for certain platforms ++ if (pg_no == 0) { ++ diag_printf("\n[INFO]: copy back data from spare to 0x%x\n", BARKER_CODE_SWAP_LOC); ++ writel(readl(NAND_SPAR_BUF0), NFC_BASE + BARKER_CODE_SWAP_LOC); ++ } ++#endif ++ ++out: ++ return res; ++} ++#endif // ifndef NFC_V3_0 ++ ++/*! ++ * Read a page's both main and spare area from NAND flash to the internal RAM buffer. ++ * It always reads data to the internal buffer 0. ++ * ++ * @param cs_line which NAND device is used ++ * @param pg_no page number of the device ++ * @param pg_off offset within a page ++ * ++ * @return 0 if no error or 1-bit error; -1 otherwise ++ */ ++static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off) ++{ ++ return nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_ON, cs_line, num_of_nand_chips); ++} ++ ++// Read data into buffer ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_read_buf(void* addr, void* data, int len) ++#else ++int nandflash_read_buf(void* addr, void* data, int len) ++#endif ++{ ++ return nfc_read_region((u32)addr, (u32)data, (u32)len); ++} ++ ++void mxc_nfc_print_info(void) ++{ ++ diag_printf("[0x%08x bytes]: %d blocks of %d pages of %d bytes each.\n", ++ NF_DEV_SZ, NF_BLK_CNT, ++ NF_PG_PER_BLK, NF_PG_SZ); ++} ++ ++/* ++ * Look for the BBT table depending on the passed-in lowlevel value. ++ * @param lowlevel If true, then it does a low level scan based on factory ++ * marked BI(block info) field with ECC off to decide if a ++ * block is bad. ++ * If false, then it checks to see if an existing BBT in the ++ * flash or not. If not, then it returns -1. If yes, it will ++ * prints out the number of bad blocks. ++ * ++ * @return number of bad blocks for the whole nand flash ++ * ++ * Note: For a brand new flash, this function has to be called with ++ * lowlevel=true. ++ * ++ * ++ */ ++static int mxc_nfc_scan(bool lowlevel) ++{ ++ u32 addr, bad = 0, i = 0, blk; ++ u32 count1 = 0, count2 = 0; ++ u8 *buf = 0; ++ ++ nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__); ++ ++ if (g_nfc_debug_measure) { ++ count1 = hal_timer_count(); ++ } ++ // read out the last 4 blocks for marker ++ // need to keep where is the td and md block number ++ if (!lowlevel) { ++ diag_printf("Searching for BBT table in the flash ...\n"); ++ g_main_bbt_addr = 0; ++ for (i = 0; i < NF_BBT_MAX_NR; i++) { ++ blk = NF_BLK_CNT - i - 1; ++ addr = blk * NF_BLK_SZ; ++ if (nfc_read_pg_random(addr / NF_PG_SZ, addr % NF_PG_SZ, ECC_FORCE_ON, 0, num_of_nand_chips) != 0) ++ continue; ++ if (*(u32 *)g_main_bbt_des == *(u32 *)NAND_SPAR_BUF0) { ++ diag_printf1("bingo\n"); ++ g_main_bbt_addr = addr; ++ g_main_bbt_ver = readw(NAND_SPAR_BUF0 + 4); ++ if (nfc_read_region(addr, (u32)g_bbt, g_bbt_sz) != 0) { ++ diag_printf("ERROR!!! Can't read BBT table at addr: 0x%x\n", addr); ++ return -1; ++ } ++ diag_printf("\nFound version %d Bbt0 at block %d (0x%x)\n", ++ g_main_bbt_ver, OFFSET_TO_BLOCK(g_main_bbt_addr), g_main_bbt_addr); ++ break; ++ } ++ // todo: finish up the mirror block detection also ++ } ++ if (!g_main_bbt_addr) { ++ diag_printf("No BBT table found. Need to do \"nand scan\" first\n"); ++ return -1; ++ } ++ buf = g_bbt; ++ } else ++ diag_printf("Do low level scan to construct BBT\n"); ++ ++ // do some low level scan of each block and check for bad. ++ for (i = 0; i < NF_BLK_CNT; i++) { ++ if (nfc_is_badblock(i, buf)) { ++ // construct the bad block table ++ if (!buf) ++ mark_blk_bad(i, g_bbt, BLK_BAD_FACTORY); ++ bad++; ++ diag_printf("Block %d is bad\n", i); ++ } ++ } ++ ++ diag_printf("Total bad blocks: %d\n", bad); ++ if (g_nfc_debug_measure) { ++ count2 = hal_timer_count(); ++ diag_printf("counter1=0x%x, counter2=0x%x, diff=0x%x\n", ++ count1, count2, count2 - count1); ++ diag_printf("Using [diff * 1000000 / 32768] to get usec\n"); ++ } ++ return bad; ++} ++ ++////////////////////////// "nand" commands support ///////////////////////// ++// Image management functions ++local_cmd_entry("info", ++ "Show nand flash info (number of good/bad blocks)", ++ "", ++ nand_info, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("show", ++ "Show a page main/spare areas or spare area only (-s)", ++ "-f [-s]", ++ nand_show, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("read", ++ "Read data from nand flash into RAM", ++ "-f -b -l [-c ]\n \ ++ Note -c is only for 2K-page for value <0, 2048+64-1>", ++ nand_read, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("write", ++ "Write data from RAM into nand flash", ++ "-f -b -l [-c ]", ++ nand_write, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("erase", ++ "Erase nand flash contents", ++ "-f -l [-o] \n\ ++ -o: force erase (even for bad blocks)", ++ nand_erase, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("scan", ++ "Scan bad blocks and may also save bad block table into the NAND flash.", ++ "[-o] [-r] \n\ ++ No argument: save existing bad block table (BBT) \n\ ++ -r: re-scan with ECC off and save BBT -- for brand NEW flash \n\ ++ -o: force erase all, reconstruct BBT (no ECC) and save BBT -- for development. ", ++ nand_scan, ++ NAND_cmds ++ ); ++ ++local_cmd_entry("debug", ++ "Various NAND debug features ", ++ "<0> min debug messages \n\ ++ <1> med debug messages \n\ ++ <2> max debug messages \n\ ++ <3> enable(default)/disable h/w ECC for both r/w \n\ ++ <4> disable(default)/enalbe spare-only read \n\ ++ <9> enable/disable measurement \n\ ++ no parameter - display current debug setup", ++ nand_debug_fun, ++ NAND_cmds ++ ); ++ ++// Define table boundaries ++CYG_HAL_TABLE_BEGIN( __NAND_cmds_TAB__, NAND_cmds); ++CYG_HAL_TABLE_END( __NAND_cmds_TAB_END__, NAND_cmds); ++ ++extern struct cmd __NAND_cmds_TAB__[], __NAND_cmds_TAB_END__; ++ ++// CLI function ++static cmd_fun do_nand_cmds; ++RedBoot_nested_cmd("nand", ++ "Utility function to NAND flash using raw address", ++ "{cmds}", ++ do_nand_cmds, ++ __NAND_cmds_TAB__, &__NAND_cmds_TAB_END__ ++ ); ++ ++static void nand_usage(char *why) ++{ ++ diag_printf("*** invalid 'nand' command: %s\n", why); ++ cmd_usage(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__, "nand "); ++} ++ ++static u32 curr_addr; ++static void nand_show(int argc, char *argv[]) ++{ ++ u32 ra; ++ bool flash_addr_set = false; ++ bool spar_only = false; ++ struct option_info opts[2]; ++ ++ init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void *)&ra, (bool *)&flash_addr_set, "NAND FLASH memory byte address"); ++ init_opts(&opts[1], 's', false, OPTION_ARG_TYPE_FLG, ++ (void *)&spar_only, (bool *)0, "Spare only"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, 0)) { ++ return; ++ } ++ if (!flash_addr_set) { ++ ra = curr_addr; ++ curr_addr += NF_PG_SZ; ++ } else { ++ curr_addr = ra; ++ } ++ ++ if (ra % NF_PG_SZ) { ++ diag_printf("error: non-page aligned\n"); ++ return; ++ } ++ ++ if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) { ++ diag_printf("This is a bad block\n"); ++ } ++ ++ print_page(ra, spar_only); ++} ++ ++/*! ++ * For low level nand read command. It doesn't check for bad block or not ++ */ ++static void nand_read(int argc, char *argv[]) ++{ ++ int len; ++ u32 mem_addr, ra, col, i, pg_no, pg_off; ++ bool mem_addr_set = false; ++ bool flash_addr_set = false; ++ bool length_set = false; ++ bool col_set = false; ++ struct option_info opts[4]; ++ int j = 0; ++ bool ecc_status = g_ecc_enable;; ++ ++ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address"); ++ init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void *)&ra, (bool *)&flash_addr_set, "FLASH memory base address"); ++ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void *)&len, (bool *)&length_set, "image length [in FLASH]"); ++ init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM, ++ (void *)&col, (bool *)&col_set, "column addr"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) { ++ nand_usage("invalid arguments"); ++ return; ++ } ++ ++ if (ra % NF_PG_SZ) { ++ diag_printf("Non page-aligned read not supported here: 0x%x\n", ra); ++ return; ++ } ++ ++ if (!mem_addr_set || !flash_addr_set || !length_set) { ++ nand_usage("required parameter missing"); ++ return; ++ } ++ if ((mem_addr < (CYG_ADDRESS)ram_start) || ++ ((mem_addr+len) >= (CYG_ADDRESS)ram_end)) { ++ diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr); ++ diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end); ++ } ++ ++ // Safety check - make sure the address range is not within the code we're running ++ if (flash_code_overlaps((void *)ra, (void *)(ra+len-1))) { ++ diag_printf("Can't program this region - contains code in use!\n"); ++ return; ++ } ++ ++ if (col_set) { ++ diag_printf("Random read at page %d, column %d\n", ++ ra / NF_PG_SZ, col); ++ ++ if (g_is_2k_page || g_is_4k_page) { ++ g_ecc_enable = false; ++ } ++ nfc_read_pg_random(ra / NF_PG_SZ, col, ECC_FORCE_OFF, 0, num_of_nand_chips); ++ if (g_is_2k_page || g_is_4k_page) { ++ g_ecc_enable = ecc_status; ++ } ++ nfc_buf_mem_cpy((void *)mem_addr, (void *)NAND_MAIN_BUF0, NF_PG_SZ); ++ return; ++ } ++ ++ // insure integer multiple of page size ++ len = (len + NF_PG_SZ - 1) & ~(NF_PG_SZ - 1); ++ ++ do { ++ if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) { ++ diag_printf("Out of range: addr=0x%x\n", ra); ++ return; ++ } ++ pg_no = ra / NF_PG_SZ; ++ pg_off = ra % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ if (nfc_read_page(i, pg_no, pg_off) != 0) { ++ diag_printf("Error %d: uncorrectable ECC at addr 0x%x\n", __LINE__, ra); ++ diag_printf("should invoke bad block management to replace this block \n"); ++ diag_printf("and then mark this block \"bad\". But Redboot doesn't do it yet.\n"); ++ } ++ if ((j++ % 0x20) == 0) ++ diag_printf("\n%s 0x%08x: ", __FUNCTION__, ra); ++ diag_printf("."); ++ ++ nfc_buf_mem_cpy((void *)mem_addr, (void *)NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips); ++ ++ ra += NF_PG_SZ / num_of_nand_chips; ++ mem_addr += NF_PG_SZ / num_of_nand_chips; ++ len -= NF_PG_SZ / num_of_nand_chips; ++ pg_off = 0; ++ } ++ } while (len > 0); ++ diag_printf("\n"); ++} ++ ++static void nand_write(int argc, char *argv[]) ++{ ++ int len, len_st, j = 0; ++ u32 mem_addr, mem_addr_st, ra, col; ++ bool mem_addr_set = false; ++ bool flash_addr_set = false; ++ bool length_set = false; ++ bool col_set = false; ++ struct option_info opts[4]; ++ bool ecc_status = g_ecc_enable; ++ int skip = 0; ++ ++ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&mem_addr, (bool *)&mem_addr_set, "memory base address"); ++ init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void *)&ra, (bool *)&flash_addr_set, "FLASH memory base address"); ++ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void *)&len, (bool *)&length_set, "image length [in FLASH]"); ++ init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM, ++ (void *)&col, (bool *)&col_set, "column addr"); ++ if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) ++ { ++ nand_usage("invalid arguments"); ++ return; ++ } ++ ++ if (!mem_addr_set || !flash_addr_set || !length_set) { ++ nand_usage("required parameter missing"); ++ return; ++ } ++ ++ if ((mem_addr < (CYG_ADDRESS)ram_start) || ++ ((mem_addr+len) >= (CYG_ADDRESS)ram_end)) { ++ diag_printf("** WARNING: RAM address: %p may be invalid\n", (void *)mem_addr); ++ diag_printf(" valid range is %p-%p\n", (void *)ram_start, (void *)ram_end); ++ } ++ ++ if (col_set) { ++ diag_printf("Random write at page %d, column %d\n", ra / NF_PG_SZ, col); ++ ++ if (g_is_2k_page || g_is_4k_page) { ++ g_ecc_enable = false; ++ } ++ nfc_write_pg_random(ra / NF_PG_SZ, col, mem_addr, 0, FILE_FORMAT_NORMAL); ++ if (g_is_2k_page || g_is_4k_page) { ++ g_ecc_enable = ecc_status; ++ } ++ return; ++ } ++ ++ if ((ra % NF_PG_SZ) != 0) { ++ diag_printf("Need a Page-aligned address in Flash\n\n"); ++ return; ++ } ++ ++ if ((len % NF_PG_SZ) != 0) { ++ diag_printf("Not a full page write?\n\n"); ++ } ++ ++ mem_addr_st = mem_addr; ++ len_st = len; ++ do { ++ if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) { ++ diag_printf("Out of range: addr=0x%x\n", ra); ++ return; ++ } ++ if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) { ++ diag_printf("\nWarning: skipping bad block at raw addr=0x%x(block=%d)\n", ++ ra, OFFSET_TO_BLOCK(ra)); ++ ra = (OFFSET_TO_BLOCK(ra) + 1) * NF_BLK_SZ; ++ skip++; ++ continue; ++ } ++ ++ if ((ra % NF_BLK_SZ) == 0) { ++ mem_addr_st = mem_addr; ++ len_st = len; ++ } ++ if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, mem_addr, 0, FILE_FORMAT_NORMAL) != 0) { ++ if (g_nfc_debug_level >= NFC_DEBUG_DEF) { ++ diag_printf("Warning %d: program error at addr 0x%x\n", __LINE__, ra); ++ } ++ mark_blk_bad(OFFSET_TO_BLOCK(ra), g_bbt, BLK_BAD_RUNTIME); ++ ra = (OFFSET_TO_BLOCK(ra) + 1) * NF_BLK_SZ; //make sure block size aligned ++ mem_addr = mem_addr_st; // rewind to blocl boundary ++ len = len_st; ++ continue; ++ } ++ if ((j++ % 0x20) == 0) ++ diag_printf("\nProgramming 0x%08x: ", ra); ++ diag_printf("."); ++ ++ len -= NF_PG_SZ; ++ ra += NF_PG_SZ; ++ mem_addr += NF_PG_SZ; ++ } while (len > 0); ++ if (skip) { ++ diag_printf("\n%s(skip bad blocks=%d\n\n", __FUNCTION__, skip); ++ } ++ diag_printf("\n"); ++} ++ ++void nand_debug_fun(int argc, char *argv[]) ++{ ++ int opt; ++ ++ if (argc == 3) { ++ opt = argv[2][0] - '0'; ++ switch (opt) { ++ case 0: ++ g_nfc_debug_level = NFC_DEBUG_MIN; ++ break; ++ case 1: ++ g_nfc_debug_level = NFC_DEBUG_MED; ++ break; ++ case 2: ++ g_nfc_debug_level = NFC_DEBUG_MAX; ++ break; ++ case 3: ++ g_ecc_enable = g_ecc_enable? false: true; ++ break; ++ case 4: ++ // toggle g_spare_only_read_ok ++ g_spare_only_read_ok = g_spare_only_read_ok? false: true; ++ break; ++ case 9: ++ g_nfc_debug_measure = g_nfc_debug_measure? false: true; ++ break; ++ ++ default: ++ diag_printf("%s(%s) not supported\n", __FUNCTION__, argv[2]); ++ break; ++ ++ } ++ } ++ diag_printf("Current debug options are: \n"); ++ diag_printf(" h/w ECC: %s\n", g_ecc_enable ? "on":"off"); ++ diag_printf(" sp-only read: %s\n", g_spare_only_read_ok ? "on":"off"); ++ diag_printf(" measurement: %s\n", g_nfc_debug_measure ? "on":"off"); ++ diag_printf(" message level: %s\n", (g_nfc_debug_level == NFC_DEBUG_MIN) ? "min" : \ ++ ((g_nfc_debug_level == NFC_DEBUG_MED) ? "med" : "max")); ++} ++ ++static void nand_erase(int argc, char *argv[]) ++{ ++ u32 len, ra; ++ bool faddr_set = false; ++ bool force_erase_set = false; ++ bool length_set = false; ++ struct option_info opts[4]; ++ ++ init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void **)&ra, (bool *)&faddr_set, "FLASH memory base address"); ++ init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void **)&len, (bool *)&length_set, "length in bytes"); ++ init_opts(&opts[2], 'o', false, OPTION_ARG_TYPE_FLG, ++ (void **)&force_erase_set, (bool *)&force_erase_set, "force erases block"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 3, 0, 0, 0)) { ++ nand_usage("invalid arguments"); ++ return; ++ } ++ ++ if (!faddr_set || !length_set) { ++ nand_usage("missing argument"); ++ return; ++ } ++ if ((ra % NF_BLK_SZ) != 0 || ++ (len % NF_BLK_SZ) != 0 || len == 0) { ++ diag_printf("Address or length is not block aligned or length is zero!\n"); ++ diag_printf("Block size is 0x%x\n", NF_BLK_SZ); ++ return; ++ } ++ ++ if (!verify_action("About to erase 0x%x bytes from nand offset 0x%x\n", len, ra)) { ++ diag_printf("** Aborted\n"); ++ return; ++ } ++ ++ // now ra is block aligned ++ if (force_erase_set == true) { ++ diag_printf("Force erase ..."); ++ nfc_erase_region(ra, len, 0, 1); ++ diag_printf("\n"); ++ } else { ++ nfc_erase_region(ra, len, 1, 1); ++ } ++ diag_printf("\n"); ++} ++ ++extern void romupdate(int argc, char *argv[]); ++static void nand_scan(int argc, char *argv[]) ++{ ++ bool force_erase = false; ++ bool force_rescan = false; ++ struct option_info opts[2]; ++ ++ init_opts(&opts[0], 'o', false, OPTION_ARG_TYPE_FLG, ++ (void *)&force_erase, (bool *)0, "force erases block first"); ++ ++ init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG, ++ (void *)&force_rescan, (bool *)0, "force low level re-scan"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 2, 0, 0, 0)) { ++ nand_usage("invalid arguments"); ++ return; ++ } ++ ++ if (!force_erase && !force_rescan && !g_main_bbt_addr) { ++ diag_printf("Need to build BBT table first with \"nand scan [-o|-r]\"\n"); ++ return; ++ } ++ if (force_erase) { ++ diag_printf("Force erase first ...\n"); ++ memset(g_bbt, -1, g_bbt_sz); ++ // do force erase, including bad blocks. After this call, g_bbt should be re-built ++ // for the whole NAND flash. ++ nfc_erase_region(0, NF_DEV_SZ, 0, 1); ++ g_main_bbt_addr = 0; ++ diag_printf("\n"); ++ } ++ if (force_rescan) { ++ diag_printf("Force re-scan ...\n"); ++ memset(g_bbt, -1, g_bbt_sz); ++ mxc_nfc_scan(true); ++ g_main_bbt_addr = 0; ++ } ++ // program g_bbt into the flash ++ diag_printf("Writing Bbt0 to flash\n"); ++ if (program_bbt_to_flash() != 0) { ++ diag_printf("ERROR: TOO BAD! What can I do?\n"); ++ } else ++ diag_printf("Format successful\n"); ++ ++ if (force_erase) { ++ romupdate(0, (char **)NULL); ++ } ++} ++ ++static void nand_info(int argc, char *argv[]) ++{ ++ u32 i, j = 0; ++ ++ if (nand_flash_index == -1) { ++ diag_printf("Can't find valid NAND flash: %d\n", __LINE__); ++ return; ++ } ++ ++ diag_printf("\nType:\t\t %s\n", NF_VEND_INFO); ++ diag_printf("Total size:\t 0x%08x bytes (%d MB)\n", NF_DEV_SZ, NF_DEV_SZ/0x100000); ++ diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT); ++ diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ); ++ diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ); ++ diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK); ++ ++ if (mxc_nfc_scan(false) == -1) { ++ return; ++ } ++ diag_printf("\n"); ++ for (i = 0; i < NF_BLK_CNT; i++) { ++ if (nfc_is_badblock(i, g_bbt)) { ++ diag_printf("block %d at offset 0x%x is bad\n", i, i * NF_BLK_SZ); ++ j++; ++ } ++ } ++ diag_printf("==================================\n"); ++ diag_printf("Found %d bad block(s) out of %d\n\n", j, i); ++} ++ ++static void do_nand_cmds(int argc, char *argv[]) ++{ ++ struct cmd *cmd; ++ ++ if (!mxcnfc_init_ok) { ++ diag_printf("\nWarning:NAND flash hasn't been initialized. Try \"factive nand\" first\n\n"); ++ return; ++ } ++ ++ if (argc < 2) { ++ nand_usage("too few arguments"); ++ return; ++ } ++ ++ if ((cmd = cmd_search(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__, ++ argv[1])) != (struct cmd *)0) { ++ (cmd->fun)(argc, argv); ++ return; ++ } ++ nand_usage("unrecognized command"); ++} ++ ++/*! ++ * Display a memory region by 16-bit words ++ * @param pkt pointer to the starting address of the memory ++ * @param len byte length of the buffer to be displayed ++ */ ++static void print_pkt_16(u16* pkt, u32 len) ++{ ++ diag_printf("******************** %d bytes********************\n", len); ++ u32 i = 0, tempLen = (len + 1) / 2; ++ ++ while(tempLen >= 0) ++ { ++ if(tempLen >= 8) { ++ diag_printf("[%03x-%03x] ", i*2, ((i*2)+14)); ++ diag_printf("%04x %04x %04x %04x %04x %04x %04x %04x\n", ++ pkt[i], pkt[i+1], pkt[i+2], pkt[i+3], ++ pkt[i+4], pkt[i+5], pkt[i+6], pkt[i+7]); ++ } ++ else { ++ if (tempLen == 0) { ++ diag_printf("*************************************************\n"); ++ return; ++ } ++ diag_printf("[%03x-%03x] ", i*2, ((i*2)+14)); ++ switch(tempLen) { ++ case 1: ++ diag_printf("%04x\n", pkt[i]); ++ break; ++ case 2: ++ diag_printf("%04x %04x\n", pkt[i], pkt[i+1]); ++ break; ++ case 3: ++ diag_printf("%04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2]); ++ break; ++ case 4: ++ diag_printf("%04x %04x %04x %04x\n", pkt[i],pkt[i+1], pkt[i+2],pkt[i+3]); ++ break; ++ case 5: ++ diag_printf("%04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4]); ++ break; ++ case 6: ++ diag_printf("%04x %04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4], ++ pkt[i+5]); ++ break; ++ case 7: ++ diag_printf("%04x %04x %04x %04x %04x %04x %04x\n", pkt[i], pkt[i+1], pkt[i+2], pkt[i+3],pkt[i+4], ++ pkt[i+5], pkt[i+6]); ++ break; ++ } ++ } ++ tempLen -= 8; ++ i += 8; ++ } ++} ++ ++// addr = starting byte address within NAND flash ++static void print_page (u32 addr, bool spare_only) ++{ ++ u32 i, pg_no, pg_off; ++ u32 blk_num = OFFSET_TO_BLOCK(addr), pg_num = OFFSET_TO_PAGE(addr); ++ ++ if (addr % NF_PG_SZ) { ++ diag_printf("Non page-aligned read not supported here: 0x%x\n", addr); ++ return; ++ } ++ if (spare_only) { ++ diag_printf("Error %d: Not supported\n", __LINE__); ++ return; ++ } else { ++ pg_no = addr / NF_PG_SZ; ++ pg_off = addr % NF_PG_SZ; ++ for (i = 0; i < num_of_nand_chips; i++) { ++ if(nfc_read_page(i, pg_no, pg_off) != 0) { ++ diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__); ++ } ++ pg_off = 0; ++ diag_printf("\n============ Printing block(%d) page(%d) ==============\n", ++ blk_num, pg_num); ++ ++ diag_printf("<<<<<<<<< spare area >>>>>>>>>\n"); ++ print_pkt_16((u16*)(NAND_SPAR_BUF0), 16); ++ ++ if (!spare_only) { ++ diag_printf("<<<<<<<<< main area >>>>>>>>>\n"); ++ print_pkt_16((u16*)(NAND_MAIN_BUF0), (NF_PG_SZ / num_of_nand_chips)); ++ } ++ ++ diag_printf("\n"); ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcflash_wrapper.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcflash_wrapper.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcflash_wrapper.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcflash_wrapper.c 2010-01-26 17:33:13.022965134 +0000 +@@ -0,0 +1,345 @@ ++//========================================================================== ++// ++// mxcflash_wrapper.c ++// ++// Flash programming wrapper to support both NOR and NAND flashes ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-01-23 ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++ ++extern void norflash_query(void* data); ++extern int norflash_hwr_init(void); ++extern int norflash_hwr_map_error(int e); ++extern bool norflash_code_overlaps(void *start, void *end); ++extern int norflash_erase_block(void* block, unsigned int size); ++extern int norflash_program_buf(void* addr, void* data, int len); ++extern int norflash_lock_block(void* block); ++extern int norflash_unlock_block(void* block, int block_size, int blocks); ++ ++extern void nandflash_query(void* data); ++extern int nandflash_hwr_init(void); ++extern int nandflash_hwr_map_error(int e); ++extern bool nandflash_code_overlaps(void *start, void *end); ++extern int nandflash_erase_block(void* block, unsigned int size); ++extern int nandflash_program_buf(void* addr, void* data, int len); ++extern int nandflash_lock_block(void* block); ++extern int nandflash_unlock_block(void* block, int block_size, int blocks); ++extern void mxc_nfc_print_info(void); ++extern int nandflash_read_buf(void* addr, void* data, int len); ++ ++extern void mmcflash_query(void* data); ++extern int mmcflash_hwr_init(void); ++extern int mmcflash_hwr_map_error(int e); ++extern bool mmcflash_code_overlaps(void *start, void *end); ++extern int mmcflash_erase_block(void* block, unsigned int size); ++extern int mmcflash_program_buf(void* addr, void* data, int len); ++extern int mmcflash_lock_block(void* block); ++extern int mmcflash_unlock_block(void* block, int block_size, int blocks); ++extern void mxc_mmc_print_info(void); ++extern int mmcflash_read_buf(void* addr, void* data, int len); ++ ++extern void spi_norflash_query(void* data); ++extern int spi_norflash_hwr_init(void); ++extern int spi_norflash_hwr_map_error(int e); ++extern bool spi_norflash_code_overlaps(void *start, void *end); ++extern int spi_norflash_erase_block(void* block, unsigned int size); ++extern int spi_norflash_program_buf(void* addr, void* data, int len); ++extern int spi_norflash_lock_block(void* block); ++extern int spi_norflash_unlock_block(void* block, int block_size, int blocks); ++extern int spi_norflash_read_buf(void* addr, void* data, int len); ++ ++#ifndef IS_BOOTING_FROM_SPI_NOR() ++#define IS_BOOTING_FROM_SPI_NOR() 0 ++#endif ++#ifndef IS_FIS_FROM_SPI_NOR() ++#define IS_FIS_FROM_SPI_NOR() 0 ++#endif ++ ++static int mxc_flash_warning_done = 0; ++ ++void flash_query(void* data) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ norflash_query(data); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ spi_norflash_query(data); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++ nandflash_query(data); ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ mmcflash_query(data); ++#endif ++ } else { ++ if (!mxc_flash_warning_done) { ++ mxc_flash_warning_done = 1; ++ diag_printf("1: Use \"factive\" to select a boot type such as NAND|NOR|MMC|...\n"); ++ } ++ } ++} ++ ++int flash_hwr_init(void) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_hwr_init(); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_norflash_hwr_init(); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_hwr_init(); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_hwr_init(); ++#endif ++ } else { ++ if (!mxc_flash_warning_done) ++ mxc_flash_warning_done = 1; ++ diag_printf("2: Use \"factive\" to select a boot type such as NAND|NOR|MMC|...\n"); ++ return -1; ++ } ++ ++ return -1; ++} ++ ++int flash_hwr_map_error(int e) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_hwr_map_error(e); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_hwr_map_error(e); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_norflash_hwr_map_error(e); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_hwr_map_error(e); ++#endif ++ } ++ return e; ++} ++ ++bool flash_code_overlaps(void *start, void *end) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_code_overlaps(start, end); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_norflash_code_overlaps(start, end); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_code_overlaps(start, end); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){ ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_code_overlaps(start, end); ++#endif ++ } else { ++ diag_printf("Error %d: where is fis\n", __LINE__); ++ return true; ++ } ++ return false; ++} ++ ++int flash_erase_block(void* block, unsigned int size) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_erase_block(block, size); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_norflash_erase_block(block, size); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_erase_block(block, size); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){ ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_erase_block(block, size); ++#endif ++ } else { ++ diag_printf("Error %d: where is fis\n", __LINE__); ++ return -1; ++ } ++ return 0; ++} ++ ++int flash_program_buf(void* addr, void* data, int len) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_program_buf(addr, data, len); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_norflash_program_buf(addr, data, len); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_program_buf(addr, data, len); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_program_buf(addr, data, len); ++#else ++ return 0; ++#endif ++ } else { ++ return -1; ++ } ++} ++ ++int flash_read_buf(void* addr, void* data, int len) ++{ ++ if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()){ ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_read_buf(addr, data, len); ++#endif ++ } else if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ memcpy(data, addr, len); ++ return 0; ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()){ ++#ifdef IMXFLASH_SELECT_SPI_NOR ++ return spi_nor_read(addr, data, len); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()) { ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_read_buf(addr, data, len); ++#endif ++ } else { ++ return -1; ++ } ++ return 0; ++} ++ ++int flash_lock_block(void* block) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_lock_block(block); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_lock_block(block); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_lock_block(block); ++#endif ++ } ++ return 0; ++} ++ ++int flash_unlock_block(void* block, int block_size, int blocks) ++{ ++ if (IS_BOOTING_FROM_NOR() || IS_FIS_FROM_NOR()) { ++#ifdef MXCFLASH_SELECT_NOR ++ return norflash_unlock_block(block, block_size, blocks); ++#endif ++ } else if (IS_BOOTING_FROM_MMC() || IS_FIS_FROM_MMC()){ ++#ifdef MXCFLASH_SELECT_MMC ++ return mmcflash_unlock_block(block, block_size, blocks); ++#endif ++ } else if (IS_BOOTING_FROM_NAND() || IS_FIS_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ return nandflash_unlock_block(block, block_size, blocks); ++#endif ++ } ++ return 0; ++} ++ ++static void mxc_flash_print_info(void) ++{ ++ if (IS_BOOTING_FROM_NOR()) { ++ diag_printf("\nBooting from [NOR flash]\n"); ++ } else if (IS_BOOTING_FROM_NAND()) { ++#ifdef MXCFLASH_SELECT_NAND ++ diag_printf("\nBooting from [NAND flash]\n"); ++ mxc_nfc_print_info(); ++#endif ++ } else if (IS_BOOTING_FROM_SPI_NOR()) { ++#ifdef MXCFLASH_SELECT_SPI_NOR ++ diag_printf("\nBooting from [SPI NOR flash]\n"); ++ imx_spi_nor_print_info(); ++#endif ++ } else if (IS_BOOTING_FROM_SDRAM()) { ++ diag_printf("\nBooting from [SDRAM]\n"); ++ } else if (IS_BOOTING_FROM_MMC() ){ ++#ifdef MXCFLASH_SELECT_MMC ++ mxc_mmc_print_info(); ++#else ++ return; ++#endif ++ } ++ diag_printf("\n"); ++} ++ ++RedBoot_init(mxc_flash_print_info, RedBoot_INIT_LAST); +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_core.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_core.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_core.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_core.c 2010-01-26 17:33:13.022965134 +0000 +@@ -0,0 +1,481 @@ ++// ========================================================================== ++// ++// mxcmci_core.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++ ++static cyg_uint32 csd_get_value(cyg_uint32 * pcsd, cyg_uint32 start_bit, ++ cyg_uint32 end_bit); ++ ++#define MMCSD_INIT_DELAY 64 ++ ++cyg_uint32 Card_rca = 0x1; /* Relative Card Address */ ++card_ident Card_identification; /* Card Identification Data */ ++card_type Card_type; /* Card Type */ ++cyg_uint32 MMC_Spec_vers = 0x1; /* Spec vers used for MMC */ ++card_specific_data csd; /* Global variable for Card Specific Data */ ++cyg_uint32 Card_capacity_size = 0; /*Card capacity size */ ++cyg_uint32 CCC = 0; /* Card Command Class */ ++int Card_Mode = 2; ++int HighCapacityCard = 0; ++ ++/*========================================================================== ++ Global FUNCTIONS ++==========================================================================*/ ++ ++cyg_uint32 mxcmci_init(cyg_uint32 bus_width, cyg_uint32 base_address) ++{ ++ cyg_uint32 init_status = FAIL; ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to init base address...\n", ++ __FUNCTION__); ++ /* initialize Interface Controller */ ++ host_init(base_address); ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to software reset...\n", ++ __FUNCTION__); ++ ++ /* Software Reset to Interface Controller */ ++ host_reset(ESDHC_ONE_BIT_SUPPORT, ESDHC_LITTLE_ENDIAN_MODE); ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to set identification freq...\n", ++ __FUNCTION__); ++ ++ /* Enable Identification Frequency */ ++ host_cfg_clock(IDENTIFICATION_FREQ); ++ ++ /* Add delay of 2 msec, let mmc/sd card to initialize */ ++ hal_delay_us(2 * 1000); ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to software resetto card...\n", ++ __FUNCTION__); ++ ++ //diag_printf("SW Reset...\n"); ++ /* Issue Software Reset to card */ ++ if (mxcmci_software_reset()) ++ return FAIL; ++ ++ //diag_printf("Check Card...\n"); ++ ++ /* Check if the card is SD Memory Card */ ++ if (!sd_voltage_validation()) { ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to verify SD card...\n", ++ __FUNCTION__); ++ /* Call SD Initialization Function */ ++ init_status = sd_init(bus_width); ++ Card_type = ++ ((csd.csd3 & CSD_STRUCT_MSK) ? SD_CSD_2_0 : SD_CSD_1_0); ++ Card_Mode = 1; ++ /* Card Command Class */ ++ CCC = csd_get_value(&csd, 84, 95); ++ } else { ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:try to verify MMC card...\n", ++ __FUNCTION__); ++ /* Check if the card is MMC Memory Card */ ++ if (!mmc_voltage_validation()) { ++ ++ /* Call MMC Initialization Function */ ++ init_status = mmc_init(bus_width); ++ Card_Mode = 0; ++ Card_type = ((csd.csd3 & CSD_STRUCT_MSK) >> CSD_STRUCT_SHIFT) + SD_CSD_2_0; ++ MMC_Spec_vers = (csd.csd3 & MMC_CSD_SPEC_VERS_MASK) >> MMC_CSD_SPEC_VERS_SHIFT; ++ /* Card Command Class */ ++ CCC = csd_get_value(&csd, 84, 95); ++ } ++ } ++ ++ return init_status; ++} ++ ++/*========================================================================== ++FUNCTION: static cyg_uint32 card_get_csd (void) ++DESCRIPTION: ++ this function will read MMC/SD CSD register and store in the global Variable. ++ ++ARGUMENTS PASSED: ++ None ++ ++RETURN VALUE: ++ cyg_uint32 ++ ++PRE-CONDITIONS: ++ None ++ ++POST-CONDITIONS: ++ None ++ ++Detailed Description: ++ 1.Send CMD9 to get CSD value of MMC/SD Card. ++ 2.Extract CSD value from CMDRSP0,CMDRSP1,CMDRSP2,CMDRSP3 registers. ++==============================================================================*/ ++cyg_uint32 card_get_csd(void) ++{ ++ ++ command_t cmd; ++ command_response_t response; ++ cyg_uint32 status = FAIL; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD9 for MMC/SD card */ ++ /* 16bit card address is expected as Argument */ ++ mxcmci_cmd_config(&cmd, CMD9, card_address, READ, RESPONSE_136, ++ DATA_PRESENT_NONE, ENABLE, DISABLE); ++ ++ /* Issue Command CMD9 to Extrace CSD register contents */ ++ ++ if (host_send_cmd(&cmd) != FAIL) { ++ /* Read Command response */ ++ response.format = RESPONSE_136; ++ host_read_response(&response); ++ ++ /* Assign Response to CSD Strcuture */ ++ csd.csd0 = response.cmd_rsp0; ++ csd.csd1 = response.cmd_rsp1; ++ csd.csd2 = response.cmd_rsp2; ++ csd.csd3 = response.cmd_rsp3; ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "CSD:%x:%x:%x:%x\n", csd.csd0, ++ csd.csd1, csd.csd2, csd.csd3); ++ status = SUCCESS; ++ } else { ++ diag_printf("Get CSD Failed.\n"); ++ } ++ ++ return status; ++ ++} ++ ++static cyg_uint32 csd_get_value(cyg_uint32 * pcsd, cyg_uint32 start_bit, ++ cyg_uint32 end_bit) ++{ ++ cyg_uint32 index = (start_bit / 32); ++ cyg_uint32 end_index = (end_bit / 32); ++ cyg_uint32 offset = (start_bit - 8) % 32; ++ cyg_uint32 end_offset = (end_bit - 8) % 32; ++ cyg_uint32 value; ++ cyg_uint32 temp; ++ //pcsd = &(csd.csd0); ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "start_bit=%d, end_bit=%d, index=%d, end_index=%d, offset=%d\n", ++ start_bit, end_bit, index, end_index, offset); ++ ++ if (index == end_index) { ++ flash_dprintf(FLASH_DEBUG_MAX, "onl1y in index register\n"); ++ value = ++ (*((cyg_uint32 *) ((cyg_uint32) pcsd + (index << 2)))) & ++ ((1 << (end_offset + 1)) - (1 << offset)); ++ value = (value >> offset); ++ } else { ++ flash_dprintf(FLASH_DEBUG_MAX, "index and index+1 registers\n"); ++ value = ++ *((cyg_uint32 *) ((cyg_uint32) pcsd + ++ (index << 2))) & (0xFFFFFFFF - ++ (1 << offset) + 1); ++ value = (value >> offset); ++ temp = (1 << (offset + end_bit - start_bit - 31)) - 1; ++ temp = ++ (*((cyg_uint32 *) ((cyg_uint32) pcsd + (index + 1) * 4)) & ++ temp); ++ value += temp << (32 - offset); ++ } ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:value=%x (CSD:%x:%x:%x:%x)\n", ++ __FUNCTION__, value, *pcsd, *(pcsd + 1), *(pcsd + 2), ++ *(pcsd + 3)); ++ return value; ++ ++} ++ ++cyg_uint32 card_get_capacity_size(void) ++{ ++ cyg_uint32 capacity = 0; ++ cyg_uint32 c_size, c_size_mult, blk_len; ++ ++ if (!csd.csd0 && !csd.csd1 && !csd.csd2 && !csd.csd3) ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "WARNINGS:mxcmci_init should be done first!\n"); ++ ++ switch (Card_type) { ++ case SD_CSD_1_0: ++ case MMC_CSD_1_0: ++ case MMC_CSD_1_1: ++ case MMC_CSD_1_2: ++ c_size = csd_get_value(&csd, 62, 73); ++ c_size_mult = csd_get_value(&csd, 47, 49); ++ blk_len = csd_get_value(&csd, 80, 83); ++ capacity = (c_size + 1) << (c_size_mult + 2 + blk_len - 10); ++ break; ++ case SD_CSD_2_0: ++ //blk_len = csd_get_value(&csd, 80, 83); ++ c_size = csd_get_value(&csd, 48, 69); ++ capacity = (c_size + 1) * 512; /* block length is fixed to 512B */ ++ break; ++ default: ++ capacity = 1; ++ break; ++ } ++ ++ /* check whether the card is high capacity card */ ++ if(capacity>2*1024*1024) ++ HighCapacityCard = 1; ++ else ++ HighCapacityCard = 0; ++ ++ return capacity; ++ ++} ++ ++cyg_uint32 mxcmci_data_read(cyg_uint32 * dest_ptr, cyg_uint32 len, ++ cyg_uint32 offset) ++{ ++ cyg_uint32 read_status = FAIL; ++ ++ read_status = mmc_data_read(dest_ptr, len, offset); ++ ++ if (read_status) { ++ len = 0; ++ } ++ return len; ++ ++} ++ ++cyg_uint32 mxcmci_software_reset(void) ++{ ++ command_t cmd; ++ cyg_uint32 response = FAIL; ++ ++ /*Configure CMD0 for MMC/SD card */ ++ /*CMD0 doesnt expect any response */ ++ mxcmci_cmd_config(&cmd, CMD0, NO_ARG, READ, RESPONSE_NONE, ++ DATA_PRESENT_NONE, DISABLE, DISABLE); ++ ++ /*Issue CMD0 to MMC/SD card to put in active state */ ++ if (host_send_cmd(&cmd) != FAIL) { ++ response = SUCCESS; ++ } else { ++ diag_printf("Card SW Reset Failed.\n"); ++ } ++ ++ return response; ++} ++ ++cyg_uint32 mxcmci_get_cid(void) ++{ ++ ++ command_t cmd; ++ cyg_uint32 cid_request = FAIL; ++ command_response_t response; ++ ++ /* Configure CMD2 for card */ ++ /* No Argument is expected for CMD2 */ ++ mxcmci_cmd_config(&cmd, CMD2, NO_ARG, READ, RESPONSE_136, ++ DATA_PRESENT_NONE, ENABLE, DISABLE); ++ ++ /* Issue CMD2 to card to determine CID contents */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ cid_request = FAIL; ++ diag_printf("Send CMD2 Failed.\n"); ++ } else { ++ /* Read Command response */ ++ response.format = RESPONSE_136; ++ host_read_response(&response); ++ ++ /* Assign CID values to mmc_cid structures */ ++ Card_identification.cid0 = response.cmd_rsp0; ++ Card_identification.cid1 = response.cmd_rsp1; ++ Card_identification.cid2 = response.cmd_rsp2; ++ Card_identification.cid3 = response.cmd_rsp3; ++ ++ /* Assign cid_request as SUCCESS */ ++ cid_request = SUCCESS; ++ } ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:CID=%X:%X:%X:%X\n", __FUNCTION__, ++ Card_identification.cid0, Card_identification.cid1, ++ Card_identification.cid2, Card_identification.cid3); ++ return cid_request; ++} ++ ++cyg_uint32 mxcmci_trans_prepare(void) ++{ ++ command_t cmd; ++ cyg_uint32 card_state = 0; ++ cyg_uint32 transfer_status = 0; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD7 for MMC card */ ++ /* 16bit card address is expected as Argument */ ++ mxcmci_cmd_config(&cmd, CMD7, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Sending the card from stand-by to transfer state */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ transfer_status = FAIL; ++ diag_printf("Send CMD7 Failed.\n"); ++ } else { ++ ++ /* Configure CMD13 to read status of the card becuase CMD7 has R1b response */ ++ mxcmci_cmd_config(&cmd, CMD13, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ transfer_status = FAIL; ++ diag_printf("Send CMD13 Failed.\n"); ++ } else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ card_state = CURR_CARD_STATE(response.cmd_rsp0); ++ ++ if (card_state == TRAN) { ++ transfer_status = SUCCESS; ++ ++ } else { ++ diag_printf("card_state: 0x%x\n", card_state); ++ transfer_status = FAIL; ++ } ++ } ++ ++ } ++ ++ return transfer_status; ++ ++} ++ ++cyg_uint32 mxcmci_trans_status(void) ++{ ++ command_t cmd; ++ cyg_uint32 card_state = 0; ++ cyg_uint32 transfer_status = 0; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD13 to read status of the card becuase CMD7 has R1b response */ ++ mxcmci_cmd_config(&cmd, CMD13, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("Fail, CMD13\n"); ++ transfer_status = FAIL; ++ } ++ ++ else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ card_state = CURR_CARD_STATE(response.cmd_rsp0); ++ ++ if (card_state == TRAN) { ++ transfer_status = SUCCESS; ++ //diag_printf("card_state: 0x%x\n", card_state); ++ } ++ ++ else { ++ //diag_printf("card_state: 0x%x\n", card_state); ++ transfer_status = FAIL; ++ } ++ } ++ return transfer_status; ++ ++} ++ ++void mxcmci_cmd_config(command_t * cmd_config, cyg_uint32 index, ++ cyg_uint32 argument, xfer_type_t transfer, ++ response_format_t format, data_present_select data, ++ crc_check_enable crc, cmdindex_check_enable cmdindex) ++{ ++ ++ command_t *cmd; ++ ++ /* Assign cmd to cmd_config */ ++ cmd = cmd_config; ++ ++ /* Configure Command index */ ++ cmd->command = index; ++ ++ /* Configure Command Argument */ ++ cmd->arg = argument; ++ ++ /* Configure Data transfer type */ ++ cmd->data_transfer = transfer; ++ ++ /* Configure Response Format */ ++ cmd->response_format = format; ++ ++ /* Configure Data Present Select */ ++ cmd->data_present = data; ++ ++ /* Configiure CRC check Enable */ ++ cmd->crc_check = crc; ++ ++ /*Configure Command index check enable */ ++ cmd->cmdindex_check = cmdindex; ++ ++ /* if multi-block is used */ ++ if (CMD18 == index || CMD25 == index) { ++ /*Configure Block count enable */ ++ cmd->block_count_enable_check = ENABLE; ++ /*Configure Multi single block select */ ++ cmd->multi_single_block = MULTIPLE; ++ } else { ++ /*Configure Block count enable */ ++ cmd->block_count_enable_check = DISABLE; ++ ++ /*Configure Multi single block select */ ++ cmd->multi_single_block = SINGLE; ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_host.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_host.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_host.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_host.c 2010-01-26 17:33:13.032961509 +0000 +@@ -0,0 +1,491 @@ ++// ========================================================================== ++// ++// mxcmci_host.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++ ++host_register_ptr esdhc_base_pointer; ++extern void mxc_mmc_init(unsigned int module_base); ++ ++static void esdhc_cmd_config(command_t *); ++static int esdhc_wait_end_cmd_resp_intr(void); ++static cyg_uint32 esdhc_check_response(void); ++static void esdhc_wait_buf_rdy_intr(cyg_uint32, multi_single_block_select); ++static void esdhc_wait_op_done_intr(cyg_uint32); ++static cyg_uint32 esdhc_check_data(cyg_uint32, cyg_uint32, cyg_uint32); ++static void esdhc_set_data_transfer_width(cyg_uint32 data_transfer_width); ++static void esdhc_set_endianness(cyg_uint32 endian_mode); ++static int esdhc_check_for_send_cmd(int data_present); ++ ++void host_reset(cyg_uint32 data_transfer_width, cyg_uint32 endian_mode) ++{ ++ int counter = 0; ++ ++ /* Reset the entire host controller by writing 1 to RSTA bit of SYSCTRL Register */ ++ esdhc_base_pointer->system_control |= ESDHC_SOFTWARE_RESET; ++ ++ //use WDOG timer: 3 ms delay ++ hal_delay_us(3 * 1000); ++ ++ /* Wait for clearance of CIHB and CDIHB Bits */ ++ while (esdhc_base_pointer->present_state & ESDHC_CMD_INHIBIT) { ++ if (counter++ > 200) { ++ diag_printf ++ ("%s: something goes wrong with the DSDHC and int is not received!\n", ++ __FUNCTION__); ++ counter = 0; ++ break; ++ } ++ } ++ ++ /* send 80 clock ticks for card to power up */ ++ esdhc_base_pointer->system_control |= ESDHC_SOFTWARE_INIT; ++ ++ /* Set data bus width of ESDCH */ ++ esdhc_set_data_transfer_width(data_transfer_width); ++ ++ /* Set Endianness of ESDHC */ ++ esdhc_set_endianness(endian_mode); ++ ++} ++ ++void esdhc_softreset(cyg_uint32 mask) ++{ ++ //wait max timeout 100ms ++ cyg_uint32 timeout = 100; ++ ++ esdhc_base_pointer->system_control |= mask; ++ ++ /* hw clears the bit when it's done */ ++ while (esdhc_base_pointer->system_control & mask) { ++ if (timeout == 0) { ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "%s:Reset 0x%X never complete!\n"); ++ return; ++ } ++ timeout--; ++ hal_delay_us(100); ++ } ++} ++ ++void host_init(cyg_uint32 base_address) ++{ ++ esdhc_base_pointer = (host_register_ptr) base_address; ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s: interface_esdc=%d\n", __FUNCTION__, ++ base_address); ++ ++ mxc_mmc_init(base_address); ++} ++ ++void host_cfg_clock(sdhc_freq_t frequency) ++{ ++ unsigned int timeout = 9000; ++ /* Enable ipg_perclk, HCLK enable, IPG Clock enable. */ ++ esdhc_base_pointer->system_control |= ESDHC_CLOCK_ENABLE; ++ ++ esdhc_base_pointer->system_control |= 0xe0000; //set timeout counter ++ ++ /* Clear DTOCV SDCLKFS bits, clear SD clk enable bit to change frequency */ ++ esdhc_base_pointer->system_control &= ESDHC_FREQ_MASK; ++ ++ /* Disable SD clock */ ++ esdhc_base_pointer->system_control &= ~ESDHC_ENABLE; ++ ++ if (frequency == IDENTIFICATION_FREQ) { ++ /* Input frequecy to eSDHC is 36 MHZ */ ++ /* PLL3 is the source of input frequency */ ++ /*Set DTOCV and SDCLKFS bit to get SD_CLK of frequency below 400 KHZ (70.31 KHZ) */ ++ esdhc_base_pointer->system_control |= ESDHC_IDENT_FREQ; ++ } else if (frequency == OPERATING_FREQ) { ++ /*Set DTOCV and SDCLKFS bit to get SD_CLK of frequency around 25 MHz.(18 MHz) */ ++ esdhc_base_pointer->system_control |= ESDHC_OPERT_FREQ; ++ } ++ ++ /* Wait for clock to be steady */ ++ while (((esdhc_base_pointer->present_state & 0x8) == 0) && (timeout != 0)) { ++ timeout--; ++ hal_delay_us(10); ++ } ++ ++ /* Enable SD clock */ ++ esdhc_base_pointer->system_control |= ESDHC_ENABLE; ++} ++ ++static void esdhc_set_data_transfer_width(cyg_uint32 data_transfer_width) ++{ ++ ++ /* Set DWT bit of protocol control register according to bus_width */ ++ esdhc_base_pointer->protocol_control &= ~0x6; ++ esdhc_base_pointer->protocol_control |= data_transfer_width; ++ ++} ++ ++static void esdhc_set_endianness(cyg_uint32 endian_mode) ++{ ++ ++ /* Set DWT bit of protocol control register according to bus_width */ ++ esdhc_base_pointer->protocol_control |= endian_mode; ++ ++} ++ ++cyg_uint32 host_send_cmd(command_t * cmd) ++{ ++ ++ /* Clear Interrupt status register */ ++ esdhc_base_pointer->interrupt_status = ESDHC_CLEAR_INTERRUPT; ++ //esdhc_base_pointer->interrupt_status = 0x117f01ff; ++ ++ /* Enable Interrupt */ ++ esdhc_base_pointer->interrupt_status_enable |= ESDHC_INTERRUPT_ENABLE; ++ //esdhc_base_pointer->interrupt_status_enable |= 0x007f0123; ++ ++#if 0 ++ if (esdhc_check_for_send_cmd(cmd->data_present)) { ++ diag_printf("Data/Cmd Line Busy.\n"); ++ return FAIL; ++ } ++#endif ++ ++ /* Configure Command */ ++ esdhc_cmd_config(cmd); ++ ++ /* Wait interrupt (END COMMAND RESPONSE) */ ++ //diag_printf("Wait for CMD Response.\n"); ++ if (esdhc_wait_end_cmd_resp_intr()) { ++ diag_printf("Wait CMD (%d) RESPONSE TIMEOUT.\n", cmd->command); ++ return FAIL; ++ } ++ //Just test for Erase functionality:Lewis-20080505: ++ if (cmd->command == CMD38) { ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:Check DAT0 status:\n", ++ __FUNCTION__); ++ //while(((esdhc_base_pointer->present_state) & 0x01000004)){ ++ // flash_dprintf(FLASH_DEBUG_MAX,"."); ++ // hal_delay_us(1000); ++ //} ++ /* I'm not sure the minimum value of delay */ ++ hal_delay_us(100000); ++ hal_delay_us(100000); ++ hal_delay_us(100000); ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "\nCheck DAT0 status DONE: present_state=%x\n", ++ (cyg_uint32) (esdhc_base_pointer->present_state)); ++ } ++ ++ /* Mask all interrupts */ ++ //esdhc_base_pointer->interrupt_signal_enable =0; ++ ++ /* Check if an error occured */ ++ return esdhc_check_response(); ++} ++ ++static void esdhc_cmd_config(command_t * cmd) ++{ ++ unsigned int transfer_type; ++ ++ /* Write Command Argument in Command Argument Register */ ++ esdhc_base_pointer->command_argument = cmd->arg; ++ ++ /* *Configure e-SDHC Register value according to Command */ ++ transfer_type = (((cmd->data_transfer) << DATA_TRANSFER_SHIFT) | ++ ((cmd->response_format) << RESPONSE_FORMAT_SHIFT) | ++ ((cmd->data_present) << DATA_PRESENT_SHIFT) | ++ ((cmd->crc_check) << CRC_CHECK_SHIFT) | ++ ((cmd->cmdindex_check) << CMD_INDEX_CHECK_SHIFT) | ++ ((cmd->command) << CMD_INDEX_SHIFT) | ++ ((cmd-> ++ block_count_enable_check) << ++ BLOCK_COUNT_ENABLE_SHIFT) | ((cmd-> ++ multi_single_block) << ++ MULTI_SINGLE_BLOCK_SELECT_SHIFT)); ++ ++ esdhc_base_pointer->command_transfer_type = transfer_type; ++ ++ //diag_printf("arg: 0x%x | tp: 0x%x\n", esdhc_base_pointer->command_argument, esdhc_base_pointer->command_transfer_type); ++ ++} ++ ++static int esdhc_wait_end_cmd_resp_intr(void) ++{ ++ /* Wait interrupt (END COMMAND RESPONSE) */ ++ cyg_uint32 i = 50000; ++ while (! ++ ((esdhc_base_pointer-> ++ interrupt_status) & ESDHC_STATUS_END_CMD_RESP_TIME_MSK) && i) { ++ i--; ++ hal_delay_us(10); ++ //diag_printf("0x%x\n", esdhc_base_pointer->interrupt_status); ++ } ++ ++ if (! ++ ((esdhc_base_pointer-> ++ interrupt_status) & ESDHC_STATUS_END_CMD_RESP_TIME_MSK)) { ++ //diag_printf("%s: can't get END COMMAND RESPONSE! Tried %d times\n", __FUNCTION__, (5000000-i)); ++ return FAIL; ++ } ++ ++ return SUCCESS; ++} ++ ++static cyg_uint32 esdhc_check_response(void) ++{ ++ cyg_uint32 status = FAIL; ++ ++ /* Check whether the interrupt is an END_CMD_RESP ++ * or a response time out or a CRC error ++ */ ++ if ((esdhc_base_pointer-> ++ interrupt_status & ESDHC_STATUS_END_CMD_RESP_MSK) ++ && !(esdhc_base_pointer-> ++ interrupt_status & ESDHC_STATUS_TIME_OUT_RESP_MSK) ++ && !(esdhc_base_pointer-> ++ interrupt_status & ESDHC_STATUS_RESP_CRC_ERR_MSK) ++ && !(esdhc_base_pointer-> ++ interrupt_status & ESDHC_STATUS_RESP_INDEX_ERR_MSK)) { ++ ++ status = SUCCESS; ++ } else { ++ //diag_printf("Warning: Check CMD response, Intr Status: 0x%x\n", esdhc_base_pointer->interrupt_status); ++ status = FAIL; ++ } ++ ++ return status; ++ ++} ++ ++void host_read_response(command_response_t * cmd_resp) ++{ ++ /* get response values from e-SDHC CMDRSP registers. */ ++ cmd_resp->cmd_rsp0 = (cyg_uint32) esdhc_base_pointer->command_response0; ++ cmd_resp->cmd_rsp1 = (cyg_uint32) esdhc_base_pointer->command_response1; ++ cmd_resp->cmd_rsp2 = (cyg_uint32) esdhc_base_pointer->command_response2; ++ cmd_resp->cmd_rsp3 = (cyg_uint32) esdhc_base_pointer->command_response3; ++} ++ ++static void esdhc_wait_buf_rdy_intr(cyg_uint32 mask, ++ multi_single_block_select ++ multi_single_block) ++{ ++ ++ /* Wait interrupt (BUF_READ_RDY) */ ++ ++ cyg_uint32 i; ++ for (i = 3000; i > 0; i--) { ++ if (esdhc_base_pointer->interrupt_status & mask) { ++ break; ++ } ++ hal_delay_us(100); ++ } ++ ++ if (multi_single_block == MULTIPLE ++ && esdhc_base_pointer->interrupt_status & mask) ++ esdhc_base_pointer->interrupt_status |= mask; ++ if (i == 0) ++ flash_dprintf(FLASH_DEBUG_MAX, "%s:Debug: tried %d times\n", ++ __FUNCTION__, (3000 - i)); ++ ++} ++ ++static void esdhc_wait_op_done_intr(cyg_uint32 transfer_mask) ++{ ++ /* Wait interrupt (Transfer Complete) */ ++ ++ cyg_uint32 i; ++ while (!(esdhc_base_pointer->interrupt_status & transfer_mask)) ; ++ ++ //diag_printf("Wait OP Done Failed.\n"); ++ //flash_dprintf(FLASH_DEBUG_MAX,"%s:Debug: tried %d times\n", __FUNCTION__, (3001-i)); ++ ++} ++ ++static cyg_uint32 esdhc_check_data(cyg_uint32 op_done_mask, ++ cyg_uint32 read_time_out_mask, ++ cyg_uint32 read_crc_err_mask) ++{ ++ ++ cyg_uint32 status = FAIL; ++ ++ /* Check whether the interrupt is an OP_DONE ++ * or a data time out or a CRC error */ ++ if ((esdhc_base_pointer->interrupt_status & op_done_mask) && ++ !(esdhc_base_pointer->interrupt_status & read_time_out_mask) && ++ !(esdhc_base_pointer->interrupt_status & read_crc_err_mask)) { ++ status = SUCCESS; ++ } else { ++ status = FAIL; ++ //diag_printf("Warning: Check data, interrupt_status=%X\n", (esdhc_base_pointer->interrupt_status)); ++ } ++ ++ return status; ++} ++ ++void host_cfg_block(cyg_uint32 blk_len, cyg_uint32 nob) ++{ ++ /* Configre block Attributes register */ ++ esdhc_base_pointer->block_attributes = ++ ((nob << 16) | (blk_len & 0xffff)); ++ ++ //diag_printf("nob: 0x%x, block_attributes: 0x%x\n", nob, esdhc_base_pointer->block_attributes); ++ ++ /* Set Read Water Mark Level register */ ++ esdhc_base_pointer->watermark_level = WRITE_READ_WATER_MARK_LEVEL; ++} ++ ++cyg_uint32 host_data_read(cyg_uint32 * dest_ptr, cyg_uint32 read_len) ++{ ++ cyg_uint32 j, k; ++ cyg_uint32 status = FAIL; ++ unsigned int len = WRITE_READ_WATER_MARK_LEVEL & 0xff; ++ //int counter = 0; ++ ++ /* Enable Interrupt */ ++ esdhc_base_pointer->interrupt_status_enable |= ESDHC_INTERRUPT_ENABLE; ++ ++ for (j = 0; j < read_len / (len * 4); j++) { ++ //StartCounter(); ++ /* wait for read fifo full (equal or beyond the watermark) */ ++ while (!(esdhc_base_pointer->present_state & (1 << 11))) ; ++ ++ //counter = StopCounter(); ++ //diag_printf("counter: 0x%x\n", counter); ++ ++ for (k = 0; k < len; k++) { ++ *dest_ptr++ = esdhc_base_pointer->data_buffer_access; ++ } ++ } ++ ++ /* Wait for transfer complete operation interrupt */ ++ esdhc_wait_op_done_intr(ESDHC_STATUS_TRANSFER_COMPLETE_MSK); ++ ++ /* Check for status errors */ ++ status = ++ esdhc_check_data(ESDHC_STATUS_TRANSFER_COMPLETE_MSK, ++ ESDHC_STATUS_TIME_OUT_READ, ESDHC_STATUS_READ_CRC_ERR_MSK); ++ ++ return status; ++ ++} ++ ++cyg_uint32 host_data_write(cyg_uint32 * src_ptr, cyg_uint32 write_len) ++{ ++ cyg_uint32 i = 0, k; ++ cyg_uint32 status = FAIL; ++ unsigned int len = (WRITE_READ_WATER_MARK_LEVEL >> 16) & 0xff; ++ //cyg_uint32 counter = 0; ++ ++ /* Enable Interrupt */ ++ esdhc_base_pointer->interrupt_status_enable |= ESDHC_INTERRUPT_ENABLE; ++ ++ //StartCounter(); ++ for (i = 0; i < (write_len) / (len * 4); i++) { ++ /* wait for write fifo empty (equal or less than the watermark), BWEN */ ++ while (!(esdhc_base_pointer->present_state & (1 << 10))) ; ++ ++ for (k = 0; k < len; k++) { ++ esdhc_base_pointer->data_buffer_access = *src_ptr++; ++ } ++ ++ } ++ ++ /* Wait for transfer complete operation interrupt */ ++ esdhc_wait_op_done_intr(ESDHC_STATUS_TRANSFER_COMPLETE_MSK); ++ ++ //counter = StopCounter(); ++ //diag_printf("0x%x\n", counter); ++ ++ /* Check for status errors */ ++ status = ++ esdhc_check_data(ESDHC_STATUS_TRANSFER_COMPLETE_MSK, ++ ESDHC_STATUS_TIME_OUT_READ, ESDHC_STATUS_READ_CRC_ERR_MSK); ++ ++ return status; ++ ++} ++ ++static int esdhc_check_for_send_cmd(int data_present) ++{ ++ ++ int status = SUCCESS; ++ int counter; ++ ++ /* Wait for the command line to be free (poll the CIHB bit of ++ * the present state register. ++ */ ++ counter = 1000; ++ while (((esdhc_base_pointer->present_state & 0x1) == 0x1) && counter--) { ++ hal_delay_us(10); ++ } ++ ++ if (!counter) ++ return FAIL; ++ ++ /* Wait for the data line to be free (poll the CDIHB bit of ++ * the present state register. ++ */ ++ counter = 1000; ++ if (data_present == DATA_PRESENT) { ++ while (((esdhc_base_pointer->present_state & 0x2) == 0x2) && counter--) { ++ hal_delay_us(10); ++ } ++ ++ } ++ ++ if (!counter) ++ return FAIL; ++ ++ return status; ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_mmc.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_mmc.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_mmc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_mmc.c 2010-01-26 17:33:13.032961509 +0000 +@@ -0,0 +1,698 @@ ++// ========================================================================== ++// ++// mxcmci_mmc.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++ ++extern int HighCapacityCard; ++ ++static cyg_uint32 mmc_set_rca(void); ++static cyg_uint32 mmc_set_bus_width_sector_sz(cyg_uint32 bus_width); ++static cyg_uint32 mmc_set_high_speed_mode(void); ++ ++cyg_uint32 address_mode; /* Global variable for addressing mode */ ++ ++cyg_uint32 mmc_init(cyg_uint32 bus_width) ++{ ++ cyg_uint32 status = FAIL; ++ cyg_uint32 spec_version; ++ /* Get CID number of MMC Card */ ++ if (!mxcmci_get_cid()) { ++ /* Set RCA of the MMC Card */ ++ if (!mmc_set_rca()) { ++ flash_dprintf(FLASH_DEBUG_MAX, "%s: mmc_set_rca OK!", ++ __FUNCTION__); ++ /* Get Spec version supported by the card */ ++ spec_version = mmc_get_spec_ver(); ++ //diag_printf("SPEC Version: %d\n", spec_version); ++ ++ /*Enable operating frequency */ ++ host_cfg_clock(OPERATING_FREQ); ++ ++ /*Put MMC in Transfer State */ ++ if (!mxcmci_trans_prepare()) { ++#if 0 ++ if (mmc_set_high_speed_mode()) { ++ return FAIL; ++ } ++#endif ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s: mxcmci_trans_prepare OK!", ++ __FUNCTION__); ++ ++ if (!mmc_set_bus_width_sector_sz(bus_width)) { ++ esdhc_base_pointer->protocol_control &= ~(0x3 << 1); ++ esdhc_base_pointer->protocol_control |= (bus_width >> 2) << 1; ++ status = SUCCESS; ++ diag_printf("Bus Width: %d\n", ++ bus_width); ++ } ++ ++ } ++ } ++ } ++ ++ return status; ++ ++} ++ ++cyg_uint32 mmc_data_read(cyg_uint32 * dest_ptr, cyg_uint32 length, ++ cyg_uint32 offset) ++{ ++ command_t cmd; ++ int len; ++ cyg_uint32 read_block_status = 0; ++ cyg_uint32 blk_len = BLK_LEN; ++ unsigned int SectorNum = 0; ++ ++ /* Assing length of data to be read */ ++ SectorNum = length / blk_len; ++ if ((length % blk_len) != 0) ++ SectorNum++; ++ /* hight capacity card uses sector mode */ ++ if(HighCapacityCard) ++ offset = offset/512; ++ ++ /* wait until in transfer mode */ ++ while (mxcmci_trans_status()) { ++ hal_delay_us(5); ++ } ++ ++ reread: ++ /* Configure interface block and number of blocks */ ++ host_cfg_block(BLK_LEN, SectorNum); ++ ++ if (SectorNum == 1) { ++ //diag_printf("Send CMD17...\n"); ++ /* Comfigure command CMD17 for single block read */ ++ mxcmci_cmd_config(&cmd, CMD17, offset, READ, RESPONSE_48, ++ DATA_PRESENT, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Can't send CMD17!\n", __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ++ ESDHC_RESET_DAT_MSK); ++ read_block_status = FAIL; ++ ++ } else { ++ //diag_printf("host_data_read! dest_ptr: 0%x \n", dest_ptr); ++ /* Call interface Data read function */ ++ read_block_status = host_data_read(dest_ptr, BLK_LEN); ++ ++ if (read_block_status) { /* fail */ ++ //diag_printf("%s: Failed, read_block_status =%d\n", __FUNCTION__, read_block_status); ++ /* re-transfer if data transfer error occurs */ ++ goto reread; ++ } ++ } ++ } else { /* read multi-blocks */ ++ ++ /* Comfigure command CMD18 for multiple block read */ ++ mxcmci_cmd_config(&cmd, CMD18, offset, READ, RESPONSE_48, ++ DATA_PRESENT, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Can't send CMD18!\n", __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ read_block_status = FAIL; ++ } else { ++ /* Call interface Data read function */ ++ read_block_status = ++ host_data_read(dest_ptr, BLK_LEN * SectorNum); ++ ++ /* Comfigure command CMD12 for multi-block read stop */ ++ mxcmci_cmd_config(&cmd, CMD12, 0, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Can't send CMD12!\n", ++ __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ //read_block_status = FAIL; ++ } ++ ++ if (read_block_status) { /* fail */ ++ //diag_printf("%s: Failed, read_block_status =%d\n", __FUNCTION__, read_block_status); ++ /* re-transfer if data transfer error occurs */ ++ goto reread; ++ } ++ ++ } ++ ++ } ++ return read_block_status; ++} ++ ++cyg_uint32 mmc_data_write(cyg_uint32 * src_ptr, cyg_uint32 length, ++ cyg_uint32 offset) ++{ ++ ++ command_t cmd; ++ cyg_int32 len; ++ cyg_uint32 blk_len = BLK_LEN; ++ cyg_uint32 write_block_status = SUCCESS; ++ unsigned int SectorNum; ++ //int counter; ++ //diag_printf("%s: src: 0x%x, offset: 0x%x, length: 0x%x\n", __FUNCTION__, (unsigned int)src_ptr, offset, length); ++ /* Write data size aligned with block size */ ++ SectorNum = length / blk_len; ++ if ((length % blk_len) != 0) ++ SectorNum++; ++ ++ /* hight capacity card uses sector mode */ ++ if(HighCapacityCard) ++ offset = offset/512; ++ ++ //need waiting until CARD out of Prg status, or will cause CMD25 timeout ++ //hal_delay_us(100); ++ ++ //StartCounter(); ++ ++ while (mxcmci_trans_status()) { ++ hal_delay_us(2); ++ } ++ ++ //counter = StopCounter(); ++ //diag_printf("counter: 0x%x\n",counter); ++ ++ rewrite: ++ /* Configure interface block and number of blocks , SctorNum will decrease to zero after transfer */ ++ host_cfg_block(BLK_LEN, SectorNum); ++ ++ if (SectorNum == 1) { ++ //diag_printf("Send CMD24...\n"); ++ /* Comfigure command CMD24 for single block write */ ++ mxcmci_cmd_config(&cmd, CMD24, offset, WRITE, RESPONSE_48, ++ DATA_PRESENT, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Failed in configuring CMD24\n", ++ __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ write_block_status = FAIL; ++ ++ //hal_delay_us(1000); ++ goto rewrite; ++ ++ } else { ++ //diag_printf("Start host_data_write:\n"); ++ /* Call interface write read function */ ++ write_block_status = host_data_write(src_ptr, BLK_LEN); ++ //diag_printf("0x%x\n", esdhc_base_pointer->present_state); ++ ++ if (write_block_status) { /* fail */ ++ //diag_printf("transfer failed.(0x%x)\n", esdhc_base_pointer->block_attributes); ++ while (mxcmci_trans_status()) ; ++ //diag_printf("%s: Failed, write_block_status=%d\n", __FUNCTION__, write_block_status); ++ /* re-transfer */ ++ goto rewrite; ++ } ++ ++ } ++ } else { /* multi-block write */ ++ ++ //diag_printf("Send CMD25...\n"); ++ /* Comfigure command CMD25 for single block write */ ++ mxcmci_cmd_config(&cmd, CMD25, offset, WRITE, RESPONSE_48, ++ DATA_PRESENT, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ //diag_printf("%s: Failed in configuring CMD25\n", ++ // __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ write_block_status = FAIL; ++ goto rewrite; ++ } else { ++ /* Call interface write read function */ ++ write_block_status = ++ host_data_write(src_ptr, SectorNum * BLK_LEN); ++ ++ /* Comfigure command CMD12 for multi-block read stop */ ++ mxcmci_cmd_config(&cmd, CMD12, 0, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Can't send CMD12!\n", ++ __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ //write_block_status = FAIL; ++ } ++ ++ if (write_block_status) { /* fail */ ++ //diag_printf("%s: Failed, write_block_status=%d\n", __FUNCTION__, write_block_status); ++ while (mxcmci_trans_status()); ++ /* re-transfer */ ++ goto rewrite; ++ } ++ } ++ } ++ ++ return write_block_status; ++ ++} ++ ++cyg_uint32 mmc_data_erase(cyg_uint32 offset, cyg_uint32 size) ++{ ++ command_t cmd; ++ extern int Card_Mode; ++ cyg_uint8 startEraseBlockCmd = CMD35; ++ cyg_uint8 endEraseBlockCmd = CMD36; ++ ++ cyg_uint32 startBlock = offset / BLK_LEN; ++ cyg_uint32 endBlock = (offset + size - 1) / BLK_LEN; ++ cyg_uint32 ret; ++// diag_printf("card_data_erase\n"); ++ if (Card_Mode == 0) { ++ startBlock *= BLK_LEN; ++ endBlock *= BLK_LEN; ++ startEraseBlockCmd = CMD35; ++ endEraseBlockCmd = CMD36; ++ } ++ ++ else if (Card_Mode == 1) { ++ startBlock *= BLK_LEN; ++ endBlock *= BLK_LEN; ++ startEraseBlockCmd = CMD32; ++ endEraseBlockCmd = CMD33; ++ } ++#if 1 ++ /* hight capacity card uses sector mode */ ++ if(HighCapacityCard) ++ startBlock /= BLK_LEN; ++ endBlock /= BLK_LEN; ++#endif ++// diag_printf("0x%x - 0x%x, size: 0x%x\n", startBlock, endBlock, size); ++ /* Configure start erase command to set first block */ ++ mxcmci_cmd_config(&cmd, startEraseBlockCmd, startBlock, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ENABLE, ENABLE); ++ /* wait response */ ++ if ((ret = host_send_cmd(&cmd)) == SUCCESS) { ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "%s: successful for host_send_cmd\n", ++ __FUNCTION__); ++ /* Configure end erase command to set end block */ ++ mxcmci_cmd_config(&cmd, endEraseBlockCmd, endBlock, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ENABLE, ENABLE); ++ if ((ret = host_send_cmd(&cmd)) == SUCCESS) { ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "%s: successful for host_send_cmd:2\n", ++ __FUNCTION__); ++ /* Comfigure command to start erase */ ++ mxcmci_cmd_config(&cmd, CMD38, 0, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ if ((ret = host_send_cmd(&cmd)) == SUCCESS) { ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "%s: successful for host_send_cmd:3\n", ++ __FUNCTION__); ++ //wait for completion ++ return ret; ++ } ++ } ++ } ++ ++ flash_dprintf(FLASH_DEBUG_MAX, "%s: Error return (%d)\n", __FUNCTION__, ++ ret); ++ return ret; ++} ++ ++cyg_uint32 mmc_voltage_validation(void) ++{ ++ command_t cmd; ++ command_response_t response; ++ cyg_uint32 voltage_validation_command = 0; ++ cyg_uint32 ocr_val = 0; ++ cyg_uint32 voltage_validation = FAIL; ++ ++ ocr_val = (cyg_uint32) ((MMC_OCR_VALUE) & 0xFFFFFFFF); ++ ++ while ((voltage_validation_command < MMCSD_READY_TIMEOUT) ++ && (voltage_validation != SUCCESS)) { ++ /* Configure CMD1 for MMC card */ ++ mxcmci_cmd_config(&cmd, CMD1, ocr_val, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, DISABLE, DISABLE); ++ ++ /* Issue CMD1 to MMC card to determine OCR value */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ voltage_validation = FAIL; ++ break; ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Check if card busy bit is cleared or not */ ++ if (!(response.cmd_rsp0 & CARD_BUSY_BIT)) { ++ /* Iterate One more time */ ++ voltage_validation_command++; ++ } else { ++ if ((response.cmd_rsp0 & MMC_OCR_HC_RES) == ++ MMC_OCR_HC_RES) { ++ address_mode = SECT_MODE; ++ voltage_validation = SUCCESS; ++ } else if ((response.cmd_rsp0 & MMC_OCR_LC_RES) ++ == MMC_OCR_LC_RES) { ++ address_mode = BYTE_MODE; ++ voltage_validation = SUCCESS; ++ } ++ } ++ ++ } ++ } ++ ++ return voltage_validation; ++} ++ ++static cyg_uint32 mmc_set_rca(void) ++{ ++ command_t cmd; ++ cyg_uint32 card_state = 0; ++ cyg_uint32 rca_request = 0; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD3 for MMC card */ ++ /* 32bit card address is expected as Argument */ ++ mxcmci_cmd_config(&cmd, CMD3, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Assigns relative address to the card ++ */ ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ rca_request = FAIL; ++ } ++ ++ else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ card_state = CURR_CARD_STATE(response.cmd_rsp0); ++ if (card_state == IDENT) { ++ rca_request = SUCCESS; ++ ++ } else { ++ rca_request = FAIL; ++ } ++ } ++ ++ return rca_request; ++} ++ ++cyg_uint32 mmc_get_spec_ver(void) ++{ ++ ++ cyg_uint32 mmc_spec_version; ++ ++ if (card_get_csd() == FAIL) { ++ mmc_spec_version = 0; ++ } else { ++ mmc_spec_version = ((csd.csd3 && MMC_SPEC_VER) >> MMC_SPEC_VER_SHIFT); ++ } ++ ++ return mmc_spec_version; ++ ++} ++ ++cyg_uint32 card_flash_query(void *data) ++{ ++ command_t cmd; ++ cyg_uint32 cid_request = FAIL; ++ command_response_t response; ++ ++ /* Configure CMD2 for card */ ++ mxcmci_cmd_config(&cmd, CMD2, NO_ARG, READ, RESPONSE_136, ++ DATA_PRESENT_NONE, ENABLE, DISABLE); ++ /* Issue CMD2 to card to determine CID contents */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ cid_request = FAIL; ++ flash_dprintf(FLASH_DEBUG_MAX, "%s: can't send query command\n", ++ __FUNCTION__); ++ } else { ++ cyg_uint32 *d = (cyg_uint32 *) data; ++ /* Read Command response */ ++ response.format = RESPONSE_136; ++ host_read_response(&response); ++ /* Assign CID values to mmc_cid structures */ ++ *d++ = response.cmd_rsp0; ++ *d++ = response.cmd_rsp1; ++ *d++ = response.cmd_rsp2; ++ *d = response.cmd_rsp3; ++ ++ /* Assign cid_request as SUCCESS */ ++ cid_request = SUCCESS; ++ } ++ flash_dprintf(FLASH_DEBUG_MAX, ++ "%s(Success?=%d):(ID=0x%x: 0x%x, 0x%x, 0x%x)\n", ++ __FUNCTION__, cid_request, *(cyg_uint32 *) (data), ++ *(cyg_uint32 *) ((cyg_uint32) data + 4), ++ *(cyg_uint8 *) ((cyg_uint32) data + 8), ++ *(cyg_uint8 *) ((cyg_uint32) data + 12)); ++ return; ++} ++ ++static cyg_uint32 mmc_set_bus_width_sector_sz(cyg_uint32 bus_width) ++{ ++ command_t cmd; ++ cyg_uint32 set_bus_width_status = FAIL; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ if ((bus_width == FOUR) || (bus_width == EIGHT) || (bus_width == ONE)) { ++ ++ /* Configure CMD6 to write to EXT_CSD register for BUS_WIDTH */ ++ mxcmci_cmd_config(&cmd, CMD6, 0x03b70001 | ((bus_width >> 2) << 8), READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == SUCCESS) { ++ /* wait until in transfer mode */ ++ while (mxcmci_trans_status()) { ++ hal_delay_us(5); ++ } ++ mxcmci_cmd_config(&cmd, CMD16, 512, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ENABLE, ENABLE); ++ if (host_send_cmd(&cmd) == SUCCESS) { ++ set_bus_width_status = SUCCESS; ++ } else ++ diag_printf("Setting MMC sector size failed.\n"); ++ } else { ++ diag_printf("Setting MMC bus width failed.\n"); ++ } ++ } ++ ++ return set_bus_width_status; ++} ++ ++static cyg_uint32 mmc_set_high_speed_mode(void) ++{ ++ command_t cmd; ++ command_response_t response; ++ cyg_uint32 status = FAIL; ++ ++ //diag_printf("Send CMD6 to Set High Speed Mode.\n"); ++ /* Configure CMD6 to write to EXT_CSD register for BUS_WIDTH */ ++ mxcmci_cmd_config(&cmd, CMD6, 0x03b90100, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == SUCCESS) { ++ /* wait until in transfer mode */ ++ while (mxcmci_trans_status()) { ++ hal_delay_us(5); ++ } ++ ++ status = SUCCESS; ++ } else { ++ diag_printf("Setting MMC High Speed Mode FAILED.\n"); ++ } ++ ++ return status; ++} ++ ++int sdmmc_set_blklen(int len) ++{ ++ int status = FAIL; ++ command_t cmd; ++ command_response_t response; ++ ++ /* Configure CMD16 to set block length as 512 bytes. */ ++ mxcmci_cmd_config(&cmd, CMD16, len, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue command CMD16 to set block length as 512 bytes */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ diag_printf("%s: Can't set block length!(CMD16)\n", ++ __FUNCTION__); ++ esdhc_softreset(ESDHC_RESET_CMD_MSK); ++ status = FAIL; ++ } else { ++ status = SUCCESS; ++ } ++ ++ return status; ++} ++ ++int sdmmc_stop_transmission(void) ++{ ++ int status = FAIL; ++ command_t cmd; ++ command_response_t response; ++ ++ /* Comfigure command CMD12 for read stop */ ++ mxcmci_cmd_config(&cmd, CMD12, 0, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ //diag_printf("%s: Can't send CMD12!\n", __FUNCTION__); ++ //esdhc_softreset(ESDHC_RESET_CMD_MSK | ESDHC_RESET_DAT_MSK); ++ //read_block_status = FAIL; ++ } ++ ++ return 0; ++} ++ ++static unsigned int mmc_set_extendCSD(unsigned int ECSD_index, unsigned int value, unsigned int access_mode) ++{ ++ unsigned int argument = 0; ++ command_t cmd; ++ ++ /* access mode: 0b01 set bits/ 0b10 clear bits/ 0b11 write bytes */ ++ argument = (access_mode << 24) | (ECSD_index << 16) | (value << 8); ++ //argument = 0x1b30000; ++ ++ mxcmci_cmd_config(&cmd, CMD6, argument, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ if(host_send_cmd(&cmd) == SUCCESS) { ++ return 0; ++ } else { ++ //diag_printf("%s: Setting MMC boot Failed.\n", __FUNCTION__); ++ return 1; ++ } ++} ++ ++static void mmc_set_boot_partition_size(unsigned int value) ++{ ++ command_t cmd; ++ command_response_t response; ++ cyg_uint32 card_state = 0; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ mxcmci_cmd_config(&cmd, CMD62, 0XEFAC62EC, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ host_send_cmd(&cmd); ++ ++ mxcmci_cmd_config(&cmd, CMD62, 0X00CBAEA7, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ host_send_cmd(&cmd); ++ ++ mxcmci_cmd_config(&cmd, CMD62, value, READ, RESPONSE_48, ++ DATA_PRESENT, ENABLE, ENABLE); ++ host_send_cmd(&cmd); ++} ++ ++cyg_uint32 emmc_set_boot_partition (cyg_uint32 *src_ptr, cyg_uint32 length) ++{ ++ cyg_uint32 status=FAIL; ++ unsigned int value; ++ unsigned int eMMCBootDataSize = (length / (128 * 1024)) + 1; ++ ++ if (MMC_Spec_vers < 4) ++ return 1; ++ ++ /* read back 1KB data as we are programming to user are and want to aviod erasing MBR ++ * will be removed once we program Redboot to boot partition of the card ++ */ ++ mmc_data_read(src_ptr, 0x400, 0); ++ ++ /* Set boot partition */ ++ /* 1. Configure CMD6 to write to EXT_CSD register for eMMC boot partition, Byte 179*/ ++ /* boot partition: user area enable and r/w enable */ ++ value = (0x7 << 3) | (0x7); ++ //value = (0x1 << 3) | (0x1); ++ status = mmc_set_extendCSD(179, value, 0x3); ++ if(status) { ++ return 1; /* failed */ ++ } ++ ++ /* 2. Set boot partition size: n*128KB */ ++ value = eMMCBootDataSize; ++ //status = mmc_set_extendCSD(226, value, 0x3); ++ //if(status) { ++ // return 1; /* failed */ ++ //} ++ //mmc_set_boot_partition_size(value); ++ ++ //diag_printf("Boot partition size: 0x%xKB\n", eMMCBootDataSize * 128); ++ ++ /* 3. Program to boot partition, default address is alway 0x0 */ ++ status = mmc_data_write (src_ptr, eMMCBootDataSize*128*1024, 0); ++ if(status) { ++ return 1; /* failed */ ++ } ++ ++ while (mxcmci_trans_status()); ++ ++ /* 4. Clear boot partition access bits, to protect w/r of boot partition */ ++ /* bit 6: send boot ack signal, boot partition: user area enable and r/w access disable */ ++ //value = (0x1 << 6) | (0x1 << 3) | (0x0); ++ value = (0x1 << 6) | (0x7 << 3) | (0x0); ++ status = mmc_set_extendCSD(179, value, 0x3); ++ if(status) { ++ return 1; /* failed */ ++ } ++ ++ return 0; ++} ++ ++/* end of mxcmci_mmc.c */ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_sd.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_sd.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/mxcmci_sd.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/mxcmci_sd.c 2010-01-26 17:33:13.042961508 +0000 +@@ -0,0 +1,588 @@ ++// ========================================================================== ++// ++// mxcmci_sd.c ++// (c) 2008, Freescale ++// ++// MMC card driver for MXC platform ++// ++// ========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Lewis Liu ++// Contributors: Lewis Liu ++// Date: 2008-05-13 Initial version ++// Purpose: ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++ ++static cyg_uint32 sd_get_rca(void); ++static cyg_uint32 sd_get_bit_mode_support(void); ++static cyg_uint32 sd_set_bus_width(cyg_uint32); ++static cyg_uint32 sd_set_high_speed_mode(void); ++ ++#define SD_OCR_VALUE_HV_LC 0x00ff8000 /* 3.3v, LC */ ++#define SD_OCR_VALUE_HV_HC 0x40ff8000 /* 3.3v, HC */ ++/* LV_LC not needed - 1.8v is only supported under eSD which supports HC by default (SD>2.00) */ ++#define SD_OCR_VALUE_LV_HC 0x40000080 /* 1.8v, HC */ ++ ++#define SD_OCR_HC_RES 0x40000000 ++#define SD_OCR_LC_RES 0x00000000 ++ ++#define SD_IF_HV_COND_ARG 0x000001AA ++#define SD_IF_LV_COND_ARG 0x000002AA ++ ++#define RCA_SHIFT 16 ++#define SD_R1_STATUS_APP_CMD_MSK 0x20 ++#define BIT_MODE_4_SUPPORT 5 ++#define SD_BUS_WIDTH_OFFSET 6 ++#define BIT_4_MODE 4 ++#define SD_STATUS_LEN 64 ++ ++#define SD_BOOT_SWITCH_ARG 0x80FFFF2F ++#define SD_PARTITION1 0x01000000 ++ ++cyg_uint32 sd_init(cyg_uint32 bus_width) ++{ ++ cyg_uint32 status = FAIL; ++ cyg_uint32 bus_size = bus_width; ++ ++ /* Get CID number of SD Memory Card */ ++ if (!mxcmci_get_cid()) { ++ //diag_printf("%s:mxcmci_get_cid OK!\n", __FUNCTION__); ++ /* Set RCA of the SD Card */ ++ if (!sd_get_rca()) { ++ //diag_printf("%s:sd_get_rca OK!\n", __FUNCTION__); ++ /*Get CSD from Card */ ++ if (card_get_csd()) ++ return FAIL; ++ ++ /*Enable operating frequency */ ++ host_cfg_clock(OPERATING_FREQ); ++ ++ //diag_printf("Set SD Card in Transfer State.\n"); ++ ++ /*Put SD Card in Transfer State */ ++ if (!mxcmci_trans_prepare()) { ++#if 0 ++ if (sd_set_high_speed_mode()) { ++ return FAIL; ++ } ++#endif ++ ++ if (sdmmc_set_blklen(BLK_LEN)) ++ return FAIL; ++ ++ /* SD can only support 1/4 bit bitwidth, 8 bit is not supported */ ++ if (EIGHT == bus_width) { ++ bus_width = FOUR; ++ } ++ if (!sd_set_bus_width(bus_width)) { ++ esdhc_base_pointer->protocol_control &= ++ ~(0x3 << 1); ++ esdhc_base_pointer->protocol_control |= ++ (bus_width / 4) << 1; ++ diag_printf("Bus Width: %d\n", ++ bus_width); ++ status = SUCCESS; ++ } ++ } ++ } ++ ++ } else { ++ diag_printf("Get CID Failed.\n"); ++ ++ } ++ ++ //diag_printf("%s:failed to Init SD card!\n", __FUNCTION__); ++ return status; ++ ++} ++ ++cyg_uint32 sd_voltage_validation(void) ++{ ++ //wait max timeout (unit: ms) ++ cyg_uint32 timeout = 15000; ++ ++ command_t cmd; ++ command_response_t response; ++ cyg_uint32 voltage_validation_command = 0; ++ cyg_uint32 default_rca = 0; ++ ++ cyg_uint32 ocr_value = SD_OCR_VALUE_HV_LC; /* nirp_oct07: <- split OCR to 3.3v and 1.8v cases */ ++ cyg_uint32 voltage_validation = FAIL; ++ cyg_uint32 interface_value = 0; ++ cyg_uint32 card_usable = SUCCESS; ++ ++ /* Configure Command CMD8 to check for High capacity support */ ++ /* try 3.3V first */ ++ mxcmci_cmd_config(&cmd, CMD8, SD_IF_HV_COND_ARG, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue Command CMD8 to SD Memory card */ ++ if (host_send_cmd(&cmd) == SUCCESS) { /* nirp_oct07: <- changed order of detection */ ++ //diag_printf("%s:CMD8 OK!\n", __FUNCTION__); ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Obtain Interface value from the response buffer */ ++ interface_value = response.cmd_rsp0; ++ ++ /* Check if volatge lies in range or not */ ++ if ((interface_value & SD_IF_HV_COND_ARG) == SD_IF_HV_COND_ARG) { ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_HV_HC) & 0xFFFFFFFF); /* nirp_oct07: <- split OCR to 3.3v and 1.8v cases */ ++ } ++ ++ /* start timer for a delay of 1.5sec, for ACMD41 */ ++ hal_delay_us(1500); ++ ++ while ((voltage_validation_command < 200) ++ && (voltage_validation != SUCCESS) ++ && (card_usable == SUCCESS)) { ++ /* Configure CMD55 for SD card */ ++ /* This command expects defualt RCA 0x0000 as argument. */ ++ mxcmci_cmd_config(&cmd, CMD55, default_rca, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ++ ENABLE, ENABLE); ++ ++ /* Issue CMD55 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ voltage_validation = FAIL; ++ //diag_printf("Send CMD55 Failed.\n"); ++ break; ++ } else { ++ /* Configure ACMD41 for SD card */ ++ /* This command expects operating voltage range as argument. */ ++ /* CODE REVIEW START: Need to check why BUSY was expected */ ++ /* INTERNAL CODE REVIEW: Accepted - to fix original code if needed */ ++ /* nirp: changed RESPONSE_48_CHECK_BUSY to RESPONSE_48 */ ++ /* nirp_oct03: why with busy again? ACMD41 doesn't hold busy line */ ++ mxcmci_cmd_config(&cmd, ACMD41, ocr_value, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, DISABLE, ++ DISABLE); ++ ++ /* Issue ACMD41 to SD Memory card to determine OCR value */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ voltage_validation = FAIL; ++ diag_printf("Send CMD41 Failed.\n"); ++ break; ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Obtain OCR Values from the response */ ++ /* Obtain OCR value from the response buffer */ ++ ocr_value = response.cmd_rsp0; ++ ++ /* Check if card busy bit is cleared or not */ ++ if (!(response.cmd_rsp0 & CARD_BUSY_BIT)) { ++ /* Iterate One more time */ ++ voltage_validation_command++; ++ } else { ++ ++ /*CODE REVIEW START: Update code and check only bit 30, HC or LC card type. All voltage bits needs to be masked. */ ++ /* INTERNAL CODE REVIEW: Accepted - need fix the code accordingly */ ++ /* nirp: It may be better to check the actual power supply voltage - requiring the entire range (0xff8000) may fail the sequence even if the device can be supported */ ++ /*CODE REVIEW END: */ ++ ++ if ((response.cmd_rsp0 & SD_OCR_HC_RES) == SD_OCR_HC_RES) { ++ address_mode = SECT_MODE; ++ voltage_validation = SUCCESS; ++ } ++ /* CODE REVIEW 3: (same as above) Check is logically correct, but seems redundent. ++ Anything that fails the HC check, is assumed Low Capacity */ ++ /* nirp_oct03: this can be just an "else". the LC macro is 0 anyway, ++ and anything not HC is LC by default */ ++ /* removed else if */ ++ else { ++ address_mode = BYTE_MODE; ++ voltage_validation = SUCCESS; ++ } ++ } ++ } ++ } ++ ++ hal_delay_us(1000); ++ } ++ ++ if (voltage_validation == FAIL) { ++ card_usable = FAIL; ++ } ++ ++ } else { ++ /*3.3v test failed, try to test 1.8v mode! */ ++ mxcmci_cmd_config(&cmd, CMD8, SD_IF_LV_COND_ARG, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ENABLE, ++ ENABLE); ++ ++ /* Issue Command CMD8 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ //diag_printf("%s:CMD8 for 1.8v failed!\n", __FUNCTION__); ++ /* nirp_oct07: CMD8 failed both in 3.3 and in 1.8v, try SD 1.x case - no CMD8, LC, 3.3v only */ ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_HV_LC) & 0xFFFFFFFF); /* nirp_oct07: <- changed order of detection */ ++ } else { ++ //diag_printf("%s:CMD8 for 1.8v OK!\n", __FUNCTION__); ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Obtain Interface value from the response buffer */ ++ interface_value = response.cmd_rsp0; ++ ++ /* Check if volatge lies in range or not */ ++ if ((interface_value & SD_IF_LV_COND_ARG) == SD_IF_LV_COND_ARG) { ++ ocr_value = ((cyg_uint32) (SD_OCR_VALUE_LV_HC) & 0xFFFFFFFF); /* nirp_oct07: <- split OCR to 3.3v and 1.8v cases */ ++ } ++ /* nirp_oct07: otherwise, try with HV_LC settings (set at function start) */ ++ } ++ ++ } ++ ++ /* start timer for a delay of 1.5sec, for ACMD41 */ ++ hal_delay_us(1500); ++ ++ /* nirp_oct03: MMCSD_READY_TIMEOUT too long. ++ ACMD41 also takes longer than CMD1 (twice - ~200 clocks for CMD55+resp+CMD41+resp */ ++ /* In any case ,ACMD 41 will loop not more than 1.5 sec */ ++ while ((voltage_validation_command < 200) ++ && (voltage_validation != SUCCESS) && (card_usable == SUCCESS)) { ++ /* Configure CMD55 for SD card */ ++ /* This command expects defualt RCA 0x0000 as argument. */ ++ mxcmci_cmd_config(&cmd, CMD55, default_rca, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue CMD55 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ voltage_validation = FAIL; ++ //diag_printf("Send CMD55 Failed!\n"); ++ break; ++ } else { ++ /* Configure ACMD41 for SD card */ ++ /* This command expects operating voltage range as argument. */ ++ /* CODE REVIEW START: Need to check why BUSY was expected */ ++ /* INTERNAL CODE REVIEW: Accepted - to fix original code if needed */ ++ /* nirp: changed RESPONSE_48_CHECK_BUSY to RESPONSE_48 */ ++ /* nirp_oct03: why with busy again? ACMD41 doesn't hold busy line */ ++ mxcmci_cmd_config(&cmd, ACMD41, ocr_value, READ, ++ RESPONSE_48, DATA_PRESENT_NONE, ++ DISABLE, DISABLE); ++ ++ /* CODE REVIEW END: */ ++ ++ /* Issue ACMD41 to SD Memory card to determine OCR value */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ voltage_validation = FAIL; ++ diag_printf("Send ACMD41 Failed!\n"); ++ break; ++ } else { ++ /* Read Response from CMDRSP0 Register */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Obtain OCR Values from the response */ ++ /* Obtain OCR value from the response buffer ++ */ ++ ocr_value = response.cmd_rsp0; ++ ++ /* Check if card busy bit is cleared or not */ ++ if (!(response.cmd_rsp0 & CARD_BUSY_BIT)) { ++ /* Iterate One more time */ ++ voltage_validation_command++; ++ } else { ++ /*CODE REVIEW START: Update code and check only bit 30, HC or LC card type. All voltage bits needs to be masked. */ ++ /* INTERNAL CODE REVIEW: Accepted - need fix the code accordingly */ ++ /* nirp: It may be better to check the actual power supply voltage - requiring the entire range (0xff8000) may fail the sequence even if the device can be supported */ ++ /*CODE REVIEW END: */ ++ ++ if ((response.cmd_rsp0 & SD_OCR_HC_RES) == SD_OCR_HC_RES) { ++ address_mode = SECT_MODE; ++ voltage_validation = SUCCESS; ++ } ++ /* CODE REVIEW 3: (same as above) Check is logically correct, but seems redundent. ++ Anything that fails the HC check, is assumed Low Capacity */ ++ /* nirp_oct03: this can be just an "else". the LC macro is 0 anyway, ++ and anything not HC is LC by default */ ++ else { ++ address_mode = BYTE_MODE; ++ voltage_validation = SUCCESS; ++ } ++ } ++ } ++ ++ } ++ ++ hal_delay_us(1000); ++ ++ } ++ ++ return voltage_validation; ++} ++ ++static cyg_uint32 sd_get_rca(void) ++{ ++ command_t cmd; ++ cyg_uint32 card_state = 0; ++ cyg_uint32 rca_request = 0; ++ command_response_t response; ++ ++ /* Configure CMD3 for MMC card */ ++ /* 32bit card address is expected as Argument */ ++ mxcmci_cmd_config(&cmd, CMD3, NO_ARG, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Get relative address of the card */ ++ ++ if (host_send_cmd(&cmd) == FAIL) { ++ rca_request = FAIL; ++ diag_printf("Send CMD3 Failed.\n"); ++ } else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ Card_rca = ((cyg_uint32) (response.cmd_rsp0 >> RCA_SHIFT)); ++ ++ card_state = CURR_CARD_STATE(response.cmd_rsp0); ++ ++ if (card_state == IDENT) { ++ rca_request = SUCCESS; ++ } else { ++ rca_request = FAIL; ++ diag_printf("Get RCA Failed.\n"); ++ } ++ } ++ ++ return rca_request; ++} ++ ++static cyg_uint32 sd_get_bit_mode_support(void) ++{ ++ command_t cmd; ++ cyg_uint32 rd_data_buff[128]; ++ cyg_uint32 bit4_mode_support; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ /* Configure CMD55 for SD card */ ++ /* This command expects RCA as argument. */ ++ mxcmci_cmd_config(&cmd, CMD55, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue CMD55 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ bit4_mode_support = 0; ++ } else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Afetr giving ACMD Command, the R1 response should have ++ * STATUS_APP_CMD set ++ */ ++ if (response.cmd_rsp0 & SD_R1_STATUS_APP_CMD_MSK) { ++ ++ /* Configure ACMD51 for SD card */ ++ /* This command expects No argument. */ ++ ++ mxcmci_cmd_config(&cmd, ACMD51, NO_ARG, READ, ++ RESPONSE_48, DATA_PRESENT, ENABLE, ++ ENABLE); ++ ++ /* Issue ACMD51 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ bit4_mode_support = 0; ++ } else { ++ /* Read Response from e-SDHC buffer */ ++ host_data_read(rd_data_buff, 512); ++ ++ /* Check for bus width supported */ ++ bit4_mode_support = (rd_data_buff[SD_BUS_WIDTH_OFFSET] & BIT_MODE_4_SUPPORT); ++ ++ if (bit4_mode_support) { ++ bit4_mode_support = BIT_4_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ return bit4_mode_support; ++} ++ ++static cyg_uint32 sd_set_bus_width(cyg_uint32 bus_width) ++{ ++ command_t cmd; ++ cyg_uint32 set_bus_width_status = 0; ++ command_response_t response; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ ++ if ((bus_width == FOUR) || (bus_width == ONE)) { ++ /* Configure CMD55 for SD card */ ++ /* This command expects RCA as argument. */ ++ ++ mxcmci_cmd_config(&cmd, CMD55, card_address, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue CMD55 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ set_bus_width_status = FAIL; ++ } else { ++ /* Read Command response */ ++ response.format = RESPONSE_48; ++ host_read_response(&response); ++ ++ /* Afetr giving ACMD Command, the R1 response should have ++ * STATUS_APP_CMD set ++ */ ++ if (response.cmd_rsp0 & SD_R1_STATUS_APP_CMD_MSK) { ++ bus_width = (bus_width >> ONE); ++ ++ /* Configure ACMD6 for SD card */ ++ mxcmci_cmd_config(&cmd, ACMD6, bus_width, READ, ++ RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ++ ENABLE); ++ ++ /* Issue ACMD6 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ set_bus_width_status = FAIL; ++ } else { ++ set_bus_width_status = SUCCESS; ++ } ++ } ++ } ++ } ++ ++ return set_bus_width_status; ++} ++ ++/*========================================================================== ++FUNCTION: cyg_uint32 sd_set_boot_partition (void) ++DESCRIPTION: ++ sd_set_boot_partition() will set set boot partition for Partition1 ++ ++RETURN VALUE: ++ SUCCESS / FAILURE ++ ++PRE-CONDITIONS: ++ None ++ ++POST-CONDITIONS: ++ None ++ ++Detailed Description: ++ ++==============================================================================*/ ++ ++cyg_uint32 esd_set_boot_partition(cyg_uint32 *src_ptr, cyg_uint32 length) ++{ ++ command_t cmd; ++ cyg_uint32 set_partition_status = FAIL; ++ command_response_t response; ++ cyg_uint8 response_data[512]; ++ cyg_uint32 *response_pointer = (cyg_uint32 *) response_data; ++ cyg_uint32 card_address = (Card_rca << RCA_SHIFT); ++ cyg_uint32 card_state; ++ ++ /* Send CMD43 to select partition PARTITION1 active */ ++ mxcmci_cmd_config(&cmd, CMD43, ++ 0x1<<24, ++ READ, ++ RESPONSE_48, ++ DATA_PRESENT_NONE, ++ ENABLE, ++ ENABLE); ++ ++ if(host_send_cmd(&cmd) == FAIL) { ++ //diag_printf("%s: Send CMD43 Failed.\n", __FUNCTION__); ++ return 1; ++ } ++ ++ set_partition_status = mmc_data_write (src_ptr, length, 0); ++ if(set_partition_status) { ++ return 1; /* failed */ ++ } ++ ++ return 0; ++} ++ ++static cyg_uint32 sd_set_high_speed_mode(void) ++{ ++ command_t cmd; ++ cyg_uint32 status = FAIL; ++ command_response_t response; ++ ++ /* Configure CMD6 for SD card */ ++ mxcmci_cmd_config(&cmd, CMD6, 0xfffff1, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue CMD6 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf("Send CMD6 Failed.\n"); ++ return FAIL; ++ } else { ++ hal_delay_us(1000); ++ status = SUCCESS; ++ ++ } ++ ++ mxcmci_cmd_config(&cmd, CMD6, 0x80fffff1, READ, RESPONSE_48, ++ DATA_PRESENT_NONE, ENABLE, ENABLE); ++ ++ /* Issue CMD6 to SD Memory card */ ++ if (host_send_cmd(&cmd) == FAIL) { ++ status = FAIL; ++ diag_printf("Send CMD6 Failed.\n"); ++ } else { ++ /* wait until in transfer mode */ ++ while (mxcmci_trans_status()) { ++ hal_delay_us(5); ++ } ++ ++ status = SUCCESS; ++ } ++ ++ return status; ++} ++ ++/* end of mxcmic_sd.c */ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor.c 2010-01-26 17:33:13.062960756 +0000 +@@ -0,0 +1,446 @@ ++//========================================================================== ++// ++// spi_nor.c ++// ++// SPI NOR flash support ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================*/ ++ ++#include ++#include ++#include ++#include CYGHWR_MEMORY_LAYOUT_H ++#include ++#define _FLASH_PRIVATE_ ++#include ++ ++#include ++#include ++ ++static unsigned char g_tx_buf[256]; ++static unsigned char g_rx_buf[256]; ++static int spi_nor_init_ok; ++ ++imx_spi_write_func_t *spi_write_func; ++imx_spi_erase_func_t *spi_erase_func; ++ ++#ifndef MXCFLASH_SELECT_MULTI ++void flash_query(void* data) ++#else ++void spi_norflash_query(void* data) ++#endif ++{ ++ unsigned char tmp[4]; ++ unsigned char *ptr = (unsigned char *)data; ++ ++ g_tx_buf[3] = JEDEC_ID; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, tmp, (4 * 8)) != 0) { ++ return; ++ } ++ diag_printf("JEDEC ID: 0x%02x:0x%02x:0x%02x\n", tmp[2], tmp[1], tmp[0]); ++ ptr[0] = tmp[2]; ++ ptr[1] = tmp[1]; ++ ptr[2] = tmp[0]; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_program_buf(void* addr, void* data, int len) ++#else ++int spi_norflash_program_buf(void* addr, void* data, int len) ++#endif ++{ ++ return spi_nor_program_buf(addr, data, len); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_erase_block(void* block, unsigned int size) ++#else ++int spi_norflash_erase_block(void* block, unsigned int size) ++#endif ++{ ++ return spi_nor_erase_64k(block, size); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++bool flash_code_overlaps(void *start, void *end) ++#else ++bool spi_norflash_code_overlaps(void *start, void *end) ++#endif ++{ ++ extern unsigned char _stext[], _etext[]; ++ ++ return ((((unsigned long)&_stext >= (unsigned long)start) && ++ ((unsigned long)&_stext < (unsigned long)end)) || ++ (((unsigned long)&_etext >= (unsigned long)start) && ++ ((unsigned long)&_etext < (unsigned long)end))); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_map_error(int e) ++#else ++int spi_norflash_hwr_map_error(int e) ++#endif ++{ ++ return e; ++} ++ ++//---------------------------------------------------------------------------- ++// Now that device properties are defined, include magic for defining ++// accessor type and constants. ++#include ++ ++// Information about supported devices ++typedef struct flash_dev_info { ++ cyg_uint8 device_id; ++ cyg_uint8 device_id2; ++ cyg_uint8 device_id3; ++ cyg_uint8 device_id4; ++ cyg_uint32 block_size; ++ cyg_int32 block_count; ++ cyg_uint32 device_size; ++ cyg_uint32 fis_start_addr; ++ cyg_uint8 vendor_info[96]; ++} __attribute__((aligned(4),packed))flash_dev_info_t; ++ ++static const flash_dev_info_t* flash_dev_info; ++static const flash_dev_info_t supported_devices[] = { ++#include ++}; ++ ++#define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t)) ++ ++#define ASSERT_SPI_NOR_INIT() \ ++ do { \ ++ if (spi_nor_init(&imx_spi_nor) != 0) { \ ++ diag_printf("Error: failed to initialize SPI NOR\n"); \ ++ return -1; \ ++ } \ ++ } while (0); \ ++ ++int ++#ifndef MXCFLASH_SELECT_MULTI ++flash_hwr_init(void) ++#else ++spi_norflash_hwr_init(void) ++#endif ++{ ++ cyg_uint8 id[4]; ++ int i; ++ ++ if (!spi_nor_init_ok) { ++ diag_printf("Initializing SPI-NOR flash...\n"); ++ if (spi_nor_init(&imx_spi_nor) != 0) { ++ diag_printf("Error: failed to initialize SPI NOR\n"); ++ return -1; ++ } ++ spi_nor_init_ok = 1; ++ } ++ // Look through table for device data ++ //flash_dev_query(id); ++ spi_norflash_query(id); ++ flash_dev_info = supported_devices; ++ for (i = 0; i < NUM_DEVICES; i++) { ++ if ((flash_dev_info->device_id == id[0]) && ++ (flash_dev_info->device_id2 == id[1]) && ++ (flash_dev_info->device_id3 == id[2])) ++ break; ++ flash_dev_info++; ++ } ++ ++ // Do we find the device? If not, return error. ++ if (NUM_DEVICES == i) { ++ diag_printf("Unrecognized SPI NOR part: 0x%02x, 0x%02x, 0x%02x\n", ++ id[0], id[1], id[2]); ++ return FLASH_ERR_DRV_WRONG_PART; ++ } ++ ++ // Hard wired for now ++ flash_info.block_size = flash_dev_info->block_size; ++ flash_info.blocks = flash_dev_info->block_count; ++ flash_info.start = (void *)0; ++ flash_info.end = (void *)flash_dev_info->device_size; ++ ++ diag_printf("SPI NOR: block_size=0x%x, blocks=0x%x, start=%p, end=%p\n", ++ flash_info.block_size, flash_info.blocks, ++ flash_info.start, flash_info.end); ++ ++ if ((flash_dev_info->device_id == 0xbf) && ++ (flash_dev_info->device_id2 == 0x25) && ++ (flash_dev_info->device_id3 == 0x41)) { ++ spi_write_func = (imx_spi_write_func_t *)spi_nor_program_buf_sst; ++ spi_erase_func = (imx_spi_erase_func_t *)spi_nor_erase_block_sst; ++ } else { ++ spi_write_func = (imx_spi_write_func_t *)spi_nor_program_buf_atm; ++ spi_erase_func = (imx_spi_erase_func_t *)spi_nor_erase_block_atm; ++ } ++ ++ ++ return FLASH_ERR_OK; ++} ++ ++// used by redboot/current/src/flash.c ++int mxc_spi_nor_fis_start(void) ++{ ++ return (flash_dev_info->fis_start_addr); ++} ++ ++/*! ++ * Read from SPI NOR at src address to RAM at dest with len bytes ++ * @param src source address in the flash ++ * @param dest destination address in the RAM ++ * @param len # of bytes to copy ++ */ ++int spi_nor_read(void *src, void *dest, int len) ++{ ++ unsigned int *cmd = (unsigned int *)g_tx_buf; ++ unsigned int max_rx_sz = imx_spi_nor.fifo_sz - 4; // max rx bytes per burst ++ unsigned char *d_buf = (unsigned char *) dest; ++ unsigned char *s_buf; ++ int i; ++ ++ imx_spi_nor.us_delay = 100; ++ diag_printf1("%s(from flash=%p to ram=%p len=0x%x)\n", __FUNCTION__, ++ src, dest, len); ++ ++ if (len == 0) ++ return 0; ++ ++ *cmd = (READ << 24) | ((unsigned int)src & 0x00FFFFFF); ++ ++ while (1) { ++ if (len == 0) { ++ imx_spi_nor.us_delay = 0; ++ return 0; ++ } ++ if (len < max_rx_sz) { ++ diag_printf1("last read len=0x%x\n", len); ++ // deal with the last read ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (len + 4) * 8) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ s_buf = g_rx_buf + 4; // throw away 4 bytes (5th received bytes is real) ++ // now adjust the endianness ++ for (i = len; i >= 0; i -= 4, s_buf += 4) { ++ if (i < 4) { ++ if (i == 1) { ++ *d_buf = s_buf[0]; ++ } else if (i == 2) { ++ *d_buf++ = s_buf[1]; ++ *d_buf++ = s_buf[0]; ++ } else if (i == 3) { ++ *d_buf++ = s_buf[2]; ++ *d_buf++ = s_buf[1]; ++ *d_buf++ = s_buf[0]; ++ } ++ imx_spi_nor.us_delay = 0; ++ return 0; ++ } ++ // copy 4 bytes ++ *d_buf++ = s_buf[3]; ++ *d_buf++ = s_buf[2]; ++ *d_buf++ = s_buf[1]; ++ *d_buf++ = s_buf[0]; ++ } ++ } ++ // now grab max_rx_sz data (+4 is needed due to 4-throw away bytes ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (max_rx_sz + 4) * 8) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ s_buf = g_rx_buf + 4; // throw away 4 bytes (5th received bytes is real) ++ // now adjust the endianness ++ for (i = 0; i < max_rx_sz; i += 4, s_buf += 4) { ++ *d_buf++ = s_buf[3]; ++ *d_buf++ = s_buf[2]; ++ *d_buf++ = s_buf[1]; ++ *d_buf++ = s_buf[0]; ++ } ++ *cmd += max_rx_sz; // increase # of bytes in NOR address as cmd == g_tx_buf ++ len -= max_rx_sz; // # of bytes left ++ ++ diag_printf1("d_buf=%p, g_rx_buf=%p, len=0x%x\n", d_buf, g_rx_buf, len); ++ } ++ ++ imx_spi_nor.us_delay = 0; ++} ++ ++/*! ++ * program data from RAM to flash ++ * @param addr destination address in flash ++ * @param data source address in RAM ++ * @param len # of bytes to program ++ * Note: - when starting AAI programming, ++ * 1) the starting addr has to be 16-bit aligned ++ * 2) the prog len has to be even number of bytes ++ */ ++int spi_nor_program_buf(void *addr, void *data, int len) ++{ ++ int ret = 0; ++ ++ if (len == 0) ++ return 0; ++ ++ diag_printf1("%s(flash addr=%p, ram=%p, len=0x%x)\n", __FUNCTION__, addr, data, len); ++ imx_spi_nor.us_delay = 0; ++ ret = spi_write_func(addr, data, len, flash_dev_info->block_size); ++ ++ return ret; ++} ++ ++/*! ++ * Erase a block_size data from block_addr offset in the flash ++ */ ++int spi_nor_erase_block(void* block_addr, unsigned int block_size) ++{ ++ unsigned int addr = (unsigned int) block_addr; ++ int ret = 0; ++ ++ imx_spi_nor.us_delay = 0; ++ ++ if (block_size != SZ_64K && block_size != SZ_32K && block_size != SZ_4K) { ++ diag_printf("Error - block_size is not 64kB: 0x%x\n", block_size); ++ return -1; ++ } ++ ++ if ((addr & (block_size -1)) != 0) { ++ diag_printf("Error - block_addr is not 64kB aligned: %p\n", block_addr); ++ return -1; ++ } ++ ++ ret = spi_erase_func(block_addr, block_size); ++ return ret; ++} ++ ++/*! ++ * Erase a variable bytes data from SPI NOR flash for 64K blocks ++ * @param block_addr starting addresss in the SPI NOR flash ++ * @param size # of bytes to erase ++ */ ++int spi_nor_erase_64k(void* block_addr, unsigned int size) ++{ ++ unsigned int addr = (unsigned int) block_addr; ++ ++ if (size == 0) { ++ diag_printf("Error: size (0x%x) is not integer multiples of 64kB(0x10000)\n", size); ++ return -1; ++ } ++ if ((addr & (SZ_64K -1)) != 0) { ++ diag_printf("Error - addr is not 64kB(0x10000) aligned: %p\n", block_addr); ++ return -1; ++ } ++ for (; size > 0; size -= SZ_64K, addr += SZ_64K) { ++ if (spi_nor_erase_block((void *)addr, SZ_64K) != 0) { ++ diag_printf("Error: spi_nor_erase_64k(): %d\n", __LINE__); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++void spi_nor_setup(void) ++{ ++ if (!spi_nor_init_ok) { ++ diag_printf("Initializing SPI-NOR flash...\n"); ++ if (spi_nor_init(&imx_spi_nor) != 0) { ++ diag_printf("Error: failed to initialize SPI NOR\n"); ++ } ++ spi_nor_init_ok = 1; ++ } ++} ++ ++RedBoot_init(spi_nor_setup, RedBoot_INIT_PRIO(6800)); ++ ++////////////////////////////// commands /////////////////// ++static void do_spi_nor_op(int argc, char *argv[]); ++RedBoot_cmd("spiflash", ++ "Read/Write/Erase SPI NOR flash", ++ " ", ++ do_spi_nor_op ++ ); ++ ++static void do_spi_nor_op(int argc,char *argv[]) ++{ ++ unsigned int ram, flash, len; ++ unsigned char op; ++ int stat = -1; ++ ++ if (argc == 1 || argc != 5) { ++ diag_printf("\tRead: spiflash \n"); ++ diag_printf("\tWrite: spiflash \n"); ++ diag_printf("\tErase: spiflash \n"); ++ diag_printf(" NOTE: For erase, the ram-addr is ignored\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)&ram, &argv[1], ":")) { ++ diag_printf("Error: Invalid ram parameter\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[2]), (unsigned long *)&flash, &argv[2], ":")) { ++ diag_printf("Error: Invalid flash parameter\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[3]), (unsigned long *)&len, &argv[3], ":")) { ++ diag_printf("Error: Invalid length parameter\n"); ++ return; ++ } ++ ++ op = argv[4][0]; ++ switch (op) { ++ case 'r': ++ case 'R': ++ diag_printf("Reading SPI NOR flash 0x%x [0x%x bytes] -> ram 0x%x\n", flash, len, ram); ++ stat = spi_nor_read((void *)flash, (void *)ram, len); ++ break; ++ case 'w': ++ case 'W': ++ diag_printf("Writing SPI NOR flash 0x%x [0x%x bytes] <- ram 0x%x\n", flash, len, ram); ++ stat = spi_nor_program_buf((void *)flash, (void *)ram, len); ++ break; ++ case 'e': ++ case 'E': ++ diag_printf("Erasing SPI NOR flash 0x%x [0x%x bytes]\n", flash, len); ++ stat = spi_nor_erase_64k((void *)flash, len); ++ break; ++ default: ++ diag_printf("Error: unknown operation: 0x%02x\n", op); ++ } ++ diag_printf("%s\n\n", (stat == 0)? "SUCCESS": "FAILED"); ++ return; ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor_atmel.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor_atmel.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor_atmel.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor_atmel.c 2010-01-26 17:33:13.062960756 +0000 +@@ -0,0 +1,192 @@ ++#include ++#include ++#include ++#include ++ ++static unsigned char g_tx_buf[256]; ++static unsigned char g_rx_buf[256]; ++ ++static int spi_nor_status_atm(void) ++{ ++ g_tx_buf[1] = STAT_READ; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (2 * 8)) != 0) { ++ diag_printf("Error: %s(): %d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ return g_rx_buf[0]; ++} ++ ++int spi_nor_program_buf_atm(void *addr, void *data, int len, unsigned int block_size) ++{ ++ unsigned int d_addr = (unsigned int) addr; ++ unsigned char *s_buf = (unsigned char *) data; ++ unsigned int final_addr = 0; ++ int page_size = 528, trans_bytes = 0, buf_ptr = 0, bytes_sent = 0, byte_sent_per_iter = 0; ++ int page_no = 0, buf_addr = 0, page_off = 0, i = 0, j = 0, k = 0, fifo_size = 32; ++ int remain_len = 0; ++ ++ /* Read the status register to get the Page size */ ++ if (spi_nor_status_atm() & STAT_PG_SZ) { ++ page_size = 512; ++ } else { ++ diag_printf("Unsupported Page Size of 528 bytes\n"); ++ ++ g_tx_buf[0] = CONFIG_REG4; ++ g_tx_buf[1] = CONFIG_REG3; ++ g_tx_buf[2] = CONFIG_REG2; ++ g_tx_buf[3] = CONFIG_REG1; ++ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (4 * 8)) != 0) { ++ diag_printf("Error: %s(): %d\n", __FUNCTION__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (!(spi_nor_status_atm() & STAT_BUSY)) {} ++ ++ diag_printf("Reprogrammed the Page Size to be 512 bytes\n"); ++ diag_printf("Please Power Cycle the board for the change to take effect\n"); ++ return TRANS_FAIL; ++ } ++ ++ /* Due to the way CSPI operates send data less that 4 bytes in a different manner */ ++ remain_len = len % 4; ++ if (remain_len) ++ len -= remain_len; ++ ++ while (1) { ++ page_no = d_addr / page_size; ++ /* Get the offset within the page if address is not page-aligned */ ++ if (page_off = (d_addr % page_size)) { ++ if (page_no == 0) { ++ buf_addr = d_addr; ++ } else { ++ buf_addr = page_off; ++ } ++ trans_bytes = page_size - buf_addr; ++ } else { ++ buf_addr = 0; ++ trans_bytes = page_size; ++ } ++ ++ if (len <=0) ++ break; ++ ++ if (trans_bytes > len) ++ trans_bytes = len; ++ ++ bytes_sent = trans_bytes; ++ /* Write the data to the SPI-NOR Buffer first */ ++ while (trans_bytes > 0) { ++ final_addr = (buf_addr & 0x3FF); ++ g_tx_buf[0] = final_addr; ++ g_tx_buf[1] = final_addr >> 8; ++ g_tx_buf[2] = final_addr >> 16; ++ g_tx_buf[3] = BUF1_WR; /*Opcode */ ++ ++ /* 4 bytes already used for Opcode & address bytes, ++ check to ensure we do not overflow the SPI TX buffer */ ++ if (trans_bytes > (fifo_size - 4)) ++ byte_sent_per_iter = fifo_size; ++ else ++ byte_sent_per_iter = trans_bytes + 4; ++ ++ for (i = 4; i < byte_sent_per_iter; i += 4) { ++ g_tx_buf[i + 3] = s_buf[buf_ptr++]; ++ g_tx_buf[i + 2] = s_buf[buf_ptr++]; ++ g_tx_buf[i + 1] = s_buf[buf_ptr++]; ++ g_tx_buf[i] = s_buf[buf_ptr++]; ++ } ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (byte_sent_per_iter * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (!(spi_nor_status_atm() & STAT_BUSY)) {} ++ ++ /* Deduct 4 bytes as it is used for Opcode & address bytes */ ++ trans_bytes -= (byte_sent_per_iter - 4); ++ /* Update the destination buffer address */ ++ buf_addr += (byte_sent_per_iter - 4); ++ } ++ ++ /* Send the command to write data from the SPI-NOR Buffer to Flash memory */ ++ if (page_size == 512) { ++ final_addr = (page_no & 0x1FFF) << 9; ++ } else { ++ final_addr = (page_no & 0x1FFF) << 10; ++ } ++ ++ /* Specify the Page address in Flash where the data should be written to */ ++ g_tx_buf[0] = final_addr; ++ g_tx_buf[1] = final_addr >> 8; ++ g_tx_buf[2] = final_addr >> 16; ++ g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (4 * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (!(spi_nor_status_atm() & STAT_BUSY)) {} ++ ++ d_addr += bytes_sent; ++ len -= bytes_sent; ++ if (d_addr % (page_size * 50) == 0) { ++ diag_printf("."); ++ } ++ } ++ ++ if (remain_len) { ++ buf_ptr += remain_len; ++ /* Write the remaining data bytes first */ ++ for (i = 0; i < remain_len; i++) { ++ g_tx_buf[i] = s_buf[buf_ptr--]; ++ } ++ /* Write the address bytes next in the same word as the data byte from the next byte */ ++ for (j = i, k = 0; j < 4; j++, k++) { ++ g_tx_buf[j] = final_addr >> (k * 8); ++ } ++ /* Write the remaining address bytes in the next word */ ++ j = 0; ++ final_addr = (buf_addr & 0x3FF); ++ ++ for (j = 0; k < 3; j++, k++) { ++ g_tx_buf[j] = final_addr >> (k * 8); ++ } ++ /* Finally the Opcode to write the data to the buffer */ ++ g_tx_buf[j] = BUF1_WR; /*Opcode */ ++ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (remain_len + 4) * 8) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (!(spi_nor_status_atm() & STAT_BUSY)) {} ++ ++ if (page_size == 512) { ++ final_addr = (page_no & 0x1FFF) << 9; ++ } else { ++ final_addr = (page_no & 0x1FFF) << 10; ++ } ++ ++ g_tx_buf[0] = final_addr; ++ g_tx_buf[1] = final_addr >> 8; ++ g_tx_buf[2] = final_addr >> 16; ++ g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (4 * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (!(spi_nor_status_atm() & STAT_BUSY)) {} ++ ++ } ++ ++ return 0; ++} ++ ++int spi_nor_erase_block_atm(void* block_addr, unsigned int block_size) ++{ ++ /* Erase not implemented, the write command has a built-in erase */ ++ return 0; ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor_sst.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor_sst.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/spi_nor_sst.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/spi_nor_sst.c 2010-01-26 17:33:13.062960756 +0000 +@@ -0,0 +1,194 @@ ++#include ++#include ++#include ++#include ++ ++static unsigned char g_tx_buf[256]; ++static unsigned char g_rx_buf[256]; ++ ++#define WRITE_ENABLE() spi_nor_cmd_1byte(WREN) ++#define WRITE_DISABLE() spi_nor_cmd_1byte(WRDI) ++#define ENABLE_WRITE_STATUS() spi_nor_cmd_1byte(EWSR) ++ ++static int spi_nor_cmd_1byte(unsigned char cmd) ++{ ++ g_tx_buf[0] = cmd; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (1 * 8)) != 0) { ++ diag_printf("Error: %s(): %d\n", __FUNCTION__, __LINE__); ++ return TRANS_FAIL; ++ } ++ return 0; ++} ++ ++static int spi_nor_program_1byte(unsigned char data, void *addr) ++{ ++ unsigned int addr_val = (unsigned int) addr; ++ ++ // need to do write-enable command ++ if (WRITE_ENABLE() != 0) { ++ diag_printf("Error : %d\n", __LINE__); ++ return -1; ++ } ++ g_tx_buf[0] = BYTE_PROG; // need to skip bytes 1, 2, 3 ++ g_tx_buf[4] = data; ++ g_tx_buf[5] = addr_val & 0xFF; ++ g_tx_buf[6] = (addr_val >> 8) & 0xFF; ++ g_tx_buf[7] = (addr_val >> 16) & 0xFF; ++ ++ diag_printf("0x%x: 0x%x\n", *(unsigned int*)g_tx_buf, *(unsigned int*)(g_tx_buf + 4)); ++ diag_printf("addr=0x%x\n", addr_val); ++ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (5 * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (spi_nor_status() & RDSR_BUSY) { ++ } ++ return 0; ++} ++ ++int spi_nor_program_buf_sst(void *addr, void *data, int len, unsigned int block_size) ++{ ++ unsigned int d_addr = (unsigned int) addr; ++ unsigned char *s_buf = (unsigned char *) data; ++ ++ if (ENABLE_WRITE_STATUS() != 0 || spi_nor_write_status(0) != 0) { ++ diag_printf("Error: %s: %d\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ ++ if ((d_addr & 1) != 0) { ++ // program 1st byte ++ if (spi_nor_program_1byte(s_buf[0], (void *)d_addr) != 0) { ++ diag_printf("Error: %s(%d)\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ if (--len == 0) ++ return 0; ++ d_addr++; ++ s_buf++; ++ } ++ ++ // need to do write-enable command ++ if (WRITE_ENABLE() != 0) { ++ diag_printf("Error : %d\n", __LINE__); ++ return -1; ++ } ++ ++ // These two bytes write will be copied to txfifo first with ++ // g_tx_buf[1] being shifted out and followed by g_tx_buf[0]. ++ // The reason for this is we will specify burst len=6. So SPI will ++ // do this kind of data movement. ++ g_tx_buf[0] = d_addr >> 16; ++ g_tx_buf[1] = AAI_PROG; // need to skip bytes 1, 2 ++ // byte shifted order is: 7, 6, 5, 4 ++ g_tx_buf[4] = s_buf[1]; ++ g_tx_buf[5] = s_buf[0]; ++ g_tx_buf[6] = d_addr; ++ g_tx_buf[7] = d_addr >> 8; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (6 * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (spi_nor_status() & RDSR_BUSY) { ++ } ++ ++ for (d_addr += 2, s_buf += 2, len -= 2 ; ++ len > 1; ++ d_addr += 2, s_buf += 2, len -= 2) { ++ // byte shifted order is: 2,1,0 ++ g_tx_buf[2] = AAI_PROG; ++ g_tx_buf[1] = s_buf[0]; ++ g_tx_buf[0] = s_buf[1]; ++ ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (3 * 8)) != 0) { ++ diag_printf("Error: %s(%d): failed\n", __FILE__, __LINE__); ++ return TRANS_FAIL; ++ } ++ ++ while (spi_nor_status() & RDSR_BUSY) { ++ } ++ if ((len % block_size) == 0) { ++ diag_printf("."); ++ } ++ } ++ WRITE_DISABLE(); ++ while (spi_nor_status() & RDSR_BUSY) { ++ } ++ ++ if (WRITE_ENABLE() != 0) { ++ diag_printf("Error : %d\n", __LINE__); ++ return -1; ++ } ++ if (len == 1) { ++ // need to do write-enable command ++ // only 1 byte left ++ if (spi_nor_program_1byte(s_buf[0], (void *)d_addr) != 0) { ++ diag_printf("Error: %s(%d)\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++static int spi_nor_status(void) ++{ ++ g_tx_buf[1] = RDSR; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (2 * 8)) != 0) { ++ diag_printf("Error: %s(): %d\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ return g_rx_buf[0]; ++} ++ ++/*! ++ * Write 'val' to flash WRSR (write status register) ++ */ ++static int spi_nor_write_status(unsigned char val) ++{ ++ g_tx_buf[0] = val; ++ g_tx_buf[1] = WRSR; ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (2 * 8)) != 0) { ++ diag_printf("Error: %s(): %d\n", __FUNCTION__, __LINE__); ++ return TRANS_FAIL; ++ } ++ return 0; ++} ++ ++int spi_nor_erase_block_sst(void* block_addr, unsigned int block_size) ++{ ++ unsigned int *cmd = (unsigned int *)g_tx_buf; ++ unsigned int addr = (unsigned int) block_addr; ++ ++ if (ENABLE_WRITE_STATUS() != 0 || spi_nor_write_status(0) != 0) { ++ diag_printf("Error: %s: %d\n", __FUNCTION__, __LINE__); ++ return -1; ++ } ++ ++ // need to do write-enable command ++ if (WRITE_ENABLE() != 0) { ++ diag_printf("Error : %d\n", __LINE__); ++ return -1; ++ } ++ ++ if (block_size == SZ_64K) { ++ *cmd = (ERASE_64K << 24) | (addr & 0x00FFFFFF); ++ } else if (block_size == SZ_32K) { ++ *cmd = (ERASE_32K << 24) | (addr & 0x00FFFFFF); ++ } else if (block_size == SZ_4K) { ++ *cmd = (ERASE_4K << 24) | (addr & 0x00FFFFFF); ++ } ++ ++ // now do the block erase ++ if (spi_nor_xfer(&imx_spi_nor, g_tx_buf, g_rx_buf, (4 * 8)) != 0) { ++ return TRANS_FAIL; ++ } ++ ++ while (spi_nor_status() & RDSR_BUSY) { ++ } ++ ++ return 0; ++} +diff -urNad redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/stmp_nand.c redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/stmp_nand.c +--- redboot-imx-200952~/packages/devs/flash/arm/mxc/current/src/stmp_nand.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/arm/mxc/current/src/stmp_nand.c 2010-01-26 17:33:13.082954129 +0000 +@@ -0,0 +1,2367 @@ ++//========================================================================== ++// ++// stmp_nfc.c ++// ++// Flash programming to support NAND flash on Freescale STMP platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ivan Xu ++// Contributors: Ivan Xu ++// Purpose: ++// Description: ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#define _FLASH_PRIVATE_ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Search good / bad pattern on the first page only */ ++#define NAND_BBT_SCAN1STPAGE 0x00000001 ++/* Search good / bad pattern on the first and the second page */ ++#define NAND_BBT_SCAN2NDPAGE 0x00000002 ++/* Search good / bad pattern on the last page only */ ++#define NAND_BBT_SCANLSTPAGE 0x00000004 ++ ++static const flash_dev_info_t* flash_dev_info; ++ ++static const flash_dev_info_t supported_devices[] = { ++#include ++}; ++ ++#define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t)) ++ ++#define COL_CYCLE flash_dev_info->col_cycle ++#define ROW_CYCLE flash_dev_info->row_cycle ++#define NF_PG_SZ flash_dev_info->page_size ++#define NF_PG_PER_BLK flash_dev_info->pages_per_block ++#define NF_DEV_SZ flash_dev_info->device_size ++#define NF_BLK_SZ flash_dev_info->block_size ++#define NF_BLK_CNT flash_dev_info->block_count ++#define NF_VEND_INFO flash_dev_info->vendor_info ++#define NF_OPTIONS flash_dev_info->options ++#define NF_BBT_MAX_NR flash_dev_info->bbt_blk_max_nr ++#define NF_OPTIONS flash_dev_info->options ++#define NF_BI_OFF flash_dev_info->bi_off ++ ++#define BLOCK_TO_OFFSET(blk) (blk * NF_PG_PER_BLK * NF_PG_SZ) ++#define BLOCK_TO_PAGE(blk) (blk * NF_PG_PER_BLK) ++#define BLOCK_PAGE_TO_OFFSET(blk, pge) ((blk * NF_PG_PER_BLK + pge) * NF_PG_SZ) ++#define OFFSET_TO_BLOCK(offset) ((offset / NF_PG_SZ) / NF_PG_PER_BLK) ++#define OFFSET_TO_PAGE(offset) ((offset / NF_PG_SZ) % NF_PG_PER_BLK) ++ ++static int nand_flash_index = -1; ++static int g_nfc_debug_level = NFC_DEBUG_MIN; ++ ++#define nfc_printf(level, args...) \ ++ do { \ ++ if (g_nfc_debug_level >= level) \ ++ diag_printf(args); \ ++ } while(0) ++ ++#define SUCCESS 0 ++#define FAIL 1 ++ ++#define RSVBUFFADDR 0x41000000 // unbufferable, uncacheable ++#define BUFFER_SIZE 0x10000 ++ ++// globals ++static NAND_ECC_Params_t nand_ecc_params; ++extern void nand_ConfigurePinmux(void); ++ ++int ++#ifndef MXCFLASH_SELECT_MULTI ++flash_hwr_init(void) ++#else ++nandflash_hwr_init(void) ++#endif ++{ ++ int i; ++ ReadIDCode *pReadIDBuf; ++ unsigned short device_id2; ++ ++ nfc_printf(NFC_DEBUG_MED, "%s()\n", __FUNCTION__); ++ ++ pReadIDBuf = (ReadIDCode *)(RSVBUFFADDR+ BUFFER_SIZE); ++ memset(pReadIDBuf, 0x34, sizeof(ReadIDCode)); ++ ++ nand_Init(pReadIDBuf); ++ device_id2 = ((pReadIDBuf->SamsungHSSerialAccess << 15) | (pReadIDBuf->Organization << 14) | ++ (pReadIDBuf->BlockSize << 12) | (pReadIDBuf->Reserved0 << 11) | ++ (pReadIDBuf->RedundantAreaSize << 10) | (pReadIDBuf->PageSize << 8) | ++ (pReadIDBuf->CacheProgram << 7) | (pReadIDBuf->VendorSpecific0 << 4) | ++ (pReadIDBuf->CellType << 2) | (pReadIDBuf->InternalChipNumber)) & 0xFFFF; ++ ++ flash_dev_info = supported_devices; ++ for (i = 0; i < NUM_DEVICES; i++) { ++ if ((flash_dev_info->device_id == pReadIDBuf->DeviceID_Code.usDeviceID) && ++ ((flash_dev_info->device_id2 == 0xFFFF) || ++ (flash_dev_info->device_id2 == device_id2))) ++ break; ++ ++ flash_dev_info++; ++ } ++ ++ // Do we find the device? If not, return error. ++ if (NUM_DEVICES == i) { ++ diag_printf("Unrecognized NAND part: 0x%x 0x%x\n", pReadIDBuf->DeviceID_Code.usDeviceID, device_id2); ++ return FLASH_ERR_DRV_WRONG_PART; ++ } ++ ++ nand_flash_index = i; ++ ++ flash_info.block_size = NF_BLK_SZ; ++ flash_info.blocks = NF_BLK_CNT; ++ flash_info.start = (void *)0; ++ flash_info.end = NF_DEV_SZ; ++ ++ return SUCCESS; ++ ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++void flash_query(void* data) ++#else ++void nandflash_query(void* data) ++#endif ++{ ++ return; ++ ++} ++ ++// Read data into buffer ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_read_buf(void* addr, void* data, int len) ++#else ++int nandflash_read_buf(void* addr, void* data, int len) ++#endif ++{ ++ int status; ++ int i; ++ unsigned char *p8PageBuf, *phy_8PageBuf; ++ unsigned char * p8AuxillaryBuf, *phy_8AuxillaryBuf; ++ int size; ++ unsigned int offset, pageNum; ++ ++ ++ nfc_printf(NFC_DEBUG_MED, "%s()\n", __FUNCTION__); ++ ++ p8PageBuf = (unsigned char *)(RSVBUFFADDR + BUFFER_SIZE); ++ memset(p8PageBuf, 0x0, 0x2000); ++ p8AuxillaryBuf = (unsigned char *)(RSVBUFFADDR + BUFFER_SIZE + 0x2000); ++ memset(p8AuxillaryBuf, 0x0, 0x2000); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(p8PageBuf, phy_8PageBuf); ++ HAL_VIRT_TO_PHYS_ADDRESS(p8AuxillaryBuf, phy_8AuxillaryBuf); ++ ++ size = len; ++ // convert addr to pageNum; ++ nfc_printf(NFC_DEBUG_MAX, "len: 0x%x\n", len); ++ nfc_printf(NFC_DEBUG_MAX, "addr: 0x%x\n", (unsigned int)addr); ++ ++ nand_offset2pagenum((unsigned int)addr, &pageNum); ++ ++ i = 0; ++ ++ while (size>0) { ++ nfc_printf(NFC_DEBUG_MAX, "Page Num: 0x%x", pageNum); ++ status = nand_Read(0, 0, pageNum, NF_PG_SZ + flash_dev_info->spare_size, phy_8PageBuf, phy_8AuxillaryBuf); ++ if (status == SUCCESS){ ++ nfc_printf(NFC_DEBUG_MAX, "0x%x 0x%x 0x%x \n", *p8PageBuf, *(p8PageBuf+1), *(p8PageBuf+2)); ++ nfc_printf(NFC_DEBUG_MED, "Read Passed.\n"); ++ } ++ ++ if (size >= NF_PG_SZ){ ++ memcpy((unsigned int)data + i * NF_PG_SZ, p8PageBuf , NF_PG_SZ); ++ } ++ else{ ++ memcpy((unsigned int)data + i * NF_PG_SZ, p8PageBuf , size); ++ } ++ ++ i++; ++ pageNum++; ++ size -= NF_PG_SZ; ++ } ++ ++ return SUCCESS; ++ //return nfc_read_region((u32)addr, (u32)data, (u32)len); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_program_buf(void* addr, void* data, int len) ++#else ++int nandflash_program_buf(void* addr, void* data, int len) ++#endif ++{ ++ int status; ++ int i; ++ unsigned char *p8PageBuf, *phy_8PageBuf; ++ unsigned char * p8AuxillaryBuf, *phy_8AuxillaryBuf; ++ int size; ++ unsigned int offset, pageNum, BlockNum; ++ ++ nfc_printf(NFC_DEBUG_MED, "===========Write NAND==============\n"); ++ p8PageBuf = (unsigned char *)(RSVBUFFADDR+BUFFER_SIZE); ++ memset(p8PageBuf, 0x00, 0x2000); ++ p8AuxillaryBuf = (unsigned char *)(RSVBUFFADDR+BUFFER_SIZE + 0x2000); ++ memset(p8AuxillaryBuf, 0x00, 0x2000); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(p8PageBuf, phy_8PageBuf); ++ HAL_VIRT_TO_PHYS_ADDRESS(p8AuxillaryBuf, phy_8AuxillaryBuf); ++ ++ size = len; ++ // convert addr to pageNum; ++ nfc_printf(NFC_DEBUG_MAX, "len: 0x%x\n", len); ++ nfc_printf(NFC_DEBUG_MAX, "addr: 0x%x\n", (unsigned int)addr); ++ ++ nand_offset2pagenum((unsigned int)addr, &pageNum); ++ ++ BlockNum = pageNum / NF_PG_PER_BLK; ++ while(size > 0) { ++ nand_Erase(0, BlockNum); ++ BlockNum++; ++ size -= NF_PG_SZ * NF_PG_PER_BLK; ++ } ++ ++ i = 0; ++ size = len; ++ while (size > 0) { ++ nfc_printf(NFC_DEBUG_MAX, "Page Num: 0x%x", pageNum); ++ ++ memcpy(p8PageBuf , (unsigned int)data + i * NF_PG_SZ, NF_PG_SZ); ++ status = nand_Write(0, pageNum, phy_8PageBuf, phy_8AuxillaryBuf); ++ if(status == SUCCESS){ ++ nfc_printf(NFC_DEBUG_MED, "Write Passed.\n"); ++ } ++ ++ size -= NF_PG_SZ; ++ pageNum++; ++ i++; ++ } ++ ++ return SUCCESS; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_erase_block(void* block, unsigned int size) ++#else ++int nandflash_erase_block(void* block, unsigned int size) ++#endif ++{ ++ int status; ++ int i; ++ unsigned int offset, BlockNum; ++ ++ return SUCCESS; ++ ++ diag_printf("block: 0x%x size: 0x%x\n", (unsigned int)block, size); ++ ++ BlockNum = (unsigned int)block; ++ ++ while(size>0){ ++ nand_Erase(0, BlockNum); ++ size -= NF_PG_SZ * 64; ++ BlockNum++; ++ } ++ ++ return 0; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++bool flash_code_overlaps(void *start, void *end) ++#else ++bool nandflash_code_overlaps(void *start, void *end) ++#endif ++{ ++ extern unsigned char _stext[], _etext[]; ++ ++ return ((((unsigned long)&_stext >= (unsigned long)start) && ++ ((unsigned long)&_stext < (unsigned long)end)) || ++ (((unsigned long)&_etext >= (unsigned long)start) && ++ ((unsigned long)&_etext < (unsigned long)end))); ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_map_error(int e) ++#else ++int nandflash_hwr_map_error(int e) ++#endif ++{ ++ return e; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_lock_block(void* block) ++#else ++int nandflash_lock_block(void* block) ++#endif ++{ ++ // Not supported yet ++ return 0; ++} ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_unlock_block(void* block, int block_size, int blocks) ++#else ++int nandflash_unlock_block(void* block, int block_size, int blocks) ++#endif ++{ ++ // Not supported yet ++ return 0; ++} ++ ++ ++int nand_offset2pagenum(unsigned int offset, unsigned int * pagenum) ++{ ++ if (offset % NF_PG_SZ) { ++ diag_printf("%s: nand read/write/erase address should be 2KB aligned\n", __FUNCTION__); ++ return 1; ++ } ++ ++ *pagenum = (offset / NF_PG_SZ); ++ ++ return 0; ++} ++ ++int nand_FindGpmiCycles(unsigned int u32NandTime_ns, ++ unsigned int u32GpmiPeriod_ns, ++ unsigned int u32MaxSearchTimes) ++{ ++ int i, iCycleTime = u32GpmiPeriod_ns; ++ ++ // Assume a maximum of 15 tests ++ for (i=1;i u32NandTime_ns) { ++ break; ++ } else { ++ iCycleTime += u32GpmiPeriod_ns; ++ } ++ } ++ return i; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++//! \brief Setup the NAND clocks ++//! ++//! This function sets the GPMI NAND timing based upon the NAND timings that ++//! are passed in. This module assumes a GPMI_CLK of 24MHz if the GpmiPeriod ++//! parameter is zero (41nsec period). If the GPMI clock period is non-zero ++//! it is used in the calculation of the new register values. ++//! ++//! \param[in] pNANDTiming Structure with Address Setup, Data Setup and Hold. ++//! \param[in] u32GpmiPeriod_ns GPMI Clock Period in nsec. ++//! ++//! \return void ++//////////////////////////////////////////////////////////////////////////////// ++void nand_GpmiSetNandTiming(void * pNewNANDTiming, unsigned int u32GpmiPeriod_ns) ++{ ++ NAND_Timing_t * pNANDTiming = (NAND_Timing_t *) pNewNANDTiming; ++ unsigned int val; ++ ++ ++ // CLKGATE = 0 and DIV = 1 (we're assuming a 24MHz XTAL for this). ++ // HW_CLKCTRL_GPMICLKCTRL_WR(0x01); ++ // Clock dividers are now set globally for PLL bypass in startup / setup_default_clocks() ++ // The divider may also be changed by drivers (like USB) that turn on the PLL ++ // HW_CLKCTRL_GPMICLKCTRL_CLR(BM_CLKCTRL_GPMICLKCTRL_CLKGATE); // ungate ++ ++ // Ungate GPMICLK. Because the gate is upstream of the divider, special ++ // care must be taken to make sure the divider is set correctly. Any ++ // change to HW_CLKCTRL_GPMICLKCTRL.B.DIV while the clock is gated is ++ // saved to the register, but *NOT* transferred to the actual divider. ++ // Clearing HW_CLKCTRL_GPMICLKCTRL.B.WAIT_PLL_LOCK serves two purposes. ++ // First, it forces the divider to update because it writes the control ++ // register while the clock is not gated. Second, it makes sure the update ++ // completes immediately by removing the PLL locked qualifier. ++ //HW_CLKCTRL_GPMI.B.CLKGATE = 0; ++ val = readl(CLKCTRL_GPMI_ADDR); // clock control GPMI, clock on ++ val &= ~(1<<31); ++ writel(val, CLKCTRL_GPMI_ADDR); ++ ++ ++ // If u32GpmiPeriod is passed in as 0, we'll use the default 41nsec ++ // for a 24MHz clock. ++ if (u32GpmiPeriod_ns == 0) ++ u32GpmiPeriod_ns = 42; ++ ++ // Set all NAND timing parameters ++ // Setup pin timing parameters: ADRESS_SETUP, DATA_SETUP, and DATA_HOLD. ++ // (Note that these are in units of GPMICLK cycles.) ++ { ++ unsigned int u32AddressSetup ; ++ unsigned int u32DataSetup ; ++ unsigned int u32DataHold ; ++ unsigned int u32DataSampleTime ; ++ unsigned int u32BusyTimeout ; ++ ++ u32AddressSetup = nand_FindGpmiCycles( ++ pNANDTiming->m_u8AddressSetup, u32GpmiPeriod_ns, ++ 20); ++ u32DataSetup = nand_FindGpmiCycles( ++ pNANDTiming->m_u8DataSetup, u32GpmiPeriod_ns, ++ 20); ++ u32DataHold = nand_FindGpmiCycles( ++ pNANDTiming->m_u8DataHold, u32GpmiPeriod_ns, ++ 20); ++ ++ // DSAMPLE is calculated in 1/2 GPMI clock units, so use shifts to compensate. ++ // This one should not round up so I subtract the cycle back off. ++ u32DataSampleTime = nand_FindGpmiCycles( ++ (pNANDTiming->m_u8DSAMPLE_TIME + (u32GpmiPeriod_ns >> 2)), (u32GpmiPeriod_ns>>1), ++ 20) - 1; ++ ++ HW_GPMI_TIMING0_WR(NAND_GPMI_TIMING0(u32AddressSetup, u32DataSetup, u32DataHold)); ++ ++ // set rdn_delay ++ val = readl(GPMI_CTRL1_ADDR); ++ val &= ~(0xf<<12); ++ val |= ((u32DataSampleTime & 0xf)<<12); ++ writel(val, GPMI_CTRL1_ADDR); ++ ++ // Set DSAMPLE_TIME value ++ //BW_GPMI_CTRL1_DSAMPLE_TIME(ROUND_CLK(pNANDTiming->m_u8DSAMPLE_TIME, u32GpmiPeriod)); ++ //BW_GPMI_CTRL1_DSAMPLE_TIME(u32DataSampleTime); ++ ++ u32BusyTimeout = 0x132; ++// u32BusyTimeout = nand_FindGpmiCycles(((10000000 + 4095) / 4096), ++// u32GpmiPeriod_ns, ++// ((10000000 + 4095) / 4096)/5); ++ ++ // Number of cycles / 4096. ++// HW_GPMI_TIMING1_WR( BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(u32BusyTimeout)); ++ writel(u32BusyTimeout<<16, GPMI_TIMEOUT1_ADDR); ++ ++ nfc_printf(NFC_DEBUG_MED, "GPMI TIME0: 0x%x\n", readl(GPMI_TIMEOUT0_ADDR)); ++ nfc_printf(NFC_DEBUG_MED, "GPMI TIME1: 0x%x\n", readl(GPMI_TIMEOUT1_ADDR)); ++ } ++} ++ ++int nand_EnableGPMI(void) ++{ ++ unsigned int val; ++ ++#if 1 ++ const NAND_Timing_t zFailsafeTimings = ++ { ++ 100, //!< Data Setup (ns) ++ 80, //!< Data Hold (ns) ++ 120, //!< Address Setup (ns) ++ 10 //!< DSAMPLE_TIME (ns) ++ }; ++ ++#else ++ const NAND_Timing_t zFailsafeTimings = ++ { ++ 10, //!< Data Setup (ns) ++ 5, //!< Data Hold (ns) ++ 10, //!< Address Setup (ns) ++ 10 //!< DSAMPLE_TIME (ns) ++ }; ++#endif ++ ++ /* enable GPMI clock */ ++ val = readl(CLKCTRL_GPMI_ADDR); // clock control GPMI, clock on ++ val &= ~(1<<31); ++ writel(val, CLKCTRL_GPMI_ADDR); ++ ++ // Bring GPMI out of soft reset and release clock gate. ++ // SoftReset needs to be set before ClockGate - can't be the same ++ // instruction. ++ ++ // preparing soft reset and clock gate. ++ val = readl(GPMI_CTRL0_ADDR); ++ val &= ~(0x3<<30); ++ writel(val, GPMI_CTRL0_ADDR); ++ ++ // Only soft reset if GPMI hasn't been enabled. ++ val = readl(GPMI_CTRL0_ADDR); ++ val |= (1<<31); ++ writel(val, GPMI_CTRL0_ADDR); ++ ++ // At 24Mhz, it takes no more than 4 clocks (160 ns) Maximum for ++ // the part to reset, reading the register twice should ++ // be sufficient to get 4 clks delay. ++ // waiting for confirmation of soft reset ++ while (!(readl(GPMI_CTRL0_ADDR) & (1<<30))) ++ { ++ // busy wait ++ } ++ ++ // Now bring out of reset and disable Clk gate. ++ val = readl(GPMI_CTRL0_ADDR); ++ val &= ~(0x3<<30); ++ writel(val, GPMI_CTRL0_ADDR); ++ ++ // Use the failsafe timings and default 24MHz clock ++ nand_GpmiSetNandTiming((NAND_Timing_t *)&zFailsafeTimings, 0); ++ ++ // Configure all of the pads that will be used for GPMI. ++ nand_ConfigurePinmux(); ++ ++ // Put GPMI in NAND mode, keep DEVICE reset enabled, and make certain ++ // polarity is active high ++ HW_GPMI_CTRL1_WR( ++ BF_GPMI_CTRL1_DEV_RESET(BV_GPMI_CTRL1_DEV_RESET__DISABLED) | ++ BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH) | ++ BW_GPMI_CTRL1_GPMI_MODE(BV_GPMI_CTRL1_GPMI_MODE__NAND)); ++ ++ return SUCCESS; ++} ++ ++// for BCH ++void nand_SetFlashLayout(unsigned int u32NandDeviceNumber, ++ NAND_ECC_Params_t* pnandecc) ++{ ++ unsigned int val; ++ if( u32NandDeviceNumber == 0 ) ++ { ++ // for nand0 ++ ++ // set flash0layout0 bch ecc register ++#if 0 ++ BW_BCH_FLASH0LAYOUT0_NBLOCKS(pReadSeed->zNANDEccParams.m_u32NumEccBlocksPerPage); ++ BW_BCH_FLASH0LAYOUT0_META_SIZE(pReadSeed->zNANDEccParams.m_u32MetadataBytes); ++ BW_BCH_FLASH0LAYOUT0_ECC0(pReadSeed->zNANDEccParams.m_u32EccBlock0EccLevel/2); ++ BW_BCH_FLASH0LAYOUT0_DATA0_SIZE(pReadSeed->zNANDEccParams.m_u32EccBlock0Size); ++#else ++ val = (pnandecc->m_u32EccBlock0Size & 0xfff) | ++ (((pnandecc->m_u32EccBlock0EccLevel/2) & 0xf)<<12 )| ++ ((pnandecc->m_u32MetadataBytes & 0xff)<<16) | ++ ((pnandecc->m_u32NumEccBlocksPerPage & 0xff)<<24); ++ nfc_printf(NFC_DEBUG_MAX, "BCH Flash layout 0: 0x%x\n", val); ++ writel(val, BCH_FLASH0_LAYOUT0_ADDR); ++#endif ++ ++ // set flash0layout1 bch ecc register ++#if 0 ++ BW_BCH_FLASH0LAYOUT1_PAGE_SIZE(pReadSeed->zNANDEccParams.m_u32PageSize); ++ BW_BCH_FLASH0LAYOUT1_ECCN(pReadSeed->zNANDEccParams.u32EccType/2); ++ BW_BCH_FLASH0LAYOUT1_DATAN_SIZE(pReadSeed->zNANDEccParams.m_u32EccBlockNSize); ++ ++#else ++ val = (pnandecc->m_u32EccBlockNSize & 0xfff) | ++ (((pnandecc->u32EccType/2) & 0xf)<<12) | ++ ((pnandecc->m_u32PageSize & 0xffff)<<16); ++ ++ nfc_printf(NFC_DEBUG_MAX, "BCH Flash layout 1: 0x%x\n", val); ++ ++ writel(val, BCH_FLASH0_LAYOUT1_ADDR); ++#endif ++ ++ } else if (u32NandDeviceNumber == 1 ) { ++ // for nand1 ++/* ++ // set flash1layout0 bch ecc register ++ BW_BCH_FLASH1LAYOUT0_NBLOCKS(pReadSeed->zNANDEccParams.m_u32NumEccBlocksPerPage); ++ BW_BCH_FLASH1LAYOUT0_META_SIZE(pReadSeed->zNANDEccParams.m_u32MetadataBytes); ++ BW_BCH_FLASH1LAYOUT0_ECC0(pReadSeed->zNANDEccParams.m_u32EccBlock0EccLevel/2); ++ BW_BCH_FLASH1LAYOUT0_DATA0_SIZE(pReadSeed->zNANDEccParams.m_u32EccBlock0Size); ++ ++ // set flash1layout1 bch ecc register ++ BW_BCH_FLASH1LAYOUT1_PAGE_SIZE(pReadSeed->zNANDEccParams.m_u32PageSize); ++ BW_BCH_FLASH1LAYOUT1_ECCN(pReadSeed->zNANDEccParams.u32EccType/2); ++ BW_BCH_FLASH1LAYOUT1_DATAN_SIZE(pReadSeed->zNANDEccParams.m_u32EccBlockNSize); ++ ++*/ ++ } ++ ++ // Set flash layoutselect ++ //writel(0x0, 0x8000a070); ++} ++ ++void nand_ResetECC8(void) ++{ ++ unsigned int val; ++ // Bring out of reset and disable Clk gate. ++ // Soft Reset the ECC8 block ++ val = readl(ECC8_CTRL_ADDR); ++ val |= (1<<31); ++ writel(val, ECC8_CTRL_ADDR); ++ val &= ~(1<<31); ++ writel(val, ECC8_CTRL_ADDR); ++ ++ // Now bring out of reset and disable Clk gate. ++ val = readl(ECC8_CTRL_ADDR); ++ val |= (1<<30); ++ writel(val, ECC8_CTRL_ADDR); ++ val &= ~(1<<30); ++ writel(val, ECC8_CTRL_ADDR); ++ // Set the AHBM soft reset. ++ val = readl(ECC8_CTRL_ADDR); ++ val |= (1<<29); ++ writel(val, ECC8_CTRL_ADDR); ++ val &= ~(1<<29); ++ writel(val, ECC8_CTRL_ADDR); ++ ++} ++ ++void nand_ResetBCH(void) ++{ ++ unsigned int val; ++ // Bring out of reset and disable Clk gate. ++ // Soft Reset the BCH block ++ val = readl(BCH_CTRL_ADDR); ++ val |= (1<<31); ++ writel(val, BCH_CTRL_ADDR); ++ val &= ~(1<<31); ++ writel(val, BCH_CTRL_ADDR); ++ // Now bring out of reset and disable Clk gate. ++ val = readl(BCH_CTRL_ADDR); ++ val |= (1<<30); ++ writel(val, BCH_CTRL_ADDR); ++ val &= ~(1<<30); ++ writel(val, BCH_CTRL_ADDR); ++ ++} ++ ++void nand_ResetDma(NAND_dma_reset_device_t* pChain, unsigned int u32NandDeviceNumber) ++{ ++ // First we want to wait for Ready. The chip may be busy on power-up. ++ // Wait for Ready. ++ pChain->wait4rdy_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->sense_rdy_dma); ++ pChain->wait4rdy_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ // BAR points to alternate branch if timeout occurs. ++ pChain->wait4rdy_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Set GPMI wait for ready. ++ pChain->wait4rdy_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++ // Now check for successful Ready. ++ pChain->sense_rdy_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->tx_dma); ++ pChain->sense_rdy_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // BAR points to alternate branch if timeout occurs. ++ pChain->sense_rdy_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_rdy_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++ // Next command will be a wait. ++ pChain->tx_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->wait_dma); ++ // Configure APBH DMA for NAND Reset command. ++ pChain->tx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_RESET_DEVICE_SIZE,0,NAND_LOCK,3); ++ ++ // Buffer Address Register being used to hold command. ++ pChain->tx_dma.bar = pChain->tx_reset_command_buf; ++ // Setup GPMI bus for Reset Command. Need to set CLE high, then ++ // low, then ALE toggles high and low. (Actually, in this case ++ // ALE toggling probably isn't necessary) ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_RESET_DEVICE_SIZE,0,ASSERT_CS); ++ // Nothing needs to happen to the compare. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int) NULL; ++ // Disable the ECC. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ // Setup 2nd complete DMA sequence. ++ // Wait for Ready. ++ pChain->wait_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->sense_dma); ++ pChain->wait_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ // BAR points to alternate branch if timeout occurs. ++ pChain->wait_dma.bar = (apbh_dma_gpmi1_t*)0x00; ++ // Set GPMI wait for ready. ++ pChain->wait_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++ // Now check for success. ++ pChain->sense_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->success_dma); ++ // Decrement semaphore. ++ pChain->sense_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // BAR points to alternate branch if timeout occurs. ++ pChain->sense_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to success termination code. ++ pChain->success_dma.bar = (void *) SUCCESS; ++ ++ // Next function is null. ++ pChain->timeout_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->timeout_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to timeout termination code. ++ pChain->timeout_dma.bar = (void *) 0x80508008; ++ ++} ++ ++void nand_StartDma(void *pDmaChain, unsigned int u32NandDeviceNumber) ++{ ++ unsigned int val; ++ unsigned int channel_mask = (0x1 << (NAND0_APBH_CH+u32NandDeviceNumber)); ++ ++ // soft reset dma chan, load cmd pointer and inc semaphore ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= (0xff<<16); ++ val |= (channel_mask<<16); ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ // Clear IRQ ++ writel(channel_mask, APBH_DMA_CTRL1_CLR); ++ ++#if 0 ++ // Enable IRQ ++ val = readl(APBH_DMA_CTRL1_ADDR); ++ val |= (channel_mask<<16); ++ writel(val, APBH_DMA_CTRL1_ADDR); ++#endif ++ ++ HW_APBH_CHn_NXTCMDAR_WR(NAND0_APBH_CH+u32NandDeviceNumber,(unsigned int)pDmaChain); ++ ++ // Start DMA by incrementing the semaphore. ++ BW_APBH_CHn_SEMA_INCREMENT_SEMA(NAND0_APBH_CH+u32NandDeviceNumber,1); ++ ++} ++ ++int nand_WaitDma(unsigned int u32uSecTimeout, unsigned int u32NandDeviceNumber) ++{ ++ unsigned int val; ++ int iComplete; ++ unsigned int channel_mask = (0x1 << (NAND0_APBH_CH+u32NandDeviceNumber)); ++ ++ // end of DMA chain will set IRQ. ++ do { ++ iComplete = readl(APBH_DMA_CTRL1_ADDR) & (channel_mask); ++ }while ((iComplete == 0)); // && ((readl(0x80004240) &(0xff<<16))!=0) ++ ++ // if timeout return error, else return NXTCMDAR field from last DMA command ++ if (iComplete == 0) { ++ // abort dma by resetting channel ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= (0xff<<16); ++ val |= (channel_mask<<16); ++ writel(val, APBH_DMA_CTRL_ADDR); ++ return 0x80508009; ++ } ++ else { ++ val = readl(APBH_DMA_CH4_BAR); ++ nfc_printf(NFC_DEBUG_MED, "APBH_DMA_CH4_BAR: 0x%x\n", val); ++ return val; ++ } ++} ++ ++ ++void nand_BuildReadStatusDma(NAND_dma_read_status_t* pChain, ++ unsigned int u32NandDeviceNumber, ++ void* pBuffer) ++{ ++ pChain->tx_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->rx_dma); ++ // Configure APBH DMA to push CheckStatus command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer NAND_READ_STATUS_SIZE (1) bytes to GPMI when GPMI ready. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->tx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_READ_STATUS_SIZE,0,NAND_LOCK,3); ++ // Point to byte where NAND Read Status Command is kept. ++ pChain->tx_dma.bar = &(pChain->tx_cle1); ++ // Setup GPMI bus for first part of Read Status Command. Need to ++ // set CLE high, then send Read Status command (0x70/71), then ++ // clear CLE. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_READ_STATUS_SIZE,BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++ // Set compare to NULL. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ // Disable the ECC. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ // Next dma chain is SUCCESS. ++ //pChain->rx_dma.nxt = (apbh_dma_gpmi1_t*)&APBH_SUCCESS_DMA; ++ pChain->rx_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->success_dma); ++ // Read back 1 word. ++ //pChain->rx_dma.cmd.U = NAND_DMA_RX_CMD(NAND_READ_STATUS_RESULT_SIZE, ++ // DECR_SEMAPHORE); ++ pChain->rx_dma.cmd.U = NAND_DMA_RX_NO_ECC_CMD(NAND_READ_STATUS_RESULT_SIZE, 0); ++ // Put result into pBuffer. ++ pChain->rx_dma.bar = pBuffer; ++ // Read NAND_STATUS_SIZE bytes from GPMI. ++ pChain->rx_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_RX_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, NAND_READ_STATUS_RESULT_SIZE); ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to success termination code. ++ pChain->success_dma.bar = (void *) SUCCESS; ++} ++ ++ ++// send a reset command to nand ++int nand_Reset(void) ++{ ++ int retCode; ++ unsigned int u32BusyTimeout; ++ NAND_dma_reset_device_t *pdma_reset_device; ++ NAND_dma_reset_device_t *phy_dma_reset_device; ++ ++ pdma_reset_device = (NAND_dma_reset_device_t *)RSVBUFFADDR; ++ ++ // Set GPMI DMA timeout for ~1msec in preparation for Reset. ++ u32BusyTimeout = 6; ++ writel(u32BusyTimeout<<16, GPMI_TIMEOUT1_ADDR); ++ ++ // convert from virtual address to physical address ++ HAL_VIRT_TO_PHYS_ADDRESS(pdma_reset_device, phy_dma_reset_device); ++ ++ // Load the reset command ++ // Most devices have the same reset command (0xFF) ++ pdma_reset_device->tx_reset_command_buf[0] = 0xff; ++ ++ // Build the Reset Device DMA chain. ++ nand_ResetDma(phy_dma_reset_device, 0); ++ ++ // Kick it off. ++ nand_StartDma((dma_cmd_t *)phy_dma_reset_device, 0); ++ ++ retCode = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, 0); ++ ++ if (retCode != SUCCESS){ ++ diag_printf("Reset Failed.\n"); ++ return 0x80508009; ++ } ++ ++ u32BusyTimeout = 0x132; //default ++ writel(u32BusyTimeout<<16, GPMI_TIMEOUT1_ADDR); ++ ++ return(retCode); // Success or Failure? ++} ++ ++ ++int nand_Init(ReadIDCode *pReadIDBuf) ++{ ++ int status; ++ unsigned int val; ++ unsigned int id; ++ unsigned int u32NandDeviceNumber = 0; ++ ReadIDCode *phy_ReadIDBuf; ++ unsigned int u32NumberOfECCbytes; ++ ++ nand_EnableGPMI(); ++ ++ // Now reset the bch block. ++ nand_ResetBCH(); ++ ++ // Take the APBH out of reset. ++ // APBH - disable reset, enable clock. ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= ~(0x3<<30); ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ // Reset the APBH NAND channels and clr IRQs ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= ~(0xff<<16); ++ val |= (0x10<<16); // reset nand0 channel ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ writel(0xf0, APBH_DMA_CTRL1_CLR); ++ ++ // Reset the NAND so we're in a known state. ++ // Don't return a failure because we may still be able to boot from the ++ // other nands. The reset is not a good indicator of whether ++ // a NAND is present. ++ nfc_printf(NFC_DEBUG_MED, "============NAND Reset========\n"); ++ status = nand_Reset(); ++ if(status != SUCCESS) ++ return FAIL; ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(pReadIDBuf, phy_ReadIDBuf); ++ ++ status = nand_ReadID(0, phy_ReadIDBuf); ++ diag_printf("Manuf ID: 0x%X\n", pReadIDBuf->DeviceID_Code.Device_Code.btManufacturerCode); ++ diag_printf("Device ID: 0x%X\n", pReadIDBuf->DeviceID_Code.Device_Code.btDeviceCode); ++ ++ // Configure ECC parameters ++ // BCH is used ++ val = readl(GPMI_CTRL1_ADDR); ++ val |= (1<<18); ++ writel(val, GPMI_CTRL1_ADDR); ++ ++ //set erase threshold, SLC as 0x0 ++ writel(0x0, BCH_MODE_ADDR); ++ ++ /* Configure BCH flash layout */ ++ nand_ecc_params.m_u32EccBlock0EccLevel = 8; ++ nand_ecc_params.m_u32EccBlock0Size = 0; ++ nand_ecc_params.m_u32EccBlockNSize = 512; ++ nand_ecc_params.m_u32EraseThreshold = 0; ++ nand_ecc_params.m_u32MetadataBytes = 8; ++ nand_ecc_params.m_u32NumEccBlocksPerPage = 8; ++ nand_ecc_params.u32ECCEngine = 1; ++ nand_ecc_params.u32EccType = 8; ++ ++ // Calculate ecc bytes for 1 page from zNANDEccParams, ++ // Block0 might have separate ecc level than other blocks. ++ // Formula for calculating number of parity bits for each block is (ecc_level * 13) ++ u32NumberOfECCbytes = (nand_ecc_params.m_u32EccBlock0EccLevel * 13) + // block0 ++ (nand_ecc_params.m_u32NumEccBlocksPerPage * // blockN ++ nand_ecc_params.u32EccType * 13); ++ ++ nand_ecc_params.m_u32PageSize = NF_PG_SZ + ++ nand_ecc_params.m_u32MetadataBytes + ++ u32NumberOfECCbytes; ++ ++ ++ nand_SetFlashLayout(u32NandDeviceNumber, &nand_ecc_params); ++ ++ return SUCCESS; ++} ++ ++ ++void nand_BuildReadDma(NAND_dma_read_t* pChain, ++ unsigned int u32NandDeviceNumber, ++ NAND_read_seed_t * pReadSeed) ++{ ++ // CLE1 chain size is # columns + # Rows + CLE command. ++ unsigned int iCLE1_Size = pReadSeed->uiAddressSize + 1; ++ ++ // Send the 2nd CLE. ++ pChain->tx_cle1_addr_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->tx_cle2_dma); ++ ++ // Configure APBH DMA to push Read command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer CLE1_SIZE (5) bytes to GPMI when GPMI ready. ++ // Transfer CLE1 and 4 ADDRESS bytes to GPMI_CTRL0 (see command below) ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->tx_cle1_addr_dma.cmd.U = NAND_DMA_COMMAND_CMD(iCLE1_Size, 0, NAND_LOCK, 3); ++ // Buffer Address Register holds Read Address command. ++ //pChain->tx_cle1_addr_dma.bar = pReadSeed->tx_cle1_addr_buf; ++ pChain->tx_cle1_addr_dma.bar = pReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_buf; ++ // Setup GPMI bus for first part of Read Command. Need to set CLE ++ // high, then send Read command (0x00), then clear CLE, set ALE high ++ // send # address bytes (Column then row) [Type1=2; Type2 = 4]. ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ iCLE1_Size, BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED, ASSERT_CS); ++ ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ // Setup next command - wait. ++ pChain->tx_cle2_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->wait_dma); ++ // Configure APBH DMA to push 2nd Read command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer CLE2_SIZE (1) bytes to GPMI when GPMI ready. ++ // Transfer CLE2 byte to GPMI_CTRL0 (see command below) ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ ++ pChain->tx_cle2_dma.cmd.U = NAND_DMA_COMMAND_CMD(1, 0, NAND_LOCK, 1); ++ ++ // Buffer Address Register holds tx_cle2 command ++ pChain->tx_cle2_dma.bar = pReadSeed->tx_cle2_addr_dma_buffer.tx_cle2_buf; ++ // Setup GPMI bus for second part of Read Command. Need to set CLE ++ // high, then send Read2 command (0x30), then clear CLE. ++ pChain->tx_cle2_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ 1, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ // tt_todo - does CSLock = 1 cause problem here? ++ ++ // Once we've received ready, need to receive data. ++ pChain->wait_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->sense_dma); ++ // Wait for Ready (No transfer count) ++ pChain->wait_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ // If there is an error, load Timeout DMA sequence. ++ pChain->sense_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Send commands Wait for Ready to go high. ++ pChain->wait_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++ // Now psense to see if a timeout has occurred. ++ pChain->sense_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->rx_data_dma); ++ // Wait for Ready (No transfer count) - Do not decrement semaphore. ++ pChain->sense_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // If there is an error, load Timeout DMA sequence. ++ pChain->sense_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++ // Next step is to disable the ECC. ++ pChain->rx_data_dma.nxt = (apbh_dma_gpmi1_t*) &pChain->rx_wait4done_dma; ++ ++ if (pReadSeed->bEnableHWECC) ++ { ++ // Configure APBH DMA to NOT read any bytes from the NAND into ++ // memory using GPMI. The ECC will become the Bus Master and ++ // write the read data into memory. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // NO_DMA_XFER - No DMA transfer occurs on APBH - see above. ++ // Decrement Semaphore to indicate finished. ++ pChain->rx_data_dma.cmd.U = NAND_DMA_RX_CMD_ECC(0, 0); ++ // Save Data into buffer. ++ pChain->rx_data_dma.bar = 0x00; // This field isn't used. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_compare.U = 0x00; // This field isn't used. ++ // Operate on 4 buffers (2K transfers) Select which type of Decode - 4 bit or 8 bit. ++ if( pReadSeed->zNANDEccParams.u32ECCEngine == 0 ) //ECC8 ++ { ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_CTRL_PIO(0x0F, pReadSeed->zNANDEccParams.u32EccType); ++ } ++ else ++ { ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_CTRL_PIO(pReadSeed->uiECCMask, BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT); ++ } ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.B.COUNT = pReadSeed->uiReadSize; ++ } else { ++ // ECC is disabled. Configure DMA to write directly to memory. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ pChain->rx_data_dma.cmd.U = NAND_DMA_RX_NO_ECC_CMD(pReadSeed->uiReadSize, 0); ++ // Save Data into buffer. ++ pChain->rx_data_dma.bar = (void *)(((unsigned int)pReadSeed->pDataBuffer) & 0xFFFFFFFC); // not sure if this is right... ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_compare.U = 0x00; // This field isn't used. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U = 0; // This field isn't used. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.U = 0; // This field isn't used. ++ } ++ // Setup the data buffer. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_payload.U = (((unsigned int)pReadSeed->pDataBuffer) & 0xFFFFFFFC); ++ // And the Auxiliary buffer here. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_auxiliary.U = (((unsigned int)pReadSeed->pAuxBuffer) & 0xFFFFFFFC); ++ // Setup GPMI bus for Read Sector Result. GPMI Read. ++ // Read ReadSize words (16 or 8 bit) data ++ // Note - althought the GPMI knows more than one byte/word may be ++ // sent, the APBH assumes bytes only. ++ ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ctrl0.U = NAND_DMA_RX_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, pReadSeed->uiReadSize); ++ ++ // Disable the ECC then load Success DMA sequence. ++ pChain->rx_wait4done_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->success_dma); ++ // Configure to send 3 GPMI PIO reads. ++ pChain->rx_wait4done_dma.cmd.U = NAND_DMA_DISABLE_ECC_TRANSFER; ++ // Nothing to be sent. ++ pChain->rx_wait4done_dma.bar = NULL; ++ // Disable the Chip Select and other outstanding GPMI things. ++ pChain->rx_wait4done_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_DISABLE_ECC_PIO(u32NandDeviceNumber); ++ // Ignore the compare - we need to skip over it. ++ pChain->rx_wait4done_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = 0x00; ++ // Disable the ECC Block. ++ pChain->rx_wait4done_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = ++ BF_GPMI_ECCCTRL_ENABLE_ECC(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ // Disable bch mode ++ //pChain->rx_wait4done_dma.gpmi_ctrl1.B.BCH_MODE = 0; ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*)0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to success termination code. ++ pChain->success_dma.bar = (void *)SUCCESS; ++ ++ // Next function is null. ++ pChain->timeout_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->timeout_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to timeout termination code. ++ pChain->timeout_dma.bar = (void *) 0x80508008; ++ ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++//! \brief Build the abbreviated DMA to send a NAND Read Command to the device. ++//! ++//! This function builds the DMA descriptor for a NAND Read command to the ++//! device. This function assumes the DMA has already been setup once so ++//! only the parameters that change need to be updated. ++//////////////////////////////////////////////////////////////////////////////// ++void nand_BuildQuickReadDma(NAND_dma_read_t* pChain, ++ unsigned int u32NandDeviceNumber, ++ NAND_read_seed_t * pReadSeed) ++{ ++ unsigned int uiGPMITransferSize; ++ ++ // Setup GPMI bus for first part of Read Command. Need to set CLE ++ // high, then send Read command (0x00), then clear CLE, set ALE high ++ // send # address bytes (Column then row) [Type1=3; Type2 = 4]. ++ // Only thing that needs to be set here is which NAND to talk to. ++ //pChain->tx_cle1_addr_dma.gpmi_ctrl0.B.CS = BF_GPMI_CTRL0_CS(u32NandDeviceNumber); ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.B.CS = u32NandDeviceNumber; ++ ++ // Setup GPMI bus for second part of Read Command. Need to set CLE ++ // high, then send Read2 command (0x30), then clear CLE. ++ // Only thing that needs to be set here is which NAND to talk to. ++ //pChain->tx_cle2_dma.gpmi_ctrl0.B.CS = BF_GPMI_CTRL0_CS(u32NandDeviceNumber); ++ pChain->tx_cle2_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.B.CS = u32NandDeviceNumber; ++ ++ // Only thing that needs to be set here is which NAND to talk to. ++ //pChain->wait_dma.gpmi_ctrl0.B.CS = BF_GPMI_CTRL0_CS(u32NandDeviceNumber); ++ pChain->wait_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.B.CS = u32NandDeviceNumber; ++ ++ if (pReadSeed->bEnableHWECC) ++ { ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.B.BUFFER_MASK = pReadSeed->uiECCMask; ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.B.COUNT = pReadSeed->uiReadSize; ++ } else { ++ // ECC is disabled. ++ pChain->rx_data_dma.cmd.B.XFER_COUNT = pReadSeed->uiReadSize; ++ pChain->rx_data_dma.bar = pReadSeed->pDataBuffer; ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U = 0; ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.U = 0; ++ } ++ ++ // Setup the data buffer. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_payload.U = (((unsigned int)pReadSeed->pDataBuffer) & 0xFFFFFFFC); ++ // And the Auxiliary buffer here. ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_auxiliary.U = (((unsigned int)pReadSeed->pAuxBuffer) & 0xFFFFFFFC); ++ // Setup GPMI bus for Read Sector Result. GPMI Read. ++ // Read ReadSize words (16 or 8 bit) data ++ // Note - althought the GPMI knows more than one byte/word may be ++ // sent, the APBH assumes bytes only. ++ uiGPMITransferSize = (pReadSeed->uiWordSize == BV_GPMI_CTRL0_WORD_LENGTH__8_BIT) ? ++ pReadSeed->uiReadSize : (pReadSeed->uiReadSize>>1); ++ // Change only those values that need to be changed. ++ //pChain->rx_data_dma.gpmi_ctrl0.B.CS = BF_GPMI_CTRL0_CS(u32NandDeviceNumber); ++ //pChain->rx_data_dma.gpmi_ctrl0.B.XFER_COUNT = BF_GPMI_CTRL0_XFER_COUNT(uiGPMITransferSize); ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ctrl0.B.CS = u32NandDeviceNumber; ++ pChain->rx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ctrl0.B.XFER_COUNT = uiGPMITransferSize; ++ ++ // Disable the Chip Select and other outstanding GPMI things. ++ pChain->rx_wait4done_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.B.CS = u32NandDeviceNumber; ++} ++ ++ ++void nand_InitReadDma(void * pReadDmaDescriptor, ++ unsigned int u32NumRowBytes, ++ unsigned int u32BusWidth, ++ unsigned int u32ECCSize, ++ unsigned int u32ReadCode1, ++ unsigned int u32ReadCode2) ++{ ++ unsigned int u32NumberOfECCbytes; ++ //int32_t iSectorOffset=0; ++ NAND_dma_read_t *pDmaReadDescriptor = (NAND_dma_read_t *)pReadDmaDescriptor; ++ NAND_read_seed_t *pDmaReadSeed = (NAND_read_seed_t *) &(pDmaReadDescriptor->NAND_DMA_Read_Seed); ++ NAND_read_seed_t *phy_DmaReadSeed; ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(pDmaReadSeed, phy_DmaReadSeed); ++ ++ /* for BCH */ ++ // Initialize ReadSeed ++ pDmaReadSeed->zNANDEccParams.u32EccType = u32ECCSize; ++ // Initialize mask to read from the beginning of a page including metadata ++ pDmaReadSeed->uiECCMask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE; ++ ++ // Calculate ecc bytes for 1 page from zNANDEccParams, ++ // Block0 might have separate ecc level than other blocks. ++ // Formula for calculating number of parity bits for each block is (ecc_level * 13) ++ u32NumberOfECCbytes = (pDmaReadSeed->zNANDEccParams.m_u32EccBlock0EccLevel * 13) + // block0 ++ (pDmaReadSeed->zNANDEccParams.m_u32NumEccBlocksPerPage * // blockN ++ pDmaReadSeed->zNANDEccParams.u32EccType * 13); ++ ++ // Convert the result to bytes ++ u32NumberOfECCbytes = (u32NumberOfECCbytes + (8-1)) / 8; ++ ++ nfc_printf(NFC_DEBUG_MAX, "u32NumberOfECCbytes: %d\n", u32NumberOfECCbytes); ++ ++ // Alway 2 column bytes. ++ pDmaReadSeed->uiAddressSize = MAX_COLUMNS + u32NumRowBytes; ++ ++ // Start off assuming we'll only read the data size. ++ pDmaReadSeed->uiReadSize = (NF_PG_SZ + u32NumberOfECCbytes + pDmaReadSeed->zNANDEccParams.m_u32MetadataBytes); ++ ++ // set the Word size ++ // default to 8 bit data width ++ if (u32BusWidth == 16) ++ { ++ pDmaReadSeed->uiWordSize = BV_GPMI_CTRL0_WORD_LENGTH__16_BIT; ++ } ++ else ++ { ++ pDmaReadSeed->uiWordSize = BV_GPMI_CTRL0_WORD_LENGTH__8_BIT; ++ } ++ ++ // Setup the Read Data command words. ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1 = (unsigned char)u32ReadCode1; ++ pDmaReadSeed->tx_cle2_addr_dma_buffer.tx_cle2_addr_dma.tx_cle2 = (unsigned char)u32ReadCode2; ++ ++ // Fill in the Column Address (Always 2 bytes) ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Columns[0] = (unsigned char)(0); ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Columns[1] = (unsigned char)(0); ++ ++ // Fill in the Row Address. (Can be 2 or 3 bytes) ++ // Fill in the Column Address (Always 2 bytes) ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[0] = (unsigned char)(0); ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[1] = (unsigned char)(0); ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[2] = (unsigned char)(0); ++ ++ // Buffer pointers used for DMA chain. ++ pDmaReadSeed->pDataBuffer = NULL; ++ pDmaReadSeed->pAuxBuffer = NULL; ++ ++ nand_BuildReadDma(pDmaReadDescriptor, 0, phy_DmaReadSeed); ++ ++} ++ ++ ++void nand_BuildProgramDma(NAND_dma_program_t* pChain, unsigned int u32NandDeviceNumber, ++ unsigned int u32AddressSize, unsigned int u32DataSize, ++ unsigned int u32EccSize, void* pWriteBuffer, ++ void* pAuxBuffer) ++{ ++ unsigned int u32EccDataSize = 0; ++ ++ // CLE1 chain size is # columns + # Rows + CLE command. ++ unsigned int iCLE1_Size = u32AddressSize + 1; ++ ++ nfc_printf(NFC_DEBUG_MAX, "u32AddressSize: 0x%x\n", u32AddressSize); ++ nfc_printf(NFC_DEBUG_MAX, "u32DataSize: 0x%x\n", u32DataSize); ++ nfc_printf(NFC_DEBUG_MAX, "u32EccSize: 0x%x\n", u32EccSize); ++ nfc_printf(NFC_DEBUG_MAX, "pAuxBuffer: 0x%x\n", (unsigned int)pAuxBuffer); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor1: Issue NAND write setup command ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->tx_cle1_addr_dma.nxt = (apbh_dma_gpmi1_t*) (&pChain->tx_data_dma); ++ pChain->tx_cle1_addr_dma.cmd.U = NAND_DMA_COMMAND_CMD(iCLE1_Size,0,NAND_LOCK,3)|(1<<8); ++ pChain->tx_cle1_addr_dma.bar = pChain->NandProgSeed.tx_cle1_addr_buf; ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ iCLE1_Size, BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED, ASSERT_CS); ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ // Disable the ECC. ++ pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor2: write the data payload ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->tx_data_dma.nxt = (apbh_dma_gpmi1_t*) (&pChain->tx_cle2_dma); ++ // Calculate the ECC Mask for this transaction. ++ // Auxilliary = 0x100 set to request transfer to/from the Auxiliary buffer. ++ // Buffer7 = 0x080 set to request transfer to/from buffer7. ++ // Buffer6 = 0x040 set to request transfer to/from buffer6. ++ // Buffer5 = 0x020 set to request transfer to/from buffer5. ++ // Buffer4 = 0x010 set to request transfer to/from buffer4. ++ // Buffer3 = 0x008 set to request transfer to/from buffer3. ++ // Buffer2 = 0x004 set to request transfer to/from buffer2. ++ // Buffer1 = 0x002 set to request transfer to/from buffer1. ++ // Buffer0 = 0x001 set to request transfer to/from buffer0. ++ // First calculate how many 512 byte buffers fit in here. ++ ++ // Set DMA command. ++ pChain->tx_data_dma.cmd.U = NAND_DMA_TXDATA_CMD(0, 0, 6, 1)|(1<<8); ++ ++ // Set Buffer Address Register to WriteBuffer. ++ pChain->tx_data_dma.bar = (void *)pWriteBuffer; ++ ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ctrl0.U = NAND_DMA_TXDATA_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, 0); ++ // Compare isn't used. ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_compare.U = 0; ++ ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_CTRL_PIO(0x1ff, BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT); ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.U = u32DataSize; ++ // Setup the data buffer. ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_payload.U = ((unsigned int)(pWriteBuffer) & 0xFFFFFFFC); ++ // And the Auxiliary buffer here. ++ pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_auxiliary.U = ((unsigned int)(pAuxBuffer) & 0xFFFFFFFC); ++ ++ ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor3: issue NAND write execute command ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Current Action - Send CLE2 to the NAND. ++ // Next Action - Wait for Write to complete. ++ pChain->tx_cle2_dma.nxt = (apbh_dma_gpmi1_t*) (&pChain->wait_dma); ++ pChain->tx_cle2_dma.cmd.U = NAND_DMA_COMMAND_CMD(1,0,NAND_LOCK,3)|(1<<8);; ++ pChain->tx_cle2_dma.bar = pChain->NandProgSeed.tx_cle2_buf; ++ pChain->tx_cle2_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ 1, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++ // Set compare to NULL. ++ pChain->tx_cle2_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ // Disable the ECC. ++ pChain->tx_cle2_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = 0; //NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor4: wait for ready ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->wait_dma.nxt = (apbh_dma_gpmi1_t*) (&pChain->sense_dma); ++ pChain->wait_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ pChain->wait_dma.bar = 0x00; ++ pChain->wait_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor5: psense compare ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->sense_dma.nxt = (apbh_dma_t*)(&pChain->statustx_dma); ++ pChain->sense_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ pChain->sense_dma.bar = (apbh_dma_t*)(&pChain->program_failed_dma); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor6: issue NAND status command ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->statustx_dma.nxt = (apbh_dma_gpmi1_t*)(&pChain->statusrx_dma); ++ pChain->statustx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_READ_STATUS_SIZE,0, NAND_LOCK, 3)|(1<<8);; ++ pChain->statustx_dma.bar = &pChain->NandProgSeed.u8StatusCmd; ++ pChain->statustx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_READ_STATUS_SIZE, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++ ++ // Set compare to NULL. ++ pChain->statustx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ // Disable the ECC. ++ pChain->statustx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = 0; //NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor7: read status and compare ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->statusrx_dma.nxt = (apbh_dma_gpmi2_t*)(&pChain->statbranch_dma); ++ pChain->statusrx_dma.cmd.U = NAND_DMA_RX_NO_ECC_CMD(NAND_READ_STATUS_RESULT_SIZE, 0)|(1<<8);; ++ pChain->statusrx_dma.bar = (&pChain->NandProgSeed.u16Status); ++ pChain->statusrx_dma.gpmi_ctrl0.U = NAND_DMA_RX_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, NAND_READ_STATUS_RESULT_SIZE); ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor8: psense compare ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ pChain->statbranch_dma.nxt = (apbh_dma_t*)(&pChain->success_dma); ++ pChain->statbranch_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ pChain->statbranch_dma.bar = (apbh_dma_t*)(&pChain->program_failed_dma); ++ ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Descriptor9: emit GPMI interrupt ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to TRUE termination code. ++ pChain->success_dma.bar = (void *) 0; ++ ++ //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Next function is null. ++ pChain->program_failed_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->program_failed_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to timeout termination code. ++ pChain->program_failed_dma.bar = (void *)0x80508008; ++ ++#if 0 ++ diag_printf("pChain->tx_cle1_addr_dma addr: 0x%x\n", (unsigned int)&pChain->tx_cle1_addr_dma); ++ diag_printf("pChain->tx_cle1_addr_dma.nxt: 0x%x\n", (unsigned int)pChain->tx_cle1_addr_dma.nxt ); ++ diag_printf("pChain->tx_cle1_addr_dma.cmd: 0x%x\n", (unsigned int)pChain->tx_cle1_addr_dma.cmd.U); ++ diag_printf("pChain->tx_cle1_addr_dma.bar: 0x%x\n", (unsigned int)pChain->tx_cle1_addr_dma.bar); ++ diag_printf("bar data: 0x%x\n", *(unsigned int *)pChain->tx_cle1_addr_dma.bar); ++ diag_printf("pChain->tx_cle1_addr_dma ctrl0: 0x%x\n", (unsigned int)pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U); ++ diag_printf("pChain->tx_cle1_addr_dma eccctrl: 0x%x\n", (unsigned int)pChain->tx_cle1_addr_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U); ++ ++ ++ diag_printf("pChain->tx_data_dma addr: 0x%x\n", (unsigned int)&pChain->tx_data_dma); ++ diag_printf("pChain->tx_data_dma.nxt: 0x%x\n", (unsigned int)pChain->tx_data_dma.nxt); ++ diag_printf("pChain->tx_data_dma.cmd: 0x%x\n", (unsigned int)pChain->tx_data_dma.cmd.U); ++ diag_printf("pChain->tx_data_dma.bar: 0x%x\n", (unsigned int)pChain->tx_data_dma.bar); ++ diag_printf("pChain->tx_data_dma ctrl0: 0x%x\n", (unsigned int)pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ctrl0.U); ++ diag_printf("pChain->tx_data_dma counter: 0x%x\n", (unsigned int)pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_ecccount.U); ++ diag_printf("pChain->tx_data_dma eccctrl: 0x%x\n", (unsigned int)pChain->tx_data_dma.apbh_dma_gpmi6_u.apbh_dma_gpmi6_ctrl.gpmi_eccctrl.U); ++ ++ diag_printf("pChain->tx_cle2_dma eccctrl: 0x%x\n", (unsigned int)pChain->tx_cle2_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U); ++ ++ diag_printf("pChain->statbranch_dma addr: 0x%x\n", (unsigned int)&pChain->statbranch_dma); ++ diag_printf("pChain->success_dma addr: 0x%x\n", (unsigned int)&pChain->success_dma); ++ diag_printf("pChain->program_failed_dma addr: 0x%x\n", (unsigned int)&pChain->program_failed_dma); ++ ++ diag_printf("pChain->statusrx_dma.gpmi_ctrl0: 0x%x\n", (unsigned int)pChain->statusrx_dma.gpmi_ctrl0.U); ++ diag_printf("pChain->sense_dma.bar: 0x%x\n", (unsigned int)pChain->sense_dma.bar); ++ ++#endif ++ ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++//! \brief Build the Erase Block DMA descriptor for the NAND. ++//! ++//! \fntype Non-Reentrant ++//! ++//! Build descriptor to erase the block. This is a synchronous call. ++//! ++//! \param[in] pChain - pointer to the descriptor chain that gets filled. ++//! \param[in] u32BlockAddressBytes TBD ++//! \param[in] u32ChipSelect - Chip Select - NANDs 0-3. ++//! ++//! \note branches to TRUE DMA upon completion. ++//! ++//! \todo [PUBS] Define TBD parameter(s) ++//////////////////////////////////////////////////////////////////////////////// ++void nand_BuildEraseDma( ++ NAND_dma_block_erase_t *pChain, ++ unsigned int u32NandDeviceNumber, ++ unsigned int u32BlockAddressBytes) ++{ ++ // CLE1 chain size is # Blocks + CLE command. ++ unsigned int iCLE1_Size = u32BlockAddressBytes + 1; ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ // Point to next command. ++ pChain->tx_cle1_row_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->tx_cle2_dma); ++ // Configure APBH DMA to push Erase command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer CLE1_SIZE (3) bytes to GPMI when GPMI ready. ++ // Transfer CLE1 and the row address bytes to GPMI_CTRL0. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->tx_cle1_row_dma.cmd.U = NAND_DMA_COMMAND_CMD(iCLE1_Size, 0, NAND_LOCK,3); ++ // Buffer Address Register holds Erase Block command and address. ++ pChain->tx_cle1_row_dma.bar = (pChain->NandEraseSeed.tx_cle1_block_buf); ++ // Setup GPMI bus for first part of Write Command. Need to set CLE ++ // high, then send Write command (0x80), then clear CLE, set ALE high ++ // send 4 address bytes. ++ pChain->tx_cle1_row_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ iCLE1_Size, BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED, ASSERT_CS); ++ ++ // Set compare to NULL. ++ pChain->tx_cle1_row_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int)NULL; ++ // Disable the ECC. ++ pChain->tx_cle1_row_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++// diag_printf("pChain->NandEraseSeed.tx_cle1_block_buf: 0x%x\n", *(unsigned int *)pChain->NandEraseSeed.tx_cle1_block_buf); ++// diag_printf("pChain->tx_cle1_row_dma.bar: 0x%x\n", pChain->tx_cle1_row_dma.bar); ++// diag_printf("pChain->tx_cle1_row_dma.bar content: 0x%x\n", *(unsigned int *)pChain->tx_cle1_row_dma.bar); ++ ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Setup 2nd transfer. ++ // Setup next command - wait. ++ pChain->tx_cle2_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->wait_dma); ++ // Configure APBH DMA to push 2nd Erase command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer CLE2_SIZE (1) bytes to GPMI when GPMI ready. ++ // Transfer CLE2 byte to GPMI_CTRL0 (see command below) ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->tx_cle2_dma.cmd.U = NAND_DMA_COMMAND_CMD(1, 0, NAND_LOCK,1); ++ // Buffer Address Register holds tx_cle2 command ++ pChain->tx_cle2_dma.bar = (pChain->NandEraseSeed.tx_cle2_buf); ++ // Setup GPMI bus for second part of Erase Command. Need to set CLE ++ // high, then send Erase2 command (0xD0), then clear CLE. ++ pChain->tx_cle2_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ 1, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Setup Wait for Ready descriptor. ++ // Setup success DMA pointer. ++ pChain->wait_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->sense_dma); ++ // Setup Wait for Ready (No transfer count) ++ pChain->wait_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ // If there is an error, load Timeout DMA sequence. ++ pChain->wait_dma.bar = 0x0; ++ // Wait for Ready to go high. ++ pChain->wait_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Now use Sense sequence to wait for ready. ++ pChain->sense_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->statustx_dma); ++ // Wait for Ready (No transfer count)- Decrement semaphore. ++ pChain->sense_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // If failure occurs, branch to pTimeout DMA. ++ //pChain->sense_dma.bar = (apbh_dma_gpmi1_t*)&APBH_PROGRAM_FAILED_DMA; ++ pChain->sense_dma.bar = (apbh_dma_t*)&(pChain->program_failed_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Next link will Read Status. ++ pChain->statustx_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->statusrx_dma); ++ // Configure APBH DMA to push CheckStatus command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer NAND_READ_STATUS_SIZE (1) bytes to GPMI when GPMI ready. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->statustx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_READ_STATUS_SIZE,0, NAND_LOCK,1); ++ // Point to structure where NAND Read Status Command is kept. ++ pChain->statustx_dma.bar = &(pChain->NandEraseSeed.u8StatusCmd); ++ // Setup GPMI bus for first part of Read Status Command. Need to ++ // set CLE high, then send Read Status command (0x70/71), then ++ // clear CLE. ++ pChain->statustx_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_READ_STATUS_SIZE, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Next Link determines SUCCESS or FAILURE. ++ pChain->statusrx_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->statbranch_dma); ++ // Send a Read & Compare command to the NAND. ++ pChain->statusrx_dma.cmd.U = NAND_DMA_RX_NO_ECC_CMD(NAND_READ_STATUS_RESULT_SIZE, 0); ++ // No DMA Transfer. ++ pChain->statusrx_dma.bar = &(pChain->NandEraseSeed.u16Status); ++ // GPMI commands. ++ pChain->statusrx_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_RX_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, NAND_READ_STATUS_RESULT_SIZE); ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ // Branch to appropriate result DMA. ++ //pChain->statbranch_dma.nxt = (apbh_dma_t*)&APBH_SUCCESS_DMA; ++ pChain->statbranch_dma.nxt = (apbh_dma_t*)&(pChain->success_dma); ++ // Based upon above Compare. ++ pChain->statbranch_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // Failure. ++ //pChain->sense_dma.bar = (apbh_dma_gpmi1_t*)&APBH_PROGRAM_FAILED_DMA; ++ pChain->sense_dma.bar = (apbh_dma_t*)&(pChain->program_failed_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++ //TODO: future enhancement - use compare structure. The mask will need to be ++ // computed ahead of time. ++/* ++ // Next link will Compare. ++ //pChain->tx_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->statcmp_dma); ++ pChain->statustx_dma.nxt = &pPhyDmaDescriptor[5]; ++ // Configure APBH DMA to push CheckStatus command (toggling CLE) ++ // into GPMI_CTRL. ++ // Transfer NAND_READ_STATUS_SIZE (1) bytes to GPMI when GPMI ready. ++ // Wait for end command from GPMI before next part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->statustx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_READ_STATUS_SIZE,0, NAND_LOCK); ++ // Point to structure where NAND Read Status Command is kept. ++ pChain->statustx_dma.bar = pPhyStatusCmd; ++ // Setup GPMI bus for first part of Read Status Command. Need to ++ // set CLE high, then send Read Status command (0x70/71), then ++ // clear CLE. ++ pChain->statustx_dma.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_READ_STATUS_SIZE, BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED, ASSERT_CS); ++ ++ // Next Link determines SUCCESS or FAILURE. ++ pChain->statcmp_dma.nxt = (apbh_dma_gpmi2_t*) &(pChain->statbranch_dma); ++ // Send a Read & Compare command to the NAND. ++ pChain->statcmp_dma.cmd.U = NAND_DMA_COMPARE_CMD(2); ++ // No DMA Transfer. ++ pChain->statcmp_dma.bar = &(pChain->NandEraseSeed.u16Status); ++ // GPMI commands. ++ pChain->statcmp_dma.gpmi_ctrl0.U = NAND_DMA_COMPARE_PIO(u32NandDeviceNumber, ++ NAND_READ_STATUS_SIZE); ++ // Mask and then compare. ++ pChain->statcmp_dma.gpmi_compare.U = pChain->NandEraseSeed.u32StatusMaskRef; ++ ++ // Branch to appropriate result DMA. ++ pChain->statbranch_dma.nxt = (apbh_dma_t*)&APBH_SUCCESS_DMA;; ++ // Based upon above Compare. ++ //pChain->branch_dma.cmd.U = NAND_DMA_SENSE_CMD(DECR_SEMAPHORE); ++ pChain->statbranch_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // Failure. ++ pChain->statbranch_dma.bar = (apbh_dma_t*)&APBH_PROGRAM_FAILED_DMA; ++*/ ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to success termination code. ++ pChain->success_dma.bar = (void *) SUCCESS; ++ ++ ++ // Next function is null. ++ pChain->program_failed_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->program_failed_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_WAIT4ENDCMD(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to timeout termination code. ++ pChain->program_failed_dma.bar = 0x80508008; ++ ++} ++ ++ ++int rom_nand_hal_FindEccErrors(unsigned int u32ECCEngineType, ++ unsigned int u32NumberOfCorrections) ++{ ++ int i; ++ unsigned int u32EccErrors = 0, u32Temp; ++ unsigned int uEccStatus; ++ ++ if( u32ECCEngineType == 0 ) ++ { ++ // ECC8 not supported ++ } ++ else ++ { ++ // Spin until ECC Complete Interrupt triggers. ++ nfc_printf(NFC_DEBUG_MED, "Wait until ECC Complete Interrupt triggers.\n"); ++ nfc_printf(NFC_DEBUG_MAX, "BCH_CTRL_ADDR: 0x%x\n", readl(BCH_CTRL_ADDR)); ++ while(1) ++ { ++ if(HW_BCH_CTRL_RD() & BM_BCH_CTRL_COMPLETE_IRQ) ++ { ++ nfc_printf(NFC_DEBUG_MED, "BCH completed interrupt\n"); ++ break; ++ } ++ if(HW_BCH_CTRL_RD() & BM_BCH_CTRL_BM_ERROR_IRQ) ++ { ++ nfc_printf(NFC_DEBUG_MED, "BCH: AHB Bus interface Error\n"); ++ break; ++ } ++ } ++ ++ // Now read the ECC status. ++ uEccStatus = HW_BCH_STATUS0_RD(); ++ nfc_printf(NFC_DEBUG_MAX, "BCH ECC Status0 = 0x%X\n", uEccStatus); ++ ++ if( uEccStatus != SUCCESS ) ++ { ++ //:dig later u32EccErrors = -1; //at least 1 error is corrected ++ u32EccErrors = uEccStatus; ++ } ++ ++ } ++ return u32EccErrors; ++} ++ ++int nand_CheckECCStatus(unsigned int u32NandDeviceNumber, unsigned int u32Threshold, NAND_dma_read_t* pReadDmaDescriptor) ++{ ++ int retStatus = SUCCESS; ++ bool bThresholdReached = FAIL; ++ NAND_dma_read_t *pDmaReadDescriptor = (NAND_dma_read_t *) pReadDmaDescriptor; ++ NAND_read_seed_t *pDmaReadSeed = (NAND_read_seed_t *) &(pDmaReadDescriptor->NAND_DMA_Read_Seed); ++ ++ unsigned int u32MaxCorrections = rom_nand_hal_FindEccErrors(pDmaReadSeed->zNANDEccParams.u32ECCEngine, u32Threshold); ++ ++ ++ // bch ++ if(u32MaxCorrections) ++ { ++ // u32MaxCorrections will be Status0 for BCH. ++ // get the errors from auxillary pointer at offset after metadata bytes ++ unsigned char * p8AuxPointer = (unsigned char *)pDmaReadSeed->pAuxBuffer; ++ int i=0; ++ int indexToAuxBuffer = 0; ++ unsigned int u32Temp; ++ unsigned int uNumBlks = pDmaReadSeed->zNANDEccParams.m_u32NumEccBlocksPerPage+1; ++ ++ // get the status of Blocks. Each block's status is in a byte, starts at the beginning of a new word where metadata ends ++ indexToAuxBuffer = pDmaReadSeed->zNANDEccParams.m_u32MetadataBytes + (pDmaReadSeed->zNANDEccParams.m_u32MetadataBytes % 4); ++ // now get the max ecc corrections of data blocks including metadata ecc ++ for(i=0; izNANDEccParams.m_u32EccBlock0EccLevel; ++ else ++ u32EccLevel = pDmaReadSeed->zNANDEccParams.u32EccType; ++ ++ u32Temp = p8AuxPointer[indexToAuxBuffer + i]; ++ if (u32Temp == BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE) ++ { ++ nfc_printf(NFC_DEBUG_MAX, "BCH Status ECC Sub-Block Not Recoverable %d = 0x%X\n", i, u32Temp); ++ } ++ else if(u32Temp == BV_BCH_STATUS0_STATUS_BLK0__ERASED) ++ { ++ nfc_printf(NFC_DEBUG_MAX, "BCH Status ECC Sub-Block Erased %d = 0x%X\n", i, u32Temp); ++ } ++ else ++ { ++ if( u32EccLevel == u32Temp ) ++ { ++ bThresholdReached = 1; ++ } ++ nfc_printf(NFC_DEBUG_MAX, "BCH Status Sub-Block %d = 0x%X\n", i, u32Temp); ++ } ++ } ++ } ++ ++ if (u32MaxCorrections & BM_BCH_STATUS0_ALLONES) ++ { ++ nfc_printf(NFC_DEBUG_MAX, "ECC returned ALL ONES Error\n"); ++ retStatus = 0x8050800F; ++ } ++ else if (u32MaxCorrections & BM_BCH_STATUS0_UNCORRECTABLE) ++ retStatus = 0x8050800F; ++ else if (u32MaxCorrections & BM_BCH_STATUS0_CORRECTED) ++ { ++ if(bThresholdReached) ++ { ++ retStatus = 0x80508017; ++ } ++ } ++ ++ // Clear the ECC Complete IRQ. ++ BW_BCH_CTRL_COMPLETE_IRQ(0); ++ return retStatus; ++} ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++//! \brief Read a given number of bytes from the NAND. ++//! ++//! This function will read a # of bytes from the NAND. The structure holding ++//! the address, the # of bytes to read, the commands to send, the buffer ++//! pointer, the auxillary pointer, the ECCSize, etc are part of the Read ++//! DMA descriptor. This descriptor is passed in and overwritten with ++//! the data that needs to change for this transaction. The Read DMA ++//! descriptor will have been filled in with the values that are constant ++//! for all transactions using the /e rom_nand_hal_InitReadDma function. ++//! ++//! \param[in] pReadDmaDescriptor Pointer to the Read Dma Descriptor. ++//! \param[in] u32NandDeviceNumber Physical NAND number to initialize. ++//! \param[in] u32ColumnOffset Offset in page to start at. ++//! \param[in] u32PageNum Physical page to read. ++//! \param[in] u32ReadSize Number of bytes to read from NAND. ++//! \param[in] p8PageBuf Buffer pointer where the data will be placed. ++//! \param[in] p8AuxillaryBuf Buffer pointer for auxillary buffer. ++//! ++//! \return Status of call or error. ++//! \retval 0 If no error has occurred. ++//! ++//! \post If successful, the data is in pPageBuf. The auxillary data (ECC) ++//! is appended at the end of the valid data. ++//! \note p8PageBuf must be larger than 2112 because the ECC working area ++//! is appended after the valid data. ++//! \note u32ReadSize is the total size which includes the ECC. ++//////////////////////////////////////////////////////////////////////////////// ++int nand_Read(unsigned int u32NandDeviceNumber, ++ unsigned int u32ColumnOffset, ++ unsigned int u32PageNum, ++ unsigned int u32ReadSize, ++ unsigned char *p8PageBuf, ++ unsigned char *p8AuxillaryBuf) ++{ ++ unsigned int val; ++ int status; ++ ++ NAND_dma_read_t *pDmaReadDescriptor = (NAND_dma_read_t *)RSVBUFFADDR; ++ NAND_dma_read_t *phy_DmaReadDescriptor; ++ ++ NAND_read_seed_t *pDmaReadSeed = (NAND_read_seed_t *) &(pDmaReadDescriptor->NAND_DMA_Read_Seed); ++ NAND_read_seed_t *phy_DmaReadSeed; ++ unsigned int u32Temp; ++ ++ /* Init DMA Descriptor */ ++ unsigned int u32NumRowBytes = 3; ++ ++ memset(pDmaReadDescriptor, 0x0, sizeof(NAND_dma_read_t)); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(pDmaReadDescriptor, phy_DmaReadDescriptor); ++ ++ /* Configuration parameters for BCH/ECC */ ++ pDmaReadSeed->zNANDEccParams.u32ECCEngine = nand_ecc_params.u32ECCEngine; //BCH ++ pDmaReadSeed->zNANDEccParams.m_u32NumEccBlocksPerPage = nand_ecc_params.m_u32NumEccBlocksPerPage; ++ pDmaReadSeed->zNANDEccParams.m_u32MetadataBytes = nand_ecc_params.m_u32MetadataBytes; ++ pDmaReadSeed->zNANDEccParams.m_u32EccBlock0Size = nand_ecc_params.m_u32EccBlock0Size; ++ pDmaReadSeed->zNANDEccParams.m_u32EccBlockNSize = nand_ecc_params.m_u32EccBlockNSize; ++ pDmaReadSeed->zNANDEccParams.m_u32EccBlock0EccLevel = nand_ecc_params.m_u32EccBlock0EccLevel; ++ pDmaReadSeed->zNANDEccParams.m_u32EraseThreshold = nand_ecc_params.m_u32EraseThreshold; ++ pDmaReadSeed->zNANDEccParams.u32EccType = nand_ecc_params.u32EccType; ++ pDmaReadSeed->zNANDEccParams.m_u32PageSize = nand_ecc_params.m_u32PageSize; ++ pDmaReadSeed->bEnableHWECC = 1; //enable ecc ++ ++ // Reset the APBH NAND channels and clr IRQs ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= ~(0xff<<16); ++ val |= (0x10<<16); // reset nand0 channel ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ writel(0xf0, APBH_DMA_CTRL1_CLR); ++ ++ val &= ~(0xff<<16); ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ /* BCH complete IRQ enable */ ++ //HW_BCH_CTRL_SET(1<<8); ++ ++ nand_InitReadDma(phy_DmaReadDescriptor, u32NumRowBytes, 8, pDmaReadSeed->zNANDEccParams.u32EccType, 0x00, 0x30); //ecc type: RS_Ecc_4bit ++ ++ nfc_printf(NFC_DEBUG_MED, "Read NAND - NAND Read size %d\n", u32ReadSize); ++ ++ // Fill in the Column Address (Always 2 bytes) ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Columns[0] = (unsigned char)(u32ColumnOffset & 0xFF); ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Columns[1] = (unsigned char)((u32ColumnOffset>>8) & 0xFF); ++ ++ // Fill in the Row Address. (Can be 2 or 3 bytes) ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[0] = (unsigned char)(u32PageNum & 0xFF); ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[1] = (unsigned char)((u32PageNum>>8) & 0xFF); ++ // This is always created, but the Address size determines whether ++ // this data is actually sent. ++ pDmaReadSeed->tx_cle1_addr_dma_buffer.tx_cle1_addr_Columns_Rows.tx_cle1_Columns_Rows.tx_cle1_Type2.bType2Rows[2] = (unsigned char)((u32PageNum>>16) & 0xFF); ++ ++ // Set how many bytes need to be read. ++ pDmaReadSeed->uiReadSize = u32ReadSize; ++ // Set the location where data will be read into. ++ pDmaReadSeed->pDataBuffer = p8PageBuf; ++ // Set the location where auxillary buffers will reside.. ++ pDmaReadSeed->pAuxBuffer = p8AuxillaryBuf; ++ ++ // Calculate the ECC Mask for this transaction. ++ // BCH-AuxOnly = 0x100 set to request transfer to/from the Auxiliary buffer. ++ // BCH Page = 0x1FF set to request transfer to/from the whole page buffer. ++ // Auxilliary = 0x100 set to request transfer to/from the Auxiliary buffer. ++ // Buffer7 = 0x080 set to request transfer to/from buffer7. ++ // Buffer6 = 0x040 set to request transfer to/from buffer6. ++ // Buffer5 = 0x020 set to request transfer to/from buffer5. ++ // Buffer4 = 0x010 set to request transfer to/from buffer4. ++ // Buffer3 = 0x008 set to request transfer to/from buffer3. ++ // Buffer2 = 0x004 set to request transfer to/from buffer2. ++ // Buffer1 = 0x002 set to request transfer to/from buffer1. ++ // Buffer0 = 0x001 set to request transfer to/from buffer0. ++ ++ ++ // BCH: initialize mask to read from the beginning of a page including metadata ++ pDmaReadSeed->uiECCMask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE; ++ ++ ++ nand_BuildQuickReadDma(pDmaReadDescriptor, u32NandDeviceNumber, pDmaReadSeed); ++ ++ // Clear the ECC Complete flag. ++ writel(0x1, BCH_CTRL_CLR); ++ ++ // Kick off the DMA. ++ nand_StartDma((dma_cmd_t *)phy_DmaReadDescriptor, u32NandDeviceNumber); ++ ++ nfc_printf(NFC_DEBUG_MED, "Wait for NAND read complete\n"); ++ status = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, 0); ++ if(status != SUCCESS){ ++ nfc_printf(NFC_DEBUG_MAX, "Nand Read Failed.\n"); ++ nfc_printf(NFC_DEBUG_MAX, "DGB1: 0x%x, DGB2: 0x%x\n", readl(APBH_DMA_CH4_DBG), readl(APBH_DMA_CH4_DBG2)); ++ nfc_printf(NFC_DEBUG_MAX, "GPMI Data: 0x%x\n", readl(GPMI_DATA)); ++ nfc_printf(NFC_DEBUG_MAX, "GPMI Status: 0x%x\n", readl(GPMI_STATUS)); ++ nfc_printf(NFC_DEBUG_MAX, "GPMI Debug info: 0x%x\n", readl(GPMI_DEBUG)); ++ nfc_printf(NFC_DEBUG_MAX, "GPMI TIME1: 0x%x\n", readl(GPMI_TIMEOUT1_ADDR)); ++ return FAIL; ++ } ++ else{ ++ nfc_printf(NFC_DEBUG_MED, "NAND Read Complete, Check ECC Status.\n"); ++ nand_CheckECCStatus(u32NandDeviceNumber, pDmaReadSeed->zNANDEccParams.u32EccType, phy_DmaReadDescriptor); ++ } ++ ++ ++ return(SUCCESS); ++} ++ ++ ++int nand_Erase(unsigned int u32NandDeviceNumber, ++ unsigned int BlockNum ) ++{ ++ int status; ++ unsigned int wRowAddr; ++// unsigned int wChipNum = pNANDDescriptor->wChipNumber; ++ unsigned int u32BlockAddressBytes; ++ unsigned int u32NumRowBytes = 3; ++ ++ NAND_dma_block_erase_t * pNandDmaDescriptor = (NAND_dma_block_erase_t *)RSVBUFFADDR; ++ ++ NAND_dma_block_erase_t * phy_DmaEraseDescriptor; ++ ++ memset(pNandDmaDescriptor, 0xaa, sizeof(NAND_dma_block_erase_t)); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(pNandDmaDescriptor, phy_DmaEraseDescriptor); ++ ++ // The seed can be local because the DMA portion will complete before ++ // leaving this function. ++ ++ // Use the 1st page of the block to calculate the Row address. ++ wRowAddr = BlockNum * NF_PG_PER_BLK; ++ ++ u32BlockAddressBytes = u32NumRowBytes; //pNANDDescriptor->pNANDParams->wNumRowBytes; ++ ++ // Fill in the Row Address. (Can be 2 or 3 bytes) ++ // The Address size will determine how many bytes are sent. ++ pNandDmaDescriptor->NandEraseSeed.tx_block[0] = (unsigned char)(wRowAddr & 0xFF); ++ pNandDmaDescriptor->NandEraseSeed.tx_block[1] = (unsigned char)((wRowAddr >> 8) & 0xFF); ++ pNandDmaDescriptor->NandEraseSeed.tx_block[2] = (unsigned char)((wRowAddr >> 16) & 0xFF); ++ ++ // Load Command Code for Serial Data Input ++ pNandDmaDescriptor->NandEraseSeed.tx_cle1 = 0x60; ++ ++ // Load Command Code for Page Program ++ pNandDmaDescriptor->NandEraseSeed.tx_cle2 = 0xD0; ++ ++ // Load command and mask for GetStatus portion of DMA. ++ pNandDmaDescriptor->NandEraseSeed.u8StatusCmd = 0x70; ++ ++ // Build the DMA that will program this sector. ++ nand_BuildEraseDma(phy_DmaEraseDescriptor, 0, u32BlockAddressBytes); ++ ++ nand_StartDma((dma_cmd_t *)phy_DmaEraseDescriptor, u32NandDeviceNumber); ++ ++ nfc_printf(NFC_DEBUG_MED, "Wait for NAND Erase complete\n"); ++ status = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, 0); ++ if(status != SUCCESS){ ++ diag_printf("Nand Erase Failed.\n"); ++ diag_printf("DGB1: 0x%x, DGB2: 0x%x\n", readl(APBH_DMA_CH4_DBG), readl(APBH_DMA_CH4_DBG2)); ++ diag_printf("GPMI Data: 0x%x\n", readl(GPMI_DATA)); ++ diag_printf("GPMI Status: 0x%x\n", readl(GPMI_STATUS)); ++ diag_printf("GPMI Debug info: 0x%x\n", readl(GPMI_DEBUG)); ++ diag_printf("GPMI TIME1: 0x%x\n", readl(GPMI_TIMEOUT1_ADDR)); ++ return FAIL; ++ } ++ ++ return SUCCESS; ++ ++} ++ ++ ++int nand_Write(unsigned int u32NandDeviceNumber, unsigned int u32PageNum, unsigned char *p8PageBuf, unsigned char *p8AuxillaryBuf) ++{ ++ ++ unsigned int i, val; ++ ++ int rtCode; ++ ++ unsigned int btNumRowBytes = 0x3; ++ ++ // Create a pointer to this device. ++ NAND_dma_program_t * pDmaWriteDescriptor = (NAND_dma_program_t *)RSVBUFFADDR; ++ NAND_dma_program_t * phy_DmaWriteDescriptor = 0; ++ HAL_VIRT_TO_PHYS_ADDRESS(pDmaWriteDescriptor, phy_DmaWriteDescriptor); ++ memset(pDmaWriteDescriptor, 0x0, sizeof(NAND_dma_program_t)); ++ ++ // TT_Fixme - I need to add the ECC calculation in here. ++ // Set address size to # row bytes + 2 (for column bytes). ++ pDmaWriteDescriptor->NandProgSeed.NandSizeVars.uiAddressSize = btNumRowBytes + 2; ++ ++ pDmaWriteDescriptor->NandProgSeed.NandSizeVars.uiWriteSize = NF_PG_SZ + flash_dev_info->spare_size; //u32TotalPageSize; ++ ++ // set the Word size ++ // normally use 8 bit data width ++ pDmaWriteDescriptor->NandProgSeed.NandSizeVars.uiWordSize = BV_GPMI_CTRL0_WORD_LENGTH__8_BIT; ++ ++ // Always 2 bytes and we're always going to be column 0. ++ pDmaWriteDescriptor->NandProgSeed.bType2Columns[0] = (unsigned char)0; ++ pDmaWriteDescriptor->NandProgSeed.bType2Columns[1] = (unsigned char)0; ++ ++ // Fill in the Row Address. (Can be 2 or 3 bytes) ++ for (i=0;iNandProgSeed.bType2Rows[i] = (unsigned char)((u32PageNum>>(8*i)) & 0xFF); ++ } ++ ++ // Load Command Code for Serial Data Input (0x80) ++ pDmaWriteDescriptor->NandProgSeed.tx_cle1 = 0x80; ++ ++ // Load Command Code for Page Program (0x10) ++ pDmaWriteDescriptor->NandProgSeed.tx_cle2 = 0x10; ++ ++ // Load Command Code for Read Status (0x70) ++ pDmaWriteDescriptor->NandProgSeed.u8StatusCmd = 0x70; ++ ++ nfc_printf(NFC_DEBUG_MAX, "pDmaWriteDescriptor->NandProgSeed addr: 0x%x\n", (unsigned int)&pDmaWriteDescriptor->NandProgSeed); ++ ++ // set bEnableHWECC of progseed ++ pDmaWriteDescriptor->NandProgSeed.bEnableHWECC = 1; ++ ++ // Reset the APBH NAND channels and clr IRQs ++ val = readl(APBH_DMA_CTRL_ADDR); ++ val &= ~(0xff<<16); ++ val |= (0x10<<16); // reset nand0 channel ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ writel(0xf0, APBH_DMA_CTRL1_CLR); ++ ++ val &= ~(0xff<<16); ++ writel(val, APBH_DMA_CTRL_ADDR); ++ ++ /* BCH complete IRQ enable */ ++ //HW_BCH_CTRL_SET(1<<8); ++ ++ // Clear the ECC Complete flag. ++ writel(0x1, BCH_CTRL_CLR); ++ ++ nfc_printf(NFC_DEBUG_MAX, "GPMI CTRL1: 0x%x\n", readl(GPMI_CTRL1_ADDR)); ++ /* disable write protect */ ++ writel(1<<3, GPMI_CTRL1_SET); ++ ++ /* Set for BCH */ ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.u32ECCEngine = nand_ecc_params.u32ECCEngine; //BCH ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32NumEccBlocksPerPage = nand_ecc_params.m_u32NumEccBlocksPerPage; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32MetadataBytes = nand_ecc_params.m_u32MetadataBytes; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32EccBlock0Size = nand_ecc_params.m_u32EccBlock0Size; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32EccBlockNSize = nand_ecc_params.m_u32EccBlockNSize; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32EccBlock0EccLevel = nand_ecc_params.m_u32EccBlock0EccLevel; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32EraseThreshold = nand_ecc_params.m_u32EraseThreshold; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.u32EccType = nand_ecc_params.u32EccType; ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32PageSize = nand_ecc_params.m_u32PageSize; ++ pDmaWriteDescriptor->NandProgSeed.bEnableHWECC = 1; //enable ecc ++ ++ // Build the DMA that will program this sector. ++ nand_BuildProgramDma(phy_DmaWriteDescriptor, u32NandDeviceNumber, ++ pDmaWriteDescriptor->NandProgSeed.NandSizeVars.uiAddressSize, ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.m_u32PageSize, ++ pDmaWriteDescriptor->NandProgSeed.zNANDEccParams.u32EccType, ++ p8PageBuf, p8AuxillaryBuf); ++ ++// hal_delay_us(10000); ++ ++ nfc_printf(NFC_DEBUG_MAX, "GPMI Ctrl0: 0x%x\n", readl(GPMI_CTRL0_ADDR)); ++ nfc_printf(NFC_DEBUG_MAX, "GPMI Ctrl1: 0x%x\n", readl(GPMI_CTRL1_ADDR)); ++ ++ nand_StartDma((dma_cmd_t *)phy_DmaWriteDescriptor, u32NandDeviceNumber); ++ ++ rtCode = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, u32NandDeviceNumber); ++ ++ // Check the status of the write. ++ // Check the Pass Fail bit (bit 0) and the inverted Write Protect bit (bit 7) ++ if ((pDmaWriteDescriptor->NandProgSeed.u16Status & 0x81) ^ 0x80) ++ { ++ rtCode = 0x80508009; ++ // Writes are not normally included in ++ } ++ ++ return(rtCode); // Success or failure? ++ ++} ++ ++int nand_ReadStatus(unsigned int u32NandDeviceNumber, unsigned int * pStatusResult) ++{ ++ ++ int retCode; ++ NAND_dma_read_status_t *pdma_read_status = (NAND_dma_read_status_t *)RSVBUFFADDR; ++ NAND_dma_read_status_t *phy_dma_read_status; ++ ++ memset(pdma_read_status, 0xaa, sizeof(NAND_dma_read_status_t)); ++ HAL_VIRT_TO_PHYS_ADDRESS(pdma_read_status, phy_dma_read_status); ++ ++ // Send one byte ++ pdma_read_status->uiReadStatusSize = 1; ++ ++ pdma_read_status->tx_cle1 = 0x70; ++ ++ // Receive one byte back. ++ pdma_read_status->uiReadStatusResultSize = 1; ++ ++ nand_BuildReadStatusDma(pdma_read_status, u32NandDeviceNumber, ++ &pdma_read_status->rx_Result); ++ ++ nand_StartDma((dma_cmd_t *)phy_dma_read_status, u32NandDeviceNumber); ++ ++ retCode = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, u32NandDeviceNumber); ++ ++ *pStatusResult = (unsigned int)pdma_read_status->rx_Result; ++ ++ return retCode; ++} ++ ++/* ++ ++// used by redboot/current/src/flash.c ++int mxc_nand_fis_start(void) ++{ ++ return (flash_dev_info->fis_start_addr * num_of_nand_chips); ++} ++ ++*/ ++ ++void nand_ReadID(unsigned int u32NandDeviceNumber, void* pReadIDBuffer) ++{ ++ int status; ++ NAND_dma_read_id_t *pdma_read_id, *pChain; ++ ++ pdma_read_id = (NAND_dma_read_id_t *)RSVBUFFADDR; ++ ++ // convert from virtual address to physical address ++ HAL_VIRT_TO_PHYS_ADDRESS(pdma_read_id, pChain); ++// pChain = (NAND_dma_read_id_t *)((unsigned int)&dma_read_id + 0x40000000); ++ ++ // Change the default ReadID code to what is being passed in. ++ pChain->dma_read_id_buffer.txCLE_txALE.txCLEByte = 0x90; ++ pChain->dma_read_id_buffer.txCLE_txALE.txALEByte = 0x00; ++ ++ // First we want to wait for Ready. The chip may be busy on power-up. ++ // Wait for Ready. ++ pChain->wait4rdy_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->sense_rdy_dma); ++ pChain->wait4rdy_dma.cmd.U = NAND_DMA_WAIT4RDY_CMD; ++ // BAR points to alternate branch if timeout occurs. ++ pChain->wait4rdy_dma.bar = (apbh_dma_gpmi1_t*)0x00; ++ // Set GPMI wait for ready. ++ pChain->wait4rdy_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_WAIT4RDY_PIO(u32NandDeviceNumber); ++ ++ // Now check for successful Ready. ++ pChain->sense_rdy_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->tx_dma); ++ pChain->sense_rdy_dma.cmd.U = NAND_DMA_SENSE_CMD(0); ++ // BAR points to alternate branch if timeout occurs. ++ pChain->sense_rdy_dma.bar = (apbh_dma_gpmi1_t*)&(pChain->timeout_dma); ++ // Even though PIO is unused, set it to zero for comparison purposes. ++ pChain->sense_rdy_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = 0; ++ ++ // Next command in chain will be a read. ++ pChain->tx_dma.nxt = (apbh_dma_gpmi1_t*) &(pChain->rx_dma); ++ // Configure APBH DMA to push Read ID command (toggling CLE & ALE) ++ // into GPMI_CTRL. ++ // Transfer NAND_READ_ID_SIZE to GPMI when GPMI ready. ++ // Transfer 1 word to GPMI_CTRL0 (see command below) ++ // Wait for end command from GPMI before rx part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_READ - Perform PIO word transfers then transfer ++ // from memory to peripheral for specified # of bytes. ++ pChain->tx_dma.cmd.U = NAND_DMA_COMMAND_CMD(NAND_READ_ID_SIZE, 0, NAND_LOCK,3); ++ ++ // Buffer Address Register being used to hold Read ID command. ++ pChain->tx_dma.bar = pChain->dma_read_id_buffer.tx_readid_command_buf; //FIXME - ReadID is packed inside chain. ++ // Setup GPMI bus for Read ID Command. Need to set CLE high, then ++ // low, then ALE toggles high and low. Read ID Code sent during ++ // CLE, 2nd byte (0x00) sent during ALE. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_ctrl0.U = NAND_DMA_COMMAND_PIO(u32NandDeviceNumber, ++ NAND_READ_ID_SIZE, BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED, ASSERT_CS); ++ // Nothing needs to happen to the compare. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_compare.U = (unsigned int) NULL; ++ // Disable the ECC. ++ pChain->tx_dma.apbh_dma_gpmi3_u.apbh_dma_gpmi3_ctrl.gpmi_eccctrl.U = NAND_DMA_ECC_PIO(BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE); ++ ++ // Setup 2nd complete DMA sequence. ++ // Setup to use SUCESS DMA sequence if successful. ++ pChain->rx_dma.nxt = (apbh_dma_gpmi1_t*)&(pChain->success_dma); ++ // Configure APBH DMA to push Read ID command ++ // into GPMI_CTRL. ++ // Transfer NAND_READ_ID_SIZE to GPMI when GPMI ready. ++ // Transfer 1 word to GPMI_CTRL0 (see command below) ++ // Wait for end command from GPMI before rx part of chain. ++ // Lock GPMI to this NAND during transfer. ++ // DMA_WRITE - Perform PIO word transfers then transfer to ++ // memory from peripheral for specified # of bytes. ++ pChain->rx_dma.cmd.U = NAND_DMA_RX_NO_ECC_CMD(NAND_READ_ID_RESULT_SIZE, 0); ++ // Buffer Address Register being used to hold Read ID result. ++ pChain->rx_dma.bar = pReadIDBuffer; ++ // Setup GPMI bus for Read ID Result. Read data back in. ++ // Read RESULT_SIZE bytes (8 bit) data ++ pChain->rx_dma.apbh_dma_gpmi1_u.apbh_dma_gpmi1_ctrl.gpmi_ctrl0.U = NAND_DMA_RX_PIO(u32NandDeviceNumber, ++ BV_GPMI_CTRL0_WORD_LENGTH__8_BIT, NAND_READ_ID_RESULT_SIZE); ++ ++ // Initialize the Terminator functions ++ // Next function is null. ++ pChain->success_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->success_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to success termination code. ++ pChain->success_dma.bar = (void *) 0; ++ ++ // Next function is null. ++ pChain->timeout_dma.nxt = (apbh_dma_t*) 0x0; ++ // Decrement semaphore, set IRQ, no DMA transfer. ++ pChain->timeout_dma.cmd.U = ((unsigned int) ++ (BF_APBH_CHn_CMD_IRQONCMPLT(1) | \ ++ BF_APBH_CHn_CMD_SEMAPHORE(1) | \ ++ BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER))); ++ // BAR points to timeout termination code. ++ pChain->timeout_dma.bar = (void *) 0x80508008; ++ ++ nfc_printf(NFC_DEBUG_MED, "Start DMA to get NAND ID: \n"); ++ ++ nand_StartDma((dma_cmd_t *)pChain, 0); ++ ++ status = nand_WaitDma(MAX_TRANSACTION_TIMEOUT, 0); ++ if(status != SUCCESS){ ++ diag_printf("Read ID Failed.\n"); ++ } ++ ++} ++ ++// Define table boundaries ++CYG_HAL_TABLE_BEGIN( __NAND_cmds_TAB__, NAND_cmds); ++CYG_HAL_TABLE_END( __NAND_cmds_TAB_END__, NAND_cmds); ++ ++extern struct cmd __NAND_cmds_TAB__[], __NAND_cmds_TAB_END__; ++ ++ ++void do_nand_test(int argc, char *argv[]) ++{ ++ int status; ++ int i, j; ++ unsigned int id, pageNum; ++ unsigned char *p8PageBuf, *phy_8PageBuf; ++ unsigned char * p8AuxillaryBuf, *phy_8AuxillaryBuf; ++ unsigned int StatusResult; ++ ReadIDCode *pReadIDBuf; ++ ++ diag_printf("do nand test:\n"); ++ ++ diag_printf("===========NAND Init==============\n"); ++ ++ pReadIDBuf = (ReadIDCode *)(RSVBUFFADDR+ BUFFER_SIZE); ++ memset(pReadIDBuf, 0x34, sizeof(ReadIDCode)); ++ ++ nand_Init(pReadIDBuf); ++ ++ /* Read NAND status */ ++ nand_ReadStatus(0, &StatusResult); ++ diag_printf("Return value: 0x%x\n", StatusResult); ++ ++ diag_printf("===========Write TEST==============\n"); ++ p8PageBuf = (unsigned char *)(RSVBUFFADDR + BUFFER_SIZE); ++ memset(p8PageBuf, 0x88, 0x2000); ++ p8AuxillaryBuf = (unsigned char *)(RSVBUFFADDR + BUFFER_SIZE + 0x2000); ++ memset(p8AuxillaryBuf, 0x00, 0x2000); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(p8PageBuf, phy_8PageBuf); ++ HAL_VIRT_TO_PHYS_ADDRESS(p8AuxillaryBuf, phy_8AuxillaryBuf); ++ ++ pageNum = 0x000; ++ ++ for(i=0; i < 20; i++) { ++ memset(p8PageBuf, i, 0x2000); ++ ++ status = nand_Write(0, pageNum, phy_8PageBuf, phy_8AuxillaryBuf); ++ if(status == SUCCESS){ ++ diag_printf("Write Test Passed.\n"); ++ } ++ ++ pageNum++; ++ } ++ ++ diag_printf("==========Read Test===============\n"); ++ nfc_printf(NFC_DEBUG_MED, "GPMI TIME1: 0x%x\n", readl(GPMI_TIMEOUT1_ADDR)); ++ ++ p8PageBuf = (unsigned char *)(RSVBUFFADDR+BUFFER_SIZE); ++ memset(p8PageBuf, 0x12, 0x2000); ++ ++ p8AuxillaryBuf = (unsigned char *)(RSVBUFFADDR+BUFFER_SIZE + 0x2000); ++ memset(p8AuxillaryBuf, 0x89, 0x2000); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(p8PageBuf, phy_8PageBuf); ++ HAL_VIRT_TO_PHYS_ADDRESS(p8AuxillaryBuf, phy_8AuxillaryBuf); ++ ++ pageNum = 0x001; ++ ++ for(i=0; i<20; i++) { ++ status = nand_Read(0, 0, pageNum, 2112, phy_8PageBuf, phy_8AuxillaryBuf); ++ if(status == SUCCESS){ ++ diag_printf("0x%x 0x%x 0x%x \n", *p8PageBuf, *(p8PageBuf+1), *(p8PageBuf+2)); ++ diag_printf("Read Test Passed.\n"); ++ } ++ ++ pageNum++; ++ } ++ ++ diag_printf("===========Erase TEST==============\n"); ++ nand_Erase(0, 0x600/64); //block 1 ++ ++ nand_ReadStatus(0, &StatusResult); ++ diag_printf("Return value2: 0x%x\n", StatusResult); ++} ++ ++static void nand_info(int argc, char *argv[]) ++{ ++ u32 i, j = 0; ++ ++ if (nand_flash_index == -1) { ++ diag_printf("Can't find valid NAND flash: %d\n", __LINE__); ++ return; ++ } ++ ++ diag_printf("\nType:\t\t %s\n", NF_VEND_INFO); ++ diag_printf("Total size:\t 0x%08x bytes (%d MB)\n", NF_DEV_SZ, NF_DEV_SZ/0x100000); ++ diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT); ++ diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ); ++ diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ); ++ diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK); ++} ++ ++RedBoot_cmd("nandtest", ++ "nand test", ++ "", ++ do_nand_test ++ ); ++ ++RedBoot_cmd("nandinfo", ++ "nand info", ++ "", ++ nand_info ++ ); ++ +diff -urNad redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl +--- redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl 2006-12-14 11:25:19.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl 2010-01-26 17:33:13.212956004 +0000 +@@ -230,4 +230,15 @@ + is implemented using the same command status definitions." + + } ++ ++ cdl_option CYGHWR_DEVS_FLASH_INTEL_28F256L18 { ++ display "Intel 28F256L18 flash memory support" ++ default_value 0 ++ implements CYGHWR_IO_FLASH_BLOCK_LOCKING ++ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS ++ description " ++ When this option is enabled, the Intel flash driver will be ++ able to recognize and handle the 28F256L18 ++ part in the family." ++ } + } +diff -urNad redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl +--- redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl 2006-11-17 14:03:35.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl 2010-01-26 17:33:13.222967129 +0000 +@@ -74,6 +74,8 @@ + typedef void (*call_t)(char* str, ...); + extern void diag_printf(char* str, ...); + call_t d_print = &diag_printf; ++#else ++#define d_print(fmt,args...) + #endif + + //---------------------------------------------------------------------------- +@@ -81,7 +83,9 @@ + #define FLASH_Read_ID FLASHWORD( 0x90 ) + #define FLASH_Reset FLASHWORD( 0xFF ) + #define FLASH_Program FLASHWORD( 0x40 ) +-#define FLASH_Write_Buffer FLASHWORD( 0xe8 ) ++#define FLASH_Program_M18 FLASHWORD( 0x41 ) ++#define FLASH_Write_Buffer FLASHWORD( 0xE8 ) ++#define FLASH_Write_Buffer_M18 FLASHWORD( 0xE9 ) + #define FLASH_Block_Erase FLASHWORD( 0x20 ) + #define FLASH_Confirm FLASHWORD( 0xD0 ) + #define FLASH_Resume FLASHWORD( 0xD0 ) +@@ -158,6 +162,7 @@ + //---------------------------------------------------------------------------- + // Functions that put the flash device into non-read mode must reside + // in RAM. ++#ifndef MXCFLASH_SELECT_MULTI + void flash_query(void* data) __attribute__ ((section (".2ram.flash_query"))); + int flash_erase_block(void* block, unsigned int size) + __attribute__ ((section (".2ram.flash_erase_block"))); +@@ -168,11 +173,22 @@ + __attribute__ ((section (".2ram.flash_lock_block"))); + int flash_unlock_block(void* block, int block_size, int blocks) + __attribute__ ((section (".2ram.flash_unlock_block"))); ++#else ++void norflash_query(void* data); ++int norflash_erase_block(void* block, unsigned int block_size); ++int norflash_program_buf(void* addr, void* data, int len, ++ unsigned long block_mask, int buffer_size); ++int norflash_lock_block(void* addr); ++int norflash_unlock_block(void* block, int block_size, int blocks); ++#endif //MXCFLASH_SELECT_MULTI + + //---------------------------------------------------------------------------- + // Initialize driver details +-int +-flash_hwr_init(void) ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_init(void) ++#else ++int norflash_hwr_init(void) ++#endif + { + int i; + flash_data_t id[2]; +@@ -204,8 +220,11 @@ + + //---------------------------------------------------------------------------- + // Map a hardware status to a package error +-int +-flash_hwr_map_error(int e) ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_hwr_map_error(int e) ++#else ++int norflash_hwr_map_error(int e) ++#endif + { + return e; + } +@@ -213,8 +232,11 @@ + + //---------------------------------------------------------------------------- + // See if a range of FLASH addresses overlaps currently running code +-bool +-flash_code_overlaps(void *start, void *end) ++#ifndef MXCFLASH_SELECT_MULTI ++bool flash_code_overlaps(void *start, void *end) ++#else ++bool norflash_code_overlaps(void *start, void *end) ++#endif + { + extern unsigned char _stext[], _etext[]; + +@@ -231,8 +253,11 @@ + // device(s) in series. It is assumed that any devices in series + // will be of the same type. + +-void +-flash_query(void* data) ++#ifndef MXCFLASH_SELECT_MULTI ++void flash_query(void* data) ++#else ++void norflash_query(void* data) ++#endif + { + volatile flash_data_t *ROM; + flash_data_t* id = (flash_data_t*) data; +@@ -261,8 +286,11 @@ + + //---------------------------------------------------------------------------- + // Erase Block +-int +-flash_erase_block(void* block, unsigned int block_size) ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_erase_block(void* block, unsigned int block_size) ++#else ++int norflash_erase_block(void* block, unsigned int block_size) ++#endif + { + int res = FLASH_ERR_OK; + int timeout; +@@ -294,16 +322,16 @@ + ROM[0] = FLASH_Clear_Status; + + // Erase block +- ROM[0] = FLASH_Block_Erase; ++ *b_v = FLASH_Block_Erase; + *b_v = FLASH_Confirm; + + timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT ; +- while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((stat = *b_v) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) break; + } + + // Restore ROM to "normal" mode +- ROM[0] = FLASH_Reset; ++ *b_v = FLASH_Reset; + + if (stat & FLASH_ErrorMask) { + if (!(stat & FLASH_ErrorErase)) { +@@ -340,9 +368,14 @@ + + //---------------------------------------------------------------------------- + // Program Buffer +-int +-flash_program_buf(void* addr, void* data, int len, ++ ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_program_buf(void* addr, void* data, int len, + unsigned long block_mask, int buffer_size) ++#else ++int norflash_program_buf(void* addr, void* data, int len, ++ unsigned long block_mask, int buffer_size) ++#endif + { + flash_data_t stat = 0; + int timeout; +@@ -359,6 +392,72 @@ + ROM = FLASH_P2V((unsigned long)addr & flash_dev_info->base_mask); + BA = FLASH_P2V((unsigned long)addr & ~(flash_dev_info->block_size - 1)); + ++#ifdef CYGPKG_HAL_ARM_MXC30031ADS ++ d_print("ROM=%p, BA=%p\n", ROM, BA); ++ ROM = BA; ++ ++ CYGHWR_FLASH_WRITE_ENABLE(); ++ ++ // Clear any error conditions ++ BA[0] = FLASH_Clear_Status; ++ addr_v = FLASH_P2V(addr_p); ++ d_print("%s: len=0x%x, *addr_v=0x%x, *data_p=0x%x, addr_v=%p, addr_p=%p\n", ++ __FUNCTION__, len, *addr_v, *data_p, addr_v, addr_p); ++ ++ while (len > 0) { ++ int wc = (len >= 0x400) ? 0x400: len; ++ len -= 0x400; ++ ++ wc = (wc + 1) & ~0x1; ++ ++ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT; ++ do { ++ *addr_v = FLASH_Write_Buffer_M18; ++ if (--timeout == 0) { ++ res = FLASH_ERR_DRV_TIMEOUT; ++ d_print("flash_program_buf0: addr_v=0x%x, *addr_v=0x%x, *data_p=0x%x\n", ++ addr_v, *addr_v, *data_p); ++ goto bad; ++ } ++ } while(((stat = *addr_v) & FLASH_Status_Ready) != FLASH_Status_Ready); ++ ++ *addr_v = (wc / 2) - 1; ++ //memcpy(addr_v, data_p, wc); ++ for (; wc > 0; wc -= 2) { ++ *addr_v++ = *data_p++; ++ } ++ ++ // confirm ++ *addr_p = FLASH_Confirm; ++ timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT; ++ while(((stat = *addr_p) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ if (--timeout == 0) { ++ res = FLASH_ERR_DRV_TIMEOUT; ++ d_print("flash_program_buf0: addr_v=0x%x, *addr_v=0x%x, *data_p=0x%x\n", ++ addr_v, *addr_v, *data_p); ++ goto bad; ++ } ++ } ++ if (stat & FLASH_ErrorMask) { ++ if (!(stat & FLASH_ErrorProgram)) ++ res = FLASH_ERR_HWR; // Unknown error ++ else { ++ if (stat & FLASH_ErrorLowVoltage) ++ res = FLASH_ERR_LOW_VOLTAGE; ++ else if (stat & FLASH_ErrorLocked) ++ res = FLASH_ERR_PROTECT; ++ else ++ res = FLASH_ERR_PROGRAM; ++ } ++ break; ++ } ++ addr_p[0] = FLASH_Clear_Status; ++ addr_p[0] = FLASH_Reset; ++ ++ addr_p += 512; ++ } ++#else //CYGPKG_HAL_ARM_MXC30031ADS ++ + CYGHWR_FLASH_WRITE_ENABLE(); + + // Clear any error conditions +@@ -379,7 +478,7 @@ + timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT; + + *BA = FLASH_Write_Buffer; +- while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((stat = BA[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + res = FLASH_ERR_DRV_TIMEOUT; + goto bad; +@@ -393,9 +492,9 @@ + } + *BA = FLASH_Confirm; + +- ROM[0] = FLASH_Read_Status; ++ *BA = FLASH_Read_Status; + timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT; +- while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((stat = BA[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + res = FLASH_ERR_DRV_TIMEOUT; + goto bad; +@@ -407,12 +506,14 @@ + + while (len > 0) { + addr_v = FLASH_P2V(addr_p++); +- ROM[0] = FLASH_Program; ++ *addr_v = FLASH_Program; + *addr_v = *data_p; + timeout = CYGNUM_DEVS_FLASH_INTEL_28FXXX_TIMEOUT; +- while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((stat = *addr_v) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + res = FLASH_ERR_DRV_TIMEOUT; ++ d_print("flash_program_buf0: addr_v=0x%x, *addr_v=0x%x, *data_p=0x%x\n", ++ addr_v, *addr_v, *data_p); + goto bad; + } + } +@@ -432,12 +533,14 @@ + ROM[0] = FLASH_Clear_Status; + ROM[0] = FLASH_Reset; + if (*addr_v != *data_p++) { ++ d_print("flash_program_buf: addr_v=0x%x, *addr_v=0x%x, *data_p=0x%x\n", ++ addr_v, *addr_v, *data_p); + res = FLASH_ERR_DRV_VERIFY; + break; + } + len -= sizeof( flash_data_t ); + } +- ++#endif //CYGPKG_HAL_ARM_MXC30031ADS + // Restore ROM to "normal" mode + bad: + ROM[0] = FLASH_Reset; +@@ -452,8 +555,11 @@ + #ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING + //---------------------------------------------------------------------------- + // Lock block +-int +-flash_lock_block(void* block) ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_lock_block(void* block) ++#else ++int norflash_lock_block(void* block) ++#endif + { + volatile flash_data_t *ROM; + int res = FLASH_ERR_OK; +@@ -467,9 +573,7 @@ + if (!flash_dev_info->locking) + return res; + +-#ifdef DEBUG + d_print("flash_lock_block %08x\n", block); +-#endif + + ROM = (volatile flash_data_t*)((unsigned long)block & flash_dev_info->base_mask); + +@@ -478,6 +582,7 @@ + (flash_dev_info->bootblocks[0] == ((unsigned long)block - (unsigned long)ROM))); + if (bootblock) { + len = flash_dev_info->bootblocks[len_ix++]; ++ d_print("\nboot block\n"); + } else { + len = flash_dev_info->block_size; + } +@@ -486,14 +591,16 @@ + + while (len > 0) { + b_v = FLASH_P2V(b_p); +- ++#ifdef CYGPKG_HAL_ARM_MXC30031ADS ++ ROM = b_v; ++#endif + // Clear any error conditions + ROM[0] = FLASH_Clear_Status; + + // Set lock bit + *b_v = FLASH_Set_Lock; + *b_v = FLASH_Set_Lock_Confirm; // Confirmation +- while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((state = *b_v) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + res = FLASH_ERR_DRV_TIMEOUT; + break; +@@ -525,8 +632,11 @@ + //---------------------------------------------------------------------------- + // Unlock block + +-int +-flash_unlock_block(void* block, int block_size, int blocks) ++#ifndef MXCFLASH_SELECT_MULTI ++int flash_unlock_block(void* block, int block_size, int blocks) ++#else ++int norflash_unlock_block(void* block, int block_size, int blocks) ++#endif + { + volatile flash_data_t *ROM; + int res = FLASH_ERR_OK; +@@ -653,6 +763,7 @@ + (flash_dev_info->bootblocks[0] == ((unsigned long)block - (unsigned long)ROM))); + if (bootblock) { + len = flash_dev_info->bootblocks[len_ix++]; ++ d_print("\nboot block\n"); + } else { + len = flash_dev_info->block_size; + } +@@ -664,12 +775,15 @@ + b_v = FLASH_P2V(b_p); + + // Clear any error conditions ++#ifdef CYGPKG_HAL_ARM_MXC30031ADS ++ ROM = b_v; ++#endif + ROM[0] = FLASH_Clear_Status; + + // Clear lock bit + *b_v = FLASH_Clear_Lock; + *b_v = FLASH_Clear_Lock_Confirm; // Confirmation +- while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { ++ while(((state = *b_v) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) { + res = FLASH_ERR_DRV_TIMEOUT; + break; +diff -urNad redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl +--- redboot-imx-200952~/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl 2006-12-14 11:25:19.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl 2010-01-26 17:33:13.222967129 +0000 +@@ -351,7 +351,57 @@ + }, + #endif + +-#endif // 16 bit devices ++#ifdef CYGHWR_DEVS_FLASH_INTEL_28F256L18 ++ { // 28F256L18-T ++ device_id : FLASHWORD(0x880d), ++ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 256, ++ device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ locking : true, ++ buffered_w : true, ++ bootblock : true, ++ bootblocks : {0x1fe0000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0 ++ }, ++ banked : false ++ }, ++ { // 28F256L18-B ++ device_id : FLASHWORD(0x8810), ++ block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 256, ++ device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ locking : true, ++ buffered_w : true, ++ bootblock : true, ++ bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0x008000 * CYGNUM_FLASH_INTERLEAVE, ++ 0 ++ }, ++ banked : false ++ }, ++ { // M18 ++ device_id : FLASHWORD(0x887E), ++ block_size : 0x40000 * CYGNUM_FLASH_INTERLEAVE, ++ block_count: 256, ++ device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE, ++ base_mask : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1), ++ locking : true, ++ buffered_w : true, ++ bootblock : false, ++ banked : false ++ }, + ++#endif ++ ++#endif // 16 bit devices + + #endif // CYGONCE_DEVS_FLASH_INTEL_28FXXX_PARTS_INL +diff -urNad redboot-imx-200952~/packages/devs/flash/intel/strata/current/cdl/flash_strata.cdl redboot-imx-200952/packages/devs/flash/intel/strata/current/cdl/flash_strata.cdl +--- redboot-imx-200952~/packages/devs/flash/intel/strata/current/cdl/flash_strata.cdl 2004-08-21 08:37:48.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/intel/strata/current/cdl/flash_strata.cdl 2010-01-26 17:33:13.232964755 +0000 +@@ -89,4 +89,3 @@ + } + } + } +- +diff -urNad redboot-imx-200952~/packages/devs/flash/intel/strata/current/src/strata.c redboot-imx-200952/packages/devs/flash/intel/strata/current/src/strata.c +--- redboot-imx-200952~/packages/devs/flash/intel/strata/current/src/strata.c 2004-01-26 23:59:10.000000000 +0000 ++++ redboot-imx-200952/packages/devs/flash/intel/strata/current/src/strata.c 2010-01-26 17:33:13.242958630 +0000 +@@ -107,7 +107,7 @@ + buffer_size = 0; + #else // CYGOPT_FLASH_IS_BOOTBLOCK + && (strncmp(qp->id, "QRY", 3) == 0)) { +- num_regions = _si(qp->num_regions)+1; ++ num_regions = _si(qp->num_regions)+2; + region_size = _si(qp->region_size)*256; + if (_si(qp->buffer_size)) { + buffer_size = CYGNUM_FLASH_DEVICES << _si(qp->buffer_size); +diff -urNad redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/cdl/mxc_i2c.cdl redboot-imx-200952/packages/devs/i2c/arm/mxc/current/cdl/mxc_i2c.cdl +--- redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/cdl/mxc_i2c.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/i2c/arm/mxc/current/cdl/mxc_i2c.cdl 2010-01-26 17:33:13.502955260 +0000 +@@ -0,0 +1,55 @@ ++# ==================================================================== ++# ++# mxc_i2c.cdl ++# ++# A Freescale MXC I2C package. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. ++## Copyright (C) 2004 eCosCentric, Ltd ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Kevin Zhang ++# Contributors: ++# Date: 2006-08-23 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_MXC_I2C { ++ display "I2C driver for FSL MXC-based platforms" ++ ++ compile -library=libextras.a mxc_i2c.c ++ ++ include_dir cyg/io ++} +diff -urNad redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/include/mxc_i2c.h redboot-imx-200952/packages/devs/i2c/arm/mxc/current/include/mxc_i2c.h +--- redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/include/mxc_i2c.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/i2c/arm/mxc/current/include/mxc_i2c.h 2010-01-26 17:33:13.502955260 +0000 +@@ -0,0 +1,83 @@ ++//========================================================================== ++// ++// mxc_i2c.h ++// ++// I2C support on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#ifndef __MXC_I2C_H__ ++#define __MXC_I2C_H__ ++ ++#define I2C_AR 0x0 ++#define I2C_IFDR 0x4 ++#define I2C_I2CR 0x8 ++#define I2C_I2SR 0xC ++#define I2C_I2DR 0x10 ++ ++#define I2C_I2CR_IEN (1 << 7) ++#define I2C_I2CR_IIEN (1 << 6) ++#define I2C_I2CR_MSTA (1 << 5) ++#define I2C_I2CR_MTX (1 << 4) ++#define I2C_I2CR_TXAK (1 << 3) ++#define I2C_I2CR_RSTA (1 << 2) ++ ++#define I2C_I2SR_ICF (1 << 7) ++#define I2C_I2SR_IAAS (1 << 6) ++#define I2C_I2SR_IBB (1 << 5) ++#define I2C_I2SR_IAL (1 << 4) ++#define I2C_I2SR_SRW (1 << 2) ++#define I2C_I2SR_IIF (1 << 1) ++#define I2C_I2SR_RXAK (1 << 0) ++ ++#define I2C_WRITE 0 ++#define I2C_READ 1 ++ ++struct mxc_i2c_request { ++ unsigned int dev_addr; ++ unsigned int reg_addr; ++ unsigned int reg_addr_sz; ++ unsigned char * buffer; ++ unsigned int buffer_sz; ++}; ++ ++extern unsigned int i2c_base_addr[]; ++extern unsigned int i2c_num; ++ ++extern int i2c_init(unsigned int base, unsigned int baud); ++extern int i2c_xfer(unsigned int i2c_nr, struct mxc_i2c_request *rq, int dir); ++ ++#endif /* __MXC_I2C_H__ */ +diff -urNad redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/src/mxc_i2c.c redboot-imx-200952/packages/devs/i2c/arm/mxc/current/src/mxc_i2c.c +--- redboot-imx-200952~/packages/devs/i2c/arm/mxc/current/src/mxc_i2c.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/i2c/arm/mxc/current/src/mxc_i2c.c 2010-01-26 17:33:13.512958760 +0000 +@@ -0,0 +1,479 @@ ++//========================================================================== ++// ++// mxc_i2c.c ++// ++// I2C support on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++#include ++#ifdef CYGPKG_REDBOOT ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++extern void mxc_i2c_init(unsigned int module_base); ++ ++//#define MXC_I2C_DEBUG ++#undef MXC_I2C_DEBUG ++ ++#ifdef MXC_I2C_DEBUG ++#define diag_printf1 diag_printf ++#else ++#define diag_printf1(fmt,args...) ++#endif ++ ++struct clk_div_table { ++ int reg_value; ++ int div; ++}; ++ ++static const struct clk_div_table i2c_clk_table[] = { ++ {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, ++ {0, 30}, {1, 32}, {0x24, 32}, {2, 36}, ++ {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44}, ++ {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56}, ++ {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72}, ++ {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96}, ++ {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128}, ++ {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192}, ++ {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256}, ++ {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, ++ {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, ++ {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, ++ {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, ++ {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, ++ {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, ++ {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, ++ {0, 0} ++}; ++ ++#define ERR_TX -1 ++#define ERR_RX -2 ++#define ERR_ARB_LOST -3 ++#define ERR_NO_ACK -4 ++#define ERR_XFER -5 ++#define ERR_RX_ACK -6 ++ ++static inline int wait_till_busy(unsigned int base) ++{ ++ int i = 10000; ++ ++ while(((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0) && (--i > 0)) { ++ if (readw(base + I2C_I2SR) & I2C_I2SR_IAL) { ++ diag_printf1("Error: arbitration lost!\n"); ++ return ERR_ARB_LOST; ++ } ++ } ++ ++ if (i <= 0) { ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static unsigned int g_dev_addr_width, g_dev_data_width; ++static unsigned char g_dev_value[4]; ++static unsigned int g_i2c_nr = -1; ++ ++static inline int is_bus_free(unsigned int base) ++{ ++ return ((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0); ++} ++ ++#define ASSERT_NO_ARBITRATION_LOST(stat) \ ++{ \ ++ if (stat & I2C_I2SR_IAL) { \ ++ diag_printf("Error %d: Arbitration lost\n", __LINE__); \ ++ return ERR_ARB_LOST; \ ++ } \ ++} ++ ++#define WAIT_RXAK_LOOPS 1000000 ++ ++static inline unsigned short wait_op_done(unsigned int base, int is_tx) ++{ ++ volatile unsigned short v; ++ int i = WAIT_RXAK_LOOPS; ++ ++ while ((((v = readw(base + I2C_I2SR)) & I2C_I2SR_IIF) == 0) && (--i > 0)); ++ ++ if (i <= 0) { ++ diag_printf1("I2C Error: timeout unexpected\n"); ++ return -1; ++ } ++ ++ writew(0x0, base + I2C_I2SR); ++ if (v & I2C_I2SR_IAL) { ++ diag_printf1("Error %d: Arbitration lost\n", __LINE__); ++ return ERR_ARB_LOST; ++ } ++ ++ if (is_tx) { ++ if (v & I2C_I2SR_RXAK) { ++ diag_printf1("Error %d: no ack received\n", __LINE__); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++// ++// For master TX, always expect a RXAK signal to be set! ++static int tx_byte(unsigned char *data, unsigned int base) ++{ ++ diag_printf1("%s(data=0x%02x, base=0x%x)\n", __FUNCTION__, *data, base); ++ ++ // clear both IAL and IIF bits ++ writew(0, base + I2C_I2SR); ++ ++ writew(*data, base + I2C_I2DR); ++ ++ if (wait_op_done(base, 1) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++// For master RX ++static int rx_bytes(unsigned char *data, unsigned int base, int sz) ++{ ++ unsigned short i2cr; ++ int i; ++ ++ for (i = 0; sz > 0; sz--, i++) { ++ if (wait_op_done(base, 0) != 0) ++ return -1; ++ ++ // the next two if-statements setup for the next read control register value ++ if (sz == 1) { ++ // last byte --> generate STOP ++ i2cr = readw(base + I2C_I2CR); ++ writew(i2cr & ~(I2C_I2CR_MSTA | I2C_I2CR_MTX), base + I2C_I2CR); ++ } ++ if (sz == 2) { ++ // 2nd last byte --> set TXAK bit to NOT generate ACK ++ i2cr = readw(base + I2C_I2CR); ++ writew(i2cr | I2C_I2CR_TXAK, base + I2C_I2CR); ++ } ++ ++ // read the true data ++ data[i] = readw(base + I2C_I2DR); ++ diag_printf1("OK 0x%02x\n", data[i]); ++ } ++ return 0; ++} ++ ++int i2c_xfer(unsigned int i2c_nr, struct mxc_i2c_request *rq, int dir) ++{ ++ unsigned int base, reg; ++ unsigned char i, data; ++ unsigned short i2cr; ++ int ret = 0; ++ ++ if ( rq == NULL || i2c_nr >= i2c_num) { ++ diag_printf("Invalid request or invalid i2c port number\n"); ++ return -1; ++ } ++ ++ base = i2c_base_addr[i2c_nr]; ++ if (rq->reg_addr_sz == 0 || rq->buffer_sz == 0 || rq->buffer == NULL) { ++ diag_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n", ++ rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer); ++ return -1; ++ } ++ ++ // reset and enable I2C ++ writew(0, base + I2C_I2CR); ++ ++ writew(I2C_I2CR_IEN, base + I2C_I2CR); ++ ++ /* Need wait at least 2 cycles of per_clk*/ ++ hal_delay_us(5000); ++ // Step 1: generate START signal ++ // 1.1 make sure bus is free ++ if (!is_bus_free(base)) { ++ return -1; ++ } ++ // 1.2 clear both IAL and IIF bits ++ writew(0, base + I2C_I2SR); ++ ++ // 1.3 assert START signal and also indicate TX mode ++ i2cr = I2C_I2CR_IEN | I2C_I2CR_MSTA | I2C_I2CR_MTX; ++ writew(i2cr, base + I2C_I2CR); ++ ++ // 1.4 make sure bus is busy after the START signal ++ if (wait_till_busy(base) != 0) { ++ return ERR_TX; ++ } ++ ++ // Step 2: send slave address + read/write at the LSB ++ data = (rq->dev_addr << 1) | I2C_WRITE; ++ if (tx_byte(&data, base) != 0) { ++ return -1; ++ } ++ ++ // Step 3: send I2C device register address ++ if (rq->reg_addr_sz > 4) { ++ diag_printf("Warning register address size %d should less than 4\n", ++ rq->reg_addr_sz); ++ rq->reg_addr_sz = 4; ++ } ++ reg = rq->reg_addr; ++ ++ for (i = 0; i < rq->reg_addr_sz; i++, reg>>=8) { ++ data = reg & 0xFF; ++ diag_printf1("sending I2C=0x%x device register: data=0x%x, byte %d\n", ++ base, data, i); ++ if (tx_byte(&data, base) != 0) { ++ return -1; ++ } ++ } ++ // Step 4: read/write data ++ if (dir == I2C_READ) { ++ // do repeat-start ++ i2cr = readw(base + I2C_I2CR); ++ writew(i2cr | I2C_I2CR_RSTA, base + I2C_I2CR); ++ ++ // make sure bus is busy after the repeat-start signal ++ if (wait_till_busy(base) != 0) { ++ return ERR_TX; ++ } ++ // send slave address again, but indicate read operation ++ data = (rq->dev_addr << 1) | I2C_READ; ++ if (tx_byte(&data, base) != 0) { ++ return -1; ++ } ++ ++ // change to receive mode ++ i2cr = readw(base + I2C_I2CR); ++ if (rq->buffer_sz == 1) { ++ // if only one byte to read, make sure don't send ack ++ i2cr |= I2C_I2CR_TXAK; ++ } ++ writew(i2cr & ~I2C_I2CR_MTX, base + I2C_I2CR); ++ // dummy read ++ readw(base + I2C_I2DR); ++ ++ // now reading ... ++ if (rx_bytes(rq->buffer, base, rq->buffer_sz) != 0) { ++ return -1; ++ } ++ } else { ++ // I2C_WRITE ++ for (i = 0; i < rq->buffer_sz; i++) { ++ // send device register value ++ data = rq->buffer[i]; ++ if ((ret = tx_byte(&data, base)) != 0) { ++ break; ++ } ++ } ++ // generate STOP by clearing MSTA bit ++ writew(I2C_I2CR_IEN | I2C_I2CR_MTX, base + I2C_I2CR); ++ } ++ ++ return ret; ++} ++ ++/*! ++ * Initialize and enable a i2c module -- mainly enable the I2C clock, module ++ * itself and the I2C clock prescaler. ++ * ++ * @param base base address of i2c module (also assigned for I2Cx_CLK) ++ * @param baue the desired data rate ++ * ++ * @return 0 if successful; non-zero otherwise ++ */ ++int i2c_init(unsigned int base, unsigned int baud) ++{ ++ unsigned int clock = get_main_clock(IPG_PER_CLK); ++ int div = clock / baud; ++ struct clk_div_table *p = (struct clk_div_table *)&i2c_clk_table[0]; ++ ++ mxc_i2c_init(base); ++ ++ // reset and enable I2C ++ writew(0, base + I2C_I2CR); ++ writew(I2C_I2CR_IEN, base + I2C_I2CR); ++ ++ while (p->div != 0) { ++ if (div <= p->div) ++ break; ++ p++; ++ } ++ ++ if (p->div == 0) { ++ diag_printf("Error: can't meet I2C baud rate request (%d) for 0x%x)\n", ++ baud, base); ++ return -1; ++ } ++ ++ diag_printf1("baud=%d, div=%d, reg_val=%d\n", baud, p->div, p->reg_value); ++ ++ writew(p->reg_value, base + I2C_IFDR); ++ ++ diag_printf1("requested data rate is: %d, actual rate is: %d\n", ++ baud, clock / p->div); ++ ++ return 0; ++} ++#ifdef CYGPKG_REDBOOT ++static void do_i2c(int argc, char *argv[]); ++RedBoot_cmd("i2c", ++ "i2c R/W operations as master", ++ " []]", ++ do_i2c ++ ); ++ ++ ++static void do_i2c(int argc,char *argv[]) ++{ ++ int dir = I2C_READ, i; ++ unsigned long v; ++ unsigned int dev_addr, dev_reg; ++ struct mxc_i2c_request rq; ++ ++ if (g_i2c_nr == -1) { ++ diag_printf("I2C module [%d] not initialized. Issue i2c_init first\n\n", g_i2c_nr); ++ return; ++ } ++ if (argc == 1) { ++ diag_printf("\tRead: i2c \n"); ++ diag_printf("\tWrite: i2c \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)&dev_addr, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter %d\n", __LINE__); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[2]), (unsigned long *)&dev_reg, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter %d\n", __LINE__); ++ return; ++ } ++ ++ if (argc == 4) { ++ if (!parse_num(*(&argv[3]), &v, &argv[3], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ dir = I2C_WRITE; ++ diag_printf("Writing I2C[%d] for addr 0x%x register 0x%x with value 0x%08lx\n", ++ g_i2c_nr, dev_addr, dev_reg, v); ++ for (i = 0; i < g_dev_data_width; i++) { ++ g_dev_value[i] = v >> (8 * (g_dev_data_width - i - 1)) & 0xff; ++ } ++ diag_printf1("testing reversed data: 0x%08x\n", *(unsigned int*)g_dev_value); ++ ++ } else { ++ diag_printf("Reading I2C [%d] from slave addr [0x%x] register [0x%x]\n", ++ g_i2c_nr, dev_addr, dev_reg); ++ } ++ ++ rq.dev_addr = dev_addr; ++ rq.reg_addr = dev_reg; ++ rq.reg_addr_sz = g_dev_addr_width; ++ rq.buffer = g_dev_value; ++ rq.buffer_sz = g_dev_data_width; ++ ++ if (i2c_xfer(g_i2c_nr, &rq, dir) != 0) { ++ diag_printf("Error I2C transfer 1\n\n"); ++ return; ++ } ++ ++ if (dir == I2C_READ) { ++ diag_printf("---> "); ++ for (i = 0; i < g_dev_data_width; i++) { ++ diag_printf("0x%02x ", g_dev_value[i]); ++ } ++ diag_printf("\n\n"); ++ } ++} ++ ++static void do_i2c_init(int argc, char *argv[]); ++RedBoot_cmd("i2c_init", ++ "Initialize i2c (i2c_num is 0-indexed)", ++ " ", ++ do_i2c_init ++ ); ++ ++static void do_i2c_init(int argc,char *argv[]) ++{ ++ unsigned freq; ++ ++ if (argc == 1 || argc != 5) { ++ diag_printf("\ni2c_init \n\n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)&g_i2c_nr, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ if (g_i2c_nr > i2c_num - 1) { ++ diag_printf("invalide i2c number: %d, max number is: %d\n", g_i2c_nr, i2c_num - 1); ++ return; ++ } ++ diag_printf1("i2c max number is: %d\n", i2c_num - 1); ++ ++ if (!parse_num(*(&argv[2]), (unsigned long *)&freq, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ if (!parse_num(*(&argv[3]), (unsigned long *)&g_dev_addr_width, &argv[3], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ if (!parse_num(*(&argv[4]), (unsigned long *)&g_dev_data_width, &argv[4], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ i2c_init(i2c_base_addr[g_i2c_nr], freq); ++ ++ diag_printf("initializing i2c:%d, addr-width:%d, data-width:%d\n\n", ++ g_i2c_nr, g_dev_addr_width, g_dev_data_width); ++} ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/cdl/imx_ipu.cdl redboot-imx-200952/packages/devs/ipu/arm/imx/current/cdl/imx_ipu.cdl +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/cdl/imx_ipu.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/cdl/imx_ipu.cdl 2010-01-26 17:33:13.522959634 +0000 +@@ -0,0 +1,76 @@ ++# ==================================================================== ++# ++# ipu.cdl ++# ++# A Freescale MXC-3stack ipu package. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. ++## Copyright (C) 2004 eCosCentric, Ltd ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Ray Sun ++# Contributors: ++# Date: 2009-05-20 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_IMX_IPU { ++ display "ipu driver for mxc" ++ ++ compile -library=libextras.a ipu_common.c ipu_dma.c ipu_proc.c ipu_display.c ++ ++ include_dir cyg/io ++ ++ cdl_option CYGHWR_DEVS_IPU_3_EX { ++ display "IPU version 3EX support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates the IPU version ++ is 3EX" ++ define_proc { ++ puts $::cdl_system_header "#define IMX_IPU_VER_3_EX" ++ } ++ } ++ cdl_option CYGHWR_DEVS_IPU_3_D { ++ display "IPU version 3D support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates the IPU version ++ is 3D" ++ define_proc { ++ puts $::cdl_system_header "#define IMX_IPU_VER_3_D" ++ } ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipu_common.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipu_common.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipu_common.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipu_common.h 2010-01-26 17:33:13.522959634 +0000 +@@ -0,0 +1,433 @@ ++//========================================================================== ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//===========================================================================*/ ++// ++// ipu_common.h ++// ++// common functions declaration and macro definitions for IPUv3d ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#ifndef IPU_COMMON_H_ ++#define IPU_COMMON_H_ ++ ++#include ++#include ++// System-wide configuration info ++#include ++#include ++ ++#ifdef IMX_IPU_VER_3_EX ++#include "ipuv3ex_reg_def.h" ++#endif ++ ++#ifdef IMX_IPU_VER_3_D ++#include "ipuv3d_reg_def.h" ++#endif ++ ++//#define IPU_DEBUG ++#undef IPU_DEBUG ++#ifdef IPU_DEBUG ++#define DP(fmt,args...) diag_printf(fmt, ## args) ++#else ++#define DP(fmt,args...) ++#endif ++#define ERRDP(fmt, arg...) diag_printf("[ERR] " fmt, ## arg) ++#define WARNDP(fmt, arg...) diag_printf("[WARN] " fmt, ## arg) ++#define INFODP(fmt, arg...) diag_printf("[INFO] " fmt, ## arg) ++ ++ ++#define TIMEOUT_VALUE 0x1000 ++ ++#define T_VALUE 2 ++ ++//Epson LCD command definitions ++#define DISON 0x29 ++#define DISOFF 0x28 ++#define GAMSET 0x26 ++#define SLPIN 0x10 ++#define SLPOUT 0x11 ++#define PASET 0x2b ++#define CASET 0x2a ++#define MADCTL 0x36 ++#define COLMOD 0x3a ++#define RAMWR 0x2c ++#define PTLON 0x12 ++#define PTLAR 0x30 ++#define NORON 0x13 ++ ++// DI counter definitions ++#define DI_COUNTER_BASECLK 0 ++#define DI_COUNTER_IHSYNC 1 ++#define DI_COUNTER_OHSYNC 2 ++#define DI_COUNTER_OVSYNC 3 ++#define DI_COUNTER_ALINE 4 ++#define DI_COUNTER_ACLOCK 5 ++ ++// IDMAC defines ++#define INTERLEAVED_MODE 0 ++#define NON_INTERLEAVED_MODE 1 ++ ++#define SHIFT_DISABLE 0 ++#define SHIFT_ENABLE 1 ++ ++#define GET_LSB(bit, val) (((unsigned int)(val)) & ((0x1<<(bit)) - 1)) ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++/* Display buffer starts at the end of DDR */ ++#ifndef DISPLAY_BUFFER_ADDR ++#define DISPLAY_BUFFER_ADDR (SDRAM_BASE_ADDR + CYGMEM_REGION_ram_SIZE - 0x400000) ++#endif ++ ++typedef struct { ++ unsigned int lowmask; // low mask inorder to find the correct masking in case of splitted data ++ unsigned int ID_mask; // ID mask of the current field ++ unsigned int ID_addrs; // ID address of the current channel ++ unsigned int data_high_sh; // High data shift if needed ++} idmac_bpp_STC; ++ ++typedef struct display_buffer_info ++{ ++ unsigned int startAddr; ++ unsigned int width; ++ unsigned int height; ++ int dataFormat; ++ int bpp; ++}display_buffer_info_t; ++ ++typedef struct { ++ unsigned int channel; ++ unsigned int xv; ++ unsigned int yv; ++ unsigned int xb; ++ unsigned int yb; ++ unsigned int nsb_b; ++ unsigned int cf; ++ unsigned int sx; ++ unsigned int sy; ++ unsigned int ns; ++ unsigned int sdx; ++ unsigned int sm; ++ unsigned int scc; ++ unsigned int sce; ++ unsigned int sdy; ++ unsigned int sdrx; ++ unsigned int sdry; ++ unsigned int bpp; ++ unsigned int dec_sel; ++ unsigned int dim; ++ unsigned int so; ++ unsigned int bndm; ++ unsigned int bm; ++ unsigned int rot; ++ unsigned int hf; ++ unsigned int vf; ++ unsigned int the; ++ unsigned int cap; ++ unsigned int cae; ++ unsigned int fw; ++ unsigned int fh; ++ unsigned int eba0; ++ unsigned int eba1; ++ unsigned int ilo; ++ unsigned int npb; ++ unsigned int pfs; ++ unsigned int alu; ++ unsigned int albm; ++ unsigned int id; ++ unsigned int th; ++ unsigned int sl; ++ unsigned int wid0; ++ unsigned int wid1; ++ unsigned int wid2; ++ unsigned int wid3; ++ unsigned int ofs0; ++ unsigned int ofs1; ++ unsigned int ofs2; ++ unsigned int ofs3; ++ unsigned int cre; ++ unsigned int ubo; ++ unsigned int vbo; ++ unsigned int sly; ++ unsigned int sluv; ++} ipu_channel_parameter_t; ++ ++typedef struct ipu_res_info { ++ int taskType; ++ unsigned int inAddr0; ++ unsigned int inAddr1; ++ unsigned int outAddr0; ++ unsigned int outAddr1; ++ int inWidth; ++ int inHeight; ++ int outWidth; ++ int outHeight; ++ int xSplitParts; ++ int ySplitParts; ++ int stridelineIn; ++ int stridelineOut; ++ int uOffsetIn; ++ int uOffsetOut; ++ int inDataFormat; ++ int outDataFormat; ++} ipu_res_info_t; ++ ++typedef struct ipu_rot_info { ++ int taskType; ++ unsigned int inAddr0; ++ unsigned int inAddr1; ++ unsigned int outAddr0; ++ unsigned int outAddr1; ++ int inWidth; ++ int inHeight; ++ int outWidth; ++ int outHeight; ++ int stridelineIn; ++ int stridelineOut; ++ int uOffsetIn; ++ int uOffsetOut; ++ int inDataFormat; ++ int outDataFormat; ++ int HorizFlip; ++ int VertFlip; ++ int rotation; ++} ipu_rot_info_t; ++ ++typedef struct display_device { ++ unsigned int type; ++ int width; ++ int height; ++} display_device_t; ++ ++enum icTaskType { ++ PrP_ENC_TASK = 0, ++ PrP_VF_TASK, ++ PP_TASK, ++ IC_CMB, ++ IC_CSC1, ++ IC_CSC2, ++ IC_PP, ++ IC_PRPENC, ++ IC_PRPVF, ++}; ++ ++enum colorSpace { ++ RGB = 0, ++ YCbCr, ++ RGB565, ++ RGB666, ++ RGB888, ++ RGBA8888, ++ YUV888, ++ YUVA8888, ++ GRAY, ++}; ++ ++enum dest { ++ DMA_CH0 = 0, ++ DMA_CH22, ++ DMA_CH23, ++ DMA_CH28, ++}; ++ ++enum tv_display_mode { ++ TVNTSC = 0, ++ TVPALM, ++ TVPALN, ++ TVPAL, ++ TV720P60, ++ TV720P50, ++ TV720P30, ++ TV720P25, ++ TV720P24, ++ TV1080I60, ++ TV1080I50, ++ TV1035I60, ++ TV1080P30, ++ TV1080P25, ++ TV1080P24, ++ TVNONE ++}; ++typedef struct alpha_chan_params { ++ unsigned int alphaChanBaseAddr; ++ int alphaWidth; ++ int alphaHeight; ++ int alphaStrideline; ++} alpha_chan_params_t; ++typedef struct ic_comb_params { ++ int taskType; ++ unsigned int baseAddr; ++ int width; ++ int height; ++ int alpha; ++ int inDataformat; ++ alpha_chan_params_t alphaChan; ++} ic_comb_params_t; ++ ++typedef struct ic_csc_params { ++ int taskType; ++ int inFormat; ++ int outFormat; ++} ic_csc_params_t; ++ ++typedef struct ipu_task_params { ++ int taskType; ++ int resEnable; ++ int rotEnable; ++ ipu_res_info_t resInfo; ++ ipu_rot_info_t rotInfo; ++} ipu_task_params_t; ++ ++typedef struct dp_csc_param { ++ int mode; ++ int **coeff; ++} dp_csc_param_t; ++ ++typedef struct dp_fg_param { ++ int fgEnable; ++ int opaque; ++ int offsetVert; ++ int offsetHoriz; ++ int cursorEnable; ++ int colorKeyEnable; ++ int graphicSelect; ++ int alphaMode; ++} dp_fg_param_t; ++ ++typedef struct cam_caputure_params { ++ int camMode; ++ int camRate; ++ int camInWidth; ++ int camInHeight; ++ int camOutWidth; ++ int camOutHeight; ++} cam_capture_params_t; ++ ++typedef struct dc_microcode { ++ int addr; ++ int stop; ++ char *opcode; ++ int lf; ++ int af; ++ int operand; ++ int mapping; ++ int waveform; ++ int gluelogic; ++ int sync; ++} dc_microcode_t; ++ ++typedef struct di_sync_wave_gen { ++ int runValue; ++ int runResolution; ++ int offsetValue; ++ int offsetResolution; ++ int cntAutoReload; ++ int stepRepeat; ++ int cntClrSel; ++ int cntPolarityGenEn; ++ int cntPolarityTrigSel; ++ int cntPolarityClrSel; ++ int cntUp; ++ int cntDown; ++} di_sync_wave_gen_t; ++ ++//common API functions for IPU ++void ipu_write_field(unsigned int id_addr, unsigned int id_mask, unsigned int data); ++void ipu_enable_display(void); ++void ipu_disable_display(void); ++void ipu_csi_config(int width, int height); ++ ++//dma API functions for IPU ++void ipu_idmac_params_init(ipu_channel_parameter_t * ipu_channel_params_ptr); ++void ipu_idmac_cpmem_param_update(int ch_number, int int_mode, char field_name[10], int data); ++void ipu_idmac_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params); ++void ipu_idmac_non_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params); ++void ipu_idmac_cpmem_param_set(int ch_number, unsigned int id_addr, ++ unsigned int id_mask, int sh_en, idmac_bpp_STC * idmac_bpp); ++void ipu_idmac_channel_buf_ready(int channel, int buf); ++void ipu_idmac_channel_buf_not_ready(int channel, int buf); ++void ipu_idmac_channel_mode_sel(int channel, int double_buf_en); ++void ipu_idmac_channel_enable(int channel, int enable); ++int ipu_idmac_channel_busy(int channel); ++int ipu_idmac_chan_cur_buff(int channel); ++int ipu_idamc_chan_eof_int(int channel); ++int ipu_idmac_chan_till_idle(int channel, int timeout); ++int ipu_dmfc_fifo_allocate(int channel, int fifo_size, int burst_size, int offset_addr); ++int ipu_smfc_fifo_allocate(int channel, int map, int burst_size); ++ ++//processing API functions for IPU ++void ipu_ic_enable(int ic_enable, int irt_enable); ++void ipu_ic_task_config(ipu_task_params_t task_params); ++void ipu_ic_calc_resize_coeffs(unsigned int in_size, unsigned int out_size, ++ unsigned int *resize_coeff, unsigned int *downsize_coeff); ++int ipu_ic_config_resize_rate(char *task_type, unsigned int res_vert, ++ unsigned int down_vert, unsigned int res_horiz, ++ unsigned int down_horiz); ++void ipu_ic_calc_vout_size(ipu_res_info_t * info, display_device_t disp_dev, int rotation, ++ int full_screen_enable); ++int ipu_ic_combine_config(ic_comb_params_t comb_params); ++int ipu_ic_csc_config(int csc_index, ic_csc_params_t csc_params); ++int ipu_ic_task_enable(int task_type, int task, int enable); ++void ipu_dp_csc_config(int dp, dp_csc_param_t dp_csc_params, bool srm_mode_update); ++void ipu_dp_fg_config(dp_fg_param_t foreground_params); ++void ipu_dp_fg_config(dp_fg_param_t foreground_params); ++void ipu_dc_microcode_config(dc_microcode_t microcode); ++void ipu_dc_microcode_event(int channel, char event[8], int priority, int address); ++int ipu_dc_map(int map, int format); ++int ipu_dc_display_config(int disp_port, int type, int increment, int strideline); ++int ipu_dc_write_channel_config(int dma_channel, int disp_port, int link_di_index, ++ int field_mode_enable); ++ ++//disolay API functions for IPU ++void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_wave_gen); ++void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst, ++ int pt0, int pt1, int pt2, int pt3, int pt4, int pt5, int pt6); ++void ipu_di_waveform_config(int di, int pointer, int set, int up, int down); ++int ipu_di_bsclk_gen(int di, int division, int up, int down); ++int ipu_di_screen_set(int di, int screen_height); ++int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel); ++void lcd_backlit_on(void); ++void lcd_config(void); ++ ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipuv3d_reg_def.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipuv3d_reg_def.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipuv3d_reg_def.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipuv3d_reg_def.h 2010-01-26 17:33:13.652967874 +0000 +@@ -0,0 +1,10047 @@ ++//========================================================================== ++// ++// IPUV3D_REG_DEF.h ++// ++// regs definitions of IPUv3d ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#ifndef _IPUV3D_REG_DEF_H_ ++#define _IPUV3D_REG_DEF_H_ ++ ++// part before __ means register name, while part after __ ++//means the property or bit fields of this reg. ++#define IPU_IPU_CONF__ADDR 0x1E000000 ++#define IPU_IPU_CONF__EMPTY 0x1E000000,0x00000000 ++#define IPU_IPU_CONF__FULL 0x1E000000,0xffffffff ++#define IPU_IPU_CONF__IC_DMFC_SYNC 0x1E000000,0x04000000 ++#define IPU_IPU_CONF__IC_DMFC_SEL 0x1E000000,0x02000000 ++#define IPU_IPU_CONF__IDMAC_DISABLE 0x1E000000,0x00400000 ++#define IPU_IPU_CONF__IPU_DIAGBUS_ON 0x1E000000,0x00200000 ++#define IPU_IPU_CONF__IPU_DIAGBUS_MODE 0x1E000000,0x001F0000 ++#define IPU_IPU_CONF__DMFC_EN 0x1E000000,0x00000400 ++#define IPU_IPU_CONF__DC_EN 0x1E000000,0x00000200 ++#define IPU_IPU_CONF__DI1_EN 0x1E000000,0x00000080 ++#define IPU_IPU_CONF__DI0_EN 0x1E000000,0x00000040 ++#define IPU_IPU_CONF__DP_EN 0x1E000000,0x00000020 ++#define IPU_IPU_CONF__IRT_EN 0x1E000000,0x00000008 ++#define IPU_IPU_CONF__IC_EN 0x1E000000,0x00000004 ++ ++#define IPU_IPU_INT_CTRL_1__ADDR 0x1E00003C ++#define IPU_IPU_INT_CTRL_1__EMPTY 0x1E00003C,0x00000000 ++#define IPU_IPU_INT_CTRL_1__FULL 0x1E00003C,0xffffffff ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1E00003C,0x80000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1E00003C,0x20000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1E00003C,0x10000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1E00003C,0x08000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1E00003C,0x01000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1E00003C,0x00800000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1E00003C,0x00400000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1E00003C,0x00200000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1E00003C,0x00100000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1E00003C,0x00040000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1E00003C,0x00020000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1E00003C,0x00008000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1E00003C,0x00004000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1E00003C,0x00001000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1E00003C,0x00000800 ++ ++#define IPU_IPU_INT_CTRL_2__ADDR 0x1E000040 ++#define IPU_IPU_INT_CTRL_2__EMPTY 0x1E000040,0x00000000 ++#define IPU_IPU_INT_CTRL_2__FULL 0x1E000040,0xffffffff ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1E000040,0x00100000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1E000040,0x00080000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1E000040,0x00040000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1E000040,0x00020000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1E000040,0x00010000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1E000040,0x00008000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1E000040,0x00004000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1E000040,0x00002000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1E000040,0x00001000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1E000040,0x00000800 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1E000040,0x00000400 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1E000040,0x00000200 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1E000040,0x00000100 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1E000040,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_3__ADDR 0x1E000044 ++#define IPU_IPU_INT_CTRL_3__EMPTY 0x1E000044,0x00000000 ++#define IPU_IPU_INT_CTRL_3__FULL 0x1E000044,0xffffffff ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1E000044,0x80000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1E000044,0x20000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1E000044,0x10000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1E000044,0x08000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1E000044,0x01000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1E000044,0x00800000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1E000044,0x00400000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1E000044,0x00200000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1E000044,0x00100000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1E000044,0x00040000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1E000044,0x00020000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1E000044,0x00008000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1E000044,0x00004000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1E000044,0x00001000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1E000044,0x00000800 ++ ++#define IPU_IPU_INT_CTRL_4__ADDR 0x1E000048 ++#define IPU_IPU_INT_CTRL_4__EMPTY 0x1E000048,0x00000000 ++#define IPU_IPU_INT_CTRL_4__FULL 0x1E000048,0xffffffff ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1E000048,0x00100000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1E000048,0x00080000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1E000048,0x00040000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1E000048,0x00020000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1E000048,0x00010000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1E000048,0x00008000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1E000048,0x00004000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1E000048,0x00002000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1E000048,0x00001000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1E000048,0x00000800 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1E000048,0x00000400 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1E000048,0x00000200 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1E000048,0x00000100 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1E000048,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_5__ADDR 0x1E00004C ++#define IPU_IPU_INT_CTRL_5__EMPTY 0x1E00004C,0x00000000 ++#define IPU_IPU_INT_CTRL_5__FULL 0x1E00004C,0xffffffff ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1E00004C,0x80000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1E00004C,0x20000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1E00004C,0x10000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1E00004C,0x08000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1E00004C,0x01000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1E00004C,0x00800000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1E00004C,0x00400000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1E00004C,0x00200000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1E00004C,0x00100000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1E00004C,0x00040000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1E00004C,0x00020000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1E00004C,0x00008000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1E00004C,0x00004000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1E00004C,0x00001000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1E00004C,0x00000800 ++ ++#define IPU_IPU_INT_CTRL_6__ADDR 0x1E000050 ++#define IPU_IPU_INT_CTRL_6__EMPTY 0x1E000050,0x00000000 ++#define IPU_IPU_INT_CTRL_6__FULL 0x1E000050,0xffffffff ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1E000050,0x00100000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1E000050,0x00080000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1E000050,0x00040000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1E000050,0x00020000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1E000050,0x00010000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1E000050,0x00008000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1E000050,0x00004000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1E000050,0x00002000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1E000050,0x00001000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1E000050,0x00000800 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1E000050,0x00000400 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1E000050,0x00000200 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1E000050,0x00000100 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1E000050,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_7__ADDR 0x1E000054 ++#define IPU_IPU_INT_CTRL_7__EMPTY 0x1E000054,0x00000000 ++#define IPU_IPU_INT_CTRL_7__FULL 0x1E000054,0xffffffff ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1E000054,0x80000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1E000054,0x20000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1E000054,0x10000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1E000054,0x08000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1E000054,0x01000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1E000054,0x00800000 ++ ++#define IPU_IPU_INT_CTRL_8__ADDR 0x1E000058 ++#define IPU_IPU_INT_CTRL_8__EMPTY 0x1E000058,0x00000000 ++#define IPU_IPU_INT_CTRL_8__FULL 0x1E000058,0xffffffff ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1E000058,0x00100000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1E000058,0x00080000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1E000058,0x00001000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1E000058,0x00000800 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1E000058,0x00000400 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1E000058,0x00000200 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1E000058,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_10__ADDR 0x1E000060 ++#define IPU_IPU_INT_CTRL_10__EMPTY 0x1E000060,0x00000000 ++#define IPU_IPU_INT_CTRL_10__FULL 0x1E000060,0xffffffff ++#define IPU_IPU_INT_CTRL_10__AXIR_ERR_EN 0x1E000060,0x40000000 ++#define IPU_IPU_INT_CTRL_10__AXIW_ERR_EN 0x1E000060,0x20000000 ++#define IPU_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1E000060,0x10000000 ++#define IPU_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN 0x1E000060,0x04000000 ++#define IPU_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN 0x1E000060,0x02000000 ++#define IPU_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN 0x1E000060,0x01000000 ++#define IPU_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN 0x1E000060,0x00400000 ++#define IPU_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN 0x1E000060,0x00200000 ++#define IPU_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN 0x1E000060,0x00100000 ++#define IPU_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN 0x1E000060,0x00080000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN 0x1E000060,0x00040000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN 0x1E000060,0x00020000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN 0x1E000060,0x00010000 ++ ++#define IPU_IPU_INT_CTRL_11__ADDR 0x1E000064 ++#define IPU_IPU_INT_CTRL_11__EMPTY 0x1E000064,0x00000000 ++#define IPU_IPU_INT_CTRL_11__FULL 0x1E000064,0xffffffff ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1E000064,0x00400000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1E000064,0x00200000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1E000064,0x00100000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1E000064,0x00001000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1E000064,0x00000800 ++ ++#define IPU_IPU_INT_CTRL_12__ADDR 0x1E000068 ++#define IPU_IPU_INT_CTRL_12__EMPTY 0x1E000068,0x00000000 ++#define IPU_IPU_INT_CTRL_12__FULL 0x1E000068,0xffffffff ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1E000068,0x00040000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1E000068,0x00020000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1E000068,0x00010000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1E000068,0x00008000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1E000068,0x00004000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1E000068,0x00002000 ++ ++#define IPU_IPU_INT_CTRL_13__ADDR 0x1E00006C ++#define IPU_IPU_INT_CTRL_13__EMPTY 0x1E00006C,0x00000000 ++#define IPU_IPU_INT_CTRL_13__FULL 0x1E00006C,0xffffffff ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1E00006C,0x80000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1E00006C,0x20000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1E00006C,0x10000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1E00006C,0x08000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1E00006C,0x01000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1E00006C,0x00800000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1E00006C,0x00400000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1E00006C,0x00200000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1E00006C,0x00100000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1E00006C,0x00040000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1E00006C,0x00020000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1E00006C,0x00008000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1E00006C,0x00004000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1E00006C,0x00001000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1E00006C,0x00000800 ++ ++#define IPU_IPU_INT_CTRL_14__ADDR 0x1E000070 ++#define IPU_IPU_INT_CTRL_14__EMPTY 0x1E000070,0x00000000 ++#define IPU_IPU_INT_CTRL_14__FULL 0x1E000070,0xffffffff ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1E000070,0x00100000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1E000070,0x00080000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1E000070,0x00040000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1E000070,0x00020000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1E000070,0x00010000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1E000070,0x00008000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1E000070,0x00004000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1E000070,0x00002000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1E000070,0x00001000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1E000070,0x00000800 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1E000070,0x00000400 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1E000070,0x00000200 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1E000070,0x00000100 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1E000070,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_15__ADDR 0x1E000074 ++#define IPU_IPU_INT_CTRL_15__EMPTY 0x1E000074,0x00000000 ++#define IPU_IPU_INT_CTRL_15__FULL 0x1E000074,0xffffffff ++#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN 0x1E000074,0x80000000 ++#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN 0x1E000074,0x40000000 ++#define IPU_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1E000074,0x20000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN 0x1E000074,0x10000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN 0x1E000074,0x08000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN 0x1E000074,0x04000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN 0x1E000074,0x02000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN 0x1E000074,0x01000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN 0x1E000074,0x00800000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN 0x1E000074,0x00400000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN 0x1E000074,0x00200000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN 0x1E000074,0x00100000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN 0x1E000074,0x00080000 ++#define IPU_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1E000074,0x00040000 ++#define IPU_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN 0x1E000074,0x00020000 ++#define IPU_IPU_INT_CTRL_15__DC_DP_START_EN 0x1E000074,0x00010000 ++#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN 0x1E000074,0x00008000 ++#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN 0x1E000074,0x00004000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_6_EN 0x1E000074,0x00002000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_4_EN 0x1E000074,0x00001000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_3_EN 0x1E000074,0x00000800 ++#define IPU_IPU_INT_CTRL_15__DC_FC_2_EN 0x1E000074,0x00000400 ++#define IPU_IPU_INT_CTRL_15__DC_FC_1_EN 0x1E000074,0x00000200 ++#define IPU_IPU_INT_CTRL_15__DC_FC_0_EN 0x1E000074,0x00000100 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN 0x1E000074,0x00000080 ++#define IPU_IPU_INT_CTRL_15__DP_SF_BRAKE_EN 0x1E000074,0x00000040 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_END_EN 0x1E000074,0x00000020 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_START_EN 0x1E000074,0x00000010 ++#define IPU_IPU_INT_CTRL_15__DP_SF_END_EN 0x1E000074,0x00000008 ++#define IPU_IPU_INT_CTRL_15__DP_SF_START_EN 0x1E000074,0x00000004 ++#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN 0x1E000074,0x00000002 ++#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN 0x1E000074,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_1__ADDR 0x1E000078 ++#define IPU_IPU_SDMA_EVENT_1__EMPTY 0x1E000078,0x00000000 ++#define IPU_IPU_SDMA_EVENT_1__FULL 0x1E000078,0xffffffff ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1E000078,0x80000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1E000078,0x20000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1E000078,0x10000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1E000078,0x08000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1E000078,0x01000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1E000078,0x00800000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1E000078,0x00400000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1E000078,0x00200000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1E000078,0x00100000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1E000078,0x00040000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1E000078,0x00020000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1E000078,0x00008000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1E000078,0x00004000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1E000078,0x00001000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1E000078,0x00000800 ++ ++#define IPU_IPU_SDMA_EVENT_2__ADDR 0x1E00007C ++#define IPU_IPU_SDMA_EVENT_2__EMPTY 0x1E00007C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_2__FULL 0x1E00007C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1E00007C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1E00007C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1E00007C,0x00040000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1E00007C,0x00020000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1E00007C,0x00010000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1E00007C,0x00008000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1E00007C,0x00004000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1E00007C,0x00002000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1E00007C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1E00007C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1E00007C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1E00007C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1E00007C,0x00000100 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1E00007C,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_3__ADDR 0x1E000080 ++#define IPU_IPU_SDMA_EVENT_3__EMPTY 0x1E000080,0x00000000 ++#define IPU_IPU_SDMA_EVENT_3__FULL 0x1E000080,0xffffffff ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1E000080,0x80000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1E000080,0x20000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1E000080,0x10000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1E000080,0x08000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1E000080,0x01000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1E000080,0x00800000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1E000080,0x00400000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1E000080,0x00200000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1E000080,0x00100000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1E000080,0x00040000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1E000080,0x00020000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1E000080,0x00008000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1E000080,0x00004000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1E000080,0x00001000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1E000080,0x00000800 ++ ++#define IPU_IPU_SDMA_EVENT_4__ADDR 0x1E000084 ++#define IPU_IPU_SDMA_EVENT_4__EMPTY 0x1E000084,0x00000000 ++#define IPU_IPU_SDMA_EVENT_4__FULL 0x1E000084,0xffffffff ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1E000084,0x00100000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1E000084,0x00080000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1E000084,0x00040000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1E000084,0x00020000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1E000084,0x00010000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1E000084,0x00008000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1E000084,0x00004000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1E000084,0x00002000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1E000084,0x00001000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1E000084,0x00000800 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1E000084,0x00000400 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1E000084,0x00000200 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1E000084,0x00000100 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1E000084,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_7__ADDR 0x1E000088 ++#define IPU_IPU_SDMA_EVENT_7__EMPTY 0x1E000088,0x00000000 ++#define IPU_IPU_SDMA_EVENT_7__FULL 0x1E000088,0xffffffff ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1E000088,0x80000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1E000088,0x20000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1E000088,0x10000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1E000088,0x08000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1E000088,0x01000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1E000088,0x00800000 ++ ++#define IPU_IPU_SDMA_EVENT_8__ADDR 0x1E00008C ++#define IPU_IPU_SDMA_EVENT_8__EMPTY 0x1E00008C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_8__FULL 0x1E00008C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1E00008C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1E00008C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1E00008C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1E00008C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1E00008C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1E00008C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1E00008C,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_11__ADDR 0x1E000090 ++#define IPU_IPU_SDMA_EVENT_11__EMPTY 0x1E000090,0x00000000 ++#define IPU_IPU_SDMA_EVENT_11__FULL 0x1E000090,0xffffffff ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1E000090,0x00400000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1E000090,0x00200000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1E000090,0x00100000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1E000090,0x00001000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1E000090,0x00000800 ++ ++#define IPU_IPU_SDMA_EVENT_12__ADDR 0x1E000094 ++#define IPU_IPU_SDMA_EVENT_12__EMPTY 0x1E000094,0x00000000 ++#define IPU_IPU_SDMA_EVENT_12__FULL 0x1E000094,0xffffffff ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1E000094,0x00040000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1E000094,0x00020000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1E000094,0x00010000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1E000094,0x00008000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1E000094,0x00004000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1E000094,0x00002000 ++ ++#define IPU_IPU_SDMA_EVENT_13__ADDR 0x1E000098 ++#define IPU_IPU_SDMA_EVENT_13__EMPTY 0x1E000098,0x00000000 ++#define IPU_IPU_SDMA_EVENT_13__FULL 0x1E000098,0xffffffff ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1E000098,0x80000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1E000098,0x20000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1E000098,0x10000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1E000098,0x08000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1E000098,0x01000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1E000098,0x00800000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1E000098,0x00400000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1E000098,0x00200000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1E000098,0x00100000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1E000098,0x00040000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1E000098,0x00020000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1E000098,0x00008000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1E000098,0x00004000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1E000098,0x00001000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1E000098,0x00000800 ++ ++#define IPU_IPU_SDMA_EVENT_14__ADDR 0x1E00009C ++#define IPU_IPU_SDMA_EVENT_14__EMPTY 0x1E00009C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_14__FULL 0x1E00009C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1E00009C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1E00009C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1E00009C,0x00040000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1E00009C,0x00020000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1E00009C,0x00010000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1E00009C,0x00008000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1E00009C,0x00004000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1E00009C,0x00002000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1E00009C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1E00009C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1E00009C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1E00009C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1E00009C,0x00000100 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1E00009C,0x00000002 ++ ++#define IPU_IPU_SRM_PRI2__ADDR 0x1E0000A4 ++#define IPU_IPU_SRM_PRI2__EMPTY 0x1E0000A4,0x00000000 ++#define IPU_IPU_SRM_PRI2__FULL 0x1E0000A4,0xffffffff ++#define IPU_IPU_SRM_PRI2__DI1_SRM_MODE 0x1E0000A4,0x18000000 ++#define IPU_IPU_SRM_PRI2__DI1_SRM_PRI 0x1E0000A4,0x07000000 ++#define IPU_IPU_SRM_PRI2__DI0_SRM_MODE 0x1E0000A4,0x00180000 ++#define IPU_IPU_SRM_PRI2__DI0_SRM_PRI 0x1E0000A4,0x00070000 ++#define IPU_IPU_SRM_PRI2__DC_6_SRM_MODE 0x1E0000A4,0x0000C000 ++#define IPU_IPU_SRM_PRI2__DC_2_SRM_MODE 0x1E0000A4,0x00003000 ++#define IPU_IPU_SRM_PRI2__DC_SRM_PRI 0x1E0000A4,0x00000E00 ++#define IPU_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1E0000A4,0x00000180 ++#define IPU_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1E0000A4,0x00000060 ++#define IPU_IPU_SRM_PRI2__DP_S_SRM_MODE 0x1E0000A4,0x00000018 ++#define IPU_IPU_SRM_PRI2__DP_SRM_PRI 0x1E0000A4,0x00000007 ++ ++#define IPU_IPU_FS_PROC_FLOW1__ADDR 0x1E0000A8 ++#define IPU_IPU_FS_PROC_FLOW1__EMPTY 0x1E0000A8,0x00000000 ++#define IPU_IPU_FS_PROC_FLOW1__FULL 0x1E0000A8,0xffffffff ++#define IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID 0x1E0000A8,0x80000000 ++#define IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID 0x1E0000A8,0x40000000 ++#define IPU_IPU_FS_PROC_FLOW1__PRP_SRC_SEL 0x1E0000A8,0x0F000000 ++#define IPU_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL 0x1E0000A8,0x000F0000 ++#define IPU_IPU_FS_PROC_FLOW1__PP_SRC_SEL 0x1E0000A8,0x0000F000 ++#define IPU_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL 0x1E0000A8,0x00000F00 ++#define IPU_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1E0000A8,0x0000000F ++ ++#define IPU_IPU_FS_PROC_FLOW2__ADDR 0x1E0000AC ++#define IPU_IPU_FS_PROC_FLOW2__EMPTY 0x1E0000AC,0x00000000 ++#define IPU_IPU_FS_PROC_FLOW2__FULL 0x1E0000AC,0xffffffff ++#define IPU_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1E0000AC,0x00F00000 ++#define IPU_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL 0x1E0000AC,0x000F0000 ++#define IPU_IPU_FS_PROC_FLOW2__PP_DEST_SEL 0x1E0000AC,0x0000F000 ++#define IPU_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL 0x1E0000AC,0x00000F00 ++#define IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL 0x1E0000AC,0x000000F0 ++#define IPU_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL 0x1E0000AC,0x0000000F ++ ++#define IPU_IPU_FS_DISP_FLOW1__ADDR 0x1E0000B4 ++#define IPU_IPU_FS_DISP_FLOW1__EMPTY 0x1E0000B4,0x00000000 ++#define IPU_IPU_FS_DISP_FLOW1__FULL 0x1E0000B4,0xffffffff ++#define IPU_IPU_FS_DISP_FLOW1__DC1_SRC_SEL 0x1E0000B4,0x00F00000 ++#define IPU_IPU_FS_DISP_FLOW1__DC2_SRC_SEL 0x1E0000B4,0x000F0000 ++#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1E0000B4,0x0000F000 ++#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1E0000B4,0x00000F00 ++#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL 0x1E0000B4,0x000000F0 ++#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL 0x1E0000B4,0x0000000F ++ ++#define IPU_IPU_FS_DISP_FLOW2__ADDR 0x1E0000B8 ++#define IPU_IPU_FS_DISP_FLOW2__EMPTY 0x1E0000B8,0x00000000 ++#define IPU_IPU_FS_DISP_FLOW2__FULL 0x1E0000B8,0xffffffff ++#define IPU_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL 0x1E0000B8,0x000F0000 ++#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1E0000B8,0x000000F0 ++#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1E0000B8,0x0000000F ++ ++#define IPU_IPU_DISP_GEN__ADDR 0x1E0000C4 ++#define IPU_IPU_DISP_GEN__EMPTY 0x1E0000C4,0x00000000 ++#define IPU_IPU_DISP_GEN__FULL 0x1E0000C4,0xffffffff ++#define IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE 0x1E0000C4,0x02000000 ++#define IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE 0x1E0000C4,0x01000000 ++#define IPU_IPU_DISP_GEN__MCU_MAX_BURST_STOP 0x1E0000C4,0x00400000 ++#define IPU_IPU_DISP_GEN__MCU_T 0x1E0000C4,0x003C0000 ++#define IPU_IPU_DISP_GEN__MCU_DI_ID_9 0x1E0000C4,0x00020000 ++#define IPU_IPU_DISP_GEN__MCU_DI_ID_8 0x1E0000C4,0x00010000 ++#define IPU_IPU_DISP_GEN__DP_PIPE_CLR 0x1E0000C4,0x00000040 ++#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC1 0x1E0000C4,0x00000020 ++#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC0 0x1E0000C4,0x00000010 ++#define IPU_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1E0000C4,0x00000008 ++#define IPU_IPU_DISP_GEN__DC2_DOUBLE_FLOW 0x1E0000C4,0x00000004 ++#define IPU_IPU_DISP_GEN__DI1_DUAL_MODE 0x1E0000C4,0x00000002 ++#define IPU_IPU_DISP_GEN__DI0_DUAL_MODE 0x1E0000C4,0x00000001 ++ ++#define IPU_IPU_DISP_ALT1__ADDR 0x1E0000C8 ++#define IPU_IPU_DISP_ALT1__EMPTY 0x1E0000C8,0x00000000 ++#define IPU_IPU_DISP_ALT1__FULL 0x1E0000C8,0xffffffff ++#define IPU_IPU_DISP_ALT1__SEL_ALT_0 0x1E0000C8,0xF0000000 ++#define IPU_IPU_DISP_ALT1__STEP_REPEAT_ALT_0 0x1E0000C8,0x0FFF0000 ++#define IPU_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1E0000C8,0x00008000 ++#define IPU_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0 0x1E0000C8,0x00007000 ++#define IPU_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0 0x1E0000C8,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT2__ADDR 0x1E0000CC ++#define IPU_IPU_DISP_ALT2__EMPTY 0x1E0000CC,0x00000000 ++#define IPU_IPU_DISP_ALT2__FULL 0x1E0000CC,0xffffffff ++#define IPU_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0 0x1E0000CC,0x00070000 ++#define IPU_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1E0000CC,0x00007000 ++#define IPU_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0 0x1E0000CC,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT3__ADDR 0x1E0000D0 ++#define IPU_IPU_DISP_ALT3__EMPTY 0x1E0000D0,0x00000000 ++#define IPU_IPU_DISP_ALT3__FULL 0x1E0000D0,0xffffffff ++#define IPU_IPU_DISP_ALT3__SEL_ALT_1 0x1E0000D0,0xF0000000 ++#define IPU_IPU_DISP_ALT3__STEP_REPEAT_ALT_1 0x1E0000D0,0x0FFF0000 ++#define IPU_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1E0000D0,0x00008000 ++#define IPU_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1 0x1E0000D0,0x00007000 ++#define IPU_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1 0x1E0000D0,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT4__ADDR 0x1E0000D4 ++#define IPU_IPU_DISP_ALT4__EMPTY 0x1E0000D4,0x00000000 ++#define IPU_IPU_DISP_ALT4__FULL 0x1E0000D4,0xffffffff ++#define IPU_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1 0x1E0000D4,0x00070000 ++#define IPU_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1E0000D4,0x00007000 ++#define IPU_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1 0x1E0000D4,0x00000FFF ++ ++#define IPU_IPU_SNOOP__ADDR 0x1E0000D8 ++#define IPU_IPU_SNOOP__EMPTY 0x1E0000D8,0x00000000 ++#define IPU_IPU_SNOOP__FULL 0x1E0000D8,0xffffffff ++#define IPU_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1E0000D8,0x00010000 ++#define IPU_IPU_SNOOP__AUTOREF_PER 0x1E0000D8,0x000003FF ++ ++#define IPU_IPU_MEM_RST__ADDR 0x1E0000DC ++#define IPU_IPU_MEM_RST__EMPTY 0x1E0000DC,0x00000000 ++#define IPU_IPU_MEM_RST__FULL 0x1E0000DC,0xffffffff ++#define IPU_IPU_MEM_RST__RST_MEM_START 0x1E0000DC,0x80000000 ++#define IPU_IPU_MEM_RST__RST_MEM_EN 0x1E0000DC,0x007FFFFF ++ ++#define IPU_IPU_PM__ADDR 0x1E0000E0 ++#define IPU_IPU_PM__EMPTY 0x1E0000E0,0x00000000 ++#define IPU_IPU_PM__FULL 0x1E0000E0,0xffffffff ++#define IPU_IPU_PM__LPSR_MODE 0x1E0000E0,0x80000000 ++#define IPU_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x40000000 ++#define IPU_IPU_PM__DI1_CLK_PERIOD_1 0x1E0000E0,0x3F800000 ++#define IPU_IPU_PM__DI1_CLK_PERIOD_0 0x1E0000E0,0x007F0000 ++#define IPU_IPU_PM__CLOCK_MODE_STAT 0x1E0000E0,0x00008000 ++#define IPU_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x00004000 ++#define IPU_IPU_PM__DI0_CLK_PERIOD_1 0x1E0000E0,0x00003F80 ++#define IPU_IPU_PM__DI0_CLK_PERIOD_0 0x1E0000E0,0x0000007F ++ ++#define IPU_IPU_GPR__ADDR 0x1E0000E4 ++#define IPU_IPU_GPR__EMPTY 0x1E0000E4,0x00000000 ++#define IPU_IPU_GPR__FULL 0x1E0000E4,0xffffffff ++#define IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR 0x1E0000E4,0x80000000 ++#define IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR 0x1E0000E4,0x40000000 ++#define IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR 0x1E0000E4,0x20000000 ++#define IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR 0x1E0000E4,0x10000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1E0000E4,0x08000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1E0000E4,0x04000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1E0000E4,0x02000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1E0000E4,0x01000000 ++#define IPU_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00800000 ++#define IPU_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00400000 ++#define IPU_IPU_GPR__IPU_GP21 0x1E0000E4,0x00200000 ++#define IPU_IPU_GPR__IPU_GP20 0x1E0000E4,0x00100000 ++#define IPU_IPU_GPR__IPU_GP19 0x1E0000E4,0x00080000 ++#define IPU_IPU_GPR__IPU_GP18 0x1E0000E4,0x00040000 ++#define IPU_IPU_GPR__IPU_GP17 0x1E0000E4,0x00020000 ++#define IPU_IPU_GPR__IPU_GP16 0x1E0000E4,0x00010000 ++#define IPU_IPU_GPR__IPU_GP15 0x1E0000E4,0x00008000 ++#define IPU_IPU_GPR__IPU_GP14 0x1E0000E4,0x00004000 ++#define IPU_IPU_GPR__IPU_GP13 0x1E0000E4,0x00002000 ++#define IPU_IPU_GPR__IPU_GP12 0x1E0000E4,0x00001000 ++#define IPU_IPU_GPR__IPU_GP11 0x1E0000E4,0x00000800 ++#define IPU_IPU_GPR__IPU_GP10 0x1E0000E4,0x00000400 ++#define IPU_IPU_GPR__IPU_GP9 0x1E0000E4,0x00000200 ++#define IPU_IPU_GPR__IPU_GP8 0x1E0000E4,0x00000100 ++#define IPU_IPU_GPR__IPU_GP7 0x1E0000E4,0x00000080 ++#define IPU_IPU_GPR__IPU_GP6 0x1E0000E4,0x00000040 ++#define IPU_IPU_GPR__IPU_GP5 0x1E0000E4,0x00000020 ++#define IPU_IPU_GPR__IPU_GP4 0x1E0000E4,0x00000010 ++#define IPU_IPU_GPR__IPU_GP3 0x1E0000E4,0x00000008 ++#define IPU_IPU_GPR__IPU_GP2 0x1E0000E4,0x00000004 ++#define IPU_IPU_GPR__IPU_GP1 0x1E0000E4,0x00000002 ++#define IPU_IPU_GPR__IPU_GP0 0x1E0000E4,0x00000001 ++ ++#define IPU_IPU_INT_STAT_1__ADDR 0x1E0000E8 ++#define IPU_IPU_INT_STAT_1__EMPTY 0x1E0000E8,0x00000000 ++#define IPU_IPU_INT_STAT_1__FULL 0x1E0000E8,0xffffffff ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_31 0x1E0000E8,0x80000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_29 0x1E0000E8,0x20000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_28 0x1E0000E8,0x10000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_27 0x1E0000E8,0x08000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_24 0x1E0000E8,0x01000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_23 0x1E0000E8,0x00800000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_22 0x1E0000E8,0x00400000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_21 0x1E0000E8,0x00200000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_20 0x1E0000E8,0x00100000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_18 0x1E0000E8,0x00040000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_17 0x1E0000E8,0x00020000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_15 0x1E0000E8,0x00008000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_14 0x1E0000E8,0x00004000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_12 0x1E0000E8,0x00001000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_11 0x1E0000E8,0x00000800 ++ ++#define IPU_IPU_INT_STAT_2__ADDR 0x1E0000EC ++#define IPU_IPU_INT_STAT_2__EMPTY 0x1E0000EC,0x00000000 ++#define IPU_IPU_INT_STAT_2__FULL 0x1E0000EC,0xffffffff ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_52 0x1E0000EC,0x00100000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_51 0x1E0000EC,0x00080000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_50 0x1E0000EC,0x00040000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_49 0x1E0000EC,0x00020000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_48 0x1E0000EC,0x00010000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_47 0x1E0000EC,0x00008000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_46 0x1E0000EC,0x00004000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_45 0x1E0000EC,0x00002000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_44 0x1E0000EC,0x00001000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_43 0x1E0000EC,0x00000800 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_42 0x1E0000EC,0x00000400 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_41 0x1E0000EC,0x00000200 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_40 0x1E0000EC,0x00000100 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_33 0x1E0000EC,0x00000002 ++ ++#define IPU_IPU_INT_STAT_3__ADDR 0x1E0000F0 ++#define IPU_IPU_INT_STAT_3__EMPTY 0x1E0000F0,0x00000000 ++#define IPU_IPU_INT_STAT_3__FULL 0x1E0000F0,0xffffffff ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_31 0x1E0000F0,0x80000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_29 0x1E0000F0,0x20000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_28 0x1E0000F0,0x10000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_27 0x1E0000F0,0x08000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_24 0x1E0000F0,0x01000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_23 0x1E0000F0,0x00800000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_22 0x1E0000F0,0x00400000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_21 0x1E0000F0,0x00200000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_20 0x1E0000F0,0x00100000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_18 0x1E0000F0,0x00040000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_17 0x1E0000F0,0x00020000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_15 0x1E0000F0,0x00008000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_14 0x1E0000F0,0x00004000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_12 0x1E0000F0,0x00001000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_11 0x1E0000F0,0x00000800 ++ ++#define IPU_IPU_INT_STAT_4__ADDR 0x1E0000F4 ++#define IPU_IPU_INT_STAT_4__EMPTY 0x1E0000F4,0x00000000 ++#define IPU_IPU_INT_STAT_4__FULL 0x1E0000F4,0xffffffff ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_52 0x1E0000F4,0x00100000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_51 0x1E0000F4,0x00080000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_50 0x1E0000F4,0x00040000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_49 0x1E0000F4,0x00020000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_48 0x1E0000F4,0x00010000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_47 0x1E0000F4,0x00008000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_46 0x1E0000F4,0x00004000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_45 0x1E0000F4,0x00002000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_44 0x1E0000F4,0x00001000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_43 0x1E0000F4,0x00000800 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_42 0x1E0000F4,0x00000400 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_41 0x1E0000F4,0x00000200 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_40 0x1E0000F4,0x00000100 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_33 0x1E0000F4,0x00000002 ++ ++#define IPU_IPU_INT_STAT_5__ADDR 0x1E0000F8 ++#define IPU_IPU_INT_STAT_5__EMPTY 0x1E0000F8,0x00000000 ++#define IPU_IPU_INT_STAT_5__FULL 0x1E0000F8,0xffffffff ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_31 0x1E0000F8,0x80000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_29 0x1E0000F8,0x20000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_28 0x1E0000F8,0x10000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_27 0x1E0000F8,0x08000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_24 0x1E0000F8,0x01000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_23 0x1E0000F8,0x00800000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_22 0x1E0000F8,0x00400000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_21 0x1E0000F8,0x00200000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_20 0x1E0000F8,0x00100000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_18 0x1E0000F8,0x00040000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_17 0x1E0000F8,0x00020000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_15 0x1E0000F8,0x00008000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_14 0x1E0000F8,0x00004000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_12 0x1E0000F8,0x00001000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_11 0x1E0000F8,0x00000800 ++ ++#define IPU_IPU_INT_STAT_6__ADDR 0x1E0000FC ++#define IPU_IPU_INT_STAT_6__EMPTY 0x1E0000FC,0x00000000 ++#define IPU_IPU_INT_STAT_6__FULL 0x1E0000FC,0xffffffff ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_52 0x1E0000FC,0x00100000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_51 0x1E0000FC,0x00080000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_50 0x1E0000FC,0x00040000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_49 0x1E0000FC,0x00020000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_48 0x1E0000FC,0x00010000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_47 0x1E0000FC,0x00008000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_46 0x1E0000FC,0x00004000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_45 0x1E0000FC,0x00002000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_44 0x1E0000FC,0x00001000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_43 0x1E0000FC,0x00000800 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_42 0x1E0000FC,0x00000400 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_41 0x1E0000FC,0x00000200 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_40 0x1E0000FC,0x00000100 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_33 0x1E0000FC,0x00000002 ++ ++#define IPU_IPU_INT_STAT_7__ADDR 0x1E000100 ++#define IPU_IPU_INT_STAT_7__EMPTY 0x1E000100,0x00000000 ++#define IPU_IPU_INT_STAT_7__FULL 0x1E000100,0xffffffff ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_31 0x1E000100,0x80000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_29 0x1E000100,0x20000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_28 0x1E000100,0x10000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_27 0x1E000100,0x08000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_24 0x1E000100,0x01000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_23 0x1E000100,0x00800000 ++ ++#define IPU_IPU_INT_STAT_8__ADDR 0x1E000104 ++#define IPU_IPU_INT_STAT_8__EMPTY 0x1E000104,0x00000000 ++#define IPU_IPU_INT_STAT_8__FULL 0x1E000104,0xffffffff ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_52 0x1E000104,0x00100000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_51 0x1E000104,0x00080000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_44 0x1E000104,0x00001000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_43 0x1E000104,0x00000800 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_42 0x1E000104,0x00000400 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_41 0x1E000104,0x00000200 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_32 0x1E000104,0x00000002 ++ ++#define IPU_IPU_INT_STAT_10__ADDR 0x1E00010C ++#define IPU_IPU_INT_STAT_10__EMPTY 0x1E00010C,0x00000000 ++#define IPU_IPU_INT_STAT_10__FULL 0x1E00010C,0xffffffff ++#define IPU_IPU_INT_STAT_10__AXIR_ERR 0x1E00010C,0x40000000 ++#define IPU_IPU_INT_STAT_10__AXIW_ERR 0x1E00010C,0x20000000 ++#define IPU_IPU_INT_STAT_10__NON_PRIVILEGED_ACC_ERR 0x1E00010C,0x10000000 ++#define IPU_IPU_INT_STAT_10__IC_BAYER_FRM_LOST_ERR 0x1E00010C,0x04000000 ++#define IPU_IPU_INT_STAT_10__IC_ENC_FRM_LOST_ERR 0x1E00010C,0x02000000 ++#define IPU_IPU_INT_STAT_10__IC_VF_FRM_LOST_ERR 0x1E00010C,0x01000000 ++#define IPU_IPU_INT_STAT_10__DI1_TIME_OUT_ERR 0x1E00010C,0x00400000 ++#define IPU_IPU_INT_STAT_10__DI0_TIME_OUT_ERR 0x1E00010C,0x00200000 ++#define IPU_IPU_INT_STAT_10__DI1_SYNC_DISP_ERR 0x1E00010C,0x00100000 ++#define IPU_IPU_INT_STAT_10__DI0_SYNC_DISP_ERR 0x1E00010C,0x00080000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_6 0x1E00010C,0x00040000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_2 0x1E00010C,0x00020000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_1 0x1E00010C,0x00010000 ++ ++#define IPU_IPU_INT_STAT_11__ADDR 0x1E000110 ++#define IPU_IPU_INT_STAT_11__EMPTY 0x1E000110,0x00000000 ++#define IPU_IPU_INT_STAT_11__FULL 0x1E000110,0xffffffff ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_22 0x1E000110,0x00400000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_21 0x1E000110,0x00200000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_20 0x1E000110,0x00100000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_12 0x1E000110,0x00001000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_11 0x1E000110,0x00000800 ++ ++#define IPU_IPU_INT_STAT_12__ADDR 0x1E000114 ++#define IPU_IPU_INT_STAT_12__EMPTY 0x1E000114,0x00000000 ++#define IPU_IPU_INT_STAT_12__FULL 0x1E000114,0xffffffff ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_50 0x1E000114,0x00040000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_49 0x1E000114,0x00020000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_48 0x1E000114,0x00010000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_47 0x1E000114,0x00008000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_46 0x1E000114,0x00004000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_45 0x1E000114,0x00002000 ++ ++#define IPU_IPU_INT_STAT_13__ADDR 0x1E000118 ++#define IPU_IPU_INT_STAT_13__EMPTY 0x1E000118,0x00000000 ++#define IPU_IPU_INT_STAT_13__FULL 0x1E000118,0xffffffff ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_31 0x1E000118,0x80000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_29 0x1E000118,0x20000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_28 0x1E000118,0x10000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_27 0x1E000118,0x08000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_24 0x1E000118,0x01000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_23 0x1E000118,0x00800000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_22 0x1E000118,0x00400000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_21 0x1E000118,0x00200000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_20 0x1E000118,0x00100000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_18 0x1E000118,0x00040000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_17 0x1E000118,0x00020000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_15 0x1E000118,0x00008000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_14 0x1E000118,0x00004000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_12 0x1E000118,0x00001000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_11 0x1E000118,0x00000800 ++ ++#define IPU_IPU_INT_STAT_14__ADDR 0x1E00011C ++#define IPU_IPU_INT_STAT_14__EMPTY 0x1E00011C,0x00000000 ++#define IPU_IPU_INT_STAT_14__FULL 0x1E00011C,0xffffffff ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_52 0x1E00011C,0x00100000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_51 0x1E00011C,0x00080000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_50 0x1E00011C,0x00040000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_49 0x1E00011C,0x00020000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_48 0x1E00011C,0x00010000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_47 0x1E00011C,0x00008000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_46 0x1E00011C,0x00004000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_45 0x1E00011C,0x00002000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_44 0x1E00011C,0x00001000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_43 0x1E00011C,0x00000800 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_42 0x1E00011C,0x00000400 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_41 0x1E00011C,0x00000200 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_40 0x1E00011C,0x00000100 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_33 0x1E00011C,0x00000002 ++ ++#define IPU_IPU_INT_STAT_15__ADDR 0x1E000120 ++#define IPU_IPU_INT_STAT_15__EMPTY 0x1E000120,0x00000000 ++#define IPU_IPU_INT_STAT_15__FULL 0x1E000120,0xffffffff ++#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_8 0x1E000120,0x80000000 ++#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_3 0x1E000120,0x40000000 ++#define IPU_IPU_INT_STAT_15__DI1_DISP_CLK_EN_PRE 0x1E000120,0x20000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_10 0x1E000120,0x10000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_9 0x1E000120,0x08000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_8 0x1E000120,0x04000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_7 0x1E000120,0x02000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_6 0x1E000120,0x01000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_5 0x1E000120,0x00800000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_4 0x1E000120,0x00400000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_3 0x1E000120,0x00200000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_2 0x1E000120,0x00100000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_1 0x1E000120,0x00080000 ++#define IPU_IPU_INT_STAT_15__DI0_DISP_CLK_EN_PRE 0x1E000120,0x00040000 ++#define IPU_IPU_INT_STAT_15__DC_ASYNC_STOP 0x1E000120,0x00020000 ++#define IPU_IPU_INT_STAT_15__DC_DP_START 0x1E000120,0x00010000 ++#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_1 0x1E000120,0x00008000 ++#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_0 0x1E000120,0x00004000 ++#define IPU_IPU_INT_STAT_15__DC_FC_6 0x1E000120,0x00002000 ++#define IPU_IPU_INT_STAT_15__DC_FC_4 0x1E000120,0x00001000 ++#define IPU_IPU_INT_STAT_15__DC_FC_3 0x1E000120,0x00000800 ++#define IPU_IPU_INT_STAT_15__DC_FC_2 0x1E000120,0x00000400 ++#define IPU_IPU_INT_STAT_15__DC_FC_1 0x1E000120,0x00000200 ++#define IPU_IPU_INT_STAT_15__DC_FC_0 0x1E000120,0x00000100 ++#define IPU_IPU_INT_STAT_15__DP_ASF_BRAKE 0x1E000120,0x00000080 ++#define IPU_IPU_INT_STAT_15__DP_SF_BRAKE 0x1E000120,0x00000040 ++#define IPU_IPU_INT_STAT_15__DP_ASF_END 0x1E000120,0x00000020 ++#define IPU_IPU_INT_STAT_15__DP_ASF_START 0x1E000120,0x00000010 ++#define IPU_IPU_INT_STAT_15__DP_SF_END 0x1E000120,0x00000008 ++#define IPU_IPU_INT_STAT_15__DP_SF_START 0x1E000120,0x00000004 ++#define IPU_IPU_INT_STAT_15__IPU_SNOOPING2_INT 0x1E000120,0x00000002 ++#define IPU_IPU_INT_STAT_15__IPU_SNOOPING1_INT 0x1E000120,0x00000001 ++ ++#define IPU_IPU_CUR_BUF_0__ADDR 0x1E000124 ++#define IPU_IPU_CUR_BUF_0__EMPTY 0x1E000124,0x00000000 ++#define IPU_IPU_CUR_BUF_0__FULL 0x1E000124,0xffffffff ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_31 0x1E000124,0x80000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_29 0x1E000124,0x20000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_28 0x1E000124,0x10000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_27 0x1E000124,0x08000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_24 0x1E000124,0x01000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_23 0x1E000124,0x00800000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_22 0x1E000124,0x00400000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_21 0x1E000124,0x00200000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_20 0x1E000124,0x00100000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_18 0x1E000124,0x00040000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_17 0x1E000124,0x00020000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_15 0x1E000124,0x00008000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_14 0x1E000124,0x00004000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_12 0x1E000124,0x00001000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_11 0x1E000124,0x00000800 ++ ++#define IPU_IPU_CUR_BUF_1__ADDR 0x1E000128 ++#define IPU_IPU_CUR_BUF_1__EMPTY 0x1E000128,0x00000000 ++#define IPU_IPU_CUR_BUF_1__FULL 0x1E000128,0xffffffff ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_52 0x1E000128,0x00100000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_51 0x1E000128,0x00080000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_50 0x1E000128,0x00040000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_49 0x1E000128,0x00020000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_48 0x1E000128,0x00010000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_47 0x1E000128,0x00008000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_46 0x1E000128,0x00004000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_45 0x1E000128,0x00002000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_44 0x1E000128,0x00001000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_43 0x1E000128,0x00000800 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_42 0x1E000128,0x00000400 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_41 0x1E000128,0x00000200 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_40 0x1E000128,0x00000100 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_33 0x1E000128,0x00000002 ++ ++#define IPU_IPU_ALT_CUR_BUF_0__ADDR 0x1E00012C ++#define IPU_IPU_ALT_CUR_BUF_0__EMPTY 0x1E00012C,0x00000000 ++#define IPU_IPU_ALT_CUR_BUF_0__FULL 0x1E00012C,0xffffffff ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_29 0x1E00012C,0x20000000 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_24 0x1E00012C,0x01000000 ++ ++#define IPU_IPU_ALT_CUR_BUF_1__ADDR 0x1E000130 ++#define IPU_IPU_ALT_CUR_BUF_1__EMPTY 0x1E000130,0x00000000 ++#define IPU_IPU_ALT_CUR_BUF_1__FULL 0x1E000130,0xffffffff ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_52 0x1E000130,0x00100000 ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_41 0x1E000130,0x00000200 ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_33 0x1E000130,0x00000002 ++ ++#define IPU_IPU_SRM_STAT__ADDR 0x1E000134 ++#define IPU_IPU_SRM_STAT__EMPTY 0x1E000134,0x00000000 ++#define IPU_IPU_SRM_STAT__FULL 0x1E000134,0xffffffff ++#define IPU_IPU_SRM_STAT__DI1_SRM_STAT 0x1E000134,0x00000200 ++#define IPU_IPU_SRM_STAT__DI0_SRM_STAT 0x1E000134,0x00000100 ++#define IPU_IPU_SRM_STAT__DC_6_SRM_STAT 0x1E000134,0x00000020 ++#define IPU_IPU_SRM_STAT__DC_2_SRM_STAT 0x1E000134,0x00000010 ++#define IPU_IPU_SRM_STAT__DP_A1_SRM_STAT 0x1E000134,0x00000004 ++#define IPU_IPU_SRM_STAT__DP_A0_SRM_STAT 0x1E000134,0x00000002 ++#define IPU_IPU_SRM_STAT__DP_S_SRM_STAT 0x1E000134,0x00000001 ++ ++#define IPU_IPU_DISP_TASKS_STAT__ADDR 0x1E00013C ++#define IPU_IPU_DISP_TASKS_STAT__EMPTY 0x1E00013C,0x00000000 ++#define IPU_IPU_DISP_TASKS_STAT__FULL 0x1E00013C,0xffffffff ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_CUR_FLOW 0x1E00013C,0x00000800 ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_TSTAT 0x1E00013C,0x00000700 ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC0_TSTAT 0x1E00013C,0x00000030 ++#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_CUR_FLOW 0x1E00013C,0x00000008 ++#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_TSTAT 0x1E00013C,0x00000007 ++ ++#define IPU_IPU_CH_BUF0_RDY0__ADDR 0x1E000140 ++#define IPU_IPU_CH_BUF0_RDY0__EMPTY 0x1E000140,0x00000000 ++#define IPU_IPU_CH_BUF0_RDY0__FULL 0x1E000140,0xffffffff ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_31 0x1E000140,0x80000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_29 0x1E000140,0x20000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_28 0x1E000140,0x10000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_27 0x1E000140,0x08000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_24 0x1E000140,0x01000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_23 0x1E000140,0x00800000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_22 0x1E000140,0x00400000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_21 0x1E000140,0x00200000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_20 0x1E000140,0x00100000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_18 0x1E000140,0x00040000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_17 0x1E000140,0x00020000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_15 0x1E000140,0x00008000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_14 0x1E000140,0x00004000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_12 0x1E000140,0x00001000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_11 0x1E000140,0x00000800 ++ ++#define IPU_IPU_CH_BUF0_RDY1__ADDR 0x1E000144 ++#define IPU_IPU_CH_BUF0_RDY1__EMPTY 0x1E000144,0x00000000 ++#define IPU_IPU_CH_BUF0_RDY1__FULL 0x1E000144,0xffffffff ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_52 0x1E000144,0x00100000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_51 0x1E000144,0x00080000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_50 0x1E000144,0x00040000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_49 0x1E000144,0x00020000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_48 0x1E000144,0x00010000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_47 0x1E000144,0x00008000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_46 0x1E000144,0x00004000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_45 0x1E000144,0x00002000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_44 0x1E000144,0x00001000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_43 0x1E000144,0x00000800 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_42 0x1E000144,0x00000400 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_41 0x1E000144,0x00000200 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_40 0x1E000144,0x00000100 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_33 0x1E000144,0x00000002 ++ ++#define IPU_IPU_CH_BUF1_RDY0__ADDR 0x1E000148 ++#define IPU_IPU_CH_BUF1_RDY0__EMPTY 0x1E000148,0x00000000 ++#define IPU_IPU_CH_BUF1_RDY0__FULL 0x1E000148,0xffffffff ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_31 0x1E000148,0x80000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_29 0x1E000148,0x20000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_28 0x1E000148,0x10000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_27 0x1E000148,0x08000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_24 0x1E000148,0x01000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_23 0x1E000148,0x00800000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_22 0x1E000148,0x00400000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_21 0x1E000148,0x00200000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_20 0x1E000148,0x00100000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_18 0x1E000148,0x00040000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_17 0x1E000148,0x00020000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_15 0x1E000148,0x00008000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_14 0x1E000148,0x00004000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_12 0x1E000148,0x00001000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_11 0x1E000148,0x00000800 ++ ++#define IPU_IPU_CH_BUF1_RDY1__ADDR 0x1E00014C ++#define IPU_IPU_CH_BUF1_RDY1__EMPTY 0x1E00014C,0x00000000 ++#define IPU_IPU_CH_BUF1_RDY1__FULL 0x1E00014C,0xffffffff ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_52 0x1E00014C,0x00100000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_51 0x1E00014C,0x00080000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_50 0x1E00014C,0x00040000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_49 0x1E00014C,0x00020000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_48 0x1E00014C,0x00010000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_47 0x1E00014C,0x00008000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_46 0x1E00014C,0x00004000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_45 0x1E00014C,0x00002000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_44 0x1E00014C,0x00001000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_43 0x1E00014C,0x00000800 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_42 0x1E00014C,0x00000400 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_41 0x1E00014C,0x00000200 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_40 0x1E00014C,0x00000100 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_33 0x1E00014C,0x00000002 ++ ++#define IPU_IPU_CH_DB_MODE_SEL_0__ADDR 0x1E000150 ++#define IPU_IPU_CH_DB_MODE_SEL_0__EMPTY 0x1E000150,0x00000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__FULL 0x1E000150,0xffffffff ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_31 0x1E000150,0x80000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_29 0x1E000150,0x20000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_28 0x1E000150,0x10000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_27 0x1E000150,0x08000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_24 0x1E000150,0x01000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_23 0x1E000150,0x00800000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_22 0x1E000150,0x00400000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_21 0x1E000150,0x00200000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_20 0x1E000150,0x00100000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_18 0x1E000150,0x00040000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_17 0x1E000150,0x00020000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_15 0x1E000150,0x00008000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_14 0x1E000150,0x00004000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_12 0x1E000150,0x00001000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_11 0x1E000150,0x00000800 ++ ++#define IPU_IPU_CH_DB_MODE_SEL_1__ADDR 0x1E000154 ++#define IPU_IPU_CH_DB_MODE_SEL_1__EMPTY 0x1E000154,0x00000000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__FULL 0x1E000154,0xffffffff ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_52 0x1E000154,0x00100000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_51 0x1E000154,0x00080000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_50 0x1E000154,0x00040000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_49 0x1E000154,0x00020000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_48 0x1E000154,0x00010000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_47 0x1E000154,0x00008000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_46 0x1E000154,0x00004000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_45 0x1E000154,0x00002000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_44 0x1E000154,0x00001000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_43 0x1E000154,0x00000800 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_42 0x1E000154,0x00000400 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_41 0x1E000154,0x00000200 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_40 0x1E000154,0x00000100 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_33 0x1E000154,0x00000002 ++ ++#define IPU_IPU_ALT_CH_BUF0_RDY0__ADDR 0x1E000158 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__EMPTY 0x1E000158,0x00000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__FULL 0x1E000158,0xffffffff ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_29 0x1E000158,0x20000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_24 0x1E000158,0x01000000 ++ ++#define IPU_IPU_ALT_CH_BUF0_RDY1__ADDR 0x1E00015C ++#define IPU_IPU_ALT_CH_BUF0_RDY1__EMPTY 0x1E00015C,0x00000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__FULL 0x1E00015C,0xffffffff ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_52 0x1E00015C,0x00100000 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_41 0x1E00015C,0x00000200 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_33 0x1E00015C,0x00000002 ++ ++#define IPU_IPU_ALT_CH_BUF1_RDY0__ADDR 0x1E000160 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__EMPTY 0x1E000160,0x00000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__FULL 0x1E000160,0xffffffff ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_29 0x1E000160,0x20000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_24 0x1E000160,0x01000000 ++ ++#define IPU_IPU_ALT_CH_BUF1_RDY1__ADDR 0x1E000164 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__EMPTY 0x1E000164,0x00000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__FULL 0x1E000164,0xffffffff ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_52 0x1E000164,0x00100000 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_41 0x1E000164,0x00000200 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_33 0x1E000164,0x00000002 ++ ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__ADDR 0x1E000168 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__EMPTY 0x1E000168,0x00000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__FULL 0x1E000168,0xffffffff ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_29 0x1E000168,0x20000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_24 0x1E000168,0x01000000 ++ ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__ADDR 0x1E00016C ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__EMPTY 0x1E00016C,0x00000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__FULL 0x1E00016C,0xffffffff ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_52 0x1E00016C,0x00100000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_41 0x1E00016C,0x00000200 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_33 0x1E00016C,0x00000002 ++ ++#define IPU_IDMAC_CONF__ADDR 0x1E008000 ++#define IPU_IDMAC_CONF__EMPTY 0x1E008000,0x00000000 ++#define IPU_IDMAC_CONF__FULL 0x1E008000,0xffffffff ++#define IPU_IDMAC_CONF__P_ENDIAN 0x1E008000,0x00010000 ++#define IPU_IDMAC_CONF__WIDPT 0x1E008000,0x00000018 ++#define IPU_IDMAC_CONF__MAX_REQ_READ 0x1E008000,0x00000007 ++ ++#define IPU_IDMAC_CH_EN_1__ADDR 0x1E008004 ++#define IPU_IDMAC_CH_EN_1__EMPTY 0x1E008004,0x00000000 ++#define IPU_IDMAC_CH_EN_1__FULL 0x1E008004,0xffffffff ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1E008004,0x80000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1E008004,0x20000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1E008004,0x10000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1E008004,0x08000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1E008004,0x01000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1E008004,0x00800000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1E008004,0x00400000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1E008004,0x00200000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1E008004,0x00100000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1E008004,0x00040000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1E008004,0x00020000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1E008004,0x00008000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1E008004,0x00004000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1E008004,0x00001000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1E008004,0x00000800 ++ ++#define IPU_IDMAC_CH_EN_2__ADDR 0x1E008008 ++#define IPU_IDMAC_CH_EN_2__EMPTY 0x1E008008,0x00000000 ++#define IPU_IDMAC_CH_EN_2__FULL 0x1E008008,0xffffffff ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1E008008,0x00100000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1E008008,0x00080000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1E008008,0x00040000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1E008008,0x00020000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1E008008,0x00010000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1E008008,0x00008000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1E008008,0x00004000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1E008008,0x00002000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1E008008,0x00001000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1E008008,0x00000800 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1E008008,0x00000400 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1E008008,0x00000200 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1E008008,0x00000100 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1E008008,0x00000002 ++ ++#define IPU_IDMAC_SEP_ALPHA__ADDR 0x1E00800C ++#define IPU_IDMAC_SEP_ALPHA__EMPTY 0x1E00800C,0x00000000 ++#define IPU_IDMAC_SEP_ALPHA__FULL 0x1E00800C,0xffffffff ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1E00800C,0x20000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1E00800C,0x08000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1E00800C,0x01000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1E00800C,0x00800000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1E00800C,0x00008000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1E00800C,0x00004000 ++ ++#define IPU_IDMAC_ALT_SEP_ALPHA__ADDR 0x1E008010 ++#define IPU_IDMAC_ALT_SEP_ALPHA__EMPTY 0x1E008010,0x00000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__FULL 0x1E008010,0xffffffff ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1E008010,0x20000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1E008010,0x01000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1E008010,0x00800000 ++ ++#define IPU_IDMAC_CH_PRI_1__ADDR 0x1E008014 ++#define IPU_IDMAC_CH_PRI_1__EMPTY 0x1E008014,0x00000000 ++#define IPU_IDMAC_CH_PRI_1__FULL 0x1E008014,0xffffffff ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1E008014,0x20000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1E008014,0x10000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1E008014,0x08000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1E008014,0x01000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1E008014,0x00800000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1E008014,0x00400000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1E008014,0x00200000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1E008014,0x00100000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1E008014,0x00008000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1E008014,0x00004000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1E008014,0x00001000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1E008014,0x00000800 ++ ++#define IPU_IDMAC_CH_PRI_2__ADDR 0x1E008018 ++#define IPU_IDMAC_CH_PRI_2__EMPTY 0x1E008018,0x00000000 ++#define IPU_IDMAC_CH_PRI_2__FULL 0x1E008018,0xffffffff ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1E008018,0x00040000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1E008018,0x00020000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1E008018,0x00010000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1E008018,0x00008000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1E008018,0x00004000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1E008018,0x00002000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1E008018,0x00001000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1E008018,0x00000800 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1E008018,0x00000400 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1E008018,0x00000200 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1E008018,0x00000100 ++ ++#define IPU_IDMAC_WM_EN_1__ADDR 0x1E00801C ++#define IPU_IDMAC_WM_EN_1__EMPTY 0x1E00801C,0x00000000 ++#define IPU_IDMAC_WM_EN_1__FULL 0x1E00801C,0xffffffff ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1E00801C,0x20000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1E00801C,0x10000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1E00801C,0x08000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1E00801C,0x01000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1E00801C,0x00800000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1E00801C,0x00004000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1E00801C,0x00001000 ++ ++#define IPU_IDMAC_WM_EN_2__ADDR 0x1E008020 ++#define IPU_IDMAC_WM_EN_2__EMPTY 0x1E008020,0x00000000 ++#define IPU_IDMAC_WM_EN_2__FULL 0x1E008020,0xffffffff ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1E008020,0x00001000 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1E008020,0x00000800 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1E008020,0x00000400 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1E008020,0x00000200 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1E008020,0x00000100 ++ ++#define IPU_IDMAC_LOCK_EN_2__ADDR 0x1E008024 ++#define IPU_IDMAC_LOCK_EN_2__EMPTY 0x1E008024,0x00000000 ++#define IPU_IDMAC_LOCK_EN_2__FULL 0x1E008024,0xffffffff ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1E008024,0x00040000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1E008024,0x00020000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1E008024,0x00010000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1E008024,0x00008000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1E008024,0x00004000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1E008024,0x00002000 ++ ++#define IPU_IDMAC_SUB_ADDR_1__ADDR 0x1E00802C ++#define IPU_IDMAC_SUB_ADDR_1__EMPTY 0x1E00802C,0x00000000 ++#define IPU_IDMAC_SUB_ADDR_1__FULL 0x1E00802C,0xffffffff ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1E00802C,0x7F000000 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1E00802C,0x007F0000 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1E00802C,0x00007F00 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1E00802C,0x0000007F ++ ++#define IPU_IDMAC_SUB_ADDR_2__ADDR 0x1E008030 ++#define IPU_IDMAC_SUB_ADDR_2__EMPTY 0x1E008030,0x00000000 ++#define IPU_IDMAC_SUB_ADDR_2__FULL 0x1E008030,0xffffffff ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1E008030,0x007F0000 ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1E008030,0x00007F00 ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1E008030,0x0000007F ++ ++#define IPU_IDMAC_BNDM_EN_1__ADDR 0x1E008034 ++#define IPU_IDMAC_BNDM_EN_1__EMPTY 0x1E008034,0x00000000 ++#define IPU_IDMAC_BNDM_EN_1__FULL 0x1E008034,0xffffffff ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1E008034,0x00400000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1E008034,0x00200000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1E008034,0x00100000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1E008034,0x00001000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1E008034,0x00000800 ++ ++#define IPU_IDMAC_BNDM_EN_2__ADDR 0x1E008038 ++#define IPU_IDMAC_BNDM_EN_2__EMPTY 0x1E008038,0x00000000 ++#define IPU_IDMAC_BNDM_EN_2__FULL 0x1E008038,0xffffffff ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1E008038,0x00040000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1E008038,0x00020000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1E008038,0x00010000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1E008038,0x00008000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1E008038,0x00004000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1E008038,0x00002000 ++ ++#define IPU_IDMAC_SC_CORD__ADDR 0x1E00803C ++#define IPU_IDMAC_SC_CORD__EMPTY 0x1E00803C,0x00000000 ++#define IPU_IDMAC_SC_CORD__FULL 0x1E00803C,0xffffffff ++#define IPU_IDMAC_SC_CORD__SX0 0x1E00803C,0x0FFF0000 ++#define IPU_IDMAC_SC_CORD__SY0 0x1E00803C,0x000007FF ++ ++#define IPU_IDMAC_CH_BUSY_1__ADDR 0x1E008040 ++#define IPU_IDMAC_CH_BUSY_1__EMPTY 0x1E008040,0x00000000 ++#define IPU_IDMAC_CH_BUSY_1__FULL 0x1E008040,0xffffffff ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_31 0x1E008040,0x80000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_29 0x1E008040,0x20000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_28 0x1E008040,0x10000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_27 0x1E008040,0x08000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_24 0x1E008040,0x01000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_23 0x1E008040,0x00800000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_22 0x1E008040,0x00400000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_21 0x1E008040,0x00200000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_20 0x1E008040,0x00100000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_18 0x1E008040,0x00040000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_17 0x1E008040,0x00020000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_15 0x1E008040,0x00008000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_14 0x1E008040,0x00004000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_12 0x1E008040,0x00001000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_11 0x1E008040,0x00000800 ++ ++#define IPU_IDMAC_CH_BUSY_2__ADDR 0x1E008044 ++#define IPU_IDMAC_CH_BUSY_2__EMPTY 0x1E008044,0x00000000 ++#define IPU_IDMAC_CH_BUSY_2__FULL 0x1E008044,0xffffffff ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_52 0x1E008044,0x00100000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_51 0x1E008044,0x00080000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_50 0x1E008044,0x00040000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_49 0x1E008044,0x00020000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_48 0x1E008044,0x00010000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_47 0x1E008044,0x00008000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_46 0x1E008044,0x00004000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_45 0x1E008044,0x00002000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_44 0x1E008044,0x00001000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_43 0x1E008044,0x00000800 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_42 0x1E008044,0x00000400 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_41 0x1E008044,0x00000200 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_40 0x1E008044,0x00000100 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_33 0x1E008044,0x00000002 ++ ++#define IPU_DP_COM_CONF_SYNC__ADDR 0x1E018000 ++#define IPU_DP_COM_CONF_SYNC__EMPTY 0x1E018000,0x00000000 ++#define IPU_DP_COM_CONF_SYNC__FULL 0x1E018000,0xffffffff ++#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC 0x1E018000,0x00002000 ++#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC 0x1E018000,0x00001000 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1E018000,0x00000800 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1E018000,0x00000400 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC 0x1E018000,0x00000300 ++#define IPU_DP_COM_CONF_SYNC__DP_COC_SYNC 0x1E018000,0x00000070 ++#define IPU_DP_COM_CONF_SYNC__DP_GWCKE_SYNC 0x1E018000,0x00000008 ++#define IPU_DP_COM_CONF_SYNC__DP_GWAM_SYNC 0x1E018000,0x00000004 ++#define IPU_DP_COM_CONF_SYNC__DP_GWSEL_SYNC 0x1E018000,0x00000002 ++#define IPU_DP_COM_CONF_SYNC__DP_FG_EN_SYNC 0x1E018000,0x00000001 ++ ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__ADDR 0x1E018004 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__EMPTY 0x1E018004,0x00000000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__FULL 0x1E018004,0xffffffff ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC 0x1E018004,0xFF000000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1E018004,0x00FF0000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1E018004,0x0000FF00 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1E018004,0x000000FF ++ ++#define IPU_DP_FG_POS_SYNC__ADDR 0x1E018008 ++#define IPU_DP_FG_POS_SYNC__EMPTY 0x1E018008,0x00000000 ++#define IPU_DP_FG_POS_SYNC__FULL 0x1E018008,0xffffffff ++#define IPU_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1E018008,0x07FF0000 ++#define IPU_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1E018008,0x000007FF ++ ++#define IPU_DP_CUR_POS_SYNC__ADDR 0x1E01800C ++#define IPU_DP_CUR_POS_SYNC__EMPTY 0x1E01800C,0x00000000 ++#define IPU_DP_CUR_POS_SYNC__FULL 0x1E01800C,0xffffffff ++#define IPU_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1E01800C,0xF8000000 ++#define IPU_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1E01800C,0x07FF0000 ++#define IPU_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1E01800C,0x0000F800 ++#define IPU_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1E01800C,0x000007FF ++ ++#define IPU_DP_CUR_MAP_SYNC__ADDR 0x1E018010 ++#define IPU_DP_CUR_MAP_SYNC__EMPTY 0x1E018010,0x00000000 ++#define IPU_DP_CUR_MAP_SYNC__FULL 0x1E018010,0xffffffff ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1E018010,0x00FF0000 ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1E018010,0x0000FF00 ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1E018010,0x000000FF ++ ++#define IPU_DP_GAMMA_C_SYNC_0__ADDR 0x1E018014 ++#define IPU_DP_GAMMA_C_SYNC_0__EMPTY 0x1E018014,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_0__FULL 0x1E018014,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1E018014,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1E018014,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_1__ADDR 0x1E018018 ++#define IPU_DP_GAMMA_C_SYNC_1__EMPTY 0x1E018018,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_1__FULL 0x1E018018,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1E018018,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1E018018,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_2__ADDR 0x1E01801C ++#define IPU_DP_GAMMA_C_SYNC_2__EMPTY 0x1E01801C,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_2__FULL 0x1E01801C,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1E01801C,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1E01801C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_3__ADDR 0x1E018020 ++#define IPU_DP_GAMMA_C_SYNC_3__EMPTY 0x1E018020,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_3__FULL 0x1E018020,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1E018020,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1E018020,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_4__ADDR 0x1E018024 ++#define IPU_DP_GAMMA_C_SYNC_4__EMPTY 0x1E018024,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_4__FULL 0x1E018024,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1E018024,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1E018024,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_5__ADDR 0x1E018028 ++#define IPU_DP_GAMMA_C_SYNC_5__EMPTY 0x1E018028,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_5__FULL 0x1E018028,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1E018028,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1E018028,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_6__ADDR 0x1E01802C ++#define IPU_DP_GAMMA_C_SYNC_6__EMPTY 0x1E01802C,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_6__FULL 0x1E01802C,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1E01802C,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1E01802C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_7__ADDR 0x1E018030 ++#define IPU_DP_GAMMA_C_SYNC_7__EMPTY 0x1E018030,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_7__FULL 0x1E018030,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1E018030,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1E018030,0x000001FF ++ ++#define IPU_DP_GAMMA_S_SYNC_0__ADDR 0x1E018034 ++#define IPU_DP_GAMMA_S_SYNC_0__EMPTY 0x1E018034,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_0__FULL 0x1E018034,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1E018034,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1E018034,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1E018034,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1E018034,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_1__ADDR 0x1E018038 ++#define IPU_DP_GAMMA_S_SYNC_1__EMPTY 0x1E018038,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_1__FULL 0x1E018038,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1E018038,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1E018038,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1E018038,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1E018038,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_2__ADDR 0x1E01803C ++#define IPU_DP_GAMMA_S_SYNC_2__EMPTY 0x1E01803C,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_2__FULL 0x1E01803C,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1E01803C,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1E01803C,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9 0x1E01803C,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8 0x1E01803C,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_3__ADDR 0x1E018040 ++#define IPU_DP_GAMMA_S_SYNC_3__EMPTY 0x1E018040,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_3__FULL 0x1E018040,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1E018040,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1E018040,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1E018040,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1E018040,0x000000FF ++ ++#define IPU_DP_CSCA_SYNC_0__ADDR 0x1E018044 ++#define IPU_DP_CSCA_SYNC_0__EMPTY 0x1E018044,0x00000000 ++#define IPU_DP_CSCA_SYNC_0__FULL 0x1E018044,0xffffffff ++#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1E018044,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1E018044,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_1__ADDR 0x1E018048 ++#define IPU_DP_CSCA_SYNC_1__EMPTY 0x1E018048,0x00000000 ++#define IPU_DP_CSCA_SYNC_1__FULL 0x1E018048,0xffffffff ++#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1E018048,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1E018048,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_2__ADDR 0x1E01804C ++#define IPU_DP_CSCA_SYNC_2__EMPTY 0x1E01804C,0x00000000 ++#define IPU_DP_CSCA_SYNC_2__FULL 0x1E01804C,0xffffffff ++#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1E01804C,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1E01804C,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_3__ADDR 0x1E018050 ++#define IPU_DP_CSCA_SYNC_3__EMPTY 0x1E018050,0x00000000 ++#define IPU_DP_CSCA_SYNC_3__FULL 0x1E018050,0xffffffff ++#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1E018050,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1E018050,0x000003FF ++ ++#define IPU_DP_CSC_SYNC_0__ADDR 0x1E018054 ++#define IPU_DP_CSC_SYNC_0__EMPTY 0x1E018054,0x00000000 ++#define IPU_DP_CSC_SYNC_0__FULL 0x1E018054,0xffffffff ++#define IPU_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1E018054,0xC0000000 ++#define IPU_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1E018054,0x3FFF0000 ++#define IPU_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1E018054,0x000003FF ++ ++#define IPU_DP_CSC_SYNC_1__ADDR 0x1E018058 ++#define IPU_DP_CSC_SYNC_1__EMPTY 0x1E018058,0x00000000 ++#define IPU_DP_CSC_SYNC_1__FULL 0x1E018058,0xffffffff ++#define IPU_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1E018058,0xC0000000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1E018058,0x3FFF0000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1E018058,0x0000C000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1E018058,0x00003FFF ++ ++#define IPU_DP_CUR_POS_ALT__ADDR 0x1E01805C ++#define IPU_DP_CUR_POS_ALT__EMPTY 0x1E01805C,0x00000000 ++#define IPU_DP_CUR_POS_ALT__FULL 0x1E01805C,0xffffffff ++#define IPU_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1E01805C,0xF8000000 ++#define IPU_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1E01805C,0x07FF0000 ++#define IPU_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1E01805C,0x0000F800 ++#define IPU_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1E01805C,0x000007FF ++ ++#define IPU_DP_COM_CONF_ASYNC__ADDR 0x1E018060 ++#define IPU_DP_COM_CONF_ASYNC__EMPTY 0x1E018060,0x00000000 ++#define IPU_DP_COM_CONF_ASYNC__FULL 0x1E018060,0xffffffff ++#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_YUV_EN_ASYNC 0x1E018060,0x00002000 ++#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_EN_ASYNC 0x1E018060,0x00001000 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_YUV_SAT_MODE_ASYNC 0x1E018060,0x00000800 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_GAMUT_SAT_EN_ASYNC 0x1E018060,0x00000400 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_DEF_ASYNC 0x1E018060,0x00000300 ++#define IPU_DP_COM_CONF_ASYNC__DP_COC_ASYNC 0x1E018060,0x00000070 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWCKE_ASYNC 0x1E018060,0x00000008 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWAM_ASYNC 0x1E018060,0x00000004 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWSEL_ASYNC 0x1E018060,0x00000002 ++#define IPU_DP_COM_CONF_ASYNC__DP_FG_EN_ASYNC 0x1E018060,0x00000001 ++ ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__ADDR 0x1E018064 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__EMPTY 0x1E018064,0x00000000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__FULL 0x1E018064,0xffffffff ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWAV_ASYNC 0x1E018064,0xFF000000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKR_ASYNC 0x1E018064,0x00FF0000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKG_ASYNC 0x1E018064,0x0000FF00 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKB_ASYNC 0x1E018064,0x000000FF ++ ++#define IPU_DP_FG_POS_ASYNC__ADDR 0x1E018068 ++#define IPU_DP_FG_POS_ASYNC__EMPTY 0x1E018068,0x00000000 ++#define IPU_DP_FG_POS_ASYNC__FULL 0x1E018068,0xffffffff ++#define IPU_DP_FG_POS_ASYNC__DP_FGXP_ASYNC 0x1E018068,0x07FF0000 ++#define IPU_DP_FG_POS_ASYNC__DP_FGYP_ASYNC 0x1E018068,0x000007FF ++ ++#define IPU_DP_CUR_POS_ASYNC__ADDR 0x1E01806C ++#define IPU_DP_CUR_POS_ASYNC__EMPTY 0x1E01806C,0x00000000 ++#define IPU_DP_CUR_POS_ASYNC__FULL 0x1E01806C,0xffffffff ++#define IPU_DP_CUR_POS_ASYNC__DP_CXW_ASYNC 0x1E01806C,0xF8000000 ++#define IPU_DP_CUR_POS_ASYNC__DP_CXP_ASYNC 0x1E01806C,0x07FF0000 ++#define IPU_DP_CUR_POS_ASYNC__DP_CYH_ASYNC 0x1E01806C,0x0000F800 ++#define IPU_DP_CUR_POS_ASYNC__DP_CYP_ASYNC 0x1E01806C,0x000007FF ++ ++#define IPU_DP_CUR_MAP_ASYNC__ADDR 0x1E018070 ++#define IPU_DP_CUR_MAP_ASYNC__EMPTY 0x1E018070,0x00000000 ++#define IPU_DP_CUR_MAP_ASYNC__FULL 0x1E018070,0xffffffff ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_R_ASYNC 0x1E018070,0x00FF0000 ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_G_ASYNC 0x1E018070,0x0000FF00 ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_B_ASYNC 0x1E018070,0x000000FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_0__ADDR 0x1E018074 ++#define IPU_DP_GAMMA_C_ASYNC_0__EMPTY 0x1E018074,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_0__FULL 0x1E018074,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_1 0x1E018074,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_0 0x1E018074,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_1__ADDR 0x1E018078 ++#define IPU_DP_GAMMA_C_ASYNC_1__EMPTY 0x1E018078,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_1__FULL 0x1E018078,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_3 0x1E018078,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_2 0x1E018078,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_2__ADDR 0x1E01807C ++#define IPU_DP_GAMMA_C_ASYNC_2__EMPTY 0x1E01807C,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_2__FULL 0x1E01807C,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_5 0x1E01807C,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_4 0x1E01807C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_3__ADDR 0x1E018080 ++#define IPU_DP_GAMMA_C_ASYNC_3__EMPTY 0x1E018080,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_3__FULL 0x1E018080,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_7 0x1E018080,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_6 0x1E018080,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_4__ADDR 0x1E018084 ++#define IPU_DP_GAMMA_C_ASYNC_4__EMPTY 0x1E018084,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_4__FULL 0x1E018084,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_9 0x1E018084,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_8 0x1E018084,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_5__ADDR 0x1E018088 ++#define IPU_DP_GAMMA_C_ASYNC_5__EMPTY 0x1E018088,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_5__FULL 0x1E018088,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_11 0x1E018088,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_10 0x1E018088,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_6__ADDR 0x1E01808C ++#define IPU_DP_GAMMA_C_ASYNC_6__EMPTY 0x1E01808C,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_6__FULL 0x1E01808C,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_13 0x1E01808C,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_12 0x1E01808C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_7__ADDR 0x1E018090 ++#define IPU_DP_GAMMA_C_ASYNC_7__EMPTY 0x1E018090,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_7__FULL 0x1E018090,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_15 0x1E018090,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_14 0x1E018090,0x000001FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_0__ADDR 0x1E018094 ++#define IPU_DP_GAMMA_S_ASYNC_0__EMPTY 0x1E018094,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_0__FULL 0x1E018094,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_3 0x1E018094,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_2 0x1E018094,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_1 0x1E018094,0x0000FF04 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_0 0x1E018094,0x00000103 ++ ++#define IPU_DP_GAMMA_S_ASYNC_1__ADDR 0x1E018098 ++#define IPU_DP_GAMMA_S_ASYNC_1__EMPTY 0x1E018098,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_1__FULL 0x1E018098,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_7 0x1E018098,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_6 0x1E018098,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_5 0x1E018098,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_4 0x1E018098,0x000000FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_2__ADDR 0x1E01809C ++#define IPU_DP_GAMMA_S_ASYNC_2__EMPTY 0x1E01809C,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_2__FULL 0x1E01809C,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_11 0x1E01809C,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_10 0x1E01809C,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_9 0x1E01809C,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_8 0x1E01809C,0x000000FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_3__ADDR 0x1E0180A0 ++#define IPU_DP_GAMMA_S_ASYNC_3__EMPTY 0x1E0180A0,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_3__FULL 0x1E0180A0,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_15 0x1E0180A0,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_14 0x1E0180A0,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_13 0x1E0180A0,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_12 0x1E0180A0,0x000000FF ++ ++#define IPU_DP_CSCA_ASYNC_0__ADDR 0x1E0180A4 ++#define IPU_DP_CSCA_ASYNC_0__EMPTY 0x1E0180A4,0x00000000 ++#define IPU_DP_CSCA_ASYNC_0__FULL 0x1E0180A4,0xffffffff ++#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_1 0x1E0180A4,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_0 0x1E0180A4,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_1__ADDR 0x1E0180A8 ++#define IPU_DP_CSCA_ASYNC_1__EMPTY 0x1E0180A8,0x00000000 ++#define IPU_DP_CSCA_ASYNC_1__FULL 0x1E0180A8,0xffffffff ++#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_3 0x1E0180A8,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_2 0x1E0180A8,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_2__ADDR 0x1E0180AC ++#define IPU_DP_CSCA_ASYNC_2__EMPTY 0x1E0180AC,0x00000000 ++#define IPU_DP_CSCA_ASYNC_2__FULL 0x1E0180AC,0xffffffff ++#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_5 0x1E0180AC,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_4 0x1E0180AC,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_3__ADDR 0x1E0180B0 ++#define IPU_DP_CSCA_ASYNC_3__EMPTY 0x1E0180B0,0x00000000 ++#define IPU_DP_CSCA_ASYNC_3__FULL 0x1E0180B0,0xffffffff ++#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_7 0x1E0180B0,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_6 0x1E0180B0,0x000003FF ++ ++#define IPU_DP_CSC_ASYNC_0__ADDR 0x1E0180B4 ++#define IPU_DP_CSC_ASYNC_0__EMPTY 0x1E0180B4,0x00000000 ++#define IPU_DP_CSC_ASYNC_0__FULL 0x1E0180B4,0xffffffff ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_S0_ASYNC 0x1E0180B4,0xC0000000 ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_B0_ASYNC 0x1E0180B4,0x3FFF0000 ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_A8_ASYNC 0x1E0180B4,0x00000403 ++ ++#define IPU_DP_CSC_ASYNC_1__ADDR 0x1E0180B8 ++#define IPU_DP_CSC_ASYNC_1__EMPTY 0x1E0180B8,0x00000000 ++#define IPU_DP_CSC_ASYNC_1__FULL 0x1E0180B8,0xffffffff ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_S2_ASYNC 0x1E0180B8,0xC0000000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_B2_ASYNC 0x1E0180B8,0x3FFF0000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_S1_ASYNC 0x1E0180B8,0x0000C000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_B1_ASYNC 0x1E0180B8,0x00003FFF ++ ++#define IPU_DP_DEBUG_CNT__ADDR 0x1E0180BC ++#define IPU_DP_DEBUG_CNT__EMPTY 0x1E0180BC,0x00000000 ++#define IPU_DP_DEBUG_CNT__FULL 0x1E0180BC,0xffffffff ++#define IPU_DP_DEBUG_CNT__BRAKE_CNT_1 0x1E0180BC,0x000000E0 ++#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_1 0x1E0180BC,0x00000010 ++#define IPU_DP_DEBUG_CNT__BRAKE_CNT_0 0x1E0180BC,0x0000000E ++#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_0 0x1E0180BC,0x00000001 ++ ++#define IPU_DP_DEBUG_STAT__ADDR 0x1E0180C0 ++#define IPU_DP_DEBUG_STAT__EMPTY 0x1E0180C0,0x00000000 ++#define IPU_DP_DEBUG_STAT__FULL 0x1E0180C0,0xffffffff ++#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_1 0x1E0180C0,0x20000000 ++#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_1 0x1E0180C0,0x10000000 ++#define IPU_DP_DEBUG_STAT__FG_ACTIVE_1 0x1E0180C0,0x08000000 ++#define IPU_DP_DEBUG_STAT__V_CNT_OLD_1 0x1E0180C0,0x07FF0000 ++#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_0 0x1E0180C0,0x00002000 ++#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_0 0x1E0180C0,0x00001000 ++#define IPU_DP_DEBUG_STAT__FG_ACTIVE_0 0x1E0180C0,0x00000800 ++#define IPU_DP_DEBUG_STAT__V_CNT_OLD_0 0x1E0180C0,0x000007FF ++ ++#define IPU_IC_CONF__ADDR 0x1E020000 ++#define IPU_IC_CONF__EMPTY 0x1E020000,0x00000000 ++#define IPU_IC_CONF__FULL 0x1E020000,0xffffffff ++#define IPU_IC_CONF__CSI_MEM_WR_EN 0x1E020000,0x80000000 ++#define IPU_IC_CONF__RWS_EN 0x1E020000,0x40000000 ++#define IPU_IC_CONF__IC_KEY_COLOR_EN 0x1E020000,0x20000000 ++#define IPU_IC_CONF__IC_GLB_LOC_A 0x1E020000,0x10000000 ++#define IPU_IC_CONF__PP_ROT_EN 0x1E020000,0x00100000 ++#define IPU_IC_CONF__PP_CMB 0x1E020000,0x00080000 ++#define IPU_IC_CONF__PP_CSC2 0x1E020000,0x00040000 ++#define IPU_IC_CONF__PP_CSC1 0x1E020000,0x00020000 ++#define IPU_IC_CONF__PP_EN 0x1E020000,0x00010000 ++#define IPU_IC_CONF__PRPVF_ROT_EN 0x1E020000,0x00001000 ++#define IPU_IC_CONF__PRPVF_CMB 0x1E020000,0x00000800 ++#define IPU_IC_CONF__PRPVF_CSC2 0x1E020000,0x00000400 ++#define IPU_IC_CONF__PRPVF_CSC1 0x1E020000,0x00000200 ++#define IPU_IC_CONF__PRPVF_EN 0x1E020000,0x00000100 ++#define IPU_IC_CONF__PRPENC_ROT_EN 0x1E020000,0x00000004 ++#define IPU_IC_CONF__PRPENC_CSC1 0x1E020000,0x00000002 ++#define IPU_IC_CONF__PRPENC_EN 0x1E020000,0x00000001 ++ ++#define IPU_IC_PRP_ENC_RSC__ADDR 0x1E020004 ++#define IPU_IC_PRP_ENC_RSC__EMPTY 0x1E020004,0x00000000 ++#define IPU_IC_PRP_ENC_RSC__FULL 0x1E020004,0xffffffff ++#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1E020004,0xC0000000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1E020004,0x3FFF0000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1E020004,0x0000C000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1E020004,0x00003FFF ++ ++#define IPU_IC_PRP_VF_RSC__ADDR 0x1E020008 ++#define IPU_IC_PRP_VF_RSC__EMPTY 0x1E020008,0x00000000 ++#define IPU_IC_PRP_VF_RSC__FULL 0x1E020008,0xffffffff ++#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1E020008,0xC0000000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1E020008,0x3FFF0000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1E020008,0x0000C000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1E020008,0x00003FFF ++ ++#define IPU_IC_PP_RSC__ADDR 0x1E02000C ++#define IPU_IC_PP_RSC__EMPTY 0x1E02000C,0x00000000 ++#define IPU_IC_PP_RSC__FULL 0x1E02000C,0xffffffff ++#define IPU_IC_PP_RSC__PP_DS_R_V 0x1E02000C,0xC0000000 ++#define IPU_IC_PP_RSC__PP_RS_R_V 0x1E02000C,0x3FFF0000 ++#define IPU_IC_PP_RSC__PP_DS_R_H 0x1E02000C,0x0000C000 ++#define IPU_IC_PP_RSC__PP_RS_R_H 0x1E02000C,0x00003FFF ++ ++#define IPU_IC_CMBP_1__ADDR 0x1E020010 ++#define IPU_IC_CMBP_1__EMPTY 0x1E020010,0x00000000 ++#define IPU_IC_CMBP_1__FULL 0x1E020010,0xffffffff ++#define IPU_IC_CMBP_1__IC_PP_ALPHA_V 0x1E020010,0x0000FF00 ++#define IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1E020010,0x000000FF ++ ++#define IPU_IC_CMBP_2__ADDR 0x1E020014 ++#define IPU_IC_CMBP_2__EMPTY 0x1E020014,0x00000000 ++#define IPU_IC_CMBP_2__FULL 0x1E020014,0xffffffff ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_R 0x1E020014,0x00FF0000 ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_G 0x1E020014,0x0000FF00 ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_B 0x1E020014,0x000000FF ++ ++#define IPU_IC_IDMAC_1__ADDR 0x1E020018 ++#define IPU_IC_IDMAC_1__EMPTY 0x1E020018,0x00000000 ++#define IPU_IC_IDMAC_1__FULL 0x1E020018,0xffffffff ++#define IPU_IC_IDMAC_1__ALT_CB7_BURST_16 0x1E020018,0x02000000 ++#define IPU_IC_IDMAC_1__ALT_CB6_BURST_16 0x1E020018,0x01000000 ++#define IPU_IC_IDMAC_1__T3_FLIP_UD 0x1E020018,0x00080000 ++#define IPU_IC_IDMAC_1__T3_FLIP_LR 0x1E020018,0x00040000 ++#define IPU_IC_IDMAC_1__T3_ROT 0x1E020018,0x00020000 ++#define IPU_IC_IDMAC_1__T2_FLIP_UD 0x1E020018,0x00010000 ++#define IPU_IC_IDMAC_1__T2_FLIP_LR 0x1E020018,0x00008000 ++#define IPU_IC_IDMAC_1__T2_ROT 0x1E020018,0x00004000 ++#define IPU_IC_IDMAC_1__T1_FLIP_UD 0x1E020018,0x00002000 ++#define IPU_IC_IDMAC_1__T1_FLIP_LR 0x1E020018,0x00001000 ++#define IPU_IC_IDMAC_1__T1_ROT 0x1E020018,0x00000800 ++#define IPU_IC_IDMAC_1__CB7_BURST_16 0x1E020018,0x00000080 ++#define IPU_IC_IDMAC_1__CB6_BURST_16 0x1E020018,0x00000040 ++#define IPU_IC_IDMAC_1__CB5_BURST_16 0x1E020018,0x00000020 ++#define IPU_IC_IDMAC_1__CB4_BURST_16 0x1E020018,0x00000010 ++#define IPU_IC_IDMAC_1__CB3_BURST_16 0x1E020018,0x00000008 ++#define IPU_IC_IDMAC_1__CB2_BURST_16 0x1E020018,0x00000004 ++#define IPU_IC_IDMAC_1__CB1_BURST_16 0x1E020018,0x00000002 ++#define IPU_IC_IDMAC_1__CB0_BURST_16 0x1E020018,0x00000001 ++ ++#define IPU_IC_IDMAC_2__ADDR 0x1E02001C ++#define IPU_IC_IDMAC_2__EMPTY 0x1E02001C,0x00000000 ++#define IPU_IC_IDMAC_2__FULL 0x1E02001C,0xffffffff ++#define IPU_IC_IDMAC_2__T3_FR_HEIGHT 0x1E02001C,0x3FF00000 ++#define IPU_IC_IDMAC_2__T2_FR_HEIGHT 0x1E02001C,0x000FFC00 ++#define IPU_IC_IDMAC_2__T1_FR_HEIGHT 0x1E02001C,0x000003FF ++ ++#define IPU_IC_IDMAC_3__ADDR 0x1E020020 ++#define IPU_IC_IDMAC_3__EMPTY 0x1E020020,0x00000000 ++#define IPU_IC_IDMAC_3__FULL 0x1E020020,0xffffffff ++#define IPU_IC_IDMAC_3__T3_FR_WIDTH 0x1E020020,0x3FF00000 ++#define IPU_IC_IDMAC_3__T2_FR_WIDTH 0x1E020020,0x000FFC00 ++#define IPU_IC_IDMAC_3__T1_FR_WIDTH 0x1E020020,0x000003FF ++ ++#define IPU_IC_IDMAC_4__ADDR 0x1E020024 ++#define IPU_IC_IDMAC_4__EMPTY 0x1E020024,0x00000000 ++#define IPU_IC_IDMAC_4__FULL 0x1E020024,0xffffffff ++#define IPU_IC_IDMAC_4__RM_BRDG_MAX_RQ 0x1E020024,0x0000F000 ++#define IPU_IC_IDMAC_4__IBM_BRDG_MAX_RQ 0x1E020024,0x00000F00 ++#define IPU_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1E020024,0x000000F0 ++#define IPU_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ 0x1E020024,0x0000000F ++ ++#define IPU_DI0_GENERAL__ADDR 0x1E040000 ++#define IPU_DI0_GENERAL__EMPTY 0x1E040000,0x00000000 ++#define IPU_DI0_GENERAL__FULL 0x1E040000,0xffffffff ++#define IPU_DI0_GENERAL__DI0_DISP_Y_SEL 0x1E040000,0x70000000 ++#define IPU_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1E040000,0x0F000000 ++#define IPU_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1E040000,0x00800000 ++#define IPU_DI0_GENERAL__DI0_MASK_SEL 0x1E040000,0x00400000 ++#define IPU_DI0_GENERAL__DI0_VSYNC_EXT 0x1E040000,0x00200000 ++#define IPU_DI0_GENERAL__DI0_CLK_EXT 0x1E040000,0x00100000 ++#define IPU_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1E040000,0x000C0000 ++#define IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1E040000,0x00020000 ++#define IPU_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1E040000,0x0000F000 ++#define IPU_DI0_GENERAL__DI0_ERR_TREATMENT 0x1E040000,0x00000800 ++#define IPU_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1E040000,0x00000400 ++#define IPU_DI0_GENERAL__DI0_POLARITY_CS1 0x1E040000,0x00000200 ++#define IPU_DI0_GENERAL__DI0_POLARITY_CS0 0x1E040000,0x00000100 ++#define IPU_DI0_GENERAL__DI0_POLARITY_8 0x1E040000,0x00000080 ++#define IPU_DI0_GENERAL__DI0_POLARITY_7 0x1E040000,0x00000040 ++#define IPU_DI0_GENERAL__DI0_POLARITY_6 0x1E040000,0x00000020 ++#define IPU_DI0_GENERAL__DI0_POLARITY_5 0x1E040000,0x00000010 ++#define IPU_DI0_GENERAL__DI0_POLARITY_4 0x1E040000,0x00000008 ++#define IPU_DI0_GENERAL__DI0_POLARITY_3 0x1E040000,0x00000004 ++#define IPU_DI0_GENERAL__DI0_POLARITY_2 0x1E040000,0x00000002 ++#define IPU_DI0_GENERAL__DI0_POLARITY_1 0x1E040000,0x00000001 ++ ++#define IPU_DI0_BS_CLKGEN0__ADDR 0x1E040004 ++#define IPU_DI0_BS_CLKGEN0__EMPTY 0x1E040004,0x00000000 ++#define IPU_DI0_BS_CLKGEN0__FULL 0x1E040004,0xffffffff ++#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1E040004,0x01FF0000 ++#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1E040004,0x00000FFF ++ ++#define IPU_DI0_BS_CLKGEN1__ADDR 0x1E040008 ++#define IPU_DI0_BS_CLKGEN1__EMPTY 0x1E040008,0x00000000 ++#define IPU_DI0_BS_CLKGEN1__FULL 0x1E040008,0xffffffff ++#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1E040008,0x01FF0000 ++#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1E040008,0x000001FF ++ ++#define DI_SWGEN0_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di *0x8000 + \ ++ (pointer-1) * 0x4 + 0x000C) ++#define DI_SWGEN0_EMPTY(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00000000 ++#define DI_SWGEN0_FULL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0xFFFFFFFF ++ ++#define DI_SWGEN0_RUN_VALUE_M1(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x7FF80000 ++#define DI_SWGEN0_RUN_RESOL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00070000 ++#define DI_SWGEN0_OFFSET_VALUE(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00007FF8 ++#define DI_SWGEN0_OFFSET_RESOL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00000007 ++ ++#define DI_SWGEN1_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di *0x8000 + \ ++ (pointer-1) * 0x4 + 0x0030) ++#define DI_SWGEN1_EMPTY(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000000 ++#define DI_SWGEN1_FULL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0xFFFFFFFF ++ ++#define DI_SWGEN1_CNT_POL_GEN_EN(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x60000000 ++#define DI_SWGEN1_CNT_AUTOLOAD(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x10000000 ++#define DI_SWGEN1_CNT_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x0E000000 ++#define DI_SWGEN1_CNT_DOW(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x01FF0000 ++#define DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00007000 ++#define DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000E00 ++#define DI_SWGEN1_CNT_CNT_UP(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x000001FF ++ ++/*sync waveform generator 9 is special*/ ++#define IPU_DI0_SW_GEN0_9__ADDR 0x1E04002C ++#define IPU_DI0_SW_GEN0_9__EMPTY 0x1E04002C,0x00000000 ++#define IPU_DI0_SW_GEN0_9__FULL 0x1E04002C,0xffffffff ++#define IPU_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1E04002C,0x7FF80000 ++#define IPU_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1E04002C,0x00070000 ++#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1E04002C,0x00007FF8 ++#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1E04002C,0x00000007 ++ ++#define IPU_DI0_SW_GEN1_9__ADDR 0x1E040050 ++#define IPU_DI0_SW_GEN1_9__EMPTY 0x1E040050,0x00000000 ++#define IPU_DI0_SW_GEN1_9__FULL 0x1E040050,0xffffffff ++#define IPU_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1E040050,0xE0000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1E040050,0x10000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1E040050,0x0E000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1E040050,0x01FF0000 ++#define IPU_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1E040050,0x00008000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1E040050,0x000001FF ++ ++#define IPU_DI0_SYNC_AS_GEN__ADDR 0x1E040054 ++#define IPU_DI0_SYNC_AS_GEN__EMPTY 0x1E040054,0x00000000 ++#define IPU_DI0_SYNC_AS_GEN__FULL 0x1E040054,0xffffffff ++#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1E040054,0x10000000 ++#define IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1E040054,0x0000E000 ++#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1E040054,0x00000FFF ++ ++#define IPU_DI0_DW_GEN_0__ADDR 0x1E040058 ++#define IPU_DI0_DW_GEN_0__EMPTY 0x1E040058,0x00000000 ++#define IPU_DI0_DW_GEN_0__FULL 0x1E040058,0xffffffff ++#define IPU_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1E040058,0xFF000000 ++#define IPU_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1E040058,0x00FF0000 ++#define IPU_DI0_DW_GEN_0__DI0_CST_0 0x1E040058,0x0000C000 ++#define IPU_DI0_DW_GEN_0__DI0_PT_6_0 0x1E040058,0x00003000 ++#define IPU_DI0_DW_GEN_0__DI0_PT_5_0 0x1E040058,0x00000C00 ++#define IPU_DI0_DW_GEN_0__DI0_PT_4_0 0x1E040058,0x00000300 ++#define IPU_DI0_DW_GEN_0__DI0_PT_3_0 0x1E040058,0x000000C0 ++#define IPU_DI0_DW_GEN_0__DI0_PT_2_0 0x1E040058,0x00000030 ++#define IPU_DI0_DW_GEN_0__DI0_PT_1_0 0x1E040058,0x0000000C ++#define IPU_DI0_DW_GEN_0__DI0_PT_0_0 0x1E040058,0x00000003 ++ ++#define IPU_DI0_DW_GEN_0__ADDR 0x1E040058 ++#define IPU_DI0_DW_GEN_0__EMPTY 0x1E040058,0x00000000 ++#define IPU_DI0_DW_GEN_0__FULL 0x1E040058,0xffffffff ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1E040058,0xFF000000 ++#define IPU_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1E040058,0x00FF0000 ++#define IPU_DI0_DW_GEN_0__DI0_CST_0 0x1E040058,0x0000C000 ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1E040058,0x000001F0 ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1E040058,0x0000000C ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1E040058,0x00000003 ++ ++#define IPU_DI0_DW_GEN_1__ADDR 0x1E04005C ++#define IPU_DI0_DW_GEN_1__EMPTY 0x1E04005C,0x00000000 ++#define IPU_DI0_DW_GEN_1__FULL 0x1E04005C,0xffffffff ++#define IPU_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1E04005C,0xFF000000 ++#define IPU_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1E04005C,0x00FF0000 ++#define IPU_DI0_DW_GEN_1__DI0_CST_1 0x1E04005C,0x0000C000 ++#define IPU_DI0_DW_GEN_1__DI0_PT_6_1 0x1E04005C,0x00003000 ++#define IPU_DI0_DW_GEN_1__DI0_PT_5_1 0x1E04005C,0x00000C00 ++#define IPU_DI0_DW_GEN_1__DI0_PT_4_1 0x1E04005C,0x00000300 ++#define IPU_DI0_DW_GEN_1__DI0_PT_3_1 0x1E04005C,0x000000C0 ++#define IPU_DI0_DW_GEN_1__DI0_PT_2_1 0x1E04005C,0x00000030 ++#define IPU_DI0_DW_GEN_1__DI0_PT_1_1 0x1E04005C,0x0000000C ++#define IPU_DI0_DW_GEN_1__DI0_PT_0_1 0x1E04005C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_1__ADDR 0x1E04005C ++#define IPU_DI0_DW_GEN_1__EMPTY 0x1E04005C,0x00000000 ++#define IPU_DI0_DW_GEN_1__FULL 0x1E04005C,0xffffffff ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1E04005C,0xFF000000 ++#define IPU_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1E04005C,0x00FF0000 ++#define IPU_DI0_DW_GEN_1__DI0_CST_1 0x1E04005C,0x0000C000 ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1E04005C,0x000001F0 ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1E04005C,0x0000000C ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1E04005C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_2__ADDR 0x1E040060 ++#define IPU_DI0_DW_GEN_2__EMPTY 0x1E040060,0x00000000 ++#define IPU_DI0_DW_GEN_2__FULL 0x1E040060,0xffffffff ++#define IPU_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1E040060,0xFF000000 ++#define IPU_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1E040060,0x00FF0000 ++#define IPU_DI0_DW_GEN_2__DI0_CST_2 0x1E040060,0x0000C000 ++#define IPU_DI0_DW_GEN_2__DI0_PT_6_2 0x1E040060,0x00003000 ++#define IPU_DI0_DW_GEN_2__DI0_PT_5_2 0x1E040060,0x00000C00 ++#define IPU_DI0_DW_GEN_2__DI0_PT_4_2 0x1E040060,0x00000300 ++#define IPU_DI0_DW_GEN_2__DI0_PT_3_2 0x1E040060,0x000000C0 ++#define IPU_DI0_DW_GEN_2__DI0_PT_2_2 0x1E040060,0x00000030 ++#define IPU_DI0_DW_GEN_2__DI0_PT_1_2 0x1E040060,0x0000000C ++#define IPU_DI0_DW_GEN_2__DI0_PT_0_2 0x1E040060,0x00000003 ++ ++#define IPU_DI0_DW_GEN_2__ADDR 0x1E040060 ++#define IPU_DI0_DW_GEN_2__EMPTY 0x1E040060,0x00000000 ++#define IPU_DI0_DW_GEN_2__FULL 0x1E040060,0xffffffff ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1E040060,0xFF000000 ++#define IPU_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1E040060,0x00FF0000 ++#define IPU_DI0_DW_GEN_2__DI0_CST_2 0x1E040060,0x0000C000 ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1E040060,0x000001F0 ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1E040060,0x0000000C ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1E040060,0x00000003 ++ ++#define IPU_DI0_DW_GEN_3__ADDR 0x1E040064 ++#define IPU_DI0_DW_GEN_3__EMPTY 0x1E040064,0x00000000 ++#define IPU_DI0_DW_GEN_3__FULL 0x1E040064,0xffffffff ++#define IPU_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1E040064,0xFF000000 ++#define IPU_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1E040064,0x00FF0000 ++#define IPU_DI0_DW_GEN_3__DI0_CST_3 0x1E040064,0x0000C000 ++#define IPU_DI0_DW_GEN_3__DI0_PT_6_3 0x1E040064,0x00003000 ++#define IPU_DI0_DW_GEN_3__DI0_PT_5_3 0x1E040064,0x00000C00 ++#define IPU_DI0_DW_GEN_3__DI0_PT_4_3 0x1E040064,0x00000300 ++#define IPU_DI0_DW_GEN_3__DI0_PT_3_3 0x1E040064,0x000000C0 ++#define IPU_DI0_DW_GEN_3__DI0_PT_2_3 0x1E040064,0x00000030 ++#define IPU_DI0_DW_GEN_3__DI0_PT_1_3 0x1E040064,0x0000000C ++#define IPU_DI0_DW_GEN_3__DI0_PT_0_3 0x1E040064,0x00000003 ++ ++#define IPU_DI0_DW_GEN_3__ADDR 0x1E040064 ++#define IPU_DI0_DW_GEN_3__EMPTY 0x1E040064,0x00000000 ++#define IPU_DI0_DW_GEN_3__FULL 0x1E040064,0xffffffff ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1E040064,0xFF000000 ++#define IPU_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1E040064,0x00FF0000 ++#define IPU_DI0_DW_GEN_3__DI0_CST_3 0x1E040064,0x0000C000 ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1E040064,0x000001F0 ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1E040064,0x0000000C ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1E040064,0x00000003 ++ ++#define IPU_DI0_DW_GEN_4__ADDR 0x1E040068 ++#define IPU_DI0_DW_GEN_4__EMPTY 0x1E040068,0x00000000 ++#define IPU_DI0_DW_GEN_4__FULL 0x1E040068,0xffffffff ++#define IPU_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1E040068,0xFF000000 ++#define IPU_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1E040068,0x00FF0000 ++#define IPU_DI0_DW_GEN_4__DI0_CST_4 0x1E040068,0x0000C000 ++#define IPU_DI0_DW_GEN_4__DI0_PT_6_4 0x1E040068,0x00003000 ++#define IPU_DI0_DW_GEN_4__DI0_PT_5_4 0x1E040068,0x00000C00 ++#define IPU_DI0_DW_GEN_4__DI0_PT_4_4 0x1E040068,0x00000300 ++#define IPU_DI0_DW_GEN_4__DI0_PT_3_4 0x1E040068,0x000000C0 ++#define IPU_DI0_DW_GEN_4__DI0_PT_2_4 0x1E040068,0x00000030 ++#define IPU_DI0_DW_GEN_4__DI0_PT_1_4 0x1E040068,0x0000000C ++#define IPU_DI0_DW_GEN_4__DI0_PT_0_4 0x1E040068,0x00000003 ++ ++#define IPU_DI0_DW_GEN_4__ADDR 0x1E040068 ++#define IPU_DI0_DW_GEN_4__EMPTY 0x1E040068,0x00000000 ++#define IPU_DI0_DW_GEN_4__FULL 0x1E040068,0xffffffff ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1E040068,0xFF000000 ++#define IPU_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1E040068,0x00FF0000 ++#define IPU_DI0_DW_GEN_4__DI0_CST_4 0x1E040068,0x0000C000 ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1E040068,0x000001F0 ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1E040068,0x0000000C ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1E040068,0x00000003 ++ ++#define IPU_DI0_DW_GEN_5__ADDR 0x1E04006C ++#define IPU_DI0_DW_GEN_5__EMPTY 0x1E04006C,0x00000000 ++#define IPU_DI0_DW_GEN_5__FULL 0x1E04006C,0xffffffff ++#define IPU_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1E04006C,0xFF000000 ++#define IPU_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1E04006C,0x00FF0000 ++#define IPU_DI0_DW_GEN_5__DI0_CST_5 0x1E04006C,0x0000C000 ++#define IPU_DI0_DW_GEN_5__DI0_PT_6_5 0x1E04006C,0x00003000 ++#define IPU_DI0_DW_GEN_5__DI0_PT_5_5 0x1E04006C,0x00000C00 ++#define IPU_DI0_DW_GEN_5__DI0_PT_4_5 0x1E04006C,0x00000300 ++#define IPU_DI0_DW_GEN_5__DI0_PT_3_5 0x1E04006C,0x000000C0 ++#define IPU_DI0_DW_GEN_5__DI0_PT_2_5 0x1E04006C,0x00000030 ++#define IPU_DI0_DW_GEN_5__DI0_PT_1_5 0x1E04006C,0x0000000C ++#define IPU_DI0_DW_GEN_5__DI0_PT_0_5 0x1E04006C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_5__ADDR 0x1E04006C ++#define IPU_DI0_DW_GEN_5__EMPTY 0x1E04006C,0x00000000 ++#define IPU_DI0_DW_GEN_5__FULL 0x1E04006C,0xffffffff ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1E04006C,0xFF000000 ++#define IPU_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1E04006C,0x00FF0000 ++#define IPU_DI0_DW_GEN_5__DI0_CST_5 0x1E04006C,0x0000C000 ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1E04006C,0x000001F0 ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1E04006C,0x0000000C ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1E04006C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_6__ADDR 0x1E040070 ++#define IPU_DI0_DW_GEN_6__EMPTY 0x1E040070,0x00000000 ++#define IPU_DI0_DW_GEN_6__FULL 0x1E040070,0xffffffff ++#define IPU_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1E040070,0xFF000000 ++#define IPU_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1E040070,0x00FF0000 ++#define IPU_DI0_DW_GEN_6__DI0_CST_6 0x1E040070,0x0000C000 ++#define IPU_DI0_DW_GEN_6__DI0_PT_6_6 0x1E040070,0x00003000 ++#define IPU_DI0_DW_GEN_6__DI0_PT_5_6 0x1E040070,0x00000C00 ++#define IPU_DI0_DW_GEN_6__DI0_PT_4_6 0x1E040070,0x00000300 ++#define IPU_DI0_DW_GEN_6__DI0_PT_3_6 0x1E040070,0x000000C0 ++#define IPU_DI0_DW_GEN_6__DI0_PT_2_6 0x1E040070,0x00000030 ++#define IPU_DI0_DW_GEN_6__DI0_PT_1_6 0x1E040070,0x0000000C ++#define IPU_DI0_DW_GEN_6__DI0_PT_0_6 0x1E040070,0x00000003 ++ ++#define IPU_DI0_DW_GEN_6__ADDR 0x1E040070 ++#define IPU_DI0_DW_GEN_6__EMPTY 0x1E040070,0x00000000 ++#define IPU_DI0_DW_GEN_6__FULL 0x1E040070,0xffffffff ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1E040070,0xFF000000 ++#define IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1E040070,0x00FF0000 ++#define IPU_DI0_DW_GEN_6__DI0_CST_6 0x1E040070,0x0000C000 ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1E040070,0x000001F0 ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1E040070,0x0000000C ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1E040070,0x00000003 ++ ++#define IPU_DI0_DW_GEN_7__ADDR 0x1E040074 ++#define IPU_DI0_DW_GEN_7__EMPTY 0x1E040074,0x00000000 ++#define IPU_DI0_DW_GEN_7__FULL 0x1E040074,0xffffffff ++#define IPU_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1E040074,0xFF000000 ++#define IPU_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1E040074,0x00FF0000 ++#define IPU_DI0_DW_GEN_7__DI0_CST_7 0x1E040074,0x0000C000 ++#define IPU_DI0_DW_GEN_7__DI0_PT_6_7 0x1E040074,0x00003000 ++#define IPU_DI0_DW_GEN_7__DI0_PT_5_7 0x1E040074,0x00000C00 ++#define IPU_DI0_DW_GEN_7__DI0_PT_4_7 0x1E040074,0x00000300 ++#define IPU_DI0_DW_GEN_7__DI0_PT_3_7 0x1E040074,0x000000C0 ++#define IPU_DI0_DW_GEN_7__DI0_PT_2_7 0x1E040074,0x00000030 ++#define IPU_DI0_DW_GEN_7__DI0_PT_1_7 0x1E040074,0x0000000C ++#define IPU_DI0_DW_GEN_7__DI0_PT_0_7 0x1E040074,0x00000003 ++ ++#define IPU_DI0_DW_GEN_7__ADDR 0x1E040074 ++#define IPU_DI0_DW_GEN_7__EMPTY 0x1E040074,0x00000000 ++#define IPU_DI0_DW_GEN_7__FULL 0x1E040074,0xffffffff ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1E040074,0xFF000000 ++#define IPU_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1E040074,0x00FF0000 ++#define IPU_DI0_DW_GEN_7__DI0_CST_7 0x1E040074,0x0000C000 ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1E040074,0x000001F0 ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1E040074,0x0000000C ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1E040074,0x00000003 ++ ++#define IPU_DI0_DW_GEN_8__ADDR 0x1E040078 ++#define IPU_DI0_DW_GEN_8__EMPTY 0x1E040078,0x00000000 ++#define IPU_DI0_DW_GEN_8__FULL 0x1E040078,0xffffffff ++#define IPU_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1E040078,0xFF000000 ++#define IPU_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1E040078,0x00FF0000 ++#define IPU_DI0_DW_GEN_8__DI0_CST_8 0x1E040078,0x0000C000 ++#define IPU_DI0_DW_GEN_8__DI0_PT_6_8 0x1E040078,0x00003000 ++#define IPU_DI0_DW_GEN_8__DI0_PT_5_8 0x1E040078,0x00000C00 ++#define IPU_DI0_DW_GEN_8__DI0_PT_4_8 0x1E040078,0x00000300 ++#define IPU_DI0_DW_GEN_8__DI0_PT_3_8 0x1E040078,0x000000C0 ++#define IPU_DI0_DW_GEN_8__DI0_PT_2_8 0x1E040078,0x00000030 ++#define IPU_DI0_DW_GEN_8__DI0_PT_1_8 0x1E040078,0x0000000C ++#define IPU_DI0_DW_GEN_8__DI0_PT_0_8 0x1E040078,0x00000003 ++ ++#define IPU_DI0_DW_GEN_8__ADDR 0x1E040078 ++#define IPU_DI0_DW_GEN_8__EMPTY 0x1E040078,0x00000000 ++#define IPU_DI0_DW_GEN_8__FULL 0x1E040078,0xffffffff ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1E040078,0xFF000000 ++#define IPU_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1E040078,0x00FF0000 ++#define IPU_DI0_DW_GEN_8__DI0_CST_8 0x1E040078,0x0000C000 ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1E040078,0x000001F0 ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1E040078,0x0000000C ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1E040078,0x00000003 ++ ++#define IPU_DI0_DW_GEN_9__ADDR 0x1E04007C ++#define IPU_DI0_DW_GEN_9__EMPTY 0x1E04007C,0x00000000 ++#define IPU_DI0_DW_GEN_9__FULL 0x1E04007C,0xffffffff ++#define IPU_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1E04007C,0xFF000000 ++#define IPU_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1E04007C,0x00FF0000 ++#define IPU_DI0_DW_GEN_9__DI0_CST_9 0x1E04007C,0x0000C000 ++#define IPU_DI0_DW_GEN_9__DI0_PT_6_9 0x1E04007C,0x00003000 ++#define IPU_DI0_DW_GEN_9__DI0_PT_5_9 0x1E04007C,0x00000C00 ++#define IPU_DI0_DW_GEN_9__DI0_PT_4_9 0x1E04007C,0x00000300 ++#define IPU_DI0_DW_GEN_9__DI0_PT_3_9 0x1E04007C,0x000000C0 ++#define IPU_DI0_DW_GEN_9__DI0_PT_2_9 0x1E04007C,0x00000030 ++#define IPU_DI0_DW_GEN_9__DI0_PT_1_9 0x1E04007C,0x0000000C ++#define IPU_DI0_DW_GEN_9__DI0_PT_0_9 0x1E04007C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_9__ADDR 0x1E04007C ++#define IPU_DI0_DW_GEN_9__EMPTY 0x1E04007C,0x00000000 ++#define IPU_DI0_DW_GEN_9__FULL 0x1E04007C,0xffffffff ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1E04007C,0xFF000000 ++#define IPU_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1E04007C,0x00FF0000 ++#define IPU_DI0_DW_GEN_9__DI0_CST_9 0x1E04007C,0x0000C000 ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1E04007C,0x000001F0 ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1E04007C,0x0000000C ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1E04007C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_10__ADDR 0x1E040080 ++#define IPU_DI0_DW_GEN_10__EMPTY 0x1E040080,0x00000000 ++#define IPU_DI0_DW_GEN_10__FULL 0x1E040080,0xffffffff ++#define IPU_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1E040080,0xFF000000 ++#define IPU_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1E040080,0x00FF0000 ++#define IPU_DI0_DW_GEN_10__DI0_CST_10 0x1E040080,0x0000C000 ++#define IPU_DI0_DW_GEN_10__DI0_PT_6_10 0x1E040080,0x00003000 ++#define IPU_DI0_DW_GEN_10__DI0_PT_5_10 0x1E040080,0x00000C00 ++#define IPU_DI0_DW_GEN_10__DI0_PT_4_10 0x1E040080,0x00000300 ++#define IPU_DI0_DW_GEN_10__DI0_PT_3_10 0x1E040080,0x000000C0 ++#define IPU_DI0_DW_GEN_10__DI0_PT_2_10 0x1E040080,0x00000030 ++#define IPU_DI0_DW_GEN_10__DI0_PT_1_10 0x1E040080,0x0000000C ++#define IPU_DI0_DW_GEN_10__DI0_PT_0_10 0x1E040080,0x00000003 ++ ++#define IPU_DI0_DW_GEN_10__ADDR 0x1E040080 ++#define IPU_DI0_DW_GEN_10__EMPTY 0x1E040080,0x00000000 ++#define IPU_DI0_DW_GEN_10__FULL 0x1E040080,0xffffffff ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1E040080,0xFF000000 ++#define IPU_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1E040080,0x00FF0000 ++#define IPU_DI0_DW_GEN_10__DI0_CST_10 0x1E040080,0x0000C000 ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E040080,0x000001F0 ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1E040080,0x0000000C ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1E040080,0x00000003 ++ ++#define IPU_DI0_DW_GEN_11__ADDR 0x1E040084 ++#define IPU_DI0_DW_GEN_11__EMPTY 0x1E040084,0x00000000 ++#define IPU_DI0_DW_GEN_11__FULL 0x1E040084,0xffffffff ++#define IPU_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1E040084,0xFF000000 ++#define IPU_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1E040084,0x00FF0000 ++#define IPU_DI0_DW_GEN_11__DI0_CST_11 0x1E040084,0x0000C000 ++#define IPU_DI0_DW_GEN_11__DI0_PT_6_11 0x1E040084,0x00003000 ++#define IPU_DI0_DW_GEN_11__DI0_PT_5_11 0x1E040084,0x00000C00 ++#define IPU_DI0_DW_GEN_11__DI0_PT_4_11 0x1E040084,0x00000300 ++#define IPU_DI0_DW_GEN_11__DI0_PT_3_11 0x1E040084,0x000000C0 ++#define IPU_DI0_DW_GEN_11__DI0_PT_2_11 0x1E040084,0x00000030 ++#define IPU_DI0_DW_GEN_11__DI0_PT_1_11 0x1E040084,0x0000000C ++#define IPU_DI0_DW_GEN_11__DI0_PT_0_11 0x1E040084,0x00000003 ++ ++#define IPU_DI0_DW_GEN_11__ADDR 0x1E040084 ++#define IPU_DI0_DW_GEN_11__EMPTY 0x1E040084,0x00000000 ++#define IPU_DI0_DW_GEN_11__FULL 0x1E040084,0xffffffff ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1E040084,0xFF000000 ++#define IPU_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1E040084,0x00FF0000 ++#define IPU_DI0_DW_GEN_11__DI0_CST_11 0x1E040084,0x0000C000 ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E040084,0x000001F0 ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1E040084,0x0000000C ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1E040084,0x00000003 ++ ++#define IPU_DI_DW_OFFSET 0x0088 ++#define DI_WAVESET_ADDR(di, pointer, set) (IPU_DI0_GENERAL__ADDR + \ ++ di*0x8000 + IPU_DI_DW_OFFSET + \ ++ pointer*0x4 + set * 0x30) ++#define DI_WAVESET_UP(di, pointer, set) DI_WAVESET_ADDR(di, pointer, set), 0x000001FF ++#define DI_WAVESET_DOWN(di, pointer, set) DI_WAVESET_ADDR(di, pointer, set), 0x01FF0000 ++ ++#define IPU_DI_STEP_RPT_OFFSET 0x0148 ++#define DI_STEP_RPT_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di*0x8000 + IPU_DI_STEP_RPT_OFFSET + \ ++ ((pointer-1) / 2)*0x4 ) ++#define DI_STEP_RPT(di, pointer) DI_STEP_RPT_ADDR(di, pointer), 0x0FFF<<((pointer-1)%2)*16 ++ ++#define IPU_DI0_STP_REP_9__ADDR 0x1E040158 ++#define IPU_DI0_STP_REP_9__EMPTY 0x1E040158,0x00000000 ++#define IPU_DI0_STP_REP_9__FULL 0x1E040158,0xffffffff ++#define IPU_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1E040158,0x00000FFF ++ ++#define IPU_DI0_SER_CONF__ADDR 0x1E04015C ++#define IPU_DI0_SER_CONF__EMPTY 0x1E04015C,0x00000000 ++#define IPU_DI0_SER_CONF__FULL 0x1E04015C,0xffffffff ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1E04015C,0xF0000000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1E04015C,0x0F000000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1E04015C,0x00F00000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1E04015C,0x000F0000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1E04015C,0x0000FF00 ++#define IPU_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1E04015C,0x00000020 ++#define IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1E04015C,0x00000010 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1E04015C,0x00000008 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1E04015C,0x00000004 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1E04015C,0x00000002 ++#define IPU_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1E04015C,0x00000001 ++ ++#define IPU_DI0_SSC__ADDR 0x1E040160 ++#define IPU_DI0_SSC__EMPTY 0x1E040160,0x00000000 ++#define IPU_DI0_SSC__FULL 0x1E040160,0xffffffff ++#define IPU_DI0_SSC__DI0_PIN17_ERM 0x1E040160,0x00800000 ++#define IPU_DI0_SSC__DI0_PIN16_ERM 0x1E040160,0x00400000 ++#define IPU_DI0_SSC__DI0_PIN15_ERM 0x1E040160,0x00200000 ++#define IPU_DI0_SSC__DI0_PIN14_ERM 0x1E040160,0x00100000 ++#define IPU_DI0_SSC__DI0_PIN13_ERM 0x1E040160,0x00080000 ++#define IPU_DI0_SSC__DI0_PIN12_ERM 0x1E040160,0x00040000 ++#define IPU_DI0_SSC__DI0_PIN11_ERM 0x1E040160,0x00020000 ++#define IPU_DI0_SSC__DI0_CS_ERM 0x1E040160,0x00010000 ++#define IPU_DI0_SSC__DI0_WAIT_ON 0x1E040160,0x00000020 ++#define IPU_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1E040160,0x00000008 ++#define IPU_DI0_SSC__DI0_BYTE_EN_PNTR 0x1E040160,0x00000007 ++ ++#define IPU_DI0_POL__ADDR 0x1E040164 ++#define IPU_DI0_POL__EMPTY 0x1E040164,0x00000000 ++#define IPU_DI0_POL__FULL 0x1E040164,0xffffffff ++#define IPU_DI0_POL__DI0_WAIT_POLARITY 0x1E040164,0x04000000 ++#define IPU_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1E040164,0x02000000 ++#define IPU_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1E040164,0x01000000 ++#define IPU_DI0_POL__DI0_CS1_DATA_POLARITY 0x1E040164,0x00800000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_17 0x1E040164,0x00400000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_16 0x1E040164,0x00200000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_15 0x1E040164,0x00100000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_14 0x1E040164,0x00080000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_13 0x1E040164,0x00040000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_12 0x1E040164,0x00020000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_11 0x1E040164,0x00010000 ++#define IPU_DI0_POL__DI0_CS0_DATA_POLARITY 0x1E040164,0x00008000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_17 0x1E040164,0x00004000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_16 0x1E040164,0x00002000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_15 0x1E040164,0x00001000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_14 0x1E040164,0x00000800 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_13 0x1E040164,0x00000400 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_12 0x1E040164,0x00000200 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_11 0x1E040164,0x00000100 ++#define IPU_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1E040164,0x00000080 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_17 0x1E040164,0x00000040 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_16 0x1E040164,0x00000020 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_15 0x1E040164,0x00000010 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_14 0x1E040164,0x00000008 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_13 0x1E040164,0x00000004 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_12 0x1E040164,0x00000002 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_11 0x1E040164,0x00000001 ++ ++#define IPU_DI0_AW0__ADDR 0x1E040168 ++#define IPU_DI0_AW0__EMPTY 0x1E040168,0x00000000 ++#define IPU_DI0_AW0__FULL 0x1E040168,0xffffffff ++#define IPU_DI0_AW0__DI0_AW_TRIG_SEL 0x1E040168,0xF0000000 ++#define IPU_DI0_AW0__DI0_AW_HEND 0x1E040168,0x0FFF0000 ++#define IPU_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1E040168,0x0000F000 ++#define IPU_DI0_AW0__DI0_AW_HSTART 0x1E040168,0x00000FFF ++ ++#define IPU_DI0_AW1__ADDR 0x1E04016C ++#define IPU_DI0_AW1__EMPTY 0x1E04016C,0x00000000 ++#define IPU_DI0_AW1__FULL 0x1E04016C,0xffffffff ++#define IPU_DI0_AW1__DI0_AW_VEND 0x1E04016C,0x0FFF0000 ++#define IPU_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1E04016C,0x0000F000 ++#define IPU_DI0_AW1__DI0_AW_VSTART 0x1E04016C,0x00000FFF ++ ++#define IPU_DI0_SCR_CONF__ADDR 0x1E040170 ++#define IPU_DI0_SCR_CONF__EMPTY 0x1E040170,0x00000000 ++#define IPU_DI0_SCR_CONF__FULL 0x1E040170,0xffffffff ++#define IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1E040170,0x00000FFF ++ ++#define IPU_DI0_STAT__ADDR 0x1E040174 ++#define IPU_DI0_STAT__EMPTY 0x1E040174,0x00000000 ++#define IPU_DI0_STAT__FULL 0x1E040174,0xffffffff ++#define IPU_DI0_STAT__DI0_CNTR_FIFO_FULL 0x1E040174,0x00000008 ++#define IPU_DI0_STAT__DI0_CNTR_FIFO_EMPTY 0x1E040174,0x00000004 ++#define IPU_DI0_STAT__DI0_READ_FIFO_FULL 0x1E040174,0x00000002 ++#define IPU_DI0_STAT__DI0_READ_FIFO_EMPTY 0x1E040174,0x00000001 ++ ++#define IPU_DI1_GENERAL__ADDR 0x1E048000 ++#define IPU_DI1_GENERAL__EMPTY 0x1E048000,0x00000000 ++#define IPU_DI1_GENERAL__FULL 0x1E048000,0xffffffff ++#define IPU_DI1_GENERAL__DI1_DISP_Y_SEL 0x1E048000,0x70000000 ++#define IPU_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1E048000,0x0F000000 ++#define IPU_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1E048000,0x00800000 ++#define IPU_DI1_GENERAL__DI1_MASK_SEL 0x1E048000,0x00400000 ++#define IPU_DI1_GENERAL__DI1_VSYNC_EXT 0x1E048000,0x00200000 ++#define IPU_DI1_GENERAL__DI1_CLK_EXT 0x1E048000,0x00100000 ++#define IPU_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1E048000,0x000C0000 ++#define IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1E048000,0x00020000 ++#define IPU_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1E048000,0x0000F000 ++#define IPU_DI1_GENERAL__DI1_ERR_TREATMENT 0x1E048000,0x00000800 ++#define IPU_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1E048000,0x00000400 ++#define IPU_DI1_GENERAL__DI1_POLARITY_CS1 0x1E048000,0x00000200 ++#define IPU_DI1_GENERAL__DI1_POLARITY_CS0 0x1E048000,0x00000100 ++#define IPU_DI1_GENERAL__DI1_POLARITY_8 0x1E048000,0x00000080 ++#define IPU_DI1_GENERAL__DI1_POLARITY_7 0x1E048000,0x00000040 ++#define IPU_DI1_GENERAL__DI1_POLARITY_6 0x1E048000,0x00000020 ++#define IPU_DI1_GENERAL__DI1_POLARITY_5 0x1E048000,0x00000010 ++#define IPU_DI1_GENERAL__DI1_POLARITY_4 0x1E048000,0x00000008 ++#define IPU_DI1_GENERAL__DI1_POLARITY_3 0x1E048000,0x00000004 ++#define IPU_DI1_GENERAL__DI1_POLARITY_2 0x1E048000,0x00000002 ++#define IPU_DI1_GENERAL__DI1_POLARITY_1 0x1E048000,0x00000001 ++ ++#define IPU_DI1_BS_CLKGEN0__ADDR 0x1E048004 ++#define IPU_DI1_BS_CLKGEN0__EMPTY 0x1E048004,0x00000000 ++#define IPU_DI1_BS_CLKGEN0__FULL 0x1E048004,0xffffffff ++#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1E048004,0x01FF0000 ++#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1E048004,0x00000FFF ++ ++#define IPU_DI1_BS_CLKGEN1__ADDR 0x1E048008 ++#define IPU_DI1_BS_CLKGEN1__EMPTY 0x1E048008,0x00000000 ++#define IPU_DI1_BS_CLKGEN1__FULL 0x1E048008,0xffffffff ++#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1E048008,0x01FF0000 ++#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1E048008,0x000001FF ++ ++#define IPU_DI1_SW_GEN0_9__ADDR 0x1E04802C ++#define IPU_DI1_SW_GEN0_9__EMPTY 0x1E04802C,0x00000000 ++#define IPU_DI1_SW_GEN0_9__FULL 0x1E04802C,0xffffffff ++#define IPU_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1E04802C,0x7FF80000 ++#define IPU_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1E04802C,0x00070000 ++#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1E04802C,0x00007FF8 ++#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1E04802C,0x00000007 ++ ++#define IPU_DI1_SW_GEN1_9__ADDR 0x1E048050 ++#define IPU_DI1_SW_GEN1_9__EMPTY 0x1E048050,0x00000000 ++#define IPU_DI1_SW_GEN1_9__FULL 0x1E048050,0xffffffff ++#define IPU_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1E048050,0xE0000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1E048050,0x10000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1E048050,0x0E000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1E048050,0x01FF0000 ++#define IPU_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1E048050,0x00008000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1E048050,0x000001FF ++ ++#define IPU_DI1_SYNC_AS_GEN__ADDR 0x1E048054 ++#define IPU_DI1_SYNC_AS_GEN__EMPTY 0x1E048054,0x00000000 ++#define IPU_DI1_SYNC_AS_GEN__FULL 0x1E048054,0xffffffff ++#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1E048054,0x10000000 ++#define IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1E048054,0x0000E000 ++#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1E048054,0x00000FFF ++ ++#define IPU_DI1_DW_GEN_0__ADDR 0x1E048058 ++#define IPU_DI1_DW_GEN_0__EMPTY 0x1E048058,0x00000000 ++#define IPU_DI1_DW_GEN_0__FULL 0x1E048058,0xffffffff ++#define IPU_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1E048058,0xFF000000 ++#define IPU_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1E048058,0x00FF0000 ++#define IPU_DI1_DW_GEN_0__DI1_CST_0 0x1E048058,0x0000C000 ++#define IPU_DI1_DW_GEN_0__DI1_PT_6_0 0x1E048058,0x00003000 ++#define IPU_DI1_DW_GEN_0__DI1_PT_5_0 0x1E048058,0x00000C00 ++#define IPU_DI1_DW_GEN_0__DI1_PT_4_0 0x1E048058,0x00000300 ++#define IPU_DI1_DW_GEN_0__DI1_PT_3_0 0x1E048058,0x000000C0 ++#define IPU_DI1_DW_GEN_0__DI1_PT_2_0 0x1E048058,0x00000030 ++#define IPU_DI1_DW_GEN_0__DI1_PT_1_0 0x1E048058,0x0000000C ++#define IPU_DI1_DW_GEN_0__DI1_PT_0_0 0x1E048058,0x00000003 ++ ++#define IPU_DI1_DW_GEN_0__ADDR 0x1E048058 ++#define IPU_DI1_DW_GEN_0__EMPTY 0x1E048058,0x00000000 ++#define IPU_DI1_DW_GEN_0__FULL 0x1E048058,0xffffffff ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1E048058,0xFF000000 ++#define IPU_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1E048058,0x00FF0000 ++#define IPU_DI1_DW_GEN_0__DI1_CST_0 0x1E048058,0x0000C000 ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1E048058,0x000001F0 ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1E048058,0x0000000C ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1E048058,0x00000003 ++ ++#define IPU_DI1_DW_GEN_1__ADDR 0x1E04805C ++#define IPU_DI1_DW_GEN_1__EMPTY 0x1E04805C,0x00000000 ++#define IPU_DI1_DW_GEN_1__FULL 0x1E04805C,0xffffffff ++#define IPU_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1E04805C,0xFF000000 ++#define IPU_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1E04805C,0x00FF0000 ++#define IPU_DI1_DW_GEN_1__DI1_CST_1 0x1E04805C,0x0000C000 ++#define IPU_DI1_DW_GEN_1__DI1_PT_6_1 0x1E04805C,0x00003000 ++#define IPU_DI1_DW_GEN_1__DI1_PT_5_1 0x1E04805C,0x00000C00 ++#define IPU_DI1_DW_GEN_1__DI1_PT_4_1 0x1E04805C,0x00000300 ++#define IPU_DI1_DW_GEN_1__DI1_PT_3_1 0x1E04805C,0x000000C0 ++#define IPU_DI1_DW_GEN_1__DI1_PT_2_1 0x1E04805C,0x00000030 ++#define IPU_DI1_DW_GEN_1__DI1_PT_1_1 0x1E04805C,0x0000000C ++#define IPU_DI1_DW_GEN_1__DI1_PT_0_1 0x1E04805C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_1__ADDR 0x1E04805C ++#define IPU_DI1_DW_GEN_1__EMPTY 0x1E04805C,0x00000000 ++#define IPU_DI1_DW_GEN_1__FULL 0x1E04805C,0xffffffff ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1E04805C,0xFF000000 ++#define IPU_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1E04805C,0x00FF0000 ++#define IPU_DI1_DW_GEN_1__DI1_CST_1 0x1E04805C,0x0000C000 ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1E04805C,0x000001F0 ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1E04805C,0x0000000C ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1E04805C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_2__ADDR 0x1E048060 ++#define IPU_DI1_DW_GEN_2__EMPTY 0x1E048060,0x00000000 ++#define IPU_DI1_DW_GEN_2__FULL 0x1E048060,0xffffffff ++#define IPU_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1E048060,0xFF000000 ++#define IPU_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1E048060,0x00FF0000 ++#define IPU_DI1_DW_GEN_2__DI1_CST_2 0x1E048060,0x0000C000 ++#define IPU_DI1_DW_GEN_2__DI1_PT_6_2 0x1E048060,0x00003000 ++#define IPU_DI1_DW_GEN_2__DI1_PT_5_2 0x1E048060,0x00000C00 ++#define IPU_DI1_DW_GEN_2__DI1_PT_4_2 0x1E048060,0x00000300 ++#define IPU_DI1_DW_GEN_2__DI1_PT_3_2 0x1E048060,0x000000C0 ++#define IPU_DI1_DW_GEN_2__DI1_PT_2_2 0x1E048060,0x00000030 ++#define IPU_DI1_DW_GEN_2__DI1_PT_1_2 0x1E048060,0x0000000C ++#define IPU_DI1_DW_GEN_2__DI1_PT_0_2 0x1E048060,0x00000003 ++ ++#define IPU_DI1_DW_GEN_2__ADDR 0x1E048060 ++#define IPU_DI1_DW_GEN_2__EMPTY 0x1E048060,0x00000000 ++#define IPU_DI1_DW_GEN_2__FULL 0x1E048060,0xffffffff ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1E048060,0xFF000000 ++#define IPU_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1E048060,0x00FF0000 ++#define IPU_DI1_DW_GEN_2__DI1_CST_2 0x1E048060,0x0000C000 ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1E048060,0x000001F0 ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1E048060,0x0000000C ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1E048060,0x00000003 ++ ++#define IPU_DI1_DW_GEN_3__ADDR 0x1E048064 ++#define IPU_DI1_DW_GEN_3__EMPTY 0x1E048064,0x00000000 ++#define IPU_DI1_DW_GEN_3__FULL 0x1E048064,0xffffffff ++#define IPU_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1E048064,0xFF000000 ++#define IPU_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1E048064,0x00FF0000 ++#define IPU_DI1_DW_GEN_3__DI1_CST_3 0x1E048064,0x0000C000 ++#define IPU_DI1_DW_GEN_3__DI1_PT_6_3 0x1E048064,0x00003000 ++#define IPU_DI1_DW_GEN_3__DI1_PT_5_3 0x1E048064,0x00000C00 ++#define IPU_DI1_DW_GEN_3__DI1_PT_4_3 0x1E048064,0x00000300 ++#define IPU_DI1_DW_GEN_3__DI1_PT_3_3 0x1E048064,0x000000C0 ++#define IPU_DI1_DW_GEN_3__DI1_PT_2_3 0x1E048064,0x00000030 ++#define IPU_DI1_DW_GEN_3__DI1_PT_1_3 0x1E048064,0x0000000C ++#define IPU_DI1_DW_GEN_3__DI1_PT_0_3 0x1E048064,0x00000003 ++ ++#define IPU_DI1_DW_GEN_3__ADDR 0x1E048064 ++#define IPU_DI1_DW_GEN_3__EMPTY 0x1E048064,0x00000000 ++#define IPU_DI1_DW_GEN_3__FULL 0x1E048064,0xffffffff ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1E048064,0xFF000000 ++#define IPU_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1E048064,0x00FF0000 ++#define IPU_DI1_DW_GEN_3__DI1_CST_3 0x1E048064,0x0000C000 ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1E048064,0x000001F0 ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1E048064,0x0000000C ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1E048064,0x00000003 ++ ++#define IPU_DI1_DW_GEN_4__ADDR 0x1E048068 ++#define IPU_DI1_DW_GEN_4__EMPTY 0x1E048068,0x00000000 ++#define IPU_DI1_DW_GEN_4__FULL 0x1E048068,0xffffffff ++#define IPU_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1E048068,0xFF000000 ++#define IPU_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1E048068,0x00FF0000 ++#define IPU_DI1_DW_GEN_4__DI1_CST_4 0x1E048068,0x0000C000 ++#define IPU_DI1_DW_GEN_4__DI1_PT_6_4 0x1E048068,0x00003000 ++#define IPU_DI1_DW_GEN_4__DI1_PT_5_4 0x1E048068,0x00000C00 ++#define IPU_DI1_DW_GEN_4__DI1_PT_4_4 0x1E048068,0x00000300 ++#define IPU_DI1_DW_GEN_4__DI1_PT_3_4 0x1E048068,0x000000C0 ++#define IPU_DI1_DW_GEN_4__DI1_PT_2_4 0x1E048068,0x00000030 ++#define IPU_DI1_DW_GEN_4__DI1_PT_1_4 0x1E048068,0x0000000C ++#define IPU_DI1_DW_GEN_4__DI1_PT_0_4 0x1E048068,0x00000003 ++ ++#define IPU_DI1_DW_GEN_4__ADDR 0x1E048068 ++#define IPU_DI1_DW_GEN_4__EMPTY 0x1E048068,0x00000000 ++#define IPU_DI1_DW_GEN_4__FULL 0x1E048068,0xffffffff ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1E048068,0xFF000000 ++#define IPU_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1E048068,0x00FF0000 ++#define IPU_DI1_DW_GEN_4__DI1_CST_4 0x1E048068,0x0000C000 ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1E048068,0x000001F0 ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1E048068,0x0000000C ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1E048068,0x00000003 ++ ++#define IPU_DI1_DW_GEN_5__ADDR 0x1E04806C ++#define IPU_DI1_DW_GEN_5__EMPTY 0x1E04806C,0x00000000 ++#define IPU_DI1_DW_GEN_5__FULL 0x1E04806C,0xffffffff ++#define IPU_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1E04806C,0xFF000000 ++#define IPU_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1E04806C,0x00FF0000 ++#define IPU_DI1_DW_GEN_5__DI1_CST_5 0x1E04806C,0x0000C000 ++#define IPU_DI1_DW_GEN_5__DI1_PT_6_5 0x1E04806C,0x00003000 ++#define IPU_DI1_DW_GEN_5__DI1_PT_5_5 0x1E04806C,0x00000C00 ++#define IPU_DI1_DW_GEN_5__DI1_PT_4_5 0x1E04806C,0x00000300 ++#define IPU_DI1_DW_GEN_5__DI1_PT_3_5 0x1E04806C,0x000000C0 ++#define IPU_DI1_DW_GEN_5__DI1_PT_2_5 0x1E04806C,0x00000030 ++#define IPU_DI1_DW_GEN_5__DI1_PT_1_5 0x1E04806C,0x0000000C ++#define IPU_DI1_DW_GEN_5__DI1_PT_0_5 0x1E04806C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_5__ADDR 0x1E04806C ++#define IPU_DI1_DW_GEN_5__EMPTY 0x1E04806C,0x00000000 ++#define IPU_DI1_DW_GEN_5__FULL 0x1E04806C,0xffffffff ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1E04806C,0xFF000000 ++#define IPU_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1E04806C,0x00FF0000 ++#define IPU_DI1_DW_GEN_5__DI1_CST_5 0x1E04806C,0x0000C000 ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1E04806C,0x000001F0 ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1E04806C,0x0000000C ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1E04806C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_6__ADDR 0x1E048070 ++#define IPU_DI1_DW_GEN_6__EMPTY 0x1E048070,0x00000000 ++#define IPU_DI1_DW_GEN_6__FULL 0x1E048070,0xffffffff ++#define IPU_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1E048070,0xFF000000 ++#define IPU_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1E048070,0x00FF0000 ++#define IPU_DI1_DW_GEN_6__DI1_CST_6 0x1E048070,0x0000C000 ++#define IPU_DI1_DW_GEN_6__DI1_PT_6_6 0x1E048070,0x00003000 ++#define IPU_DI1_DW_GEN_6__DI1_PT_5_6 0x1E048070,0x00000C00 ++#define IPU_DI1_DW_GEN_6__DI1_PT_4_6 0x1E048070,0x00000300 ++#define IPU_DI1_DW_GEN_6__DI1_PT_3_6 0x1E048070,0x000000C0 ++#define IPU_DI1_DW_GEN_6__DI1_PT_2_6 0x1E048070,0x00000030 ++#define IPU_DI1_DW_GEN_6__DI1_PT_1_6 0x1E048070,0x0000000C ++#define IPU_DI1_DW_GEN_6__DI1_PT_0_6 0x1E048070,0x00000003 ++ ++#define IPU_DI1_DW_GEN_6__ADDR 0x1E048070 ++#define IPU_DI1_DW_GEN_6__EMPTY 0x1E048070,0x00000000 ++#define IPU_DI1_DW_GEN_6__FULL 0x1E048070,0xffffffff ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1E048070,0xFF000000 ++#define IPU_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1E048070,0x00FF0000 ++#define IPU_DI1_DW_GEN_6__DI1_CST_6 0x1E048070,0x0000C000 ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1E048070,0x000001F0 ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1E048070,0x0000000C ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1E048070,0x00000003 ++ ++#define IPU_DI1_DW_GEN_7__ADDR 0x1E048074 ++#define IPU_DI1_DW_GEN_7__EMPTY 0x1E048074,0x00000000 ++#define IPU_DI1_DW_GEN_7__FULL 0x1E048074,0xffffffff ++#define IPU_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1E048074,0xFF000000 ++#define IPU_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1E048074,0x00FF0000 ++#define IPU_DI1_DW_GEN_7__DI1_CST_7 0x1E048074,0x0000C000 ++#define IPU_DI1_DW_GEN_7__DI1_PT_6_7 0x1E048074,0x00003000 ++#define IPU_DI1_DW_GEN_7__DI1_PT_5_7 0x1E048074,0x00000C00 ++#define IPU_DI1_DW_GEN_7__DI1_PT_4_7 0x1E048074,0x00000300 ++#define IPU_DI1_DW_GEN_7__DI1_PT_3_7 0x1E048074,0x000000C0 ++#define IPU_DI1_DW_GEN_7__DI1_PT_2_7 0x1E048074,0x00000030 ++#define IPU_DI1_DW_GEN_7__DI1_PT_1_7 0x1E048074,0x0000000C ++#define IPU_DI1_DW_GEN_7__DI1_PT_0_7 0x1E048074,0x00000003 ++ ++#define IPU_DI1_DW_GEN_7__ADDR 0x1E048074 ++#define IPU_DI1_DW_GEN_7__EMPTY 0x1E048074,0x00000000 ++#define IPU_DI1_DW_GEN_7__FULL 0x1E048074,0xffffffff ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1E048074,0xFF000000 ++#define IPU_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1E048074,0x00FF0000 ++#define IPU_DI1_DW_GEN_7__DI1_CST_7 0x1E048074,0x0000C000 ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1E048074,0x000001F0 ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1E048074,0x0000000C ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1E048074,0x00000003 ++ ++#define IPU_DI1_DW_GEN_8__ADDR 0x1E048078 ++#define IPU_DI1_DW_GEN_8__EMPTY 0x1E048078,0x00000000 ++#define IPU_DI1_DW_GEN_8__FULL 0x1E048078,0xffffffff ++#define IPU_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1E048078,0xFF000000 ++#define IPU_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1E048078,0x00FF0000 ++#define IPU_DI1_DW_GEN_8__DI1_CST_8 0x1E048078,0x0000C000 ++#define IPU_DI1_DW_GEN_8__DI1_PT_6_8 0x1E048078,0x00003000 ++#define IPU_DI1_DW_GEN_8__DI1_PT_5_8 0x1E048078,0x00000C00 ++#define IPU_DI1_DW_GEN_8__DI1_PT_4_8 0x1E048078,0x00000300 ++#define IPU_DI1_DW_GEN_8__DI1_PT_3_8 0x1E048078,0x000000C0 ++#define IPU_DI1_DW_GEN_8__DI1_PT_2_8 0x1E048078,0x00000030 ++#define IPU_DI1_DW_GEN_8__DI1_PT_1_8 0x1E048078,0x0000000C ++#define IPU_DI1_DW_GEN_8__DI1_PT_0_8 0x1E048078,0x00000003 ++ ++#define IPU_DI1_DW_GEN_8__ADDR 0x1E048078 ++#define IPU_DI1_DW_GEN_8__EMPTY 0x1E048078,0x00000000 ++#define IPU_DI1_DW_GEN_8__FULL 0x1E048078,0xffffffff ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1E048078,0xFF000000 ++#define IPU_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1E048078,0x00FF0000 ++#define IPU_DI1_DW_GEN_8__DI1_CST_8 0x1E048078,0x0000C000 ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1E048078,0x000001F0 ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1E048078,0x0000000C ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1E048078,0x00000003 ++ ++#define IPU_DI1_DW_GEN_9__ADDR 0x1E04807C ++#define IPU_DI1_DW_GEN_9__EMPTY 0x1E04807C,0x00000000 ++#define IPU_DI1_DW_GEN_9__FULL 0x1E04807C,0xffffffff ++#define IPU_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1E04807C,0xFF000000 ++#define IPU_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1E04807C,0x00FF0000 ++#define IPU_DI1_DW_GEN_9__DI1_CST_9 0x1E04807C,0x0000C000 ++#define IPU_DI1_DW_GEN_9__DI1_PT_6_9 0x1E04807C,0x00003000 ++#define IPU_DI1_DW_GEN_9__DI1_PT_5_9 0x1E04807C,0x00000C00 ++#define IPU_DI1_DW_GEN_9__DI1_PT_4_9 0x1E04807C,0x00000300 ++#define IPU_DI1_DW_GEN_9__DI1_PT_3_9 0x1E04807C,0x000000C0 ++#define IPU_DI1_DW_GEN_9__DI1_PT_2_9 0x1E04807C,0x00000030 ++#define IPU_DI1_DW_GEN_9__DI1_PT_1_9 0x1E04807C,0x0000000C ++#define IPU_DI1_DW_GEN_9__DI1_PT_0_9 0x1E04807C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_9__ADDR 0x1E04807C ++#define IPU_DI1_DW_GEN_9__EMPTY 0x1E04807C,0x00000000 ++#define IPU_DI1_DW_GEN_9__FULL 0x1E04807C,0xffffffff ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1E04807C,0xFF000000 ++#define IPU_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1E04807C,0x00FF0000 ++#define IPU_DI1_DW_GEN_9__DI1_CST_9 0x1E04807C,0x0000C000 ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1E04807C,0x000001F0 ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1E04807C,0x0000000C ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1E04807C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_10__ADDR 0x1E048080 ++#define IPU_DI1_DW_GEN_10__EMPTY 0x1E048080,0x00000000 ++#define IPU_DI1_DW_GEN_10__FULL 0x1E048080,0xffffffff ++#define IPU_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1E048080,0xFF000000 ++#define IPU_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1E048080,0x00FF0000 ++#define IPU_DI1_DW_GEN_10__DI1_CST_10 0x1E048080,0x0000C000 ++#define IPU_DI1_DW_GEN_10__DI1_PT_6_10 0x1E048080,0x00003000 ++#define IPU_DI1_DW_GEN_10__DI1_PT_5_10 0x1E048080,0x00000C00 ++#define IPU_DI1_DW_GEN_10__DI1_PT_4_10 0x1E048080,0x00000300 ++#define IPU_DI1_DW_GEN_10__DI1_PT_3_10 0x1E048080,0x000000C0 ++#define IPU_DI1_DW_GEN_10__DI1_PT_2_10 0x1E048080,0x00000030 ++#define IPU_DI1_DW_GEN_10__DI1_PT_1_10 0x1E048080,0x0000000C ++#define IPU_DI1_DW_GEN_10__DI1_PT_0_10 0x1E048080,0x00000003 ++ ++#define IPU_DI1_DW_GEN_10__ADDR 0x1E048080 ++#define IPU_DI1_DW_GEN_10__EMPTY 0x1E048080,0x00000000 ++#define IPU_DI1_DW_GEN_10__FULL 0x1E048080,0xffffffff ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1E048080,0xFF000000 ++#define IPU_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1E048080,0x00FF0000 ++#define IPU_DI1_DW_GEN_10__DI1_CST_10 0x1E048080,0x0000C000 ++#define IPU_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E048080,0x000001F0 ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1E048080,0x0000000C ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1E048080,0x00000003 ++ ++#define IPU_DI1_DW_GEN_11__ADDR 0x1E048084 ++#define IPU_DI1_DW_GEN_11__EMPTY 0x1E048084,0x00000000 ++#define IPU_DI1_DW_GEN_11__FULL 0x1E048084,0xffffffff ++#define IPU_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1E048084,0xFF000000 ++#define IPU_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1E048084,0x00FF0000 ++#define IPU_DI1_DW_GEN_11__DI1_CST_11 0x1E048084,0x0000C000 ++#define IPU_DI1_DW_GEN_11__DI1_PT_6_11 0x1E048084,0x00003000 ++#define IPU_DI1_DW_GEN_11__DI1_PT_5_11 0x1E048084,0x00000C00 ++#define IPU_DI1_DW_GEN_11__DI1_PT_4_11 0x1E048084,0x00000300 ++#define IPU_DI1_DW_GEN_11__DI1_PT_3_11 0x1E048084,0x000000C0 ++#define IPU_DI1_DW_GEN_11__DI1_PT_2_11 0x1E048084,0x00000030 ++#define IPU_DI1_DW_GEN_11__DI1_PT_1_11 0x1E048084,0x0000000C ++#define IPU_DI1_DW_GEN_11__DI1_PT_0_11 0x1E048084,0x00000003 ++ ++#define IPU_DI1_DW_GEN_11__ADDR 0x1E048084 ++#define IPU_DI1_DW_GEN_11__EMPTY 0x1E048084,0x00000000 ++#define IPU_DI1_DW_GEN_11__FULL 0x1E048084,0xffffffff ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1E048084,0xFF000000 ++#define IPU_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1E048084,0x00FF0000 ++#define IPU_DI1_DW_GEN_11__DI1_CST_11 0x1E048084,0x0000C000 ++#define IPU_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E048084,0x000001F0 ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1E048084,0x0000000C ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1E048084,0x00000003 ++ ++#define IPU_DI1_STP_REP_9__ADDR 0x1E048158 ++#define IPU_DI1_STP_REP_9__EMPTY 0x1E048158,0x00000000 ++#define IPU_DI1_STP_REP_9__FULL 0x1E048158,0xffffffff ++#define IPU_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1E048158,0x00000FFF ++ ++#define IPU_DI1_SER_CONF__ADDR 0x1E04815C ++#define IPU_DI1_SER_CONF__EMPTY 0x1E04815C,0x00000000 ++#define IPU_DI1_SER_CONF__FULL 0x1E04815C,0xffffffff ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1E04815C,0xF0000000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1E04815C,0x0F000000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1E04815C,0x00F00000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1E04815C,0x000F0000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1E04815C,0x0000FF00 ++#define IPU_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1E04815C,0x00000020 ++#define IPU_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1E04815C,0x00000010 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1E04815C,0x00000008 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1E04815C,0x00000004 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1E04815C,0x00000002 ++#define IPU_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1E04815C,0x00000001 ++ ++#define IPU_DI1_SSC__ADDR 0x1E048160 ++#define IPU_DI1_SSC__EMPTY 0x1E048160,0x00000000 ++#define IPU_DI1_SSC__FULL 0x1E048160,0xffffffff ++#define IPU_DI1_SSC__DI1_PIN17_ERM 0x1E048160,0x00800000 ++#define IPU_DI1_SSC__DI1_PIN16_ERM 0x1E048160,0x00400000 ++#define IPU_DI1_SSC__DI1_PIN15_ERM 0x1E048160,0x00200000 ++#define IPU_DI1_SSC__DI1_PIN14_ERM 0x1E048160,0x00100000 ++#define IPU_DI1_SSC__DI1_PIN13_ERM 0x1E048160,0x00080000 ++#define IPU_DI1_SSC__DI1_PIN12_ERM 0x1E048160,0x00040000 ++#define IPU_DI1_SSC__DI1_PIN11_ERM 0x1E048160,0x00020000 ++#define IPU_DI1_SSC__DI1_CS_ERM 0x1E048160,0x00010000 ++#define IPU_DI1_SSC__DI1_WAIT_ON 0x1E048160,0x00000020 ++#define IPU_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1E048160,0x00000008 ++#define IPU_DI1_SSC__DI1_BYTE_EN_PNTR 0x1E048160,0x00000007 ++ ++#define IPU_DI1_POL__ADDR 0x1E048164 ++#define IPU_DI1_POL__EMPTY 0x1E048164,0x00000000 ++#define IPU_DI1_POL__FULL 0x1E048164,0xffffffff ++#define IPU_DI1_POL__DI1_WAIT_POLARITY 0x1E048164,0x04000000 ++#define IPU_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1E048164,0x02000000 ++#define IPU_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1E048164,0x01000000 ++#define IPU_DI1_POL__DI1_CS1_DATA_POLARITY 0x1E048164,0x00800000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_17 0x1E048164,0x00400000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_16 0x1E048164,0x00200000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_15 0x1E048164,0x00100000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_14 0x1E048164,0x00080000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_13 0x1E048164,0x00040000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_12 0x1E048164,0x00020000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_11 0x1E048164,0x00010000 ++#define IPU_DI1_POL__DI1_CS0_DATA_POLARITY 0x1E048164,0x00008000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_17 0x1E048164,0x00004000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_16 0x1E048164,0x00002000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_15 0x1E048164,0x00001000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_14 0x1E048164,0x00000800 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_13 0x1E048164,0x00000400 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_12 0x1E048164,0x00000200 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_11 0x1E048164,0x00000100 ++#define IPU_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1E048164,0x00000080 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_17 0x1E048164,0x00000040 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_16 0x1E048164,0x00000020 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_15 0x1E048164,0x00000010 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_14 0x1E048164,0x00000008 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_13 0x1E048164,0x00000004 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_12 0x1E048164,0x00000002 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_11 0x1E048164,0x00000001 ++ ++#define IPU_DI1_AW0__ADDR 0x1E048168 ++#define IPU_DI1_AW0__EMPTY 0x1E048168,0x00000000 ++#define IPU_DI1_AW0__FULL 0x1E048168,0xffffffff ++#define IPU_DI1_AW0__DI1_AW_TRIG_SEL 0x1E048168,0xF0000000 ++#define IPU_DI1_AW0__DI1_AW_HEND 0x1E048168,0x0FFF0000 ++#define IPU_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1E048168,0x0000F000 ++#define IPU_DI1_AW0__DI1_AW_HSTART 0x1E048168,0x00000FFF ++ ++#define IPU_DI1_AW1__ADDR 0x1E04816C ++#define IPU_DI1_AW1__EMPTY 0x1E04816C,0x00000000 ++#define IPU_DI1_AW1__FULL 0x1E04816C,0xffffffff ++#define IPU_DI1_AW1__DI1_AW_VEND 0x1E04816C,0x0FFF0000 ++#define IPU_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1E04816C,0x0000F000 ++#define IPU_DI1_AW1__DI1_AW_VSTART 0x1E04816C,0x00000FFF ++ ++#define IPU_DI1_SCR_CONF__ADDR 0x1E048170 ++#define IPU_DI1_SCR_CONF__EMPTY 0x1E048170,0x00000000 ++#define IPU_DI1_SCR_CONF__FULL 0x1E048170,0xffffffff ++#define IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1E048170,0x00000FFF ++ ++#define IPU_DI1_STAT__ADDR 0x1E048174 ++#define IPU_DI1_STAT__EMPTY 0x1E048174,0x00000000 ++#define IPU_DI1_STAT__FULL 0x1E048174,0xffffffff ++#define IPU_DI1_STAT__DI1_CNTR_FIFO_FULL 0x1E048174,0x00000008 ++#define IPU_DI1_STAT__DI1_CNTR_FIFO_EMPTY 0x1E048174,0x00000004 ++#define IPU_DI1_STAT__DI1_READ_FIFO_FULL 0x1E048174,0x00000002 ++#define IPU_DI1_STAT__DI1_READ_FIFO_EMPTY 0x1E048174,0x00000001 ++ ++#define IPU_DC_READ_CH_CONF__ADDR 0x1E058000 ++#define IPU_DC_READ_CH_CONF__EMPTY 0x1E058000,0x00000000 ++#define IPU_DC_READ_CH_CONF__FULL 0x1E058000,0xffffffff ++#define IPU_DC_READ_CH_CONF__TIME_OUT_VALUE 0x1E058000,0xFFFF0000 ++#define IPU_DC_READ_CH_CONF__CS_ID_3 0x1E058000,0x00000800 ++#define IPU_DC_READ_CH_CONF__CS_ID_2 0x1E058000,0x00000400 ++#define IPU_DC_READ_CH_CONF__CS_ID_1 0x1E058000,0x00000200 ++#define IPU_DC_READ_CH_CONF__CS_ID_0 0x1E058000,0x00000100 ++#define IPU_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1E058000,0x00000040 ++#define IPU_DC_READ_CH_CONF__W_SIZE_0 0x1E058000,0x00000030 ++#define IPU_DC_READ_CH_CONF__PROG_DISP_ID_0 0x1E058000,0x0000000C ++#define IPU_DC_READ_CH_CONF__PROG_DI_ID_0 0x1E058000,0x00000002 ++#define IPU_DC_READ_CH_CONF__RD_CHANNEL_EN 0x1E058000,0x00000001 ++ ++#define IPU_DC_READ_CH_ADDR__ADDR 0x1E058004 ++#define IPU_DC_READ_CH_ADDR__EMPTY 0x1E058004,0x00000000 ++#define IPU_DC_READ_CH_ADDR__FULL 0x1E058004,0xffffffff ++#define IPU_DC_READ_CH_ADDR__ST_ADDR_0 0x1E058004,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_0__ADDR 0x1E058008 ++#define IPU_DC_RL0_CH_0__EMPTY 0x1E058008,0x00000000 ++#define IPU_DC_RL0_CH_0__FULL 0x1E058008,0xffffffff ++#define IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0 0x1E058008,0xFF000000 ++#define IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1E058008,0x000F0000 ++#define IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0 0x1E058008,0x0000FF00 ++#define IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1E058008,0x0000000F ++ ++#define IPU_DC_RL1_CH_0__ADDR 0x1E05800C ++#define IPU_DC_RL1_CH_0__EMPTY 0x1E05800C,0x00000000 ++#define IPU_DC_RL1_CH_0__FULL 0x1E05800C,0xffffffff ++#define IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0 0x1E05800C,0xFF000000 ++#define IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1E05800C,0x000F0000 ++#define IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0 0x1E05800C,0x0000FF00 ++#define IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0 0x1E05800C,0x0000000F ++ ++#define IPU_DC_RL2_CH_0__ADDR 0x1E058010 ++#define IPU_DC_RL2_CH_0__EMPTY 0x1E058010,0x00000000 ++#define IPU_DC_RL2_CH_0__FULL 0x1E058010,0xffffffff ++#define IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0 0x1E058010,0xFF000000 ++#define IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1E058010,0x000F0000 ++#define IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0 0x1E058010,0x0000FF00 ++#define IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0 0x1E058010,0x0000000F ++ ++#define IPU_DC_RL3_CH_0__ADDR 0x1E058014 ++#define IPU_DC_RL3_CH_0__EMPTY 0x1E058014,0x00000000 ++#define IPU_DC_RL3_CH_0__FULL 0x1E058014,0xffffffff ++#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0 0x1E058014,0xFF000000 ++#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1E058014,0x000F0000 ++#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0 0x1E058014,0x0000FF00 ++#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1E058014,0x0000000F ++ ++#define IPU_DC_RL4_CH_0__ADDR 0x1E058018 ++#define IPU_DC_RL4_CH_0__EMPTY 0x1E058018,0x00000000 ++#define IPU_DC_RL4_CH_0__FULL 0x1E058018,0xffffffff ++#define IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0 0x1E058018,0x0000FF00 ++#define IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1E058018,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_1__ADDR 0x1E05801C ++#define IPU_DC_WR_CH_CONF_1__EMPTY 0x1E05801C,0x00000000 ++#define IPU_DC_WR_CH_CONF_1__FULL 0x1E05801C,0xffffffff ++#define IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1 0x1E05801C,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_1__FIELD_MODE_1 0x1E05801C,0x00000200 ++#define IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1E05801C,0x00000100 ++#define IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1 0x1E05801C,0x000000E0 ++#define IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1 0x1E05801C,0x00000018 ++#define IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1 0x1E05801C,0x00000004 ++#define IPU_DC_WR_CH_CONF_1__W_SIZE_1 0x1E05801C,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_1__ADDR 0x1E058020 ++#define IPU_DC_WR_CH_ADDR_1__EMPTY 0x1E058020,0x00000000 ++#define IPU_DC_WR_CH_ADDR_1__FULL 0x1E058020,0xffffffff ++#define IPU_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1E058020,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_1__ADDR 0x1E058024 ++#define IPU_DC_RL0_CH_1__EMPTY 0x1E058024,0x00000000 ++#define IPU_DC_RL0_CH_1__FULL 0x1E058024,0xffffffff ++#define IPU_DC_RL0_CH_1__COD_NL_START_CHAN_1 0x1E058024,0xFF000000 ++#define IPU_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1E058024,0x000F0000 ++#define IPU_DC_RL0_CH_1__COD_NF_START_CHAN_1 0x1E058024,0x0000FF00 ++#define IPU_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1E058024,0x0000000F ++ ++#define IPU_DC_RL1_CH_1__ADDR 0x1E058028 ++#define IPU_DC_RL1_CH_1__EMPTY 0x1E058028,0x00000000 ++#define IPU_DC_RL1_CH_1__FULL 0x1E058028,0xffffffff ++#define IPU_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1 0x1E058028,0xFF000000 ++#define IPU_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1E058028,0x000F0000 ++#define IPU_DC_RL1_CH_1__COD_EOF_START_CHAN_1 0x1E058028,0x0000FF00 ++#define IPU_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1 0x1E058028,0x0000000F ++ ++#define IPU_DC_RL2_CH_1__ADDR 0x1E05802C ++#define IPU_DC_RL2_CH_1__EMPTY 0x1E05802C,0x00000000 ++#define IPU_DC_RL2_CH_1__FULL 0x1E05802C,0xffffffff ++#define IPU_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1 0x1E05802C,0xFF000000 ++#define IPU_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1E05802C,0x000F0000 ++#define IPU_DC_RL2_CH_1__COD_EOL_START_CHAN_1 0x1E05802C,0x0000FF00 ++#define IPU_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1 0x1E05802C,0x0000000F ++ ++#define IPU_DC_RL3_CH_1__ADDR 0x1E058030 ++#define IPU_DC_RL3_CH_1__EMPTY 0x1E058030,0x00000000 ++#define IPU_DC_RL3_CH_1__FULL 0x1E058030,0xffffffff ++#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1 0x1E058030,0xFF000000 ++#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1E058030,0x000F0000 ++#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1 0x1E058030,0x0000FF00 ++#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1E058030,0x0000000F ++ ++#define IPU_DC_RL4_CH_1__ADDR 0x1E058034 ++#define IPU_DC_RL4_CH_1__EMPTY 0x1E058034,0x00000000 ++#define IPU_DC_RL4_CH_1__FULL 0x1E058034,0xffffffff ++#define IPU_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1 0x1E058034,0x0000FF00 ++#define IPU_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1E058034,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_2__ADDR 0x1E058038 ++#define IPU_DC_WR_CH_CONF_2__EMPTY 0x1E058038,0x00000000 ++#define IPU_DC_WR_CH_CONF_2__FULL 0x1E058038,0xffffffff ++#define IPU_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1E058038,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1E058038,0x00000100 ++#define IPU_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1E058038,0x000000E0 ++#define IPU_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1E058038,0x00000018 ++#define IPU_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1E058038,0x00000004 ++#define IPU_DC_WR_CH_CONF_2__W_SIZE_2 0x1E058038,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_2__ADDR 0x1E05803C ++#define IPU_DC_WR_CH_ADDR_2__EMPTY 0x1E05803C,0x00000000 ++#define IPU_DC_WR_CH_ADDR_2__FULL 0x1E05803C,0xffffffff ++#define IPU_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1E05803C,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_2__ADDR 0x1E058040 ++#define IPU_DC_RL0_CH_2__EMPTY 0x1E058040,0x00000000 ++#define IPU_DC_RL0_CH_2__FULL 0x1E058040,0xffffffff ++#define IPU_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1E058040,0xFF000000 ++#define IPU_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1E058040,0x000F0000 ++#define IPU_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1E058040,0x0000FF00 ++#define IPU_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1E058040,0x0000000F ++ ++#define IPU_DC_RL1_CH_2__ADDR 0x1E058044 ++#define IPU_DC_RL1_CH_2__EMPTY 0x1E058044,0x00000000 ++#define IPU_DC_RL1_CH_2__FULL 0x1E058044,0xffffffff ++#define IPU_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1E058044,0xFF000000 ++#define IPU_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1E058044,0x000F0000 ++#define IPU_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1E058044,0x0000FF00 ++#define IPU_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1E058044,0x0000000F ++ ++#define IPU_DC_RL2_CH_2__ADDR 0x1E058048 ++#define IPU_DC_RL2_CH_2__EMPTY 0x1E058048,0x00000000 ++#define IPU_DC_RL2_CH_2__FULL 0x1E058048,0xffffffff ++#define IPU_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1E058048,0xFF000000 ++#define IPU_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1E058048,0x000F0000 ++#define IPU_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1E058048,0x0000FF00 ++#define IPU_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1E058048,0x0000000F ++ ++#define IPU_DC_RL3_CH_2__ADDR 0x1E05804C ++#define IPU_DC_RL3_CH_2__EMPTY 0x1E05804C,0x00000000 ++#define IPU_DC_RL3_CH_2__FULL 0x1E05804C,0xffffffff ++#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1E05804C,0xFF000000 ++#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1E05804C,0x000F0000 ++#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1E05804C,0x0000FF00 ++#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1E05804C,0x0000000F ++ ++#define IPU_DC_RL4_CH_2__ADDR 0x1E058050 ++#define IPU_DC_RL4_CH_2__EMPTY 0x1E058050,0x00000000 ++#define IPU_DC_RL4_CH_2__FULL 0x1E058050,0xffffffff ++#define IPU_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1E058050,0x0000FF00 ++#define IPU_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1E058050,0x0000000F ++ ++#define IPU_DC_CMD_CH_CONF_3__ADDR 0x1E058054 ++#define IPU_DC_CMD_CH_CONF_3__EMPTY 0x1E058054,0x00000000 ++#define IPU_DC_CMD_CH_CONF_3__FULL 0x1E058054,0xffffffff ++#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1E058054,0xFF000000 ++#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1E058054,0x0000FF00 ++#define IPU_DC_CMD_CH_CONF_3__W_SIZE_3 0x1E058054,0x00000003 ++ ++#define IPU_DC_CMD_CH_CONF_4__ADDR 0x1E058058 ++#define IPU_DC_CMD_CH_CONF_4__EMPTY 0x1E058058,0x00000000 ++#define IPU_DC_CMD_CH_CONF_4__FULL 0x1E058058,0xffffffff ++#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1E058058,0xFF000000 ++#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1E058058,0x0000FF00 ++#define IPU_DC_CMD_CH_CONF_4__W_SIZE_4 0x1E058058,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF_5__ADDR 0x1E05805C ++#define IPU_DC_WR_CH_CONF_5__EMPTY 0x1E05805C,0x00000000 ++#define IPU_DC_WR_CH_CONF_5__FULL 0x1E05805C,0xffffffff ++#define IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5 0x1E05805C,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_5__FIELD_MODE_5 0x1E05805C,0x00000200 ++#define IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1E05805C,0x00000100 ++#define IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5 0x1E05805C,0x000000E0 ++#define IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5 0x1E05805C,0x00000018 ++#define IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5 0x1E05805C,0x00000004 ++#define IPU_DC_WR_CH_CONF_5__W_SIZE_5 0x1E05805C,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_5__ADDR 0x1E058060 ++#define IPU_DC_WR_CH_ADDR_5__EMPTY 0x1E058060,0x00000000 ++#define IPU_DC_WR_CH_ADDR_5__FULL 0x1E058060,0xffffffff ++#define IPU_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1E058060,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_5__ADDR 0x1E058064 ++#define IPU_DC_RL0_CH_5__EMPTY 0x1E058064,0x00000000 ++#define IPU_DC_RL0_CH_5__FULL 0x1E058064,0xffffffff ++#define IPU_DC_RL0_CH_5__COD_NL_START_CHAN_5 0x1E058064,0xFF000000 ++#define IPU_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1E058064,0x000F0000 ++#define IPU_DC_RL0_CH_5__COD_NF_START_CHAN_5 0x1E058064,0x0000FF00 ++#define IPU_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1E058064,0x0000000F ++ ++#define IPU_DC_RL1_CH_5__ADDR 0x1E058068 ++#define IPU_DC_RL1_CH_5__EMPTY 0x1E058068,0x00000000 ++#define IPU_DC_RL1_CH_5__FULL 0x1E058068,0xffffffff ++#define IPU_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5 0x1E058068,0xFF000000 ++#define IPU_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1E058068,0x000F0000 ++#define IPU_DC_RL1_CH_5__COD_EOF_START_CHAN_5 0x1E058068,0x0000FF00 ++#define IPU_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5 0x1E058068,0x0000000F ++ ++#define IPU_DC_RL2_CH_5__ADDR 0x1E05806C ++#define IPU_DC_RL2_CH_5__EMPTY 0x1E05806C,0x00000000 ++#define IPU_DC_RL2_CH_5__FULL 0x1E05806C,0xffffffff ++#define IPU_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5 0x1E05806C,0xFF000000 ++#define IPU_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1E05806C,0x000F0000 ++#define IPU_DC_RL2_CH_5__COD_EOL_START_CHAN_5 0x1E05806C,0x0000FF00 ++#define IPU_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5 0x1E05806C,0x0000000F ++ ++#define IPU_DC_RL3_CH_5__ADDR 0x1E058070 ++#define IPU_DC_RL3_CH_5__EMPTY 0x1E058070,0x00000000 ++#define IPU_DC_RL3_CH_5__FULL 0x1E058070,0xffffffff ++#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5 0x1E058070,0xFF000000 ++#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1E058070,0x000F0000 ++#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5 0x1E058070,0x0000FF00 ++#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1E058070,0x0000000F ++ ++#define IPU_DC_RL4_CH_5__ADDR 0x1E058074 ++#define IPU_DC_RL4_CH_5__EMPTY 0x1E058074,0x00000000 ++#define IPU_DC_RL4_CH_5__FULL 0x1E058074,0xffffffff ++#define IPU_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5 0x1E058074,0x0000FF00 ++#define IPU_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1E058074,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_6__ADDR 0x1E058078 ++#define IPU_DC_WR_CH_CONF_6__EMPTY 0x1E058078,0x00000000 ++#define IPU_DC_WR_CH_CONF_6__FULL 0x1E058078,0xffffffff ++#define IPU_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1E058078,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1E058078,0x00000100 ++#define IPU_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1E058078,0x000000E0 ++#define IPU_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1E058078,0x00000018 ++#define IPU_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1E058078,0x00000004 ++#define IPU_DC_WR_CH_CONF_6__W_SIZE_6 0x1E058078,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_6__ADDR 0x1E05807C ++#define IPU_DC_WR_CH_ADDR_6__EMPTY 0x1E05807C,0x00000000 ++#define IPU_DC_WR_CH_ADDR_6__FULL 0x1E05807C,0xffffffff ++#define IPU_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1E05807C,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_6__ADDR 0x1E058080 ++#define IPU_DC_RL0_CH_6__EMPTY 0x1E058080,0x00000000 ++#define IPU_DC_RL0_CH_6__FULL 0x1E058080,0xffffffff ++#define IPU_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1E058080,0xFF000000 ++#define IPU_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1E058080,0x000F0000 ++#define IPU_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1E058080,0x0000FF00 ++#define IPU_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1E058080,0x0000000F ++ ++#define IPU_DC_RL1_CH_6__ADDR 0x1E058084 ++#define IPU_DC_RL1_CH_6__EMPTY 0x1E058084,0x00000000 ++#define IPU_DC_RL1_CH_6__FULL 0x1E058084,0xffffffff ++#define IPU_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1E058084,0xFF000000 ++#define IPU_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1E058084,0x000F0000 ++#define IPU_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1E058084,0x0000FF00 ++#define IPU_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1E058084,0x0000000F ++ ++#define IPU_DC_RL2_CH_6__ADDR 0x1E058088 ++#define IPU_DC_RL2_CH_6__EMPTY 0x1E058088,0x00000000 ++#define IPU_DC_RL2_CH_6__FULL 0x1E058088,0xffffffff ++#define IPU_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1E058088,0xFF000000 ++#define IPU_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1E058088,0x000F0000 ++#define IPU_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1E058088,0x0000FF00 ++#define IPU_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1E058088,0x0000000F ++ ++#define IPU_DC_RL3_CH_6__ADDR 0x1E05808C ++#define IPU_DC_RL3_CH_6__EMPTY 0x1E05808C,0x00000000 ++#define IPU_DC_RL3_CH_6__FULL 0x1E05808C,0xffffffff ++#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1E05808C,0xFF000000 ++#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1E05808C,0x000F0000 ++#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1E05808C,0x0000FF00 ++#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1E05808C,0x0000000F ++ ++#define IPU_DC_RL4_CH_6__ADDR 0x1E058090 ++#define IPU_DC_RL4_CH_6__EMPTY 0x1E058090,0x00000000 ++#define IPU_DC_RL4_CH_6__FULL 0x1E058090,0xffffffff ++#define IPU_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1E058090,0x0000FF00 ++#define IPU_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1E058090,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF1_8__ADDR 0x1E058094 ++#define IPU_DC_WR_CH_CONF1_8__EMPTY 0x1E058094,0x00000000 ++#define IPU_DC_WR_CH_CONF1_8__FULL 0x1E058094,0xffffffff ++#define IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8 0x1E058094,0x00000018 ++#define IPU_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1E058094,0x00000004 ++#define IPU_DC_WR_CH_CONF1_8__W_SIZE_8 0x1E058094,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF2_8__ADDR 0x1E058098 ++#define IPU_DC_WR_CH_CONF2_8__EMPTY 0x1E058098,0x00000000 ++#define IPU_DC_WR_CH_CONF2_8__FULL 0x1E058098,0xffffffff ++#define IPU_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1E058098,0x1FFFFFFF ++ ++#define IPU_DC_RL1_CH_8__ADDR 0x1E05809C ++#define IPU_DC_RL1_CH_8__EMPTY 0x1E05809C,0x00000000 ++#define IPU_DC_RL1_CH_8__FULL 0x1E05809C,0xffffffff ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1E05809C,0xFF000000 ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1E05809C,0x0000FF00 ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8 0x1E05809C,0x0000000F ++ ++#define IPU_DC_RL2_CH_8__ADDR 0x1E0580A0 ++#define IPU_DC_RL2_CH_8__EMPTY 0x1E0580A0,0x00000000 ++#define IPU_DC_RL2_CH_8__FULL 0x1E0580A0,0xffffffff ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1E0580A0,0xFF000000 ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1E0580A0,0x0000FF00 ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8 0x1E0580A0,0x0000000F ++ ++#define IPU_DC_RL3_CH_8__ADDR 0x1E0580A4 ++#define IPU_DC_RL3_CH_8__EMPTY 0x1E0580A4,0x00000000 ++#define IPU_DC_RL3_CH_8__FULL 0x1E0580A4,0xffffffff ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1E0580A4,0xFF000000 ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1E0580A4,0x0000FF00 ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8 0x1E0580A4,0x0000000F ++ ++#define IPU_DC_RL4_CH_8__ADDR 0x1E0580A8 ++#define IPU_DC_RL4_CH_8__EMPTY 0x1E0580A8,0x00000000 ++#define IPU_DC_RL4_CH_8__FULL 0x1E0580A8,0xffffffff ++#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1E0580A8,0xFF000000 ++#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1E0580A8,0x0000FF00 ++ ++#define IPU_DC_RL5_CH_8__ADDR 0x1E0580AC ++#define IPU_DC_RL5_CH_8__EMPTY 0x1E0580AC,0x00000000 ++#define IPU_DC_RL5_CH_8__FULL 0x1E0580AC,0xffffffff ++#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1E0580AC,0xFF000000 ++#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1E0580AC,0x0000FF00 ++ ++#define IPU_DC_RL6_CH_8__ADDR 0x1E0580B0 ++#define IPU_DC_RL6_CH_8__EMPTY 0x1E0580B0,0x00000000 ++#define IPU_DC_RL6_CH_8__FULL 0x1E0580B0,0xffffffff ++#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1E0580B0,0xFF000000 ++#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1E0580B0,0x0000FF00 ++ ++#define IPU_DC_WR_CH_CONF1_9__ADDR 0x1E0580B4 ++#define IPU_DC_WR_CH_CONF1_9__EMPTY 0x1E0580B4,0x00000000 ++#define IPU_DC_WR_CH_CONF1_9__FULL 0x1E0580B4,0xffffffff ++#define IPU_DC_WR_CH_CONF1_9__MCU_DISP_ID_9 0x1E0580B4,0x00000018 ++#define IPU_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1E0580B4,0x00000004 ++#define IPU_DC_WR_CH_CONF1_9__W_SIZE_9 0x1E0580B4,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF2_9__ADDR 0x1E0580B8 ++#define IPU_DC_WR_CH_CONF2_9__EMPTY 0x1E0580B8,0x00000000 ++#define IPU_DC_WR_CH_CONF2_9__FULL 0x1E0580B8,0xffffffff ++#define IPU_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1E0580B8,0x1FFFFFFF ++ ++#define IPU_DC_RL1_CH_9__ADDR 0x1E0580BC ++#define IPU_DC_RL1_CH_9__EMPTY 0x1E0580BC,0x00000000 ++#define IPU_DC_RL1_CH_9__FULL 0x1E0580BC,0xffffffff ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1E0580BC,0xFF000000 ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1E0580BC,0x0000FF00 ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9 0x1E0580BC,0x0000000F ++ ++#define IPU_DC_RL2_CH_9__ADDR 0x1E0580C0 ++#define IPU_DC_RL2_CH_9__EMPTY 0x1E0580C0,0x00000000 ++#define IPU_DC_RL2_CH_9__FULL 0x1E0580C0,0xffffffff ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1E0580C0,0xFF000000 ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1E0580C0,0x0000FF00 ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9 0x1E0580C0,0x0000000F ++ ++#define IPU_DC_RL3_CH_9__ADDR 0x1E0580C4 ++#define IPU_DC_RL3_CH_9__EMPTY 0x1E0580C4,0x00000000 ++#define IPU_DC_RL3_CH_9__FULL 0x1E0580C4,0xffffffff ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1E0580C4,0xFF000000 ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1E0580C4,0x0000FF00 ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9 0x1E0580C4,0x0000000F ++ ++#define IPU_DC_RL4_CH_9__ADDR 0x1E0580C8 ++#define IPU_DC_RL4_CH_9__EMPTY 0x1E0580C8,0x00000000 ++#define IPU_DC_RL4_CH_9__FULL 0x1E0580C8,0xffffffff ++#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1E0580C8,0xFF000000 ++#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1E0580C8,0x0000FF00 ++ ++#define IPU_DC_RL5_CH_9__ADDR 0x1E0580CC ++#define IPU_DC_RL5_CH_9__EMPTY 0x1E0580CC,0x00000000 ++#define IPU_DC_RL5_CH_9__FULL 0x1E0580CC,0xffffffff ++#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1E0580CC,0xFF000000 ++#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1E0580CC,0x0000FF00 ++ ++#define IPU_DC_RL6_CH_9__ADDR 0x1E0580D0 ++#define IPU_DC_RL6_CH_9__EMPTY 0x1E0580D0,0x00000000 ++#define IPU_DC_RL6_CH_9__FULL 0x1E0580D0,0xffffffff ++#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1E0580D0,0xFF000000 ++#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1E0580D0,0x0000FF00 ++ ++#define IPU_DC_GEN__ADDR 0x1E0580D4 ++#define IPU_DC_GEN__EMPTY 0x1E0580D4,0x00000000 ++#define IPU_DC_GEN__FULL 0x1E0580D4,0xffffffff ++#define IPU_DC_GEN__DC_BK_EN 0x1E0580D4,0x01000000 ++#define IPU_DC_GEN__DC_BKDIV 0x1E0580D4,0x00FF0000 ++#define IPU_DC_GEN__DC_CH5_TYPE 0x1E0580D4,0x00000100 ++#define IPU_DC_GEN__SYNC_PRIORITY_1 0x1E0580D4,0x00000080 ++#define IPU_DC_GEN__SYNC_PRIORITY_5 0x1E0580D4,0x00000040 ++#define IPU_DC_GEN__MASK4CHAN_5 0x1E0580D4,0x00000020 ++#define IPU_DC_GEN__MASK_EN 0x1E0580D4,0x00000010 ++#define IPU_DC_GEN__SYNC_1_6 0x1E0580D4,0x00000006 ++ ++#define IPU_DC_DISP_CONF1_0__ADDR 0x1E0580D8 ++#define IPU_DC_DISP_CONF1_0__EMPTY 0x1E0580D8,0x00000000 ++#define IPU_DC_DISP_CONF1_0__FULL 0x1E0580D8,0xffffffff ++#define IPU_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1E0580D8,0x00000080 ++#define IPU_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0 0x1E0580D8,0x00000040 ++#define IPU_DC_DISP_CONF1_0__ADDR_BE_L_INC_0 0x1E0580D8,0x00000030 ++#define IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0 0x1E0580D8,0x0000000C ++#define IPU_DC_DISP_CONF1_0__DISP_TYP_0 0x1E0580D8,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_1__ADDR 0x1E0580DC ++#define IPU_DC_DISP_CONF1_1__EMPTY 0x1E0580DC,0x00000000 ++#define IPU_DC_DISP_CONF1_1__FULL 0x1E0580DC,0xffffffff ++#define IPU_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1E0580DC,0x00000080 ++#define IPU_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1 0x1E0580DC,0x00000040 ++#define IPU_DC_DISP_CONF1_1__ADDR_BE_L_INC_1 0x1E0580DC,0x00000030 ++#define IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1 0x1E0580DC,0x0000000C ++#define IPU_DC_DISP_CONF1_1__DISP_TYP_1 0x1E0580DC,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_2__ADDR 0x1E0580E0 ++#define IPU_DC_DISP_CONF1_2__EMPTY 0x1E0580E0,0x00000000 ++#define IPU_DC_DISP_CONF1_2__FULL 0x1E0580E0,0xffffffff ++#define IPU_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1E0580E0,0x00000080 ++#define IPU_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2 0x1E0580E0,0x00000040 ++#define IPU_DC_DISP_CONF1_2__ADDR_BE_L_INC_2 0x1E0580E0,0x00000030 ++#define IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2 0x1E0580E0,0x0000000C ++#define IPU_DC_DISP_CONF1_2__DISP_TYP_2 0x1E0580E0,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_3__ADDR 0x1E0580E4 ++#define IPU_DC_DISP_CONF1_3__EMPTY 0x1E0580E4,0x00000000 ++#define IPU_DC_DISP_CONF1_3__FULL 0x1E0580E4,0xffffffff ++#define IPU_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1E0580E4,0x00000080 ++#define IPU_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3 0x1E0580E4,0x00000040 ++#define IPU_DC_DISP_CONF1_3__ADDR_BE_L_INC_3 0x1E0580E4,0x00000030 ++#define IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3 0x1E0580E4,0x0000000C ++#define IPU_DC_DISP_CONF1_3__DISP_TYP_3 0x1E0580E4,0x00000003 ++ ++#define IPU_DC_DISP_CONF2_0__ADDR 0x1E0580E8 ++#define IPU_DC_DISP_CONF2_0__EMPTY 0x1E0580E8,0x00000000 ++#define IPU_DC_DISP_CONF2_0__FULL 0x1E0580E8,0xffffffff ++#define IPU_DC_DISP_CONF2_0__SL_0 0x1E0580E8,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_1__ADDR 0x1E0580EC ++#define IPU_DC_DISP_CONF2_1__EMPTY 0x1E0580EC,0x00000000 ++#define IPU_DC_DISP_CONF2_1__FULL 0x1E0580EC,0xffffffff ++#define IPU_DC_DISP_CONF2_1__SL_1 0x1E0580EC,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_2__ADDR 0x1E0580F0 ++#define IPU_DC_DISP_CONF2_2__EMPTY 0x1E0580F0,0x00000000 ++#define IPU_DC_DISP_CONF2_2__FULL 0x1E0580F0,0xffffffff ++#define IPU_DC_DISP_CONF2_2__SL_2 0x1E0580F0,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_3__ADDR 0x1E0580F4 ++#define IPU_DC_DISP_CONF2_3__EMPTY 0x1E0580F4,0x00000000 ++#define IPU_DC_DISP_CONF2_3__FULL 0x1E0580F4,0xffffffff ++#define IPU_DC_DISP_CONF2_3__SL_3 0x1E0580F4,0x1FFFFFFF ++ ++#define IPU_DC_DI0_CONF_1__ADDR 0x1E0580F8 ++#define IPU_DC_DI0_CONF_1__EMPTY 0x1E0580F8,0x00000000 ++#define IPU_DC_DI0_CONF_1__FULL 0x1E0580F8,0xffffffff ++#define IPU_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1E0580F8,0xFFFFFFFF ++ ++#define IPU_DC_DI0_CONF_2__ADDR 0x1E0580FC ++#define IPU_DC_DI0_CONF_2__EMPTY 0x1E0580FC,0x00000000 ++#define IPU_DC_DI0_CONF_2__FULL 0x1E0580FC,0xffffffff ++#define IPU_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1E0580FC,0xFFFFFFFF ++ ++#define IPU_DC_DI1_CONF_1__ADDR 0x1E058100 ++#define IPU_DC_DI1_CONF_1__EMPTY 0x1E058100,0x00000000 ++#define IPU_DC_DI1_CONF_1__FULL 0x1E058100,0xffffffff ++#define IPU_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1E058100,0xFFFFFFFF ++ ++#define IPU_DC_DI1_CONF_2__ADDR 0x1E058104 ++#define IPU_DC_DI1_CONF_2__EMPTY 0x1E058104,0x00000000 ++#define IPU_DC_DI1_CONF_2__FULL 0x1E058104,0xffffffff ++#define IPU_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1E058104,0xFFFFFFFF ++ ++#define IPU_DC_MAP_CONF_0__ADDR 0x1E058108 ++#define IPU_DC_MAP_CONF_0__EMPTY 0x1E058108,0x00000000 ++#define IPU_DC_MAP_CONF_0__FULL 0x1E058108,0xffffffff ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1E058108,0x7C000000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1E058108,0x03E00000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1E058108,0x001F0000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1E058108,0x00007C00 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1E058108,0x000003E0 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1E058108,0x0000001F ++ ++#define IPU_DC_MAP_CONF_1__ADDR 0x1E05810C ++#define IPU_DC_MAP_CONF_1__EMPTY 0x1E05810C,0x00000000 ++#define IPU_DC_MAP_CONF_1__FULL 0x1E05810C,0xffffffff ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1E05810C,0x7C000000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1E05810C,0x03E00000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1E05810C,0x001F0000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1E05810C,0x00007C00 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1E05810C,0x000003E0 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1E05810C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_2__ADDR 0x1E058110 ++#define IPU_DC_MAP_CONF_2__EMPTY 0x1E058110,0x00000000 ++#define IPU_DC_MAP_CONF_2__FULL 0x1E058110,0xffffffff ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1E058110,0x7C000000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1E058110,0x03E00000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1E058110,0x001F0000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1E058110,0x00007C00 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1E058110,0x000003E0 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1E058110,0x0000001F ++ ++#define IPU_DC_MAP_CONF_3__ADDR 0x1E058114 ++#define IPU_DC_MAP_CONF_3__EMPTY 0x1E058114,0x00000000 ++#define IPU_DC_MAP_CONF_3__FULL 0x1E058114,0xffffffff ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1E058114,0x7C000000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1E058114,0x03E00000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1E058114,0x001F0000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1E058114,0x00007C00 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1E058114,0x000003E0 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1E058114,0x0000001F ++ ++#define IPU_DC_MAP_CONF_4__ADDR 0x1E058118 ++#define IPU_DC_MAP_CONF_4__EMPTY 0x1E058118,0x00000000 ++#define IPU_DC_MAP_CONF_4__FULL 0x1E058118,0xffffffff ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1E058118,0x7C000000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1E058118,0x03E00000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1E058118,0x001F0000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1E058118,0x00007C00 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1E058118,0x000003E0 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1E058118,0x0000001F ++ ++#define IPU_DC_MAP_CONF_5__ADDR 0x1E05811C ++#define IPU_DC_MAP_CONF_5__EMPTY 0x1E05811C,0x00000000 ++#define IPU_DC_MAP_CONF_5__FULL 0x1E05811C,0xffffffff ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1E05811C,0x7C000000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1E05811C,0x03E00000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1E05811C,0x001F0000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1E05811C,0x00007C00 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1E05811C,0x000003E0 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1E05811C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_6__ADDR 0x1E058120 ++#define IPU_DC_MAP_CONF_6__EMPTY 0x1E058120,0x00000000 ++#define IPU_DC_MAP_CONF_6__FULL 0x1E058120,0xffffffff ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1E058120,0x7C000000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1E058120,0x03E00000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1E058120,0x001F0000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1E058120,0x00007C00 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1E058120,0x000003E0 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1E058120,0x0000001F ++ ++#define IPU_DC_MAP_CONF_7__ADDR 0x1E058124 ++#define IPU_DC_MAP_CONF_7__EMPTY 0x1E058124,0x00000000 ++#define IPU_DC_MAP_CONF_7__FULL 0x1E058124,0xffffffff ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1E058124,0x7C000000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1E058124,0x03E00000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1E058124,0x001F0000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1E058124,0x00007C00 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1E058124,0x000003E0 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1E058124,0x0000001F ++ ++#define IPU_DC_MAP_CONF_8__ADDR 0x1E058128 ++#define IPU_DC_MAP_CONF_8__EMPTY 0x1E058128,0x00000000 ++#define IPU_DC_MAP_CONF_8__FULL 0x1E058128,0xffffffff ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1E058128,0x7C000000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1E058128,0x03E00000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1E058128,0x001F0000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1E058128,0x00007C00 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1E058128,0x000003E0 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1E058128,0x0000001F ++ ++#define IPU_DC_MAP_CONF_9__ADDR 0x1E05812C ++#define IPU_DC_MAP_CONF_9__EMPTY 0x1E05812C,0x00000000 ++#define IPU_DC_MAP_CONF_9__FULL 0x1E05812C,0xffffffff ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1E05812C,0x7C000000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1E05812C,0x03E00000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1E05812C,0x001F0000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1E05812C,0x00007C00 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1E05812C,0x000003E0 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1E05812C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_10__ADDR 0x1E058130 ++#define IPU_DC_MAP_CONF_10__EMPTY 0x1E058130,0x00000000 ++#define IPU_DC_MAP_CONF_10__FULL 0x1E058130,0xffffffff ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1E058130,0x7C000000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1E058130,0x03E00000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1E058130,0x001F0000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1E058130,0x00007C00 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1E058130,0x000003E0 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1E058130,0x0000001F ++ ++#define IPU_DC_MAP_CONF_11__ADDR 0x1E058134 ++#define IPU_DC_MAP_CONF_11__EMPTY 0x1E058134,0x00000000 ++#define IPU_DC_MAP_CONF_11__FULL 0x1E058134,0xffffffff ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1E058134,0x7C000000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1E058134,0x03E00000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1E058134,0x001F0000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1E058134,0x00007C00 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1E058134,0x000003E0 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1E058134,0x0000001F ++ ++#define IPU_DC_MAP_CONF_12__ADDR 0x1E058138 ++#define IPU_DC_MAP_CONF_12__EMPTY 0x1E058138,0x00000000 ++#define IPU_DC_MAP_CONF_12__FULL 0x1E058138,0xffffffff ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1E058138,0x7C000000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1E058138,0x03E00000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1E058138,0x001F0000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1E058138,0x00007C00 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1E058138,0x000003E0 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1E058138,0x0000001F ++ ++#define IPU_DC_MAP_CONF_13__ADDR 0x1E05813C ++#define IPU_DC_MAP_CONF_13__EMPTY 0x1E05813C,0x00000000 ++#define IPU_DC_MAP_CONF_13__FULL 0x1E05813C,0xffffffff ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1E05813C,0x7C000000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1E05813C,0x03E00000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1E05813C,0x001F0000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1E05813C,0x00007C00 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1E05813C,0x000003E0 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1E05813C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_14__ADDR 0x1E058140 ++#define IPU_DC_MAP_CONF_14__EMPTY 0x1E058140,0x00000000 ++#define IPU_DC_MAP_CONF_14__FULL 0x1E058140,0xffffffff ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1E058140,0x7C000000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1E058140,0x03E00000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1E058140,0x001F0000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1E058140,0x00007C00 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1E058140,0x000003E0 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1E058140,0x0000001F ++ ++#define IPU_DC_MAP_CONF_15__ADDR 0x1E058144 ++#define IPU_DC_MAP_CONF_15__EMPTY 0x1E058144,0x00000000 ++#define IPU_DC_MAP_CONF_15__FULL 0x1E058144,0xffffffff ++#define IPU_DC_MAP_CONF_15__MD_OFFSET_1 0x1E058144,0x1F000000 ++#define IPU_DC_MAP_CONF_15__MD_MASK_1 0x1E058144,0x00FF0000 ++#define IPU_DC_MAP_CONF_15__MD_OFFSET_0 0x1E058144,0x00001F00 ++#define IPU_DC_MAP_CONF_15__MD_MASK_0 0x1E058144,0x000000FF ++ ++#define IPU_DC_MAP_CONF_16__ADDR 0x1E058148 ++#define IPU_DC_MAP_CONF_16__EMPTY 0x1E058148,0x00000000 ++#define IPU_DC_MAP_CONF_16__FULL 0x1E058148,0xffffffff ++#define IPU_DC_MAP_CONF_16__MD_OFFSET_3 0x1E058148,0x1F000000 ++#define IPU_DC_MAP_CONF_16__MD_MASK_3 0x1E058148,0x00FF0000 ++#define IPU_DC_MAP_CONF_16__MD_OFFSET_2 0x1E058148,0x00001F00 ++#define IPU_DC_MAP_CONF_16__MD_MASK_2 0x1E058148,0x000000FF ++ ++#define IPU_DC_MAP_CONF_17__ADDR 0x1E05814C ++#define IPU_DC_MAP_CONF_17__EMPTY 0x1E05814C,0x00000000 ++#define IPU_DC_MAP_CONF_17__FULL 0x1E05814C,0xffffffff ++#define IPU_DC_MAP_CONF_17__MD_OFFSET_5 0x1E05814C,0x1F000000 ++#define IPU_DC_MAP_CONF_17__MD_MASK_5 0x1E05814C,0x00FF0000 ++#define IPU_DC_MAP_CONF_17__MD_OFFSET_4 0x1E05814C,0x00001F00 ++#define IPU_DC_MAP_CONF_17__MD_MASK_4 0x1E05814C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_18__ADDR 0x1E058150 ++#define IPU_DC_MAP_CONF_18__EMPTY 0x1E058150,0x00000000 ++#define IPU_DC_MAP_CONF_18__FULL 0x1E058150,0xffffffff ++#define IPU_DC_MAP_CONF_18__MD_OFFSET_7 0x1E058150,0x1F000000 ++#define IPU_DC_MAP_CONF_18__MD_MASK_7 0x1E058150,0x00FF0000 ++#define IPU_DC_MAP_CONF_18__MD_OFFSET_6 0x1E058150,0x00001F00 ++#define IPU_DC_MAP_CONF_18__MD_MASK_6 0x1E058150,0x000000FF ++ ++#define IPU_DC_MAP_CONF_19__ADDR 0x1E058154 ++#define IPU_DC_MAP_CONF_19__EMPTY 0x1E058154,0x00000000 ++#define IPU_DC_MAP_CONF_19__FULL 0x1E058154,0xffffffff ++#define IPU_DC_MAP_CONF_19__MD_OFFSET_9 0x1E058154,0x1F000000 ++#define IPU_DC_MAP_CONF_19__MD_MASK_9 0x1E058154,0x00FF0000 ++#define IPU_DC_MAP_CONF_19__MD_OFFSET_8 0x1E058154,0x00001F00 ++#define IPU_DC_MAP_CONF_19__MD_MASK_8 0x1E058154,0x000000FF ++ ++#define IPU_DC_MAP_CONF_20__ADDR 0x1E058158 ++#define IPU_DC_MAP_CONF_20__EMPTY 0x1E058158,0x00000000 ++#define IPU_DC_MAP_CONF_20__FULL 0x1E058158,0xffffffff ++#define IPU_DC_MAP_CONF_20__MD_OFFSET_11 0x1E058158,0x1F000000 ++#define IPU_DC_MAP_CONF_20__MD_MASK_11 0x1E058158,0x00FF0000 ++#define IPU_DC_MAP_CONF_20__MD_OFFSET_10 0x1E058158,0x00001F00 ++#define IPU_DC_MAP_CONF_20__MD_MASK_10 0x1E058158,0x000000FF ++ ++#define IPU_DC_MAP_CONF_21__ADDR 0x1E05815C ++#define IPU_DC_MAP_CONF_21__EMPTY 0x1E05815C,0x00000000 ++#define IPU_DC_MAP_CONF_21__FULL 0x1E05815C,0xffffffff ++#define IPU_DC_MAP_CONF_21__MD_OFFSET_13 0x1E05815C,0x1F000000 ++#define IPU_DC_MAP_CONF_21__MD_MASK_13 0x1E05815C,0x00FF0000 ++#define IPU_DC_MAP_CONF_21__MD_OFFSET_12 0x1E05815C,0x00001F00 ++#define IPU_DC_MAP_CONF_21__MD_MASK_12 0x1E05815C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_22__ADDR 0x1E058160 ++#define IPU_DC_MAP_CONF_22__EMPTY 0x1E058160,0x00000000 ++#define IPU_DC_MAP_CONF_22__FULL 0x1E058160,0xffffffff ++#define IPU_DC_MAP_CONF_22__MD_OFFSET_15 0x1E058160,0x1F000000 ++#define IPU_DC_MAP_CONF_22__MD_MASK_15 0x1E058160,0x00FF0000 ++#define IPU_DC_MAP_CONF_22__MD_OFFSET_14 0x1E058160,0x00001F00 ++#define IPU_DC_MAP_CONF_22__MD_MASK_14 0x1E058160,0x000000FF ++ ++#define IPU_DC_MAP_CONF_23__ADDR 0x1E058164 ++#define IPU_DC_MAP_CONF_23__EMPTY 0x1E058164,0x00000000 ++#define IPU_DC_MAP_CONF_23__FULL 0x1E058164,0xffffffff ++#define IPU_DC_MAP_CONF_23__MD_OFFSET_17 0x1E058164,0x1F000000 ++#define IPU_DC_MAP_CONF_23__MD_MASK_17 0x1E058164,0x00FF0000 ++#define IPU_DC_MAP_CONF_23__MD_OFFSET_16 0x1E058164,0x00001F00 ++#define IPU_DC_MAP_CONF_23__MD_MASK_16 0x1E058164,0x000000FF ++ ++#define IPU_DC_MAP_CONF_24__ADDR 0x1E058168 ++#define IPU_DC_MAP_CONF_24__EMPTY 0x1E058168,0x00000000 ++#define IPU_DC_MAP_CONF_24__FULL 0x1E058168,0xffffffff ++#define IPU_DC_MAP_CONF_24__MD_OFFSET_19 0x1E058168,0x1F000000 ++#define IPU_DC_MAP_CONF_24__MD_MASK_19 0x1E058168,0x00FF0000 ++#define IPU_DC_MAP_CONF_24__MD_OFFSET_18 0x1E058168,0x00001F00 ++#define IPU_DC_MAP_CONF_24__MD_MASK_18 0x1E058168,0x000000FF ++ ++#define IPU_DC_MAP_CONF_25__ADDR 0x1E05816C ++#define IPU_DC_MAP_CONF_25__EMPTY 0x1E05816C,0x00000000 ++#define IPU_DC_MAP_CONF_25__FULL 0x1E05816C,0xffffffff ++#define IPU_DC_MAP_CONF_25__MD_OFFSET_21 0x1E05816C,0x1F000000 ++#define IPU_DC_MAP_CONF_25__MD_MASK_21 0x1E05816C,0x00FF0000 ++#define IPU_DC_MAP_CONF_25__MD_OFFSET_20 0x1E05816C,0x00001F00 ++#define IPU_DC_MAP_CONF_25__MD_MASK_20 0x1E05816C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_26__ADDR 0x1E058170 ++#define IPU_DC_MAP_CONF_26__EMPTY 0x1E058170,0x00000000 ++#define IPU_DC_MAP_CONF_26__FULL 0x1E058170,0xffffffff ++#define IPU_DC_MAP_CONF_26__MD_OFFSET_23 0x1E058170,0x1F000000 ++#define IPU_DC_MAP_CONF_26__MD_MASK_23 0x1E058170,0x00FF0000 ++#define IPU_DC_MAP_CONF_26__MD_OFFSET_22 0x1E058170,0x00001F00 ++#define IPU_DC_MAP_CONF_26__MD_MASK_22 0x1E058170,0x000000FF ++ ++#define IPU_DC_UGDE0_0__ADDR 0x1E058174 ++#define IPU_DC_UGDE0_0__EMPTY 0x1E058174,0x00000000 ++#define IPU_DC_UGDE0_0__FULL 0x1E058174,0xffffffff ++#define IPU_DC_UGDE0_0__NF_NL_0 0x1E058174,0x18000000 ++#define IPU_DC_UGDE0_0__AUTORESTART_0 0x1E058174,0x04000000 ++#define IPU_DC_UGDE0_0__ODD_EN_0 0x1E058174,0x02000000 ++#define IPU_DC_UGDE0_0__COD_ODD_START_0 0x1E058174,0x00FF0000 ++#define IPU_DC_UGDE0_0__COD_EV_START_0 0x1E058174,0x0000FF00 ++#define IPU_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1E058174,0x00000078 ++#define IPU_DC_UGDE0_0__ID_CODED_0 0x1E058174,0x00000007 ++ ++#define IPU_DC_UGDE0_1__ADDR 0x1E058178 ++#define IPU_DC_UGDE0_1__EMPTY 0x1E058178,0x00000000 ++#define IPU_DC_UGDE0_1__FULL 0x1E058178,0xffffffff ++#define IPU_DC_UGDE0_1__STEP_0 0x1E058178,0x1FFFFFFF ++ ++#define IPU_DC_UGDE0_2__ADDR 0x1E05817C ++#define IPU_DC_UGDE0_2__EMPTY 0x1E05817C,0x00000000 ++#define IPU_DC_UGDE0_2__FULL 0x1E05817C,0xffffffff ++#define IPU_DC_UGDE0_2__OFFSET_DT_0 0x1E05817C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE0_3__ADDR 0x1E058180 ++#define IPU_DC_UGDE0_3__EMPTY 0x1E058180,0x00000000 ++#define IPU_DC_UGDE0_3__FULL 0x1E058180,0xffffffff ++#define IPU_DC_UGDE0_3__STEP_REPEAT_0 0x1E058180,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_0__ADDR 0x1E058184 ++#define IPU_DC_UGDE1_0__EMPTY 0x1E058184,0x00000000 ++#define IPU_DC_UGDE1_0__FULL 0x1E058184,0xffffffff ++#define IPU_DC_UGDE1_0__NF_NL_1 0x1E058184,0x18000000 ++#define IPU_DC_UGDE1_0__AUTORESTART_1 0x1E058184,0x04000000 ++#define IPU_DC_UGDE1_0__ODD_EN_1 0x1E058184,0x02000000 ++#define IPU_DC_UGDE1_0__COD_ODD_START_1 0x1E058184,0x00FF0000 ++#define IPU_DC_UGDE1_0__COD_EV_START_1 0x1E058184,0x00007F80 ++#define IPU_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1E058184,0x00000078 ++#define IPU_DC_UGDE1_0__ID_CODED_1 0x1E058184,0x00000007 ++ ++#define IPU_DC_UGDE1_1__ADDR 0x1E058188 ++#define IPU_DC_UGDE1_1__EMPTY 0x1E058188,0x00000000 ++#define IPU_DC_UGDE1_1__FULL 0x1E058188,0xffffffff ++#define IPU_DC_UGDE1_1__STEP_1 0x1E058188,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_2__ADDR 0x1E05818C ++#define IPU_DC_UGDE1_2__EMPTY 0x1E05818C,0x00000000 ++#define IPU_DC_UGDE1_2__FULL 0x1E05818C,0xffffffff ++#define IPU_DC_UGDE1_2__OFFSET_DT_1 0x1E05818C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_3__ADDR 0x1E058190 ++#define IPU_DC_UGDE1_3__EMPTY 0x1E058190,0x00000000 ++#define IPU_DC_UGDE1_3__FULL 0x1E058190,0xffffffff ++#define IPU_DC_UGDE1_3__STEP_REPEAT_1 0x1E058190,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_0__ADDR 0x1E058194 ++#define IPU_DC_UGDE2_0__EMPTY 0x1E058194,0x00000000 ++#define IPU_DC_UGDE2_0__FULL 0x1E058194,0xffffffff ++#define IPU_DC_UGDE2_0__NF_NL_2 0x1E058194,0x18000000 ++#define IPU_DC_UGDE2_0__AUTORESTART_2 0x1E058194,0x04000000 ++#define IPU_DC_UGDE2_0__ODD_EN_2 0x1E058194,0x02000000 ++#define IPU_DC_UGDE2_0__COD_ODD_START_2 0x1E058194,0x00FF0000 ++#define IPU_DC_UGDE2_0__COD_EV_START_2 0x1E058194,0x00007F80 ++#define IPU_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1E058194,0x00000078 ++#define IPU_DC_UGDE2_0__ID_CODED_2 0x1E058194,0x00000007 ++ ++#define IPU_DC_UGDE2_1__ADDR 0x1E058198 ++#define IPU_DC_UGDE2_1__EMPTY 0x1E058198,0x00000000 ++#define IPU_DC_UGDE2_1__FULL 0x1E058198,0xffffffff ++#define IPU_DC_UGDE2_1__STEP_2 0x1E058198,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_2__ADDR 0x1E05819C ++#define IPU_DC_UGDE2_2__EMPTY 0x1E05819C,0x00000000 ++#define IPU_DC_UGDE2_2__FULL 0x1E05819C,0xffffffff ++#define IPU_DC_UGDE2_2__OFFSET_DT_2 0x1E05819C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_3__ADDR 0x1E0581A0 ++#define IPU_DC_UGDE2_3__EMPTY 0x1E0581A0,0x00000000 ++#define IPU_DC_UGDE2_3__FULL 0x1E0581A0,0xffffffff ++#define IPU_DC_UGDE2_3__STEP_REPEAT_2 0x1E0581A0,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_0__ADDR 0x1E0581A4 ++#define IPU_DC_UGDE3_0__EMPTY 0x1E0581A4,0x00000000 ++#define IPU_DC_UGDE3_0__FULL 0x1E0581A4,0xffffffff ++#define IPU_DC_UGDE3_0__NF_NL_3 0x1E0581A4,0x18000000 ++#define IPU_DC_UGDE3_0__AUTORESTART_3 0x1E0581A4,0x04000000 ++#define IPU_DC_UGDE3_0__ODD_EN_3 0x1E0581A4,0x02000000 ++#define IPU_DC_UGDE3_0__COD_ODD_START_3 0x1E0581A4,0x00FF0000 ++#define IPU_DC_UGDE3_0__COD_EV_START_3 0x1E0581A4,0x00007F80 ++#define IPU_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1E0581A4,0x00000078 ++#define IPU_DC_UGDE3_0__ID_CODED_3 0x1E0581A4,0x00000007 ++ ++#define IPU_DC_UGDE3_1__ADDR 0x1E0581A8 ++#define IPU_DC_UGDE3_1__EMPTY 0x1E0581A8,0x00000000 ++#define IPU_DC_UGDE3_1__FULL 0x1E0581A8,0xffffffff ++#define IPU_DC_UGDE3_1__STEP_3 0x1E0581A8,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_2__ADDR 0x1E0581AC ++#define IPU_DC_UGDE3_2__EMPTY 0x1E0581AC,0x00000000 ++#define IPU_DC_UGDE3_2__FULL 0x1E0581AC,0xffffffff ++#define IPU_DC_UGDE3_2__OFFSET_DT_3 0x1E0581AC,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_3__ADDR 0x1E0581B0 ++#define IPU_DC_UGDE3_3__EMPTY 0x1E0581B0,0x00000000 ++#define IPU_DC_UGDE3_3__FULL 0x1E0581B0,0xffffffff ++#define IPU_DC_UGDE3_3__STEP_REPEAT_3 0x1E0581B0,0x1FFFFFFF ++ ++#define IPU_DC_LLA0__ADDR 0x1E0581B4 ++#define IPU_DC_LLA0__EMPTY 0x1E0581B4,0x00000000 ++#define IPU_DC_LLA0__FULL 0x1E0581B4,0xffffffff ++#define IPU_DC_LLA0__MCU_RS_3_0 0x1E0581B4,0xFF000000 ++#define IPU_DC_LLA0__MCU_RS_2_0 0x1E0581B4,0x00FF0000 ++#define IPU_DC_LLA0__MCU_RS_1_0 0x1E0581B4,0x0000FF00 ++#define IPU_DC_LLA0__MCU_RS_0_0 0x1E0581B4,0x000000FF ++ ++#define IPU_DC_LLA1__ADDR 0x1E0581B8 ++#define IPU_DC_LLA1__EMPTY 0x1E0581B8,0x00000000 ++#define IPU_DC_LLA1__FULL 0x1E0581B8,0xffffffff ++#define IPU_DC_LLA1__MCU_RS_3_1 0x1E0581B8,0xFF000000 ++#define IPU_DC_LLA1__MCU_RS_2_1 0x1E0581B8,0x00FF0000 ++#define IPU_DC_LLA1__MCU_RS_1_1 0x1E0581B8,0x0000FF00 ++#define IPU_DC_LLA1__MCU_RS_0_1 0x1E0581B8,0x000000FF ++ ++#define IPU_DC_R_LLA0__ADDR 0x1E0581BC ++#define IPU_DC_R_LLA0__EMPTY 0x1E0581BC,0x00000000 ++#define IPU_DC_R_LLA0__FULL 0x1E0581BC,0xffffffff ++#define IPU_DC_R_LLA0__MCU_RS_R_3_0 0x1E0581BC,0xFF000000 ++#define IPU_DC_R_LLA0__MCU_RS_R_2_0 0x1E0581BC,0x00FF0000 ++#define IPU_DC_R_LLA0__MCU_RS_R_1_0 0x1E0581BC,0x0000FF00 ++#define IPU_DC_R_LLA0__MCU_RS_R_0_0 0x1E0581BC,0x000000FF ++ ++#define IPU_DC_R_LLA1__ADDR 0x1E0581C0 ++#define IPU_DC_R_LLA1__EMPTY 0x1E0581C0,0x00000000 ++#define IPU_DC_R_LLA1__FULL 0x1E0581C0,0xffffffff ++#define IPU_DC_R_LLA1__MCU_RS_R_3_1 0x1E0581C0,0xFF000000 ++#define IPU_DC_R_LLA1__MCU_RS_R_2_1 0x1E0581C0,0x00FF0000 ++#define IPU_DC_R_LLA1__MCU_RS_R_1_1 0x1E0581C0,0x0000FF00 ++#define IPU_DC_R_LLA1__MCU_RS_R_0_1 0x1E0581C0,0x000000FF ++ ++#define IPU_DC_WR_CH_ADDR_5_ALT__ADDR 0x1E0581C4 ++#define IPU_DC_WR_CH_ADDR_5_ALT__EMPTY 0x1E0581C4,0x00000000 ++#define IPU_DC_WR_CH_ADDR_5_ALT__FULL 0x1E0581C4,0xffffffff ++#define IPU_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1E0581C4,0x1FFFFFFF ++ ++#define IPU_DC_STAT__ADDR 0x1E0581C8 ++#define IPU_DC_STAT__EMPTY 0x1E0581C8,0x00000000 ++#define IPU_DC_STAT__FULL 0x1E0581C8,0xffffffff ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_1 0x1E0581C8,0x00000080 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_1 0x1E0581C8,0x00000040 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_1 0x1E0581C8,0x00000020 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_1 0x1E0581C8,0x00000010 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_0 0x1E0581C8,0x00000008 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_0 0x1E0581C8,0x00000004 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_0 0x1E0581C8,0x00000002 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_0 0x1E0581C8,0x00000001 ++ ++#define IPU_DMFC_RD_CHAN__ADDR 0x1E060000 ++#define IPU_DMFC_RD_CHAN__EMPTY 0x1E060000,0x00000000 ++#define IPU_DMFC_RD_CHAN__FULL 0x1E060000,0xffffffff ++#define IPU_DMFC_RD_CHAN__DMFC_PPW_C 0x1E060000,0x03000000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_CLR_0 0x1E060000,0x00E00000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_SET_0 0x1E060000,0x001C0000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_EN_0 0x1E060000,0x00020000 ++#define IPU_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1E060000,0x000000C0 ++ ++#define IPU_DMFC_WR_CHAN__ADDR 0x1E060004 ++#define IPU_DMFC_WR_CHAN__EMPTY 0x1E060004,0x00000000 ++#define IPU_DMFC_WR_CHAN__FULL 0x1E060004,0xffffffff ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1E060004,0xC0000000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C 0x1E060004,0x38000000 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2C 0x1E060004,0x07000000 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1E060004,0x00C00000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C 0x1E060004,0x00380000 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1C 0x1E060004,0x00070000 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2 0x1E060004,0x0000C000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2 0x1E060004,0x00003800 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2 0x1E060004,0x00000700 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1 0x1E060004,0x000000C0 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1 0x1E060004,0x00000038 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1 0x1E060004,0x00000007 ++ ++#define IPU_DMFC_WR_CHAN_DEF__ADDR 0x1E060008 ++#define IPU_DMFC_WR_CHAN_DEF__EMPTY 0x1E060008,0x00000000 ++#define IPU_DMFC_WR_CHAN_DEF__FULL 0x1E060008,0xffffffff ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1E060008,0xE0000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1E060008,0x1C000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C 0x1E060008,0x02000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1E060008,0x00E00000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1E060008,0x001C0000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C 0x1E060008,0x00020000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2 0x1E060008,0x0000E000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2 0x1E060008,0x00001C00 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2 0x1E060008,0x00000200 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1 0x1E060008,0x000000E0 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1 0x1E060008,0x0000001C ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1 0x1E060008,0x00000002 ++ ++#define IPU_DMFC_DP_CHAN__ADDR 0x1E06000C ++#define IPU_DMFC_DP_CHAN__EMPTY 0x1E06000C,0x00000000 ++#define IPU_DMFC_DP_CHAN__FULL 0x1E06000C,0xffffffff ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1E06000C,0xC0000000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F 0x1E06000C,0x38000000 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6F 0x1E06000C,0x07000000 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1E06000C,0x00C00000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B 0x1E06000C,0x00380000 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6B 0x1E06000C,0x00070000 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1E06000C,0x0000C000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F 0x1E06000C,0x00003800 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F 0x1E06000C,0x00000700 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1E06000C,0x000000C0 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B 0x1E06000C,0x00000038 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B 0x1E06000C,0x00000007 ++ ++#define IPU_DMFC_DP_CHAN_DEF__ADDR 0x1E060010 ++#define IPU_DMFC_DP_CHAN_DEF__EMPTY 0x1E060010,0x00000000 ++#define IPU_DMFC_DP_CHAN_DEF__FULL 0x1E060010,0xffffffff ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1E060010,0xE0000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1E060010,0x1C000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F 0x1E060010,0x02000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1E060010,0x00E00000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1E060010,0x001C0000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B 0x1E060010,0x00020000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1E060010,0x0000E000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1E060010,0x00001C00 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F 0x1E060010,0x00000200 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1E060010,0x000000E0 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1E060010,0x0000001C ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B 0x1E060010,0x00000002 ++ ++#define IPU_DMFC_GENERAL1__ADDR 0x1E060014 ++#define IPU_DMFC_GENERAL1__EMPTY 0x1E060014,0x00000000 ++#define IPU_DMFC_GENERAL1__FULL 0x1E060014,0xffffffff ++#define IPU_DMFC_GENERAL1__WAIT4EOT_9 0x1E060014,0x01000000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_6F 0x1E060014,0x00800000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_6B 0x1E060014,0x00400000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_5F 0x1E060014,0x00200000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_5B 0x1E060014,0x00100000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_4 0x1E060014,0x00080000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_3 0x1E060014,0x00040000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_2 0x1E060014,0x00020000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_1 0x1E060014,0x00010000 ++#define IPU_DMFC_GENERAL1__DMFC_WM_CLR_9 0x1E060014,0x0000E000 ++#define IPU_DMFC_GENERAL1__DMFC_WM_SET_9 0x1E060014,0x00001C00 ++#define IPU_DMFC_GENERAL1__DMFC_WM_EN_9 0x1E060014,0x00000200 ++#define IPU_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1E060014,0x00000060 ++#define IPU_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1E060014,0x00000003 ++ ++#define IPU_DMFC_GENERAL2__ADDR 0x1E060018 ++#define IPU_DMFC_GENERAL2__EMPTY 0x1E060018,0x00000000 ++#define IPU_DMFC_GENERAL2__FULL 0x1E060018,0xffffffff ++#define IPU_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1E060018,0x1FFF0000 ++#define IPU_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD 0x1E060018,0x00001FFF ++ ++#define IPU_DMFC_IC_CTRL__ADDR 0x1E06001C ++#define IPU_DMFC_IC_CTRL__EMPTY 0x1E06001C,0x00000000 ++#define IPU_DMFC_IC_CTRL__FULL 0x1E06001C,0xffffffff ++#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1E06001C,0xFFF80000 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD 0x1E06001C,0x0007FFC0 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_PPW_C 0x1E06001C,0x00000030 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_IN_PORT 0x1E06001C,0x00000007 ++ ++#define IPU_DMFC_STAT__ADDR 0x1E060020 ++#define IPU_DMFC_STAT__EMPTY 0x1E060020,0x00000000 ++#define IPU_DMFC_STAT__FULL 0x1E060020,0xffffffff ++#define IPU_DMFC_STAT__DMFC_IC_BUFFER_EMPTY 0x1E060020,0x02000000 ++#define IPU_DMFC_STAT__DMFC_IC_BUFFER_FULL 0x1E060020,0x01000000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_11 0x1E060020,0x00800000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_10 0x1E060020,0x00400000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_9 0x1E060020,0x00200000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_8 0x1E060020,0x00100000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_7 0x1E060020,0x00080000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_6 0x1E060020,0x00040000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_5 0x1E060020,0x00020000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_4 0x1E060020,0x00010000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_3 0x1E060020,0x00008000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_2 0x1E060020,0x00004000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_1 0x1E060020,0x00002000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_0 0x1E060020,0x00001000 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_11 0x1E060020,0x00000800 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_10 0x1E060020,0x00000400 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_9 0x1E060020,0x00000200 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_8 0x1E060020,0x00000100 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_7 0x1E060020,0x00000080 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_6 0x1E060020,0x00000040 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_5 0x1E060020,0x00000020 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_4 0x1E060020,0x00000010 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_3 0x1E060020,0x00000008 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_2 0x1E060020,0x00000004 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_1 0x1E060020,0x00000002 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_0 0x1E060020,0x00000001 ++ ++#define CPMEM_WORD0_DATA0_INT__ADDR 0x1F000000 ++#define CPMEM_WORD0_DATA0_INT__EMPTY 0x1F000000,0x00000000 ++#define CPMEM_WORD0_DATA0_INT__FULL 0x1F000000,0xffffffff ++#define CPMEM_WORD0_DATA0_INT__XB 0x1F000000,0xFFF80000 ++#define CPMEM_WORD0_DATA0_INT__YV 0x1F000000,0x0007FC00 ++#define CPMEM_WORD0_DATA0_INT__XV 0x1F000000,0x000003FF ++ ++#define CPMEM_WORD0_DATA1_INT__ADDR 0x1F000004 ++#define CPMEM_WORD0_DATA1_INT__EMPTY 0x1F000004,0x00000000 ++#define CPMEM_WORD0_DATA1_INT__FULL 0x1F000004,0xffffffff ++#define CPMEM_WORD0_DATA1_INT__SY_LOW 0x1F000004,0xFC000000 ++#define CPMEM_WORD0_DATA1_INT__SX 0x1F000004,0x03FFC000 ++#define CPMEM_WORD0_DATA1_INT__CF 0x1F000004,0x00002000 ++#define CPMEM_WORD0_DATA1_INT__NSB_B 0x1F000004,0x00001000 ++#define CPMEM_WORD0_DATA1_INT__YB 0x1F000004,0x00000FFF ++ ++#define CPMEM_WORD0_DATA2_INT__ADDR 0x1F000008 ++#define CPMEM_WORD0_DATA2_INT__EMPTY 0x1F000008,0x00000000 ++#define CPMEM_WORD0_DATA2_INT__FULL 0x1F000008,0xffffffff ++#define CPMEM_WORD0_DATA2_INT__SM 0x1F000008,0xFFC00000 ++#define CPMEM_WORD0_DATA2_INT__SDX 0x1F000008,0x003F8000 ++#define CPMEM_WORD0_DATA2_INT__NS 0x1F000008,0x00007FE0 ++#define CPMEM_WORD0_DATA2_INT__SY_HIGH 0x1F000008,0x0000001F ++ ++#define CPMEM_WORD0_DATA3_INT__ADDR 0x1F00000C ++#define CPMEM_WORD0_DATA3_INT__EMPTY 0x1F00000C,0x00000000 ++#define CPMEM_WORD0_DATA3_INT__FULL 0x1F00000C,0xffffffff ++#define CPMEM_WORD0_DATA3_INT__FW_LOW 0x1F00000C,0xE0000000 ++#define CPMEM_WORD0_DATA3_INT__CAE 0x1F00000C,0x10000000 ++#define CPMEM_WORD0_DATA3_INT__CAP 0x1F00000C,0x08000000 ++#define CPMEM_WORD0_DATA3_INT__THE 0x1F00000C,0x04000000 ++#define CPMEM_WORD0_DATA3_INT__VF 0x1F00000C,0x02000000 ++#define CPMEM_WORD0_DATA3_INT__HF 0x1F00000C,0x01000000 ++#define CPMEM_WORD0_DATA3_INT__ROT 0x1F00000C,0x00800000 ++#define CPMEM_WORD0_DATA3_INT__BM 0x1F00000C,0x00600000 ++#define CPMEM_WORD0_DATA3_INT__BNDM 0x1F00000C,0x001C0000 ++#define CPMEM_WORD0_DATA3_INT__SO 0x1F00000C,0x00020000 ++#define CPMEM_WORD0_DATA3_INT__DIM 0x1F00000C,0x00010000 ++#define CPMEM_WORD0_DATA3_INT__DEC_SEL 0x1F00000C,0x0000C000 ++#define CPMEM_WORD0_DATA3_INT__BPP 0x1F00000C,0x00003800 ++#define CPMEM_WORD0_DATA3_INT__SDRY 0x1F00000C,0x00000400 ++#define CPMEM_WORD0_DATA3_INT__SDRX 0x1F00000C,0x00000200 ++#define CPMEM_WORD0_DATA3_INT__SDY 0x1F00000C,0x000001FC ++#define CPMEM_WORD0_DATA3_INT__SCE 0x1F00000C,0x00000002 ++#define CPMEM_WORD0_DATA3_INT__SCC 0x1F00000C,0x00000001 ++ ++#define CPMEM_WORD0_DATA4_INT__ADDR 0x1F000010 ++#define CPMEM_WORD0_DATA4_INT__EMPTY 0x1F000010,0x00000000 ++#define CPMEM_WORD0_DATA4_INT__FULL 0x1F000010,0xffffffff ++#define CPMEM_WORD0_DATA4_INT__RESERVED 0x1F000010,0xFFC00000 ++#define CPMEM_WORD0_DATA4_INT__FH 0x1F000010,0x003FFC00 ++#define CPMEM_WORD0_DATA4_INT__FW_HIGH 0x1F000010,0x000003FF ++ ++#define CPMEM_WORD0_DATA0_N_INT__ADDR 0x1F000000 ++#define CPMEM_WORD0_DATA0_N_INT__EMPTY 0x1F000000,0x00000000 ++#define CPMEM_WORD0_DATA0_N_INT__FULL 0x1F000000,0xffffffff ++#define CPMEM_WORD0_DATA0_N_INT__XB 0x1F000000,0xFFF80000 ++#define CPMEM_WORD0_DATA0_N_INT__YV 0x1F000000,0x0007FC00 ++#define CPMEM_WORD0_DATA0_N_INT__XV 0x1F000000,0x000003FF ++ ++#define CPMEM_WORD0_DATA1_N_INT__ADDR 0x1F000004 ++#define CPMEM_WORD0_DATA1_N_INT__EMPTY 0x1F000004,0x00000000 ++#define CPMEM_WORD0_DATA1_N_INT__FULL 0x1F000004,0xffffffff ++#define CPMEM_WORD0_DATA1_N_INT__UBO_LOW 0x1F000004,0xFFFFC000 ++#define CPMEM_WORD0_DATA1_N_INT__CF 0x1F000004,0x00002000 ++#define CPMEM_WORD0_DATA1_N_INT__NSB_B 0x1F000004,0x00001000 ++#define CPMEM_WORD0_DATA1_N_INT__YB 0x1F000004,0x00000FFF ++ ++#define CPMEM_WORD0_DATA2_N_INT__ADDR 0x1F000008 ++#define CPMEM_WORD0_DATA2_N_INT__EMPTY 0x1F000008,0x00000000 ++#define CPMEM_WORD0_DATA2_N_INT__FULL 0x1F000008,0xffffffff ++#define CPMEM_WORD0_DATA2_N_INT__RESERVED 0x1F000008,0xFC000000 ++#define CPMEM_WORD0_DATA2_N_INT__VBO 0x1F000008,0x03FFFFF0 ++#define CPMEM_WORD0_DATA2_N_INT__UBO_HIGH 0x1F000008,0x0000000F ++ ++#define CPMEM_WORD0_DATA3_N_INT__ADDR 0x1F00000C ++#define CPMEM_WORD0_DATA3_N_INT__EMPTY 0x1F00000C,0x00000000 ++#define CPMEM_WORD0_DATA3_N_INT__FULL 0x1F00000C,0xffffffff ++#define CPMEM_WORD0_DATA3_N_INT__FW_LOW 0x1F00000C,0xE0000000 ++#define CPMEM_WORD0_DATA3_N_INT__CAE 0x1F00000C,0x10000000 ++#define CPMEM_WORD0_DATA3_N_INT__CAP 0x1F00000C,0x08000000 ++#define CPMEM_WORD0_DATA3_N_INT__THE 0x1F00000C,0x04000000 ++#define CPMEM_WORD0_DATA3_N_INT__VF 0x1F00000C,0x02000000 ++#define CPMEM_WORD0_DATA3_N_INT__HF 0x1F00000C,0x01000000 ++#define CPMEM_WORD0_DATA3_N_INT__ROT 0x1F00000C,0x00800000 ++#define CPMEM_WORD0_DATA3_N_INT__BM 0x1F00000C,0x00600000 ++#define CPMEM_WORD0_DATA3_N_INT__BNDM 0x1F00000C,0x001C0000 ++#define CPMEM_WORD0_DATA3_N_INT__SO 0x1F00000C,0x00020000 ++#define CPMEM_WORD0_DATA3_N_INT__RESERVED 0x1F00000C,0x0001FFFF ++ ++#define CPMEM_WORD0_DATA4_N_INT__ADDR 0x1F000010 ++#define CPMEM_WORD0_DATA4_N_INT__EMPTY 0x1F000010,0x00000000 ++#define CPMEM_WORD0_DATA4_N_INT__FULL 0x1F000010,0xffffffff ++#define CPMEM_WORD0_DATA4_N_INT__RESERVED 0x1F000010,0xFFC00000 ++#define CPMEM_WORD0_DATA4_N_INT__FH 0x1F000010,0x003FFC00 ++#define CPMEM_WORD0_DATA4_N_INT__FW_HIGH 0x1F000010,0x000003FF ++ ++#define CPMEM_WORD1_DATA0_INT__ADDR 0x1F000020 ++#define CPMEM_WORD1_DATA0_INT__EMPTY 0x1F000020,0x00000000 ++#define CPMEM_WORD1_DATA0_INT__FULL 0x1F000020,0xffffffff ++#define CPMEM_WORD1_DATA0_INT__EBA1_LOW 0x1F000020,0xE0000000 ++#define CPMEM_WORD1_DATA0_INT__EBA0 0x1F000020,0x1FFFFFFF ++ ++#define CPMEM_WORD1_DATA1_INT__ADDR 0x1F000024 ++#define CPMEM_WORD1_DATA1_INT__EMPTY 0x1F000024,0x00000000 ++#define CPMEM_WORD1_DATA1_INT__FULL 0x1F000024,0xffffffff ++#define CPMEM_WORD1_DATA1_INT__ILO_LOW 0x1F000024,0xFC000000 ++#define CPMEM_WORD1_DATA1_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF ++ ++#define CPMEM_WORD1_DATA2_INT__ADDR 0x1F000028 ++#define CPMEM_WORD1_DATA2_INT__EMPTY 0x1F000028,0x00000000 ++#define CPMEM_WORD1_DATA2_INT__FULL 0x1F000028,0xffffffff ++#define CPMEM_WORD1_DATA2_INT__TH_LOW 0x1F000028,0x80000000 ++#define CPMEM_WORD1_DATA2_INT__ID 0x1F000028,0x60000000 ++#define CPMEM_WORD1_DATA2_INT__ALBM 0x1F000028,0x1C000000 ++#define CPMEM_WORD1_DATA2_INT__ALU 0x1F000028,0x02000000 ++#define CPMEM_WORD1_DATA2_INT__PFS 0x1F000028,0x01E00000 ++#define CPMEM_WORD1_DATA2_INT__NPB 0x1F000028,0x001FC000 ++#define CPMEM_WORD1_DATA2_INT__ILO_HIGH 0x1F000028,0x00003FFF ++ ++#define CPMEM_WORD1_DATA3_INT__ADDR 0x1F00002C ++#define CPMEM_WORD1_DATA3_INT__EMPTY 0x1F00002C,0x00000000 ++#define CPMEM_WORD1_DATA3_INT__FULL 0x1F00002C,0xffffffff ++#define CPMEM_WORD1_DATA3_INT__WID3 0x1F00002C,0xE0000000 ++#define CPMEM_WORD1_DATA3_INT__WID2 0x1F00002C,0x1C000000 ++#define CPMEM_WORD1_DATA3_INT__WID1 0x1F00002C,0x03800000 ++#define CPMEM_WORD1_DATA3_INT__WID0 0x1F00002C,0x00700000 ++#define CPMEM_WORD1_DATA3_INT__SL 0x1F00002C,0x000FFFC0 ++#define CPMEM_WORD1_DATA3_INT__TH_HIGH 0x1F00002C,0x0000003F ++ ++#define CPMEM_WORD1_DATA4_INT__ADDR 0x1F000030 ++#define CPMEM_WORD1_DATA4_INT__EMPTY 0x1F000030,0x00000000 ++#define CPMEM_WORD1_DATA4_INT__FULL 0x1F000030,0xffffffff ++#define CPMEM_WORD1_DATA4_INT__RESERVED 0x1F000030,0xFFF00000 ++#define CPMEM_WORD1_DATA4_INT__OFS3 0x1F000030,0x000F8000 ++#define CPMEM_WORD1_DATA4_INT__OFS2 0x1F000030,0x00007C00 ++#define CPMEM_WORD1_DATA4_INT__OFS1 0x1F000030,0x000003E0 ++#define CPMEM_WORD1_DATA4_INT__OFS0 0x1F000030,0x0000001F ++ ++#define CPMEM_WORD1_DATA0_N_INT__ADDR 0x1F000020 ++#define CPMEM_WORD1_DATA0_N_INT__EMPTY 0x1F000020,0x00000000 ++#define CPMEM_WORD1_DATA0_N_INT__FULL 0x1F000020,0xffffffff ++#define CPMEM_WORD1_DATA0_N_INT__EBA1_LOW 0x1F000020,0xE0000000 ++#define CPMEM_WORD1_DATA0_N_INT__EBA0 0x1F000020,0x1FFFFFFF ++ ++#define CPMEM_WORD1_DATA1_N_INT__ADDR 0x1F000024 ++#define CPMEM_WORD1_DATA1_N_INT__EMPTY 0x1F000024,0x00000000 ++#define CPMEM_WORD1_DATA1_N_INT__FULL 0x1F000024,0xffffffff ++#define CPMEM_WORD1_DATA1_N_INT__ILO_LOW 0x1F000024,0xFC000000 ++#define CPMEM_WORD1_DATA1_N_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF ++ ++#define CPMEM_WORD1_DATA2_N_INT__ADDR 0x1F000028 ++#define CPMEM_WORD1_DATA2_N_INT__EMPTY 0x1F000028,0x00000000 ++#define CPMEM_WORD1_DATA2_N_INT__FULL 0x1F000028,0xffffffff ++#define CPMEM_WORD1_DATA2_N_INT__TH_LOW 0x1F000028,0x80000000 ++#define CPMEM_WORD1_DATA2_N_INT__ID 0x1F000028,0x60000000 ++#define CPMEM_WORD1_DATA2_N_INT__ALBM 0x1F000028,0x1C000000 ++#define CPMEM_WORD1_DATA2_N_INT__ALU 0x1F000028,0x02000000 ++#define CPMEM_WORD1_DATA2_N_INT__PFS 0x1F000028,0x01E00000 ++#define CPMEM_WORD1_DATA2_N_INT__NPB 0x1F000028,0x001FC000 ++#define CPMEM_WORD1_DATA2_N_INT__ILO_HIGH 0x1F000028,0x00003FFF ++ ++#define CPMEM_WORD1_DATA3_N_INT__ADDR 0x1F00002C ++#define CPMEM_WORD1_DATA3_N_INT__EMPTY 0x1F00002C,0x00000000 ++#define CPMEM_WORD1_DATA3_N_INT__FULL 0x1F00002C,0xffffffff ++#define CPMEM_WORD1_DATA3_N_INT__SLY 0x1F00002C,0x000FFFC0 ++#define CPMEM_WORD1_DATA3_N_INT__WID3 0x1F00002C,0xE0000000 ++#define CPMEM_WORD1_DATA3_N_INT__TH_HIGH 0x1F00002C,0x0000003F ++ ++#define CPMEM_WORD1_DATA4_N_INT__ADDR 0x1F000030 ++#define CPMEM_WORD1_DATA4_N_INT__EMPTY 0x1F000030,0x00000000 ++#define CPMEM_WORD1_DATA4_N_INT__FULL 0x1F000030,0xffffffff ++#define CPMEM_WORD1_DATA4_N_INT__RESERVED 0x1F000030,0xFFFFC000 ++#define CPMEM_WORD1_DATA4_N_INT__SLUV 0x1F000030,0x00003FFF ++ ++#define IC_INTERNAL_MEM_FW 0x400 ++#define TASK1_TMP_COEF IC_INTERNAL_MEM_FW ++#define TASK1_CSC1_W0 (TASK1_TMP_COEF+1) ++#define TASK1_CSC1_W1 (TASK1_CSC1_W0+1) ++#define TASK1_CSC1_W2 (TASK1_CSC1_W1+1 ) ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR (0x1F060000 + (TASK1_CSC1_W0 << 3)) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__FULL IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C00 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C11 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C22 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR 0x1F060000 + (TASK1_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__FULL IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SCALE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR 0x1F060000 + (TASK1_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__FULL IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C01 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C10 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C20 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR 0x1F060000 + (TASK1_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__FULL IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR 0x1F060000 + (TASK1_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__FULL IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C02 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C12 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C21 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR 0x1F060000 + (TASK1_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__FULL IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x000000FF ++ ++#define TASK2_TMP_COEF (TASK1_CSC1_W2+IC_INTERNAL_MEM_FW+1) ++#define TASK2_CSC1_W0 (TASK2_TMP_COEF+1) ++#define TASK2_CSC1_W1 (TASK2_CSC1_W0+1) ++#define TASK2_CSC1_W2 (TASK2_CSC1_W1+1) ++#define TASK2_CSC2_W0 (TASK2_CSC1_W2+1) ++#define TASK2_CSC2_W1 (TASK2_CSC2_W0+1) ++#define TASK2_CSC2_W2 (TASK2_CSC2_W1+1) ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR (0x1F060000 + (TASK2_CSC1_W0 << 3)) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C00 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C11 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C22 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR 0x1F060000 + (TASK2_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SCALE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR 0x1F060000 + (TASK2_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C01 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C10 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C20 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR 0x1F060000 + (TASK2_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR 0x1F060000 + (TASK2_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C02 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C12 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C21 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR 0x1F060000 + (TASK2_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR 0x1F060000 + (TASK2_CSC2_W0 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C00 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C11 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C22 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR 0x1F060000 + (TASK2_CSC2_W0 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SCALE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__A0_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR 0x1F060000 + (TASK2_CSC2_W1 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C01 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C10 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C20 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR 0x1F060000 + (TASK2_CSC2_W1 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR 0x1F060000 + (TASK2_CSC2_W2 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C02 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C12 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C21 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR 0x1F060000 + (TASK2_CSC2_W2 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x000000FF ++ ++#define TASK3_TMP_COEF (TASK2_CSC2_W2+IC_INTERNAL_MEM_FW+1) ++#define TASK3_CSC1_W0 (TASK3_TMP_COEF+1) ++#define TASK3_CSC1_W1 (TASK3_CSC1_W0+1) ++#define TASK3_CSC1_W2 (TASK3_CSC1_W1+1) ++#define TASK3_CSC2_W0 (TASK3_CSC1_W2+1) ++#define TASK3_CSC2_W1 (TASK3_CSC2_W0+1) ++#define TASK3_CSC2_W2 (TASK3_CSC2_W1+1) ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR (0x1F060000 + (TASK3_CSC1_W0 << 3)) ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__FULL IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C00 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C11 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C22 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR 0x1F060000 + (TASK3_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__FULL IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__SCALE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR 0x1F060000 + (TASK3_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__FULL IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C01 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C10 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C20 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR 0x1F060000 + (TASK3_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__FULL IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR 0x1F060000 + (TASK3_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__FULL IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C02 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C12 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C21 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR 0x1F060000 + (TASK3_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__FULL IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR 0x1F060000 + (TASK3_CSC2_W0 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__FULL IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C00 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C11 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C22 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR 0x1F060000 + (TASK3_CSC2_W0 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__FULL IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__SCALE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__A0_HIGH IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR 0x1F060000 + (TASK3_CSC2_W1 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__FULL IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C01 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C10 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C20 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR 0x1F060000 + (TASK3_CSC2_W1 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__FULL IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR 0x1F060000 + (TASK3_CSC2_W2 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__FULL IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C02 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C12 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C21 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR 0x1F060000 + (TASK3_CSC2_W2 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__FULL IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x000000FF ++ ++#define SRM_DP_COM_CONF_SYNC__ADDR 0x1F040000 ++#define SRM_DP_COM_CONF_SYNC__EMPTY 0x1F040000,0x00000000 ++#define SRM_DP_COM_CONF_SYNC__FULL 0x1F040000,0xffffffff ++#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC 0x1F040000,0x00002000 ++#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC 0x1F040000,0x00001000 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1F040000,0x00000800 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1F040000,0x00000400 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC 0x1F040000,0x00000300 ++#define SRM_DP_COM_CONF_SYNC__DP_COC_SYNC 0x1F040000,0x00000070 ++#define SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC 0x1F040000,0x00000008 ++#define SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC 0x1F040000,0x00000004 ++#define SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC 0x1F040000,0x00000002 ++#define SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC 0x1F040000,0x00000001 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__ADDR 0x1F040004 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__EMPTY 0x1F040004,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__FULL 0x1F040004,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC 0x1F040004,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1F040004,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1F040004,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1F040004,0x000000FF ++ ++#define SRM_DP_FG_POS_SYNC__ADDR 0x1F040008 ++#define SRM_DP_FG_POS_SYNC__EMPTY 0x1F040008,0x00000000 ++#define SRM_DP_FG_POS_SYNC__FULL 0x1F040008,0xffffffff ++#define SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1F040008,0x07FF0000 ++#define SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1F040008,0x000007FF ++ ++#define SRM_DP_CUR_POS_SYNC__ADDR 0x1F04000C ++#define SRM_DP_CUR_POS_SYNC__EMPTY 0x1F04000C,0x00000000 ++#define SRM_DP_CUR_POS_SYNC__FULL 0x1F04000C,0xffffffff ++#define SRM_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1F04000C,0xF8000000 ++#define SRM_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1F04000C,0x07FF0000 ++#define SRM_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1F04000C,0x0000F800 ++#define SRM_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1F04000C,0x000007FF ++ ++#define SRM_DP_CUR_MAP_SYNC__ADDR 0x1F040010 ++#define SRM_DP_CUR_MAP_SYNC__EMPTY 0x1F040010,0x00000000 ++#define SRM_DP_CUR_MAP_SYNC__FULL 0x1F040010,0xffffffff ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1F040010,0x00FF0000 ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1F040010,0x0000FF00 ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1F040010,0x000000FF ++ ++#define SRM_DP_GAMMA_C_SYNC_0__ADDR 0x1F040014 ++#define SRM_DP_GAMMA_C_SYNC_0__EMPTY 0x1F040014,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_0__FULL 0x1F040014,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1F040014,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1F040014,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_1__ADDR 0x1F040018 ++#define SRM_DP_GAMMA_C_SYNC_1__EMPTY 0x1F040018,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_1__FULL 0x1F040018,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1F040018,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1F040018,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_2__ADDR 0x1F04001C ++#define SRM_DP_GAMMA_C_SYNC_2__EMPTY 0x1F04001C,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_2__FULL 0x1F04001C,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1F04001C,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1F04001C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_3__ADDR 0x1F040020 ++#define SRM_DP_GAMMA_C_SYNC_3__EMPTY 0x1F040020,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_3__FULL 0x1F040020,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1F040020,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1F040020,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_4__ADDR 0x1F040024 ++#define SRM_DP_GAMMA_C_SYNC_4__EMPTY 0x1F040024,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_4__FULL 0x1F040024,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1F040024,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1F040024,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_5__ADDR 0x1F040028 ++#define SRM_DP_GAMMA_C_SYNC_5__EMPTY 0x1F040028,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_5__FULL 0x1F040028,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1F040028,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1F040028,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_6__ADDR 0x1F04002C ++#define SRM_DP_GAMMA_C_SYNC_6__EMPTY 0x1F04002C,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_6__FULL 0x1F04002C,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1F04002C,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1F04002C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_7__ADDR 0x1F040030 ++#define SRM_DP_GAMMA_C_SYNC_7__EMPTY 0x1F040030,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_7__FULL 0x1F040030,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1F040030,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1F040030,0x000001FF ++ ++#define SRM_DP_GAMMA_S_SYNC_0__ADDR 0x1F040034 ++#define SRM_DP_GAMMA_S_SYNC_0__EMPTY 0x1F040034,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_0__FULL 0x1F040034,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1F040034,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1F040034,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1F040034,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1F040034,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_1__ADDR 0x1F040038 ++#define SRM_DP_GAMMA_S_SYNC_1__EMPTY 0x1F040038,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_1__FULL 0x1F040038,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1F040038,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1F040038,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1F040038,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1F040038,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_2__ADDR 0x1F04003C ++#define SRM_DP_GAMMA_S_SYNC_2__EMPTY 0x1F04003C,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_2__FULL 0x1F04003C,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1F04003C,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1F04003C,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9 0x1F04003C,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8 0x1F04003C,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_3__ADDR 0x1F040040 ++#define SRM_DP_GAMMA_S_SYNC_3__EMPTY 0x1F040040,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_3__FULL 0x1F040040,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1F040040,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1F040040,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1F040040,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1F040040,0x000000FF ++ ++#define SRM_DP_CSCA_SYNC_0__ADDR 0x1F040044 ++#define SRM_DP_CSCA_SYNC_0__EMPTY 0x1F040044,0x00000000 ++#define SRM_DP_CSCA_SYNC_0__FULL 0x1F040044,0xffffffff ++#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1F040044,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1F040044,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_1__ADDR 0x1F040048 ++#define SRM_DP_CSCA_SYNC_1__EMPTY 0x1F040048,0x00000000 ++#define SRM_DP_CSCA_SYNC_1__FULL 0x1F040048,0xffffffff ++#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1F040048,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1F040048,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_2__ADDR 0x1F04004C ++#define SRM_DP_CSCA_SYNC_2__EMPTY 0x1F04004C,0x00000000 ++#define SRM_DP_CSCA_SYNC_2__FULL 0x1F04004C,0xffffffff ++#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1F04004C,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1F04004C,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_3__ADDR 0x1F040050 ++#define SRM_DP_CSCA_SYNC_3__EMPTY 0x1F040050,0x00000000 ++#define SRM_DP_CSCA_SYNC_3__FULL 0x1F040050,0xffffffff ++#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1F040050,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1F040050,0x000003FF ++ ++#define SRM_DP_CSC_SYNC_0__ADDR 0x1F040054 ++#define SRM_DP_CSC_SYNC_0__EMPTY 0x1F040054,0x00000000 ++#define SRM_DP_CSC_SYNC_0__FULL 0x1F040054,0xffffffff ++#define SRM_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1F040054,0xC0000000 ++#define SRM_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1F040054,0x3FFF0000 ++#define SRM_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1F040054,0x000003FF ++ ++#define SRM_DP_CSC_SYNC_1__ADDR 0x1F040058 ++#define SRM_DP_CSC_SYNC_1__EMPTY 0x1F040058,0x00000000 ++#define SRM_DP_CSC_SYNC_1__FULL 0x1F040058,0xffffffff ++#define SRM_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1F040058,0xC0000000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1F040058,0x3FFF0000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1F040058,0x0000C000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1F040058,0x00003FFF ++ ++#define SRM_DP_CUR_POS_ALT__ADDR 0x1F04005C ++#define SRM_DP_CUR_POS_ALT__EMPTY 0x1F04005C,0x00000000 ++#define SRM_DP_CUR_POS_ALT__FULL 0x1F04005C,0xffffffff ++#define SRM_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1F04005C,0xF8000000 ++#define SRM_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1F04005C,0x07FF0000 ++#define SRM_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1F04005C,0x0000F800 ++#define SRM_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1F04005C,0x000007FF ++ ++#define SRM_DP_COM_CONF_ASYNC0__ADDR 0x1F040060 ++#define SRM_DP_COM_CONF_ASYNC0__EMPTY 0x1F040060,0x00000000 ++#define SRM_DP_COM_CONF_ASYNC0__FULL 0x1F040060,0xffffffff ++#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_YUV_EN_ASYNC0 0x1F040060,0x00002000 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_EN_ASYNC0 0x1F040060,0x00001000 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_YUV_SAT_MODE_ASYNC0 0x1F040060,0x00000800 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_GAMUT_SAT_EN_ASYNC0 0x1F040060,0x00000400 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_DEF_ASYNC0 0x1F040060,0x00000300 ++#define SRM_DP_COM_CONF_ASYNC0__DP_COC_ASYNC0 0x1F040060,0x00000070 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWCKE_ASYNC0 0x1F040060,0x00000008 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWAM_ASYNC0 0x1F040060,0x00000004 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWSEL_ASYNC0 0x1F040060,0x00000002 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__ADDR 0x1F040064 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__EMPTY 0x1F040064,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__FULL 0x1F040064,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWAV_ASYNC0 0x1F040064,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKR_ASYNC0 0x1F040064,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKG_ASYNC0 0x1F040064,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKB_ASYNC0 0x1F040064,0x000000FF ++ ++#define SRM_DP_FG_POS_ASYNC0__ADDR 0x1F040068 ++#define SRM_DP_FG_POS_ASYNC0__EMPTY 0x1F040068,0x00000000 ++#define SRM_DP_FG_POS_ASYNC0__FULL 0x1F040068,0xffffffff ++#define SRM_DP_FG_POS_ASYNC0__DP_FGXP_ASYNC0 0x1F040068,0x07FF0000 ++#define SRM_DP_FG_POS_ASYNC0__DP_FGYP_ASYNC0 0x1F040068,0x000007FF ++ ++#define SRM_DP_CUR_POS_ASYNC0__ADDR 0x1F04006C ++#define SRM_DP_CUR_POS_ASYNC0__EMPTY 0x1F04006C,0x00000000 ++#define SRM_DP_CUR_POS_ASYNC0__FULL 0x1F04006C,0xffffffff ++#define SRM_DP_CUR_POS_ASYNC0__DP_CXW_ASYNC0 0x1F04006C,0xF8000000 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CXP_ASYNC0 0x1F04006C,0x07FF0000 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CYH_ASYNC0 0x1F04006C,0x0000F800 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CYP_ASYNC0 0x1F04006C,0x000007FF ++ ++#define SRM_DP_CUR_MAP_ASYNC0__ADDR 0x1F040070 ++#define SRM_DP_CUR_MAP_ASYNC0__EMPTY 0x1F040070,0x00000000 ++#define SRM_DP_CUR_MAP_ASYNC0__FULL 0x1F040070,0xffffffff ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_R_ASYNC0 0x1F040070,0x00FF0000 ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_G_ASYNC0 0x1F040070,0x0000FF00 ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_B_ASYNC0 0x1F040070,0x000000FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_0__ADDR 0x1F040074 ++#define SRM_DP_GAMMA_C_ASYNC0_0__EMPTY 0x1F040074,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_0__FULL 0x1F040074,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_1 0x1F040074,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_0 0x1F040074,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_1__ADDR 0x1F040078 ++#define SRM_DP_GAMMA_C_ASYNC0_1__EMPTY 0x1F040078,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_1__FULL 0x1F040078,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_3 0x1F040078,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_2 0x1F040078,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_2__ADDR 0x1F04007C ++#define SRM_DP_GAMMA_C_ASYNC0_2__EMPTY 0x1F04007C,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_2__FULL 0x1F04007C,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_5 0x1F04007C,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_4 0x1F04007C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_3__ADDR 0x1F040080 ++#define SRM_DP_GAMMA_C_ASYNC0_3__EMPTY 0x1F040080,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_3__FULL 0x1F040080,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_7 0x1F040080,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_6 0x1F040080,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_4__ADDR 0x1F040084 ++#define SRM_DP_GAMMA_C_ASYNC0_4__EMPTY 0x1F040084,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_4__FULL 0x1F040084,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_9 0x1F040084,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_8 0x1F040084,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_5__ADDR 0x1F040088 ++#define SRM_DP_GAMMA_C_ASYNC0_5__EMPTY 0x1F040088,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_5__FULL 0x1F040088,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_11 0x1F040088,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_10 0x1F040088,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_6__ADDR 0x1F04008C ++#define SRM_DP_GAMMA_C_ASYNC0_6__EMPTY 0x1F04008C,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_6__FULL 0x1F04008C,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_13 0x1F04008C,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_12 0x1F04008C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_7__ADDR 0x1F040090 ++#define SRM_DP_GAMMA_C_ASYNC0_7__EMPTY 0x1F040090,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_7__FULL 0x1F040090,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_15 0x1F040090,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_14 0x1F040090,0x000001FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_0__ADDR 0x1F040094 ++#define SRM_DP_GAMMA_S_ASYNC0_0__EMPTY 0x1F040094,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__FULL 0x1F040094,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_3 0x1F040094,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_2 0x1F040094,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_1 0x1F040094,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_0 0x1F040094,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_1__ADDR 0x1F040098 ++#define SRM_DP_GAMMA_S_ASYNC0_1__EMPTY 0x1F040098,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__FULL 0x1F040098,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_7 0x1F040098,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_6 0x1F040098,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_5 0x1F040098,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_4 0x1F040098,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_2__ADDR 0x1F04009C ++#define SRM_DP_GAMMA_S_ASYNC0_2__EMPTY 0x1F04009C,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__FULL 0x1F04009C,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_11 0x1F04009C,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_10 0x1F04009C,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_9 0x1F04009C,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_8 0x1F04009C,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_3__ADDR 0x1F0400A0 ++#define SRM_DP_GAMMA_S_ASYNC0_3__EMPTY 0x1F0400A0,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__FULL 0x1F0400A0,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_15 0x1F0400A0,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_14 0x1F0400A0,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_13 0x1F0400A0,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_12 0x1F0400A0,0x000000FF ++ ++#define SRM_DP_CSCA_ASYNC0_0__ADDR 0x1F0400A4 ++#define SRM_DP_CSCA_ASYNC0_0__EMPTY 0x1F0400A4,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_0__FULL 0x1F0400A4,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_1 0x1F0400A4,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_0 0x1F0400A4,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_1__ADDR 0x1F0400A8 ++#define SRM_DP_CSCA_ASYNC0_1__EMPTY 0x1F0400A8,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_1__FULL 0x1F0400A8,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_3 0x1F0400A8,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_2 0x1F0400A8,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_2__ADDR 0x1F0400AC ++#define SRM_DP_CSCA_ASYNC0_2__EMPTY 0x1F0400AC,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_2__FULL 0x1F0400AC,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_5 0x1F0400AC,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_4 0x1F0400AC,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_3__ADDR 0x1F0400B0 ++#define SRM_DP_CSCA_ASYNC0_3__EMPTY 0x1F0400B0,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_3__FULL 0x1F0400B0,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_7 0x1F0400B0,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_6 0x1F0400B0,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC0_0__ADDR 0x1F0400B4 ++#define SRM_DP_CSC_ASYNC0_0__EMPTY 0x1F0400B4,0x00000000 ++#define SRM_DP_CSC_ASYNC0_0__FULL 0x1F0400B4,0xffffffff ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_S0_ASYNC0 0x1F0400B4,0xC0000000 ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_B0_ASYNC0 0x1F0400B4,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_A8_ASYNC0 0x1F0400B4,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC0_1__ADDR 0x1F0400B8 ++#define SRM_DP_CSC_ASYNC0_1__EMPTY 0x1F0400B8,0x00000000 ++#define SRM_DP_CSC_ASYNC0_1__FULL 0x1F0400B8,0xffffffff ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S2_ASYNC0 0x1F0400B8,0xC0000000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B2_ASYNC0 0x1F0400B8,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S1_ASYNC0 0x1F0400B8,0x0000C000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B1_ASYNC0 0x1F0400B8,0x00003FFF ++ ++#define SRM_DP_COM_CONF_ASYNC1__ADDR 0x1F0400BC ++#define SRM_DP_COM_CONF_ASYNC1__EMPTY 0x1F0400BC,0x00000000 ++#define SRM_DP_COM_CONF_ASYNC1__FULL 0x1F0400BC,0xffffffff ++#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_YUV_EN_ASYNC1 0x1F0400BC,0x00002000 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_EN_ASYNC1 0x1F0400BC,0x00001000 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_YUV_SAT_MODE_ASYNC1 0x1F0400BC,0x00000800 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_GAMUT_SAT_EN_ASYNC1 0x1F0400BC,0x00000400 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_DEF_ASYNC1 0x1F0400BC,0x00000300 ++#define SRM_DP_COM_CONF_ASYNC1__DP_COC_ASYNC1 0x1F0400BC,0x00000070 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWCKE_ASYNC1 0x1F0400BC,0x00000008 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWAM_ASYNC1 0x1F0400BC,0x00000004 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWSEL_ASYNC1 0x1F0400BC,0x00000002 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__ADDR 0x1F0400C0 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__EMPTY 0x1F0400C0,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__FULL 0x1F0400C0,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWAV_ASYNC1 0x1F0400C0,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKR_ASYNC1 0x1F0400C0,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKG_ASYNC1 0x1F0400C0,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKB_ASYNC1 0x1F0400C0,0x000000FF ++ ++#define SRM_DP_FG_POS_ASYNC1__ADDR 0x1F0400C4 ++#define SRM_DP_FG_POS_ASYNC1__EMPTY 0x1F0400C4,0x00000000 ++#define SRM_DP_FG_POS_ASYNC1__FULL 0x1F0400C4,0xffffffff ++#define SRM_DP_FG_POS_ASYNC1__DP_FGXP_ASYNC1 0x1F0400C4,0x07FF0000 ++#define SRM_DP_FG_POS_ASYNC1__DP_FGYP_ASYNC1 0x1F0400C4,0x000007FF ++ ++#define SRM_DP_CUR_POS_ASYNC1__ADDR 0x1F0400C8 ++#define SRM_DP_CUR_POS_ASYNC1__EMPTY 0x1F0400C8,0x00000000 ++#define SRM_DP_CUR_POS_ASYNC1__FULL 0x1F0400C8,0xffffffff ++#define SRM_DP_CUR_POS_ASYNC1__DP_CXW_ASYNC1 0x1F0400C8,0xF8000000 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CXP_ASYNC1 0x1F0400C8,0x07FF0000 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CYH_ASYNC1 0x1F0400C8,0x0000F800 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CYP_ASYNC1 0x1F0400C8,0x000007FF ++ ++#define SRM_DP_CUR_MAP_ASYNC1__ADDR 0x1F0400CC ++#define SRM_DP_CUR_MAP_ASYNC1__EMPTY 0x1F0400CC,0x00000000 ++#define SRM_DP_CUR_MAP_ASYNC1__FULL 0x1F0400CC,0xffffffff ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_R_ASYNC1 0x1F0400CC,0x00FF0000 ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_G_ASYNC1 0x1F0400CC,0x0000FF00 ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_B_ASYNC1 0x1F0400CC,0x000000FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_0__ADDR 0x1F0400D0 ++#define SRM_DP_GAMMA_C_ASYNC1_0__EMPTY 0x1F0400D0,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_0__FULL 0x1F0400D0,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_1 0x1F0400D0,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_0 0x1F0400D0,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_1__ADDR 0x1F0400D4 ++#define SRM_DP_GAMMA_C_ASYNC1_1__EMPTY 0x1F0400D4,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_1__FULL 0x1F0400D4,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_3 0x1F0400D4,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_2 0x1F0400D4,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_2__ADDR 0x1F0400D8 ++#define SRM_DP_GAMMA_C_ASYNC1_2__EMPTY 0x1F0400D8,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_2__FULL 0x1F0400D8,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_5 0x1F0400D8,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_4 0x1F0400D8,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_3__ADDR 0x1F0400DC ++#define SRM_DP_GAMMA_C_ASYNC1_3__EMPTY 0x1F0400DC,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_3__FULL 0x1F0400DC,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_7 0x1F0400DC,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_6 0x1F0400DC,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_4__ADDR 0x1F0400E0 ++#define SRM_DP_GAMMA_C_ASYNC1_4__EMPTY 0x1F0400E0,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_4__FULL 0x1F0400E0,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_9 0x1F0400E0,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_8 0x1F0400E0,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_5__ADDR 0x1F0400E4 ++#define SRM_DP_GAMMA_C_ASYNC1_5__EMPTY 0x1F0400E4,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_5__FULL 0x1F0400E4,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_11 0x1F0400E4,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_10 0x1F0400E4,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_6__ADDR 0x1F0400E8 ++#define SRM_DP_GAMMA_C_ASYNC1_6__EMPTY 0x1F0400E8,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_6__FULL 0x1F0400E8,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_13 0x1F0400E8,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_12 0x1F0400E8,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_7__ADDR 0x1F0400EC ++#define SRM_DP_GAMMA_C_ASYNC1_7__EMPTY 0x1F0400EC,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_7__FULL 0x1F0400EC,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_15 0x1F0400EC,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_14 0x1F0400EC,0x000001FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_0__ADDR 0x1F0400F0 ++#define SRM_DP_GAMMA_S_ASYNC1_0__EMPTY 0x1F0400F0,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__FULL 0x1F0400F0,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_3 0x1F0400F0,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_2 0x1F0400F0,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_1 0x1F0400F0,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_0 0x1F0400F0,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_1__ADDR 0x1F0400F4 ++#define SRM_DP_GAMMA_S_ASYNC1_1__EMPTY 0x1F0400F4,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__FULL 0x1F0400F4,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_7 0x1F0400F4,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_6 0x1F0400F4,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_5 0x1F0400F4,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_4 0x1F0400F4,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_2__ADDR 0x1F0400F8 ++#define SRM_DP_GAMMA_S_ASYNC1_2__EMPTY 0x1F0400F8,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__FULL 0x1F0400F8,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_11 0x1F0400F8,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_10 0x1F0400F8,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_9 0x1F0400F8,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_8 0x1F0400F8,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_3__ADDR 0x1F0400FC ++#define SRM_DP_GAMMA_S_ASYNC1_3__EMPTY 0x1F0400FC,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__FULL 0x1F0400FC,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_15 0x1F0400FC,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_14 0x1F0400FC,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_13 0x1F0400FC,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_12 0x1F0400FC,0x000000FF ++ ++#define SRM_DP_CSCA_ASYNC1_0__ADDR 0x1F040100 ++#define SRM_DP_CSCA_ASYNC1_0__EMPTY 0x1F040100,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_0__FULL 0x1F040100,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_1 0x1F040100,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_0 0x1F040100,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_1__ADDR 0x1F040104 ++#define SRM_DP_CSCA_ASYNC1_1__EMPTY 0x1F040104,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_1__FULL 0x1F040104,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_3 0x1F040104,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_2 0x1F040104,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_2__ADDR 0x1F040108 ++#define SRM_DP_CSCA_ASYNC1_2__EMPTY 0x1F040108,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_2__FULL 0x1F040108,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_5 0x1F040108,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_4 0x1F040108,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_3__ADDR 0x1F04010C ++#define SRM_DP_CSCA_ASYNC1_3__EMPTY 0x1F04010C,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_3__FULL 0x1F04010C,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_7 0x1F04010C,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_6 0x1F04010C,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC1_0__ADDR 0x1F040110 ++#define SRM_DP_CSC_ASYNC1_0__EMPTY 0x1F040110,0x00000000 ++#define SRM_DP_CSC_ASYNC1_0__FULL 0x1F040110,0xffffffff ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_S0_ASYNC1 0x1F040110,0xC0000000 ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_B0_ASYNC1 0x1F040110,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_A8_ASYNC1 0x1F040110,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC1_1__ADDR 0x1F040114 ++#define SRM_DP_CSC_ASYNC1_1__EMPTY 0x1F040114,0x00000000 ++#define SRM_DP_CSC_ASYNC1_1__FULL 0x1F040114,0xffffffff ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S2_ASYNC1 0x1F040114,0xC0000000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B2_ASYNC1 0x1F040114,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S1_ASYNC1 0x1F040114,0x0000C000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B1_ASYNC1 0x1F040114,0x00003FFF ++ ++#define SRM_DI0_GENERAL__ADDR 0x1F040448 ++#define SRM_DI0_GENERAL__EMPTY 0x1F040448,0x00000000 ++#define SRM_DI0_GENERAL__FULL 0x1F040448,0xffffffff ++#define SRM_DI0_GENERAL__DI0_DISP_Y_SEL 0x1F040448,0x70000000 ++#define SRM_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1F040448,0x0F000000 ++#define SRM_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1F040448,0x00800000 ++#define SRM_DI0_GENERAL__DI0_MASK_SEL 0x1F040448,0x00400000 ++#define SRM_DI0_GENERAL__DI0_VSYNC_EXT 0x1F040448,0x00200000 ++#define SRM_DI0_GENERAL__DI0_CLK_EXT 0x1F040448,0x00100000 ++#define SRM_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1F040448,0x000C0000 ++#define SRM_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1F040448,0x00020000 ++#define SRM_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1F040448,0x0000F000 ++#define SRM_DI0_GENERAL__DI0_ERR_TREATMENT 0x1F040448,0x00000800 ++#define SRM_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1F040448,0x00000400 ++#define SRM_DI0_GENERAL__DI0_POLARITY_CS1 0x1F040448,0x00000200 ++#define SRM_DI0_GENERAL__DI0_POLARITY_CS0 0x1F040448,0x00000100 ++#define SRM_DI0_GENERAL__DI0_POLARITY_8 0x1F040448,0x00000080 ++#define SRM_DI0_GENERAL__DI0_POLARITY_7 0x1F040448,0x00000040 ++#define SRM_DI0_GENERAL__DI0_POLARITY_6 0x1F040448,0x00000020 ++#define SRM_DI0_GENERAL__DI0_POLARITY_5 0x1F040448,0x00000010 ++#define SRM_DI0_GENERAL__DI0_POLARITY_4 0x1F040448,0x00000008 ++#define SRM_DI0_GENERAL__DI0_POLARITY_3 0x1F040448,0x00000004 ++#define SRM_DI0_GENERAL__DI0_POLARITY_2 0x1F040448,0x00000002 ++#define SRM_DI0_GENERAL__DI0_POLARITY_1 0x1F040448,0x00000001 ++ ++#define SRM_DI0_BS_CLKGEN0__ADDR 0x1F04044C ++#define SRM_DI0_BS_CLKGEN0__EMPTY 0x1F04044C,0x00000000 ++#define SRM_DI0_BS_CLKGEN0__FULL 0x1F04044C,0xffffffff ++#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1F04044C,0x01FF0000 ++#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1F04044C,0x00000FFF ++ ++#define SRM_DI0_BS_CLKGEN1__ADDR 0x1F040450 ++#define SRM_DI0_BS_CLKGEN1__EMPTY 0x1F040450,0x00000000 ++#define SRM_DI0_BS_CLKGEN1__FULL 0x1F040450,0xffffffff ++#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1F040450,0x01FF0000 ++#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1F040450,0x000001FF ++ ++#define SRM_DI0_SW_GEN0_1__ADDR 0x1F040454 ++#define SRM_DI0_SW_GEN0_1__EMPTY 0x1F040454,0x00000000 ++#define SRM_DI0_SW_GEN0_1__FULL 0x1F040454,0xffffffff ++#define SRM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1 0x1F040454,0x7FF80000 ++#define SRM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1 0x1F040454,0x00070000 ++#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1 0x1F040454,0x00007FF8 ++#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1 0x1F040454,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_2__ADDR 0x1F040458 ++#define SRM_DI0_SW_GEN0_2__EMPTY 0x1F040458,0x00000000 ++#define SRM_DI0_SW_GEN0_2__FULL 0x1F040458,0xffffffff ++#define SRM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2 0x1F040458,0x7FF80000 ++#define SRM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2 0x1F040458,0x00070000 ++#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2 0x1F040458,0x00007FF8 ++#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2 0x1F040458,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_3__ADDR 0x1F04045C ++#define SRM_DI0_SW_GEN0_3__EMPTY 0x1F04045C,0x00000000 ++#define SRM_DI0_SW_GEN0_3__FULL 0x1F04045C,0xffffffff ++#define SRM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3 0x1F04045C,0x7FF80000 ++#define SRM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3 0x1F04045C,0x00070000 ++#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3 0x1F04045C,0x00007FF8 ++#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3 0x1F04045C,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_4__ADDR 0x1F040460 ++#define SRM_DI0_SW_GEN0_4__EMPTY 0x1F040460,0x00000000 ++#define SRM_DI0_SW_GEN0_4__FULL 0x1F040460,0xffffffff ++#define SRM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4 0x1F040460,0x7FF80000 ++#define SRM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4 0x1F040460,0x00070000 ++#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4 0x1F040460,0x00007FF8 ++#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4 0x1F040460,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_5__ADDR 0x1F040464 ++#define SRM_DI0_SW_GEN0_5__EMPTY 0x1F040464,0x00000000 ++#define SRM_DI0_SW_GEN0_5__FULL 0x1F040464,0xffffffff ++#define SRM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5 0x1F040464,0x7FF80000 ++#define SRM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5 0x1F040464,0x00070000 ++#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5 0x1F040464,0x00007FF8 ++#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5 0x1F040464,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_6__ADDR 0x1F040468 ++#define SRM_DI0_SW_GEN0_6__EMPTY 0x1F040468,0x00000000 ++#define SRM_DI0_SW_GEN0_6__FULL 0x1F040468,0xffffffff ++#define SRM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6 0x1F040468,0x7FF80000 ++#define SRM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6 0x1F040468,0x00070000 ++#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6 0x1F040468,0x00007FF8 ++#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6 0x1F040468,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_7__ADDR 0x1F04046C ++#define SRM_DI0_SW_GEN0_7__EMPTY 0x1F04046C,0x00000000 ++#define SRM_DI0_SW_GEN0_7__FULL 0x1F04046C,0xffffffff ++#define SRM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7 0x1F04046C,0x7FF80000 ++#define SRM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7 0x1F04046C,0x00070000 ++#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7 0x1F04046C,0x00007FF8 ++#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7 0x1F04046C,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_8__ADDR 0x1F040470 ++#define SRM_DI0_SW_GEN0_8__EMPTY 0x1F040470,0x00000000 ++#define SRM_DI0_SW_GEN0_8__FULL 0x1F040470,0xffffffff ++#define SRM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8 0x1F040470,0x7FF80000 ++#define SRM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8 0x1F040470,0x00070000 ++#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8 0x1F040470,0x00007FF8 ++#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8 0x1F040470,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_9__ADDR 0x1F040474 ++#define SRM_DI0_SW_GEN0_9__EMPTY 0x1F040474,0x00000000 ++#define SRM_DI0_SW_GEN0_9__FULL 0x1F040474,0xffffffff ++#define SRM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1F040474,0x7FF80000 ++#define SRM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1F040474,0x00070000 ++#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1F040474,0x00007FF8 ++#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1F040474,0x00000007 ++ ++#define SRM_DI0_SW_GEN1_1__ADDR 0x1F040478 ++#define SRM_DI0_SW_GEN1_1__EMPTY 0x1F040478,0x00000000 ++#define SRM_DI0_SW_GEN1_1__FULL 0x1F040478,0xffffffff ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1 0x1F040478,0x60000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1 0x1F040478,0x10000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1 0x1F040478,0x0E000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1 0x1F040478,0x01FF0000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1 0x1F040478,0x00007000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1 0x1F040478,0x00000E00 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_UP_1 0x1F040478,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_2__ADDR 0x1F04047C ++#define SRM_DI0_SW_GEN1_2__EMPTY 0x1F04047C,0x00000000 ++#define SRM_DI0_SW_GEN1_2__FULL 0x1F04047C,0xffffffff ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2 0x1F04047C,0x60000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2 0x1F04047C,0x10000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2 0x1F04047C,0x0E000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2 0x1F04047C,0x01FF0000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2 0x1F04047C,0x00007000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2 0x1F04047C,0x00000E00 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_UP_2 0x1F04047C,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_3__ADDR 0x1F040480 ++#define SRM_DI0_SW_GEN1_3__EMPTY 0x1F040480,0x00000000 ++#define SRM_DI0_SW_GEN1_3__FULL 0x1F040480,0xffffffff ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3 0x1F040480,0x60000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3 0x1F040480,0x10000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3 0x1F040480,0x0E000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3 0x1F040480,0x01FF0000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3 0x1F040480,0x00007000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3 0x1F040480,0x00000E00 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_UP_3 0x1F040480,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_4__ADDR 0x1F040484 ++#define SRM_DI0_SW_GEN1_4__EMPTY 0x1F040484,0x00000000 ++#define SRM_DI0_SW_GEN1_4__FULL 0x1F040484,0xffffffff ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4 0x1F040484,0x60000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4 0x1F040484,0x10000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4 0x1F040484,0x0E000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4 0x1F040484,0x01FF0000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4 0x1F040484,0x00007000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4 0x1F040484,0x00000E00 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_UP_4 0x1F040484,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_5__ADDR 0x1F040488 ++#define SRM_DI0_SW_GEN1_5__EMPTY 0x1F040488,0x00000000 ++#define SRM_DI0_SW_GEN1_5__FULL 0x1F040488,0xffffffff ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5 0x1F040488,0x60000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5 0x1F040488,0x10000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5 0x1F040488,0x0E000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5 0x1F040488,0x01FF0000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5 0x1F040488,0x00007000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5 0x1F040488,0x00000E00 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_UP_5 0x1F040488,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_6__ADDR 0x1F04048C ++#define SRM_DI0_SW_GEN1_6__EMPTY 0x1F04048C,0x00000000 ++#define SRM_DI0_SW_GEN1_6__FULL 0x1F04048C,0xffffffff ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6 0x1F04048C,0x60000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6 0x1F04048C,0x10000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6 0x1F04048C,0x0E000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6 0x1F04048C,0x01FF0000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6 0x1F04048C,0x00007000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6 0x1F04048C,0x00000E00 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_UP_6 0x1F04048C,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_7__ADDR 0x1F040490 ++#define SRM_DI0_SW_GEN1_7__EMPTY 0x1F040490,0x00000000 ++#define SRM_DI0_SW_GEN1_7__FULL 0x1F040490,0xffffffff ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7 0x1F040490,0x60000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7 0x1F040490,0x10000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7 0x1F040490,0x0E000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7 0x1F040490,0x01FF0000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7 0x1F040490,0x00007000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7 0x1F040490,0x00000E00 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_UP_7 0x1F040490,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_8__ADDR 0x1F040494 ++#define SRM_DI0_SW_GEN1_8__EMPTY 0x1F040494,0x00000000 ++#define SRM_DI0_SW_GEN1_8__FULL 0x1F040494,0xffffffff ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8 0x1F040494,0x60000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8 0x1F040494,0x10000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8 0x1F040494,0x0E000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8 0x1F040494,0x01FF0000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8 0x1F040494,0x00007000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8 0x1F040494,0x00000E00 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_UP_8 0x1F040494,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_9__ADDR 0x1F040498 ++#define SRM_DI0_SW_GEN1_9__EMPTY 0x1F040498,0x00000000 ++#define SRM_DI0_SW_GEN1_9__FULL 0x1F040498,0xffffffff ++#define SRM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1F040498,0xE0000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1F040498,0x10000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1F040498,0x0E000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1F040498,0x01FF0000 ++#define SRM_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1F040498,0x00008000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1F040498,0x000001FF ++ ++#define SRM_DI0_SYNC_AS_GEN__ADDR 0x1F04049C ++#define SRM_DI0_SYNC_AS_GEN__EMPTY 0x1F04049C,0x00000000 ++#define SRM_DI0_SYNC_AS_GEN__FULL 0x1F04049C,0xffffffff ++#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1F04049C,0x10000000 ++#define SRM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1F04049C,0x0000E000 ++#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1F04049C,0x00000FFF ++ ++#define SRM_DI0_DW_GEN_0__ADDR 0x1F0404A0 ++#define SRM_DI0_DW_GEN_0__EMPTY 0x1F0404A0,0x00000000 ++#define SRM_DI0_DW_GEN_0__FULL 0x1F0404A0,0xffffffff ++#define SRM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1F0404A0,0xFF000000 ++#define SRM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F0404A0,0x00FF0000 ++#define SRM_DI0_DW_GEN_0__DI0_CST_0 0x1F0404A0,0x0000C000 ++#define SRM_DI0_DW_GEN_0__DI0_PT_6_0 0x1F0404A0,0x00003000 ++#define SRM_DI0_DW_GEN_0__DI0_PT_5_0 0x1F0404A0,0x00000C00 ++#define SRM_DI0_DW_GEN_0__DI0_PT_4_0 0x1F0404A0,0x00000300 ++#define SRM_DI0_DW_GEN_0__DI0_PT_3_0 0x1F0404A0,0x000000C0 ++#define SRM_DI0_DW_GEN_0__DI0_PT_2_0 0x1F0404A0,0x00000030 ++#define SRM_DI0_DW_GEN_0__DI0_PT_1_0 0x1F0404A0,0x0000000C ++#define SRM_DI0_DW_GEN_0__DI0_PT_0_0 0x1F0404A0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_0__ADDR 0x1F0404A0 ++#define SRM_DI0_DW_GEN_0__EMPTY 0x1F0404A0,0x00000000 ++#define SRM_DI0_DW_GEN_0__FULL 0x1F0404A0,0xffffffff ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1F0404A0,0xFF000000 ++#define SRM_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1F0404A0,0x00FF0000 ++#define SRM_DI0_DW_GEN_0__DI0_CST_0 0x1F0404A0,0x0000C000 ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F0404A0,0x000001F0 ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1F0404A0,0x0000000C ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1F0404A0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_1__ADDR 0x1F0404A4 ++#define SRM_DI0_DW_GEN_1__EMPTY 0x1F0404A4,0x00000000 ++#define SRM_DI0_DW_GEN_1__FULL 0x1F0404A4,0xffffffff ++#define SRM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1F0404A4,0xFF000000 ++#define SRM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F0404A4,0x00FF0000 ++#define SRM_DI0_DW_GEN_1__DI0_CST_1 0x1F0404A4,0x0000C000 ++#define SRM_DI0_DW_GEN_1__DI0_PT_6_1 0x1F0404A4,0x00003000 ++#define SRM_DI0_DW_GEN_1__DI0_PT_5_1 0x1F0404A4,0x00000C00 ++#define SRM_DI0_DW_GEN_1__DI0_PT_4_1 0x1F0404A4,0x00000300 ++#define SRM_DI0_DW_GEN_1__DI0_PT_3_1 0x1F0404A4,0x000000C0 ++#define SRM_DI0_DW_GEN_1__DI0_PT_2_1 0x1F0404A4,0x00000030 ++#define SRM_DI0_DW_GEN_1__DI0_PT_1_1 0x1F0404A4,0x0000000C ++#define SRM_DI0_DW_GEN_1__DI0_PT_0_1 0x1F0404A4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_1__ADDR 0x1F0404A4 ++#define SRM_DI0_DW_GEN_1__EMPTY 0x1F0404A4,0x00000000 ++#define SRM_DI0_DW_GEN_1__FULL 0x1F0404A4,0xffffffff ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1F0404A4,0xFF000000 ++#define SRM_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1F0404A4,0x00FF0000 ++#define SRM_DI0_DW_GEN_1__DI0_CST_1 0x1F0404A4,0x0000C000 ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F0404A4,0x000001F0 ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1F0404A4,0x0000000C ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1F0404A4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_2__ADDR 0x1F0404A8 ++#define SRM_DI0_DW_GEN_2__EMPTY 0x1F0404A8,0x00000000 ++#define SRM_DI0_DW_GEN_2__FULL 0x1F0404A8,0xffffffff ++#define SRM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1F0404A8,0xFF000000 ++#define SRM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F0404A8,0x00FF0000 ++#define SRM_DI0_DW_GEN_2__DI0_CST_2 0x1F0404A8,0x0000C000 ++#define SRM_DI0_DW_GEN_2__DI0_PT_6_2 0x1F0404A8,0x00003000 ++#define SRM_DI0_DW_GEN_2__DI0_PT_5_2 0x1F0404A8,0x00000C00 ++#define SRM_DI0_DW_GEN_2__DI0_PT_4_2 0x1F0404A8,0x00000300 ++#define SRM_DI0_DW_GEN_2__DI0_PT_3_2 0x1F0404A8,0x000000C0 ++#define SRM_DI0_DW_GEN_2__DI0_PT_2_2 0x1F0404A8,0x00000030 ++#define SRM_DI0_DW_GEN_2__DI0_PT_1_2 0x1F0404A8,0x0000000C ++#define SRM_DI0_DW_GEN_2__DI0_PT_0_2 0x1F0404A8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_2__ADDR 0x1F0404A8 ++#define SRM_DI0_DW_GEN_2__EMPTY 0x1F0404A8,0x00000000 ++#define SRM_DI0_DW_GEN_2__FULL 0x1F0404A8,0xffffffff ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1F0404A8,0xFF000000 ++#define SRM_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1F0404A8,0x00FF0000 ++#define SRM_DI0_DW_GEN_2__DI0_CST_2 0x1F0404A8,0x0000C000 ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F0404A8,0x000001F0 ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1F0404A8,0x0000000C ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1F0404A8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_3__ADDR 0x1F0404AC ++#define SRM_DI0_DW_GEN_3__EMPTY 0x1F0404AC,0x00000000 ++#define SRM_DI0_DW_GEN_3__FULL 0x1F0404AC,0xffffffff ++#define SRM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1F0404AC,0xFF000000 ++#define SRM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F0404AC,0x00FF0000 ++#define SRM_DI0_DW_GEN_3__DI0_CST_3 0x1F0404AC,0x0000C000 ++#define SRM_DI0_DW_GEN_3__DI0_PT_6_3 0x1F0404AC,0x00003000 ++#define SRM_DI0_DW_GEN_3__DI0_PT_5_3 0x1F0404AC,0x00000C00 ++#define SRM_DI0_DW_GEN_3__DI0_PT_4_3 0x1F0404AC,0x00000300 ++#define SRM_DI0_DW_GEN_3__DI0_PT_3_3 0x1F0404AC,0x000000C0 ++#define SRM_DI0_DW_GEN_3__DI0_PT_2_3 0x1F0404AC,0x00000030 ++#define SRM_DI0_DW_GEN_3__DI0_PT_1_3 0x1F0404AC,0x0000000C ++#define SRM_DI0_DW_GEN_3__DI0_PT_0_3 0x1F0404AC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_3__ADDR 0x1F0404AC ++#define SRM_DI0_DW_GEN_3__EMPTY 0x1F0404AC,0x00000000 ++#define SRM_DI0_DW_GEN_3__FULL 0x1F0404AC,0xffffffff ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1F0404AC,0xFF000000 ++#define SRM_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1F0404AC,0x00FF0000 ++#define SRM_DI0_DW_GEN_3__DI0_CST_3 0x1F0404AC,0x0000C000 ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F0404AC,0x000001F0 ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1F0404AC,0x0000000C ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1F0404AC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_4__ADDR 0x1F0404B0 ++#define SRM_DI0_DW_GEN_4__EMPTY 0x1F0404B0,0x00000000 ++#define SRM_DI0_DW_GEN_4__FULL 0x1F0404B0,0xffffffff ++#define SRM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1F0404B0,0xFF000000 ++#define SRM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F0404B0,0x00FF0000 ++#define SRM_DI0_DW_GEN_4__DI0_CST_4 0x1F0404B0,0x0000C000 ++#define SRM_DI0_DW_GEN_4__DI0_PT_6_4 0x1F0404B0,0x00003000 ++#define SRM_DI0_DW_GEN_4__DI0_PT_5_4 0x1F0404B0,0x00000C00 ++#define SRM_DI0_DW_GEN_4__DI0_PT_4_4 0x1F0404B0,0x00000300 ++#define SRM_DI0_DW_GEN_4__DI0_PT_3_4 0x1F0404B0,0x000000C0 ++#define SRM_DI0_DW_GEN_4__DI0_PT_2_4 0x1F0404B0,0x00000030 ++#define SRM_DI0_DW_GEN_4__DI0_PT_1_4 0x1F0404B0,0x0000000C ++#define SRM_DI0_DW_GEN_4__DI0_PT_0_4 0x1F0404B0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_4__ADDR 0x1F0404B0 ++#define SRM_DI0_DW_GEN_4__EMPTY 0x1F0404B0,0x00000000 ++#define SRM_DI0_DW_GEN_4__FULL 0x1F0404B0,0xffffffff ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1F0404B0,0xFF000000 ++#define SRM_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1F0404B0,0x00FF0000 ++#define SRM_DI0_DW_GEN_4__DI0_CST_4 0x1F0404B0,0x0000C000 ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F0404B0,0x000001F0 ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1F0404B0,0x0000000C ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1F0404B0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_5__ADDR 0x1F0404B4 ++#define SRM_DI0_DW_GEN_5__EMPTY 0x1F0404B4,0x00000000 ++#define SRM_DI0_DW_GEN_5__FULL 0x1F0404B4,0xffffffff ++#define SRM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1F0404B4,0xFF000000 ++#define SRM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F0404B4,0x00FF0000 ++#define SRM_DI0_DW_GEN_5__DI0_CST_5 0x1F0404B4,0x0000C000 ++#define SRM_DI0_DW_GEN_5__DI0_PT_6_5 0x1F0404B4,0x00003000 ++#define SRM_DI0_DW_GEN_5__DI0_PT_5_5 0x1F0404B4,0x00000C00 ++#define SRM_DI0_DW_GEN_5__DI0_PT_4_5 0x1F0404B4,0x00000300 ++#define SRM_DI0_DW_GEN_5__DI0_PT_3_5 0x1F0404B4,0x000000C0 ++#define SRM_DI0_DW_GEN_5__DI0_PT_2_5 0x1F0404B4,0x00000030 ++#define SRM_DI0_DW_GEN_5__DI0_PT_1_5 0x1F0404B4,0x0000000C ++#define SRM_DI0_DW_GEN_5__DI0_PT_0_5 0x1F0404B4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_5__ADDR 0x1F0404B4 ++#define SRM_DI0_DW_GEN_5__EMPTY 0x1F0404B4,0x00000000 ++#define SRM_DI0_DW_GEN_5__FULL 0x1F0404B4,0xffffffff ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1F0404B4,0xFF000000 ++#define SRM_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1F0404B4,0x00FF0000 ++#define SRM_DI0_DW_GEN_5__DI0_CST_5 0x1F0404B4,0x0000C000 ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F0404B4,0x000001F0 ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1F0404B4,0x0000000C ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1F0404B4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_6__ADDR 0x1F0404B8 ++#define SRM_DI0_DW_GEN_6__EMPTY 0x1F0404B8,0x00000000 ++#define SRM_DI0_DW_GEN_6__FULL 0x1F0404B8,0xffffffff ++#define SRM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1F0404B8,0xFF000000 ++#define SRM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F0404B8,0x00FF0000 ++#define SRM_DI0_DW_GEN_6__DI0_CST_6 0x1F0404B8,0x0000C000 ++#define SRM_DI0_DW_GEN_6__DI0_PT_6_6 0x1F0404B8,0x00003000 ++#define SRM_DI0_DW_GEN_6__DI0_PT_5_6 0x1F0404B8,0x00000C00 ++#define SRM_DI0_DW_GEN_6__DI0_PT_4_6 0x1F0404B8,0x00000300 ++#define SRM_DI0_DW_GEN_6__DI0_PT_3_6 0x1F0404B8,0x000000C0 ++#define SRM_DI0_DW_GEN_6__DI0_PT_2_6 0x1F0404B8,0x00000030 ++#define SRM_DI0_DW_GEN_6__DI0_PT_1_6 0x1F0404B8,0x0000000C ++#define SRM_DI0_DW_GEN_6__DI0_PT_0_6 0x1F0404B8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_6__ADDR 0x1F0404B8 ++#define SRM_DI0_DW_GEN_6__EMPTY 0x1F0404B8,0x00000000 ++#define SRM_DI0_DW_GEN_6__FULL 0x1F0404B8,0xffffffff ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1F0404B8,0xFF000000 ++#define SRM_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1F0404B8,0x00FF0000 ++#define SRM_DI0_DW_GEN_6__DI0_CST_6 0x1F0404B8,0x0000C000 ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F0404B8,0x000001F0 ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1F0404B8,0x0000000C ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1F0404B8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_7__ADDR 0x1F0404BC ++#define SRM_DI0_DW_GEN_7__EMPTY 0x1F0404BC,0x00000000 ++#define SRM_DI0_DW_GEN_7__FULL 0x1F0404BC,0xffffffff ++#define SRM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1F0404BC,0xFF000000 ++#define SRM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F0404BC,0x00FF0000 ++#define SRM_DI0_DW_GEN_7__DI0_CST_7 0x1F0404BC,0x0000C000 ++#define SRM_DI0_DW_GEN_7__DI0_PT_6_7 0x1F0404BC,0x00003000 ++#define SRM_DI0_DW_GEN_7__DI0_PT_5_7 0x1F0404BC,0x00000C00 ++#define SRM_DI0_DW_GEN_7__DI0_PT_4_7 0x1F0404BC,0x00000300 ++#define SRM_DI0_DW_GEN_7__DI0_PT_3_7 0x1F0404BC,0x000000C0 ++#define SRM_DI0_DW_GEN_7__DI0_PT_2_7 0x1F0404BC,0x00000030 ++#define SRM_DI0_DW_GEN_7__DI0_PT_1_7 0x1F0404BC,0x0000000C ++#define SRM_DI0_DW_GEN_7__DI0_PT_0_7 0x1F0404BC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_7__ADDR 0x1F0404BC ++#define SRM_DI0_DW_GEN_7__EMPTY 0x1F0404BC,0x00000000 ++#define SRM_DI0_DW_GEN_7__FULL 0x1F0404BC,0xffffffff ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1F0404BC,0xFF000000 ++#define SRM_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1F0404BC,0x00FF0000 ++#define SRM_DI0_DW_GEN_7__DI0_CST_7 0x1F0404BC,0x0000C000 ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F0404BC,0x000001F0 ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1F0404BC,0x0000000C ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1F0404BC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_8__ADDR 0x1F0404C0 ++#define SRM_DI0_DW_GEN_8__EMPTY 0x1F0404C0,0x00000000 ++#define SRM_DI0_DW_GEN_8__FULL 0x1F0404C0,0xffffffff ++#define SRM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1F0404C0,0xFF000000 ++#define SRM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F0404C0,0x00FF0000 ++#define SRM_DI0_DW_GEN_8__DI0_CST_8 0x1F0404C0,0x0000C000 ++#define SRM_DI0_DW_GEN_8__DI0_PT_6_8 0x1F0404C0,0x00003000 ++#define SRM_DI0_DW_GEN_8__DI0_PT_5_8 0x1F0404C0,0x00000C00 ++#define SRM_DI0_DW_GEN_8__DI0_PT_4_8 0x1F0404C0,0x00000300 ++#define SRM_DI0_DW_GEN_8__DI0_PT_3_8 0x1F0404C0,0x000000C0 ++#define SRM_DI0_DW_GEN_8__DI0_PT_2_8 0x1F0404C0,0x00000030 ++#define SRM_DI0_DW_GEN_8__DI0_PT_1_8 0x1F0404C0,0x0000000C ++#define SRM_DI0_DW_GEN_8__DI0_PT_0_8 0x1F0404C0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_8__ADDR 0x1F0404C0 ++#define SRM_DI0_DW_GEN_8__EMPTY 0x1F0404C0,0x00000000 ++#define SRM_DI0_DW_GEN_8__FULL 0x1F0404C0,0xffffffff ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1F0404C0,0xFF000000 ++#define SRM_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1F0404C0,0x00FF0000 ++#define SRM_DI0_DW_GEN_8__DI0_CST_8 0x1F0404C0,0x0000C000 ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F0404C0,0x000001F0 ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1F0404C0,0x0000000C ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1F0404C0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_9__ADDR 0x1F0404C4 ++#define SRM_DI0_DW_GEN_9__EMPTY 0x1F0404C4,0x00000000 ++#define SRM_DI0_DW_GEN_9__FULL 0x1F0404C4,0xffffffff ++#define SRM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1F0404C4,0xFF000000 ++#define SRM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F0404C4,0x00FF0000 ++#define SRM_DI0_DW_GEN_9__DI0_CST_9 0x1F0404C4,0x0000C000 ++#define SRM_DI0_DW_GEN_9__DI0_PT_6_9 0x1F0404C4,0x00003000 ++#define SRM_DI0_DW_GEN_9__DI0_PT_5_9 0x1F0404C4,0x00000C00 ++#define SRM_DI0_DW_GEN_9__DI0_PT_4_9 0x1F0404C4,0x00000300 ++#define SRM_DI0_DW_GEN_9__DI0_PT_3_9 0x1F0404C4,0x000000C0 ++#define SRM_DI0_DW_GEN_9__DI0_PT_2_9 0x1F0404C4,0x00000030 ++#define SRM_DI0_DW_GEN_9__DI0_PT_1_9 0x1F0404C4,0x0000000C ++#define SRM_DI0_DW_GEN_9__DI0_PT_0_9 0x1F0404C4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_9__ADDR 0x1F0404C4 ++#define SRM_DI0_DW_GEN_9__EMPTY 0x1F0404C4,0x00000000 ++#define SRM_DI0_DW_GEN_9__FULL 0x1F0404C4,0xffffffff ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1F0404C4,0xFF000000 ++#define SRM_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1F0404C4,0x00FF0000 ++#define SRM_DI0_DW_GEN_9__DI0_CST_9 0x1F0404C4,0x0000C000 ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F0404C4,0x000001F0 ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1F0404C4,0x0000000C ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1F0404C4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_10__ADDR 0x1F0404C8 ++#define SRM_DI0_DW_GEN_10__EMPTY 0x1F0404C8,0x00000000 ++#define SRM_DI0_DW_GEN_10__FULL 0x1F0404C8,0xffffffff ++#define SRM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1F0404C8,0xFF000000 ++#define SRM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F0404C8,0x00FF0000 ++#define SRM_DI0_DW_GEN_10__DI0_CST_10 0x1F0404C8,0x0000C000 ++#define SRM_DI0_DW_GEN_10__DI0_PT_6_10 0x1F0404C8,0x00003000 ++#define SRM_DI0_DW_GEN_10__DI0_PT_5_10 0x1F0404C8,0x00000C00 ++#define SRM_DI0_DW_GEN_10__DI0_PT_4_10 0x1F0404C8,0x00000300 ++#define SRM_DI0_DW_GEN_10__DI0_PT_3_10 0x1F0404C8,0x000000C0 ++#define SRM_DI0_DW_GEN_10__DI0_PT_2_10 0x1F0404C8,0x00000030 ++#define SRM_DI0_DW_GEN_10__DI0_PT_1_10 0x1F0404C8,0x0000000C ++#define SRM_DI0_DW_GEN_10__DI0_PT_0_10 0x1F0404C8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_10__ADDR 0x1F0404C8 ++#define SRM_DI0_DW_GEN_10__EMPTY 0x1F0404C8,0x00000000 ++#define SRM_DI0_DW_GEN_10__FULL 0x1F0404C8,0xffffffff ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1F0404C8,0xFF000000 ++#define SRM_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1F0404C8,0x00FF0000 ++#define SRM_DI0_DW_GEN_10__DI0_CST_10 0x1F0404C8,0x0000C000 ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F0404C8,0x000001F0 ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1F0404C8,0x0000000C ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1F0404C8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_11__ADDR 0x1F0404CC ++#define SRM_DI0_DW_GEN_11__EMPTY 0x1F0404CC,0x00000000 ++#define SRM_DI0_DW_GEN_11__FULL 0x1F0404CC,0xffffffff ++#define SRM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1F0404CC,0xFF000000 ++#define SRM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F0404CC,0x00FF0000 ++#define SRM_DI0_DW_GEN_11__DI0_CST_11 0x1F0404CC,0x0000C000 ++#define SRM_DI0_DW_GEN_11__DI0_PT_6_11 0x1F0404CC,0x00003000 ++#define SRM_DI0_DW_GEN_11__DI0_PT_5_11 0x1F0404CC,0x00000C00 ++#define SRM_DI0_DW_GEN_11__DI0_PT_4_11 0x1F0404CC,0x00000300 ++#define SRM_DI0_DW_GEN_11__DI0_PT_3_11 0x1F0404CC,0x000000C0 ++#define SRM_DI0_DW_GEN_11__DI0_PT_2_11 0x1F0404CC,0x00000030 ++#define SRM_DI0_DW_GEN_11__DI0_PT_1_11 0x1F0404CC,0x0000000C ++#define SRM_DI0_DW_GEN_11__DI0_PT_0_11 0x1F0404CC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_11__ADDR 0x1F0404CC ++#define SRM_DI0_DW_GEN_11__EMPTY 0x1F0404CC,0x00000000 ++#define SRM_DI0_DW_GEN_11__FULL 0x1F0404CC,0xffffffff ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1F0404CC,0xFF000000 ++#define SRM_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1F0404CC,0x00FF0000 ++#define SRM_DI0_DW_GEN_11__DI0_CST_11 0x1F0404CC,0x0000C000 ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F0404CC,0x000001F0 ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1F0404CC,0x0000000C ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1F0404CC,0x00000003 ++ ++#define SRM_DI0_DW_SET0_0__ADDR 0x1F0404D0 ++#define SRM_DI0_DW_SET0_0__EMPTY 0x1F0404D0,0x00000000 ++#define SRM_DI0_DW_SET0_0__FULL 0x1F0404D0,0xffffffff ++#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0 0x1F0404D0,0x01FF0000 ++#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0 0x1F0404D0,0x000001FF ++ ++#define SRM_DI0_DW_SET0_1__ADDR 0x1F0404D4 ++#define SRM_DI0_DW_SET0_1__EMPTY 0x1F0404D4,0x00000000 ++#define SRM_DI0_DW_SET0_1__FULL 0x1F0404D4,0xffffffff ++#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1 0x1F0404D4,0x01FF0000 ++#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1 0x1F0404D4,0x000001FF ++ ++#define SRM_DI0_DW_SET0_2__ADDR 0x1F0404D8 ++#define SRM_DI0_DW_SET0_2__EMPTY 0x1F0404D8,0x00000000 ++#define SRM_DI0_DW_SET0_2__FULL 0x1F0404D8,0xffffffff ++#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2 0x1F0404D8,0x01FF0000 ++#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2 0x1F0404D8,0x000001FF ++ ++#define SRM_DI0_DW_SET0_3__ADDR 0x1F0404DC ++#define SRM_DI0_DW_SET0_3__EMPTY 0x1F0404DC,0x00000000 ++#define SRM_DI0_DW_SET0_3__FULL 0x1F0404DC,0xffffffff ++#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3 0x1F0404DC,0x01FF0000 ++#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3 0x1F0404DC,0x000001FF ++ ++#define SRM_DI0_DW_SET0_4__ADDR 0x1F0404E0 ++#define SRM_DI0_DW_SET0_4__EMPTY 0x1F0404E0,0x00000000 ++#define SRM_DI0_DW_SET0_4__FULL 0x1F0404E0,0xffffffff ++#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4 0x1F0404E0,0x01FF0000 ++#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4 0x1F0404E0,0x000001FF ++ ++#define SRM_DI0_DW_SET0_5__ADDR 0x1F0404E4 ++#define SRM_DI0_DW_SET0_5__EMPTY 0x1F0404E4,0x00000000 ++#define SRM_DI0_DW_SET0_5__FULL 0x1F0404E4,0xffffffff ++#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5 0x1F0404E4,0x01FF0000 ++#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5 0x1F0404E4,0x000001FF ++ ++#define SRM_DI0_DW_SET0_6__ADDR 0x1F0404E8 ++#define SRM_DI0_DW_SET0_6__EMPTY 0x1F0404E8,0x00000000 ++#define SRM_DI0_DW_SET0_6__FULL 0x1F0404E8,0xffffffff ++#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6 0x1F0404E8,0x01FF0000 ++#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6 0x1F0404E8,0x000001FF ++ ++#define SRM_DI0_DW_SET0_7__ADDR 0x1F0404EC ++#define SRM_DI0_DW_SET0_7__EMPTY 0x1F0404EC,0x00000000 ++#define SRM_DI0_DW_SET0_7__FULL 0x1F0404EC,0xffffffff ++#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7 0x1F0404EC,0x01FF0000 ++#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7 0x1F0404EC,0x000001FF ++ ++#define SRM_DI0_DW_SET0_8__ADDR 0x1F0404F0 ++#define SRM_DI0_DW_SET0_8__EMPTY 0x1F0404F0,0x00000000 ++#define SRM_DI0_DW_SET0_8__FULL 0x1F0404F0,0xffffffff ++#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8 0x1F0404F0,0x01FF0000 ++#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8 0x1F0404F0,0x000001FF ++ ++#define SRM_DI0_DW_SET0_9__ADDR 0x1F0404F4 ++#define SRM_DI0_DW_SET0_9__EMPTY 0x1F0404F4,0x00000000 ++#define SRM_DI0_DW_SET0_9__FULL 0x1F0404F4,0xffffffff ++#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9 0x1F0404F4,0x01FF0000 ++#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9 0x1F0404F4,0x000001FF ++ ++#define SRM_DI0_DW_SET0_10__ADDR 0x1F0404F8 ++#define SRM_DI0_DW_SET0_10__EMPTY 0x1F0404F8,0x00000000 ++#define SRM_DI0_DW_SET0_10__FULL 0x1F0404F8,0xffffffff ++#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10 0x1F0404F8,0x01FF0000 ++#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10 0x1F0404F8,0x000001FF ++ ++#define SRM_DI0_DW_SET0_11__ADDR 0x1F0404FC ++#define SRM_DI0_DW_SET0_11__EMPTY 0x1F0404FC,0x00000000 ++#define SRM_DI0_DW_SET0_11__FULL 0x1F0404FC,0xffffffff ++#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11 0x1F0404FC,0x01FF0000 ++#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11 0x1F0404FC,0x000001FF ++ ++#define SRM_DI0_DW_SET1_0__ADDR 0x1F040500 ++#define SRM_DI0_DW_SET1_0__EMPTY 0x1F040500,0x00000000 ++#define SRM_DI0_DW_SET1_0__FULL 0x1F040500,0xffffffff ++#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0 0x1F040500,0x01FF0000 ++#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0 0x1F040500,0x000001FF ++ ++#define SRM_DI0_DW_SET1_1__ADDR 0x1F040504 ++#define SRM_DI0_DW_SET1_1__EMPTY 0x1F040504,0x00000000 ++#define SRM_DI0_DW_SET1_1__FULL 0x1F040504,0xffffffff ++#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1 0x1F040504,0x01FF0000 ++#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1 0x1F040504,0x000001FF ++ ++#define SRM_DI0_DW_SET1_2__ADDR 0x1F040508 ++#define SRM_DI0_DW_SET1_2__EMPTY 0x1F040508,0x00000000 ++#define SRM_DI0_DW_SET1_2__FULL 0x1F040508,0xffffffff ++#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2 0x1F040508,0x01FF0000 ++#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2 0x1F040508,0x000001FF ++ ++#define SRM_DI0_DW_SET1_3__ADDR 0x1F04050C ++#define SRM_DI0_DW_SET1_3__EMPTY 0x1F04050C,0x00000000 ++#define SRM_DI0_DW_SET1_3__FULL 0x1F04050C,0xffffffff ++#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3 0x1F04050C,0x01FF0000 ++#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3 0x1F04050C,0x000001FF ++ ++#define SRM_DI0_DW_SET1_4__ADDR 0x1F040510 ++#define SRM_DI0_DW_SET1_4__EMPTY 0x1F040510,0x00000000 ++#define SRM_DI0_DW_SET1_4__FULL 0x1F040510,0xffffffff ++#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4 0x1F040510,0x01FF0000 ++#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4 0x1F040510,0x000001FF ++ ++#define SRM_DI0_DW_SET1_5__ADDR 0x1F040514 ++#define SRM_DI0_DW_SET1_5__EMPTY 0x1F040514,0x00000000 ++#define SRM_DI0_DW_SET1_5__FULL 0x1F040514,0xffffffff ++#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5 0x1F040514,0x01FF0000 ++#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5 0x1F040514,0x000001FF ++ ++#define SRM_DI0_DW_SET1_6__ADDR 0x1F040518 ++#define SRM_DI0_DW_SET1_6__EMPTY 0x1F040518,0x00000000 ++#define SRM_DI0_DW_SET1_6__FULL 0x1F040518,0xffffffff ++#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6 0x1F040518,0x01FF0000 ++#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6 0x1F040518,0x000001FF ++ ++#define SRM_DI0_DW_SET1_7__ADDR 0x1F04051C ++#define SRM_DI0_DW_SET1_7__EMPTY 0x1F04051C,0x00000000 ++#define SRM_DI0_DW_SET1_7__FULL 0x1F04051C,0xffffffff ++#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7 0x1F04051C,0x01FF0000 ++#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7 0x1F04051C,0x000001FF ++ ++#define SRM_DI0_DW_SET1_8__ADDR 0x1F040520 ++#define SRM_DI0_DW_SET1_8__EMPTY 0x1F040520,0x00000000 ++#define SRM_DI0_DW_SET1_8__FULL 0x1F040520,0xffffffff ++#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8 0x1F040520,0x01FF0000 ++#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8 0x1F040520,0x000001FF ++ ++#define SRM_DI0_DW_SET1_9__ADDR 0x1F040524 ++#define SRM_DI0_DW_SET1_9__EMPTY 0x1F040524,0x00000000 ++#define SRM_DI0_DW_SET1_9__FULL 0x1F040524,0xffffffff ++#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9 0x1F040524,0x01FF0000 ++#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9 0x1F040524,0x000001FF ++ ++#define SRM_DI0_DW_SET1_10__ADDR 0x1F040528 ++#define SRM_DI0_DW_SET1_10__EMPTY 0x1F040528,0x00000000 ++#define SRM_DI0_DW_SET1_10__FULL 0x1F040528,0xffffffff ++#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10 0x1F040528,0x01FF0000 ++#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10 0x1F040528,0x000001FF ++ ++#define SRM_DI0_DW_SET1_11__ADDR 0x1F04052C ++#define SRM_DI0_DW_SET1_11__EMPTY 0x1F04052C,0x00000000 ++#define SRM_DI0_DW_SET1_11__FULL 0x1F04052C,0xffffffff ++#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11 0x1F04052C,0x01FF0000 ++#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11 0x1F04052C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_0__ADDR 0x1F040530 ++#define SRM_DI0_DW_SET2_0__EMPTY 0x1F040530,0x00000000 ++#define SRM_DI0_DW_SET2_0__FULL 0x1F040530,0xffffffff ++#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0 0x1F040530,0x01FF0000 ++#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0 0x1F040530,0x000001FF ++ ++#define SRM_DI0_DW_SET2_1__ADDR 0x1F040534 ++#define SRM_DI0_DW_SET2_1__EMPTY 0x1F040534,0x00000000 ++#define SRM_DI0_DW_SET2_1__FULL 0x1F040534,0xffffffff ++#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1 0x1F040534,0x01FF0000 ++#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1 0x1F040534,0x000001FF ++ ++#define SRM_DI0_DW_SET2_2__ADDR 0x1F040538 ++#define SRM_DI0_DW_SET2_2__EMPTY 0x1F040538,0x00000000 ++#define SRM_DI0_DW_SET2_2__FULL 0x1F040538,0xffffffff ++#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2 0x1F040538,0x01FF0000 ++#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2 0x1F040538,0x000001FF ++ ++#define SRM_DI0_DW_SET2_3__ADDR 0x1F04053C ++#define SRM_DI0_DW_SET2_3__EMPTY 0x1F04053C,0x00000000 ++#define SRM_DI0_DW_SET2_3__FULL 0x1F04053C,0xffffffff ++#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3 0x1F04053C,0x01FF0000 ++#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3 0x1F04053C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_4__ADDR 0x1F040540 ++#define SRM_DI0_DW_SET2_4__EMPTY 0x1F040540,0x00000000 ++#define SRM_DI0_DW_SET2_4__FULL 0x1F040540,0xffffffff ++#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4 0x1F040540,0x01FF0000 ++#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4 0x1F040540,0x000001FF ++ ++#define SRM_DI0_DW_SET2_5__ADDR 0x1F040544 ++#define SRM_DI0_DW_SET2_5__EMPTY 0x1F040544,0x00000000 ++#define SRM_DI0_DW_SET2_5__FULL 0x1F040544,0xffffffff ++#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5 0x1F040544,0x01FF0000 ++#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5 0x1F040544,0x000001FF ++ ++#define SRM_DI0_DW_SET2_6__ADDR 0x1F040548 ++#define SRM_DI0_DW_SET2_6__EMPTY 0x1F040548,0x00000000 ++#define SRM_DI0_DW_SET2_6__FULL 0x1F040548,0xffffffff ++#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6 0x1F040548,0x01FF0000 ++#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6 0x1F040548,0x000001FF ++ ++#define SRM_DI0_DW_SET2_7__ADDR 0x1F04054C ++#define SRM_DI0_DW_SET2_7__EMPTY 0x1F04054C,0x00000000 ++#define SRM_DI0_DW_SET2_7__FULL 0x1F04054C,0xffffffff ++#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7 0x1F04054C,0x01FF0000 ++#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7 0x1F04054C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_8__ADDR 0x1F040550 ++#define SRM_DI0_DW_SET2_8__EMPTY 0x1F040550,0x00000000 ++#define SRM_DI0_DW_SET2_8__FULL 0x1F040550,0xffffffff ++#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8 0x1F040550,0x01FF0000 ++#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8 0x1F040550,0x000001FF ++ ++#define SRM_DI0_DW_SET2_9__ADDR 0x1F040554 ++#define SRM_DI0_DW_SET2_9__EMPTY 0x1F040554,0x00000000 ++#define SRM_DI0_DW_SET2_9__FULL 0x1F040554,0xffffffff ++#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9 0x1F040554,0x01FF0000 ++#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9 0x1F040554,0x000001FF ++ ++#define SRM_DI0_DW_SET2_10__ADDR 0x1F040558 ++#define SRM_DI0_DW_SET2_10__EMPTY 0x1F040558,0x00000000 ++#define SRM_DI0_DW_SET2_10__FULL 0x1F040558,0xffffffff ++#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10 0x1F040558,0x01FF0000 ++#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10 0x1F040558,0x000001FF ++ ++#define SRM_DI0_DW_SET2_11__ADDR 0x1F04055C ++#define SRM_DI0_DW_SET2_11__EMPTY 0x1F04055C,0x00000000 ++#define SRM_DI0_DW_SET2_11__FULL 0x1F04055C,0xffffffff ++#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11 0x1F04055C,0x01FF0000 ++#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11 0x1F04055C,0x000001FF ++ ++#define SRM_DI0_DW_SET3_0__ADDR 0x1F040560 ++#define SRM_DI0_DW_SET3_0__EMPTY 0x1F040560,0x00000000 ++#define SRM_DI0_DW_SET3_0__FULL 0x1F040560,0xffffffff ++#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0 0x1F040560,0x01FF0000 ++#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0 0x1F040560,0x000001FF ++ ++#define SRM_DI0_DW_SET3_1__ADDR 0x1F040564 ++#define SRM_DI0_DW_SET3_1__EMPTY 0x1F040564,0x00000000 ++#define SRM_DI0_DW_SET3_1__FULL 0x1F040564,0xffffffff ++#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1 0x1F040564,0x01FF0000 ++#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1 0x1F040564,0x000001FF ++ ++#define SRM_DI0_DW_SET3_2__ADDR 0x1F040568 ++#define SRM_DI0_DW_SET3_2__EMPTY 0x1F040568,0x00000000 ++#define SRM_DI0_DW_SET3_2__FULL 0x1F040568,0xffffffff ++#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2 0x1F040568,0x01FF0000 ++#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2 0x1F040568,0x000001FF ++ ++#define SRM_DI0_DW_SET3_3__ADDR 0x1F04056C ++#define SRM_DI0_DW_SET3_3__EMPTY 0x1F04056C,0x00000000 ++#define SRM_DI0_DW_SET3_3__FULL 0x1F04056C,0xffffffff ++#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3 0x1F04056C,0x01FF0000 ++#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3 0x1F04056C,0x000001FF ++ ++#define SRM_DI0_DW_SET3_4__ADDR 0x1F040570 ++#define SRM_DI0_DW_SET3_4__EMPTY 0x1F040570,0x00000000 ++#define SRM_DI0_DW_SET3_4__FULL 0x1F040570,0xffffffff ++#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4 0x1F040570,0x01FF0000 ++#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4 0x1F040570,0x000001FF ++ ++#define SRM_DI0_DW_SET3_5__ADDR 0x1F040574 ++#define SRM_DI0_DW_SET3_5__EMPTY 0x1F040574,0x00000000 ++#define SRM_DI0_DW_SET3_5__FULL 0x1F040574,0xffffffff ++#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5 0x1F040574,0x01FF0000 ++#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5 0x1F040574,0x000001FF ++ ++#define SRM_DI0_DW_SET3_6__ADDR 0x1F040578 ++#define SRM_DI0_DW_SET3_6__EMPTY 0x1F040578,0x00000000 ++#define SRM_DI0_DW_SET3_6__FULL 0x1F040578,0xffffffff ++#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6 0x1F040578,0x01FF0000 ++#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6 0x1F040578,0x000001FF ++ ++#define SRM_DI0_DW_SET3_7__ADDR 0x1F04057C ++#define SRM_DI0_DW_SET3_7__EMPTY 0x1F04057C,0x00000000 ++#define SRM_DI0_DW_SET3_7__FULL 0x1F04057C,0xffffffff ++#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7 0x1F04057C,0x01FF0000 ++#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7 0x1F04057C,0x000001FF ++ ++#define SRM_DI0_DW_SET3_8__ADDR 0x1F040580 ++#define SRM_DI0_DW_SET3_8__EMPTY 0x1F040580,0x00000000 ++#define SRM_DI0_DW_SET3_8__FULL 0x1F040580,0xffffffff ++#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8 0x1F040580,0x01FF0000 ++#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8 0x1F040580,0x000001FF ++ ++#define SRM_DI0_DW_SET3_9__ADDR 0x1F040584 ++#define SRM_DI0_DW_SET3_9__EMPTY 0x1F040584,0x00000000 ++#define SRM_DI0_DW_SET3_9__FULL 0x1F040584,0xffffffff ++#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9 0x1F040584,0x01FF0000 ++#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9 0x1F040584,0x000001FF ++ ++#define SRM_DI0_DW_SET3_10__ADDR 0x1F040588 ++#define SRM_DI0_DW_SET3_10__EMPTY 0x1F040588,0x00000000 ++#define SRM_DI0_DW_SET3_10__FULL 0x1F040588,0xffffffff ++#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10 0x1F040588,0x01FF0000 ++#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10 0x1F040588,0x000001FF ++ ++#define SRM_DI0_DW_SET3_11__ADDR 0x1F04058C ++#define SRM_DI0_DW_SET3_11__EMPTY 0x1F04058C,0x00000000 ++#define SRM_DI0_DW_SET3_11__FULL 0x1F04058C,0xffffffff ++#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11 0x1F04058C,0x01FF0000 ++#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11 0x1F04058C,0x000001FF ++ ++#define SRM_DI0_STP_REP_1__ADDR 0x1F040590 ++#define SRM_DI0_STP_REP_1__EMPTY 0x1F040590,0x00000000 ++#define SRM_DI0_STP_REP_1__FULL 0x1F040590,0xffffffff ++#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_2 0x1F040590,0x0FFF0000 ++#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_1 0x1F040590,0x00000FFF ++ ++#define SRM_DI0_STP_REP_2__ADDR 0x1F040594 ++#define SRM_DI0_STP_REP_2__EMPTY 0x1F040594,0x00000000 ++#define SRM_DI0_STP_REP_2__FULL 0x1F040594,0xffffffff ++#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_4 0x1F040594,0x0FFF0000 ++#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_3 0x1F040594,0x00000FFF ++ ++#define SRM_DI0_STP_REP_3__ADDR 0x1F040598 ++#define SRM_DI0_STP_REP_3__EMPTY 0x1F040598,0x00000000 ++#define SRM_DI0_STP_REP_3__FULL 0x1F040598,0xffffffff ++#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_6 0x1F040598,0x0FFF0000 ++#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_5 0x1F040598,0x00000FFF ++ ++#define SRM_DI0_STP_REP_4__ADDR 0x1F04059C ++#define SRM_DI0_STP_REP_4__EMPTY 0x1F04059C,0x00000000 ++#define SRM_DI0_STP_REP_4__FULL 0x1F04059C,0xffffffff ++#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_8 0x1F04059C,0x0FFF0000 ++#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_7 0x1F04059C,0x00000FFF ++ ++#define SRM_DI0_STP_REP_9__ADDR 0x1F0405A0 ++#define SRM_DI0_STP_REP_9__EMPTY 0x1F0405A0,0x00000000 ++#define SRM_DI0_STP_REP_9__FULL 0x1F0405A0,0xffffffff ++#define SRM_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1F0405A0,0x00000FFF ++ ++#define SRM_DI0_SER_CONF__ADDR 0x1F0405A4 ++#define SRM_DI0_SER_CONF__EMPTY 0x1F0405A4,0x00000000 ++#define SRM_DI0_SER_CONF__FULL 0x1F0405A4,0xffffffff ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1F0405A4,0xF0000000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1F0405A4,0x0F000000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1F0405A4,0x00F00000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1F0405A4,0x000F0000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1F0405A4,0x0000FF00 ++#define SRM_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1F0405A4,0x00000020 ++#define SRM_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1F0405A4,0x00000010 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1F0405A4,0x00000008 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1F0405A4,0x00000004 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1F0405A4,0x00000002 ++#define SRM_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1F0405A4,0x00000001 ++ ++#define SRM_DI0_SSC__ADDR 0x1F0405A8 ++#define SRM_DI0_SSC__EMPTY 0x1F0405A8,0x00000000 ++#define SRM_DI0_SSC__FULL 0x1F0405A8,0xffffffff ++#define SRM_DI0_SSC__DI0_PIN17_ERM 0x1F0405A8,0x00800000 ++#define SRM_DI0_SSC__DI0_PIN16_ERM 0x1F0405A8,0x00400000 ++#define SRM_DI0_SSC__DI0_PIN15_ERM 0x1F0405A8,0x00200000 ++#define SRM_DI0_SSC__DI0_PIN14_ERM 0x1F0405A8,0x00100000 ++#define SRM_DI0_SSC__DI0_PIN13_ERM 0x1F0405A8,0x00080000 ++#define SRM_DI0_SSC__DI0_PIN12_ERM 0x1F0405A8,0x00040000 ++#define SRM_DI0_SSC__DI0_PIN11_ERM 0x1F0405A8,0x00020000 ++#define SRM_DI0_SSC__DI0_CS_ERM 0x1F0405A8,0x00010000 ++#define SRM_DI0_SSC__DI0_WAIT_ON 0x1F0405A8,0x00000020 ++#define SRM_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1F0405A8,0x00000008 ++#define SRM_DI0_SSC__DI0_BYTE_EN_PNTR 0x1F0405A8,0x00000007 ++ ++#define SRM_DI0_POL__ADDR 0x1F0405AC ++#define SRM_DI0_POL__EMPTY 0x1F0405AC,0x00000000 ++#define SRM_DI0_POL__FULL 0x1F0405AC,0xffffffff ++#define SRM_DI0_POL__DI0_WAIT_POLARITY 0x1F0405AC,0x04000000 ++#define SRM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1F0405AC,0x02000000 ++#define SRM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1F0405AC,0x01000000 ++#define SRM_DI0_POL__DI0_CS1_DATA_POLARITY 0x1F0405AC,0x00800000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_17 0x1F0405AC,0x00400000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_16 0x1F0405AC,0x00200000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_15 0x1F0405AC,0x00100000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_14 0x1F0405AC,0x00080000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_13 0x1F0405AC,0x00040000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_12 0x1F0405AC,0x00020000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_11 0x1F0405AC,0x00010000 ++#define SRM_DI0_POL__DI0_CS0_DATA_POLARITY 0x1F0405AC,0x00008000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_17 0x1F0405AC,0x00004000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_16 0x1F0405AC,0x00002000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_15 0x1F0405AC,0x00001000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_14 0x1F0405AC,0x00000800 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_13 0x1F0405AC,0x00000400 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_12 0x1F0405AC,0x00000200 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_11 0x1F0405AC,0x00000100 ++#define SRM_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1F0405AC,0x00000080 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_17 0x1F0405AC,0x00000040 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_16 0x1F0405AC,0x00000020 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_15 0x1F0405AC,0x00000010 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_14 0x1F0405AC,0x00000008 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_13 0x1F0405AC,0x00000004 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_12 0x1F0405AC,0x00000002 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_11 0x1F0405AC,0x00000001 ++ ++#define SRM_DI0_AW0__ADDR 0x1F0405B0 ++#define SRM_DI0_AW0__EMPTY 0x1F0405B0,0x00000000 ++#define SRM_DI0_AW0__FULL 0x1F0405B0,0xffffffff ++#define SRM_DI0_AW0__DI0_AW_TRIG_SEL 0x1F0405B0,0xF0000000 ++#define SRM_DI0_AW0__DI0_AW_HEND 0x1F0405B0,0x0FFF0000 ++#define SRM_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1F0405B0,0x0000F000 ++#define SRM_DI0_AW0__DI0_AW_HSTART 0x1F0405B0,0x00000FFF ++ ++#define SRM_DI0_AW1__ADDR 0x1F0405B4 ++#define SRM_DI0_AW1__EMPTY 0x1F0405B4,0x00000000 ++#define SRM_DI0_AW1__FULL 0x1F0405B4,0xffffffff ++#define SRM_DI0_AW1__DI0_AW_VEND 0x1F0405B4,0x0FFF0000 ++#define SRM_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1F0405B4,0x0000F000 ++#define SRM_DI0_AW1__DI0_AW_VSTART 0x1F0405B4,0x00000FFF ++ ++#define SRM_DI0_SCR_CONF__ADDR 0x1F0405B8 ++#define SRM_DI0_SCR_CONF__EMPTY 0x1F0405B8,0x00000000 ++#define SRM_DI0_SCR_CONF__FULL 0x1F0405B8,0xffffffff ++#define SRM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1F0405B8,0x00000FFF ++ ++#define SRM_DI1_GENERAL__ADDR 0x1F0405BC ++#define SRM_DI1_GENERAL__EMPTY 0x1F0405BC,0x00000000 ++#define SRM_DI1_GENERAL__FULL 0x1F0405BC,0xffffffff ++#define SRM_DI1_GENERAL__DI1_DISP_Y_SEL 0x1F0405BC,0x70000000 ++#define SRM_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1F0405BC,0x0F000000 ++#define SRM_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1F0405BC,0x00800000 ++#define SRM_DI1_GENERAL__DI1_MASK_SEL 0x1F0405BC,0x00400000 ++#define SRM_DI1_GENERAL__DI1_VSYNC_EXT 0x1F0405BC,0x00200000 ++#define SRM_DI1_GENERAL__DI1_CLK_EXT 0x1F0405BC,0x00100000 ++#define SRN_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1F0405BC,0x000C0000 ++#define SRM_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1F0405BC,0x00020000 ++#define SRM_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1F0405BC,0x0000F000 ++#define SRM_DI1_GENERAL__DI1_ERR_TREATMENT 0x1F0405BC,0x00000800 ++#define SRM_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1F0405BC,0x00000400 ++#define SRM_DI1_GENERAL__DI1_POLARITY_CS1 0x1F0405BC,0x00000200 ++#define SRM_DI1_GENERAL__DI1_POLARITY_CS0 0x1F0405BC,0x00000100 ++#define SRM_DI1_GENERAL__DI1_POLARITY_8 0x1F0405BC,0x00000080 ++#define SRM_DI1_GENERAL__DI1_POLARITY_7 0x1F0405BC,0x00000040 ++#define SRM_DI1_GENERAL__DI1_POLARITY_6 0x1F0405BC,0x00000020 ++#define SRM_DI1_GENERAL__DI1_POLARITY_5 0x1F0405BC,0x00000010 ++#define SRM_DI1_GENERAL__DI1_POLARITY_4 0x1F0405BC,0x00000008 ++#define SRM_DI1_GENERAL__DI1_POLARITY_3 0x1F0405BC,0x00000004 ++#define SRM_DI1_GENERAL__DI1_POLARITY_2 0x1F0405BC,0x00000002 ++#define SRM_DI1_GENERAL__DI1_POLARITY_1 0x1F0405BC,0x00000001 ++ ++#define SRM_DI1_BS_CLKGEN0__ADDR 0x1F0405C0 ++#define SRM_DI1_BS_CLKGEN0__EMPTY 0x1F0405C0,0x00000000 ++#define SRM_DI1_BS_CLKGEN0__FULL 0x1F0405C0,0xffffffff ++#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1F0405C0,0x01FF0000 ++#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1F0405C0,0x00000FFF ++ ++#define SRM_DI1_BS_CLKGEN1__ADDR 0x1F0405C4 ++#define SRM_DI1_BS_CLKGEN1__EMPTY 0x1F0405C4,0x00000000 ++#define SRM_DI1_BS_CLKGEN1__FULL 0x1F0405C4,0xffffffff ++#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1F0405C4,0x01FF0000 ++#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1F0405C4,0x000001FF ++ ++#define SRM_DI1_SW_GEN0_1__ADDR 0x1F0405C8 ++#define SRM_DI1_SW_GEN0_1__EMPTY 0x1F0405C8,0x00000000 ++#define SRM_DI1_SW_GEN0_1__FULL 0x1F0405C8,0xffffffff ++#define SRM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1 0x1F0405C8,0x7FF80000 ++#define SRM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1 0x1F0405C8,0x00070000 ++#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1 0x1F0405C8,0x00007FF8 ++#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1 0x1F0405C8,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_2__ADDR 0x1F0405CC ++#define SRM_DI1_SW_GEN0_2__EMPTY 0x1F0405CC,0x00000000 ++#define SRM_DI1_SW_GEN0_2__FULL 0x1F0405CC,0xffffffff ++#define SRM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2 0x1F0405CC,0x7FF80000 ++#define SRM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2 0x1F0405CC,0x00070000 ++#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2 0x1F0405CC,0x00007FF8 ++#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2 0x1F0405CC,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_3__ADDR 0x1F0405D0 ++#define SRM_DI1_SW_GEN0_3__EMPTY 0x1F0405D0,0x00000000 ++#define SRM_DI1_SW_GEN0_3__FULL 0x1F0405D0,0xffffffff ++#define SRM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3 0x1F0405D0,0x7FF80000 ++#define SRM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3 0x1F0405D0,0x00070000 ++#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3 0x1F0405D0,0x00007FF8 ++#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3 0x1F0405D0,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_4__ADDR 0x1F0405D4 ++#define SRM_DI1_SW_GEN0_4__EMPTY 0x1F0405D4,0x00000000 ++#define SRM_DI1_SW_GEN0_4__FULL 0x1F0405D4,0xffffffff ++#define SRM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4 0x1F0405D4,0x7FF80000 ++#define SRM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4 0x1F0405D4,0x00070000 ++#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4 0x1F0405D4,0x00007FF8 ++#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4 0x1F0405D4,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_5__ADDR 0x1F0405D8 ++#define SRM_DI1_SW_GEN0_5__EMPTY 0x1F0405D8,0x00000000 ++#define SRM_DI1_SW_GEN0_5__FULL 0x1F0405D8,0xffffffff ++#define SRM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5 0x1F0405D8,0x7FF80000 ++#define SRM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5 0x1F0405D8,0x00070000 ++#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5 0x1F0405D8,0x00007FF8 ++#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5 0x1F0405D8,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_6__ADDR 0x1F0405DC ++#define SRM_DI1_SW_GEN0_6__EMPTY 0x1F0405DC,0x00000000 ++#define SRM_DI1_SW_GEN0_6__FULL 0x1F0405DC,0xffffffff ++#define SRM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6 0x1F0405DC,0x7FF80000 ++#define SRM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6 0x1F0405DC,0x00070000 ++#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6 0x1F0405DC,0x00007FF8 ++#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6 0x1F0405DC,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_7__ADDR 0x1F0405E0 ++#define SRM_DI1_SW_GEN0_7__EMPTY 0x1F0405E0,0x00000000 ++#define SRM_DI1_SW_GEN0_7__FULL 0x1F0405E0,0xffffffff ++#define SRM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7 0x1F0405E0,0x7FF80000 ++#define SRM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7 0x1F0405E0,0x00070000 ++#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7 0x1F0405E0,0x00007FF8 ++#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7 0x1F0405E0,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_8__ADDR 0x1F0405E4 ++#define SRM_DI1_SW_GEN0_8__EMPTY 0x1F0405E4,0x00000000 ++#define SRM_DI1_SW_GEN0_8__FULL 0x1F0405E4,0xffffffff ++#define SRM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8 0x1F0405E4,0x7FF80000 ++#define SRM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8 0x1F0405E4,0x00070000 ++#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8 0x1F0405E4,0x00007FF8 ++#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8 0x1F0405E4,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_9__ADDR 0x1F0405E8 ++#define SRM_DI1_SW_GEN0_9__EMPTY 0x1F0405E8,0x00000000 ++#define SRM_DI1_SW_GEN0_9__FULL 0x1F0405E8,0xffffffff ++#define SRM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1F0405E8,0x7FF80000 ++#define SRM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1F0405E8,0x00070000 ++#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1F0405E8,0x00007FF8 ++#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1F0405E8,0x00000007 ++ ++#define SRM_DI1_SW_GEN1_1__ADDR 0x1F0405EC ++#define SRM_DI1_SW_GEN1_1__EMPTY 0x1F0405EC,0x00000000 ++#define SRM_DI1_SW_GEN1_1__FULL 0x1F0405EC,0xffffffff ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1 0x1F0405EC,0x60000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1 0x1F0405EC,0x10000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1 0x1F0405EC,0x0E000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1 0x1F0405EC,0x01FF0000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1 0x1F0405EC,0x00007000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1 0x1F0405EC,0x00000E00 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_UP_1 0x1F0405EC,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_2__ADDR 0x1F0405F0 ++#define SRM_DI1_SW_GEN1_2__EMPTY 0x1F0405F0,0x00000000 ++#define SRM_DI1_SW_GEN1_2__FULL 0x1F0405F0,0xffffffff ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2 0x1F0405F0,0x60000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2 0x1F0405F0,0x10000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2 0x1F0405F0,0x0E000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2 0x1F0405F0,0x01FF0000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2 0x1F0405F0,0x00007000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2 0x1F0405F0,0x00000E00 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_UP_2 0x1F0405F0,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_3__ADDR 0x1F0405F4 ++#define SRM_DI1_SW_GEN1_3__EMPTY 0x1F0405F4,0x00000000 ++#define SRM_DI1_SW_GEN1_3__FULL 0x1F0405F4,0xffffffff ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3 0x1F0405F4,0x60000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3 0x1F0405F4,0x10000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3 0x1F0405F4,0x0E000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3 0x1F0405F4,0x01FF0000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3 0x1F0405F4,0x00007000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3 0x1F0405F4,0x00000E00 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_UP_3 0x1F0405F4,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_4__ADDR 0x1F0405F8 ++#define SRM_DI1_SW_GEN1_4__EMPTY 0x1F0405F8,0x00000000 ++#define SRM_DI1_SW_GEN1_4__FULL 0x1F0405F8,0xffffffff ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4 0x1F0405F8,0x60000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4 0x1F0405F8,0x10000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4 0x1F0405F8,0x0E000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4 0x1F0405F8,0x01FF0000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4 0x1F0405F8,0x00007000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4 0x1F0405F8,0x00000E00 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_UP_4 0x1F0405F8,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_5__ADDR 0x1F0405FC ++#define SRM_DI1_SW_GEN1_5__EMPTY 0x1F0405FC,0x00000000 ++#define SRM_DI1_SW_GEN1_5__FULL 0x1F0405FC,0xffffffff ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5 0x1F0405FC,0x60000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5 0x1F0405FC,0x10000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5 0x1F0405FC,0x0E000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5 0x1F0405FC,0x01FF0000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5 0x1F0405FC,0x00007000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5 0x1F0405FC,0x00000E00 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_UP_5 0x1F0405FC,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_6__ADDR 0x1F040600 ++#define SRM_DI1_SW_GEN1_6__EMPTY 0x1F040600,0x00000000 ++#define SRM_DI1_SW_GEN1_6__FULL 0x1F040600,0xffffffff ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6 0x1F040600,0x60000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6 0x1F040600,0x10000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6 0x1F040600,0x0E000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6 0x1F040600,0x01FF0000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6 0x1F040600,0x00007000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6 0x1F040600,0x00000E00 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_UP_6 0x1F040600,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_7__ADDR 0x1F040604 ++#define SRM_DI1_SW_GEN1_7__EMPTY 0x1F040604,0x00000000 ++#define SRM_DI1_SW_GEN1_7__FULL 0x1F040604,0xffffffff ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7 0x1F040604,0x60000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7 0x1F040604,0x10000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7 0x1F040604,0x0E000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7 0x1F040604,0x01FF0000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7 0x1F040604,0x00007000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7 0x1F040604,0x00000E00 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_UP_7 0x1F040604,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_8__ADDR 0x1F040608 ++#define SRM_DI1_SW_GEN1_8__EMPTY 0x1F040608,0x00000000 ++#define SRM_DI1_SW_GEN1_8__FULL 0x1F040608,0xffffffff ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8 0x1F040608,0x60000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8 0x1F040608,0x10000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8 0x1F040608,0x0E000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8 0x1F040608,0x01FF0000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8 0x1F040608,0x00007000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8 0x1F040608,0x00000E00 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_UP_8 0x1F040608,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_9__ADDR 0x1F04060C ++#define SRM_DI1_SW_GEN1_9__EMPTY 0x1F04060C,0x00000000 ++#define SRM_DI1_SW_GEN1_9__FULL 0x1F04060C,0xffffffff ++#define SRM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1F04060C,0xE0000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1F04060C,0x10000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1F04060C,0x0E000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1F04060C,0x01FF0000 ++#define SRM_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1F04060C,0x00008000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1F04060C,0x000001FF ++ ++#define SRM_DI1_SYNC_AS_GEN__ADDR 0x1F040610 ++#define SRM_DI1_SYNC_AS_GEN__EMPTY 0x1F040610,0x00000000 ++#define SRM_DI1_SYNC_AS_GEN__FULL 0x1F040610,0xffffffff ++#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1F040610,0x10000000 ++#define SRM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1F040610,0x0000E000 ++#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1F040610,0x00000FFF ++ ++#define SRM_DI1_DW_GEN_0__ADDR 0x1F040614 ++#define SRM_DI1_DW_GEN_0__EMPTY 0x1F040614,0x00000000 ++#define SRM_DI1_DW_GEN_0__FULL 0x1F040614,0xffffffff ++#define SRM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1F040614,0xFF000000 ++#define SRM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040614,0x00FF0000 ++#define SRM_DI1_DW_GEN_0__DI1_CST_0 0x1F040614,0x0000C000 ++#define SRM_DI1_DW_GEN_0__DI1_PT_6_0 0x1F040614,0x00003000 ++#define SRM_DI1_DW_GEN_0__DI1_PT_5_0 0x1F040614,0x00000C00 ++#define SRM_DI1_DW_GEN_0__DI1_PT_4_0 0x1F040614,0x00000300 ++#define SRM_DI1_DW_GEN_0__DI1_PT_3_0 0x1F040614,0x000000C0 ++#define SRM_DI1_DW_GEN_0__DI1_PT_2_0 0x1F040614,0x00000030 ++#define SRM_DI1_DW_GEN_0__DI1_PT_1_0 0x1F040614,0x0000000C ++#define SRM_DI1_DW_GEN_0__DI1_PT_0_0 0x1F040614,0x00000003 ++ ++#define SRM_DI1_DW_GEN_0__ADDR 0x1F040614 ++#define SRM_DI1_DW_GEN_0__EMPTY 0x1F040614,0x00000000 ++#define SRM_DI1_DW_GEN_0__FULL 0x1F040614,0xffffffff ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1F040614,0xFF000000 ++#define SRM_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1F040614,0x00FF0000 ++#define SRM_DI1_DW_GEN_0__DI1_CST_0 0x1F040614,0x0000C000 ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040614,0x000001F0 ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1F040614,0x0000000C ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1F040614,0x00000003 ++ ++#define SRM_DI1_DW_GEN_1__ADDR 0x1F040618 ++#define SRM_DI1_DW_GEN_1__EMPTY 0x1F040618,0x00000000 ++#define SRM_DI1_DW_GEN_1__FULL 0x1F040618,0xffffffff ++#define SRM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1F040618,0xFF000000 ++#define SRM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040618,0x00FF0000 ++#define SRM_DI1_DW_GEN_1__DI1_CST_1 0x1F040618,0x0000C000 ++#define SRM_DI1_DW_GEN_1__DI1_PT_6_1 0x1F040618,0x00003000 ++#define SRM_DI1_DW_GEN_1__DI1_PT_5_1 0x1F040618,0x00000C00 ++#define SRM_DI1_DW_GEN_1__DI1_PT_4_1 0x1F040618,0x00000300 ++#define SRM_DI1_DW_GEN_1__DI1_PT_3_1 0x1F040618,0x000000C0 ++#define SRM_DI1_DW_GEN_1__DI1_PT_2_1 0x1F040618,0x00000030 ++#define SRM_DI1_DW_GEN_1__DI1_PT_1_1 0x1F040618,0x0000000C ++#define SRM_DI1_DW_GEN_1__DI1_PT_0_1 0x1F040618,0x00000003 ++ ++#define SRM_DI1_DW_GEN_1__ADDR 0x1F040618 ++#define SRM_DI1_DW_GEN_1__EMPTY 0x1F040618,0x00000000 ++#define SRM_DI1_DW_GEN_1__FULL 0x1F040618,0xffffffff ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1F040618,0xFF000000 ++#define SRM_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1F040618,0x00FF0000 ++#define SRM_DI1_DW_GEN_1__DI1_CST_1 0x1F040618,0x0000C000 ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040618,0x000001F0 ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1F040618,0x0000000C ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1F040618,0x00000003 ++ ++#define SRM_DI1_DW_GEN_2__ADDR 0x1F04061C ++#define SRM_DI1_DW_GEN_2__EMPTY 0x1F04061C,0x00000000 ++#define SRM_DI1_DW_GEN_2__FULL 0x1F04061C,0xffffffff ++#define SRM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1F04061C,0xFF000000 ++#define SRM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F04061C,0x00FF0000 ++#define SRM_DI1_DW_GEN_2__DI1_CST_2 0x1F04061C,0x0000C000 ++#define SRM_DI1_DW_GEN_2__DI1_PT_6_2 0x1F04061C,0x00003000 ++#define SRM_DI1_DW_GEN_2__DI1_PT_5_2 0x1F04061C,0x00000C00 ++#define SRM_DI1_DW_GEN_2__DI1_PT_4_2 0x1F04061C,0x00000300 ++#define SRM_DI1_DW_GEN_2__DI1_PT_3_2 0x1F04061C,0x000000C0 ++#define SRM_DI1_DW_GEN_2__DI1_PT_2_2 0x1F04061C,0x00000030 ++#define SRM_DI1_DW_GEN_2__DI1_PT_1_2 0x1F04061C,0x0000000C ++#define SRM_DI1_DW_GEN_2__DI1_PT_0_2 0x1F04061C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_2__ADDR 0x1F04061C ++#define SRM_DI1_DW_GEN_2__EMPTY 0x1F04061C,0x00000000 ++#define SRM_DI1_DW_GEN_2__FULL 0x1F04061C,0xffffffff ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1F04061C,0xFF000000 ++#define SRM_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1F04061C,0x00FF0000 ++#define SRM_DI1_DW_GEN_2__DI1_CST_2 0x1F04061C,0x0000C000 ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F04061C,0x000001F0 ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1F04061C,0x0000000C ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1F04061C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_3__ADDR 0x1F040620 ++#define SRM_DI1_DW_GEN_3__EMPTY 0x1F040620,0x00000000 ++#define SRM_DI1_DW_GEN_3__FULL 0x1F040620,0xffffffff ++#define SRM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1F040620,0xFF000000 ++#define SRM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F040620,0x00FF0000 ++#define SRM_DI1_DW_GEN_3__DI1_CST_3 0x1F040620,0x0000C000 ++#define SRM_DI1_DW_GEN_3__DI1_PT_6_3 0x1F040620,0x00003000 ++#define SRM_DI1_DW_GEN_3__DI1_PT_5_3 0x1F040620,0x00000C00 ++#define SRM_DI1_DW_GEN_3__DI1_PT_4_3 0x1F040620,0x00000300 ++#define SRM_DI1_DW_GEN_3__DI1_PT_3_3 0x1F040620,0x000000C0 ++#define SRM_DI1_DW_GEN_3__DI1_PT_2_3 0x1F040620,0x00000030 ++#define SRM_DI1_DW_GEN_3__DI1_PT_1_3 0x1F040620,0x0000000C ++#define SRM_DI1_DW_GEN_3__DI1_PT_0_3 0x1F040620,0x00000003 ++ ++#define SRM_DI1_DW_GEN_3__ADDR 0x1F040620 ++#define SRM_DI1_DW_GEN_3__EMPTY 0x1F040620,0x00000000 ++#define SRM_DI1_DW_GEN_3__FULL 0x1F040620,0xffffffff ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1F040620,0xFF000000 ++#define SRM_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1F040620,0x00FF0000 ++#define SRM_DI1_DW_GEN_3__DI1_CST_3 0x1F040620,0x0000C000 ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F040620,0x000001F0 ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1F040620,0x0000000C ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1F040620,0x00000003 ++ ++#define SRM_DI1_DW_GEN_4__ADDR 0x1F040624 ++#define SRM_DI1_DW_GEN_4__EMPTY 0x1F040624,0x00000000 ++#define SRM_DI1_DW_GEN_4__FULL 0x1F040624,0xffffffff ++#define SRM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1F040624,0xFF000000 ++#define SRM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F040624,0x00FF0000 ++#define SRM_DI1_DW_GEN_4__DI1_CST_4 0x1F040624,0x0000C000 ++#define SRM_DI1_DW_GEN_4__DI1_PT_6_4 0x1F040624,0x00003000 ++#define SRM_DI1_DW_GEN_4__DI1_PT_5_4 0x1F040624,0x00000C00 ++#define SRM_DI1_DW_GEN_4__DI1_PT_4_4 0x1F040624,0x00000300 ++#define SRM_DI1_DW_GEN_4__DI1_PT_3_4 0x1F040624,0x000000C0 ++#define SRM_DI1_DW_GEN_4__DI1_PT_2_4 0x1F040624,0x00000030 ++#define SRM_DI1_DW_GEN_4__DI1_PT_1_4 0x1F040624,0x0000000C ++#define SRM_DI1_DW_GEN_4__DI1_PT_0_4 0x1F040624,0x00000003 ++ ++#define SRM_DI1_DW_GEN_4__ADDR 0x1F040624 ++#define SRM_DI1_DW_GEN_4__EMPTY 0x1F040624,0x00000000 ++#define SRM_DI1_DW_GEN_4__FULL 0x1F040624,0xffffffff ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1F040624,0xFF000000 ++#define SRM_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1F040624,0x00FF0000 ++#define SRM_DI1_DW_GEN_4__DI1_CST_4 0x1F040624,0x0000C000 ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F040624,0x000001F0 ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1F040624,0x0000000C ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1F040624,0x00000003 ++ ++#define SRM_DI1_DW_GEN_5__ADDR 0x1F040628 ++#define SRM_DI1_DW_GEN_5__EMPTY 0x1F040628,0x00000000 ++#define SRM_DI1_DW_GEN_5__FULL 0x1F040628,0xffffffff ++#define SRM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1F040628,0xFF000000 ++#define SRM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F040628,0x00FF0000 ++#define SRM_DI1_DW_GEN_5__DI1_CST_5 0x1F040628,0x0000C000 ++#define SRM_DI1_DW_GEN_5__DI1_PT_6_5 0x1F040628,0x00003000 ++#define SRM_DI1_DW_GEN_5__DI1_PT_5_5 0x1F040628,0x00000C00 ++#define SRM_DI1_DW_GEN_5__DI1_PT_4_5 0x1F040628,0x00000300 ++#define SRM_DI1_DW_GEN_5__DI1_PT_3_5 0x1F040628,0x000000C0 ++#define SRM_DI1_DW_GEN_5__DI1_PT_2_5 0x1F040628,0x00000030 ++#define SRM_DI1_DW_GEN_5__DI1_PT_1_5 0x1F040628,0x0000000C ++#define SRM_DI1_DW_GEN_5__DI1_PT_0_5 0x1F040628,0x00000003 ++ ++#define SRM_DI1_DW_GEN_5__ADDR 0x1F040628 ++#define SRM_DI1_DW_GEN_5__EMPTY 0x1F040628,0x00000000 ++#define SRM_DI1_DW_GEN_5__FULL 0x1F040628,0xffffffff ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1F040628,0xFF000000 ++#define SRM_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1F040628,0x00FF0000 ++#define SRM_DI1_DW_GEN_5__DI1_CST_5 0x1F040628,0x0000C000 ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F040628,0x000001F0 ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1F040628,0x0000000C ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1F040628,0x00000003 ++ ++#define SRM_DI1_DW_GEN_6__ADDR 0x1F04062C ++#define SRM_DI1_DW_GEN_6__EMPTY 0x1F04062C,0x00000000 ++#define SRM_DI1_DW_GEN_6__FULL 0x1F04062C,0xffffffff ++#define SRM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1F04062C,0xFF000000 ++#define SRM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F04062C,0x00FF0000 ++#define SRM_DI1_DW_GEN_6__DI1_CST_6 0x1F04062C,0x0000C000 ++#define SRM_DI1_DW_GEN_6__DI1_PT_6_6 0x1F04062C,0x00003000 ++#define SRM_DI1_DW_GEN_6__DI1_PT_5_6 0x1F04062C,0x00000C00 ++#define SRM_DI1_DW_GEN_6__DI1_PT_4_6 0x1F04062C,0x00000300 ++#define SRM_DI1_DW_GEN_6__DI1_PT_3_6 0x1F04062C,0x000000C0 ++#define SRM_DI1_DW_GEN_6__DI1_PT_2_6 0x1F04062C,0x00000030 ++#define SRM_DI1_DW_GEN_6__DI1_PT_1_6 0x1F04062C,0x0000000C ++#define SRM_DI1_DW_GEN_6__DI1_PT_0_6 0x1F04062C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_6__ADDR 0x1F04062C ++#define SRM_DI1_DW_GEN_6__EMPTY 0x1F04062C,0x00000000 ++#define SRM_DI1_DW_GEN_6__FULL 0x1F04062C,0xffffffff ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1F04062C,0xFF000000 ++#define SRM_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1F04062C,0x00FF0000 ++#define SRM_DI1_DW_GEN_6__DI1_CST_6 0x1F04062C,0x0000C000 ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F04062C,0x000001F0 ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1F04062C,0x0000000C ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1F04062C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_7__ADDR 0x1F040630 ++#define SRM_DI1_DW_GEN_7__EMPTY 0x1F040630,0x00000000 ++#define SRM_DI1_DW_GEN_7__FULL 0x1F040630,0xffffffff ++#define SRM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1F040630,0xFF000000 ++#define SRM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F040630,0x00FF0000 ++#define SRM_DI1_DW_GEN_7__DI1_CST_7 0x1F040630,0x0000C000 ++#define SRM_DI1_DW_GEN_7__DI1_PT_6_7 0x1F040630,0x00003000 ++#define SRM_DI1_DW_GEN_7__DI1_PT_5_7 0x1F040630,0x00000C00 ++#define SRM_DI1_DW_GEN_7__DI1_PT_4_7 0x1F040630,0x00000300 ++#define SRM_DI1_DW_GEN_7__DI1_PT_3_7 0x1F040630,0x000000C0 ++#define SRM_DI1_DW_GEN_7__DI1_PT_2_7 0x1F040630,0x00000030 ++#define SRM_DI1_DW_GEN_7__DI1_PT_1_7 0x1F040630,0x0000000C ++#define SRM_DI1_DW_GEN_7__DI1_PT_0_7 0x1F040630,0x00000003 ++ ++#define SRM_DI1_DW_GEN_7__ADDR 0x1F040630 ++#define SRM_DI1_DW_GEN_7__EMPTY 0x1F040630,0x00000000 ++#define SRM_DI1_DW_GEN_7__FULL 0x1F040630,0xffffffff ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1F040630,0xFF000000 ++#define SRM_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1F040630,0x00FF0000 ++#define SRM_DI1_DW_GEN_7__DI1_CST_7 0x1F040630,0x0000C000 ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F040630,0x000001F0 ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1F040630,0x0000000C ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1F040630,0x00000003 ++ ++#define SRM_DI1_DW_GEN_8__ADDR 0x1F040634 ++#define SRM_DI1_DW_GEN_8__EMPTY 0x1F040634,0x00000000 ++#define SRM_DI1_DW_GEN_8__FULL 0x1F040634,0xffffffff ++#define SRM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1F040634,0xFF000000 ++#define SRM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040634,0x00FF0000 ++#define SRM_DI1_DW_GEN_8__DI1_CST_8 0x1F040634,0x0000C000 ++#define SRM_DI1_DW_GEN_8__DI1_PT_6_8 0x1F040634,0x00003000 ++#define SRM_DI1_DW_GEN_8__DI1_PT_5_8 0x1F040634,0x00000C00 ++#define SRM_DI1_DW_GEN_8__DI1_PT_4_8 0x1F040634,0x00000300 ++#define SRM_DI1_DW_GEN_8__DI1_PT_3_8 0x1F040634,0x000000C0 ++#define SRM_DI1_DW_GEN_8__DI1_PT_2_8 0x1F040634,0x00000030 ++#define SRM_DI1_DW_GEN_8__DI1_PT_1_8 0x1F040634,0x0000000C ++#define SRM_DI1_DW_GEN_8__DI1_PT_0_8 0x1F040634,0x00000003 ++ ++#define SRM_DI1_DW_GEN_8__ADDR 0x1F040634 ++#define SRM_DI1_DW_GEN_8__EMPTY 0x1F040634,0x00000000 ++#define SRM_DI1_DW_GEN_8__FULL 0x1F040634,0xffffffff ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1F040634,0xFF000000 ++#define SRM_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1F040634,0x00FF0000 ++#define SRM_DI1_DW_GEN_8__DI1_CST_8 0x1F040634,0x0000C000 ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040634,0x000001F0 ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1F040634,0x0000000C ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1F040634,0x00000003 ++ ++#define SRM_DI1_DW_GEN_9__ADDR 0x1F040638 ++#define SRM_DI1_DW_GEN_9__EMPTY 0x1F040638,0x00000000 ++#define SRM_DI1_DW_GEN_9__FULL 0x1F040638,0xffffffff ++#define SRM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1F040638,0xFF000000 ++#define SRM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040638,0x00FF0000 ++#define SRM_DI1_DW_GEN_9__DI1_CST_9 0x1F040638,0x0000C000 ++#define SRM_DI1_DW_GEN_9__DI1_PT_6_9 0x1F040638,0x00003000 ++#define SRM_DI1_DW_GEN_9__DI1_PT_5_9 0x1F040638,0x00000C00 ++#define SRM_DI1_DW_GEN_9__DI1_PT_4_9 0x1F040638,0x00000300 ++#define SRM_DI1_DW_GEN_9__DI1_PT_3_9 0x1F040638,0x000000C0 ++#define SRM_DI1_DW_GEN_9__DI1_PT_2_9 0x1F040638,0x00000030 ++#define SRM_DI1_DW_GEN_9__DI1_PT_1_9 0x1F040638,0x0000000C ++#define SRM_DI1_DW_GEN_9__DI1_PT_0_9 0x1F040638,0x00000003 ++ ++#define SRM_DI1_DW_GEN_9__ADDR 0x1F040638 ++#define SRM_DI1_DW_GEN_9__EMPTY 0x1F040638,0x00000000 ++#define SRM_DI1_DW_GEN_9__FULL 0x1F040638,0xffffffff ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1F040638,0xFF000000 ++#define SRM_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1F040638,0x00FF0000 ++#define SRM_DI1_DW_GEN_9__DI1_CST_9 0x1F040638,0x0000C000 ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040638,0x000001F0 ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1F040638,0x0000000C ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1F040638,0x00000003 ++ ++#define SRM_DI1_DW_GEN_10__ADDR 0x1F04063C ++#define SRM_DI1_DW_GEN_10__EMPTY 0x1F04063C,0x00000000 ++#define SRM_DI1_DW_GEN_10__FULL 0x1F04063C,0xffffffff ++#define SRM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1F04063C,0xFF000000 ++#define SRM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F04063C,0x00FF0000 ++#define SRM_DI1_DW_GEN_10__DI1_CST_10 0x1F04063C,0x0000C000 ++#define SRM_DI1_DW_GEN_10__DI1_PT_6_10 0x1F04063C,0x00003000 ++#define SRM_DI1_DW_GEN_10__DI1_PT_5_10 0x1F04063C,0x00000C00 ++#define SRM_DI1_DW_GEN_10__DI1_PT_4_10 0x1F04063C,0x00000300 ++#define SRM_DI1_DW_GEN_10__DI1_PT_3_10 0x1F04063C,0x000000C0 ++#define SRM_DI1_DW_GEN_10__DI1_PT_2_10 0x1F04063C,0x00000030 ++#define SRM_DI1_DW_GEN_10__DI1_PT_1_10 0x1F04063C,0x0000000C ++#define SRM_DI1_DW_GEN_10__DI1_PT_0_10 0x1F04063C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_10__ADDR 0x1F04063C ++#define SRM_DI1_DW_GEN_10__EMPTY 0x1F04063C,0x00000000 ++#define SRM_DI1_DW_GEN_10__FULL 0x1F04063C,0xffffffff ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1F04063C,0xFF000000 ++#define SRM_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1F04063C,0x00FF0000 ++#define SRM_DI1_DW_GEN_10__DI1_CST_10 0x1F04063C,0x0000C000 ++#define SRM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F04063C,0x000001F0 ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1F04063C,0x0000000C ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1F04063C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_11__ADDR 0x1F040640 ++#define SRM_DI1_DW_GEN_11__EMPTY 0x1F040640,0x00000000 ++#define SRM_DI1_DW_GEN_11__FULL 0x1F040640,0xffffffff ++#define SRM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1F040640,0xFF000000 ++#define SRM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F040640,0x00FF0000 ++#define SRM_DI1_DW_GEN_11__DI1_CST_11 0x1F040640,0x0000C000 ++#define SRM_DI1_DW_GEN_11__DI1_PT_6_11 0x1F040640,0x00003000 ++#define SRM_DI1_DW_GEN_11__DI1_PT_5_11 0x1F040640,0x00000C00 ++#define SRM_DI1_DW_GEN_11__DI1_PT_4_11 0x1F040640,0x00000300 ++#define SRM_DI1_DW_GEN_11__DI1_PT_3_11 0x1F040640,0x000000C0 ++#define SRM_DI1_DW_GEN_11__DI1_PT_2_11 0x1F040640,0x00000030 ++#define SRM_DI1_DW_GEN_11__DI1_PT_1_11 0x1F040640,0x0000000C ++#define SRM_DI1_DW_GEN_11__DI1_PT_0_11 0x1F040640,0x00000003 ++ ++#define SRM_DI1_DW_GEN_11__ADDR 0x1F040640 ++#define SRM_DI1_DW_GEN_11__EMPTY 0x1F040640,0x00000000 ++#define SRM_DI1_DW_GEN_11__FULL 0x1F040640,0xffffffff ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1F040640,0xFF000000 ++#define SRM_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1F040640,0x00FF0000 ++#define SRM_DI1_DW_GEN_11__DI1_CST_11 0x1F040640,0x0000C000 ++#define SRM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040640,0x000001F0 ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1F040640,0x0000000C ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1F040640,0x00000003 ++ ++#define SRM_DI1_DW_SET0_0__ADDR 0x1F040644 ++#define SRM_DI1_DW_SET0_0__EMPTY 0x1F040644,0x00000000 ++#define SRM_DI1_DW_SET0_0__FULL 0x1F040644,0xffffffff ++#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0 0x1F040644,0x01FF0000 ++#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0 0x1F040644,0x000001FF ++ ++#define SRM_DI1_DW_SET0_1__ADDR 0x1F040648 ++#define SRM_DI1_DW_SET0_1__EMPTY 0x1F040648,0x00000000 ++#define SRM_DI1_DW_SET0_1__FULL 0x1F040648,0xffffffff ++#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1 0x1F040648,0x01FF0000 ++#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1 0x1F040648,0x000001FF ++ ++#define SRM_DI1_DW_SET0_2__ADDR 0x1F04064C ++#define SRM_DI1_DW_SET0_2__EMPTY 0x1F04064C,0x00000000 ++#define SRM_DI1_DW_SET0_2__FULL 0x1F04064C,0xffffffff ++#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2 0x1F04064C,0x01FF0000 ++#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2 0x1F04064C,0x000001FF ++ ++#define SRM_DI1_DW_SET0_3__ADDR 0x1F040650 ++#define SRM_DI1_DW_SET0_3__EMPTY 0x1F040650,0x00000000 ++#define SRM_DI1_DW_SET0_3__FULL 0x1F040650,0xffffffff ++#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3 0x1F040650,0x01FF0000 ++#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3 0x1F040650,0x000001FF ++ ++#define SRM_DI1_DW_SET0_4__ADDR 0x1F040654 ++#define SRM_DI1_DW_SET0_4__EMPTY 0x1F040654,0x00000000 ++#define SRM_DI1_DW_SET0_4__FULL 0x1F040654,0xffffffff ++#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4 0x1F040654,0x01FF0000 ++#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4 0x1F040654,0x000001FF ++ ++#define SRM_DI1_DW_SET0_5__ADDR 0x1F040658 ++#define SRM_DI1_DW_SET0_5__EMPTY 0x1F040658,0x00000000 ++#define SRM_DI1_DW_SET0_5__FULL 0x1F040658,0xffffffff ++#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5 0x1F040658,0x01FF0000 ++#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5 0x1F040658,0x000001FF ++ ++#define SRM_DI1_DW_SET0_6__ADDR 0x1F04065C ++#define SRM_DI1_DW_SET0_6__EMPTY 0x1F04065C,0x00000000 ++#define SRM_DI1_DW_SET0_6__FULL 0x1F04065C,0xffffffff ++#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6 0x1F04065C,0x01FF0000 ++#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6 0x1F04065C,0x000001FF ++ ++#define SRM_DI1_DW_SET0_7__ADDR 0x1F040660 ++#define SRM_DI1_DW_SET0_7__EMPTY 0x1F040660,0x00000000 ++#define SRM_DI1_DW_SET0_7__FULL 0x1F040660,0xffffffff ++#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7 0x1F040660,0x01FF0000 ++#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7 0x1F040660,0x000001FF ++ ++#define SRM_DI1_DW_SET0_8__ADDR 0x1F040664 ++#define SRM_DI1_DW_SET0_8__EMPTY 0x1F040664,0x00000000 ++#define SRM_DI1_DW_SET0_8__FULL 0x1F040664,0xffffffff ++#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8 0x1F040664,0x01FF0000 ++#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8 0x1F040664,0x000001FF ++ ++#define SRM_DI1_DW_SET0_9__ADDR 0x1F040668 ++#define SRM_DI1_DW_SET0_9__EMPTY 0x1F040668,0x00000000 ++#define SRM_DI1_DW_SET0_9__FULL 0x1F040668,0xffffffff ++#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9 0x1F040668,0x01FF0000 ++#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9 0x1F040668,0x000001FF ++ ++#define SRM_DI1_DW_SET0_10__ADDR 0x1F04066C ++#define SRM_DI1_DW_SET0_10__EMPTY 0x1F04066C,0x00000000 ++#define SRM_DI1_DW_SET0_10__FULL 0x1F04066C,0xffffffff ++#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10 0x1F04066C,0x01FF0000 ++#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10 0x1F04066C,0x000001FF ++ ++#define SRM_DI1_DW_SET0_11__ADDR 0x1F040670 ++#define SRM_DI1_DW_SET0_11__EMPTY 0x1F040670,0x00000000 ++#define SRM_DI1_DW_SET0_11__FULL 0x1F040670,0xffffffff ++#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11 0x1F040670,0x01FF0000 ++#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11 0x1F040670,0x000001FF ++ ++#define SRM_DI1_DW_SET1_0__ADDR 0x1F040674 ++#define SRM_DI1_DW_SET1_0__EMPTY 0x1F040674,0x00000000 ++#define SRM_DI1_DW_SET1_0__FULL 0x1F040674,0xffffffff ++#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0 0x1F040674,0x01FF0000 ++#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0 0x1F040674,0x000001FF ++ ++#define SRM_DI1_DW_SET1_1__ADDR 0x1F040678 ++#define SRM_DI1_DW_SET1_1__EMPTY 0x1F040678,0x00000000 ++#define SRM_DI1_DW_SET1_1__FULL 0x1F040678,0xffffffff ++#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1 0x1F040678,0x01FF0000 ++#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1 0x1F040678,0x000001FF ++ ++#define SRM_DI1_DW_SET1_2__ADDR 0x1F04067C ++#define SRM_DI1_DW_SET1_2__EMPTY 0x1F04067C,0x00000000 ++#define SRM_DI1_DW_SET1_2__FULL 0x1F04067C,0xffffffff ++#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2 0x1F04067C,0x01FF0000 ++#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2 0x1F04067C,0x000001FF ++ ++#define SRM_DI1_DW_SET1_3__ADDR 0x1F040680 ++#define SRM_DI1_DW_SET1_3__EMPTY 0x1F040680,0x00000000 ++#define SRM_DI1_DW_SET1_3__FULL 0x1F040680,0xffffffff ++#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3 0x1F040680,0x01FF0000 ++#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3 0x1F040680,0x000001FF ++ ++#define SRM_DI1_DW_SET1_4__ADDR 0x1F040684 ++#define SRM_DI1_DW_SET1_4__EMPTY 0x1F040684,0x00000000 ++#define SRM_DI1_DW_SET1_4__FULL 0x1F040684,0xffffffff ++#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4 0x1F040684,0x01FF0000 ++#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4 0x1F040684,0x000001FF ++ ++#define SRM_DI1_DW_SET1_5__ADDR 0x1F040688 ++#define SRM_DI1_DW_SET1_5__EMPTY 0x1F040688,0x00000000 ++#define SRM_DI1_DW_SET1_5__FULL 0x1F040688,0xffffffff ++#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5 0x1F040688,0x01FF0000 ++#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5 0x1F040688,0x000001FF ++ ++#define SRM_DI1_DW_SET1_6__ADDR 0x1F04068C ++#define SRM_DI1_DW_SET1_6__EMPTY 0x1F04068C,0x00000000 ++#define SRM_DI1_DW_SET1_6__FULL 0x1F04068C,0xffffffff ++#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6 0x1F04068C,0x01FF0000 ++#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6 0x1F04068C,0x000001FF ++ ++#define SRM_DI1_DW_SET1_7__ADDR 0x1F040690 ++#define SRM_DI1_DW_SET1_7__EMPTY 0x1F040690,0x00000000 ++#define SRM_DI1_DW_SET1_7__FULL 0x1F040690,0xffffffff ++#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7 0x1F040690,0x01FF0000 ++#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7 0x1F040690,0x000001FF ++ ++#define SRM_DI1_DW_SET1_8__ADDR 0x1F040694 ++#define SRM_DI1_DW_SET1_8__EMPTY 0x1F040694,0x00000000 ++#define SRM_DI1_DW_SET1_8__FULL 0x1F040694,0xffffffff ++#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8 0x1F040694,0x01FF0000 ++#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8 0x1F040694,0x000001FF ++ ++#define SRM_DI1_DW_SET1_9__ADDR 0x1F040698 ++#define SRM_DI1_DW_SET1_9__EMPTY 0x1F040698,0x00000000 ++#define SRM_DI1_DW_SET1_9__FULL 0x1F040698,0xffffffff ++#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9 0x1F040698,0x01FF0000 ++#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9 0x1F040698,0x000001FF ++ ++#define SRM_DI1_DW_SET1_10__ADDR 0x1F04069C ++#define SRM_DI1_DW_SET1_10__EMPTY 0x1F04069C,0x00000000 ++#define SRM_DI1_DW_SET1_10__FULL 0x1F04069C,0xffffffff ++#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10 0x1F04069C,0x01FF0000 ++#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10 0x1F04069C,0x000001FF ++ ++#define SRM_DI1_DW_SET1_11__ADDR 0x1F0406A0 ++#define SRM_DI1_DW_SET1_11__EMPTY 0x1F0406A0,0x00000000 ++#define SRM_DI1_DW_SET1_11__FULL 0x1F0406A0,0xffffffff ++#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11 0x1F0406A0,0x01FF0000 ++#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11 0x1F0406A0,0x000001FF ++ ++#define SRM_DI1_DW_SET2_0__ADDR 0x1F0406A4 ++#define SRM_DI1_DW_SET2_0__EMPTY 0x1F0406A4,0x00000000 ++#define SRM_DI1_DW_SET2_0__FULL 0x1F0406A4,0xffffffff ++#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0 0x1F0406A4,0x01FF0000 ++#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0 0x1F0406A4,0x000001FF ++ ++#define SRM_DI1_DW_SET2_1__ADDR 0x1F0406A8 ++#define SRM_DI1_DW_SET2_1__EMPTY 0x1F0406A8,0x00000000 ++#define SRM_DI1_DW_SET2_1__FULL 0x1F0406A8,0xffffffff ++#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1 0x1F0406A8,0x01FF0000 ++#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1 0x1F0406A8,0x000001FF ++ ++#define SRM_DI1_DW_SET2_2__ADDR 0x1F0406AC ++#define SRM_DI1_DW_SET2_2__EMPTY 0x1F0406AC,0x00000000 ++#define SRM_DI1_DW_SET2_2__FULL 0x1F0406AC,0xffffffff ++#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2 0x1F0406AC,0x01FF0000 ++#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2 0x1F0406AC,0x000001FF ++ ++#define SRM_DI1_DW_SET2_3__ADDR 0x1F0406B0 ++#define SRM_DI1_DW_SET2_3__EMPTY 0x1F0406B0,0x00000000 ++#define SRM_DI1_DW_SET2_3__FULL 0x1F0406B0,0xffffffff ++#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3 0x1F0406B0,0x01FF0000 ++#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3 0x1F0406B0,0x000001FF ++ ++#define SRM_DI1_DW_SET2_4__ADDR 0x1F0406B4 ++#define SRM_DI1_DW_SET2_4__EMPTY 0x1F0406B4,0x00000000 ++#define SRM_DI1_DW_SET2_4__FULL 0x1F0406B4,0xffffffff ++#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4 0x1F0406B4,0x01FF0000 ++#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4 0x1F0406B4,0x000001FF ++ ++#define SRM_DI1_DW_SET2_5__ADDR 0x1F0406B8 ++#define SRM_DI1_DW_SET2_5__EMPTY 0x1F0406B8,0x00000000 ++#define SRM_DI1_DW_SET2_5__FULL 0x1F0406B8,0xffffffff ++#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5 0x1F0406B8,0x01FF0000 ++#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5 0x1F0406B8,0x000001FF ++ ++#define SRM_DI1_DW_SET2_6__ADDR 0x1F0406BC ++#define SRM_DI1_DW_SET2_6__EMPTY 0x1F0406BC,0x00000000 ++#define SRM_DI1_DW_SET2_6__FULL 0x1F0406BC,0xffffffff ++#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6 0x1F0406BC,0x01FF0000 ++#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6 0x1F0406BC,0x000001FF ++ ++#define SRM_DI1_DW_SET2_7__ADDR 0x1F0406C0 ++#define SRM_DI1_DW_SET2_7__EMPTY 0x1F0406C0,0x00000000 ++#define SRM_DI1_DW_SET2_7__FULL 0x1F0406C0,0xffffffff ++#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7 0x1F0406C0,0x01FF0000 ++#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7 0x1F0406C0,0x000001FF ++ ++#define SRM_DI1_DW_SET2_8__ADDR 0x1F0406C4 ++#define SRM_DI1_DW_SET2_8__EMPTY 0x1F0406C4,0x00000000 ++#define SRM_DI1_DW_SET2_8__FULL 0x1F0406C4,0xffffffff ++#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8 0x1F0406C4,0x01FF0000 ++#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8 0x1F0406C4,0x000001FF ++ ++#define SRM_DI1_DW_SET2_9__ADDR 0x1F0406C8 ++#define SRM_DI1_DW_SET2_9__EMPTY 0x1F0406C8,0x00000000 ++#define SRM_DI1_DW_SET2_9__FULL 0x1F0406C8,0xffffffff ++#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9 0x1F0406C8,0x01FF0000 ++#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9 0x1F0406C8,0x000001FF ++ ++#define SRM_DI1_DW_SET2_10__ADDR 0x1F0406CC ++#define SRM_DI1_DW_SET2_10__EMPTY 0x1F0406CC,0x00000000 ++#define SRM_DI1_DW_SET2_10__FULL 0x1F0406CC,0xffffffff ++#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10 0x1F0406CC,0x01FF0000 ++#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10 0x1F0406CC,0x000001FF ++ ++#define SRM_DI1_DW_SET2_11__ADDR 0x1F0406D0 ++#define SRM_DI1_DW_SET2_11__EMPTY 0x1F0406D0,0x00000000 ++#define SRM_DI1_DW_SET2_11__FULL 0x1F0406D0,0xffffffff ++#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11 0x1F0406D0,0x01FF0000 ++#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11 0x1F0406D0,0x000001FF ++ ++#define SRM_DI1_DW_SET3_0__ADDR 0x1F0406D4 ++#define SRM_DI1_DW_SET3_0__EMPTY 0x1F0406D4,0x00000000 ++#define SRM_DI1_DW_SET3_0__FULL 0x1F0406D4,0xffffffff ++#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0 0x1F0406D4,0x01FF0000 ++#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0 0x1F0406D4,0x000001FF ++ ++#define SRM_DI1_DW_SET3_1__ADDR 0x1F0406D8 ++#define SRM_DI1_DW_SET3_1__EMPTY 0x1F0406D8,0x00000000 ++#define SRM_DI1_DW_SET3_1__FULL 0x1F0406D8,0xffffffff ++#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1 0x1F0406D8,0x01FF0000 ++#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1 0x1F0406D8,0x000001FF ++ ++#define SRM_DI1_DW_SET3_2__ADDR 0x1F0406DC ++#define SRM_DI1_DW_SET3_2__EMPTY 0x1F0406DC,0x00000000 ++#define SRM_DI1_DW_SET3_2__FULL 0x1F0406DC,0xffffffff ++#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2 0x1F0406DC,0x01FF0000 ++#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2 0x1F0406DC,0x000001FF ++ ++#define SRM_DI1_DW_SET3_3__ADDR 0x1F0406E0 ++#define SRM_DI1_DW_SET3_3__EMPTY 0x1F0406E0,0x00000000 ++#define SRM_DI1_DW_SET3_3__FULL 0x1F0406E0,0xffffffff ++#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3 0x1F0406E0,0x01FF0000 ++#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3 0x1F0406E0,0x000001FF ++ ++#define SRM_DI1_DW_SET3_4__ADDR 0x1F0406E4 ++#define SRM_DI1_DW_SET3_4__EMPTY 0x1F0406E4,0x00000000 ++#define SRM_DI1_DW_SET3_4__FULL 0x1F0406E4,0xffffffff ++#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4 0x1F0406E4,0x01FF0000 ++#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4 0x1F0406E4,0x000001FF ++ ++#define SRM_DI1_DW_SET3_5__ADDR 0x1F0406E8 ++#define SRM_DI1_DW_SET3_5__EMPTY 0x1F0406E8,0x00000000 ++#define SRM_DI1_DW_SET3_5__FULL 0x1F0406E8,0xffffffff ++#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5 0x1F0406E8,0x01FF0000 ++#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5 0x1F0406E8,0x000001FF ++ ++#define SRM_DI1_DW_SET3_6__ADDR 0x1F0406EC ++#define SRM_DI1_DW_SET3_6__EMPTY 0x1F0406EC,0x00000000 ++#define SRM_DI1_DW_SET3_6__FULL 0x1F0406EC,0xffffffff ++#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6 0x1F0406EC,0x01FF0000 ++#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6 0x1F0406EC,0x000001FF ++ ++#define SRM_DI1_DW_SET3_7__ADDR 0x1F0406F0 ++#define SRM_DI1_DW_SET3_7__EMPTY 0x1F0406F0,0x00000000 ++#define SRM_DI1_DW_SET3_7__FULL 0x1F0406F0,0xffffffff ++#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7 0x1F0406F0,0x01FF0000 ++#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7 0x1F0406F0,0x000001FF ++ ++#define SRM_DI1_DW_SET3_8__ADDR 0x1F0406F4 ++#define SRM_DI1_DW_SET3_8__EMPTY 0x1F0406F4,0x00000000 ++#define SRM_DI1_DW_SET3_8__FULL 0x1F0406F4,0xffffffff ++#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8 0x1F0406F4,0x01FF0000 ++#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8 0x1F0406F4,0x000001FF ++ ++#define SRM_DI1_DW_SET3_9__ADDR 0x1F0406F8 ++#define SRM_DI1_DW_SET3_9__EMPTY 0x1F0406F8,0x00000000 ++#define SRM_DI1_DW_SET3_9__FULL 0x1F0406F8,0xffffffff ++#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9 0x1F0406F8,0x01FF0000 ++#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9 0x1F0406F8,0x000001FF ++ ++#define SRM_DI1_DW_SET3_10__ADDR 0x1F0406FC ++#define SRM_DI1_DW_SET3_10__EMPTY 0x1F0406FC,0x00000000 ++#define SRM_DI1_DW_SET3_10__FULL 0x1F0406FC,0xffffffff ++#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10 0x1F0406FC,0x01FF0000 ++#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10 0x1F0406FC,0x000001FF ++ ++#define SRM_DI1_DW_SET3_11__ADDR 0x1F040700 ++#define SRM_DI1_DW_SET3_11__EMPTY 0x1F040700,0x00000000 ++#define SRM_DI1_DW_SET3_11__FULL 0x1F040700,0xffffffff ++#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11 0x1F040700,0x01FF0000 ++#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11 0x1F040700,0x000001FF ++ ++#define SRM_DI1_STP_REP_1__ADDR 0x1F040704 ++#define SRM_DI1_STP_REP_1__EMPTY 0x1F040704,0x00000000 ++#define SRM_DI1_STP_REP_1__FULL 0x1F040704,0xffffffff ++#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_2 0x1F040704,0x0FFF0000 ++#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_1 0x1F040704,0x00000FFF ++ ++#define SRM_DI1_STP_REP_2__ADDR 0x1F040708 ++#define SRM_DI1_STP_REP_2__EMPTY 0x1F040708,0x00000000 ++#define SRM_DI1_STP_REP_2__FULL 0x1F040708,0xffffffff ++#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_4 0x1F040708,0x0FFF0000 ++#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_3 0x1F040708,0x00000FFF ++ ++#define SRM_DI1_STP_REP_3__ADDR 0x1F04070C ++#define SRM_DI1_STP_REP_3__EMPTY 0x1F04070C,0x00000000 ++#define SRM_DI1_STP_REP_3__FULL 0x1F04070C,0xffffffff ++#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_6 0x1F04070C,0x0FFF0000 ++#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_5 0x1F04070C,0x00000FFF ++ ++#define SRM_DI1_STP_REP_4__ADDR 0x1F040710 ++#define SRM_DI1_STP_REP_4__EMPTY 0x1F040710,0x00000000 ++#define SRM_DI1_STP_REP_4__FULL 0x1F040710,0xffffffff ++#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_8 0x1F040710,0x0FFF0000 ++#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_7 0x1F040710,0x00000FFF ++ ++#define SRM_DI1_STP_REP_9__ADDR 0x1F040714 ++#define SRM_DI1_STP_REP_9__EMPTY 0x1F040714,0x00000000 ++#define SRM_DI1_STP_REP_9__FULL 0x1F040714,0xffffffff ++#define SRM_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1F040714,0x00000FFF ++ ++#define SRM_DI1_SER_CONF__ADDR 0x1F040718 ++#define SRM_DI1_SER_CONF__EMPTY 0x1F040718,0x00000000 ++#define SRM_DI1_SER_CONF__FULL 0x1F040718,0xffffffff ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1F040718,0xF0000000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1F040718,0x0F000000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1F040718,0x00F00000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1F040718,0x000F0000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1F040718,0x0000FF00 ++#define SRM_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1F040718,0x00000020 ++#define SRM_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1F040718,0x00000010 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1F040718,0x00000008 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1F040718,0x00000004 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1F040718,0x00000002 ++#define SRM_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1F040718,0x00000001 ++ ++#define SRM_DI1_SSC__ADDR 0x1F04071C ++#define SRM_DI1_SSC__EMPTY 0x1F04071C,0x00000000 ++#define SRM_DI1_SSC__FULL 0x1F04071C,0xffffffff ++#define SRM_DI1_SSC__DI1_PIN17_ERM 0x1F04071C,0x00800000 ++#define SRM_DI1_SSC__DI1_PIN16_ERM 0x1F04071C,0x00400000 ++#define SRM_DI1_SSC__DI1_PIN15_ERM 0x1F04071C,0x00200000 ++#define SRM_DI1_SSC__DI1_PIN14_ERM 0x1F04071C,0x00100000 ++#define SRM_DI1_SSC__DI1_PIN13_ERM 0x1F04071C,0x00080000 ++#define SRM_DI1_SSC__DI1_PIN12_ERM 0x1F04071C,0x00040000 ++#define SRM_DI1_SSC__DI1_PIN11_ERM 0x1F04071C,0x00020000 ++#define SRM_DI1_SSC__DI1_CS_ERM 0x1F04071C,0x00010000 ++#define SRM_DI1_SSC__DI1_WAIT_ON 0x1F04071C,0x00000020 ++#define SRM_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1F04071C,0x00000008 ++#define SRM_DI1_SSC__DI1_BYTE_EN_PNTR 0x1F04071C,0x00000007 ++ ++#define SRM_DI1_POL__ADDR 0x1F040720 ++#define SRM_DI1_POL__EMPTY 0x1F040720,0x00000000 ++#define SRM_DI1_POL__FULL 0x1F040720,0xffffffff ++#define SRM_DI1_POL__DI1_WAIT_POLARITY 0x1F040720,0x04000000 ++#define SRM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1F040720,0x02000000 ++#define SRM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1F040720,0x01000000 ++#define SRM_DI1_POL__DI1_CS1_DATA_POLARITY 0x1F040720,0x00800000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_17 0x1F040720,0x00400000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_16 0x1F040720,0x00200000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_15 0x1F040720,0x00100000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_14 0x1F040720,0x00080000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_13 0x1F040720,0x00040000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_12 0x1F040720,0x00020000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_11 0x1F040720,0x00010000 ++#define SRM_DI1_POL__DI1_CS0_DATA_POLARITY 0x1F040720,0x00008000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_17 0x1F040720,0x00004000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_16 0x1F040720,0x00002000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_15 0x1F040720,0x00001000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_14 0x1F040720,0x00000800 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_13 0x1F040720,0x00000400 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_12 0x1F040720,0x00000200 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_11 0x1F040720,0x00000100 ++#define SRM_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1F040720,0x00000080 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_17 0x1F040720,0x00000040 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_16 0x1F040720,0x00000020 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_15 0x1F040720,0x00000010 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_14 0x1F040720,0x00000008 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_13 0x1F040720,0x00000004 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_12 0x1F040720,0x00000002 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_11 0x1F040720,0x00000001 ++ ++#define SRM_DI1_AW0__ADDR 0x1F040724 ++#define SRM_DI1_AW0__EMPTY 0x1F040724,0x00000000 ++#define SRM_DI1_AW0__FULL 0x1F040724,0xffffffff ++#define SRM_DI1_AW0__DI1_AW_TRIG_SEL 0x1F040724,0xF0000000 ++#define SRM_DI1_AW0__DI1_AW_HEND 0x1F040724,0x0FFF0000 ++#define SRM_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1F040724,0x0000F000 ++#define SRM_DI1_AW0__DI1_AW_HSTART 0x1F040724,0x00000FFF ++ ++#define SRM_DI1_AW1__ADDR 0x1F040728 ++#define SRM_DI1_AW1__EMPTY 0x1F040728,0x00000000 ++#define SRM_DI1_AW1__FULL 0x1F040728,0xffffffff ++#define SRM_DI1_AW1__DI1_AW_VEND 0x1F040728,0x0FFF0000 ++#define SRM_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1F040728,0x0000F000 ++#define SRM_DI1_AW1__DI1_AW_VSTART 0x1F040728,0x00000FFF ++ ++#define SRM_DI1_SCR_CONF__ADDR 0x1F04072C ++#define SRM_DI1_SCR_CONF__EMPTY 0x1F04072C,0x00000000 ++#define SRM_DI1_SCR_CONF__FULL 0x1F04072C,0xffffffff ++#define SRM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1F04072C,0x00000FFF ++ ++#define SRM_DC_WR_CH_CONF_2__ADDR 0x1F040410 ++#define SRM_DC_WR_CH_CONF_2__EMPTY 0x1F040410,0x00000000 ++#define SRM_DC_WR_CH_CONF_2__FULL 0x1F040410,0xffffffff ++#define SRM_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1F040410,0x07FF0000 ++#define SRM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1F040410,0x00000100 ++#define SRM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1F040410,0x000000E0 ++#define SRM_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1F040410,0x00000018 ++#define SRM_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1F040410,0x00000004 ++#define SRM_DC_WR_CH_CONF_2__W_SIZE_2 0x1F040410,0x00000003 ++ ++#define SRM_DC_WR_CH_ADDR_2__ADDR 0x1F040414 ++#define SRM_DC_WR_CH_ADDR_2__EMPTY 0x1F040414,0x00000000 ++#define SRM_DC_WR_CH_ADDR_2__FULL 0x1F040414,0xffffffff ++#define SRM_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1F040414,0x1FFFFFFF ++ ++#define SRM_DC_RL0_CH_2__ADDR 0x1F040418 ++#define SRM_DC_RL0_CH_2__EMPTY 0x1F040418,0x00000000 ++#define SRM_DC_RL0_CH_2__FULL 0x1F040418,0xffffffff ++#define SRM_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1F040418,0xFF000000 ++#define SRM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1F040418,0x000F0000 ++#define SRM_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1F040418,0x0000FF00 ++#define SRM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1F040418,0x0000000F ++ ++#define SRM_DC_RL1_CH_2__ADDR 0x1F04041C ++#define SRM_DC_RL1_CH_2__EMPTY 0x1F04041C,0x00000000 ++#define SRM_DC_RL1_CH_2__FULL 0x1F04041C,0xffffffff ++#define SRM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1F04041C,0xFF000000 ++#define SRM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1F04041C,0x000F0000 ++#define SRM_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1F04041C,0x0000FF00 ++#define SRM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1F04041C,0x0000000F ++ ++#define SRM_DC_RL2_CH_2__ADDR 0x1F040420 ++#define SRM_DC_RL2_CH_2__EMPTY 0x1F040420,0x00000000 ++#define SRM_DC_RL2_CH_2__FULL 0x1F040420,0xffffffff ++#define SRM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1F040420,0xFF000000 ++#define SRM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1F040420,0x000F0000 ++#define SRM_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1F040420,0x0000FF00 ++#define SRM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1F040420,0x0000000F ++ ++#define SRM_DC_RL3_CH_2__ADDR 0x1F040424 ++#define SRM_DC_RL3_CH_2__EMPTY 0x1F040424,0x00000000 ++#define SRM_DC_RL3_CH_2__FULL 0x1F040424,0xffffffff ++#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1F040424,0xFF000000 ++#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1F040424,0x000F0000 ++#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1F040424,0x0000FF00 ++#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1F040424,0x0000000F ++ ++#define SRM_DC_RL4_CH_2__ADDR 0x1F040428 ++#define SRM_DC_RL4_CH_2__EMPTY 0x1F040428,0x00000000 ++#define SRM_DC_RL4_CH_2__FULL 0x1F040428,0xffffffff ++#define SRM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1F040428,0x0000FF00 ++#define SRM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1F040428,0x0000000F ++ ++#define SRM_DC_WR_CH_CONF_6__ADDR 0x1F04042C ++#define SRM_DC_WR_CH_CONF_6__EMPTY 0x1F04042C,0x00000000 ++#define SRM_DC_WR_CH_CONF_6__FULL 0x1F04042C,0xffffffff ++#define SRM_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1F04042C,0x07FF0000 ++#define SRM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1F04042C,0x00000100 ++#define SRM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1F04042C,0x000000E0 ++#define SRM_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1F04042C,0x00000018 ++#define SRM_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1F04042C,0x00000004 ++#define SRM_DC_WR_CH_CONF_6__W_SIZE_6 0x1F04042C,0x00000003 ++ ++#define SRM_DC_WR_CH_ADDR_6__ADDR 0x1F040430 ++#define SRM_DC_WR_CH_ADDR_6__EMPTY 0x1F040430,0x00000000 ++#define SRM_DC_WR_CH_ADDR_6__FULL 0x1F040430,0xffffffff ++#define SRM_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1F040430,0x1FFFFFFF ++ ++#define SRM_DC_RL0_CH_6__ADDR 0x1F040434 ++#define SRM_DC_RL0_CH_6__EMPTY 0x1F040434,0x00000000 ++#define SRM_DC_RL0_CH_6__FULL 0x1F040434,0xffffffff ++#define SRM_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1F040434,0xFF000000 ++#define SRM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1F040434,0x000F0000 ++#define SRM_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1F040434,0x0000FF00 ++#define SRM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1F040434,0x0000000F ++ ++#define SRM_DC_RL1_CH_6__ADDR 0x1F040438 ++#define SRM_DC_RL1_CH_6__EMPTY 0x1F040438,0x00000000 ++#define SRM_DC_RL1_CH_6__FULL 0x1F040438,0xffffffff ++#define SRM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1F040438,0xFF000000 ++#define SRM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1F040438,0x000F0000 ++#define SRM_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1F040438,0x0000FF00 ++#define SRM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1F040438,0x0000000F ++ ++#define SRM_DC_RL2_CH_6__ADDR 0x1F04043C ++#define SRM_DC_RL2_CH_6__EMPTY 0x1F04043C,0x00000000 ++#define SRM_DC_RL2_CH_6__FULL 0x1F04043C,0xffffffff ++#define SRM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1F04043C,0xFF000000 ++#define SRM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1F04043C,0x000F0000 ++#define SRM_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1F04043C,0x0000FF00 ++#define SRM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1F04043C,0x0000000F ++ ++#define SRM_DC_RL3_CH_6__ADDR 0x1F040440 ++#define SRM_DC_RL3_CH_6__EMPTY 0x1F040440,0x00000000 ++#define SRM_DC_RL3_CH_6__FULL 0x1F040440,0xffffffff ++#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1F040440,0xFF000000 ++#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1F040440,0x000F0000 ++#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1F040440,0x0000FF00 ++#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1F040440,0x0000000F ++ ++#define SRM_DC_RL4_CH_6__ADDR 0x1F040444 ++#define SRM_DC_RL4_CH_6__EMPTY 0x1F040444,0x00000000 ++#define SRM_DC_RL4_CH_6__FULL 0x1F040444,0xffffffff ++#define SRM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1F040444,0x0000FF00 ++#define SRM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1F040444,0x0000000F ++ ++#define IPU_MEM_DC_MICROCODE_BASE_ADDR 0x1F080000 ++ ++#define LPM_MEM_DI0_GENERAL__ADDR 0x1F040118 ++#define LPM_MEM_DI0_GENERAL__EMPTY 0x1F040118,0x00000000 ++#define LPM_MEM_DI0_GENERAL__FULL 0x1F040118,0xffffffff ++#define LPM_MEM_DI0_GENERAL__DI0_DISP_Y_SEL 0x1F040118,0x70000000 ++#define LPM_MEM_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1F040118,0x0F000000 ++#define LPM_MEM_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1F040118,0x00800000 ++#define LPM_MEM_DI0_GENERAL__DI0_MASK_SEL 0x1F040118,0x00400000 ++#define LPM_MEM_DI0_GENERAL__DI0_VSYNC_EXT 0x1F040118,0x00200000 ++#define LPM_MEM_DI0_GENERAL__DI0_CLK_EXT 0x1F040118,0x00100000 ++#define LPM_MEM_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1F040118,0x000C0000 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1F040118,0x00020000 ++#define LPM_MEM_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1F040118,0x0000F000 ++#define LPM_MEM_DI0_GENERAL__DI0_ERR_TREATMENT 0x1F040118,0x00000800 ++#define LPM_MEM_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1F040118,0x00000400 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS1 0x1F040118,0x00000200 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS0 0x1F040118,0x00000100 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_8 0x1F040118,0x00000080 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_7 0x1F040118,0x00000040 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_6 0x1F040118,0x00000020 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_5 0x1F040118,0x00000010 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_4 0x1F040118,0x00000008 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_3 0x1F040118,0x00000004 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_2 0x1F040118,0x00000002 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_1 0x1F040118,0x00000001 ++ ++#define LPM_MEM_DI0_BS_CLKGEN0__ADDR 0x1F04011C ++#define LPM_MEM_DI0_BS_CLKGEN0__EMPTY 0x1F04011C,0x00000000 ++#define LPM_MEM_DI0_BS_CLKGEN0__FULL 0x1F04011C,0xffffffff ++#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1F04011C,0x01FF0000 ++#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1F04011C,0x00000FFF ++ ++#define LPM_MEM_DI0_BS_CLKGEN1__ADDR 0x1F040120 ++#define LPM_MEM_DI0_BS_CLKGEN1__EMPTY 0x1F040120,0x00000000 ++#define LPM_MEM_DI0_BS_CLKGEN1__FULL 0x1F040120,0xffffffff ++#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1F040120,0x01FF0000 ++#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1F040120,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN0_1__ADDR 0x1F040124 ++#define LPM_MEM_DI0_SW_GEN0_1__EMPTY 0x1F040124,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_1__FULL 0x1F040124,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1 0x1F040124,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1 0x1F040124,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1 0x1F040124,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1 0x1F040124,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_2__ADDR 0x1F040128 ++#define LPM_MEM_DI0_SW_GEN0_2__EMPTY 0x1F040128,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_2__FULL 0x1F040128,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2 0x1F040128,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2 0x1F040128,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2 0x1F040128,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2 0x1F040128,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_3__ADDR 0x1F04012C ++#define LPM_MEM_DI0_SW_GEN0_3__EMPTY 0x1F04012C,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_3__FULL 0x1F04012C,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3 0x1F04012C,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3 0x1F04012C,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3 0x1F04012C,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3 0x1F04012C,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_4__ADDR 0x1F040130 ++#define LPM_MEM_DI0_SW_GEN0_4__EMPTY 0x1F040130,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_4__FULL 0x1F040130,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4 0x1F040130,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4 0x1F040130,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4 0x1F040130,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4 0x1F040130,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_5__ADDR 0x1F040134 ++#define LPM_MEM_DI0_SW_GEN0_5__EMPTY 0x1F040134,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_5__FULL 0x1F040134,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5 0x1F040134,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5 0x1F040134,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5 0x1F040134,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5 0x1F040134,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_6__ADDR 0x1F040138 ++#define LPM_MEM_DI0_SW_GEN0_6__EMPTY 0x1F040138,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_6__FULL 0x1F040138,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6 0x1F040138,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6 0x1F040138,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6 0x1F040138,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6 0x1F040138,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_7__ADDR 0x1F04013C ++#define LPM_MEM_DI0_SW_GEN0_7__EMPTY 0x1F04013C,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_7__FULL 0x1F04013C,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7 0x1F04013C,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7 0x1F04013C,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7 0x1F04013C,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7 0x1F04013C,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_8__ADDR 0x1F040140 ++#define LPM_MEM_DI0_SW_GEN0_8__EMPTY 0x1F040140,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_8__FULL 0x1F040140,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8 0x1F040140,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8 0x1F040140,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8 0x1F040140,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8 0x1F040140,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_9__ADDR 0x1F040144 ++#define LPM_MEM_DI0_SW_GEN0_9__EMPTY 0x1F040144,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_9__FULL 0x1F040144,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1F040144,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1F040144,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1F040144,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1F040144,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN1_1__ADDR 0x1F040148 ++#define LPM_MEM_DI0_SW_GEN1_1__EMPTY 0x1F040148,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_1__FULL 0x1F040148,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1 0x1F040148,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1 0x1F040148,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1 0x1F040148,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1 0x1F040148,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1 0x1F040148,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1 0x1F040148,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_UP_1 0x1F040148,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_2__ADDR 0x1F04014C ++#define LPM_MEM_DI0_SW_GEN1_2__EMPTY 0x1F04014C,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_2__FULL 0x1F04014C,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2 0x1F04014C,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2 0x1F04014C,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2 0x1F04014C,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2 0x1F04014C,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2 0x1F04014C,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2 0x1F04014C,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_UP_2 0x1F04014C,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_3__ADDR 0x1F040150 ++#define LPM_MEM_DI0_SW_GEN1_3__EMPTY 0x1F040150,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_3__FULL 0x1F040150,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3 0x1F040150,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3 0x1F040150,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3 0x1F040150,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3 0x1F040150,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3 0x1F040150,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3 0x1F040150,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_UP_3 0x1F040150,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_4__ADDR 0x1F040154 ++#define LPM_MEM_DI0_SW_GEN1_4__EMPTY 0x1F040154,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_4__FULL 0x1F040154,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4 0x1F040154,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4 0x1F040154,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4 0x1F040154,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4 0x1F040154,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4 0x1F040154,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4 0x1F040154,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_UP_4 0x1F040154,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_5__ADDR 0x1F040158 ++#define LPM_MEM_DI0_SW_GEN1_5__EMPTY 0x1F040158,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_5__FULL 0x1F040158,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5 0x1F040158,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5 0x1F040158,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5 0x1F040158,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5 0x1F040158,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5 0x1F040158,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5 0x1F040158,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_UP_5 0x1F040158,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_6__ADDR 0x1F04015C ++#define LPM_MEM_DI0_SW_GEN1_6__EMPTY 0x1F04015C,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_6__FULL 0x1F04015C,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6 0x1F04015C,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6 0x1F04015C,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6 0x1F04015C,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6 0x1F04015C,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6 0x1F04015C,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6 0x1F04015C,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_UP_6 0x1F04015C,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_7__ADDR 0x1F040160 ++#define LPM_MEM_DI0_SW_GEN1_7__EMPTY 0x1F040160,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_7__FULL 0x1F040160,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7 0x1F040160,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7 0x1F040160,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7 0x1F040160,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7 0x1F040160,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7 0x1F040160,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7 0x1F040160,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_UP_7 0x1F040160,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_8__ADDR 0x1F040164 ++#define LPM_MEM_DI0_SW_GEN1_8__EMPTY 0x1F040164,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_8__FULL 0x1F040164,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8 0x1F040164,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8 0x1F040164,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8 0x1F040164,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8 0x1F040164,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8 0x1F040164,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8 0x1F040164,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_UP_8 0x1F040164,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_9__ADDR 0x1F040168 ++#define LPM_MEM_DI0_SW_GEN1_9__EMPTY 0x1F040168,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_9__FULL 0x1F040168,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1F040168,0xE0000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1F040168,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1F040168,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1F040168,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1F040168,0x00008000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1F040168,0x000001FF ++ ++#define LPM_MEM_DI0_SYNC_AS_GEN__ADDR 0x1F04016C ++#define LPM_MEM_DI0_SYNC_AS_GEN__EMPTY 0x1F04016C,0x00000000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__FULL 0x1F04016C,0xffffffff ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1F04016C,0x10000000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1F04016C,0x0000E000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1F04016C,0x00000FFF ++ ++#define LPM_MEM_DI0_DW_GEN_0__ADDR 0x1F040170 ++#define LPM_MEM_DI0_DW_GEN_0__EMPTY 0x1F040170,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_0__FULL 0x1F040170,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1F040170,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F040170,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0 0x1F040170,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_6_0 0x1F040170,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_5_0 0x1F040170,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_4_0 0x1F040170,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_3_0 0x1F040170,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_2_0 0x1F040170,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_1_0 0x1F040170,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_0_0 0x1F040170,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_0__ADDR 0x1F040170 ++#define LPM_MEM_DI0_DW_GEN_0__EMPTY 0x1F040170,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_0__FULL 0x1F040170,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1F040170,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1F040170,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0 0x1F040170,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F040170,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1F040170,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1F040170,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_1__ADDR 0x1F040174 ++#define LPM_MEM_DI0_DW_GEN_1__EMPTY 0x1F040174,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_1__FULL 0x1F040174,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1F040174,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F040174,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1 0x1F040174,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_6_1 0x1F040174,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_5_1 0x1F040174,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_4_1 0x1F040174,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_3_1 0x1F040174,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_2_1 0x1F040174,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_1_1 0x1F040174,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_0_1 0x1F040174,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_1__ADDR 0x1F040174 ++#define LPM_MEM_DI0_DW_GEN_1__EMPTY 0x1F040174,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_1__FULL 0x1F040174,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1F040174,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1F040174,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1 0x1F040174,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F040174,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1F040174,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1F040174,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_2__ADDR 0x1F040178 ++#define LPM_MEM_DI0_DW_GEN_2__EMPTY 0x1F040178,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_2__FULL 0x1F040178,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1F040178,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F040178,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2 0x1F040178,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_6_2 0x1F040178,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_5_2 0x1F040178,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_4_2 0x1F040178,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_3_2 0x1F040178,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_2_2 0x1F040178,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_1_2 0x1F040178,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_0_2 0x1F040178,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_2__ADDR 0x1F040178 ++#define LPM_MEM_DI0_DW_GEN_2__EMPTY 0x1F040178,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_2__FULL 0x1F040178,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1F040178,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1F040178,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2 0x1F040178,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F040178,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1F040178,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1F040178,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_3__ADDR 0x1F04017C ++#define LPM_MEM_DI0_DW_GEN_3__EMPTY 0x1F04017C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_3__FULL 0x1F04017C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1F04017C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F04017C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3 0x1F04017C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_6_3 0x1F04017C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_5_3 0x1F04017C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_4_3 0x1F04017C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_3_3 0x1F04017C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_2_3 0x1F04017C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_1_3 0x1F04017C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_0_3 0x1F04017C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_3__ADDR 0x1F04017C ++#define LPM_MEM_DI0_DW_GEN_3__EMPTY 0x1F04017C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_3__FULL 0x1F04017C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1F04017C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1F04017C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3 0x1F04017C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F04017C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1F04017C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1F04017C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_4__ADDR 0x1F040180 ++#define LPM_MEM_DI0_DW_GEN_4__EMPTY 0x1F040180,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_4__FULL 0x1F040180,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1F040180,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F040180,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4 0x1F040180,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_6_4 0x1F040180,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_5_4 0x1F040180,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_4_4 0x1F040180,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_3_4 0x1F040180,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_2_4 0x1F040180,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_1_4 0x1F040180,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_0_4 0x1F040180,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_4__ADDR 0x1F040180 ++#define LPM_MEM_DI0_DW_GEN_4__EMPTY 0x1F040180,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_4__FULL 0x1F040180,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1F040180,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1F040180,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4 0x1F040180,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F040180,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1F040180,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1F040180,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_5__ADDR 0x1F040184 ++#define LPM_MEM_DI0_DW_GEN_5__EMPTY 0x1F040184,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_5__FULL 0x1F040184,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1F040184,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F040184,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5 0x1F040184,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_6_5 0x1F040184,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_5_5 0x1F040184,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_4_5 0x1F040184,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_3_5 0x1F040184,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_2_5 0x1F040184,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_1_5 0x1F040184,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_0_5 0x1F040184,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_5__ADDR 0x1F040184 ++#define LPM_MEM_DI0_DW_GEN_5__EMPTY 0x1F040184,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_5__FULL 0x1F040184,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1F040184,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1F040184,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5 0x1F040184,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F040184,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1F040184,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1F040184,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_6__ADDR 0x1F040188 ++#define LPM_MEM_DI0_DW_GEN_6__EMPTY 0x1F040188,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_6__FULL 0x1F040188,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1F040188,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F040188,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6 0x1F040188,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_6_6 0x1F040188,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_5_6 0x1F040188,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_4_6 0x1F040188,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_3_6 0x1F040188,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_2_6 0x1F040188,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_1_6 0x1F040188,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_0_6 0x1F040188,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_6__ADDR 0x1F040188 ++#define LPM_MEM_DI0_DW_GEN_6__EMPTY 0x1F040188,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_6__FULL 0x1F040188,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1F040188,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1F040188,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6 0x1F040188,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F040188,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1F040188,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1F040188,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_7__ADDR 0x1F04018C ++#define LPM_MEM_DI0_DW_GEN_7__EMPTY 0x1F04018C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_7__FULL 0x1F04018C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1F04018C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F04018C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7 0x1F04018C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_6_7 0x1F04018C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_5_7 0x1F04018C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_4_7 0x1F04018C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_3_7 0x1F04018C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_2_7 0x1F04018C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_1_7 0x1F04018C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_0_7 0x1F04018C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_7__ADDR 0x1F04018C ++#define LPM_MEM_DI0_DW_GEN_7__EMPTY 0x1F04018C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_7__FULL 0x1F04018C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1F04018C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1F04018C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7 0x1F04018C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F04018C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1F04018C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1F04018C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_8__ADDR 0x1F040190 ++#define LPM_MEM_DI0_DW_GEN_8__EMPTY 0x1F040190,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_8__FULL 0x1F040190,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1F040190,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F040190,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8 0x1F040190,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_6_8 0x1F040190,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_5_8 0x1F040190,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_4_8 0x1F040190,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_3_8 0x1F040190,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_2_8 0x1F040190,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_1_8 0x1F040190,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_0_8 0x1F040190,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_8__ADDR 0x1F040190 ++#define LPM_MEM_DI0_DW_GEN_8__EMPTY 0x1F040190,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_8__FULL 0x1F040190,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1F040190,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1F040190,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8 0x1F040190,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F040190,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1F040190,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1F040190,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_9__ADDR 0x1F040194 ++#define LPM_MEM_DI0_DW_GEN_9__EMPTY 0x1F040194,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_9__FULL 0x1F040194,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1F040194,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F040194,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9 0x1F040194,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_6_9 0x1F040194,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_5_9 0x1F040194,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_4_9 0x1F040194,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_3_9 0x1F040194,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_2_9 0x1F040194,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_1_9 0x1F040194,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_0_9 0x1F040194,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_9__ADDR 0x1F040194 ++#define LPM_MEM_DI0_DW_GEN_9__EMPTY 0x1F040194,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_9__FULL 0x1F040194,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1F040194,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1F040194,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9 0x1F040194,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F040194,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1F040194,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1F040194,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_10__ADDR 0x1F040198 ++#define LPM_MEM_DI0_DW_GEN_10__EMPTY 0x1F040198,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_10__FULL 0x1F040198,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1F040198,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F040198,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10 0x1F040198,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_6_10 0x1F040198,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_5_10 0x1F040198,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_4_10 0x1F040198,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_3_10 0x1F040198,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_2_10 0x1F040198,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_1_10 0x1F040198,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_0_10 0x1F040198,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_10__ADDR 0x1F040198 ++#define LPM_MEM_DI0_DW_GEN_10__EMPTY 0x1F040198,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_10__FULL 0x1F040198,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1F040198,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1F040198,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10 0x1F040198,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040198,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1F040198,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1F040198,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_11__ADDR 0x1F04019C ++#define LPM_MEM_DI0_DW_GEN_11__EMPTY 0x1F04019C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_11__FULL 0x1F04019C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1F04019C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F04019C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11 0x1F04019C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_6_11 0x1F04019C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_5_11 0x1F04019C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_4_11 0x1F04019C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_3_11 0x1F04019C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_2_11 0x1F04019C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_1_11 0x1F04019C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_0_11 0x1F04019C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_11__ADDR 0x1F04019C ++#define LPM_MEM_DI0_DW_GEN_11__EMPTY 0x1F04019C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_11__FULL 0x1F04019C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1F04019C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1F04019C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11 0x1F04019C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F04019C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1F04019C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1F04019C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_SET0_0__ADDR 0x1F0401A0 ++#define LPM_MEM_DI0_DW_SET0_0__EMPTY 0x1F0401A0,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_0__FULL 0x1F0401A0,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0 0x1F0401A0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0 0x1F0401A0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_1__ADDR 0x1F0401A4 ++#define LPM_MEM_DI0_DW_SET0_1__EMPTY 0x1F0401A4,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_1__FULL 0x1F0401A4,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1 0x1F0401A4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1 0x1F0401A4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_2__ADDR 0x1F0401A8 ++#define LPM_MEM_DI0_DW_SET0_2__EMPTY 0x1F0401A8,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_2__FULL 0x1F0401A8,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2 0x1F0401A8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2 0x1F0401A8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_3__ADDR 0x1F0401AC ++#define LPM_MEM_DI0_DW_SET0_3__EMPTY 0x1F0401AC,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_3__FULL 0x1F0401AC,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3 0x1F0401AC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3 0x1F0401AC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_4__ADDR 0x1F0401B0 ++#define LPM_MEM_DI0_DW_SET0_4__EMPTY 0x1F0401B0,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_4__FULL 0x1F0401B0,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4 0x1F0401B0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4 0x1F0401B0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_5__ADDR 0x1F0401B4 ++#define LPM_MEM_DI0_DW_SET0_5__EMPTY 0x1F0401B4,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_5__FULL 0x1F0401B4,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5 0x1F0401B4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5 0x1F0401B4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_6__ADDR 0x1F0401B8 ++#define LPM_MEM_DI0_DW_SET0_6__EMPTY 0x1F0401B8,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_6__FULL 0x1F0401B8,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6 0x1F0401B8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6 0x1F0401B8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_7__ADDR 0x1F0401BC ++#define LPM_MEM_DI0_DW_SET0_7__EMPTY 0x1F0401BC,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_7__FULL 0x1F0401BC,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7 0x1F0401BC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7 0x1F0401BC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_8__ADDR 0x1F0401C0 ++#define LPM_MEM_DI0_DW_SET0_8__EMPTY 0x1F0401C0,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_8__FULL 0x1F0401C0,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8 0x1F0401C0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8 0x1F0401C0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_9__ADDR 0x1F0401C4 ++#define LPM_MEM_DI0_DW_SET0_9__EMPTY 0x1F0401C4,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_9__FULL 0x1F0401C4,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9 0x1F0401C4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9 0x1F0401C4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_10__ADDR 0x1F0401C8 ++#define LPM_MEM_DI0_DW_SET0_10__EMPTY 0x1F0401C8,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_10__FULL 0x1F0401C8,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10 0x1F0401C8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10 0x1F0401C8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_11__ADDR 0x1F0401CC ++#define LPM_MEM_DI0_DW_SET0_11__EMPTY 0x1F0401CC,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_11__FULL 0x1F0401CC,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11 0x1F0401CC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11 0x1F0401CC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_0__ADDR 0x1F0401D0 ++#define LPM_MEM_DI0_DW_SET1_0__EMPTY 0x1F0401D0,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_0__FULL 0x1F0401D0,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0 0x1F0401D0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0 0x1F0401D0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_1__ADDR 0x1F0401D4 ++#define LPM_MEM_DI0_DW_SET1_1__EMPTY 0x1F0401D4,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_1__FULL 0x1F0401D4,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1 0x1F0401D4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1 0x1F0401D4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_2__ADDR 0x1F0401D8 ++#define LPM_MEM_DI0_DW_SET1_2__EMPTY 0x1F0401D8,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_2__FULL 0x1F0401D8,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2 0x1F0401D8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2 0x1F0401D8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_3__ADDR 0x1F0401DC ++#define LPM_MEM_DI0_DW_SET1_3__EMPTY 0x1F0401DC,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_3__FULL 0x1F0401DC,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3 0x1F0401DC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3 0x1F0401DC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_4__ADDR 0x1F0401E0 ++#define LPM_MEM_DI0_DW_SET1_4__EMPTY 0x1F0401E0,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_4__FULL 0x1F0401E0,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4 0x1F0401E0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4 0x1F0401E0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_5__ADDR 0x1F0401E4 ++#define LPM_MEM_DI0_DW_SET1_5__EMPTY 0x1F0401E4,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_5__FULL 0x1F0401E4,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5 0x1F0401E4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5 0x1F0401E4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_6__ADDR 0x1F0401E8 ++#define LPM_MEM_DI0_DW_SET1_6__EMPTY 0x1F0401E8,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_6__FULL 0x1F0401E8,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6 0x1F0401E8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6 0x1F0401E8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_7__ADDR 0x1F0401EC ++#define LPM_MEM_DI0_DW_SET1_7__EMPTY 0x1F0401EC,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_7__FULL 0x1F0401EC,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7 0x1F0401EC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7 0x1F0401EC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_8__ADDR 0x1F0401F0 ++#define LPM_MEM_DI0_DW_SET1_8__EMPTY 0x1F0401F0,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_8__FULL 0x1F0401F0,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8 0x1F0401F0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8 0x1F0401F0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_9__ADDR 0x1F0401F4 ++#define LPM_MEM_DI0_DW_SET1_9__EMPTY 0x1F0401F4,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_9__FULL 0x1F0401F4,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9 0x1F0401F4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9 0x1F0401F4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_10__ADDR 0x1F0401F8 ++#define LPM_MEM_DI0_DW_SET1_10__EMPTY 0x1F0401F8,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_10__FULL 0x1F0401F8,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10 0x1F0401F8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10 0x1F0401F8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_11__ADDR 0x1F0401FC ++#define LPM_MEM_DI0_DW_SET1_11__EMPTY 0x1F0401FC,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_11__FULL 0x1F0401FC,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11 0x1F0401FC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11 0x1F0401FC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_0__ADDR 0x1F040200 ++#define LPM_MEM_DI0_DW_SET2_0__EMPTY 0x1F040200,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_0__FULL 0x1F040200,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0 0x1F040200,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0 0x1F040200,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_1__ADDR 0x1F040204 ++#define LPM_MEM_DI0_DW_SET2_1__EMPTY 0x1F040204,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_1__FULL 0x1F040204,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1 0x1F040204,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1 0x1F040204,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_2__ADDR 0x1F040208 ++#define LPM_MEM_DI0_DW_SET2_2__EMPTY 0x1F040208,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_2__FULL 0x1F040208,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2 0x1F040208,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2 0x1F040208,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_3__ADDR 0x1F04020C ++#define LPM_MEM_DI0_DW_SET2_3__EMPTY 0x1F04020C,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_3__FULL 0x1F04020C,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3 0x1F04020C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3 0x1F04020C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_4__ADDR 0x1F040210 ++#define LPM_MEM_DI0_DW_SET2_4__EMPTY 0x1F040210,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_4__FULL 0x1F040210,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4 0x1F040210,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4 0x1F040210,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_5__ADDR 0x1F040214 ++#define LPM_MEM_DI0_DW_SET2_5__EMPTY 0x1F040214,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_5__FULL 0x1F040214,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5 0x1F040214,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5 0x1F040214,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_6__ADDR 0x1F040218 ++#define LPM_MEM_DI0_DW_SET2_6__EMPTY 0x1F040218,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_6__FULL 0x1F040218,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6 0x1F040218,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6 0x1F040218,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_7__ADDR 0x1F04021C ++#define LPM_MEM_DI0_DW_SET2_7__EMPTY 0x1F04021C,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_7__FULL 0x1F04021C,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7 0x1F04021C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7 0x1F04021C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_8__ADDR 0x1F040220 ++#define LPM_MEM_DI0_DW_SET2_8__EMPTY 0x1F040220,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_8__FULL 0x1F040220,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8 0x1F040220,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8 0x1F040220,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_9__ADDR 0x1F040224 ++#define LPM_MEM_DI0_DW_SET2_9__EMPTY 0x1F040224,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_9__FULL 0x1F040224,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9 0x1F040224,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9 0x1F040224,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_10__ADDR 0x1F040228 ++#define LPM_MEM_DI0_DW_SET2_10__EMPTY 0x1F040228,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_10__FULL 0x1F040228,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10 0x1F040228,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10 0x1F040228,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_11__ADDR 0x1F04022C ++#define LPM_MEM_DI0_DW_SET2_11__EMPTY 0x1F04022C,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_11__FULL 0x1F04022C,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11 0x1F04022C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11 0x1F04022C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_0__ADDR 0x1F040230 ++#define LPM_MEM_DI0_DW_SET3_0__EMPTY 0x1F040230,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_0__FULL 0x1F040230,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0 0x1F040230,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0 0x1F040230,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_1__ADDR 0x1F040234 ++#define LPM_MEM_DI0_DW_SET3_1__EMPTY 0x1F040234,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_1__FULL 0x1F040234,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1 0x1F040234,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1 0x1F040234,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_2__ADDR 0x1F040238 ++#define LPM_MEM_DI0_DW_SET3_2__EMPTY 0x1F040238,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_2__FULL 0x1F040238,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2 0x1F040238,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2 0x1F040238,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_3__ADDR 0x1F04023C ++#define LPM_MEM_DI0_DW_SET3_3__EMPTY 0x1F04023C,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_3__FULL 0x1F04023C,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3 0x1F04023C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3 0x1F04023C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_4__ADDR 0x1F040240 ++#define LPM_MEM_DI0_DW_SET3_4__EMPTY 0x1F040240,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_4__FULL 0x1F040240,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4 0x1F040240,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4 0x1F040240,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_5__ADDR 0x1F040244 ++#define LPM_MEM_DI0_DW_SET3_5__EMPTY 0x1F040244,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_5__FULL 0x1F040244,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5 0x1F040244,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5 0x1F040244,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_6__ADDR 0x1F040248 ++#define LPM_MEM_DI0_DW_SET3_6__EMPTY 0x1F040248,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_6__FULL 0x1F040248,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6 0x1F040248,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6 0x1F040248,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_7__ADDR 0x1F04024C ++#define LPM_MEM_DI0_DW_SET3_7__EMPTY 0x1F04024C,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_7__FULL 0x1F04024C,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7 0x1F04024C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7 0x1F04024C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_8__ADDR 0x1F040250 ++#define LPM_MEM_DI0_DW_SET3_8__EMPTY 0x1F040250,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_8__FULL 0x1F040250,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8 0x1F040250,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8 0x1F040250,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_9__ADDR 0x1F040254 ++#define LPM_MEM_DI0_DW_SET3_9__EMPTY 0x1F040254,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_9__FULL 0x1F040254,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9 0x1F040254,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9 0x1F040254,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_10__ADDR 0x1F040258 ++#define LPM_MEM_DI0_DW_SET3_10__EMPTY 0x1F040258,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_10__FULL 0x1F040258,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10 0x1F040258,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10 0x1F040258,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_11__ADDR 0x1F04025C ++#define LPM_MEM_DI0_DW_SET3_11__EMPTY 0x1F04025C,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_11__FULL 0x1F04025C,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11 0x1F04025C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11 0x1F04025C,0x000001FF ++ ++#define LPM_MEM_DI0_STP_REP_1__ADDR 0x1F040260 ++#define LPM_MEM_DI0_STP_REP_1__EMPTY 0x1F040260,0x00000000 ++#define LPM_MEM_DI0_STP_REP_1__FULL 0x1F040260,0xffffffff ++#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_2 0x1F040260,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_1 0x1F040260,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_2__ADDR 0x1F040264 ++#define LPM_MEM_DI0_STP_REP_2__EMPTY 0x1F040264,0x00000000 ++#define LPM_MEM_DI0_STP_REP_2__FULL 0x1F040264,0xffffffff ++#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_4 0x1F040264,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_3 0x1F040264,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_3__ADDR 0x1F040268 ++#define LPM_MEM_DI0_STP_REP_3__EMPTY 0x1F040268,0x00000000 ++#define LPM_MEM_DI0_STP_REP_3__FULL 0x1F040268,0xffffffff ++#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_6 0x1F040268,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_5 0x1F040268,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_4__ADDR 0x1F04026C ++#define LPM_MEM_DI0_STP_REP_4__EMPTY 0x1F04026C,0x00000000 ++#define LPM_MEM_DI0_STP_REP_4__FULL 0x1F04026C,0xffffffff ++#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_8 0x1F04026C,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_7 0x1F04026C,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_9__ADDR 0x1F040270 ++#define LPM_MEM_DI0_STP_REP_9__EMPTY 0x1F040270,0x00000000 ++#define LPM_MEM_DI0_STP_REP_9__FULL 0x1F040270,0xffffffff ++#define LPM_MEM_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1F040270,0x00000FFF ++ ++#define LPM_MEM_DI0_SER_CONF__ADDR 0x1F040274 ++#define LPM_MEM_DI0_SER_CONF__EMPTY 0x1F040274,0x00000000 ++#define LPM_MEM_DI0_SER_CONF__FULL 0x1F040274,0xffffffff ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1F040274,0xF0000000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1F040274,0x0F000000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1F040274,0x00F00000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1F040274,0x000F0000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1F040274,0x0000FF00 ++#define LPM_MEM_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1F040274,0x00000020 ++#define LPM_MEM_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1F040274,0x00000010 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1F040274,0x00000008 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1F040274,0x00000004 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1F040274,0x00000002 ++#define LPM_MEM_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1F040274,0x00000001 ++ ++#define LPM_MEM_DI0_SSC__ADDR 0x1F040278 ++#define LPM_MEM_DI0_SSC__EMPTY 0x1F040278,0x00000000 ++#define LPM_MEM_DI0_SSC__FULL 0x1F040278,0xffffffff ++#define LPM_MEM_DI0_SSC__DI0_PIN17_ERM 0x1F040278,0x00800000 ++#define LPM_MEM_DI0_SSC__DI0_PIN16_ERM 0x1F040278,0x00400000 ++#define LPM_MEM_DI0_SSC__DI0_PIN15_ERM 0x1F040278,0x00200000 ++#define LPM_MEM_DI0_SSC__DI0_PIN14_ERM 0x1F040278,0x00100000 ++#define LPM_MEM_DI0_SSC__DI0_PIN13_ERM 0x1F040278,0x00080000 ++#define LPM_MEM_DI0_SSC__DI0_PIN12_ERM 0x1F040278,0x00040000 ++#define LPM_MEM_DI0_SSC__DI0_PIN11_ERM 0x1F040278,0x00020000 ++#define LPM_MEM_DI0_SSC__DI0_CS_ERM 0x1F040278,0x00010000 ++#define LPM_MEM_DI0_SSC__DI0_WAIT_ON 0x1F040278,0x00000020 ++#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1F040278,0x00000008 ++#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_PNTR 0x1F040278,0x00000007 ++ ++#define LPM_MEM_DI0_POL__ADDR 0x1F04027C ++#define LPM_MEM_DI0_POL__EMPTY 0x1F04027C,0x00000000 ++#define LPM_MEM_DI0_POL__FULL 0x1F04027C,0xffffffff ++#define LPM_MEM_DI0_POL__DI0_WAIT_POLARITY 0x1F04027C,0x04000000 ++#define LPM_MEM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1F04027C,0x02000000 ++#define LPM_MEM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1F04027C,0x01000000 ++#define LPM_MEM_DI0_POL__DI0_CS1_DATA_POLARITY 0x1F04027C,0x00800000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_17 0x1F04027C,0x00400000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_16 0x1F04027C,0x00200000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_15 0x1F04027C,0x00100000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_14 0x1F04027C,0x00080000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_13 0x1F04027C,0x00040000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_12 0x1F04027C,0x00020000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_11 0x1F04027C,0x00010000 ++#define LPM_MEM_DI0_POL__DI0_CS0_DATA_POLARITY 0x1F04027C,0x00008000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_17 0x1F04027C,0x00004000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_16 0x1F04027C,0x00002000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_15 0x1F04027C,0x00001000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_14 0x1F04027C,0x00000800 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_13 0x1F04027C,0x00000400 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_12 0x1F04027C,0x00000200 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_11 0x1F04027C,0x00000100 ++#define LPM_MEM_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1F04027C,0x00000080 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_17 0x1F04027C,0x00000040 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_16 0x1F04027C,0x00000020 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_15 0x1F04027C,0x00000010 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_14 0x1F04027C,0x00000008 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_13 0x1F04027C,0x00000004 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_12 0x1F04027C,0x00000002 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_11 0x1F04027C,0x00000001 ++ ++#define LPM_MEM_DI0_AW0__ADDR 0x1F040280 ++#define LPM_MEM_DI0_AW0__EMPTY 0x1F040280,0x00000000 ++#define LPM_MEM_DI0_AW0__FULL 0x1F040280,0xffffffff ++#define LPM_MEM_DI0_AW0__DI0_AW_TRIG_SEL 0x1F040280,0xF0000000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HEND 0x1F040280,0x0FFF0000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1F040280,0x0000F000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HSTART 0x1F040280,0x00000FFF ++ ++#define LPM_MEM_DI0_AW1__ADDR 0x1F040284 ++#define LPM_MEM_DI0_AW1__EMPTY 0x1F040284,0x00000000 ++#define LPM_MEM_DI0_AW1__FULL 0x1F040284,0xffffffff ++#define LPM_MEM_DI0_AW1__DI0_AW_VEND 0x1F040284,0x0FFF0000 ++#define LPM_MEM_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1F040284,0x0000F000 ++#define LPM_MEM_DI0_AW1__DI0_AW_VSTART 0x1F040284,0x00000FFF ++ ++#define LPM_MEM_DI0_SCR_CONF__ADDR 0x1F040288 ++#define LPM_MEM_DI0_SCR_CONF__EMPTY 0x1F040288,0x00000000 ++#define LPM_MEM_DI0_SCR_CONF__FULL 0x1F040288,0xffffffff ++#define LPM_MEM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1F040288,0x00000FFF ++ ++#define LPM_MEM_DI1_GENERAL__ADDR 0x1F04028C ++#define LPM_MEM_DI1_GENERAL__EMPTY 0x1F04028C,0x00000000 ++#define LPM_MEM_DI1_GENERAL__FULL 0x1F04028C,0xffffffff ++#define LPM_MEM_DI1_GENERAL__DI1_DISP_Y_SEL 0x1F04028C,0x70000000 ++#define LPM_MEM_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1F04028C,0x0F000000 ++#define LPM_MEM_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1F04028C,0x00800000 ++#define LPM_MEM_DI1_GENERAL__DI1_MASK_SEL 0x1F04028C,0x00400000 ++#define LPM_MEM_DI1_GENERAL__DI1_VSYNC_EXT 0x1F04028C,0x00200000 ++#define LPM_MEM_DI1_GENERAL__DI1_CLK_EXT 0x1F04028C,0x00100000 ++#define LPM_MEM_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1F04028C,0x000C0000 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1F04028C,0x00020000 ++#define LPM_MEM_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1F04028C,0x0000F000 ++#define LPM_MEM_DI1_GENERAL__DI1_ERR_TREATMENT 0x1F04028C,0x00000800 ++#define LPM_MEM_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1F04028C,0x00000400 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS1 0x1F04028C,0x00000200 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS0 0x1F04028C,0x00000100 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_8 0x1F04028C,0x00000080 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_7 0x1F04028C,0x00000040 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_6 0x1F04028C,0x00000020 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_5 0x1F04028C,0x00000010 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_4 0x1F04028C,0x00000008 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_3 0x1F04028C,0x00000004 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_2 0x1F04028C,0x00000002 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_1 0x1F04028C,0x00000001 ++ ++#define LPM_MEM_DI1_BS_CLKGEN0__ADDR 0x1F040290 ++#define LPM_MEM_DI1_BS_CLKGEN0__EMPTY 0x1F040290,0x00000000 ++#define LPM_MEM_DI1_BS_CLKGEN0__FULL 0x1F040290,0xffffffff ++#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1F040290,0x01FF0000 ++#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1F040290,0x00000FFF ++ ++#define LPM_MEM_DI1_BS_CLKGEN1__ADDR 0x1F040294 ++#define LPM_MEM_DI1_BS_CLKGEN1__EMPTY 0x1F040294,0x00000000 ++#define LPM_MEM_DI1_BS_CLKGEN1__FULL 0x1F040294,0xffffffff ++#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1F040294,0x01FF0000 ++#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1F040294,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN0_1__ADDR 0x1F040298 ++#define LPM_MEM_DI1_SW_GEN0_1__EMPTY 0x1F040298,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_1__FULL 0x1F040298,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1 0x1F040298,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1 0x1F040298,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1 0x1F040298,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1 0x1F040298,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_2__ADDR 0x1F04029C ++#define LPM_MEM_DI1_SW_GEN0_2__EMPTY 0x1F04029C,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_2__FULL 0x1F04029C,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2 0x1F04029C,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2 0x1F04029C,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2 0x1F04029C,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2 0x1F04029C,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_3__ADDR 0x1F0402A0 ++#define LPM_MEM_DI1_SW_GEN0_3__EMPTY 0x1F0402A0,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_3__FULL 0x1F0402A0,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3 0x1F0402A0,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3 0x1F0402A0,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3 0x1F0402A0,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3 0x1F0402A0,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_4__ADDR 0x1F0402A4 ++#define LPM_MEM_DI1_SW_GEN0_4__EMPTY 0x1F0402A4,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_4__FULL 0x1F0402A4,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4 0x1F0402A4,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4 0x1F0402A4,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4 0x1F0402A4,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4 0x1F0402A4,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_5__ADDR 0x1F0402A8 ++#define LPM_MEM_DI1_SW_GEN0_5__EMPTY 0x1F0402A8,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_5__FULL 0x1F0402A8,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5 0x1F0402A8,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5 0x1F0402A8,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5 0x1F0402A8,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5 0x1F0402A8,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_6__ADDR 0x1F0402AC ++#define LPM_MEM_DI1_SW_GEN0_6__EMPTY 0x1F0402AC,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_6__FULL 0x1F0402AC,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6 0x1F0402AC,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6 0x1F0402AC,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6 0x1F0402AC,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6 0x1F0402AC,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_7__ADDR 0x1F0402B0 ++#define LPM_MEM_DI1_SW_GEN0_7__EMPTY 0x1F0402B0,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_7__FULL 0x1F0402B0,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7 0x1F0402B0,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7 0x1F0402B0,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7 0x1F0402B0,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7 0x1F0402B0,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_8__ADDR 0x1F0402B4 ++#define LPM_MEM_DI1_SW_GEN0_8__EMPTY 0x1F0402B4,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_8__FULL 0x1F0402B4,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8 0x1F0402B4,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8 0x1F0402B4,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8 0x1F0402B4,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8 0x1F0402B4,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_9__ADDR 0x1F0402B8 ++#define LPM_MEM_DI1_SW_GEN0_9__EMPTY 0x1F0402B8,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_9__FULL 0x1F0402B8,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1F0402B8,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1F0402B8,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1F0402B8,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1F0402B8,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN1_1__ADDR 0x1F0402BC ++#define LPM_MEM_DI1_SW_GEN1_1__EMPTY 0x1F0402BC,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_1__FULL 0x1F0402BC,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1 0x1F0402BC,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1 0x1F0402BC,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1 0x1F0402BC,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1 0x1F0402BC,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1 0x1F0402BC,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1 0x1F0402BC,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_UP_1 0x1F0402BC,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_2__ADDR 0x1F0402C0 ++#define LPM_MEM_DI1_SW_GEN1_2__EMPTY 0x1F0402C0,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_2__FULL 0x1F0402C0,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2 0x1F0402C0,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2 0x1F0402C0,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2 0x1F0402C0,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2 0x1F0402C0,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2 0x1F0402C0,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2 0x1F0402C0,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_UP_2 0x1F0402C0,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_3__ADDR 0x1F0402C4 ++#define LPM_MEM_DI1_SW_GEN1_3__EMPTY 0x1F0402C4,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_3__FULL 0x1F0402C4,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3 0x1F0402C4,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3 0x1F0402C4,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3 0x1F0402C4,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3 0x1F0402C4,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3 0x1F0402C4,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3 0x1F0402C4,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_UP_3 0x1F0402C4,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_4__ADDR 0x1F0402C8 ++#define LPM_MEM_DI1_SW_GEN1_4__EMPTY 0x1F0402C8,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_4__FULL 0x1F0402C8,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4 0x1F0402C8,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4 0x1F0402C8,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4 0x1F0402C8,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4 0x1F0402C8,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4 0x1F0402C8,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4 0x1F0402C8,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_UP_4 0x1F0402C8,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_5__ADDR 0x1F0402CC ++#define LPM_MEM_DI1_SW_GEN1_5__EMPTY 0x1F0402CC,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_5__FULL 0x1F0402CC,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5 0x1F0402CC,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5 0x1F0402CC,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5 0x1F0402CC,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5 0x1F0402CC,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5 0x1F0402CC,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5 0x1F0402CC,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_UP_5 0x1F0402CC,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_6__ADDR 0x1F0402D0 ++#define LPM_MEM_DI1_SW_GEN1_6__EMPTY 0x1F0402D0,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_6__FULL 0x1F0402D0,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6 0x1F0402D0,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6 0x1F0402D0,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6 0x1F0402D0,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6 0x1F0402D0,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6 0x1F0402D0,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6 0x1F0402D0,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_UP_6 0x1F0402D0,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_7__ADDR 0x1F0402D4 ++#define LPM_MEM_DI1_SW_GEN1_7__EMPTY 0x1F0402D4,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_7__FULL 0x1F0402D4,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7 0x1F0402D4,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7 0x1F0402D4,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7 0x1F0402D4,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7 0x1F0402D4,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7 0x1F0402D4,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7 0x1F0402D4,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_UP_7 0x1F0402D4,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_8__ADDR 0x1F0402D8 ++#define LPM_MEM_DI1_SW_GEN1_8__EMPTY 0x1F0402D8,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_8__FULL 0x1F0402D8,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8 0x1F0402D8,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8 0x1F0402D8,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8 0x1F0402D8,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8 0x1F0402D8,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8 0x1F0402D8,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8 0x1F0402D8,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_UP_8 0x1F0402D8,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_9__ADDR 0x1F0402DC ++#define LPM_MEM_DI1_SW_GEN1_9__EMPTY 0x1F0402DC,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_9__FULL 0x1F0402DC,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1F0402DC,0xE0000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1F0402DC,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1F0402DC,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1F0402DC,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1F0402DC,0x00008000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1F0402DC,0x000001FF ++ ++#define LPM_MEM_DI1_SYNC_AS_GEN__ADDR 0x1F0402E0 ++#define LPM_MEM_DI1_SYNC_AS_GEN__EMPTY 0x1F0402E0,0x00000000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__FULL 0x1F0402E0,0xffffffff ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1F0402E0,0x10000000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1F0402E0,0x0000E000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1F0402E0,0x00000FFF ++ ++#define LPM_MEM_DI1_DW_GEN_0__ADDR 0x1F0402E4 ++#define LPM_MEM_DI1_DW_GEN_0__EMPTY 0x1F0402E4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_0__FULL 0x1F0402E4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1F0402E4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F0402E4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0 0x1F0402E4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_6_0 0x1F0402E4,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_5_0 0x1F0402E4,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_4_0 0x1F0402E4,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_3_0 0x1F0402E4,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_2_0 0x1F0402E4,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_1_0 0x1F0402E4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_0_0 0x1F0402E4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_0__ADDR 0x1F0402E4 ++#define LPM_MEM_DI1_DW_GEN_0__EMPTY 0x1F0402E4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_0__FULL 0x1F0402E4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1F0402E4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1F0402E4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0 0x1F0402E4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F0402E4,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1F0402E4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1F0402E4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_1__ADDR 0x1F0402E8 ++#define LPM_MEM_DI1_DW_GEN_1__EMPTY 0x1F0402E8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_1__FULL 0x1F0402E8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1F0402E8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F0402E8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1 0x1F0402E8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_6_1 0x1F0402E8,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_5_1 0x1F0402E8,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_4_1 0x1F0402E8,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_3_1 0x1F0402E8,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_2_1 0x1F0402E8,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_1_1 0x1F0402E8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_0_1 0x1F0402E8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_1__ADDR 0x1F0402E8 ++#define LPM_MEM_DI1_DW_GEN_1__EMPTY 0x1F0402E8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_1__FULL 0x1F0402E8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1F0402E8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1F0402E8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1 0x1F0402E8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F0402E8,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1F0402E8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1F0402E8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_2__ADDR 0x1F0402EC ++#define LPM_MEM_DI1_DW_GEN_2__EMPTY 0x1F0402EC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_2__FULL 0x1F0402EC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1F0402EC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F0402EC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2 0x1F0402EC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_6_2 0x1F0402EC,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_5_2 0x1F0402EC,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_4_2 0x1F0402EC,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_3_2 0x1F0402EC,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_2_2 0x1F0402EC,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_1_2 0x1F0402EC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_0_2 0x1F0402EC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_2__ADDR 0x1F0402EC ++#define LPM_MEM_DI1_DW_GEN_2__EMPTY 0x1F0402EC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_2__FULL 0x1F0402EC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1F0402EC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1F0402EC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2 0x1F0402EC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F0402EC,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1F0402EC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1F0402EC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_3__ADDR 0x1F0402F0 ++#define LPM_MEM_DI1_DW_GEN_3__EMPTY 0x1F0402F0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_3__FULL 0x1F0402F0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1F0402F0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F0402F0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3 0x1F0402F0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_6_3 0x1F0402F0,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_5_3 0x1F0402F0,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_4_3 0x1F0402F0,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_3_3 0x1F0402F0,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_2_3 0x1F0402F0,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_1_3 0x1F0402F0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_0_3 0x1F0402F0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_3__ADDR 0x1F0402F0 ++#define LPM_MEM_DI1_DW_GEN_3__EMPTY 0x1F0402F0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_3__FULL 0x1F0402F0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1F0402F0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1F0402F0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3 0x1F0402F0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F0402F0,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1F0402F0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1F0402F0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_4__ADDR 0x1F0402F4 ++#define LPM_MEM_DI1_DW_GEN_4__EMPTY 0x1F0402F4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_4__FULL 0x1F0402F4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1F0402F4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F0402F4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4 0x1F0402F4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_6_4 0x1F0402F4,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_5_4 0x1F0402F4,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_4_4 0x1F0402F4,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_3_4 0x1F0402F4,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_2_4 0x1F0402F4,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_1_4 0x1F0402F4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_0_4 0x1F0402F4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_4__ADDR 0x1F0402F4 ++#define LPM_MEM_DI1_DW_GEN_4__EMPTY 0x1F0402F4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_4__FULL 0x1F0402F4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1F0402F4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1F0402F4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4 0x1F0402F4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F0402F4,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1F0402F4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1F0402F4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_5__ADDR 0x1F0402F8 ++#define LPM_MEM_DI1_DW_GEN_5__EMPTY 0x1F0402F8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_5__FULL 0x1F0402F8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1F0402F8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F0402F8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5 0x1F0402F8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_6_5 0x1F0402F8,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_5_5 0x1F0402F8,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_4_5 0x1F0402F8,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_3_5 0x1F0402F8,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_2_5 0x1F0402F8,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_1_5 0x1F0402F8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_0_5 0x1F0402F8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_5__ADDR 0x1F0402F8 ++#define LPM_MEM_DI1_DW_GEN_5__EMPTY 0x1F0402F8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_5__FULL 0x1F0402F8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1F0402F8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1F0402F8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5 0x1F0402F8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F0402F8,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1F0402F8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1F0402F8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_6__ADDR 0x1F0402FC ++#define LPM_MEM_DI1_DW_GEN_6__EMPTY 0x1F0402FC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_6__FULL 0x1F0402FC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1F0402FC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F0402FC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6 0x1F0402FC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_6_6 0x1F0402FC,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_5_6 0x1F0402FC,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_4_6 0x1F0402FC,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_3_6 0x1F0402FC,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_2_6 0x1F0402FC,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_1_6 0x1F0402FC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_0_6 0x1F0402FC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_6__ADDR 0x1F0402FC ++#define LPM_MEM_DI1_DW_GEN_6__EMPTY 0x1F0402FC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_6__FULL 0x1F0402FC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1F0402FC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1F0402FC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6 0x1F0402FC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F0402FC,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1F0402FC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1F0402FC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_7__ADDR 0x1F040300 ++#define LPM_MEM_DI1_DW_GEN_7__EMPTY 0x1F040300,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_7__FULL 0x1F040300,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1F040300,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F040300,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7 0x1F040300,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_6_7 0x1F040300,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_5_7 0x1F040300,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_4_7 0x1F040300,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_3_7 0x1F040300,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_2_7 0x1F040300,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_1_7 0x1F040300,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_0_7 0x1F040300,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_7__ADDR 0x1F040300 ++#define LPM_MEM_DI1_DW_GEN_7__EMPTY 0x1F040300,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_7__FULL 0x1F040300,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1F040300,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1F040300,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7 0x1F040300,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F040300,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1F040300,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1F040300,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_8__ADDR 0x1F040304 ++#define LPM_MEM_DI1_DW_GEN_8__EMPTY 0x1F040304,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_8__FULL 0x1F040304,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1F040304,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040304,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8 0x1F040304,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_6_8 0x1F040304,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_5_8 0x1F040304,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_4_8 0x1F040304,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_3_8 0x1F040304,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_2_8 0x1F040304,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_1_8 0x1F040304,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_0_8 0x1F040304,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_8__ADDR 0x1F040304 ++#define LPM_MEM_DI1_DW_GEN_8__EMPTY 0x1F040304,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_8__FULL 0x1F040304,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1F040304,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1F040304,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8 0x1F040304,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040304,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1F040304,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1F040304,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_9__ADDR 0x1F040308 ++#define LPM_MEM_DI1_DW_GEN_9__EMPTY 0x1F040308,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_9__FULL 0x1F040308,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1F040308,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040308,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9 0x1F040308,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_6_9 0x1F040308,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_5_9 0x1F040308,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_4_9 0x1F040308,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_3_9 0x1F040308,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_2_9 0x1F040308,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_1_9 0x1F040308,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_0_9 0x1F040308,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_9__ADDR 0x1F040308 ++#define LPM_MEM_DI1_DW_GEN_9__EMPTY 0x1F040308,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_9__FULL 0x1F040308,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1F040308,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1F040308,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9 0x1F040308,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040308,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1F040308,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1F040308,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_10__ADDR 0x1F04030C ++#define LPM_MEM_DI1_DW_GEN_10__EMPTY 0x1F04030C,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_10__FULL 0x1F04030C,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1F04030C,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F04030C,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10 0x1F04030C,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_6_10 0x1F04030C,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_5_10 0x1F04030C,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_4_10 0x1F04030C,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_3_10 0x1F04030C,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_2_10 0x1F04030C,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_1_10 0x1F04030C,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_0_10 0x1F04030C,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_10__ADDR 0x1F04030C ++#define LPM_MEM_DI1_DW_GEN_10__EMPTY 0x1F04030C,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_10__FULL 0x1F04030C,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1F04030C,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1F04030C,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10 0x1F04030C,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F04030C,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1F04030C,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1F04030C,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_11__ADDR 0x1F040310 ++#define LPM_MEM_DI1_DW_GEN_11__EMPTY 0x1F040310,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_11__FULL 0x1F040310,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1F040310,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F040310,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11 0x1F040310,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_6_11 0x1F040310,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_5_11 0x1F040310,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_4_11 0x1F040310,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_3_11 0x1F040310,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_2_11 0x1F040310,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_1_11 0x1F040310,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_0_11 0x1F040310,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_11__ADDR 0x1F040310 ++#define LPM_MEM_DI1_DW_GEN_11__EMPTY 0x1F040310,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_11__FULL 0x1F040310,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1F040310,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1F040310,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11 0x1F040310,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040310,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1F040310,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1F040310,0x00000003 ++ ++#define LPM_MEM_DI1_DW_SET0_0__ADDR 0x1F040314 ++#define LPM_MEM_DI1_DW_SET0_0__EMPTY 0x1F040314,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_0__FULL 0x1F040314,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0 0x1F040314,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0 0x1F040314,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_1__ADDR 0x1F040318 ++#define LPM_MEM_DI1_DW_SET0_1__EMPTY 0x1F040318,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_1__FULL 0x1F040318,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1 0x1F040318,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1 0x1F040318,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_2__ADDR 0x1F04031C ++#define LPM_MEM_DI1_DW_SET0_2__EMPTY 0x1F04031C,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_2__FULL 0x1F04031C,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2 0x1F04031C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2 0x1F04031C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_3__ADDR 0x1F040320 ++#define LPM_MEM_DI1_DW_SET0_3__EMPTY 0x1F040320,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_3__FULL 0x1F040320,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3 0x1F040320,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3 0x1F040320,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_4__ADDR 0x1F040324 ++#define LPM_MEM_DI1_DW_SET0_4__EMPTY 0x1F040324,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_4__FULL 0x1F040324,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4 0x1F040324,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4 0x1F040324,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_5__ADDR 0x1F040328 ++#define LPM_MEM_DI1_DW_SET0_5__EMPTY 0x1F040328,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_5__FULL 0x1F040328,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5 0x1F040328,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5 0x1F040328,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_6__ADDR 0x1F04032C ++#define LPM_MEM_DI1_DW_SET0_6__EMPTY 0x1F04032C,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_6__FULL 0x1F04032C,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6 0x1F04032C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6 0x1F04032C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_7__ADDR 0x1F040330 ++#define LPM_MEM_DI1_DW_SET0_7__EMPTY 0x1F040330,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_7__FULL 0x1F040330,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7 0x1F040330,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7 0x1F040330,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_8__ADDR 0x1F040334 ++#define LPM_MEM_DI1_DW_SET0_8__EMPTY 0x1F040334,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_8__FULL 0x1F040334,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8 0x1F040334,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8 0x1F040334,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_9__ADDR 0x1F040338 ++#define LPM_MEM_DI1_DW_SET0_9__EMPTY 0x1F040338,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_9__FULL 0x1F040338,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9 0x1F040338,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9 0x1F040338,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_10__ADDR 0x1F04033C ++#define LPM_MEM_DI1_DW_SET0_10__EMPTY 0x1F04033C,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_10__FULL 0x1F04033C,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10 0x1F04033C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10 0x1F04033C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_11__ADDR 0x1F040340 ++#define LPM_MEM_DI1_DW_SET0_11__EMPTY 0x1F040340,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_11__FULL 0x1F040340,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11 0x1F040340,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11 0x1F040340,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_0__ADDR 0x1F040344 ++#define LPM_MEM_DI1_DW_SET1_0__EMPTY 0x1F040344,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_0__FULL 0x1F040344,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0 0x1F040344,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0 0x1F040344,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_1__ADDR 0x1F040348 ++#define LPM_MEM_DI1_DW_SET1_1__EMPTY 0x1F040348,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_1__FULL 0x1F040348,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1 0x1F040348,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1 0x1F040348,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_2__ADDR 0x1F04034C ++#define LPM_MEM_DI1_DW_SET1_2__EMPTY 0x1F04034C,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_2__FULL 0x1F04034C,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2 0x1F04034C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2 0x1F04034C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_3__ADDR 0x1F040350 ++#define LPM_MEM_DI1_DW_SET1_3__EMPTY 0x1F040350,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_3__FULL 0x1F040350,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3 0x1F040350,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3 0x1F040350,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_4__ADDR 0x1F040354 ++#define LPM_MEM_DI1_DW_SET1_4__EMPTY 0x1F040354,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_4__FULL 0x1F040354,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4 0x1F040354,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4 0x1F040354,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_5__ADDR 0x1F040358 ++#define LPM_MEM_DI1_DW_SET1_5__EMPTY 0x1F040358,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_5__FULL 0x1F040358,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5 0x1F040358,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5 0x1F040358,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_6__ADDR 0x1F04035C ++#define LPM_MEM_DI1_DW_SET1_6__EMPTY 0x1F04035C,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_6__FULL 0x1F04035C,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6 0x1F04035C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6 0x1F04035C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_7__ADDR 0x1F040360 ++#define LPM_MEM_DI1_DW_SET1_7__EMPTY 0x1F040360,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_7__FULL 0x1F040360,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7 0x1F040360,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7 0x1F040360,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_8__ADDR 0x1F040364 ++#define LPM_MEM_DI1_DW_SET1_8__EMPTY 0x1F040364,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_8__FULL 0x1F040364,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8 0x1F040364,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8 0x1F040364,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_9__ADDR 0x1F040368 ++#define LPM_MEM_DI1_DW_SET1_9__EMPTY 0x1F040368,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_9__FULL 0x1F040368,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9 0x1F040368,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9 0x1F040368,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_10__ADDR 0x1F04036C ++#define LPM_MEM_DI1_DW_SET1_10__EMPTY 0x1F04036C,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_10__FULL 0x1F04036C,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10 0x1F04036C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10 0x1F04036C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_11__ADDR 0x1F040370 ++#define LPM_MEM_DI1_DW_SET1_11__EMPTY 0x1F040370,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_11__FULL 0x1F040370,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11 0x1F040370,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11 0x1F040370,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_0__ADDR 0x1F040374 ++#define LPM_MEM_DI1_DW_SET2_0__EMPTY 0x1F040374,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_0__FULL 0x1F040374,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0 0x1F040374,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0 0x1F040374,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_1__ADDR 0x1F040378 ++#define LPM_MEM_DI1_DW_SET2_1__EMPTY 0x1F040378,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_1__FULL 0x1F040378,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1 0x1F040378,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1 0x1F040378,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_2__ADDR 0x1F04037C ++#define LPM_MEM_DI1_DW_SET2_2__EMPTY 0x1F04037C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_2__FULL 0x1F04037C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2 0x1F04037C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2 0x1F04037C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_3__ADDR 0x1F040380 ++#define LPM_MEM_DI1_DW_SET2_3__EMPTY 0x1F040380,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_3__FULL 0x1F040380,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3 0x1F040380,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3 0x1F040380,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_4__ADDR 0x1F040384 ++#define LPM_MEM_DI1_DW_SET2_4__EMPTY 0x1F040384,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_4__FULL 0x1F040384,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4 0x1F040384,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4 0x1F040384,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_5__ADDR 0x1F040388 ++#define LPM_MEM_DI1_DW_SET2_5__EMPTY 0x1F040388,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_5__FULL 0x1F040388,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5 0x1F040388,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5 0x1F040388,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_6__ADDR 0x1F04038C ++#define LPM_MEM_DI1_DW_SET2_6__EMPTY 0x1F04038C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_6__FULL 0x1F04038C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6 0x1F04038C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6 0x1F04038C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_7__ADDR 0x1F040390 ++#define LPM_MEM_DI1_DW_SET2_7__EMPTY 0x1F040390,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_7__FULL 0x1F040390,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7 0x1F040390,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7 0x1F040390,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_8__ADDR 0x1F040394 ++#define LPM_MEM_DI1_DW_SET2_8__EMPTY 0x1F040394,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_8__FULL 0x1F040394,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8 0x1F040394,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8 0x1F040394,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_9__ADDR 0x1F040398 ++#define LPM_MEM_DI1_DW_SET2_9__EMPTY 0x1F040398,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_9__FULL 0x1F040398,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9 0x1F040398,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9 0x1F040398,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_10__ADDR 0x1F04039C ++#define LPM_MEM_DI1_DW_SET2_10__EMPTY 0x1F04039C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_10__FULL 0x1F04039C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10 0x1F04039C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10 0x1F04039C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_11__ADDR 0x1F0403A0 ++#define LPM_MEM_DI1_DW_SET2_11__EMPTY 0x1F0403A0,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_11__FULL 0x1F0403A0,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11 0x1F0403A0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11 0x1F0403A0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_0__ADDR 0x1F0403A4 ++#define LPM_MEM_DI1_DW_SET3_0__EMPTY 0x1F0403A4,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_0__FULL 0x1F0403A4,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0 0x1F0403A4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0 0x1F0403A4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_1__ADDR 0x1F0403A8 ++#define LPM_MEM_DI1_DW_SET3_1__EMPTY 0x1F0403A8,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_1__FULL 0x1F0403A8,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1 0x1F0403A8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1 0x1F0403A8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_2__ADDR 0x1F0403AC ++#define LPM_MEM_DI1_DW_SET3_2__EMPTY 0x1F0403AC,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_2__FULL 0x1F0403AC,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2 0x1F0403AC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2 0x1F0403AC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_3__ADDR 0x1F0403B0 ++#define LPM_MEM_DI1_DW_SET3_3__EMPTY 0x1F0403B0,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_3__FULL 0x1F0403B0,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3 0x1F0403B0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3 0x1F0403B0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_4__ADDR 0x1F0403B4 ++#define LPM_MEM_DI1_DW_SET3_4__EMPTY 0x1F0403B4,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_4__FULL 0x1F0403B4,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4 0x1F0403B4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4 0x1F0403B4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_5__ADDR 0x1F0403B8 ++#define LPM_MEM_DI1_DW_SET3_5__EMPTY 0x1F0403B8,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_5__FULL 0x1F0403B8,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5 0x1F0403B8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5 0x1F0403B8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_6__ADDR 0x1F0403BC ++#define LPM_MEM_DI1_DW_SET3_6__EMPTY 0x1F0403BC,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_6__FULL 0x1F0403BC,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6 0x1F0403BC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6 0x1F0403BC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_7__ADDR 0x1F0403C0 ++#define LPM_MEM_DI1_DW_SET3_7__EMPTY 0x1F0403C0,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_7__FULL 0x1F0403C0,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7 0x1F0403C0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7 0x1F0403C0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_8__ADDR 0x1F0403C4 ++#define LPM_MEM_DI1_DW_SET3_8__EMPTY 0x1F0403C4,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_8__FULL 0x1F0403C4,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8 0x1F0403C4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8 0x1F0403C4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_9__ADDR 0x1F0403C8 ++#define LPM_MEM_DI1_DW_SET3_9__EMPTY 0x1F0403C8,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_9__FULL 0x1F0403C8,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9 0x1F0403C8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9 0x1F0403C8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_10__ADDR 0x1F0403CC ++#define LPM_MEM_DI1_DW_SET3_10__EMPTY 0x1F0403CC,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_10__FULL 0x1F0403CC,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10 0x1F0403CC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10 0x1F0403CC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_11__ADDR 0x1F0403D0 ++#define LPM_MEM_DI1_DW_SET3_11__EMPTY 0x1F0403D0,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_11__FULL 0x1F0403D0,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11 0x1F0403D0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11 0x1F0403D0,0x000001FF ++ ++#define LPM_MEM_DI1_STP_REP_1__ADDR 0x1F0403D4 ++#define LPM_MEM_DI1_STP_REP_1__EMPTY 0x1F0403D4,0x00000000 ++#define LPM_MEM_DI1_STP_REP_1__FULL 0x1F0403D4,0xffffffff ++#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_2 0x1F0403D4,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_1 0x1F0403D4,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_2__ADDR 0x1F0403D8 ++#define LPM_MEM_DI1_STP_REP_2__EMPTY 0x1F0403D8,0x00000000 ++#define LPM_MEM_DI1_STP_REP_2__FULL 0x1F0403D8,0xffffffff ++#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_4 0x1F0403D8,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_3 0x1F0403D8,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_3__ADDR 0x1F0403DC ++#define LPM_MEM_DI1_STP_REP_3__EMPTY 0x1F0403DC,0x00000000 ++#define LPM_MEM_DI1_STP_REP_3__FULL 0x1F0403DC,0xffffffff ++#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_6 0x1F0403DC,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_5 0x1F0403DC,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_4__ADDR 0x1F0403E0 ++#define LPM_MEM_DI1_STP_REP_4__EMPTY 0x1F0403E0,0x00000000 ++#define LPM_MEM_DI1_STP_REP_4__FULL 0x1F0403E0,0xffffffff ++#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_8 0x1F0403E0,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_7 0x1F0403E0,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_9__ADDR 0x1F0403E4 ++#define LPM_MEM_DI1_STP_REP_9__EMPTY 0x1F0403E4,0x00000000 ++#define LPM_MEM_DI1_STP_REP_9__FULL 0x1F0403E4,0xffffffff ++#define LPM_MEM_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1F0403E4,0x00000FFF ++ ++#define LPM_MEM_DI1_SER_CONF__ADDR 0x1F0403E8 ++#define LPM_MEM_DI1_SER_CONF__EMPTY 0x1F0403E8,0x00000000 ++#define LPM_MEM_DI1_SER_CONF__FULL 0x1F0403E8,0xffffffff ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1F0403E8,0xF0000000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1F0403E8,0x0F000000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1F0403E8,0x00F00000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1F0403E8,0x000F0000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1F0403E8,0x0000FF00 ++#define LPM_MEM_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1F0403E8,0x00000020 ++#define LPM_MEM_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1F0403E8,0x00000010 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1F0403E8,0x00000008 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1F0403E8,0x00000004 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1F0403E8,0x00000002 ++#define LPM_MEM_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1F0403E8,0x00000001 ++ ++#define LPM_MEM_DI1_SSC__ADDR 0x1F0403EC ++#define LPM_MEM_DI1_SSC__EMPTY 0x1F0403EC,0x00000000 ++#define LPM_MEM_DI1_SSC__FULL 0x1F0403EC,0xffffffff ++#define LPM_MEM_DI1_SSC__DI1_PIN17_ERM 0x1F0403EC,0x00800000 ++#define LPM_MEM_DI1_SSC__DI1_PIN16_ERM 0x1F0403EC,0x00400000 ++#define LPM_MEM_DI1_SSC__DI1_PIN15_ERM 0x1F0403EC,0x00200000 ++#define LPM_MEM_DI1_SSC__DI1_PIN14_ERM 0x1F0403EC,0x00100000 ++#define LPM_MEM_DI1_SSC__DI1_PIN13_ERM 0x1F0403EC,0x00080000 ++#define LPM_MEM_DI1_SSC__DI1_PIN12_ERM 0x1F0403EC,0x00040000 ++#define LPM_MEM_DI1_SSC__DI1_PIN11_ERM 0x1F0403EC,0x00020000 ++#define LPM_MEM_DI1_SSC__DI1_CS_ERM 0x1F0403EC,0x00010000 ++#define LPM_MEM_DI1_SSC__DI1_WAIT_ON 0x1F0403EC,0x00000020 ++#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1F0403EC,0x00000008 ++#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_PNTR 0x1F0403EC,0x00000007 ++ ++#define LPM_MEM_DI1_POL__ADDR 0x1F0403F0 ++#define LPM_MEM_DI1_POL__EMPTY 0x1F0403F0,0x00000000 ++#define LPM_MEM_DI1_POL__FULL 0x1F0403F0,0xffffffff ++#define LPM_MEM_DI1_POL__DI1_WAIT_POLARITY 0x1F0403F0,0x04000000 ++#define LPM_MEM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1F0403F0,0x02000000 ++#define LPM_MEM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1F0403F0,0x01000000 ++#define LPM_MEM_DI1_POL__DI1_CS1_DATA_POLARITY 0x1F0403F0,0x00800000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_17 0x1F0403F0,0x00400000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_16 0x1F0403F0,0x00200000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_15 0x1F0403F0,0x00100000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_14 0x1F0403F0,0x00080000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_13 0x1F0403F0,0x00040000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_12 0x1F0403F0,0x00020000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_11 0x1F0403F0,0x00010000 ++#define LPM_MEM_DI1_POL__DI1_CS0_DATA_POLARITY 0x1F0403F0,0x00008000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_17 0x1F0403F0,0x00004000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_16 0x1F0403F0,0x00002000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_15 0x1F0403F0,0x00001000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_14 0x1F0403F0,0x00000800 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_13 0x1F0403F0,0x00000400 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_12 0x1F0403F0,0x00000200 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_11 0x1F0403F0,0x00000100 ++#define LPM_MEM_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1F0403F0,0x00000080 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_17 0x1F0403F0,0x00000040 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_16 0x1F0403F0,0x00000020 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_15 0x1F0403F0,0x00000010 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_14 0x1F0403F0,0x00000008 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_13 0x1F0403F0,0x00000004 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_12 0x1F0403F0,0x00000002 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_11 0x1F0403F0,0x00000001 ++ ++#define LPM_MEM_DI1_AW0__ADDR 0x1F0403F4 ++#define LPM_MEM_DI1_AW0__EMPTY 0x1F0403F4,0x00000000 ++#define LPM_MEM_DI1_AW0__FULL 0x1F0403F4,0xffffffff ++#define LPM_MEM_DI1_AW0__DI1_AW_TRIG_SEL 0x1F0403F4,0xF0000000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HEND 0x1F0403F4,0x0FFF0000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1F0403F4,0x0000F000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HSTART 0x1F0403F4,0x00000FFF ++ ++#define LPM_MEM_DI1_AW1__ADDR 0x1F0403F8 ++#define LPM_MEM_DI1_AW1__EMPTY 0x1F0403F8,0x00000000 ++#define LPM_MEM_DI1_AW1__FULL 0x1F0403F8,0xffffffff ++#define LPM_MEM_DI1_AW1__DI1_AW_VEND 0x1F0403F8,0x0FFF0000 ++#define LPM_MEM_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1F0403F8,0x0000F000 ++#define LPM_MEM_DI1_AW1__DI1_AW_VSTART 0x1F0403F8,0x00000FFF ++ ++#define LPM_MEM_DI1_SCR_CONF__ADDR 0x1F0403FC ++#define LPM_MEM_DI1_SCR_CONF__EMPTY 0x1F0403FC,0x00000000 ++#define LPM_MEM_DI1_SCR_CONF__FULL 0x1F0403FC,0xffffffff ++#define LPM_MEM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1F0403FC,0x00000FFF ++ ++#define LPM_MEM_DMFC_RD_CHAN__ADDR 0x1F040400 ++#define LPM_MEM_DMFC_RD_CHAN__EMPTY 0x1F040400,0x00000000 ++#define LPM_MEM_DMFC_RD_CHAN__FULL 0x1F040400,0xffffffff ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_PPW_C 0x1F040400,0x03000000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_CLR_0 0x1F040400,0x00E00000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_SET_0 0x1F040400,0x001C0000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_EN_0 0x1F040400,0x00020000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1F040400,0x000000C0 ++ ++#define LPM_MEM_DMFC_WR_CHAN__ADDR 0x1F040404 ++#define LPM_MEM_DMFC_WR_CHAN__EMPTY 0x1F040404,0x00000000 ++#define LPM_MEM_DMFC_WR_CHAN__FULL 0x1F040404,0xffffffff ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1F040404,0xC0000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C 0x1F040404,0x38000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2C 0x1F040404,0x07000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1F040404,0x00C00000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C 0x1F040404,0x00380000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1C 0x1F040404,0x00070000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2 0x1F040404,0x0000C000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2 0x1F040404,0x00003800 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2 0x1F040404,0x00000700 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1 0x1F040404,0x000000C0 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1 0x1F040404,0x00000038 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1 0x1F040404,0x00000007 ++ ++#define LPM_MEM_DMFC_WR_CHAN_DEF__ADDR 0x1F040408 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__EMPTY 0x1F040408,0x00000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__FULL 0x1F040408,0xffffffff ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1F040408,0xE0000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1F040408,0x1C000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C 0x1F040408,0x02000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1F040408,0x00E00000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1F040408,0x001C0000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C 0x1F040408,0x00020000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2 0x1F040408,0x0000E000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2 0x1F040408,0x00001C00 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2 0x1F040408,0x00000200 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1 0x1F040408,0x000000E0 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1 0x1F040408,0x0000001C ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1 0x1F040408,0x00000002 ++ ++#define LPM_MEM_DMFC_DP_CHAN__ADDR 0x1F04040C ++#define LPM_MEM_DMFC_DP_CHAN__EMPTY 0x1F04040C,0x00000000 ++#define LPM_MEM_DMFC_DP_CHAN__FULL 0x1F04040C,0xffffffff ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1F04040C,0xC0000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F 0x1F04040C,0x38000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6F 0x1F04040C,0x07000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1F04040C,0x00C00000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B 0x1F04040C,0x00380000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6B 0x1F04040C,0x00070000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1F04040C,0x0000C000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F 0x1F04040C,0x00003800 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5F 0x1F04040C,0x00000700 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1F04040C,0x000000C0 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B 0x1F04040C,0x00000038 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5B 0x1F04040C,0x00000007 ++ ++#define LPM_MEM_DMFC_DP_CHAN_DEF__ADDR 0x1F040410 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__EMPTY 0x1F040410,0x00000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__FULL 0x1F040410,0xffffffff ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1F040410,0xE0000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1F040410,0x1C000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F 0x1F040410,0x02000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1F040410,0x00E00000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1F040410,0x001C0000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B 0x1F040410,0x00020000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1F040410,0x0000E000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1F040410,0x00001C00 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F 0x1F040410,0x00000200 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1F040410,0x000000E0 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1F040410,0x0000001C ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B 0x1F040410,0x00000002 ++ ++#define LPM_MEM_DMFC_GENERAL1__ADDR 0x1F040414 ++#define LPM_MEM_DMFC_GENERAL1__EMPTY 0x1F040414,0x00000000 ++#define LPM_MEM_DMFC_GENERAL1__FULL 0x1F040414,0xffffffff ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_9 0x1F040414,0x01000000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6F 0x1F040414,0x00800000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6B 0x1F040414,0x00400000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5F 0x1F040414,0x00200000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5B 0x1F040414,0x00100000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_4 0x1F040414,0x00080000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_3 0x1F040414,0x00040000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_2 0x1F040414,0x00020000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_1 0x1F040414,0x00010000 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_CLR_9 0x1F040414,0x0000E000 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_SET_9 0x1F040414,0x00001C00 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_EN_9 0x1F040414,0x00000200 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1F040414,0x00000060 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1F040414,0x00000003 ++ ++#define LPM_MEM_DMFC_GENERAL2__ADDR 0x1F040418 ++#define LPM_MEM_DMFC_GENERAL2__EMPTY 0x1F040418,0x00000000 ++#define LPM_MEM_DMFC_GENERAL2__FULL 0x1F040418,0xffffffff ++#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1F040418,0x1FFF0000 ++#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD 0x1F040418,0x00001FFF ++ ++#define LPM_MEM_DMFC_IC_CTRL__ADDR 0x1F04041C ++#define LPM_MEM_DMFC_IC_CTRL__EMPTY 0x1F04041C,0x00000000 ++#define LPM_MEM_DMFC_IC_CTRL__FULL 0x1F04041C,0xffffffff ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1F04041C,0xFFF80000 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD 0x1F04041C,0x0007FFC0 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_PPW_C 0x1F04041C,0x00000030 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_IN_PORT 0x1F04041C,0x00000007 ++ ++#define LPM_MEM_DC_READ_CH_CONF__ADDR 0x1F040420 ++#define LPM_MEM_DC_READ_CH_CONF__EMPTY 0x1F040420,0x00000000 ++#define LPM_MEM_DC_READ_CH_CONF__FULL 0x1F040420,0xffffffff ++#define LPM_MEM_DC_READ_CH_CONF__TIME_OUT_VALUE 0x1F040420,0xFFFF0000 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_3 0x1F040420,0x00000800 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_2 0x1F040420,0x00000400 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_1 0x1F040420,0x00000200 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_0 0x1F040420,0x00000100 ++#define LPM_MEM_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1F040420,0x00000040 ++#define LPM_MEM_DC_READ_CH_CONF__W_SIZE_0 0x1F040420,0x00000030 ++#define LPM_MEM_DC_READ_CH_CONF__PROG_DISP_ID_0 0x1F040420,0x0000000C ++#define LPM_MEM_DC_READ_CH_CONF__PROG_DI_ID_0 0x1F040420,0x00000002 ++#define LPM_MEM_DC_READ_CH_CONF__RD_CHANNEL_EN 0x1F040420,0x00000001 ++ ++#define LPM_MEM_DC_READ_CH_ADDR__ADDR 0x1F040424 ++#define LPM_MEM_DC_READ_CH_ADDR__EMPTY 0x1F040424,0x00000000 ++#define LPM_MEM_DC_READ_CH_ADDR__FULL 0x1F040424,0xffffffff ++#define LPM_MEM_DC_READ_CH_ADDR__ST_ADDR_0 0x1F040424,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_0__ADDR 0x1F040428 ++#define LPM_MEM_DC_RL0_CH_0__EMPTY 0x1F040428,0x00000000 ++#define LPM_MEM_DC_RL0_CH_0__FULL 0x1F040428,0xffffffff ++#define LPM_MEM_DC_RL0_CH_0__COD_NL_START_CHAN_0 0x1F040428,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1F040428,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_0__COD_NF_START_CHAN_0 0x1F040428,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1F040428,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_0__ADDR 0x1F04042C ++#define LPM_MEM_DC_RL1_CH_0__EMPTY 0x1F04042C,0x00000000 ++#define LPM_MEM_DC_RL1_CH_0__FULL 0x1F04042C,0xffffffff ++#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0 0x1F04042C,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1F04042C,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_0__COD_EOF_START_CHAN_0 0x1F04042C,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0 0x1F04042C,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_0__ADDR 0x1F040430 ++#define LPM_MEM_DC_RL2_CH_0__EMPTY 0x1F040430,0x00000000 ++#define LPM_MEM_DC_RL2_CH_0__FULL 0x1F040430,0xffffffff ++#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0 0x1F040430,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1F040430,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOL_START_CHAN_0 0x1F040430,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0 0x1F040430,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_0__ADDR 0x1F040434 ++#define LPM_MEM_DC_RL3_CH_0__EMPTY 0x1F040434,0x00000000 ++#define LPM_MEM_DC_RL3_CH_0__FULL 0x1F040434,0xffffffff ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0 0x1F040434,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1F040434,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0 0x1F040434,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1F040434,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_0__ADDR 0x1F040438 ++#define LPM_MEM_DC_RL4_CH_0__EMPTY 0x1F040438,0x00000000 ++#define LPM_MEM_DC_RL4_CH_0__FULL 0x1F040438,0xffffffff ++#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0 0x1F040438,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1F040438,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_1__ADDR 0x1F04043C ++#define LPM_MEM_DC_WR_CH_CONF_1__EMPTY 0x1F04043C,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_1__FULL 0x1F04043C,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_START_TIME_1 0x1F04043C,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_1__FIELD_MODE_1 0x1F04043C,0x00000200 ++#define LPM_MEM_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1F04043C,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1 0x1F04043C,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DISP_ID_1 0x1F04043C,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DI_ID_1 0x1F04043C,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_1__W_SIZE_1 0x1F04043C,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_1__ADDR 0x1F040440 ++#define LPM_MEM_DC_WR_CH_ADDR_1__EMPTY 0x1F040440,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_1__FULL 0x1F040440,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1F040440,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_1__ADDR 0x1F040444 ++#define LPM_MEM_DC_RL0_CH_1__EMPTY 0x1F040444,0x00000000 ++#define LPM_MEM_DC_RL0_CH_1__FULL 0x1F040444,0xffffffff ++#define LPM_MEM_DC_RL0_CH_1__COD_NL_START_CHAN_1 0x1F040444,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1F040444,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_1__COD_NF_START_CHAN_1 0x1F040444,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1F040444,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_1__ADDR 0x1F040448 ++#define LPM_MEM_DC_RL1_CH_1__EMPTY 0x1F040448,0x00000000 ++#define LPM_MEM_DC_RL1_CH_1__FULL 0x1F040448,0xffffffff ++#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1 0x1F040448,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1F040448,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_1__COD_EOF_START_CHAN_1 0x1F040448,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1 0x1F040448,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_1__ADDR 0x1F04044C ++#define LPM_MEM_DC_RL2_CH_1__EMPTY 0x1F04044C,0x00000000 ++#define LPM_MEM_DC_RL2_CH_1__FULL 0x1F04044C,0xffffffff ++#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1 0x1F04044C,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1F04044C,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOL_START_CHAN_1 0x1F04044C,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1 0x1F04044C,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_1__ADDR 0x1F040450 ++#define LPM_MEM_DC_RL3_CH_1__EMPTY 0x1F040450,0x00000000 ++#define LPM_MEM_DC_RL3_CH_1__FULL 0x1F040450,0xffffffff ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1 0x1F040450,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1F040450,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1 0x1F040450,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1F040450,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_1__ADDR 0x1F040454 ++#define LPM_MEM_DC_RL4_CH_1__EMPTY 0x1F040454,0x00000000 ++#define LPM_MEM_DC_RL4_CH_1__FULL 0x1F040454,0xffffffff ++#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1 0x1F040454,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1F040454,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_2__ADDR 0x1F040458 ++#define LPM_MEM_DC_WR_CH_CONF_2__EMPTY 0x1F040458,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_2__FULL 0x1F040458,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1F040458,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1F040458,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1F040458,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1F040458,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1F040458,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_2__W_SIZE_2 0x1F040458,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_2__ADDR 0x1F04045C ++#define LPM_MEM_DC_WR_CH_ADDR_2__EMPTY 0x1F04045C,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_2__FULL 0x1F04045C,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1F04045C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_2__ADDR 0x1F040460 ++#define LPM_MEM_DC_RL0_CH_2__EMPTY 0x1F040460,0x00000000 ++#define LPM_MEM_DC_RL0_CH_2__FULL 0x1F040460,0xffffffff ++#define LPM_MEM_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1F040460,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1F040460,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1F040460,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1F040460,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_2__ADDR 0x1F040464 ++#define LPM_MEM_DC_RL1_CH_2__EMPTY 0x1F040464,0x00000000 ++#define LPM_MEM_DC_RL1_CH_2__FULL 0x1F040464,0xffffffff ++#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1F040464,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1F040464,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1F040464,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1F040464,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_2__ADDR 0x1F040468 ++#define LPM_MEM_DC_RL2_CH_2__EMPTY 0x1F040468,0x00000000 ++#define LPM_MEM_DC_RL2_CH_2__FULL 0x1F040468,0xffffffff ++#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1F040468,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1F040468,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1F040468,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1F040468,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_2__ADDR 0x1F04046C ++#define LPM_MEM_DC_RL3_CH_2__EMPTY 0x1F04046C,0x00000000 ++#define LPM_MEM_DC_RL3_CH_2__FULL 0x1F04046C,0xffffffff ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1F04046C,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1F04046C,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1F04046C,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1F04046C,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_2__ADDR 0x1F040470 ++#define LPM_MEM_DC_RL4_CH_2__EMPTY 0x1F040470,0x00000000 ++#define LPM_MEM_DC_RL4_CH_2__FULL 0x1F040470,0xffffffff ++#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1F040470,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1F040470,0x0000000F ++ ++#define LPM_MEM_DC_CMD_CH_CONF_3__ADDR 0x1F040474 ++#define LPM_MEM_DC_CMD_CH_CONF_3__EMPTY 0x1F040474,0x00000000 ++#define LPM_MEM_DC_CMD_CH_CONF_3__FULL 0x1F040474,0xffffffff ++#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1F040474,0xFF000000 ++#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1F040474,0x0000FF00 ++#define LPM_MEM_DC_CMD_CH_CONF_3__W_SIZE_3 0x1F040474,0x00000003 ++ ++#define LPM_MEM_DC_CMD_CH_CONF_4__ADDR 0x1F040478 ++#define LPM_MEM_DC_CMD_CH_CONF_4__EMPTY 0x1F040478,0x00000000 ++#define LPM_MEM_DC_CMD_CH_CONF_4__FULL 0x1F040478,0xffffffff ++#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1F040478,0xFF000000 ++#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1F040478,0x0000FF00 ++#define LPM_MEM_DC_CMD_CH_CONF_4__W_SIZE_4 0x1F040478,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF_5__ADDR 0x1F04047C ++#define LPM_MEM_DC_WR_CH_CONF_5__EMPTY 0x1F04047C,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_5__FULL 0x1F04047C,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_START_TIME_5 0x1F04047C,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_5__FIELD_MODE_5 0x1F04047C,0x00000200 ++#define LPM_MEM_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1F04047C,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5 0x1F04047C,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DISP_ID_5 0x1F04047C,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DI_ID_5 0x1F04047C,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_5__W_SIZE_5 0x1F04047C,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_5__ADDR 0x1F040480 ++#define LPM_MEM_DC_WR_CH_ADDR_5__EMPTY 0x1F040480,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_5__FULL 0x1F040480,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1F040480,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_5__ADDR 0x1F040484 ++#define LPM_MEM_DC_RL0_CH_5__EMPTY 0x1F040484,0x00000000 ++#define LPM_MEM_DC_RL0_CH_5__FULL 0x1F040484,0xffffffff ++#define LPM_MEM_DC_RL0_CH_5__COD_NL_START_CHAN_5 0x1F040484,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1F040484,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_5__COD_NF_START_CHAN_5 0x1F040484,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1F040484,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_5__ADDR 0x1F040488 ++#define LPM_MEM_DC_RL1_CH_5__EMPTY 0x1F040488,0x00000000 ++#define LPM_MEM_DC_RL1_CH_5__FULL 0x1F040488,0xffffffff ++#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5 0x1F040488,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1F040488,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_5__COD_EOF_START_CHAN_5 0x1F040488,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5 0x1F040488,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_5__ADDR 0x1F04048C ++#define LPM_MEM_DC_RL2_CH_5__EMPTY 0x1F04048C,0x00000000 ++#define LPM_MEM_DC_RL2_CH_5__FULL 0x1F04048C,0xffffffff ++#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5 0x1F04048C,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1F04048C,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOL_START_CHAN_5 0x1F04048C,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5 0x1F04048C,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_5__ADDR 0x1F040490 ++#define LPM_MEM_DC_RL3_CH_5__EMPTY 0x1F040490,0x00000000 ++#define LPM_MEM_DC_RL3_CH_5__FULL 0x1F040490,0xffffffff ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5 0x1F040490,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1F040490,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5 0x1F040490,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1F040490,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_5__ADDR 0x1F040494 ++#define LPM_MEM_DC_RL4_CH_5__EMPTY 0x1F040494,0x00000000 ++#define LPM_MEM_DC_RL4_CH_5__FULL 0x1F040494,0xffffffff ++#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5 0x1F040494,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1F040494,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_6__ADDR 0x1F040498 ++#define LPM_MEM_DC_WR_CH_CONF_6__EMPTY 0x1F040498,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_6__FULL 0x1F040498,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1F040498,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1F040498,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1F040498,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1F040498,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1F040498,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_6__W_SIZE_6 0x1F040498,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_6__ADDR 0x1F04049C ++#define LPM_MEM_DC_WR_CH_ADDR_6__EMPTY 0x1F04049C,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_6__FULL 0x1F04049C,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1F04049C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_6__ADDR 0x1F0404A0 ++#define LPM_MEM_DC_RL0_CH_6__EMPTY 0x1F0404A0,0x00000000 ++#define LPM_MEM_DC_RL0_CH_6__FULL 0x1F0404A0,0xffffffff ++#define LPM_MEM_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1F0404A0,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1F0404A0,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1F0404A0,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1F0404A0,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_6__ADDR 0x1F0404A4 ++#define LPM_MEM_DC_RL1_CH_6__EMPTY 0x1F0404A4,0x00000000 ++#define LPM_MEM_DC_RL1_CH_6__FULL 0x1F0404A4,0xffffffff ++#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1F0404A4,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1F0404A4,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1F0404A4,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1F0404A4,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_6__ADDR 0x1F0404A8 ++#define LPM_MEM_DC_RL2_CH_6__EMPTY 0x1F0404A8,0x00000000 ++#define LPM_MEM_DC_RL2_CH_6__FULL 0x1F0404A8,0xffffffff ++#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1F0404A8,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1F0404A8,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1F0404A8,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1F0404A8,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_6__ADDR 0x1F0404AC ++#define LPM_MEM_DC_RL3_CH_6__EMPTY 0x1F0404AC,0x00000000 ++#define LPM_MEM_DC_RL3_CH_6__FULL 0x1F0404AC,0xffffffff ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1F0404AC,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1F0404AC,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1F0404AC,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1F0404AC,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_6__ADDR 0x1F0404B0 ++#define LPM_MEM_DC_RL4_CH_6__EMPTY 0x1F0404B0,0x00000000 ++#define LPM_MEM_DC_RL4_CH_6__FULL 0x1F0404B0,0xffffffff ++#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1F0404B0,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1F0404B0,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF1_8__ADDR 0x1F0404B4 ++#define LPM_MEM_DC_WR_CH_CONF1_8__EMPTY 0x1F0404B4,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF1_8__FULL 0x1F0404B4,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF1_8__MCU_DISP_ID_8 0x1F0404B4,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1F0404B4,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF1_8__W_SIZE_8 0x1F0404B4,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF2_8__ADDR 0x1F0404B8 ++#define LPM_MEM_DC_WR_CH_CONF2_8__EMPTY 0x1F0404B8,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF2_8__FULL 0x1F0404B8,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1F0404B8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL1_CH_8__ADDR 0x1F0404BC ++#define LPM_MEM_DC_RL1_CH_8__EMPTY 0x1F0404BC,0x00000000 ++#define LPM_MEM_DC_RL1_CH_8__FULL 0x1F0404BC,0xffffffff ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1F0404BC,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1F0404BC,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8 0x1F0404BC,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_8__ADDR 0x1F0404C0 ++#define LPM_MEM_DC_RL2_CH_8__EMPTY 0x1F0404C0,0x00000000 ++#define LPM_MEM_DC_RL2_CH_8__FULL 0x1F0404C0,0xffffffff ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1F0404C0,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1F0404C0,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8 0x1F0404C0,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_8__ADDR 0x1F0404C4 ++#define LPM_MEM_DC_RL3_CH_8__EMPTY 0x1F0404C4,0x00000000 ++#define LPM_MEM_DC_RL3_CH_8__FULL 0x1F0404C4,0xffffffff ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1F0404C4,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1F0404C4,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8 0x1F0404C4,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_8__ADDR 0x1F0404C8 ++#define LPM_MEM_DC_RL4_CH_8__EMPTY 0x1F0404C8,0x00000000 ++#define LPM_MEM_DC_RL4_CH_8__FULL 0x1F0404C8,0xffffffff ++#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1F0404C8,0xFF000000 ++#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1F0404C8,0x0000FF00 ++ ++#define LPM_MEM_DC_RL5_CH_8__ADDR 0x1F0404CC ++#define LPM_MEM_DC_RL5_CH_8__EMPTY 0x1F0404CC,0x00000000 ++#define LPM_MEM_DC_RL5_CH_8__FULL 0x1F0404CC,0xffffffff ++#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1F0404CC,0xFF000000 ++#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1F0404CC,0x0000FF00 ++ ++#define LPM_MEM_DC_RL6_CH_8__ADDR 0x1F0404D0 ++#define LPM_MEM_DC_RL6_CH_8__EMPTY 0x1F0404D0,0x00000000 ++#define LPM_MEM_DC_RL6_CH_8__FULL 0x1F0404D0,0xffffffff ++#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1F0404D0,0xFF000000 ++#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1F0404D0,0x0000FF00 ++ ++#define LPM_MEM_DC_WR_CH_CONF1_9__ADDR 0x1F0404D4 ++#define LPM_MEM_DC_WR_CH_CONF1_9__EMPTY 0x1F0404D4,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF1_9__FULL 0x1F0404D4,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF1_9__MCU_DISP_ID_9 0x1F0404D4,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1F0404D4,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF1_9__W_SIZE_9 0x1F0404D4,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF2_9__ADDR 0x1F0404D8 ++#define LPM_MEM_DC_WR_CH_CONF2_9__EMPTY 0x1F0404D8,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF2_9__FULL 0x1F0404D8,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1F0404D8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL1_CH_9__ADDR 0x1F0404DC ++#define LPM_MEM_DC_RL1_CH_9__EMPTY 0x1F0404DC,0x00000000 ++#define LPM_MEM_DC_RL1_CH_9__FULL 0x1F0404DC,0xffffffff ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1F0404DC,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1F0404DC,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9 0x1F0404DC,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_9__ADDR 0x1F0404E0 ++#define LPM_MEM_DC_RL2_CH_9__EMPTY 0x1F0404E0,0x00000000 ++#define LPM_MEM_DC_RL2_CH_9__FULL 0x1F0404E0,0xffffffff ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1F0404E0,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1F0404E0,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9 0x1F0404E0,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_9__ADDR 0x1F0404E4 ++#define LPM_MEM_DC_RL3_CH_9__EMPTY 0x1F0404E4,0x00000000 ++#define LPM_MEM_DC_RL3_CH_9__FULL 0x1F0404E4,0xffffffff ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1F0404E4,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1F0404E4,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9 0x1F0404E4,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_9__ADDR 0x1F0404E8 ++#define LPM_MEM_DC_RL4_CH_9__EMPTY 0x1F0404E8,0x00000000 ++#define LPM_MEM_DC_RL4_CH_9__FULL 0x1F0404E8,0xffffffff ++#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1F0404E8,0xFF000000 ++#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1F0404E8,0x0000FF00 ++ ++#define LPM_MEM_DC_RL5_CH_9__ADDR 0x1F0404EC ++#define LPM_MEM_DC_RL5_CH_9__EMPTY 0x1F0404EC,0x00000000 ++#define LPM_MEM_DC_RL5_CH_9__FULL 0x1F0404EC,0xffffffff ++#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1F0404EC,0xFF000000 ++#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1F0404EC,0x0000FF00 ++ ++#define LPM_MEM_DC_RL6_CH_9__ADDR 0x1F0404F0 ++#define LPM_MEM_DC_RL6_CH_9__EMPTY 0x1F0404F0,0x00000000 ++#define LPM_MEM_DC_RL6_CH_9__FULL 0x1F0404F0,0xffffffff ++#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1F0404F0,0xFF000000 ++#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1F0404F0,0x0000FF00 ++ ++#define LPM_MEM_DC_GEN__ADDR 0x1F0404F4 ++#define LPM_MEM_DC_GEN__EMPTY 0x1F0404F4,0x00000000 ++#define LPM_MEM_DC_GEN__FULL 0x1F0404F4,0xffffffff ++#define LPM_MEM_DC_GEN__DC_BK_EN 0x1F0404F4,0x01000000 ++#define LPM_MEM_DC_GEN__DC_BKDIV 0x1F0404F4,0x00FF0000 ++#define LPM_MEM_DC_GEN__DC_CH5_TYPE 0x1F0404F4,0x00000100 ++#define LPM_MEM_DC_GEN__SYNC_PRIORITY_1 0x1F0404F4,0x00000080 ++#define LPM_MEM_DC_GEN__SYNC_PRIORITY_5 0x1F0404F4,0x00000040 ++#define LPM_MEM_DC_GEN__MASK4CHAN_5 0x1F0404F4,0x00000020 ++#define LPM_MEM_DC_GEN__MASK_EN 0x1F0404F4,0x00000010 ++#define LPM_MEM_DC_GEN__SYNC_1_6 0x1F0404F4,0x00000006 ++ ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR 0x1F0404F8 ++#define LPM_MEM_DC_DISP_CONF1_0__EMPTY 0x1F0404F8,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_0__FULL 0x1F0404F8,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1F0404F8,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0 0x1F0404F8,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR_BE_L_INC_0 0x1F0404F8,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR_INCREMENT_0 0x1F0404F8,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_0__DISP_TYP_0 0x1F0404F8,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR 0x1F0404FC ++#define LPM_MEM_DC_DISP_CONF1_1__EMPTY 0x1F0404FC,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_1__FULL 0x1F0404FC,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1F0404FC,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1 0x1F0404FC,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR_BE_L_INC_1 0x1F0404FC,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR_INCREMENT_1 0x1F0404FC,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_1__DISP_TYP_1 0x1F0404FC,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR 0x1F040500 ++#define LPM_MEM_DC_DISP_CONF1_2__EMPTY 0x1F040500,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_2__FULL 0x1F040500,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1F040500,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2 0x1F040500,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR_BE_L_INC_2 0x1F040500,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR_INCREMENT_2 0x1F040500,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_2__DISP_TYP_2 0x1F040500,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR 0x1F040504 ++#define LPM_MEM_DC_DISP_CONF1_3__EMPTY 0x1F040504,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_3__FULL 0x1F040504,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1F040504,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3 0x1F040504,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR_BE_L_INC_3 0x1F040504,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR_INCREMENT_3 0x1F040504,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_3__DISP_TYP_3 0x1F040504,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF2_0__ADDR 0x1F040508 ++#define LPM_MEM_DC_DISP_CONF2_0__EMPTY 0x1F040508,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_0__FULL 0x1F040508,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_0__SL_0 0x1F040508,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_1__ADDR 0x1F04050C ++#define LPM_MEM_DC_DISP_CONF2_1__EMPTY 0x1F04050C,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_1__FULL 0x1F04050C,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_1__SL_1 0x1F04050C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_2__ADDR 0x1F040510 ++#define LPM_MEM_DC_DISP_CONF2_2__EMPTY 0x1F040510,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_2__FULL 0x1F040510,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_2__SL_2 0x1F040510,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_3__ADDR 0x1F040514 ++#define LPM_MEM_DC_DISP_CONF2_3__EMPTY 0x1F040514,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_3__FULL 0x1F040514,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_3__SL_3 0x1F040514,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DI0_CONF_1__ADDR 0x1F040518 ++#define LPM_MEM_DC_DI0_CONF_1__EMPTY 0x1F040518,0x00000000 ++#define LPM_MEM_DC_DI0_CONF_1__FULL 0x1F040518,0xffffffff ++#define LPM_MEM_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1F040518,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI0_CONF_2__ADDR 0x1F04051C ++#define LPM_MEM_DC_DI0_CONF_2__EMPTY 0x1F04051C,0x00000000 ++#define LPM_MEM_DC_DI0_CONF_2__FULL 0x1F04051C,0xffffffff ++#define LPM_MEM_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1F04051C,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI1_CONF_1__ADDR 0x1F040520 ++#define LPM_MEM_DC_DI1_CONF_1__EMPTY 0x1F040520,0x00000000 ++#define LPM_MEM_DC_DI1_CONF_1__FULL 0x1F040520,0xffffffff ++#define LPM_MEM_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1F040520,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI1_CONF_2__ADDR 0x1F040524 ++#define LPM_MEM_DC_DI1_CONF_2__EMPTY 0x1F040524,0x00000000 ++#define LPM_MEM_DC_DI1_CONF_2__FULL 0x1F040524,0xffffffff ++#define LPM_MEM_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1F040524,0xFFFFFFFF ++ ++#define LPM_MEM_DC_MAP_CONF_0__ADDR 0x1F040528 ++#define LPM_MEM_DC_MAP_CONF_0__EMPTY 0x1F040528,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_0__FULL 0x1F040528,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1F040528,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1F040528,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1F040528,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1F040528,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1F040528,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1F040528,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_1__ADDR 0x1F04052C ++#define LPM_MEM_DC_MAP_CONF_1__EMPTY 0x1F04052C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_1__FULL 0x1F04052C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1F04052C,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1F04052C,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1F04052C,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1F04052C,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1F04052C,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1F04052C,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_2__ADDR 0x1F040530 ++#define LPM_MEM_DC_MAP_CONF_2__EMPTY 0x1F040530,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_2__FULL 0x1F040530,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1F040530,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1F040530,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1F040530,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1F040530,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1F040530,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1F040530,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_3__ADDR 0x1F040534 ++#define LPM_MEM_DC_MAP_CONF_3__EMPTY 0x1F040534,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_3__FULL 0x1F040534,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1F040534,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1F040534,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1F040534,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1F040534,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1F040534,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1F040534,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_4__ADDR 0x1F040538 ++#define LPM_MEM_DC_MAP_CONF_4__EMPTY 0x1F040538,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_4__FULL 0x1F040538,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1F040538,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1F040538,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1F040538,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1F040538,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1F040538,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1F040538,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_5__ADDR 0x1F04053C ++#define LPM_MEM_DC_MAP_CONF_5__EMPTY 0x1F04053C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_5__FULL 0x1F04053C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1F04053C,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1F04053C,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1F04053C,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1F04053C,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1F04053C,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1F04053C,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_6__ADDR 0x1F040540 ++#define LPM_MEM_DC_MAP_CONF_6__EMPTY 0x1F040540,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_6__FULL 0x1F040540,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1F040540,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1F040540,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1F040540,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1F040540,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1F040540,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1F040540,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_7__ADDR 0x1F040544 ++#define LPM_MEM_DC_MAP_CONF_7__EMPTY 0x1F040544,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_7__FULL 0x1F040544,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1F040544,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1F040544,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1F040544,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1F040544,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1F040544,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1F040544,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_8__ADDR 0x1F040548 ++#define LPM_MEM_DC_MAP_CONF_8__EMPTY 0x1F040548,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_8__FULL 0x1F040548,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1F040548,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1F040548,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1F040548,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1F040548,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1F040548,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1F040548,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_9__ADDR 0x1F04054C ++#define LPM_MEM_DC_MAP_CONF_9__EMPTY 0x1F04054C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_9__FULL 0x1F04054C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1F04054C,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1F04054C,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1F04054C,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1F04054C,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1F04054C,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1F04054C,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_10__ADDR 0x1F040550 ++#define LPM_MEM_DC_MAP_CONF_10__EMPTY 0x1F040550,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_10__FULL 0x1F040550,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1F040550,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1F040550,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1F040550,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1F040550,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1F040550,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1F040550,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_11__ADDR 0x1F040554 ++#define LPM_MEM_DC_MAP_CONF_11__EMPTY 0x1F040554,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_11__FULL 0x1F040554,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1F040554,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1F040554,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1F040554,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1F040554,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1F040554,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1F040554,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_12__ADDR 0x1F040558 ++#define LPM_MEM_DC_MAP_CONF_12__EMPTY 0x1F040558,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_12__FULL 0x1F040558,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1F040558,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1F040558,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1F040558,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1F040558,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1F040558,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1F040558,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_13__ADDR 0x1F04055C ++#define LPM_MEM_DC_MAP_CONF_13__EMPTY 0x1F04055C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_13__FULL 0x1F04055C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1F04055C,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1F04055C,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1F04055C,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1F04055C,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1F04055C,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1F04055C,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_14__ADDR 0x1F040560 ++#define LPM_MEM_DC_MAP_CONF_14__EMPTY 0x1F040560,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_14__FULL 0x1F040560,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1F040560,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1F040560,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1F040560,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1F040560,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1F040560,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1F040560,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_15__ADDR 0x1F040564 ++#define LPM_MEM_DC_MAP_CONF_15__EMPTY 0x1F040564,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_15__FULL 0x1F040564,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_1 0x1F040564,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_1 0x1F040564,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_0 0x1F040564,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_0 0x1F040564,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_16__ADDR 0x1F040568 ++#define LPM_MEM_DC_MAP_CONF_16__EMPTY 0x1F040568,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_16__FULL 0x1F040568,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_3 0x1F040568,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_3 0x1F040568,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_2 0x1F040568,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_2 0x1F040568,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_17__ADDR 0x1F04056C ++#define LPM_MEM_DC_MAP_CONF_17__EMPTY 0x1F04056C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_17__FULL 0x1F04056C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_5 0x1F04056C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_5 0x1F04056C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_4 0x1F04056C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_4 0x1F04056C,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_18__ADDR 0x1F040570 ++#define LPM_MEM_DC_MAP_CONF_18__EMPTY 0x1F040570,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_18__FULL 0x1F040570,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_7 0x1F040570,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_7 0x1F040570,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_6 0x1F040570,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_6 0x1F040570,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_19__ADDR 0x1F040574 ++#define LPM_MEM_DC_MAP_CONF_19__EMPTY 0x1F040574,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_19__FULL 0x1F040574,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_9 0x1F040574,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_9 0x1F040574,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_8 0x1F040574,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_8 0x1F040574,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_20__ADDR 0x1F040578 ++#define LPM_MEM_DC_MAP_CONF_20__EMPTY 0x1F040578,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_20__FULL 0x1F040578,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_11 0x1F040578,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_11 0x1F040578,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_10 0x1F040578,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_10 0x1F040578,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_21__ADDR 0x1F04057C ++#define LPM_MEM_DC_MAP_CONF_21__EMPTY 0x1F04057C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_21__FULL 0x1F04057C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_13 0x1F04057C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_13 0x1F04057C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_12 0x1F04057C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_12 0x1F04057C,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_22__ADDR 0x1F040580 ++#define LPM_MEM_DC_MAP_CONF_22__EMPTY 0x1F040580,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_22__FULL 0x1F040580,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_15 0x1F040580,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_15 0x1F040580,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_14 0x1F040580,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_14 0x1F040580,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_23__ADDR 0x1F040584 ++#define LPM_MEM_DC_MAP_CONF_23__EMPTY 0x1F040584,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_23__FULL 0x1F040584,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_17 0x1F040584,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_17 0x1F040584,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_16 0x1F040584,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_16 0x1F040584,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_24__ADDR 0x1F040588 ++#define LPM_MEM_DC_MAP_CONF_24__EMPTY 0x1F040588,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_24__FULL 0x1F040588,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_19 0x1F040588,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_19 0x1F040588,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_18 0x1F040588,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_18 0x1F040588,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_25__ADDR 0x1F04058C ++#define LPM_MEM_DC_MAP_CONF_25__EMPTY 0x1F04058C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_25__FULL 0x1F04058C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_21 0x1F04058C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_21 0x1F04058C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_20 0x1F04058C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_20 0x1F04058C,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_26__ADDR 0x1F040590 ++#define LPM_MEM_DC_MAP_CONF_26__EMPTY 0x1F040590,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_26__FULL 0x1F040590,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_23 0x1F040590,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_23 0x1F040590,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_22 0x1F040590,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_22 0x1F040590,0x000000FF ++ ++#define LPM_MEM_DC_UGDE0_0__ADDR 0x1F040594 ++#define LPM_MEM_DC_UGDE0_0__EMPTY 0x1F040594,0x00000000 ++#define LPM_MEM_DC_UGDE0_0__FULL 0x1F040594,0xffffffff ++#define LPM_MEM_DC_UGDE0_0__NF_NL_0 0x1F040594,0x18000000 ++#define LPM_MEM_DC_UGDE0_0__AUTORESTART_0 0x1F040594,0x04000000 ++#define LPM_MEM_DC_UGDE0_0__ODD_EN_0 0x1F040594,0x02000000 ++#define LPM_MEM_DC_UGDE0_0__COD_ODD_START_0 0x1F040594,0x00FF0000 ++#define LPM_MEM_DC_UGDE0_0__COD_EV_START_0 0x1F040594,0x0000FF00 ++#define LPM_MEM_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1F040594,0x00000078 ++#define LPM_MEM_DC_UGDE0_0__ID_CODED_0 0x1F040594,0x00000007 ++ ++#define LPM_MEM_DC_UGDE0_1__ADDR 0x1F040598 ++#define LPM_MEM_DC_UGDE0_1__EMPTY 0x1F040598,0x00000000 ++#define LPM_MEM_DC_UGDE0_1__FULL 0x1F040598,0xffffffff ++#define LPM_MEM_DC_UGDE0_1__STEP_0 0x1F040598,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE0_2__ADDR 0x1F04059C ++#define LPM_MEM_DC_UGDE0_2__EMPTY 0x1F04059C,0x00000000 ++#define LPM_MEM_DC_UGDE0_2__FULL 0x1F04059C,0xffffffff ++#define LPM_MEM_DC_UGDE0_2__OFFSET_DT_0 0x1F04059C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE0_3__ADDR 0x1F0405A0 ++#define LPM_MEM_DC_UGDE0_3__EMPTY 0x1F0405A0,0x00000000 ++#define LPM_MEM_DC_UGDE0_3__FULL 0x1F0405A0,0xffffffff ++#define LPM_MEM_DC_UGDE0_3__STEP_REPEAT_0 0x1F0405A0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_0__ADDR 0x1F0405A4 ++#define LPM_MEM_DC_UGDE1_0__EMPTY 0x1F0405A4,0x00000000 ++#define LPM_MEM_DC_UGDE1_0__FULL 0x1F0405A4,0xffffffff ++#define LPM_MEM_DC_UGDE1_0__NF_NL_1 0x1F0405A4,0x18000000 ++#define LPM_MEM_DC_UGDE1_0__AUTORESTART_1 0x1F0405A4,0x04000000 ++#define LPM_MEM_DC_UGDE1_0__ODD_EN_1 0x1F0405A4,0x02000000 ++#define LPM_MEM_DC_UGDE1_0__COD_ODD_START_1 0x1F0405A4,0x00FF0000 ++#define LPM_MEM_DC_UGDE1_0__COD_EV_START_1 0x1F0405A4,0x00007F80 ++#define LPM_MEM_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1F0405A4,0x00000078 ++#define LPM_MEM_DC_UGDE1_0__ID_CODED_1 0x1F0405A4,0x00000007 ++ ++#define LPM_MEM_DC_UGDE1_1__ADDR 0x1F0405A8 ++#define LPM_MEM_DC_UGDE1_1__EMPTY 0x1F0405A8,0x00000000 ++#define LPM_MEM_DC_UGDE1_1__FULL 0x1F0405A8,0xffffffff ++#define LPM_MEM_DC_UGDE1_1__STEP_1 0x1F0405A8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_2__ADDR 0x1F0405AC ++#define LPM_MEM_DC_UGDE1_2__EMPTY 0x1F0405AC,0x00000000 ++#define LPM_MEM_DC_UGDE1_2__FULL 0x1F0405AC,0xffffffff ++#define LPM_MEM_DC_UGDE1_2__OFFSET_DT_1 0x1F0405AC,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_3__ADDR 0x1F0405B0 ++#define LPM_MEM_DC_UGDE1_3__EMPTY 0x1F0405B0,0x00000000 ++#define LPM_MEM_DC_UGDE1_3__FULL 0x1F0405B0,0xffffffff ++#define LPM_MEM_DC_UGDE1_3__STEP_REPEAT_1 0x1F0405B0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_0__ADDR 0x1F0405B4 ++#define LPM_MEM_DC_UGDE2_0__EMPTY 0x1F0405B4,0x00000000 ++#define LPM_MEM_DC_UGDE2_0__FULL 0x1F0405B4,0xffffffff ++#define LPM_MEM_DC_UGDE2_0__NF_NL_2 0x1F0405B4,0x18000000 ++#define LPM_MEM_DC_UGDE2_0__AUTORESTART_2 0x1F0405B4,0x04000000 ++#define LPM_MEM_DC_UGDE2_0__ODD_EN_2 0x1F0405B4,0x02000000 ++#define LPM_MEM_DC_UGDE2_0__COD_ODD_START_2 0x1F0405B4,0x00FF0000 ++#define LPM_MEM_DC_UGDE2_0__COD_EV_START_2 0x1F0405B4,0x00007F80 ++#define LPM_MEM_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1F0405B4,0x00000078 ++#define LPM_MEM_DC_UGDE2_0__ID_CODED_2 0x1F0405B4,0x00000007 ++ ++#define LPM_MEM_DC_UGDE2_1__ADDR 0x1F0405B8 ++#define LPM_MEM_DC_UGDE2_1__EMPTY 0x1F0405B8,0x00000000 ++#define LPM_MEM_DC_UGDE2_1__FULL 0x1F0405B8,0xffffffff ++#define LPM_MEM_DC_UGDE2_1__STEP_2 0x1F0405B8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_2__ADDR 0x1F0405BC ++#define LPM_MEM_DC_UGDE2_2__EMPTY 0x1F0405BC,0x00000000 ++#define LPM_MEM_DC_UGDE2_2__FULL 0x1F0405BC,0xffffffff ++#define LPM_MEM_DC_UGDE2_2__OFFSET_DT_2 0x1F0405BC,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_3__ADDR 0x1F0405C0 ++#define LPM_MEM_DC_UGDE2_3__EMPTY 0x1F0405C0,0x00000000 ++#define LPM_MEM_DC_UGDE2_3__FULL 0x1F0405C0,0xffffffff ++#define LPM_MEM_DC_UGDE2_3__STEP_REPEAT_2 0x1F0405C0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_0__ADDR 0x1F0405C4 ++#define LPM_MEM_DC_UGDE3_0__EMPTY 0x1F0405C4,0x00000000 ++#define LPM_MEM_DC_UGDE3_0__FULL 0x1F0405C4,0xffffffff ++#define LPM_MEM_DC_UGDE3_0__NF_NL_3 0x1F0405C4,0x18000000 ++#define LPM_MEM_DC_UGDE3_0__AUTORESTART_3 0x1F0405C4,0x04000000 ++#define LPM_MEM_DC_UGDE3_0__ODD_EN_3 0x1F0405C4,0x02000000 ++#define LPM_MEM_DC_UGDE3_0__COD_ODD_START_3 0x1F0405C4,0x00FF0000 ++#define LPM_MEM_DC_UGDE3_0__COD_EV_START_3 0x1F0405C4,0x00007F80 ++#define LPM_MEM_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1F0405C4,0x00000078 ++#define LPM_MEM_DC_UGDE3_0__ID_CODED_3 0x1F0405C4,0x00000007 ++ ++#define LPM_MEM_DC_UGDE3_1__ADDR 0x1F0405C8 ++#define LPM_MEM_DC_UGDE3_1__EMPTY 0x1F0405C8,0x00000000 ++#define LPM_MEM_DC_UGDE3_1__FULL 0x1F0405C8,0xffffffff ++#define LPM_MEM_DC_UGDE3_1__STEP_3 0x1F0405C8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_2__ADDR 0x1F0405CC ++#define LPM_MEM_DC_UGDE3_2__EMPTY 0x1F0405CC,0x00000000 ++#define LPM_MEM_DC_UGDE3_2__FULL 0x1F0405CC,0xffffffff ++#define LPM_MEM_DC_UGDE3_2__OFFSET_DT_3 0x1F0405CC,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_3__ADDR 0x1F0405D0 ++#define LPM_MEM_DC_UGDE3_3__EMPTY 0x1F0405D0,0x00000000 ++#define LPM_MEM_DC_UGDE3_3__FULL 0x1F0405D0,0xffffffff ++#define LPM_MEM_DC_UGDE3_3__STEP_REPEAT_3 0x1F0405D0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_LLA0__ADDR 0x1F0405D4 ++#define LPM_MEM_DC_LLA0__EMPTY 0x1F0405D4,0x00000000 ++#define LPM_MEM_DC_LLA0__FULL 0x1F0405D4,0xffffffff ++#define LPM_MEM_DC_LLA0__MCU_RS_3_0 0x1F0405D4,0xFF000000 ++#define LPM_MEM_DC_LLA0__MCU_RS_2_0 0x1F0405D4,0x00FF0000 ++#define LPM_MEM_DC_LLA0__MCU_RS_1_0 0x1F0405D4,0x0000FF00 ++#define LPM_MEM_DC_LLA0__MCU_RS_0_0 0x1F0405D4,0x000000FF ++ ++#define LPM_MEM_DC_LLA1__ADDR 0x1F0405D8 ++#define LPM_MEM_DC_LLA1__EMPTY 0x1F0405D8,0x00000000 ++#define LPM_MEM_DC_LLA1__FULL 0x1F0405D8,0xffffffff ++#define LPM_MEM_DC_LLA1__MCU_RS_3_1 0x1F0405D8,0xFF000000 ++#define LPM_MEM_DC_LLA1__MCU_RS_2_1 0x1F0405D8,0x00FF0000 ++#define LPM_MEM_DC_LLA1__MCU_RS_1_1 0x1F0405D8,0x0000FF00 ++#define LPM_MEM_DC_LLA1__MCU_RS_0_1 0x1F0405D8,0x000000FF ++ ++#define LPM_MEM_DC_R_LLA0__ADDR 0x1F0405DC ++#define LPM_MEM_DC_R_LLA0__EMPTY 0x1F0405DC,0x00000000 ++#define LPM_MEM_DC_R_LLA0__FULL 0x1F0405DC,0xffffffff ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_3_0 0x1F0405DC,0xFF000000 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_2_0 0x1F0405DC,0x00FF0000 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_1_0 0x1F0405DC,0x0000FF00 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_0_0 0x1F0405DC,0x000000FF ++ ++#define LPM_MEM_DC_R_LLA1__ADDR 0x1F0405E0 ++#define LPM_MEM_DC_R_LLA1__EMPTY 0x1F0405E0,0x00000000 ++#define LPM_MEM_DC_R_LLA1__FULL 0x1F0405E0,0xffffffff ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_3_1 0x1F0405E0,0xFF000000 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_2_1 0x1F0405E0,0x00FF0000 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_1_1 0x1F0405E0,0x0000FF00 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_0_1 0x1F0405E0,0x000000FF ++ ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ADDR 0x1F0405E4 ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__EMPTY 0x1F0405E4,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__FULL 0x1F0405E4,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1F0405E4,0x1FFFFFFF ++ ++#define LPM_MEM_IDMAC_CONF__ADDR 0x1F0405E8 ++#define LPM_MEM_IDMAC_CONF__EMPTY 0x1F0405E8,0x00000000 ++#define LPM_MEM_IDMAC_CONF__FULL 0x1F0405E8,0xffffffff ++#define LPM_MEM_IDMAC_CONF__P_ENDIAN 0x1F0405E8,0x00010000 ++#define LPM_MEM_IDMAC_CONF__WIDPT 0x1F0405E8,0x00000018 ++#define LPM_MEM_IDMAC_CONF__MAX_REQ_READ 0x1F0405E8,0x00000007 ++ ++#define LPM_MEM_IDMAC_CH_EN_1__ADDR 0x1F0405EC ++#define LPM_MEM_IDMAC_CH_EN_1__EMPTY 0x1F0405EC,0x00000000 ++#define LPM_MEM_IDMAC_CH_EN_1__FULL 0x1F0405EC,0xffffffff ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1F0405EC,0x80000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1F0405EC,0x20000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1F0405EC,0x10000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1F0405EC,0x08000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1F0405EC,0x01000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1F0405EC,0x00800000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1F0405EC,0x00400000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1F0405EC,0x00200000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1F0405EC,0x00100000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1F0405EC,0x00040000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1F0405EC,0x00020000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1F0405EC,0x00008000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1F0405EC,0x00004000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1F0405EC,0x00001000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1F0405EC,0x00000800 ++ ++#define LPM_MEM_IDMAC_CH_EN_2__ADDR 0x1F0405F0 ++#define LPM_MEM_IDMAC_CH_EN_2__EMPTY 0x1F0405F0,0x00000000 ++#define LPM_MEM_IDMAC_CH_EN_2__FULL 0x1F0405F0,0xffffffff ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1F0405F0,0x00100000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1F0405F0,0x00080000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1F0405F0,0x00040000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1F0405F0,0x00020000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1F0405F0,0x00010000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1F0405F0,0x00008000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1F0405F0,0x00004000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1F0405F0,0x00002000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1F0405F0,0x00001000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1F0405F0,0x00000800 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1F0405F0,0x00000400 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1F0405F0,0x00000200 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1F0405F0,0x00000100 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1F0405F0,0x00000002 ++ ++#define LPM_MEM_IDMAC_SEP_ALPHA__ADDR 0x1F0405F4 ++#define LPM_MEM_IDMAC_SEP_ALPHA__EMPTY 0x1F0405F4,0x00000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__FULL 0x1F0405F4,0xffffffff ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1F0405F4,0x20000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1F0405F4,0x08000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1F0405F4,0x01000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1F0405F4,0x00800000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1F0405F4,0x00008000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1F0405F4,0x00004000 ++ ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__ADDR 0x1F0405F8 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__EMPTY 0x1F0405F8,0x00000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__FULL 0x1F0405F8,0xffffffff ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1F0405F8,0x20000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1F0405F8,0x01000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1F0405F8,0x00800000 ++ ++#define LPM_MEM_IDMAC_CH_PRI_1__ADDR 0x1F0405FC ++#define LPM_MEM_IDMAC_CH_PRI_1__EMPTY 0x1F0405FC,0x00000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__FULL 0x1F0405FC,0xffffffff ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1F0405FC,0x20000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1F0405FC,0x10000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1F0405FC,0x08000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1F0405FC,0x01000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1F0405FC,0x00800000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1F0405FC,0x00400000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1F0405FC,0x00200000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1F0405FC,0x00100000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1F0405FC,0x00008000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1F0405FC,0x00004000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1F0405FC,0x00001000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1F0405FC,0x00000800 ++ ++#define LPM_MEM_IDMAC_CH_PRI_2__ADDR 0x1F040600 ++#define LPM_MEM_IDMAC_CH_PRI_2__EMPTY 0x1F040600,0x00000000 ++#define LPM_MEM_IDMAC_CH_PRI_2__FULL 0x1F040600,0xffffffff ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1F040600,0x00040000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1F040600,0x00020000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1F040600,0x00010000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1F040600,0x00008000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1F040600,0x00004000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1F040600,0x00002000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1F040600,0x00001000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1F040600,0x00000800 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1F040600,0x00000400 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1F040600,0x00000200 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1F040600,0x00000100 ++ ++#define LPM_MEM_IDMAC_WM_EN_1__ADDR 0x1F040604 ++#define LPM_MEM_IDMAC_WM_EN_1__EMPTY 0x1F040604,0x00000000 ++#define LPM_MEM_IDMAC_WM_EN_1__FULL 0x1F040604,0xffffffff ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1F040604,0x20000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1F040604,0x10000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1F040604,0x08000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1F040604,0x01000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1F040604,0x00800000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1F040604,0x00004000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1F040604,0x00001000 ++ ++#define LPM_MEM_IDMAC_WM_EN_2__ADDR 0x1F040608 ++#define LPM_MEM_IDMAC_WM_EN_2__EMPTY 0x1F040608,0x00000000 ++#define LPM_MEM_IDMAC_WM_EN_2__FULL 0x1F040608,0xffffffff ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1F040608,0x00001000 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1F040608,0x00000800 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1F040608,0x00000400 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1F040608,0x00000200 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1F040608,0x00000100 ++ ++#define LPM_MEM_IDMAC_LOCK_EN_2__ADDR 0x1F04060C ++#define LPM_MEM_IDMAC_LOCK_EN_2__EMPTY 0x1F04060C,0x00000000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__FULL 0x1F04060C,0xffffffff ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1F04060C,0x00040000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1F04060C,0x00020000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1F04060C,0x00010000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1F04060C,0x00008000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1F04060C,0x00004000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1F04060C,0x00002000 ++ ++#define LPM_MEM_IDMAC_SUB_ADDR_1__ADDR 0x1F040614 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__EMPTY 0x1F040614,0x00000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__FULL 0x1F040614,0xffffffff ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1F040614,0x7F000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1F040614,0x007F0000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1F040614,0x00007F00 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1F040614,0x0000007F ++ ++#define LPM_MEM_IDMAC_SUB_ADDR_2__ADDR 0x1F040618 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__EMPTY 0x1F040618,0x00000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__FULL 0x1F040618,0xffffffff ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1F040618,0x007F0000 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1F040618,0x00007F00 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1F040618,0x0000007F ++ ++#define LPM_MEM_IDMAC_BNDM_EN_1__ADDR 0x1F04061C ++#define LPM_MEM_IDMAC_BNDM_EN_1__EMPTY 0x1F04061C,0x00000000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__FULL 0x1F04061C,0xffffffff ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1F04061C,0x00400000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1F04061C,0x00200000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1F04061C,0x00100000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1F04061C,0x00001000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1F04061C,0x00000800 ++ ++#define LPM_MEM_IDMAC_BNDM_EN_2__ADDR 0x1F040620 ++#define LPM_MEM_IDMAC_BNDM_EN_2__EMPTY 0x1F040620,0x00000000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__FULL 0x1F040620,0xffffffff ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1F040620,0x00040000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1F040620,0x00020000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1F040620,0x00010000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1F040620,0x00008000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1F040620,0x00004000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1F040620,0x00002000 ++ ++#define LPM_MEM_IDMAC_SC_CORD__ADDR 0x1F040624 ++#define LPM_MEM_IDMAC_SC_CORD__EMPTY 0x1F040624,0x00000000 ++#define LPM_MEM_IDMAC_SC_CORD__FULL 0x1F040624,0xffffffff ++#define LPM_MEM_IDMAC_SC_CORD__SX0 0x1F040624,0x0FFF0000 ++#define LPM_MEM_IDMAC_SC_CORD__SY0 0x1F040624,0x000007FF ++ ++#define LPM_MEM_IPU_CONF__ADDR 0x1F040628 ++#define LPM_MEM_IPU_CONF__EMPTY 0x1F040628,0x00000000 ++#define LPM_MEM_IPU_CONF__FULL 0x1F040628,0xffffffff ++#define LPM_MEM_IPU_CONF__IC_DMFC_SYNC 0x1F040628,0x04000000 ++#define LPM_MEM_IPU_CONF__IC_DMFC_SEL 0x1F040628,0x02000000 ++#define LPM_MEM_IPU_CONF__IDMAC_DISABLE 0x1F040628,0x00400000 ++#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_ON 0x1F040628,0x00200000 ++#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_MODE 0x1F040628,0x001F0000 ++#define LPM_MEM_IPU_CONF__DMFC_EN 0x1F040628,0x00000400 ++#define LPM_MEM_IPU_CONF__DC_EN 0x1F040628,0x00000200 ++#define LPM_MEM_IPU_CONF__DI1_EN 0x1F040628,0x00000080 ++#define LPM_MEM_IPU_CONF__DI0_EN 0x1F040628,0x00000040 ++#define LPM_MEM_IPU_CONF__DP_EN 0x1F040628,0x00000020 ++#define LPM_MEM_IPU_CONF__IRT_EN 0x1F040628,0x00000008 ++#define LPM_MEM_IPU_CONF__IC_EN 0x1F040628,0x00000004 ++ ++#define LPM_MEM_IPU_INT_CTRL_1__ADDR 0x1F040664 ++#define LPM_MEM_IPU_INT_CTRL_1__EMPTY 0x1F040664,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_1__FULL 0x1F040664,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1F040664,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1F040664,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1F040664,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1F040664,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1F040664,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1F040664,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1F040664,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1F040664,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1F040664,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1F040664,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1F040664,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1F040664,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1F040664,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1F040664,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1F040664,0x00000800 ++ ++#define LPM_MEM_IPU_INT_CTRL_2__ADDR 0x1F040668 ++#define LPM_MEM_IPU_INT_CTRL_2__EMPTY 0x1F040668,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_2__FULL 0x1F040668,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1F040668,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1F040668,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1F040668,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1F040668,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1F040668,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1F040668,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1F040668,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1F040668,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1F040668,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1F040668,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1F040668,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1F040668,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1F040668,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1F040668,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_3__ADDR 0x1F04066C ++#define LPM_MEM_IPU_INT_CTRL_3__EMPTY 0x1F04066C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_3__FULL 0x1F04066C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1F04066C,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1F04066C,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1F04066C,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1F04066C,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1F04066C,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1F04066C,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1F04066C,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1F04066C,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1F04066C,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1F04066C,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1F04066C,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1F04066C,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1F04066C,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1F04066C,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1F04066C,0x00000800 ++ ++#define LPM_MEM_IPU_INT_CTRL_4__ADDR 0x1F040670 ++#define LPM_MEM_IPU_INT_CTRL_4__EMPTY 0x1F040670,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_4__FULL 0x1F040670,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1F040670,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1F040670,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1F040670,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1F040670,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1F040670,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1F040670,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1F040670,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1F040670,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1F040670,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1F040670,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1F040670,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1F040670,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1F040670,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1F040670,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_5__ADDR 0x1F040674 ++#define LPM_MEM_IPU_INT_CTRL_5__EMPTY 0x1F040674,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_5__FULL 0x1F040674,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1F040674,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1F040674,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1F040674,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1F040674,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1F040674,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1F040674,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1F040674,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1F040674,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1F040674,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1F040674,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1F040674,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1F040674,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1F040674,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1F040674,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1F040674,0x00000800 ++ ++#define LPM_MEM_IPU_INT_CTRL_6__ADDR 0x1F040678 ++#define LPM_MEM_IPU_INT_CTRL_6__EMPTY 0x1F040678,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_6__FULL 0x1F040678,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1F040678,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1F040678,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1F040678,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1F040678,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1F040678,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1F040678,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1F040678,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1F040678,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1F040678,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1F040678,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1F040678,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1F040678,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1F040678,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1F040678,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_7__ADDR 0x1F04067C ++#define LPM_MEM_IPU_INT_CTRL_7__EMPTY 0x1F04067C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_7__FULL 0x1F04067C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1F04067C,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1F04067C,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1F04067C,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1F04067C,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1F04067C,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1F04067C,0x00800000 ++ ++#define LPM_MEM_IPU_INT_CTRL_8__ADDR 0x1F040680 ++#define LPM_MEM_IPU_INT_CTRL_8__EMPTY 0x1F040680,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_8__FULL 0x1F040680,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1F040680,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1F040680,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1F040680,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1F040680,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1F040680,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1F040680,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1F040680,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_10__ADDR 0x1F040688 ++#define LPM_MEM_IPU_INT_CTRL_10__EMPTY 0x1F040688,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_10__FULL 0x1F040688,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_10__AXIR_ERR_EN 0x1F040688,0x40000000 ++#define LPM_MEM_IPU_INT_CTRL_10__AXIW_ERR_EN 0x1F040688,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1F040688,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN 0x1F040688,0x04000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN 0x1F040688,0x02000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN 0x1F040688,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN 0x1F040688,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN 0x1F040688,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN 0x1F040688,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN 0x1F040688,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN 0x1F040688,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN 0x1F040688,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN 0x1F040688,0x00010000 ++ ++#define LPM_MEM_IPU_INT_CTRL_11__ADDR 0x1F04068C ++#define LPM_MEM_IPU_INT_CTRL_11__EMPTY 0x1F04068C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_11__FULL 0x1F04068C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1F04068C,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1F04068C,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1F04068C,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1F04068C,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1F04068C,0x00000800 ++ ++#define LPM_MEM_IPU_INT_CTRL_12__ADDR 0x1F040690 ++#define LPM_MEM_IPU_INT_CTRL_12__EMPTY 0x1F040690,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_12__FULL 0x1F040690,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1F040690,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1F040690,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1F040690,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1F040690,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1F040690,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1F040690,0x00002000 ++ ++#define LPM_MEM_IPU_INT_CTRL_13__ADDR 0x1F040694 ++#define LPM_MEM_IPU_INT_CTRL_13__EMPTY 0x1F040694,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_13__FULL 0x1F040694,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1F040694,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1F040694,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1F040694,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1F040694,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1F040694,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1F040694,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1F040694,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1F040694,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1F040694,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1F040694,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1F040694,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1F040694,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1F040694,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1F040694,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1F040694,0x00000800 ++ ++#define LPM_MEM_IPU_INT_CTRL_14__ADDR 0x1F040698 ++#define LPM_MEM_IPU_INT_CTRL_14__EMPTY 0x1F040698,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_14__FULL 0x1F040698,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1F040698,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1F040698,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1F040698,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1F040698,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1F040698,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1F040698,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1F040698,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1F040698,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1F040698,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1F040698,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1F040698,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1F040698,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1F040698,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1F040698,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_15__ADDR 0x1F04069C ++#define LPM_MEM_IPU_INT_CTRL_15__EMPTY 0x1F04069C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_15__FULL 0x1F04069C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN 0x1F04069C,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN 0x1F04069C,0x40000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1F04069C,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN 0x1F04069C,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN 0x1F04069C,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN 0x1F04069C,0x04000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN 0x1F04069C,0x02000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN 0x1F04069C,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN 0x1F04069C,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN 0x1F04069C,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN 0x1F04069C,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN 0x1F04069C,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN 0x1F04069C,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1F04069C,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN 0x1F04069C,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_DP_START_EN 0x1F04069C,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN 0x1F04069C,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN 0x1F04069C,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_6_EN 0x1F04069C,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_4_EN 0x1F04069C,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_3_EN 0x1F04069C,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_2_EN 0x1F04069C,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_1_EN 0x1F04069C,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_0_EN 0x1F04069C,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN 0x1F04069C,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_BRAKE_EN 0x1F04069C,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_END_EN 0x1F04069C,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_START_EN 0x1F04069C,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_END_EN 0x1F04069C,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_START_EN 0x1F04069C,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN 0x1F04069C,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN 0x1F04069C,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_1__ADDR 0x1F0406A0 ++#define LPM_MEM_IPU_SDMA_EVENT_1__EMPTY 0x1F0406A0,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__FULL 0x1F0406A0,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1F0406A0,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1F0406A0,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1F0406A0,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1F0406A0,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1F0406A0,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1F0406A0,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1F0406A0,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1F0406A0,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1F0406A0,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1F0406A0,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1F0406A0,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1F0406A0,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1F0406A0,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1F0406A0,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1F0406A0,0x00000800 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_2__ADDR 0x1F0406A4 ++#define LPM_MEM_IPU_SDMA_EVENT_2__EMPTY 0x1F0406A4,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__FULL 0x1F0406A4,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1F0406A4,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1F0406A4,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1F0406A4,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1F0406A4,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1F0406A4,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1F0406A4,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1F0406A4,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1F0406A4,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1F0406A4,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1F0406A4,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1F0406A4,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1F0406A4,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1F0406A4,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1F0406A4,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_3__ADDR 0x1F0406A8 ++#define LPM_MEM_IPU_SDMA_EVENT_3__EMPTY 0x1F0406A8,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__FULL 0x1F0406A8,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1F0406A8,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1F0406A8,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1F0406A8,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1F0406A8,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1F0406A8,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1F0406A8,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1F0406A8,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1F0406A8,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1F0406A8,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1F0406A8,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1F0406A8,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1F0406A8,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1F0406A8,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1F0406A8,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1F0406A8,0x00000800 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_4__ADDR 0x1F0406AC ++#define LPM_MEM_IPU_SDMA_EVENT_4__EMPTY 0x1F0406AC,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__FULL 0x1F0406AC,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1F0406AC,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1F0406AC,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1F0406AC,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1F0406AC,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1F0406AC,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1F0406AC,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1F0406AC,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1F0406AC,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1F0406AC,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1F0406AC,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1F0406AC,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1F0406AC,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1F0406AC,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1F0406AC,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_7__ADDR 0x1F0406B0 ++#define LPM_MEM_IPU_SDMA_EVENT_7__EMPTY 0x1F0406B0,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__FULL 0x1F0406B0,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1F0406B0,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1F0406B0,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1F0406B0,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1F0406B0,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1F0406B0,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1F0406B0,0x00800000 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_8__ADDR 0x1F0406B4 ++#define LPM_MEM_IPU_SDMA_EVENT_8__EMPTY 0x1F0406B4,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__FULL 0x1F0406B4,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1F0406B4,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1F0406B4,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1F0406B4,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1F0406B4,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1F0406B4,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1F0406B4,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1F0406B4,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_11__ADDR 0x1F0406B8 ++#define LPM_MEM_IPU_SDMA_EVENT_11__EMPTY 0x1F0406B8,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__FULL 0x1F0406B8,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1F0406B8,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1F0406B8,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1F0406B8,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1F0406B8,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1F0406B8,0x00000800 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_12__ADDR 0x1F0406BC ++#define LPM_MEM_IPU_SDMA_EVENT_12__EMPTY 0x1F0406BC,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__FULL 0x1F0406BC,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1F0406BC,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1F0406BC,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1F0406BC,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1F0406BC,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1F0406BC,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1F0406BC,0x00002000 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_13__ADDR 0x1F0406C0 ++#define LPM_MEM_IPU_SDMA_EVENT_13__EMPTY 0x1F0406C0,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__FULL 0x1F0406C0,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1F0406C0,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1F0406C0,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1F0406C0,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1F0406C0,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1F0406C0,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1F0406C0,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1F0406C0,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1F0406C0,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1F0406C0,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1F0406C0,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1F0406C0,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1F0406C0,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1F0406C0,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1F0406C0,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1F0406C0,0x00000800 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_14__ADDR 0x1F0406C4 ++#define LPM_MEM_IPU_SDMA_EVENT_14__EMPTY 0x1F0406C4,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__FULL 0x1F0406C4,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1F0406C4,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1F0406C4,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1F0406C4,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1F0406C4,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1F0406C4,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1F0406C4,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1F0406C4,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1F0406C4,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1F0406C4,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1F0406C4,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1F0406C4,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1F0406C4,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1F0406C4,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1F0406C4,0x00000002 ++ ++#define LPM_MEM_IPU_SRM_PRI2__ADDR 0x1F0006CC ++#define LPM_MEM_IPU_SRM_PRI2__EMPTY 0x1F0006CC,0x00000000 ++#define LPM_MEM_IPU_SRM_PRI2__FULL 0x1F0006CC,0xffffffff ++#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_MODE 0x1F0006CC,0x18000000 ++#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_PRI 0x1F0006CC,0x07000000 ++#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_MODE 0x1F0006CC,0x00180000 ++#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_PRI 0x1F0006CC,0x00070000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_6_SRM_MODE 0x1F0006CC,0x0000C000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_2_SRM_MODE 0x1F0006CC,0x00003000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_SRM_PRI 0x1F0006CC,0x00000E00 ++#define LPM_MEM_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1F0006CC,0x00000180 ++#define LPM_MEM_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1F0006CC,0x00000060 ++#define LPM_MEM_IPU_SRM_PRI2__DP_S_SRM_MODE 0x1F0006CC,0x00000018 ++#define LPM_MEM_IPU_SRM_PRI2__DP_SRM_PRI 0x1F0006CC,0x00000007 ++ ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ADDR 0x1F0406D0 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__EMPTY 0x1F0406D0,0x00000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__FULL 0x1F0406D0,0xffffffff ++#define LPM_MEM_IPU_FS_PROC_FLOW1__VF_IN_VALID 0x1F0406D0,0x80000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ENC_IN_VALID 0x1F0406D0,0x40000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRP_SRC_SEL 0x1F0406D0,0x0F000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL 0x1F0406D0,0x000F0000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_SRC_SEL 0x1F0406D0,0x0000F000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL 0x1F0406D0,0x00000F00 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1F0406D0,0x0000000F ++ ++#define LPM_MEM_IPU_FS_PROC_FLOW2__ADDR 0x1F0406D4 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__EMPTY 0x1F0406D4,0x00000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__FULL 0x1F0406D4,0xffffffff ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1F0406D4,0x00F00000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL 0x1F0406D4,0x000F0000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_DEST_SEL 0x1F0406D4,0x0000F000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL 0x1F0406D4,0x00000F00 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL 0x1F0406D4,0x000000F0 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL 0x1F0406D4,0x0000000F ++ ++#define LPM_MEM_IPU_FS_DISP_FLOW1__ADDR 0x1F0406DC ++#define LPM_MEM_IPU_FS_DISP_FLOW1__EMPTY 0x1F0406DC,0x00000000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__FULL 0x1F0406DC,0xffffffff ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DC1_SRC_SEL 0x1F0406DC,0x00F00000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DC2_SRC_SEL 0x1F0406DC,0x000F0000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1F0406DC,0x0000F000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1F0406DC,0x00000F00 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL 0x1F0406DC,0x000000F0 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL 0x1F0406DC,0x0000000F ++ ++#define LPM_MEM_IPU_FS_DISP_FLOW2__ADDR 0x1F0406E0 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__EMPTY 0x1F0406E0,0x00000000 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__FULL 0x1F0406E0,0xffffffff ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL 0x1F0406E0,0x000F0000 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1F0406E0,0x000000F0 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1F0406E0,0x0000000F ++ ++#define LPM_MEM_IPU_DISP_GEN__ADDR 0x1F0406EC ++#define LPM_MEM_IPU_DISP_GEN__EMPTY 0x1F0406EC,0x00000000 ++#define LPM_MEM_IPU_DISP_GEN__FULL 0x1F0406EC,0xffffffff ++#define LPM_MEM_IPU_DISP_GEN__DI1_COUNTER_RELEASE 0x1F0406EC,0x02000000 ++#define LPM_MEM_IPU_DISP_GEN__DI0_COUNTER_RELEASE 0x1F0406EC,0x01000000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_MAX_BURST_STOP 0x1F0406EC,0x00400000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_T 0x1F0406EC,0x003C0000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_9 0x1F0406EC,0x00020000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_8 0x1F0406EC,0x00010000 ++#define LPM_MEM_IPU_DISP_GEN__DP_PIPE_CLR 0x1F0406EC,0x00000040 ++#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC1 0x1F0406EC,0x00000020 ++#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC0 0x1F0406EC,0x00000010 ++#define LPM_MEM_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1F0406EC,0x00000008 ++#define LPM_MEM_IPU_DISP_GEN__DC2_DOUBLE_FLOW 0x1F0406EC,0x00000004 ++#define LPM_MEM_IPU_DISP_GEN__DI1_DUAL_MODE 0x1F0406EC,0x00000002 ++#define LPM_MEM_IPU_DISP_GEN__DI0_DUAL_MODE 0x1F0406EC,0x00000001 ++ ++#define LPM_MEM_IPU_DISP_ALT1__ADDR 0x1F0406F0 ++#define LPM_MEM_IPU_DISP_ALT1__EMPTY 0x1F0406F0,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT1__FULL 0x1F0406F0,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT1__SEL_ALT_0 0x1F0406F0,0xF0000000 ++#define LPM_MEM_IPU_DISP_ALT1__STEP_REPEAT_ALT_0 0x1F0406F0,0x0FFF0000 ++#define LPM_MEM_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1F0406F0,0x00008000 ++#define LPM_MEM_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0 0x1F0406F0,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0 0x1F0406F0,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT2__ADDR 0x1F0406F4 ++#define LPM_MEM_IPU_DISP_ALT2__EMPTY 0x1F0406F4,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT2__FULL 0x1F0406F4,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0 0x1F0406F4,0x00070000 ++#define LPM_MEM_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1F0406F4,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0 0x1F0406F4,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT3__ADDR 0x1F0406F8 ++#define LPM_MEM_IPU_DISP_ALT3__EMPTY 0x1F0406F8,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT3__FULL 0x1F0406F8,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT3__SEL_ALT_1 0x1F0406F8,0xF0000000 ++#define LPM_MEM_IPU_DISP_ALT3__STEP_REPEAT_ALT_1 0x1F0406F8,0x0FFF0000 ++#define LPM_MEM_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1F0406F8,0x00008000 ++#define LPM_MEM_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1 0x1F0406F8,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1 0x1F0406F8,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT4__ADDR 0x1F0406FC ++#define LPM_MEM_IPU_DISP_ALT4__EMPTY 0x1F0406FC,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT4__FULL 0x1F0406FC,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1 0x1F0406FC,0x00070000 ++#define LPM_MEM_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1F0406FC,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1 0x1F0406FC,0x00000FFF ++ ++#define LPM_MEM_IPU_SNOOP__ADDR 0x1F040700 ++#define LPM_MEM_IPU_SNOOP__EMPTY 0x1F040700,0x00000000 ++#define LPM_MEM_IPU_SNOOP__FULL 0x1F040700,0xffffffff ++#define LPM_MEM_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1F040700,0x00010000 ++#define LPM_MEM_IPU_SNOOP__AUTOREF_PER 0x1F040700,0x000003FF ++ ++#define LPM_MEM_IPU_MEM_RST__ADDR 0x1F040704 ++#define LPM_MEM_IPU_MEM_RST__EMPTY 0x1F040704,0x00000000 ++#define LPM_MEM_IPU_MEM_RST__FULL 0x1F040704,0xffffffff ++#define LPM_MEM_IPU_MEM_RST__RST_MEM_START 0x1F040704,0x80000000 ++#define LPM_MEM_IPU_MEM_RST__RST_MEM_EN 0x1F040704,0x007FFFFF ++ ++#define LPM_MEM_IPU_PM__ADDR 0x1F040708 ++#define LPM_MEM_IPU_PM__EMPTY 0x1F040708,0x00000000 ++#define LPM_MEM_IPU_PM__FULL 0x1F040708,0xffffffff ++#define LPM_MEM_IPU_PM__LPSR_MODE 0x1F040708,0x80000000 ++#define LPM_MEM_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1F040708,0x40000000 ++#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_1 0x1F040708,0x3F800000 ++#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_0 0x1F040708,0x007F0000 ++#define LPM_MEM_IPU_PM__CLOCK_MODE_STAT 0x1F040708,0x00008000 ++#define LPM_MEM_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1F040708,0x00004000 ++#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_1 0x1F040708,0x00003F80 ++#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_0 0x1F040708,0x0000007F ++ ++#define LPM_MEM_IPU_GPR__ADDR 0x1F04070C ++#define LPM_MEM_IPU_GPR__EMPTY 0x1F04070C,0x00000000 ++#define LPM_MEM_IPU_GPR__FULL 0x1F04070C,0xffffffff ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY1_CLR 0x1F04070C,0x80000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY0_CLR 0x1F04070C,0x40000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY1_CLR 0x1F04070C,0x20000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY0_CLR 0x1F04070C,0x10000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1F04070C,0x08000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1F04070C,0x04000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1F04070C,0x02000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1F04070C,0x01000000 ++#define LPM_MEM_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1F04070C,0x00800000 ++#define LPM_MEM_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1F04070C,0x00400000 ++#define LPM_MEM_IPU_GPR__IPU_GP21 0x1F04070C,0x00200000 ++#define LPM_MEM_IPU_GPR__IPU_GP20 0x1F04070C,0x00100000 ++#define LPM_MEM_IPU_GPR__IPU_GP19 0x1F04070C,0x00080000 ++#define LPM_MEM_IPU_GPR__IPU_GP18 0x1F04070C,0x00040000 ++#define LPM_MEM_IPU_GPR__IPU_GP17 0x1F04070C,0x00020000 ++#define LPM_MEM_IPU_GPR__IPU_GP16 0x1F04070C,0x00010000 ++#define LPM_MEM_IPU_GPR__IPU_GP15 0x1F04070C,0x00008000 ++#define LPM_MEM_IPU_GPR__IPU_GP14 0x1F04070C,0x00004000 ++#define LPM_MEM_IPU_GPR__IPU_GP13 0x1F04070C,0x00002000 ++#define LPM_MEM_IPU_GPR__IPU_GP12 0x1F04070C,0x00001000 ++#define LPM_MEM_IPU_GPR__IPU_GP11 0x1F04070C,0x00000800 ++#define LPM_MEM_IPU_GPR__IPU_GP10 0x1F04070C,0x00000400 ++#define LPM_MEM_IPU_GPR__IPU_GP9 0x1F04070C,0x00000200 ++#define LPM_MEM_IPU_GPR__IPU_GP8 0x1F04070C,0x00000100 ++#define LPM_MEM_IPU_GPR__IPU_GP7 0x1F04070C,0x00000080 ++#define LPM_MEM_IPU_GPR__IPU_GP6 0x1F04070C,0x00000040 ++#define LPM_MEM_IPU_GPR__IPU_GP5 0x1F04070C,0x00000020 ++#define LPM_MEM_IPU_GPR__IPU_GP4 0x1F04070C,0x00000010 ++#define LPM_MEM_IPU_GPR__IPU_GP3 0x1F04070C,0x00000008 ++#define LPM_MEM_IPU_GPR__IPU_GP2 0x1F04070C,0x00000004 ++#define LPM_MEM_IPU_GPR__IPU_GP1 0x1F04070C,0x00000002 ++#define LPM_MEM_IPU_GPR__IPU_GP0 0x1F04070C,0x00000001 ++ ++#define LPM_MEM_IC_CONF__ADDR 0x1F040710 ++#define LPM_MEM_IC_CONF__EMPTY 0x1F040710,0x00000000 ++#define LPM_MEM_IC_CONF__FULL 0x1F040710,0xffffffff ++#define LPM_MEM_IC_CONF__CSI_MEM_WR_EN 0x1F040710,0x80000000 ++#define LPM_MEM_IC_CONF__RWS_EN 0x1F040710,0x40000000 ++#define LPM_MEM_IC_CONF__IC_KEY_COLOR_EN 0x1F040710,0x20000000 ++#define LPM_MEM_IC_CONF__IC_GLB_LOC_A 0x1F040710,0x10000000 ++#define LPM_MEM_IC_CONF__PP_ROT_EN 0x1F040710,0x00100000 ++#define LPM_MEM_IC_CONF__PP_CMB 0x1F040710,0x00080000 ++#define LPM_MEM_IC_CONF__PP_CSC2 0x1F040710,0x00040000 ++#define LPM_MEM_IC_CONF__PP_CSC1 0x1F040710,0x00020000 ++#define LPM_MEM_IC_CONF__PP_EN 0x1F040710,0x00010000 ++#define LPM_MEM_IC_CONF__PRPVF_ROT_EN 0x1F040710,0x00001000 ++#define LPM_MEM_IC_CONF__PRPVF_CMB 0x1F040710,0x00000800 ++#define LPM_MEM_IC_CONF__PRPVF_CSC2 0x1F040710,0x00000400 ++#define LPM_MEM_IC_CONF__PRPVF_CSC1 0x1F040710,0x00000200 ++#define LPM_MEM_IC_CONF__PRPVF_EN 0x1F040710,0x00000100 ++#define LPM_MEM_IC_CONF__PRPENC_ROT_EN 0x1F040710,0x00000004 ++#define LPM_MEM_IC_CONF__PRPENC_CSC1 0x1F040710,0x00000002 ++#define LPM_MEM_IC_CONF__PRPENC_EN 0x1F040710,0x00000001 ++ ++#define LPM_MEM_IC_PRP_ENC_RSC__ADDR 0x1F040714 ++#define LPM_MEM_IC_PRP_ENC_RSC__EMPTY 0x1F040714,0x00000000 ++#define LPM_MEM_IC_PRP_ENC_RSC__FULL 0x1F040714,0xffffffff ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1F040714,0xC0000000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1F040714,0x3FFF0000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1F040714,0x0000C000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1F040714,0x00003FFF ++ ++#define LPM_MEM_IC_PRP_VF_RSC__ADDR 0x1F040718 ++#define LPM_MEM_IC_PRP_VF_RSC__EMPTY 0x1F040718,0x00000000 ++#define LPM_MEM_IC_PRP_VF_RSC__FULL 0x1F040718,0xffffffff ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1F040718,0xC0000000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1F040718,0x3FFF0000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1F040718,0x0000C000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1F040718,0x00003FFF ++ ++#define LPM_MEM_IC_PP_RSC__ADDR 0x1F04071C ++#define LPM_MEM_IC_PP_RSC__EMPTY 0x1F04071C,0x00000000 ++#define LPM_MEM_IC_PP_RSC__FULL 0x1F04071C,0xffffffff ++#define LPM_MEM_IC_PP_RSC__PP_DS_R_V 0x1F04071C,0xC0000000 ++#define LPM_MEM_IC_PP_RSC__PP_RS_R_V 0x1F04071C,0x3FFF0000 ++#define LPM_MEM_IC_PP_RSC__PP_DS_R_H 0x1F04071C,0x0000C000 ++#define LPM_MEM_IC_PP_RSC__PP_RS_R_H 0x1F04071C,0x00003FFF ++ ++#define LPM_MEM_IC_CMBP_1__ADDR 0x1F040720 ++#define LPM_MEM_IC_CMBP_1__EMPTY 0x1F040720,0x00000000 ++#define LPM_MEM_IC_CMBP_1__FULL 0x1F040720,0xffffffff ++#define LPM_MEM_IC_CMBP_1__IC_PP_ALPHA_V 0x1F040720,0x0000FF00 ++#define LPM_MEM_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1F040720,0x000000FF ++ ++#define LPM_MEM_IC_CMBP_2__ADDR 0x1F040724 ++#define LPM_MEM_IC_CMBP_2__EMPTY 0x1F040724,0x00000000 ++#define LPM_MEM_IC_CMBP_2__FULL 0x1F040724,0xffffffff ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_R 0x1F040724,0x00FF0000 ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_G 0x1F040724,0x0000FF00 ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_B 0x1F040724,0x000000FF ++ ++#define LPM_MEM_IC_IDMAC_1__ADDR 0x1F040728 ++#define LPM_MEM_IC_IDMAC_1__EMPTY 0x1F040728,0x00000000 ++#define LPM_MEM_IC_IDMAC_1__FULL 0x1F040728,0xffffffff ++#define LPM_MEM_IC_IDMAC_1__ALT_CB7_BURST_16 0x1F040728,0x02000000 ++#define LPM_MEM_IC_IDMAC_1__ALT_CB6_BURST_16 0x1F040728,0x01000000 ++#define LPM_MEM_IC_IDMAC_1__T3_FLIP_UD 0x1F040728,0x00080000 ++#define LPM_MEM_IC_IDMAC_1__T3_FLIP_LR 0x1F040728,0x00040000 ++#define LPM_MEM_IC_IDMAC_1__T3_ROT 0x1F040728,0x00020000 ++#define LPM_MEM_IC_IDMAC_1__T2_FLIP_UD 0x1F040728,0x00010000 ++#define LPM_MEM_IC_IDMAC_1__T2_FLIP_LR 0x1F040728,0x00008000 ++#define LPM_MEM_IC_IDMAC_1__T2_ROT 0x1F040728,0x00004000 ++#define LPM_MEM_IC_IDMAC_1__T1_FLIP_UD 0x1F040728,0x00002000 ++#define LPM_MEM_IC_IDMAC_1__T1_FLIP_LR 0x1F040728,0x00001000 ++#define LPM_MEM_IC_IDMAC_1__T1_ROT 0x1F040728,0x00000800 ++#define LPM_MEM_IC_IDMAC_1__CB7_BURST_16 0x1F040728,0x00000080 ++#define LPM_MEM_IC_IDMAC_1__CB6_BURST_16 0x1F040728,0x00000040 ++#define LPM_MEM_IC_IDMAC_1__CB5_BURST_16 0x1F040728,0x00000020 ++#define LPM_MEM_IC_IDMAC_1__CB4_BURST_16 0x1F040728,0x00000010 ++#define LPM_MEM_IC_IDMAC_1__CB3_BURST_16 0x1F040728,0x00000008 ++#define LPM_MEM_IC_IDMAC_1__CB2_BURST_16 0x1F040728,0x00000004 ++#define LPM_MEM_IC_IDMAC_1__CB1_BURST_16 0x1F040728,0x00000002 ++#define LPM_MEM_IC_IDMAC_1__CB0_BURST_16 0x1F040728,0x00000001 ++ ++#define LPM_MEM_IC_IDMAC_2__ADDR 0x1F04072C ++#define LPM_MEM_IC_IDMAC_2__EMPTY 0x1F04072C,0x00000000 ++#define LPM_MEM_IC_IDMAC_2__FULL 0x1F04072C,0xffffffff ++#define LPM_MEM_IC_IDMAC_2__T3_FR_HEIGHT 0x1F04072C,0x3FF00000 ++#define LPM_MEM_IC_IDMAC_2__T2_FR_HEIGHT 0x1F04072C,0x000FFC00 ++#define LPM_MEM_IC_IDMAC_2__T1_FR_HEIGHT 0x1F04072C,0x000003FF ++ ++#define LPM_MEM_IC_IDMAC_3__ADDR 0x1F040730 ++#define LPM_MEM_IC_IDMAC_3__EMPTY 0x1F040730,0x00000000 ++#define LPM_MEM_IC_IDMAC_3__FULL 0x1F040730,0xffffffff ++#define LPM_MEM_IC_IDMAC_3__T3_FR_WIDTH 0x1F040730,0x3FF00000 ++#define LPM_MEM_IC_IDMAC_3__T2_FR_WIDTH 0x1F040730,0x000FFC00 ++#define LPM_MEM_IC_IDMAC_3__T1_FR_WIDTH 0x1F040730,0x000003FF ++ ++#define LPM_MEM_IC_IDMAC_4__ADDR 0x1F040734 ++#define LPM_MEM_IC_IDMAC_4__EMPTY 0x1F040734,0x00000000 ++#define LPM_MEM_IC_IDMAC_4__FULL 0x1F040734,0xffffffff ++#define LPM_MEM_IC_IDMAC_4__RM_BRDG_MAX_RQ 0x1F040734,0x0000F000 ++#define LPM_MEM_IC_IDMAC_4__IBM_BRDG_MAX_RQ 0x1F040734,0x00000F00 ++#define LPM_MEM_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1F040734,0x000000F0 ++#define LPM_MEM_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ 0x1F040734,0x0000000F ++ ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipuv3ex_reg_def.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipuv3ex_reg_def.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/ipuv3ex_reg_def.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/ipuv3ex_reg_def.h 2010-01-26 17:33:13.812964635 +0000 +@@ -0,0 +1,14005 @@ ++//========================================================================== ++// ++// IPUV3ex_REG_DEF.h ++// ++// regs definitions of IPUv3ex ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#ifndef _IPUV3E_REGS_DEF_H_ ++#define _IPUV3E_REGS_DEF_H_ ++ ++// ================= Start of IPUV3EX Common Registers ===================== ++ ++#define IPU_IPU_CONF__ADDR 0x1E000000 ++#define IPU_IPU_CONF__EMPTY 0x1E000000,0x00000000 ++#define IPU_IPU_CONF__FULL 0x1E000000,0xffffffff ++#define IPU_IPU_CONF__CSI_SEL 0x1E000000,0x80000000 ++#define IPU_IPU_CONF__IC_INPUT 0x1E000000,0x40000000 ++#define IPU_IPU_CONF__CSI1_DATA_SOURCE 0x1E000000,0x20000000 ++#define IPU_IPU_CONF__CSI0_DATA_SOURCE 0x1E000000,0x10000000 ++#define IPU_IPU_CONF__IC_DMFC_SYNC 0x1E000000,0x04000000 ++#define IPU_IPU_CONF__IC_DMFC_SEL 0x1E000000,0x02000000 ++#define IPU_IPU_CONF__ISP_DOUBLE_FLOW 0x1E000000,0x01000000 ++#define IPU_IPU_CONF__IDMAC_DISABLE 0x1E000000,0x00400000 ++#define IPU_IPU_CONF__IPU_DIAGBUS_ON 0x1E000000,0x00200000 ++#define IPU_IPU_CONF__IPU_DIAGBUS_MODE 0x1E000000,0x001F0000 ++#define IPU_IPU_CONF__IPU_HSP_CLK_EN 0x1E000000,0x00008000 ++#define IPU_IPU_CONF__SISG_EN 0x1E000000,0x00000800 ++#define IPU_IPU_CONF__DMFC_EN 0x1E000000,0x00000400 ++#define IPU_IPU_CONF__DC_EN 0x1E000000,0x00000200 ++#define IPU_IPU_CONF__SMFC_EN 0x1E000000,0x00000100 ++#define IPU_IPU_CONF__DI1_EN 0x1E000000,0x00000080 ++#define IPU_IPU_CONF__DI0_EN 0x1E000000,0x00000040 ++#define IPU_IPU_CONF__DP_EN 0x1E000000,0x00000020 ++#define IPU_IPU_CONF__ISP_EN 0x1E000000,0x00000010 ++#define IPU_IPU_CONF__IRT_EN 0x1E000000,0x00000008 ++#define IPU_IPU_CONF__IC_EN 0x1E000000,0x00000004 ++#define IPU_IPU_CONF__CSI1_EN 0x1E000000,0x00000002 ++#define IPU_IPU_CONF__CSI0_EN 0x1E000000,0x00000001 ++ ++#define IPU_SISG_CTRL0__ADDR 0x1E000004 ++#define IPU_SISG_CTRL0__EMPTY 0x1E000004,0x00000000 ++#define IPU_SISG_CTRL0__FULL 0x1E000004,0xffffffff ++#define IPU_SISG_CTRL0__EXT_ACTV 0x1E000004,0x40000000 ++#define IPU_SISG_CTRL0__MCU_ACTV_TRIG 0x1E000004,0x20000000 ++#define IPU_SISG_CTRL0__VAL_STOP_SISG_COUNTER 0x1E000004,0x1FFFFFF0 ++#define IPU_SISG_CTRL0__NO_OF_VSYNC 0x1E000004,0x0000000E ++#define IPU_SISG_CTRL0__VSYNC_RESET_COUNTER 0x1E000004,0x00000001 ++ ++#define IPU_SISG_CTRL1__ADDR 0x1E000008 ++#define IPU_SISG_CTRL1__EMPTY 0x1E000008,0x00000000 ++#define IPU_SISG_CTRL1__FULL 0x1E000008,0xffffffff ++#define IPU_SISG_CTRL1__SISG_OUT_POL 0x1E000008,0x00003F00 ++#define IPU_SISG_CTRL1__SISG_STROBE_CNT 0x1E000008,0x0000001F ++ ++#define IPU_SISG_SET_1__ADDR 0x1E00000C ++#define IPU_SISG_SET_1__EMPTY 0x1E00000C,0x00000000 ++#define IPU_SISG_SET_1__FULL 0x1E00000C,0xffffffff ++#define IPU_SISG_SET_1__SISG_SET_1 0x1E00000C,0x01FFFFFF ++ ++#define IPU_SISG_SET_2__ADDR 0x1E000010 ++#define IPU_SISG_SET_2__EMPTY 0x1E000010,0x00000000 ++#define IPU_SISG_SET_2__FULL 0x1E000010,0xffffffff ++#define IPU_SISG_SET_2__SISG_SET_2 0x1E000010,0x01FFFFFF ++ ++#define IPU_SISG_SET_3__ADDR 0x1E000014 ++#define IPU_SISG_SET_3__EMPTY 0x1E000014,0x00000000 ++#define IPU_SISG_SET_3__FULL 0x1E000014,0xffffffff ++#define IPU_SISG_SET_3__SISG_SET_3 0x1E000014,0x01FFFFFF ++ ++#define IPU_SISG_SET_4__ADDR 0x1E000018 ++#define IPU_SISG_SET_4__EMPTY 0x1E000018,0x00000000 ++#define IPU_SISG_SET_4__FULL 0x1E000018,0xffffffff ++#define IPU_SISG_SET_4__SISG_SET_4 0x1E000018,0x01FFFFFF ++ ++#define IPU_SISG_SET_5__ADDR 0x1E00001C ++#define IPU_SISG_SET_5__EMPTY 0x1E00001C,0x00000000 ++#define IPU_SISG_SET_5__FULL 0x1E00001C,0xffffffff ++#define IPU_SISG_SET_5__SISG_SET_5 0x1E00001C,0x01FFFFFF ++ ++#define IPU_SISG_SET_6__ADDR 0x1E000020 ++#define IPU_SISG_SET_6__EMPTY 0x1E000020,0x00000000 ++#define IPU_SISG_SET_6__FULL 0x1E000020,0xffffffff ++#define IPU_SISG_SET_6__SISG_SET_6 0x1E000020,0x01FFFFFF ++ ++#define IPU_SISG_CLR_1__ADDR 0x1E000024 ++#define IPU_SISG_CLR_1__EMPTY 0x1E000024,0x00000000 ++#define IPU_SISG_CLR_1__FULL 0x1E000024,0xffffffff ++#define IPU_SISG_CLR_1__SISG_CLEAR_1 0x1E000024,0x01FFFFFF ++ ++#define IPU_SISG_CLR_2__ADDR 0x1E000028 ++#define IPU_SISG_CLR_2__EMPTY 0x1E000028,0x00000000 ++#define IPU_SISG_CLR_2__FULL 0x1E000028,0xffffffff ++#define IPU_SISG_CLR_2__SISG_CLEAR_2 0x1E000028,0x01FFFFFF ++ ++#define IPU_SISG_CLR_3__ADDR 0x1E00002C ++#define IPU_SISG_CLR_3__EMPTY 0x1E00002C,0x00000000 ++#define IPU_SISG_CLR_3__FULL 0x1E00002C,0xffffffff ++#define IPU_SISG_CLR_3__SISG_CLEAR_3 0x1E00002C,0x01FFFFFF ++ ++#define IPU_SISG_CLR_4__ADDR 0x1E000030 ++#define IPU_SISG_CLR_4__EMPTY 0x1E000030,0x00000000 ++#define IPU_SISG_CLR_4__FULL 0x1E000030,0xffffffff ++#define IPU_SISG_CLR_4__SISG_CLEAR_4 0x1E000030,0x01FFFFFF ++ ++#define IPU_SISG_CLR_5__ADDR 0x1E000034 ++#define IPU_SISG_CLR_5__EMPTY 0x1E000034,0x00000000 ++#define IPU_SISG_CLR_5__FULL 0x1E000034,0xffffffff ++#define IPU_SISG_CLR_5__SISG_CLEAR_5 0x1E000034,0x01FFFFFF ++ ++#define IPU_SISG_CLR_6__ADDR 0x1E000038 ++#define IPU_SISG_CLR_6__EMPTY 0x1E000038,0x00000000 ++#define IPU_SISG_CLR_6__FULL 0x1E000038,0xffffffff ++#define IPU_SISG_CLR_6__SISG_CLEAR_6 0x1E000038,0x01FFFFFF ++ ++#define IPU_IPU_INT_CTRL_1__ADDR 0x1E00003C ++#define IPU_IPU_INT_CTRL_1__EMPTY 0x1E00003C,0x00000000 ++#define IPU_IPU_INT_CTRL_1__FULL 0x1E00003C,0xffffffff ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1E00003C,0x80000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1E00003C,0x20000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1E00003C,0x10000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1E00003C,0x08000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1E00003C,0x01000000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1E00003C,0x00800000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1E00003C,0x00400000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1E00003C,0x00200000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1E00003C,0x00100000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1E00003C,0x00040000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1E00003C,0x00020000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1E00003C,0x00008000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1E00003C,0x00004000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1E00003C,0x00001000 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1E00003C,0x00000800 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_7 0x1E00003C,0x00000080 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_6 0x1E00003C,0x00000040 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_5 0x1E00003C,0x00000020 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_4 0x1E00003C,0x00000010 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_3 0x1E00003C,0x00000008 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_2 0x1E00003C,0x00000004 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_1 0x1E00003C,0x00000002 ++#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_0 0x1E00003C,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_2__ADDR 0x1E000040 ++#define IPU_IPU_INT_CTRL_2__EMPTY 0x1E000040,0x00000000 ++#define IPU_IPU_INT_CTRL_2__FULL 0x1E000040,0xffffffff ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1E000040,0x00100000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1E000040,0x00080000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1E000040,0x00040000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1E000040,0x00020000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1E000040,0x00010000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1E000040,0x00008000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1E000040,0x00004000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1E000040,0x00002000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1E000040,0x00001000 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1E000040,0x00000800 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1E000040,0x00000400 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1E000040,0x00000200 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1E000040,0x00000100 ++#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1E000040,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_3__ADDR 0x1E000044 ++#define IPU_IPU_INT_CTRL_3__EMPTY 0x1E000044,0x00000000 ++#define IPU_IPU_INT_CTRL_3__FULL 0x1E000044,0xffffffff ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1E000044,0x80000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1E000044,0x20000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1E000044,0x10000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1E000044,0x08000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1E000044,0x01000000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1E000044,0x00800000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1E000044,0x00400000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1E000044,0x00200000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1E000044,0x00100000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1E000044,0x00040000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1E000044,0x00020000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1E000044,0x00008000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1E000044,0x00004000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1E000044,0x00001000 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1E000044,0x00000800 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7 0x1E000044,0x00000080 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6 0x1E000044,0x00000040 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5 0x1E000044,0x00000020 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4 0x1E000044,0x00000010 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3 0x1E000044,0x00000008 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2 0x1E000044,0x00000004 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1 0x1E000044,0x00000002 ++#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0 0x1E000044,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_4__ADDR 0x1E000048 ++#define IPU_IPU_INT_CTRL_4__EMPTY 0x1E000048,0x00000000 ++#define IPU_IPU_INT_CTRL_4__FULL 0x1E000048,0xffffffff ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1E000048,0x00100000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1E000048,0x00080000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1E000048,0x00040000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1E000048,0x00020000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1E000048,0x00010000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1E000048,0x00008000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1E000048,0x00004000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1E000048,0x00002000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1E000048,0x00001000 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1E000048,0x00000800 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1E000048,0x00000400 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1E000048,0x00000200 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1E000048,0x00000100 ++#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1E000048,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_5__ADDR 0x1E00004C ++#define IPU_IPU_INT_CTRL_5__EMPTY 0x1E00004C,0x00000000 ++#define IPU_IPU_INT_CTRL_5__FULL 0x1E00004C,0xffffffff ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1E00004C,0x80000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1E00004C,0x20000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1E00004C,0x10000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1E00004C,0x08000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1E00004C,0x01000000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1E00004C,0x00800000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1E00004C,0x00400000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1E00004C,0x00200000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1E00004C,0x00100000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1E00004C,0x00040000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1E00004C,0x00020000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1E00004C,0x00008000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1E00004C,0x00004000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1E00004C,0x00001000 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1E00004C,0x00000800 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7 0x1E00004C,0x00000080 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6 0x1E00004C,0x00000040 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5 0x1E00004C,0x00000020 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4 0x1E00004C,0x00000010 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3 0x1E00004C,0x00000008 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2 0x1E00004C,0x00000004 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1 0x1E00004C,0x00000002 ++#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0 0x1E00004C,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_6__ADDR 0x1E000050 ++#define IPU_IPU_INT_CTRL_6__EMPTY 0x1E000050,0x00000000 ++#define IPU_IPU_INT_CTRL_6__FULL 0x1E000050,0xffffffff ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1E000050,0x00100000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1E000050,0x00080000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1E000050,0x00040000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1E000050,0x00020000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1E000050,0x00010000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1E000050,0x00008000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1E000050,0x00004000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1E000050,0x00002000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1E000050,0x00001000 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1E000050,0x00000800 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1E000050,0x00000400 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1E000050,0x00000200 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1E000050,0x00000100 ++#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1E000050,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_7__ADDR 0x1E000054 ++#define IPU_IPU_INT_CTRL_7__EMPTY 0x1E000054,0x00000000 ++#define IPU_IPU_INT_CTRL_7__FULL 0x1E000054,0xffffffff ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1E000054,0x80000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1E000054,0x20000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1E000054,0x10000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1E000054,0x08000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1E000054,0x01000000 ++#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1E000054,0x00800000 ++ ++#define IPU_IPU_INT_CTRL_8__ADDR 0x1E000058 ++#define IPU_IPU_INT_CTRL_8__EMPTY 0x1E000058,0x00000000 ++#define IPU_IPU_INT_CTRL_8__FULL 0x1E000058,0xffffffff ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1E000058,0x00100000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1E000058,0x00080000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1E000058,0x00001000 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1E000058,0x00000800 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1E000058,0x00000400 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1E000058,0x00000200 ++#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1E000058,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_9__ADDR 0x1E00005C ++#define IPU_IPU_INT_CTRL_9__EMPTY 0x1E00005C,0x00000000 ++#define IPU_IPU_INT_CTRL_9__FULL 0x1E00005C,0xffffffff ++#define IPU_IPU_INT_CTRL_9__CSI1_PUPE_EN 0x1E00005C,0x80000000 ++#define IPU_IPU_INT_CTRL_9__CSI0_PUPE_EN 0x1E00005C,0x40000000 ++#define IPU_IPU_INT_CTRL_9__ISP_PUPE_EN 0x1E00005C,0x20000000 ++#define IPU_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN 0x1E00005C,0x10000000 ++#define IPU_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN 0x1E00005C,0x08000000 ++#define IPU_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN 0x1E00005C,0x04000000 ++ ++#define IPU_IPU_INT_CTRL_10__ADDR 0x1E000060 ++#define IPU_IPU_INT_CTRL_10__EMPTY 0x1E000060,0x00000000 ++#define IPU_IPU_INT_CTRL_10__FULL 0x1E000060,0xffffffff ++#define IPU_IPU_INT_CTRL_10__AXIR_ERR_EN 0x1E000060,0x40000000 ++#define IPU_IPU_INT_CTRL_10__AXIW_ERR_EN 0x1E000060,0x20000000 ++#define IPU_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1E000060,0x10000000 ++#define IPU_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN 0x1E000060,0x04000000 ++#define IPU_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN 0x1E000060,0x02000000 ++#define IPU_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN 0x1E000060,0x01000000 ++#define IPU_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN 0x1E000060,0x00400000 ++#define IPU_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN 0x1E000060,0x00200000 ++#define IPU_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN 0x1E000060,0x00100000 ++#define IPU_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN 0x1E000060,0x00080000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN 0x1E000060,0x00040000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN 0x1E000060,0x00020000 ++#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN 0x1E000060,0x00010000 ++#define IPU_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN 0x1E000060,0x00000020 ++#define IPU_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN 0x1E000060,0x00000010 ++#define IPU_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN 0x1E000060,0x00000008 ++#define IPU_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN 0x1E000060,0x00000004 ++#define IPU_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN 0x1E000060,0x00000002 ++#define IPU_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN 0x1E000060,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_11__ADDR 0x1E000064 ++#define IPU_IPU_INT_CTRL_11__EMPTY 0x1E000064,0x00000000 ++#define IPU_IPU_INT_CTRL_11__FULL 0x1E000064,0xffffffff ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1E000064,0x00400000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1E000064,0x00200000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1E000064,0x00100000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1E000064,0x00001000 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1E000064,0x00000800 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5 0x1E000064,0x00000020 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3 0x1E000064,0x00000008 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2 0x1E000064,0x00000004 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1 0x1E000064,0x00000002 ++#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0 0x1E000064,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_12__ADDR 0x1E000068 ++#define IPU_IPU_INT_CTRL_12__EMPTY 0x1E000068,0x00000000 ++#define IPU_IPU_INT_CTRL_12__FULL 0x1E000068,0xffffffff ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1E000068,0x00040000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1E000068,0x00020000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1E000068,0x00010000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1E000068,0x00008000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1E000068,0x00004000 ++#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1E000068,0x00002000 ++ ++#define IPU_IPU_INT_CTRL_13__ADDR 0x1E00006C ++#define IPU_IPU_INT_CTRL_13__EMPTY 0x1E00006C,0x00000000 ++#define IPU_IPU_INT_CTRL_13__FULL 0x1E00006C,0xffffffff ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1E00006C,0x80000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1E00006C,0x20000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1E00006C,0x10000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1E00006C,0x08000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1E00006C,0x01000000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1E00006C,0x00800000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1E00006C,0x00400000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1E00006C,0x00200000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1E00006C,0x00100000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1E00006C,0x00040000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1E00006C,0x00020000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1E00006C,0x00008000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1E00006C,0x00004000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1E00006C,0x00001000 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1E00006C,0x00000800 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_7 0x1E00006C,0x00000080 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_6 0x1E00006C,0x00000040 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_5 0x1E00006C,0x00000020 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_4 0x1E00006C,0x00000010 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_3 0x1E00006C,0x00000008 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_2 0x1E00006C,0x00000004 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_1 0x1E00006C,0x00000002 ++#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_0 0x1E00006C,0x00000001 ++ ++#define IPU_IPU_INT_CTRL_14__ADDR 0x1E000070 ++#define IPU_IPU_INT_CTRL_14__EMPTY 0x1E000070,0x00000000 ++#define IPU_IPU_INT_CTRL_14__FULL 0x1E000070,0xffffffff ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1E000070,0x00100000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1E000070,0x00080000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1E000070,0x00040000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1E000070,0x00020000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1E000070,0x00010000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1E000070,0x00008000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1E000070,0x00004000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1E000070,0x00002000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1E000070,0x00001000 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1E000070,0x00000800 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1E000070,0x00000400 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1E000070,0x00000200 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1E000070,0x00000100 ++#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1E000070,0x00000002 ++ ++#define IPU_IPU_INT_CTRL_15__ADDR 0x1E000074 ++#define IPU_IPU_INT_CTRL_15__EMPTY 0x1E000074,0x00000000 ++#define IPU_IPU_INT_CTRL_15__FULL 0x1E000074,0xffffffff ++#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN 0x1E000074,0x80000000 ++#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN 0x1E000074,0x40000000 ++#define IPU_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1E000074,0x20000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN 0x1E000074,0x10000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN 0x1E000074,0x08000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN 0x1E000074,0x04000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN 0x1E000074,0x02000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN 0x1E000074,0x01000000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN 0x1E000074,0x00800000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN 0x1E000074,0x00400000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN 0x1E000074,0x00200000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN 0x1E000074,0x00100000 ++#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN 0x1E000074,0x00080000 ++#define IPU_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1E000074,0x00040000 ++#define IPU_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN 0x1E000074,0x00020000 ++#define IPU_IPU_INT_CTRL_15__DC_DP_START_EN 0x1E000074,0x00010000 ++#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN 0x1E000074,0x00008000 ++#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN 0x1E000074,0x00004000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_6_EN 0x1E000074,0x00002000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_4_EN 0x1E000074,0x00001000 ++#define IPU_IPU_INT_CTRL_15__DC_FC_3_EN 0x1E000074,0x00000800 ++#define IPU_IPU_INT_CTRL_15__DC_FC_2_EN 0x1E000074,0x00000400 ++#define IPU_IPU_INT_CTRL_15__DC_FC_1_EN 0x1E000074,0x00000200 ++#define IPU_IPU_INT_CTRL_15__DC_FC_0_EN 0x1E000074,0x00000100 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN 0x1E000074,0x00000080 ++#define IPU_IPU_INT_CTRL_15__DP_SF_BRAKE_EN 0x1E000074,0x00000040 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_END_EN 0x1E000074,0x00000020 ++#define IPU_IPU_INT_CTRL_15__DP_ASF_START_EN 0x1E000074,0x00000010 ++#define IPU_IPU_INT_CTRL_15__DP_SF_END_EN 0x1E000074,0x00000008 ++#define IPU_IPU_INT_CTRL_15__DP_SF_START_EN 0x1E000074,0x00000004 ++#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN 0x1E000074,0x00000002 ++#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN 0x1E000074,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_1__ADDR 0x1E000078 ++#define IPU_IPU_SDMA_EVENT_1__EMPTY 0x1E000078,0x00000000 ++#define IPU_IPU_SDMA_EVENT_1__FULL 0x1E000078,0xffffffff ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1E000078,0x80000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1E000078,0x20000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1E000078,0x10000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1E000078,0x08000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1E000078,0x01000000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1E000078,0x00800000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1E000078,0x00400000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1E000078,0x00200000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1E000078,0x00100000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1E000078,0x00040000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1E000078,0x00020000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1E000078,0x00008000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1E000078,0x00004000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1E000078,0x00001000 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1E000078,0x00000800 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7 0x1E000078,0x00000080 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6 0x1E000078,0x00000040 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5 0x1E000078,0x00000020 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4 0x1E000078,0x00000010 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3 0x1E000078,0x00000008 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2 0x1E000078,0x00000004 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1 0x1E000078,0x00000002 ++#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0 0x1E000078,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_2__ADDR 0x1E00007C ++#define IPU_IPU_SDMA_EVENT_2__EMPTY 0x1E00007C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_2__FULL 0x1E00007C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1E00007C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1E00007C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1E00007C,0x00040000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1E00007C,0x00020000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1E00007C,0x00010000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1E00007C,0x00008000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1E00007C,0x00004000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1E00007C,0x00002000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1E00007C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1E00007C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1E00007C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1E00007C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1E00007C,0x00000100 ++#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1E00007C,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_3__ADDR 0x1E000080 ++#define IPU_IPU_SDMA_EVENT_3__EMPTY 0x1E000080,0x00000000 ++#define IPU_IPU_SDMA_EVENT_3__FULL 0x1E000080,0xffffffff ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1E000080,0x80000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1E000080,0x20000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1E000080,0x10000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1E000080,0x08000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1E000080,0x01000000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1E000080,0x00800000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1E000080,0x00400000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1E000080,0x00200000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1E000080,0x00100000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1E000080,0x00040000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1E000080,0x00020000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1E000080,0x00008000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1E000080,0x00004000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1E000080,0x00001000 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1E000080,0x00000800 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7 0x1E000080,0x00000080 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6 0x1E000080,0x00000040 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5 0x1E000080,0x00000020 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4 0x1E000080,0x00000010 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3 0x1E000080,0x00000008 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2 0x1E000080,0x00000004 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1 0x1E000080,0x00000002 ++#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0 0x1E000080,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_4__ADDR 0x1E000084 ++#define IPU_IPU_SDMA_EVENT_4__EMPTY 0x1E000084,0x00000000 ++#define IPU_IPU_SDMA_EVENT_4__FULL 0x1E000084,0xffffffff ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1E000084,0x00100000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1E000084,0x00080000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1E000084,0x00040000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1E000084,0x00020000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1E000084,0x00010000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1E000084,0x00008000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1E000084,0x00004000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1E000084,0x00002000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1E000084,0x00001000 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1E000084,0x00000800 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1E000084,0x00000400 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1E000084,0x00000200 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1E000084,0x00000100 ++#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1E000084,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_7__ADDR 0x1E000088 ++#define IPU_IPU_SDMA_EVENT_7__EMPTY 0x1E000088,0x00000000 ++#define IPU_IPU_SDMA_EVENT_7__FULL 0x1E000088,0xffffffff ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1E000088,0x80000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1E000088,0x20000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1E000088,0x10000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1E000088,0x08000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1E000088,0x01000000 ++#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1E000088,0x00800000 ++ ++#define IPU_IPU_SDMA_EVENT_8__ADDR 0x1E00008C ++#define IPU_IPU_SDMA_EVENT_8__EMPTY 0x1E00008C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_8__FULL 0x1E00008C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1E00008C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1E00008C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1E00008C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1E00008C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1E00008C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1E00008C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1E00008C,0x00000002 ++ ++#define IPU_IPU_SDMA_EVENT_11__ADDR 0x1E000090 ++#define IPU_IPU_SDMA_EVENT_11__EMPTY 0x1E000090,0x00000000 ++#define IPU_IPU_SDMA_EVENT_11__FULL 0x1E000090,0xffffffff ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1E000090,0x00400000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1E000090,0x00200000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1E000090,0x00100000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1E000090,0x00001000 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1E000090,0x00000800 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5 0x1E000090,0x00000020 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3 0x1E000090,0x00000008 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2 0x1E000090,0x00000004 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1 0x1E000090,0x00000002 ++#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0 0x1E000090,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_12__ADDR 0x1E000094 ++#define IPU_IPU_SDMA_EVENT_12__EMPTY 0x1E000094,0x00000000 ++#define IPU_IPU_SDMA_EVENT_12__FULL 0x1E000094,0xffffffff ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1E000094,0x00040000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1E000094,0x00020000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1E000094,0x00010000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1E000094,0x00008000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1E000094,0x00004000 ++#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1E000094,0x00002000 ++ ++#define IPU_IPU_SDMA_EVENT_13__ADDR 0x1E000098 ++#define IPU_IPU_SDMA_EVENT_13__EMPTY 0x1E000098,0x00000000 ++#define IPU_IPU_SDMA_EVENT_13__FULL 0x1E000098,0xffffffff ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1E000098,0x80000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1E000098,0x20000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1E000098,0x10000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1E000098,0x08000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1E000098,0x01000000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1E000098,0x00800000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1E000098,0x00400000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1E000098,0x00200000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1E000098,0x00100000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1E000098,0x00040000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1E000098,0x00020000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1E000098,0x00008000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1E000098,0x00004000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1E000098,0x00001000 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1E000098,0x00000800 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7 0x1E000098,0x00000080 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6 0x1E000098,0x00000040 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5 0x1E000098,0x00000020 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4 0x1E000098,0x00000010 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3 0x1E000098,0x00000008 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2 0x1E000098,0x00000004 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1 0x1E000098,0x00000002 ++#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0 0x1E000098,0x00000001 ++ ++#define IPU_IPU_SDMA_EVENT_14__ADDR 0x1E00009C ++#define IPU_IPU_SDMA_EVENT_14__EMPTY 0x1E00009C,0x00000000 ++#define IPU_IPU_SDMA_EVENT_14__FULL 0x1E00009C,0xffffffff ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1E00009C,0x00100000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1E00009C,0x00080000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1E00009C,0x00040000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1E00009C,0x00020000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1E00009C,0x00010000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1E00009C,0x00008000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1E00009C,0x00004000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1E00009C,0x00002000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1E00009C,0x00001000 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1E00009C,0x00000800 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1E00009C,0x00000400 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1E00009C,0x00000200 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1E00009C,0x00000100 ++#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1E00009C,0x00000002 ++ ++#define IPU_IPU_SRM_PRI1__ADDR 0x1E0000A0 ++#define IPU_IPU_SRM_PRI1__EMPTY 0x1E0000A0,0x00000000 ++#define IPU_IPU_SRM_PRI1__FULL 0x1E0000A0,0xffffffff ++#define IPU_IPU_SRM_PRI1__ISP_SRM_MODE 0x1E0000A0,0x00180000 ++#define IPU_IPU_SRM_PRI1__ISP_SRM_PRI 0x1E0000A0,0x00070000 ++#define IPU_IPU_SRM_PRI1__CSI0_SRM_MODE 0x1E0000A0,0x00001800 ++#define IPU_IPU_SRM_PRI1__CSI0_SRM_PRI 0x1E0000A0,0x00000700 ++#define IPU_IPU_SRM_PRI1__CSI1_SRM_MODE 0x1E0000A0,0x00000018 ++#define IPU_IPU_SRM_PRI1__CSI1_SRM_PRI 0x1E0000A0,0x00000007 ++ ++#define IPU_IPU_SRM_PRI2__ADDR 0x1E0000A4 ++#define IPU_IPU_SRM_PRI2__EMPTY 0x1E0000A4,0x00000000 ++#define IPU_IPU_SRM_PRI2__FULL 0x1E0000A4,0xffffffff ++#define IPU_IPU_SRM_PRI2__DI1_SRM_MODE 0x1E0000A4,0x18000000 ++#define IPU_IPU_SRM_PRI2__DI1_SRM_PRI 0x1E0000A4,0x07000000 ++#define IPU_IPU_SRM_PRI2__DI0_SRM_MODE 0x1E0000A4,0x00180000 ++#define IPU_IPU_SRM_PRI2__DI0_SRM_PRI 0x1E0000A4,0x00070000 ++#define IPU_IPU_SRM_PRI2__DC_6_SRM_MODE 0x1E0000A4,0x0000C000 ++#define IPU_IPU_SRM_PRI2__DC_2_SRM_MODE 0x1E0000A4,0x00003000 ++#define IPU_IPU_SRM_PRI2__DC_SRM_PRI 0x1E0000A4,0x00000E00 ++#define IPU_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1E0000A4,0x00000180 ++#define IPU_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1E0000A4,0x00000060 ++#define IPU_IPU_SRM_PRI2__DP_S_SRM_MODE 0x1E0000A4,0x00000018 ++#define IPU_IPU_SRM_PRI2__DP_SRM_PRI 0x1E0000A4,0x00000007 ++ ++#define IPU_IPU_FS_PROC_FLOW1__ADDR 0x1E0000A8 ++#define IPU_IPU_FS_PROC_FLOW1__EMPTY 0x1E0000A8,0x00000000 ++#define IPU_IPU_FS_PROC_FLOW1__FULL 0x1E0000A8,0xffffffff ++#define IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID 0x1E0000A8,0x80000000 ++#define IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID 0x1E0000A8,0x40000000 ++#define IPU_IPU_FS_PROC_FLOW1__PRP_SRC_SEL 0x1E0000A8,0x0F000000 ++#define IPU_IPU_FS_PROC_FLOW1__ISP_SRC_SEL 0x1E0000A8,0x00F00000 ++#define IPU_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL 0x1E0000A8,0x000F0000 ++#define IPU_IPU_FS_PROC_FLOW1__PP_SRC_SEL 0x1E0000A8,0x0000F000 ++#define IPU_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL 0x1E0000A8,0x00000F00 ++#define IPU_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL 0x1E0000A8,0x000000F0 ++#define IPU_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1E0000A8,0x0000000F ++ ++#define IPU_IPU_FS_PROC_FLOW2__ADDR 0x1E0000AC ++#define IPU_IPU_FS_PROC_FLOW2__EMPTY 0x1E0000AC,0x00000000 ++#define IPU_IPU_FS_PROC_FLOW2__FULL 0x1E0000AC,0xffffffff ++#define IPU_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL 0x1E0000AC,0xF0000000 ++#define IPU_IPU_FS_PROC_FLOW2__PRP_DEST_SEL 0x1E0000AC,0x0F000000 ++#define IPU_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1E0000AC,0x00F00000 ++#define IPU_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL 0x1E0000AC,0x000F0000 ++#define IPU_IPU_FS_PROC_FLOW2__PP_DEST_SEL 0x1E0000AC,0x0000F000 ++#define IPU_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL 0x1E0000AC,0x00000F00 ++#define IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL 0x1E0000AC,0x000000F0 ++#define IPU_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL 0x1E0000AC,0x0000000F ++ ++#define IPU_IPU_FS_PROC_FLOW3__ADDR 0x1E0000B0 ++#define IPU_IPU_FS_PROC_FLOW3__EMPTY 0x1E0000B0,0x00000000 ++#define IPU_IPU_FS_PROC_FLOW3__FULL 0x1E0000B0,0xffffffff ++#define IPU_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL 0x1E0000B0,0x00003800 ++#define IPU_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL 0x1E0000B0,0x00000780 ++#define IPU_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL 0x1E0000B0,0x00000070 ++#define IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL 0x1E0000B0,0x0000000F ++ ++#define IPU_IPU_FS_DISP_FLOW1__ADDR 0x1E0000B4 ++#define IPU_IPU_FS_DISP_FLOW1__EMPTY 0x1E0000B4,0x00000000 ++#define IPU_IPU_FS_DISP_FLOW1__FULL 0x1E0000B4,0xffffffff ++#define IPU_IPU_FS_DISP_FLOW1__DC1_SRC_SEL 0x1E0000B4,0x00F00000 ++#define IPU_IPU_FS_DISP_FLOW1__DC2_SRC_SEL 0x1E0000B4,0x000F0000 ++#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1E0000B4,0x0000F000 ++#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1E0000B4,0x00000F00 ++#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL 0x1E0000B4,0x000000F0 ++#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL 0x1E0000B4,0x0000000F ++ ++#define IPU_IPU_FS_DISP_FLOW2__ADDR 0x1E0000B8 ++#define IPU_IPU_FS_DISP_FLOW2__EMPTY 0x1E0000B8,0x00000000 ++#define IPU_IPU_FS_DISP_FLOW2__FULL 0x1E0000B8,0xffffffff ++#define IPU_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL 0x1E0000B8,0x000F0000 ++#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1E0000B8,0x000000F0 ++#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1E0000B8,0x0000000F ++ ++#define IPU_IPU_SKIP__ADDR 0x1E0000BC ++#define IPU_IPU_SKIP__EMPTY 0x1E0000BC,0x00000000 ++#define IPU_IPU_SKIP__FULL 0x1E0000BC,0xffffffff ++#define IPU_IPU_SKIP__CSI_SKIP_IC_VF 0x1E0000BC,0x0000F800 ++#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF 0x1E0000BC,0x00000700 ++#define IPU_IPU_SKIP__CSI_SKIP_IC_ENC 0x1E0000BC,0x000000F8 ++#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC 0x1E0000BC,0x00000007 ++ ++#define IPU_IPU_DISP_ALT_CONF__ADDR 0x1E0000C0 ++#define IPU_IPU_DISP_ALT_CONF__EMPTY 0x1E0000C0,0x00000000 ++#define IPU_IPU_DISP_ALT_CONF__FULL 0x1E0000C0,0xffffffff ++ ++#define IPU_IPU_DISP_GEN__ADDR 0x1E0000C4 ++#define IPU_IPU_DISP_GEN__EMPTY 0x1E0000C4,0x00000000 ++#define IPU_IPU_DISP_GEN__FULL 0x1E0000C4,0xffffffff ++#define IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE 0x1E0000C4,0x02000000 ++#define IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE 0x1E0000C4,0x01000000 ++#define IPU_IPU_DISP_GEN__CSI_VSYNC_DEST 0x1E0000C4,0x00800000 ++#define IPU_IPU_DISP_GEN__MCU_MAX_BURST_STOP 0x1E0000C4,0x00400000 ++#define IPU_IPU_DISP_GEN__MCU_T 0x1E0000C4,0x003C0000 ++#define IPU_IPU_DISP_GEN__MCU_DI_ID_9 0x1E0000C4,0x00020000 ++#define IPU_IPU_DISP_GEN__MCU_DI_ID_8 0x1E0000C4,0x00010000 ++#define IPU_IPU_DISP_GEN__DP_PIPE_CLR 0x1E0000C4,0x00000040 ++#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC1 0x1E0000C4,0x00000020 ++#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC0 0x1E0000C4,0x00000010 ++#define IPU_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1E0000C4,0x00000008 ++#define IPU_IPU_DISP_GEN__DC2_DOUBLE_FLOW 0x1E0000C4,0x00000004 ++#define IPU_IPU_DISP_GEN__DI1_DUAL_MODE 0x1E0000C4,0x00000002 ++#define IPU_IPU_DISP_GEN__DI0_DUAL_MODE 0x1E0000C4,0x00000001 ++ ++#define IPU_IPU_DISP_ALT1__ADDR 0x1E0000C8 ++#define IPU_IPU_DISP_ALT1__EMPTY 0x1E0000C8,0x00000000 ++#define IPU_IPU_DISP_ALT1__FULL 0x1E0000C8,0xffffffff ++#define IPU_IPU_DISP_ALT1__SEL_ALT_0 0x1E0000C8,0xF0000000 ++#define IPU_IPU_DISP_ALT1__STEP_REPEAT_ALT_0 0x1E0000C8,0x0FFF0000 ++#define IPU_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1E0000C8,0x00008000 ++#define IPU_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0 0x1E0000C8,0x00007000 ++#define IPU_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0 0x1E0000C8,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT2__ADDR 0x1E0000CC ++#define IPU_IPU_DISP_ALT2__EMPTY 0x1E0000CC,0x00000000 ++#define IPU_IPU_DISP_ALT2__FULL 0x1E0000CC,0xffffffff ++#define IPU_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0 0x1E0000CC,0x00070000 ++#define IPU_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1E0000CC,0x00007000 ++#define IPU_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0 0x1E0000CC,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT3__ADDR 0x1E0000D0 ++#define IPU_IPU_DISP_ALT3__EMPTY 0x1E0000D0,0x00000000 ++#define IPU_IPU_DISP_ALT3__FULL 0x1E0000D0,0xffffffff ++#define IPU_IPU_DISP_ALT3__SEL_ALT_1 0x1E0000D0,0xF0000000 ++#define IPU_IPU_DISP_ALT3__STEP_REPEAT_ALT_1 0x1E0000D0,0x0FFF0000 ++#define IPU_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1E0000D0,0x00008000 ++#define IPU_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1 0x1E0000D0,0x00007000 ++#define IPU_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1 0x1E0000D0,0x00000FFF ++ ++#define IPU_IPU_DISP_ALT4__ADDR 0x1E0000D4 ++#define IPU_IPU_DISP_ALT4__EMPTY 0x1E0000D4,0x00000000 ++#define IPU_IPU_DISP_ALT4__FULL 0x1E0000D4,0xffffffff ++#define IPU_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1 0x1E0000D4,0x00070000 ++#define IPU_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1E0000D4,0x00007000 ++#define IPU_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1 0x1E0000D4,0x00000FFF ++ ++#define IPU_IPU_SNOOP__ADDR 0x1E0000D8 ++#define IPU_IPU_SNOOP__EMPTY 0x1E0000D8,0x00000000 ++#define IPU_IPU_SNOOP__FULL 0x1E0000D8,0xffffffff ++#define IPU_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1E0000D8,0x00010000 ++#define IPU_IPU_SNOOP__AUTOREF_PER 0x1E0000D8,0x000003FF ++ ++#define IPU_IPU_MEM_RST__ADDR 0x1E0000DC ++#define IPU_IPU_MEM_RST__EMPTY 0x1E0000DC,0x00000000 ++#define IPU_IPU_MEM_RST__FULL 0x1E0000DC,0xffffffff ++#define IPU_IPU_MEM_RST__RST_MEM_START 0x1E0000DC,0x80000000 ++#define IPU_IPU_MEM_RST__RST_MEM_EN 0x1E0000DC,0x007FFFFF ++ ++#define IPU_IPU_PM__ADDR 0x1E0000E0 ++#define IPU_IPU_PM__EMPTY 0x1E0000E0,0x00000000 ++#define IPU_IPU_PM__FULL 0x1E0000E0,0xffffffff ++#define IPU_IPU_PM__LPSR_MODE 0x1E0000E0,0x80000000 ++#define IPU_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x40000000 ++#define IPU_IPU_PM__DI1_CLK_PERIOD_1 0x1E0000E0,0x3F800000 ++#define IPU_IPU_PM__DI1_CLK_PERIOD_0 0x1E0000E0,0x007F0000 ++#define IPU_IPU_PM__CLOCK_MODE_STAT 0x1E0000E0,0x00008000 ++#define IPU_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x00004000 ++#define IPU_IPU_PM__DI0_CLK_PERIOD_1 0x1E0000E0,0x00003F80 ++#define IPU_IPU_PM__DI0_CLK_PERIOD_0 0x1E0000E0,0x0000007F ++ ++#define IPU_IPU_GPR__ADDR 0x1E0000E4 ++#define IPU_IPU_GPR__EMPTY 0x1E0000E4,0x00000000 ++#define IPU_IPU_GPR__FULL 0x1E0000E4,0xffffffff ++#define IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR 0x1E0000E4,0x80000000 ++#define IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR 0x1E0000E4,0x40000000 ++#define IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR 0x1E0000E4,0x20000000 ++#define IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR 0x1E0000E4,0x10000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1E0000E4,0x08000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1E0000E4,0x04000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1E0000E4,0x02000000 ++#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1E0000E4,0x01000000 ++#define IPU_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00800000 ++#define IPU_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00400000 ++#define IPU_IPU_GPR__IPU_GP21 0x1E0000E4,0x00200000 ++#define IPU_IPU_GPR__IPU_GP20 0x1E0000E4,0x00100000 ++#define IPU_IPU_GPR__IPU_GP19 0x1E0000E4,0x00080000 ++#define IPU_IPU_GPR__IPU_GP18 0x1E0000E4,0x00040000 ++#define IPU_IPU_GPR__IPU_GP17 0x1E0000E4,0x00020000 ++#define IPU_IPU_GPR__IPU_GP16 0x1E0000E4,0x00010000 ++#define IPU_IPU_GPR__IPU_GP15 0x1E0000E4,0x00008000 ++#define IPU_IPU_GPR__IPU_GP14 0x1E0000E4,0x00004000 ++#define IPU_IPU_GPR__IPU_GP13 0x1E0000E4,0x00002000 ++#define IPU_IPU_GPR__IPU_GP12 0x1E0000E4,0x00001000 ++#define IPU_IPU_GPR__IPU_GP11 0x1E0000E4,0x00000800 ++#define IPU_IPU_GPR__IPU_GP10 0x1E0000E4,0x00000400 ++#define IPU_IPU_GPR__IPU_GP9 0x1E0000E4,0x00000200 ++#define IPU_IPU_GPR__IPU_GP8 0x1E0000E4,0x00000100 ++#define IPU_IPU_GPR__IPU_GP7 0x1E0000E4,0x00000080 ++#define IPU_IPU_GPR__IPU_GP6 0x1E0000E4,0x00000040 ++#define IPU_IPU_GPR__IPU_GP5 0x1E0000E4,0x00000020 ++#define IPU_IPU_GPR__IPU_GP4 0x1E0000E4,0x00000010 ++#define IPU_IPU_GPR__IPU_GP3 0x1E0000E4,0x00000008 ++#define IPU_IPU_GPR__IPU_GP2 0x1E0000E4,0x00000004 ++#define IPU_IPU_GPR__IPU_GP1 0x1E0000E4,0x00000002 ++#define IPU_IPU_GPR__IPU_GP0 0x1E0000E4,0x00000001 ++ ++#define IPU_IPU_CH_DB_MODE_SEL_0__ADDR 0x1E000150 ++#define IPU_IPU_CH_DB_MODE_SEL_0__EMPTY 0x1E000150,0x00000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__FULL 0x1E000150,0xffffffff ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_31 0x1E000150,0x80000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_29 0x1E000150,0x20000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_28 0x1E000150,0x10000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_27 0x1E000150,0x08000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_24 0x1E000150,0x01000000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_23 0x1E000150,0x00800000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_22 0x1E000150,0x00400000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_21 0x1E000150,0x00200000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_20 0x1E000150,0x00100000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_18 0x1E000150,0x00040000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_17 0x1E000150,0x00020000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_15 0x1E000150,0x00008000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_14 0x1E000150,0x00004000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_12 0x1E000150,0x00001000 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_11 0x1E000150,0x00000800 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_7 0x1E000150,0x00000080 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_6 0x1E000150,0x00000040 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_5 0x1E000150,0x00000020 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_4 0x1E000150,0x00000010 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_3 0x1E000150,0x00000008 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_2 0x1E000150,0x00000004 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_1 0x1E000150,0x00000002 ++#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_0 0x1E000150,0x00000001 ++ ++#define IPU_IPU_CH_DB_MODE_SEL_1__ADDR 0x1E000154 ++#define IPU_IPU_CH_DB_MODE_SEL_1__EMPTY 0x1E000154,0x00000000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__FULL 0x1E000154,0xffffffff ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_52 0x1E000154,0x00100000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_51 0x1E000154,0x00080000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_50 0x1E000154,0x00040000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_49 0x1E000154,0x00020000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_48 0x1E000154,0x00010000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_47 0x1E000154,0x00008000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_46 0x1E000154,0x00004000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_45 0x1E000154,0x00002000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_44 0x1E000154,0x00001000 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_43 0x1E000154,0x00000800 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_42 0x1E000154,0x00000400 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_41 0x1E000154,0x00000200 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_40 0x1E000154,0x00000100 ++#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_33 0x1E000154,0x00000002 ++ ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__ADDR 0x1E000168 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__EMPTY 0x1E000168,0x00000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__FULL 0x1E000168,0xffffffff ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_29 0x1E000168,0x20000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_24 0x1E000168,0x01000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_7 0x1E000168,0x00000080 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_6 0x1E000168,0x00000040 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_5 0x1E000168,0x00000020 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_4 0x1E000168,0x00000010 ++ ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__ADDR 0x1E00016C ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__EMPTY 0x1E00016C,0x00000000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__FULL 0x1E00016C,0xffffffff ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_52 0x1E00016C,0x00100000 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_41 0x1E00016C,0x00000200 ++#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_33 0x1E00016C,0x00000002 ++ ++#define IPU_IPU_CH_TRB_MODE_SEL_0__ADDR 0x1E000178 ++#define IPU_IPU_CH_TRB_MODE_SEL_1__ADDR 0x1E00017C ++ ++// ================== End of IPUV3EX Common Registers ====================== ++ ++// ================= Start of IPUV3EX Status Registers ===================== ++ ++#define IPU_IPU_INT_STAT_1__ADDR 0x1E000200 ++#define IPU_IPU_INT_STAT_1__EMPTY 0x1E000200,0x00000000 ++#define IPU_IPU_INT_STAT_1__FULL 0x1E000200,0xffffffff ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_31 0x1E000200,0x80000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_29 0x1E000200,0x20000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_28 0x1E000200,0x10000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_27 0x1E000200,0x08000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_24 0x1E000200,0x01000000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_23 0x1E000200,0x00800000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_22 0x1E000200,0x00400000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_21 0x1E000200,0x00200000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_20 0x1E000200,0x00100000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_18 0x1E000200,0x00040000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_17 0x1E000200,0x00020000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_15 0x1E000200,0x00008000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_14 0x1E000200,0x00004000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_12 0x1E000200,0x00001000 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_11 0x1E000200,0x00000800 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_7 0x1E000200,0x00000080 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_6 0x1E000200,0x00000040 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_5 0x1E000200,0x00000020 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_4 0x1E000200,0x00000010 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_3 0x1E000200,0x00000008 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_2 0x1E000200,0x00000004 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_1 0x1E000200,0x00000002 ++#define IPU_IPU_INT_STAT_1__IDMAC_EOF_0 0x1E000200,0x00000001 ++ ++#define IPU_IPU_INT_STAT_2__ADDR 0x1E000204 ++#define IPU_IPU_INT_STAT_2__EMPTY 0x1E000204,0x00000000 ++#define IPU_IPU_INT_STAT_2__FULL 0x1E000204,0xffffffff ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_52 0x1E000204,0x00100000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_51 0x1E000204,0x00080000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_50 0x1E000204,0x00040000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_49 0x1E000204,0x00020000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_48 0x1E000204,0x00010000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_47 0x1E000204,0x00008000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_46 0x1E000204,0x00004000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_45 0x1E000204,0x00002000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_44 0x1E000204,0x00001000 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_43 0x1E000204,0x00000800 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_42 0x1E000204,0x00000400 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_41 0x1E000204,0x00000200 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_40 0x1E000204,0x00000100 ++#define IPU_IPU_INT_STAT_2__IDMAC_EOF_33 0x1E000204,0x00000002 ++ ++#define IPU_IPU_INT_STAT_3__ADDR 0x1E000208 ++#define IPU_IPU_INT_STAT_3__EMPTY 0x1E000208,0x00000000 ++#define IPU_IPU_INT_STAT_3__FULL 0x1E000208,0xffffffff ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_31 0x1E000208,0x80000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_29 0x1E000208,0x20000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_28 0x1E000208,0x10000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_27 0x1E000208,0x08000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_24 0x1E000208,0x01000000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_23 0x1E000208,0x00800000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_22 0x1E000208,0x00400000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_21 0x1E000208,0x00200000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_20 0x1E000208,0x00100000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_18 0x1E000208,0x00040000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_17 0x1E000208,0x00020000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_15 0x1E000208,0x00008000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_14 0x1E000208,0x00004000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_12 0x1E000208,0x00001000 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_11 0x1E000208,0x00000800 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_7 0x1E000208,0x00000080 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_6 0x1E000208,0x00000040 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_5 0x1E000208,0x00000020 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_4 0x1E000208,0x00000010 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_3 0x1E000208,0x00000008 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_2 0x1E000208,0x00000004 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_1 0x1E000208,0x00000002 ++#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_0 0x1E000208,0x00000001 ++ ++#define IPU_IPU_INT_STAT_4__ADDR 0x1E00020C ++#define IPU_IPU_INT_STAT_4__EMPTY 0x1E00020C,0x00000000 ++#define IPU_IPU_INT_STAT_4__FULL 0x1E00020C,0xffffffff ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_52 0x1E00020C,0x00100000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_51 0x1E00020C,0x00080000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_50 0x1E00020C,0x00040000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_49 0x1E00020C,0x00020000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_48 0x1E00020C,0x00010000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_47 0x1E00020C,0x00008000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_46 0x1E00020C,0x00004000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_45 0x1E00020C,0x00002000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_44 0x1E00020C,0x00001000 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_43 0x1E00020C,0x00000800 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_42 0x1E00020C,0x00000400 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_41 0x1E00020C,0x00000200 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_40 0x1E00020C,0x00000100 ++#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_33 0x1E00020C,0x00000002 ++ ++#define IPU_IPU_INT_STAT_5__ADDR 0x1E000210 ++#define IPU_IPU_INT_STAT_5__EMPTY 0x1E000210,0x00000000 ++#define IPU_IPU_INT_STAT_5__FULL 0x1E000210,0xffffffff ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_31 0x1E000210,0x80000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_29 0x1E000210,0x20000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_28 0x1E000210,0x10000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_27 0x1E000210,0x08000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_24 0x1E000210,0x01000000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_23 0x1E000210,0x00800000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_22 0x1E000210,0x00400000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_21 0x1E000210,0x00200000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_20 0x1E000210,0x00100000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_18 0x1E000210,0x00040000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_17 0x1E000210,0x00020000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_15 0x1E000210,0x00008000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_14 0x1E000210,0x00004000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_12 0x1E000210,0x00001000 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_11 0x1E000210,0x00000800 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_7 0x1E000210,0x00000080 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_6 0x1E000210,0x00000040 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_5 0x1E000210,0x00000020 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_4 0x1E000210,0x00000010 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_3 0x1E000210,0x00000008 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_2 0x1E000210,0x00000004 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_1 0x1E000210,0x00000002 ++#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_0 0x1E000210,0x00000001 ++ ++#define IPU_IPU_INT_STAT_6__ADDR 0x1E000214 ++#define IPU_IPU_INT_STAT_6__EMPTY 0x1E000214,0x00000000 ++#define IPU_IPU_INT_STAT_6__FULL 0x1E000214,0xffffffff ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_52 0x1E000214,0x00100000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_51 0x1E000214,0x00080000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_50 0x1E000214,0x00040000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_49 0x1E000214,0x00020000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_48 0x1E000214,0x00010000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_47 0x1E000214,0x00008000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_46 0x1E000214,0x00004000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_45 0x1E000214,0x00002000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_44 0x1E000214,0x00001000 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_43 0x1E000214,0x00000800 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_42 0x1E000214,0x00000400 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_41 0x1E000214,0x00000200 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_40 0x1E000214,0x00000100 ++#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_33 0x1E000214,0x00000002 ++ ++#define IPU_IPU_INT_STAT_7__ADDR 0x1E000218 ++#define IPU_IPU_INT_STAT_7__EMPTY 0x1E000218,0x00000000 ++#define IPU_IPU_INT_STAT_7__FULL 0x1E000218,0xffffffff ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_31 0x1E000218,0x80000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_29 0x1E000218,0x20000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_28 0x1E000218,0x10000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_27 0x1E000218,0x08000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_24 0x1E000218,0x01000000 ++#define IPU_IPU_INT_STAT_7__IDMAC_EOS_23 0x1E000218,0x00800000 ++ ++#define IPU_IPU_INT_STAT_8__ADDR 0x1E00021C ++#define IPU_IPU_INT_STAT_8__EMPTY 0x1E00021C,0x00000000 ++#define IPU_IPU_INT_STAT_8__FULL 0x1E00021C,0xffffffff ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_52 0x1E00021C,0x00100000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_51 0x1E00021C,0x00080000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_44 0x1E00021C,0x00001000 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_43 0x1E00021C,0x00000800 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_42 0x1E00021C,0x00000400 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_41 0x1E00021C,0x00000200 ++#define IPU_IPU_INT_STAT_8__IDMAC_EOS_32 0x1E00021C,0x00000002 ++ ++#define IPU_IPU_INT_STAT_9__ADDR 0x1E000220 ++#define IPU_IPU_INT_STAT_9__EMPTY 0x1E000220,0x00000000 ++#define IPU_IPU_INT_STAT_9__FULL 0x1E000220,0xffffffff ++#define IPU_IPU_INT_STAT_9__CSI1_PUPE 0x1E000220,0x80000000 ++#define IPU_IPU_INT_STAT_9__CSI0_PUPE 0x1E000220,0x40000000 ++#define IPU_IPU_INT_STAT_9__ISP_PUPE 0x1E000220,0x20000000 ++#define IPU_IPU_INT_STAT_9__IC_VF_BUF_OVF 0x1E000220,0x10000000 ++#define IPU_IPU_INT_STAT_9__IC_ENC_BUF_OVF 0x1E000220,0x08000000 ++#define IPU_IPU_INT_STAT_9__IC_BAYER_BUF_OVF 0x1E000220,0x04000000 ++ ++#define IPU_IPU_INT_STAT_10__ADDR 0x1E000224 ++#define IPU_IPU_INT_STAT_10__EMPTY 0x1E000224,0x00000000 ++#define IPU_IPU_INT_STAT_10__FULL 0x1E000224,0xffffffff ++#define IPU_IPU_INT_STAT_10__AXIR_ERR 0x1E000224,0x40000000 ++#define IPU_IPU_INT_STAT_10__AXIW_ERR 0x1E000224,0x20000000 ++#define IPU_IPU_INT_STAT_10__NON_PRIVILEGED_ACC_ERR 0x1E000224,0x10000000 ++#define IPU_IPU_INT_STAT_10__IC_BAYER_FRM_LOST_ERR 0x1E000224,0x04000000 ++#define IPU_IPU_INT_STAT_10__IC_ENC_FRM_LOST_ERR 0x1E000224,0x02000000 ++#define IPU_IPU_INT_STAT_10__IC_VF_FRM_LOST_ERR 0x1E000224,0x01000000 ++#define IPU_IPU_INT_STAT_10__DI1_TIME_OUT_ERR 0x1E000224,0x00400000 ++#define IPU_IPU_INT_STAT_10__DI0_TIME_OUT_ERR 0x1E000224,0x00200000 ++#define IPU_IPU_INT_STAT_10__DI1_SYNC_DISP_ERR 0x1E000224,0x00100000 ++#define IPU_IPU_INT_STAT_10__DI0_SYNC_DISP_ERR 0x1E000224,0x00080000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_6 0x1E000224,0x00040000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_2 0x1E000224,0x00020000 ++#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_1 0x1E000224,0x00010000 ++#define IPU_IPU_INT_STAT_10__ISP_RAM_HIST_OF 0x1E000224,0x00000020 ++#define IPU_IPU_INT_STAT_10__ISP_RAM_ST_OF 0x1E000224,0x00000010 ++#define IPU_IPU_INT_STAT_10__SMFC3_FRM_LOST 0x1E000224,0x00000008 ++#define IPU_IPU_INT_STAT_10__SMFC2_FRM_LOST 0x1E000224,0x00000004 ++#define IPU_IPU_INT_STAT_10__SMFC1_FRM_LOST 0x1E000224,0x00000002 ++#define IPU_IPU_INT_STAT_10__SMFC0_FRM_LOST 0x1E000224,0x00000001 ++ ++#define IPU_IPU_INT_STAT_11__ADDR 0x1E000228 ++#define IPU_IPU_INT_STAT_11__EMPTY 0x1E000228,0x00000000 ++#define IPU_IPU_INT_STAT_11__FULL 0x1E000228,0xffffffff ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_22 0x1E000228,0x00400000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_21 0x1E000228,0x00200000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_20 0x1E000228,0x00100000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_12 0x1E000228,0x00001000 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_11 0x1E000228,0x00000800 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_5 0x1E000228,0x00000020 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_3 0x1E000228,0x00000008 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_2 0x1E000228,0x00000004 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_1 0x1E000228,0x00000002 ++#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_0 0x1E000228,0x00000001 ++ ++#define IPU_IPU_INT_STAT_12__ADDR 0x1E00022C ++#define IPU_IPU_INT_STAT_12__EMPTY 0x1E00022C,0x00000000 ++#define IPU_IPU_INT_STAT_12__FULL 0x1E00022C,0xffffffff ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_50 0x1E00022C,0x00040000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_49 0x1E00022C,0x00020000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_48 0x1E00022C,0x00010000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_47 0x1E00022C,0x00008000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_46 0x1E00022C,0x00004000 ++#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_45 0x1E00022C,0x00002000 ++ ++#define IPU_IPU_INT_STAT_13__ADDR 0x1E000230 ++#define IPU_IPU_INT_STAT_13__EMPTY 0x1E000230,0x00000000 ++#define IPU_IPU_INT_STAT_13__FULL 0x1E000230,0xffffffff ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_31 0x1E000230,0x80000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_29 0x1E000230,0x20000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_28 0x1E000230,0x10000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_27 0x1E000230,0x08000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_24 0x1E000230,0x01000000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_23 0x1E000230,0x00800000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_22 0x1E000230,0x00400000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_21 0x1E000230,0x00200000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_20 0x1E000230,0x00100000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_18 0x1E000230,0x00040000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_17 0x1E000230,0x00020000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_15 0x1E000230,0x00008000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_14 0x1E000230,0x00004000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_12 0x1E000230,0x00001000 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_11 0x1E000230,0x00000800 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_7 0x1E000230,0x00000080 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_6 0x1E000230,0x00000040 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_5 0x1E000230,0x00000020 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_4 0x1E000230,0x00000010 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_3 0x1E000230,0x00000008 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_2 0x1E000230,0x00000004 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_1 0x1E000230,0x00000002 ++#define IPU_IPU_INT_STAT_13__IDMAC_TH_0 0x1E000230,0x00000001 ++ ++#define IPU_IPU_INT_STAT_14__ADDR 0x1E000234 ++#define IPU_IPU_INT_STAT_14__EMPTY 0x1E000234,0x00000000 ++#define IPU_IPU_INT_STAT_14__FULL 0x1E000234,0xffffffff ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_52 0x1E000234,0x00100000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_51 0x1E000234,0x00080000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_50 0x1E000234,0x00040000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_49 0x1E000234,0x00020000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_48 0x1E000234,0x00010000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_47 0x1E000234,0x00008000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_46 0x1E000234,0x00004000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_45 0x1E000234,0x00002000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_44 0x1E000234,0x00001000 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_43 0x1E000234,0x00000800 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_42 0x1E000234,0x00000400 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_41 0x1E000234,0x00000200 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_40 0x1E000234,0x00000100 ++#define IPU_IPU_INT_STAT_14__IDMAC_TH_33 0x1E000234,0x00000002 ++ ++#define IPU_IPU_INT_STAT_15__ADDR 0x1E000238 ++#define IPU_IPU_INT_STAT_15__EMPTY 0x1E000238,0x00000000 ++#define IPU_IPU_INT_STAT_15__FULL 0x1E000238,0xffffffff ++#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_8 0x1E000238,0x80000000 ++#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_3 0x1E000238,0x40000000 ++#define IPU_IPU_INT_STAT_15__DI1_DISP_CLK_EN_PRE 0x1E000238,0x20000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_10 0x1E000238,0x10000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_9 0x1E000238,0x08000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_8 0x1E000238,0x04000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_7 0x1E000238,0x02000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_6 0x1E000238,0x01000000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_5 0x1E000238,0x00800000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_4 0x1E000238,0x00400000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_3 0x1E000238,0x00200000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_2 0x1E000238,0x00100000 ++#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_1 0x1E000238,0x00080000 ++#define IPU_IPU_INT_STAT_15__DI0_DISP_CLK_EN_PRE 0x1E000238,0x00040000 ++#define IPU_IPU_INT_STAT_15__DC_ASYNC_STOP 0x1E000238,0x00020000 ++#define IPU_IPU_INT_STAT_15__DC_DP_START 0x1E000238,0x00010000 ++#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_1 0x1E000238,0x00008000 ++#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_0 0x1E000238,0x00004000 ++#define IPU_IPU_INT_STAT_15__DC_FC_6 0x1E000238,0x00002000 ++#define IPU_IPU_INT_STAT_15__DC_FC_4 0x1E000238,0x00001000 ++#define IPU_IPU_INT_STAT_15__DC_FC_3 0x1E000238,0x00000800 ++#define IPU_IPU_INT_STAT_15__DC_FC_2 0x1E000238,0x00000400 ++#define IPU_IPU_INT_STAT_15__DC_FC_1 0x1E000238,0x00000200 ++#define IPU_IPU_INT_STAT_15__DC_FC_0 0x1E000238,0x00000100 ++#define IPU_IPU_INT_STAT_15__DP_ASF_BRAKE 0x1E000238,0x00000080 ++#define IPU_IPU_INT_STAT_15__DP_SF_BRAKE 0x1E000238,0x00000040 ++#define IPU_IPU_INT_STAT_15__DP_ASF_END 0x1E000238,0x00000020 ++#define IPU_IPU_INT_STAT_15__DP_ASF_START 0x1E000238,0x00000010 ++#define IPU_IPU_INT_STAT_15__DP_SF_END 0x1E000238,0x00000008 ++#define IPU_IPU_INT_STAT_15__DP_SF_START 0x1E000238,0x00000004 ++#define IPU_IPU_INT_STAT_15__IPU_SNOOPING2_INT 0x1E000238,0x00000002 ++#define IPU_IPU_INT_STAT_15__IPU_SNOOPING1_INT 0x1E000238,0x00000001 ++ ++#define IPU_IPU_CUR_BUF_0__ADDR 0x1E00023C ++#define IPU_IPU_CUR_BUF_0__EMPTY 0x1E00023C,0x00000000 ++#define IPU_IPU_CUR_BUF_0__FULL 0x1E00023C,0xffffffff ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_31 0x1E00023C,0x80000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_29 0x1E00023C,0x20000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_28 0x1E00023C,0x10000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_27 0x1E00023C,0x08000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_24 0x1E00023C,0x01000000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_23 0x1E00023C,0x00800000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_22 0x1E00023C,0x00400000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_21 0x1E00023C,0x00200000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_20 0x1E00023C,0x00100000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_18 0x1E00023C,0x00040000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_17 0x1E00023C,0x00020000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_15 0x1E00023C,0x00008000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_14 0x1E00023C,0x00004000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_12 0x1E00023C,0x00001000 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_11 0x1E00023C,0x00000800 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_7 0x1E00023C,0x00000080 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_6 0x1E00023C,0x00000040 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_5 0x1E00023C,0x00000020 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_4 0x1E00023C,0x00000010 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_3 0x1E00023C,0x00000008 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_2 0x1E00023C,0x00000004 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_1 0x1E00023C,0x00000002 ++#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_0 0x1E00023C,0x00000001 ++ ++#define IPU_IPU_CUR_BUF_1__ADDR 0x1E000240 ++#define IPU_IPU_CUR_BUF_1__EMPTY 0x1E000240,0x00000000 ++#define IPU_IPU_CUR_BUF_1__FULL 0x1E000240,0xffffffff ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_52 0x1E000240,0x00100000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_51 0x1E000240,0x00080000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_50 0x1E000240,0x00040000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_49 0x1E000240,0x00020000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_48 0x1E000240,0x00010000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_47 0x1E000240,0x00008000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_46 0x1E000240,0x00004000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_45 0x1E000240,0x00002000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_44 0x1E000240,0x00001000 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_43 0x1E000240,0x00000800 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_42 0x1E000240,0x00000400 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_41 0x1E000240,0x00000200 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_40 0x1E000240,0x00000100 ++#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_33 0x1E000240,0x00000002 ++ ++#define IPU_IPU_ALT_CUR_BUF_0__ADDR 0x1E000244 ++#define IPU_IPU_ALT_CUR_BUF_0__EMPTY 0x1E000244,0x00000000 ++#define IPU_IPU_ALT_CUR_BUF_0__FULL 0x1E000244,0xffffffff ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_29 0x1E000244,0x20000000 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_24 0x1E000244,0x01000000 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_7 0x1E000244,0x00000080 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_6 0x1E000244,0x00000040 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_5 0x1E000244,0x00000020 ++#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_4 0x1E000244,0x00000010 ++ ++#define IPU_IPU_ALT_CUR_BUF_1__ADDR 0x1E000248 ++#define IPU_IPU_ALT_CUR_BUF_1__EMPTY 0x1E000248,0x00000000 ++#define IPU_IPU_ALT_CUR_BUF_1__FULL 0x1E000248,0xffffffff ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_52 0x1E000248,0x00100000 ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_41 0x1E000248,0x00000200 ++#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_33 0x1E000248,0x00000002 ++ ++#define IPU_IPU_SRM_STAT__ADDR 0x1E00024C ++#define IPU_IPU_SRM_STAT__EMPTY 0x1E00024C,0x00000000 ++#define IPU_IPU_SRM_STAT__FULL 0x1E00024C,0xffffffff ++#define IPU_IPU_SRM_STAT__DI1_SRM_STAT 0x1E00024C,0x00000200 ++#define IPU_IPU_SRM_STAT__DI0_SRM_STAT 0x1E00024C,0x00000100 ++#define IPU_IPU_SRM_STAT__CSI1_SRM_STAT 0x1E00024C,0x00000080 ++#define IPU_IPU_SRM_STAT__CSI0_SRM_STAT 0x1E00024C,0x00000040 ++#define IPU_IPU_SRM_STAT__DC_6_SRM_STAT 0x1E00024C,0x00000020 ++#define IPU_IPU_SRM_STAT__DC_2_SRM_STAT 0x1E00024C,0x00000010 ++#define IPU_IPU_SRM_STAT__ISP_SRM_STAT 0x1E00024C,0x00000008 ++#define IPU_IPU_SRM_STAT__DP_A1_SRM_STAT 0x1E00024C,0x00000004 ++#define IPU_IPU_SRM_STAT__DP_A0_SRM_STAT 0x1E00024C,0x00000002 ++#define IPU_IPU_SRM_STAT__DP_S_SRM_STAT 0x1E00024C,0x00000001 ++ ++#define IPU_IPU_PROC_TASKS_STAT__ADDR 0x1E000250 ++#define IPU_IPU_PROC_TASKS_STAT__EMPTY 0x1E000250,0x00000000 ++#define IPU_IPU_PROC_TASKS_STAT__FULL 0x1E000250,0xffffffff ++#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC3_TSTAT 0x1E000250,0x00C00000 ++#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC2_TSTAT 0x1E000250,0x00300000 ++#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC1_TSTAT 0x1E000250,0x000C0000 ++#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC0_TSTAT 0x1E000250,0x00030000 ++#define IPU_IPU_PROC_TASKS_STAT__MEM2PRP_TSTAT 0x1E000250,0x00007000 ++#define IPU_IPU_PROC_TASKS_STAT__PP_ROT_TSTAT 0x1E000250,0x00000C00 ++#define IPU_IPU_PROC_TASKS_STAT__VF_ROT_TSTAT 0x1E000250,0x00000300 ++#define IPU_IPU_PROC_TASKS_STAT__ENC_ROT_TSTAT 0x1E000250,0x000000C0 ++#define IPU_IPU_PROC_TASKS_STAT__PP_TSTAT 0x1E000250,0x00000030 ++#define IPU_IPU_PROC_TASKS_STAT__VF_TSTAT 0x1E000250,0x0000000C ++#define IPU_IPU_PROC_TASKS_STAT__ENC_TSTAT 0x1E000250,0x00000003 ++ ++#define IPU_IPU_DISP_TASKS_STAT__ADDR 0x1E000254 ++#define IPU_IPU_DISP_TASKS_STAT__EMPTY 0x1E000254,0x00000000 ++#define IPU_IPU_DISP_TASKS_STAT__FULL 0x1E000254,0xffffffff ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_CUR_FLOW 0x1E000254,0x00000800 ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_STAT 0x1E000254,0x00000700 ++#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_STAT 0x1E000254,0x00000030 ++#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_CUR_FLOW 0x1E000254,0x00000008 ++#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_STAT 0x1E000254,0x00000007 ++ ++#define IPU_IPU_TRB_CUR_BUF_REG0__ADDR 0x0E000258 ++#define IPU_IPU_TRB_CUR_BUF_REG1__ADDR 0x0E00025C ++#define IPU_IPU_TRB_CUR_BUF_REG2__ADDR 0x0E000260 ++#define IPU_IPU_TRB_CUR_BUF_REG3__ADDR 0x0E000264 ++ ++#define IPU_IPU_CH_BUF0_RDY0__ADDR 0x1E000268 ++#define IPU_IPU_CH_BUF0_RDY0__EMPTY 0x1E000268,0x00000000 ++#define IPU_IPU_CH_BUF0_RDY0__FULL 0x1E000268,0xffffffff ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_31 0x1E000268,0x80000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_29 0x1E000268,0x20000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_28 0x1E000268,0x10000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_27 0x1E000268,0x08000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_24 0x1E000268,0x01000000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_23 0x1E000268,0x00800000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_22 0x1E000268,0x00400000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_21 0x1E000268,0x00200000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_20 0x1E000268,0x00100000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_18 0x1E000268,0x00040000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_17 0x1E000268,0x00020000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_15 0x1E000268,0x00008000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_14 0x1E000268,0x00004000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_12 0x1E000268,0x00001000 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_11 0x1E000268,0x00000800 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_7 0x1E000268,0x00000080 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_6 0x1E000268,0x00000040 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_5 0x1E000268,0x00000020 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_4 0x1E000268,0x00000010 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_3 0x1E000268,0x00000008 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_2 0x1E000268,0x00000004 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_1 0x1E000268,0x00000002 ++#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_0 0x1E000268,0x00000001 ++ ++#define IPU_IPU_CH_BUF0_RDY1__ADDR 0x1E00026C ++#define IPU_IPU_CH_BUF0_RDY1__EMPTY 0x1E00026C,0x00000000 ++#define IPU_IPU_CH_BUF0_RDY1__FULL 0x1E00026C,0xffffffff ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_52 0x1E00026C,0x00100000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_51 0x1E00026C,0x00080000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_50 0x1E00026C,0x00040000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_49 0x1E00026C,0x00020000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_48 0x1E00026C,0x00010000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_47 0x1E00026C,0x00008000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_46 0x1E00026C,0x00004000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_45 0x1E00026C,0x00002000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_44 0x1E00026C,0x00001000 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_43 0x1E00026C,0x00000800 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_42 0x1E00026C,0x00000400 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_41 0x1E00026C,0x00000200 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_40 0x1E00026C,0x00000100 ++#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_33 0x1E00026C,0x00000002 ++ ++#define IPU_IPU_CH_BUF1_RDY0__ADDR 0x1E000270 ++#define IPU_IPU_CH_BUF1_RDY0__EMPTY 0x1E000270,0x00000000 ++#define IPU_IPU_CH_BUF1_RDY0__FULL 0x1E000270,0xffffffff ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_31 0x1E000270,0x80000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_29 0x1E000270,0x20000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_28 0x1E000270,0x10000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_27 0x1E000270,0x08000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_24 0x1E000270,0x01000000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_23 0x1E000270,0x00800000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_22 0x1E000270,0x00400000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_21 0x1E000270,0x00200000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_20 0x1E000270,0x00100000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_18 0x1E000270,0x00040000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_17 0x1E000270,0x00020000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_15 0x1E000270,0x00008000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_14 0x1E000270,0x00004000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_12 0x1E000270,0x00001000 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_11 0x1E000270,0x00000800 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_7 0x1E000270,0x00000080 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_6 0x1E000270,0x00000040 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_5 0x1E000270,0x00000020 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_4 0x1E000270,0x00000010 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_3 0x1E000270,0x00000008 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_2 0x1E000270,0x00000004 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_1 0x1E000270,0x00000002 ++#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_0 0x1E000270,0x00000001 ++ ++#define IPU_IPU_CH_BUF1_RDY1__ADDR 0x1E000274 ++#define IPU_IPU_CH_BUF1_RDY1__EMPTY 0x1E000274,0x00000000 ++#define IPU_IPU_CH_BUF1_RDY1__FULL 0x1E000274,0xffffffff ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_52 0x1E000274,0x00100000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_51 0x1E000274,0x00080000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_50 0x1E000274,0x00040000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_49 0x1E000274,0x00020000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_48 0x1E000274,0x00010000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_47 0x1E000274,0x00008000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_46 0x1E000274,0x00004000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_45 0x1E000274,0x00002000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_44 0x1E000274,0x00001000 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_43 0x1E000274,0x00000800 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_42 0x1E000274,0x00000400 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_41 0x1E000274,0x00000200 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_40 0x1E000274,0x00000100 ++#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_33 0x1E000274,0x00000002 ++ ++#define IPU_IPU_ALT_CH_BUF0_RDY0__ADDR 0x1E000278 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__EMPTY 0x1E000278,0x00000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__FULL 0x1E000278,0xffffffff ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_29 0x1E000278,0x20000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_24 0x1E000278,0x01000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_7 0x1E000278,0x00000080 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_6 0x1E000278,0x00000040 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_5 0x1E000278,0x00000020 ++#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_4 0x1E000278,0x00000010 ++ ++#define IPU_IPU_ALT_CH_BUF0_RDY1__ADDR 0x1E00027C ++#define IPU_IPU_ALT_CH_BUF0_RDY1__EMPTY 0x1E00027C,0x00000000 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__FULL 0x1E00027C,0xffffffff ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_52 0x1E00027C,0x00100000 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_41 0x1E00027C,0x00000200 ++#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_33 0x1E00027C,0x00000002 ++ ++#define IPU_IPU_ALT_CH_BUF1_RDY0__ADDR 0x1E000280 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__EMPTY 0x1E000280,0x00000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__FULL 0x1E000280,0xffffffff ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_29 0x1E000280,0x20000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_24 0x1E000280,0x01000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_7 0x1E000280,0x00000080 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_6 0x1E000280,0x00000040 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_5 0x1E000280,0x00000020 ++#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_4 0x1E000280,0x00000010 ++ ++#define IPU_IPU_ALT_CH_BUF1_RDY1__ADDR 0x1E000284 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__EMPTY 0x1E000284,0x00000000 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__FULL 0x1E000284,0xffffffff ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_52 0x1E000284,0x00100000 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_41 0x1E000284,0x00000200 ++#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_33 0x1E000284,0x00000002 ++ ++#define IPU_IPU_CH_BUF2_RDY0__ADDR 0x1E000288 ++#define IPU_IPU_CH_BUF2_RDY1__ADDR 0x1E00028C ++ ++// ================== End of IPUV3EX Status Registers ====================== ++ ++// ================= Start of IPUV3EX IDMAC Registers ===================== ++#define IPU_IDMAC_CONF__ADDR 0x1E008000 ++#define IPU_IDMAC_CONF__EMPTY 0x1E008000,0x00000000 ++#define IPU_IDMAC_CONF__FULL 0x1E008000,0xffffffff ++#define IPU_IDMAC_CONF__P_ENDIAN 0x1E008000,0x00010000 ++#define IPU_IDMAC_CONF__RDI 0x1E008000,0x00000020 ++#define IPU_IDMAC_CONF__WIDPT 0x1E008000,0x00000018 ++#define IPU_IDMAC_CONF__MAX_REQ_READ 0x1E008000,0x00000007 ++ ++#define IPU_IDMAC_CH_EN_1__ADDR 0x1E008004 ++#define IPU_IDMAC_CH_EN_1__EMPTY 0x1E008004,0x00000000 ++#define IPU_IDMAC_CH_EN_1__FULL 0x1E008004,0xffffffff ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1E008004,0x80000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1E008004,0x20000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1E008004,0x10000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1E008004,0x08000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1E008004,0x01000000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1E008004,0x00800000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1E008004,0x00400000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1E008004,0x00200000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1E008004,0x00100000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1E008004,0x00040000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1E008004,0x00020000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1E008004,0x00008000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1E008004,0x00004000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1E008004,0x00001000 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1E008004,0x00000800 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_7 0x1E008004,0x00000080 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_6 0x1E008004,0x00000040 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_5 0x1E008004,0x00000020 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_4 0x1E008004,0x00000010 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_3 0x1E008004,0x00000008 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_2 0x1E008004,0x00000004 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_1 0x1E008004,0x00000002 ++#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_0 0x1E008004,0x00000001 ++ ++#define IPU_IDMAC_CH_EN_2__ADDR 0x1E008008 ++#define IPU_IDMAC_CH_EN_2__EMPTY 0x1E008008,0x00000000 ++#define IPU_IDMAC_CH_EN_2__FULL 0x1E008008,0xffffffff ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1E008008,0x00100000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1E008008,0x00080000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1E008008,0x00040000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1E008008,0x00020000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1E008008,0x00010000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1E008008,0x00008000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1E008008,0x00004000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1E008008,0x00002000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1E008008,0x00001000 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1E008008,0x00000800 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1E008008,0x00000400 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1E008008,0x00000200 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1E008008,0x00000100 ++#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1E008008,0x00000002 ++ ++#define IPU_IDMAC_SEP_ALPHA__ADDR 0x1E00800C ++#define IPU_IDMAC_SEP_ALPHA__EMPTY 0x1E00800C,0x00000000 ++#define IPU_IDMAC_SEP_ALPHA__FULL 0x1E00800C,0xffffffff ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1E00800C,0x20000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1E00800C,0x08000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1E00800C,0x01000000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1E00800C,0x00800000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1E00800C,0x00008000 ++#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1E00800C,0x00004000 ++ ++#define IPU_IDMAC_ALT_SEP_ALPHA__ADDR 0x1E008010 ++#define IPU_IDMAC_ALT_SEP_ALPHA__EMPTY 0x1E008010,0x00000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__FULL 0x1E008010,0xffffffff ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1E008010,0x20000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1E008010,0x01000000 ++#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1E008010,0x00800000 ++ ++#define IPU_IDMAC_CH_PRI_1__ADDR 0x1E008014 ++#define IPU_IDMAC_CH_PRI_1__EMPTY 0x1E008014,0x00000000 ++#define IPU_IDMAC_CH_PRI_1__FULL 0x1E008014,0xffffffff ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1E008014,0x20000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1E008014,0x10000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1E008014,0x08000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1E008014,0x01000000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1E008014,0x00800000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1E008014,0x00400000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1E008014,0x00200000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1E008014,0x00100000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1E008014,0x00008000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1E008014,0x00004000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1E008014,0x00001000 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1E008014,0x00000800 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7 0x1E008014,0x00000080 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6 0x1E008014,0x00000040 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5 0x1E008014,0x00000020 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4 0x1E008014,0x00000010 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3 0x1E008014,0x00000008 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2 0x1E008014,0x00000004 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1 0x1E008014,0x00000002 ++#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0 0x1E008014,0x00000001 ++ ++#define IPU_IDMAC_CH_PRI_2__ADDR 0x1E008018 ++#define IPU_IDMAC_CH_PRI_2__EMPTY 0x1E008018,0x00000000 ++#define IPU_IDMAC_CH_PRI_2__FULL 0x1E008018,0xffffffff ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1E008018,0x00040000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1E008018,0x00020000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1E008018,0x00010000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1E008018,0x00008000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1E008018,0x00004000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1E008018,0x00002000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1E008018,0x00001000 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1E008018,0x00000800 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1E008018,0x00000400 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1E008018,0x00000200 ++#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1E008018,0x00000100 ++ ++#define IPU_IDMAC_WM_EN_1__ADDR 0x1E00801C ++#define IPU_IDMAC_WM_EN_1__EMPTY 0x1E00801C,0x00000000 ++#define IPU_IDMAC_WM_EN_1__FULL 0x1E00801C,0xffffffff ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1E00801C,0x20000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1E00801C,0x10000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1E00801C,0x08000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1E00801C,0x01000000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1E00801C,0x00800000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1E00801C,0x00004000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1E00801C,0x00001000 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_3 0x1E00801C,0x00000008 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_2 0x1E00801C,0x00000004 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_1 0x1E00801C,0x00000002 ++#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_0 0x1E00801C,0x00000001 ++ ++#define IPU_IDMAC_WM_EN_2__ADDR 0x1E008020 ++#define IPU_IDMAC_WM_EN_2__EMPTY 0x1E008020,0x00000000 ++#define IPU_IDMAC_WM_EN_2__FULL 0x1E008020,0xffffffff ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1E008020,0x00001000 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1E008020,0x00000800 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1E008020,0x00000400 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1E008020,0x00000200 ++#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1E008020,0x00000100 ++ ++#define IPU_IDMAC_LOCK_EN_1__ADDR 0x1E008024 ++ ++#define IPU_IDMAC_LOCK_EN_2__ADDR 0x1E008028 ++#define IPU_IDMAC_LOCK_EN_2__EMPTY 0x1E008028,0x00000000 ++#define IPU_IDMAC_LOCK_EN_2__FULL 0x1E008028,0xffffffff ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1E008028,0x00040000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1E008028,0x00020000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1E008028,0x00010000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1E008028,0x00008000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1E008028,0x00004000 ++#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1E008028,0x00002000 ++ ++#define IPU_IDMAC_SUB_ADDR_0__ADDR 0x1E00802C ++#define IPU_IDMAC_SUB_ADDR_0__EMPTY 0x1E00802C,0x00000000 ++#define IPU_IDMAC_SUB_ADDR_0__FULL 0x1E00802C,0xffffffff ++#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7 0x1E00802C,0x7F000000 ++#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6 0x1E00802C,0x007F0000 ++#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5 0x1E00802C,0x00007F00 ++#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4 0x1E00802C,0x0000007F ++ ++#define IPU_IDMAC_SUB_ADDR_1__ADDR 0x1E008030 ++#define IPU_IDMAC_SUB_ADDR_1__EMPTY 0x1E008030,0x00000000 ++#define IPU_IDMAC_SUB_ADDR_1__FULL 0x1E008030,0xffffffff ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1E008030,0x7F000000 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1E008030,0x007F0000 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1E008030,0x00007F00 ++#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1E008030,0x0000007F ++ ++#define IPU_IDMAC_SUB_ADDR_2__ADDR 0x1E008034 ++#define IPU_IDMAC_SUB_ADDR_2__EMPTY 0x1E008034,0x00000000 ++#define IPU_IDMAC_SUB_ADDR_2__FULL 0x1E008034,0xffffffff ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1E008034,0x007F0000 ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1E008034,0x00007F00 ++#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1E008034,0x0000007F ++ ++#define IPU_IDMAC_SUB_ADDR_3__ADDR 0x1E008038 ++#define IPU_IDMAC_SUB_ADDR_4__ADDR 0x1E00803C ++ ++#define IPU_IDMAC_BNDM_EN_1__ADDR 0x1E008040 ++#define IPU_IDMAC_BNDM_EN_1__EMPTY 0x1E008040,0x00000000 ++#define IPU_IDMAC_BNDM_EN_1__FULL 0x1E008040,0xffffffff ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1E008040,0x00400000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1E008040,0x00200000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1E008040,0x00100000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1E008040,0x00001000 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1E008040,0x00000800 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5 0x1E008040,0x00000020 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3 0x1E008040,0x00000008 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2 0x1E008040,0x00000004 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1 0x1E008040,0x00000002 ++#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0 0x1E008040,0x00000001 ++ ++#define IPU_IDMAC_BNDM_EN_2__ADDR 0x1E008044 ++#define IPU_IDMAC_BNDM_EN_2__EMPTY 0x1E008044,0x00000000 ++#define IPU_IDMAC_BNDM_EN_2__FULL 0x1E008044,0xffffffff ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1E008044,0x00040000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1E008044,0x00020000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1E008044,0x00010000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1E008044,0x00008000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1E008044,0x00004000 ++#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1E008044,0x00002000 ++ ++#define IPU_IDMAC_SC_CORD__ADDR 0x1E008048 ++#define IPU_IDMAC_SC_CORD__EMPTY 0x1E008048,0x00000000 ++#define IPU_IDMAC_SC_CORD__FULL 0x1E008048,0xffffffff ++#define IPU_IDMAC_SC_CORD__SX0 0x1E008048,0x0FFF0000 ++#define IPU_IDMAC_SC_CORD__SY0 0x1E008048,0x000007FF ++ ++#define IPU_IDMAC_SC_CORD2__ADDR 0x1E00804C ++ ++#define IPU_IDMAC_CH_BUSY_1__ADDR 0x1E008100 ++#define IPU_IDMAC_CH_BUSY_1__EMPTY 0x1E008100,0x00000000 ++#define IPU_IDMAC_CH_BUSY_1__FULL 0x1E008100,0xffffffff ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_31 0x1E008100,0x80000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_29 0x1E008100,0x20000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_28 0x1E008100,0x10000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_27 0x1E008100,0x08000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_24 0x1E008100,0x01000000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_23 0x1E008100,0x00800000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_22 0x1E008100,0x00400000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_21 0x1E008100,0x00200000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_20 0x1E008100,0x00100000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_18 0x1E008100,0x00040000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_17 0x1E008100,0x00020000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_15 0x1E008100,0x00008000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_14 0x1E008100,0x00004000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_12 0x1E008100,0x00001000 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_11 0x1E008100,0x00000800 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_7 0x1E008100,0x00000080 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_6 0x1E008100,0x00000040 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_5 0x1E008100,0x00000020 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_4 0x1E008100,0x00000010 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_3 0x1E008100,0x00000008 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_2 0x1E008100,0x00000004 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_1 0x1E008100,0x00000002 ++#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_0 0x1E008100,0x00000001 ++ ++#define IPU_IDMAC_CH_BUSY_2__ADDR 0x1E008104 ++#define IPU_IDMAC_CH_BUSY_2__EMPTY 0x1E008104,0x00000000 ++#define IPU_IDMAC_CH_BUSY_2__FULL 0x1E008104,0xffffffff ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_52 0x1E008104,0x00100000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_51 0x1E008104,0x00080000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_50 0x1E008104,0x00040000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_49 0x1E008104,0x00020000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_48 0x1E008104,0x00010000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_47 0x1E008104,0x00008000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_46 0x1E008104,0x00004000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_45 0x1E008104,0x00002000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_44 0x1E008104,0x00001000 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_43 0x1E008104,0x00000800 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_42 0x1E008104,0x00000400 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_41 0x1E008104,0x00000200 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_40 0x1E008104,0x00000100 ++#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_33 0x1E008104,0x00000002 ++ ++// ================== End of IPUV3EX IDMAC Registers ====================== ++ ++// ================= Start of IPUV3EX ISP Registers ===================== ++#define IPU_ISP_C0__ADDR 0x1E010000 ++#define IPU_ISP_C0__EMPTY 0x1E010000,0x00000000 ++#define IPU_ISP_C0__FULL 0x1E010000,0xffffffff ++#define IPU_ISP_C0__ISP_BURST_SIZE 0x1E010000,0x001C0000 ++#define IPU_ISP_C0__ISP_RED_ROW_BEGIN 0x1E010000,0x00020000 ++#define IPU_ISP_C0__ISP_GREEN_P_BEGIN 0x1E010000,0x00010000 ++#define IPU_ISP_C0__LINEARCCM_ON 0x1E010000,0x00004000 ++#define IPU_ISP_C0__LLF_G_EN 0x1E010000,0x00002000 ++#define IPU_ISP_C0__LLF_RB_EN 0x1E010000,0x00001000 ++#define IPU_ISP_C0__AD_EN 0x1E010000,0x00000800 ++#define IPU_ISP_C0__STS_EN 0x1E010000,0x00000400 ++#define IPU_ISP_C0__CL_EN 0x1E010000,0x00000200 ++#define IPU_ISP_C0__CS_EN 0x1E010000,0x00000100 ++#define IPU_ISP_C0__CCA_EN 0x1E010000,0x00000080 ++#define IPU_ISP_C0__HFE_EN 0x1E010000,0x00000040 ++#define IPU_ISP_C0__CNS_EN 0x1E010000,0x00000020 ++#define IPU_ISP_C0__MTF_ROC_EN 0x1E010000,0x00000010 ++#define IPU_ISP_C0__GAMMA_EN 0x1E010000,0x00000008 ++#define IPU_ISP_C0__CROC_EN 0x1E010000,0x00000004 ++#define IPU_ISP_C0__TBPR_EN 0x1E010000,0x00000002 ++#define IPU_ISP_C0__BPR_EN 0x1E010000,0x00000001 ++ ++#define IPU_ISP_C1__ADDR 0x1E010004 ++#define IPU_ISP_C1__EMPTY 0x1E010004,0x00000000 ++#define IPU_ISP_C1__FULL 0x1E010004,0xffffffff ++#define IPU_ISP_C1__YUV_EN 0x1E010004,0x20000000 ++#define IPU_ISP_C1__CSC_SAT_MODE 0x1E010004,0x10000000 ++#define IPU_ISP_C1__BOTTOM_CROP 0x1E010004,0x0E000000 ++#define IPU_ISP_C1__TOP_CROP 0x1E010004,0x01C00000 ++#define IPU_ISP_C1__RIGHT_CROP 0x1E010004,0x00380000 ++#define IPU_ISP_C1__LEFT_CROP 0x1E010004,0x00070000 ++#define IPU_ISP_C1__MTF_ROC_SH_M 0x1E010004,0x00006000 ++#define IPU_ISP_C1__MTF_ROC_SH_N 0x1E010004,0x00001800 ++#define IPU_ISP_C1__MTF_ROC_SH_QA 0x1E010004,0x00000700 ++#define IPU_ISP_C1__MTF_ROC_SH_SHARP 0x1E010004,0x000000E0 ++#define IPU_ISP_C1__WIDEASPECT 0x1E010004,0x00000010 ++#define IPU_ISP_C1__APP_SEL 0x1E010004,0x0000000C ++#define IPU_ISP_C1__INT_MODE 0x1E010004,0x00000003 ++ ++#define IPU_ISP_FS__ADDR 0x1E010008 ++#define IPU_ISP_FS__EMPTY 0x1E010008,0x00000000 ++#define IPU_ISP_FS__FULL 0x1E010008,0xffffffff ++#define IPU_ISP_FS__FWIDTH 0x1E010008,0x0FFF0000 ++#define IPU_ISP_FS__FHEIGHT 0x1E010008,0x00000FFF ++ ++#define IPU_ISP_BI__ADDR 0x1E01000C ++#define IPU_ISP_BI__EMPTY 0x1E01000C,0x00000000 ++#define IPU_ISP_BI__FULL 0x1E01000C,0xffffffff ++#define IPU_ISP_BI__HBLANK 0x1E01000C,0x0FFF0000 ++#define IPU_ISP_BI__VBLANK 0x1E01000C,0x00000FFF ++ ++#define IPU_ISP_OCO__ADDR 0x1E010010 ++#define IPU_ISP_OCO__EMPTY 0x1E010010,0x00000000 ++#define IPU_ISP_OCO__FULL 0x1E010010,0xffffffff ++#define IPU_ISP_OCO__HOFFSET 0x1E010010,0x1FFF0000 ++#define IPU_ISP_OCO__VOFFSET 0x1E010010,0x00001FFF ++ ++#define IPU_ISP_BPR1__ADDR 0x1E010014 ++#define IPU_ISP_BPR1__EMPTY 0x1E010014,0x00000000 ++#define IPU_ISP_BPR1__FULL 0x1E010014,0xffffffff ++#define IPU_ISP_BPR1__TB 0x1E010014,0xFF000000 ++#define IPU_ISP_BPR1__TDR 0x1E010014,0x00FF0000 ++#define IPU_ISP_BPR1__TR 0x1E010014,0x0000FF00 ++#define IPU_ISP_BPR1__DKR 0x1E010014,0x000000FF ++ ++#define IPU_ISP_BPR2__ADDR 0x1E010018 ++#define IPU_ISP_BPR2__EMPTY 0x1E010018,0x00000000 ++#define IPU_ISP_BPR2__FULL 0x1E010018,0xffffffff ++#define IPU_ISP_BPR2__BRB 0x1E010018,0xFF000000 ++#define IPU_ISP_BPR2__TT 0x1E010018,0x00FF0000 ++#define IPU_ISP_BPR2__TVDB 0x1E010018,0x0000FF00 ++#define IPU_ISP_BPR2__TDB 0x1E010018,0x000000FF ++ ++#define IPU_ISP_BPR3__ADDR 0x1E01001C ++#define IPU_ISP_BPR3__EMPTY 0x1E01001C,0x00000000 ++#define IPU_ISP_BPR3__FULL 0x1E01001C,0xffffffff ++#define IPU_ISP_BPR3__TG 0x1E01001C,0xFF000000 ++#define IPU_ISP_BPR3__TGF 0x1E01001C,0x00FF0000 ++#define IPU_ISP_BPR3__DKB 0x1E01001C,0x0000FF00 ++#define IPU_ISP_BPR3__TG2 0x1E01001C,0x000000FF ++ ++#define IPU_ISP_BPR4__ADDR 0x1E010020 ++#define IPU_ISP_BPR4__EMPTY 0x1E010020,0x00000000 ++#define IPU_ISP_BPR4__FULL 0x1E010020,0xffffffff ++#define IPU_ISP_BPR4__DKRCL 0x1E010020,0xFF000000 ++#define IPU_ISP_BPR4__TGFCL 0x1E010020,0x00FF0000 ++#define IPU_ISP_BPR4__TCL2 0x1E010020,0x0000FF00 ++#define IPU_ISP_BPR4__TCL 0x1E010020,0x000000FF ++ ++#define IPU_ISP_BPR5__ADDR 0x1E010024 ++#define IPU_ISP_BPR5__EMPTY 0x1E010024,0x00000000 ++#define IPU_ISP_BPR5__FULL 0x1E010024,0xffffffff ++#define IPU_ISP_BPR5__TGL2 0x1E010024,0x0000FF00 ++#define IPU_ISP_BPR5__TBC 0x1E010024,0x000000FF ++ ++#define IPU_ISP_CCMLIN0__ADDR 0x1E010028 ++#define IPU_ISP_CCMLIN0__EMPTY 0x1E010028,0x00000000 ++#define IPU_ISP_CCMLIN0__FULL 0x1E010028,0xffffffff ++#define IPU_ISP_CCMLIN0__CCMLIN12 0x1E010028,0x7C000000 ++#define IPU_ISP_CCMLIN0__CCMLIN11 0x1E010028,0x03E00000 ++#define IPU_ISP_CCMLIN0__CCMLIN10 0x1E010028,0x001F0000 ++#define IPU_ISP_CCMLIN0__CCMLIN02 0x1E010028,0x00007C00 ++#define IPU_ISP_CCMLIN0__CCMLIN01 0x1E010028,0x000003E0 ++#define IPU_ISP_CCMLIN0__CCMLIN00 0x1E010028,0x0000001F ++ ++#define IPU_ISP_CCMLIN1__ADDR 0x1E01002C ++#define IPU_ISP_CCMLIN1__EMPTY 0x1E01002C,0x00000000 ++#define IPU_ISP_CCMLIN1__FULL 0x1E01002C,0xffffffff ++#define IPU_ISP_CCMLIN1__CCMLIN22 0x1E01002C,0x00007C00 ++#define IPU_ISP_CCMLIN1__CCMLIN21 0x1E01002C,0x000003E0 ++#define IPU_ISP_CCMLIN1__CCMLIN20 0x1E01002C,0x0000001F ++ ++#define IPU_ISP_CG_0__ADDR 0x1E010030 ++#define IPU_ISP_CG_0__EMPTY 0x1E010030,0x00000000 ++#define IPU_ISP_CG_0__FULL 0x1E010030,0xffffffff ++#define IPU_ISP_CG_0__BGAIN 0x1E010030,0xFF000000 ++#define IPU_ISP_CG_0__GBGAIN 0x1E010030,0x00FF0000 ++#define IPU_ISP_CG_0__GRGAIN 0x1E010030,0x0000FF00 ++#define IPU_ISP_CG_0__RGAIN 0x1E010030,0x000000FF ++ ++#define IPU_ISP_CG_1__ADDR 0x1E010034 ++#define IPU_ISP_CG_1__EMPTY 0x1E010034,0x00000000 ++#define IPU_ISP_CG_1__FULL 0x1E010034,0xffffffff ++#define IPU_ISP_CG_1__BSHIFT 0x1E010034,0x00000030 ++#define IPU_ISP_CG_1__GSHIFT 0x1E010034,0x0000000C ++#define IPU_ISP_CG_1__RSHIFT 0x1E010034,0x00000003 ++ ++#define IPU_ISP_ROC_0__ADDR 0x1E010038 ++#define IPU_ISP_ROC_0__EMPTY 0x1E010038,0x00000000 ++#define IPU_ISP_ROC_0__FULL 0x1E010038,0xffffffff ++#define IPU_ISP_ROC_0__CROC_Q_BLIN 0x1E010038,0x01C00000 ++#define IPU_ISP_ROC_0__CROC_Q_GLIN 0x1E010038,0x00380000 ++#define IPU_ISP_ROC_0__CROC_Q_RLIN 0x1E010038,0x00070000 ++#define IPU_ISP_ROC_0__CROC_SH_QR 0x1E010038,0x00007000 ++#define IPU_ISP_ROC_0__CROC_SH_QRGB 0x1E010038,0x00000E00 ++#define IPU_ISP_ROC_0__CROC_SH_QB 0x1E010038,0x000001C0 ++#define IPU_ISP_ROC_0__CROC_R_APP 0x1E010038,0x00000030 ++#define IPU_ISP_ROC_0__CROC_G_APP 0x1E010038,0x0000000C ++#define IPU_ISP_ROC_0__CROC_B_APP 0x1E010038,0x00000003 ++ ++#define IPU_ISP_ROC_1__ADDR 0x1E01003C ++#define IPU_ISP_ROC_1__EMPTY 0x1E01003C,0x00000000 ++#define IPU_ISP_ROC_1__FULL 0x1E01003C,0xffffffff ++#define IPU_ISP_ROC_1__CROC_MYB 0x1E01003C,0xFF000000 ++#define IPU_ISP_ROC_1__CROC_MXB 0x1E01003C,0x00FF0000 ++#define IPU_ISP_ROC_1__CROC_MYG 0x1E01003C,0x0000FF00 ++#define IPU_ISP_ROC_1__CROC_MXG 0x1E01003C,0x000000FF ++ ++#define IPU_ISP_ROC_2__ADDR 0x1E010040 ++#define IPU_ISP_ROC_2__EMPTY 0x1E010040,0x00000000 ++#define IPU_ISP_ROC_2__FULL 0x1E010040,0xffffffff ++#define IPU_ISP_ROC_2__CROC_MYR 0x1E010040,0x0000FF00 ++#define IPU_ISP_ROC_2__CROC_MXR 0x1E010040,0x000000FF ++ ++#define IPU_ISP_ROC_3__ADDR 0x1E010044 ++ ++/*not all IPS regs defined here*/ ++// ================= End of IPUV3EX ISP Registers ===================== ++ ++// ================= Start of IPUV3EX DP Registers ===================== ++#define IPU_DP_COM_CONF_SYNC__ADDR 0x1E018000 ++#define IPU_DP_COM_CONF_SYNC__EMPTY 0x1E018000,0x00000000 ++#define IPU_DP_COM_CONF_SYNC__FULL 0x1E018000,0xffffffff ++#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC 0x1E018000,0x00002000 ++#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC 0x1E018000,0x00001000 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1E018000,0x00000800 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1E018000,0x00000400 ++#define IPU_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC 0x1E018000,0x00000300 ++#define IPU_DP_COM_CONF_SYNC__DP_COC_SYNC 0x1E018000,0x00000070 ++#define IPU_DP_COM_CONF_SYNC__DP_GWCKE_SYNC 0x1E018000,0x00000008 ++#define IPU_DP_COM_CONF_SYNC__DP_GWAM_SYNC 0x1E018000,0x00000004 ++#define IPU_DP_COM_CONF_SYNC__DP_GWSEL_SYNC 0x1E018000,0x00000002 ++#define IPU_DP_COM_CONF_SYNC__DP_FG_EN_SYNC 0x1E018000,0x00000001 ++ ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__ADDR 0x1E018004 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__EMPTY 0x1E018004,0x00000000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__FULL 0x1E018004,0xffffffff ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC 0x1E018004,0xFF000000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1E018004,0x00FF0000 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1E018004,0x0000FF00 ++#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1E018004,0x000000FF ++ ++#define IPU_DP_FG_POS_SYNC__ADDR 0x1E018008 ++#define IPU_DP_FG_POS_SYNC__EMPTY 0x1E018008,0x00000000 ++#define IPU_DP_FG_POS_SYNC__FULL 0x1E018008,0xffffffff ++#define IPU_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1E018008,0x07FF0000 ++#define IPU_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1E018008,0x000007FF ++ ++#define IPU_DP_CUR_POS_SYNC__ADDR 0x1E01800C ++#define IPU_DP_CUR_POS_SYNC__EMPTY 0x1E01800C,0x00000000 ++#define IPU_DP_CUR_POS_SYNC__FULL 0x1E01800C,0xffffffff ++#define IPU_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1E01800C,0xF8000000 ++#define IPU_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1E01800C,0x07FF0000 ++#define IPU_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1E01800C,0x0000F800 ++#define IPU_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1E01800C,0x000007FF ++ ++#define IPU_DP_CUR_MAP_SYNC__ADDR 0x1E018010 ++#define IPU_DP_CUR_MAP_SYNC__EMPTY 0x1E018010,0x00000000 ++#define IPU_DP_CUR_MAP_SYNC__FULL 0x1E018010,0xffffffff ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1E018010,0x00FF0000 ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1E018010,0x0000FF00 ++#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1E018010,0x000000FF ++ ++#define IPU_DP_GAMMA_C_SYNC_0__ADDR 0x1E018014 ++#define IPU_DP_GAMMA_C_SYNC_0__EMPTY 0x1E018014,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_0__FULL 0x1E018014,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1E018014,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1E018014,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_1__ADDR 0x1E018018 ++#define IPU_DP_GAMMA_C_SYNC_1__EMPTY 0x1E018018,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_1__FULL 0x1E018018,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1E018018,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1E018018,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_2__ADDR 0x1E01801C ++#define IPU_DP_GAMMA_C_SYNC_2__EMPTY 0x1E01801C,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_2__FULL 0x1E01801C,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1E01801C,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1E01801C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_3__ADDR 0x1E018020 ++#define IPU_DP_GAMMA_C_SYNC_3__EMPTY 0x1E018020,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_3__FULL 0x1E018020,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1E018020,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1E018020,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_4__ADDR 0x1E018024 ++#define IPU_DP_GAMMA_C_SYNC_4__EMPTY 0x1E018024,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_4__FULL 0x1E018024,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1E018024,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1E018024,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_5__ADDR 0x1E018028 ++#define IPU_DP_GAMMA_C_SYNC_5__EMPTY 0x1E018028,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_5__FULL 0x1E018028,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1E018028,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1E018028,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_6__ADDR 0x1E01802C ++#define IPU_DP_GAMMA_C_SYNC_6__EMPTY 0x1E01802C,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_6__FULL 0x1E01802C,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1E01802C,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1E01802C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_SYNC_7__ADDR 0x1E018030 ++#define IPU_DP_GAMMA_C_SYNC_7__EMPTY 0x1E018030,0x00000000 ++#define IPU_DP_GAMMA_C_SYNC_7__FULL 0x1E018030,0xffffffff ++#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1E018030,0x01FF0000 ++#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1E018030,0x000001FF ++ ++#define IPU_DP_GAMMA_S_SYNC_0__ADDR 0x1E018034 ++#define IPU_DP_GAMMA_S_SYNC_0__EMPTY 0x1E018034,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_0__FULL 0x1E018034,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1E018034,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1E018034,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1E018034,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1E018034,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_1__ADDR 0x1E018038 ++#define IPU_DP_GAMMA_S_SYNC_1__EMPTY 0x1E018038,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_1__FULL 0x1E018038,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1E018038,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1E018038,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1E018038,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1E018038,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_2__ADDR 0x1E01803C ++#define IPU_DP_GAMMA_S_SYNC_2__EMPTY 0x1E01803C,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_2__FULL 0x1E01803C,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1E01803C,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1E01803C,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9 0x1E01803C,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8 0x1E01803C,0x000000FF ++ ++#define IPU_DP_GAMMA_S_SYNC_3__ADDR 0x1E018040 ++#define IPU_DP_GAMMA_S_SYNC_3__EMPTY 0x1E018040,0x00000000 ++#define IPU_DP_GAMMA_S_SYNC_3__FULL 0x1E018040,0xffffffff ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1E018040,0xFF000000 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1E018040,0x00FF0000 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1E018040,0x0000FF00 ++#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1E018040,0x000000FF ++ ++#define IPU_DP_CSCA_SYNC_0__ADDR 0x1E018044 ++#define IPU_DP_CSCA_SYNC_0__EMPTY 0x1E018044,0x00000000 ++#define IPU_DP_CSCA_SYNC_0__FULL 0x1E018044,0xffffffff ++#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1E018044,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1E018044,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_1__ADDR 0x1E018048 ++#define IPU_DP_CSCA_SYNC_1__EMPTY 0x1E018048,0x00000000 ++#define IPU_DP_CSCA_SYNC_1__FULL 0x1E018048,0xffffffff ++#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1E018048,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1E018048,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_2__ADDR 0x1E01804C ++#define IPU_DP_CSCA_SYNC_2__EMPTY 0x1E01804C,0x00000000 ++#define IPU_DP_CSCA_SYNC_2__FULL 0x1E01804C,0xffffffff ++#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1E01804C,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1E01804C,0x000003FF ++ ++#define IPU_DP_CSCA_SYNC_3__ADDR 0x1E018050 ++#define IPU_DP_CSCA_SYNC_3__EMPTY 0x1E018050,0x00000000 ++#define IPU_DP_CSCA_SYNC_3__FULL 0x1E018050,0xffffffff ++#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1E018050,0x03FF0000 ++#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1E018050,0x000003FF ++ ++#define IPU_DP_CSC_SYNC_0__ADDR 0x1E018054 ++#define IPU_DP_CSC_SYNC_0__EMPTY 0x1E018054,0x00000000 ++#define IPU_DP_CSC_SYNC_0__FULL 0x1E018054,0xffffffff ++#define IPU_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1E018054,0xC0000000 ++#define IPU_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1E018054,0x3FFF0000 ++#define IPU_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1E018054,0x000003FF ++ ++#define IPU_DP_CSC_SYNC_1__ADDR 0x1E018058 ++#define IPU_DP_CSC_SYNC_1__EMPTY 0x1E018058,0x00000000 ++#define IPU_DP_CSC_SYNC_1__FULL 0x1E018058,0xffffffff ++#define IPU_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1E018058,0xC0000000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1E018058,0x3FFF0000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1E018058,0x0000C000 ++#define IPU_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1E018058,0x00003FFF ++ ++#define IPU_DP_CUR_POS_ALT__ADDR 0x1E01805C ++#define IPU_DP_CUR_POS_ALT__EMPTY 0x1E01805C,0x00000000 ++#define IPU_DP_CUR_POS_ALT__FULL 0x1E01805C,0xffffffff ++#define IPU_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1E01805C,0xF8000000 ++#define IPU_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1E01805C,0x07FF0000 ++#define IPU_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1E01805C,0x0000F800 ++#define IPU_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1E01805C,0x000007FF ++ ++#define IPU_DP_COM_CONF_ASYNC__ADDR 0x1E018060 ++#define IPU_DP_COM_CONF_ASYNC__EMPTY 0x1E018060,0x00000000 ++#define IPU_DP_COM_CONF_ASYNC__FULL 0x1E018060,0xffffffff ++#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_YUV_EN_ASYNC 0x1E018060,0x00002000 ++#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_EN_ASYNC 0x1E018060,0x00001000 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_YUV_SAT_MODE_ASYNC 0x1E018060,0x00000800 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_GAMUT_SAT_EN_ASYNC 0x1E018060,0x00000400 ++#define IPU_DP_COM_CONF_ASYNC__DP_CSC_DEF_ASYNC 0x1E018060,0x00000300 ++#define IPU_DP_COM_CONF_ASYNC__DP_COC_ASYNC 0x1E018060,0x00000070 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWCKE_ASYNC 0x1E018060,0x00000008 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWAM_ASYNC 0x1E018060,0x00000004 ++#define IPU_DP_COM_CONF_ASYNC__DP_GWSEL_ASYNC 0x1E018060,0x00000002 ++ ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__ADDR 0x1E018064 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__EMPTY 0x1E018064,0x00000000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__FULL 0x1E018064,0xffffffff ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWAV_ASYNC 0x1E018064,0xFF000000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKR_ASYNC 0x1E018064,0x00FF0000 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKG_ASYNC 0x1E018064,0x0000FF00 ++#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKB_ASYNC 0x1E018064,0x000000FF ++ ++#define IPU_DP_FG_POS_ASYNC__ADDR 0x1E018068 ++#define IPU_DP_FG_POS_ASYNC__EMPTY 0x1E018068,0x00000000 ++#define IPU_DP_FG_POS_ASYNC__FULL 0x1E018068,0xffffffff ++#define IPU_DP_FG_POS_ASYNC__DP_FGXP_ASYNC 0x1E018068,0x07FF0000 ++#define IPU_DP_FG_POS_ASYNC__DP_FGYP_ASYNC 0x1E018068,0x000007FF ++ ++#define IPU_DP_CUR_POS_ASYNC__ADDR 0x1E01806C ++#define IPU_DP_CUR_POS_ASYNC__EMPTY 0x1E01806C,0x00000000 ++#define IPU_DP_CUR_POS_ASYNC__FULL 0x1E01806C,0xffffffff ++#define IPU_DP_CUR_POS_ASYNC__DP_CXW_ASYNC 0x1E01806C,0xF8000000 ++#define IPU_DP_CUR_POS_ASYNC__DP_CXP_ASYNC 0x1E01806C,0x07FF0000 ++#define IPU_DP_CUR_POS_ASYNC__DP_CYH_ASYNC 0x1E01806C,0x0000F800 ++#define IPU_DP_CUR_POS_ASYNC__DP_CYP_ASYNC 0x1E01806C,0x000007FF ++ ++#define IPU_DP_CUR_MAP_ASYNC__ADDR 0x1E018070 ++#define IPU_DP_CUR_MAP_ASYNC__EMPTY 0x1E018070,0x00000000 ++#define IPU_DP_CUR_MAP_ASYNC__FULL 0x1E018070,0xffffffff ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_R_ASYNC 0x1E018070,0x00FF0000 ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_G_ASYNC 0x1E018070,0x0000FF00 ++#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_B_ASYNC 0x1E018070,0x000000FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_0__ADDR 0x1E018074 ++#define IPU_DP_GAMMA_C_ASYNC_0__EMPTY 0x1E018074,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_0__FULL 0x1E018074,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_1 0x1E018074,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_0 0x1E018074,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_1__ADDR 0x1E018078 ++#define IPU_DP_GAMMA_C_ASYNC_1__EMPTY 0x1E018078,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_1__FULL 0x1E018078,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_3 0x1E018078,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_2 0x1E018078,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_2__ADDR 0x1E01807C ++#define IPU_DP_GAMMA_C_ASYNC_2__EMPTY 0x1E01807C,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_2__FULL 0x1E01807C,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_5 0x1E01807C,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_4 0x1E01807C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_3__ADDR 0x1E018080 ++#define IPU_DP_GAMMA_C_ASYNC_3__EMPTY 0x1E018080,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_3__FULL 0x1E018080,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_7 0x1E018080,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_6 0x1E018080,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_4__ADDR 0x1E018084 ++#define IPU_DP_GAMMA_C_ASYNC_4__EMPTY 0x1E018084,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_4__FULL 0x1E018084,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_9 0x1E018084,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_8 0x1E018084,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_5__ADDR 0x1E018088 ++#define IPU_DP_GAMMA_C_ASYNC_5__EMPTY 0x1E018088,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_5__FULL 0x1E018088,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_11 0x1E018088,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_10 0x1E018088,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_6__ADDR 0x1E01808C ++#define IPU_DP_GAMMA_C_ASYNC_6__EMPTY 0x1E01808C,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_6__FULL 0x1E01808C,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_13 0x1E01808C,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_12 0x1E01808C,0x000001FF ++ ++#define IPU_DP_GAMMA_C_ASYNC_7__ADDR 0x1E018090 ++#define IPU_DP_GAMMA_C_ASYNC_7__EMPTY 0x1E018090,0x00000000 ++#define IPU_DP_GAMMA_C_ASYNC_7__FULL 0x1E018090,0xffffffff ++#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_15 0x1E018090,0x01FF0000 ++#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_14 0x1E018090,0x000001FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_0__ADDR 0x1E018094 ++#define IPU_DP_GAMMA_S_ASYNC_0__EMPTY 0x1E018094,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_0__FULL 0x1E018094,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_3 0x1E018094,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_2 0x1E018094,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_1 0x1E018094,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_0 0x1E018094,0x000000FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_1__ADDR 0x1E018098 ++#define IPU_DP_GAMMA_S_ASYNC_1__EMPTY 0x1E018098,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_1__FULL 0x1E018098,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_7 0x1E018098,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_6 0x1E018098,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_5 0x1E018098,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_4 0x1E018098,0x000000FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_2__ADDR 0x1E01809C ++#define IPU_DP_GAMMA_S_ASYNC_2__EMPTY 0x1E01809C,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_2__FULL 0x1E01809C,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_11 0x1E01809C,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_10 0x1E01809C,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_9 0x1E01809C,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_8 0x1E01809C,0x000000FF ++ ++#define IPU_DP_GAMMA_S_ASYNC_3__ADDR 0x1E0180A0 ++#define IPU_DP_GAMMA_S_ASYNC_3__EMPTY 0x1E0180A0,0x00000000 ++#define IPU_DP_GAMMA_S_ASYNC_3__FULL 0x1E0180A0,0xffffffff ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_15 0x1E0180A0,0xFF000000 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_14 0x1E0180A0,0x00FF0000 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_13 0x1E0180A0,0x0000FF00 ++#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_12 0x1E0180A0,0x000000FF ++ ++#define IPU_DP_CSCA_ASYNC_0__ADDR 0x1E0180A4 ++#define IPU_DP_CSCA_ASYNC_0__EMPTY 0x1E0180A4,0x00000000 ++#define IPU_DP_CSCA_ASYNC_0__FULL 0x1E0180A4,0xffffffff ++#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_1 0x1E0180A4,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_0 0x1E0180A4,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_1__ADDR 0x1E0180A8 ++#define IPU_DP_CSCA_ASYNC_1__EMPTY 0x1E0180A8,0x00000000 ++#define IPU_DP_CSCA_ASYNC_1__FULL 0x1E0180A8,0xffffffff ++#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_3 0x1E0180A8,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_2 0x1E0180A8,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_2__ADDR 0x1E0180AC ++#define IPU_DP_CSCA_ASYNC_2__EMPTY 0x1E0180AC,0x00000000 ++#define IPU_DP_CSCA_ASYNC_2__FULL 0x1E0180AC,0xffffffff ++#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_5 0x1E0180AC,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_4 0x1E0180AC,0x000003FF ++ ++#define IPU_DP_CSCA_ASYNC_3__ADDR 0x1E0180B0 ++#define IPU_DP_CSCA_ASYNC_3__EMPTY 0x1E0180B0,0x00000000 ++#define IPU_DP_CSCA_ASYNC_3__FULL 0x1E0180B0,0xffffffff ++#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_7 0x1E0180B0,0x03FF0000 ++#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_6 0x1E0180B0,0x000003FF ++ ++#define IPU_DP_CSC_ASYNC_0__ADDR 0x1E0180B4 ++#define IPU_DP_CSC_ASYNC_0__EMPTY 0x1E0180B4,0x00000000 ++#define IPU_DP_CSC_ASYNC_0__FULL 0x1E0180B4,0xffffffff ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_S0_ASYNC 0x1E0180B4,0xC0000000 ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_B0_ASYNC 0x1E0180B4,0x3FFF0000 ++#define IPU_DP_CSC_ASYNC_0__DP_CSC_A8_ASYNC 0x1E0180B4,0x000003FF ++ ++#define IPU_DP_CSC_ASYNC_1__ADDR 0x1E0180B8 ++#define IPU_DP_CSC_ASYNC_1__EMPTY 0x1E0180B8,0x00000000 ++#define IPU_DP_CSC_ASYNC_1__FULL 0x1E0180B8,0xffffffff ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_S2_ASYNC 0x1E0180B8,0xC0000000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_B2_ASYNC 0x1E0180B8,0x3FFF0000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_S1_ASYNC 0x1E0180B8,0x0000C000 ++#define IPU_DP_CSC_ASYNC_1__DP_CSC_B1_ASYNC 0x1E0180B8,0x00003FFF ++ ++#define IPU_DP_DEBUG_CNT__ADDR 0x1E0180BC ++#define IPU_DP_DEBUG_CNT__EMPTY 0x1E0180BC,0x00000000 ++#define IPU_DP_DEBUG_CNT__FULL 0x1E0180BC,0xffffffff ++#define IPU_DP_DEBUG_CNT__BRAKE_CNT_1 0x1E0180BC,0x000000E0 ++#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_1 0x1E0180BC,0x00000010 ++#define IPU_DP_DEBUG_CNT__BRAKE_CNT_0 0x1E0180BC,0x0000000E ++#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_0 0x1E0180BC,0x00000001 ++ ++#define IPU_DP_DEBUG_STAT__ADDR 0x1E0180C0 ++#define IPU_DP_DEBUG_STAT__EMPTY 0x1E0180C0,0x00000000 ++#define IPU_DP_DEBUG_STAT__FULL 0x1E0180C0,0xffffffff ++#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_1 0x1E0180C0,0x20000000 ++#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_1 0x1E0180C0,0x10000000 ++#define IPU_DP_DEBUG_STAT__FG_ACTIVE_1 0x1E0180C0,0x08000000 ++#define IPU_DP_DEBUG_STAT__V_CNT_OLD_1 0x1E0180C0,0x07FF0000 ++#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_0 0x1E0180C0,0x00002000 ++#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_0 0x1E0180C0,0x00001000 ++#define IPU_DP_DEBUG_STAT__FG_ACTIVE_0 0x1E0180C0,0x00000800 ++#define IPU_DP_DEBUG_STAT__V_CNT_OLD_0 0x1E0180C0,0x000007FF ++ ++// ================= Start of IPUV3EX SRM DP Registers ===================== ++ ++// ================= Start of IPUV3EX IC Registers ===================== ++#define IPU_IC_CONF__ADDR 0x1E020000 ++#define IPU_IC_CONF__EMPTY 0x1E020000,0x00000000 ++#define IPU_IC_CONF__FULL 0x1E020000,0xffffffff ++#define IPU_IC_CONF__CSI_MEM_WR_EN 0x1E020000,0x80000000 ++#define IPU_IC_CONF__RWS_EN 0x1E020000,0x40000000 ++#define IPU_IC_CONF__IC_KEY_COLOR_EN 0x1E020000,0x20000000 ++#define IPU_IC_CONF__IC_GLB_LOC_A 0x1E020000,0x10000000 ++#define IPU_IC_CONF__PP_ROT_EN 0x1E020000,0x00100000 ++#define IPU_IC_CONF__PP_CMB 0x1E020000,0x00080000 ++#define IPU_IC_CONF__PP_CSC2 0x1E020000,0x00040000 ++#define IPU_IC_CONF__PP_CSC1 0x1E020000,0x00020000 ++#define IPU_IC_CONF__PP_EN 0x1E020000,0x00010000 ++#define IPU_IC_CONF__PRPVF_ROT_EN 0x1E020000,0x00001000 ++#define IPU_IC_CONF__PRPVF_CMB 0x1E020000,0x00000800 ++#define IPU_IC_CONF__PRPVF_CSC2 0x1E020000,0x00000400 ++#define IPU_IC_CONF__PRPVF_CSC1 0x1E020000,0x00000200 ++#define IPU_IC_CONF__PRPVF_EN 0x1E020000,0x00000100 ++#define IPU_IC_CONF__PRPENC_ROT_EN 0x1E020000,0x00000004 ++#define IPU_IC_CONF__PRPENC_CSC1 0x1E020000,0x00000002 ++#define IPU_IC_CONF__PRPENC_EN 0x1E020000,0x00000001 ++ ++#define IPU_IC_PRP_ENC_RSC__ADDR 0x1E020004 ++#define IPU_IC_PRP_ENC_RSC__EMPTY 0x1E020004,0x00000000 ++#define IPU_IC_PRP_ENC_RSC__FULL 0x1E020004,0xffffffff ++#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1E020004,0xC0000000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1E020004,0x3FFF0000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1E020004,0x0000C000 ++#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1E020004,0x00003FFF ++ ++#define IPU_IC_PRP_VF_RSC__ADDR 0x1E020008 ++#define IPU_IC_PRP_VF_RSC__EMPTY 0x1E020008,0x00000000 ++#define IPU_IC_PRP_VF_RSC__FULL 0x1E020008,0xffffffff ++#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1E020008,0xC0000000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1E020008,0x3FFF0000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1E020008,0x0000C000 ++#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1E020008,0x00003FFF ++ ++#define IPU_IC_PP_RSC__ADDR 0x1E02000C ++#define IPU_IC_PP_RSC__EMPTY 0x1E02000C,0x00000000 ++#define IPU_IC_PP_RSC__FULL 0x1E02000C,0xffffffff ++#define IPU_IC_PP_RSC__PP_DS_R_V 0x1E02000C,0xC0000000 ++#define IPU_IC_PP_RSC__PP_RS_R_V 0x1E02000C,0x3FFF0000 ++#define IPU_IC_PP_RSC__PP_DS_R_H 0x1E02000C,0x0000C000 ++#define IPU_IC_PP_RSC__PP_RS_R_H 0x1E02000C,0x00003FFF ++ ++#define IPU_IC_CMBP_1__ADDR 0x1E020010 ++#define IPU_IC_CMBP_1__EMPTY 0x1E020010,0x00000000 ++#define IPU_IC_CMBP_1__FULL 0x1E020010,0xffffffff ++#define IPU_IC_CMBP_1__IC_PP_ALPHA_V 0x1E020010,0x0000FF00 ++#define IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1E020010,0x000000FF ++ ++#define IPU_IC_CMBP_2__ADDR 0x1E020014 ++#define IPU_IC_CMBP_2__EMPTY 0x1E020014,0x00000000 ++#define IPU_IC_CMBP_2__FULL 0x1E020014,0xffffffff ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_R 0x1E020014,0x00FF0000 ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_G 0x1E020014,0x0000FF00 ++#define IPU_IC_CMBP_2__IC_KEY_COLOR_B 0x1E020014,0x000000FF ++ ++#define IPU_IC_IDMAC_1__ADDR 0x1E020018 ++#define IPU_IC_IDMAC_1__EMPTY 0x1E020018,0x00000000 ++#define IPU_IC_IDMAC_1__FULL 0x1E020018,0xffffffff ++#define IPU_IC_IDMAC_1__ALT_CB7_BURST_16 0x1E020018,0x02000000 ++#define IPU_IC_IDMAC_1__ALT_CB6_BURST_16 0x1E020018,0x01000000 ++#define IPU_IC_IDMAC_1__T3_FLIP_RS 0x1E020018,0x00400000 ++#define IPU_IC_IDMAC_1__T2_FLIP_RS 0x1E020018,0x00200000 ++#define IPU_IC_IDMAC_1__T1_FLIP_RS 0x1E020018,0x00100000 ++#define IPU_IC_IDMAC_1__T3_FLIP_UD 0x1E020018,0x00080000 ++#define IPU_IC_IDMAC_1__T3_FLIP_LR 0x1E020018,0x00040000 ++#define IPU_IC_IDMAC_1__T3_ROT 0x1E020018,0x00020000 ++#define IPU_IC_IDMAC_1__T2_FLIP_UD 0x1E020018,0x00010000 ++#define IPU_IC_IDMAC_1__T2_FLIP_LR 0x1E020018,0x00008000 ++#define IPU_IC_IDMAC_1__T2_ROT 0x1E020018,0x00004000 ++#define IPU_IC_IDMAC_1__T1_FLIP_UD 0x1E020018,0x00002000 ++#define IPU_IC_IDMAC_1__T1_FLIP_LR 0x1E020018,0x00001000 ++#define IPU_IC_IDMAC_1__T1_ROT 0x1E020018,0x00000800 ++#define IPU_IC_IDMAC_1__CB7_BURST_16 0x1E020018,0x00000080 ++#define IPU_IC_IDMAC_1__CB6_BURST_16 0x1E020018,0x00000040 ++#define IPU_IC_IDMAC_1__CB5_BURST_16 0x1E020018,0x00000020 ++#define IPU_IC_IDMAC_1__CB4_BURST_16 0x1E020018,0x00000010 ++#define IPU_IC_IDMAC_1__CB3_BURST_16 0x1E020018,0x00000008 ++#define IPU_IC_IDMAC_1__CB2_BURST_16 0x1E020018,0x00000004 ++#define IPU_IC_IDMAC_1__CB1_BURST_16 0x1E020018,0x00000002 ++#define IPU_IC_IDMAC_1__CB0_BURST_16 0x1E020018,0x00000001 ++ ++#define IPU_IC_IDMAC_2__ADDR 0x1E02001C ++#define IPU_IC_IDMAC_2__EMPTY 0x1E02001C,0x00000000 ++#define IPU_IC_IDMAC_2__FULL 0x1E02001C,0xffffffff ++#define IPU_IC_IDMAC_2__T3_FR_HEIGHT 0x1E02001C,0x3FF00000 ++#define IPU_IC_IDMAC_2__T2_FR_HEIGHT 0x1E02001C,0x000FFC00 ++#define IPU_IC_IDMAC_2__T1_FR_HEIGHT 0x1E02001C,0x000003FF ++ ++#define IPU_IC_IDMAC_3__ADDR 0x1E020020 ++#define IPU_IC_IDMAC_3__EMPTY 0x1E020020,0x00000000 ++#define IPU_IC_IDMAC_3__FULL 0x1E020020,0xffffffff ++#define IPU_IC_IDMAC_3__T3_FR_WIDTH 0x1E020020,0x3FF00000 ++#define IPU_IC_IDMAC_3__T2_FR_WIDTH 0x1E020020,0x000FFC00 ++#define IPU_IC_IDMAC_3__T1_FR_WIDTH 0x1E020020,0x000003FF ++ ++#define IPU_IC_IDMAC_4__ADDR 0x1E020024 ++#define IPU_IC_IDMAC_4__EMPTY 0x1E020024,0x00000000 ++#define IPU_IC_IDMAC_4__FULL 0x1E020024,0xffffffff ++#define IPU_IC_IDMAC_4__RM_BRDG_MAX_RQ 0x1E020024,0x0000F000 ++#define IPU_IC_IDMAC_4__IBM_BRDG_MAX_RQ 0x1E020024,0x00000F00 ++#define IPU_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1E020024,0x000000F0 ++#define IPU_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ 0x1E020024,0x0000000F ++// ================= End of IPUV3EX IC Registers ===================== ++ ++// ================= Start of IPUV3EX CSI Registers ===================== ++#define IPU_CSI0_SENS_CONF__ADDR 0x1E030000 ++#define IPU_CSI0_SENS_CONF__EMPTY 0x1E030000,0x00000000 ++#define IPU_CSI0_SENS_CONF__FULL 0x1E030000,0xffffffff ++#define IPU_CSI0_SENS_CONF__CSI0_FORCE_EOF 0x1E030000,0x20000000 ++#define IPU_CSI0_SENS_CONF__CSI0_JPEG_MODE 0x1E030000,0x10000000 ++#define IPU_CSI0_SENS_CONF__CSI0_JPEG8_EN 0x1E030000,0x08000000 ++#define IPU_CSI0_SENS_CONF__CSI0_DATA_DEST 0x1E030000,0x07000000 ++#define IPU_CSI0_SENS_CONF__CSI0_DIV_RATIO 0x1E030000,0x00FF0000 ++#define IPU_CSI0_SENS_CONF__CSI0_EXT_VSYNC 0x1E030000,0x00008000 ++#define IPU_CSI0_SENS_CONF__CSI0_DATA_WIDTH 0x1E030000,0x00007800 ++#define IPU_CSI0_SENS_CONF__CSI0_SENS_DATA_FORMAT 0x1E030000,0x00000700 ++#define IPU_CSI0_SENS_CONF__CSI0_PACK_TIGHT 0x1E030000,0x00000080 ++#define IPU_CSI0_SENS_CONF__CSI0_SENS_PRTCL 0x1E030000,0x00000070 ++#define IPU_CSI0_SENS_CONF__CSI0_SENS_PIX_CLK_POL 0x1E030000,0x00000008 ++#define IPU_CSI0_SENS_CONF__CSI0_DATA_POL 0x1E030000,0x00000004 ++#define IPU_CSI0_SENS_CONF__CSI0_HSYNC_POL 0x1E030000,0x00000002 ++#define IPU_CSI0_SENS_CONF__CSI0_VSYNC_POL 0x1E030000,0x00000001 ++ ++#define IPU_CSI0_SENS_FRM_SIZE__ADDR 0x1E030004 ++#define IPU_CSI0_SENS_FRM_SIZE__EMPTY 0x1E030004,0x00000000 ++#define IPU_CSI0_SENS_FRM_SIZE__FULL 0x1E030004,0xffffffff ++#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_HEIGHT 0x1E030004,0x0FFF0000 ++#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_WIDTH 0x1E030004,0x00001FFF ++ ++#define IPU_CSI0_ACT_FRM_SIZE__ADDR 0x1E030008 ++#define IPU_CSI0_ACT_FRM_SIZE__EMPTY 0x1E030008,0x00000000 ++#define IPU_CSI0_ACT_FRM_SIZE__FULL 0x1E030008,0xffffffff ++#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_HEIGHT 0x1E030008,0x0FFF0000 ++#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_WIDTH 0x1E030008,0x00001FFF ++ ++#define IPU_CSI0_OUT_FRM_CTRL__ADDR 0x1E03000C ++#define IPU_CSI0_OUT_FRM_CTRL__EMPTY 0x1E03000C,0x00000000 ++#define IPU_CSI0_OUT_FRM_CTRL__FULL 0x1E03000C,0xffffffff ++#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HORZ_DWNS 0x1E03000C,0x80000000 ++#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VERT_DWNS 0x1E03000C,0x40000000 ++#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HSC 0x1E03000C,0x1FFF0000 ++#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VSC 0x1E03000C,0x00000FFF ++ ++#define IPU_CSI0_TST_CTRL__ADDR 0x1E030010 ++#define IPU_CSI0_TST_CTRL__EMPTY 0x1E030010,0x00000000 ++#define IPU_CSI0_TST_CTRL__FULL 0x1E030010,0xffffffff ++#define IPU_CSI0_TST_CTRL__CSI0_TEST_GEN_MODE 0x1E030010,0x01000000 ++#define IPU_CSI0_TST_CTRL__CSI0_PG_B_VALUE 0x1E030010,0x00FF0000 ++#define IPU_CSI0_TST_CTRL__CSI0_PG_G_VALUE 0x1E030010,0x0000FF00 ++#define IPU_CSI0_TST_CTRL__CSI0_PG_R_VALUE 0x1E030010,0x000000FF ++ ++#define IPU_CSI0_CCIR_CODE_1__ADDR 0x1E030014 ++#define IPU_CSI0_CCIR_CODE_1__EMPTY 0x1E030014,0x00000000 ++#define IPU_CSI0_CCIR_CODE_1__FULL 0x1E030014,0xffffffff ++#define IPU_CSI0_CCIR_CODE_1__CSI0_CCIR_ERR_DET_EN 0x1E030014,0x01000000 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_ACTV 0x1E030014,0x00380000 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_ACTV 0x1E030014,0x00070000 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_2ND 0x1E030014,0x00000E00 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_2ND 0x1E030014,0x000001C0 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_1ST 0x1E030014,0x00000038 ++#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_1ST 0x1E030014,0x00000007 ++ ++#define IPU_CSI0_CCIR_CODE_2__ADDR 0x1E030018 ++#define IPU_CSI0_CCIR_CODE_2__EMPTY 0x1E030018,0x00000000 ++#define IPU_CSI0_CCIR_CODE_2__FULL 0x1E030018,0xffffffff ++#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_ACTV 0x1E030018,0x00380000 ++#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_ACTV 0x1E030018,0x00070000 ++#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_2ND 0x1E030018,0x00000E00 ++#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_2ND 0x1E030018,0x000001C0 ++#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_1ST 0x1E030018,0x00000038 ++#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_1ST 0x1E030018,0x00000007 ++ ++#define IPU_CSI0_CCIR_CODE_3__ADDR 0x1E03001C ++#define IPU_CSI0_CCIR_CODE_3__EMPTY 0x1E03001C,0x00000000 ++#define IPU_CSI0_CCIR_CODE_3__FULL 0x1E03001C,0xffffffff ++#define IPU_CSI0_CCIR_CODE_3__CSI0_CCIR_PRECOM 0x1E03001C,0x3FFFFFFF ++ ++#define IPU_CSI0_DI__ADDR 0x1E030020 ++#define IPU_CSI0_DI__EMPTY 0x1E030020,0x00000000 ++#define IPU_CSI0_DI__FULL 0x1E030020,0xffffffff ++#define IPU_CSI0_DI__CSI0_MIPI_DI3 0x1E030020,0xFF000000 ++#define IPU_CSI0_DI__CSI0_MIPI_DI2 0x1E030020,0x00FF0000 ++#define IPU_CSI0_DI__CSI0_MIPI_DI1 0x1E030020,0x0000FF00 ++#define IPU_CSI0_DI__CSI0_MIPI_DI0 0x1E030020,0x000000FF ++ ++#define IPU_CSI0_SKIP__ADDR 0x1E030024 ++#define IPU_CSI0_SKIP__EMPTY 0x1E030024,0x00000000 ++#define IPU_CSI0_SKIP__FULL 0x1E030024,0xffffffff ++#define IPU_CSI0_SKIP__CSI0_SKIP_ISP 0x1E030024,0x00F80000 ++#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_ISP 0x1E030024,0x00070000 ++#define IPU_CSI0_SKIP__CSI0_ID_2_SKIP 0x1E030024,0x00000300 ++#define IPU_CSI0_SKIP__CSI0_SKIP_SMFC 0x1E030024,0x000000F8 ++#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_SMFC 0x1E030024,0x00000007 ++ ++#define IPU_CSI0_CPD_CTRL__ADDR 0x1E030028 ++#define IPU_CSI0_CPD_CTRL__EMPTY 0x1E030028,0x00000000 ++#define IPU_CSI0_CPD_CTRL__FULL 0x1E030028,0xffffffff ++#define IPU_CSI0_CPD_CTRL__CSI0_CPD 0x1E030028,0x0000001C ++#define IPU_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN 0x1E030028,0x00000002 ++#define IPU_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN 0x1E030028,0x00000001 ++ ++#define IPU_CSI0_CPD_RC_0__ADDR 0x1E03002C ++#define IPU_CSI0_CPD_RC_0__EMPTY 0x1E03002C,0x00000000 ++#define IPU_CSI0_CPD_RC_0__FULL 0x1E03002C,0xffffffff ++#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_1 0x1E03002C,0x01FF0000 ++#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_0 0x1E03002C,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_1__ADDR 0x1E030030 ++#define IPU_CSI0_CPD_RC_1__EMPTY 0x1E030030,0x00000000 ++#define IPU_CSI0_CPD_RC_1__FULL 0x1E030030,0xffffffff ++#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_3 0x1E030030,0x01FF0000 ++#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_2 0x1E030030,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_2__ADDR 0x1E030034 ++#define IPU_CSI0_CPD_RC_2__EMPTY 0x1E030034,0x00000000 ++#define IPU_CSI0_CPD_RC_2__FULL 0x1E030034,0xffffffff ++#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_5 0x1E030034,0x01FF0000 ++#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_4 0x1E030034,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_3__ADDR 0x1E030038 ++#define IPU_CSI0_CPD_RC_3__EMPTY 0x1E030038,0x00000000 ++#define IPU_CSI0_CPD_RC_3__FULL 0x1E030038,0xffffffff ++#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_7 0x1E030038,0x01FF0000 ++#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_6 0x1E030038,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_4__ADDR 0x1E03003C ++#define IPU_CSI0_CPD_RC_4__EMPTY 0x1E03003C,0x00000000 ++#define IPU_CSI0_CPD_RC_4__FULL 0x1E03003C,0xffffffff ++#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_9 0x1E03003C,0x01FF0000 ++#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_8 0x1E03003C,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_5__ADDR 0x1E030040 ++#define IPU_CSI0_CPD_RC_5__EMPTY 0x1E030040,0x00000000 ++#define IPU_CSI0_CPD_RC_5__FULL 0x1E030040,0xffffffff ++#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_11 0x1E030040,0x01FF0000 ++#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_10 0x1E030040,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_6__ADDR 0x1E030044 ++#define IPU_CSI0_CPD_RC_6__EMPTY 0x1E030044,0x00000000 ++#define IPU_CSI0_CPD_RC_6__FULL 0x1E030044,0xffffffff ++#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_13 0x1E030044,0x01FF0000 ++#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_12 0x1E030044,0x000001FF ++ ++#define IPU_CSI0_CPD_RC_7__ADDR 0x1E030048 ++#define IPU_CSI0_CPD_RC_7__EMPTY 0x1E030048,0x00000000 ++#define IPU_CSI0_CPD_RC_7__FULL 0x1E030048,0xffffffff ++#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_15 0x1E030048,0x01FF0000 ++#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_14 0x1E030048,0x000001FF ++ ++#define IPU_CSI0_CPD_RS_0__ADDR 0x1E03004C ++#define IPU_CSI0_CPD_RS_0__EMPTY 0x1E03004C,0x00000000 ++#define IPU_CSI0_CPD_RS_0__FULL 0x1E03004C,0xffffffff ++#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS3 0x1E03004C,0xFF000000 ++#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS2 0x1E03004C,0x00FF0000 ++#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS1 0x1E03004C,0x0000FF00 ++#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS0 0x1E03004C,0x000000FF ++ ++#define IPU_CSI0_CPD_RS_1__ADDR 0x1E030050 ++#define IPU_CSI0_CPD_RS_1__EMPTY 0x1E030050,0x00000000 ++#define IPU_CSI0_CPD_RS_1__FULL 0x1E030050,0xffffffff ++#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS7 0x1E030050,0xFF000000 ++#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS6 0x1E030050,0x00FF0000 ++#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS5 0x1E030050,0x0000FF00 ++#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS4 0x1E030050,0x000000FF ++ ++#define IPU_CSI0_CPD_RS_2__ADDR 0x1E030054 ++#define IPU_CSI0_CPD_RS_2__EMPTY 0x1E030054,0x00000000 ++#define IPU_CSI0_CPD_RS_2__FULL 0x1E030054,0xffffffff ++#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS11 0x1E030054,0xFF000000 ++#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS10 0x1E030054,0x00FF0000 ++#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS9 0x1E030054,0x0000FF00 ++#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS8 0x1E030054,0x000000FF ++ ++#define IPU_CSI0_CPD_RS_3__ADDR 0x1E030058 ++#define IPU_CSI0_CPD_RS_3__EMPTY 0x1E030058,0x00000000 ++#define IPU_CSI0_CPD_RS_3__FULL 0x1E030058,0xffffffff ++#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS15 0x1E030058,0xFF000000 ++#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS14 0x1E030058,0x00FF0000 ++#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS13 0x1E030058,0x0000FF00 ++#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS12 0x1E030058,0x000000FF ++ ++#define IPU_CSI0_CPD_GRC_0__ADDR 0x1E03005C ++#define IPU_CSI0_CPD_GRC_0__EMPTY 0x1E03005C,0x00000000 ++#define IPU_CSI0_CPD_GRC_0__FULL 0x1E03005C,0xffffffff ++#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC1 0x1E03005C,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC0 0x1E03005C,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_1__ADDR 0x1E030060 ++#define IPU_CSI0_CPD_GRC_1__EMPTY 0x1E030060,0x00000000 ++#define IPU_CSI0_CPD_GRC_1__FULL 0x1E030060,0xffffffff ++#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC3 0x1E030060,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC2 0x1E030060,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_2__ADDR 0x1E030064 ++#define IPU_CSI0_CPD_GRC_2__EMPTY 0x1E030064,0x00000000 ++#define IPU_CSI0_CPD_GRC_2__FULL 0x1E030064,0xffffffff ++#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC5 0x1E030064,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC4 0x1E030064,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_3__ADDR 0x1E030068 ++#define IPU_CSI0_CPD_GRC_3__EMPTY 0x1E030068,0x00000000 ++#define IPU_CSI0_CPD_GRC_3__FULL 0x1E030068,0xffffffff ++#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC7 0x1E030068,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC6 0x1E030068,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_4__ADDR 0x1E03006C ++#define IPU_CSI0_CPD_GRC_4__EMPTY 0x1E03006C,0x00000000 ++#define IPU_CSI0_CPD_GRC_4__FULL 0x1E03006C,0xffffffff ++#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC9 0x1E03006C,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC8 0x1E03006C,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_5__ADDR 0x1E030070 ++#define IPU_CSI0_CPD_GRC_5__EMPTY 0x1E030070,0x00000000 ++#define IPU_CSI0_CPD_GRC_5__FULL 0x1E030070,0xffffffff ++#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC11 0x1E030070,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC10 0x1E030070,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_6__ADDR 0x1E030074 ++#define IPU_CSI0_CPD_GRC_6__EMPTY 0x1E030074,0x00000000 ++#define IPU_CSI0_CPD_GRC_6__FULL 0x1E030074,0xffffffff ++#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC13 0x1E030074,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC12 0x1E030074,0x000001FF ++ ++#define IPU_CSI0_CPD_GRC_7__ADDR 0x1E030078 ++#define IPU_CSI0_CPD_GRC_7__EMPTY 0x1E030078,0x00000000 ++#define IPU_CSI0_CPD_GRC_7__FULL 0x1E030078,0xffffffff ++#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC15 0x1E030078,0x01FF0000 ++#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC14 0x1E030078,0x000001FF ++ ++#define IPU_CSI0_CPD_GRS_0__ADDR 0x1E03007C ++#define IPU_CSI0_CPD_GRS_0__EMPTY 0x1E03007C,0x00000000 ++#define IPU_CSI0_CPD_GRS_0__FULL 0x1E03007C,0xffffffff ++#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS3 0x1E03007C,0xFF000000 ++#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS2 0x1E03007C,0x00FF0000 ++#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS1 0x1E03007C,0x0000FF00 ++#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS0 0x1E03007C,0x000000FF ++ ++#define IPU_CSI0_CPD_GRS_1__ADDR 0x1E030080 ++#define IPU_CSI0_CPD_GRS_1__EMPTY 0x1E030080,0x00000000 ++#define IPU_CSI0_CPD_GRS_1__FULL 0x1E030080,0xffffffff ++#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS7 0x1E030080,0xFF000000 ++#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS6 0x1E030080,0x00FF0000 ++#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS5 0x1E030080,0x0000FF00 ++#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS4 0x1E030080,0x000000FF ++ ++#define IPU_CSI0_CPD_GRS_2__ADDR 0x1E030084 ++#define IPU_CSI0_CPD_GRS_2__EMPTY 0x1E030084,0x00000000 ++#define IPU_CSI0_CPD_GRS_2__FULL 0x1E030084,0xffffffff ++#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS11 0x1E030084,0xFF000000 ++#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS10 0x1E030084,0x00FF0000 ++#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS9 0x1E030084,0x0000FF00 ++#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS8 0x1E030084,0x000000FF ++ ++#define IPU_CSI0_CPD_GRS_3__ADDR 0x1E030088 ++#define IPU_CSI0_CPD_GRS_3__EMPTY 0x1E030088,0x00000000 ++#define IPU_CSI0_CPD_GRS_3__FULL 0x1E030088,0xffffffff ++#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS15 0x1E030088,0xFF000000 ++#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS14 0x1E030088,0x00FF0000 ++#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS13 0x1E030088,0x0000FF00 ++#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS12 0x1E030088,0x000000FF ++ ++#define IPU_CSI0_CPD_GBC_0__ADDR 0x1E03008C ++#define IPU_CSI0_CPD_GBC_0__EMPTY 0x1E03008C,0x00000000 ++#define IPU_CSI0_CPD_GBC_0__FULL 0x1E03008C,0xffffffff ++#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC1 0x1E03008C,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC0 0x1E03008C,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_1__ADDR 0x1E030090 ++#define IPU_CSI0_CPD_GBC_1__EMPTY 0x1E030090,0x00000000 ++#define IPU_CSI0_CPD_GBC_1__FULL 0x1E030090,0xffffffff ++#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC3 0x1E030090,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC2 0x1E030090,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_2__ADDR 0x1E030094 ++#define IPU_CSI0_CPD_GBC_2__EMPTY 0x1E030094,0x00000000 ++#define IPU_CSI0_CPD_GBC_2__FULL 0x1E030094,0xffffffff ++#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC5 0x1E030094,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC4 0x1E030094,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_3__ADDR 0x1E030098 ++#define IPU_CSI0_CPD_GBC_3__EMPTY 0x1E030098,0x00000000 ++#define IPU_CSI0_CPD_GBC_3__FULL 0x1E030098,0xffffffff ++#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC7 0x1E030098,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC6 0x1E030098,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_4__ADDR 0x1E03009C ++#define IPU_CSI0_CPD_GBC_4__EMPTY 0x1E03009C,0x00000000 ++#define IPU_CSI0_CPD_GBC_4__FULL 0x1E03009C,0xffffffff ++#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC9 0x1E03009C,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC8 0x1E03009C,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_5__ADDR 0x1E0300A0 ++#define IPU_CSI0_CPD_GBC_5__EMPTY 0x1E0300A0,0x00000000 ++#define IPU_CSI0_CPD_GBC_5__FULL 0x1E0300A0,0xffffffff ++#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC11 0x1E0300A0,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC10 0x1E0300A0,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_6__ADDR 0x1E0300A4 ++#define IPU_CSI0_CPD_GBC_6__EMPTY 0x1E0300A4,0x00000000 ++#define IPU_CSI0_CPD_GBC_6__FULL 0x1E0300A4,0xffffffff ++#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC13 0x1E0300A4,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC12 0x1E0300A4,0x000001FF ++ ++#define IPU_CSI0_CPD_GBC_7__ADDR 0x1E0300A8 ++#define IPU_CSI0_CPD_GBC_7__EMPTY 0x1E0300A8,0x00000000 ++#define IPU_CSI0_CPD_GBC_7__FULL 0x1E0300A8,0xffffffff ++#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC15 0x1E0300A8,0x01FF0000 ++#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC14 0x1E0300A8,0x000001FF ++ ++#define IPU_CSI0_CPD_GBS_0__ADDR 0x1E0300AC ++#define IPU_CSI0_CPD_GBS_0__EMPTY 0x1E0300AC,0x00000000 ++#define IPU_CSI0_CPD_GBS_0__FULL 0x1E0300AC,0xffffffff ++#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS3 0x1E0300AC,0xFF000000 ++#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS2 0x1E0300AC,0x00FF0000 ++#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS1 0x1E0300AC,0x0000FF00 ++#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS0 0x1E0300AC,0x000000FF ++ ++#define IPU_CSI0_CPD_GBS_1__ADDR 0x1E0300B0 ++#define IPU_CSI0_CPD_GBS_1__EMPTY 0x1E0300B0,0x00000000 ++#define IPU_CSI0_CPD_GBS_1__FULL 0x1E0300B0,0xffffffff ++#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS7 0x1E0300B0,0xFF000000 ++#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS6 0x1E0300B0,0x00FF0000 ++#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS5 0x1E0300B0,0x0000FF00 ++#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS4 0x1E0300B0,0x000000FF ++ ++#define IPU_CSI0_CPD_GBS_2__ADDR 0x1E0300B4 ++#define IPU_CSI0_CPD_GBS_2__EMPTY 0x1E0300B4,0x00000000 ++#define IPU_CSI0_CPD_GBS_2__FULL 0x1E0300B4,0xffffffff ++#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS11 0x1E0300B4,0xFF000000 ++#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS10 0x1E0300B4,0x00FF0000 ++#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS9 0x1E0300B4,0x0000FF00 ++#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS8 0x1E0300B4,0x000000FF ++ ++#define IPU_CSI0_CPD_GBS_3__ADDR 0x1E0300B8 ++#define IPU_CSI0_CPD_GBS_3__EMPTY 0x1E0300B8,0x00000000 ++#define IPU_CSI0_CPD_GBS_3__FULL 0x1E0300B8,0xffffffff ++#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS15 0x1E0300B8,0xFF000000 ++#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS14 0x1E0300B8,0x00FF0000 ++#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS13 0x1E0300B8,0x0000FF00 ++#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS12 0x1E0300B8,0x000000FF ++ ++#define IPU_CSI0_CPD_BC_0__ADDR 0x1E0300BC ++#define IPU_CSI0_CPD_BC_0__EMPTY 0x1E0300BC,0x00000000 ++#define IPU_CSI0_CPD_BC_0__FULL 0x1E0300BC,0xffffffff ++#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC1 0x1E0300BC,0x01FF0000 ++#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC0 0x1E0300BC,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_1__ADDR 0x1E0300C0 ++#define IPU_CSI0_CPD_BC_1__EMPTY 0x1E0300C0,0x00000000 ++#define IPU_CSI0_CPD_BC_1__FULL 0x1E0300C0,0xffffffff ++#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC3 0x1E0300C0,0x01FF0000 ++#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC2 0x1E0300C0,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_2__ADDR 0x1E0300C4 ++#define IPU_CSI0_CPD_BC_2__EMPTY 0x1E0300C4,0x00000000 ++#define IPU_CSI0_CPD_BC_2__FULL 0x1E0300C4,0xffffffff ++#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC5 0x1E0300C4,0x01FF0000 ++#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC4 0x1E0300C4,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_3__ADDR 0x1E0300C8 ++#define IPU_CSI0_CPD_BC_3__EMPTY 0x1E0300C8,0x00000000 ++#define IPU_CSI0_CPD_BC_3__FULL 0x1E0300C8,0xffffffff ++#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC7 0x1E0300C8,0x01FF0000 ++#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC6 0x1E0300C8,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_4__ADDR 0x1E0300CC ++#define IPU_CSI0_CPD_BC_4__EMPTY 0x1E0300CC,0x00000000 ++#define IPU_CSI0_CPD_BC_4__FULL 0x1E0300CC,0xffffffff ++#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC9 0x1E0300CC,0x01FF0000 ++#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC8 0x1E0300CC,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_5__ADDR 0x1E0300D0 ++#define IPU_CSI0_CPD_BC_5__EMPTY 0x1E0300D0,0x00000000 ++#define IPU_CSI0_CPD_BC_5__FULL 0x1E0300D0,0xffffffff ++#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC11 0x1E0300D0,0x01FF0000 ++#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC10 0x1E0300D0,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_6__ADDR 0x1E0300D4 ++#define IPU_CSI0_CPD_BC_6__EMPTY 0x1E0300D4,0x00000000 ++#define IPU_CSI0_CPD_BC_6__FULL 0x1E0300D4,0xffffffff ++#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC13 0x1E0300D4,0x01FF0000 ++#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC12 0x1E0300D4,0x000001FF ++ ++#define IPU_CSI0_CPD_BC_7__ADDR 0x1E0300D8 ++#define IPU_CSI0_CPD_BC_7__EMPTY 0x1E0300D8,0x00000000 ++#define IPU_CSI0_CPD_BC_7__FULL 0x1E0300D8,0xffffffff ++#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC15 0x1E0300D8,0x01FF0000 ++#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC14 0x1E0300D8,0x000001FF ++ ++#define IPU_CSI0_CPD_BS_0__ADDR 0x1E0300DC ++#define IPU_CSI0_CPD_BS_0__EMPTY 0x1E0300DC,0x00000000 ++#define IPU_CSI0_CPD_BS_0__FULL 0x1E0300DC,0xffffffff ++#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS3 0x1E0300DC,0xFF000000 ++#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS2 0x1E0300DC,0x00FF0000 ++#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS1 0x1E0300DC,0x0000FF00 ++#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS0 0x1E0300DC,0x000000FF ++ ++#define IPU_CSI0_CPD_BS_1__ADDR 0x1E0300E0 ++#define IPU_CSI0_CPD_BS_1__EMPTY 0x1E0300E0,0x00000000 ++#define IPU_CSI0_CPD_BS_1__FULL 0x1E0300E0,0xffffffff ++#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS7 0x1E0300E0,0xFF000000 ++#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS6 0x1E0300E0,0x00FF0000 ++#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS5 0x1E0300E0,0x0000FF00 ++#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS4 0x1E0300E0,0x000000FF ++ ++#define IPU_CSI0_CPD_BS_2__ADDR 0x1E0300E4 ++#define IPU_CSI0_CPD_BS_2__EMPTY 0x1E0300E4,0x00000000 ++#define IPU_CSI0_CPD_BS_2__FULL 0x1E0300E4,0xffffffff ++#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS11 0x1E0300E4,0xFF000000 ++#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS10 0x1E0300E4,0x00FF0000 ++#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS9 0x1E0300E4,0x0000FF00 ++#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS8 0x1E0300E4,0x000000FF ++ ++#define IPU_CSI0_CPD_BS_3__ADDR 0x1E0300E8 ++#define IPU_CSI0_CPD_BS_3__EMPTY 0x1E0300E8,0x00000000 ++#define IPU_CSI0_CPD_BS_3__FULL 0x1E0300E8,0xffffffff ++#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS15 0x1E0300E8,0xFF000000 ++#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS14 0x1E0300E8,0x00FF0000 ++#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS13 0x1E0300E8,0x0000FF00 ++#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS12 0x1E0300E8,0x000000FF ++ ++#define IPU_CSI0_CPD_OFFSET1__ADDR 0x1E0300EC ++#define IPU_CSI0_CPD_OFFSET1__EMPTY 0x1E0300EC,0x00000000 ++#define IPU_CSI0_CPD_OFFSET1__FULL 0x1E0300EC,0xffffffff ++#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET 0x1E0300EC,0x3FF00000 ++#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET 0x1E0300EC,0x000FFC00 ++#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET 0x1E0300EC,0x000003FF ++ ++#define IPU_CSI0_CPD_OFFSET2__ADDR 0x1E0300F0 ++#define IPU_CSI0_CPD_OFFSET2__EMPTY 0x1E0300F0,0x00000000 ++#define IPU_CSI0_CPD_OFFSET2__FULL 0x1E0300F0,0xffffffff ++#define IPU_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET 0x1E0300F0,0x000003FF ++ ++#define IPU_CSI1_SENS_CONF__ADDR 0x1E038000 ++#define IPU_CSI1_SENS_CONF__EMPTY 0x1E038000,0x00000000 ++#define IPU_CSI1_SENS_CONF__FULL 0x1E038000,0xffffffff ++#define IPU_CSI1_SENS_CONF__CSI1_DATA_EN_POL 0x1E038000,0x80000000 ++#define IPU_CSI1_SENS_CONF__CSI1_FORCE_EOF 0x1E038000,0x20000000 ++#define IPU_CSI1_SENS_CONF__CSI1_JPEG_MODE 0x1E038000,0x10000000 ++#define IPU_CSI1_SENS_CONF__CSI1_JPEG8_EN 0x1E038000,0x08000000 ++#define IPU_CSI1_SENS_CONF__CSI1_DATA_DEST 0x1E038000,0x07000000 ++#define IPU_CSI1_SENS_CONF__CSI1_DIV_RATIO 0x1E038000,0x00FF0000 ++#define IPU_CSI1_SENS_CONF__CSI1_EXT_VSYNC 0x1E038000,0x00008000 ++#define IPU_CSI1_SENS_CONF__CSI1_DATA_WIDTH 0x1E038000,0x00007800 ++#define IPU_CSI1_SENS_CONF__CSI1_SENS_DATA_FORMAT 0x1E038000,0x00000700 ++#define IPU_CSI1_SENS_CONF__CSI1_PACK_TIGHT 0x1E038000,0x00000080 ++#define IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL 0x1E038000,0x00000070 ++#define IPU_CSI1_SENS_CONF__CSI1_SENS_PIX_CLK_POL 0x1E038000,0x00000008 ++#define IPU_CSI1_SENS_CONF__CSI1_DATA_POL 0x1E038000,0x00000004 ++#define IPU_CSI1_SENS_CONF__CSI1_HSYNC_POL 0x1E038000,0x00000002 ++#define IPU_CSI1_SENS_CONF__CSI1_VSYNC_POL 0x1E038000,0x00000001 ++ ++#define IPU_CSI1_SENS_FRM_SIZE__ADDR 0x1E038004 ++#define IPU_CSI1_SENS_FRM_SIZE__EMPTY 0x1E038004,0x00000000 ++#define IPU_CSI1_SENS_FRM_SIZE__FULL 0x1E038004,0xffffffff ++#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_HEIGHT 0x1E038004,0x0FFF0000 ++#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_WIDTH 0x1E038004,0x00001FFF ++ ++#define IPU_CSI1_ACT_FRM_SIZE__ADDR 0x1E038008 ++#define IPU_CSI1_ACT_FRM_SIZE__EMPTY 0x1E038008,0x00000000 ++#define IPU_CSI1_ACT_FRM_SIZE__FULL 0x1E038008,0xffffffff ++#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_HEIGHT 0x1E038008,0x0FFF0000 ++#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_WIDTH 0x1E038008,0x00001FFF ++ ++#define IPU_CSI1_OUT_FRM_CTRL__ADDR 0x1E03800C ++#define IPU_CSI1_OUT_FRM_CTRL__EMPTY 0x1E03800C,0x00000000 ++#define IPU_CSI1_OUT_FRM_CTRL__FULL 0x1E03800C,0xffffffff ++#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HORZ_DWNS 0x1E03800C,0x80000000 ++#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VERT_DWNS 0x1E03800C,0x40000000 ++#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HSC 0x1E03800C,0x1FFF0000 ++#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VSC 0x1E03800C,0x00000FFF ++ ++#define IPU_CSI1_TST_CTRL__ADDR 0x1E038010 ++#define IPU_CSI1_TST_CTRL__EMPTY 0x1E038010,0x00000000 ++#define IPU_CSI1_TST_CTRL__FULL 0x1E038010,0xffffffff ++#define IPU_CSI1_TST_CTRL__CSI1_TEST_GEN_MODE 0x1E038010,0x01000000 ++#define IPU_CSI1_TST_CTRL__CSI1_PG_B_VALUE 0x1E038010,0x00FF0000 ++#define IPU_CSI1_TST_CTRL__CSI1_PG_G_VALUE 0x1E038010,0x0000FF00 ++#define IPU_CSI1_TST_CTRL__CSI1_PG_R_VALUE 0x1E038010,0x000000FF ++ ++#define IPU_CSI1_CCIR_CODE_1__ADDR 0x1E038014 ++#define IPU_CSI1_CCIR_CODE_1__EMPTY 0x1E038014,0x00000000 ++#define IPU_CSI1_CCIR_CODE_1__FULL 0x1E038014,0xffffffff ++#define IPU_CSI1_CCIR_CODE_1__CSI1_CCIR_ERR_DET_EN 0x1E038014,0x01000000 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_ACTV 0x1E038014,0x00380000 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_ACTV 0x1E038014,0x00070000 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_2ND 0x1E038014,0x00000E00 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_2ND 0x1E038014,0x000001C0 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_1ST 0x1E038014,0x00000038 ++#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_1ST 0x1E038014,0x00000007 ++ ++#define IPU_CSI1_CCIR_CODE_2__ADDR 0x1E038018 ++#define IPU_CSI1_CCIR_CODE_2__EMPTY 0x1E038018,0x00000000 ++#define IPU_CSI1_CCIR_CODE_2__FULL 0x1E038018,0xffffffff ++#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_ACTV 0x1E038018,0x00380000 ++#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_ACTV 0x1E038018,0x00070000 ++#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_2ND 0x1E038018,0x00000E00 ++#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_2ND 0x1E038018,0x000001C0 ++#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_1ST 0x1E038018,0x00000038 ++#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_1ST 0x1E038018,0x00000007 ++ ++#define IPU_CSI1_CCIR_CODE_3__ADDR 0x1E03801C ++#define IPU_CSI1_CCIR_CODE_3__EMPTY 0x1E03801C,0x00000000 ++#define IPU_CSI1_CCIR_CODE_3__FULL 0x1E03801C,0xffffffff ++#define IPU_CSI1_CCIR_CODE_3__CSI1_CCIR_PRECOM 0x1E03801C,0x3FFFFFFF ++ ++#define IPU_CSI1_DI__ADDR 0x1E038020 ++#define IPU_CSI1_DI__EMPTY 0x1E038020,0x00000000 ++#define IPU_CSI1_DI__FULL 0x1E038020,0xffffffff ++#define IPU_CSI1_DI__CSI1_MIPI_DI3 0x1E038020,0xFF000000 ++#define IPU_CSI1_DI__CSI1_MIPI_DI2 0x1E038020,0x00FF0000 ++#define IPU_CSI1_DI__CSI1_MIPI_DI1 0x1E038020,0x0000FF00 ++#define IPU_CSI1_DI__CSI1_MIPI_DI0 0x1E038020,0x000000FF ++ ++#define IPU_CSI1_SKIP__ADDR 0x1E038024 ++#define IPU_CSI1_SKIP__EMPTY 0x1E038024,0x00000000 ++#define IPU_CSI1_SKIP__FULL 0x1E038024,0xffffffff ++#define IPU_CSI1_SKIP__CSI1_SKIP_ISP 0x1E038024,0x00F80000 ++#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_ISP 0x1E038024,0x00070000 ++#define IPU_CSI1_SKIP__CSI1_ID_2_SKIP 0x1E038024,0x00000300 ++#define IPU_CSI1_SKIP__CSI1_SKIP_SMFC 0x1E038024,0x000000F8 ++#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_SMFC 0x1E038024,0x00000007 ++ ++#define IPU_CSI1_CPD_CTRL__ADDR 0x1E038028 ++#define IPU_CSI1_CPD_CTRL__EMPTY 0x1E038028,0x00000000 ++#define IPU_CSI1_CPD_CTRL__FULL 0x1E038028,0xffffffff ++#define IPU_CSI1_CPD_CTRL__CSI1_CPD 0x1E038028,0x0000001C ++#define IPU_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN 0x1E038028,0x00000002 ++#define IPU_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN 0x1E038028,0x00000001 ++ ++#define IPU_CSI1_CPD_RC_0__ADDR 0x1E03802C ++#define IPU_CSI1_CPD_RC_0__EMPTY 0x1E03802C,0x00000000 ++#define IPU_CSI1_CPD_RC_0__FULL 0x1E03802C,0xffffffff ++#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_1 0x1E03802C,0x01FF0000 ++#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_0 0x1E03802C,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_1__ADDR 0x1E038030 ++#define IPU_CSI1_CPD_RC_1__EMPTY 0x1E038030,0x00000000 ++#define IPU_CSI1_CPD_RC_1__FULL 0x1E038030,0xffffffff ++#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_3 0x1E038030,0x01FF0000 ++#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_2 0x1E038030,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_2__ADDR 0x1E038034 ++#define IPU_CSI1_CPD_RC_2__EMPTY 0x1E038034,0x00000000 ++#define IPU_CSI1_CPD_RC_2__FULL 0x1E038034,0xffffffff ++#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_5 0x1E038034,0x01FF0000 ++#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_4 0x1E038034,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_3__ADDR 0x1E038038 ++#define IPU_CSI1_CPD_RC_3__EMPTY 0x1E038038,0x00000000 ++#define IPU_CSI1_CPD_RC_3__FULL 0x1E038038,0xffffffff ++#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_7 0x1E038038,0x01FF0000 ++#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_6 0x1E038038,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_4__ADDR 0x1E03803C ++#define IPU_CSI1_CPD_RC_4__EMPTY 0x1E03803C,0x00000000 ++#define IPU_CSI1_CPD_RC_4__FULL 0x1E03803C,0xffffffff ++#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_9 0x1E03803C,0x01FF0000 ++#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_8 0x1E03803C,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_5__ADDR 0x1E038040 ++#define IPU_CSI1_CPD_RC_5__EMPTY 0x1E038040,0x00000000 ++#define IPU_CSI1_CPD_RC_5__FULL 0x1E038040,0xffffffff ++#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_11 0x1E038040,0x01FF0000 ++#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_10 0x1E038040,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_6__ADDR 0x1E038044 ++#define IPU_CSI1_CPD_RC_6__EMPTY 0x1E038044,0x00000000 ++#define IPU_CSI1_CPD_RC_6__FULL 0x1E038044,0xffffffff ++#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_13 0x1E038044,0x01FF0000 ++#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_12 0x1E038044,0x000001FF ++ ++#define IPU_CSI1_CPD_RC_7__ADDR 0x1E038048 ++#define IPU_CSI1_CPD_RC_7__EMPTY 0x1E038048,0x00000000 ++#define IPU_CSI1_CPD_RC_7__FULL 0x1E038048,0xffffffff ++#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_15 0x1E038048,0x01FF0000 ++#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_14 0x1E038048,0x000001FF ++ ++#define IPU_CSI1_CPD_RS_0__ADDR 0x1E03804C ++#define IPU_CSI1_CPD_RS_0__EMPTY 0x1E03804C,0x00000000 ++#define IPU_CSI1_CPD_RS_0__FULL 0x1E03804C,0xffffffff ++#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS3 0x1E03804C,0xFF000000 ++#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS2 0x1E03804C,0x00FF0000 ++#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS1 0x1E03804C,0x0000FF00 ++#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS0 0x1E03804C,0x000000FF ++ ++#define IPU_CSI1_CPD_RS_1__ADDR 0x1E038050 ++#define IPU_CSI1_CPD_RS_1__EMPTY 0x1E038050,0x00000000 ++#define IPU_CSI1_CPD_RS_1__FULL 0x1E038050,0xffffffff ++#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS7 0x1E038050,0xFF000000 ++#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS6 0x1E038050,0x00FF0000 ++#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS5 0x1E038050,0x0000FF00 ++#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS4 0x1E038050,0x000000FF ++ ++#define IPU_CSI1_CPD_RS_2__ADDR 0x1E038054 ++#define IPU_CSI1_CPD_RS_2__EMPTY 0x1E038054,0x00000000 ++#define IPU_CSI1_CPD_RS_2__FULL 0x1E038054,0xffffffff ++#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS11 0x1E038054,0xFF000000 ++#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS10 0x1E038054,0x00FF0000 ++#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS9 0x1E038054,0x0000FF00 ++#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS8 0x1E038054,0x000000FF ++ ++#define IPU_CSI1_CPD_RS_3__ADDR 0x1E038058 ++#define IPU_CSI1_CPD_RS_3__EMPTY 0x1E038058,0x00000000 ++#define IPU_CSI1_CPD_RS_3__FULL 0x1E038058,0xffffffff ++#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS15 0x1E038058,0xFF000000 ++#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS14 0x1E038058,0x00FF0000 ++#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS13 0x1E038058,0x0000FF00 ++#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS12 0x1E038058,0x000000FF ++ ++#define IPU_CSI1_CPD_GRC_0__ADDR 0x1E03805C ++#define IPU_CSI1_CPD_GRC_0__EMPTY 0x1E03805C,0x00000000 ++#define IPU_CSI1_CPD_GRC_0__FULL 0x1E03805C,0xffffffff ++#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC1 0x1E03805C,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC0 0x1E03805C,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_1__ADDR 0x1E038060 ++#define IPU_CSI1_CPD_GRC_1__EMPTY 0x1E038060,0x00000000 ++#define IPU_CSI1_CPD_GRC_1__FULL 0x1E038060,0xffffffff ++#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC3 0x1E038060,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC2 0x1E038060,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_2__ADDR 0x1E038064 ++#define IPU_CSI1_CPD_GRC_2__EMPTY 0x1E038064,0x00000000 ++#define IPU_CSI1_CPD_GRC_2__FULL 0x1E038064,0xffffffff ++#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC5 0x1E038064,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC4 0x1E038064,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_3__ADDR 0x1E038068 ++#define IPU_CSI1_CPD_GRC_3__EMPTY 0x1E038068,0x00000000 ++#define IPU_CSI1_CPD_GRC_3__FULL 0x1E038068,0xffffffff ++#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC7 0x1E038068,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC6 0x1E038068,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_4__ADDR 0x1E03806C ++#define IPU_CSI1_CPD_GRC_4__EMPTY 0x1E03806C,0x00000000 ++#define IPU_CSI1_CPD_GRC_4__FULL 0x1E03806C,0xffffffff ++#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC9 0x1E03806C,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC8 0x1E03806C,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_5__ADDR 0x1E038070 ++#define IPU_CSI1_CPD_GRC_5__EMPTY 0x1E038070,0x00000000 ++#define IPU_CSI1_CPD_GRC_5__FULL 0x1E038070,0xffffffff ++#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC11 0x1E038070,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC10 0x1E038070,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_6__ADDR 0x1E038074 ++#define IPU_CSI1_CPD_GRC_6__EMPTY 0x1E038074,0x00000000 ++#define IPU_CSI1_CPD_GRC_6__FULL 0x1E038074,0xffffffff ++#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC13 0x1E038074,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC12 0x1E038074,0x000001FF ++ ++#define IPU_CSI1_CPD_GRC_7__ADDR 0x1E038078 ++#define IPU_CSI1_CPD_GRC_7__EMPTY 0x1E038078,0x00000000 ++#define IPU_CSI1_CPD_GRC_7__FULL 0x1E038078,0xffffffff ++#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC15 0x1E038078,0x01FF0000 ++#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC14 0x1E038078,0x000001FF ++ ++#define IPU_CSI1_CPD_GRS_0__ADDR 0x1E03807C ++#define IPU_CSI1_CPD_GRS_0__EMPTY 0x1E03807C,0x00000000 ++#define IPU_CSI1_CPD_GRS_0__FULL 0x1E03807C,0xffffffff ++#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS3 0x1E03807C,0xFF000000 ++#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS2 0x1E03807C,0x00FF0000 ++#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS1 0x1E03807C,0x0000FF00 ++#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS0 0x1E03807C,0x000000FF ++ ++#define IPU_CSI1_CPD_GRS_1__ADDR 0x1E038080 ++#define IPU_CSI1_CPD_GRS_1__EMPTY 0x1E038080,0x00000000 ++#define IPU_CSI1_CPD_GRS_1__FULL 0x1E038080,0xffffffff ++#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS7 0x1E038080,0xFF000000 ++#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS6 0x1E038080,0x00FF0000 ++#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS5 0x1E038080,0x0000FF00 ++#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS4 0x1E038080,0x000000FF ++ ++#define IPU_CSI1_CPD_GRS_2__ADDR 0x1E038084 ++#define IPU_CSI1_CPD_GRS_2__EMPTY 0x1E038084,0x00000000 ++#define IPU_CSI1_CPD_GRS_2__FULL 0x1E038084,0xffffffff ++#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS11 0x1E038084,0xFF000000 ++#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS10 0x1E038084,0x00FF0000 ++#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS9 0x1E038084,0x0000FF00 ++#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS8 0x1E038084,0x000000FF ++ ++#define IPU_CSI1_CPD_GRS_3__ADDR 0x1E038088 ++#define IPU_CSI1_CPD_GRS_3__EMPTY 0x1E038088,0x00000000 ++#define IPU_CSI1_CPD_GRS_3__FULL 0x1E038088,0xffffffff ++#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS15 0x1E038088,0xFF000000 ++#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS14 0x1E038088,0x00FF0000 ++#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS13 0x1E038088,0x0000FF00 ++#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS12 0x1E038088,0x000000FF ++ ++#define IPU_CSI1_CPD_GBC_0__ADDR 0x1E03808C ++#define IPU_CSI1_CPD_GBC_0__EMPTY 0x1E03808C,0x00000000 ++#define IPU_CSI1_CPD_GBC_0__FULL 0x1E03808C,0xffffffff ++#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC1 0x1E03808C,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC0 0x1E03808C,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_1__ADDR 0x1E038090 ++#define IPU_CSI1_CPD_GBC_1__EMPTY 0x1E038090,0x00000000 ++#define IPU_CSI1_CPD_GBC_1__FULL 0x1E038090,0xffffffff ++#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC3 0x1E038090,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC2 0x1E038090,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_2__ADDR 0x1E038094 ++#define IPU_CSI1_CPD_GBC_2__EMPTY 0x1E038094,0x00000000 ++#define IPU_CSI1_CPD_GBC_2__FULL 0x1E038094,0xffffffff ++#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC5 0x1E038094,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC4 0x1E038094,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_3__ADDR 0x1E038098 ++#define IPU_CSI1_CPD_GBC_3__EMPTY 0x1E038098,0x00000000 ++#define IPU_CSI1_CPD_GBC_3__FULL 0x1E038098,0xffffffff ++#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC7 0x1E038098,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC6 0x1E038098,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_4__ADDR 0x1E03809C ++#define IPU_CSI1_CPD_GBC_4__EMPTY 0x1E03809C,0x00000000 ++#define IPU_CSI1_CPD_GBC_4__FULL 0x1E03809C,0xffffffff ++#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC9 0x1E03809C,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC8 0x1E03809C,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_5__ADDR 0x1E0380A0 ++#define IPU_CSI1_CPD_GBC_5__EMPTY 0x1E0380A0,0x00000000 ++#define IPU_CSI1_CPD_GBC_5__FULL 0x1E0380A0,0xffffffff ++#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC11 0x1E0380A0,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC10 0x1E0380A0,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_6__ADDR 0x1E0380A4 ++#define IPU_CSI1_CPD_GBC_6__EMPTY 0x1E0380A4,0x00000000 ++#define IPU_CSI1_CPD_GBC_6__FULL 0x1E0380A4,0xffffffff ++#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC13 0x1E0380A4,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC12 0x1E0380A4,0x000001FF ++ ++#define IPU_CSI1_CPD_GBC_7__ADDR 0x1E0380A8 ++#define IPU_CSI1_CPD_GBC_7__EMPTY 0x1E0380A8,0x00000000 ++#define IPU_CSI1_CPD_GBC_7__FULL 0x1E0380A8,0xffffffff ++#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC15 0x1E0380A8,0x01FF0000 ++#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC14 0x1E0380A8,0x000001FF ++ ++#define IPU_CSI1_CPD_GBS_0__ADDR 0x1E0380AC ++#define IPU_CSI1_CPD_GBS_0__EMPTY 0x1E0380AC,0x00000000 ++#define IPU_CSI1_CPD_GBS_0__FULL 0x1E0380AC,0xffffffff ++#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS3 0x1E0380AC,0xFF000000 ++#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS2 0x1E0380AC,0x00FF0000 ++#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS1 0x1E0380AC,0x0000FF00 ++#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS0 0x1E0380AC,0x000000FF ++ ++#define IPU_CSI1_CPD_GBS_1__ADDR 0x1E0380B0 ++#define IPU_CSI1_CPD_GBS_1__EMPTY 0x1E0380B0,0x00000000 ++#define IPU_CSI1_CPD_GBS_1__FULL 0x1E0380B0,0xffffffff ++#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS7 0x1E0380B0,0xFF000000 ++#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS6 0x1E0380B0,0x00FF0000 ++#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS5 0x1E0380B0,0x0000FF00 ++#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS4 0x1E0380B0,0x000000FF ++ ++#define IPU_CSI1_CPD_GBS_2__ADDR 0x1E0380B4 ++#define IPU_CSI1_CPD_GBS_2__EMPTY 0x1E0380B4,0x00000000 ++#define IPU_CSI1_CPD_GBS_2__FULL 0x1E0380B4,0xffffffff ++#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS11 0x1E0380B4,0xFF000000 ++#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS10 0x1E0380B4,0x00FF0000 ++#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS9 0x1E0380B4,0x0000FF00 ++#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS8 0x1E0380B4,0x000000FF ++ ++#define IPU_CSI1_CPD_GBS_3__ADDR 0x1E0380B8 ++#define IPU_CSI1_CPD_GBS_3__EMPTY 0x1E0380B8,0x00000000 ++#define IPU_CSI1_CPD_GBS_3__FULL 0x1E0380B8,0xffffffff ++#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS15 0x1E0380B8,0xFF000000 ++#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS14 0x1E0380B8,0x00FF0000 ++#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS13 0x1E0380B8,0x0000FF00 ++#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS12 0x1E0380B8,0x000000FF ++ ++#define IPU_CSI1_CPD_BC_0__ADDR 0x1E0380BC ++#define IPU_CSI1_CPD_BC_0__EMPTY 0x1E0380BC,0x00000000 ++#define IPU_CSI1_CPD_BC_0__FULL 0x1E0380BC,0xffffffff ++#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC1 0x1E0380BC,0x01FF0000 ++#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC0 0x1E0380BC,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_1__ADDR 0x1E0380C0 ++#define IPU_CSI1_CPD_BC_1__EMPTY 0x1E0380C0,0x00000000 ++#define IPU_CSI1_CPD_BC_1__FULL 0x1E0380C0,0xffffffff ++#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC3 0x1E0380C0,0x01FF0000 ++#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC2 0x1E0380C0,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_2__ADDR 0x1E0380C4 ++#define IPU_CSI1_CPD_BC_2__EMPTY 0x1E0380C4,0x00000000 ++#define IPU_CSI1_CPD_BC_2__FULL 0x1E0380C4,0xffffffff ++#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC5 0x1E0380C4,0x01FF0000 ++#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC4 0x1E0380C4,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_3__ADDR 0x1E0380C8 ++#define IPU_CSI1_CPD_BC_3__EMPTY 0x1E0380C8,0x00000000 ++#define IPU_CSI1_CPD_BC_3__FULL 0x1E0380C8,0xffffffff ++#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC7 0x1E0380C8,0x01FF0000 ++#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC6 0x1E0380C8,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_4__ADDR 0x1E0380CC ++#define IPU_CSI1_CPD_BC_4__EMPTY 0x1E0380CC,0x00000000 ++#define IPU_CSI1_CPD_BC_4__FULL 0x1E0380CC,0xffffffff ++#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC9 0x1E0380CC,0x01FF0000 ++#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC8 0x1E0380CC,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_5__ADDR 0x1E0380D0 ++#define IPU_CSI1_CPD_BC_5__EMPTY 0x1E0380D0,0x00000000 ++#define IPU_CSI1_CPD_BC_5__FULL 0x1E0380D0,0xffffffff ++#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC11 0x1E0380D0,0x01FF0000 ++#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC10 0x1E0380D0,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_6__ADDR 0x1E0380D4 ++#define IPU_CSI1_CPD_BC_6__EMPTY 0x1E0380D4,0x00000000 ++#define IPU_CSI1_CPD_BC_6__FULL 0x1E0380D4,0xffffffff ++#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC13 0x1E0380D4,0x01FF0000 ++#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC12 0x1E0380D4,0x000001FF ++ ++#define IPU_CSI1_CPD_BC_7__ADDR 0x1E0380D8 ++#define IPU_CSI1_CPD_BC_7__EMPTY 0x1E0380D8,0x00000000 ++#define IPU_CSI1_CPD_BC_7__FULL 0x1E0380D8,0xffffffff ++#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC15 0x1E0380D8,0x01FF0000 ++#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC14 0x1E0380D8,0x000001FF ++ ++#define IPU_CSI1_CPD_BS_0__ADDR 0x1E0380DC ++#define IPU_CSI1_CPD_BS_0__EMPTY 0x1E0380DC,0x00000000 ++#define IPU_CSI1_CPD_BS_0__FULL 0x1E0380DC,0xffffffff ++#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS3 0x1E0380DC,0xFF000000 ++#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS2 0x1E0380DC,0x00FF0000 ++#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS1 0x1E0380DC,0x0000FF00 ++#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS0 0x1E0380DC,0x000000FF ++ ++#define IPU_CSI1_CPD_BS_1__ADDR 0x1E0380E0 ++#define IPU_CSI1_CPD_BS_1__EMPTY 0x1E0380E0,0x00000000 ++#define IPU_CSI1_CPD_BS_1__FULL 0x1E0380E0,0xffffffff ++#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS7 0x1E0380E0,0xFF000000 ++#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS6 0x1E0380E0,0x00FF0000 ++#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS5 0x1E0380E0,0x0000FF00 ++#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS4 0x1E0380E0,0x000000FF ++ ++#define IPU_CSI1_CPD_BS_2__ADDR 0x1E0380E4 ++#define IPU_CSI1_CPD_BS_2__EMPTY 0x1E0380E4,0x00000000 ++#define IPU_CSI1_CPD_BS_2__FULL 0x1E0380E4,0xffffffff ++#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS11 0x1E0380E4,0xFF000000 ++#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS10 0x1E0380E4,0x00FF0000 ++#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS9 0x1E0380E4,0x0000FF00 ++#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS8 0x1E0380E4,0x000000FF ++ ++#define IPU_CSI1_CPD_BS_3__ADDR 0x1E0380E8 ++#define IPU_CSI1_CPD_BS_3__EMPTY 0x1E0380E8,0x00000000 ++#define IPU_CSI1_CPD_BS_3__FULL 0x1E0380E8,0xffffffff ++#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS15 0x1E0380E8,0xFF000000 ++#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS14 0x1E0380E8,0x00FF0000 ++#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS13 0x1E0380E8,0x0000FF00 ++#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS12 0x1E0380E8,0x000000FF ++ ++#define IPU_CSI1_CPD_OFFSET1__ADDR 0x1E0380EC ++#define IPU_CSI1_CPD_OFFSET1__EMPTY 0x1E0380EC,0x00000000 ++#define IPU_CSI1_CPD_OFFSET1__FULL 0x1E0380EC,0xffffffff ++#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET 0x1E0380EC,0x3FF00000 ++#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET 0x1E0380EC,0x000FFC00 ++#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET 0x1E0380EC,0x000003FF ++ ++#define IPU_CSI1_CPD_OFFSET2__ADDR 0x1E0380F0 ++#define IPU_CSI1_CPD_OFFSET2__EMPTY 0x1E0380F0,0x00000000 ++#define IPU_CSI1_CPD_OFFSET2__FULL 0x1E0380F0,0xffffffff ++#define IPU_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET 0x1E0380F0,0x000003FF ++// ================= End of IPUV3EX CSI Registers ===================== ++ ++// ================= Start of IPUV3EX DI Registers ===================== ++#define IPU_DI0_GENERAL__ADDR 0x1E040000 ++#define IPU_DI0_GENERAL__EMPTY 0x1E040000,0x00000000 ++#define IPU_DI0_GENERAL__FULL 0x1E040000,0xffffffff ++#define IPU_DI0_GENERAL__DI0_DISP_Y_SEL 0x1E040000,0x70000000 ++#define IPU_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1E040000,0x0F000000 ++#define IPU_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1E040000,0x00800000 ++#define IPU_DI0_GENERAL__DI0_MASK_SEL 0x1E040000,0x00400000 ++#define IPU_DI0_GENERAL__DI0_VSYNC_EXT 0x1E040000,0x00200000 ++#define IPU_DI0_GENERAL__DI0_CLK_EXT 0x1E040000,0x00100000 ++#define IPU_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1E040000,0x000C0000 ++#define IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1E040000,0x00020000 ++#define IPU_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1E040000,0x0000F000 ++#define IPU_DI0_GENERAL__DI0_ERR_TREATMENT 0x1E040000,0x00000800 ++#define IPU_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1E040000,0x00000400 ++#define IPU_DI0_GENERAL__DI0_POLARITY_CS1 0x1E040000,0x00000200 ++#define IPU_DI0_GENERAL__DI0_POLARITY_CS0 0x1E040000,0x00000100 ++#define IPU_DI0_GENERAL__DI0_POLARITY_8 0x1E040000,0x00000080 ++#define IPU_DI0_GENERAL__DI0_POLARITY_7 0x1E040000,0x00000040 ++#define IPU_DI0_GENERAL__DI0_POLARITY_6 0x1E040000,0x00000020 ++#define IPU_DI0_GENERAL__DI0_POLARITY_5 0x1E040000,0x00000010 ++#define IPU_DI0_GENERAL__DI0_POLARITY_4 0x1E040000,0x00000008 ++#define IPU_DI0_GENERAL__DI0_POLARITY_3 0x1E040000,0x00000004 ++#define IPU_DI0_GENERAL__DI0_POLARITY_2 0x1E040000,0x00000002 ++#define IPU_DI0_GENERAL__DI0_POLARITY_1 0x1E040000,0x00000001 ++ ++#define IPU_DI0_BS_CLKGEN0__ADDR 0x1E040004 ++#define IPU_DI0_BS_CLKGEN0__EMPTY 0x1E040004,0x00000000 ++#define IPU_DI0_BS_CLKGEN0__FULL 0x1E040004,0xffffffff ++#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1E040004,0x01FF0000 ++#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1E040004,0x00000FFF ++ ++#define IPU_DI0_BS_CLKGEN1__ADDR 0x1E040008 ++#define IPU_DI0_BS_CLKGEN1__EMPTY 0x1E040008,0x00000000 ++#define IPU_DI0_BS_CLKGEN1__FULL 0x1E040008,0xffffffff ++#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1E040008,0x01FF0000 ++#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1E040008,0x000001FF ++ ++#define DI_SWGEN0_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di *0x8000 + \ ++ (pointer-1) * 0x4 + 0x000C) ++#define DI_SWGEN0_EMPTY(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00000000 ++#define DI_SWGEN0_FULL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0xFFFFFFFF ++ ++#define DI_SWGEN0_RUN_VALUE_M1(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x7FF80000 ++#define DI_SWGEN0_RUN_RESOL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00070000 ++#define DI_SWGEN0_OFFSET_VALUE(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00007FF8 ++#define DI_SWGEN0_OFFSET_RESOL(di, pointer) DI_SWGEN0_ADDR(di, pointer), 0x00000007 ++ ++#define DI_SWGEN1_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di *0x8000 + \ ++ (pointer-1) * 0x4 + 0x0030) ++#define DI_SWGEN1_EMPTY(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000000 ++#define DI_SWGEN1_FULL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0xFFFFFFFF ++ ++#define DI_SWGEN1_CNT_POL_GEN_EN(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x60000000 ++#define DI_SWGEN1_CNT_AUTOLOAD(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x10000000 ++#define DI_SWGEN1_CNT_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x0E000000 ++#define DI_SWGEN1_CNT_DOW(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x01FF0000 ++#define DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00007000 ++#define DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000E00 ++#define DI_SWGEN1_CNT_CNT_UP(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x000001FF ++ ++/*sync waveform generator 9 is special*/ ++#define IPU_DI0_SW_GEN0_9__ADDR 0x1E04002C ++#define IPU_DI0_SW_GEN0_9__EMPTY 0x1E04002C,0x00000000 ++#define IPU_DI0_SW_GEN0_9__FULL 0x1E04002C,0xffffffff ++#define IPU_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1E04002C,0x7FF80000 ++#define IPU_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1E04002C,0x00070000 ++#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1E04002C,0x00007FF8 ++#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1E04002C,0x00000007 ++ ++#define IPU_DI0_SW_GEN1_9__ADDR 0x1E040050 ++#define IPU_DI0_SW_GEN1_9__EMPTY 0x1E040050,0x00000000 ++#define IPU_DI0_SW_GEN1_9__FULL 0x1E040050,0xffffffff ++#define IPU_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1E040050,0xE0000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1E040050,0x10000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1E040050,0x0E000000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1E040050,0x01FF0000 ++#define IPU_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1E040050,0x00008000 ++#define IPU_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1E040050,0x000001FF ++ ++#define IPU_DI0_SYNC_AS_GEN__ADDR 0x1E040054 ++#define IPU_DI0_SYNC_AS_GEN__EMPTY 0x1E040054,0x00000000 ++#define IPU_DI0_SYNC_AS_GEN__FULL 0x1E040054,0xffffffff ++#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1E040054,0x10000000 ++#define IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1E040054,0x0000E000 ++#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1E040054,0x00000FFF ++ ++#define IPU_DI0_DW_GEN_0__ADDR 0x1E040058 ++#define IPU_DI0_DW_GEN_0__EMPTY 0x1E040058,0x00000000 ++#define IPU_DI0_DW_GEN_0__FULL 0x1E040058,0xffffffff ++#define IPU_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1E040058,0xFF000000 ++#define IPU_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1E040058,0x00FF0000 ++#define IPU_DI0_DW_GEN_0__DI0_CST_0 0x1E040058,0x0000C000 ++#define IPU_DI0_DW_GEN_0__DI0_PT_6_0 0x1E040058,0x00003000 ++#define IPU_DI0_DW_GEN_0__DI0_PT_5_0 0x1E040058,0x00000C00 ++#define IPU_DI0_DW_GEN_0__DI0_PT_4_0 0x1E040058,0x00000300 ++#define IPU_DI0_DW_GEN_0__DI0_PT_3_0 0x1E040058,0x000000C0 ++#define IPU_DI0_DW_GEN_0__DI0_PT_2_0 0x1E040058,0x00000030 ++#define IPU_DI0_DW_GEN_0__DI0_PT_1_0 0x1E040058,0x0000000C ++#define IPU_DI0_DW_GEN_0__DI0_PT_0_0 0x1E040058,0x00000003 ++ ++#define IPU_DI0_DW_GEN_0__ADDR 0x1E040058 ++#define IPU_DI0_DW_GEN_0__EMPTY 0x1E040058,0x00000000 ++#define IPU_DI0_DW_GEN_0__FULL 0x1E040058,0xffffffff ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1E040058,0xFF000000 ++#define IPU_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1E040058,0x00FF0000 ++#define IPU_DI0_DW_GEN_0__DI0_CST_0 0x1E040058,0x0000C000 ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1E040058,0x000001F0 ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1E040058,0x0000000C ++#define IPU_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1E040058,0x00000003 ++ ++#define IPU_DI0_DW_GEN_1__ADDR 0x1E04005C ++#define IPU_DI0_DW_GEN_1__EMPTY 0x1E04005C,0x00000000 ++#define IPU_DI0_DW_GEN_1__FULL 0x1E04005C,0xffffffff ++#define IPU_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1E04005C,0xFF000000 ++#define IPU_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1E04005C,0x00FF0000 ++#define IPU_DI0_DW_GEN_1__DI0_CST_1 0x1E04005C,0x0000C000 ++#define IPU_DI0_DW_GEN_1__DI0_PT_6_1 0x1E04005C,0x00003000 ++#define IPU_DI0_DW_GEN_1__DI0_PT_5_1 0x1E04005C,0x00000C00 ++#define IPU_DI0_DW_GEN_1__DI0_PT_4_1 0x1E04005C,0x00000300 ++#define IPU_DI0_DW_GEN_1__DI0_PT_3_1 0x1E04005C,0x000000C0 ++#define IPU_DI0_DW_GEN_1__DI0_PT_2_1 0x1E04005C,0x00000030 ++#define IPU_DI0_DW_GEN_1__DI0_PT_1_1 0x1E04005C,0x0000000C ++#define IPU_DI0_DW_GEN_1__DI0_PT_0_1 0x1E04005C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_1__ADDR 0x1E04005C ++#define IPU_DI0_DW_GEN_1__EMPTY 0x1E04005C,0x00000000 ++#define IPU_DI0_DW_GEN_1__FULL 0x1E04005C,0xffffffff ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1E04005C,0xFF000000 ++#define IPU_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1E04005C,0x00FF0000 ++#define IPU_DI0_DW_GEN_1__DI0_CST_1 0x1E04005C,0x0000C000 ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1E04005C,0x000001F0 ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1E04005C,0x0000000C ++#define IPU_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1E04005C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_2__ADDR 0x1E040060 ++#define IPU_DI0_DW_GEN_2__EMPTY 0x1E040060,0x00000000 ++#define IPU_DI0_DW_GEN_2__FULL 0x1E040060,0xffffffff ++#define IPU_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1E040060,0xFF000000 ++#define IPU_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1E040060,0x00FF0000 ++#define IPU_DI0_DW_GEN_2__DI0_CST_2 0x1E040060,0x0000C000 ++#define IPU_DI0_DW_GEN_2__DI0_PT_6_2 0x1E040060,0x00003000 ++#define IPU_DI0_DW_GEN_2__DI0_PT_5_2 0x1E040060,0x00000C00 ++#define IPU_DI0_DW_GEN_2__DI0_PT_4_2 0x1E040060,0x00000300 ++#define IPU_DI0_DW_GEN_2__DI0_PT_3_2 0x1E040060,0x000000C0 ++#define IPU_DI0_DW_GEN_2__DI0_PT_2_2 0x1E040060,0x00000030 ++#define IPU_DI0_DW_GEN_2__DI0_PT_1_2 0x1E040060,0x0000000C ++#define IPU_DI0_DW_GEN_2__DI0_PT_0_2 0x1E040060,0x00000003 ++ ++#define IPU_DI0_DW_GEN_2__ADDR 0x1E040060 ++#define IPU_DI0_DW_GEN_2__EMPTY 0x1E040060,0x00000000 ++#define IPU_DI0_DW_GEN_2__FULL 0x1E040060,0xffffffff ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1E040060,0xFF000000 ++#define IPU_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1E040060,0x00FF0000 ++#define IPU_DI0_DW_GEN_2__DI0_CST_2 0x1E040060,0x0000C000 ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1E040060,0x000001F0 ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1E040060,0x0000000C ++#define IPU_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1E040060,0x00000003 ++ ++#define IPU_DI0_DW_GEN_3__ADDR 0x1E040064 ++#define IPU_DI0_DW_GEN_3__EMPTY 0x1E040064,0x00000000 ++#define IPU_DI0_DW_GEN_3__FULL 0x1E040064,0xffffffff ++#define IPU_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1E040064,0xFF000000 ++#define IPU_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1E040064,0x00FF0000 ++#define IPU_DI0_DW_GEN_3__DI0_CST_3 0x1E040064,0x0000C000 ++#define IPU_DI0_DW_GEN_3__DI0_PT_6_3 0x1E040064,0x00003000 ++#define IPU_DI0_DW_GEN_3__DI0_PT_5_3 0x1E040064,0x00000C00 ++#define IPU_DI0_DW_GEN_3__DI0_PT_4_3 0x1E040064,0x00000300 ++#define IPU_DI0_DW_GEN_3__DI0_PT_3_3 0x1E040064,0x000000C0 ++#define IPU_DI0_DW_GEN_3__DI0_PT_2_3 0x1E040064,0x00000030 ++#define IPU_DI0_DW_GEN_3__DI0_PT_1_3 0x1E040064,0x0000000C ++#define IPU_DI0_DW_GEN_3__DI0_PT_0_3 0x1E040064,0x00000003 ++ ++#define IPU_DI0_DW_GEN_3__ADDR 0x1E040064 ++#define IPU_DI0_DW_GEN_3__EMPTY 0x1E040064,0x00000000 ++#define IPU_DI0_DW_GEN_3__FULL 0x1E040064,0xffffffff ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1E040064,0xFF000000 ++#define IPU_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1E040064,0x00FF0000 ++#define IPU_DI0_DW_GEN_3__DI0_CST_3 0x1E040064,0x0000C000 ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1E040064,0x000001F0 ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1E040064,0x0000000C ++#define IPU_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1E040064,0x00000003 ++ ++#define IPU_DI0_DW_GEN_4__ADDR 0x1E040068 ++#define IPU_DI0_DW_GEN_4__EMPTY 0x1E040068,0x00000000 ++#define IPU_DI0_DW_GEN_4__FULL 0x1E040068,0xffffffff ++#define IPU_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1E040068,0xFF000000 ++#define IPU_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1E040068,0x00FF0000 ++#define IPU_DI0_DW_GEN_4__DI0_CST_4 0x1E040068,0x0000C000 ++#define IPU_DI0_DW_GEN_4__DI0_PT_6_4 0x1E040068,0x00003000 ++#define IPU_DI0_DW_GEN_4__DI0_PT_5_4 0x1E040068,0x00000C00 ++#define IPU_DI0_DW_GEN_4__DI0_PT_4_4 0x1E040068,0x00000300 ++#define IPU_DI0_DW_GEN_4__DI0_PT_3_4 0x1E040068,0x000000C0 ++#define IPU_DI0_DW_GEN_4__DI0_PT_2_4 0x1E040068,0x00000030 ++#define IPU_DI0_DW_GEN_4__DI0_PT_1_4 0x1E040068,0x0000000C ++#define IPU_DI0_DW_GEN_4__DI0_PT_0_4 0x1E040068,0x00000003 ++ ++#define IPU_DI0_DW_GEN_4__ADDR 0x1E040068 ++#define IPU_DI0_DW_GEN_4__EMPTY 0x1E040068,0x00000000 ++#define IPU_DI0_DW_GEN_4__FULL 0x1E040068,0xffffffff ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1E040068,0xFF000000 ++#define IPU_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1E040068,0x00FF0000 ++#define IPU_DI0_DW_GEN_4__DI0_CST_4 0x1E040068,0x0000C000 ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1E040068,0x000001F0 ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1E040068,0x0000000C ++#define IPU_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1E040068,0x00000003 ++ ++#define IPU_DI0_DW_GEN_5__ADDR 0x1E04006C ++#define IPU_DI0_DW_GEN_5__EMPTY 0x1E04006C,0x00000000 ++#define IPU_DI0_DW_GEN_5__FULL 0x1E04006C,0xffffffff ++#define IPU_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1E04006C,0xFF000000 ++#define IPU_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1E04006C,0x00FF0000 ++#define IPU_DI0_DW_GEN_5__DI0_CST_5 0x1E04006C,0x0000C000 ++#define IPU_DI0_DW_GEN_5__DI0_PT_6_5 0x1E04006C,0x00003000 ++#define IPU_DI0_DW_GEN_5__DI0_PT_5_5 0x1E04006C,0x00000C00 ++#define IPU_DI0_DW_GEN_5__DI0_PT_4_5 0x1E04006C,0x00000300 ++#define IPU_DI0_DW_GEN_5__DI0_PT_3_5 0x1E04006C,0x000000C0 ++#define IPU_DI0_DW_GEN_5__DI0_PT_2_5 0x1E04006C,0x00000030 ++#define IPU_DI0_DW_GEN_5__DI0_PT_1_5 0x1E04006C,0x0000000C ++#define IPU_DI0_DW_GEN_5__DI0_PT_0_5 0x1E04006C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_5__ADDR 0x1E04006C ++#define IPU_DI0_DW_GEN_5__EMPTY 0x1E04006C,0x00000000 ++#define IPU_DI0_DW_GEN_5__FULL 0x1E04006C,0xffffffff ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1E04006C,0xFF000000 ++#define IPU_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1E04006C,0x00FF0000 ++#define IPU_DI0_DW_GEN_5__DI0_CST_5 0x1E04006C,0x0000C000 ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1E04006C,0x000001F0 ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1E04006C,0x0000000C ++#define IPU_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1E04006C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_6__ADDR 0x1E040070 ++#define IPU_DI0_DW_GEN_6__EMPTY 0x1E040070,0x00000000 ++#define IPU_DI0_DW_GEN_6__FULL 0x1E040070,0xffffffff ++#define IPU_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1E040070,0xFF000000 ++#define IPU_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1E040070,0x00FF0000 ++#define IPU_DI0_DW_GEN_6__DI0_CST_6 0x1E040070,0x0000C000 ++#define IPU_DI0_DW_GEN_6__DI0_PT_6_6 0x1E040070,0x00003000 ++#define IPU_DI0_DW_GEN_6__DI0_PT_5_6 0x1E040070,0x00000C00 ++#define IPU_DI0_DW_GEN_6__DI0_PT_4_6 0x1E040070,0x00000300 ++#define IPU_DI0_DW_GEN_6__DI0_PT_3_6 0x1E040070,0x000000C0 ++#define IPU_DI0_DW_GEN_6__DI0_PT_2_6 0x1E040070,0x00000030 ++#define IPU_DI0_DW_GEN_6__DI0_PT_1_6 0x1E040070,0x0000000C ++#define IPU_DI0_DW_GEN_6__DI0_PT_0_6 0x1E040070,0x00000003 ++ ++#define IPU_DI0_DW_GEN_6__ADDR 0x1E040070 ++#define IPU_DI0_DW_GEN_6__EMPTY 0x1E040070,0x00000000 ++#define IPU_DI0_DW_GEN_6__FULL 0x1E040070,0xffffffff ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1E040070,0xFF000000 ++#define IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1E040070,0x00FF0000 ++#define IPU_DI0_DW_GEN_6__DI0_CST_6 0x1E040070,0x0000C000 ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1E040070,0x000001F0 ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1E040070,0x0000000C ++#define IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1E040070,0x00000003 ++ ++#define IPU_DI0_DW_GEN_7__ADDR 0x1E040074 ++#define IPU_DI0_DW_GEN_7__EMPTY 0x1E040074,0x00000000 ++#define IPU_DI0_DW_GEN_7__FULL 0x1E040074,0xffffffff ++#define IPU_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1E040074,0xFF000000 ++#define IPU_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1E040074,0x00FF0000 ++#define IPU_DI0_DW_GEN_7__DI0_CST_7 0x1E040074,0x0000C000 ++#define IPU_DI0_DW_GEN_7__DI0_PT_6_7 0x1E040074,0x00003000 ++#define IPU_DI0_DW_GEN_7__DI0_PT_5_7 0x1E040074,0x00000C00 ++#define IPU_DI0_DW_GEN_7__DI0_PT_4_7 0x1E040074,0x00000300 ++#define IPU_DI0_DW_GEN_7__DI0_PT_3_7 0x1E040074,0x000000C0 ++#define IPU_DI0_DW_GEN_7__DI0_PT_2_7 0x1E040074,0x00000030 ++#define IPU_DI0_DW_GEN_7__DI0_PT_1_7 0x1E040074,0x0000000C ++#define IPU_DI0_DW_GEN_7__DI0_PT_0_7 0x1E040074,0x00000003 ++ ++#define IPU_DI0_DW_GEN_7__ADDR 0x1E040074 ++#define IPU_DI0_DW_GEN_7__EMPTY 0x1E040074,0x00000000 ++#define IPU_DI0_DW_GEN_7__FULL 0x1E040074,0xffffffff ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1E040074,0xFF000000 ++#define IPU_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1E040074,0x00FF0000 ++#define IPU_DI0_DW_GEN_7__DI0_CST_7 0x1E040074,0x0000C000 ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1E040074,0x000001F0 ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1E040074,0x0000000C ++#define IPU_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1E040074,0x00000003 ++ ++#define IPU_DI0_DW_GEN_8__ADDR 0x1E040078 ++#define IPU_DI0_DW_GEN_8__EMPTY 0x1E040078,0x00000000 ++#define IPU_DI0_DW_GEN_8__FULL 0x1E040078,0xffffffff ++#define IPU_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1E040078,0xFF000000 ++#define IPU_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1E040078,0x00FF0000 ++#define IPU_DI0_DW_GEN_8__DI0_CST_8 0x1E040078,0x0000C000 ++#define IPU_DI0_DW_GEN_8__DI0_PT_6_8 0x1E040078,0x00003000 ++#define IPU_DI0_DW_GEN_8__DI0_PT_5_8 0x1E040078,0x00000C00 ++#define IPU_DI0_DW_GEN_8__DI0_PT_4_8 0x1E040078,0x00000300 ++#define IPU_DI0_DW_GEN_8__DI0_PT_3_8 0x1E040078,0x000000C0 ++#define IPU_DI0_DW_GEN_8__DI0_PT_2_8 0x1E040078,0x00000030 ++#define IPU_DI0_DW_GEN_8__DI0_PT_1_8 0x1E040078,0x0000000C ++#define IPU_DI0_DW_GEN_8__DI0_PT_0_8 0x1E040078,0x00000003 ++ ++#define IPU_DI0_DW_GEN_8__ADDR 0x1E040078 ++#define IPU_DI0_DW_GEN_8__EMPTY 0x1E040078,0x00000000 ++#define IPU_DI0_DW_GEN_8__FULL 0x1E040078,0xffffffff ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1E040078,0xFF000000 ++#define IPU_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1E040078,0x00FF0000 ++#define IPU_DI0_DW_GEN_8__DI0_CST_8 0x1E040078,0x0000C000 ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1E040078,0x000001F0 ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1E040078,0x0000000C ++#define IPU_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1E040078,0x00000003 ++ ++#define IPU_DI0_DW_GEN_9__ADDR 0x1E04007C ++#define IPU_DI0_DW_GEN_9__EMPTY 0x1E04007C,0x00000000 ++#define IPU_DI0_DW_GEN_9__FULL 0x1E04007C,0xffffffff ++#define IPU_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1E04007C,0xFF000000 ++#define IPU_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1E04007C,0x00FF0000 ++#define IPU_DI0_DW_GEN_9__DI0_CST_9 0x1E04007C,0x0000C000 ++#define IPU_DI0_DW_GEN_9__DI0_PT_6_9 0x1E04007C,0x00003000 ++#define IPU_DI0_DW_GEN_9__DI0_PT_5_9 0x1E04007C,0x00000C00 ++#define IPU_DI0_DW_GEN_9__DI0_PT_4_9 0x1E04007C,0x00000300 ++#define IPU_DI0_DW_GEN_9__DI0_PT_3_9 0x1E04007C,0x000000C0 ++#define IPU_DI0_DW_GEN_9__DI0_PT_2_9 0x1E04007C,0x00000030 ++#define IPU_DI0_DW_GEN_9__DI0_PT_1_9 0x1E04007C,0x0000000C ++#define IPU_DI0_DW_GEN_9__DI0_PT_0_9 0x1E04007C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_9__ADDR 0x1E04007C ++#define IPU_DI0_DW_GEN_9__EMPTY 0x1E04007C,0x00000000 ++#define IPU_DI0_DW_GEN_9__FULL 0x1E04007C,0xffffffff ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1E04007C,0xFF000000 ++#define IPU_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1E04007C,0x00FF0000 ++#define IPU_DI0_DW_GEN_9__DI0_CST_9 0x1E04007C,0x0000C000 ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1E04007C,0x000001F0 ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1E04007C,0x0000000C ++#define IPU_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1E04007C,0x00000003 ++ ++#define IPU_DI0_DW_GEN_10__ADDR 0x1E040080 ++#define IPU_DI0_DW_GEN_10__EMPTY 0x1E040080,0x00000000 ++#define IPU_DI0_DW_GEN_10__FULL 0x1E040080,0xffffffff ++#define IPU_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1E040080,0xFF000000 ++#define IPU_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1E040080,0x00FF0000 ++#define IPU_DI0_DW_GEN_10__DI0_CST_10 0x1E040080,0x0000C000 ++#define IPU_DI0_DW_GEN_10__DI0_PT_6_10 0x1E040080,0x00003000 ++#define IPU_DI0_DW_GEN_10__DI0_PT_5_10 0x1E040080,0x00000C00 ++#define IPU_DI0_DW_GEN_10__DI0_PT_4_10 0x1E040080,0x00000300 ++#define IPU_DI0_DW_GEN_10__DI0_PT_3_10 0x1E040080,0x000000C0 ++#define IPU_DI0_DW_GEN_10__DI0_PT_2_10 0x1E040080,0x00000030 ++#define IPU_DI0_DW_GEN_10__DI0_PT_1_10 0x1E040080,0x0000000C ++#define IPU_DI0_DW_GEN_10__DI0_PT_0_10 0x1E040080,0x00000003 ++ ++#define IPU_DI0_DW_GEN_10__ADDR 0x1E040080 ++#define IPU_DI0_DW_GEN_10__EMPTY 0x1E040080,0x00000000 ++#define IPU_DI0_DW_GEN_10__FULL 0x1E040080,0xffffffff ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1E040080,0xFF000000 ++#define IPU_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1E040080,0x00FF0000 ++#define IPU_DI0_DW_GEN_10__DI0_CST_10 0x1E040080,0x0000C000 ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E040080,0x000001F0 ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1E040080,0x0000000C ++#define IPU_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1E040080,0x00000003 ++ ++#define IPU_DI0_DW_GEN_11__ADDR 0x1E040084 ++#define IPU_DI0_DW_GEN_11__EMPTY 0x1E040084,0x00000000 ++#define IPU_DI0_DW_GEN_11__FULL 0x1E040084,0xffffffff ++#define IPU_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1E040084,0xFF000000 ++#define IPU_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1E040084,0x00FF0000 ++#define IPU_DI0_DW_GEN_11__DI0_CST_11 0x1E040084,0x0000C000 ++#define IPU_DI0_DW_GEN_11__DI0_PT_6_11 0x1E040084,0x00003000 ++#define IPU_DI0_DW_GEN_11__DI0_PT_5_11 0x1E040084,0x00000C00 ++#define IPU_DI0_DW_GEN_11__DI0_PT_4_11 0x1E040084,0x00000300 ++#define IPU_DI0_DW_GEN_11__DI0_PT_3_11 0x1E040084,0x000000C0 ++#define IPU_DI0_DW_GEN_11__DI0_PT_2_11 0x1E040084,0x00000030 ++#define IPU_DI0_DW_GEN_11__DI0_PT_1_11 0x1E040084,0x0000000C ++#define IPU_DI0_DW_GEN_11__DI0_PT_0_11 0x1E040084,0x00000003 ++ ++#define IPU_DI0_DW_GEN_11__ADDR 0x1E040084 ++#define IPU_DI0_DW_GEN_11__EMPTY 0x1E040084,0x00000000 ++#define IPU_DI0_DW_GEN_11__FULL 0x1E040084,0xffffffff ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1E040084,0xFF000000 ++#define IPU_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1E040084,0x00FF0000 ++#define IPU_DI0_DW_GEN_11__DI0_CST_11 0x1E040084,0x0000C000 ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E040084,0x000001F0 ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1E040084,0x0000000C ++#define IPU_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1E040084,0x00000003 ++ ++#define IPU_DI_DW_OFFSET 0x0088 ++#define DI_WAVESET_ADDR(di, pointer, set) (IPU_DI0_GENERAL__ADDR + \ ++ di*0x8000 + IPU_DI_DW_OFFSET + \ ++ pointer*0x4 + set * 0x30) ++#define DI_WAVESET_UP(di, pointer, set) DI_WAVESET_ADDR(di, pointer, set), 0x000001FF ++#define DI_WAVESET_DOWN(di, pointer, set) DI_WAVESET_ADDR(di, pointer, set), 0x01FF0000 ++ ++#define IPU_DI_STEP_RPT_OFFSET 0x0148 ++#define DI_STEP_RPT_ADDR(di, pointer) (IPU_DI0_GENERAL__ADDR + \ ++ di*0x8000 + IPU_DI_STEP_RPT_OFFSET + \ ++ ((pointer-1) / 2)*0x4 ) ++#define DI_STEP_RPT(di, pointer) DI_STEP_RPT_ADDR(di, pointer), 0x0FFF<<((pointer-1)%2)*16 ++ ++#define IPU_DI0_STP_REP_9__ADDR 0x1E040158 ++#define IPU_DI0_STP_REP_9__EMPTY 0x1E040158,0x00000000 ++#define IPU_DI0_STP_REP_9__FULL 0x1E040158,0xffffffff ++#define IPU_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1E040158,0x00000FFF ++ ++#define IPU_DI0_SER_CONF__ADDR 0x1E04015C ++#define IPU_DI0_SER_CONF__EMPTY 0x1E04015C,0x00000000 ++#define IPU_DI0_SER_CONF__FULL 0x1E04015C,0xffffffff ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1E04015C,0xF0000000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1E04015C,0x0F000000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1E04015C,0x00F00000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1E04015C,0x000F0000 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1E04015C,0x0000FF00 ++#define IPU_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1E04015C,0x00000020 ++#define IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1E04015C,0x00000010 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1E04015C,0x00000008 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1E04015C,0x00000004 ++#define IPU_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1E04015C,0x00000002 ++#define IPU_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1E04015C,0x00000001 ++ ++#define IPU_DI0_SSC__ADDR 0x1E040160 ++#define IPU_DI0_SSC__EMPTY 0x1E040160,0x00000000 ++#define IPU_DI0_SSC__FULL 0x1E040160,0xffffffff ++#define IPU_DI0_SSC__DI0_PIN17_ERM 0x1E040160,0x00800000 ++#define IPU_DI0_SSC__DI0_PIN16_ERM 0x1E040160,0x00400000 ++#define IPU_DI0_SSC__DI0_PIN15_ERM 0x1E040160,0x00200000 ++#define IPU_DI0_SSC__DI0_PIN14_ERM 0x1E040160,0x00100000 ++#define IPU_DI0_SSC__DI0_PIN13_ERM 0x1E040160,0x00080000 ++#define IPU_DI0_SSC__DI0_PIN12_ERM 0x1E040160,0x00040000 ++#define IPU_DI0_SSC__DI0_PIN11_ERM 0x1E040160,0x00020000 ++#define IPU_DI0_SSC__DI0_CS_ERM 0x1E040160,0x00010000 ++#define IPU_DI0_SSC__DI0_WAIT_ON 0x1E040160,0x00000020 ++#define IPU_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1E040160,0x00000008 ++#define IPU_DI0_SSC__DI0_BYTE_EN_PNTR 0x1E040160,0x00000007 ++ ++#define IPU_DI0_POL__ADDR 0x1E040164 ++#define IPU_DI0_POL__EMPTY 0x1E040164,0x00000000 ++#define IPU_DI0_POL__FULL 0x1E040164,0xffffffff ++#define IPU_DI0_POL__DI0_WAIT_POLARITY 0x1E040164,0x04000000 ++#define IPU_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1E040164,0x02000000 ++#define IPU_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1E040164,0x01000000 ++#define IPU_DI0_POL__DI0_CS1_DATA_POLARITY 0x1E040164,0x00800000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_17 0x1E040164,0x00400000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_16 0x1E040164,0x00200000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_15 0x1E040164,0x00100000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_14 0x1E040164,0x00080000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_13 0x1E040164,0x00040000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_12 0x1E040164,0x00020000 ++#define IPU_DI0_POL__DI0_CS1_POLARITY_11 0x1E040164,0x00010000 ++#define IPU_DI0_POL__DI0_CS0_DATA_POLARITY 0x1E040164,0x00008000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_17 0x1E040164,0x00004000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_16 0x1E040164,0x00002000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_15 0x1E040164,0x00001000 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_14 0x1E040164,0x00000800 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_13 0x1E040164,0x00000400 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_12 0x1E040164,0x00000200 ++#define IPU_DI0_POL__DI0_CS0_POLARITY_11 0x1E040164,0x00000100 ++#define IPU_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1E040164,0x00000080 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_17 0x1E040164,0x00000040 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_16 0x1E040164,0x00000020 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_15 0x1E040164,0x00000010 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_14 0x1E040164,0x00000008 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_13 0x1E040164,0x00000004 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_12 0x1E040164,0x00000002 ++#define IPU_DI0_POL__DI0_DRDY_POLARITY_11 0x1E040164,0x00000001 ++ ++#define IPU_DI0_AW0__ADDR 0x1E040168 ++#define IPU_DI0_AW0__EMPTY 0x1E040168,0x00000000 ++#define IPU_DI0_AW0__FULL 0x1E040168,0xffffffff ++#define IPU_DI0_AW0__DI0_AW_TRIG_SEL 0x1E040168,0xF0000000 ++#define IPU_DI0_AW0__DI0_AW_HEND 0x1E040168,0x0FFF0000 ++#define IPU_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1E040168,0x0000F000 ++#define IPU_DI0_AW0__DI0_AW_HSTART 0x1E040168,0x00000FFF ++ ++#define IPU_DI0_AW1__ADDR 0x1E04016C ++#define IPU_DI0_AW1__EMPTY 0x1E04016C,0x00000000 ++#define IPU_DI0_AW1__FULL 0x1E04016C,0xffffffff ++#define IPU_DI0_AW1__DI0_AW_VEND 0x1E04016C,0x0FFF0000 ++#define IPU_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1E04016C,0x0000F000 ++#define IPU_DI0_AW1__DI0_AW_VSTART 0x1E04016C,0x00000FFF ++ ++#define IPU_DI0_SCR_CONF__ADDR 0x1E040170 ++#define IPU_DI0_SCR_CONF__EMPTY 0x1E040170,0x00000000 ++#define IPU_DI0_SCR_CONF__FULL 0x1E040170,0xffffffff ++#define IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1E040170,0x00000FFF ++ ++#define IPU_DI0_STAT__ADDR 0x1E040174 ++#define IPU_DI0_STAT__EMPTY 0x1E040174,0x00000000 ++#define IPU_DI0_STAT__FULL 0x1E040174,0xffffffff ++#define IPU_DI0_STAT__DI0_CNTR_FIFO_FULL 0x1E040174,0x00000008 ++#define IPU_DI0_STAT__DI0_CNTR_FIFO_EMPTY 0x1E040174,0x00000004 ++#define IPU_DI0_STAT__DI0_READ_FIFO_FULL 0x1E040174,0x00000002 ++#define IPU_DI0_STAT__DI0_READ_FIFO_EMPTY 0x1E040174,0x00000001 ++ ++#define IPU_DI1_GENERAL__ADDR 0x1E048000 ++#define IPU_DI1_GENERAL__EMPTY 0x1E048000,0x00000000 ++#define IPU_DI1_GENERAL__FULL 0x1E048000,0xffffffff ++#define IPU_DI1_GENERAL__DI1_DISP_Y_SEL 0x1E048000,0x70000000 ++#define IPU_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1E048000,0x0F000000 ++#define IPU_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1E048000,0x00800000 ++#define IPU_DI1_GENERAL__DI1_MASK_SEL 0x1E048000,0x00400000 ++#define IPU_DI1_GENERAL__DI1_VSYNC_EXT 0x1E048000,0x00200000 ++#define IPU_DI1_GENERAL__DI1_CLK_EXT 0x1E048000,0x00100000 ++#define IPU_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1E048000,0x000C0000 ++#define IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1E048000,0x00020000 ++#define IPU_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1E048000,0x0000F000 ++#define IPU_DI1_GENERAL__DI1_ERR_TREATMENT 0x1E048000,0x00000800 ++#define IPU_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1E048000,0x00000400 ++#define IPU_DI1_GENERAL__DI1_POLARITY_CS1 0x1E048000,0x00000200 ++#define IPU_DI1_GENERAL__DI1_POLARITY_CS0 0x1E048000,0x00000100 ++#define IPU_DI1_GENERAL__DI1_POLARITY_8 0x1E048000,0x00000080 ++#define IPU_DI1_GENERAL__DI1_POLARITY_7 0x1E048000,0x00000040 ++#define IPU_DI1_GENERAL__DI1_POLARITY_6 0x1E048000,0x00000020 ++#define IPU_DI1_GENERAL__DI1_POLARITY_5 0x1E048000,0x00000010 ++#define IPU_DI1_GENERAL__DI1_POLARITY_4 0x1E048000,0x00000008 ++#define IPU_DI1_GENERAL__DI1_POLARITY_3 0x1E048000,0x00000004 ++#define IPU_DI1_GENERAL__DI1_POLARITY_2 0x1E048000,0x00000002 ++#define IPU_DI1_GENERAL__DI1_POLARITY_1 0x1E048000,0x00000001 ++ ++#define IPU_DI1_BS_CLKGEN0__ADDR 0x1E048004 ++#define IPU_DI1_BS_CLKGEN0__EMPTY 0x1E048004,0x00000000 ++#define IPU_DI1_BS_CLKGEN0__FULL 0x1E048004,0xffffffff ++#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1E048004,0x01FF0000 ++#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1E048004,0x00000FFF ++ ++#define IPU_DI1_BS_CLKGEN1__ADDR 0x1E048008 ++#define IPU_DI1_BS_CLKGEN1__EMPTY 0x1E048008,0x00000000 ++#define IPU_DI1_BS_CLKGEN1__FULL 0x1E048008,0xffffffff ++#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1E048008,0x01FF0000 ++#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1E048008,0x000001FF ++ ++#define IPU_DI1_SW_GEN0_9__ADDR 0x1E04802C ++#define IPU_DI1_SW_GEN0_9__EMPTY 0x1E04802C,0x00000000 ++#define IPU_DI1_SW_GEN0_9__FULL 0x1E04802C,0xffffffff ++#define IPU_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1E04802C,0x7FF80000 ++#define IPU_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1E04802C,0x00070000 ++#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1E04802C,0x00007FF8 ++#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1E04802C,0x00000007 ++ ++#define IPU_DI1_SW_GEN1_9__ADDR 0x1E048050 ++#define IPU_DI1_SW_GEN1_9__EMPTY 0x1E048050,0x00000000 ++#define IPU_DI1_SW_GEN1_9__FULL 0x1E048050,0xffffffff ++#define IPU_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1E048050,0xE0000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1E048050,0x10000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1E048050,0x0E000000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1E048050,0x01FF0000 ++#define IPU_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1E048050,0x00008000 ++#define IPU_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1E048050,0x000001FF ++ ++#define IPU_DI1_SYNC_AS_GEN__ADDR 0x1E048054 ++#define IPU_DI1_SYNC_AS_GEN__EMPTY 0x1E048054,0x00000000 ++#define IPU_DI1_SYNC_AS_GEN__FULL 0x1E048054,0xffffffff ++#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1E048054,0x10000000 ++#define IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1E048054,0x0000E000 ++#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1E048054,0x00000FFF ++ ++#define IPU_DI1_DW_GEN_0__ADDR 0x1E048058 ++#define IPU_DI1_DW_GEN_0__EMPTY 0x1E048058,0x00000000 ++#define IPU_DI1_DW_GEN_0__FULL 0x1E048058,0xffffffff ++#define IPU_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1E048058,0xFF000000 ++#define IPU_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1E048058,0x00FF0000 ++#define IPU_DI1_DW_GEN_0__DI1_CST_0 0x1E048058,0x0000C000 ++#define IPU_DI1_DW_GEN_0__DI1_PT_6_0 0x1E048058,0x00003000 ++#define IPU_DI1_DW_GEN_0__DI1_PT_5_0 0x1E048058,0x00000C00 ++#define IPU_DI1_DW_GEN_0__DI1_PT_4_0 0x1E048058,0x00000300 ++#define IPU_DI1_DW_GEN_0__DI1_PT_3_0 0x1E048058,0x000000C0 ++#define IPU_DI1_DW_GEN_0__DI1_PT_2_0 0x1E048058,0x00000030 ++#define IPU_DI1_DW_GEN_0__DI1_PT_1_0 0x1E048058,0x0000000C ++#define IPU_DI1_DW_GEN_0__DI1_PT_0_0 0x1E048058,0x00000003 ++ ++#define IPU_DI1_DW_GEN_0__ADDR 0x1E048058 ++#define IPU_DI1_DW_GEN_0__EMPTY 0x1E048058,0x00000000 ++#define IPU_DI1_DW_GEN_0__FULL 0x1E048058,0xffffffff ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1E048058,0xFF000000 ++#define IPU_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1E048058,0x00FF0000 ++#define IPU_DI1_DW_GEN_0__DI1_CST_0 0x1E048058,0x0000C000 ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1E048058,0x000001F0 ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1E048058,0x0000000C ++#define IPU_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1E048058,0x00000003 ++ ++#define IPU_DI1_DW_GEN_1__ADDR 0x1E04805C ++#define IPU_DI1_DW_GEN_1__EMPTY 0x1E04805C,0x00000000 ++#define IPU_DI1_DW_GEN_1__FULL 0x1E04805C,0xffffffff ++#define IPU_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1E04805C,0xFF000000 ++#define IPU_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1E04805C,0x00FF0000 ++#define IPU_DI1_DW_GEN_1__DI1_CST_1 0x1E04805C,0x0000C000 ++#define IPU_DI1_DW_GEN_1__DI1_PT_6_1 0x1E04805C,0x00003000 ++#define IPU_DI1_DW_GEN_1__DI1_PT_5_1 0x1E04805C,0x00000C00 ++#define IPU_DI1_DW_GEN_1__DI1_PT_4_1 0x1E04805C,0x00000300 ++#define IPU_DI1_DW_GEN_1__DI1_PT_3_1 0x1E04805C,0x000000C0 ++#define IPU_DI1_DW_GEN_1__DI1_PT_2_1 0x1E04805C,0x00000030 ++#define IPU_DI1_DW_GEN_1__DI1_PT_1_1 0x1E04805C,0x0000000C ++#define IPU_DI1_DW_GEN_1__DI1_PT_0_1 0x1E04805C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_1__ADDR 0x1E04805C ++#define IPU_DI1_DW_GEN_1__EMPTY 0x1E04805C,0x00000000 ++#define IPU_DI1_DW_GEN_1__FULL 0x1E04805C,0xffffffff ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1E04805C,0xFF000000 ++#define IPU_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1E04805C,0x00FF0000 ++#define IPU_DI1_DW_GEN_1__DI1_CST_1 0x1E04805C,0x0000C000 ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1E04805C,0x000001F0 ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1E04805C,0x0000000C ++#define IPU_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1E04805C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_2__ADDR 0x1E048060 ++#define IPU_DI1_DW_GEN_2__EMPTY 0x1E048060,0x00000000 ++#define IPU_DI1_DW_GEN_2__FULL 0x1E048060,0xffffffff ++#define IPU_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1E048060,0xFF000000 ++#define IPU_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1E048060,0x00FF0000 ++#define IPU_DI1_DW_GEN_2__DI1_CST_2 0x1E048060,0x0000C000 ++#define IPU_DI1_DW_GEN_2__DI1_PT_6_2 0x1E048060,0x00003000 ++#define IPU_DI1_DW_GEN_2__DI1_PT_5_2 0x1E048060,0x00000C00 ++#define IPU_DI1_DW_GEN_2__DI1_PT_4_2 0x1E048060,0x00000300 ++#define IPU_DI1_DW_GEN_2__DI1_PT_3_2 0x1E048060,0x000000C0 ++#define IPU_DI1_DW_GEN_2__DI1_PT_2_2 0x1E048060,0x00000030 ++#define IPU_DI1_DW_GEN_2__DI1_PT_1_2 0x1E048060,0x0000000C ++#define IPU_DI1_DW_GEN_2__DI1_PT_0_2 0x1E048060,0x00000003 ++ ++#define IPU_DI1_DW_GEN_2__ADDR 0x1E048060 ++#define IPU_DI1_DW_GEN_2__EMPTY 0x1E048060,0x00000000 ++#define IPU_DI1_DW_GEN_2__FULL 0x1E048060,0xffffffff ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1E048060,0xFF000000 ++#define IPU_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1E048060,0x00FF0000 ++#define IPU_DI1_DW_GEN_2__DI1_CST_2 0x1E048060,0x0000C000 ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1E048060,0x000001F0 ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1E048060,0x0000000C ++#define IPU_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1E048060,0x00000003 ++ ++#define IPU_DI1_DW_GEN_3__ADDR 0x1E048064 ++#define IPU_DI1_DW_GEN_3__EMPTY 0x1E048064,0x00000000 ++#define IPU_DI1_DW_GEN_3__FULL 0x1E048064,0xffffffff ++#define IPU_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1E048064,0xFF000000 ++#define IPU_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1E048064,0x00FF0000 ++#define IPU_DI1_DW_GEN_3__DI1_CST_3 0x1E048064,0x0000C000 ++#define IPU_DI1_DW_GEN_3__DI1_PT_6_3 0x1E048064,0x00003000 ++#define IPU_DI1_DW_GEN_3__DI1_PT_5_3 0x1E048064,0x00000C00 ++#define IPU_DI1_DW_GEN_3__DI1_PT_4_3 0x1E048064,0x00000300 ++#define IPU_DI1_DW_GEN_3__DI1_PT_3_3 0x1E048064,0x000000C0 ++#define IPU_DI1_DW_GEN_3__DI1_PT_2_3 0x1E048064,0x00000030 ++#define IPU_DI1_DW_GEN_3__DI1_PT_1_3 0x1E048064,0x0000000C ++#define IPU_DI1_DW_GEN_3__DI1_PT_0_3 0x1E048064,0x00000003 ++ ++#define IPU_DI1_DW_GEN_3__ADDR 0x1E048064 ++#define IPU_DI1_DW_GEN_3__EMPTY 0x1E048064,0x00000000 ++#define IPU_DI1_DW_GEN_3__FULL 0x1E048064,0xffffffff ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1E048064,0xFF000000 ++#define IPU_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1E048064,0x00FF0000 ++#define IPU_DI1_DW_GEN_3__DI1_CST_3 0x1E048064,0x0000C000 ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1E048064,0x000001F0 ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1E048064,0x0000000C ++#define IPU_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1E048064,0x00000003 ++ ++#define IPU_DI1_DW_GEN_4__ADDR 0x1E048068 ++#define IPU_DI1_DW_GEN_4__EMPTY 0x1E048068,0x00000000 ++#define IPU_DI1_DW_GEN_4__FULL 0x1E048068,0xffffffff ++#define IPU_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1E048068,0xFF000000 ++#define IPU_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1E048068,0x00FF0000 ++#define IPU_DI1_DW_GEN_4__DI1_CST_4 0x1E048068,0x0000C000 ++#define IPU_DI1_DW_GEN_4__DI1_PT_6_4 0x1E048068,0x00003000 ++#define IPU_DI1_DW_GEN_4__DI1_PT_5_4 0x1E048068,0x00000C00 ++#define IPU_DI1_DW_GEN_4__DI1_PT_4_4 0x1E048068,0x00000300 ++#define IPU_DI1_DW_GEN_4__DI1_PT_3_4 0x1E048068,0x000000C0 ++#define IPU_DI1_DW_GEN_4__DI1_PT_2_4 0x1E048068,0x00000030 ++#define IPU_DI1_DW_GEN_4__DI1_PT_1_4 0x1E048068,0x0000000C ++#define IPU_DI1_DW_GEN_4__DI1_PT_0_4 0x1E048068,0x00000003 ++ ++#define IPU_DI1_DW_GEN_4__ADDR 0x1E048068 ++#define IPU_DI1_DW_GEN_4__EMPTY 0x1E048068,0x00000000 ++#define IPU_DI1_DW_GEN_4__FULL 0x1E048068,0xffffffff ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1E048068,0xFF000000 ++#define IPU_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1E048068,0x00FF0000 ++#define IPU_DI1_DW_GEN_4__DI1_CST_4 0x1E048068,0x0000C000 ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1E048068,0x000001F0 ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1E048068,0x0000000C ++#define IPU_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1E048068,0x00000003 ++ ++#define IPU_DI1_DW_GEN_5__ADDR 0x1E04806C ++#define IPU_DI1_DW_GEN_5__EMPTY 0x1E04806C,0x00000000 ++#define IPU_DI1_DW_GEN_5__FULL 0x1E04806C,0xffffffff ++#define IPU_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1E04806C,0xFF000000 ++#define IPU_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1E04806C,0x00FF0000 ++#define IPU_DI1_DW_GEN_5__DI1_CST_5 0x1E04806C,0x0000C000 ++#define IPU_DI1_DW_GEN_5__DI1_PT_6_5 0x1E04806C,0x00003000 ++#define IPU_DI1_DW_GEN_5__DI1_PT_5_5 0x1E04806C,0x00000C00 ++#define IPU_DI1_DW_GEN_5__DI1_PT_4_5 0x1E04806C,0x00000300 ++#define IPU_DI1_DW_GEN_5__DI1_PT_3_5 0x1E04806C,0x000000C0 ++#define IPU_DI1_DW_GEN_5__DI1_PT_2_5 0x1E04806C,0x00000030 ++#define IPU_DI1_DW_GEN_5__DI1_PT_1_5 0x1E04806C,0x0000000C ++#define IPU_DI1_DW_GEN_5__DI1_PT_0_5 0x1E04806C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_5__ADDR 0x1E04806C ++#define IPU_DI1_DW_GEN_5__EMPTY 0x1E04806C,0x00000000 ++#define IPU_DI1_DW_GEN_5__FULL 0x1E04806C,0xffffffff ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1E04806C,0xFF000000 ++#define IPU_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1E04806C,0x00FF0000 ++#define IPU_DI1_DW_GEN_5__DI1_CST_5 0x1E04806C,0x0000C000 ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1E04806C,0x000001F0 ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1E04806C,0x0000000C ++#define IPU_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1E04806C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_6__ADDR 0x1E048070 ++#define IPU_DI1_DW_GEN_6__EMPTY 0x1E048070,0x00000000 ++#define IPU_DI1_DW_GEN_6__FULL 0x1E048070,0xffffffff ++#define IPU_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1E048070,0xFF000000 ++#define IPU_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1E048070,0x00FF0000 ++#define IPU_DI1_DW_GEN_6__DI1_CST_6 0x1E048070,0x0000C000 ++#define IPU_DI1_DW_GEN_6__DI1_PT_6_6 0x1E048070,0x00003000 ++#define IPU_DI1_DW_GEN_6__DI1_PT_5_6 0x1E048070,0x00000C00 ++#define IPU_DI1_DW_GEN_6__DI1_PT_4_6 0x1E048070,0x00000300 ++#define IPU_DI1_DW_GEN_6__DI1_PT_3_6 0x1E048070,0x000000C0 ++#define IPU_DI1_DW_GEN_6__DI1_PT_2_6 0x1E048070,0x00000030 ++#define IPU_DI1_DW_GEN_6__DI1_PT_1_6 0x1E048070,0x0000000C ++#define IPU_DI1_DW_GEN_6__DI1_PT_0_6 0x1E048070,0x00000003 ++ ++#define IPU_DI1_DW_GEN_6__ADDR 0x1E048070 ++#define IPU_DI1_DW_GEN_6__EMPTY 0x1E048070,0x00000000 ++#define IPU_DI1_DW_GEN_6__FULL 0x1E048070,0xffffffff ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1E048070,0xFF000000 ++#define IPU_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1E048070,0x00FF0000 ++#define IPU_DI1_DW_GEN_6__DI1_CST_6 0x1E048070,0x0000C000 ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1E048070,0x000001F0 ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1E048070,0x0000000C ++#define IPU_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1E048070,0x00000003 ++ ++#define IPU_DI1_DW_GEN_7__ADDR 0x1E048074 ++#define IPU_DI1_DW_GEN_7__EMPTY 0x1E048074,0x00000000 ++#define IPU_DI1_DW_GEN_7__FULL 0x1E048074,0xffffffff ++#define IPU_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1E048074,0xFF000000 ++#define IPU_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1E048074,0x00FF0000 ++#define IPU_DI1_DW_GEN_7__DI1_CST_7 0x1E048074,0x0000C000 ++#define IPU_DI1_DW_GEN_7__DI1_PT_6_7 0x1E048074,0x00003000 ++#define IPU_DI1_DW_GEN_7__DI1_PT_5_7 0x1E048074,0x00000C00 ++#define IPU_DI1_DW_GEN_7__DI1_PT_4_7 0x1E048074,0x00000300 ++#define IPU_DI1_DW_GEN_7__DI1_PT_3_7 0x1E048074,0x000000C0 ++#define IPU_DI1_DW_GEN_7__DI1_PT_2_7 0x1E048074,0x00000030 ++#define IPU_DI1_DW_GEN_7__DI1_PT_1_7 0x1E048074,0x0000000C ++#define IPU_DI1_DW_GEN_7__DI1_PT_0_7 0x1E048074,0x00000003 ++ ++#define IPU_DI1_DW_GEN_7__ADDR 0x1E048074 ++#define IPU_DI1_DW_GEN_7__EMPTY 0x1E048074,0x00000000 ++#define IPU_DI1_DW_GEN_7__FULL 0x1E048074,0xffffffff ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1E048074,0xFF000000 ++#define IPU_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1E048074,0x00FF0000 ++#define IPU_DI1_DW_GEN_7__DI1_CST_7 0x1E048074,0x0000C000 ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1E048074,0x000001F0 ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1E048074,0x0000000C ++#define IPU_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1E048074,0x00000003 ++ ++#define IPU_DI1_DW_GEN_8__ADDR 0x1E048078 ++#define IPU_DI1_DW_GEN_8__EMPTY 0x1E048078,0x00000000 ++#define IPU_DI1_DW_GEN_8__FULL 0x1E048078,0xffffffff ++#define IPU_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1E048078,0xFF000000 ++#define IPU_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1E048078,0x00FF0000 ++#define IPU_DI1_DW_GEN_8__DI1_CST_8 0x1E048078,0x0000C000 ++#define IPU_DI1_DW_GEN_8__DI1_PT_6_8 0x1E048078,0x00003000 ++#define IPU_DI1_DW_GEN_8__DI1_PT_5_8 0x1E048078,0x00000C00 ++#define IPU_DI1_DW_GEN_8__DI1_PT_4_8 0x1E048078,0x00000300 ++#define IPU_DI1_DW_GEN_8__DI1_PT_3_8 0x1E048078,0x000000C0 ++#define IPU_DI1_DW_GEN_8__DI1_PT_2_8 0x1E048078,0x00000030 ++#define IPU_DI1_DW_GEN_8__DI1_PT_1_8 0x1E048078,0x0000000C ++#define IPU_DI1_DW_GEN_8__DI1_PT_0_8 0x1E048078,0x00000003 ++ ++#define IPU_DI1_DW_GEN_8__ADDR 0x1E048078 ++#define IPU_DI1_DW_GEN_8__EMPTY 0x1E048078,0x00000000 ++#define IPU_DI1_DW_GEN_8__FULL 0x1E048078,0xffffffff ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1E048078,0xFF000000 ++#define IPU_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1E048078,0x00FF0000 ++#define IPU_DI1_DW_GEN_8__DI1_CST_8 0x1E048078,0x0000C000 ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1E048078,0x000001F0 ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1E048078,0x0000000C ++#define IPU_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1E048078,0x00000003 ++ ++#define IPU_DI1_DW_GEN_9__ADDR 0x1E04807C ++#define IPU_DI1_DW_GEN_9__EMPTY 0x1E04807C,0x00000000 ++#define IPU_DI1_DW_GEN_9__FULL 0x1E04807C,0xffffffff ++#define IPU_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1E04807C,0xFF000000 ++#define IPU_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1E04807C,0x00FF0000 ++#define IPU_DI1_DW_GEN_9__DI1_CST_9 0x1E04807C,0x0000C000 ++#define IPU_DI1_DW_GEN_9__DI1_PT_6_9 0x1E04807C,0x00003000 ++#define IPU_DI1_DW_GEN_9__DI1_PT_5_9 0x1E04807C,0x00000C00 ++#define IPU_DI1_DW_GEN_9__DI1_PT_4_9 0x1E04807C,0x00000300 ++#define IPU_DI1_DW_GEN_9__DI1_PT_3_9 0x1E04807C,0x000000C0 ++#define IPU_DI1_DW_GEN_9__DI1_PT_2_9 0x1E04807C,0x00000030 ++#define IPU_DI1_DW_GEN_9__DI1_PT_1_9 0x1E04807C,0x0000000C ++#define IPU_DI1_DW_GEN_9__DI1_PT_0_9 0x1E04807C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_9__ADDR 0x1E04807C ++#define IPU_DI1_DW_GEN_9__EMPTY 0x1E04807C,0x00000000 ++#define IPU_DI1_DW_GEN_9__FULL 0x1E04807C,0xffffffff ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1E04807C,0xFF000000 ++#define IPU_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1E04807C,0x00FF0000 ++#define IPU_DI1_DW_GEN_9__DI1_CST_9 0x1E04807C,0x0000C000 ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1E04807C,0x000001F0 ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1E04807C,0x0000000C ++#define IPU_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1E04807C,0x00000003 ++ ++#define IPU_DI1_DW_GEN_10__ADDR 0x1E048080 ++#define IPU_DI1_DW_GEN_10__EMPTY 0x1E048080,0x00000000 ++#define IPU_DI1_DW_GEN_10__FULL 0x1E048080,0xffffffff ++#define IPU_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1E048080,0xFF000000 ++#define IPU_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1E048080,0x00FF0000 ++#define IPU_DI1_DW_GEN_10__DI1_CST_10 0x1E048080,0x0000C000 ++#define IPU_DI1_DW_GEN_10__DI1_PT_6_10 0x1E048080,0x00003000 ++#define IPU_DI1_DW_GEN_10__DI1_PT_5_10 0x1E048080,0x00000C00 ++#define IPU_DI1_DW_GEN_10__DI1_PT_4_10 0x1E048080,0x00000300 ++#define IPU_DI1_DW_GEN_10__DI1_PT_3_10 0x1E048080,0x000000C0 ++#define IPU_DI1_DW_GEN_10__DI1_PT_2_10 0x1E048080,0x00000030 ++#define IPU_DI1_DW_GEN_10__DI1_PT_1_10 0x1E048080,0x0000000C ++#define IPU_DI1_DW_GEN_10__DI1_PT_0_10 0x1E048080,0x00000003 ++ ++#define IPU_DI1_DW_GEN_10__ADDR 0x1E048080 ++#define IPU_DI1_DW_GEN_10__EMPTY 0x1E048080,0x00000000 ++#define IPU_DI1_DW_GEN_10__FULL 0x1E048080,0xffffffff ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1E048080,0xFF000000 ++#define IPU_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1E048080,0x00FF0000 ++#define IPU_DI1_DW_GEN_10__DI1_CST_10 0x1E048080,0x0000C000 ++#define IPU_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E048080,0x000001F0 ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1E048080,0x0000000C ++#define IPU_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1E048080,0x00000003 ++ ++#define IPU_DI1_DW_GEN_11__ADDR 0x1E048084 ++#define IPU_DI1_DW_GEN_11__EMPTY 0x1E048084,0x00000000 ++#define IPU_DI1_DW_GEN_11__FULL 0x1E048084,0xffffffff ++#define IPU_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1E048084,0xFF000000 ++#define IPU_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1E048084,0x00FF0000 ++#define IPU_DI1_DW_GEN_11__DI1_CST_11 0x1E048084,0x0000C000 ++#define IPU_DI1_DW_GEN_11__DI1_PT_6_11 0x1E048084,0x00003000 ++#define IPU_DI1_DW_GEN_11__DI1_PT_5_11 0x1E048084,0x00000C00 ++#define IPU_DI1_DW_GEN_11__DI1_PT_4_11 0x1E048084,0x00000300 ++#define IPU_DI1_DW_GEN_11__DI1_PT_3_11 0x1E048084,0x000000C0 ++#define IPU_DI1_DW_GEN_11__DI1_PT_2_11 0x1E048084,0x00000030 ++#define IPU_DI1_DW_GEN_11__DI1_PT_1_11 0x1E048084,0x0000000C ++#define IPU_DI1_DW_GEN_11__DI1_PT_0_11 0x1E048084,0x00000003 ++ ++#define IPU_DI1_DW_GEN_11__ADDR 0x1E048084 ++#define IPU_DI1_DW_GEN_11__EMPTY 0x1E048084,0x00000000 ++#define IPU_DI1_DW_GEN_11__FULL 0x1E048084,0xffffffff ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1E048084,0xFF000000 ++#define IPU_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1E048084,0x00FF0000 ++#define IPU_DI1_DW_GEN_11__DI1_CST_11 0x1E048084,0x0000C000 ++#define IPU_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E048084,0x000001F0 ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1E048084,0x0000000C ++#define IPU_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1E048084,0x00000003 ++ ++#define IPU_DI1_STP_REP_9__ADDR 0x1E048158 ++#define IPU_DI1_STP_REP_9__EMPTY 0x1E048158,0x00000000 ++#define IPU_DI1_STP_REP_9__FULL 0x1E048158,0xffffffff ++#define IPU_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1E048158,0x00000FFF ++ ++#define IPU_DI1_SER_CONF__ADDR 0x1E04815C ++#define IPU_DI1_SER_CONF__EMPTY 0x1E04815C,0x00000000 ++#define IPU_DI1_SER_CONF__FULL 0x1E04815C,0xffffffff ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1E04815C,0xF0000000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1E04815C,0x0F000000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1E04815C,0x00F00000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1E04815C,0x000F0000 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1E04815C,0x0000FF00 ++#define IPU_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1E04815C,0x00000020 ++#define IPU_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1E04815C,0x00000010 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1E04815C,0x00000008 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1E04815C,0x00000004 ++#define IPU_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1E04815C,0x00000002 ++#define IPU_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1E04815C,0x00000001 ++ ++#define IPU_DI1_SSC__ADDR 0x1E048160 ++#define IPU_DI1_SSC__EMPTY 0x1E048160,0x00000000 ++#define IPU_DI1_SSC__FULL 0x1E048160,0xffffffff ++#define IPU_DI1_SSC__DI1_PIN17_ERM 0x1E048160,0x00800000 ++#define IPU_DI1_SSC__DI1_PIN16_ERM 0x1E048160,0x00400000 ++#define IPU_DI1_SSC__DI1_PIN15_ERM 0x1E048160,0x00200000 ++#define IPU_DI1_SSC__DI1_PIN14_ERM 0x1E048160,0x00100000 ++#define IPU_DI1_SSC__DI1_PIN13_ERM 0x1E048160,0x00080000 ++#define IPU_DI1_SSC__DI1_PIN12_ERM 0x1E048160,0x00040000 ++#define IPU_DI1_SSC__DI1_PIN11_ERM 0x1E048160,0x00020000 ++#define IPU_DI1_SSC__DI1_CS_ERM 0x1E048160,0x00010000 ++#define IPU_DI1_SSC__DI1_WAIT_ON 0x1E048160,0x00000020 ++#define IPU_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1E048160,0x00000008 ++#define IPU_DI1_SSC__DI1_BYTE_EN_PNTR 0x1E048160,0x00000007 ++ ++#define IPU_DI1_POL__ADDR 0x1E048164 ++#define IPU_DI1_POL__EMPTY 0x1E048164,0x00000000 ++#define IPU_DI1_POL__FULL 0x1E048164,0xffffffff ++#define IPU_DI1_POL__DI1_WAIT_POLARITY 0x1E048164,0x04000000 ++#define IPU_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1E048164,0x02000000 ++#define IPU_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1E048164,0x01000000 ++#define IPU_DI1_POL__DI1_CS1_DATA_POLARITY 0x1E048164,0x00800000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_17 0x1E048164,0x00400000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_16 0x1E048164,0x00200000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_15 0x1E048164,0x00100000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_14 0x1E048164,0x00080000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_13 0x1E048164,0x00040000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_12 0x1E048164,0x00020000 ++#define IPU_DI1_POL__DI1_CS1_POLARITY_11 0x1E048164,0x00010000 ++#define IPU_DI1_POL__DI1_CS0_DATA_POLARITY 0x1E048164,0x00008000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_17 0x1E048164,0x00004000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_16 0x1E048164,0x00002000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_15 0x1E048164,0x00001000 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_14 0x1E048164,0x00000800 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_13 0x1E048164,0x00000400 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_12 0x1E048164,0x00000200 ++#define IPU_DI1_POL__DI1_CS0_POLARITY_11 0x1E048164,0x00000100 ++#define IPU_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1E048164,0x00000080 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_17 0x1E048164,0x00000040 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_16 0x1E048164,0x00000020 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_15 0x1E048164,0x00000010 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_14 0x1E048164,0x00000008 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_13 0x1E048164,0x00000004 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_12 0x1E048164,0x00000002 ++#define IPU_DI1_POL__DI1_DRDY_POLARITY_11 0x1E048164,0x00000001 ++ ++#define IPU_DI1_AW0__ADDR 0x1E048168 ++#define IPU_DI1_AW0__EMPTY 0x1E048168,0x00000000 ++#define IPU_DI1_AW0__FULL 0x1E048168,0xffffffff ++#define IPU_DI1_AW0__DI1_AW_TRIG_SEL 0x1E048168,0xF0000000 ++#define IPU_DI1_AW0__DI1_AW_HEND 0x1E048168,0x0FFF0000 ++#define IPU_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1E048168,0x0000F000 ++#define IPU_DI1_AW0__DI1_AW_HSTART 0x1E048168,0x00000FFF ++ ++#define IPU_DI1_AW1__ADDR 0x1E04816C ++#define IPU_DI1_AW1__EMPTY 0x1E04816C,0x00000000 ++#define IPU_DI1_AW1__FULL 0x1E04816C,0xffffffff ++#define IPU_DI1_AW1__DI1_AW_VEND 0x1E04816C,0x0FFF0000 ++#define IPU_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1E04816C,0x0000F000 ++#define IPU_DI1_AW1__DI1_AW_VSTART 0x1E04816C,0x00000FFF ++ ++#define IPU_DI1_SCR_CONF__ADDR 0x1E048170 ++#define IPU_DI1_SCR_CONF__EMPTY 0x1E048170,0x00000000 ++#define IPU_DI1_SCR_CONF__FULL 0x1E048170,0xffffffff ++#define IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1E048170,0x00000FFF ++ ++#define IPU_DI1_STAT__ADDR 0x1E048174 ++#define IPU_DI1_STAT__EMPTY 0x1E048174,0x00000000 ++#define IPU_DI1_STAT__FULL 0x1E048174,0xffffffff ++#define IPU_DI1_STAT__DI1_CNTR_FIFO_FULL 0x1E048174,0x00000008 ++#define IPU_DI1_STAT__DI1_CNTR_FIFO_EMPTY 0x1E048174,0x00000004 ++#define IPU_DI1_STAT__DI1_READ_FIFO_FULL 0x1E048174,0x00000002 ++#define IPU_DI1_STAT__DI1_READ_FIFO_EMPTY 0x1E048174,0x00000001 ++// ================= End of IPUV3EX DI Registers ===================== ++ ++// ================= Start of IPUV3EX SMFC Registers ===================== ++#define IPU_SMFC_MAP__ADDR 0x1E050000 ++#define IPU_SMFC_MAP__EMPTY 0x1E050000,0x00000000 ++#define IPU_SMFC_MAP__FULL 0x1E050000,0xffffffff ++#define IPU_SMFC_MAP__MAP_CH3 0x1E050000,0x00000E00 ++#define IPU_SMFC_MAP__MAP_CH2 0x1E050000,0x000001C0 ++#define IPU_SMFC_MAP__MAP_CH1 0x1E050000,0x00000038 ++#define IPU_SMFC_MAP__MAP_CH0 0x1E050000,0x00000007 ++ ++#define IPU_SMFC_WMC__ADDR 0x1E050004 ++#define IPU_SMFC_WMC__EMPTY 0x1E050004,0x00000000 ++#define IPU_SMFC_WMC__FULL 0x1E050004,0xffffffff ++#define IPU_SMFC_WMC__WM3_CLR 0x1E050004,0x0E000000 ++#define IPU_SMFC_WMC__WM3_SET 0x1E050004,0x01C00000 ++#define IPU_SMFC_WMC__WM2_CLR 0x1E050004,0x00380000 ++#define IPU_SMFC_WMC__WM2_SET 0x1E050004,0x00070000 ++#define IPU_SMFC_WMC__WM1_CLR 0x1E050004,0x00000E00 ++#define IPU_SMFC_WMC__WM1_SET 0x1E050004,0x000001C0 ++#define IPU_SMFC_WMC__WM0_CLR 0x1E050004,0x00000038 ++#define IPU_SMFC_WMC__WM0_SET 0x1E050004,0x00000007 ++ ++#define IPU_SMFC_BS__ADDR 0x1E050008 ++#define IPU_SMFC_BS__EMPTY 0x1E050008,0x00000000 ++#define IPU_SMFC_BS__FULL 0x1E050008,0xffffffff ++#define IPU_SMFC_BS__BURST3_SIZE 0x1E050008,0x0000F000 ++#define IPU_SMFC_BS__BURST2_SIZE 0x1E050008,0x00000F00 ++#define IPU_SMFC_BS__BURST1_SIZE 0x1E050008,0x000000F0 ++#define IPU_SMFC_BS__BURST0_SIZE 0x1E050008,0x0000000F ++// ================= End of IPUV3EX SMFC Registers ===================== ++ ++// ================= Start of IPUV3EX DC Registers ===================== ++#define IPU_DC_READ_CH_CONF__ADDR 0x1E058000 ++#define IPU_DC_READ_CH_CONF__EMPTY 0x1E058000,0x00000000 ++#define IPU_DC_READ_CH_CONF__FULL 0x1E058000,0xffffffff ++#define IPU_DC_READ_CH_CONF__TIME_OUT_VALUE 0x1E058000,0xFFFF0000 ++#define IPU_DC_READ_CH_CONF__CS_ID_3 0x1E058000,0x00000800 ++#define IPU_DC_READ_CH_CONF__CS_ID_2 0x1E058000,0x00000400 ++#define IPU_DC_READ_CH_CONF__CS_ID_1 0x1E058000,0x00000200 ++#define IPU_DC_READ_CH_CONF__CS_ID_0 0x1E058000,0x00000100 ++#define IPU_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1E058000,0x00000040 ++#define IPU_DC_READ_CH_CONF__W_SIZE_0 0x1E058000,0x00000030 ++#define IPU_DC_READ_CH_CONF__PROG_DISP_ID_0 0x1E058000,0x0000000C ++#define IPU_DC_READ_CH_CONF__PROG_DI_ID_0 0x1E058000,0x00000002 ++#define IPU_DC_READ_CH_CONF__RD_CHANNEL_EN 0x1E058000,0x00000001 ++ ++#define IPU_DC_READ_CH_ADDR__ADDR 0x1E058004 ++#define IPU_DC_READ_CH_ADDR__EMPTY 0x1E058004,0x00000000 ++#define IPU_DC_READ_CH_ADDR__FULL 0x1E058004,0xffffffff ++#define IPU_DC_READ_CH_ADDR__ST_ADDR_0 0x1E058004,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_0__ADDR 0x1E058008 ++#define IPU_DC_RL0_CH_0__EMPTY 0x1E058008,0x00000000 ++#define IPU_DC_RL0_CH_0__FULL 0x1E058008,0xffffffff ++#define IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0 0x1E058008,0xFF000000 ++#define IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1E058008,0x000F0000 ++#define IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0 0x1E058008,0x0000FF00 ++#define IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1E058008,0x0000000F ++ ++#define IPU_DC_RL1_CH_0__ADDR 0x1E05800C ++#define IPU_DC_RL1_CH_0__EMPTY 0x1E05800C,0x00000000 ++#define IPU_DC_RL1_CH_0__FULL 0x1E05800C,0xffffffff ++#define IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0 0x1E05800C,0xFF000000 ++#define IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1E05800C,0x000F0000 ++#define IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0 0x1E05800C,0x0000FF00 ++#define IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0 0x1E05800C,0x0000000F ++ ++#define IPU_DC_RL2_CH_0__ADDR 0x1E058010 ++#define IPU_DC_RL2_CH_0__EMPTY 0x1E058010,0x00000000 ++#define IPU_DC_RL2_CH_0__FULL 0x1E058010,0xffffffff ++#define IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0 0x1E058010,0xFF000000 ++#define IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1E058010,0x000F0000 ++#define IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0 0x1E058010,0x0000FF00 ++#define IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0 0x1E058010,0x0000000F ++ ++#define IPU_DC_RL3_CH_0__ADDR 0x1E058014 ++#define IPU_DC_RL3_CH_0__EMPTY 0x1E058014,0x00000000 ++#define IPU_DC_RL3_CH_0__FULL 0x1E058014,0xffffffff ++#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0 0x1E058014,0xFF000000 ++#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1E058014,0x000F0000 ++#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0 0x1E058014,0x0000FF00 ++#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1E058014,0x0000000F ++ ++#define IPU_DC_RL4_CH_0__ADDR 0x1E058018 ++#define IPU_DC_RL4_CH_0__EMPTY 0x1E058018,0x00000000 ++#define IPU_DC_RL4_CH_0__FULL 0x1E058018,0xffffffff ++#define IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0 0x1E058018,0x0000FF00 ++#define IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1E058018,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_1__ADDR 0x1E05801C ++#define IPU_DC_WR_CH_CONF_1__EMPTY 0x1E05801C,0x00000000 ++#define IPU_DC_WR_CH_CONF_1__FULL 0x1E05801C,0xffffffff ++#define IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1 0x1E05801C,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_1__FIELD_MODE_1 0x1E05801C,0x00000200 ++#define IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1E05801C,0x00000100 ++#define IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1 0x1E05801C,0x000000E0 ++#define IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1 0x1E05801C,0x00000018 ++#define IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1 0x1E05801C,0x00000004 ++#define IPU_DC_WR_CH_CONF_1__W_SIZE_1 0x1E05801C,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_1__ADDR 0x1E058020 ++#define IPU_DC_WR_CH_ADDR_1__EMPTY 0x1E058020,0x00000000 ++#define IPU_DC_WR_CH_ADDR_1__FULL 0x1E058020,0xffffffff ++#define IPU_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1E058020,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_1__ADDR 0x1E058024 ++#define IPU_DC_RL0_CH_1__EMPTY 0x1E058024,0x00000000 ++#define IPU_DC_RL0_CH_1__FULL 0x1E058024,0xffffffff ++#define IPU_DC_RL0_CH_1__COD_NL_START_CHAN_1 0x1E058024,0xFF000000 ++#define IPU_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1E058024,0x000F0000 ++#define IPU_DC_RL0_CH_1__COD_NF_START_CHAN_1 0x1E058024,0x0000FF00 ++#define IPU_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1E058024,0x0000000F ++ ++#define IPU_DC_RL1_CH_1__ADDR 0x1E058028 ++#define IPU_DC_RL1_CH_1__EMPTY 0x1E058028,0x00000000 ++#define IPU_DC_RL1_CH_1__FULL 0x1E058028,0xffffffff ++#define IPU_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1 0x1E058028,0xFF000000 ++#define IPU_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1E058028,0x000F0000 ++#define IPU_DC_RL1_CH_1__COD_EOF_START_CHAN_1 0x1E058028,0x0000FF00 ++#define IPU_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1 0x1E058028,0x0000000F ++ ++#define IPU_DC_RL2_CH_1__ADDR 0x1E05802C ++#define IPU_DC_RL2_CH_1__EMPTY 0x1E05802C,0x00000000 ++#define IPU_DC_RL2_CH_1__FULL 0x1E05802C,0xffffffff ++#define IPU_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1 0x1E05802C,0xFF000000 ++#define IPU_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1E05802C,0x000F0000 ++#define IPU_DC_RL2_CH_1__COD_EOL_START_CHAN_1 0x1E05802C,0x0000FF00 ++#define IPU_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1 0x1E05802C,0x0000000F ++ ++#define IPU_DC_RL3_CH_1__ADDR 0x1E058030 ++#define IPU_DC_RL3_CH_1__EMPTY 0x1E058030,0x00000000 ++#define IPU_DC_RL3_CH_1__FULL 0x1E058030,0xffffffff ++#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1 0x1E058030,0xFF000000 ++#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1E058030,0x000F0000 ++#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1 0x1E058030,0x0000FF00 ++#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1E058030,0x0000000F ++ ++#define IPU_DC_RL4_CH_1__ADDR 0x1E058034 ++#define IPU_DC_RL4_CH_1__EMPTY 0x1E058034,0x00000000 ++#define IPU_DC_RL4_CH_1__FULL 0x1E058034,0xffffffff ++#define IPU_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1 0x1E058034,0x0000FF00 ++#define IPU_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1E058034,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_2__ADDR 0x1E058038 ++#define IPU_DC_WR_CH_CONF_2__EMPTY 0x1E058038,0x00000000 ++#define IPU_DC_WR_CH_CONF_2__FULL 0x1E058038,0xffffffff ++#define IPU_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1E058038,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1E058038,0x00000100 ++#define IPU_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1E058038,0x000000E0 ++#define IPU_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1E058038,0x00000018 ++#define IPU_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1E058038,0x00000004 ++#define IPU_DC_WR_CH_CONF_2__W_SIZE_2 0x1E058038,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_2__ADDR 0x1E05803C ++#define IPU_DC_WR_CH_ADDR_2__EMPTY 0x1E05803C,0x00000000 ++#define IPU_DC_WR_CH_ADDR_2__FULL 0x1E05803C,0xffffffff ++#define IPU_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1E05803C,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_2__ADDR 0x1E058040 ++#define IPU_DC_RL0_CH_2__EMPTY 0x1E058040,0x00000000 ++#define IPU_DC_RL0_CH_2__FULL 0x1E058040,0xffffffff ++#define IPU_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1E058040,0xFF000000 ++#define IPU_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1E058040,0x000F0000 ++#define IPU_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1E058040,0x0000FF00 ++#define IPU_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1E058040,0x0000000F ++ ++#define IPU_DC_RL1_CH_2__ADDR 0x1E058044 ++#define IPU_DC_RL1_CH_2__EMPTY 0x1E058044,0x00000000 ++#define IPU_DC_RL1_CH_2__FULL 0x1E058044,0xffffffff ++#define IPU_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1E058044,0xFF000000 ++#define IPU_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1E058044,0x000F0000 ++#define IPU_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1E058044,0x0000FF00 ++#define IPU_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1E058044,0x0000000F ++ ++#define IPU_DC_RL2_CH_2__ADDR 0x1E058048 ++#define IPU_DC_RL2_CH_2__EMPTY 0x1E058048,0x00000000 ++#define IPU_DC_RL2_CH_2__FULL 0x1E058048,0xffffffff ++#define IPU_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1E058048,0xFF000000 ++#define IPU_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1E058048,0x000F0000 ++#define IPU_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1E058048,0x0000FF00 ++#define IPU_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1E058048,0x0000000F ++ ++#define IPU_DC_RL3_CH_2__ADDR 0x1E05804C ++#define IPU_DC_RL3_CH_2__EMPTY 0x1E05804C,0x00000000 ++#define IPU_DC_RL3_CH_2__FULL 0x1E05804C,0xffffffff ++#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1E05804C,0xFF000000 ++#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1E05804C,0x000F0000 ++#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1E05804C,0x0000FF00 ++#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1E05804C,0x0000000F ++ ++#define IPU_DC_RL4_CH_2__ADDR 0x1E058050 ++#define IPU_DC_RL4_CH_2__EMPTY 0x1E058050,0x00000000 ++#define IPU_DC_RL4_CH_2__FULL 0x1E058050,0xffffffff ++#define IPU_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1E058050,0x0000FF00 ++#define IPU_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1E058050,0x0000000F ++ ++#define IPU_DC_CMD_CH_CONF_3__ADDR 0x1E058054 ++#define IPU_DC_CMD_CH_CONF_3__EMPTY 0x1E058054,0x00000000 ++#define IPU_DC_CMD_CH_CONF_3__FULL 0x1E058054,0xffffffff ++#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1E058054,0xFF000000 ++#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1E058054,0x0000FF00 ++#define IPU_DC_CMD_CH_CONF_3__W_SIZE_3 0x1E058054,0x00000003 ++ ++#define IPU_DC_CMD_CH_CONF_4__ADDR 0x1E058058 ++#define IPU_DC_CMD_CH_CONF_4__EMPTY 0x1E058058,0x00000000 ++#define IPU_DC_CMD_CH_CONF_4__FULL 0x1E058058,0xffffffff ++#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1E058058,0xFF000000 ++#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1E058058,0x0000FF00 ++#define IPU_DC_CMD_CH_CONF_4__W_SIZE_4 0x1E058058,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF_5__ADDR 0x1E05805C ++#define IPU_DC_WR_CH_CONF_5__EMPTY 0x1E05805C,0x00000000 ++#define IPU_DC_WR_CH_CONF_5__FULL 0x1E05805C,0xffffffff ++#define IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5 0x1E05805C,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_5__FIELD_MODE_5 0x1E05805C,0x00000200 ++#define IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1E05805C,0x00000100 ++#define IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5 0x1E05805C,0x000000E0 ++#define IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5 0x1E05805C,0x00000018 ++#define IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5 0x1E05805C,0x00000004 ++#define IPU_DC_WR_CH_CONF_5__W_SIZE_5 0x1E05805C,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_5__ADDR 0x1E058060 ++#define IPU_DC_WR_CH_ADDR_5__EMPTY 0x1E058060,0x00000000 ++#define IPU_DC_WR_CH_ADDR_5__FULL 0x1E058060,0xffffffff ++#define IPU_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1E058060,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_5__ADDR 0x1E058064 ++#define IPU_DC_RL0_CH_5__EMPTY 0x1E058064,0x00000000 ++#define IPU_DC_RL0_CH_5__FULL 0x1E058064,0xffffffff ++#define IPU_DC_RL0_CH_5__COD_NL_START_CHAN_5 0x1E058064,0xFF000000 ++#define IPU_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1E058064,0x000F0000 ++#define IPU_DC_RL0_CH_5__COD_NF_START_CHAN_5 0x1E058064,0x0000FF00 ++#define IPU_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1E058064,0x0000000F ++ ++#define IPU_DC_RL1_CH_5__ADDR 0x1E058068 ++#define IPU_DC_RL1_CH_5__EMPTY 0x1E058068,0x00000000 ++#define IPU_DC_RL1_CH_5__FULL 0x1E058068,0xffffffff ++#define IPU_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5 0x1E058068,0xFF000000 ++#define IPU_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1E058068,0x000F0000 ++#define IPU_DC_RL1_CH_5__COD_EOF_START_CHAN_5 0x1E058068,0x0000FF00 ++#define IPU_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5 0x1E058068,0x0000000F ++ ++#define IPU_DC_RL2_CH_5__ADDR 0x1E05806C ++#define IPU_DC_RL2_CH_5__EMPTY 0x1E05806C,0x00000000 ++#define IPU_DC_RL2_CH_5__FULL 0x1E05806C,0xffffffff ++#define IPU_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5 0x1E05806C,0xFF000000 ++#define IPU_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1E05806C,0x000F0000 ++#define IPU_DC_RL2_CH_5__COD_EOL_START_CHAN_5 0x1E05806C,0x0000FF00 ++#define IPU_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5 0x1E05806C,0x0000000F ++ ++#define IPU_DC_RL3_CH_5__ADDR 0x1E058070 ++#define IPU_DC_RL3_CH_5__EMPTY 0x1E058070,0x00000000 ++#define IPU_DC_RL3_CH_5__FULL 0x1E058070,0xffffffff ++#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5 0x1E058070,0xFF000000 ++#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1E058070,0x000F0000 ++#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5 0x1E058070,0x0000FF00 ++#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1E058070,0x0000000F ++ ++#define IPU_DC_RL4_CH_5__ADDR 0x1E058074 ++#define IPU_DC_RL4_CH_5__EMPTY 0x1E058074,0x00000000 ++#define IPU_DC_RL4_CH_5__FULL 0x1E058074,0xffffffff ++#define IPU_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5 0x1E058074,0x0000FF00 ++#define IPU_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1E058074,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF_6__ADDR 0x1E058078 ++#define IPU_DC_WR_CH_CONF_6__EMPTY 0x1E058078,0x00000000 ++#define IPU_DC_WR_CH_CONF_6__FULL 0x1E058078,0xffffffff ++#define IPU_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1E058078,0x07FF0000 ++#define IPU_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1E058078,0x00000100 ++#define IPU_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1E058078,0x000000E0 ++#define IPU_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1E058078,0x00000018 ++#define IPU_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1E058078,0x00000004 ++#define IPU_DC_WR_CH_CONF_6__W_SIZE_6 0x1E058078,0x00000003 ++ ++#define IPU_DC_WR_CH_ADDR_6__ADDR 0x1E05807C ++#define IPU_DC_WR_CH_ADDR_6__EMPTY 0x1E05807C,0x00000000 ++#define IPU_DC_WR_CH_ADDR_6__FULL 0x1E05807C,0xffffffff ++#define IPU_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1E05807C,0x1FFFFFFF ++ ++#define IPU_DC_RL0_CH_6__ADDR 0x1E058080 ++#define IPU_DC_RL0_CH_6__EMPTY 0x1E058080,0x00000000 ++#define IPU_DC_RL0_CH_6__FULL 0x1E058080,0xffffffff ++#define IPU_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1E058080,0xFF000000 ++#define IPU_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1E058080,0x000F0000 ++#define IPU_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1E058080,0x0000FF00 ++#define IPU_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1E058080,0x0000000F ++ ++#define IPU_DC_RL1_CH_6__ADDR 0x1E058084 ++#define IPU_DC_RL1_CH_6__EMPTY 0x1E058084,0x00000000 ++#define IPU_DC_RL1_CH_6__FULL 0x1E058084,0xffffffff ++#define IPU_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1E058084,0xFF000000 ++#define IPU_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1E058084,0x000F0000 ++#define IPU_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1E058084,0x0000FF00 ++#define IPU_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1E058084,0x0000000F ++ ++#define IPU_DC_RL2_CH_6__ADDR 0x1E058088 ++#define IPU_DC_RL2_CH_6__EMPTY 0x1E058088,0x00000000 ++#define IPU_DC_RL2_CH_6__FULL 0x1E058088,0xffffffff ++#define IPU_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1E058088,0xFF000000 ++#define IPU_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1E058088,0x000F0000 ++#define IPU_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1E058088,0x0000FF00 ++#define IPU_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1E058088,0x0000000F ++ ++#define IPU_DC_RL3_CH_6__ADDR 0x1E05808C ++#define IPU_DC_RL3_CH_6__EMPTY 0x1E05808C,0x00000000 ++#define IPU_DC_RL3_CH_6__FULL 0x1E05808C,0xffffffff ++#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1E05808C,0xFF000000 ++#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1E05808C,0x000F0000 ++#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1E05808C,0x0000FF00 ++#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1E05808C,0x0000000F ++ ++#define IPU_DC_RL4_CH_6__ADDR 0x1E058090 ++#define IPU_DC_RL4_CH_6__EMPTY 0x1E058090,0x00000000 ++#define IPU_DC_RL4_CH_6__FULL 0x1E058090,0xffffffff ++#define IPU_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1E058090,0x0000FF00 ++#define IPU_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1E058090,0x0000000F ++ ++#define IPU_DC_WR_CH_CONF1_8__ADDR 0x1E058094 ++#define IPU_DC_WR_CH_CONF1_8__EMPTY 0x1E058094,0x00000000 ++#define IPU_DC_WR_CH_CONF1_8__FULL 0x1E058094,0xffffffff ++#define IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8 0x1E058094,0x00000018 ++#define IPU_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1E058094,0x00000004 ++#define IPU_DC_WR_CH_CONF1_8__W_SIZE_8 0x1E058094,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF2_8__ADDR 0x1E058098 ++#define IPU_DC_WR_CH_CONF2_8__EMPTY 0x1E058098,0x00000000 ++#define IPU_DC_WR_CH_CONF2_8__FULL 0x1E058098,0xffffffff ++#define IPU_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1E058098,0x1FFFFFFF ++ ++#define IPU_DC_RL1_CH_8__ADDR 0x1E05809C ++#define IPU_DC_RL1_CH_8__EMPTY 0x1E05809C,0x00000000 ++#define IPU_DC_RL1_CH_8__FULL 0x1E05809C,0xffffffff ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1E05809C,0xFF000000 ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1E05809C,0x0000FF00 ++#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8 0x1E05809C,0x0000000F ++ ++#define IPU_DC_RL2_CH_8__ADDR 0x1E0580A0 ++#define IPU_DC_RL2_CH_8__EMPTY 0x1E0580A0,0x00000000 ++#define IPU_DC_RL2_CH_8__FULL 0x1E0580A0,0xffffffff ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1E0580A0,0xFF000000 ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1E0580A0,0x0000FF00 ++#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8 0x1E0580A0,0x0000000F ++ ++#define IPU_DC_RL3_CH_8__ADDR 0x1E0580A4 ++#define IPU_DC_RL3_CH_8__EMPTY 0x1E0580A4,0x00000000 ++#define IPU_DC_RL3_CH_8__FULL 0x1E0580A4,0xffffffff ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1E0580A4,0xFF000000 ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1E0580A4,0x0000FF00 ++#define IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8 0x1E0580A4,0x0000000F ++ ++#define IPU_DC_RL4_CH_8__ADDR 0x1E0580A8 ++#define IPU_DC_RL4_CH_8__EMPTY 0x1E0580A8,0x00000000 ++#define IPU_DC_RL4_CH_8__FULL 0x1E0580A8,0xffffffff ++#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1E0580A8,0xFF000000 ++#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1E0580A8,0x0000FF00 ++ ++#define IPU_DC_RL5_CH_8__ADDR 0x1E0580AC ++#define IPU_DC_RL5_CH_8__EMPTY 0x1E0580AC,0x00000000 ++#define IPU_DC_RL5_CH_8__FULL 0x1E0580AC,0xffffffff ++#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1E0580AC,0xFF000000 ++#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1E0580AC,0x0000FF00 ++ ++#define IPU_DC_RL6_CH_8__ADDR 0x1E0580B0 ++#define IPU_DC_RL6_CH_8__EMPTY 0x1E0580B0,0x00000000 ++#define IPU_DC_RL6_CH_8__FULL 0x1E0580B0,0xffffffff ++#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1E0580B0,0xFF000000 ++#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1E0580B0,0x0000FF00 ++ ++#define IPU_DC_WR_CH_CONF1_9__ADDR 0x1E0580B4 ++#define IPU_DC_WR_CH_CONF1_9__EMPTY 0x1E0580B4,0x00000000 ++#define IPU_DC_WR_CH_CONF1_9__FULL 0x1E0580B4,0xffffffff ++#define IPU_DC_WR_CH_CONF1_9__MCU_DISP_ID_9 0x1E0580B4,0x00000018 ++#define IPU_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1E0580B4,0x00000004 ++#define IPU_DC_WR_CH_CONF1_9__W_SIZE_9 0x1E0580B4,0x00000003 ++ ++#define IPU_DC_WR_CH_CONF2_9__ADDR 0x1E0580B8 ++#define IPU_DC_WR_CH_CONF2_9__EMPTY 0x1E0580B8,0x00000000 ++#define IPU_DC_WR_CH_CONF2_9__FULL 0x1E0580B8,0xffffffff ++#define IPU_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1E0580B8,0x1FFFFFFF ++ ++#define IPU_DC_RL1_CH_9__ADDR 0x1E0580BC ++#define IPU_DC_RL1_CH_9__EMPTY 0x1E0580BC,0x00000000 ++#define IPU_DC_RL1_CH_9__FULL 0x1E0580BC,0xffffffff ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1E0580BC,0xFF000000 ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1E0580BC,0x0000FF00 ++#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9 0x1E0580BC,0x0000000F ++ ++#define IPU_DC_RL2_CH_9__ADDR 0x1E0580C0 ++#define IPU_DC_RL2_CH_9__EMPTY 0x1E0580C0,0x00000000 ++#define IPU_DC_RL2_CH_9__FULL 0x1E0580C0,0xffffffff ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1E0580C0,0xFF000000 ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1E0580C0,0x0000FF00 ++#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9 0x1E0580C0,0x0000000F ++ ++#define IPU_DC_RL3_CH_9__ADDR 0x1E0580C4 ++#define IPU_DC_RL3_CH_9__EMPTY 0x1E0580C4,0x00000000 ++#define IPU_DC_RL3_CH_9__FULL 0x1E0580C4,0xffffffff ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1E0580C4,0xFF000000 ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1E0580C4,0x0000FF00 ++#define IPU_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9 0x1E0580C4,0x0000000F ++ ++#define IPU_DC_RL4_CH_9__ADDR 0x1E0580C8 ++#define IPU_DC_RL4_CH_9__EMPTY 0x1E0580C8,0x00000000 ++#define IPU_DC_RL4_CH_9__FULL 0x1E0580C8,0xffffffff ++#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1E0580C8,0xFF000000 ++#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1E0580C8,0x0000FF00 ++ ++#define IPU_DC_RL5_CH_9__ADDR 0x1E0580CC ++#define IPU_DC_RL5_CH_9__EMPTY 0x1E0580CC,0x00000000 ++#define IPU_DC_RL5_CH_9__FULL 0x1E0580CC,0xffffffff ++#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1E0580CC,0xFF000000 ++#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1E0580CC,0x0000FF00 ++ ++#define IPU_DC_RL6_CH_9__ADDR 0x1E0580D0 ++#define IPU_DC_RL6_CH_9__EMPTY 0x1E0580D0,0x00000000 ++#define IPU_DC_RL6_CH_9__FULL 0x1E0580D0,0xffffffff ++#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1E0580D0,0xFF000000 ++#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1E0580D0,0x0000FF00 ++ ++#define IPU_DC_GEN__ADDR 0x1E0580D4 ++#define IPU_DC_GEN__EMPTY 0x1E0580D4,0x00000000 ++#define IPU_DC_GEN__FULL 0x1E0580D4,0xffffffff ++#define IPU_DC_GEN__DC_BK_EN 0x1E0580D4,0x01000000 ++#define IPU_DC_GEN__DC_BKDIV 0x1E0580D4,0x00FF0000 ++#define IPU_DC_GEN__DC_CH5_TYPE 0x1E0580D4,0x00000100 ++#define IPU_DC_GEN__SYNC_PRIORITY_1 0x1E0580D4,0x00000080 ++#define IPU_DC_GEN__SYNC_PRIORITY_5 0x1E0580D4,0x00000040 ++#define IPU_DC_GEN__MASK4CHAN_5 0x1E0580D4,0x00000020 ++#define IPU_DC_GEN__MASK_EN 0x1E0580D4,0x00000010 ++#define IPU_DC_GEN__SYNC_1_6 0x1E0580D4,0x00000006 ++ ++#define IPU_DC_DISP_CONF1_0__ADDR 0x1E0580D8 ++#define IPU_DC_DISP_CONF1_0__EMPTY 0x1E0580D8,0x00000000 ++#define IPU_DC_DISP_CONF1_0__FULL 0x1E0580D8,0xffffffff ++#define IPU_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1E0580D8,0x00000080 ++#define IPU_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0 0x1E0580D8,0x00000040 ++#define IPU_DC_DISP_CONF1_0__ADDR_BE_L_INC_0 0x1E0580D8,0x00000030 ++#define IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0 0x1E0580D8,0x0000000C ++#define IPU_DC_DISP_CONF1_0__DISP_TYP_0 0x1E0580D8,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_1__ADDR 0x1E0580DC ++#define IPU_DC_DISP_CONF1_1__EMPTY 0x1E0580DC,0x00000000 ++#define IPU_DC_DISP_CONF1_1__FULL 0x1E0580DC,0xffffffff ++#define IPU_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1E0580DC,0x00000080 ++#define IPU_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1 0x1E0580DC,0x00000040 ++#define IPU_DC_DISP_CONF1_1__ADDR_BE_L_INC_1 0x1E0580DC,0x00000030 ++#define IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1 0x1E0580DC,0x0000000C ++#define IPU_DC_DISP_CONF1_1__DISP_TYP_1 0x1E0580DC,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_2__ADDR 0x1E0580E0 ++#define IPU_DC_DISP_CONF1_2__EMPTY 0x1E0580E0,0x00000000 ++#define IPU_DC_DISP_CONF1_2__FULL 0x1E0580E0,0xffffffff ++#define IPU_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1E0580E0,0x00000080 ++#define IPU_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2 0x1E0580E0,0x00000040 ++#define IPU_DC_DISP_CONF1_2__ADDR_BE_L_INC_2 0x1E0580E0,0x00000030 ++#define IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2 0x1E0580E0,0x0000000C ++#define IPU_DC_DISP_CONF1_2__DISP_TYP_2 0x1E0580E0,0x00000003 ++ ++#define IPU_DC_DISP_CONF1_3__ADDR 0x1E0580E4 ++#define IPU_DC_DISP_CONF1_3__EMPTY 0x1E0580E4,0x00000000 ++#define IPU_DC_DISP_CONF1_3__FULL 0x1E0580E4,0xffffffff ++#define IPU_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1E0580E4,0x00000080 ++#define IPU_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3 0x1E0580E4,0x00000040 ++#define IPU_DC_DISP_CONF1_3__ADDR_BE_L_INC_3 0x1E0580E4,0x00000030 ++#define IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3 0x1E0580E4,0x0000000C ++#define IPU_DC_DISP_CONF1_3__DISP_TYP_3 0x1E0580E4,0x00000003 ++ ++#define IPU_DC_DISP_CONF2_0__ADDR 0x1E0580E8 ++#define IPU_DC_DISP_CONF2_0__EMPTY 0x1E0580E8,0x00000000 ++#define IPU_DC_DISP_CONF2_0__FULL 0x1E0580E8,0xffffffff ++#define IPU_DC_DISP_CONF2_0__SL_0 0x1E0580E8,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_1__ADDR 0x1E0580EC ++#define IPU_DC_DISP_CONF2_1__EMPTY 0x1E0580EC,0x00000000 ++#define IPU_DC_DISP_CONF2_1__FULL 0x1E0580EC,0xffffffff ++#define IPU_DC_DISP_CONF2_1__SL_1 0x1E0580EC,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_2__ADDR 0x1E0580F0 ++#define IPU_DC_DISP_CONF2_2__EMPTY 0x1E0580F0,0x00000000 ++#define IPU_DC_DISP_CONF2_2__FULL 0x1E0580F0,0xffffffff ++#define IPU_DC_DISP_CONF2_2__SL_2 0x1E0580F0,0x1FFFFFFF ++ ++#define IPU_DC_DISP_CONF2_3__ADDR 0x1E0580F4 ++#define IPU_DC_DISP_CONF2_3__EMPTY 0x1E0580F4,0x00000000 ++#define IPU_DC_DISP_CONF2_3__FULL 0x1E0580F4,0xffffffff ++#define IPU_DC_DISP_CONF2_3__SL_3 0x1E0580F4,0x1FFFFFFF ++ ++#define IPU_DC_DI0_CONF_1__ADDR 0x1E0580F8 ++#define IPU_DC_DI0_CONF_1__EMPTY 0x1E0580F8,0x00000000 ++#define IPU_DC_DI0_CONF_1__FULL 0x1E0580F8,0xffffffff ++#define IPU_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1E0580F8,0xFFFFFFFF ++ ++#define IPU_DC_DI0_CONF_2__ADDR 0x1E0580FC ++#define IPU_DC_DI0_CONF_2__EMPTY 0x1E0580FC,0x00000000 ++#define IPU_DC_DI0_CONF_2__FULL 0x1E0580FC,0xffffffff ++#define IPU_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1E0580FC,0xFFFFFFFF ++ ++#define IPU_DC_DI1_CONF_1__ADDR 0x1E058100 ++#define IPU_DC_DI1_CONF_1__EMPTY 0x1E058100,0x00000000 ++#define IPU_DC_DI1_CONF_1__FULL 0x1E058100,0xffffffff ++#define IPU_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1E058100,0xFFFFFFFF ++ ++#define IPU_DC_DI1_CONF_2__ADDR 0x1E058104 ++#define IPU_DC_DI1_CONF_2__EMPTY 0x1E058104,0x00000000 ++#define IPU_DC_DI1_CONF_2__FULL 0x1E058104,0xffffffff ++#define IPU_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1E058104,0xFFFFFFFF ++ ++#define IPU_DC_MAP_CONF_0__ADDR 0x1E058108 ++#define IPU_DC_MAP_CONF_0__EMPTY 0x1E058108,0x00000000 ++#define IPU_DC_MAP_CONF_0__FULL 0x1E058108,0xffffffff ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1E058108,0x7C000000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1E058108,0x03E00000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1E058108,0x001F0000 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1E058108,0x00007C00 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1E058108,0x000003E0 ++#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1E058108,0x0000001F ++ ++#define IPU_DC_MAP_CONF_1__ADDR 0x1E05810C ++#define IPU_DC_MAP_CONF_1__EMPTY 0x1E05810C,0x00000000 ++#define IPU_DC_MAP_CONF_1__FULL 0x1E05810C,0xffffffff ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1E05810C,0x7C000000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1E05810C,0x03E00000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1E05810C,0x001F0000 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1E05810C,0x00007C00 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1E05810C,0x000003E0 ++#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1E05810C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_2__ADDR 0x1E058110 ++#define IPU_DC_MAP_CONF_2__EMPTY 0x1E058110,0x00000000 ++#define IPU_DC_MAP_CONF_2__FULL 0x1E058110,0xffffffff ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1E058110,0x7C000000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1E058110,0x03E00000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1E058110,0x001F0000 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1E058110,0x00007C00 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1E058110,0x000003E0 ++#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1E058110,0x0000001F ++ ++#define IPU_DC_MAP_CONF_3__ADDR 0x1E058114 ++#define IPU_DC_MAP_CONF_3__EMPTY 0x1E058114,0x00000000 ++#define IPU_DC_MAP_CONF_3__FULL 0x1E058114,0xffffffff ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1E058114,0x7C000000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1E058114,0x03E00000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1E058114,0x001F0000 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1E058114,0x00007C00 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1E058114,0x000003E0 ++#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1E058114,0x0000001F ++ ++#define IPU_DC_MAP_CONF_4__ADDR 0x1E058118 ++#define IPU_DC_MAP_CONF_4__EMPTY 0x1E058118,0x00000000 ++#define IPU_DC_MAP_CONF_4__FULL 0x1E058118,0xffffffff ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1E058118,0x7C000000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1E058118,0x03E00000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1E058118,0x001F0000 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1E058118,0x00007C00 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1E058118,0x000003E0 ++#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1E058118,0x0000001F ++ ++#define IPU_DC_MAP_CONF_5__ADDR 0x1E05811C ++#define IPU_DC_MAP_CONF_5__EMPTY 0x1E05811C,0x00000000 ++#define IPU_DC_MAP_CONF_5__FULL 0x1E05811C,0xffffffff ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1E05811C,0x7C000000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1E05811C,0x03E00000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1E05811C,0x001F0000 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1E05811C,0x00007C00 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1E05811C,0x000003E0 ++#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1E05811C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_6__ADDR 0x1E058120 ++#define IPU_DC_MAP_CONF_6__EMPTY 0x1E058120,0x00000000 ++#define IPU_DC_MAP_CONF_6__FULL 0x1E058120,0xffffffff ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1E058120,0x7C000000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1E058120,0x03E00000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1E058120,0x001F0000 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1E058120,0x00007C00 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1E058120,0x000003E0 ++#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1E058120,0x0000001F ++ ++#define IPU_DC_MAP_CONF_7__ADDR 0x1E058124 ++#define IPU_DC_MAP_CONF_7__EMPTY 0x1E058124,0x00000000 ++#define IPU_DC_MAP_CONF_7__FULL 0x1E058124,0xffffffff ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1E058124,0x7C000000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1E058124,0x03E00000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1E058124,0x001F0000 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1E058124,0x00007C00 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1E058124,0x000003E0 ++#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1E058124,0x0000001F ++ ++#define IPU_DC_MAP_CONF_8__ADDR 0x1E058128 ++#define IPU_DC_MAP_CONF_8__EMPTY 0x1E058128,0x00000000 ++#define IPU_DC_MAP_CONF_8__FULL 0x1E058128,0xffffffff ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1E058128,0x7C000000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1E058128,0x03E00000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1E058128,0x001F0000 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1E058128,0x00007C00 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1E058128,0x000003E0 ++#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1E058128,0x0000001F ++ ++#define IPU_DC_MAP_CONF_9__ADDR 0x1E05812C ++#define IPU_DC_MAP_CONF_9__EMPTY 0x1E05812C,0x00000000 ++#define IPU_DC_MAP_CONF_9__FULL 0x1E05812C,0xffffffff ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1E05812C,0x7C000000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1E05812C,0x03E00000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1E05812C,0x001F0000 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1E05812C,0x00007C00 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1E05812C,0x000003E0 ++#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1E05812C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_10__ADDR 0x1E058130 ++#define IPU_DC_MAP_CONF_10__EMPTY 0x1E058130,0x00000000 ++#define IPU_DC_MAP_CONF_10__FULL 0x1E058130,0xffffffff ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1E058130,0x7C000000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1E058130,0x03E00000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1E058130,0x001F0000 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1E058130,0x00007C00 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1E058130,0x000003E0 ++#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1E058130,0x0000001F ++ ++#define IPU_DC_MAP_CONF_11__ADDR 0x1E058134 ++#define IPU_DC_MAP_CONF_11__EMPTY 0x1E058134,0x00000000 ++#define IPU_DC_MAP_CONF_11__FULL 0x1E058134,0xffffffff ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1E058134,0x7C000000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1E058134,0x03E00000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1E058134,0x001F0000 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1E058134,0x00007C00 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1E058134,0x000003E0 ++#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1E058134,0x0000001F ++ ++#define IPU_DC_MAP_CONF_12__ADDR 0x1E058138 ++#define IPU_DC_MAP_CONF_12__EMPTY 0x1E058138,0x00000000 ++#define IPU_DC_MAP_CONF_12__FULL 0x1E058138,0xffffffff ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1E058138,0x7C000000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1E058138,0x03E00000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1E058138,0x001F0000 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1E058138,0x00007C00 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1E058138,0x000003E0 ++#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1E058138,0x0000001F ++ ++#define IPU_DC_MAP_CONF_13__ADDR 0x1E05813C ++#define IPU_DC_MAP_CONF_13__EMPTY 0x1E05813C,0x00000000 ++#define IPU_DC_MAP_CONF_13__FULL 0x1E05813C,0xffffffff ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1E05813C,0x7C000000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1E05813C,0x03E00000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1E05813C,0x001F0000 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1E05813C,0x00007C00 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1E05813C,0x000003E0 ++#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1E05813C,0x0000001F ++ ++#define IPU_DC_MAP_CONF_14__ADDR 0x1E058140 ++#define IPU_DC_MAP_CONF_14__EMPTY 0x1E058140,0x00000000 ++#define IPU_DC_MAP_CONF_14__FULL 0x1E058140,0xffffffff ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1E058140,0x7C000000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1E058140,0x03E00000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1E058140,0x001F0000 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1E058140,0x00007C00 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1E058140,0x000003E0 ++#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1E058140,0x0000001F ++ ++#define IPU_DC_MAP_CONF_15__ADDR 0x1E058144 ++#define IPU_DC_MAP_CONF_15__EMPTY 0x1E058144,0x00000000 ++#define IPU_DC_MAP_CONF_15__FULL 0x1E058144,0xffffffff ++#define IPU_DC_MAP_CONF_15__MD_OFFSET_1 0x1E058144,0x1F000000 ++#define IPU_DC_MAP_CONF_15__MD_MASK_1 0x1E058144,0x00FF0000 ++#define IPU_DC_MAP_CONF_15__MD_OFFSET_0 0x1E058144,0x00001F00 ++#define IPU_DC_MAP_CONF_15__MD_MASK_0 0x1E058144,0x000000FF ++ ++#define IPU_DC_MAP_CONF_16__ADDR 0x1E058148 ++#define IPU_DC_MAP_CONF_16__EMPTY 0x1E058148,0x00000000 ++#define IPU_DC_MAP_CONF_16__FULL 0x1E058148,0xffffffff ++#define IPU_DC_MAP_CONF_16__MD_OFFSET_3 0x1E058148,0x1F000000 ++#define IPU_DC_MAP_CONF_16__MD_MASK_3 0x1E058148,0x00FF0000 ++#define IPU_DC_MAP_CONF_16__MD_OFFSET_2 0x1E058148,0x00001F00 ++#define IPU_DC_MAP_CONF_16__MD_MASK_2 0x1E058148,0x000000FF ++ ++#define IPU_DC_MAP_CONF_17__ADDR 0x1E05814C ++#define IPU_DC_MAP_CONF_17__EMPTY 0x1E05814C,0x00000000 ++#define IPU_DC_MAP_CONF_17__FULL 0x1E05814C,0xffffffff ++#define IPU_DC_MAP_CONF_17__MD_OFFSET_5 0x1E05814C,0x1F000000 ++#define IPU_DC_MAP_CONF_17__MD_MASK_5 0x1E05814C,0x00FF0000 ++#define IPU_DC_MAP_CONF_17__MD_OFFSET_4 0x1E05814C,0x00001F00 ++#define IPU_DC_MAP_CONF_17__MD_MASK_4 0x1E05814C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_18__ADDR 0x1E058150 ++#define IPU_DC_MAP_CONF_18__EMPTY 0x1E058150,0x00000000 ++#define IPU_DC_MAP_CONF_18__FULL 0x1E058150,0xffffffff ++#define IPU_DC_MAP_CONF_18__MD_OFFSET_7 0x1E058150,0x1F000000 ++#define IPU_DC_MAP_CONF_18__MD_MASK_7 0x1E058150,0x00FF0000 ++#define IPU_DC_MAP_CONF_18__MD_OFFSET_6 0x1E058150,0x00001F00 ++#define IPU_DC_MAP_CONF_18__MD_MASK_6 0x1E058150,0x000000FF ++ ++#define IPU_DC_MAP_CONF_19__ADDR 0x1E058154 ++#define IPU_DC_MAP_CONF_19__EMPTY 0x1E058154,0x00000000 ++#define IPU_DC_MAP_CONF_19__FULL 0x1E058154,0xffffffff ++#define IPU_DC_MAP_CONF_19__MD_OFFSET_9 0x1E058154,0x1F000000 ++#define IPU_DC_MAP_CONF_19__MD_MASK_9 0x1E058154,0x00FF0000 ++#define IPU_DC_MAP_CONF_19__MD_OFFSET_8 0x1E058154,0x00001F00 ++#define IPU_DC_MAP_CONF_19__MD_MASK_8 0x1E058154,0x000000FF ++ ++#define IPU_DC_MAP_CONF_20__ADDR 0x1E058158 ++#define IPU_DC_MAP_CONF_20__EMPTY 0x1E058158,0x00000000 ++#define IPU_DC_MAP_CONF_20__FULL 0x1E058158,0xffffffff ++#define IPU_DC_MAP_CONF_20__MD_OFFSET_11 0x1E058158,0x1F000000 ++#define IPU_DC_MAP_CONF_20__MD_MASK_11 0x1E058158,0x00FF0000 ++#define IPU_DC_MAP_CONF_20__MD_OFFSET_10 0x1E058158,0x00001F00 ++#define IPU_DC_MAP_CONF_20__MD_MASK_10 0x1E058158,0x000000FF ++ ++#define IPU_DC_MAP_CONF_21__ADDR 0x1E05815C ++#define IPU_DC_MAP_CONF_21__EMPTY 0x1E05815C,0x00000000 ++#define IPU_DC_MAP_CONF_21__FULL 0x1E05815C,0xffffffff ++#define IPU_DC_MAP_CONF_21__MD_OFFSET_13 0x1E05815C,0x1F000000 ++#define IPU_DC_MAP_CONF_21__MD_MASK_13 0x1E05815C,0x00FF0000 ++#define IPU_DC_MAP_CONF_21__MD_OFFSET_12 0x1E05815C,0x00001F00 ++#define IPU_DC_MAP_CONF_21__MD_MASK_12 0x1E05815C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_22__ADDR 0x1E058160 ++#define IPU_DC_MAP_CONF_22__EMPTY 0x1E058160,0x00000000 ++#define IPU_DC_MAP_CONF_22__FULL 0x1E058160,0xffffffff ++#define IPU_DC_MAP_CONF_22__MD_OFFSET_15 0x1E058160,0x1F000000 ++#define IPU_DC_MAP_CONF_22__MD_MASK_15 0x1E058160,0x00FF0000 ++#define IPU_DC_MAP_CONF_22__MD_OFFSET_14 0x1E058160,0x00001F00 ++#define IPU_DC_MAP_CONF_22__MD_MASK_14 0x1E058160,0x000000FF ++ ++#define IPU_DC_MAP_CONF_23__ADDR 0x1E058164 ++#define IPU_DC_MAP_CONF_23__EMPTY 0x1E058164,0x00000000 ++#define IPU_DC_MAP_CONF_23__FULL 0x1E058164,0xffffffff ++#define IPU_DC_MAP_CONF_23__MD_OFFSET_17 0x1E058164,0x1F000000 ++#define IPU_DC_MAP_CONF_23__MD_MASK_17 0x1E058164,0x00FF0000 ++#define IPU_DC_MAP_CONF_23__MD_OFFSET_16 0x1E058164,0x00001F00 ++#define IPU_DC_MAP_CONF_23__MD_MASK_16 0x1E058164,0x000000FF ++ ++#define IPU_DC_MAP_CONF_24__ADDR 0x1E058168 ++#define IPU_DC_MAP_CONF_24__EMPTY 0x1E058168,0x00000000 ++#define IPU_DC_MAP_CONF_24__FULL 0x1E058168,0xffffffff ++#define IPU_DC_MAP_CONF_24__MD_OFFSET_19 0x1E058168,0x1F000000 ++#define IPU_DC_MAP_CONF_24__MD_MASK_19 0x1E058168,0x00FF0000 ++#define IPU_DC_MAP_CONF_24__MD_OFFSET_18 0x1E058168,0x00001F00 ++#define IPU_DC_MAP_CONF_24__MD_MASK_18 0x1E058168,0x000000FF ++ ++#define IPU_DC_MAP_CONF_25__ADDR 0x1E05816C ++#define IPU_DC_MAP_CONF_25__EMPTY 0x1E05816C,0x00000000 ++#define IPU_DC_MAP_CONF_25__FULL 0x1E05816C,0xffffffff ++#define IPU_DC_MAP_CONF_25__MD_OFFSET_21 0x1E05816C,0x1F000000 ++#define IPU_DC_MAP_CONF_25__MD_MASK_21 0x1E05816C,0x00FF0000 ++#define IPU_DC_MAP_CONF_25__MD_OFFSET_20 0x1E05816C,0x00001F00 ++#define IPU_DC_MAP_CONF_25__MD_MASK_20 0x1E05816C,0x000000FF ++ ++#define IPU_DC_MAP_CONF_26__ADDR 0x1E058170 ++#define IPU_DC_MAP_CONF_26__EMPTY 0x1E058170,0x00000000 ++#define IPU_DC_MAP_CONF_26__FULL 0x1E058170,0xffffffff ++#define IPU_DC_MAP_CONF_26__MD_OFFSET_23 0x1E058170,0x1F000000 ++#define IPU_DC_MAP_CONF_26__MD_MASK_23 0x1E058170,0x00FF0000 ++#define IPU_DC_MAP_CONF_26__MD_OFFSET_22 0x1E058170,0x00001F00 ++#define IPU_DC_MAP_CONF_26__MD_MASK_22 0x1E058170,0x000000FF ++ ++#define IPU_DC_UGDE0_0__ADDR 0x1E058174 ++#define IPU_DC_UGDE0_0__EMPTY 0x1E058174,0x00000000 ++#define IPU_DC_UGDE0_0__FULL 0x1E058174,0xffffffff ++#define IPU_DC_UGDE0_0__NF_NL_0 0x1E058174,0x18000000 ++#define IPU_DC_UGDE0_0__AUTORESTART_0 0x1E058174,0x04000000 ++#define IPU_DC_UGDE0_0__ODD_EN_0 0x1E058174,0x02000000 ++#define IPU_DC_UGDE0_0__COD_ODD_START_0 0x1E058174,0x00FF0000 ++#define IPU_DC_UGDE0_0__COD_EV_START_0 0x1E058174,0x0000FF00 ++#define IPU_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1E058174,0x00000078 ++#define IPU_DC_UGDE0_0__ID_CODED_0 0x1E058174,0x00000007 ++ ++#define IPU_DC_UGDE0_1__ADDR 0x1E058178 ++#define IPU_DC_UGDE0_1__EMPTY 0x1E058178,0x00000000 ++#define IPU_DC_UGDE0_1__FULL 0x1E058178,0xffffffff ++#define IPU_DC_UGDE0_1__STEP_0 0x1E058178,0x1FFFFFFF ++ ++#define IPU_DC_UGDE0_2__ADDR 0x1E05817C ++#define IPU_DC_UGDE0_2__EMPTY 0x1E05817C,0x00000000 ++#define IPU_DC_UGDE0_2__FULL 0x1E05817C,0xffffffff ++#define IPU_DC_UGDE0_2__OFFSET_DT_0 0x1E05817C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE0_3__ADDR 0x1E058180 ++#define IPU_DC_UGDE0_3__EMPTY 0x1E058180,0x00000000 ++#define IPU_DC_UGDE0_3__FULL 0x1E058180,0xffffffff ++#define IPU_DC_UGDE0_3__STEP_REPEAT_0 0x1E058180,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_0__ADDR 0x1E058184 ++#define IPU_DC_UGDE1_0__EMPTY 0x1E058184,0x00000000 ++#define IPU_DC_UGDE1_0__FULL 0x1E058184,0xffffffff ++#define IPU_DC_UGDE1_0__NF_NL_1 0x1E058184,0x18000000 ++#define IPU_DC_UGDE1_0__AUTORESTART_1 0x1E058184,0x04000000 ++#define IPU_DC_UGDE1_0__ODD_EN_1 0x1E058184,0x02000000 ++#define IPU_DC_UGDE1_0__COD_ODD_START_1 0x1E058184,0x00FF0000 ++#define IPU_DC_UGDE1_0__COD_EV_START_1 0x1E058184,0x00007F80 ++#define IPU_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1E058184,0x00000078 ++#define IPU_DC_UGDE1_0__ID_CODED_1 0x1E058184,0x00000007 ++ ++#define IPU_DC_UGDE1_1__ADDR 0x1E058188 ++#define IPU_DC_UGDE1_1__EMPTY 0x1E058188,0x00000000 ++#define IPU_DC_UGDE1_1__FULL 0x1E058188,0xffffffff ++#define IPU_DC_UGDE1_1__STEP_1 0x1E058188,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_2__ADDR 0x1E05818C ++#define IPU_DC_UGDE1_2__EMPTY 0x1E05818C,0x00000000 ++#define IPU_DC_UGDE1_2__FULL 0x1E05818C,0xffffffff ++#define IPU_DC_UGDE1_2__OFFSET_DT_1 0x1E05818C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE1_3__ADDR 0x1E058190 ++#define IPU_DC_UGDE1_3__EMPTY 0x1E058190,0x00000000 ++#define IPU_DC_UGDE1_3__FULL 0x1E058190,0xffffffff ++#define IPU_DC_UGDE1_3__STEP_REPEAT_1 0x1E058190,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_0__ADDR 0x1E058194 ++#define IPU_DC_UGDE2_0__EMPTY 0x1E058194,0x00000000 ++#define IPU_DC_UGDE2_0__FULL 0x1E058194,0xffffffff ++#define IPU_DC_UGDE2_0__NF_NL_2 0x1E058194,0x18000000 ++#define IPU_DC_UGDE2_0__AUTORESTART_2 0x1E058194,0x04000000 ++#define IPU_DC_UGDE2_0__ODD_EN_2 0x1E058194,0x02000000 ++#define IPU_DC_UGDE2_0__COD_ODD_START_2 0x1E058194,0x00FF0000 ++#define IPU_DC_UGDE2_0__COD_EV_START_2 0x1E058194,0x00007F80 ++#define IPU_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1E058194,0x00000078 ++#define IPU_DC_UGDE2_0__ID_CODED_2 0x1E058194,0x00000007 ++ ++#define IPU_DC_UGDE2_1__ADDR 0x1E058198 ++#define IPU_DC_UGDE2_1__EMPTY 0x1E058198,0x00000000 ++#define IPU_DC_UGDE2_1__FULL 0x1E058198,0xffffffff ++#define IPU_DC_UGDE2_1__STEP_2 0x1E058198,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_2__ADDR 0x1E05819C ++#define IPU_DC_UGDE2_2__EMPTY 0x1E05819C,0x00000000 ++#define IPU_DC_UGDE2_2__FULL 0x1E05819C,0xffffffff ++#define IPU_DC_UGDE2_2__OFFSET_DT_2 0x1E05819C,0x1FFFFFFF ++ ++#define IPU_DC_UGDE2_3__ADDR 0x1E0581A0 ++#define IPU_DC_UGDE2_3__EMPTY 0x1E0581A0,0x00000000 ++#define IPU_DC_UGDE2_3__FULL 0x1E0581A0,0xffffffff ++#define IPU_DC_UGDE2_3__STEP_REPEAT_2 0x1E0581A0,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_0__ADDR 0x1E0581A4 ++#define IPU_DC_UGDE3_0__EMPTY 0x1E0581A4,0x00000000 ++#define IPU_DC_UGDE3_0__FULL 0x1E0581A4,0xffffffff ++#define IPU_DC_UGDE3_0__NF_NL_3 0x1E0581A4,0x18000000 ++#define IPU_DC_UGDE3_0__AUTORESTART_3 0x1E0581A4,0x04000000 ++#define IPU_DC_UGDE3_0__ODD_EN_3 0x1E0581A4,0x02000000 ++#define IPU_DC_UGDE3_0__COD_ODD_START_3 0x1E0581A4,0x00FF0000 ++#define IPU_DC_UGDE3_0__COD_EV_START_3 0x1E0581A4,0x00007F80 ++#define IPU_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1E0581A4,0x00000078 ++#define IPU_DC_UGDE3_0__ID_CODED_3 0x1E0581A4,0x00000007 ++ ++#define IPU_DC_UGDE3_1__ADDR 0x1E0581A8 ++#define IPU_DC_UGDE3_1__EMPTY 0x1E0581A8,0x00000000 ++#define IPU_DC_UGDE3_1__FULL 0x1E0581A8,0xffffffff ++#define IPU_DC_UGDE3_1__STEP_3 0x1E0581A8,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_2__ADDR 0x1E0581AC ++#define IPU_DC_UGDE3_2__EMPTY 0x1E0581AC,0x00000000 ++#define IPU_DC_UGDE3_2__FULL 0x1E0581AC,0xffffffff ++#define IPU_DC_UGDE3_2__OFFSET_DT_3 0x1E0581AC,0x1FFFFFFF ++ ++#define IPU_DC_UGDE3_3__ADDR 0x1E0581B0 ++#define IPU_DC_UGDE3_3__EMPTY 0x1E0581B0,0x00000000 ++#define IPU_DC_UGDE3_3__FULL 0x1E0581B0,0xffffffff ++#define IPU_DC_UGDE3_3__STEP_REPEAT_3 0x1E0581B0,0x1FFFFFFF ++ ++#define IPU_DC_LLA0__ADDR 0x1E0581B4 ++#define IPU_DC_LLA0__EMPTY 0x1E0581B4,0x00000000 ++#define IPU_DC_LLA0__FULL 0x1E0581B4,0xffffffff ++#define IPU_DC_LLA0__MCU_RS_3_0 0x1E0581B4,0xFF000000 ++#define IPU_DC_LLA0__MCU_RS_2_0 0x1E0581B4,0x00FF0000 ++#define IPU_DC_LLA0__MCU_RS_1_0 0x1E0581B4,0x0000FF00 ++#define IPU_DC_LLA0__MCU_RS_0_0 0x1E0581B4,0x000000FF ++ ++#define IPU_DC_LLA1__ADDR 0x1E0581B8 ++#define IPU_DC_LLA1__EMPTY 0x1E0581B8,0x00000000 ++#define IPU_DC_LLA1__FULL 0x1E0581B8,0xffffffff ++#define IPU_DC_LLA1__MCU_RS_3_1 0x1E0581B8,0xFF000000 ++#define IPU_DC_LLA1__MCU_RS_2_1 0x1E0581B8,0x00FF0000 ++#define IPU_DC_LLA1__MCU_RS_1_1 0x1E0581B8,0x0000FF00 ++#define IPU_DC_LLA1__MCU_RS_0_1 0x1E0581B8,0x000000FF ++ ++#define IPU_DC_R_LLA0__ADDR 0x1E0581BC ++#define IPU_DC_R_LLA0__EMPTY 0x1E0581BC,0x00000000 ++#define IPU_DC_R_LLA0__FULL 0x1E0581BC,0xffffffff ++#define IPU_DC_R_LLA0__MCU_RS_R_3_0 0x1E0581BC,0xFF000000 ++#define IPU_DC_R_LLA0__MCU_RS_R_2_0 0x1E0581BC,0x00FF0000 ++#define IPU_DC_R_LLA0__MCU_RS_R_1_0 0x1E0581BC,0x0000FF00 ++#define IPU_DC_R_LLA0__MCU_RS_R_0_0 0x1E0581BC,0x000000FF ++ ++#define IPU_DC_R_LLA1__ADDR 0x1E0581C0 ++#define IPU_DC_R_LLA1__EMPTY 0x1E0581C0,0x00000000 ++#define IPU_DC_R_LLA1__FULL 0x1E0581C0,0xffffffff ++#define IPU_DC_R_LLA1__MCU_RS_R_3_1 0x1E0581C0,0xFF000000 ++#define IPU_DC_R_LLA1__MCU_RS_R_2_1 0x1E0581C0,0x00FF0000 ++#define IPU_DC_R_LLA1__MCU_RS_R_1_1 0x1E0581C0,0x0000FF00 ++#define IPU_DC_R_LLA1__MCU_RS_R_0_1 0x1E0581C0,0x000000FF ++ ++#define IPU_DC_WR_CH_ADDR_5_ALT__ADDR 0x1E0581C4 ++#define IPU_DC_WR_CH_ADDR_5_ALT__EMPTY 0x1E0581C4,0x00000000 ++#define IPU_DC_WR_CH_ADDR_5_ALT__FULL 0x1E0581C4,0xffffffff ++#define IPU_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1E0581C4,0x1FFFFFFF ++ ++#define IPU_DC_STAT__ADDR 0x1E0581C8 ++#define IPU_DC_STAT__EMPTY 0x1E0581C8,0x00000000 ++#define IPU_DC_STAT__FULL 0x1E0581C8,0xffffffff ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_1 0x1E0581C8,0x00000080 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_1 0x1E0581C8,0x00000040 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_1 0x1E0581C8,0x00000020 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_1 0x1E0581C8,0x00000010 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_0 0x1E0581C8,0x00000008 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_0 0x1E0581C8,0x00000004 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_0 0x1E0581C8,0x00000002 ++#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_0 0x1E0581C8,0x00000001 ++// ================= End of IPUV3EX DC Registers ===================== ++ ++// ================= Start of IPUV3EX DMFC Registers ===================== ++#define IPU_DMFC_RD_CHAN__ADDR 0x1E060000 ++#define IPU_DMFC_RD_CHAN__EMPTY 0x1E060000,0x00000000 ++#define IPU_DMFC_RD_CHAN__FULL 0x1E060000,0xffffffff ++#define IPU_DMFC_RD_CHAN__DMFC_PPW_C 0x1E060000,0x03000000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_CLR_0 0x1E060000,0x00E00000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_SET_0 0x1E060000,0x001C0000 ++#define IPU_DMFC_RD_CHAN__DMFC_WM_EN_0 0x1E060000,0x00020000 ++#define IPU_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1E060000,0x000000C0 ++ ++#define IPU_DMFC_WR_CHAN__ADDR 0x1E060004 ++#define IPU_DMFC_WR_CHAN__EMPTY 0x1E060004,0x00000000 ++#define IPU_DMFC_WR_CHAN__FULL 0x1E060004,0xffffffff ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1E060004,0xC0000000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C 0x1E060004,0x38000000 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2C 0x1E060004,0x07000000 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1E060004,0x00C00000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C 0x1E060004,0x00380000 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1C 0x1E060004,0x00070000 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2 0x1E060004,0x0000C000 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2 0x1E060004,0x00003800 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2 0x1E060004,0x00000700 ++#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1 0x1E060004,0x000000C0 ++#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1 0x1E060004,0x00000038 ++#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1 0x1E060004,0x00000007 ++ ++#define IPU_DMFC_WR_CHAN_DEF__ADDR 0x1E060008 ++#define IPU_DMFC_WR_CHAN_DEF__EMPTY 0x1E060008,0x00000000 ++#define IPU_DMFC_WR_CHAN_DEF__FULL 0x1E060008,0xffffffff ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1E060008,0xE0000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1E060008,0x1C000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C 0x1E060008,0x02000000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1E060008,0x00E00000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1E060008,0x001C0000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C 0x1E060008,0x00020000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2 0x1E060008,0x0000E000 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2 0x1E060008,0x00001C00 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2 0x1E060008,0x00000200 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1 0x1E060008,0x000000E0 ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1 0x1E060008,0x0000001C ++#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1 0x1E060008,0x00000002 ++ ++#define IPU_DMFC_DP_CHAN__ADDR 0x1E06000C ++#define IPU_DMFC_DP_CHAN__EMPTY 0x1E06000C,0x00000000 ++#define IPU_DMFC_DP_CHAN__FULL 0x1E06000C,0xffffffff ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1E06000C,0xC0000000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F 0x1E06000C,0x38000000 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6F 0x1E06000C,0x07000000 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1E06000C,0x00C00000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B 0x1E06000C,0x00380000 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6B 0x1E06000C,0x00070000 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1E06000C,0x0000C000 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F 0x1E06000C,0x00003800 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F 0x1E06000C,0x00000700 ++#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1E06000C,0x000000C0 ++#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B 0x1E06000C,0x00000038 ++#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B 0x1E06000C,0x00000007 ++ ++#define IPU_DMFC_DP_CHAN_DEF__ADDR 0x1E060010 ++#define IPU_DMFC_DP_CHAN_DEF__EMPTY 0x1E060010,0x00000000 ++#define IPU_DMFC_DP_CHAN_DEF__FULL 0x1E060010,0xffffffff ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1E060010,0xE0000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1E060010,0x1C000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F 0x1E060010,0x02000000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1E060010,0x00E00000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1E060010,0x001C0000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B 0x1E060010,0x00020000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1E060010,0x0000E000 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1E060010,0x00001C00 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F 0x1E060010,0x00000200 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1E060010,0x000000E0 ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1E060010,0x0000001C ++#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B 0x1E060010,0x00000002 ++ ++#define IPU_DMFC_GENERAL1__ADDR 0x1E060014 ++#define IPU_DMFC_GENERAL1__EMPTY 0x1E060014,0x00000000 ++#define IPU_DMFC_GENERAL1__FULL 0x1E060014,0xffffffff ++#define IPU_DMFC_GENERAL1__WAIT4EOT_9 0x1E060014,0x01000000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_6F 0x1E060014,0x00800000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_6B 0x1E060014,0x00400000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_5F 0x1E060014,0x00200000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_5B 0x1E060014,0x00100000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_4 0x1E060014,0x00080000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_3 0x1E060014,0x00040000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_2 0x1E060014,0x00020000 ++#define IPU_DMFC_GENERAL1__WAIT4EOT_1 0x1E060014,0x00010000 ++#define IPU_DMFC_GENERAL1__DMFC_WM_CLR_9 0x1E060014,0x0000E000 ++#define IPU_DMFC_GENERAL1__DMFC_WM_SET_9 0x1E060014,0x00001C00 ++#define IPU_DMFC_GENERAL1__DMFC_WM_EN_9 0x1E060014,0x00000200 ++#define IPU_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1E060014,0x00000060 ++#define IPU_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1E060014,0x00000003 ++ ++#define IPU_DMFC_GENERAL2__ADDR 0x1E060018 ++#define IPU_DMFC_GENERAL2__EMPTY 0x1E060018,0x00000000 ++#define IPU_DMFC_GENERAL2__FULL 0x1E060018,0xffffffff ++#define IPU_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1E060018,0x1FFF0000 ++#define IPU_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD 0x1E060018,0x00001FFF ++ ++#define IPU_DMFC_IC_CTRL__ADDR 0x1E06001C ++#define IPU_DMFC_IC_CTRL__EMPTY 0x1E06001C,0x00000000 ++#define IPU_DMFC_IC_CTRL__FULL 0x1E06001C,0xffffffff ++#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1E06001C,0xFFF80000 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD 0x1E06001C,0x0007FFC0 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_PPW_C 0x1E06001C,0x00000030 ++#define IPU_DMFC_IC_CTRL__DMFC_IC_IN_PORT 0x1E06001C,0x00000007 ++ ++#define IPU_DMFC_WR_CHAN_ALT__ADDR 0x1E060020 ++#define IPU_DMFC_WR_CHAN_ALT__EMPTY 0x1E060020,0x00000000 ++#define IPU_DMFC_WR_CHAN_ALT__FULL 0x1E060020,0xffffffff ++#define IPU_DMFC_WR_CHAN_ALT__DMFC_BURST_SIZE_2_ALT 0x1E060020,0x0000C000 ++#define IPU_DMFC_WR_CHAN_ALT__DMFC_FIFO_SIZE_2_ALT 0x1E060020,0x00003800 ++#define IPU_DMFC_WR_CHAN_ALT__DMFC_ST_ADDR_2_ALT 0x1E060020,0x00000700 ++ ++#define IPU_DMFC_WR_CHAN_DEF_ALT__ADDR 0x1E060024 ++#define IPU_DMFC_WR_CHAN_DEF_ALT__EMPTY 0x1E060024,0x00000000 ++#define IPU_DMFC_WR_CHAN_DEF_ALT__FULL 0x1E060024,0xffffffff ++#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_CLR_2_ALT 0x1E060024,0x0000E000 ++#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_SET_2_ALT 0x1E060024,0x00001C00 ++#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_EN_2_ALT 0x1E060024,0x00000200 ++ ++#define IPU_DMFC_DP_CHAN_ALT__ADDR 0x1E060028 ++#define IPU_DMFC_DP_CHAN_ALT__EMPTY 0x1E060028,0x00000000 ++#define IPU_DMFC_DP_CHAN_ALT__FULL 0x1E060028,0xffffffff ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6F_ALT 0x1E060028,0xC0000000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6F_ALT 0x1E060028,0x38000000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6F_ALT 0x1E060028,0x07000000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6B_ALT 0x1E060028,0x00C00000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6B_ALT 0x1E060028,0x00380000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6B_ALT 0x1E060028,0x00070000 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_5B_ALT 0x1E060028,0x000000C0 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_5B_ALT 0x1E060028,0x00000038 ++#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_5B_ALT 0x1E060028,0x00000007 ++ ++#define IPU_DMFC_DP_CHAN_DEF_ALT__ADDR 0x1E06002C ++#define IPU_DMFC_DP_CHAN_DEF_ALT__EMPTY 0x1E06002C,0x00000000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__FULL 0x1E06002C,0xffffffff ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6F_ALT 0x1E06002C,0xE0000000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6F_ALT 0x1E06002C,0x1C000000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6F_ALT 0x1E06002C,0x02000000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6B_ALT 0x1E06002C,0x00E00000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6B_ALT 0x1E06002C,0x001C0000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6B_ALT 0x1E06002C,0x00020000 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_5B_ALT 0x1E06002C,0x000000E0 ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_5B_ALT 0x1E06002C,0x0000001C ++#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_5B_ALT 0x1E06002C,0x00000002 ++ ++#define IPU_DMFC_GENERAL1_ALT__ADDR 0x1E060030 ++#define IPU_DMFC_GENERAL1_ALT__EMPTY 0x1E060030,0x00000000 ++#define IPU_DMFC_GENERAL1_ALT__FULL 0x1E060030,0xffffffff ++#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6F_ALT 0x1E060030,0x00800000 ++#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6B_ALT 0x1E060030,0x00400000 ++#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_5B_ALT 0x1E060030,0x00100000 ++#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_2_ALT 0x1E060030,0x00020000 ++ ++#define IPU_DMFC_STAT__ADDR 0x1E060034 ++#define IPU_DMFC_STAT__EMPTY 0x1E060034,0x00000000 ++#define IPU_DMFC_STAT__FULL 0x1E060034,0xffffffff ++#define IPU_DMFC_STAT__DMFC_IC_BUFFER_EMPTY 0x1E060034,0x02000000 ++#define IPU_DMFC_STAT__DMFC_IC_BUFFER_FULL 0x1E060034,0x01000000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_11 0x1E060034,0x00800000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_10 0x1E060034,0x00400000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_9 0x1E060034,0x00200000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_8 0x1E060034,0x00100000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_7 0x1E060034,0x00080000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_6 0x1E060034,0x00040000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_5 0x1E060034,0x00020000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_4 0x1E060034,0x00010000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_3 0x1E060034,0x00008000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_2 0x1E060034,0x00004000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_1 0x1E060034,0x00002000 ++#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_0 0x1E060034,0x00001000 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_11 0x1E060034,0x00000800 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_10 0x1E060034,0x00000400 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_9 0x1E060034,0x00000200 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_8 0x1E060034,0x00000100 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_7 0x1E060034,0x00000080 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_6 0x1E060034,0x00000040 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_5 0x1E060034,0x00000020 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_4 0x1E060034,0x00000010 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_3 0x1E060034,0x00000008 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_2 0x1E060034,0x00000004 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_1 0x1E060034,0x00000002 ++#define IPU_DMFC_STAT__DMFC_FIFO_FULL_0 0x1E060034,0x00000001 ++// ================= End of IPUV3EX DMFC Registers ===================== ++ ++// ================= Start of IPUV3EX CPMEM Registers ===================== ++#define CPMEM_WORD0_DATA0_INT__ADDR 0x1F000000 ++#define CPMEM_WORD0_DATA0_INT__EMPTY 0x1F000000,0x00000000 ++#define CPMEM_WORD0_DATA0_INT__FULL 0x1F000000,0xffffffff ++#define CPMEM_WORD0_DATA0_INT__XB 0x1F000000,0xFFF80000 ++#define CPMEM_WORD0_DATA0_INT__YV 0x1F000000,0x0007FC00 ++#define CPMEM_WORD0_DATA0_INT__XV 0x1F000000,0x000003FF ++ ++#define CPMEM_WORD0_DATA1_INT__ADDR 0x1F000004 ++#define CPMEM_WORD0_DATA1_INT__EMPTY 0x1F000004,0x00000000 ++#define CPMEM_WORD0_DATA1_INT__FULL 0x1F000004,0xffffffff ++#define CPMEM_WORD0_DATA1_INT__SY_LOW 0x1F000004,0xFC000000 ++#define CPMEM_WORD0_DATA1_INT__SX 0x1F000004,0x03FFC000 ++#define CPMEM_WORD0_DATA1_INT__CF 0x1F000004,0x00002000 ++#define CPMEM_WORD0_DATA1_INT__NSB_B 0x1F000004,0x00001000 ++#define CPMEM_WORD0_DATA1_INT__YB 0x1F000004,0x00000FFF ++ ++#define CPMEM_WORD0_DATA2_INT__ADDR 0x1F000008 ++#define CPMEM_WORD0_DATA2_INT__EMPTY 0x1F000008,0x00000000 ++#define CPMEM_WORD0_DATA2_INT__FULL 0x1F000008,0xffffffff ++#define CPMEM_WORD0_DATA2_INT__SM 0x1F000008,0xFFC00000 ++#define CPMEM_WORD0_DATA2_INT__SDX 0x1F000008,0x003F8000 ++#define CPMEM_WORD0_DATA2_INT__NS 0x1F000008,0x00007FE0 ++#define CPMEM_WORD0_DATA2_INT__SY_HIGH 0x1F000008,0x0000001F ++ ++#define CPMEM_WORD0_DATA3_INT__ADDR 0x1F00000C ++#define CPMEM_WORD0_DATA3_INT__EMPTY 0x1F00000C,0x00000000 ++#define CPMEM_WORD0_DATA3_INT__FULL 0x1F00000C,0xffffffff ++#define CPMEM_WORD0_DATA3_INT__FW_LOW 0x1F00000C,0xE0000000 ++#define CPMEM_WORD0_DATA3_INT__CAE 0x1F00000C,0x10000000 ++#define CPMEM_WORD0_DATA3_INT__CAP 0x1F00000C,0x08000000 ++#define CPMEM_WORD0_DATA3_INT__THE 0x1F00000C,0x04000000 ++#define CPMEM_WORD0_DATA3_INT__VF 0x1F00000C,0x02000000 ++#define CPMEM_WORD0_DATA3_INT__HF 0x1F00000C,0x01000000 ++#define CPMEM_WORD0_DATA3_INT__ROT 0x1F00000C,0x00800000 ++#define CPMEM_WORD0_DATA3_INT__BM 0x1F00000C,0x00600000 ++#define CPMEM_WORD0_DATA3_INT__BNDM 0x1F00000C,0x001C0000 ++#define CPMEM_WORD0_DATA3_INT__SO 0x1F00000C,0x00020000 ++#define CPMEM_WORD0_DATA3_INT__DIM 0x1F00000C,0x00010000 ++#define CPMEM_WORD0_DATA3_INT__DEC_SEL 0x1F00000C,0x0000C000 ++#define CPMEM_WORD0_DATA3_INT__BPP 0x1F00000C,0x00003800 ++#define CPMEM_WORD0_DATA3_INT__SDRY 0x1F00000C,0x00000400 ++#define CPMEM_WORD0_DATA3_INT__SDRX 0x1F00000C,0x00000200 ++#define CPMEM_WORD0_DATA3_INT__SDY 0x1F00000C,0x000001FC ++#define CPMEM_WORD0_DATA3_INT__SCE 0x1F00000C,0x00000002 ++#define CPMEM_WORD0_DATA3_INT__SCC 0x1F00000C,0x00000001 ++ ++#define CPMEM_WORD0_DATA4_INT__ADDR 0x1F000010 ++#define CPMEM_WORD0_DATA4_INT__EMPTY 0x1F000010,0x00000000 ++#define CPMEM_WORD0_DATA4_INT__FULL 0x1F000010,0xffffffff ++#define CPMEM_WORD0_DATA4_INT__RESERVED 0x1F000010,0xFFC00000 ++#define CPMEM_WORD0_DATA4_INT__FH 0x1F000010,0x003FFC00 ++#define CPMEM_WORD0_DATA4_INT__FW_HIGH 0x1F000010,0x000003FF ++ ++#define CPMEM_WORD0_DATA0_N_INT__ADDR 0x1F000000 ++#define CPMEM_WORD0_DATA0_N_INT__EMPTY 0x1F000000,0x00000000 ++#define CPMEM_WORD0_DATA0_N_INT__FULL 0x1F000000,0xffffffff ++#define CPMEM_WORD0_DATA0_N_INT__XB 0x1F000000,0xFFF80000 ++#define CPMEM_WORD0_DATA0_N_INT__YV 0x1F000000,0x0007FC00 ++#define CPMEM_WORD0_DATA0_N_INT__XV 0x1F000000,0x000003FF ++ ++#define CPMEM_WORD0_DATA1_N_INT__ADDR 0x1F000004 ++#define CPMEM_WORD0_DATA1_N_INT__EMPTY 0x1F000004,0x00000000 ++#define CPMEM_WORD0_DATA1_N_INT__FULL 0x1F000004,0xffffffff ++#define CPMEM_WORD0_DATA1_N_INT__UBO_LOW 0x1F000004,0xFFFFC000 ++#define CPMEM_WORD0_DATA1_N_INT__CF 0x1F000004,0x00002000 ++#define CPMEM_WORD0_DATA1_N_INT__NSB_B 0x1F000004,0x00001000 ++#define CPMEM_WORD0_DATA1_N_INT__YB 0x1F000004,0x00000FFF ++ ++#define CPMEM_WORD0_DATA2_N_INT__ADDR 0x1F000008 ++#define CPMEM_WORD0_DATA2_N_INT__EMPTY 0x1F000008,0x00000000 ++#define CPMEM_WORD0_DATA2_N_INT__FULL 0x1F000008,0xffffffff ++#define CPMEM_WORD0_DATA2_N_INT__RESERVED 0x1F000008,0xFC000000 ++#define CPMEM_WORD0_DATA2_N_INT__IOX 0x1F000008,0x3c000000 ++#define CPMEM_WORD0_DATA2_N_INT__VBO 0x1F000008,0x03FFFFF0 ++#define CPMEM_WORD0_DATA2_N_INT__UBO_HIGH 0x1F000008,0x0000000F ++ ++#define CPMEM_WORD0_DATA3_N_INT__ADDR 0x1F00000C ++#define CPMEM_WORD0_DATA3_N_INT__EMPTY 0x1F00000C,0x00000000 ++#define CPMEM_WORD0_DATA3_N_INT__FULL 0x1F00000C,0xffffffff ++#define CPMEM_WORD0_DATA3_N_INT__FW_LOW 0x1F00000C,0xE0000000 ++#define CPMEM_WORD0_DATA3_N_INT__CAE 0x1F00000C,0x10000000 ++#define CPMEM_WORD0_DATA3_N_INT__CAP 0x1F00000C,0x08000000 ++#define CPMEM_WORD0_DATA3_N_INT__THE 0x1F00000C,0x04000000 ++#define CPMEM_WORD0_DATA3_N_INT__VF 0x1F00000C,0x02000000 ++#define CPMEM_WORD0_DATA3_N_INT__HF 0x1F00000C,0x01000000 ++#define CPMEM_WORD0_DATA3_N_INT__ROT 0x1F00000C,0x00800000 ++#define CPMEM_WORD0_DATA3_N_INT__BM 0x1F00000C,0x00600000 ++#define CPMEM_WORD0_DATA3_N_INT__BNDM 0x1F00000C,0x001C0000 ++#define CPMEM_WORD0_DATA3_N_INT__SO 0x1F00000C,0x00020000 ++#define CPMEM_WORD0_DATA3_N_INT__RESERVED 0x1F00000C,0x0001FFFF ++ ++#define CPMEM_WORD0_DATA4_N_INT__ADDR 0x1F000010 ++#define CPMEM_WORD0_DATA4_N_INT__EMPTY 0x1F000010,0x00000000 ++#define CPMEM_WORD0_DATA4_N_INT__FULL 0x1F000010,0xffffffff ++#define CPMEM_WORD0_DATA4_N_INT__RESERVED 0x1F000010,0xFFC00000 ++#define CPMEM_WORD0_DATA4_N_INT__FH 0x1F000010,0x003FFC00 ++#define CPMEM_WORD0_DATA4_N_INT__FW_HIGH 0x1F000010,0x000003FF ++ ++#define CPMEM_WORD1_DATA0_INT__ADDR 0x1F000020 ++#define CPMEM_WORD1_DATA0_INT__EMPTY 0x1F000020,0x00000000 ++#define CPMEM_WORD1_DATA0_INT__FULL 0x1F000020,0xffffffff ++#define CPMEM_WORD1_DATA0_INT__EBA1_LOW 0x1F000020,0xE0000000 ++#define CPMEM_WORD1_DATA0_INT__EBA0 0x1F000020,0x1FFFFFFF ++ ++#define CPMEM_WORD1_DATA1_INT__ADDR 0x1F000024 ++#define CPMEM_WORD1_DATA1_INT__EMPTY 0x1F000024,0x00000000 ++#define CPMEM_WORD1_DATA1_INT__FULL 0x1F000024,0xffffffff ++#define CPMEM_WORD1_DATA1_INT__ILO_LOW 0x1F000024,0xFC000000 ++#define CPMEM_WORD1_DATA1_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF ++ ++#define CPMEM_WORD1_DATA2_INT__ADDR 0x1F000028 ++#define CPMEM_WORD1_DATA2_INT__EMPTY 0x1F000028,0x00000000 ++#define CPMEM_WORD1_DATA2_INT__FULL 0x1F000028,0xffffffff ++#define CPMEM_WORD1_DATA2_INT__TH_LOW 0x1F000028,0x80000000 ++#define CPMEM_WORD1_DATA2_INT__ID 0x1F000028,0x60000000 ++#define CPMEM_WORD1_DATA2_INT__ALBM 0x1F000028,0x1C000000 ++#define CPMEM_WORD1_DATA2_INT__ALU 0x1F000028,0x02000000 ++#define CPMEM_WORD1_DATA2_INT__PFS 0x1F000028,0x01E00000 ++#define CPMEM_WORD1_DATA2_INT__NPB 0x1F000028,0x001FC000 ++#define CPMEM_WORD1_DATA2_INT__ILO_HIGH 0x1F000028,0x00003FFF ++ ++#define CPMEM_WORD1_DATA3_INT__ADDR 0x1F00002C ++#define CPMEM_WORD1_DATA3_INT__EMPTY 0x1F00002C,0x00000000 ++#define CPMEM_WORD1_DATA3_INT__FULL 0x1F00002C,0xffffffff ++#define CPMEM_WORD1_DATA3_INT__WID3 0x1F00002C,0xE0000000 ++#define CPMEM_WORD1_DATA3_INT__WID2 0x1F00002C,0x1C000000 ++#define CPMEM_WORD1_DATA3_INT__WID1 0x1F00002C,0x03800000 ++#define CPMEM_WORD1_DATA3_INT__WID0 0x1F00002C,0x00700000 ++#define CPMEM_WORD1_DATA3_INT__SL 0x1F00002C,0x000FFFC0 ++#define CPMEM_WORD1_DATA3_INT__TH_HIGH 0x1F00002C,0x0000003F ++ ++#define CPMEM_WORD1_DATA4_INT__ADDR 0x1F000030 ++#define CPMEM_WORD1_DATA4_INT__EMPTY 0x1F000030,0x00000000 ++#define CPMEM_WORD1_DATA4_INT__FULL 0x1F000030,0xffffffff ++#define CPMEM_WORD1_DATA4_INT__RESERVED 0x1F000030,0xFFF00000 ++#define CPMEM_WORD1_DATA4_INT__SXYS 0x1F000030,0x00100000 ++#define CPMEM_WORD1_DATA4_INT__OFS3 0x1F000030,0x000F8000 ++#define CPMEM_WORD1_DATA4_INT__OFS2 0x1F000030,0x00007C00 ++#define CPMEM_WORD1_DATA4_INT__OFS1 0x1F000030,0x000003E0 ++#define CPMEM_WORD1_DATA4_INT__OFS0 0x1F000030,0x0000001F ++ ++#define CPMEM_WORD1_DATA0_N_INT__ADDR 0x1F000020 ++#define CPMEM_WORD1_DATA0_N_INT__EMPTY 0x1F000020,0x00000000 ++#define CPMEM_WORD1_DATA0_N_INT__FULL 0x1F000020,0xffffffff ++#define CPMEM_WORD1_DATA0_N_INT__EBA1_LOW 0x1F000020,0xE0000000 ++#define CPMEM_WORD1_DATA0_N_INT__EBA0 0x1F000020,0x1FFFFFFF ++ ++#define CPMEM_WORD1_DATA1_N_INT__ADDR 0x1F000024 ++#define CPMEM_WORD1_DATA1_N_INT__EMPTY 0x1F000024,0x00000000 ++#define CPMEM_WORD1_DATA1_N_INT__FULL 0x1F000024,0xffffffff ++#define CPMEM_WORD1_DATA1_N_INT__ILO_LOW 0x1F000024,0xFC000000 ++#define CPMEM_WORD1_DATA1_N_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF ++ ++#define CPMEM_WORD1_DATA2_N_INT__ADDR 0x1F000028 ++#define CPMEM_WORD1_DATA2_N_INT__EMPTY 0x1F000028,0x00000000 ++#define CPMEM_WORD1_DATA2_N_INT__FULL 0x1F000028,0xffffffff ++#define CPMEM_WORD1_DATA2_N_INT__TH_LOW 0x1F000028,0x80000000 ++#define CPMEM_WORD1_DATA2_N_INT__ID 0x1F000028,0x60000000 ++#define CPMEM_WORD1_DATA2_N_INT__ALBM 0x1F000028,0x1C000000 ++#define CPMEM_WORD1_DATA2_N_INT__ALU 0x1F000028,0x02000000 ++#define CPMEM_WORD1_DATA2_N_INT__PFS 0x1F000028,0x01E00000 ++#define CPMEM_WORD1_DATA2_N_INT__NPB 0x1F000028,0x001FC000 ++#define CPMEM_WORD1_DATA2_N_INT__ILO_HIGH 0x1F000028,0x00003FFF ++ ++#define CPMEM_WORD1_DATA3_N_INT__ADDR 0x1F00002C ++#define CPMEM_WORD1_DATA3_N_INT__EMPTY 0x1F00002C,0x00000000 ++#define CPMEM_WORD1_DATA3_N_INT__FULL 0x1F00002C,0xffffffff ++#define CPMEM_WORD1_DATA3_N_INT__SLY 0x1F00002C,0x000FFFC0 ++#define CPMEM_WORD1_DATA3_N_INT__WID3 0x1F00002C,0xE0000000 ++#define CPMEM_WORD1_DATA3_N_INT__TH_HIGH 0x1F00002C,0x0000003F ++ ++#define CPMEM_WORD1_DATA4_N_INT__ADDR 0x1F000030 ++#define CPMEM_WORD1_DATA4_N_INT__EMPTY 0x1F000030,0x00000000 ++#define CPMEM_WORD1_DATA4_N_INT__FULL 0x1F000030,0xffffffff ++#define CPMEM_WORD1_DATA4_N_INT__RESERVED 0x1F000030,0xFFFFC000 ++#define CPMEM_WORD1_DATA4_N_INT__SLUV 0x1F000030,0x00003FFF ++// ================= End of IPUV3EX CPMEM Registers ===================== ++ ++#define IC_INTERNAL_MEM_FW 0x400 ++#define TASK1_TMP_COEF IC_INTERNAL_MEM_FW ++#define TASK1_CSC1_W0 TASK1_TMP_COEF+1 ++#define TASK1_CSC1_W1 TASK1_CSC1_W0+1 ++#define TASK1_CSC1_W2 TASK1_CSC1_W1+1 ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR 0x1F060000 + (TASK1_CSC1_W0 << 3) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__FULL IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C00 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C11 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C22 IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR 0x1F060000 + (TASK1_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__FULL IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SCALE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR 0x1F060000 + (TASK1_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__FULL IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C01 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C10 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C20 IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR 0x1F060000 + (TASK1_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__FULL IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR 0x1F060000 + (TASK1_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__FULL IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C02 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C12 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C21 IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR 0x1F060000 + (TASK1_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__EMPTY IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__FULL IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_ENC_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x000000FF ++ ++#define TASK2_TMP_COEF TASK1_CSC1_W2+IC_INTERNAL_MEM_FW+1 ++#define TASK2_CSC1_W0 TASK2_TMP_COEF+1 ++#define TASK2_CSC1_W1 TASK2_CSC1_W0+1 ++#define TASK2_CSC1_W2 TASK2_CSC1_W1+1 ++#define TASK2_CSC2_W0 TASK2_CSC1_W2+1 ++#define TASK2_CSC2_W1 TASK2_CSC2_W0+1 ++#define TASK2_CSC2_W2 TASK2_CSC2_W1+1 ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR 0x1F060000 + (TASK2_CSC1_W0 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C00 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C11 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C22 IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR 0x1F060000 + (TASK2_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SCALE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR 0x1F060000 + (TASK2_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C01 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C10 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C20 IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR 0x1F060000 + (TASK2_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR 0x1F060000 + (TASK2_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C02 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C12 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C21 IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR 0x1F060000 + (TASK2_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__EMPTY IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__FULL IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR 0x1F060000 + (TASK2_CSC2_W0 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C00 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C11 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C22 IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR 0x1F060000 + (TASK2_CSC2_W0 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SCALE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__A0_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR 0x1F060000 + (TASK2_CSC2_W1 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C01 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C10 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C20 IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR 0x1F060000 + (TASK2_CSC2_W1 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR 0x1F060000 + (TASK2_CSC2_W2 << 3) ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C02 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C12 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C21 IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR 0x1F060000 + (TASK2_CSC2_W2 << 3) + 4 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__EMPTY IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__FULL IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x000000FF ++ ++#define TASK3_TMP_COEF TASK2_CSC2_W2+IC_INTERNAL_MEM_FW+1 ++#define TASK3_CSC1_W0 TASK3_TMP_COEF+1 ++#define TASK3_CSC1_W1 TASK3_CSC1_W0+1 ++#define TASK3_CSC1_W2 TASK3_CSC1_W1+1 ++#define TASK3_CSC2_W0 TASK3_CSC1_W2+1 ++#define TASK3_CSC2_W1 TASK3_CSC2_W0+1 ++#define TASK3_CSC2_W2 TASK3_CSC2_W1+1 ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR 0x1F060000 + (TASK3_CSC1_W0 << 3) ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__FULL IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C00 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C11 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD0__C22 IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR 0x1F060000 + (TASK3_CSC1_W0 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__FULL IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__SCALE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_POST_CSC1_WORD1__A0_HIGH IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR 0x1F060000 + (TASK3_CSC1_W1 << 3) ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__FULL IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C01 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C10 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD2__C20 IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR 0x1F060000 + (TASK3_CSC1_W1 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__FULL IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR 0x1F060000 + (TASK3_CSC1_W2 << 3) ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__FULL IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C02 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C12 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC1_WORD4__C21 IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR 0x1F060000 + (TASK3_CSC1_W2 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__EMPTY IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__FULL IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR 0x1F060000 + (TASK3_CSC2_W0 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__FULL IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C00 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C11 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD0__C22 IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR 0x1F060000 + (TASK3_CSC2_W0 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__FULL IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000400 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__SCALE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000300 ++#define IPU_IC_TPMEM_POST_CSC2_WORD1__A0_HIGH IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR 0x1F060000 + (TASK3_CSC2_W1 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__FULL IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C01 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C10 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD2__C20 IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR 0x1F060000 + (TASK3_CSC2_W1 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__FULL IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x000000FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR 0x1F060000 + (TASK3_CSC2_W2 << 3) ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__FULL IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xF8000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C02 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x07FC0000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C12 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x0003FE00 ++#define IPU_IC_TPMEM_POST_CSC2_WORD4__C21 IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x000001FF ++ ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR 0x1F060000 + (TASK3_CSC2_W2 << 3) + 4 ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__EMPTY IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x00000000 ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__FULL IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0xffffffff ++#define IPU_IC_TPMEM_POST_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x000000FF ++ ++#define SRM_DP_COM_CONF_SYNC__ADDR 0x1F040000 ++#define SRM_DP_COM_CONF_SYNC__EMPTY 0x1F040000,0x00000000 ++#define SRM_DP_COM_CONF_SYNC__FULL 0x1F040000,0xffffffff ++#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC 0x1F040000,0x00002000 ++#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC 0x1F040000,0x00001000 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1F040000,0x00000800 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1F040000,0x00000400 ++#define SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC 0x1F040000,0x00000300 ++#define SRM_DP_COM_CONF_SYNC__DP_COC_SYNC 0x1F040000,0x00000070 ++#define SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC 0x1F040000,0x00000008 ++#define SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC 0x1F040000,0x00000004 ++#define SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC 0x1F040000,0x00000002 ++#define SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC 0x1F040000,0x00000001 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__ADDR 0x1F040004 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__EMPTY 0x1F040004,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__FULL 0x1F040004,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC 0x1F040004,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1F040004,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1F040004,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1F040004,0x000000FF ++ ++#define SRM_DP_FG_POS_SYNC__ADDR 0x1F040008 ++#define SRM_DP_FG_POS_SYNC__EMPTY 0x1F040008,0x00000000 ++#define SRM_DP_FG_POS_SYNC__FULL 0x1F040008,0xffffffff ++#define SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1F040008,0x07FF0000 ++#define SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1F040008,0x000007FF ++ ++#define SRM_DP_CUR_POS_SYNC__ADDR 0x1F04000C ++#define SRM_DP_CUR_POS_SYNC__EMPTY 0x1F04000C,0x00000000 ++#define SRM_DP_CUR_POS_SYNC__FULL 0x1F04000C,0xffffffff ++#define SRM_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1F04000C,0xF8000000 ++#define SRM_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1F04000C,0x07FF0000 ++#define SRM_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1F04000C,0x0000F800 ++#define SRM_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1F04000C,0x000007FF ++ ++#define SRM_DP_CUR_MAP_SYNC__ADDR 0x1F040010 ++#define SRM_DP_CUR_MAP_SYNC__EMPTY 0x1F040010,0x00000000 ++#define SRM_DP_CUR_MAP_SYNC__FULL 0x1F040010,0xffffffff ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1F040010,0x00FF0000 ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1F040010,0x0000FF00 ++#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1F040010,0x000000FF ++ ++#define SRM_DP_GAMMA_C_SYNC_0__ADDR 0x1F040014 ++#define SRM_DP_GAMMA_C_SYNC_0__EMPTY 0x1F040014,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_0__FULL 0x1F040014,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1F040014,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1F040014,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_1__ADDR 0x1F040018 ++#define SRM_DP_GAMMA_C_SYNC_1__EMPTY 0x1F040018,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_1__FULL 0x1F040018,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1F040018,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1F040018,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_2__ADDR 0x1F04001C ++#define SRM_DP_GAMMA_C_SYNC_2__EMPTY 0x1F04001C,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_2__FULL 0x1F04001C,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1F04001C,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1F04001C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_3__ADDR 0x1F040020 ++#define SRM_DP_GAMMA_C_SYNC_3__EMPTY 0x1F040020,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_3__FULL 0x1F040020,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1F040020,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1F040020,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_4__ADDR 0x1F040024 ++#define SRM_DP_GAMMA_C_SYNC_4__EMPTY 0x1F040024,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_4__FULL 0x1F040024,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1F040024,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1F040024,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_5__ADDR 0x1F040028 ++#define SRM_DP_GAMMA_C_SYNC_5__EMPTY 0x1F040028,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_5__FULL 0x1F040028,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1F040028,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1F040028,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_6__ADDR 0x1F04002C ++#define SRM_DP_GAMMA_C_SYNC_6__EMPTY 0x1F04002C,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_6__FULL 0x1F04002C,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1F04002C,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1F04002C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_SYNC_7__ADDR 0x1F040030 ++#define SRM_DP_GAMMA_C_SYNC_7__EMPTY 0x1F040030,0x00000000 ++#define SRM_DP_GAMMA_C_SYNC_7__FULL 0x1F040030,0xffffffff ++#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1F040030,0x01FF0000 ++#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1F040030,0x000001FF ++ ++#define SRM_DP_GAMMA_S_SYNC_0__ADDR 0x1F040034 ++#define SRM_DP_GAMMA_S_SYNC_0__EMPTY 0x1F040034,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_0__FULL 0x1F040034,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1F040034,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1F040034,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1F040034,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1F040034,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_1__ADDR 0x1F040038 ++#define SRM_DP_GAMMA_S_SYNC_1__EMPTY 0x1F040038,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_1__FULL 0x1F040038,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1F040038,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1F040038,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1F040038,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1F040038,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_2__ADDR 0x1F04003C ++#define SRM_DP_GAMMA_S_SYNC_2__EMPTY 0x1F04003C,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_2__FULL 0x1F04003C,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1F04003C,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1F04003C,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9 0x1F04003C,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8 0x1F04003C,0x000000FF ++ ++#define SRM_DP_GAMMA_S_SYNC_3__ADDR 0x1F040040 ++#define SRM_DP_GAMMA_S_SYNC_3__EMPTY 0x1F040040,0x00000000 ++#define SRM_DP_GAMMA_S_SYNC_3__FULL 0x1F040040,0xffffffff ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1F040040,0xFF000000 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1F040040,0x00FF0000 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1F040040,0x0000FF00 ++#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1F040040,0x000000FF ++ ++#define SRM_DP_CSCA_SYNC_0__ADDR 0x1F040044 ++#define SRM_DP_CSCA_SYNC_0__EMPTY 0x1F040044,0x00000000 ++#define SRM_DP_CSCA_SYNC_0__FULL 0x1F040044,0xffffffff ++#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1F040044,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1F040044,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_1__ADDR 0x1F040048 ++#define SRM_DP_CSCA_SYNC_1__EMPTY 0x1F040048,0x00000000 ++#define SRM_DP_CSCA_SYNC_1__FULL 0x1F040048,0xffffffff ++#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1F040048,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1F040048,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_2__ADDR 0x1F04004C ++#define SRM_DP_CSCA_SYNC_2__EMPTY 0x1F04004C,0x00000000 ++#define SRM_DP_CSCA_SYNC_2__FULL 0x1F04004C,0xffffffff ++#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1F04004C,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1F04004C,0x000003FF ++ ++#define SRM_DP_CSCA_SYNC_3__ADDR 0x1F040050 ++#define SRM_DP_CSCA_SYNC_3__EMPTY 0x1F040050,0x00000000 ++#define SRM_DP_CSCA_SYNC_3__FULL 0x1F040050,0xffffffff ++#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1F040050,0x03FF0000 ++#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1F040050,0x000003FF ++ ++#define SRM_DP_CSC_SYNC_0__ADDR 0x1F040054 ++#define SRM_DP_CSC_SYNC_0__EMPTY 0x1F040054,0x00000000 ++#define SRM_DP_CSC_SYNC_0__FULL 0x1F040054,0xffffffff ++#define SRM_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1F040054,0xC0000000 ++#define SRM_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1F040054,0x3FFF0000 ++#define SRM_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1F040054,0x000003FF ++ ++#define SRM_DP_CSC_SYNC_1__ADDR 0x1F040058 ++#define SRM_DP_CSC_SYNC_1__EMPTY 0x1F040058,0x00000000 ++#define SRM_DP_CSC_SYNC_1__FULL 0x1F040058,0xffffffff ++#define SRM_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1F040058,0xC0000000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1F040058,0x3FFF0000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1F040058,0x0000C000 ++#define SRM_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1F040058,0x00003FFF ++ ++#define SRM_DP_CUR_POS_ALT__ADDR 0x1F04005C ++#define SRM_DP_CUR_POS_ALT__EMPTY 0x1F04005C,0x00000000 ++#define SRM_DP_CUR_POS_ALT__FULL 0x1F04005C,0xffffffff ++#define SRM_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1F04005C,0xF8000000 ++#define SRM_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1F04005C,0x07FF0000 ++#define SRM_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1F04005C,0x0000F800 ++#define SRM_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1F04005C,0x000007FF ++ ++#define SRM_DP_COM_CONF_ASYNC0__ADDR 0x1F040060 ++#define SRM_DP_COM_CONF_ASYNC0__EMPTY 0x1F040060,0x00000000 ++#define SRM_DP_COM_CONF_ASYNC0__FULL 0x1F040060,0xffffffff ++#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_YUV_EN_ASYNC0 0x1F040060,0x00002000 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_EN_ASYNC0 0x1F040060,0x00001000 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_YUV_SAT_MODE_ASYNC0 0x1F040060,0x00000800 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_GAMUT_SAT_EN_ASYNC0 0x1F040060,0x00000400 ++#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_DEF_ASYNC0 0x1F040060,0x00000300 ++#define SRM_DP_COM_CONF_ASYNC0__DP_COC_ASYNC0 0x1F040060,0x00000070 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWCKE_ASYNC0 0x1F040060,0x00000008 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWAM_ASYNC0 0x1F040060,0x00000004 ++#define SRM_DP_COM_CONF_ASYNC0__DP_GWSEL_ASYNC0 0x1F040060,0x00000002 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__ADDR 0x1F040064 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__EMPTY 0x1F040064,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__FULL 0x1F040064,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWAV_ASYNC0 0x1F040064,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKR_ASYNC0 0x1F040064,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKG_ASYNC0 0x1F040064,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKB_ASYNC0 0x1F040064,0x000000FF ++ ++#define SRM_DP_FG_POS_ASYNC0__ADDR 0x1F040068 ++#define SRM_DP_FG_POS_ASYNC0__EMPTY 0x1F040068,0x00000000 ++#define SRM_DP_FG_POS_ASYNC0__FULL 0x1F040068,0xffffffff ++#define SRM_DP_FG_POS_ASYNC0__DP_FGXP_ASYNC0 0x1F040068,0x07FF0000 ++#define SRM_DP_FG_POS_ASYNC0__DP_FGYP_ASYNC0 0x1F040068,0x000007FF ++ ++#define SRM_DP_CUR_POS_ASYNC0__ADDR 0x1F04006C ++#define SRM_DP_CUR_POS_ASYNC0__EMPTY 0x1F04006C,0x00000000 ++#define SRM_DP_CUR_POS_ASYNC0__FULL 0x1F04006C,0xffffffff ++#define SRM_DP_CUR_POS_ASYNC0__DP_CXW_ASYNC0 0x1F04006C,0xF8000000 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CXP_ASYNC0 0x1F04006C,0x07FF0000 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CYH_ASYNC0 0x1F04006C,0x0000F800 ++#define SRM_DP_CUR_POS_ASYNC0__DP_CYP_ASYNC0 0x1F04006C,0x000007FF ++ ++#define SRM_DP_CUR_MAP_ASYNC0__ADDR 0x1F040070 ++#define SRM_DP_CUR_MAP_ASYNC0__EMPTY 0x1F040070,0x00000000 ++#define SRM_DP_CUR_MAP_ASYNC0__FULL 0x1F040070,0xffffffff ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_R_ASYNC0 0x1F040070,0x00FF0000 ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_G_ASYNC0 0x1F040070,0x0000FF00 ++#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_B_ASYNC0 0x1F040070,0x000000FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_0__ADDR 0x1F040074 ++#define SRM_DP_GAMMA_C_ASYNC0_0__EMPTY 0x1F040074,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_0__FULL 0x1F040074,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_1 0x1F040074,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_0 0x1F040074,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_1__ADDR 0x1F040078 ++#define SRM_DP_GAMMA_C_ASYNC0_1__EMPTY 0x1F040078,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_1__FULL 0x1F040078,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_3 0x1F040078,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_2 0x1F040078,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_2__ADDR 0x1F04007C ++#define SRM_DP_GAMMA_C_ASYNC0_2__EMPTY 0x1F04007C,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_2__FULL 0x1F04007C,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_5 0x1F04007C,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_4 0x1F04007C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_3__ADDR 0x1F040080 ++#define SRM_DP_GAMMA_C_ASYNC0_3__EMPTY 0x1F040080,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_3__FULL 0x1F040080,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_7 0x1F040080,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_6 0x1F040080,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_4__ADDR 0x1F040084 ++#define SRM_DP_GAMMA_C_ASYNC0_4__EMPTY 0x1F040084,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_4__FULL 0x1F040084,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_9 0x1F040084,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_8 0x1F040084,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_5__ADDR 0x1F040088 ++#define SRM_DP_GAMMA_C_ASYNC0_5__EMPTY 0x1F040088,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_5__FULL 0x1F040088,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_11 0x1F040088,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_10 0x1F040088,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_6__ADDR 0x1F04008C ++#define SRM_DP_GAMMA_C_ASYNC0_6__EMPTY 0x1F04008C,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_6__FULL 0x1F04008C,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_13 0x1F04008C,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_12 0x1F04008C,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC0_7__ADDR 0x1F040090 ++#define SRM_DP_GAMMA_C_ASYNC0_7__EMPTY 0x1F040090,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC0_7__FULL 0x1F040090,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_15 0x1F040090,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_14 0x1F040090,0x000001FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_0__ADDR 0x1F040094 ++#define SRM_DP_GAMMA_S_ASYNC0_0__EMPTY 0x1F040094,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__FULL 0x1F040094,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_3 0x1F040094,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_2 0x1F040094,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_1 0x1F040094,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_0 0x1F040094,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_1__ADDR 0x1F040098 ++#define SRM_DP_GAMMA_S_ASYNC0_1__EMPTY 0x1F040098,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__FULL 0x1F040098,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_7 0x1F040098,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_6 0x1F040098,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_5 0x1F040098,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_4 0x1F040098,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_2__ADDR 0x1F04009C ++#define SRM_DP_GAMMA_S_ASYNC0_2__EMPTY 0x1F04009C,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__FULL 0x1F04009C,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_11 0x1F04009C,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_10 0x1F04009C,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_9 0x1F04009C,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_8 0x1F04009C,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC0_3__ADDR 0x1F0400A0 ++#define SRM_DP_GAMMA_S_ASYNC0_3__EMPTY 0x1F0400A0,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__FULL 0x1F0400A0,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_15 0x1F0400A0,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_14 0x1F0400A0,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_13 0x1F0400A0,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_12 0x1F0400A0,0x000000FF ++ ++#define SRM_DP_CSCA_ASYNC0_0__ADDR 0x1F0400A4 ++#define SRM_DP_CSCA_ASYNC0_0__EMPTY 0x1F0400A4,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_0__FULL 0x1F0400A4,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_1 0x1F0400A4,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_0 0x1F0400A4,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_1__ADDR 0x1F0400A8 ++#define SRM_DP_CSCA_ASYNC0_1__EMPTY 0x1F0400A8,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_1__FULL 0x1F0400A8,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_3 0x1F0400A8,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_2 0x1F0400A8,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_2__ADDR 0x1F0400AC ++#define SRM_DP_CSCA_ASYNC0_2__EMPTY 0x1F0400AC,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_2__FULL 0x1F0400AC,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_5 0x1F0400AC,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_4 0x1F0400AC,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC0_3__ADDR 0x1F0400B0 ++#define SRM_DP_CSCA_ASYNC0_3__EMPTY 0x1F0400B0,0x00000000 ++#define SRM_DP_CSCA_ASYNC0_3__FULL 0x1F0400B0,0xffffffff ++#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_7 0x1F0400B0,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_6 0x1F0400B0,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC0_0__ADDR 0x1F0400B4 ++#define SRM_DP_CSC_ASYNC0_0__EMPTY 0x1F0400B4,0x00000000 ++#define SRM_DP_CSC_ASYNC0_0__FULL 0x1F0400B4,0xffffffff ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_S0_ASYNC0 0x1F0400B4,0xC0000000 ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_B0_ASYNC0 0x1F0400B4,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC0_0__DP_CSC_A8_ASYNC0 0x1F0400B4,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC0_1__ADDR 0x1F0400B8 ++#define SRM_DP_CSC_ASYNC0_1__EMPTY 0x1F0400B8,0x00000000 ++#define SRM_DP_CSC_ASYNC0_1__FULL 0x1F0400B8,0xffffffff ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S2_ASYNC0 0x1F0400B8,0xC0000000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B2_ASYNC0 0x1F0400B8,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S1_ASYNC0 0x1F0400B8,0x0000C000 ++#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B1_ASYNC0 0x1F0400B8,0x00003FFF ++ ++#define SRM_DP_COM_CONF_ASYNC1__ADDR 0x1F0400BC ++#define SRM_DP_COM_CONF_ASYNC1__EMPTY 0x1F0400BC,0x00000000 ++#define SRM_DP_COM_CONF_ASYNC1__FULL 0x1F0400BC,0xffffffff ++#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_YUV_EN_ASYNC1 0x1F0400BC,0x00002000 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_EN_ASYNC1 0x1F0400BC,0x00001000 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_YUV_SAT_MODE_ASYNC1 0x1F0400BC,0x00000800 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_GAMUT_SAT_EN_ASYNC1 0x1F0400BC,0x00000400 ++#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_DEF_ASYNC1 0x1F0400BC,0x00000300 ++#define SRM_DP_COM_CONF_ASYNC1__DP_COC_ASYNC1 0x1F0400BC,0x00000070 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWCKE_ASYNC1 0x1F0400BC,0x00000008 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWAM_ASYNC1 0x1F0400BC,0x00000004 ++#define SRM_DP_COM_CONF_ASYNC1__DP_GWSEL_ASYNC1 0x1F0400BC,0x00000002 ++ ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__ADDR 0x1F0400C0 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__EMPTY 0x1F0400C0,0x00000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__FULL 0x1F0400C0,0xffffffff ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWAV_ASYNC1 0x1F0400C0,0xFF000000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKR_ASYNC1 0x1F0400C0,0x00FF0000 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKG_ASYNC1 0x1F0400C0,0x0000FF00 ++#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKB_ASYNC1 0x1F0400C0,0x000000FF ++ ++#define SRM_DP_FG_POS_ASYNC1__ADDR 0x1F0400C4 ++#define SRM_DP_FG_POS_ASYNC1__EMPTY 0x1F0400C4,0x00000000 ++#define SRM_DP_FG_POS_ASYNC1__FULL 0x1F0400C4,0xffffffff ++#define SRM_DP_FG_POS_ASYNC1__DP_FGXP_ASYNC1 0x1F0400C4,0x07FF0000 ++#define SRM_DP_FG_POS_ASYNC1__DP_FGYP_ASYNC1 0x1F0400C4,0x000007FF ++ ++#define SRM_DP_CUR_POS_ASYNC1__ADDR 0x1F0400C8 ++#define SRM_DP_CUR_POS_ASYNC1__EMPTY 0x1F0400C8,0x00000000 ++#define SRM_DP_CUR_POS_ASYNC1__FULL 0x1F0400C8,0xffffffff ++#define SRM_DP_CUR_POS_ASYNC1__DP_CXW_ASYNC1 0x1F0400C8,0xF8000000 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CXP_ASYNC1 0x1F0400C8,0x07FF0000 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CYH_ASYNC1 0x1F0400C8,0x0000F800 ++#define SRM_DP_CUR_POS_ASYNC1__DP_CYP_ASYNC1 0x1F0400C8,0x000007FF ++ ++#define SRM_DP_CUR_MAP_ASYNC1__ADDR 0x1F0400CC ++#define SRM_DP_CUR_MAP_ASYNC1__EMPTY 0x1F0400CC,0x00000000 ++#define SRM_DP_CUR_MAP_ASYNC1__FULL 0x1F0400CC,0xffffffff ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_R_ASYNC1 0x1F0400CC,0x00FF0000 ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_G_ASYNC1 0x1F0400CC,0x0000FF00 ++#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_B_ASYNC1 0x1F0400CC,0x000000FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_0__ADDR 0x1F0400D0 ++#define SRM_DP_GAMMA_C_ASYNC1_0__EMPTY 0x1F0400D0,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_0__FULL 0x1F0400D0,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_1 0x1F0400D0,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_0 0x1F0400D0,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_1__ADDR 0x1F0400D4 ++#define SRM_DP_GAMMA_C_ASYNC1_1__EMPTY 0x1F0400D4,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_1__FULL 0x1F0400D4,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_3 0x1F0400D4,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_2 0x1F0400D4,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_2__ADDR 0x1F0400D8 ++#define SRM_DP_GAMMA_C_ASYNC1_2__EMPTY 0x1F0400D8,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_2__FULL 0x1F0400D8,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_5 0x1F0400D8,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_4 0x1F0400D8,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_3__ADDR 0x1F0400DC ++#define SRM_DP_GAMMA_C_ASYNC1_3__EMPTY 0x1F0400DC,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_3__FULL 0x1F0400DC,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_7 0x1F0400DC,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_6 0x1F0400DC,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_4__ADDR 0x1F0400E0 ++#define SRM_DP_GAMMA_C_ASYNC1_4__EMPTY 0x1F0400E0,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_4__FULL 0x1F0400E0,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_9 0x1F0400E0,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_8 0x1F0400E0,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_5__ADDR 0x1F0400E4 ++#define SRM_DP_GAMMA_C_ASYNC1_5__EMPTY 0x1F0400E4,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_5__FULL 0x1F0400E4,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_11 0x1F0400E4,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_10 0x1F0400E4,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_6__ADDR 0x1F0400E8 ++#define SRM_DP_GAMMA_C_ASYNC1_6__EMPTY 0x1F0400E8,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_6__FULL 0x1F0400E8,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_13 0x1F0400E8,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_12 0x1F0400E8,0x000001FF ++ ++#define SRM_DP_GAMMA_C_ASYNC1_7__ADDR 0x1F0400EC ++#define SRM_DP_GAMMA_C_ASYNC1_7__EMPTY 0x1F0400EC,0x00000000 ++#define SRM_DP_GAMMA_C_ASYNC1_7__FULL 0x1F0400EC,0xffffffff ++#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_15 0x1F0400EC,0x01FF0000 ++#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_14 0x1F0400EC,0x000001FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_0__ADDR 0x1F0400F0 ++#define SRM_DP_GAMMA_S_ASYNC1_0__EMPTY 0x1F0400F0,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__FULL 0x1F0400F0,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_3 0x1F0400F0,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_2 0x1F0400F0,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_1 0x1F0400F0,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_0 0x1F0400F0,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_1__ADDR 0x1F0400F4 ++#define SRM_DP_GAMMA_S_ASYNC1_1__EMPTY 0x1F0400F4,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__FULL 0x1F0400F4,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_7 0x1F0400F4,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_6 0x1F0400F4,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_5 0x1F0400F4,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_4 0x1F0400F4,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_2__ADDR 0x1F0400F8 ++#define SRM_DP_GAMMA_S_ASYNC1_2__EMPTY 0x1F0400F8,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__FULL 0x1F0400F8,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_11 0x1F0400F8,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_10 0x1F0400F8,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_9 0x1F0400F8,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_8 0x1F0400F8,0x000000FF ++ ++#define SRM_DP_GAMMA_S_ASYNC1_3__ADDR 0x1F0400FC ++#define SRM_DP_GAMMA_S_ASYNC1_3__EMPTY 0x1F0400FC,0x00000000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__FULL 0x1F0400FC,0xffffffff ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_15 0x1F0400FC,0xFF000000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_14 0x1F0400FC,0x00FF0000 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_13 0x1F0400FC,0x0000FF00 ++#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_12 0x1F0400FC,0x000000FF ++ ++#define SRM_DP_CSCA_ASYNC1_0__ADDR 0x1F040100 ++#define SRM_DP_CSCA_ASYNC1_0__EMPTY 0x1F040100,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_0__FULL 0x1F040100,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_1 0x1F040100,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_0 0x1F040100,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_1__ADDR 0x1F040104 ++#define SRM_DP_CSCA_ASYNC1_1__EMPTY 0x1F040104,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_1__FULL 0x1F040104,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_3 0x1F040104,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_2 0x1F040104,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_2__ADDR 0x1F040108 ++#define SRM_DP_CSCA_ASYNC1_2__EMPTY 0x1F040108,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_2__FULL 0x1F040108,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_5 0x1F040108,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_4 0x1F040108,0x000003FF ++ ++#define SRM_DP_CSCA_ASYNC1_3__ADDR 0x1F04010C ++#define SRM_DP_CSCA_ASYNC1_3__EMPTY 0x1F04010C,0x00000000 ++#define SRM_DP_CSCA_ASYNC1_3__FULL 0x1F04010C,0xffffffff ++#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_7 0x1F04010C,0x03FF0000 ++#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_6 0x1F04010C,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC1_0__ADDR 0x1F040110 ++#define SRM_DP_CSC_ASYNC1_0__EMPTY 0x1F040110,0x00000000 ++#define SRM_DP_CSC_ASYNC1_0__FULL 0x1F040110,0xffffffff ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_S0_ASYNC1 0x1F040110,0xC0000000 ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_B0_ASYNC1 0x1F040110,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC1_0__DP_CSC_A8_ASYNC1 0x1F040110,0x000003FF ++ ++#define SRM_DP_CSC_ASYNC1_1__ADDR 0x1F040114 ++#define SRM_DP_CSC_ASYNC1_1__EMPTY 0x1F040114,0x00000000 ++#define SRM_DP_CSC_ASYNC1_1__FULL 0x1F040114,0xffffffff ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S2_ASYNC1 0x1F040114,0xC0000000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B2_ASYNC1 0x1F040114,0x3FFF0000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S1_ASYNC1 0x1F040114,0x0000C000 ++#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B1_ASYNC1 0x1F040114,0x00003FFF ++ ++#define SRM_ISP_C0__ADDR 0x1F040118 ++#define SRM_ISP_C0__EMPTY 0x1F040118,0x00000000 ++#define SRM_ISP_C0__FULL 0x1F040118,0xffffffff ++#define SRM_ISP_C0__ISP_BURST_SIZE 0x1F040118,0x001C0000 ++#define SRM_ISP_C0__ISP_RED_ROW_BEGIN 0x1F040118,0x00020000 ++#define SRM_ISP_C0__ISP_GREEN_P_BEGIN 0x1F040118,0x00010000 ++#define SRM_ISP_C0__LINEARCCM_ON 0x1F040118,0x00004000 ++#define SRM_ISP_C0__LLF_G_EN 0x1F040118,0x00002000 ++#define SRM_ISP_C0__LLF_RB_EN 0x1F040118,0x00001000 ++#define SRM_ISP_C0__AD_EN 0x1F040118,0x00000800 ++#define SRM_ISP_C0__STS_EN 0x1F040118,0x00000400 ++#define SRM_ISP_C0__CL_EN 0x1F040118,0x00000200 ++#define SRM_ISP_C0__CS_EN 0x1F040118,0x00000100 ++#define SRM_ISP_C0__CCA_EN 0x1F040118,0x00000080 ++#define SRM_ISP_C0__HFE_EN 0x1F040118,0x00000040 ++#define SRM_ISP_C0__CNS_EN 0x1F040118,0x00000020 ++#define SRM_ISP_C0__MTF_ROC_EN 0x1F040118,0x00000010 ++#define SRM_ISP_C0__GAMMA_EN 0x1F040118,0x00000008 ++#define SRM_ISP_C0__CROC_EN 0x1F040118,0x00000004 ++#define SRM_ISP_C0__TBPR_EN 0x1F040118,0x00000002 ++#define SRM_ISP_C0__BPR_EN 0x1F040118,0x00000001 ++ ++#define SRM_ISP_C1__ADDR 0x1F04011C ++#define SRM_ISP_C1__EMPTY 0x1F04011C,0x00000000 ++#define SRM_ISP_C1__FULL 0x1F04011C,0xffffffff ++#define SRM_ISP_C1__YUV_EN 0x1F04011C,0x20000000 ++#define SRM_ISP_C1__CSC_SAT_MODE 0x1F04011C,0x10000000 ++#define SRM_ISP_C1__BOTTOM_CROP 0x1F04011C,0x0E000000 ++#define SRM_ISP_C1__TOP_CROP 0x1F04011C,0x01C00000 ++#define SRM_ISP_C1__RIGHT_CROP 0x1F04011C,0x00380000 ++#define SRM_ISP_C1__LEFT_CROP 0x1F04011C,0x00070000 ++#define SRM_ISP_C1__MTF_ROC_SH_M 0x1F04011C,0x00006000 ++#define SRM_ISP_C1__MTF_ROC_SH_N 0x1F04011C,0x00001800 ++#define SRM_ISP_C1__MTF_ROC_SH_QA 0x1F04011C,0x00000700 ++#define SRM_ISP_C1__MTF_ROC_SH_SHARP 0x1F04011C,0x000000E0 ++#define SRM_ISP_C1__WIDEASPECT 0x1F04011C,0x00000010 ++#define SRM_ISP_C1__APP_SEL 0x1F04011C,0x0000000C ++#define SRM_ISP_C1__INT_MODE 0x1F04011C,0x00000003 ++ ++#define SRM_ISP_FS__ADDR 0x1F040120 ++#define SRM_ISP_FS__EMPTY 0x1F040120,0x00000000 ++#define SRM_ISP_FS__FULL 0x1F040120,0xffffffff ++#define SRM_ISP_FS__FWIDTH 0x1F040120,0x0FFF0000 ++#define SRM_ISP_FS__FHEIGHT 0x1F040120,0x00000FFF ++ ++#define SRM_ISP_BI__ADDR 0x1F040124 ++#define SRM_ISP_BI__EMPTY 0x1F040124,0x00000000 ++#define SRM_ISP_BI__FULL 0x1F040124,0xffffffff ++#define SRM_ISP_BI__HBLANK 0x1F040124,0x0FFF0000 ++#define SRM_ISP_BI__VBLANK 0x1F040124,0x00000FFF ++ ++#define SRM_ISP_OCO__ADDR 0x1F040128 ++#define SRM_ISP_OCO__EMPTY 0x1F040128,0x00000000 ++#define SRM_ISP_OCO__FULL 0x1F040128,0xffffffff ++#define SRM_ISP_OCO__HOFFSET 0x1F040128,0x1FFF0000 ++#define SRM_ISP_OCO__VOFFSET 0x1F040128,0x00001FFF ++ ++#define SRM_ISP_BPR1__ADDR 0x1F04012C ++#define SRM_ISP_BPR1__EMPTY 0x1F04012C,0x00000000 ++#define SRM_ISP_BPR1__FULL 0x1F04012C,0xffffffff ++#define SRM_ISP_BPR1__TB 0x1F04012C,0xFF000000 ++#define SRM_ISP_BPR1__TDR 0x1F04012C,0x00FF0000 ++#define SRM_ISP_BPR1__TR 0x1F04012C,0x0000FF00 ++#define SRM_ISP_BPR1__DKR 0x1F04012C,0x000000FF ++ ++#define SRM_ISP_BPR2__ADDR 0x1F040130 ++#define SRM_ISP_BPR2__EMPTY 0x1F040130,0x00000000 ++#define SRM_ISP_BPR2__FULL 0x1F040130,0xffffffff ++#define SRM_ISP_BPR2__BRB 0x1F040130,0xFF000000 ++#define SRM_ISP_BPR2__TT 0x1F040130,0x00FF0000 ++#define SRM_ISP_BPR2__TVDB 0x1F040130,0x0000FF00 ++#define SRM_ISP_BPR2__TDB 0x1F040130,0x000000FF ++ ++#define SRM_ISP_BPR3__ADDR 0x1F040134 ++#define SRM_ISP_BPR3__EMPTY 0x1F040134,0x00000000 ++#define SRM_ISP_BPR3__FULL 0x1F040134,0xffffffff ++#define SRM_ISP_BPR3__TG 0x1F040134,0xFF000000 ++#define SRM_ISP_BPR3__TGF 0x1F040134,0x00FF0000 ++#define SRM_ISP_BPR3__DKB 0x1F040134,0x0000FF00 ++#define SRM_ISP_BPR3__TG2 0x1F040134,0x000000FF ++ ++#define SRM_ISP_BPR4__ADDR 0x1F040138 ++#define SRM_ISP_BPR4__EMPTY 0x1F040138,0x00000000 ++#define SRM_ISP_BPR4__FULL 0x1F040138,0xffffffff ++#define SRM_ISP_BPR4__DKRCL 0x1F040138,0xFF000000 ++#define SRM_ISP_BPR4__TGFCL 0x1F040138,0x00FF0000 ++#define SRM_ISP_BPR4__TCL2 0x1F040138,0x0000FF00 ++#define SRM_ISP_BPR4__TCL 0x1F040138,0x000000FF ++ ++#define SRM_ISP_BPR5__ADDR 0x1F04013C ++#define SRM_ISP_BPR5__EMPTY 0x1F04013C,0x00000000 ++#define SRM_ISP_BPR5__FULL 0x1F04013C,0xffffffff ++#define SRM_ISP_BPR5__TGL2 0x1E010024,0x0000FF00 ++#define SRM_ISP_BPR5__TBC 0x1F04013C,0x000000FF ++ ++#define SRM_ISP_CCMLIN0__ADDR 0x1F040140 ++#define SRM_ISP_CCMLIN0__EMPTY 0x1F040140,0x00000000 ++#define SRM_ISP_CCMLIN0__FULL 0x1F040140,0xffffffff ++#define SRM_ISP_CCMLIN0__CCMLIN12 0x1F040140,0x7C000000 ++#define SRM_ISP_CCMLIN0__CCMLIN11 0x1F040140,0x03E00000 ++#define SRM_ISP_CCMLIN0__CCMLIN10 0x1F040140,0x001F0000 ++#define SRM_ISP_CCMLIN0__CCMLIN02 0x1F040140,0x00007C00 ++#define SRM_ISP_CCMLIN0__CCMLIN01 0x1F040140,0x000003E0 ++#define SRM_ISP_CCMLIN0__CCMLIN00 0x1F040140,0x0000001F ++ ++#define SRM_ISP_CCMLIN1__ADDR 0x1F040144 ++#define SRM_ISP_CCMLIN1__EMPTY 0x1F040144,0x00000000 ++#define SRM_ISP_CCMLIN1__FULL 0x1F040144,0xffffffff ++#define SRM_ISP_CCMLIN1__CCMLIN22 0x1F040144,0x00007C00 ++#define SRM_ISP_CCMLIN1__CCMLIN21 0x1F040144,0x000003E0 ++#define SRM_ISP_CCMLIN1__CCMLIN20 0x1F040144,0x0000001F ++ ++#define SRM_ISP_CG_0__ADDR 0x1F040148 ++#define SRM_ISP_CG_0__EMPTY 0x1F040148,0x00000000 ++#define SRM_ISP_CG_0__FULL 0x1F040148,0xffffffff ++#define SRM_ISP_CG_0__BGAIN 0x1F040148,0xFF000000 ++#define SRM_ISP_CG_0__GBGAIN 0x1F040148,0x00FF0000 ++#define SRM_ISP_CG_0__GRGAIN 0x1F040148,0x0000FF00 ++#define SRM_ISP_CG_0__RGAIN 0x1F040148,0x000000FF ++ ++#define SRM_ISP_CG_1__ADDR 0x1F04014C ++#define SRM_ISP_CG_1__EMPTY 0x1F04014C,0x00000000 ++#define SRM_ISP_CG_1__FULL 0x1F04014C,0xffffffff ++#define SRM_ISP_CG_1__BSHIFT 0x1F04014C,0x00000030 ++#define SRM_ISP_CG_1__GSHIFT 0x1F04014C,0x0000000C ++#define SRM_ISP_CG_1__RSHIFT 0x1F04014C,0x00000003 ++ ++#define SRM_ISP_ROC_0__ADDR 0x1F040150 ++#define SRM_ISP_ROC_0__EMPTY 0x1F040150,0x00000000 ++#define SRM_ISP_ROC_0__FULL 0x1F040150,0xffffffff ++#define SRM_ISP_ROC_0__CROC_Q_BLIN 0x1F040150,0x01C00000 ++#define SRM_ISP_ROC_0__CROC_Q_GLIN 0x1F040150,0x00380000 ++#define SRM_ISP_ROC_0__CROC_Q_RLIN 0x1F040150,0x00070000 ++#define SRM_ISP_ROC_0__CROC_SH_QR 0x1F040150,0x00007000 ++#define SRM_ISP_ROC_0__CROC_SH_QRGB 0x1F040150,0x00000E00 ++#define SRM_ISP_ROC_0__CROC_SH_QB 0x1F040150,0x000001C0 ++#define SRM_ISP_ROC_0__CROC_R_APP 0x1F040150,0x00000030 ++#define SRM_ISP_ROC_0__CROC_G_APP 0x1F040150,0x0000000C ++#define SRM_ISP_ROC_0__CROC_B_APP 0x1F040150,0x00000003 ++ ++#define SRM_ISP_ROC_1__ADDR 0x1F040154 ++#define SRM_ISP_ROC_1__EMPTY 0x1F040154,0x00000000 ++#define SRM_ISP_ROC_1__FULL 0x1F040154,0xffffffff ++#define SRM_ISP_ROC_1__CROC_MYB 0x1F040154,0xFF000000 ++#define SRM_ISP_ROC_1__CROC_MXB 0x1F040154,0x00FF0000 ++#define SRM_ISP_ROC_1__CROC_MYG 0x1F040154,0x0000FF00 ++#define SRM_ISP_ROC_1__CROC_MXG 0x1F040154,0x000000FF ++ ++#define SRM_ISP_ROC_2__ADDR 0x1F040158 ++#define SRM_ISP_ROC_2__EMPTY 0x1F040158,0x00000000 ++#define SRM_ISP_ROC_2__FULL 0x1F040158,0xffffffff ++#define SRM_ISP_ROC_2__CROC_MYR 0x1F040158,0x0000FF00 ++#define SRM_ISP_ROC_2__CROC_MXR 0x1F040158,0x000000FF ++ ++#define SRM_ISP_RROC_0__ADDR 0x1F04015C ++#define SRM_ISP_RROC_0__EMPTY 0x1F04015C,0x00000000 ++#define SRM_ISP_RROC_0__FULL 0x1F04015C,0xffffffff ++#define SRM_ISP_RROC_0__CROC_RC1 0x1F04015C,0x07FF0000 ++#define SRM_ISP_RROC_0__CROC_RC0 0x1F04015C,0x000007FF ++ ++#define SRM_ISP_RROC_1__ADDR 0x1F040160 ++#define SRM_ISP_RROC_1__EMPTY 0x1F040160,0x00000000 ++#define SRM_ISP_RROC_1__FULL 0x1F040160,0xffffffff ++#define SRM_ISP_RROC_1__CROC_RC3 0x1F040160,0x07FF0000 ++#define SRM_ISP_RROC_1__CROC_RC2 0x1F040160,0x000007FF ++ ++#define SRM_ISP_RROC_2__ADDR 0x1F040164 ++#define SRM_ISP_RROC_2__EMPTY 0x1F040164,0x00000000 ++#define SRM_ISP_RROC_2__FULL 0x1F040164,0xffffffff ++#define SRM_ISP_RROC_2__CROC_RC5 0x1F040164,0x07FF0000 ++#define SRM_ISP_RROC_2__CROC_RC4 0x1F040164,0x000007FF ++ ++#define SRM_ISP_RROC_3__ADDR 0x1F040168 ++#define SRM_ISP_RROC_3__EMPTY 0x1F040168,0x00000000 ++#define SRM_ISP_RROC_3__FULL 0x1F040168,0xffffffff ++#define SRM_ISP_RROC_3__CROC_RC7 0x1F040168,0x07FF0000 ++#define SRM_ISP_RROC_3__CROC_RC6 0x1F040168,0x000007FF ++ ++#define SRM_ISP_RROC_4__ADDR 0x1F04016C ++#define SRM_ISP_RROC_4__EMPTY 0x1F04016C,0x00000000 ++#define SRM_ISP_RROC_4__FULL 0x1F04016C,0xffffffff ++#define SRM_ISP_RROC_4__CROC_RC9 0x1F04016C,0x07FF0000 ++#define SRM_ISP_RROC_4__CROC_RC8 0x1F04016C,0x000007FF ++ ++#define SRM_ISP_RROC_5__ADDR 0x1F040170 ++#define SRM_ISP_RROC_5__EMPTY 0x1F040170,0x00000000 ++#define SRM_ISP_RROC_5__FULL 0x1F040170,0xffffffff ++#define SRM_ISP_RROC_5__CROC_RC11 0x1F040170,0x07FF0000 ++#define SRM_ISP_RROC_5__CROC_RC10 0x1F040170,0x000007FF ++ ++#define SRM_ISP_RROC_6__ADDR 0x1F040174 ++#define SRM_ISP_RROC_6__EMPTY 0x1F040174,0x00000000 ++#define SRM_ISP_RROC_6__FULL 0x1F040174,0xffffffff ++#define SRM_ISP_RROC_6__CROC_RC13 0x1F040174,0x07FF0000 ++#define SRM_ISP_RROC_6__CROC_RC12 0x1F040174,0x000007FF ++ ++#define SRM_ISP_RROC_7__ADDR 0x1F040178 ++#define SRM_ISP_RROC_7__EMPTY 0x1F040178,0x00000000 ++#define SRM_ISP_RROC_7__FULL 0x1F040178,0xffffffff ++#define SRM_ISP_RROC_7__CROC_RC15 0x1F040178,0x07FF0000 ++#define SRM_ISP_RROC_7__CROC_RC14 0x1F040178,0x000007FF ++ ++#define SRM_ISP_RROS_0__ADDR 0x1F04017C ++#define SRM_ISP_RROS_0__EMPTY 0x1F04017C,0x00000000 ++#define SRM_ISP_RROS_0__FULL 0x1F04017C,0xffffffff ++#define SRM_ISP_RROS_0__CROC_RS3 0x1F04017C,0x7F000000 ++#define SRM_ISP_RROS_0__CROC_RS2 0x1F04017C,0x007F0000 ++#define SRM_ISP_RROS_0__CROC_RS1 0x1F04017C,0x00007F00 ++#define SRM_ISP_RROS_0__CROC_RS0 0x1F04017C,0x0000007F ++ ++#define SRM_ISP_RROS_1__ADDR 0x1F040180 ++#define SRM_ISP_RROS_1__EMPTY 0x1F040180,0x00000000 ++#define SRM_ISP_RROS_1__FULL 0x1F040180,0xffffffff ++#define SRM_ISP_RROS_1__CROC_RS7 0x1F040180,0x7F000000 ++#define SRM_ISP_RROS_1__CROC_RS6 0x1F040180,0x007F0000 ++#define SRM_ISP_RROS_1__CROC_RS5 0x1F040180,0x00007F00 ++#define SRM_ISP_RROS_1__CROC_RS4 0x1F040180,0x0000007F ++ ++#define SRM_ISP_RROS_2__ADDR 0x1F040184 ++#define SRM_ISP_RROS_2__EMPTY 0x1F040184,0x00000000 ++#define SRM_ISP_RROS_2__FULL 0x1F040184,0xffffffff ++#define SRM_ISP_RROS_2__CROC_RS11 0x1F040184,0x7F000000 ++#define SRM_ISP_RROS_2__CROC_RS10 0x1F040184,0x007F0000 ++#define SRM_ISP_RROS_2__CROC_RS9 0x1F040184,0x00007F00 ++#define SRM_ISP_RROS_2__CROC_RS8 0x1F040184,0x0000007F ++ ++#define SRM_ISP_RROS_3__ADDR 0x1F040188 ++#define SRM_ISP_RROS_3__EMPTY 0x1F040188,0x00000000 ++#define SRM_ISP_RROS_3__FULL 0x1F040188,0xffffffff ++#define SRM_ISP_RROS_3__CROC_RS15 0x1F040188,0x7F000000 ++#define SRM_ISP_RROS_3__CROC_RS14 0x1F040188,0x007F0000 ++#define SRM_ISP_RROS_3__CROC_RS13 0x1F040188,0x00007F00 ++#define SRM_ISP_RROS_3__CROC_RS12 0x1F040188,0x0000007F ++ ++#define SRM_ISP_GROC_0__ADDR 0x1F04018C ++#define SRM_ISP_GROC_0__EMPTY 0x1F04018C,0x00000000 ++#define SRM_ISP_GROC_0__FULL 0x1F04018C,0xffffffff ++#define SRM_ISP_GROC_0__CROC_GC1 0x1F04018C,0x07FF0000 ++#define SRM_ISP_GROC_0__CROC_GC0 0x1F04018C,0x000007FF ++ ++#define SRM_ISP_GROC_1__ADDR 0x1F040190 ++#define SRM_ISP_GROC_1__EMPTY 0x1F040190,0x00000000 ++#define SRM_ISP_GROC_1__FULL 0x1F040190,0xffffffff ++#define SRM_ISP_GROC_1__CROC_GC3 0x1F040190,0x07FF0000 ++#define SRM_ISP_GROC_1__CROC_GC2 0x1F040190,0x000007FF ++ ++#define SRM_ISP_GROC_2__ADDR 0x1F040194 ++#define SRM_ISP_GROC_2__EMPTY 0x1F040194,0x00000000 ++#define SRM_ISP_GROC_2__FULL 0x1F040194,0xffffffff ++#define SRM_ISP_GROC_2__CROC_GC5 0x1F040194,0x07FF0000 ++#define SRM_ISP_GROC_2__CROC_GC4 0x1F040194,0x000007FF ++ ++#define SRM_ISP_GROC_3__ADDR 0x1F040198 ++#define SRM_ISP_GROC_3__EMPTY 0x1F040198,0x00000000 ++#define SRM_ISP_GROC_3__FULL 0x1F040198,0xffffffff ++#define SRM_ISP_GROC_3__CROC_GC7 0x1F040198,0x07FF0000 ++#define SRM_ISP_GROC_3__CROC_GC6 0x1F040198,0x000007FF ++ ++#define SRM_ISP_GROC_4__ADDR 0x1F04019C ++#define SRM_ISP_GROC_4__EMPTY 0x1F04019C,0x00000000 ++#define SRM_ISP_GROC_4__FULL 0x1F04019C,0xffffffff ++#define SRM_ISP_GROC_4__CROC_GC9 0x1F04019C,0x07FF0000 ++#define SRM_ISP_GROC_4__CROC_GC8 0x1F04019C,0x000007FF ++ ++#define SRM_ISP_GROC_5__ADDR 0x1F0401A0 ++#define SRM_ISP_GROC_5__EMPTY 0x1F0401A0,0x00000000 ++#define SRM_ISP_GROC_5__FULL 0x1F0401A0,0xffffffff ++#define SRM_ISP_GROC_5__CROC_GC11 0x1F0401A0,0x07FF0000 ++#define SRM_ISP_GROC_5__CROC_GC10 0x1F0401A0,0x000007FF ++ ++#define SRM_ISP_GROC_6__ADDR 0x1F0401A4 ++#define SRM_ISP_GROC_6__EMPTY 0x1F0401A4,0x00000000 ++#define SRM_ISP_GROC_6__FULL 0x1F0401A4,0xffffffff ++#define SRM_ISP_GROC_6__CROC_GC13 0x1F0401A4,0x07FF0000 ++#define SRM_ISP_GROC_6__CROC_GC12 0x1F0401A4,0x000007FF ++ ++#define SRM_ISP_GROC_7__ADDR 0x1F0401A8 ++#define SRM_ISP_GROC_7__EMPTY 0x1F0401A8,0x00000000 ++#define SRM_ISP_GROC_7__FULL 0x1F0401A8,0xffffffff ++#define SRM_ISP_GROC_7__CROC_GC15 0x1F0401A8,0x07FF0000 ++#define SRM_ISP_GROC_7__CROC_GC14 0x1F0401A8,0x000007FF ++ ++#define SRM_ISP_GROS_0__ADDR 0x1F0401AC ++#define SRM_ISP_GROS_0__EMPTY 0x1F0401AC,0x00000000 ++#define SRM_ISP_GROS_0__FULL 0x1F0401AC,0xffffffff ++#define SRM_ISP_GROS_0__CROC_GS3 0x1F0401AC,0x7F000000 ++#define SRM_ISP_GROS_0__CROC_GS2 0x1F0401AC,0x007F0000 ++#define SRM_ISP_GROS_0__CROC_GS1 0x1F0401AC,0x00007F00 ++#define SRM_ISP_GROS_0__CROC_GS0 0x1F0401AC,0x0000007F ++ ++#define SRM_ISP_GROS_1__ADDR 0x1F0401B0 ++#define SRM_ISP_GROS_1__EMPTY 0x1F0401B0,0x00000000 ++#define SRM_ISP_GROS_1__FULL 0x1F0401B0,0xffffffff ++#define SRM_ISP_GROS_1__CROC_GS7 0x1F0401B0,0x7F000000 ++#define SRM_ISP_GROS_1__CROC_GS6 0x1F0401B0,0x007F0000 ++#define SRM_ISP_GROS_1__CROC_GS5 0x1F0401B0,0x00007F00 ++#define SRM_ISP_GROS_1__CROC_GS4 0x1F0401B0,0x0000007F ++ ++#define SRM_ISP_GROS_2__ADDR 0x1F0401B4 ++#define SRM_ISP_GROS_2__EMPTY 0x1F0401B4,0x00000000 ++#define SRM_ISP_GROS_2__FULL 0x1F0401B4,0xffffffff ++#define SRM_ISP_GROS_2__CROC_GS11 0x1F0401B4,0x7F000000 ++#define SRM_ISP_GROS_2__CROC_GS10 0x1F0401B4,0x007F0000 ++#define SRM_ISP_GROS_2__CROC_GS9 0x1F0401B4,0x00007F00 ++#define SRM_ISP_GROS_2__CROC_GS8 0x1F0401B4,0x0000007F ++ ++#define SRM_ISP_GROS_3__ADDR 0x1F0401B8 ++#define SRM_ISP_GROS_3__EMPTY 0x1F0401B8,0x00000000 ++#define SRM_ISP_GROS_3__FULL 0x1F0401B8,0xffffffff ++#define SRM_ISP_GROS_3__CROC_GS15 0x1F0401B8,0x7F000000 ++#define SRM_ISP_GROS_3__CROC_GS14 0x1F0401B8,0x007F0000 ++#define SRM_ISP_GROS_3__CROC_GS13 0x1F0401B8,0x00007F00 ++#define SRM_ISP_GROS_3__CROC_GS12 0x1F0401B8,0x0000007F ++ ++#define SRM_ISP_BROC_0__ADDR 0x1F0401BC ++#define SRM_ISP_BROC_0__EMPTY 0x1F0401BC,0x00000000 ++#define SRM_ISP_BROC_0__FULL 0x1F0401BC,0xffffffff ++#define SRM_ISP_BROC_0__CROC_BC1 0x1F0401BC,0x07FF0000 ++#define SRM_ISP_BROC_0__CROC_BC0 0x1F0401BC,0x000007FF ++ ++#define SRM_ISP_BROC_1__ADDR 0x1F0401C0 ++#define SRM_ISP_BROC_1__EMPTY 0x1F0401C0,0x00000000 ++#define SRM_ISP_BROC_1__FULL 0x1F0401C0,0xffffffff ++#define SRM_ISP_BROC_1__CROC_BC3 0x1F0401C0,0x07FF0000 ++#define SRM_ISP_BROC_1__CROC_BC2 0x1F0401C0,0x000007FF ++ ++#define SRM_ISP_BROC_2__ADDR 0x1F0401C4 ++#define SRM_ISP_BROC_2__EMPTY 0x1F0401C4,0x00000000 ++#define SRM_ISP_BROC_2__FULL 0x1F0401C4,0xffffffff ++#define SRM_ISP_BROC_2__CROC_BC5 0x1F0401C4,0x07FF0000 ++#define SRM_ISP_BROC_2__CROC_BC4 0x1F0401C4,0x000007FF ++ ++#define SRM_ISP_BROC_3__ADDR 0x1F0401C8 ++#define SRM_ISP_BROC_3__EMPTY 0x1F0401C8,0x00000000 ++#define SRM_ISP_BROC_3__FULL 0x1F0401C8,0xffffffff ++#define SRM_ISP_BROC_3__CROC_BC7 0x1F0401C8,0x07FF0000 ++#define SRM_ISP_BROC_3__CROC_BC6 0x1F0401C8,0x000007FF ++ ++#define SRM_ISP_BROC_4__ADDR 0x1F0401CC ++#define SRM_ISP_BROC_4__EMPTY 0x1F0401CC,0x00000000 ++#define SRM_ISP_BROC_4__FULL 0x1F0401CC,0xffffffff ++#define SRM_ISP_BROC_4__CROC_BC9 0x1F0401CC,0x07FF0000 ++#define SRM_ISP_BROC_4__CROC_BC8 0x1F0401CC,0x000007FF ++ ++#define SRM_ISP_BROC_5__ADDR 0x1F0401D0 ++#define SRM_ISP_BROC_5__EMPTY 0x1F0401D0,0x00000000 ++#define SRM_ISP_BROC_5__FULL 0x1F0401D0,0xffffffff ++#define SRM_ISP_BROC_5__CROC_BC11 0x1F0401D0,0x07FF0000 ++#define SRM_ISP_BROC_5__CROC_BC10 0x1F0401D0,0x000007FF ++ ++#define SRM_ISP_BROC_6__ADDR 0x1F0401D4 ++#define SRM_ISP_BROC_6__EMPTY 0x1F0401D4,0x00000000 ++#define SRM_ISP_BROC_6__FULL 0x1F0401D4,0xffffffff ++#define SRM_ISP_BROC_6__CROC_BC13 0x1F0401D4,0x07FF0000 ++#define SRM_ISP_BROC_6__CROC_BC12 0x1F0401D4,0x000007FF ++ ++#define SRM_ISP_BROC_7__ADDR 0x1F0401D8 ++#define SRM_ISP_BROC_7__EMPTY 0x1F0401D8,0x00000000 ++#define SRM_ISP_BROC_7__FULL 0x1F0401D8,0xffffffff ++#define SRM_ISP_BROC_7__CROC_BC15 0x1F0401D8,0x07FF0000 ++#define SRM_ISP_BROC_7__CROC_BC14 0x1F0401D8,0x000007FF ++ ++#define SRM_ISP_BROS_0__ADDR 0x1F0401DC ++#define SRM_ISP_BROS_0__EMPTY 0x1F0401DC,0x00000000 ++#define SRM_ISP_BROS_0__FULL 0x1F0401DC,0xffffffff ++#define SRM_ISP_BROS_0__CROC_BS3 0x1F0401DC,0x7F000000 ++#define SRM_ISP_BROS_0__CROC_BS2 0x1F0401DC,0x007F0000 ++#define SRM_ISP_BROS_0__CROC_BS1 0x1F0401DC,0x00007F00 ++#define SRM_ISP_BROS_0__CROC_BS0 0x1F0401DC,0x0000007F ++ ++#define SRM_ISP_BROS_1__ADDR 0x1F0401E0 ++#define SRM_ISP_BROS_1__EMPTY 0x1F0401E0,0x00000000 ++#define SRM_ISP_BROS_1__FULL 0x1F0401E0,0xffffffff ++#define SRM_ISP_BROS_1__CROC_BS7 0x1F0401E0,0x7F000000 ++#define SRM_ISP_BROS_1__CROC_BS6 0x1F0401E0,0x007F0000 ++#define SRM_ISP_BROS_1__CROC_BS5 0x1F0401E0,0x00007F00 ++#define SRM_ISP_BROS_1__CROC_BS4 0x1F0401E0,0x0000007F ++ ++#define SRM_ISP_BROS_2__ADDR 0x1F0401E4 ++#define SRM_ISP_BROS_2__EMPTY 0x1F0401E4,0x00000000 ++#define SRM_ISP_BROS_2__FULL 0x1F0401E4,0xffffffff ++#define SRM_ISP_BROS_2__CROC_BS11 0x1F0401E4,0x7F000000 ++#define SRM_ISP_BROS_2__CROC_BS10 0x1F0401E4,0x007F0000 ++#define SRM_ISP_BROS_2__CROC_BS9 0x1F0401E4,0x00007F00 ++#define SRM_ISP_BROS_2__CROC_BS8 0x1F0401E4,0x0000007F ++ ++#define SRM_ISP_BROS_3__ADDR 0x1F0401E8 ++#define SRM_ISP_BROS_3__EMPTY 0x1F0401E8,0x00000000 ++#define SRM_ISP_BROS_3__FULL 0x1F0401E8,0xffffffff ++#define SRM_ISP_BROS_3__CROC_BS15 0x1F0401E8,0x7F000000 ++#define SRM_ISP_BROS_3__CROC_BS14 0x1F0401E8,0x007F0000 ++#define SRM_ISP_BROS_3__CROC_BS13 0x1F0401E8,0x00007F00 ++#define SRM_ISP_BROS_3__CROC_BS12 0x1F0401E8,0x0000007F ++ ++#define SRM_ISP_GAMMA_C_0__ADDR 0x1F0401EC ++#define SRM_ISP_GAMMA_C_0__EMPTY 0x1F0401EC,0x00000000 ++#define SRM_ISP_GAMMA_C_0__FULL 0x1F0401EC,0xffffffff ++#define SRM_ISP_GAMMA_C_0__GAMMA_C1 0x1F0401EC,0x01FF0000 ++#define SRM_ISP_GAMMA_C_0__GAMMA_C0 0x1F0401EC,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_1__ADDR 0x1F0401F0 ++#define SRM_ISP_GAMMA_C_1__EMPTY 0x1F0401F0,0x00000000 ++#define SRM_ISP_GAMMA_C_1__FULL 0x1F0401F0,0xffffffff ++#define SRM_ISP_GAMMA_C_1__GAMMA_C3 0x1F0401F0,0x01FF0000 ++#define SRM_ISP_GAMMA_C_1__GAMMA_C2 0x1F0401F0,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_2__ADDR 0x1F0401F4 ++#define SRM_ISP_GAMMA_C_2__EMPTY 0x1F0401F4,0x00000000 ++#define SRM_ISP_GAMMA_C_2__FULL 0x1F0401F4,0xffffffff ++#define SRM_ISP_GAMMA_C_2__GAMMA_C5 0x1F0401F4,0x01FF0000 ++#define SRM_ISP_GAMMA_C_2__GAMMA_C4 0x1F0401F4,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_3__ADDR 0x1F0401F8 ++#define SRM_ISP_GAMMA_C_3__EMPTY 0x1F0401F8,0x00000000 ++#define SRM_ISP_GAMMA_C_3__FULL 0x1F0401F8,0xffffffff ++#define SRM_ISP_GAMMA_C_3__GAMMA_C7 0x1F0401F8,0x01FF0000 ++#define SRM_ISP_GAMMA_C_3__GAMMA_C6 0x1F0401F8,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_4__ADDR 0x1F0401FC ++#define SRM_ISP_GAMMA_C_4__EMPTY 0x1F0401FC,0x00000000 ++#define SRM_ISP_GAMMA_C_4__FULL 0x1F0401FC,0xffffffff ++#define SRM_ISP_GAMMA_C_4__GAMMA_C9 0x1F0401FC,0x01FF0000 ++#define SRM_ISP_GAMMA_C_4__GAMMA_C8 0x1F0401FC,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_5__ADDR 0x1F040200 ++#define SRM_ISP_GAMMA_C_5__EMPTY 0x1F040200,0x00000000 ++#define SRM_ISP_GAMMA_C_5__FULL 0x1F040200,0xffffffff ++#define SRM_ISP_GAMMA_C_5__GAMMA_C11 0x1F040200,0x01FF0000 ++#define SRM_ISP_GAMMA_C_5__GAMMA_C10 0x1F040200,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_6__ADDR 0x1F040204 ++#define SRM_ISP_GAMMA_C_6__EMPTY 0x1F040204,0x00000000 ++#define SRM_ISP_GAMMA_C_6__FULL 0x1F040204,0xffffffff ++#define SRM_ISP_GAMMA_C_6__GAMMA_C13 0x1F040204,0x01FF0000 ++#define SRM_ISP_GAMMA_C_6__GAMMA_C12 0x1F040204,0x000001FF ++ ++#define SRM_ISP_GAMMA_C_7__ADDR 0x1F040208 ++#define SRM_ISP_GAMMA_C_7__EMPTY 0x1F040208,0x00000000 ++#define SRM_ISP_GAMMA_C_7__FULL 0x1F040208,0xffffffff ++#define SRM_ISP_GAMMA_C_7__GAMMA_C15 0x1F040208,0x01FF0000 ++#define SRM_ISP_GAMMA_C_7__GAMMA_C14 0x1F040208,0x000001FF ++ ++#define SRM_ISP_GAMMA_S_0__ADDR 0x1F04020C ++#define SRM_ISP_GAMMA_S_0__EMPTY 0x1F04020C,0x00000000 ++#define SRM_ISP_GAMMA_S_0__FULL 0x1F04020C,0xffffffff ++#define SRM_ISP_GAMMA_S_0__GAMMA_S3 0x1F04020C,0xFF000000 ++#define SRM_ISP_GAMMA_S_0__GAMMA_S2 0x1F04020C,0x00FF0000 ++#define SRM_ISP_GAMMA_S_0__GAMMA_S1 0x1F04020C,0x0000FF00 ++#define SRM_ISP_GAMMA_S_0__GAMMA_S0 0x1F04020C,0x000000FF ++ ++#define SRM_ISP_GAMMA_S_1__ADDR 0x1F040210 ++#define SRM_ISP_GAMMA_S_1__EMPTY 0x1F040210,0x00000000 ++#define SRM_ISP_GAMMA_S_1__FULL 0x1F040210,0xffffffff ++#define SRM_ISP_GAMMA_S_1__GAMMA_S7 0x1F040210,0xFF000000 ++#define SRM_ISP_GAMMA_S_1__GAMMA_S6 0x1F040210,0x00FF0000 ++#define SRM_ISP_GAMMA_S_1__GAMMA_S5 0x1F040210,0x0000FF00 ++#define SRM_ISP_GAMMA_S_1__GAMMA_S4 0x1F040210,0x000000FF ++ ++#define SRM_ISP_GAMMA_S_2__ADDR 0x1F040214 ++#define SRM_ISP_GAMMA_S_2__EMPTY 0x1F040214,0x00000000 ++#define SRM_ISP_GAMMA_S_2__FULL 0x1F040214,0xffffffff ++#define SRM_ISP_GAMMA_S_2__GAMMA_S11 0x1F040214,0xFF000000 ++#define SRM_ISP_GAMMA_S_2__GAMMA_S10 0x1F040214,0x00FF0000 ++#define SRM_ISP_GAMMA_S_2__GAMMA_S9 0x1F040214,0x0000FF00 ++#define SRM_ISP_GAMMA_S_2__GAMMA_S8 0x1F040214,0x000000FF ++ ++#define SRM_ISP_GAMMA_S_3__ADDR 0x1F040218 ++#define SRM_ISP_GAMMA_S_3__EMPTY 0x1F040218,0x00000000 ++#define SRM_ISP_GAMMA_S_3__FULL 0x1F040218,0xffffffff ++#define SRM_ISP_GAMMA_S_3__GAMMA_S15 0x1F040218,0xFF000000 ++#define SRM_ISP_GAMMA_S_3__GAMMA_S14 0x1F040218,0x00FF0000 ++#define SRM_ISP_GAMMA_S_3__GAMMA_S13 0x1F040218,0x0000FF00 ++#define SRM_ISP_GAMMA_S_3__GAMMA_S12 0x1F040218,0x000000FF ++ ++#define SRM_ISP_CSCA_0__ADDR 0x1F04021C ++#define SRM_ISP_CSCA_0__EMPTY 0x1F04021C,0x00000000 ++#define SRM_ISP_CSCA_0__FULL 0x1F04021C,0xffffffff ++#define SRM_ISP_CSCA_0__CSC_A1 0x1F04021C,0x03FF0000 ++#define SRM_ISP_CSCA_0__CSC_A0 0x1F04021C,0x000003FF ++ ++#define SRM_ISP_CSCA_1__ADDR 0x1F040220 ++#define SRM_ISP_CSCA_1__EMPTY 0x1F040220,0x00000000 ++#define SRM_ISP_CSCA_1__FULL 0x1F040220,0xffffffff ++#define SRM_ISP_CSCA_1__CSC_A3 0x1F040220,0x03FF0000 ++#define SRM_ISP_CSCA_1__CSC_A2 0x1F040220,0x000003FF ++ ++#define SRM_ISP_CSCA_2__ADDR 0x1F040224 ++#define SRM_ISP_CSCA_2__EMPTY 0x1F040224,0x00000000 ++#define SRM_ISP_CSCA_2__FULL 0x1F040224,0xffffffff ++#define SRM_ISP_CSCA_2__CSC_A5 0x1F040224,0x03FF0000 ++#define SRM_ISP_CSCA_2__CSC_A4 0x1F040224,0x000003FF ++ ++#define SRM_ISP_CSCA_3__ADDR 0x1F040228 ++#define SRM_ISP_CSCA_3__EMPTY 0x1F040228,0x00000000 ++#define SRM_ISP_CSCA_3__FULL 0x1F040228,0xffffffff ++#define SRM_ISP_CSCA_3__CSC_A7 0x1F040228,0x03FF0000 ++#define SRM_ISP_CSCA_3__CSC_A6 0x1F040228,0x000003FF ++ ++#define SRM_ISP_CSC_0__ADDR 0x1F04022C ++#define SRM_ISP_CSC_0__EMPTY 0x1F04022C,0x00000000 ++#define SRM_ISP_CSC_0__FULL 0x1F04022C,0xffffffff ++#define SRM_ISP_CSC_0__CSC_S0 0x1F04022C,0xC0000000 ++#define SRM_ISP_CSC_0__CSC_B0 0x1F04022C,0x3FFF0000 ++#define SRM_ISP_CSC_0__CSC_A8 0x1F04022C,0x000003FF ++ ++#define SRM_ISP_CSC_1__ADDR 0x1F040230 ++#define SRM_ISP_CSC_1__EMPTY 0x1F040230,0x00000000 ++#define SRM_ISP_CSC_1__FULL 0x1F040230,0xffffffff ++#define SRM_ISP_CSC_1__CSC_S2 0x1F040230,0xC0000000 ++#define SRM_ISP_CSC_1__CSC_B2 0x1F040230,0x3FFF0000 ++#define SRM_ISP_CSC_1__CSC_S1 0x1F040230,0x0000C000 ++#define SRM_ISP_CSC_1__CSC_B1 0x1F040230,0x00003FFF ++ ++#define SRM_ISP_CNS_C_0__ADDR 0x1F040234 ++#define SRM_ISP_CNS_C_0__EMPTY 0x1F040234,0x00000000 ++#define SRM_ISP_CNS_C_0__FULL 0x1F040234,0xffffffff ++#define SRM_ISP_CNS_C_0__CNS_C1 0x1F040234,0x01FF0000 ++#define SRM_ISP_CNS_C_0__CNS_C0 0x1F040234,0x000001FF ++ ++#define SRM_ISP_CNS_C_1__ADDR 0x1F040238 ++#define SRM_ISP_CNS_C_1__EMPTY 0x1F040238,0x00000000 ++#define SRM_ISP_CNS_C_1__FULL 0x1F040238,0xffffffff ++#define SRM_ISP_CNS_C_1__CNS_C3 0x1F040238,0x01FF0000 ++#define SRM_ISP_CNS_C_1__CNS_C2 0x1F040238,0x000001FF ++ ++#define SRM_ISP_CNS_C_2__ADDR 0x1F04023C ++#define SRM_ISP_CNS_C_2__EMPTY 0x1F04023C,0x00000000 ++#define SRM_ISP_CNS_C_2__FULL 0x1F04023C,0xffffffff ++#define SRM_ISP_CNS_C_2__CNS_C5 0x1F04023C,0x01FF0000 ++#define SRM_ISP_CNS_C_2__CNS_C4 0x1F04023C,0x000001FF ++ ++#define SRM_ISP_CNS_C_3__ADDR 0x1F040240 ++#define SRM_ISP_CNS_C_3__EMPTY 0x1F040240,0x00000000 ++#define SRM_ISP_CNS_C_3__FULL 0x1F040240,0xffffffff ++#define SRM_ISP_CNS_C_3__CNS_C7 0x1F040240,0x01FF0000 ++#define SRM_ISP_CNS_C_3__CNS_C6 0x1F040240,0x000001FF ++ ++#define SRM_ISP_CNS_C_4__ADDR 0x1F040244 ++#define SRM_ISP_CNS_C_4__EMPTY 0x1F040244,0x00000000 ++#define SRM_ISP_CNS_C_4__FULL 0x1F040244,0xffffffff ++#define SRM_ISP_CNS_C_4__CNS_C9 0x1F040244,0x01FF0000 ++#define SRM_ISP_CNS_C_4__CNS_C8 0x1F040244,0x000001FF ++ ++#define SRM_ISP_CNS_C_5__ADDR 0x1F040248 ++#define SRM_ISP_CNS_C_5__EMPTY 0x1F040248,0x00000000 ++#define SRM_ISP_CNS_C_5__FULL 0x1F040248,0xffffffff ++#define SRM_ISP_CNS_C_5__CNS_C11 0x1F040248,0x01FF0000 ++#define SRM_ISP_CNS_C_5__CNS_C10 0x1F040248,0x000001FF ++ ++#define SRM_ISP_CNS_C_6__ADDR 0x1F04024C ++#define SRM_ISP_CNS_C_6__EMPTY 0x1F04024C,0x00000000 ++#define SRM_ISP_CNS_C_6__FULL 0x1F04024C,0xffffffff ++#define SRM_ISP_CNS_C_6__CNS_C13 0x1F04024C,0x01FF0000 ++#define SRM_ISP_CNS_C_6__CNS_C12 0x1F04024C,0x000001FF ++ ++#define SRM_ISP_CNS_C_7__ADDR 0x1F040250 ++#define SRM_ISP_CNS_C_7__EMPTY 0x1F040250,0x00000000 ++#define SRM_ISP_CNS_C_7__FULL 0x1F040250,0xffffffff ++#define SRM_ISP_CNS_C_7__CNS_C15 0x1F040250,0x01FF0000 ++#define SRM_ISP_CNS_C_7__CNS_C14 0x1F040250,0x000001FF ++ ++#define SRM_ISP_CNS_S_0__ADDR 0x1F040254 ++#define SRM_ISP_CNS_S_0__EMPTY 0x1F040254,0x00000000 ++#define SRM_ISP_CNS_S_0__FULL 0x1F040254,0xffffffff ++#define SRM_ISP_CNS_S_0__CNS_S3 0x1F040254,0xFF000000 ++#define SRM_ISP_CNS_S_0__CNS_S2 0x1F040254,0x00FF0000 ++#define SRM_ISP_CNS_S_0__CNS_S1 0x1F040254,0x0000FF00 ++#define SRM_ISP_CNS_S_0__CNS_S0 0x1F040254,0x000000FF ++ ++#define SRM_ISP_CNS_S_1__ADDR 0x1F040258 ++#define SRM_ISP_CNS_S_1__EMPTY 0x1F040258,0x00000000 ++#define SRM_ISP_CNS_S_1__FULL 0x1F040258,0xffffffff ++#define SRM_ISP_CNS_S_1__CNS_S7 0x1F040258,0xFF000000 ++#define SRM_ISP_CNS_S_1__CNS_S6 0x1F040258,0x00FF0000 ++#define SRM_ISP_CNS_S_1__CNS_S5 0x1F040258,0x0000FF00 ++#define SRM_ISP_CNS_S_1__CNS_S4 0x1F040258,0x000000FF ++ ++#define SRM_ISP_CNS_S_2__ADDR 0x1F04025C ++#define SRM_ISP_CNS_S_2__EMPTY 0x1F04025C,0x00000000 ++#define SRM_ISP_CNS_S_2__FULL 0x1F04025C,0xffffffff ++#define SRM_ISP_CNS_S_2__CNS_S11 0x1F04025C,0xFF000000 ++#define SRM_ISP_CNS_S_2__CNS_S10 0x1F04025C,0x00FF0000 ++#define SRM_ISP_CNS_S_2__CNS_S9 0x1F04025C,0x0000FF00 ++#define SRM_ISP_CNS_S_2__CNS_S8 0x1F04025C,0x000000FF ++ ++#define SRM_ISP_CNS_S_3__ADDR 0x1F040260 ++#define SRM_ISP_CNS_S_3__EMPTY 0x1F040260,0x00000000 ++#define SRM_ISP_CNS_S_3__FULL 0x1F040260,0xffffffff ++#define SRM_ISP_CNS_S_3__CNS_S15 0x1F040260,0xFF000000 ++#define SRM_ISP_CNS_S_3__CNS_S14 0x1F040260,0x00FF0000 ++#define SRM_ISP_CNS_S_3__CNS_S13 0x1F040260,0x0000FF00 ++#define SRM_ISP_CNS_S_3__CNS_S12 0x1F040260,0x000000FF ++ ++#define SRM_ISP_MTF_ROC_C_0__ADDR 0x1F040264 ++#define SRM_ISP_MTF_ROC_C_0__EMPTY 0x1F040264,0x00000000 ++#define SRM_ISP_MTF_ROC_C_0__FULL 0x1F040264,0xffffffff ++#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C1 0x1F040264,0x01FF0000 ++#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C0 0x1F040264,0x000001FF ++ ++#define SRM_ISP_MTF_ROC_C_1__ADDR 0x1F040268 ++#define SRM_ISP_MTF_ROC_C_1__EMPTY 0x1F040268,0x00000000 ++#define SRM_ISP_MTF_ROC_C_1__FULL 0x1F040268,0xffffffff ++#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C3 0x1F040268,0x01FF0000 ++#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C2 0x1F040268,0x000001FF ++ ++#define SRM_ISP_MTF_ROC_C_2__ADDR 0x1F04026C ++#define SRM_ISP_MTF_ROC_C_2__EMPTY 0x1F04026C,0x00000000 ++#define SRM_ISP_MTF_ROC_C_2__FULL 0x1F04026C,0xffffffff ++#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C5 0x1F04026C,0x01FF0000 ++#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C4 0x1F04026C,0x000001FF ++ ++#define SRM_ISP_MTF_ROC_C_3__ADDR 0x1F040270 ++#define SRM_ISP_MTF_ROC_C_3__EMPTY 0x1F040270,0x00000000 ++#define SRM_ISP_MTF_ROC_C_3__FULL 0x1F040270,0xffffffff ++#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C7 0x1F040270,0x01FF0000 ++#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C6 0x1F040270,0x000001FF ++ ++#define SRM_ISP_MTF_ROC_S_0__ADDR 0x1F040274 ++#define SRM_ISP_MTF_ROC_S_0__EMPTY 0x1F040274,0x00000000 ++#define SRM_ISP_MTF_ROC_S_0__FULL 0x1F040274,0xffffffff ++#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S3 0x1F040274,0xFF000000 ++#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S2 0x1F040274,0x00FF0000 ++#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S1 0x1F040274,0x0000FF00 ++#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S0 0x1F040274,0x000000FF ++ ++#define SRM_ISP_MTF_ROC_S_1__ADDR 0x1F040278 ++#define SRM_ISP_MTF_ROC_S_1__EMPTY 0x1F040278,0x00000000 ++#define SRM_ISP_MTF_ROC_S_1__FULL 0x1F040278,0xffffffff ++#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S7 0x1F040278,0xFF000000 ++#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S6 0x1F040278,0x00FF0000 ++#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S5 0x1F040278,0x0000FF00 ++#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S4 0x1F040278,0x000000FF ++ ++#define SRM_ISP_HFE_0__ADDR 0x1F04027C ++#define SRM_ISP_HFE_0__EMPTY 0x1F04027C,0x00000000 ++#define SRM_ISP_HFE_0__FULL 0x1F04027C,0xffffffff ++#define SRM_ISP_HFE_0__HFE_LUT5 0x1F04027C,0x7C000000 ++#define SRM_ISP_HFE_0__HFE_LUT4 0x1F04027C,0x03E00000 ++#define SRM_ISP_HFE_0__HFE_LUT3 0x1F04027C,0x001F0000 ++#define SRM_ISP_HFE_0__HFE_LUT2 0x1F04027C,0x00007C00 ++#define SRM_ISP_HFE_0__HFE_LUT1 0x1F04027C,0x000003E0 ++#define SRM_ISP_HFE_0__HFE_LUT0 0x1F04027C,0x0000001F ++ ++#define SRM_ISP_HFE_1__ADDR 0x1F040280 ++#define SRM_ISP_HFE_1__EMPTY 0x1F040280,0x00000000 ++#define SRM_ISP_HFE_1__FULL 0x1F040280,0xffffffff ++#define SRM_ISP_HFE_1__HFE_LUT11 0x1F040280,0x7C000000 ++#define SRM_ISP_HFE_1__HFE_LUT10 0x1F040280,0x03E00000 ++#define SRM_ISP_HFE_1__HFE_LUT9 0x1F040280,0x001F0000 ++#define SRM_ISP_HFE_1__HFE_LUT8 0x1F040280,0x00007C00 ++#define SRM_ISP_HFE_1__HFE_LUT7 0x1F040280,0x000003E0 ++#define SRM_ISP_HFE_1__HFE_LUT6 0x1F040280,0x0000001F ++ ++#define SRM_ISP_HFE_2__ADDR 0x1F040284 ++#define SRM_ISP_HFE_2__EMPTY 0x1F040284,0x00000000 ++#define SRM_ISP_HFE_2__FULL 0x1F040284,0xffffffff ++#define SRM_ISP_HFE_2__HFE_LUT15 0x1F040284,0x001F0000 ++#define SRM_ISP_HFE_2__HFE_LUT14 0x1F040284,0x00007C00 ++#define SRM_ISP_HFE_2__HFE_LUT13 0x1F040284,0x000003E0 ++#define SRM_ISP_HFE_2__HFE_LUT12 0x1F040284,0x0000001F ++ ++#define SRM_ISP_HFE_S_0__ADDR 0x1F040288 ++#define SRM_ISP_HFE_S_0__EMPTY 0x1F040288,0x00000000 ++#define SRM_ISP_HFE_S_0__FULL 0x1F040288,0xffffffff ++#define SRM_ISP_HFE_S_0__HFE_S1 0x1F040288,0x01FF0000 ++#define SRM_ISP_HFE_S_0__HFE_S0 0x1F040288,0x000001FF ++ ++#define SRM_ISP_HFE_S_1__ADDR 0x1F04028C ++#define SRM_ISP_HFE_S_1__EMPTY 0x1F04028C,0x00000000 ++#define SRM_ISP_HFE_S_1__FULL 0x1F04028C,0xffffffff ++#define SRM_ISP_HFE_S_1__HFE_S3 0x1F04028C,0x01FF0000 ++#define SRM_ISP_HFE_S_1__HFE_S2 0x1F04028C,0x000001FF ++ ++#define SRM_ISP_HFE_S_2__ADDR 0x1F040290 ++#define SRM_ISP_HFE_S_2__EMPTY 0x1F040290,0x00000000 ++#define SRM_ISP_HFE_S_2__FULL 0x1F040290,0xffffffff ++#define SRM_ISP_HFE_S_2__HFE_S5 0x1F040290,0x01FF0000 ++#define SRM_ISP_HFE_S_2__HFE_S4 0x1F040290,0x000001FF ++ ++#define SRM_ISP_HFE_S_3__ADDR 0x1F040294 ++#define SRM_ISP_HFE_S_3__EMPTY 0x1F040294,0x00000000 ++#define SRM_ISP_HFE_S_3__FULL 0x1F040294,0xffffffff ++#define SRM_ISP_HFE_S_3__HFE_S7 0x1F040294,0x01FF0000 ++#define SRM_ISP_HFE_S_3__HFE_S6 0x1F040294,0x000001FF ++ ++#define SRM_ISP_HFE_C_0__ADDR 0x1F040298 ++#define SRM_ISP_HFE_C_0__EMPTY 0x1F040298,0x00000000 ++#define SRM_ISP_HFE_C_0__FULL 0x1F040298,0xffffffff ++#define SRM_ISP_HFE_C_0__HFE_C1 0x1F040298,0x01FF0000 ++#define SRM_ISP_HFE_C_0__HFE_C0 0x1F040298,0x000001FF ++ ++#define SRM_ISP_HFE_C_1__ADDR 0x1F04029C ++#define SRM_ISP_HFE_C_1__EMPTY 0x1F04029C,0x00000000 ++#define SRM_ISP_HFE_C_1__FULL 0x1F04029C,0xffffffff ++#define SRM_ISP_HFE_C_1__HFE_C3 0x1F04029C,0x01FF0000 ++#define SRM_ISP_HFE_C_1__HFE_C2 0x1F04029C,0x000001FF ++ ++#define SRM_ISP_HFE_C_2__ADDR 0x1F0402A0 ++#define SRM_ISP_HFE_C_2__EMPTY 0x1F0402A0,0x00000000 ++#define SRM_ISP_HFE_C_2__FULL 0x1F0402A0,0xffffffff ++#define SRM_ISP_HFE_C_2__HFE_C5 0x1F0402A0,0x01FF0000 ++#define SRM_ISP_HFE_C_2__HFE_C4 0x1F0402A0,0x000001FF ++ ++#define SRM_ISP_HFE_C_3__ADDR 0x1F0402A4 ++#define SRM_ISP_HFE_C_3__EMPTY 0x1F0402A4,0x00000000 ++#define SRM_ISP_HFE_C_3__FULL 0x1F0402A4,0xffffffff ++#define SRM_ISP_HFE_C_3__HFE_C7 0x1F0402A4,0x01FF0000 ++#define SRM_ISP_HFE_C_3__HFE_C6 0x1F0402A4,0x000001FF ++ ++#define SRM_ISP_STC_0__ADDR 0x1F0402A8 ++#define SRM_ISP_STC_0__EMPTY 0x1F0402A8,0x00000000 ++#define SRM_ISP_STC_0__FULL 0x1F0402A8,0xffffffff ++#define SRM_ISP_STC_0__VNMBR_BLKS 0x1F0402A8,0x03E00000 ++#define SRM_ISP_STC_0__HNMBR_BLKS 0x1F0402A8,0x001F0000 ++#define SRM_ISP_STC_0__PIX_SKIP 0x1F0402A8,0x00006000 ++#define SRM_ISP_STC_0__VBLK_EXP 0x1F0402A8,0x00001C00 ++#define SRM_ISP_STC_0__VBLK_MNTS 0x1F0402A8,0x00000300 ++#define SRM_ISP_STC_0__HBLK_EXP 0x1F0402A8,0x000000E0 ++#define SRM_ISP_STC_0__HBLK_MNTS 0x1F0402A8,0x00000018 ++#define SRM_ISP_STC_0__Y_HT_EN 0x1F0402A8,0x00000004 ++#define SRM_ISP_STC_0__RAW_HT_EN 0x1F0402A8,0x00000002 ++#define SRM_ISP_STC_0__ST_EN 0x1F0402A8,0x00000001 ++ ++#define SRM_ISP_STC_1__ADDR 0x1F0402AC ++#define SRM_ISP_STC_1__EMPTY 0x1F0402AC,0x00000000 ++#define SRM_ISP_STC_1__FULL 0x1F0402AC,0xffffffff ++#define SRM_ISP_STC_1__TOP_SKIP 0x1F0402AC,0x07FF0000 ++#define SRM_ISP_STC_1__LEFT_SKIP 0x1F0402AC,0x000007FF ++ ++#define SRM_ISP_FC_0__ADDR 0x1F0402B0 ++#define SRM_ISP_FC_0__EMPTY 0x1F0402B0,0x00000000 ++#define SRM_ISP_FC_0__FULL 0x1F0402B0,0xffffffff ++#define SRM_ISP_FC_0__FL_LAST_PHASE 0x1F0402B0,0x00007FE0 ++#define SRM_ISP_FC_0__FL_SHIFT 0x1F0402B0,0x0000001F ++ ++#define SRM_ISP_FC_1__ADDR 0x1F0402B4 ++#define SRM_ISP_FC_1__EMPTY 0x1F0402B4,0x00000000 ++#define SRM_ISP_FC_1__FULL 0x1F0402B4,0xffffffff ++#define SRM_ISP_FC_1__FL_PHASE 0x1F0402B4,0x000FFFFF ++ ++#define SRM_ISP_DC1__ADDR 0x1F0402B8 ++#define SRM_ISP_DC1__EMPTY 0x1F0402B8,0x00000000 ++#define SRM_ISP_DC1__FULL 0x1F0402B8,0xffffffff ++#define SRM_ISP_DC1__SMOOTH 0x1F0402B8,0x7C000000 ++#define SRM_ISP_DC1__NOSTEP 0x1F0402B8,0x03E00000 ++#define SRM_ISP_DC1__NOLINE 0x1F0402B8,0x001F0000 ++#define SRM_ISP_DC1__BOTHSTEP 0x1F0402B8,0x00003800 ++#define SRM_ISP_DC1__LNSHIFTN 0x1F0402B8,0x00000600 ++#define SRM_ISP_DC1__LNSHIFTM 0x1F0402B8,0x00000180 ++#define SRM_ISP_DC1__NOLINEINSTEP 0x1F0402B8,0x0000007C ++#define SRM_ISP_DC1__ALIASSHIFT 0x1F0402B8,0x00000003 ++ ++#define SRM_ISP_DC2__ADDR 0x1F0402BC ++#define SRM_ISP_DC2__EMPTY 0x1F0402BC,0x00000000 ++#define SRM_ISP_DC2__FULL 0x1F0402BC,0xffffffff ++#define SRM_ISP_DC2__NOSTEPNOISE 0x1F0402BC,0x03E00000 ++#define SRM_ISP_DC2__NOLINENOISE 0x1F0402BC,0x001F0000 ++#define SRM_ISP_DC2__ACT 0x1F0402BC,0x00007C00 ++#define SRM_ISP_DC2__MSMOOTH 0x1F0402BC,0x00000180 ++#define SRM_ISP_DC2__MBRIGHT 0x1F0402BC,0x00000060 ++#define SRM_ISP_DC2__BRIGHT 0x1F0402BC,0x0000001F ++ ++#define SRM_ISP_DC3__ADDR 0x1F0402C0 ++#define SRM_ISP_DC3__EMPTY 0x1F0402C0,0x00000000 ++#define SRM_ISP_DC3__FULL 0x1F0402C0,0xffffffff ++#define SRM_ISP_DC3__NORIMNOISE 0x1F0402C0,0x000003FF ++ ++#define SRM_CSI0_CPD_CTRL__ADDR 0x1F0402C4 ++#define SRM_CSI0_CPD_CTRL__EMPTY 0x1F0402C4,0x00000000 ++#define SRM_CSI0_CPD_CTRL__FULL 0x1F0402C4,0xffffffff ++#define SRM_CSI0_CPD_CTRL__CSI0_CPD 0x1F0402C4,0x0000001C ++#define SRM_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN 0x1F0402C4,0x00000002 ++#define SRM_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN 0x1F0402C4,0x00000001 ++ ++#define SRM_CSI0_CPD_RC_0__ADDR 0x1F0402C8 ++#define SRM_CSI0_CPD_RC_0__EMPTY 0x1F0402C8,0x00000000 ++#define SRM_CSI0_CPD_RC_0__FULL 0x1F0402C8,0xffffffff ++#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_1 0x1F0402C8,0x01FF0000 ++#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_0 0x1F0402C8,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_1__ADDR 0x1F0402CC ++#define SRM_CSI0_CPD_RC_1__EMPTY 0x1F0402CC,0x00000000 ++#define SRM_CSI0_CPD_RC_1__FULL 0x1F0402CC,0xffffffff ++#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_3 0x1F0402CC,0x01FF0000 ++#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_2 0x1F0402CC,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_2__ADDR 0x1F0402D0 ++#define SRM_CSI0_CPD_RC_2__EMPTY 0x1F0402D0,0x00000000 ++#define SRM_CSI0_CPD_RC_2__FULL 0x1F0402D0,0xffffffff ++#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_5 0x1F0402D0,0x01FF0000 ++#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_4 0x1F0402D0,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_3__ADDR 0x1F0402D4 ++#define SRM_CSI0_CPD_RC_3__EMPTY 0x1F0402D4,0x00000000 ++#define SRM_CSI0_CPD_RC_3__FULL 0x1F0402D4,0xffffffff ++#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_7 0x1F0402D4,0x01FF0000 ++#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_6 0x1F0402D4,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_4__ADDR 0x1F0402D8 ++#define SRM_CSI0_CPD_RC_4__EMPTY 0x1F0402D8,0x00000000 ++#define SRM_CSI0_CPD_RC_4__FULL 0x1F0402D8,0xffffffff ++#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_9 0x1F0402D8,0x01FF0000 ++#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_8 0x1F0402D8,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_5__ADDR 0x1F0402DC ++#define SRM_CSI0_CPD_RC_5__EMPTY 0x1F0402DC,0x00000000 ++#define SRM_CSI0_CPD_RC_5__FULL 0x1F0402DC,0xffffffff ++#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_11 0x1F0402DC,0x01FF0000 ++#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_10 0x1F0402DC,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_6__ADDR 0x1F0402E0 ++#define SRM_CSI0_CPD_RC_6__EMPTY 0x1F0402E0,0x00000000 ++#define SRM_CSI0_CPD_RC_6__FULL 0x1F0402E0,0xffffffff ++#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_13 0x1F0402E0,0x01FF0000 ++#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_12 0x1F0402E0,0x000001FF ++ ++#define SRM_CSI0_CPD_RC_7__ADDR 0x1F0402E4 ++#define SRM_CSI0_CPD_RC_7__EMPTY 0x1F0402E4,0x00000000 ++#define SRM_CSI0_CPD_RC_7__FULL 0x1F0402E4,0xffffffff ++#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_15 0x1F0402E4,0x01FF0000 ++#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_14 0x1F0402E4,0x000001FF ++ ++#define SRM_CSI0_CPD_RS_0__ADDR 0x1F0402E8 ++#define SRM_CSI0_CPD_RS_0__EMPTY 0x1F0402E8,0x00000000 ++#define SRM_CSI0_CPD_RS_0__FULL 0x1F0402E8,0xffffffff ++#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS3 0x1F0402E8,0xFF000000 ++#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS2 0x1F0402E8,0x00FF0000 ++#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS1 0x1F0402E8,0x0000FF00 ++#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS0 0x1F0402E8,0x000000FF ++ ++#define SRM_CSI0_CPD_RS_1__ADDR 0x1F0402EC ++#define SRM_CSI0_CPD_RS_1__EMPTY 0x1F0402EC,0x00000000 ++#define SRM_CSI0_CPD_RS_1__FULL 0x1F0402EC,0xffffffff ++#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS7 0x1F0402EC,0xFF000000 ++#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS6 0x1F0402EC,0x00FF0000 ++#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS5 0x1F0402EC,0x0000FF00 ++#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS4 0x1F0402EC,0x000000FF ++ ++#define SRM_CSI0_CPD_RS_2__ADDR 0x1F0402F0 ++#define SRM_CSI0_CPD_RS_2__EMPTY 0x1F0402F0,0x00000000 ++#define SRM_CSI0_CPD_RS_2__FULL 0x1F0402F0,0xffffffff ++#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS11 0x1F0402F0,0xFF000000 ++#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS10 0x1F0402F0,0x00FF0000 ++#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS9 0x1F0402F0,0x0000FF00 ++#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS8 0x1F0402F0,0x000000FF ++ ++#define SRM_CSI0_CPD_RS_3__ADDR 0x1F0402F4 ++#define SRM_CSI0_CPD_RS_3__EMPTY 0x1F0402F4,0x00000000 ++#define SRM_CSI0_CPD_RS_3__FULL 0x1F0402F4,0xffffffff ++#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS15 0x1F0402F4,0xFF000000 ++#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS14 0x1F0402F4,0x00FF0000 ++#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS13 0x1F0402F4,0x0000FF00 ++#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS12 0x1F0402F4,0x000000FF ++ ++#define SRM_CSI0_CPD_GRC_0__ADDR 0x1F0402F8 ++#define SRM_CSI0_CPD_GRC_0__EMPTY 0x1F0402F8,0x00000000 ++#define SRM_CSI0_CPD_GRC_0__FULL 0x1F0402F8,0xffffffff ++#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC1 0x1F0402F8,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC0 0x1F0402F8,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_1__ADDR 0x1F0402FC ++#define SRM_CSI0_CPD_GRC_1__EMPTY 0x1F0402FC,0x00000000 ++#define SRM_CSI0_CPD_GRC_1__FULL 0x1F0402FC,0xffffffff ++#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC3 0x1F0402FC,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC2 0x1F0402FC,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_2__ADDR 0x1F040300 ++#define SRM_CSI0_CPD_GRC_2__EMPTY 0x1F040300,0x00000000 ++#define SRM_CSI0_CPD_GRC_2__FULL 0x1F040300,0xffffffff ++#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC5 0x1F040300,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC4 0x1F040300,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_3__ADDR 0x1F040304 ++#define SRM_CSI0_CPD_GRC_3__EMPTY 0x1F040304,0x00000000 ++#define SRM_CSI0_CPD_GRC_3__FULL 0x1F040304,0xffffffff ++#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC7 0x1F040304,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC6 0x1F040304,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_4__ADDR 0x1F040308 ++#define SRM_CSI0_CPD_GRC_4__EMPTY 0x1F040308,0x00000000 ++#define SRM_CSI0_CPD_GRC_4__FULL 0x1F040308,0xffffffff ++#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC9 0x1F040308,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC8 0x1F040308,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_5__ADDR 0x1F04030C ++#define SRM_CSI0_CPD_GRC_5__EMPTY 0x1F04030C,0x00000000 ++#define SRM_CSI0_CPD_GRC_5__FULL 0x1F04030C,0xffffffff ++#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC11 0x1F04030C,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC10 0x1F04030C,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_6__ADDR 0x1F040310 ++#define SRM_CSI0_CPD_GRC_6__EMPTY 0x1F040310,0x00000000 ++#define SRM_CSI0_CPD_GRC_6__FULL 0x1F040310,0xffffffff ++#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC13 0x1F040310,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC12 0x1F040310,0x000001FF ++ ++#define SRM_CSI0_CPD_GRC_7__ADDR 0x1F040314 ++#define SRM_CSI0_CPD_GRC_7__EMPTY 0x1F040314,0x00000000 ++#define SRM_CSI0_CPD_GRC_7__FULL 0x1F040314,0xffffffff ++#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC15 0x1F040314,0x01FF0000 ++#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC14 0x1F040314,0x000001FF ++ ++#define SRM_CSI0_CPD_GRS_0__ADDR 0x1F040318 ++#define SRM_CSI0_CPD_GRS_0__EMPTY 0x1F040318,0x00000000 ++#define SRM_CSI0_CPD_GRS_0__FULL 0x1F040318,0xffffffff ++#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS3 0x1F040318,0xFF000000 ++#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS2 0x1F040318,0x00FF0000 ++#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS1 0x1F040318,0x0000FF00 ++#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS0 0x1F040318,0x000000FF ++ ++#define SRM_CSI0_CPD_GRS_1__ADDR 0x1F04031C ++#define SRM_CSI0_CPD_GRS_1__EMPTY 0x1F04031C,0x00000000 ++#define SRM_CSI0_CPD_GRS_1__FULL 0x1F04031C,0xffffffff ++#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS7 0x1F04031C,0xFF000000 ++#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS6 0x1F04031C,0x00FF0000 ++#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS5 0x1F04031C,0x0000FF00 ++#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS4 0x1F04031C,0x000000FF ++ ++#define SRM_CSI0_CPD_GRS_2__ADDR 0x1F040320 ++#define SRM_CSI0_CPD_GRS_2__EMPTY 0x1F040320,0x00000000 ++#define SRM_CSI0_CPD_GRS_2__FULL 0x1F040320,0xffffffff ++#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS11 0x1F040320,0xFF000000 ++#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS10 0x1F040320,0x00FF0000 ++#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS9 0x1F040320,0x0000FF00 ++#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS8 0x1F040320,0x000000FF ++ ++#define SRM_CSI0_CPD_GRS_3__ADDR 0x1F040324 ++#define SRM_CSI0_CPD_GRS_3__EMPTY 0x1F040324,0x00000000 ++#define SRM_CSI0_CPD_GRS_3__FULL 0x1F040324,0xffffffff ++#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS15 0x1F040324,0xFF000000 ++#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS14 0x1F040324,0x00FF0000 ++#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS13 0x1F040324,0x0000FF00 ++#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS12 0x1F040324,0x000000FF ++ ++#define SRM_CSI0_CPD_GBC_0__ADDR 0x1F040328 ++#define SRM_CSI0_CPD_GBC_0__EMPTY 0x1F040328,0x00000000 ++#define SRM_CSI0_CPD_GBC_0__FULL 0x1F040328,0xffffffff ++#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC1 0x1F040328,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC0 0x1F040328,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_1__ADDR 0x1F04032C ++#define SRM_CSI0_CPD_GBC_1__EMPTY 0x1F04032C,0x00000000 ++#define SRM_CSI0_CPD_GBC_1__FULL 0x1F04032C,0xffffffff ++#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC3 0x1F04032C,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC2 0x1F04032C,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_2__ADDR 0x1F040330 ++#define SRM_CSI0_CPD_GBC_2__EMPTY 0x1F040330,0x00000000 ++#define SRM_CSI0_CPD_GBC_2__FULL 0x1F040330,0xffffffff ++#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC5 0x1F040330,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC4 0x1F040330,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_3__ADDR 0x1F040334 ++#define SRM_CSI0_CPD_GBC_3__EMPTY 0x1F040334,0x00000000 ++#define SRM_CSI0_CPD_GBC_3__FULL 0x1F040334,0xffffffff ++#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC7 0x1F040334,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC6 0x1F040334,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_4__ADDR 0x1F040338 ++#define SRM_CSI0_CPD_GBC_4__EMPTY 0x1F040338,0x00000000 ++#define SRM_CSI0_CPD_GBC_4__FULL 0x1F040338,0xffffffff ++#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC9 0x1F040338,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC8 0x1F040338,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_5__ADDR 0x1F04033C ++#define SRM_CSI0_CPD_GBC_5__EMPTY 0x1F04033C,0x00000000 ++#define SRM_CSI0_CPD_GBC_5__FULL 0x1F04033C,0xffffffff ++#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC11 0x1F04033C,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC10 0x1F04033C,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_6__ADDR 0x1F040340 ++#define SRM_CSI0_CPD_GBC_6__EMPTY 0x1F040340,0x00000000 ++#define SRM_CSI0_CPD_GBC_6__FULL 0x1F040340,0xffffffff ++#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC13 0x1F040340,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC12 0x1F040340,0x000001FF ++ ++#define SRM_CSI0_CPD_GBC_7__ADDR 0x1F040344 ++#define SRM_CSI0_CPD_GBC_7__EMPTY 0x1F040344,0x00000000 ++#define SRM_CSI0_CPD_GBC_7__FULL 0x1F040344,0xffffffff ++#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC15 0x1F040344,0x01FF0000 ++#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC14 0x1F040344,0x000001FF ++ ++#define SRM_CSI0_CPD_GBS_0__ADDR 0x1F040348 ++#define SRM_CSI0_CPD_GBS_0__EMPTY 0x1F040348,0x00000000 ++#define SRM_CSI0_CPD_GBS_0__FULL 0x1F040348,0xffffffff ++#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS3 0x1F040348,0xFF000000 ++#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS2 0x1F040348,0x00FF0000 ++#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS1 0x1F040348,0x0000FF00 ++#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS0 0x1F040348,0x000000FF ++ ++#define SRM_CSI0_CPD_GBS_1__ADDR 0x1F04034C ++#define SRM_CSI0_CPD_GBS_1__EMPTY 0x1F04034C,0x00000000 ++#define SRM_CSI0_CPD_GBS_1__FULL 0x1F04034C,0xffffffff ++#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS7 0x1F04034C,0xFF000000 ++#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS6 0x1F04034C,0x00FF0000 ++#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS5 0x1F04034C,0x0000FF00 ++#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS4 0x1F04034C,0x000000FF ++ ++#define SRM_CSI0_CPD_GBS_2__ADDR 0x1F040350 ++#define SRM_CSI0_CPD_GBS_2__EMPTY 0x1F040350,0x00000000 ++#define SRM_CSI0_CPD_GBS_2__FULL 0x1F040350,0xffffffff ++#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS11 0x1F040350,0xFF000000 ++#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS10 0x1F040350,0x00FF0000 ++#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS9 0x1F040350,0x0000FF00 ++#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS8 0x1F040350,0x000000FF ++ ++#define SRM_CSI0_CPD_GBS_3__ADDR 0x1F040354 ++#define SRM_CSI0_CPD_GBS_3__EMPTY 0x1F040354,0x00000000 ++#define SRM_CSI0_CPD_GBS_3__FULL 0x1F040354,0xffffffff ++#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS15 0x1F040354,0xFF000000 ++#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS14 0x1F040354,0x00FF0000 ++#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS13 0x1F040354,0x0000FF00 ++#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS12 0x1F040354,0x000000FF ++ ++#define SRM_CSI0_CPD_BC_0__ADDR 0x1F040358 ++#define SRM_CSI0_CPD_BC_0__EMPTY 0x1F040358,0x00000000 ++#define SRM_CSI0_CPD_BC_0__FULL 0x1F040358,0xffffffff ++#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC1 0x1F040358,0x01FF0000 ++#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC0 0x1F040358,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_1__ADDR 0x1F04035C ++#define SRM_CSI0_CPD_BC_1__EMPTY 0x1F04035C,0x00000000 ++#define SRM_CSI0_CPD_BC_1__FULL 0x1F04035C,0xffffffff ++#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC3 0x1F04035C,0x01FF0000 ++#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC2 0x1F04035C,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_2__ADDR 0x1F040360 ++#define SRM_CSI0_CPD_BC_2__EMPTY 0x1F040360,0x00000000 ++#define SRM_CSI0_CPD_BC_2__FULL 0x1F040360,0xffffffff ++#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC5 0x1F040360,0x01FF0000 ++#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC4 0x1F040360,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_3__ADDR 0x1F040364 ++#define SRM_CSI0_CPD_BC_3__EMPTY 0x1F040364,0x00000000 ++#define SRM_CSI0_CPD_BC_3__FULL 0x1F040364,0xffffffff ++#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC7 0x1F040364,0x01FF0000 ++#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC6 0x1F040364,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_4__ADDR 0x1F040368 ++#define SRM_CSI0_CPD_BC_4__EMPTY 0x1F040368,0x00000000 ++#define SRM_CSI0_CPD_BC_4__FULL 0x1F040368,0xffffffff ++#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC9 0x1F040368,0x01FF0000 ++#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC8 0x1F040368,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_5__ADDR 0x1F04036C ++#define SRM_CSI0_CPD_BC_5__EMPTY 0x1F04036C,0x00000000 ++#define SRM_CSI0_CPD_BC_5__FULL 0x1F04036C,0xffffffff ++#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC11 0x1F04036C,0x01FF0000 ++#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC10 0x1F04036C,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_6__ADDR 0x1F040370 ++#define SRM_CSI0_CPD_BC_6__EMPTY 0x1F040370,0x00000000 ++#define SRM_CSI0_CPD_BC_6__FULL 0x1F040370,0xffffffff ++#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC13 0x1F040370,0x01FF0000 ++#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC12 0x1F040370,0x000001FF ++ ++#define SRM_CSI0_CPD_BC_7__ADDR 0x1F040374 ++#define SRM_CSI0_CPD_BC_7__EMPTY 0x1F040374,0x00000000 ++#define SRM_CSI0_CPD_BC_7__FULL 0x1F040374,0xffffffff ++#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC15 0x1F040374,0x01FF0000 ++#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC14 0x1F040374,0x000001FF ++ ++#define SRM_CSI0_CPD_BS_0__ADDR 0x1F040378 ++#define SRM_CSI0_CPD_BS_0__EMPTY 0x1F040378,0x00000000 ++#define SRM_CSI0_CPD_BS_0__FULL 0x1F040378,0xffffffff ++#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS3 0x1F040378,0xFF000000 ++#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS2 0x1F040378,0x00FF0000 ++#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS1 0x1F040378,0x0000FF00 ++#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS0 0x1F040378,0x000000FF ++ ++#define SRM_CSI0_CPD_BS_1__ADDR 0x1F04037C ++#define SRM_CSI0_CPD_BS_1__EMPTY 0x1F04037C,0x00000000 ++#define SRM_CSI0_CPD_BS_1__FULL 0x1F04037C,0xffffffff ++#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS7 0x1F04037C,0xFF000000 ++#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS6 0x1F04037C,0x00FF0000 ++#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS5 0x1F04037C,0x0000FF00 ++#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS4 0x1F04037C,0x000000FF ++ ++#define SRM_CSI0_CPD_BS_2__ADDR 0x1F040380 ++#define SRM_CSI0_CPD_BS_2__EMPTY 0x1F040380,0x00000000 ++#define SRM_CSI0_CPD_BS_2__FULL 0x1F040380,0xffffffff ++#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS11 0x1F040380,0xFF000000 ++#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS10 0x1F040380,0x00FF0000 ++#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS9 0x1F040380,0x0000FF00 ++#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS8 0x1F040380,0x000000FF ++ ++#define SRM_CSI0_CPD_BS_3__ADDR 0x1F040384 ++#define SRM_CSI0_CPD_BS_3__EMPTY 0x1F040384,0x00000000 ++#define SRM_CSI0_CPD_BS_3__FULL 0x1F040384,0xffffffff ++#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS15 0x1F040384,0xFF000000 ++#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS14 0x1F040384,0x00FF0000 ++#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS13 0x1F040384,0x0000FF00 ++#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS12 0x1F040384,0x000000FF ++ ++#define SRM_CSI0_CPD_OFFSET1__ADDR 0x1F040388 ++#define SRM_CSI0_CPD_OFFSET1__EMPTY 0x1F040388,0x00000000 ++#define SRM_CSI0_CPD_OFFSET1__FULL 0x1F040388,0xffffffff ++#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET 0x1F040388,0x3FF00000 ++#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET 0x1F040388,0x000FFC00 ++#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET 0x1F040388,0x000003FF ++ ++#define SRM_CSI0_CPD_OFFSET2__ADDR 0x1F04038C ++#define SRM_CSI0_CPD_OFFSET2__EMPTY 0x1F04038C,0x00000000 ++#define SRM_CSI0_CPD_OFFSET2__FULL 0x1F04038C,0xffffffff ++#define SRM_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET 0x1F04038C,0x000003FF ++ ++#define SRM_CSI1_CPD_CTRL__ADDR 0x1F040390 ++#define SRM_CSI1_CPD_CTRL__EMPTY 0x1F040390,0x00000000 ++#define SRM_CSI1_CPD_CTRL__FULL 0x1F040390,0xffffffff ++#define SRM_CSI1_CPD_CTRL__CSI1_CPD 0x1F040390,0x0000001C ++#define SRM_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN 0x1F040390,0x00000002 ++#define SRM_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN 0x1F040390,0x00000001 ++ ++#define SRM_CSI1_CPD_RC_0__ADDR 0x1F040394 ++#define SRM_CSI1_CPD_RC_0__EMPTY 0x1F040394,0x00000000 ++#define SRM_CSI1_CPD_RC_0__FULL 0x1F040394,0xffffffff ++#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_1 0x1F040394,0x01FF0000 ++#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_0 0x1F040394,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_1__ADDR 0x1F040398 ++#define SRM_CSI1_CPD_RC_1__EMPTY 0x1F040398,0x00000000 ++#define SRM_CSI1_CPD_RC_1__FULL 0x1F040398,0xffffffff ++#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_3 0x1F040398,0x01FF0000 ++#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_2 0x1F040398,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_2__ADDR 0x1F04039C ++#define SRM_CSI1_CPD_RC_2__EMPTY 0x1F04039C,0x00000000 ++#define SRM_CSI1_CPD_RC_2__FULL 0x1F04039C,0xffffffff ++#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_5 0x1F04039C,0x01FF0000 ++#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_4 0x1F04039C,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_3__ADDR 0x1F0403A0 ++#define SRM_CSI1_CPD_RC_3__EMPTY 0x1F0403A0,0x00000000 ++#define SRM_CSI1_CPD_RC_3__FULL 0x1F0403A0,0xffffffff ++#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_7 0x1F0403A0,0x01FF0000 ++#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_6 0x1F0403A0,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_4__ADDR 0x1F0403A4 ++#define SRM_CSI1_CPD_RC_4__EMPTY 0x1F0403A4,0x00000000 ++#define SRM_CSI1_CPD_RC_4__FULL 0x1F0403A4,0xffffffff ++#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_9 0x1F0403A4,0x01FF0000 ++#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_8 0x1F0403A4,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_5__ADDR 0x1F0403A8 ++#define SRM_CSI1_CPD_RC_5__EMPTY 0x1F0403A8,0x00000000 ++#define SRM_CSI1_CPD_RC_5__FULL 0x1F0403A8,0xffffffff ++#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_11 0x1F0403A8,0x01FF0000 ++#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_10 0x1F0403A8,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_6__ADDR 0x1F0403AC ++#define SRM_CSI1_CPD_RC_6__EMPTY 0x1F0403AC,0x00000000 ++#define SRM_CSI1_CPD_RC_6__FULL 0x1F0403AC,0xffffffff ++#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_13 0x1F0403AC,0x01FF0000 ++#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_12 0x1F0403AC,0x000001FF ++ ++#define SRM_CSI1_CPD_RC_7__ADDR 0x1F0403B0 ++#define SRM_CSI1_CPD_RC_7__EMPTY 0x1F0403B0,0x00000000 ++#define SRM_CSI1_CPD_RC_7__FULL 0x1F0403B0,0xffffffff ++#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_15 0x1F0403B0,0x01FF0000 ++#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_14 0x1F0403B0,0x000001FF ++ ++#define SRM_CSI1_CPD_RS_0__ADDR 0x1F0403B4 ++#define SRM_CSI1_CPD_RS_0__EMPTY 0x1F0403B4,0x00000000 ++#define SRM_CSI1_CPD_RS_0__FULL 0x1F0403B4,0xffffffff ++#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS3 0x1F0403B4,0xFF000000 ++#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS2 0x1F0403B4,0x00FF0000 ++#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS1 0x1F0403B4,0x0000FF00 ++#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS0 0x1F0403B4,0x000000FF ++ ++#define SRM_CSI1_CPD_RS_1__ADDR 0x1F0403B8 ++#define SRM_CSI1_CPD_RS_1__EMPTY 0x1F0403B8,0x00000000 ++#define SRM_CSI1_CPD_RS_1__FULL 0x1F0403B8,0xffffffff ++#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS7 0x1F0403B8,0xFF000000 ++#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS6 0x1F0403B8,0x00FF0000 ++#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS5 0x1F0403B8,0x0000FF00 ++#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS4 0x1F0403B8,0x000000FF ++ ++#define SRM_CSI1_CPD_RS_2__ADDR 0x1F0403BC ++#define SRM_CSI1_CPD_RS_2__EMPTY 0x1F0403BC,0x00000000 ++#define SRM_CSI1_CPD_RS_2__FULL 0x1F0403BC,0xffffffff ++#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS11 0x1F0403BC,0xFF000000 ++#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS10 0x1F0403BC,0x00FF0000 ++#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS9 0x1F0403BC,0x0000FF00 ++#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS8 0x1F0403BC,0x000000FF ++ ++#define SRM_CSI1_CPD_RS_3__ADDR 0x1F0403C0 ++#define SRM_CSI1_CPD_RS_3__EMPTY 0x1F0403C0,0x00000000 ++#define SRM_CSI1_CPD_RS_3__FULL 0x1F0403C0,0xffffffff ++#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS15 0x1F0403C0,0xFF000000 ++#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS14 0x1F0403C0,0x00FF0000 ++#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS13 0x1F0403C0,0x0000FF00 ++#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS12 0x1F0403C0,0x000000FF ++ ++#define SRM_CSI1_CPD_GRC_0__ADDR 0x1F0403C4 ++#define SRM_CSI1_CPD_GRC_0__EMPTY 0x1F0403C4,0x00000000 ++#define SRM_CSI1_CPD_GRC_0__FULL 0x1F0403C4,0xffffffff ++#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC1 0x1F0403C4,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC0 0x1F0403C4,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_1__ADDR 0x1F0403C8 ++#define SRM_CSI1_CPD_GRC_1__EMPTY 0x1F0403C8,0x00000000 ++#define SRM_CSI1_CPD_GRC_1__FULL 0x1F0403C8,0xffffffff ++#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC3 0x1F0403C8,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC2 0x1F0403C8,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_2__ADDR 0x1F0403CC ++#define SRM_CSI1_CPD_GRC_2__EMPTY 0x1F0403CC,0x00000000 ++#define SRM_CSI1_CPD_GRC_2__FULL 0x1F0403CC,0xffffffff ++#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC5 0x1F0403CC,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC4 0x1F0403CC,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_3__ADDR 0x1F0403D0 ++#define SRM_CSI1_CPD_GRC_3__EMPTY 0x1F0403D0,0x00000000 ++#define SRM_CSI1_CPD_GRC_3__FULL 0x1F0403D0,0xffffffff ++#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC7 0x1F0403D0,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC6 0x1F0403D0,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_4__ADDR 0x1F0403D4 ++#define SRM_CSI1_CPD_GRC_4__EMPTY 0x1F0403D4,0x00000000 ++#define SRM_CSI1_CPD_GRC_4__FULL 0x1F0403D4,0xffffffff ++#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC9 0x1F0403D4,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC8 0x1F0403D4,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_5__ADDR 0x1F0403D8 ++#define SRM_CSI1_CPD_GRC_5__EMPTY 0x1F0403D8,0x00000000 ++#define SRM_CSI1_CPD_GRC_5__FULL 0x1F0403D8,0xffffffff ++#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC11 0x1F0403D8,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC10 0x1F0403D8,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_6__ADDR 0x1F0403DC ++#define SRM_CSI1_CPD_GRC_6__EMPTY 0x1F0403DC,0x00000000 ++#define SRM_CSI1_CPD_GRC_6__FULL 0x1F0403DC,0xffffffff ++#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC13 0x1F0403DC,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC12 0x1F0403DC,0x000001FF ++ ++#define SRM_CSI1_CPD_GRC_7__ADDR 0x1F0403E0 ++#define SRM_CSI1_CPD_GRC_7__EMPTY 0x1F0403E0,0x00000000 ++#define SRM_CSI1_CPD_GRC_7__FULL 0x1F0403E0,0xffffffff ++#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC15 0x1F0403E0,0x01FF0000 ++#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC14 0x1F0403E0,0x000001FF ++ ++#define SRM_CSI1_CPD_GRS_0__ADDR 0x1F0403E4 ++#define SRM_CSI1_CPD_GRS_0__EMPTY 0x1F0403E4,0x00000000 ++#define SRM_CSI1_CPD_GRS_0__FULL 0x1F0403E4,0xffffffff ++#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS3 0x1F0403E4,0xFF000000 ++#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS2 0x1F0403E4,0x00FF0000 ++#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS1 0x1F0403E4,0x0000FF00 ++#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS0 0x1F0403E4,0x000000FF ++ ++#define SRM_CSI1_CPD_GRS_1__ADDR 0x1F0403E8 ++#define SRM_CSI1_CPD_GRS_1__EMPTY 0x1F0403E8,0x00000000 ++#define SRM_CSI1_CPD_GRS_1__FULL 0x1F0403E8,0xffffffff ++#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS7 0x1F0403E8,0xFF000000 ++#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS6 0x1F0403E8,0x00FF0000 ++#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS5 0x1F0403E8,0x0000FF00 ++#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS4 0x1F0403E8,0x000000FF ++ ++#define SRM_CSI1_CPD_GRS_2__ADDR 0x1F0403EC ++#define SRM_CSI1_CPD_GRS_2__EMPTY 0x1F0403EC,0x00000000 ++#define SRM_CSI1_CPD_GRS_2__FULL 0x1F0403EC,0xffffffff ++#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS11 0x1F0403EC,0xFF000000 ++#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS10 0x1F0403EC,0x00FF0000 ++#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS9 0x1F0403EC,0x0000FF00 ++#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS8 0x1F0403EC,0x000000FF ++ ++#define SRM_CSI1_CPD_GRS_3__ADDR 0x1F0403F0 ++#define SRM_CSI1_CPD_GRS_3__EMPTY 0x1F0403F0,0x00000000 ++#define SRM_CSI1_CPD_GRS_3__FULL 0x1F0403F0,0xffffffff ++#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS15 0x1F0403F0,0xFF000000 ++#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS14 0x1F0403F0,0x00FF0000 ++#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS13 0x1F0403F0,0x0000FF00 ++#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS12 0x1F0403F0,0x000000FF ++ ++#define SRM_CSI1_CPD_GBC_0__ADDR 0x1F0403F4 ++#define SRM_CSI1_CPD_GBC_0__EMPTY 0x1F0403F4,0x00000000 ++#define SRM_CSI1_CPD_GBC_0__FULL 0x1F0403F4,0xffffffff ++#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC1 0x1F0403F4,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC0 0x1F0403F4,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_1__ADDR 0x1F0403F8 ++#define SRM_CSI1_CPD_GBC_1__EMPTY 0x1F0403F8,0x00000000 ++#define SRM_CSI1_CPD_GBC_1__FULL 0x1F0403F8,0xffffffff ++#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC3 0x1F0403F8,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC2 0x1F0403F8,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_2__ADDR 0x1F0403FC ++#define SRM_CSI1_CPD_GBC_2__EMPTY 0x1F0403FC,0x00000000 ++#define SRM_CSI1_CPD_GBC_2__FULL 0x1F0403FC,0xffffffff ++#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC5 0x1F0403FC,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC4 0x1F0403FC,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_3__ADDR 0x1F040400 ++#define SRM_CSI1_CPD_GBC_3__EMPTY 0x1F040400,0x00000000 ++#define SRM_CSI1_CPD_GBC_3__FULL 0x1F040400,0xffffffff ++#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC7 0x1F040400,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC6 0x1F040400,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_4__ADDR 0x1F040404 ++#define SRM_CSI1_CPD_GBC_4__EMPTY 0x1F040404,0x00000000 ++#define SRM_CSI1_CPD_GBC_4__FULL 0x1F040404,0xffffffff ++#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC9 0x1F040404,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC8 0x1F040404,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_5__ADDR 0x1F040408 ++#define SRM_CSI1_CPD_GBC_5__EMPTY 0x1F040408,0x00000000 ++#define SRM_CSI1_CPD_GBC_5__FULL 0x1F040408,0xffffffff ++#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC11 0x1F040408,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC10 0x1F040408,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_6__ADDR 0x1F04040C ++#define SRM_CSI1_CPD_GBC_6__EMPTY 0x1F04040C,0x00000000 ++#define SRM_CSI1_CPD_GBC_6__FULL 0x1F04040C,0xffffffff ++#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC13 0x1F04040C,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC12 0x1F04040C,0x000001FF ++ ++#define SRM_CSI1_CPD_GBC_7__ADDR 0x1F040410 ++#define SRM_CSI1_CPD_GBC_7__EMPTY 0x1F040410,0x00000000 ++#define SRM_CSI1_CPD_GBC_7__FULL 0x1F040410,0xffffffff ++#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC15 0x1F040410,0x01FF0000 ++#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC14 0x1F040410,0x000001FF ++ ++#define SRM_CSI1_CPD_GBS_0__ADDR 0x1F040414 ++#define SRM_CSI1_CPD_GBS_0__EMPTY 0x1F040414,0x00000000 ++#define SRM_CSI1_CPD_GBS_0__FULL 0x1F040414,0xffffffff ++#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS3 0x1F040414,0xFF000000 ++#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS2 0x1F040414,0x00FF0000 ++#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS1 0x1F040414,0x0000FF00 ++#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS0 0x1F040414,0x000000FF ++ ++#define SRM_CSI1_CPD_GBS_1__ADDR 0x1F040418 ++#define SRM_CSI1_CPD_GBS_1__EMPTY 0x1F040418,0x00000000 ++#define SRM_CSI1_CPD_GBS_1__FULL 0x1F040418,0xffffffff ++#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS7 0x1F040418,0xFF000000 ++#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS6 0x1F040418,0x00FF0000 ++#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS5 0x1F040418,0x0000FF00 ++#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS4 0x1F040418,0x000000FF ++ ++#define SRM_CSI1_CPD_GBS_2__ADDR 0x1F04041C ++#define SRM_CSI1_CPD_GBS_2__EMPTY 0x1F04041C,0x00000000 ++#define SRM_CSI1_CPD_GBS_2__FULL 0x1F04041C,0xffffffff ++#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS11 0x1F04041C,0xFF000000 ++#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS10 0x1F04041C,0x00FF0000 ++#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS9 0x1F04041C,0x0000FF00 ++#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS8 0x1F04041C,0x000000FF ++ ++#define SRM_CSI1_CPD_GBS_3__ADDR 0x1F040420 ++#define SRM_CSI1_CPD_GBS_3__EMPTY 0x1F040420,0x00000000 ++#define SRM_CSI1_CPD_GBS_3__FULL 0x1F040420,0xffffffff ++#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS15 0x1F040420,0xFF000000 ++#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS14 0x1F040420,0x00FF0000 ++#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS13 0x1F040420,0x0000FF00 ++#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS12 0x1F040420,0x000000FF ++ ++#define SRM_CSI1_CPD_BC_0__ADDR 0x1F040424 ++#define SRM_CSI1_CPD_BC_0__EMPTY 0x1F040424,0x00000000 ++#define SRM_CSI1_CPD_BC_0__FULL 0x1F040424,0xffffffff ++#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC1 0x1F040424,0x01FF0000 ++#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC0 0x1F040424,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_1__ADDR 0x1F040428 ++#define SRM_CSI1_CPD_BC_1__EMPTY 0x1F040428,0x00000000 ++#define SRM_CSI1_CPD_BC_1__FULL 0x1F040428,0xffffffff ++#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC3 0x1F040428,0x01FF0000 ++#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC2 0x1F040428,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_2__ADDR 0x1F04042C ++#define SRM_CSI1_CPD_BC_2__EMPTY 0x1F04042C,0x00000000 ++#define SRM_CSI1_CPD_BC_2__FULL 0x1F04042C,0xffffffff ++#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC5 0x1F04042C,0x01FF0000 ++#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC4 0x1F04042C,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_3__ADDR 0x1F040430 ++#define SRM_CSI1_CPD_BC_3__EMPTY 0x1F040430,0x00000000 ++#define SRM_CSI1_CPD_BC_3__FULL 0x1F040430,0xffffffff ++#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC7 0x1F040430,0x01FF0000 ++#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC6 0x1F040430,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_4__ADDR 0x1F040434 ++#define SRM_CSI1_CPD_BC_4__EMPTY 0x1F040434,0x00000000 ++#define SRM_CSI1_CPD_BC_4__FULL 0x1F040434,0xffffffff ++#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC9 0x1F040434,0x01FF0000 ++#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC8 0x1F040434,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_5__ADDR 0x1F040438 ++#define SRM_CSI1_CPD_BC_5__EMPTY 0x1F040438,0x00000000 ++#define SRM_CSI1_CPD_BC_5__FULL 0x1F040438,0xffffffff ++#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC11 0x1F040438,0x01FF0000 ++#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC10 0x1F040438,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_6__ADDR 0x1F04043C ++#define SRM_CSI1_CPD_BC_6__EMPTY 0x1F04043C,0x00000000 ++#define SRM_CSI1_CPD_BC_6__FULL 0x1F04043C,0xffffffff ++#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC13 0x1F04043C,0x01FF0000 ++#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC12 0x1F04043C,0x000001FF ++ ++#define SRM_CSI1_CPD_BC_7__ADDR 0x1F040440 ++#define SRM_CSI1_CPD_BC_7__EMPTY 0x1F040440,0x00000000 ++#define SRM_CSI1_CPD_BC_7__FULL 0x1F040440,0xffffffff ++#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC15 0x1F040440,0x01FF0000 ++#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC14 0x1F040440,0x000001FF ++ ++#define SRM_CSI1_CPD_BS_0__ADDR 0x1F040444 ++#define SRM_CSI1_CPD_BS_0__EMPTY 0x1F040444,0x00000000 ++#define SRM_CSI1_CPD_BS_0__FULL 0x1F040444,0xffffffff ++#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS3 0x1F040444,0xFF000000 ++#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS2 0x1F040444,0x00FF0000 ++#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS1 0x1F040444,0x0000FF00 ++#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS0 0x1F040444,0x000000FF ++ ++#define SRM_CSI1_CPD_BS_1__ADDR 0x1F040448 ++#define SRM_CSI1_CPD_BS_1__EMPTY 0x1F040448,0x00000000 ++#define SRM_CSI1_CPD_BS_1__FULL 0x1F040448,0xffffffff ++#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS7 0x1F040448,0xFF000000 ++#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS6 0x1F040448,0x00FF0000 ++#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS5 0x1F040448,0x0000FF00 ++#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS4 0x1F040448,0x000000FF ++ ++#define SRM_CSI1_CPD_BS_2__ADDR 0x1F04044C ++#define SRM_CSI1_CPD_BS_2__EMPTY 0x1F04044C,0x00000000 ++#define SRM_CSI1_CPD_BS_2__FULL 0x1F04044C,0xffffffff ++#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS11 0x1F04044C,0xFF000000 ++#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS10 0x1F04044C,0x00FF0000 ++#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS9 0x1F04044C,0x0000FF00 ++#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS8 0x1F04044C,0x000000FF ++ ++#define SRM_CSI1_CPD_BS_3__ADDR 0x1F040450 ++#define SRM_CSI1_CPD_BS_3__EMPTY 0x1F040450,0x00000000 ++#define SRM_CSI1_CPD_BS_3__FULL 0x1F040450,0xffffffff ++#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS15 0x1F040450,0xFF000000 ++#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS14 0x1F040450,0x00FF0000 ++#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS13 0x1F040450,0x0000FF00 ++#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS12 0x1F040450,0x000000FF ++ ++#define SRM_CSI1_CPD_OFFSET1__ADDR 0x1F040454 ++#define SRM_CSI1_CPD_OFFSET1__EMPTY 0x1F040454,0x00000000 ++#define SRM_CSI1_CPD_OFFSET1__FULL 0x1F040454,0xffffffff ++#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET 0x1F040454,0x3FF00000 ++#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET 0x1F040454,0x000FFC00 ++#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET 0x1F040454,0x000003FF ++ ++#define SRM_CSI1_CPD_OFFSET2__ADDR 0x1F040458 ++#define SRM_CSI1_CPD_OFFSET2__EMPTY 0x1F040458,0x00000000 ++#define SRM_CSI1_CPD_OFFSET2__FULL 0x1F040458,0xffffffff ++#define SRM_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET 0x1F040458,0x000003FF ++ ++#define SRM_DI0_GENERAL__ADDR 0x1F040494 ++#define SRM_DI0_GENERAL__EMPTY 0x1F040494,0x00000000 ++#define SRM_DI0_GENERAL__FULL 0x1F040494,0xffffffff ++#define SRM_DI0_GENERAL__DI0_DISP_Y_SEL 0x1F040494,0x70000000 ++#define SRM_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1F040494,0x0F000000 ++#define SRM_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1F040494,0x00800000 ++#define SRM_DI0_GENERAL__DI0_MASK_SEL 0x1F040494,0x00400000 ++#define SRM_DI0_GENERAL__DI0_VSYNC_EXT 0x1F040494,0x00200000 ++#define SRM_DI0_GENERAL__DI0_CLK_EXT 0x1F040494,0x00100000 ++#define SRM_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1F040494,0x000C0000 ++#define SRM_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1F040494,0x00020000 ++#define SRM_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1F040494,0x0000F000 ++#define SRM_DI0_GENERAL__DI0_ERR_TREATMENT 0x1F040494,0x00000800 ++#define SRM_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1F040494,0x00000400 ++#define SRM_DI0_GENERAL__DI0_POLARITY_CS1 0x1F040494,0x00000200 ++#define SRM_DI0_GENERAL__DI0_POLARITY_CS0 0x1F040494,0x00000100 ++#define SRM_DI0_GENERAL__DI0_POLARITY_8 0x1F040494,0x00000080 ++#define SRM_DI0_GENERAL__DI0_POLARITY_7 0x1F040494,0x00000040 ++#define SRM_DI0_GENERAL__DI0_POLARITY_6 0x1F040494,0x00000020 ++#define SRM_DI0_GENERAL__DI0_POLARITY_5 0x1F040494,0x00000010 ++#define SRM_DI0_GENERAL__DI0_POLARITY_4 0x1F040494,0x00000008 ++#define SRM_DI0_GENERAL__DI0_POLARITY_3 0x1F040494,0x00000004 ++#define SRM_DI0_GENERAL__DI0_POLARITY_2 0x1F040494,0x00000002 ++#define SRM_DI0_GENERAL__DI0_POLARITY_1 0x1F040494,0x00000001 ++ ++#define SRM_DI0_BS_CLKGEN0__ADDR 0x1F040498 ++#define SRM_DI0_BS_CLKGEN0__EMPTY 0x1F040498,0x00000000 ++#define SRM_DI0_BS_CLKGEN0__FULL 0x1F040498,0xffffffff ++#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1F040498,0x01FF0000 ++#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1F040498,0x00000FFF ++ ++#define SRM_DI0_BS_CLKGEN1__ADDR 0x1F04049C ++#define SRM_DI0_BS_CLKGEN1__EMPTY 0x1F04049C,0x00000000 ++#define SRM_DI0_BS_CLKGEN1__FULL 0x1F04049C,0xffffffff ++#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1F04049C,0x01FF0000 ++#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1F04049C,0x000001FF ++ ++#define SRM_DI0_SW_GEN0_1__ADDR 0x1F0404A0 ++#define SRM_DI0_SW_GEN0_1__EMPTY 0x1F0404A0,0x00000000 ++#define SRM_DI0_SW_GEN0_1__FULL 0x1F0404A0,0xffffffff ++#define SRM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1 0x1F0404A0,0x7FF80000 ++#define SRM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1 0x1F0404A0,0x00070000 ++#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1 0x1F0404A0,0x00007FF8 ++#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1 0x1F0404A0,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_2__ADDR 0x1F0404A4 ++#define SRM_DI0_SW_GEN0_2__EMPTY 0x1F0404A4,0x00000000 ++#define SRM_DI0_SW_GEN0_2__FULL 0x1F0404A4,0xffffffff ++#define SRM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2 0x1F0404A4,0x7FF80000 ++#define SRM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2 0x1F0404A4,0x00070000 ++#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2 0x1F0404A4,0x00007FF8 ++#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2 0x1F0404A4,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_3__ADDR 0x1F0404A8 ++#define SRM_DI0_SW_GEN0_3__EMPTY 0x1F0404A8,0x00000000 ++#define SRM_DI0_SW_GEN0_3__FULL 0x1F0404A8,0xffffffff ++#define SRM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3 0x1F0404A8,0x7FF80000 ++#define SRM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3 0x1F0404A8,0x00070000 ++#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3 0x1F0404A8,0x00007FF8 ++#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3 0x1F0404A8,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_4__ADDR 0x1F0404AC ++#define SRM_DI0_SW_GEN0_4__EMPTY 0x1F0404AC,0x00000000 ++#define SRM_DI0_SW_GEN0_4__FULL 0x1F0404AC,0xffffffff ++#define SRM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4 0x1F0404AC,0x7FF80000 ++#define SRM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4 0x1F0404AC,0x00070000 ++#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4 0x1F0404AC,0x00007FF8 ++#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4 0x1F0404AC,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_5__ADDR 0x1F0404B0 ++#define SRM_DI0_SW_GEN0_5__EMPTY 0x1F0404B0,0x00000000 ++#define SRM_DI0_SW_GEN0_5__FULL 0x1F0404B0,0xffffffff ++#define SRM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5 0x1F0404B0,0x7FF80000 ++#define SRM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5 0x1F0404B0,0x00070000 ++#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5 0x1F0404B0,0x00007FF8 ++#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5 0x1F0404B0,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_6__ADDR 0x1F0404B4 ++#define SRM_DI0_SW_GEN0_6__EMPTY 0x1F0404B4,0x00000000 ++#define SRM_DI0_SW_GEN0_6__FULL 0x1F0404B4,0xffffffff ++#define SRM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6 0x1F0404B4,0x7FF80000 ++#define SRM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6 0x1F0404B4,0x00070000 ++#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6 0x1F0404B4,0x00007FF8 ++#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6 0x1F0404B4,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_7__ADDR 0x1F0404B8 ++#define SRM_DI0_SW_GEN0_7__EMPTY 0x1F0404B8,0x00000000 ++#define SRM_DI0_SW_GEN0_7__FULL 0x1F0404B8,0xffffffff ++#define SRM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7 0x1F0404B8,0x7FF80000 ++#define SRM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7 0x1F0404B8,0x00070000 ++#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7 0x1F0404B8,0x00007FF8 ++#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7 0x1F0404B8,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_8__ADDR 0x1F0404BC ++#define SRM_DI0_SW_GEN0_8__EMPTY 0x1F0404BC,0x00000000 ++#define SRM_DI0_SW_GEN0_8__FULL 0x1F0404BC,0xffffffff ++#define SRM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8 0x1F0404BC,0x7FF80000 ++#define SRM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8 0x1F0404BC,0x00070000 ++#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8 0x1F0404BC,0x00007FF8 ++#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8 0x1F0404BC,0x00000007 ++ ++#define SRM_DI0_SW_GEN0_9__ADDR 0x1F0404C0 ++#define SRM_DI0_SW_GEN0_9__EMPTY 0x1F0404C0,0x00000000 ++#define SRM_DI0_SW_GEN0_9__FULL 0x1F0404C0,0xffffffff ++#define SRM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1F0404C0,0x7FF80000 ++#define SRM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1F0404C0,0x00070000 ++#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1F0404C0,0x00007FF8 ++#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1F0404C0,0x00000007 ++ ++#define SRM_DI0_SW_GEN1_1__ADDR 0x1F0404C4 ++#define SRM_DI0_SW_GEN1_1__EMPTY 0x1F0404C4,0x00000000 ++#define SRM_DI0_SW_GEN1_1__FULL 0x1F0404C4,0xffffffff ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1 0x1F0404C4,0x60000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1 0x1F0404C4,0x10000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1 0x1F0404C4,0x0E000000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1 0x1F0404C4,0x01FF0000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1 0x1F0404C4,0x00007000 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1 0x1F0404C4,0x00000E00 ++#define SRM_DI0_SW_GEN1_1__DI0_CNT_UP_1 0x1F0404C4,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_2__ADDR 0x1F0404C8 ++#define SRM_DI0_SW_GEN1_2__EMPTY 0x1F0404C8,0x00000000 ++#define SRM_DI0_SW_GEN1_2__FULL 0x1F0404C8,0xffffffff ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2 0x1F0404C8,0x60000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2 0x1F0404C8,0x10000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2 0x1F0404C8,0x0E000000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2 0x1F0404C8,0x01FF0000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2 0x1F0404C8,0x00007000 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2 0x1F0404C8,0x00000E00 ++#define SRM_DI0_SW_GEN1_2__DI0_CNT_UP_2 0x1F0404C8,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_3__ADDR 0x1F0404CC ++#define SRM_DI0_SW_GEN1_3__EMPTY 0x1F0404CC,0x00000000 ++#define SRM_DI0_SW_GEN1_3__FULL 0x1F0404CC,0xffffffff ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3 0x1F0404CC,0x60000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3 0x1F0404CC,0x10000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3 0x1F0404CC,0x0E000000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3 0x1F0404CC,0x01FF0000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3 0x1F0404CC,0x00007000 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3 0x1F0404CC,0x00000E00 ++#define SRM_DI0_SW_GEN1_3__DI0_CNT_UP_3 0x1F0404CC,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_4__ADDR 0x1F0404D0 ++#define SRM_DI0_SW_GEN1_4__EMPTY 0x1F0404D0,0x00000000 ++#define SRM_DI0_SW_GEN1_4__FULL 0x1F0404D0,0xffffffff ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4 0x1F0404D0,0x60000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4 0x1F0404D0,0x10000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4 0x1F0404D0,0x0E000000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4 0x1F0404D0,0x01FF0000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4 0x1F0404D0,0x00007000 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4 0x1F0404D0,0x00000E00 ++#define SRM_DI0_SW_GEN1_4__DI0_CNT_UP_4 0x1F0404D0,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_5__ADDR 0x1F0404D4 ++#define SRM_DI0_SW_GEN1_5__EMPTY 0x1F0404D4,0x00000000 ++#define SRM_DI0_SW_GEN1_5__FULL 0x1F0404D4,0xffffffff ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5 0x1F0404D4,0x60000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5 0x1F0404D4,0x10000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5 0x1F0404D4,0x0E000000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5 0x1F0404D4,0x01FF0000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5 0x1F0404D4,0x00007000 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5 0x1F0404D4,0x00000E00 ++#define SRM_DI0_SW_GEN1_5__DI0_CNT_UP_5 0x1F0404D4,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_6__ADDR 0x1F0404D8 ++#define SRM_DI0_SW_GEN1_6__EMPTY 0x1F0404D8,0x00000000 ++#define SRM_DI0_SW_GEN1_6__FULL 0x1F0404D8,0xffffffff ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6 0x1F0404D8,0x60000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6 0x1F0404D8,0x10000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6 0x1F0404D8,0x0E000000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6 0x1F0404D8,0x01FF0000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6 0x1F0404D8,0x00007000 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6 0x1F0404D8,0x00000E00 ++#define SRM_DI0_SW_GEN1_6__DI0_CNT_UP_6 0x1F0404D8,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_7__ADDR 0x1F0404DC ++#define SRM_DI0_SW_GEN1_7__EMPTY 0x1F0404DC,0x00000000 ++#define SRM_DI0_SW_GEN1_7__FULL 0x1F0404DC,0xffffffff ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7 0x1F0404DC,0x60000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7 0x1F0404DC,0x10000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7 0x1F0404DC,0x0E000000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7 0x1F0404DC,0x01FF0000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7 0x1F0404DC,0x00007000 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7 0x1F0404DC,0x00000E00 ++#define SRM_DI0_SW_GEN1_7__DI0_CNT_UP_7 0x1F0404DC,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_8__ADDR 0x1F0404E0 ++#define SRM_DI0_SW_GEN1_8__EMPTY 0x1F0404E0,0x00000000 ++#define SRM_DI0_SW_GEN1_8__FULL 0x1F0404E0,0xffffffff ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8 0x1F0404E0,0x60000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8 0x1F0404E0,0x10000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8 0x1F0404E0,0x0E000000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8 0x1F0404E0,0x01FF0000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8 0x1F0404E0,0x00007000 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8 0x1F0404E0,0x00000E00 ++#define SRM_DI0_SW_GEN1_8__DI0_CNT_UP_8 0x1F0404E0,0x000001FF ++ ++#define SRM_DI0_SW_GEN1_9__ADDR 0x1F0404E4 ++#define SRM_DI0_SW_GEN1_9__EMPTY 0x1F0404E4,0x00000000 ++#define SRM_DI0_SW_GEN1_9__FULL 0x1F0404E4,0xffffffff ++#define SRM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1F0404E4,0xE0000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1F0404E4,0x10000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1F0404E4,0x0E000000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1F0404E4,0x01FF0000 ++#define SRM_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1F0404E4,0x00008000 ++#define SRM_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1F0404E4,0x000001FF ++ ++#define SRM_DI0_SYNC_AS_GEN__ADDR 0x1F0404E8 ++#define SRM_DI0_SYNC_AS_GEN__EMPTY 0x1F0404E8,0x00000000 ++#define SRM_DI0_SYNC_AS_GEN__FULL 0x1F0404E8,0xffffffff ++#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1F0404E8,0x10000000 ++#define SRM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1F0404E8,0x0000E000 ++#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1F0404E8,0x00000FFF ++ ++#define SRM_DI0_DW_GEN_0__ADDR 0x1F0404EC ++#define SRM_DI0_DW_GEN_0__EMPTY 0x1F0404EC,0x00000000 ++#define SRM_DI0_DW_GEN_0__FULL 0x1F0404EC,0xffffffff ++#define SRM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1F0404EC,0xFF000000 ++#define SRM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F0404EC,0x00FF0000 ++#define SRM_DI0_DW_GEN_0__DI0_CST_0 0x1F0404EC,0x0000C000 ++#define SRM_DI0_DW_GEN_0__DI0_PT_6_0 0x1F0404EC,0x00003000 ++#define SRM_DI0_DW_GEN_0__DI0_PT_5_0 0x1F0404EC,0x00000C00 ++#define SRM_DI0_DW_GEN_0__DI0_PT_4_0 0x1F0404EC,0x00000300 ++#define SRM_DI0_DW_GEN_0__DI0_PT_3_0 0x1F0404EC,0x000000C0 ++#define SRM_DI0_DW_GEN_0__DI0_PT_2_0 0x1F0404EC,0x00000030 ++#define SRM_DI0_DW_GEN_0__DI0_PT_1_0 0x1F0404EC,0x0000000C ++#define SRM_DI0_DW_GEN_0__DI0_PT_0_0 0x1F0404EC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_0__ADDR 0x1F0404EC ++#define SRM_DI0_DW_GEN_0__EMPTY 0x1F0404EC,0x00000000 ++#define SRM_DI0_DW_GEN_0__FULL 0x1F0404EC,0xffffffff ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1F0404EC,0xFF000000 ++#define SRM_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1F0404EC,0x00FF0000 ++#define SRM_DI0_DW_GEN_0__DI0_CST_0 0x1F0404EC,0x0000C000 ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F0404EC,0x000001F0 ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1F0404EC,0x0000000C ++#define SRM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1F0404EC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_1__ADDR 0x1F0404F0 ++#define SRM_DI0_DW_GEN_1__EMPTY 0x1F0404F0,0x00000000 ++#define SRM_DI0_DW_GEN_1__FULL 0x1F0404F0,0xffffffff ++#define SRM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1F0404F0,0xFF000000 ++#define SRM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F0404F0,0x00FF0000 ++#define SRM_DI0_DW_GEN_1__DI0_CST_1 0x1F0404F0,0x0000C000 ++#define SRM_DI0_DW_GEN_1__DI0_PT_6_1 0x1F0404F0,0x00003000 ++#define SRM_DI0_DW_GEN_1__DI0_PT_5_1 0x1F0404F0,0x00000C00 ++#define SRM_DI0_DW_GEN_1__DI0_PT_4_1 0x1F0404F0,0x00000300 ++#define SRM_DI0_DW_GEN_1__DI0_PT_3_1 0x1F0404F0,0x000000C0 ++#define SRM_DI0_DW_GEN_1__DI0_PT_2_1 0x1F0404F0,0x00000030 ++#define SRM_DI0_DW_GEN_1__DI0_PT_1_1 0x1F0404F0,0x0000000C ++#define SRM_DI0_DW_GEN_1__DI0_PT_0_1 0x1F0404F0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_1__ADDR 0x1F0404F0 ++#define SRM_DI0_DW_GEN_1__EMPTY 0x1F0404F0,0x00000000 ++#define SRM_DI0_DW_GEN_1__FULL 0x1F0404F0,0xffffffff ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1F0404F0,0xFF000000 ++#define SRM_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1F0404F0,0x00FF0000 ++#define SRM_DI0_DW_GEN_1__DI0_CST_1 0x1F0404F0,0x0000C000 ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F0404F0,0x000001F0 ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1F0404F0,0x0000000C ++#define SRM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1F0404F0,0x00000003 ++ ++#define SRM_DI0_DW_GEN_2__ADDR 0x1F0404F4 ++#define SRM_DI0_DW_GEN_2__EMPTY 0x1F0404F4,0x00000000 ++#define SRM_DI0_DW_GEN_2__FULL 0x1F0404F4,0xffffffff ++#define SRM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1F0404F4,0xFF000000 ++#define SRM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F0404F4,0x00FF0000 ++#define SRM_DI0_DW_GEN_2__DI0_CST_2 0x1F0404F4,0x0000C000 ++#define SRM_DI0_DW_GEN_2__DI0_PT_6_2 0x1F0404F4,0x00003000 ++#define SRM_DI0_DW_GEN_2__DI0_PT_5_2 0x1F0404F4,0x00000C00 ++#define SRM_DI0_DW_GEN_2__DI0_PT_4_2 0x1F0404F4,0x00000300 ++#define SRM_DI0_DW_GEN_2__DI0_PT_3_2 0x1F0404F4,0x000000C0 ++#define SRM_DI0_DW_GEN_2__DI0_PT_2_2 0x1F0404F4,0x00000030 ++#define SRM_DI0_DW_GEN_2__DI0_PT_1_2 0x1F0404F4,0x0000000C ++#define SRM_DI0_DW_GEN_2__DI0_PT_0_2 0x1F0404F4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_2__ADDR 0x1F0404F4 ++#define SRM_DI0_DW_GEN_2__EMPTY 0x1F0404F4,0x00000000 ++#define SRM_DI0_DW_GEN_2__FULL 0x1F0404F4,0xffffffff ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1F0404F4,0xFF000000 ++#define SRM_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1F0404F4,0x00FF0000 ++#define SRM_DI0_DW_GEN_2__DI0_CST_2 0x1F0404F4,0x0000C000 ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F0404F4,0x000001F0 ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1F0404F4,0x0000000C ++#define SRM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1F0404F4,0x00000003 ++ ++#define SRM_DI0_DW_GEN_3__ADDR 0x1F0404F8 ++#define SRM_DI0_DW_GEN_3__EMPTY 0x1F0404F8,0x00000000 ++#define SRM_DI0_DW_GEN_3__FULL 0x1F0404F8,0xffffffff ++#define SRM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1F0404F8,0xFF000000 ++#define SRM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F0404F8,0x00FF0000 ++#define SRM_DI0_DW_GEN_3__DI0_CST_3 0x1F0404F8,0x0000C000 ++#define SRM_DI0_DW_GEN_3__DI0_PT_6_3 0x1F0404F8,0x00003000 ++#define SRM_DI0_DW_GEN_3__DI0_PT_5_3 0x1F0404F8,0x00000C00 ++#define SRM_DI0_DW_GEN_3__DI0_PT_4_3 0x1F0404F8,0x00000300 ++#define SRM_DI0_DW_GEN_3__DI0_PT_3_3 0x1F0404F8,0x000000C0 ++#define SRM_DI0_DW_GEN_3__DI0_PT_2_3 0x1F0404F8,0x00000030 ++#define SRM_DI0_DW_GEN_3__DI0_PT_1_3 0x1F0404F8,0x0000000C ++#define SRM_DI0_DW_GEN_3__DI0_PT_0_3 0x1F0404F8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_3__ADDR 0x1F0404F8 ++#define SRM_DI0_DW_GEN_3__EMPTY 0x1F0404F8,0x00000000 ++#define SRM_DI0_DW_GEN_3__FULL 0x1F0404F8,0xffffffff ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1F0404F8,0xFF000000 ++#define SRM_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1F0404F8,0x00FF0000 ++#define SRM_DI0_DW_GEN_3__DI0_CST_3 0x1F0404F8,0x0000C000 ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F0404F8,0x000001F0 ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1F0404F8,0x0000000C ++#define SRM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1F0404F8,0x00000003 ++ ++#define SRM_DI0_DW_GEN_4__ADDR 0x1F0404FC ++#define SRM_DI0_DW_GEN_4__EMPTY 0x1F0404FC,0x00000000 ++#define SRM_DI0_DW_GEN_4__FULL 0x1F0404FC,0xffffffff ++#define SRM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1F0404FC,0xFF000000 ++#define SRM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F0404FC,0x00FF0000 ++#define SRM_DI0_DW_GEN_4__DI0_CST_4 0x1F0404FC,0x0000C000 ++#define SRM_DI0_DW_GEN_4__DI0_PT_6_4 0x1F0404FC,0x00003000 ++#define SRM_DI0_DW_GEN_4__DI0_PT_5_4 0x1F0404FC,0x00000C00 ++#define SRM_DI0_DW_GEN_4__DI0_PT_4_4 0x1F0404FC,0x00000300 ++#define SRM_DI0_DW_GEN_4__DI0_PT_3_4 0x1F0404FC,0x000000C0 ++#define SRM_DI0_DW_GEN_4__DI0_PT_2_4 0x1F0404FC,0x00000030 ++#define SRM_DI0_DW_GEN_4__DI0_PT_1_4 0x1F0404FC,0x0000000C ++#define SRM_DI0_DW_GEN_4__DI0_PT_0_4 0x1F0404FC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_4__ADDR 0x1F0404FC ++#define SRM_DI0_DW_GEN_4__EMPTY 0x1F0404FC,0x00000000 ++#define SRM_DI0_DW_GEN_4__FULL 0x1F0404FC,0xffffffff ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1F0404FC,0xFF000000 ++#define SRM_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1F0404FC,0x00FF0000 ++#define SRM_DI0_DW_GEN_4__DI0_CST_4 0x1F0404FC,0x0000C000 ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F0404FC,0x000001F0 ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1F0404FC,0x0000000C ++#define SRM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1F0404FC,0x00000003 ++ ++#define SRM_DI0_DW_GEN_5__ADDR 0x1F040500 ++#define SRM_DI0_DW_GEN_5__EMPTY 0x1F040500,0x00000000 ++#define SRM_DI0_DW_GEN_5__FULL 0x1F040500,0xffffffff ++#define SRM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1F040500,0xFF000000 ++#define SRM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F040500,0x00FF0000 ++#define SRM_DI0_DW_GEN_5__DI0_CST_5 0x1F040500,0x0000C000 ++#define SRM_DI0_DW_GEN_5__DI0_PT_6_5 0x1F040500,0x00003000 ++#define SRM_DI0_DW_GEN_5__DI0_PT_5_5 0x1F040500,0x00000C00 ++#define SRM_DI0_DW_GEN_5__DI0_PT_4_5 0x1F040500,0x00000300 ++#define SRM_DI0_DW_GEN_5__DI0_PT_3_5 0x1F040500,0x000000C0 ++#define SRM_DI0_DW_GEN_5__DI0_PT_2_5 0x1F040500,0x00000030 ++#define SRM_DI0_DW_GEN_5__DI0_PT_1_5 0x1F040500,0x0000000C ++#define SRM_DI0_DW_GEN_5__DI0_PT_0_5 0x1F040500,0x00000003 ++ ++#define SRM_DI0_DW_GEN_5__ADDR 0x1F040500 ++#define SRM_DI0_DW_GEN_5__EMPTY 0x1F040500,0x00000000 ++#define SRM_DI0_DW_GEN_5__FULL 0x1F040500,0xffffffff ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1F040500,0xFF000000 ++#define SRM_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1F040500,0x00FF0000 ++#define SRM_DI0_DW_GEN_5__DI0_CST_5 0x1F040500,0x0000C000 ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F040500,0x000001F0 ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1F040500,0x0000000C ++#define SRM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1F040500,0x00000003 ++ ++#define SRM_DI0_DW_GEN_6__ADDR 0x1F040504 ++#define SRM_DI0_DW_GEN_6__EMPTY 0x1F040504,0x00000000 ++#define SRM_DI0_DW_GEN_6__FULL 0x1F040504,0xffffffff ++#define SRM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1F040504,0xFF000000 ++#define SRM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F040504,0x00FF0000 ++#define SRM_DI0_DW_GEN_6__DI0_CST_6 0x1F040504,0x0000C000 ++#define SRM_DI0_DW_GEN_6__DI0_PT_6_6 0x1F040504,0x00003000 ++#define SRM_DI0_DW_GEN_6__DI0_PT_5_6 0x1F040504,0x00000C00 ++#define SRM_DI0_DW_GEN_6__DI0_PT_4_6 0x1F040504,0x00000300 ++#define SRM_DI0_DW_GEN_6__DI0_PT_3_6 0x1F040504,0x000000C0 ++#define SRM_DI0_DW_GEN_6__DI0_PT_2_6 0x1F040504,0x00000030 ++#define SRM_DI0_DW_GEN_6__DI0_PT_1_6 0x1F040504,0x0000000C ++#define SRM_DI0_DW_GEN_6__DI0_PT_0_6 0x1F040504,0x00000003 ++ ++#define SRM_DI0_DW_GEN_6__ADDR 0x1F040504 ++#define SRM_DI0_DW_GEN_6__EMPTY 0x1F040504,0x00000000 ++#define SRM_DI0_DW_GEN_6__FULL 0x1F040504,0xffffffff ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1F040504,0xFF000000 ++#define SRM_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1F040504,0x00FF0000 ++#define SRM_DI0_DW_GEN_6__DI0_CST_6 0x1F040504,0x0000C000 ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F040504,0x000001F0 ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1F040504,0x0000000C ++#define SRM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1F040504,0x00000003 ++ ++#define SRM_DI0_DW_GEN_7__ADDR 0x1F040508 ++#define SRM_DI0_DW_GEN_7__EMPTY 0x1F040508,0x00000000 ++#define SRM_DI0_DW_GEN_7__FULL 0x1F040508,0xffffffff ++#define SRM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1F040508,0xFF000000 ++#define SRM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F040508,0x00FF0000 ++#define SRM_DI0_DW_GEN_7__DI0_CST_7 0x1F040508,0x0000C000 ++#define SRM_DI0_DW_GEN_7__DI0_PT_6_7 0x1F040508,0x00003000 ++#define SRM_DI0_DW_GEN_7__DI0_PT_5_7 0x1F040508,0x00000C00 ++#define SRM_DI0_DW_GEN_7__DI0_PT_4_7 0x1F040508,0x00000300 ++#define SRM_DI0_DW_GEN_7__DI0_PT_3_7 0x1F040508,0x000000C0 ++#define SRM_DI0_DW_GEN_7__DI0_PT_2_7 0x1F040508,0x00000030 ++#define SRM_DI0_DW_GEN_7__DI0_PT_1_7 0x1F040508,0x0000000C ++#define SRM_DI0_DW_GEN_7__DI0_PT_0_7 0x1F040508,0x00000003 ++ ++#define SRM_DI0_DW_GEN_7__ADDR 0x1F040508 ++#define SRM_DI0_DW_GEN_7__EMPTY 0x1F040508,0x00000000 ++#define SRM_DI0_DW_GEN_7__FULL 0x1F040508,0xffffffff ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1F040508,0xFF000000 ++#define SRM_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1F040508,0x00FF0000 ++#define SRM_DI0_DW_GEN_7__DI0_CST_7 0x1F040508,0x0000C000 ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F040508,0x000001F0 ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1F040508,0x0000000C ++#define SRM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1F040508,0x00000003 ++ ++#define SRM_DI0_DW_GEN_8__ADDR 0x1F04050C ++#define SRM_DI0_DW_GEN_8__EMPTY 0x1F04050C,0x00000000 ++#define SRM_DI0_DW_GEN_8__FULL 0x1F04050C,0xffffffff ++#define SRM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1F04050C,0xFF000000 ++#define SRM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F04050C,0x00FF0000 ++#define SRM_DI0_DW_GEN_8__DI0_CST_8 0x1F04050C,0x0000C000 ++#define SRM_DI0_DW_GEN_8__DI0_PT_6_8 0x1F04050C,0x00003000 ++#define SRM_DI0_DW_GEN_8__DI0_PT_5_8 0x1F04050C,0x00000C00 ++#define SRM_DI0_DW_GEN_8__DI0_PT_4_8 0x1F04050C,0x00000300 ++#define SRM_DI0_DW_GEN_8__DI0_PT_3_8 0x1F04050C,0x000000C0 ++#define SRM_DI0_DW_GEN_8__DI0_PT_2_8 0x1F04050C,0x00000030 ++#define SRM_DI0_DW_GEN_8__DI0_PT_1_8 0x1F04050C,0x0000000C ++#define SRM_DI0_DW_GEN_8__DI0_PT_0_8 0x1F04050C,0x00000003 ++ ++#define SRM_DI0_DW_GEN_8__ADDR 0x1F04050C ++#define SRM_DI0_DW_GEN_8__EMPTY 0x1F04050C,0x00000000 ++#define SRM_DI0_DW_GEN_8__FULL 0x1F04050C,0xffffffff ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1F04050C,0xFF000000 ++#define SRM_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1F04050C,0x00FF0000 ++#define SRM_DI0_DW_GEN_8__DI0_CST_8 0x1F04050C,0x0000C000 ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F04050C,0x000001F0 ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1F04050C,0x0000000C ++#define SRM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1F04050C,0x00000003 ++ ++#define SRM_DI0_DW_GEN_9__ADDR 0x1F040510 ++#define SRM_DI0_DW_GEN_9__EMPTY 0x1F040510,0x00000000 ++#define SRM_DI0_DW_GEN_9__FULL 0x1F040510,0xffffffff ++#define SRM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1F040510,0xFF000000 ++#define SRM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F040510,0x00FF0000 ++#define SRM_DI0_DW_GEN_9__DI0_CST_9 0x1F040510,0x0000C000 ++#define SRM_DI0_DW_GEN_9__DI0_PT_6_9 0x1F040510,0x00003000 ++#define SRM_DI0_DW_GEN_9__DI0_PT_5_9 0x1F040510,0x00000C00 ++#define SRM_DI0_DW_GEN_9__DI0_PT_4_9 0x1F040510,0x00000300 ++#define SRM_DI0_DW_GEN_9__DI0_PT_3_9 0x1F040510,0x000000C0 ++#define SRM_DI0_DW_GEN_9__DI0_PT_2_9 0x1F040510,0x00000030 ++#define SRM_DI0_DW_GEN_9__DI0_PT_1_9 0x1F040510,0x0000000C ++#define SRM_DI0_DW_GEN_9__DI0_PT_0_9 0x1F040510,0x00000003 ++ ++#define SRM_DI0_DW_GEN_9__ADDR 0x1F040510 ++#define SRM_DI0_DW_GEN_9__EMPTY 0x1F040510,0x00000000 ++#define SRM_DI0_DW_GEN_9__FULL 0x1F040510,0xffffffff ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1F040510,0xFF000000 ++#define SRM_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1F040510,0x00FF0000 ++#define SRM_DI0_DW_GEN_9__DI0_CST_9 0x1F040510,0x0000C000 ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F040510,0x000001F0 ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1F040510,0x0000000C ++#define SRM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1F040510,0x00000003 ++ ++#define SRM_DI0_DW_GEN_10__ADDR 0x1F040514 ++#define SRM_DI0_DW_GEN_10__EMPTY 0x1F040514,0x00000000 ++#define SRM_DI0_DW_GEN_10__FULL 0x1F040514,0xffffffff ++#define SRM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1F040514,0xFF000000 ++#define SRM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F040514,0x00FF0000 ++#define SRM_DI0_DW_GEN_10__DI0_CST_10 0x1F040514,0x0000C000 ++#define SRM_DI0_DW_GEN_10__DI0_PT_6_10 0x1F040514,0x00003000 ++#define SRM_DI0_DW_GEN_10__DI0_PT_5_10 0x1F040514,0x00000C00 ++#define SRM_DI0_DW_GEN_10__DI0_PT_4_10 0x1F040514,0x00000300 ++#define SRM_DI0_DW_GEN_10__DI0_PT_3_10 0x1F040514,0x000000C0 ++#define SRM_DI0_DW_GEN_10__DI0_PT_2_10 0x1F040514,0x00000030 ++#define SRM_DI0_DW_GEN_10__DI0_PT_1_10 0x1F040514,0x0000000C ++#define SRM_DI0_DW_GEN_10__DI0_PT_0_10 0x1F040514,0x00000003 ++ ++#define SRM_DI0_DW_GEN_10__ADDR 0x1F040514 ++#define SRM_DI0_DW_GEN_10__EMPTY 0x1F040514,0x00000000 ++#define SRM_DI0_DW_GEN_10__FULL 0x1F040514,0xffffffff ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1F040514,0xFF000000 ++#define SRM_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1F040514,0x00FF0000 ++#define SRM_DI0_DW_GEN_10__DI0_CST_10 0x1F040514,0x0000C000 ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040514,0x000001F0 ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1F040514,0x0000000C ++#define SRM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1F040514,0x00000003 ++ ++#define SRM_DI0_DW_GEN_11__ADDR 0x1F040518 ++#define SRM_DI0_DW_GEN_11__EMPTY 0x1F040518,0x00000000 ++#define SRM_DI0_DW_GEN_11__FULL 0x1F040518,0xffffffff ++#define SRM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1F040518,0xFF000000 ++#define SRM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F040518,0x00FF0000 ++#define SRM_DI0_DW_GEN_11__DI0_CST_11 0x1F040518,0x0000C000 ++#define SRM_DI0_DW_GEN_11__DI0_PT_6_11 0x1F040518,0x00003000 ++#define SRM_DI0_DW_GEN_11__DI0_PT_5_11 0x1F040518,0x00000C00 ++#define SRM_DI0_DW_GEN_11__DI0_PT_4_11 0x1F040518,0x00000300 ++#define SRM_DI0_DW_GEN_11__DI0_PT_3_11 0x1F040518,0x000000C0 ++#define SRM_DI0_DW_GEN_11__DI0_PT_2_11 0x1F040518,0x00000030 ++#define SRM_DI0_DW_GEN_11__DI0_PT_1_11 0x1F040518,0x0000000C ++#define SRM_DI0_DW_GEN_11__DI0_PT_0_11 0x1F040518,0x00000003 ++ ++#define SRM_DI0_DW_GEN_11__ADDR 0x1F040518 ++#define SRM_DI0_DW_GEN_11__EMPTY 0x1F040518,0x00000000 ++#define SRM_DI0_DW_GEN_11__FULL 0x1F040518,0xffffffff ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1F040518,0xFF000000 ++#define SRM_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1F040518,0x00FF0000 ++#define SRM_DI0_DW_GEN_11__DI0_CST_11 0x1F040518,0x0000C000 ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040518,0x000001F0 ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1F040518,0x0000000C ++#define SRM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1F040518,0x00000003 ++ ++#define SRM_DI0_DW_SET0_0__ADDR 0x1F04051C ++#define SRM_DI0_DW_SET0_0__EMPTY 0x1F04051C,0x00000000 ++#define SRM_DI0_DW_SET0_0__FULL 0x1F04051C,0xffffffff ++#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0 0x1F04051C,0x01FF0000 ++#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0 0x1F04051C,0x000001FF ++ ++#define SRM_DI0_DW_SET0_1__ADDR 0x1F040520 ++#define SRM_DI0_DW_SET0_1__EMPTY 0x1F040520,0x00000000 ++#define SRM_DI0_DW_SET0_1__FULL 0x1F040520,0xffffffff ++#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1 0x1F040520,0x01FF0000 ++#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1 0x1F040520,0x000001FF ++ ++#define SRM_DI0_DW_SET0_2__ADDR 0x1F040524 ++#define SRM_DI0_DW_SET0_2__EMPTY 0x1F040524,0x00000000 ++#define SRM_DI0_DW_SET0_2__FULL 0x1F040524,0xffffffff ++#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2 0x1F040524,0x01FF0000 ++#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2 0x1F040524,0x000001FF ++ ++#define SRM_DI0_DW_SET0_3__ADDR 0x1F040528 ++#define SRM_DI0_DW_SET0_3__EMPTY 0x1F040528,0x00000000 ++#define SRM_DI0_DW_SET0_3__FULL 0x1F040528,0xffffffff ++#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3 0x1F040528,0x01FF0000 ++#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3 0x1F040528,0x000001FF ++ ++#define SRM_DI0_DW_SET0_4__ADDR 0x1F04052C ++#define SRM_DI0_DW_SET0_4__EMPTY 0x1F04052C,0x00000000 ++#define SRM_DI0_DW_SET0_4__FULL 0x1F04052C,0xffffffff ++#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4 0x1F04052C,0x01FF0000 ++#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4 0x1F04052C,0x000001FF ++ ++#define SRM_DI0_DW_SET0_5__ADDR 0x1F040530 ++#define SRM_DI0_DW_SET0_5__EMPTY 0x1F040530,0x00000000 ++#define SRM_DI0_DW_SET0_5__FULL 0x1F040530,0xffffffff ++#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5 0x1F040530,0x01FF0000 ++#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5 0x1F040530,0x000001FF ++ ++#define SRM_DI0_DW_SET0_6__ADDR 0x1F040534 ++#define SRM_DI0_DW_SET0_6__EMPTY 0x1F040534,0x00000000 ++#define SRM_DI0_DW_SET0_6__FULL 0x1F040534,0xffffffff ++#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6 0x1F040534,0x01FF0000 ++#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6 0x1F040534,0x000001FF ++ ++#define SRM_DI0_DW_SET0_7__ADDR 0x1F040538 ++#define SRM_DI0_DW_SET0_7__EMPTY 0x1F040538,0x00000000 ++#define SRM_DI0_DW_SET0_7__FULL 0x1F040538,0xffffffff ++#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7 0x1F040538,0x01FF0000 ++#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7 0x1F040538,0x000001FF ++ ++#define SRM_DI0_DW_SET0_8__ADDR 0x1F04053C ++#define SRM_DI0_DW_SET0_8__EMPTY 0x1F04053C,0x00000000 ++#define SRM_DI0_DW_SET0_8__FULL 0x1F04053C,0xffffffff ++#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8 0x1F04053C,0x01FF0000 ++#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8 0x1F04053C,0x000001FF ++ ++#define SRM_DI0_DW_SET0_9__ADDR 0x1F040540 ++#define SRM_DI0_DW_SET0_9__EMPTY 0x1F040540,0x00000000 ++#define SRM_DI0_DW_SET0_9__FULL 0x1F040540,0xffffffff ++#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9 0x1F040540,0x01FF0000 ++#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9 0x1F040540,0x000001FF ++ ++#define SRM_DI0_DW_SET0_10__ADDR 0x1F040544 ++#define SRM_DI0_DW_SET0_10__EMPTY 0x1F040544,0x00000000 ++#define SRM_DI0_DW_SET0_10__FULL 0x1F040544,0xffffffff ++#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10 0x1F040544,0x01FF0000 ++#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10 0x1F040544,0x000001FF ++ ++#define SRM_DI0_DW_SET0_11__ADDR 0x1F040548 ++#define SRM_DI0_DW_SET0_11__EMPTY 0x1F040548,0x00000000 ++#define SRM_DI0_DW_SET0_11__FULL 0x1F040548,0xffffffff ++#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11 0x1F040548,0x01FF0000 ++#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11 0x1F040548,0x000001FF ++ ++#define SRM_DI0_DW_SET1_0__ADDR 0x1F04054C ++#define SRM_DI0_DW_SET1_0__EMPTY 0x1F04054C,0x00000000 ++#define SRM_DI0_DW_SET1_0__FULL 0x1F04054C,0xffffffff ++#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0 0x1F04054C,0x01FF0000 ++#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0 0x1F04054C,0x000001FF ++ ++#define SRM_DI0_DW_SET1_1__ADDR 0x1F040550 ++#define SRM_DI0_DW_SET1_1__EMPTY 0x1F040550,0x00000000 ++#define SRM_DI0_DW_SET1_1__FULL 0x1F040550,0xffffffff ++#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1 0x1F040550,0x01FF0000 ++#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1 0x1F040550,0x000001FF ++ ++#define SRM_DI0_DW_SET1_2__ADDR 0x1F040554 ++#define SRM_DI0_DW_SET1_2__EMPTY 0x1F040554,0x00000000 ++#define SRM_DI0_DW_SET1_2__FULL 0x1F040554,0xffffffff ++#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2 0x1F040554,0x01FF0000 ++#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2 0x1F040554,0x000001FF ++ ++#define SRM_DI0_DW_SET1_3__ADDR 0x1F040558 ++#define SRM_DI0_DW_SET1_3__EMPTY 0x1F040558,0x00000000 ++#define SRM_DI0_DW_SET1_3__FULL 0x1F040558,0xffffffff ++#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3 0x1F040558,0x01FF0000 ++#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3 0x1F040558,0x000001FF ++ ++#define SRM_DI0_DW_SET1_4__ADDR 0x1F04055C ++#define SRM_DI0_DW_SET1_4__EMPTY 0x1F04055C,0x00000000 ++#define SRM_DI0_DW_SET1_4__FULL 0x1F04055C,0xffffffff ++#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4 0x1F04055C,0x01FF0000 ++#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4 0x1F04055C,0x000001FF ++ ++#define SRM_DI0_DW_SET1_5__ADDR 0x1F040560 ++#define SRM_DI0_DW_SET1_5__EMPTY 0x1F040560,0x00000000 ++#define SRM_DI0_DW_SET1_5__FULL 0x1F040560,0xffffffff ++#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5 0x1F040560,0x01FF0000 ++#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5 0x1F040560,0x000001FF ++ ++#define SRM_DI0_DW_SET1_6__ADDR 0x1F040564 ++#define SRM_DI0_DW_SET1_6__EMPTY 0x1F040564,0x00000000 ++#define SRM_DI0_DW_SET1_6__FULL 0x1F040564,0xffffffff ++#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6 0x1F040564,0x01FF0000 ++#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6 0x1F040564,0x000001FF ++ ++#define SRM_DI0_DW_SET1_7__ADDR 0x1F040568 ++#define SRM_DI0_DW_SET1_7__EMPTY 0x1F040568,0x00000000 ++#define SRM_DI0_DW_SET1_7__FULL 0x1F040568,0xffffffff ++#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7 0x1F040568,0x01FF0000 ++#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7 0x1F040568,0x000001FF ++ ++#define SRM_DI0_DW_SET1_8__ADDR 0x1F04056C ++#define SRM_DI0_DW_SET1_8__EMPTY 0x1F04056C,0x00000000 ++#define SRM_DI0_DW_SET1_8__FULL 0x1F04056C,0xffffffff ++#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8 0x1F04056C,0x01FF0000 ++#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8 0x1F04056C,0x000001FF ++ ++#define SRM_DI0_DW_SET1_9__ADDR 0x1F040570 ++#define SRM_DI0_DW_SET1_9__EMPTY 0x1F040570,0x00000000 ++#define SRM_DI0_DW_SET1_9__FULL 0x1F040570,0xffffffff ++#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9 0x1F040570,0x01FF0000 ++#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9 0x1F040570,0x000001FF ++ ++#define SRM_DI0_DW_SET1_10__ADDR 0x1F040574 ++#define SRM_DI0_DW_SET1_10__EMPTY 0x1F040574,0x00000000 ++#define SRM_DI0_DW_SET1_10__FULL 0x1F040574,0xffffffff ++#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10 0x1F040574,0x01FF0000 ++#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10 0x1F040574,0x000001FF ++ ++#define SRM_DI0_DW_SET1_11__ADDR 0x1F040578 ++#define SRM_DI0_DW_SET1_11__EMPTY 0x1F040578,0x00000000 ++#define SRM_DI0_DW_SET1_11__FULL 0x1F040578,0xffffffff ++#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11 0x1F040578,0x01FF0000 ++#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11 0x1F040578,0x000001FF ++ ++#define SRM_DI0_DW_SET2_0__ADDR 0x1F04057C ++#define SRM_DI0_DW_SET2_0__EMPTY 0x1F04057C,0x00000000 ++#define SRM_DI0_DW_SET2_0__FULL 0x1F04057C,0xffffffff ++#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0 0x1F04057C,0x01FF0000 ++#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0 0x1F04057C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_1__ADDR 0x1F040580 ++#define SRM_DI0_DW_SET2_1__EMPTY 0x1F040580,0x00000000 ++#define SRM_DI0_DW_SET2_1__FULL 0x1F040580,0xffffffff ++#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1 0x1F040580,0x01FF0000 ++#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1 0x1F040580,0x000001FF ++ ++#define SRM_DI0_DW_SET2_2__ADDR 0x1F040584 ++#define SRM_DI0_DW_SET2_2__EMPTY 0x1F040584,0x00000000 ++#define SRM_DI0_DW_SET2_2__FULL 0x1F040584,0xffffffff ++#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2 0x1F040584,0x01FF0000 ++#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2 0x1F040584,0x000001FF ++ ++#define SRM_DI0_DW_SET2_3__ADDR 0x1F040588 ++#define SRM_DI0_DW_SET2_3__EMPTY 0x1F040588,0x00000000 ++#define SRM_DI0_DW_SET2_3__FULL 0x1F040588,0xffffffff ++#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3 0x1F040588,0x01FF0000 ++#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3 0x1F040588,0x000001FF ++ ++#define SRM_DI0_DW_SET2_4__ADDR 0x1F04058C ++#define SRM_DI0_DW_SET2_4__EMPTY 0x1F04058C,0x00000000 ++#define SRM_DI0_DW_SET2_4__FULL 0x1F04058C,0xffffffff ++#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4 0x1F04058C,0x01FF0000 ++#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4 0x1F04058C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_5__ADDR 0x1F040590 ++#define SRM_DI0_DW_SET2_5__EMPTY 0x1F040590,0x00000000 ++#define SRM_DI0_DW_SET2_5__FULL 0x1F040590,0xffffffff ++#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5 0x1F040590,0x01FF0000 ++#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5 0x1F040590,0x000001FF ++ ++#define SRM_DI0_DW_SET2_6__ADDR 0x1F040594 ++#define SRM_DI0_DW_SET2_6__EMPTY 0x1F040594,0x00000000 ++#define SRM_DI0_DW_SET2_6__FULL 0x1F040594,0xffffffff ++#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6 0x1F040594,0x01FF0000 ++#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6 0x1F040594,0x000001FF ++ ++#define SRM_DI0_DW_SET2_7__ADDR 0x1F040598 ++#define SRM_DI0_DW_SET2_7__EMPTY 0x1F040598,0x00000000 ++#define SRM_DI0_DW_SET2_7__FULL 0x1F040598,0xffffffff ++#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7 0x1F040598,0x01FF0000 ++#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7 0x1F040598,0x000001FF ++ ++#define SRM_DI0_DW_SET2_8__ADDR 0x1F04059C ++#define SRM_DI0_DW_SET2_8__EMPTY 0x1F04059C,0x00000000 ++#define SRM_DI0_DW_SET2_8__FULL 0x1F04059C,0xffffffff ++#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8 0x1F04059C,0x01FF0000 ++#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8 0x1F04059C,0x000001FF ++ ++#define SRM_DI0_DW_SET2_9__ADDR 0x1F0405A0 ++#define SRM_DI0_DW_SET2_9__EMPTY 0x1F0405A0,0x00000000 ++#define SRM_DI0_DW_SET2_9__FULL 0x1F0405A0,0xffffffff ++#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9 0x1F0405A0,0x01FF0000 ++#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9 0x1F0405A0,0x000001FF ++ ++#define SRM_DI0_DW_SET2_10__ADDR 0x1F0405A4 ++#define SRM_DI0_DW_SET2_10__EMPTY 0x1F0405A4,0x00000000 ++#define SRM_DI0_DW_SET2_10__FULL 0x1F0405A4,0xffffffff ++#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10 0x1F0405A4,0x01FF0000 ++#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10 0x1F0405A4,0x000001FF ++ ++#define SRM_DI0_DW_SET2_11__ADDR 0x1F0405A8 ++#define SRM_DI0_DW_SET2_11__EMPTY 0x1F0405A8,0x00000000 ++#define SRM_DI0_DW_SET2_11__FULL 0x1F0405A8,0xffffffff ++#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11 0x1F0405A8,0x01FF0000 ++#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11 0x1F0405A8,0x000001FF ++ ++#define SRM_DI0_DW_SET3_0__ADDR 0x1F0405AC ++#define SRM_DI0_DW_SET3_0__EMPTY 0x1F0405AC,0x00000000 ++#define SRM_DI0_DW_SET3_0__FULL 0x1F0405AC,0xffffffff ++#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0 0x1F0405AC,0x01FF0000 ++#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0 0x1F0405AC,0x000001FF ++ ++#define SRM_DI0_DW_SET3_1__ADDR 0x1F0405B0 ++#define SRM_DI0_DW_SET3_1__EMPTY 0x1F0405B0,0x00000000 ++#define SRM_DI0_DW_SET3_1__FULL 0x1F0405B0,0xffffffff ++#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1 0x1F0405B0,0x01FF0000 ++#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1 0x1F0405B0,0x000001FF ++ ++#define SRM_DI0_DW_SET3_2__ADDR 0x1F0405B4 ++#define SRM_DI0_DW_SET3_2__EMPTY 0x1F0405B4,0x00000000 ++#define SRM_DI0_DW_SET3_2__FULL 0x1F0405B4,0xffffffff ++#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2 0x1F0405B4,0x01FF0000 ++#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2 0x1F0405B4,0x000001FF ++ ++#define SRM_DI0_DW_SET3_3__ADDR 0x1F0405B8 ++#define SRM_DI0_DW_SET3_3__EMPTY 0x1F0405B8,0x00000000 ++#define SRM_DI0_DW_SET3_3__FULL 0x1F0405B8,0xffffffff ++#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3 0x1F0405B8,0x01FF0000 ++#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3 0x1F0405B8,0x000001FF ++ ++#define SRM_DI0_DW_SET3_4__ADDR 0x1F0405BC ++#define SRM_DI0_DW_SET3_4__EMPTY 0x1F0405BC,0x00000000 ++#define SRM_DI0_DW_SET3_4__FULL 0x1F0405BC,0xffffffff ++#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4 0x1F0405BC,0x01FF0000 ++#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4 0x1F0405BC,0x000001FF ++ ++#define SRM_DI0_DW_SET3_5__ADDR 0x1F0405C0 ++#define SRM_DI0_DW_SET3_5__EMPTY 0x1F0405C0,0x00000000 ++#define SRM_DI0_DW_SET3_5__FULL 0x1F0405C0,0xffffffff ++#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5 0x1F0405C0,0x01FF0000 ++#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5 0x1F0405C0,0x000001FF ++ ++#define SRM_DI0_DW_SET3_6__ADDR 0x1F0405C4 ++#define SRM_DI0_DW_SET3_6__EMPTY 0x1F0405C4,0x00000000 ++#define SRM_DI0_DW_SET3_6__FULL 0x1F0405C4,0xffffffff ++#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6 0x1F0405C4,0x01FF0000 ++#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6 0x1F0405C4,0x000001FF ++ ++#define SRM_DI0_DW_SET3_7__ADDR 0x1F0405C8 ++#define SRM_DI0_DW_SET3_7__EMPTY 0x1F0405C8,0x00000000 ++#define SRM_DI0_DW_SET3_7__FULL 0x1F0405C8,0xffffffff ++#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7 0x1F0405C8,0x01FF0000 ++#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7 0x1F0405C8,0x000001FF ++ ++#define SRM_DI0_DW_SET3_8__ADDR 0x1F0405CC ++#define SRM_DI0_DW_SET3_8__EMPTY 0x1F0405CC,0x00000000 ++#define SRM_DI0_DW_SET3_8__FULL 0x1F0405CC,0xffffffff ++#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8 0x1F0405CC,0x01FF0000 ++#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8 0x1F0405CC,0x000001FF ++ ++#define SRM_DI0_DW_SET3_9__ADDR 0x1F0405D0 ++#define SRM_DI0_DW_SET3_9__EMPTY 0x1F0405D0,0x00000000 ++#define SRM_DI0_DW_SET3_9__FULL 0x1F0405D0,0xffffffff ++#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9 0x1F0405D0,0x01FF0000 ++#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9 0x1F0405D0,0x000001FF ++ ++#define SRM_DI0_DW_SET3_10__ADDR 0x1F0405D4 ++#define SRM_DI0_DW_SET3_10__EMPTY 0x1F0405D4,0x00000000 ++#define SRM_DI0_DW_SET3_10__FULL 0x1F0405D4,0xffffffff ++#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10 0x1F0405D4,0x01FF0000 ++#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10 0x1F0405D4,0x000001FF ++ ++#define SRM_DI0_DW_SET3_11__ADDR 0x1F0405D8 ++#define SRM_DI0_DW_SET3_11__EMPTY 0x1F0405D8,0x00000000 ++#define SRM_DI0_DW_SET3_11__FULL 0x1F0405D8,0xffffffff ++#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11 0x1F0405D8,0x01FF0000 ++#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11 0x1F0405D8,0x000001FF ++ ++#define SRM_DI0_STP_REP_1__ADDR 0x1F0405DC ++#define SRM_DI0_STP_REP_1__EMPTY 0x1F0405DC,0x00000000 ++#define SRM_DI0_STP_REP_1__FULL 0x1F0405DC,0xffffffff ++#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_2 0x1F0405DC,0x0FFF0000 ++#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_1 0x1F0405DC,0x00000FFF ++ ++#define SRM_DI0_STP_REP_2__ADDR 0x1F0405E0 ++#define SRM_DI0_STP_REP_2__EMPTY 0x1F0405E0,0x00000000 ++#define SRM_DI0_STP_REP_2__FULL 0x1F0405E0,0xffffffff ++#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_4 0x1F0405E0,0x0FFF0000 ++#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_3 0x1F0405E0,0x00000FFF ++ ++#define SRM_DI0_STP_REP_3__ADDR 0x1F0405E4 ++#define SRM_DI0_STP_REP_3__EMPTY 0x1F0405E4,0x00000000 ++#define SRM_DI0_STP_REP_3__FULL 0x1F0405E4,0xffffffff ++#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_6 0x1F0405E4,0x0FFF0000 ++#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_5 0x1F0405E4,0x00000FFF ++ ++#define SRM_DI0_STP_REP_4__ADDR 0x1F0405E8 ++#define SRM_DI0_STP_REP_4__EMPTY 0x1F0405E8,0x00000000 ++#define SRM_DI0_STP_REP_4__FULL 0x1F0405E8,0xffffffff ++#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_8 0x1F0405E8,0x0FFF0000 ++#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_7 0x1F0405E8,0x00000FFF ++ ++#define SRM_DI0_STP_REP_9__ADDR 0x1F0405EC ++#define SRM_DI0_STP_REP_9__EMPTY 0x1F0405EC,0x00000000 ++#define SRM_DI0_STP_REP_9__FULL 0x1F0405EC,0xffffffff ++#define SRM_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1F0405EC,0x00000FFF ++ ++#define SRM_DI0_SER_CONF__ADDR 0x1F0405F0 ++#define SRM_DI0_SER_CONF__EMPTY 0x1F0405F0,0x00000000 ++#define SRM_DI0_SER_CONF__FULL 0x1F0405F0,0xffffffff ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1F0405F0,0xF0000000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1F0405F0,0x0F000000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1F0405F0,0x00F00000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1F0405F0,0x000F0000 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1F0405F0,0x0000FF00 ++#define SRM_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1F0405F0,0x00000020 ++#define SRM_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1F0405F0,0x00000010 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1F0405F0,0x00000008 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1F0405F0,0x00000004 ++#define SRM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1F0405F0,0x00000002 ++#define SRM_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1F0405F0,0x00000001 ++ ++#define SRM_DI0_SSC__ADDR 0x1F0405F4 ++#define SRM_DI0_SSC__EMPTY 0x1F0405F4,0x00000000 ++#define SRM_DI0_SSC__FULL 0x1F0405F4,0xffffffff ++#define SRM_DI0_SSC__DI0_PIN17_ERM 0x1F0405F4,0x00800000 ++#define SRM_DI0_SSC__DI0_PIN16_ERM 0x1F0405F4,0x00400000 ++#define SRM_DI0_SSC__DI0_PIN15_ERM 0x1F0405F4,0x00200000 ++#define SRM_DI0_SSC__DI0_PIN14_ERM 0x1F0405F4,0x00100000 ++#define SRM_DI0_SSC__DI0_PIN13_ERM 0x1F0405F4,0x00080000 ++#define SRM_DI0_SSC__DI0_PIN12_ERM 0x1F0405F4,0x00040000 ++#define SRM_DI0_SSC__DI0_PIN11_ERM 0x1F0405F4,0x00020000 ++#define SRM_DI0_SSC__DI0_CS_ERM 0x1F0405F4,0x00010000 ++#define SRM_DI0_SSC__DI0_WAIT_ON 0x1F0405F4,0x00000020 ++#define SRM_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1F0405F4,0x00000008 ++#define SRM_DI0_SSC__DI0_BYTE_EN_PNTR 0x1F0405F4,0x00000007 ++ ++#define SRM_DI0_POL__ADDR 0x1F0405F8 ++#define SRM_DI0_POL__EMPTY 0x1F0405F8,0x00000000 ++#define SRM_DI0_POL__FULL 0x1F0405F8,0xffffffff ++#define SRM_DI0_POL__DI0_WAIT_POLARITY 0x1F0405F8,0x04000000 ++#define SRM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1F0405F8,0x02000000 ++#define SRM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1F0405F8,0x01000000 ++#define SRM_DI0_POL__DI0_CS1_DATA_POLARITY 0x1F0405F8,0x00800000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_17 0x1F0405F8,0x00400000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_16 0x1F0405F8,0x00200000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_15 0x1F0405F8,0x00100000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_14 0x1F0405F8,0x00080000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_13 0x1F0405F8,0x00040000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_12 0x1F0405F8,0x00020000 ++#define SRM_DI0_POL__DI0_CS1_POLARITY_11 0x1F0405F8,0x00010000 ++#define SRM_DI0_POL__DI0_CS0_DATA_POLARITY 0x1F0405F8,0x00008000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_17 0x1F0405F8,0x00004000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_16 0x1F0405F8,0x00002000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_15 0x1F0405F8,0x00001000 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_14 0x1F0405F8,0x00000800 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_13 0x1F0405F8,0x00000400 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_12 0x1F0405F8,0x00000200 ++#define SRM_DI0_POL__DI0_CS0_POLARITY_11 0x1F0405F8,0x00000100 ++#define SRM_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1F0405F8,0x00000080 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_17 0x1F0405F8,0x00000040 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_16 0x1F0405F8,0x00000020 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_15 0x1F0405F8,0x00000010 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_14 0x1F0405F8,0x00000008 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_13 0x1F0405F8,0x00000004 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_12 0x1F0405F8,0x00000002 ++#define SRM_DI0_POL__DI0_DRDY_POLARITY_11 0x1F0405F8,0x00000001 ++ ++#define SRM_DI0_AW0__ADDR 0x1F0405FC ++#define SRM_DI0_AW0__EMPTY 0x1F0405FC,0x00000000 ++#define SRM_DI0_AW0__FULL 0x1F0405FC,0xffffffff ++#define SRM_DI0_AW0__DI0_AW_TRIG_SEL 0x1F0405FC,0xF0000000 ++#define SRM_DI0_AW0__DI0_AW_HEND 0x1F0405FC,0x0FFF0000 ++#define SRM_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1F0405FC,0x0000F000 ++#define SRM_DI0_AW0__DI0_AW_HSTART 0x1F0405FC,0x00000FFF ++ ++#define SRM_DI0_AW1__ADDR 0x1F040600 ++#define SRM_DI0_AW1__EMPTY 0x1F040600,0x00000000 ++#define SRM_DI0_AW1__FULL 0x1F040600,0xffffffff ++#define SRM_DI0_AW1__DI0_AW_VEND 0x1F040600,0x0FFF0000 ++#define SRM_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1F040600,0x0000F000 ++#define SRM_DI0_AW1__DI0_AW_VSTART 0x1F040600,0x00000FFF ++ ++#define SRM_DI0_SCR_CONF__ADDR 0x1F040604 ++#define SRM_DI0_SCR_CONF__EMPTY 0x1F040604,0x00000000 ++#define SRM_DI0_SCR_CONF__FULL 0x1F040604,0xffffffff ++#define SRM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1F040604,0x00000FFF ++ ++#define SRM_DI1_GENERAL__ADDR 0x1F040608 ++#define SRM_DI1_GENERAL__EMPTY 0x1F040608,0x00000000 ++#define SRM_DI1_GENERAL__FULL 0x1F040608,0xffffffff ++#define SRM_DI1_GENERAL__DI1_DISP_Y_SEL 0x1F040608,0x70000000 ++#define SRM_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1F040608,0x0F000000 ++#define SRM_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1F040608,0x00800000 ++#define SRM_DI1_GENERAL__DI1_MASK_SEL 0x1F040608,0x00400000 ++#define SRM_DI1_GENERAL__DI1_VSYNC_EXT 0x1F040608,0x00200000 ++#define SRM_DI1_GENERAL__DI1_CLK_EXT 0x1F040608,0x00100000 ++#define SRN_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1F040608,0x000C0000 ++#define SRM_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1F040608,0x00020000 ++#define SRM_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1F040608,0x0000F000 ++#define SRM_DI1_GENERAL__DI1_ERR_TREATMENT 0x1F040608,0x00000800 ++#define SRM_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1F040608,0x00000400 ++#define SRM_DI1_GENERAL__DI1_POLARITY_CS1 0x1F040608,0x00000200 ++#define SRM_DI1_GENERAL__DI1_POLARITY_CS0 0x1F040608,0x00000100 ++#define SRM_DI1_GENERAL__DI1_POLARITY_8 0x1F040608,0x00000080 ++#define SRM_DI1_GENERAL__DI1_POLARITY_7 0x1F040608,0x00000040 ++#define SRM_DI1_GENERAL__DI1_POLARITY_6 0x1F040608,0x00000020 ++#define SRM_DI1_GENERAL__DI1_POLARITY_5 0x1F040608,0x00000010 ++#define SRM_DI1_GENERAL__DI1_POLARITY_4 0x1F040608,0x00000008 ++#define SRM_DI1_GENERAL__DI1_POLARITY_3 0x1F040608,0x00000004 ++#define SRM_DI1_GENERAL__DI1_POLARITY_2 0x1F040608,0x00000002 ++#define SRM_DI1_GENERAL__DI1_POLARITY_1 0x1F040608,0x00000001 ++ ++#define SRM_DI1_BS_CLKGEN0__ADDR 0x1F04060C ++#define SRM_DI1_BS_CLKGEN0__EMPTY 0x1F04060C,0x00000000 ++#define SRM_DI1_BS_CLKGEN0__FULL 0x1F04060C,0xffffffff ++#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1F04060C,0x01FF0000 ++#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1F04060C,0x00000FFF ++ ++#define SRM_DI1_BS_CLKGEN1__ADDR 0x1F040610 ++#define SRM_DI1_BS_CLKGEN1__EMPTY 0x1F040610,0x00000000 ++#define SRM_DI1_BS_CLKGEN1__FULL 0x1F040610,0xffffffff ++#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1F040610,0x01FF0000 ++#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1F040610,0x000001FF ++ ++#define SRM_DI1_SW_GEN0_1__ADDR 0x1F040614 ++#define SRM_DI1_SW_GEN0_1__EMPTY 0x1F040614,0x00000000 ++#define SRM_DI1_SW_GEN0_1__FULL 0x1F040614,0xffffffff ++#define SRM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1 0x1F040614,0x7FF80000 ++#define SRM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1 0x1F040614,0x00070000 ++#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1 0x1F040614,0x00007FF8 ++#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1 0x1F040614,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_2__ADDR 0x1F040618 ++#define SRM_DI1_SW_GEN0_2__EMPTY 0x1F040618,0x00000000 ++#define SRM_DI1_SW_GEN0_2__FULL 0x1F040618,0xffffffff ++#define SRM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2 0x1F040618,0x7FF80000 ++#define SRM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2 0x1F040618,0x00070000 ++#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2 0x1F040618,0x00007FF8 ++#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2 0x1F040618,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_3__ADDR 0x1F04061C ++#define SRM_DI1_SW_GEN0_3__EMPTY 0x1F04061C,0x00000000 ++#define SRM_DI1_SW_GEN0_3__FULL 0x1F04061C,0xffffffff ++#define SRM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3 0x1F04061C,0x7FF80000 ++#define SRM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3 0x1F04061C,0x00070000 ++#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3 0x1F04061C,0x00007FF8 ++#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3 0x1F04061C,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_4__ADDR 0x1F040620 ++#define SRM_DI1_SW_GEN0_4__EMPTY 0x1F040620,0x00000000 ++#define SRM_DI1_SW_GEN0_4__FULL 0x1F040620,0xffffffff ++#define SRM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4 0x1F040620,0x7FF80000 ++#define SRM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4 0x1F040620,0x00070000 ++#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4 0x1F040620,0x00007FF8 ++#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4 0x1F040620,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_5__ADDR 0x1F040624 ++#define SRM_DI1_SW_GEN0_5__EMPTY 0x1F040624,0x00000000 ++#define SRM_DI1_SW_GEN0_5__FULL 0x1F040624,0xffffffff ++#define SRM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5 0x1F040624,0x7FF80000 ++#define SRM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5 0x1F040624,0x00070000 ++#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5 0x1F040624,0x00007FF8 ++#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5 0x1F040624,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_6__ADDR 0x1F040628 ++#define SRM_DI1_SW_GEN0_6__EMPTY 0x1F040628,0x00000000 ++#define SRM_DI1_SW_GEN0_6__FULL 0x1F040628,0xffffffff ++#define SRM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6 0x1F040628,0x7FF80000 ++#define SRM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6 0x1F040628,0x00070000 ++#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6 0x1F040628,0x00007FF8 ++#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6 0x1F040628,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_7__ADDR 0x1F04062C ++#define SRM_DI1_SW_GEN0_7__EMPTY 0x1F04062C,0x00000000 ++#define SRM_DI1_SW_GEN0_7__FULL 0x1F04062C,0xffffffff ++#define SRM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7 0x1F04062C,0x7FF80000 ++#define SRM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7 0x1F04062C,0x00070000 ++#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7 0x1F04062C,0x00007FF8 ++#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7 0x1F04062C,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_8__ADDR 0x1F040630 ++#define SRM_DI1_SW_GEN0_8__EMPTY 0x1F040630,0x00000000 ++#define SRM_DI1_SW_GEN0_8__FULL 0x1F040630,0xffffffff ++#define SRM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8 0x1F040630,0x7FF80000 ++#define SRM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8 0x1F040630,0x00070000 ++#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8 0x1F040630,0x00007FF8 ++#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8 0x1F040630,0x00000007 ++ ++#define SRM_DI1_SW_GEN0_9__ADDR 0x1F040634 ++#define SRM_DI1_SW_GEN0_9__EMPTY 0x1F040634,0x00000000 ++#define SRM_DI1_SW_GEN0_9__FULL 0x1F040634,0xffffffff ++#define SRM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1F040634,0x7FF80000 ++#define SRM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1F040634,0x00070000 ++#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1F040634,0x00007FF8 ++#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1F040634,0x00000007 ++ ++#define SRM_DI1_SW_GEN1_1__ADDR 0x1F040638 ++#define SRM_DI1_SW_GEN1_1__EMPTY 0x1F040638,0x00000000 ++#define SRM_DI1_SW_GEN1_1__FULL 0x1F040638,0xffffffff ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1 0x1F040638,0x60000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1 0x1F040638,0x10000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1 0x1F040638,0x0E000000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1 0x1F040638,0x01FF0000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1 0x1F040638,0x00007000 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1 0x1F040638,0x00000E00 ++#define SRM_DI1_SW_GEN1_1__DI1_CNT_UP_1 0x1F040638,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_2__ADDR 0x1F04063C ++#define SRM_DI1_SW_GEN1_2__EMPTY 0x1F04063C,0x00000000 ++#define SRM_DI1_SW_GEN1_2__FULL 0x1F04063C,0xffffffff ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2 0x1F04063C,0x60000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2 0x1F04063C,0x10000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2 0x1F04063C,0x0E000000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2 0x1F04063C,0x01FF0000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2 0x1F04063C,0x00007000 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2 0x1F04063C,0x00000E00 ++#define SRM_DI1_SW_GEN1_2__DI1_CNT_UP_2 0x1F04063C,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_3__ADDR 0x1F040640 ++#define SRM_DI1_SW_GEN1_3__EMPTY 0x1F040640,0x00000000 ++#define SRM_DI1_SW_GEN1_3__FULL 0x1F040640,0xffffffff ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3 0x1F040640,0x60000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3 0x1F040640,0x10000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3 0x1F040640,0x0E000000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3 0x1F040640,0x01FF0000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3 0x1F040640,0x00007000 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3 0x1F040640,0x00000E00 ++#define SRM_DI1_SW_GEN1_3__DI1_CNT_UP_3 0x1F040640,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_4__ADDR 0x1F040644 ++#define SRM_DI1_SW_GEN1_4__EMPTY 0x1F040644,0x00000000 ++#define SRM_DI1_SW_GEN1_4__FULL 0x1F040644,0xffffffff ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4 0x1F040644,0x60000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4 0x1F040644,0x10000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4 0x1F040644,0x0E000000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4 0x1F040644,0x01FF0000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4 0x1F040644,0x00007000 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4 0x1F040644,0x00000E00 ++#define SRM_DI1_SW_GEN1_4__DI1_CNT_UP_4 0x1F040644,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_5__ADDR 0x1F040648 ++#define SRM_DI1_SW_GEN1_5__EMPTY 0x1F040648,0x00000000 ++#define SRM_DI1_SW_GEN1_5__FULL 0x1F040648,0xffffffff ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5 0x1F040648,0x60000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5 0x1F040648,0x10000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5 0x1F040648,0x0E000000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5 0x1F040648,0x01FF0000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5 0x1F040648,0x00007000 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5 0x1F040648,0x00000E00 ++#define SRM_DI1_SW_GEN1_5__DI1_CNT_UP_5 0x1F040648,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_6__ADDR 0x1F04064C ++#define SRM_DI1_SW_GEN1_6__EMPTY 0x1F04064C,0x00000000 ++#define SRM_DI1_SW_GEN1_6__FULL 0x1F04064C,0xffffffff ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6 0x1F04064C,0x60000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6 0x1F04064C,0x10000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6 0x1F04064C,0x0E000000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6 0x1F04064C,0x01FF0000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6 0x1F04064C,0x00007000 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6 0x1F04064C,0x00000E00 ++#define SRM_DI1_SW_GEN1_6__DI1_CNT_UP_6 0x1F04064C,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_7__ADDR 0x1F040650 ++#define SRM_DI1_SW_GEN1_7__EMPTY 0x1F040650,0x00000000 ++#define SRM_DI1_SW_GEN1_7__FULL 0x1F040650,0xffffffff ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7 0x1F040650,0x60000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7 0x1F040650,0x10000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7 0x1F040650,0x0E000000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7 0x1F040650,0x01FF0000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7 0x1F040650,0x00007000 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7 0x1F040650,0x00000E00 ++#define SRM_DI1_SW_GEN1_7__DI1_CNT_UP_7 0x1F040650,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_8__ADDR 0x1F040654 ++#define SRM_DI1_SW_GEN1_8__EMPTY 0x1F040654,0x00000000 ++#define SRM_DI1_SW_GEN1_8__FULL 0x1F040654,0xffffffff ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8 0x1F040654,0x60000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8 0x1F040654,0x10000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8 0x1F040654,0x0E000000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8 0x1F040654,0x01FF0000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8 0x1F040654,0x00007000 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8 0x1F040654,0x00000E00 ++#define SRM_DI1_SW_GEN1_8__DI1_CNT_UP_8 0x1F040654,0x000001FF ++ ++#define SRM_DI1_SW_GEN1_9__ADDR 0x1F040658 ++#define SRM_DI1_SW_GEN1_9__EMPTY 0x1F040658,0x00000000 ++#define SRM_DI1_SW_GEN1_9__FULL 0x1F040658,0xffffffff ++#define SRM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1F040658,0xE0000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1F040658,0x10000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1F040658,0x0E000000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1F040658,0x01FF0000 ++#define SRM_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1F040658,0x00008000 ++#define SRM_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1F040658,0x000001FF ++ ++#define SRM_DI1_SYNC_AS_GEN__ADDR 0x1F04065C ++#define SRM_DI1_SYNC_AS_GEN__EMPTY 0x1F04065C,0x00000000 ++#define SRM_DI1_SYNC_AS_GEN__FULL 0x1F04065C,0xffffffff ++#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1F04065C,0x10000000 ++#define SRM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1F04065C,0x0000E000 ++#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1F04065C,0x00000FFF ++ ++#define SRM_DI1_DW_GEN_0__ADDR 0x1F040660 ++#define SRM_DI1_DW_GEN_0__EMPTY 0x1F040660,0x00000000 ++#define SRM_DI1_DW_GEN_0__FULL 0x1F040660,0xffffffff ++#define SRM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1F040660,0xFF000000 ++#define SRM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040660,0x00FF0000 ++#define SRM_DI1_DW_GEN_0__DI1_CST_0 0x1F040660,0x0000C000 ++#define SRM_DI1_DW_GEN_0__DI1_PT_6_0 0x1F040660,0x00003000 ++#define SRM_DI1_DW_GEN_0__DI1_PT_5_0 0x1F040660,0x00000C00 ++#define SRM_DI1_DW_GEN_0__DI1_PT_4_0 0x1F040660,0x00000300 ++#define SRM_DI1_DW_GEN_0__DI1_PT_3_0 0x1F040660,0x000000C0 ++#define SRM_DI1_DW_GEN_0__DI1_PT_2_0 0x1F040660,0x00000030 ++#define SRM_DI1_DW_GEN_0__DI1_PT_1_0 0x1F040660,0x0000000C ++#define SRM_DI1_DW_GEN_0__DI1_PT_0_0 0x1F040660,0x00000003 ++ ++#define SRM_DI1_DW_GEN_0__ADDR 0x1F040660 ++#define SRM_DI1_DW_GEN_0__EMPTY 0x1F040660,0x00000000 ++#define SRM_DI1_DW_GEN_0__FULL 0x1F040660,0xffffffff ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1F040660,0xFF000000 ++#define SRM_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1F040660,0x00FF0000 ++#define SRM_DI1_DW_GEN_0__DI1_CST_0 0x1F040660,0x0000C000 ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040660,0x000001F0 ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1F040660,0x0000000C ++#define SRM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1F040660,0x00000003 ++ ++#define SRM_DI1_DW_GEN_1__ADDR 0x1F040664 ++#define SRM_DI1_DW_GEN_1__EMPTY 0x1F040664,0x00000000 ++#define SRM_DI1_DW_GEN_1__FULL 0x1F040664,0xffffffff ++#define SRM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1F040664,0xFF000000 ++#define SRM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040664,0x00FF0000 ++#define SRM_DI1_DW_GEN_1__DI1_CST_1 0x1F040664,0x0000C000 ++#define SRM_DI1_DW_GEN_1__DI1_PT_6_1 0x1F040664,0x00003000 ++#define SRM_DI1_DW_GEN_1__DI1_PT_5_1 0x1F040664,0x00000C00 ++#define SRM_DI1_DW_GEN_1__DI1_PT_4_1 0x1F040664,0x00000300 ++#define SRM_DI1_DW_GEN_1__DI1_PT_3_1 0x1F040664,0x000000C0 ++#define SRM_DI1_DW_GEN_1__DI1_PT_2_1 0x1F040664,0x00000030 ++#define SRM_DI1_DW_GEN_1__DI1_PT_1_1 0x1F040664,0x0000000C ++#define SRM_DI1_DW_GEN_1__DI1_PT_0_1 0x1F040664,0x00000003 ++ ++#define SRM_DI1_DW_GEN_1__ADDR 0x1F040664 ++#define SRM_DI1_DW_GEN_1__EMPTY 0x1F040664,0x00000000 ++#define SRM_DI1_DW_GEN_1__FULL 0x1F040664,0xffffffff ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1F040664,0xFF000000 ++#define SRM_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1F040664,0x00FF0000 ++#define SRM_DI1_DW_GEN_1__DI1_CST_1 0x1F040664,0x0000C000 ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040664,0x000001F0 ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1F040664,0x0000000C ++#define SRM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1F040664,0x00000003 ++ ++#define SRM_DI1_DW_GEN_2__ADDR 0x1F040668 ++#define SRM_DI1_DW_GEN_2__EMPTY 0x1F040668,0x00000000 ++#define SRM_DI1_DW_GEN_2__FULL 0x1F040668,0xffffffff ++#define SRM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1F040668,0xFF000000 ++#define SRM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F040668,0x00FF0000 ++#define SRM_DI1_DW_GEN_2__DI1_CST_2 0x1F040668,0x0000C000 ++#define SRM_DI1_DW_GEN_2__DI1_PT_6_2 0x1F040668,0x00003000 ++#define SRM_DI1_DW_GEN_2__DI1_PT_5_2 0x1F040668,0x00000C00 ++#define SRM_DI1_DW_GEN_2__DI1_PT_4_2 0x1F040668,0x00000300 ++#define SRM_DI1_DW_GEN_2__DI1_PT_3_2 0x1F040668,0x000000C0 ++#define SRM_DI1_DW_GEN_2__DI1_PT_2_2 0x1F040668,0x00000030 ++#define SRM_DI1_DW_GEN_2__DI1_PT_1_2 0x1F040668,0x0000000C ++#define SRM_DI1_DW_GEN_2__DI1_PT_0_2 0x1F040668,0x00000003 ++ ++#define SRM_DI1_DW_GEN_2__ADDR 0x1F040668 ++#define SRM_DI1_DW_GEN_2__EMPTY 0x1F040668,0x00000000 ++#define SRM_DI1_DW_GEN_2__FULL 0x1F040668,0xffffffff ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1F040668,0xFF000000 ++#define SRM_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1F040668,0x00FF0000 ++#define SRM_DI1_DW_GEN_2__DI1_CST_2 0x1F040668,0x0000C000 ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F040668,0x000001F0 ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1F040668,0x0000000C ++#define SRM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1F040668,0x00000003 ++ ++#define SRM_DI1_DW_GEN_3__ADDR 0x1F04066C ++#define SRM_DI1_DW_GEN_3__EMPTY 0x1F04066C,0x00000000 ++#define SRM_DI1_DW_GEN_3__FULL 0x1F04066C,0xffffffff ++#define SRM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1F04066C,0xFF000000 ++#define SRM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F04066C,0x00FF0000 ++#define SRM_DI1_DW_GEN_3__DI1_CST_3 0x1F04066C,0x0000C000 ++#define SRM_DI1_DW_GEN_3__DI1_PT_6_3 0x1F04066C,0x00003000 ++#define SRM_DI1_DW_GEN_3__DI1_PT_5_3 0x1F04066C,0x00000C00 ++#define SRM_DI1_DW_GEN_3__DI1_PT_4_3 0x1F04066C,0x00000300 ++#define SRM_DI1_DW_GEN_3__DI1_PT_3_3 0x1F04066C,0x000000C0 ++#define SRM_DI1_DW_GEN_3__DI1_PT_2_3 0x1F04066C,0x00000030 ++#define SRM_DI1_DW_GEN_3__DI1_PT_1_3 0x1F04066C,0x0000000C ++#define SRM_DI1_DW_GEN_3__DI1_PT_0_3 0x1F04066C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_3__ADDR 0x1F04066C ++#define SRM_DI1_DW_GEN_3__EMPTY 0x1F04066C,0x00000000 ++#define SRM_DI1_DW_GEN_3__FULL 0x1F04066C,0xffffffff ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1F04066C,0xFF000000 ++#define SRM_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1F04066C,0x00FF0000 ++#define SRM_DI1_DW_GEN_3__DI1_CST_3 0x1F04066C,0x0000C000 ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F04066C,0x000001F0 ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1F04066C,0x0000000C ++#define SRM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1F04066C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_4__ADDR 0x1F040670 ++#define SRM_DI1_DW_GEN_4__EMPTY 0x1F040670,0x00000000 ++#define SRM_DI1_DW_GEN_4__FULL 0x1F040670,0xffffffff ++#define SRM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1F040670,0xFF000000 ++#define SRM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F040670,0x00FF0000 ++#define SRM_DI1_DW_GEN_4__DI1_CST_4 0x1F040670,0x0000C000 ++#define SRM_DI1_DW_GEN_4__DI1_PT_6_4 0x1F040670,0x00003000 ++#define SRM_DI1_DW_GEN_4__DI1_PT_5_4 0x1F040670,0x00000C00 ++#define SRM_DI1_DW_GEN_4__DI1_PT_4_4 0x1F040670,0x00000300 ++#define SRM_DI1_DW_GEN_4__DI1_PT_3_4 0x1F040670,0x000000C0 ++#define SRM_DI1_DW_GEN_4__DI1_PT_2_4 0x1F040670,0x00000030 ++#define SRM_DI1_DW_GEN_4__DI1_PT_1_4 0x1F040670,0x0000000C ++#define SRM_DI1_DW_GEN_4__DI1_PT_0_4 0x1F040670,0x00000003 ++ ++#define SRM_DI1_DW_GEN_4__ADDR 0x1F040670 ++#define SRM_DI1_DW_GEN_4__EMPTY 0x1F040670,0x00000000 ++#define SRM_DI1_DW_GEN_4__FULL 0x1F040670,0xffffffff ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1F040670,0xFF000000 ++#define SRM_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1F040670,0x00FF0000 ++#define SRM_DI1_DW_GEN_4__DI1_CST_4 0x1F040670,0x0000C000 ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F040670,0x000001F0 ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1F040670,0x0000000C ++#define SRM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1F040670,0x00000003 ++ ++#define SRM_DI1_DW_GEN_5__ADDR 0x1F040674 ++#define SRM_DI1_DW_GEN_5__EMPTY 0x1F040674,0x00000000 ++#define SRM_DI1_DW_GEN_5__FULL 0x1F040674,0xffffffff ++#define SRM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1F040674,0xFF000000 ++#define SRM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F040674,0x00FF0000 ++#define SRM_DI1_DW_GEN_5__DI1_CST_5 0x1F040674,0x0000C000 ++#define SRM_DI1_DW_GEN_5__DI1_PT_6_5 0x1F040674,0x00003000 ++#define SRM_DI1_DW_GEN_5__DI1_PT_5_5 0x1F040674,0x00000C00 ++#define SRM_DI1_DW_GEN_5__DI1_PT_4_5 0x1F040674,0x00000300 ++#define SRM_DI1_DW_GEN_5__DI1_PT_3_5 0x1F040674,0x000000C0 ++#define SRM_DI1_DW_GEN_5__DI1_PT_2_5 0x1F040674,0x00000030 ++#define SRM_DI1_DW_GEN_5__DI1_PT_1_5 0x1F040674,0x0000000C ++#define SRM_DI1_DW_GEN_5__DI1_PT_0_5 0x1F040674,0x00000003 ++ ++#define SRM_DI1_DW_GEN_5__ADDR 0x1F040674 ++#define SRM_DI1_DW_GEN_5__EMPTY 0x1F040674,0x00000000 ++#define SRM_DI1_DW_GEN_5__FULL 0x1F040674,0xffffffff ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1F040674,0xFF000000 ++#define SRM_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1F040674,0x00FF0000 ++#define SRM_DI1_DW_GEN_5__DI1_CST_5 0x1F040674,0x0000C000 ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F040674,0x000001F0 ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1F040674,0x0000000C ++#define SRM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1F040674,0x00000003 ++ ++#define SRM_DI1_DW_GEN_6__ADDR 0x1F040678 ++#define SRM_DI1_DW_GEN_6__EMPTY 0x1F040678,0x00000000 ++#define SRM_DI1_DW_GEN_6__FULL 0x1F040678,0xffffffff ++#define SRM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1F040678,0xFF000000 ++#define SRM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F040678,0x00FF0000 ++#define SRM_DI1_DW_GEN_6__DI1_CST_6 0x1F040678,0x0000C000 ++#define SRM_DI1_DW_GEN_6__DI1_PT_6_6 0x1F040678,0x00003000 ++#define SRM_DI1_DW_GEN_6__DI1_PT_5_6 0x1F040678,0x00000C00 ++#define SRM_DI1_DW_GEN_6__DI1_PT_4_6 0x1F040678,0x00000300 ++#define SRM_DI1_DW_GEN_6__DI1_PT_3_6 0x1F040678,0x000000C0 ++#define SRM_DI1_DW_GEN_6__DI1_PT_2_6 0x1F040678,0x00000030 ++#define SRM_DI1_DW_GEN_6__DI1_PT_1_6 0x1F040678,0x0000000C ++#define SRM_DI1_DW_GEN_6__DI1_PT_0_6 0x1F040678,0x00000003 ++ ++#define SRM_DI1_DW_GEN_6__ADDR 0x1F040678 ++#define SRM_DI1_DW_GEN_6__EMPTY 0x1F040678,0x00000000 ++#define SRM_DI1_DW_GEN_6__FULL 0x1F040678,0xffffffff ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1F040678,0xFF000000 ++#define SRM_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1F040678,0x00FF0000 ++#define SRM_DI1_DW_GEN_6__DI1_CST_6 0x1F040678,0x0000C000 ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F040678,0x000001F0 ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1F040678,0x0000000C ++#define SRM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1F040678,0x00000003 ++ ++#define SRM_DI1_DW_GEN_7__ADDR 0x1F04067C ++#define SRM_DI1_DW_GEN_7__EMPTY 0x1F04067C,0x00000000 ++#define SRM_DI1_DW_GEN_7__FULL 0x1F04067C,0xffffffff ++#define SRM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1F04067C,0xFF000000 ++#define SRM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F04067C,0x00FF0000 ++#define SRM_DI1_DW_GEN_7__DI1_CST_7 0x1F04067C,0x0000C000 ++#define SRM_DI1_DW_GEN_7__DI1_PT_6_7 0x1F04067C,0x00003000 ++#define SRM_DI1_DW_GEN_7__DI1_PT_5_7 0x1F04067C,0x00000C00 ++#define SRM_DI1_DW_GEN_7__DI1_PT_4_7 0x1F04067C,0x00000300 ++#define SRM_DI1_DW_GEN_7__DI1_PT_3_7 0x1F04067C,0x000000C0 ++#define SRM_DI1_DW_GEN_7__DI1_PT_2_7 0x1F04067C,0x00000030 ++#define SRM_DI1_DW_GEN_7__DI1_PT_1_7 0x1F04067C,0x0000000C ++#define SRM_DI1_DW_GEN_7__DI1_PT_0_7 0x1F04067C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_7__ADDR 0x1F04067C ++#define SRM_DI1_DW_GEN_7__EMPTY 0x1F04067C,0x00000000 ++#define SRM_DI1_DW_GEN_7__FULL 0x1F04067C,0xffffffff ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1F04067C,0xFF000000 ++#define SRM_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1F04067C,0x00FF0000 ++#define SRM_DI1_DW_GEN_7__DI1_CST_7 0x1F04067C,0x0000C000 ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F04067C,0x000001F0 ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1F04067C,0x0000000C ++#define SRM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1F04067C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_8__ADDR 0x1F040680 ++#define SRM_DI1_DW_GEN_8__EMPTY 0x1F040680,0x00000000 ++#define SRM_DI1_DW_GEN_8__FULL 0x1F040680,0xffffffff ++#define SRM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1F040680,0xFF000000 ++#define SRM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040680,0x00FF0000 ++#define SRM_DI1_DW_GEN_8__DI1_CST_8 0x1F040680,0x0000C000 ++#define SRM_DI1_DW_GEN_8__DI1_PT_6_8 0x1F040680,0x00003000 ++#define SRM_DI1_DW_GEN_8__DI1_PT_5_8 0x1F040680,0x00000C00 ++#define SRM_DI1_DW_GEN_8__DI1_PT_4_8 0x1F040680,0x00000300 ++#define SRM_DI1_DW_GEN_8__DI1_PT_3_8 0x1F040680,0x000000C0 ++#define SRM_DI1_DW_GEN_8__DI1_PT_2_8 0x1F040680,0x00000030 ++#define SRM_DI1_DW_GEN_8__DI1_PT_1_8 0x1F040680,0x0000000C ++#define SRM_DI1_DW_GEN_8__DI1_PT_0_8 0x1F040680,0x00000003 ++ ++#define SRM_DI1_DW_GEN_8__ADDR 0x1F040680 ++#define SRM_DI1_DW_GEN_8__EMPTY 0x1F040680,0x00000000 ++#define SRM_DI1_DW_GEN_8__FULL 0x1F040680,0xffffffff ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1F040680,0xFF000000 ++#define SRM_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1F040680,0x00FF0000 ++#define SRM_DI1_DW_GEN_8__DI1_CST_8 0x1F040680,0x0000C000 ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040680,0x000001F0 ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1F040680,0x0000000C ++#define SRM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1F040680,0x00000003 ++ ++#define SRM_DI1_DW_GEN_9__ADDR 0x1F040684 ++#define SRM_DI1_DW_GEN_9__EMPTY 0x1F040684,0x00000000 ++#define SRM_DI1_DW_GEN_9__FULL 0x1F040684,0xffffffff ++#define SRM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1F040684,0xFF000000 ++#define SRM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040684,0x00FF0000 ++#define SRM_DI1_DW_GEN_9__DI1_CST_9 0x1F040684,0x0000C000 ++#define SRM_DI1_DW_GEN_9__DI1_PT_6_9 0x1F040684,0x00003000 ++#define SRM_DI1_DW_GEN_9__DI1_PT_5_9 0x1F040684,0x00000C00 ++#define SRM_DI1_DW_GEN_9__DI1_PT_4_9 0x1F040684,0x00000300 ++#define SRM_DI1_DW_GEN_9__DI1_PT_3_9 0x1F040684,0x000000C0 ++#define SRM_DI1_DW_GEN_9__DI1_PT_2_9 0x1F040684,0x00000030 ++#define SRM_DI1_DW_GEN_9__DI1_PT_1_9 0x1F040684,0x0000000C ++#define SRM_DI1_DW_GEN_9__DI1_PT_0_9 0x1F040684,0x00000003 ++ ++#define SRM_DI1_DW_GEN_9__ADDR 0x1F040684 ++#define SRM_DI1_DW_GEN_9__EMPTY 0x1F040684,0x00000000 ++#define SRM_DI1_DW_GEN_9__FULL 0x1F040684,0xffffffff ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1F040684,0xFF000000 ++#define SRM_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1F040684,0x00FF0000 ++#define SRM_DI1_DW_GEN_9__DI1_CST_9 0x1F040684,0x0000C000 ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040684,0x000001F0 ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1F040684,0x0000000C ++#define SRM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1F040684,0x00000003 ++ ++#define SRM_DI1_DW_GEN_10__ADDR 0x1F040688 ++#define SRM_DI1_DW_GEN_10__EMPTY 0x1F040688,0x00000000 ++#define SRM_DI1_DW_GEN_10__FULL 0x1F040688,0xffffffff ++#define SRM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1F040688,0xFF000000 ++#define SRM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F040688,0x00FF0000 ++#define SRM_DI1_DW_GEN_10__DI1_CST_10 0x1F040688,0x0000C000 ++#define SRM_DI1_DW_GEN_10__DI1_PT_6_10 0x1F040688,0x00003000 ++#define SRM_DI1_DW_GEN_10__DI1_PT_5_10 0x1F040688,0x00000C00 ++#define SRM_DI1_DW_GEN_10__DI1_PT_4_10 0x1F040688,0x00000300 ++#define SRM_DI1_DW_GEN_10__DI1_PT_3_10 0x1F040688,0x000000C0 ++#define SRM_DI1_DW_GEN_10__DI1_PT_2_10 0x1F040688,0x00000030 ++#define SRM_DI1_DW_GEN_10__DI1_PT_1_10 0x1F040688,0x0000000C ++#define SRM_DI1_DW_GEN_10__DI1_PT_0_10 0x1F040688,0x00000003 ++ ++#define SRM_DI1_DW_GEN_10__ADDR 0x1F040688 ++#define SRM_DI1_DW_GEN_10__EMPTY 0x1F040688,0x00000000 ++#define SRM_DI1_DW_GEN_10__FULL 0x1F040688,0xffffffff ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1F040688,0xFF000000 ++#define SRM_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1F040688,0x00FF0000 ++#define SRM_DI1_DW_GEN_10__DI1_CST_10 0x1F040688,0x0000C000 ++#define SRM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040688,0x000001F0 ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1F040688,0x0000000C ++#define SRM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1F040688,0x00000003 ++ ++#define SRM_DI1_DW_GEN_11__ADDR 0x1F04068C ++#define SRM_DI1_DW_GEN_11__EMPTY 0x1F04068C,0x00000000 ++#define SRM_DI1_DW_GEN_11__FULL 0x1F04068C,0xffffffff ++#define SRM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1F04068C,0xFF000000 ++#define SRM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F04068C,0x00FF0000 ++#define SRM_DI1_DW_GEN_11__DI1_CST_11 0x1F04068C,0x0000C000 ++#define SRM_DI1_DW_GEN_11__DI1_PT_6_11 0x1F04068C,0x00003000 ++#define SRM_DI1_DW_GEN_11__DI1_PT_5_11 0x1F04068C,0x00000C00 ++#define SRM_DI1_DW_GEN_11__DI1_PT_4_11 0x1F04068C,0x00000300 ++#define SRM_DI1_DW_GEN_11__DI1_PT_3_11 0x1F04068C,0x000000C0 ++#define SRM_DI1_DW_GEN_11__DI1_PT_2_11 0x1F04068C,0x00000030 ++#define SRM_DI1_DW_GEN_11__DI1_PT_1_11 0x1F04068C,0x0000000C ++#define SRM_DI1_DW_GEN_11__DI1_PT_0_11 0x1F04068C,0x00000003 ++ ++#define SRM_DI1_DW_GEN_11__ADDR 0x1F04068C ++#define SRM_DI1_DW_GEN_11__EMPTY 0x1F04068C,0x00000000 ++#define SRM_DI1_DW_GEN_11__FULL 0x1F04068C,0xffffffff ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1F04068C,0xFF000000 ++#define SRM_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1F04068C,0x00FF0000 ++#define SRM_DI1_DW_GEN_11__DI1_CST_11 0x1F04068C,0x0000C000 ++#define SRM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F04068C,0x000001F0 ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1F04068C,0x0000000C ++#define SRM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1F04068C,0x00000003 ++ ++#define SRM_DI1_DW_SET0_0__ADDR 0x1F040690 ++#define SRM_DI1_DW_SET0_0__EMPTY 0x1F040690,0x00000000 ++#define SRM_DI1_DW_SET0_0__FULL 0x1F040690,0xffffffff ++#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0 0x1F040690,0x01FF0000 ++#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0 0x1F040690,0x000001FF ++ ++#define SRM_DI1_DW_SET0_1__ADDR 0x1F040694 ++#define SRM_DI1_DW_SET0_1__EMPTY 0x1F040694,0x00000000 ++#define SRM_DI1_DW_SET0_1__FULL 0x1F040694,0xffffffff ++#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1 0x1F040694,0x01FF0000 ++#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1 0x1F040694,0x000001FF ++ ++#define SRM_DI1_DW_SET0_2__ADDR 0x1F040698 ++#define SRM_DI1_DW_SET0_2__EMPTY 0x1F040698,0x00000000 ++#define SRM_DI1_DW_SET0_2__FULL 0x1F040698,0xffffffff ++#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2 0x1F040698,0x01FF0000 ++#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2 0x1F040698,0x000001FF ++ ++#define SRM_DI1_DW_SET0_3__ADDR 0x1F04069C ++#define SRM_DI1_DW_SET0_3__EMPTY 0x1F04069C,0x00000000 ++#define SRM_DI1_DW_SET0_3__FULL 0x1F04069C,0xffffffff ++#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3 0x1F04069C,0x01FF0000 ++#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3 0x1F04069C,0x000001FF ++ ++#define SRM_DI1_DW_SET0_4__ADDR 0x1F0406A0 ++#define SRM_DI1_DW_SET0_4__EMPTY 0x1F0406A0,0x00000000 ++#define SRM_DI1_DW_SET0_4__FULL 0x1F0406A0,0xffffffff ++#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4 0x1F0406A0,0x01FF0000 ++#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4 0x1F0406A0,0x000001FF ++ ++#define SRM_DI1_DW_SET0_5__ADDR 0x1F0406A4 ++#define SRM_DI1_DW_SET0_5__EMPTY 0x1F0406A4,0x00000000 ++#define SRM_DI1_DW_SET0_5__FULL 0x1F0406A4,0xffffffff ++#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5 0x1F0406A4,0x01FF0000 ++#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5 0x1F0406A4,0x000001FF ++ ++#define SRM_DI1_DW_SET0_6__ADDR 0x1F0406A8 ++#define SRM_DI1_DW_SET0_6__EMPTY 0x1F0406A8,0x00000000 ++#define SRM_DI1_DW_SET0_6__FULL 0x1F0406A8,0xffffffff ++#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6 0x1F0406A8,0x01FF0000 ++#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6 0x1F0406A8,0x000001FF ++ ++#define SRM_DI1_DW_SET0_7__ADDR 0x1F0406AC ++#define SRM_DI1_DW_SET0_7__EMPTY 0x1F0406AC,0x00000000 ++#define SRM_DI1_DW_SET0_7__FULL 0x1F0406AC,0xffffffff ++#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7 0x1F0406AC,0x01FF0000 ++#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7 0x1F0406AC,0x000001FF ++ ++#define SRM_DI1_DW_SET0_8__ADDR 0x1F0406B0 ++#define SRM_DI1_DW_SET0_8__EMPTY 0x1F0406B0,0x00000000 ++#define SRM_DI1_DW_SET0_8__FULL 0x1F0406B0,0xffffffff ++#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8 0x1F0406B0,0x01FF0000 ++#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8 0x1F0406B0,0x000001FF ++ ++#define SRM_DI1_DW_SET0_9__ADDR 0x1F0406B4 ++#define SRM_DI1_DW_SET0_9__EMPTY 0x1F0406B4,0x00000000 ++#define SRM_DI1_DW_SET0_9__FULL 0x1F0406B4,0xffffffff ++#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9 0x1F0406B4,0x01FF0000 ++#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9 0x1F0406B4,0x000001FF ++ ++#define SRM_DI1_DW_SET0_10__ADDR 0x1F0406B8 ++#define SRM_DI1_DW_SET0_10__EMPTY 0x1F0406B8,0x00000000 ++#define SRM_DI1_DW_SET0_10__FULL 0x1F0406B8,0xffffffff ++#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10 0x1F0406B8,0x01FF0000 ++#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10 0x1F0406B8,0x000001FF ++ ++#define SRM_DI1_DW_SET0_11__ADDR 0x1F0406BC ++#define SRM_DI1_DW_SET0_11__EMPTY 0x1F0406BC,0x00000000 ++#define SRM_DI1_DW_SET0_11__FULL 0x1F0406BC,0xffffffff ++#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11 0x1F0406BC,0x01FF0000 ++#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11 0x1F0406BC,0x000001FF ++ ++#define SRM_DI1_DW_SET1_0__ADDR 0x1F0406C0 ++#define SRM_DI1_DW_SET1_0__EMPTY 0x1F0406C0,0x00000000 ++#define SRM_DI1_DW_SET1_0__FULL 0x1F0406C0,0xffffffff ++#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0 0x1F0406C0,0x01FF0000 ++#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0 0x1F0406C0,0x000001FF ++ ++#define SRM_DI1_DW_SET1_1__ADDR 0x1F0406C4 ++#define SRM_DI1_DW_SET1_1__EMPTY 0x1F0406C4,0x00000000 ++#define SRM_DI1_DW_SET1_1__FULL 0x1F0406C4,0xffffffff ++#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1 0x1F0406C4,0x01FF0000 ++#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1 0x1F0406C4,0x000001FF ++ ++#define SRM_DI1_DW_SET1_2__ADDR 0x1F0406C8 ++#define SRM_DI1_DW_SET1_2__EMPTY 0x1F0406C8,0x00000000 ++#define SRM_DI1_DW_SET1_2__FULL 0x1F0406C8,0xffffffff ++#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2 0x1F0406C8,0x01FF0000 ++#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2 0x1F0406C8,0x000001FF ++ ++#define SRM_DI1_DW_SET1_3__ADDR 0x1F0406CC ++#define SRM_DI1_DW_SET1_3__EMPTY 0x1F0406CC,0x00000000 ++#define SRM_DI1_DW_SET1_3__FULL 0x1F0406CC,0xffffffff ++#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3 0x1F0406CC,0x01FF0000 ++#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3 0x1F0406CC,0x000001FF ++ ++#define SRM_DI1_DW_SET1_4__ADDR 0x1F0406D0 ++#define SRM_DI1_DW_SET1_4__EMPTY 0x1F0406D0,0x00000000 ++#define SRM_DI1_DW_SET1_4__FULL 0x1F0406D0,0xffffffff ++#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4 0x1F0406D0,0x01FF0000 ++#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4 0x1F0406D0,0x000001FF ++ ++#define SRM_DI1_DW_SET1_5__ADDR 0x1F0406D4 ++#define SRM_DI1_DW_SET1_5__EMPTY 0x1F0406D4,0x00000000 ++#define SRM_DI1_DW_SET1_5__FULL 0x1F0406D4,0xffffffff ++#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5 0x1F0406D4,0x01FF0000 ++#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5 0x1F0406D4,0x000001FF ++ ++#define SRM_DI1_DW_SET1_6__ADDR 0x1F0406D8 ++#define SRM_DI1_DW_SET1_6__EMPTY 0x1F0406D8,0x00000000 ++#define SRM_DI1_DW_SET1_6__FULL 0x1F0406D8,0xffffffff ++#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6 0x1F0406D8,0x01FF0000 ++#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6 0x1F0406D8,0x000001FF ++ ++#define SRM_DI1_DW_SET1_7__ADDR 0x1F0406DC ++#define SRM_DI1_DW_SET1_7__EMPTY 0x1F0406DC,0x00000000 ++#define SRM_DI1_DW_SET1_7__FULL 0x1F0406DC,0xffffffff ++#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7 0x1F0406DC,0x01FF0000 ++#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7 0x1F0406DC,0x000001FF ++ ++#define SRM_DI1_DW_SET1_8__ADDR 0x1F0406E0 ++#define SRM_DI1_DW_SET1_8__EMPTY 0x1F0406E0,0x00000000 ++#define SRM_DI1_DW_SET1_8__FULL 0x1F0406E0,0xffffffff ++#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8 0x1F0406E0,0x01FF0000 ++#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8 0x1F0406E0,0x000001FF ++ ++#define SRM_DI1_DW_SET1_9__ADDR 0x1F0406E4 ++#define SRM_DI1_DW_SET1_9__EMPTY 0x1F0406E4,0x00000000 ++#define SRM_DI1_DW_SET1_9__FULL 0x1F0406E4,0xffffffff ++#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9 0x1F0406E4,0x01FF0000 ++#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9 0x1F0406E4,0x000001FF ++ ++#define SRM_DI1_DW_SET1_10__ADDR 0x1F0406E8 ++#define SRM_DI1_DW_SET1_10__EMPTY 0x1F0406E8,0x00000000 ++#define SRM_DI1_DW_SET1_10__FULL 0x1F0406E8,0xffffffff ++#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10 0x1F0406E8,0x01FF0000 ++#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10 0x1F0406E8,0x000001FF ++ ++#define SRM_DI1_DW_SET1_11__ADDR 0x1F0406EC ++#define SRM_DI1_DW_SET1_11__EMPTY 0x1F0406EC,0x00000000 ++#define SRM_DI1_DW_SET1_11__FULL 0x1F0406EC,0xffffffff ++#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11 0x1F0406EC,0x01FF0000 ++#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11 0x1F0406EC,0x000001FF ++ ++#define SRM_DI1_DW_SET2_0__ADDR 0x1F0406F0 ++#define SRM_DI1_DW_SET2_0__EMPTY 0x1F0406F0,0x00000000 ++#define SRM_DI1_DW_SET2_0__FULL 0x1F0406F0,0xffffffff ++#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0 0x1F0406F0,0x01FF0000 ++#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0 0x1F0406F0,0x000001FF ++ ++#define SRM_DI1_DW_SET2_1__ADDR 0x1F0406F4 ++#define SRM_DI1_DW_SET2_1__EMPTY 0x1F0406F4,0x00000000 ++#define SRM_DI1_DW_SET2_1__FULL 0x1F0406F4,0xffffffff ++#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1 0x1F0406F4,0x01FF0000 ++#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1 0x1F0406F4,0x000001FF ++ ++#define SRM_DI1_DW_SET2_2__ADDR 0x1F0406F8 ++#define SRM_DI1_DW_SET2_2__EMPTY 0x1F0406F8,0x00000000 ++#define SRM_DI1_DW_SET2_2__FULL 0x1F0406F8,0xffffffff ++#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2 0x1F0406F8,0x01FF0000 ++#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2 0x1F0406F8,0x000001FF ++ ++#define SRM_DI1_DW_SET2_3__ADDR 0x1F0406FC ++#define SRM_DI1_DW_SET2_3__EMPTY 0x1F0406FC,0x00000000 ++#define SRM_DI1_DW_SET2_3__FULL 0x1F0406FC,0xffffffff ++#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3 0x1F0406FC,0x01FF0000 ++#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3 0x1F0406FC,0x000001FF ++ ++#define SRM_DI1_DW_SET2_4__ADDR 0x1F040700 ++#define SRM_DI1_DW_SET2_4__EMPTY 0x1F040700,0x00000000 ++#define SRM_DI1_DW_SET2_4__FULL 0x1F040700,0xffffffff ++#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4 0x1F040700,0x01FF0000 ++#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4 0x1F040700,0x000001FF ++ ++#define SRM_DI1_DW_SET2_5__ADDR 0x1F040704 ++#define SRM_DI1_DW_SET2_5__EMPTY 0x1F040704,0x00000000 ++#define SRM_DI1_DW_SET2_5__FULL 0x1F040704,0xffffffff ++#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5 0x1F040704,0x01FF0000 ++#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5 0x1F040704,0x000001FF ++ ++#define SRM_DI1_DW_SET2_6__ADDR 0x1F040708 ++#define SRM_DI1_DW_SET2_6__EMPTY 0x1F040708,0x00000000 ++#define SRM_DI1_DW_SET2_6__FULL 0x1F040708,0xffffffff ++#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6 0x1F040708,0x01FF0000 ++#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6 0x1F040708,0x000001FF ++ ++#define SRM_DI1_DW_SET2_7__ADDR 0x1F04070C ++#define SRM_DI1_DW_SET2_7__EMPTY 0x1F04070C,0x00000000 ++#define SRM_DI1_DW_SET2_7__FULL 0x1F04070C,0xffffffff ++#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7 0x1F04070C,0x01FF0000 ++#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7 0x1F04070C,0x000001FF ++ ++#define SRM_DI1_DW_SET2_8__ADDR 0x1F040710 ++#define SRM_DI1_DW_SET2_8__EMPTY 0x1F040710,0x00000000 ++#define SRM_DI1_DW_SET2_8__FULL 0x1F040710,0xffffffff ++#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8 0x1F040710,0x01FF0000 ++#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8 0x1F040710,0x000001FF ++ ++#define SRM_DI1_DW_SET2_9__ADDR 0x1F040714 ++#define SRM_DI1_DW_SET2_9__EMPTY 0x1F040714,0x00000000 ++#define SRM_DI1_DW_SET2_9__FULL 0x1F040714,0xffffffff ++#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9 0x1F040714,0x01FF0000 ++#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9 0x1F040714,0x000001FF ++ ++#define SRM_DI1_DW_SET2_10__ADDR 0x1F040718 ++#define SRM_DI1_DW_SET2_10__EMPTY 0x1F040718,0x00000000 ++#define SRM_DI1_DW_SET2_10__FULL 0x1F040718,0xffffffff ++#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10 0x1F040718,0x01FF0000 ++#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10 0x1F040718,0x000001FF ++ ++#define SRM_DI1_DW_SET2_11__ADDR 0x1F04071C ++#define SRM_DI1_DW_SET2_11__EMPTY 0x1F04071C,0x00000000 ++#define SRM_DI1_DW_SET2_11__FULL 0x1F04071C,0xffffffff ++#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11 0x1F04071C,0x01FF0000 ++#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11 0x1F04071C,0x000001FF ++ ++#define SRM_DI1_DW_SET3_0__ADDR 0x1F040720 ++#define SRM_DI1_DW_SET3_0__EMPTY 0x1F040720,0x00000000 ++#define SRM_DI1_DW_SET3_0__FULL 0x1F040720,0xffffffff ++#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0 0x1F040720,0x01FF0000 ++#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0 0x1F040720,0x000001FF ++ ++#define SRM_DI1_DW_SET3_1__ADDR 0x1F040724 ++#define SRM_DI1_DW_SET3_1__EMPTY 0x1F040724,0x00000000 ++#define SRM_DI1_DW_SET3_1__FULL 0x1F040724,0xffffffff ++#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1 0x1F040724,0x01FF0000 ++#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1 0x1F040724,0x000001FF ++ ++#define SRM_DI1_DW_SET3_2__ADDR 0x1F040728 ++#define SRM_DI1_DW_SET3_2__EMPTY 0x1F040728,0x00000000 ++#define SRM_DI1_DW_SET3_2__FULL 0x1F040728,0xffffffff ++#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2 0x1F040728,0x01FF0000 ++#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2 0x1F040728,0x000001FF ++ ++#define SRM_DI1_DW_SET3_3__ADDR 0x1F04072C ++#define SRM_DI1_DW_SET3_3__EMPTY 0x1F04072C,0x00000000 ++#define SRM_DI1_DW_SET3_3__FULL 0x1F04072C,0xffffffff ++#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3 0x1F04072C,0x01FF0000 ++#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3 0x1F04072C,0x000001FF ++ ++#define SRM_DI1_DW_SET3_4__ADDR 0x1F040730 ++#define SRM_DI1_DW_SET3_4__EMPTY 0x1F040730,0x00000000 ++#define SRM_DI1_DW_SET3_4__FULL 0x1F040730,0xffffffff ++#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4 0x1F040730,0x01FF0000 ++#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4 0x1F040730,0x000001FF ++ ++#define SRM_DI1_DW_SET3_5__ADDR 0x1F040734 ++#define SRM_DI1_DW_SET3_5__EMPTY 0x1F040734,0x00000000 ++#define SRM_DI1_DW_SET3_5__FULL 0x1F040734,0xffffffff ++#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5 0x1F040734,0x01FF0000 ++#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5 0x1F040734,0x000001FF ++ ++#define SRM_DI1_DW_SET3_6__ADDR 0x1F040738 ++#define SRM_DI1_DW_SET3_6__EMPTY 0x1F040738,0x00000000 ++#define SRM_DI1_DW_SET3_6__FULL 0x1F040738,0xffffffff ++#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6 0x1F040738,0x01FF0000 ++#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6 0x1F040738,0x000001FF ++ ++#define SRM_DI1_DW_SET3_7__ADDR 0x1F04073C ++#define SRM_DI1_DW_SET3_7__EMPTY 0x1F04073C,0x00000000 ++#define SRM_DI1_DW_SET3_7__FULL 0x1F04073C,0xffffffff ++#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7 0x1F04073C,0x01FF0000 ++#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7 0x1F04073C,0x000001FF ++ ++#define SRM_DI1_DW_SET3_8__ADDR 0x1F040740 ++#define SRM_DI1_DW_SET3_8__EMPTY 0x1F040740,0x00000000 ++#define SRM_DI1_DW_SET3_8__FULL 0x1F040740,0xffffffff ++#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8 0x1F040740,0x01FF0000 ++#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8 0x1F040740,0x000001FF ++ ++#define SRM_DI1_DW_SET3_9__ADDR 0x1F040744 ++#define SRM_DI1_DW_SET3_9__EMPTY 0x1F040744,0x00000000 ++#define SRM_DI1_DW_SET3_9__FULL 0x1F040744,0xffffffff ++#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9 0x1F040744,0x01FF0000 ++#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9 0x1F040744,0x000001FF ++ ++#define SRM_DI1_DW_SET3_10__ADDR 0x1F040748 ++#define SRM_DI1_DW_SET3_10__EMPTY 0x1F040748,0x00000000 ++#define SRM_DI1_DW_SET3_10__FULL 0x1F040748,0xffffffff ++#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10 0x1F040748,0x01FF0000 ++#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10 0x1F040748,0x000001FF ++ ++#define SRM_DI1_DW_SET3_11__ADDR 0x1F04074C ++#define SRM_DI1_DW_SET3_11__EMPTY 0x1F04074C,0x00000000 ++#define SRM_DI1_DW_SET3_11__FULL 0x1F04074C,0xffffffff ++#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11 0x1F04074C,0x01FF0000 ++#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11 0x1F04074C,0x000001FF ++ ++#define SRM_DI1_STP_REP_1__ADDR 0x1F040750 ++#define SRM_DI1_STP_REP_1__EMPTY 0x1F040750,0x00000000 ++#define SRM_DI1_STP_REP_1__FULL 0x1F040750,0xffffffff ++#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_2 0x1F040750,0x0FFF0000 ++#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_1 0x1F040750,0x00000FFF ++ ++#define SRM_DI1_STP_REP_2__ADDR 0x1F040754 ++#define SRM_DI1_STP_REP_2__EMPTY 0x1F040754,0x00000000 ++#define SRM_DI1_STP_REP_2__FULL 0x1F040754,0xffffffff ++#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_4 0x1F040754,0x0FFF0000 ++#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_3 0x1F040754,0x00000FFF ++ ++#define SRM_DI1_STP_REP_3__ADDR 0x1F040758 ++#define SRM_DI1_STP_REP_3__EMPTY 0x1F040758,0x00000000 ++#define SRM_DI1_STP_REP_3__FULL 0x1F040758,0xffffffff ++#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_6 0x1F040758,0x0FFF0000 ++#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_5 0x1F040758,0x00000FFF ++ ++#define SRM_DI1_STP_REP_4__ADDR 0x1F04075C ++#define SRM_DI1_STP_REP_4__EMPTY 0x1F04075C,0x00000000 ++#define SRM_DI1_STP_REP_4__FULL 0x1F04075C,0xffffffff ++#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_8 0x1F04075C,0x0FFF0000 ++#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_7 0x1F04075C,0x00000FFF ++ ++#define SRM_DI1_STP_REP_9__ADDR 0x1F040760 ++#define SRM_DI1_STP_REP_9__EMPTY 0x1F040760,0x00000000 ++#define SRM_DI1_STP_REP_9__FULL 0x1F040760,0xffffffff ++#define SRM_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1F040760,0x00000FFF ++ ++#define SRM_DI1_SER_CONF__ADDR 0x1F040764 ++#define SRM_DI1_SER_CONF__EMPTY 0x1F040764,0x00000000 ++#define SRM_DI1_SER_CONF__FULL 0x1F040764,0xffffffff ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1F040764,0xF0000000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1F040764,0x0F000000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1F040764,0x00F00000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1F040764,0x000F0000 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1F040764,0x0000FF00 ++#define SRM_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1F040764,0x00000020 ++#define SRM_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1F040764,0x00000010 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1F040764,0x00000008 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1F040764,0x00000004 ++#define SRM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1F040764,0x00000002 ++#define SRM_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1F040764,0x00000001 ++ ++#define SRM_DI1_SSC__ADDR 0x1F040768 ++#define SRM_DI1_SSC__EMPTY 0x1F040768,0x00000000 ++#define SRM_DI1_SSC__FULL 0x1F040768,0xffffffff ++#define SRM_DI1_SSC__DI1_PIN17_ERM 0x1F040768,0x00800000 ++#define SRM_DI1_SSC__DI1_PIN16_ERM 0x1F040768,0x00400000 ++#define SRM_DI1_SSC__DI1_PIN15_ERM 0x1F040768,0x00200000 ++#define SRM_DI1_SSC__DI1_PIN14_ERM 0x1F040768,0x00100000 ++#define SRM_DI1_SSC__DI1_PIN13_ERM 0x1F040768,0x00080000 ++#define SRM_DI1_SSC__DI1_PIN12_ERM 0x1F040768,0x00040000 ++#define SRM_DI1_SSC__DI1_PIN11_ERM 0x1F040768,0x00020000 ++#define SRM_DI1_SSC__DI1_CS_ERM 0x1F040768,0x00010000 ++#define SRM_DI1_SSC__DI1_WAIT_ON 0x1F040768,0x00000020 ++#define SRM_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1F040768,0x00000008 ++#define SRM_DI1_SSC__DI1_BYTE_EN_PNTR 0x1F040768,0x00000007 ++ ++#define SRM_DI1_POL__ADDR 0x1F04076C ++#define SRM_DI1_POL__EMPTY 0x1F04076C,0x00000000 ++#define SRM_DI1_POL__FULL 0x1F04076C,0xffffffff ++#define SRM_DI1_POL__DI1_WAIT_POLARITY 0x1F04076C,0x04000000 ++#define SRM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1F04076C,0x02000000 ++#define SRM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1F04076C,0x01000000 ++#define SRM_DI1_POL__DI1_CS1_DATA_POLARITY 0x1F04076C,0x00800000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_17 0x1F04076C,0x00400000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_16 0x1F04076C,0x00200000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_15 0x1F04076C,0x00100000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_14 0x1F04076C,0x00080000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_13 0x1F04076C,0x00040000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_12 0x1F04076C,0x00020000 ++#define SRM_DI1_POL__DI1_CS1_POLARITY_11 0x1F04076C,0x00010000 ++#define SRM_DI1_POL__DI1_CS0_DATA_POLARITY 0x1F04076C,0x00008000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_17 0x1F04076C,0x00004000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_16 0x1F04076C,0x00002000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_15 0x1F04076C,0x00001000 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_14 0x1F04076C,0x00000800 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_13 0x1F04076C,0x00000400 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_12 0x1F04076C,0x00000200 ++#define SRM_DI1_POL__DI1_CS0_POLARITY_11 0x1F04076C,0x00000100 ++#define SRM_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1F04076C,0x00000080 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_17 0x1F04076C,0x00000040 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_16 0x1F04076C,0x00000020 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_15 0x1F04076C,0x00000010 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_14 0x1F04076C,0x00000008 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_13 0x1F04076C,0x00000004 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_12 0x1F04076C,0x00000002 ++#define SRM_DI1_POL__DI1_DRDY_POLARITY_11 0x1F04076C,0x00000001 ++ ++#define SRM_DI1_AW0__ADDR 0x1F040770 ++#define SRM_DI1_AW0__EMPTY 0x1F040770,0x00000000 ++#define SRM_DI1_AW0__FULL 0x1F040770,0xffffffff ++#define SRM_DI1_AW0__DI1_AW_TRIG_SEL 0x1F040770,0xF0000000 ++#define SRM_DI1_AW0__DI1_AW_HEND 0x1F040770,0x0FFF0000 ++#define SRM_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1F040770,0x0000F000 ++#define SRM_DI1_AW0__DI1_AW_HSTART 0x1F040770,0x00000FFF ++ ++#define SRM_DI1_AW1__ADDR 0x1F040774 ++#define SRM_DI1_AW1__EMPTY 0x1F040774,0x00000000 ++#define SRM_DI1_AW1__FULL 0x1F040774,0xffffffff ++#define SRM_DI1_AW1__DI1_AW_VEND 0x1F040774,0x0FFF0000 ++#define SRM_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1F040774,0x0000F000 ++#define SRM_DI1_AW1__DI1_AW_VSTART 0x1F040774,0x00000FFF ++ ++#define SRM_DI1_SCR_CONF__ADDR 0x1F040778 ++#define SRM_DI1_SCR_CONF__EMPTY 0x1F040778,0x00000000 ++#define SRM_DI1_SCR_CONF__FULL 0x1F040778,0xffffffff ++#define SRM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1F040778,0x00000FFF ++ ++#define SRM_DC_WR_CH_CONF_2__ADDR 0x1F04045C ++#define SRM_DC_WR_CH_CONF_2__EMPTY 0x1F04045C,0x00000000 ++#define SRM_DC_WR_CH_CONF_2__FULL 0x1F04045C,0xffffffff ++#define SRM_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1F04045C,0x07FF0000 ++#define SRM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1F04045C,0x00000100 ++#define SRM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1F04045C,0x000000E0 ++#define SRM_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1F04045C,0x00000018 ++#define SRM_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1F04045C,0x00000004 ++#define SRM_DC_WR_CH_CONF_2__W_SIZE_2 0x1F04045C,0x00000003 ++ ++#define SRM_DC_WR_CH_ADDR_2__ADDR 0x1F040460 ++#define SRM_DC_WR_CH_ADDR_2__EMPTY 0x1F040460,0x00000000 ++#define SRM_DC_WR_CH_ADDR_2__FULL 0x1F040460,0xffffffff ++#define SRM_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1F040460,0x1FFFFFFF ++ ++#define SRM_DC_RL0_CH_2__ADDR 0x1F040464 ++#define SRM_DC_RL0_CH_2__EMPTY 0x1F040464,0x00000000 ++#define SRM_DC_RL0_CH_2__FULL 0x1F040464,0xffffffff ++#define SRM_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1F040464,0xFF000000 ++#define SRM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1F040464,0x000F0000 ++#define SRM_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1F040464,0x0000FF00 ++#define SRM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1F040464,0x0000000F ++ ++#define SRM_DC_RL1_CH_2__ADDR 0x1F040468 ++#define SRM_DC_RL1_CH_2__EMPTY 0x1F040468,0x00000000 ++#define SRM_DC_RL1_CH_2__FULL 0x1F040468,0xffffffff ++#define SRM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1F040468,0xFF000000 ++#define SRM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1F040468,0x000F0000 ++#define SRM_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1F040468,0x0000FF00 ++#define SRM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1F040468,0x0000000F ++ ++#define SRM_DC_RL2_CH_2__ADDR 0x1F04046C ++#define SRM_DC_RL2_CH_2__EMPTY 0x1F04046C,0x00000000 ++#define SRM_DC_RL2_CH_2__FULL 0x1F04046C,0xffffffff ++#define SRM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1F04046C,0xFF000000 ++#define SRM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1F04046C,0x000F0000 ++#define SRM_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1F04046C,0x0000FF00 ++#define SRM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1F04046C,0x0000000F ++ ++#define SRM_DC_RL3_CH_2__ADDR 0x1F040470 ++#define SRM_DC_RL3_CH_2__EMPTY 0x1F040470,0x00000000 ++#define SRM_DC_RL3_CH_2__FULL 0x1F040470,0xffffffff ++#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1F040470,0xFF000000 ++#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1F040470,0x000F0000 ++#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1F040470,0x0000FF00 ++#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1F040470,0x0000000F ++ ++#define SRM_DC_RL4_CH_2__ADDR 0x1F040474 ++#define SRM_DC_RL4_CH_2__EMPTY 0x1F040474,0x00000000 ++#define SRM_DC_RL4_CH_2__FULL 0x1F040474,0xffffffff ++#define SRM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1F040474,0x0000FF00 ++#define SRM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1F040474,0x0000000F ++ ++#define SRM_DC_WR_CH_CONF_6__ADDR 0x1F040478 ++#define SRM_DC_WR_CH_CONF_6__EMPTY 0x1F040478,0x00000000 ++#define SRM_DC_WR_CH_CONF_6__FULL 0x1F040478,0xffffffff ++#define SRM_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1F040478,0x07FF0000 ++#define SRM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1F040478,0x00000100 ++#define SRM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1F040478,0x000000E0 ++#define SRM_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1F040478,0x00000018 ++#define SRM_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1F040478,0x00000004 ++#define SRM_DC_WR_CH_CONF_6__W_SIZE_6 0x1F040478,0x00000003 ++ ++#define SRM_DC_WR_CH_ADDR_6__ADDR 0x1F04047C ++#define SRM_DC_WR_CH_ADDR_6__EMPTY 0x1F04047C,0x00000000 ++#define SRM_DC_WR_CH_ADDR_6__FULL 0x1F04047C,0xffffffff ++#define SRM_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1F04047C,0x1FFFFFFF ++ ++#define SRM_DC_RL0_CH_6__ADDR 0x1F040480 ++#define SRM_DC_RL0_CH_6__EMPTY 0x1F040480,0x00000000 ++#define SRM_DC_RL0_CH_6__FULL 0x1F040480,0xffffffff ++#define SRM_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1F040480,0xFF000000 ++#define SRM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1F040480,0x000F0000 ++#define SRM_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1F040480,0x0000FF00 ++#define SRM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1F040480,0x0000000F ++ ++#define SRM_DC_RL1_CH_6__ADDR 0x1F040484 ++#define SRM_DC_RL1_CH_6__EMPTY 0x1F040484,0x00000000 ++#define SRM_DC_RL1_CH_6__FULL 0x1F040484,0xffffffff ++#define SRM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1F040484,0xFF000000 ++#define SRM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1F040484,0x000F0000 ++#define SRM_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1F040484,0x0000FF00 ++#define SRM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1F040484,0x0000000F ++ ++#define SRM_DC_RL2_CH_6__ADDR 0x1F040488 ++#define SRM_DC_RL2_CH_6__EMPTY 0x1F040488,0x00000000 ++#define SRM_DC_RL2_CH_6__FULL 0x1F040488,0xffffffff ++#define SRM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1F040488,0xFF000000 ++#define SRM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1F040488,0x000F0000 ++#define SRM_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1F040488,0x0000FF00 ++#define SRM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1F040488,0x0000000F ++ ++#define SRM_DC_RL3_CH_6__ADDR 0x1F04048C ++#define SRM_DC_RL3_CH_6__EMPTY 0x1F04048C,0x00000000 ++#define SRM_DC_RL3_CH_6__FULL 0x1F04048C,0xffffffff ++#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1F04048C,0xFF000000 ++#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1F04048C,0x000F0000 ++#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1F04048C,0x0000FF00 ++#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1F04048C,0x0000000F ++ ++#define SRM_DC_RL4_CH_6__ADDR 0x1F040490 ++#define SRM_DC_RL4_CH_6__EMPTY 0x1F040490,0x00000000 ++#define SRM_DC_RL4_CH_6__FULL 0x1F040490,0xffffffff ++#define SRM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1F040490,0x0000FF00 ++#define SRM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1F040490,0x0000000F ++ ++#define IPU_MEM_DC_MICROCODE_BASE_ADDR 0x1F080000 ++ ++#define IPU_ISP_TBPR_0__ADDR 0x1F0C0000 ++#define IPU_ISP_TBPR_0__EMPTY 0x1F0C0000,0x00000000 ++#define IPU_ISP_TBPR_0__FULL 0x1F0C0000,0xffffffff ++#define IPU_ISP_TBPR_0__HCB_0 0x1F0C0000,0x0FFF0000 ++#define IPU_ISP_TBPR_0__VCB_0 0x1F0C0000,0x00000FFF ++ ++#define IPU_ISP_TBPR_1__ADDR 0x1F0C0004 ++#define IPU_ISP_TBPR_1__EMPTY 0x1F0C0004,0x00000000 ++#define IPU_ISP_TBPR_1__FULL 0x1F0C0004,0xffffffff ++#define IPU_ISP_TBPR_1__HCB_1 0x1F0C0004,0x0FFF0000 ++#define IPU_ISP_TBPR_1__VCB_1 0x1F0C0004,0x00000FFF ++ ++#define IPU_ISP_TBPR_2__ADDR 0x1F0C0008 ++#define IPU_ISP_TBPR_2__EMPTY 0x1F0C0008,0x00000000 ++#define IPU_ISP_TBPR_2__FULL 0x1F0C0008,0xffffffff ++#define IPU_ISP_TBPR_2__HCB_2 0x1F0C0008,0x0FFF0000 ++#define IPU_ISP_TBPR_2__VCB_2 0x1F0C0008,0x00000FFF ++ ++#define IPU_ISP_TBPR_3__ADDR 0x1F0C000C ++#define IPU_ISP_TBPR_3__EMPTY 0x1F0C000C,0x00000000 ++#define IPU_ISP_TBPR_3__FULL 0x1F0C000C,0xffffffff ++#define IPU_ISP_TBPR_3__HCB_3 0x1F0C000C,0x0FFF0000 ++#define IPU_ISP_TBPR_3__VCB_3 0x1F0C000C,0x00000FFF ++ ++#define IPU_ISP_TBPR_4__ADDR 0x1F0C0010 ++#define IPU_ISP_TBPR_4__EMPTY 0x1F0C0010,0x00000000 ++#define IPU_ISP_TBPR_4__FULL 0x1F0C0010,0xffffffff ++#define IPU_ISP_TBPR_4__HCB_4 0x1F0C0010,0x0FFF0000 ++#define IPU_ISP_TBPR_4__VCB_4 0x1F0C0010,0x00000FFF ++ ++#define IPU_ISP_TBPR_5__ADDR 0x1F0C0014 ++#define IPU_ISP_TBPR_5__EMPTY 0x1F0C0014,0x00000000 ++#define IPU_ISP_TBPR_5__FULL 0x1F0C0014,0xffffffff ++#define IPU_ISP_TBPR_5__HCB_5 0x1F0C0014,0x0FFF0000 ++#define IPU_ISP_TBPR_5__VCB_5 0x1F0C0014,0x00000FFF ++ ++#define IPU_ISP_TBPR_6__ADDR 0x1F0C0018 ++#define IPU_ISP_TBPR_6__EMPTY 0x1F0C0018,0x00000000 ++#define IPU_ISP_TBPR_6__FULL 0x1F0C0018,0xffffffff ++#define IPU_ISP_TBPR_6__HCB_6 0x1F0C0018,0x0FFF0000 ++#define IPU_ISP_TBPR_6__VCB_6 0x1F0C0018,0x00000FFF ++ ++#define IPU_ISP_TBPR_7__ADDR 0x1F0C001C ++#define IPU_ISP_TBPR_7__EMPTY 0x1F0C001C,0x00000000 ++#define IPU_ISP_TBPR_7__FULL 0x1F0C001C,0xffffffff ++#define IPU_ISP_TBPR_7__HCB_7 0x1F0C001C,0x0FFF0000 ++#define IPU_ISP_TBPR_7__VCB_7 0x1F0C001C,0x00000FFF ++ ++#define IPU_ISP_TBPR_8__ADDR 0x1F0C0020 ++#define IPU_ISP_TBPR_8__EMPTY 0x1F0C0020,0x00000000 ++#define IPU_ISP_TBPR_8__FULL 0x1F0C0020,0xffffffff ++#define IPU_ISP_TBPR_8__HCB_8 0x1F0C0020,0x0FFF0000 ++#define IPU_ISP_TBPR_8__VCB_8 0x1F0C0020,0x00000FFF ++ ++#define IPU_ISP_TBPR_9__ADDR 0x1F0C0024 ++#define IPU_ISP_TBPR_9__EMPTY 0x1F0C0024,0x00000000 ++#define IPU_ISP_TBPR_9__FULL 0x1F0C0024,0xffffffff ++#define IPU_ISP_TBPR_9__HCB_9 0x1F0C0024,0x0FFF0000 ++#define IPU_ISP_TBPR_9__VCB_9 0x1F0C0024,0x00000FFF ++ ++#define IPU_ISP_TBPR_10__ADDR 0x1F0C0028 ++#define IPU_ISP_TBPR_10__EMPTY 0x1F0C0028,0x00000000 ++#define IPU_ISP_TBPR_10__FULL 0x1F0C0028,0xffffffff ++#define IPU_ISP_TBPR_10__HCB_10 0x1F0C0028,0x0FFF0000 ++#define IPU_ISP_TBPR_10__VCB_10 0x1F0C0028,0x00000FFF ++ ++#define IPU_ISP_TBPR_11__ADDR 0x1F0C002C ++#define IPU_ISP_TBPR_11__EMPTY 0x1F0C002C,0x00000000 ++#define IPU_ISP_TBPR_11__FULL 0x1F0C002C,0xffffffff ++#define IPU_ISP_TBPR_11__HCB_11 0x1F0C002C,0x0FFF0000 ++#define IPU_ISP_TBPR_11__VCB_11 0x1F0C002C,0x00000FFF ++ ++#define IPU_ISP_TBPR_12__ADDR 0x1F0C0030 ++#define IPU_ISP_TBPR_12__EMPTY 0x1F0C0030,0x00000000 ++#define IPU_ISP_TBPR_12__FULL 0x1F0C0030,0xffffffff ++#define IPU_ISP_TBPR_12__HCB_12 0x1F0C0030,0x0FFF0000 ++#define IPU_ISP_TBPR_12__VCB_12 0x1F0C0030,0x00000FFF ++ ++#define IPU_ISP_TBPR_13__ADDR 0x1F0C0034 ++#define IPU_ISP_TBPR_13__EMPTY 0x1F0C0034,0x00000000 ++#define IPU_ISP_TBPR_13__FULL 0x1F0C0034,0xffffffff ++#define IPU_ISP_TBPR_13__HCB_13 0x1F0C0034,0x0FFF0000 ++#define IPU_ISP_TBPR_13__VCB_13 0x1F0C0034,0x00000FFF ++ ++#define IPU_ISP_TBPR_14__ADDR 0x1F0C0038 ++#define IPU_ISP_TBPR_14__EMPTY 0x1F0C0038,0x00000000 ++#define IPU_ISP_TBPR_14__FULL 0x1F0C0038,0xffffffff ++#define IPU_ISP_TBPR_14__HCB_14 0x1F0C0038,0x0FFF0000 ++#define IPU_ISP_TBPR_14__VCB_14 0x1F0C0038,0x00000FFF ++ ++#define IPU_ISP_TBPR_15__ADDR 0x1F0C003C ++#define IPU_ISP_TBPR_15__EMPTY 0x1F0C003C,0x00000000 ++#define IPU_ISP_TBPR_15__FULL 0x1F0C003C,0xffffffff ++#define IPU_ISP_TBPR_15__HCB_15 0x1F0C003C,0x0FFF0000 ++#define IPU_ISP_TBPR_15__VCB_15 0x1F0C003C,0x00000FFF ++ ++#define IPU_ISP_TBPR_16__ADDR 0x1F0C0040 ++#define IPU_ISP_TBPR_16__EMPTY 0x1F0C0040,0x00000000 ++#define IPU_ISP_TBPR_16__FULL 0x1F0C0040,0xffffffff ++#define IPU_ISP_TBPR_16__HCB_16 0x1F0C0040,0x0FFF0000 ++#define IPU_ISP_TBPR_16__VCB_16 0x1F0C0040,0x00000FFF ++ ++#define IPU_ISP_TBPR_17__ADDR 0x1F0C0044 ++#define IPU_ISP_TBPR_17__EMPTY 0x1F0C0044,0x00000000 ++#define IPU_ISP_TBPR_17__FULL 0x1F0C0044,0xffffffff ++#define IPU_ISP_TBPR_17__HCB_17 0x1F0C0044,0x0FFF0000 ++#define IPU_ISP_TBPR_17__VCB_17 0x1F0C0044,0x00000FFF ++ ++#define IPU_ISP_TBPR_18__ADDR 0x1F0C0048 ++#define IPU_ISP_TBPR_18__EMPTY 0x1F0C0048,0x00000000 ++#define IPU_ISP_TBPR_18__FULL 0x1F0C0048,0xffffffff ++#define IPU_ISP_TBPR_18__HCB_18 0x1F0C0048,0x0FFF0000 ++#define IPU_ISP_TBPR_18__VCB_18 0x1F0C0048,0x00000FFF ++ ++#define IPU_ISP_TBPR_19__ADDR 0x1F0C004C ++#define IPU_ISP_TBPR_19__EMPTY 0x1F0C004C,0x00000000 ++#define IPU_ISP_TBPR_19__FULL 0x1F0C004C,0xffffffff ++#define IPU_ISP_TBPR_19__HCB_19 0x1F0C004C,0x0FFF0000 ++#define IPU_ISP_TBPR_19__VCB_19 0x1F0C004C,0x00000FFF ++ ++#define IPU_ISP_TBPR_20__ADDR 0x1F0C0050 ++#define IPU_ISP_TBPR_20__EMPTY 0x1F0C0050,0x00000000 ++#define IPU_ISP_TBPR_20__FULL 0x1F0C0050,0xffffffff ++#define IPU_ISP_TBPR_20__HCB_20 0x1F0C0050,0x0FFF0000 ++#define IPU_ISP_TBPR_20__VCB_20 0x1F0C0050,0x00000FFF ++ ++#define IPU_ISP_TBPR_21__ADDR 0x1F0C0054 ++#define IPU_ISP_TBPR_21__EMPTY 0x1F0C0054,0x00000000 ++#define IPU_ISP_TBPR_21__FULL 0x1F0C0054,0xffffffff ++#define IPU_ISP_TBPR_21__HCB_21 0x1F0C0054,0x0FFF0000 ++#define IPU_ISP_TBPR_21__VCB_21 0x1F0C0054,0x00000FFF ++ ++#define IPU_ISP_TBPR_22__ADDR 0x1F0C0058 ++#define IPU_ISP_TBPR_22__EMPTY 0x1F0C0058,0x00000000 ++#define IPU_ISP_TBPR_22__FULL 0x1F0C0058,0xffffffff ++#define IPU_ISP_TBPR_22__HCB_22 0x1F0C0058,0x0FFF0000 ++#define IPU_ISP_TBPR_22__VCB_22 0x1F0C0058,0x00000FFF ++ ++#define IPU_ISP_TBPR_23__ADDR 0x1F0C005C ++#define IPU_ISP_TBPR_23__EMPTY 0x1F0C005C,0x00000000 ++#define IPU_ISP_TBPR_23__FULL 0x1F0C005C,0xffffffff ++#define IPU_ISP_TBPR_23__HCB_23 0x1F0C005C,0x0FFF0000 ++#define IPU_ISP_TBPR_23__VCB_23 0x1F0C005C,0x00000FFF ++ ++#define IPU_ISP_TBPR_24__ADDR 0x1F0C0060 ++#define IPU_ISP_TBPR_24__EMPTY 0x1F0C0060,0x00000000 ++#define IPU_ISP_TBPR_24__FULL 0x1F0C0060,0xffffffff ++#define IPU_ISP_TBPR_24__HCB_24 0x1F0C0060,0x0FFF0000 ++#define IPU_ISP_TBPR_24__VCB_24 0x1F0C0060,0x00000FFF ++ ++#define IPU_ISP_TBPR_25__ADDR 0x1F0C0064 ++#define IPU_ISP_TBPR_25__EMPTY 0x1F0C0064,0x00000000 ++#define IPU_ISP_TBPR_25__FULL 0x1F0C0064,0xffffffff ++#define IPU_ISP_TBPR_25__HCB_25 0x1F0C0064,0x0FFF0000 ++#define IPU_ISP_TBPR_25__VCB_25 0x1F0C0064,0x00000FFF ++ ++#define IPU_ISP_TBPR_26__ADDR 0x1F0C0068 ++#define IPU_ISP_TBPR_26__EMPTY 0x1F0C0068,0x00000000 ++#define IPU_ISP_TBPR_26__FULL 0x1F0C0068,0xffffffff ++#define IPU_ISP_TBPR_26__HCB_26 0x1F0C0068,0x0FFF0000 ++#define IPU_ISP_TBPR_26__VCB_26 0x1F0C0068,0x00000FFF ++ ++#define IPU_ISP_TBPR_27__ADDR 0x1F0C006C ++#define IPU_ISP_TBPR_27__EMPTY 0x1F0C006C,0x00000000 ++#define IPU_ISP_TBPR_27__FULL 0x1F0C006C,0xffffffff ++#define IPU_ISP_TBPR_27__HCB_27 0x1F0C006C,0x0FFF0000 ++#define IPU_ISP_TBPR_27__VCB_27 0x1F0C006C,0x00000FFF ++ ++#define IPU_ISP_TBPR_28__ADDR 0x1F0C0070 ++#define IPU_ISP_TBPR_28__EMPTY 0x1F0C0070,0x00000000 ++#define IPU_ISP_TBPR_28__FULL 0x1F0C0070,0xffffffff ++#define IPU_ISP_TBPR_28__HCB_28 0x1F0C0070,0x0FFF0000 ++#define IPU_ISP_TBPR_28__VCB_28 0x1F0C0070,0x00000FFF ++ ++#define IPU_ISP_TBPR_29__ADDR 0x1F0C0074 ++#define IPU_ISP_TBPR_29__EMPTY 0x1F0C0074,0x00000000 ++#define IPU_ISP_TBPR_29__FULL 0x1F0C0074,0xffffffff ++#define IPU_ISP_TBPR_29__HCB_29 0x1F0C0074,0x0FFF0000 ++#define IPU_ISP_TBPR_29__VCB_29 0x1F0C0074,0x00000FFF ++ ++#define IPU_ISP_TBPR_30__ADDR 0x1F0C0078 ++#define IPU_ISP_TBPR_30__EMPTY 0x1F0C0078,0x00000000 ++#define IPU_ISP_TBPR_30__FULL 0x1F0C0078,0xffffffff ++#define IPU_ISP_TBPR_30__HCB_30 0x1F0C0078,0x0FFF0000 ++#define IPU_ISP_TBPR_30__VCB_30 0x1F0C0078,0x00000FFF ++ ++#define IPU_ISP_TBPR_31__ADDR 0x1F0C007C ++#define IPU_ISP_TBPR_31__EMPTY 0x1F0C007C,0x00000000 ++#define IPU_ISP_TBPR_31__FULL 0x1F0C007C,0xffffffff ++#define IPU_ISP_TBPR_31__HCB_31 0x1F0C007C,0x0FFF0000 ++#define IPU_ISP_TBPR_31__VCB_31 0x1F0C007C,0x00000FFF ++ ++#define IPU_ISP_TBPR_32__ADDR 0x1F0C0080 ++#define IPU_ISP_TBPR_32__EMPTY 0x1F0C0080,0x00000000 ++#define IPU_ISP_TBPR_32__FULL 0x1F0C0080,0xffffffff ++#define IPU_ISP_TBPR_32__HCB_32 0x1F0C0080,0x0FFF0000 ++#define IPU_ISP_TBPR_32__VCB_32 0x1F0C0080,0x00000FFF ++ ++#define IPU_ISP_TBPR_33__ADDR 0x1F0C0084 ++#define IPU_ISP_TBPR_33__EMPTY 0x1F0C0084,0x00000000 ++#define IPU_ISP_TBPR_33__FULL 0x1F0C0084,0xffffffff ++#define IPU_ISP_TBPR_33__HCB_33 0x1F0C0084,0x0FFF0000 ++#define IPU_ISP_TBPR_33__VCB_33 0x1F0C0084,0x00000FFF ++ ++#define IPU_ISP_TBPR_34__ADDR 0x1F0C0088 ++#define IPU_ISP_TBPR_34__EMPTY 0x1F0C0088,0x00000000 ++#define IPU_ISP_TBPR_34__FULL 0x1F0C0088,0xffffffff ++#define IPU_ISP_TBPR_34__HCB_34 0x1F0C0088,0x0FFF0000 ++#define IPU_ISP_TBPR_34__VCB_34 0x1F0C0088,0x00000FFF ++ ++#define IPU_ISP_TBPR_35__ADDR 0x1F0C008C ++#define IPU_ISP_TBPR_35__EMPTY 0x1F0C008C,0x00000000 ++#define IPU_ISP_TBPR_35__FULL 0x1F0C008C,0xffffffff ++#define IPU_ISP_TBPR_35__HCB_35 0x1F0C008C,0x0FFF0000 ++#define IPU_ISP_TBPR_35__VCB_35 0x1F0C008C,0x00000FFF ++ ++#define IPU_ISP_TBPR_36__ADDR 0x1F0C0090 ++#define IPU_ISP_TBPR_36__EMPTY 0x1F0C0090,0x00000000 ++#define IPU_ISP_TBPR_36__FULL 0x1F0C0090,0xffffffff ++#define IPU_ISP_TBPR_36__HCB_36 0x1F0C0090,0x0FFF0000 ++#define IPU_ISP_TBPR_36__VCB_36 0x1F0C0090,0x00000FFF ++ ++#define IPU_ISP_TBPR_37__ADDR 0x1F0C0094 ++#define IPU_ISP_TBPR_37__EMPTY 0x1F0C0094,0x00000000 ++#define IPU_ISP_TBPR_37__FULL 0x1F0C0094,0xffffffff ++#define IPU_ISP_TBPR_37__HCB_37 0x1F0C0094,0x0FFF0000 ++#define IPU_ISP_TBPR_37__VCB_37 0x1F0C0094,0x00000FFF ++ ++#define IPU_ISP_TBPR_38__ADDR 0x1F0C0098 ++#define IPU_ISP_TBPR_38__EMPTY 0x1F0C0098,0x00000000 ++#define IPU_ISP_TBPR_38__FULL 0x1F0C0098,0xffffffff ++#define IPU_ISP_TBPR_38__HCB_38 0x1F0C0098,0x0FFF0000 ++#define IPU_ISP_TBPR_38__VCB_38 0x1F0C0098,0x00000FFF ++ ++#define IPU_ISP_TBPR_39__ADDR 0x1F0C009C ++#define IPU_ISP_TBPR_39__EMPTY 0x1F0C009C,0x00000000 ++#define IPU_ISP_TBPR_39__FULL 0x1F0C009C,0xffffffff ++#define IPU_ISP_TBPR_39__HCB_39 0x1F0C009C,0x0FFF0000 ++#define IPU_ISP_TBPR_39__VCB_39 0x1F0C009C,0x00000FFF ++ ++#define IPU_ISP_TBPR_40__ADDR 0x1F0C00A0 ++#define IPU_ISP_TBPR_40__EMPTY 0x1F0C00A0,0x00000000 ++#define IPU_ISP_TBPR_40__FULL 0x1F0C00A0,0xffffffff ++#define IPU_ISP_TBPR_40__HCB_40 0x1F0C00A0,0x0FFF0000 ++#define IPU_ISP_TBPR_40__VCB_40 0x1F0C00A0,0x00000FFF ++ ++#define IPU_ISP_TBPR_41__ADDR 0x1F0C00A4 ++#define IPU_ISP_TBPR_41__EMPTY 0x1F0C00A4,0x00000000 ++#define IPU_ISP_TBPR_41__FULL 0x1F0C00A4,0xffffffff ++#define IPU_ISP_TBPR_41__HCB_41 0x1F0C00A4,0x0FFF0000 ++#define IPU_ISP_TBPR_41__VCB_41 0x1F0C00A4,0x00000FFF ++ ++#define IPU_ISP_TBPR_42__ADDR 0x1F0C00A8 ++#define IPU_ISP_TBPR_42__EMPTY 0x1F0C00A8,0x00000000 ++#define IPU_ISP_TBPR_42__FULL 0x1F0C00A8,0xffffffff ++#define IPU_ISP_TBPR_42__HCB_42 0x1F0C00A8,0x0FFF0000 ++#define IPU_ISP_TBPR_42__VCB_42 0x1F0C00A8,0x00000FFF ++ ++#define IPU_ISP_TBPR_43__ADDR 0x1F0C00AC ++#define IPU_ISP_TBPR_43__EMPTY 0x1F0C00AC,0x00000000 ++#define IPU_ISP_TBPR_43__FULL 0x1F0C00AC,0xffffffff ++#define IPU_ISP_TBPR_43__HCB_43 0x1F0C00AC,0x0FFF0000 ++#define IPU_ISP_TBPR_43__VCB_43 0x1F0C00AC,0x00000FFF ++ ++#define IPU_ISP_TBPR_44__ADDR 0x1F0C00B0 ++#define IPU_ISP_TBPR_44__EMPTY 0x1F0C00B0,0x00000000 ++#define IPU_ISP_TBPR_44__FULL 0x1F0C00B0,0xffffffff ++#define IPU_ISP_TBPR_44__HCB_44 0x1F0C00B0,0x0FFF0000 ++#define IPU_ISP_TBPR_44__VCB_44 0x1F0C00B0,0x00000FFF ++ ++#define IPU_ISP_TBPR_45__ADDR 0x1F0C00B4 ++#define IPU_ISP_TBPR_45__EMPTY 0x1F0C00B4,0x00000000 ++#define IPU_ISP_TBPR_45__FULL 0x1F0C00B4,0xffffffff ++#define IPU_ISP_TBPR_45__HCB_45 0x1F0C00B4,0x0FFF0000 ++#define IPU_ISP_TBPR_45__VCB_45 0x1F0C00B4,0x00000FFF ++ ++#define IPU_ISP_TBPR_46__ADDR 0x1F0C00B8 ++#define IPU_ISP_TBPR_46__EMPTY 0x1F0C00B8,0x00000000 ++#define IPU_ISP_TBPR_46__FULL 0x1F0C00B8,0xffffffff ++#define IPU_ISP_TBPR_46__HCB_46 0x1F0C00B8,0x0FFF0000 ++#define IPU_ISP_TBPR_46__VCB_46 0x1F0C00B8,0x00000FFF ++ ++#define IPU_ISP_TBPR_47__ADDR 0x1F0C00BC ++#define IPU_ISP_TBPR_47__EMPTY 0x1F0C00BC,0x00000000 ++#define IPU_ISP_TBPR_47__FULL 0x1F0C00BC,0xffffffff ++#define IPU_ISP_TBPR_47__HCB_47 0x1F0C00BC,0x0FFF0000 ++#define IPU_ISP_TBPR_47__VCB_47 0x1F0C00BC,0x00000FFF ++ ++#define IPU_ISP_TBPR_48__ADDR 0x1F0C00C0 ++#define IPU_ISP_TBPR_48__EMPTY 0x1F0C00C0,0x00000000 ++#define IPU_ISP_TBPR_48__FULL 0x1F0C00C0,0xffffffff ++#define IPU_ISP_TBPR_48__HCB_48 0x1F0C00C0,0x0FFF0000 ++#define IPU_ISP_TBPR_48__VCB_48 0x1F0C00C0,0x00000FFF ++ ++#define IPU_ISP_TBPR_49__ADDR 0x1F0C00C4 ++#define IPU_ISP_TBPR_49__EMPTY 0x1F0C00C4,0x00000000 ++#define IPU_ISP_TBPR_49__FULL 0x1F0C00C4,0xffffffff ++#define IPU_ISP_TBPR_49__HCB_49 0x1F0C00C4,0x0FFF0000 ++#define IPU_ISP_TBPR_49__VCB_49 0x1F0C00C4,0x00000FFF ++ ++#define IPU_ISP_TBPR_50__ADDR 0x1F0C00C8 ++#define IPU_ISP_TBPR_50__EMPTY 0x1F0C00C8,0x00000000 ++#define IPU_ISP_TBPR_50__FULL 0x1F0C00C8,0xffffffff ++#define IPU_ISP_TBPR_50__HCB_50 0x1F0C00C8,0x0FFF0000 ++#define IPU_ISP_TBPR_50__VCB_50 0x1F0C00C8,0x00000FFF ++ ++#define IPU_ISP_TBPR_51__ADDR 0x1F0C00CC ++#define IPU_ISP_TBPR_51__EMPTY 0x1F0C00CC,0x00000000 ++#define IPU_ISP_TBPR_51__FULL 0x1F0C00CC,0xffffffff ++#define IPU_ISP_TBPR_51__HCB_51 0x1F0C00CC,0x0FFF0000 ++#define IPU_ISP_TBPR_51__VCB_51 0x1F0C00CC,0x00000FFF ++ ++#define IPU_ISP_TBPR_52__ADDR 0x1F0C00D0 ++#define IPU_ISP_TBPR_52__EMPTY 0x1F0C00D0,0x00000000 ++#define IPU_ISP_TBPR_52__FULL 0x1F0C00D0,0xffffffff ++#define IPU_ISP_TBPR_52__HCB_52 0x1F0C00D0,0x0FFF0000 ++#define IPU_ISP_TBPR_52__VCB_52 0x1F0C00D0,0x00000FFF ++ ++#define IPU_ISP_TBPR_53__ADDR 0x1F0C00D4 ++#define IPU_ISP_TBPR_53__EMPTY 0x1F0C00D4,0x00000000 ++#define IPU_ISP_TBPR_53__FULL 0x1F0C00D4,0xffffffff ++#define IPU_ISP_TBPR_53__HCB_53 0x1F0C00D4,0x0FFF0000 ++#define IPU_ISP_TBPR_53__VCB_53 0x1F0C00D4,0x00000FFF ++ ++#define IPU_ISP_TBPR_54__ADDR 0x1F0C00D8 ++#define IPU_ISP_TBPR_54__EMPTY 0x1F0C00D8,0x00000000 ++#define IPU_ISP_TBPR_54__FULL 0x1F0C00D8,0xffffffff ++#define IPU_ISP_TBPR_54__HCB_54 0x1F0C00D8,0x0FFF0000 ++#define IPU_ISP_TBPR_54__VCB_54 0x1F0C00D8,0x00000FFF ++ ++#define IPU_ISP_TBPR_55__ADDR 0x1F0C00DC ++#define IPU_ISP_TBPR_55__EMPTY 0x1F0C00DC,0x00000000 ++#define IPU_ISP_TBPR_55__FULL 0x1F0C00DC,0xffffffff ++#define IPU_ISP_TBPR_55__HCB_55 0x1F0C00DC,0x0FFF0000 ++#define IPU_ISP_TBPR_55__VCB_55 0x1F0C00DC,0x00000FFF ++ ++#define IPU_ISP_TBPR_56__ADDR 0x1F0C00E0 ++#define IPU_ISP_TBPR_56__EMPTY 0x1F0C00E0,0x00000000 ++#define IPU_ISP_TBPR_56__FULL 0x1F0C00E0,0xffffffff ++#define IPU_ISP_TBPR_56__HCB_56 0x1F0C00E0,0x0FFF0000 ++#define IPU_ISP_TBPR_56__VCB_56 0x1F0C00E0,0x00000FFF ++ ++#define IPU_ISP_TBPR_57__ADDR 0x1F0C00E4 ++#define IPU_ISP_TBPR_57__EMPTY 0x1F0C00E4,0x00000000 ++#define IPU_ISP_TBPR_57__FULL 0x1F0C00E4,0xffffffff ++#define IPU_ISP_TBPR_57__HCB_57 0x1F0C00E4,0x0FFF0000 ++#define IPU_ISP_TBPR_57__VCB_57 0x1F0C00E4,0x00000FFF ++ ++#define IPU_ISP_TBPR_58__ADDR 0x1F0C00E8 ++#define IPU_ISP_TBPR_58__EMPTY 0x1F0C00E8,0x00000000 ++#define IPU_ISP_TBPR_58__FULL 0x1F0C00E8,0xffffffff ++#define IPU_ISP_TBPR_58__HCB_58 0x1F0C00E8,0x0FFF0000 ++#define IPU_ISP_TBPR_58__VCB_58 0x1F0C00E8,0x00000FFF ++ ++#define IPU_ISP_TBPR_59__ADDR 0x1F0C00EC ++#define IPU_ISP_TBPR_59__EMPTY 0x1F0C00EC,0x00000000 ++#define IPU_ISP_TBPR_59__FULL 0x1F0C00EC,0xffffffff ++#define IPU_ISP_TBPR_59__HCB_59 0x1F0C00EC,0x0FFF0000 ++#define IPU_ISP_TBPR_59__VCB_59 0x1F0C00EC,0x00000FFF ++ ++#define IPU_ISP_TBPR_60__ADDR 0x1F0C00F0 ++#define IPU_ISP_TBPR_60__EMPTY 0x1F0C00F0,0x00000000 ++#define IPU_ISP_TBPR_60__FULL 0x1F0C00F0,0xffffffff ++#define IPU_ISP_TBPR_60__HCB_60 0x1F0C00F0,0x0FFF0000 ++#define IPU_ISP_TBPR_60__VCB_60 0x1F0C00F0,0x00000FFF ++ ++#define IPU_ISP_TBPR_61__ADDR 0x1F0C00F4 ++#define IPU_ISP_TBPR_61__EMPTY 0x1F0C00F4,0x00000000 ++#define IPU_ISP_TBPR_61__FULL 0x1F0C00F4,0xffffffff ++#define IPU_ISP_TBPR_61__HCB_61 0x1F0C00F4,0x0FFF0000 ++#define IPU_ISP_TBPR_61__VCB_61 0x1F0C00F4,0x00000FFF ++ ++#define IPU_ISP_TBPR_62__ADDR 0x1F0C00F8 ++#define IPU_ISP_TBPR_62__EMPTY 0x1F0C00F8,0x00000000 ++#define IPU_ISP_TBPR_62__FULL 0x1F0C00F8,0xffffffff ++#define IPU_ISP_TBPR_62__HCB_62 0x1F0C00F8,0x0FFF0000 ++#define IPU_ISP_TBPR_62__VCB_62 0x1F0C00F8,0x00000FFF ++ ++#define IPU_ISP_TBPR_63__ADDR 0x1F0C00FC ++#define IPU_ISP_TBPR_63__EMPTY 0x1F0C00FC,0x00000000 ++#define IPU_ISP_TBPR_63__FULL 0x1F0C00FC,0xffffffff ++#define IPU_ISP_TBPR_63__HCB_63 0x1F0C00FC,0x0FFF0000 ++#define IPU_ISP_TBPR_63__VCB_63 0x1F0C00FC,0x00000FFF ++ ++#define SRM_ISP_TBPR_0__ADDR 0x1F0C0100 ++#define SRM_ISP_TBPR_0__EMPTY 0x1F0C0100,0x00000000 ++#define SRM_ISP_TBPR_0__FULL 0x1F0C0100,0xffffffff ++#define SRM_ISP_TBPR_0__HCB_0 0x1F0C0100,0x0FFF0000 ++#define SRM_ISP_TBPR_0__VCB_0 0x1F0C0100,0x00000FFF ++ ++#define SRM_ISP_TBPR_1__ADDR 0x1F0C0104 ++#define SRM_ISP_TBPR_1__EMPTY 0x1F0C0104,0x00000000 ++#define SRM_ISP_TBPR_1__FULL 0x1F0C0104,0xffffffff ++#define SRM_ISP_TBPR_1__HCB_1 0x1F0C0104,0x0FFF0000 ++#define SRM_ISP_TBPR_1__VCB_1 0x1F0C0104,0x00000FFF ++ ++#define SRM_ISP_TBPR_2__ADDR 0x1F0C0108 ++#define SRM_ISP_TBPR_2__EMPTY 0x1F0C0108,0x00000000 ++#define SRM_ISP_TBPR_2__FULL 0x1F0C0108,0xffffffff ++#define SRM_ISP_TBPR_2__HCB_2 0x1F0C0108,0x0FFF0000 ++#define SRM_ISP_TBPR_2__VCB_2 0x1F0C0108,0x00000FFF ++ ++#define SRM_ISP_TBPR_3__ADDR 0x1F0C010C ++#define SRM_ISP_TBPR_3__EMPTY 0x1F0C010C,0x00000000 ++#define SRM_ISP_TBPR_3__FULL 0x1F0C010C,0xffffffff ++#define SRM_ISP_TBPR_3__HCB_3 0x1F0C010C,0x0FFF0000 ++#define SRM_ISP_TBPR_3__VCB_3 0x1F0C010C,0x00000FFF ++ ++#define SRM_ISP_TBPR_4__ADDR 0x1F0C0110 ++#define SRM_ISP_TBPR_4__EMPTY 0x1F0C0110,0x00000000 ++#define SRM_ISP_TBPR_4__FULL 0x1F0C0110,0xffffffff ++#define SRM_ISP_TBPR_4__HCB_4 0x1F0C0110,0x0FFF0000 ++#define SRM_ISP_TBPR_4__VCB_4 0x1F0C0110,0x00000FFF ++ ++#define SRM_ISP_TBPR_5__ADDR 0x1F0C0114 ++#define SRM_ISP_TBPR_5__EMPTY 0x1F0C0114,0x00000000 ++#define SRM_ISP_TBPR_5__FULL 0x1F0C0114,0xffffffff ++#define SRM_ISP_TBPR_5__HCB_5 0x1F0C0114,0x0FFF0000 ++#define SRM_ISP_TBPR_5__VCB_5 0x1F0C0114,0x00000FFF ++ ++#define SRM_ISP_TBPR_6__ADDR 0x1F0C0118 ++#define SRM_ISP_TBPR_6__EMPTY 0x1F0C0118,0x00000000 ++#define SRM_ISP_TBPR_6__FULL 0x1F0C0118,0xffffffff ++#define SRM_ISP_TBPR_6__HCB_6 0x1F0C0118,0x0FFF0000 ++#define SRM_ISP_TBPR_6__VCB_6 0x1F0C0118,0x00000FFF ++ ++#define SRM_ISP_TBPR_7__ADDR 0x1F0C011C ++#define SRM_ISP_TBPR_7__EMPTY 0x1F0C011C,0x00000000 ++#define SRM_ISP_TBPR_7__FULL 0x1F0C011C,0xffffffff ++#define SRM_ISP_TBPR_7__HCB_7 0x1F0C011C,0x0FFF0000 ++#define SRM_ISP_TBPR_7__VCB_7 0x1F0C011C,0x00000FFF ++ ++#define SRM_ISP_TBPR_8__ADDR 0x1F0C0120 ++#define SRM_ISP_TBPR_8__EMPTY 0x1F0C0120,0x00000000 ++#define SRM_ISP_TBPR_8__FULL 0x1F0C0120,0xffffffff ++#define SRM_ISP_TBPR_8__HCB_8 0x1F0C0120,0x0FFF0000 ++#define SRM_ISP_TBPR_8__VCB_8 0x1F0C0120,0x00000FFF ++ ++#define SRM_ISP_TBPR_9__ADDR 0x1F0C0124 ++#define SRM_ISP_TBPR_9__EMPTY 0x1F0C0124,0x00000000 ++#define SRM_ISP_TBPR_9__FULL 0x1F0C0124,0xffffffff ++#define SRM_ISP_TBPR_9__HCB_9 0x1F0C0124,0x0FFF0000 ++#define SRM_ISP_TBPR_9__VCB_9 0x1F0C0124,0x00000FFF ++ ++#define SRM_ISP_TBPR_10__ADDR 0x1F0C0128 ++#define SRM_ISP_TBPR_10__EMPTY 0x1F0C0128,0x00000000 ++#define SRM_ISP_TBPR_10__FULL 0x1F0C0128,0xffffffff ++#define SRM_ISP_TBPR_10__HCB_10 0x1F0C0128,0x0FFF0000 ++#define SRM_ISP_TBPR_10__VCB_10 0x1F0C0128,0x00000FFF ++ ++#define SRM_ISP_TBPR_11__ADDR 0x1F0C012C ++#define SRM_ISP_TBPR_11__EMPTY 0x1F0C012C,0x00000000 ++#define SRM_ISP_TBPR_11__FULL 0x1F0C012C,0xffffffff ++#define SRM_ISP_TBPR_11__HCB_11 0x1F0C012C,0x0FFF0000 ++#define SRM_ISP_TBPR_11__VCB_11 0x1F0C012C,0x00000FFF ++ ++#define SRM_ISP_TBPR_12__ADDR 0x1F0C0130 ++#define SRM_ISP_TBPR_12__EMPTY 0x1F0C0130,0x00000000 ++#define SRM_ISP_TBPR_12__FULL 0x1F0C0130,0xffffffff ++#define SRM_ISP_TBPR_12__HCB_12 0x1F0C0130,0x0FFF0000 ++#define SRM_ISP_TBPR_12__VCB_12 0x1F0C0130,0x00000FFF ++ ++#define SRM_ISP_TBPR_13__ADDR 0x1F0C0134 ++#define SRM_ISP_TBPR_13__EMPTY 0x1F0C0134,0x00000000 ++#define SRM_ISP_TBPR_13__FULL 0x1F0C0134,0xffffffff ++#define SRM_ISP_TBPR_13__HCB_13 0x1F0C0134,0x0FFF0000 ++#define SRM_ISP_TBPR_13__VCB_13 0x1F0C0134,0x00000FFF ++ ++#define SRM_ISP_TBPR_14__ADDR 0x1F0C0138 ++#define SRM_ISP_TBPR_14__EMPTY 0x1F0C0138,0x00000000 ++#define SRM_ISP_TBPR_14__FULL 0x1F0C0138,0xffffffff ++#define SRM_ISP_TBPR_14__HCB_14 0x1F0C0138,0x0FFF0000 ++#define SRM_ISP_TBPR_14__VCB_14 0x1F0C0138,0x00000FFF ++ ++#define SRM_ISP_TBPR_15__ADDR 0x1F0C013C ++#define SRM_ISP_TBPR_15__EMPTY 0x1F0C013C,0x00000000 ++#define SRM_ISP_TBPR_15__FULL 0x1F0C013C,0xffffffff ++#define SRM_ISP_TBPR_15__HCB_15 0x1F0C013C,0x0FFF0000 ++#define SRM_ISP_TBPR_15__VCB_15 0x1F0C013C,0x00000FFF ++ ++#define SRM_ISP_TBPR_16__ADDR 0x1F0C0140 ++#define SRM_ISP_TBPR_16__EMPTY 0x1F0C0140,0x00000000 ++#define SRM_ISP_TBPR_16__FULL 0x1F0C0140,0xffffffff ++#define SRM_ISP_TBPR_16__HCB_16 0x1F0C0140,0x0FFF0000 ++#define SRM_ISP_TBPR_16__VCB_16 0x1F0C0140,0x00000FFF ++ ++#define SRM_ISP_TBPR_17__ADDR 0x1F0C0144 ++#define SRM_ISP_TBPR_17__EMPTY 0x1F0C0144,0x00000000 ++#define SRM_ISP_TBPR_17__FULL 0x1F0C0144,0xffffffff ++#define SRM_ISP_TBPR_17__HCB_17 0x1F0C0144,0x0FFF0000 ++#define SRM_ISP_TBPR_17__VCB_17 0x1F0C0144,0x00000FFF ++ ++#define SRM_ISP_TBPR_18__ADDR 0x1F0C0148 ++#define SRM_ISP_TBPR_18__EMPTY 0x1F0C0148,0x00000000 ++#define SRM_ISP_TBPR_18__FULL 0x1F0C0148,0xffffffff ++#define SRM_ISP_TBPR_18__HCB_18 0x1F0C0148,0x0FFF0000 ++#define SRM_ISP_TBPR_18__VCB_18 0x1F0C0148,0x00000FFF ++ ++#define SRM_ISP_TBPR_19__ADDR 0x1F0C014C ++#define SRM_ISP_TBPR_19__EMPTY 0x1F0C014C,0x00000000 ++#define SRM_ISP_TBPR_19__FULL 0x1F0C014C,0xffffffff ++#define SRM_ISP_TBPR_19__HCB_19 0x1F0C014C,0x0FFF0000 ++#define SRM_ISP_TBPR_19__VCB_19 0x1F0C014C,0x00000FFF ++ ++#define SRM_ISP_TBPR_20__ADDR 0x1F0C0150 ++#define SRM_ISP_TBPR_20__EMPTY 0x1F0C0150,0x00000000 ++#define SRM_ISP_TBPR_20__FULL 0x1F0C0150,0xffffffff ++#define SRM_ISP_TBPR_20__HCB_20 0x1F0C0150,0x0FFF0000 ++#define SRM_ISP_TBPR_20__VCB_20 0x1F0C0150,0x00000FFF ++ ++#define SRM_ISP_TBPR_21__ADDR 0x1F0C0154 ++#define SRM_ISP_TBPR_21__EMPTY 0x1F0C0154,0x00000000 ++#define SRM_ISP_TBPR_21__FULL 0x1F0C0154,0xffffffff ++#define SRM_ISP_TBPR_21__HCB_21 0x1F0C0154,0x0FFF0000 ++#define SRM_ISP_TBPR_21__VCB_21 0x1F0C0154,0x00000FFF ++ ++#define SRM_ISP_TBPR_22__ADDR 0x1F0C0158 ++#define SRM_ISP_TBPR_22__EMPTY 0x1F0C0158,0x00000000 ++#define SRM_ISP_TBPR_22__FULL 0x1F0C0158,0xffffffff ++#define SRM_ISP_TBPR_22__HCB_22 0x1F0C0158,0x0FFF0000 ++#define SRM_ISP_TBPR_22__VCB_22 0x1F0C0158,0x00000FFF ++ ++#define SRM_ISP_TBPR_23__ADDR 0x1F0C015C ++#define SRM_ISP_TBPR_23__EMPTY 0x1F0C015C,0x00000000 ++#define SRM_ISP_TBPR_23__FULL 0x1F0C015C,0xffffffff ++#define SRM_ISP_TBPR_23__HCB_23 0x1F0C015C,0x0FFF0000 ++#define SRM_ISP_TBPR_23__VCB_23 0x1F0C015C,0x00000FFF ++ ++#define SRM_ISP_TBPR_24__ADDR 0x1F0C0160 ++#define SRM_ISP_TBPR_24__EMPTY 0x1F0C0160,0x00000000 ++#define SRM_ISP_TBPR_24__FULL 0x1F0C0160,0xffffffff ++#define SRM_ISP_TBPR_24__HCB_24 0x1F0C0160,0x0FFF0000 ++#define SRM_ISP_TBPR_24__VCB_24 0x1F0C0160,0x00000FFF ++ ++#define SRM_ISP_TBPR_25__ADDR 0x1F0C0164 ++#define SRM_ISP_TBPR_25__EMPTY 0x1F0C0164,0x00000000 ++#define SRM_ISP_TBPR_25__FULL 0x1F0C0164,0xffffffff ++#define SRM_ISP_TBPR_25__HCB_25 0x1F0C0164,0x0FFF0000 ++#define SRM_ISP_TBPR_25__VCB_25 0x1F0C0164,0x00000FFF ++ ++#define SRM_ISP_TBPR_26__ADDR 0x1F0C0168 ++#define SRM_ISP_TBPR_26__EMPTY 0x1F0C0168,0x00000000 ++#define SRM_ISP_TBPR_26__FULL 0x1F0C0168,0xffffffff ++#define SRM_ISP_TBPR_26__HCB_26 0x1F0C0168,0x0FFF0000 ++#define SRM_ISP_TBPR_26__VCB_26 0x1F0C0168,0x00000FFF ++ ++#define SRM_ISP_TBPR_27__ADDR 0x1F0C016C ++#define SRM_ISP_TBPR_27__EMPTY 0x1F0C016C,0x00000000 ++#define SRM_ISP_TBPR_27__FULL 0x1F0C016C,0xffffffff ++#define SRM_ISP_TBPR_27__HCB_27 0x1F0C016C,0x0FFF0000 ++#define SRM_ISP_TBPR_27__VCB_27 0x1F0C016C,0x00000FFF ++ ++#define SRM_ISP_TBPR_28__ADDR 0x1F0C0170 ++#define SRM_ISP_TBPR_28__EMPTY 0x1F0C0170,0x00000000 ++#define SRM_ISP_TBPR_28__FULL 0x1F0C0170,0xffffffff ++#define SRM_ISP_TBPR_28__HCB_28 0x1F0C0170,0x0FFF0000 ++#define SRM_ISP_TBPR_28__VCB_28 0x1F0C0170,0x00000FFF ++ ++#define SRM_ISP_TBPR_29__ADDR 0x1F0C0174 ++#define SRM_ISP_TBPR_29__EMPTY 0x1F0C0174,0x00000000 ++#define SRM_ISP_TBPR_29__FULL 0x1F0C0174,0xffffffff ++#define SRM_ISP_TBPR_29__HCB_29 0x1F0C0174,0x0FFF0000 ++#define SRM_ISP_TBPR_29__VCB_29 0x1F0C0174,0x00000FFF ++ ++#define SRM_ISP_TBPR_30__ADDR 0x1F0C0178 ++#define SRM_ISP_TBPR_30__EMPTY 0x1F0C0178,0x00000000 ++#define SRM_ISP_TBPR_30__FULL 0x1F0C0178,0xffffffff ++#define SRM_ISP_TBPR_30__HCB_30 0x1F0C0178,0x0FFF0000 ++#define SRM_ISP_TBPR_30__VCB_30 0x1F0C0178,0x00000FFF ++ ++#define SRM_ISP_TBPR_31__ADDR 0x1F0C017C ++#define SRM_ISP_TBPR_31__EMPTY 0x1F0C017C,0x00000000 ++#define SRM_ISP_TBPR_31__FULL 0x1F0C017C,0xffffffff ++#define SRM_ISP_TBPR_31__HCB_31 0x1F0C017C,0x0FFF0000 ++#define SRM_ISP_TBPR_31__VCB_31 0x1F0C017C,0x00000FFF ++ ++#define SRM_ISP_TBPR_32__ADDR 0x1F0C0180 ++#define SRM_ISP_TBPR_32__EMPTY 0x1F0C0180,0x00000000 ++#define SRM_ISP_TBPR_32__FULL 0x1F0C0180,0xffffffff ++#define SRM_ISP_TBPR_32__HCB_32 0x1F0C0180,0x0FFF0000 ++#define SRM_ISP_TBPR_32__VCB_32 0x1F0C0180,0x00000FFF ++ ++#define SRM_ISP_TBPR_33__ADDR 0x1F0C0184 ++#define SRM_ISP_TBPR_33__EMPTY 0x1F0C0184,0x00000000 ++#define SRM_ISP_TBPR_33__FULL 0x1F0C0184,0xffffffff ++#define SRM_ISP_TBPR_33__HCB_33 0x1F0C0184,0x0FFF0000 ++#define SRM_ISP_TBPR_33__VCB_33 0x1F0C0184,0x00000FFF ++ ++#define SRM_ISP_TBPR_34__ADDR 0x1F0C0188 ++#define SRM_ISP_TBPR_34__EMPTY 0x1F0C0188,0x00000000 ++#define SRM_ISP_TBPR_34__FULL 0x1F0C0188,0xffffffff ++#define SRM_ISP_TBPR_34__HCB_34 0x1F0C0188,0x0FFF0000 ++#define SRM_ISP_TBPR_34__VCB_34 0x1F0C0188,0x00000FFF ++ ++#define SRM_ISP_TBPR_35__ADDR 0x1F0C018C ++#define SRM_ISP_TBPR_35__EMPTY 0x1F0C018C,0x00000000 ++#define SRM_ISP_TBPR_35__FULL 0x1F0C018C,0xffffffff ++#define SRM_ISP_TBPR_35__HCB_35 0x1F0C018C,0x0FFF0000 ++#define SRM_ISP_TBPR_35__VCB_35 0x1F0C018C,0x00000FFF ++ ++#define SRM_ISP_TBPR_36__ADDR 0x1F0C0190 ++#define SRM_ISP_TBPR_36__EMPTY 0x1F0C0190,0x00000000 ++#define SRM_ISP_TBPR_36__FULL 0x1F0C0190,0xffffffff ++#define SRM_ISP_TBPR_36__HCB_36 0x1F0C0190,0x0FFF0000 ++#define SRM_ISP_TBPR_36__VCB_36 0x1F0C0190,0x00000FFF ++ ++#define SRM_ISP_TBPR_37__ADDR 0x1F0C0194 ++#define SRM_ISP_TBPR_37__EMPTY 0x1F0C0194,0x00000000 ++#define SRM_ISP_TBPR_37__FULL 0x1F0C0194,0xffffffff ++#define SRM_ISP_TBPR_37__HCB_37 0x1F0C0194,0x0FFF0000 ++#define SRM_ISP_TBPR_37__VCB_37 0x1F0C0194,0x00000FFF ++ ++#define SRM_ISP_TBPR_38__ADDR 0x1F0C0198 ++#define SRM_ISP_TBPR_38__EMPTY 0x1F0C0198,0x00000000 ++#define SRM_ISP_TBPR_38__FULL 0x1F0C0198,0xffffffff ++#define SRM_ISP_TBPR_38__HCB_38 0x1F0C0198,0x0FFF0000 ++#define SRM_ISP_TBPR_38__VCB_38 0x1F0C0198,0x00000FFF ++ ++#define SRM_ISP_TBPR_39__ADDR 0x1F0C019C ++#define SRM_ISP_TBPR_39__EMPTY 0x1F0C019C,0x00000000 ++#define SRM_ISP_TBPR_39__FULL 0x1F0C019C,0xffffffff ++#define SRM_ISP_TBPR_39__HCB_39 0x1F0C019C,0x0FFF0000 ++#define SRM_ISP_TBPR_39__VCB_39 0x1F0C019C,0x00000FFF ++ ++#define SRM_ISP_TBPR_40__ADDR 0x1F0C01A0 ++#define SRM_ISP_TBPR_40__EMPTY 0x1F0C01A0,0x00000000 ++#define SRM_ISP_TBPR_40__FULL 0x1F0C01A0,0xffffffff ++#define SRM_ISP_TBPR_40__HCB_40 0x1F0C01A0,0x0FFF0000 ++#define SRM_ISP_TBPR_40__VCB_40 0x1F0C01A0,0x00000FFF ++ ++#define SRM_ISP_TBPR_41__ADDR 0x1F0C01A4 ++#define SRM_ISP_TBPR_41__EMPTY 0x1F0C01A4,0x00000000 ++#define SRM_ISP_TBPR_41__FULL 0x1F0C01A4,0xffffffff ++#define SRM_ISP_TBPR_41__HCB_41 0x1F0C01A4,0x0FFF0000 ++#define SRM_ISP_TBPR_41__VCB_41 0x1F0C01A4,0x00000FFF ++ ++#define SRM_ISP_TBPR_42__ADDR 0x1F0C01A8 ++#define SRM_ISP_TBPR_42__EMPTY 0x1F0C01A8,0x00000000 ++#define SRM_ISP_TBPR_42__FULL 0x1F0C01A8,0xffffffff ++#define SRM_ISP_TBPR_42__HCB_42 0x1F0C01A8,0x0FFF0000 ++#define SRM_ISP_TBPR_42__VCB_42 0x1F0C01A8,0x00000FFF ++ ++#define SRM_ISP_TBPR_43__ADDR 0x1F0C01AC ++#define SRM_ISP_TBPR_43__EMPTY 0x1F0C01AC,0x00000000 ++#define SRM_ISP_TBPR_43__FULL 0x1F0C01AC,0xffffffff ++#define SRM_ISP_TBPR_43__HCB_43 0x1F0C01AC,0x0FFF0000 ++#define SRM_ISP_TBPR_43__VCB_43 0x1F0C01AC,0x00000FFF ++ ++#define SRM_ISP_TBPR_44__ADDR 0x1F0C01B0 ++#define SRM_ISP_TBPR_44__EMPTY 0x1F0C01B0,0x00000000 ++#define SRM_ISP_TBPR_44__FULL 0x1F0C01B0,0xffffffff ++#define SRM_ISP_TBPR_44__HCB_44 0x1F0C01B0,0x0FFF0000 ++#define SRM_ISP_TBPR_44__VCB_44 0x1F0C01B0,0x00000FFF ++ ++#define SRM_ISP_TBPR_45__ADDR 0x1F0C01B4 ++#define SRM_ISP_TBPR_45__EMPTY 0x1F0C01B4,0x00000000 ++#define SRM_ISP_TBPR_45__FULL 0x1F0C01B4,0xffffffff ++#define SRM_ISP_TBPR_45__HCB_45 0x1F0C01B4,0x0FFF0000 ++#define SRM_ISP_TBPR_45__VCB_45 0x1F0C01B4,0x00000FFF ++ ++#define SRM_ISP_TBPR_46__ADDR 0x1F0C01B8 ++#define SRM_ISP_TBPR_46__EMPTY 0x1F0C01B8,0x00000000 ++#define SRM_ISP_TBPR_46__FULL 0x1F0C01B8,0xffffffff ++#define SRM_ISP_TBPR_46__HCB_46 0x1F0C01B8,0x0FFF0000 ++#define SRM_ISP_TBPR_46__VCB_46 0x1F0C01B8,0x00000FFF ++ ++#define SRM_ISP_TBPR_47__ADDR 0x1F0C01BC ++#define SRM_ISP_TBPR_47__EMPTY 0x1F0C01BC,0x00000000 ++#define SRM_ISP_TBPR_47__FULL 0x1F0C01BC,0xffffffff ++#define SRM_ISP_TBPR_47__HCB_47 0x1F0C01BC,0x0FFF0000 ++#define SRM_ISP_TBPR_47__VCB_47 0x1F0C01BC,0x00000FFF ++ ++#define SRM_ISP_TBPR_48__ADDR 0x1F0C01C0 ++#define SRM_ISP_TBPR_48__EMPTY 0x1F0C01C0,0x00000000 ++#define SRM_ISP_TBPR_48__FULL 0x1F0C01C0,0xffffffff ++#define SRM_ISP_TBPR_48__HCB_48 0x1F0C01C0,0x0FFF0000 ++#define SRM_ISP_TBPR_48__VCB_48 0x1F0C01C0,0x00000FFF ++ ++#define SRM_ISP_TBPR_49__ADDR 0x1F0C01C4 ++#define SRM_ISP_TBPR_49__EMPTY 0x1F0C01C4,0x00000000 ++#define SRM_ISP_TBPR_49__FULL 0x1F0C01C4,0xffffffff ++#define SRM_ISP_TBPR_49__HCB_49 0x1F0C01C4,0x0FFF0000 ++#define SRM_ISP_TBPR_49__VCB_49 0x1F0C01C4,0x00000FFF ++ ++#define SRM_ISP_TBPR_50__ADDR 0x1F0C01C8 ++#define SRM_ISP_TBPR_50__EMPTY 0x1F0C01C8,0x00000000 ++#define SRM_ISP_TBPR_50__FULL 0x1F0C01C8,0xffffffff ++#define SRM_ISP_TBPR_50__HCB_50 0x1F0C01C8,0x0FFF0000 ++#define SRM_ISP_TBPR_50__VCB_50 0x1F0C01C8,0x00000FFF ++ ++#define SRM_ISP_TBPR_51__ADDR 0x1F0C01CC ++#define SRM_ISP_TBPR_51__EMPTY 0x1F0C01CC,0x00000000 ++#define SRM_ISP_TBPR_51__FULL 0x1F0C01CC,0xffffffff ++#define SRM_ISP_TBPR_51__HCB_51 0x1F0C01CC,0x0FFF0000 ++#define SRM_ISP_TBPR_51__VCB_51 0x1F0C01CC,0x00000FFF ++ ++#define SRM_ISP_TBPR_52__ADDR 0x1F0C01D0 ++#define SRM_ISP_TBPR_52__EMPTY 0x1F0C01D0,0x00000000 ++#define SRM_ISP_TBPR_52__FULL 0x1F0C01D0,0xffffffff ++#define SRM_ISP_TBPR_52__HCB_52 0x1F0C01D0,0x0FFF0000 ++#define SRM_ISP_TBPR_52__VCB_52 0x1F0C01D0,0x00000FFF ++ ++#define SRM_ISP_TBPR_53__ADDR 0x1F0C01D4 ++#define SRM_ISP_TBPR_53__EMPTY 0x1F0C01D4,0x00000000 ++#define SRM_ISP_TBPR_53__FULL 0x1F0C01D4,0xffffffff ++#define SRM_ISP_TBPR_53__HCB_53 0x1F0C01D4,0x0FFF0000 ++#define SRM_ISP_TBPR_53__VCB_53 0x1F0C01D4,0x00000FFF ++ ++#define SRM_ISP_TBPR_54__ADDR 0x1F0C01D8 ++#define SRM_ISP_TBPR_54__EMPTY 0x1F0C01D8,0x00000000 ++#define SRM_ISP_TBPR_54__FULL 0x1F0C01D8,0xffffffff ++#define SRM_ISP_TBPR_54__HCB_54 0x1F0C01D8,0x0FFF0000 ++#define SRM_ISP_TBPR_54__VCB_54 0x1F0C01D8,0x00000FFF ++ ++#define SRM_ISP_TBPR_55__ADDR 0x1F0C01DC ++#define SRM_ISP_TBPR_55__EMPTY 0x1F0C01DC,0x00000000 ++#define SRM_ISP_TBPR_55__FULL 0x1F0C01DC,0xffffffff ++#define SRM_ISP_TBPR_55__HCB_55 0x1F0C01DC,0x0FFF0000 ++#define SRM_ISP_TBPR_55__VCB_55 0x1F0C01DC,0x00000FFF ++ ++#define SRM_ISP_TBPR_56__ADDR 0x1F0C01E0 ++#define SRM_ISP_TBPR_56__EMPTY 0x1F0C01E0,0x00000000 ++#define SRM_ISP_TBPR_56__FULL 0x1F0C01E0,0xffffffff ++#define SRM_ISP_TBPR_56__HCB_56 0x1F0C01E0,0x0FFF0000 ++#define SRM_ISP_TBPR_56__VCB_56 0x1F0C01E0,0x00000FFF ++ ++#define SRM_ISP_TBPR_57__ADDR 0x1F0C01E4 ++#define SRM_ISP_TBPR_57__EMPTY 0x1F0C01E4,0x00000000 ++#define SRM_ISP_TBPR_57__FULL 0x1F0C01E4,0xffffffff ++#define SRM_ISP_TBPR_57__HCB_57 0x1F0C01E4,0x0FFF0000 ++#define SRM_ISP_TBPR_57__VCB_57 0x1F0C01E4,0x00000FFF ++ ++#define SRM_ISP_TBPR_58__ADDR 0x1F0C01E8 ++#define SRM_ISP_TBPR_58__EMPTY 0x1F0C01E8,0x00000000 ++#define SRM_ISP_TBPR_58__FULL 0x1F0C01E8,0xffffffff ++#define SRM_ISP_TBPR_58__HCB_58 0x1F0C01E8,0x0FFF0000 ++#define SRM_ISP_TBPR_58__VCB_58 0x1F0C01E8,0x00000FFF ++ ++#define SRM_ISP_TBPR_59__ADDR 0x1F0C01EC ++#define SRM_ISP_TBPR_59__EMPTY 0x1F0C01EC,0x00000000 ++#define SRM_ISP_TBPR_59__FULL 0x1F0C01EC,0xffffffff ++#define SRM_ISP_TBPR_59__HCB_59 0x1F0C01EC,0x0FFF0000 ++#define SRM_ISP_TBPR_59__VCB_59 0x1F0C01EC,0x00000FFF ++ ++#define SRM_ISP_TBPR_60__ADDR 0x1F0C01F0 ++#define SRM_ISP_TBPR_60__EMPTY 0x1F0C01F0,0x00000000 ++#define SRM_ISP_TBPR_60__FULL 0x1F0C01F0,0xffffffff ++#define SRM_ISP_TBPR_60__HCB_60 0x1F0C01F0,0x0FFF0000 ++#define SRM_ISP_TBPR_60__VCB_60 0x1F0C01F0,0x00000FFF ++ ++#define SRM_ISP_TBPR_61__ADDR 0x1F0C01F4 ++#define SRM_ISP_TBPR_61__EMPTY 0x1F0C01F4,0x00000000 ++#define SRM_ISP_TBPR_61__FULL 0x1F0C01F4,0xffffffff ++#define SRM_ISP_TBPR_61__HCB_61 0x1F0C01F4,0x0FFF0000 ++#define SRM_ISP_TBPR_61__VCB_61 0x1F0C01F4,0x00000FFF ++ ++#define SRM_ISP_TBPR_62__ADDR 0x1F0C01F8 ++#define SRM_ISP_TBPR_62__EMPTY 0x1F0C01F8,0x00000000 ++#define SRM_ISP_TBPR_62__FULL 0x1F0C01F8,0xffffffff ++#define SRM_ISP_TBPR_62__HCB_62 0x1F0C01F8,0x0FFF0000 ++#define SRM_ISP_TBPR_62__VCB_62 0x1F0C01F8,0x00000FFF ++ ++#define SRM_ISP_TBPR_63__ADDR 0x1F0C01FC ++#define SRM_ISP_TBPR_63__EMPTY 0x1F0C01FC,0x00000000 ++#define SRM_ISP_TBPR_63__FULL 0x1F0C01FC,0xffffffff ++#define SRM_ISP_TBPR_63__HCB_63 0x1F0C01FC,0x0FFF0000 ++#define SRM_ISP_TBPR_63__VCB_63 0x1F0C01FC,0x00000FFF ++ ++#define LPM_MEM_DI0_GENERAL__ADDR 0x1F0402C4 ++#define LPM_MEM_DI0_GENERAL__EMPTY 0x1F0402C4,0x00000000 ++#define LPM_MEM_DI0_GENERAL__FULL 0x1F0402C4,0xffffffff ++#define LPM_MEM_DI0_GENERAL__DI0_DISP_Y_SEL 0x1F0402C4,0x70000000 ++#define LPM_MEM_DI0_GENERAL__DI0_CLOCK_STOP_MODE 0x1F0402C4,0x0F000000 ++#define LPM_MEM_DI0_GENERAL__DI0_DISP_CLOCK_INIT 0x1F0402C4,0x00800000 ++#define LPM_MEM_DI0_GENERAL__DI0_MASK_SEL 0x1F0402C4,0x00400000 ++#define LPM_MEM_DI0_GENERAL__DI0_VSYNC_EXT 0x1F0402C4,0x00200000 ++#define LPM_MEM_DI0_GENERAL__DI0_CLK_EXT 0x1F0402C4,0x00100000 ++#define LPM_MEM_DI0_GENERAL__DI0_WATCHDOG_MODE 0x1F0402C4,0x000C0000 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1F0402C4,0x00020000 ++#define LPM_MEM_DI0_GENERAL__DI0_SYNC_COUNT_SEL 0x1F0402C4,0x0000F000 ++#define LPM_MEM_DI0_GENERAL__DI0_ERR_TREATMENT 0x1F0402C4,0x00000800 ++#define LPM_MEM_DI0_GENERAL__DI0_ERM_VSYNC_SEL 0x1F0402C4,0x00000400 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS1 0x1F0402C4,0x00000200 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS0 0x1F0402C4,0x00000100 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_8 0x1F0402C4,0x00000080 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_7 0x1F0402C4,0x00000040 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_6 0x1F0402C4,0x00000020 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_5 0x1F0402C4,0x00000010 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_4 0x1F0402C4,0x00000008 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_3 0x1F0402C4,0x00000004 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_2 0x1F0402C4,0x00000002 ++#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_1 0x1F0402C4,0x00000001 ++ ++#define LPM_MEM_DI0_BS_CLKGEN0__ADDR 0x1F0402C8 ++#define LPM_MEM_DI0_BS_CLKGEN0__EMPTY 0x1F0402C8,0x00000000 ++#define LPM_MEM_DI0_BS_CLKGEN0__FULL 0x1F0402C8,0xffffffff ++#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1F0402C8,0x01FF0000 ++#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1F0402C8,0x00000FFF ++ ++#define LPM_MEM_DI0_BS_CLKGEN1__ADDR 0x1F0402CC ++#define LPM_MEM_DI0_BS_CLKGEN1__EMPTY 0x1F0402CC,0x00000000 ++#define LPM_MEM_DI0_BS_CLKGEN1__FULL 0x1F0402CC,0xffffffff ++#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1F0402CC,0x01FF0000 ++#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP 0x1F0402CC,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN0_1__ADDR 0x1F0402D0 ++#define LPM_MEM_DI0_SW_GEN0_1__EMPTY 0x1F0402D0,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_1__FULL 0x1F0402D0,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1 0x1F0402D0,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1 0x1F0402D0,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1 0x1F0402D0,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1 0x1F0402D0,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_2__ADDR 0x1F0402D4 ++#define LPM_MEM_DI0_SW_GEN0_2__EMPTY 0x1F0402D4,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_2__FULL 0x1F0402D4,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2 0x1F0402D4,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2 0x1F0402D4,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2 0x1F0402D4,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2 0x1F0402D4,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_3__ADDR 0x1F0402D8 ++#define LPM_MEM_DI0_SW_GEN0_3__EMPTY 0x1F0402D8,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_3__FULL 0x1F0402D8,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3 0x1F0402D8,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3 0x1F0402D8,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3 0x1F0402D8,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3 0x1F0402D8,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_4__ADDR 0x1F0402DC ++#define LPM_MEM_DI0_SW_GEN0_4__EMPTY 0x1F0402DC,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_4__FULL 0x1F0402DC,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4 0x1F0402DC,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4 0x1F0402DC,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4 0x1F0402DC,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4 0x1F0402DC,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_5__ADDR 0x1F0402E0 ++#define LPM_MEM_DI0_SW_GEN0_5__EMPTY 0x1F0402E0,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_5__FULL 0x1F0402E0,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5 0x1F0402E0,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5 0x1F0402E0,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5 0x1F0402E0,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5 0x1F0402E0,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_6__ADDR 0x1F0402E4 ++#define LPM_MEM_DI0_SW_GEN0_6__EMPTY 0x1F0402E4,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_6__FULL 0x1F0402E4,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6 0x1F0402E4,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6 0x1F0402E4,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6 0x1F0402E4,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6 0x1F0402E4,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_7__ADDR 0x1F0402E8 ++#define LPM_MEM_DI0_SW_GEN0_7__EMPTY 0x1F0402E8,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_7__FULL 0x1F0402E8,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7 0x1F0402E8,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7 0x1F0402E8,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7 0x1F0402E8,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7 0x1F0402E8,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_8__ADDR 0x1F0402EC ++#define LPM_MEM_DI0_SW_GEN0_8__EMPTY 0x1F0402EC,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_8__FULL 0x1F0402EC,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8 0x1F0402EC,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8 0x1F0402EC,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8 0x1F0402EC,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8 0x1F0402EC,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN0_9__ADDR 0x1F0402F0 ++#define LPM_MEM_DI0_SW_GEN0_9__EMPTY 0x1F0402F0,0x00000000 ++#define LPM_MEM_DI0_SW_GEN0_9__FULL 0x1F0402F0,0xffffffff ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9 0x1F0402F0,0x7FF80000 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9 0x1F0402F0,0x00070000 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9 0x1F0402F0,0x00007FF8 ++#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1F0402F0,0x00000007 ++ ++#define LPM_MEM_DI0_SW_GEN1_1__ADDR 0x1F0402F4 ++#define LPM_MEM_DI0_SW_GEN1_1__EMPTY 0x1F0402F4,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_1__FULL 0x1F0402F4,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1 0x1F0402F4,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1 0x1F0402F4,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1 0x1F0402F4,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1 0x1F0402F4,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1 0x1F0402F4,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1 0x1F0402F4,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_UP_1 0x1F0402F4,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_2__ADDR 0x1F0402F8 ++#define LPM_MEM_DI0_SW_GEN1_2__EMPTY 0x1F0402F8,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_2__FULL 0x1F0402F8,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2 0x1F0402F8,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2 0x1F0402F8,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2 0x1F0402F8,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2 0x1F0402F8,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2 0x1F0402F8,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2 0x1F0402F8,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_UP_2 0x1F0402F8,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_3__ADDR 0x1F0402FC ++#define LPM_MEM_DI0_SW_GEN1_3__EMPTY 0x1F0402FC,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_3__FULL 0x1F0402FC,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3 0x1F0402FC,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3 0x1F0402FC,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3 0x1F0402FC,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3 0x1F0402FC,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3 0x1F0402FC,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3 0x1F0402FC,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_UP_3 0x1F0402FC,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_4__ADDR 0x1F040300 ++#define LPM_MEM_DI0_SW_GEN1_4__EMPTY 0x1F040300,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_4__FULL 0x1F040300,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4 0x1F040300,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4 0x1F040300,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4 0x1F040300,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4 0x1F040300,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4 0x1F040300,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4 0x1F040300,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_UP_4 0x1F040300,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_5__ADDR 0x1F040304 ++#define LPM_MEM_DI0_SW_GEN1_5__EMPTY 0x1F040304,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_5__FULL 0x1F040304,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5 0x1F040304,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5 0x1F040304,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5 0x1F040304,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5 0x1F040304,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5 0x1F040304,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5 0x1F040304,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_UP_5 0x1F040304,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_6__ADDR 0x1F040308 ++#define LPM_MEM_DI0_SW_GEN1_6__EMPTY 0x1F040308,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_6__FULL 0x1F040308,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6 0x1F040308,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6 0x1F040308,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6 0x1F040308,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6 0x1F040308,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6 0x1F040308,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6 0x1F040308,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_UP_6 0x1F040308,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_7__ADDR 0x1F04030C ++#define LPM_MEM_DI0_SW_GEN1_7__EMPTY 0x1F04030C,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_7__FULL 0x1F04030C,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7 0x1F04030C,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7 0x1F04030C,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7 0x1F04030C,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7 0x1F04030C,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7 0x1F04030C,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7 0x1F04030C,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_UP_7 0x1F04030C,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_8__ADDR 0x1F040310 ++#define LPM_MEM_DI0_SW_GEN1_8__EMPTY 0x1F040310,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_8__FULL 0x1F040310,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8 0x1F040310,0x60000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8 0x1F040310,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8 0x1F040310,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8 0x1F040310,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8 0x1F040310,0x00007000 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8 0x1F040310,0x00000E00 ++#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_UP_8 0x1F040310,0x000001FF ++ ++#define LPM_MEM_DI0_SW_GEN1_9__ADDR 0x1F040314 ++#define LPM_MEM_DI0_SW_GEN1_9__EMPTY 0x1F040314,0x00000000 ++#define LPM_MEM_DI0_SW_GEN1_9__FULL 0x1F040314,0xffffffff ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9 0x1F040314,0xE0000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1F040314,0x10000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9 0x1F040314,0x0E000000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9 0x1F040314,0x01FF0000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_TAG_SEL_9 0x1F040314,0x00008000 ++#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_UP_9 0x1F040314,0x000001FF ++ ++#define LPM_MEM_DI0_SYNC_AS_GEN__ADDR 0x1F040318 ++#define LPM_MEM_DI0_SYNC_AS_GEN__EMPTY 0x1F040318,0x00000000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__FULL 0x1F040318,0xffffffff ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1F040318,0x10000000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL 0x1F040318,0x0000E000 ++#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START 0x1F040318,0x00000FFF ++ ++#define LPM_MEM_DI0_DW_GEN_0__ADDR 0x1F04031C ++#define LPM_MEM_DI0_DW_GEN_0__EMPTY 0x1F04031C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_0__FULL 0x1F04031C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0 0x1F04031C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F04031C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0 0x1F04031C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_6_0 0x1F04031C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_5_0 0x1F04031C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_4_0 0x1F04031C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_3_0 0x1F04031C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_2_0 0x1F04031C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_1_0 0x1F04031C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_0_0 0x1F04031C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_0__ADDR 0x1F04031C ++#define LPM_MEM_DI0_DW_GEN_0__EMPTY 0x1F04031C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_0__FULL 0x1F04031C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0 0x1F04031C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_START_PERIOD_0 0x1F04031C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0 0x1F04031C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F04031C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_RS_0 0x1F04031C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0 0x1F04031C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_1__ADDR 0x1F040320 ++#define LPM_MEM_DI0_DW_GEN_1__EMPTY 0x1F040320,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_1__FULL 0x1F040320,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1 0x1F040320,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F040320,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1 0x1F040320,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_6_1 0x1F040320,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_5_1 0x1F040320,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_4_1 0x1F040320,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_3_1 0x1F040320,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_2_1 0x1F040320,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_1_1 0x1F040320,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_0_1 0x1F040320,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_1__ADDR 0x1F040320 ++#define LPM_MEM_DI0_DW_GEN_1__EMPTY 0x1F040320,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_1__FULL 0x1F040320,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1 0x1F040320,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_START_PERIOD_1 0x1F040320,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1 0x1F040320,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F040320,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_RS_1 0x1F040320,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1 0x1F040320,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_2__ADDR 0x1F040324 ++#define LPM_MEM_DI0_DW_GEN_2__EMPTY 0x1F040324,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_2__FULL 0x1F040324,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2 0x1F040324,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F040324,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2 0x1F040324,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_6_2 0x1F040324,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_5_2 0x1F040324,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_4_2 0x1F040324,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_3_2 0x1F040324,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_2_2 0x1F040324,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_1_2 0x1F040324,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_0_2 0x1F040324,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_2__ADDR 0x1F040324 ++#define LPM_MEM_DI0_DW_GEN_2__EMPTY 0x1F040324,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_2__FULL 0x1F040324,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2 0x1F040324,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_START_PERIOD_2 0x1F040324,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2 0x1F040324,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F040324,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_RS_2 0x1F040324,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2 0x1F040324,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_3__ADDR 0x1F040328 ++#define LPM_MEM_DI0_DW_GEN_3__EMPTY 0x1F040328,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_3__FULL 0x1F040328,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3 0x1F040328,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F040328,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3 0x1F040328,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_6_3 0x1F040328,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_5_3 0x1F040328,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_4_3 0x1F040328,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_3_3 0x1F040328,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_2_3 0x1F040328,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_1_3 0x1F040328,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_0_3 0x1F040328,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_3__ADDR 0x1F040328 ++#define LPM_MEM_DI0_DW_GEN_3__EMPTY 0x1F040328,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_3__FULL 0x1F040328,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3 0x1F040328,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_START_PERIOD_3 0x1F040328,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3 0x1F040328,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F040328,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_RS_3 0x1F040328,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3 0x1F040328,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_4__ADDR 0x1F04032C ++#define LPM_MEM_DI0_DW_GEN_4__EMPTY 0x1F04032C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_4__FULL 0x1F04032C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4 0x1F04032C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F04032C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4 0x1F04032C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_6_4 0x1F04032C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_5_4 0x1F04032C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_4_4 0x1F04032C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_3_4 0x1F04032C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_2_4 0x1F04032C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_1_4 0x1F04032C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_0_4 0x1F04032C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_4__ADDR 0x1F04032C ++#define LPM_MEM_DI0_DW_GEN_4__EMPTY 0x1F04032C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_4__FULL 0x1F04032C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4 0x1F04032C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_START_PERIOD_4 0x1F04032C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4 0x1F04032C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F04032C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_RS_4 0x1F04032C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4 0x1F04032C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_5__ADDR 0x1F040330 ++#define LPM_MEM_DI0_DW_GEN_5__EMPTY 0x1F040330,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_5__FULL 0x1F040330,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5 0x1F040330,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F040330,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5 0x1F040330,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_6_5 0x1F040330,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_5_5 0x1F040330,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_4_5 0x1F040330,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_3_5 0x1F040330,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_2_5 0x1F040330,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_1_5 0x1F040330,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_0_5 0x1F040330,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_5__ADDR 0x1F040330 ++#define LPM_MEM_DI0_DW_GEN_5__EMPTY 0x1F040330,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_5__FULL 0x1F040330,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5 0x1F040330,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_START_PERIOD_5 0x1F040330,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5 0x1F040330,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F040330,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_RS_5 0x1F040330,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5 0x1F040330,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_6__ADDR 0x1F040334 ++#define LPM_MEM_DI0_DW_GEN_6__EMPTY 0x1F040334,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_6__FULL 0x1F040334,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6 0x1F040334,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F040334,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6 0x1F040334,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_6_6 0x1F040334,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_5_6 0x1F040334,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_4_6 0x1F040334,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_3_6 0x1F040334,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_2_6 0x1F040334,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_1_6 0x1F040334,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_0_6 0x1F040334,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_6__ADDR 0x1F040334 ++#define LPM_MEM_DI0_DW_GEN_6__EMPTY 0x1F040334,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_6__FULL 0x1F040334,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6 0x1F040334,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_START_PERIOD_6 0x1F040334,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6 0x1F040334,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F040334,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_RS_6 0x1F040334,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6 0x1F040334,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_7__ADDR 0x1F040338 ++#define LPM_MEM_DI0_DW_GEN_7__EMPTY 0x1F040338,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_7__FULL 0x1F040338,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7 0x1F040338,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F040338,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7 0x1F040338,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_6_7 0x1F040338,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_5_7 0x1F040338,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_4_7 0x1F040338,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_3_7 0x1F040338,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_2_7 0x1F040338,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_1_7 0x1F040338,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_0_7 0x1F040338,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_7__ADDR 0x1F040338 ++#define LPM_MEM_DI0_DW_GEN_7__EMPTY 0x1F040338,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_7__FULL 0x1F040338,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7 0x1F040338,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_START_PERIOD_7 0x1F040338,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7 0x1F040338,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F040338,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_RS_7 0x1F040338,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7 0x1F040338,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_8__ADDR 0x1F04033C ++#define LPM_MEM_DI0_DW_GEN_8__EMPTY 0x1F04033C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_8__FULL 0x1F04033C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8 0x1F04033C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F04033C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8 0x1F04033C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_6_8 0x1F04033C,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_5_8 0x1F04033C,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_4_8 0x1F04033C,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_3_8 0x1F04033C,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_2_8 0x1F04033C,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_1_8 0x1F04033C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_0_8 0x1F04033C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_8__ADDR 0x1F04033C ++#define LPM_MEM_DI0_DW_GEN_8__EMPTY 0x1F04033C,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_8__FULL 0x1F04033C,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8 0x1F04033C,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_START_PERIOD_8 0x1F04033C,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8 0x1F04033C,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F04033C,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_RS_8 0x1F04033C,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8 0x1F04033C,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_9__ADDR 0x1F040340 ++#define LPM_MEM_DI0_DW_GEN_9__EMPTY 0x1F040340,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_9__FULL 0x1F040340,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9 0x1F040340,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F040340,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9 0x1F040340,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_6_9 0x1F040340,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_5_9 0x1F040340,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_4_9 0x1F040340,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_3_9 0x1F040340,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_2_9 0x1F040340,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_1_9 0x1F040340,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_0_9 0x1F040340,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_9__ADDR 0x1F040340 ++#define LPM_MEM_DI0_DW_GEN_9__EMPTY 0x1F040340,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_9__FULL 0x1F040340,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9 0x1F040340,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_START_PERIOD_9 0x1F040340,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9 0x1F040340,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F040340,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_RS_9 0x1F040340,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9 0x1F040340,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_10__ADDR 0x1F040344 ++#define LPM_MEM_DI0_DW_GEN_10__EMPTY 0x1F040344,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_10__FULL 0x1F040344,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10 0x1F040344,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F040344,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10 0x1F040344,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_6_10 0x1F040344,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_5_10 0x1F040344,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_4_10 0x1F040344,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_3_10 0x1F040344,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_2_10 0x1F040344,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_1_10 0x1F040344,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_0_10 0x1F040344,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_10__ADDR 0x1F040344 ++#define LPM_MEM_DI0_DW_GEN_10__EMPTY 0x1F040344,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_10__FULL 0x1F040344,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10 0x1F040344,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_START_PERIOD_10 0x1F040344,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10 0x1F040344,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040344,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_RS_10 0x1F040344,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10 0x1F040344,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_11__ADDR 0x1F040348 ++#define LPM_MEM_DI0_DW_GEN_11__EMPTY 0x1F040348,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_11__FULL 0x1F040348,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11 0x1F040348,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F040348,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11 0x1F040348,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_6_11 0x1F040348,0x00003000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_5_11 0x1F040348,0x00000C00 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_4_11 0x1F040348,0x00000300 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_3_11 0x1F040348,0x000000C0 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_2_11 0x1F040348,0x00000030 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_1_11 0x1F040348,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_0_11 0x1F040348,0x00000003 ++ ++#define LPM_MEM_DI0_DW_GEN_11__ADDR 0x1F040348 ++#define LPM_MEM_DI0_DW_GEN_11__EMPTY 0x1F040348,0x00000000 ++#define LPM_MEM_DI0_DW_GEN_11__FULL 0x1F040348,0xffffffff ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11 0x1F040348,0xFF000000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_START_PERIOD_11 0x1F040348,0x00FF0000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11 0x1F040348,0x0000C000 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040348,0x000001F0 ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_RS_11 0x1F040348,0x0000000C ++#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11 0x1F040348,0x00000003 ++ ++#define LPM_MEM_DI0_DW_SET0_0__ADDR 0x1F04034C ++#define LPM_MEM_DI0_DW_SET0_0__EMPTY 0x1F04034C,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_0__FULL 0x1F04034C,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0 0x1F04034C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0 0x1F04034C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_1__ADDR 0x1F040350 ++#define LPM_MEM_DI0_DW_SET0_1__EMPTY 0x1F040350,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_1__FULL 0x1F040350,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1 0x1F040350,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1 0x1F040350,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_2__ADDR 0x1F040354 ++#define LPM_MEM_DI0_DW_SET0_2__EMPTY 0x1F040354,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_2__FULL 0x1F040354,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2 0x1F040354,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2 0x1F040354,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_3__ADDR 0x1F040358 ++#define LPM_MEM_DI0_DW_SET0_3__EMPTY 0x1F040358,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_3__FULL 0x1F040358,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3 0x1F040358,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3 0x1F040358,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_4__ADDR 0x1F04035C ++#define LPM_MEM_DI0_DW_SET0_4__EMPTY 0x1F04035C,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_4__FULL 0x1F04035C,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4 0x1F04035C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4 0x1F04035C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_5__ADDR 0x1F040360 ++#define LPM_MEM_DI0_DW_SET0_5__EMPTY 0x1F040360,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_5__FULL 0x1F040360,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5 0x1F040360,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5 0x1F040360,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_6__ADDR 0x1F040364 ++#define LPM_MEM_DI0_DW_SET0_6__EMPTY 0x1F040364,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_6__FULL 0x1F040364,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6 0x1F040364,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6 0x1F040364,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_7__ADDR 0x1F040368 ++#define LPM_MEM_DI0_DW_SET0_7__EMPTY 0x1F040368,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_7__FULL 0x1F040368,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7 0x1F040368,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7 0x1F040368,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_8__ADDR 0x1F04036C ++#define LPM_MEM_DI0_DW_SET0_8__EMPTY 0x1F04036C,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_8__FULL 0x1F04036C,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8 0x1F04036C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8 0x1F04036C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_9__ADDR 0x1F040370 ++#define LPM_MEM_DI0_DW_SET0_9__EMPTY 0x1F040370,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_9__FULL 0x1F040370,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9 0x1F040370,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9 0x1F040370,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_10__ADDR 0x1F040374 ++#define LPM_MEM_DI0_DW_SET0_10__EMPTY 0x1F040374,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_10__FULL 0x1F040374,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10 0x1F040374,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10 0x1F040374,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET0_11__ADDR 0x1F040378 ++#define LPM_MEM_DI0_DW_SET0_11__EMPTY 0x1F040378,0x00000000 ++#define LPM_MEM_DI0_DW_SET0_11__FULL 0x1F040378,0xffffffff ++#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11 0x1F040378,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11 0x1F040378,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_0__ADDR 0x1F04037C ++#define LPM_MEM_DI0_DW_SET1_0__EMPTY 0x1F04037C,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_0__FULL 0x1F04037C,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0 0x1F04037C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0 0x1F04037C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_1__ADDR 0x1F040380 ++#define LPM_MEM_DI0_DW_SET1_1__EMPTY 0x1F040380,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_1__FULL 0x1F040380,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1 0x1F040380,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1 0x1F040380,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_2__ADDR 0x1F040384 ++#define LPM_MEM_DI0_DW_SET1_2__EMPTY 0x1F040384,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_2__FULL 0x1F040384,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2 0x1F040384,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2 0x1F040384,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_3__ADDR 0x1F040388 ++#define LPM_MEM_DI0_DW_SET1_3__EMPTY 0x1F040388,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_3__FULL 0x1F040388,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3 0x1F040388,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3 0x1F040388,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_4__ADDR 0x1F04038C ++#define LPM_MEM_DI0_DW_SET1_4__EMPTY 0x1F04038C,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_4__FULL 0x1F04038C,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4 0x1F04038C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4 0x1F04038C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_5__ADDR 0x1F040390 ++#define LPM_MEM_DI0_DW_SET1_5__EMPTY 0x1F040390,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_5__FULL 0x1F040390,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5 0x1F040390,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5 0x1F040390,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_6__ADDR 0x1F040394 ++#define LPM_MEM_DI0_DW_SET1_6__EMPTY 0x1F040394,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_6__FULL 0x1F040394,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6 0x1F040394,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6 0x1F040394,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_7__ADDR 0x1F040398 ++#define LPM_MEM_DI0_DW_SET1_7__EMPTY 0x1F040398,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_7__FULL 0x1F040398,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7 0x1F040398,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7 0x1F040398,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_8__ADDR 0x1F04039C ++#define LPM_MEM_DI0_DW_SET1_8__EMPTY 0x1F04039C,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_8__FULL 0x1F04039C,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8 0x1F04039C,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8 0x1F04039C,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_9__ADDR 0x1F0403A0 ++#define LPM_MEM_DI0_DW_SET1_9__EMPTY 0x1F0403A0,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_9__FULL 0x1F0403A0,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9 0x1F0403A0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9 0x1F0403A0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_10__ADDR 0x1F0403A4 ++#define LPM_MEM_DI0_DW_SET1_10__EMPTY 0x1F0403A4,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_10__FULL 0x1F0403A4,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10 0x1F0403A4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10 0x1F0403A4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET1_11__ADDR 0x1F0403A8 ++#define LPM_MEM_DI0_DW_SET1_11__EMPTY 0x1F0403A8,0x00000000 ++#define LPM_MEM_DI0_DW_SET1_11__FULL 0x1F0403A8,0xffffffff ++#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11 0x1F0403A8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11 0x1F0403A8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_0__ADDR 0x1F0403AC ++#define LPM_MEM_DI0_DW_SET2_0__EMPTY 0x1F0403AC,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_0__FULL 0x1F0403AC,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0 0x1F0403AC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0 0x1F0403AC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_1__ADDR 0x1F0403B0 ++#define LPM_MEM_DI0_DW_SET2_1__EMPTY 0x1F0403B0,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_1__FULL 0x1F0403B0,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1 0x1F0403B0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1 0x1F0403B0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_2__ADDR 0x1F0403B4 ++#define LPM_MEM_DI0_DW_SET2_2__EMPTY 0x1F0403B4,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_2__FULL 0x1F0403B4,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2 0x1F0403B4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2 0x1F0403B4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_3__ADDR 0x1F0403B8 ++#define LPM_MEM_DI0_DW_SET2_3__EMPTY 0x1F0403B8,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_3__FULL 0x1F0403B8,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3 0x1F0403B8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3 0x1F0403B8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_4__ADDR 0x1F0403BC ++#define LPM_MEM_DI0_DW_SET2_4__EMPTY 0x1F0403BC,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_4__FULL 0x1F0403BC,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4 0x1F0403BC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4 0x1F0403BC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_5__ADDR 0x1F0403C0 ++#define LPM_MEM_DI0_DW_SET2_5__EMPTY 0x1F0403C0,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_5__FULL 0x1F0403C0,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5 0x1F0403C0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5 0x1F0403C0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_6__ADDR 0x1F0403C4 ++#define LPM_MEM_DI0_DW_SET2_6__EMPTY 0x1F0403C4,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_6__FULL 0x1F0403C4,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6 0x1F0403C4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6 0x1F0403C4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_7__ADDR 0x1F0403C8 ++#define LPM_MEM_DI0_DW_SET2_7__EMPTY 0x1F0403C8,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_7__FULL 0x1F0403C8,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7 0x1F0403C8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7 0x1F0403C8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_8__ADDR 0x1F0403CC ++#define LPM_MEM_DI0_DW_SET2_8__EMPTY 0x1F0403CC,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_8__FULL 0x1F0403CC,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8 0x1F0403CC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8 0x1F0403CC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_9__ADDR 0x1F0403D0 ++#define LPM_MEM_DI0_DW_SET2_9__EMPTY 0x1F0403D0,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_9__FULL 0x1F0403D0,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9 0x1F0403D0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9 0x1F0403D0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_10__ADDR 0x1F0403D4 ++#define LPM_MEM_DI0_DW_SET2_10__EMPTY 0x1F0403D4,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_10__FULL 0x1F0403D4,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10 0x1F0403D4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10 0x1F0403D4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET2_11__ADDR 0x1F0403D8 ++#define LPM_MEM_DI0_DW_SET2_11__EMPTY 0x1F0403D8,0x00000000 ++#define LPM_MEM_DI0_DW_SET2_11__FULL 0x1F0403D8,0xffffffff ++#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11 0x1F0403D8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11 0x1F0403D8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_0__ADDR 0x1F0403DC ++#define LPM_MEM_DI0_DW_SET3_0__EMPTY 0x1F0403DC,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_0__FULL 0x1F0403DC,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0 0x1F0403DC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0 0x1F0403DC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_1__ADDR 0x1F0403E0 ++#define LPM_MEM_DI0_DW_SET3_1__EMPTY 0x1F0403E0,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_1__FULL 0x1F0403E0,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1 0x1F0403E0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1 0x1F0403E0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_2__ADDR 0x1F0403E4 ++#define LPM_MEM_DI0_DW_SET3_2__EMPTY 0x1F0403E4,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_2__FULL 0x1F0403E4,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2 0x1F0403E4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2 0x1F0403E4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_3__ADDR 0x1F0403E8 ++#define LPM_MEM_DI0_DW_SET3_3__EMPTY 0x1F0403E8,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_3__FULL 0x1F0403E8,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3 0x1F0403E8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3 0x1F0403E8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_4__ADDR 0x1F0403EC ++#define LPM_MEM_DI0_DW_SET3_4__EMPTY 0x1F0403EC,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_4__FULL 0x1F0403EC,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4 0x1F0403EC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4 0x1F0403EC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_5__ADDR 0x1F0403F0 ++#define LPM_MEM_DI0_DW_SET3_5__EMPTY 0x1F0403F0,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_5__FULL 0x1F0403F0,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5 0x1F0403F0,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5 0x1F0403F0,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_6__ADDR 0x1F0403F4 ++#define LPM_MEM_DI0_DW_SET3_6__EMPTY 0x1F0403F4,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_6__FULL 0x1F0403F4,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6 0x1F0403F4,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6 0x1F0403F4,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_7__ADDR 0x1F0403F8 ++#define LPM_MEM_DI0_DW_SET3_7__EMPTY 0x1F0403F8,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_7__FULL 0x1F0403F8,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7 0x1F0403F8,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7 0x1F0403F8,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_8__ADDR 0x1F0403FC ++#define LPM_MEM_DI0_DW_SET3_8__EMPTY 0x1F0403FC,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_8__FULL 0x1F0403FC,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8 0x1F0403FC,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8 0x1F0403FC,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_9__ADDR 0x1F040400 ++#define LPM_MEM_DI0_DW_SET3_9__EMPTY 0x1F040400,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_9__FULL 0x1F040400,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9 0x1F040400,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9 0x1F040400,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_10__ADDR 0x1F040404 ++#define LPM_MEM_DI0_DW_SET3_10__EMPTY 0x1F040404,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_10__FULL 0x1F040404,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10 0x1F040404,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10 0x1F040404,0x000001FF ++ ++#define LPM_MEM_DI0_DW_SET3_11__ADDR 0x1F040408 ++#define LPM_MEM_DI0_DW_SET3_11__EMPTY 0x1F040408,0x00000000 ++#define LPM_MEM_DI0_DW_SET3_11__FULL 0x1F040408,0xffffffff ++#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11 0x1F040408,0x01FF0000 ++#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11 0x1F040408,0x000001FF ++ ++#define LPM_MEM_DI0_STP_REP_1__ADDR 0x1F04040C ++#define LPM_MEM_DI0_STP_REP_1__EMPTY 0x1F04040C,0x00000000 ++#define LPM_MEM_DI0_STP_REP_1__FULL 0x1F04040C,0xffffffff ++#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_2 0x1F04040C,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_1 0x1F04040C,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_2__ADDR 0x1F040410 ++#define LPM_MEM_DI0_STP_REP_2__EMPTY 0x1F040410,0x00000000 ++#define LPM_MEM_DI0_STP_REP_2__FULL 0x1F040410,0xffffffff ++#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_4 0x1F040410,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_3 0x1F040410,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_3__ADDR 0x1F040414 ++#define LPM_MEM_DI0_STP_REP_3__EMPTY 0x1F040414,0x00000000 ++#define LPM_MEM_DI0_STP_REP_3__FULL 0x1F040414,0xffffffff ++#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_6 0x1F040414,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_5 0x1F040414,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_4__ADDR 0x1F040418 ++#define LPM_MEM_DI0_STP_REP_4__EMPTY 0x1F040418,0x00000000 ++#define LPM_MEM_DI0_STP_REP_4__FULL 0x1F040418,0xffffffff ++#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_8 0x1F040418,0x0FFF0000 ++#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_7 0x1F040418,0x00000FFF ++ ++#define LPM_MEM_DI0_STP_REP_9__ADDR 0x1F04041C ++#define LPM_MEM_DI0_STP_REP_9__EMPTY 0x1F04041C,0x00000000 ++#define LPM_MEM_DI0_STP_REP_9__FULL 0x1F04041C,0xffffffff ++#define LPM_MEM_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1F04041C,0x00000FFF ++ ++#define LPM_MEM_DI0_SER_CONF__ADDR 0x1F040420 ++#define LPM_MEM_DI0_SER_CONF__EMPTY 0x1F040420,0x00000000 ++#define LPM_MEM_DI0_SER_CONF__FULL 0x1F040420,0xffffffff ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1F040420,0xF0000000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1F040420,0x0F000000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1F040420,0x00F00000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1F040420,0x000F0000 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LATCH 0x1F040420,0x0000FF00 ++#define LPM_MEM_DI0_SER_CONF__DI0_LLA_SER_ACCESS 0x1F040420,0x00000020 ++#define LPM_MEM_DI0_SER_CONF__DI0_SER_CLK_POLARITY 0x1F040420,0x00000010 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY 0x1F040420,0x00000008 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY 0x1F040420,0x00000004 ++#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY 0x1F040420,0x00000002 ++#define LPM_MEM_DI0_SER_CONF__DI0_WAIT4SERIAL 0x1F040420,0x00000001 ++ ++#define LPM_MEM_DI0_SSC__ADDR 0x1F040424 ++#define LPM_MEM_DI0_SSC__EMPTY 0x1F040424,0x00000000 ++#define LPM_MEM_DI0_SSC__FULL 0x1F040424,0xffffffff ++#define LPM_MEM_DI0_SSC__DI0_PIN17_ERM 0x1F040424,0x00800000 ++#define LPM_MEM_DI0_SSC__DI0_PIN16_ERM 0x1F040424,0x00400000 ++#define LPM_MEM_DI0_SSC__DI0_PIN15_ERM 0x1F040424,0x00200000 ++#define LPM_MEM_DI0_SSC__DI0_PIN14_ERM 0x1F040424,0x00100000 ++#define LPM_MEM_DI0_SSC__DI0_PIN13_ERM 0x1F040424,0x00080000 ++#define LPM_MEM_DI0_SSC__DI0_PIN12_ERM 0x1F040424,0x00040000 ++#define LPM_MEM_DI0_SSC__DI0_PIN11_ERM 0x1F040424,0x00020000 ++#define LPM_MEM_DI0_SSC__DI0_CS_ERM 0x1F040424,0x00010000 ++#define LPM_MEM_DI0_SSC__DI0_WAIT_ON 0x1F040424,0x00000020 ++#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1F040424,0x00000008 ++#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_PNTR 0x1F040424,0x00000007 ++ ++#define LPM_MEM_DI0_POL__ADDR 0x1F040428 ++#define LPM_MEM_DI0_POL__EMPTY 0x1F040428,0x00000000 ++#define LPM_MEM_DI0_POL__FULL 0x1F040428,0xffffffff ++#define LPM_MEM_DI0_POL__DI0_WAIT_POLARITY 0x1F040428,0x04000000 ++#define LPM_MEM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1F040428,0x02000000 ++#define LPM_MEM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1F040428,0x01000000 ++#define LPM_MEM_DI0_POL__DI0_CS1_DATA_POLARITY 0x1F040428,0x00800000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_17 0x1F040428,0x00400000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_16 0x1F040428,0x00200000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_15 0x1F040428,0x00100000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_14 0x1F040428,0x00080000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_13 0x1F040428,0x00040000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_12 0x1F040428,0x00020000 ++#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_11 0x1F040428,0x00010000 ++#define LPM_MEM_DI0_POL__DI0_CS0_DATA_POLARITY 0x1F040428,0x00008000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_17 0x1F040428,0x00004000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_16 0x1F040428,0x00002000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_15 0x1F040428,0x00001000 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_14 0x1F040428,0x00000800 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_13 0x1F040428,0x00000400 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_12 0x1F040428,0x00000200 ++#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_11 0x1F040428,0x00000100 ++#define LPM_MEM_DI0_POL__DI0_DRDY_DATA_POLARITY 0x1F040428,0x00000080 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_17 0x1F040428,0x00000040 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_16 0x1F040428,0x00000020 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_15 0x1F040428,0x00000010 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_14 0x1F040428,0x00000008 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_13 0x1F040428,0x00000004 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_12 0x1F040428,0x00000002 ++#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_11 0x1F040428,0x00000001 ++ ++#define LPM_MEM_DI0_AW0__ADDR 0x1F04042C ++#define LPM_MEM_DI0_AW0__EMPTY 0x1F04042C,0x00000000 ++#define LPM_MEM_DI0_AW0__FULL 0x1F04042C,0xffffffff ++#define LPM_MEM_DI0_AW0__DI0_AW_TRIG_SEL 0x1F04042C,0xF0000000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HEND 0x1F04042C,0x0FFF0000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1F04042C,0x0000F000 ++#define LPM_MEM_DI0_AW0__DI0_AW_HSTART 0x1F04042C,0x00000FFF ++ ++#define LPM_MEM_DI0_AW1__ADDR 0x1F040430 ++#define LPM_MEM_DI0_AW1__EMPTY 0x1F040430,0x00000000 ++#define LPM_MEM_DI0_AW1__FULL 0x1F040430,0xffffffff ++#define LPM_MEM_DI0_AW1__DI0_AW_VEND 0x1F040430,0x0FFF0000 ++#define LPM_MEM_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1F040430,0x0000F000 ++#define LPM_MEM_DI0_AW1__DI0_AW_VSTART 0x1F040430,0x00000FFF ++ ++#define LPM_MEM_DI0_SCR_CONF__ADDR 0x1F040434 ++#define LPM_MEM_DI0_SCR_CONF__EMPTY 0x1F040434,0x00000000 ++#define LPM_MEM_DI0_SCR_CONF__FULL 0x1F040434,0xffffffff ++#define LPM_MEM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1F040434,0x00000FFF ++ ++#define LPM_MEM_DI1_GENERAL__ADDR 0x1F040438 ++#define LPM_MEM_DI1_GENERAL__EMPTY 0x1F040438,0x00000000 ++#define LPM_MEM_DI1_GENERAL__FULL 0x1F040438,0xffffffff ++#define LPM_MEM_DI1_GENERAL__DI1_DISP_Y_SEL 0x1F040438,0x70000000 ++#define LPM_MEM_DI1_GENERAL__DI1_CLOCK_STOP_MODE 0x1F040438,0x0F000000 ++#define LPM_MEM_DI1_GENERAL__DI1_DISP_CLOCK_INIT 0x1F040438,0x00800000 ++#define LPM_MEM_DI1_GENERAL__DI1_MASK_SEL 0x1F040438,0x00400000 ++#define LPM_MEM_DI1_GENERAL__DI1_VSYNC_EXT 0x1F040438,0x00200000 ++#define LPM_MEM_DI1_GENERAL__DI1_CLK_EXT 0x1F040438,0x00100000 ++#define LPM_MEM_DI1_GENERAL__DI1_WATCHDOG_MODE 0x1F040438,0x000C0000 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1F040438,0x00020000 ++#define LPM_MEM_DI1_GENERAL__DI1_SYNC_COUNT_SEL 0x1F040438,0x0000F000 ++#define LPM_MEM_DI1_GENERAL__DI1_ERR_TREATMENT 0x1F040438,0x00000800 ++#define LPM_MEM_DI1_GENERAL__DI1_ERM_VSYNC_SEL 0x1F040438,0x00000400 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS1 0x1F040438,0x00000200 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS0 0x1F040438,0x00000100 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_8 0x1F040438,0x00000080 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_7 0x1F040438,0x00000040 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_6 0x1F040438,0x00000020 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_5 0x1F040438,0x00000010 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_4 0x1F040438,0x00000008 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_3 0x1F040438,0x00000004 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_2 0x1F040438,0x00000002 ++#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_1 0x1F040438,0x00000001 ++ ++#define LPM_MEM_DI1_BS_CLKGEN0__ADDR 0x1F04043C ++#define LPM_MEM_DI1_BS_CLKGEN0__EMPTY 0x1F04043C,0x00000000 ++#define LPM_MEM_DI1_BS_CLKGEN0__FULL 0x1F04043C,0xffffffff ++#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1F04043C,0x01FF0000 ++#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1F04043C,0x00000FFF ++ ++#define LPM_MEM_DI1_BS_CLKGEN1__ADDR 0x1F040440 ++#define LPM_MEM_DI1_BS_CLKGEN1__EMPTY 0x1F040440,0x00000000 ++#define LPM_MEM_DI1_BS_CLKGEN1__FULL 0x1F040440,0xffffffff ++#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1F040440,0x01FF0000 ++#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP 0x1F040440,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN0_1__ADDR 0x1F040444 ++#define LPM_MEM_DI1_SW_GEN0_1__EMPTY 0x1F040444,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_1__FULL 0x1F040444,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1 0x1F040444,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1 0x1F040444,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1 0x1F040444,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1 0x1F040444,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_2__ADDR 0x1F040448 ++#define LPM_MEM_DI1_SW_GEN0_2__EMPTY 0x1F040448,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_2__FULL 0x1F040448,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2 0x1F040448,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2 0x1F040448,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2 0x1F040448,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2 0x1F040448,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_3__ADDR 0x1F04044C ++#define LPM_MEM_DI1_SW_GEN0_3__EMPTY 0x1F04044C,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_3__FULL 0x1F04044C,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3 0x1F04044C,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3 0x1F04044C,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3 0x1F04044C,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3 0x1F04044C,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_4__ADDR 0x1F040450 ++#define LPM_MEM_DI1_SW_GEN0_4__EMPTY 0x1F040450,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_4__FULL 0x1F040450,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4 0x1F040450,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4 0x1F040450,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4 0x1F040450,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4 0x1F040450,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_5__ADDR 0x1F040454 ++#define LPM_MEM_DI1_SW_GEN0_5__EMPTY 0x1F040454,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_5__FULL 0x1F040454,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5 0x1F040454,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5 0x1F040454,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5 0x1F040454,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5 0x1F040454,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_6__ADDR 0x1F040458 ++#define LPM_MEM_DI1_SW_GEN0_6__EMPTY 0x1F040458,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_6__FULL 0x1F040458,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6 0x1F040458,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6 0x1F040458,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6 0x1F040458,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6 0x1F040458,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_7__ADDR 0x1F04045C ++#define LPM_MEM_DI1_SW_GEN0_7__EMPTY 0x1F04045C,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_7__FULL 0x1F04045C,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7 0x1F04045C,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7 0x1F04045C,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7 0x1F04045C,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7 0x1F04045C,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_8__ADDR 0x1F040460 ++#define LPM_MEM_DI1_SW_GEN0_8__EMPTY 0x1F040460,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_8__FULL 0x1F040460,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8 0x1F040460,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8 0x1F040460,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8 0x1F040460,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8 0x1F040460,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN0_9__ADDR 0x1F040464 ++#define LPM_MEM_DI1_SW_GEN0_9__EMPTY 0x1F040464,0x00000000 ++#define LPM_MEM_DI1_SW_GEN0_9__FULL 0x1F040464,0xffffffff ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9 0x1F040464,0x7FF80000 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9 0x1F040464,0x00070000 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9 0x1F040464,0x00007FF8 ++#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1F040464,0x00000007 ++ ++#define LPM_MEM_DI1_SW_GEN1_1__ADDR 0x1F040468 ++#define LPM_MEM_DI1_SW_GEN1_1__EMPTY 0x1F040468,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_1__FULL 0x1F040468,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1 0x1F040468,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1 0x1F040468,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1 0x1F040468,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1 0x1F040468,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1 0x1F040468,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1 0x1F040468,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_UP_1 0x1F040468,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_2__ADDR 0x1F04046C ++#define LPM_MEM_DI1_SW_GEN1_2__EMPTY 0x1F04046C,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_2__FULL 0x1F04046C,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2 0x1F04046C,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2 0x1F04046C,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2 0x1F04046C,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2 0x1F04046C,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2 0x1F04046C,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2 0x1F04046C,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_UP_2 0x1F04046C,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_3__ADDR 0x1F040470 ++#define LPM_MEM_DI1_SW_GEN1_3__EMPTY 0x1F040470,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_3__FULL 0x1F040470,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3 0x1F040470,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3 0x1F040470,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3 0x1F040470,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3 0x1F040470,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3 0x1F040470,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3 0x1F040470,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_UP_3 0x1F040470,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_4__ADDR 0x1F040474 ++#define LPM_MEM_DI1_SW_GEN1_4__EMPTY 0x1F040474,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_4__FULL 0x1F040474,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4 0x1F040474,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4 0x1F040474,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4 0x1F040474,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4 0x1F040474,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4 0x1F040474,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4 0x1F040474,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_UP_4 0x1F040474,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_5__ADDR 0x1F040478 ++#define LPM_MEM_DI1_SW_GEN1_5__EMPTY 0x1F040478,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_5__FULL 0x1F040478,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5 0x1F040478,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5 0x1F040478,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5 0x1F040478,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5 0x1F040478,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5 0x1F040478,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5 0x1F040478,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_UP_5 0x1F040478,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_6__ADDR 0x1F04047C ++#define LPM_MEM_DI1_SW_GEN1_6__EMPTY 0x1F04047C,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_6__FULL 0x1F04047C,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6 0x1F04047C,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6 0x1F04047C,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6 0x1F04047C,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6 0x1F04047C,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6 0x1F04047C,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6 0x1F04047C,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_UP_6 0x1F04047C,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_7__ADDR 0x1F040480 ++#define LPM_MEM_DI1_SW_GEN1_7__EMPTY 0x1F040480,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_7__FULL 0x1F040480,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7 0x1F040480,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7 0x1F040480,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7 0x1F040480,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7 0x1F040480,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7 0x1F040480,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7 0x1F040480,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_UP_7 0x1F040480,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_8__ADDR 0x1F040484 ++#define LPM_MEM_DI1_SW_GEN1_8__EMPTY 0x1F040484,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_8__FULL 0x1F040484,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8 0x1F040484,0x60000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8 0x1F040484,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8 0x1F040484,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8 0x1F040484,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8 0x1F040484,0x00007000 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8 0x1F040484,0x00000E00 ++#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_UP_8 0x1F040484,0x000001FF ++ ++#define LPM_MEM_DI1_SW_GEN1_9__ADDR 0x1F040488 ++#define LPM_MEM_DI1_SW_GEN1_9__EMPTY 0x1F040488,0x00000000 ++#define LPM_MEM_DI1_SW_GEN1_9__FULL 0x1F040488,0xffffffff ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9 0x1F040488,0xE0000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1F040488,0x10000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9 0x1F040488,0x0E000000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9 0x1F040488,0x01FF0000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_TAG_SEL_9 0x1F040488,0x00008000 ++#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_UP_9 0x1F040488,0x000001FF ++ ++#define LPM_MEM_DI1_SYNC_AS_GEN__ADDR 0x1F04048C ++#define LPM_MEM_DI1_SYNC_AS_GEN__EMPTY 0x1F04048C,0x00000000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__FULL 0x1F04048C,0xffffffff ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1F04048C,0x10000000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL 0x1F04048C,0x0000E000 ++#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START 0x1F04048C,0x00000FFF ++ ++#define LPM_MEM_DI1_DW_GEN_0__ADDR 0x1F040490 ++#define LPM_MEM_DI1_DW_GEN_0__EMPTY 0x1F040490,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_0__FULL 0x1F040490,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0 0x1F040490,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040490,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0 0x1F040490,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_6_0 0x1F040490,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_5_0 0x1F040490,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_4_0 0x1F040490,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_3_0 0x1F040490,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_2_0 0x1F040490,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_1_0 0x1F040490,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_0_0 0x1F040490,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_0__ADDR 0x1F040490 ++#define LPM_MEM_DI1_DW_GEN_0__EMPTY 0x1F040490,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_0__FULL 0x1F040490,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0 0x1F040490,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_START_PERIOD_0 0x1F040490,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0 0x1F040490,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040490,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_RS_0 0x1F040490,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0 0x1F040490,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_1__ADDR 0x1F040494 ++#define LPM_MEM_DI1_DW_GEN_1__EMPTY 0x1F040494,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_1__FULL 0x1F040494,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1 0x1F040494,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040494,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1 0x1F040494,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_6_1 0x1F040494,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_5_1 0x1F040494,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_4_1 0x1F040494,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_3_1 0x1F040494,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_2_1 0x1F040494,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_1_1 0x1F040494,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_0_1 0x1F040494,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_1__ADDR 0x1F040494 ++#define LPM_MEM_DI1_DW_GEN_1__EMPTY 0x1F040494,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_1__FULL 0x1F040494,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1 0x1F040494,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_START_PERIOD_1 0x1F040494,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1 0x1F040494,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040494,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_RS_1 0x1F040494,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1 0x1F040494,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_2__ADDR 0x1F040498 ++#define LPM_MEM_DI1_DW_GEN_2__EMPTY 0x1F040498,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_2__FULL 0x1F040498,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2 0x1F040498,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F040498,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2 0x1F040498,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_6_2 0x1F040498,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_5_2 0x1F040498,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_4_2 0x1F040498,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_3_2 0x1F040498,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_2_2 0x1F040498,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_1_2 0x1F040498,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_0_2 0x1F040498,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_2__ADDR 0x1F040498 ++#define LPM_MEM_DI1_DW_GEN_2__EMPTY 0x1F040498,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_2__FULL 0x1F040498,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2 0x1F040498,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_START_PERIOD_2 0x1F040498,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2 0x1F040498,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F040498,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_RS_2 0x1F040498,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2 0x1F040498,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_3__ADDR 0x1F04049C ++#define LPM_MEM_DI1_DW_GEN_3__EMPTY 0x1F04049C,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_3__FULL 0x1F04049C,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3 0x1F04049C,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F04049C,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3 0x1F04049C,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_6_3 0x1F04049C,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_5_3 0x1F04049C,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_4_3 0x1F04049C,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_3_3 0x1F04049C,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_2_3 0x1F04049C,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_1_3 0x1F04049C,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_0_3 0x1F04049C,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_3__ADDR 0x1F04049C ++#define LPM_MEM_DI1_DW_GEN_3__EMPTY 0x1F04049C,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_3__FULL 0x1F04049C,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3 0x1F04049C,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_START_PERIOD_3 0x1F04049C,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3 0x1F04049C,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F04049C,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_RS_3 0x1F04049C,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3 0x1F04049C,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_4__ADDR 0x1F0404A0 ++#define LPM_MEM_DI1_DW_GEN_4__EMPTY 0x1F0404A0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_4__FULL 0x1F0404A0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4 0x1F0404A0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F0404A0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4 0x1F0404A0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_6_4 0x1F0404A0,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_5_4 0x1F0404A0,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_4_4 0x1F0404A0,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_3_4 0x1F0404A0,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_2_4 0x1F0404A0,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_1_4 0x1F0404A0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_0_4 0x1F0404A0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_4__ADDR 0x1F0404A0 ++#define LPM_MEM_DI1_DW_GEN_4__EMPTY 0x1F0404A0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_4__FULL 0x1F0404A0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4 0x1F0404A0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_START_PERIOD_4 0x1F0404A0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4 0x1F0404A0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F0404A0,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_RS_4 0x1F0404A0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4 0x1F0404A0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_5__ADDR 0x1F0404A4 ++#define LPM_MEM_DI1_DW_GEN_5__EMPTY 0x1F0404A4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_5__FULL 0x1F0404A4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5 0x1F0404A4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F0404A4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5 0x1F0404A4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_6_5 0x1F0404A4,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_5_5 0x1F0404A4,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_4_5 0x1F0404A4,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_3_5 0x1F0404A4,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_2_5 0x1F0404A4,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_1_5 0x1F0404A4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_0_5 0x1F0404A4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_5__ADDR 0x1F0404A4 ++#define LPM_MEM_DI1_DW_GEN_5__EMPTY 0x1F0404A4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_5__FULL 0x1F0404A4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5 0x1F0404A4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_START_PERIOD_5 0x1F0404A4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5 0x1F0404A4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F0404A4,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_RS_5 0x1F0404A4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5 0x1F0404A4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_6__ADDR 0x1F0404A8 ++#define LPM_MEM_DI1_DW_GEN_6__EMPTY 0x1F0404A8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_6__FULL 0x1F0404A8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6 0x1F0404A8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F0404A8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6 0x1F0404A8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_6_6 0x1F0404A8,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_5_6 0x1F0404A8,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_4_6 0x1F0404A8,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_3_6 0x1F0404A8,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_2_6 0x1F0404A8,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_1_6 0x1F0404A8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_0_6 0x1F0404A8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_6__ADDR 0x1F0404A8 ++#define LPM_MEM_DI1_DW_GEN_6__EMPTY 0x1F0404A8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_6__FULL 0x1F0404A8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6 0x1F0404A8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_START_PERIOD_6 0x1F0404A8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6 0x1F0404A8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F0404A8,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_RS_6 0x1F0404A8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6 0x1F0404A8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_7__ADDR 0x1F0404AC ++#define LPM_MEM_DI1_DW_GEN_7__EMPTY 0x1F0404AC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_7__FULL 0x1F0404AC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7 0x1F0404AC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F0404AC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7 0x1F0404AC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_6_7 0x1F0404AC,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_5_7 0x1F0404AC,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_4_7 0x1F0404AC,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_3_7 0x1F0404AC,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_2_7 0x1F0404AC,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_1_7 0x1F0404AC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_0_7 0x1F0404AC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_7__ADDR 0x1F0404AC ++#define LPM_MEM_DI1_DW_GEN_7__EMPTY 0x1F0404AC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_7__FULL 0x1F0404AC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7 0x1F0404AC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_START_PERIOD_7 0x1F0404AC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7 0x1F0404AC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F0404AC,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_RS_7 0x1F0404AC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7 0x1F0404AC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_8__ADDR 0x1F0404B0 ++#define LPM_MEM_DI1_DW_GEN_8__EMPTY 0x1F0404B0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_8__FULL 0x1F0404B0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8 0x1F0404B0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F0404B0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8 0x1F0404B0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_6_8 0x1F0404B0,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_5_8 0x1F0404B0,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_4_8 0x1F0404B0,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_3_8 0x1F0404B0,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_2_8 0x1F0404B0,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_1_8 0x1F0404B0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_0_8 0x1F0404B0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_8__ADDR 0x1F0404B0 ++#define LPM_MEM_DI1_DW_GEN_8__EMPTY 0x1F0404B0,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_8__FULL 0x1F0404B0,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8 0x1F0404B0,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_START_PERIOD_8 0x1F0404B0,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8 0x1F0404B0,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F0404B0,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_RS_8 0x1F0404B0,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8 0x1F0404B0,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_9__ADDR 0x1F0404B4 ++#define LPM_MEM_DI1_DW_GEN_9__EMPTY 0x1F0404B4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_9__FULL 0x1F0404B4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9 0x1F0404B4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F0404B4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9 0x1F0404B4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_6_9 0x1F0404B4,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_5_9 0x1F0404B4,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_4_9 0x1F0404B4,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_3_9 0x1F0404B4,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_2_9 0x1F0404B4,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_1_9 0x1F0404B4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_0_9 0x1F0404B4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_9__ADDR 0x1F0404B4 ++#define LPM_MEM_DI1_DW_GEN_9__EMPTY 0x1F0404B4,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_9__FULL 0x1F0404B4,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9 0x1F0404B4,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_START_PERIOD_9 0x1F0404B4,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9 0x1F0404B4,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F0404B4,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_RS_9 0x1F0404B4,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9 0x1F0404B4,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_10__ADDR 0x1F0404B8 ++#define LPM_MEM_DI1_DW_GEN_10__EMPTY 0x1F0404B8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_10__FULL 0x1F0404B8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10 0x1F0404B8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F0404B8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10 0x1F0404B8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_6_10 0x1F0404B8,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_5_10 0x1F0404B8,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_4_10 0x1F0404B8,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_3_10 0x1F0404B8,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_2_10 0x1F0404B8,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_1_10 0x1F0404B8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_0_10 0x1F0404B8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_10__ADDR 0x1F0404B8 ++#define LPM_MEM_DI1_DW_GEN_10__EMPTY 0x1F0404B8,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_10__FULL 0x1F0404B8,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10 0x1F0404B8,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_START_PERIOD_10 0x1F0404B8,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10 0x1F0404B8,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F0404B8,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_RS_10 0x1F0404B8,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10 0x1F0404B8,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_11__ADDR 0x1F0404BC ++#define LPM_MEM_DI1_DW_GEN_11__EMPTY 0x1F0404BC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_11__FULL 0x1F0404BC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11 0x1F0404BC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F0404BC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11 0x1F0404BC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_6_11 0x1F0404BC,0x00003000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_5_11 0x1F0404BC,0x00000C00 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_4_11 0x1F0404BC,0x00000300 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_3_11 0x1F0404BC,0x000000C0 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_2_11 0x1F0404BC,0x00000030 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_1_11 0x1F0404BC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_0_11 0x1F0404BC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_GEN_11__ADDR 0x1F0404BC ++#define LPM_MEM_DI1_DW_GEN_11__EMPTY 0x1F0404BC,0x00000000 ++#define LPM_MEM_DI1_DW_GEN_11__FULL 0x1F0404BC,0xffffffff ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11 0x1F0404BC,0xFF000000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_START_PERIOD_11 0x1F0404BC,0x00FF0000 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11 0x1F0404BC,0x0000C000 ++#define LPM_MEM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F0404BC,0x000001F0 ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_RS_11 0x1F0404BC,0x0000000C ++#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11 0x1F0404BC,0x00000003 ++ ++#define LPM_MEM_DI1_DW_SET0_0__ADDR 0x1F0404C0 ++#define LPM_MEM_DI1_DW_SET0_0__EMPTY 0x1F0404C0,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_0__FULL 0x1F0404C0,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0 0x1F0404C0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0 0x1F0404C0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_1__ADDR 0x1F0404C4 ++#define LPM_MEM_DI1_DW_SET0_1__EMPTY 0x1F0404C4,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_1__FULL 0x1F0404C4,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1 0x1F0404C4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1 0x1F0404C4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_2__ADDR 0x1F0404C8 ++#define LPM_MEM_DI1_DW_SET0_2__EMPTY 0x1F0404C8,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_2__FULL 0x1F0404C8,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2 0x1F0404C8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2 0x1F0404C8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_3__ADDR 0x1F0404CC ++#define LPM_MEM_DI1_DW_SET0_3__EMPTY 0x1F0404CC,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_3__FULL 0x1F0404CC,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3 0x1F0404CC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3 0x1F0404CC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_4__ADDR 0x1F0404D0 ++#define LPM_MEM_DI1_DW_SET0_4__EMPTY 0x1F0404D0,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_4__FULL 0x1F0404D0,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4 0x1F0404D0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4 0x1F0404D0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_5__ADDR 0x1F0404D4 ++#define LPM_MEM_DI1_DW_SET0_5__EMPTY 0x1F0404D4,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_5__FULL 0x1F0404D4,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5 0x1F0404D4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5 0x1F0404D4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_6__ADDR 0x1F0404D8 ++#define LPM_MEM_DI1_DW_SET0_6__EMPTY 0x1F0404D8,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_6__FULL 0x1F0404D8,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6 0x1F0404D8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6 0x1F0404D8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_7__ADDR 0x1F0404DC ++#define LPM_MEM_DI1_DW_SET0_7__EMPTY 0x1F0404DC,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_7__FULL 0x1F0404DC,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7 0x1F0404DC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7 0x1F0404DC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_8__ADDR 0x1F0404E0 ++#define LPM_MEM_DI1_DW_SET0_8__EMPTY 0x1F0404E0,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_8__FULL 0x1F0404E0,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8 0x1F0404E0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8 0x1F0404E0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_9__ADDR 0x1F0404E4 ++#define LPM_MEM_DI1_DW_SET0_9__EMPTY 0x1F0404E4,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_9__FULL 0x1F0404E4,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9 0x1F0404E4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9 0x1F0404E4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_10__ADDR 0x1F0404E8 ++#define LPM_MEM_DI1_DW_SET0_10__EMPTY 0x1F0404E8,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_10__FULL 0x1F0404E8,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10 0x1F0404E8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10 0x1F0404E8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET0_11__ADDR 0x1F0404EC ++#define LPM_MEM_DI1_DW_SET0_11__EMPTY 0x1F0404EC,0x00000000 ++#define LPM_MEM_DI1_DW_SET0_11__FULL 0x1F0404EC,0xffffffff ++#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11 0x1F0404EC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11 0x1F0404EC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_0__ADDR 0x1F0404F0 ++#define LPM_MEM_DI1_DW_SET1_0__EMPTY 0x1F0404F0,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_0__FULL 0x1F0404F0,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0 0x1F0404F0,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0 0x1F0404F0,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_1__ADDR 0x1F0404F4 ++#define LPM_MEM_DI1_DW_SET1_1__EMPTY 0x1F0404F4,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_1__FULL 0x1F0404F4,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1 0x1F0404F4,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1 0x1F0404F4,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_2__ADDR 0x1F0404F8 ++#define LPM_MEM_DI1_DW_SET1_2__EMPTY 0x1F0404F8,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_2__FULL 0x1F0404F8,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2 0x1F0404F8,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2 0x1F0404F8,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_3__ADDR 0x1F0404FC ++#define LPM_MEM_DI1_DW_SET1_3__EMPTY 0x1F0404FC,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_3__FULL 0x1F0404FC,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3 0x1F0404FC,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3 0x1F0404FC,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_4__ADDR 0x1F040500 ++#define LPM_MEM_DI1_DW_SET1_4__EMPTY 0x1F040500,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_4__FULL 0x1F040500,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4 0x1F040500,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4 0x1F040500,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_5__ADDR 0x1F040504 ++#define LPM_MEM_DI1_DW_SET1_5__EMPTY 0x1F040504,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_5__FULL 0x1F040504,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5 0x1F040504,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5 0x1F040504,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_6__ADDR 0x1F040508 ++#define LPM_MEM_DI1_DW_SET1_6__EMPTY 0x1F040508,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_6__FULL 0x1F040508,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6 0x1F040508,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6 0x1F040508,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_7__ADDR 0x1F04050C ++#define LPM_MEM_DI1_DW_SET1_7__EMPTY 0x1F04050C,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_7__FULL 0x1F04050C,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7 0x1F04050C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7 0x1F04050C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_8__ADDR 0x1F040510 ++#define LPM_MEM_DI1_DW_SET1_8__EMPTY 0x1F040510,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_8__FULL 0x1F040510,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8 0x1F040510,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8 0x1F040510,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_9__ADDR 0x1F040514 ++#define LPM_MEM_DI1_DW_SET1_9__EMPTY 0x1F040514,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_9__FULL 0x1F040514,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9 0x1F040514,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9 0x1F040514,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_10__ADDR 0x1F040518 ++#define LPM_MEM_DI1_DW_SET1_10__EMPTY 0x1F040518,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_10__FULL 0x1F040518,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10 0x1F040518,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10 0x1F040518,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET1_11__ADDR 0x1F04051C ++#define LPM_MEM_DI1_DW_SET1_11__EMPTY 0x1F04051C,0x00000000 ++#define LPM_MEM_DI1_DW_SET1_11__FULL 0x1F04051C,0xffffffff ++#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11 0x1F04051C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11 0x1F04051C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_0__ADDR 0x1F040520 ++#define LPM_MEM_DI1_DW_SET2_0__EMPTY 0x1F040520,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_0__FULL 0x1F040520,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0 0x1F040520,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0 0x1F040520,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_1__ADDR 0x1F040524 ++#define LPM_MEM_DI1_DW_SET2_1__EMPTY 0x1F040524,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_1__FULL 0x1F040524,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1 0x1F040524,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1 0x1F040524,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_2__ADDR 0x1F040528 ++#define LPM_MEM_DI1_DW_SET2_2__EMPTY 0x1F040528,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_2__FULL 0x1F040528,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2 0x1F040528,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2 0x1F040528,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_3__ADDR 0x1F04052C ++#define LPM_MEM_DI1_DW_SET2_3__EMPTY 0x1F04052C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_3__FULL 0x1F04052C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3 0x1F04052C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3 0x1F04052C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_4__ADDR 0x1F040530 ++#define LPM_MEM_DI1_DW_SET2_4__EMPTY 0x1F040530,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_4__FULL 0x1F040530,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4 0x1F040530,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4 0x1F040530,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_5__ADDR 0x1F040534 ++#define LPM_MEM_DI1_DW_SET2_5__EMPTY 0x1F040534,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_5__FULL 0x1F040534,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5 0x1F040534,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5 0x1F040534,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_6__ADDR 0x1F040538 ++#define LPM_MEM_DI1_DW_SET2_6__EMPTY 0x1F040538,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_6__FULL 0x1F040538,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6 0x1F040538,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6 0x1F040538,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_7__ADDR 0x1F04053C ++#define LPM_MEM_DI1_DW_SET2_7__EMPTY 0x1F04053C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_7__FULL 0x1F04053C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7 0x1F04053C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7 0x1F04053C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_8__ADDR 0x1F040540 ++#define LPM_MEM_DI1_DW_SET2_8__EMPTY 0x1F040540,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_8__FULL 0x1F040540,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8 0x1F040540,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8 0x1F040540,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_9__ADDR 0x1F040544 ++#define LPM_MEM_DI1_DW_SET2_9__EMPTY 0x1F040544,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_9__FULL 0x1F040544,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9 0x1F040544,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9 0x1F040544,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_10__ADDR 0x1F040548 ++#define LPM_MEM_DI1_DW_SET2_10__EMPTY 0x1F040548,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_10__FULL 0x1F040548,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10 0x1F040548,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10 0x1F040548,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET2_11__ADDR 0x1F04054C ++#define LPM_MEM_DI1_DW_SET2_11__EMPTY 0x1F04054C,0x00000000 ++#define LPM_MEM_DI1_DW_SET2_11__FULL 0x1F04054C,0xffffffff ++#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11 0x1F04054C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11 0x1F04054C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_0__ADDR 0x1F040550 ++#define LPM_MEM_DI1_DW_SET3_0__EMPTY 0x1F040550,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_0__FULL 0x1F040550,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0 0x1F040550,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0 0x1F040550,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_1__ADDR 0x1F040554 ++#define LPM_MEM_DI1_DW_SET3_1__EMPTY 0x1F040554,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_1__FULL 0x1F040554,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1 0x1F040554,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1 0x1F040554,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_2__ADDR 0x1F040558 ++#define LPM_MEM_DI1_DW_SET3_2__EMPTY 0x1F040558,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_2__FULL 0x1F040558,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2 0x1F040558,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2 0x1F040558,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_3__ADDR 0x1F04055C ++#define LPM_MEM_DI1_DW_SET3_3__EMPTY 0x1F04055C,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_3__FULL 0x1F04055C,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3 0x1F04055C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3 0x1F04055C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_4__ADDR 0x1F040560 ++#define LPM_MEM_DI1_DW_SET3_4__EMPTY 0x1F040560,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_4__FULL 0x1F040560,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4 0x1F040560,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4 0x1F040560,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_5__ADDR 0x1F040564 ++#define LPM_MEM_DI1_DW_SET3_5__EMPTY 0x1F040564,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_5__FULL 0x1F040564,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5 0x1F040564,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5 0x1F040564,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_6__ADDR 0x1F040568 ++#define LPM_MEM_DI1_DW_SET3_6__EMPTY 0x1F040568,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_6__FULL 0x1F040568,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6 0x1F040568,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6 0x1F040568,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_7__ADDR 0x1F04056C ++#define LPM_MEM_DI1_DW_SET3_7__EMPTY 0x1F04056C,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_7__FULL 0x1F04056C,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7 0x1F04056C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7 0x1F04056C,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_8__ADDR 0x1F040570 ++#define LPM_MEM_DI1_DW_SET3_8__EMPTY 0x1F040570,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_8__FULL 0x1F040570,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8 0x1F040570,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8 0x1F040570,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_9__ADDR 0x1F040574 ++#define LPM_MEM_DI1_DW_SET3_9__EMPTY 0x1F040574,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_9__FULL 0x1F040574,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9 0x1F040574,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9 0x1F040574,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_10__ADDR 0x1F040578 ++#define LPM_MEM_DI1_DW_SET3_10__EMPTY 0x1F040578,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_10__FULL 0x1F040578,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10 0x1F040578,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10 0x1F040578,0x000001FF ++ ++#define LPM_MEM_DI1_DW_SET3_11__ADDR 0x1F04057C ++#define LPM_MEM_DI1_DW_SET3_11__EMPTY 0x1F04057C,0x00000000 ++#define LPM_MEM_DI1_DW_SET3_11__FULL 0x1F04057C,0xffffffff ++#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11 0x1F04057C,0x01FF0000 ++#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11 0x1F04057C,0x000001FF ++ ++#define LPM_MEM_DI1_STP_REP_1__ADDR 0x1F040580 ++#define LPM_MEM_DI1_STP_REP_1__EMPTY 0x1F040580,0x00000000 ++#define LPM_MEM_DI1_STP_REP_1__FULL 0x1F040580,0xffffffff ++#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_2 0x1F040580,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_1 0x1F040580,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_2__ADDR 0x1F040584 ++#define LPM_MEM_DI1_STP_REP_2__EMPTY 0x1F040584,0x00000000 ++#define LPM_MEM_DI1_STP_REP_2__FULL 0x1F040584,0xffffffff ++#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_4 0x1F040584,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_3 0x1F040584,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_3__ADDR 0x1F040588 ++#define LPM_MEM_DI1_STP_REP_3__EMPTY 0x1F040588,0x00000000 ++#define LPM_MEM_DI1_STP_REP_3__FULL 0x1F040588,0xffffffff ++#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_6 0x1F040588,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_5 0x1F040588,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_4__ADDR 0x1F04058C ++#define LPM_MEM_DI1_STP_REP_4__EMPTY 0x1F04058C,0x00000000 ++#define LPM_MEM_DI1_STP_REP_4__FULL 0x1F04058C,0xffffffff ++#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_8 0x1F04058C,0x0FFF0000 ++#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_7 0x1F04058C,0x00000FFF ++ ++#define LPM_MEM_DI1_STP_REP_9__ADDR 0x1F040590 ++#define LPM_MEM_DI1_STP_REP_9__EMPTY 0x1F040590,0x00000000 ++#define LPM_MEM_DI1_STP_REP_9__FULL 0x1F040590,0xffffffff ++#define LPM_MEM_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1F040590,0x00000FFF ++ ++#define LPM_MEM_DI1_SER_CONF__ADDR 0x1F040594 ++#define LPM_MEM_DI1_SER_CONF__EMPTY 0x1F040594,0x00000000 ++#define LPM_MEM_DI1_SER_CONF__FULL 0x1F040594,0xffffffff ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1F040594,0xF0000000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1F040594,0x0F000000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1F040594,0x00F00000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1F040594,0x000F0000 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LATCH 0x1F040594,0x0000FF00 ++#define LPM_MEM_DI1_SER_CONF__DI1_LLA_SER_ACCESS 0x1F040594,0x00000020 ++#define LPM_MEM_DI1_SER_CONF__DI1_SER_CLK_POLARITY 0x1F040594,0x00000010 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY 0x1F040594,0x00000008 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY 0x1F040594,0x00000004 ++#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY 0x1F040594,0x00000002 ++#define LPM_MEM_DI1_SER_CONF__DI1_WAIT4SERIAL 0x1F040594,0x00000001 ++ ++#define LPM_MEM_DI1_SSC__ADDR 0x1F040598 ++#define LPM_MEM_DI1_SSC__EMPTY 0x1F040598,0x00000000 ++#define LPM_MEM_DI1_SSC__FULL 0x1F040598,0xffffffff ++#define LPM_MEM_DI1_SSC__DI1_PIN17_ERM 0x1F040598,0x00800000 ++#define LPM_MEM_DI1_SSC__DI1_PIN16_ERM 0x1F040598,0x00400000 ++#define LPM_MEM_DI1_SSC__DI1_PIN15_ERM 0x1F040598,0x00200000 ++#define LPM_MEM_DI1_SSC__DI1_PIN14_ERM 0x1F040598,0x00100000 ++#define LPM_MEM_DI1_SSC__DI1_PIN13_ERM 0x1F040598,0x00080000 ++#define LPM_MEM_DI1_SSC__DI1_PIN12_ERM 0x1F040598,0x00040000 ++#define LPM_MEM_DI1_SSC__DI1_PIN11_ERM 0x1F040598,0x00020000 ++#define LPM_MEM_DI1_SSC__DI1_CS_ERM 0x1F040598,0x00010000 ++#define LPM_MEM_DI1_SSC__DI1_WAIT_ON 0x1F040598,0x00000020 ++#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1F040598,0x00000008 ++#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_PNTR 0x1F040598,0x00000007 ++ ++#define LPM_MEM_DI1_POL__ADDR 0x1F04059C ++#define LPM_MEM_DI1_POL__EMPTY 0x1F04059C,0x00000000 ++#define LPM_MEM_DI1_POL__FULL 0x1F04059C,0xffffffff ++#define LPM_MEM_DI1_POL__DI1_WAIT_POLARITY 0x1F04059C,0x04000000 ++#define LPM_MEM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1F04059C,0x02000000 ++#define LPM_MEM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1F04059C,0x01000000 ++#define LPM_MEM_DI1_POL__DI1_CS1_DATA_POLARITY 0x1F04059C,0x00800000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_17 0x1F04059C,0x00400000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_16 0x1F04059C,0x00200000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_15 0x1F04059C,0x00100000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_14 0x1F04059C,0x00080000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_13 0x1F04059C,0x00040000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_12 0x1F04059C,0x00020000 ++#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_11 0x1F04059C,0x00010000 ++#define LPM_MEM_DI1_POL__DI1_CS0_DATA_POLARITY 0x1F04059C,0x00008000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_17 0x1F04059C,0x00004000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_16 0x1F04059C,0x00002000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_15 0x1F04059C,0x00001000 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_14 0x1F04059C,0x00000800 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_13 0x1F04059C,0x00000400 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_12 0x1F04059C,0x00000200 ++#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_11 0x1F04059C,0x00000100 ++#define LPM_MEM_DI1_POL__DI1_DRDY_DATA_POLARITY 0x1F04059C,0x00000080 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_17 0x1F04059C,0x00000040 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_16 0x1F04059C,0x00000020 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_15 0x1F04059C,0x00000010 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_14 0x1F04059C,0x00000008 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_13 0x1F04059C,0x00000004 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_12 0x1F04059C,0x00000002 ++#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_11 0x1F04059C,0x00000001 ++ ++#define LPM_MEM_DI1_AW0__ADDR 0x1F0405A0 ++#define LPM_MEM_DI1_AW0__EMPTY 0x1F0405A0,0x00000000 ++#define LPM_MEM_DI1_AW0__FULL 0x1F0405A0,0xffffffff ++#define LPM_MEM_DI1_AW0__DI1_AW_TRIG_SEL 0x1F0405A0,0xF0000000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HEND 0x1F0405A0,0x0FFF0000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1F0405A0,0x0000F000 ++#define LPM_MEM_DI1_AW0__DI1_AW_HSTART 0x1F0405A0,0x00000FFF ++ ++#define LPM_MEM_DI1_AW1__ADDR 0x1F0405A4 ++#define LPM_MEM_DI1_AW1__EMPTY 0x1F0405A4,0x00000000 ++#define LPM_MEM_DI1_AW1__FULL 0x1F0405A4,0xffffffff ++#define LPM_MEM_DI1_AW1__DI1_AW_VEND 0x1F0405A4,0x0FFF0000 ++#define LPM_MEM_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1F0405A4,0x0000F000 ++#define LPM_MEM_DI1_AW1__DI1_AW_VSTART 0x1F0405A4,0x00000FFF ++ ++#define LPM_MEM_DI1_SCR_CONF__ADDR 0x1F0405A8 ++#define LPM_MEM_DI1_SCR_CONF__EMPTY 0x1F0405A8,0x00000000 ++#define LPM_MEM_DI1_SCR_CONF__FULL 0x1F0405A8,0xffffffff ++#define LPM_MEM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1F0405A8,0x00000FFF ++ ++#define LPM_MEM_DMFC_RD_CHAN__ADDR 0x1F0405AC ++#define LPM_MEM_DMFC_RD_CHAN__EMPTY 0x1F0405AC,0x00000000 ++#define LPM_MEM_DMFC_RD_CHAN__FULL 0x1F0405AC,0xffffffff ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_PPW_C 0x1F0405AC,0x03000000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_CLR_0 0x1F0405AC,0x00E00000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_SET_0 0x1F0405AC,0x001C0000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_EN_0 0x1F0405AC,0x00020000 ++#define LPM_MEM_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1F0405AC,0x000000C0 ++ ++#define LPM_MEM_DMFC_WR_CHAN__ADDR 0x1F0405B0 ++#define LPM_MEM_DMFC_WR_CHAN__EMPTY 0x1F0405B0,0x00000000 ++#define LPM_MEM_DMFC_WR_CHAN__FULL 0x1F0405B0,0xffffffff ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1F0405B0,0xC0000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C 0x1F0405B0,0x38000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2C 0x1F0405B0,0x07000000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1F0405B0,0x00C00000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C 0x1F0405B0,0x00380000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1C 0x1F0405B0,0x00070000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2 0x1F0405B0,0x0000C000 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2 0x1F0405B0,0x00003800 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2 0x1F0405B0,0x00000700 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1 0x1F0405B0,0x000000C0 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1 0x1F0405B0,0x00000038 ++#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1 0x1F0405B0,0x00000007 ++ ++#define LPM_MEM_DMFC_WR_CHAN_DEF__ADDR 0x1F0405B4 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__EMPTY 0x1F0405B4,0x00000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__FULL 0x1F0405B4,0xffffffff ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1F0405B4,0xE0000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1F0405B4,0x1C000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C 0x1F0405B4,0x02000000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1F0405B4,0x00E00000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1F0405B4,0x001C0000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C 0x1F0405B4,0x00020000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2 0x1F0405B4,0x0000E000 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2 0x1F0405B4,0x00001C00 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2 0x1F0405B4,0x00000200 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1 0x1F0405B4,0x000000E0 ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1 0x1F0405B4,0x0000001C ++#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1 0x1F0405B4,0x00000002 ++ ++#define LPM_MEM_DMFC_DP_CHAN__ADDR 0x1F0405B8 ++#define LPM_MEM_DMFC_DP_CHAN__EMPTY 0x1F0405B8,0x00000000 ++#define LPM_MEM_DMFC_DP_CHAN__FULL 0x1F0405B8,0xffffffff ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1F0405B8,0xC0000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F 0x1F0405B8,0x38000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6F 0x1F0405B8,0x07000000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1F0405B8,0x00C00000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B 0x1F0405B8,0x00380000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6B 0x1F0405B8,0x00070000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1F0405B8,0x0000C000 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F 0x1F0405B8,0x00003800 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5F 0x1F0405B8,0x00000700 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1F0405B8,0x000000C0 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B 0x1F0405B8,0x00000038 ++#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5B 0x1F0405B8,0x00000007 ++ ++#define LPM_MEM_DMFC_DP_CHAN_DEF__ADDR 0x1F0405BC ++#define LPM_MEM_DMFC_DP_CHAN_DEF__EMPTY 0x1F0405BC,0x00000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__FULL 0x1F0405BC,0xffffffff ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1F0405BC,0xE0000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1F0405BC,0x1C000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F 0x1F0405BC,0x02000000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1F0405BC,0x00E00000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1F0405BC,0x001C0000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B 0x1F0405BC,0x00020000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1F0405BC,0x0000E000 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1F0405BC,0x00001C00 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F 0x1F0405BC,0x00000200 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1F0405BC,0x000000E0 ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1F0405BC,0x0000001C ++#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B 0x1F0405BC,0x00000002 ++ ++#define LPM_MEM_DMFC_GENERAL1__ADDR 0x1F0405C0 ++#define LPM_MEM_DMFC_GENERAL1__EMPTY 0x1F0405C0,0x00000000 ++#define LPM_MEM_DMFC_GENERAL1__FULL 0x1F0405C0,0xffffffff ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_9 0x1F0405C0,0x01000000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6F 0x1F0405C0,0x00800000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6B 0x1F0405C0,0x00400000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5F 0x1F0405C0,0x00200000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5B 0x1F0405C0,0x00100000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_4 0x1F0405C0,0x00080000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_3 0x1F0405C0,0x00040000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_2 0x1F0405C0,0x00020000 ++#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_1 0x1F0405C0,0x00010000 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_CLR_9 0x1F0401C0,0x0000E000 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_SET_9 0x1F0401C0,0x00001C00 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_EN_9 0x1F0401C0,0x00000200 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1F0401C0,0x00000060 ++#define LPM_MEM_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1F0401C0,0x00000003 ++ ++#define LPM_MEM_DMFC_GENERAL2__ADDR 0x1F0405C4 ++#define LPM_MEM_DMFC_GENERAL2__EMPTY 0x1F0405C4,0x00000000 ++#define LPM_MEM_DMFC_GENERAL2__FULL 0x1F0405C4,0xffffffff ++#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1F0405C4,0x1FFF0000 ++#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD 0x1F0405C4,0x00001FFF ++ ++#define LPM_MEM_DMFC_IC_CTRL__ADDR 0x1F0405C8 ++#define LPM_MEM_DMFC_IC_CTRL__EMPTY 0x1F0405C8,0x00000000 ++#define LPM_MEM_DMFC_IC_CTRL__FULL 0x1F0405C8,0xffffffff ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1F0405C8,0xFFF80000 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD 0x1F0405C8,0x0007FFC0 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_PPW_C 0x1F0405C8,0x00000030 ++#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_IN_PORT 0x1F0405C8,0x00000007 ++ ++#define LPM_MEM_DC_READ_CH_CONF__ADDR 0x1F0405CC ++#define LPM_MEM_DC_READ_CH_CONF__EMPTY 0x1F0405CC,0x00000000 ++#define LPM_MEM_DC_READ_CH_CONF__FULL 0x1F0405CC,0xffffffff ++#define LPM_MEM_DC_READ_CH_CONF__TIME_OUT_VALUE 0x1F0405CC,0xFFFF0000 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_3 0x1F0405CC,0x00000800 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_2 0x1F0405CC,0x00000400 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_1 0x1F0405CC,0x00000200 ++#define LPM_MEM_DC_READ_CH_CONF__CS_ID_0 0x1F0405CC,0x00000100 ++#define LPM_MEM_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1F0405CC,0x00000040 ++#define LPM_MEM_DC_READ_CH_CONF__W_SIZE_0 0x1F0405CC,0x00000030 ++#define LPM_MEM_DC_READ_CH_CONF__PROG_DISP_ID_0 0x1F0405CC,0x0000000C ++#define LPM_MEM_DC_READ_CH_CONF__PROG_DI_ID_0 0x1F0405CC,0x00000002 ++#define LPM_MEM_DC_READ_CH_CONF__RD_CHANNEL_EN 0x1F0405CC,0x00000001 ++ ++#define LPM_MEM_DC_READ_CH_ADDR__ADDR 0x1F0405D0 ++#define LPM_MEM_DC_READ_CH_ADDR__EMPTY 0x1F0405D0,0x00000000 ++#define LPM_MEM_DC_READ_CH_ADDR__FULL 0x1F0405D0,0xffffffff ++#define LPM_MEM_DC_READ_CH_ADDR__ST_ADDR_0 0x1F0405D0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_0__ADDR 0x1F0405D4 ++#define LPM_MEM_DC_RL0_CH_0__EMPTY 0x1F0405D4,0x00000000 ++#define LPM_MEM_DC_RL0_CH_0__FULL 0x1F0405D4,0xffffffff ++#define LPM_MEM_DC_RL0_CH_0__COD_NL_START_CHAN_0 0x1F0405D4,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1F0405D4,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_0__COD_NF_START_CHAN_0 0x1F0405D4,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1F0405D4,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_0__ADDR 0x1F0405D8 ++#define LPM_MEM_DC_RL1_CH_0__EMPTY 0x1F0405D8,0x00000000 ++#define LPM_MEM_DC_RL1_CH_0__FULL 0x1F0405D8,0xffffffff ++#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0 0x1F0405D8,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1F0405D8,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_0__COD_EOF_START_CHAN_0 0x1F0405D8,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0 0x1F0405D8,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_0__ADDR 0x1F0405DC ++#define LPM_MEM_DC_RL2_CH_0__EMPTY 0x1F0405DC,0x00000000 ++#define LPM_MEM_DC_RL2_CH_0__FULL 0x1F0405DC,0xffffffff ++#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0 0x1F0405DC,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1F0405DC,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOL_START_CHAN_0 0x1F0405DC,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0 0x1F0405DC,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_0__ADDR 0x1F0405E0 ++#define LPM_MEM_DC_RL3_CH_0__EMPTY 0x1F0405E0,0x00000000 ++#define LPM_MEM_DC_RL3_CH_0__FULL 0x1F0405E0,0xffffffff ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0 0x1F0405E0,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1F0405E0,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0 0x1F0405E0,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1F0405E0,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_0__ADDR 0x1F0405E4 ++#define LPM_MEM_DC_RL4_CH_0__EMPTY 0x1F0405E4,0x00000000 ++#define LPM_MEM_DC_RL4_CH_0__FULL 0x1F0405E4,0xffffffff ++#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0 0x1F0405E4,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1F0405E4,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_1__ADDR 0x1F0405E8 ++#define LPM_MEM_DC_WR_CH_CONF_1__EMPTY 0x1F0405E8,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_1__FULL 0x1F0405E8,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_START_TIME_1 0x1F0405E8,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_1__FIELD_MODE_1 0x1F0405E8,0x00000200 ++#define LPM_MEM_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1F0405E8,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1 0x1F0405E8,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DISP_ID_1 0x1F0405E8,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DI_ID_1 0x1F0405E8,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_1__W_SIZE_1 0x1F0405E8,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_1__ADDR 0x1F0405EC ++#define LPM_MEM_DC_WR_CH_ADDR_1__EMPTY 0x1F0405EC,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_1__FULL 0x1F0405EC,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1F0405EC,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_1__ADDR 0x1F0405F0 ++#define LPM_MEM_DC_RL0_CH_1__EMPTY 0x1F0405F0,0x00000000 ++#define LPM_MEM_DC_RL0_CH_1__FULL 0x1F0405F0,0xffffffff ++#define LPM_MEM_DC_RL0_CH_1__COD_NL_START_CHAN_1 0x1F0405F0,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1F0405F0,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_1__COD_NF_START_CHAN_1 0x1F0405F0,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1F0405F0,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_1__ADDR 0x1F0405F4 ++#define LPM_MEM_DC_RL1_CH_1__EMPTY 0x1F0405F4,0x00000000 ++#define LPM_MEM_DC_RL1_CH_1__FULL 0x1F0405F4,0xffffffff ++#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1 0x1F0405F4,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1F0405F4,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_1__COD_EOF_START_CHAN_1 0x1F0405F4,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1 0x1F0405F4,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_1__ADDR 0x1F0405F8 ++#define LPM_MEM_DC_RL2_CH_1__EMPTY 0x1F0405F8,0x00000000 ++#define LPM_MEM_DC_RL2_CH_1__FULL 0x1F0405F8,0xffffffff ++#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1 0x1F0405F8,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1F0405F8,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOL_START_CHAN_1 0x1F0405F8,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1 0x1F0405F8,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_1__ADDR 0x1F0405FC ++#define LPM_MEM_DC_RL3_CH_1__EMPTY 0x1F0405FC,0x00000000 ++#define LPM_MEM_DC_RL3_CH_1__FULL 0x1F0405FC,0xffffffff ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1 0x1F0405FC,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1F0405FC,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1 0x1F0405FC,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1F0405FC,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_1__ADDR 0x1F040600 ++#define LPM_MEM_DC_RL4_CH_1__EMPTY 0x1F040600,0x00000000 ++#define LPM_MEM_DC_RL4_CH_1__FULL 0x1F040600,0xffffffff ++#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1 0x1F040600,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1F040600,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_2__ADDR 0x1F040604 ++#define LPM_MEM_DC_WR_CH_CONF_2__EMPTY 0x1F040604,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_2__FULL 0x1F040604,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_START_TIME_2 0x1F040604,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1F040604,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2 0x1F040604,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DISP_ID_2 0x1F040604,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DI_ID_2 0x1F040604,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_2__W_SIZE_2 0x1F040604,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_2__ADDR 0x1F040608 ++#define LPM_MEM_DC_WR_CH_ADDR_2__EMPTY 0x1F040608,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_2__FULL 0x1F040608,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1F040608,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_2__ADDR 0x1F04060C ++#define LPM_MEM_DC_RL0_CH_2__EMPTY 0x1F04060C,0x00000000 ++#define LPM_MEM_DC_RL0_CH_2__FULL 0x1F04060C,0xffffffff ++#define LPM_MEM_DC_RL0_CH_2__COD_NL_START_CHAN_2 0x1F04060C,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1F04060C,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_2__COD_NF_START_CHAN_2 0x1F04060C,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1F04060C,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_2__ADDR 0x1F040610 ++#define LPM_MEM_DC_RL1_CH_2__EMPTY 0x1F040610,0x00000000 ++#define LPM_MEM_DC_RL1_CH_2__FULL 0x1F040610,0xffffffff ++#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2 0x1F040610,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1F040610,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_2__COD_EOF_START_CHAN_2 0x1F040610,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2 0x1F040610,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_2__ADDR 0x1F040614 ++#define LPM_MEM_DC_RL2_CH_2__EMPTY 0x1F040614,0x00000000 ++#define LPM_MEM_DC_RL2_CH_2__FULL 0x1F040614,0xffffffff ++#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2 0x1F040614,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1F040614,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOL_START_CHAN_2 0x1F040614,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2 0x1F040614,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_2__ADDR 0x1F040618 ++#define LPM_MEM_DC_RL3_CH_2__EMPTY 0x1F040618,0x00000000 ++#define LPM_MEM_DC_RL3_CH_2__FULL 0x1F040618,0xffffffff ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2 0x1F040618,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1F040618,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2 0x1F040618,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1F040618,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_2__ADDR 0x1F04061C ++#define LPM_MEM_DC_RL4_CH_2__EMPTY 0x1F04061C,0x00000000 ++#define LPM_MEM_DC_RL4_CH_2__FULL 0x1F04061C,0xffffffff ++#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2 0x1F04061C,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1F04061C,0x0000000F ++ ++#define LPM_MEM_DC_CMD_CH_CONF_3__ADDR 0x1F040620 ++#define LPM_MEM_DC_CMD_CH_CONF_3__EMPTY 0x1F040620,0x00000000 ++#define LPM_MEM_DC_CMD_CH_CONF_3__FULL 0x1F040620,0xffffffff ++#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1F040620,0xFF000000 ++#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1F040620,0x0000FF00 ++#define LPM_MEM_DC_CMD_CH_CONF_3__W_SIZE_3 0x1F040620,0x00000003 ++ ++#define LPM_MEM_DC_CMD_CH_CONF_4__ADDR 0x1F040624 ++#define LPM_MEM_DC_CMD_CH_CONF_4__EMPTY 0x1F040624,0x00000000 ++#define LPM_MEM_DC_CMD_CH_CONF_4__FULL 0x1F040624,0xffffffff ++#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1F040624,0xFF000000 ++#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1F040624,0x0000FF00 ++#define LPM_MEM_DC_CMD_CH_CONF_4__W_SIZE_4 0x1F040624,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF_5__ADDR 0x1F040628 ++#define LPM_MEM_DC_WR_CH_CONF_5__EMPTY 0x1F040628,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_5__FULL 0x1F040628,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_START_TIME_5 0x1F040628,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_5__FIELD_MODE_5 0x1F040628,0x00000200 ++#define LPM_MEM_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1F040628,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5 0x1F040628,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DISP_ID_5 0x1F040628,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DI_ID_5 0x1F040628,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_5__W_SIZE_5 0x1F040628,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_5__ADDR 0x1F04062C ++#define LPM_MEM_DC_WR_CH_ADDR_5__EMPTY 0x1F04062C,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_5__FULL 0x1F04062C,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1F04062C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_5__ADDR 0x1F040630 ++#define LPM_MEM_DC_RL0_CH_5__EMPTY 0x1F040630,0x00000000 ++#define LPM_MEM_DC_RL0_CH_5__FULL 0x1F040630,0xffffffff ++#define LPM_MEM_DC_RL0_CH_5__COD_NL_START_CHAN_5 0x1F040630,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1F040630,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_5__COD_NF_START_CHAN_5 0x1F040630,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1F040630,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_5__ADDR 0x1F040634 ++#define LPM_MEM_DC_RL1_CH_5__EMPTY 0x1F040634,0x00000000 ++#define LPM_MEM_DC_RL1_CH_5__FULL 0x1F040634,0xffffffff ++#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5 0x1F040634,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1F040634,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_5__COD_EOF_START_CHAN_5 0x1F040634,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5 0x1F040634,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_5__ADDR 0x1F040638 ++#define LPM_MEM_DC_RL2_CH_5__EMPTY 0x1F040638,0x00000000 ++#define LPM_MEM_DC_RL2_CH_5__FULL 0x1F040638,0xffffffff ++#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5 0x1F040638,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1F040638,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOL_START_CHAN_5 0x1F040638,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5 0x1F040638,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_5__ADDR 0x1F04063C ++#define LPM_MEM_DC_RL3_CH_5__EMPTY 0x1F04063C,0x00000000 ++#define LPM_MEM_DC_RL3_CH_5__FULL 0x1F04063C,0xffffffff ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5 0x1F04063C,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1F04063C,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5 0x1F04063C,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1F04063C,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_5__ADDR 0x1F040640 ++#define LPM_MEM_DC_RL4_CH_5__EMPTY 0x1F040640,0x00000000 ++#define LPM_MEM_DC_RL4_CH_5__FULL 0x1F040640,0xffffffff ++#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5 0x1F040640,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1F040640,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF_6__ADDR 0x1F040644 ++#define LPM_MEM_DC_WR_CH_CONF_6__EMPTY 0x1F040644,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF_6__FULL 0x1F040644,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_START_TIME_6 0x1F040644,0x07FF0000 ++#define LPM_MEM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1F040644,0x00000100 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6 0x1F040644,0x000000E0 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DISP_ID_6 0x1F040644,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DI_ID_6 0x1F040644,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF_6__W_SIZE_6 0x1F040644,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_ADDR_6__ADDR 0x1F040648 ++#define LPM_MEM_DC_WR_CH_ADDR_6__EMPTY 0x1F040648,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_6__FULL 0x1F040648,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1F040648,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL0_CH_6__ADDR 0x1F04064C ++#define LPM_MEM_DC_RL0_CH_6__EMPTY 0x1F04064C,0x00000000 ++#define LPM_MEM_DC_RL0_CH_6__FULL 0x1F04064C,0xffffffff ++#define LPM_MEM_DC_RL0_CH_6__COD_NL_START_CHAN_6 0x1F04064C,0xFF000000 ++#define LPM_MEM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1F04064C,0x000F0000 ++#define LPM_MEM_DC_RL0_CH_6__COD_NF_START_CHAN_6 0x1F04064C,0x0000FF00 ++#define LPM_MEM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1F04064C,0x0000000F ++ ++#define LPM_MEM_DC_RL1_CH_6__ADDR 0x1F040650 ++#define LPM_MEM_DC_RL1_CH_6__EMPTY 0x1F040650,0x00000000 ++#define LPM_MEM_DC_RL1_CH_6__FULL 0x1F040650,0xffffffff ++#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6 0x1F040650,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1F040650,0x000F0000 ++#define LPM_MEM_DC_RL1_CH_6__COD_EOF_START_CHAN_6 0x1F040650,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6 0x1F040650,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_6__ADDR 0x1F040654 ++#define LPM_MEM_DC_RL2_CH_6__EMPTY 0x1F040654,0x00000000 ++#define LPM_MEM_DC_RL2_CH_6__FULL 0x1F040654,0xffffffff ++#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6 0x1F040654,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1F040654,0x000F0000 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOL_START_CHAN_6 0x1F040654,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6 0x1F040654,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_6__ADDR 0x1F040658 ++#define LPM_MEM_DC_RL3_CH_6__EMPTY 0x1F040658,0x00000000 ++#define LPM_MEM_DC_RL3_CH_6__FULL 0x1F040658,0xffffffff ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6 0x1F040658,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1F040658,0x000F0000 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6 0x1F040658,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1F040658,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_6__ADDR 0x1F04065C ++#define LPM_MEM_DC_RL4_CH_6__EMPTY 0x1F04065C,0x00000000 ++#define LPM_MEM_DC_RL4_CH_6__FULL 0x1F04065C,0xffffffff ++#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6 0x1F04065C,0x0000FF00 ++#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1F04065C,0x0000000F ++ ++#define LPM_MEM_DC_WR_CH_CONF1_8__ADDR 0x1F040660 ++#define LPM_MEM_DC_WR_CH_CONF1_8__EMPTY 0x1F040660,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF1_8__FULL 0x1F040660,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF1_8__MCU_DISP_ID_8 0x1F040660,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1F040660,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF1_8__W_SIZE_8 0x1F040660,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF2_8__ADDR 0x1F040664 ++#define LPM_MEM_DC_WR_CH_CONF2_8__EMPTY 0x1F040664,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF2_8__FULL 0x1F040664,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1F040664,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL1_CH_8__ADDR 0x1F040668 ++#define LPM_MEM_DC_RL1_CH_8__EMPTY 0x1F040668,0x00000000 ++#define LPM_MEM_DC_RL1_CH_8__FULL 0x1F040668,0xffffffff ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1F040668,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1F040668,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8 0x1F040668,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_8__ADDR 0x1F04066C ++#define LPM_MEM_DC_RL2_CH_8__EMPTY 0x1F04066C,0x00000000 ++#define LPM_MEM_DC_RL2_CH_8__FULL 0x1F04066C,0xffffffff ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1F04066C,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1F04066C,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8 0x1F04066C,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_8__ADDR 0x1F040670 ++#define LPM_MEM_DC_RL3_CH_8__EMPTY 0x1F040670,0x00000000 ++#define LPM_MEM_DC_RL3_CH_8__FULL 0x1F040670,0xffffffff ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1F040670,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1F040670,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8 0x1F040670,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_8__ADDR 0x1F040674 ++#define LPM_MEM_DC_RL4_CH_8__EMPTY 0x1F040674,0x00000000 ++#define LPM_MEM_DC_RL4_CH_8__FULL 0x1F040674,0xffffffff ++#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1F040674,0xFF000000 ++#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1F040674,0x0000FF00 ++ ++#define LPM_MEM_DC_RL5_CH_8__ADDR 0x1F040678 ++#define LPM_MEM_DC_RL5_CH_8__EMPTY 0x1F040678,0x00000000 ++#define LPM_MEM_DC_RL5_CH_8__FULL 0x1F040678,0xffffffff ++#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1F040678,0xFF000000 ++#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1F040678,0x0000FF00 ++ ++#define LPM_MEM_DC_RL6_CH_8__ADDR 0x1F04067C ++#define LPM_MEM_DC_RL6_CH_8__EMPTY 0x1F04067C,0x00000000 ++#define LPM_MEM_DC_RL6_CH_8__FULL 0x1F04067C,0xffffffff ++#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1F04067C,0xFF000000 ++#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1F04067C,0x0000FF00 ++ ++#define LPM_MEM_DC_WR_CH_CONF1_9__ADDR 0x1F040680 ++#define LPM_MEM_DC_WR_CH_CONF1_9__EMPTY 0x1F040680,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF1_9__FULL 0x1F040680,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF1_9__MCU_DISP_ID_9 0x1F040680,0x00000018 ++#define LPM_MEM_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1F040680,0x00000004 ++#define LPM_MEM_DC_WR_CH_CONF1_9__W_SIZE_9 0x1F040680,0x00000003 ++ ++#define LPM_MEM_DC_WR_CH_CONF2_9__ADDR 0x1F040684 ++#define LPM_MEM_DC_WR_CH_CONF2_9__EMPTY 0x1F040684,0x00000000 ++#define LPM_MEM_DC_WR_CH_CONF2_9__FULL 0x1F040684,0xffffffff ++#define LPM_MEM_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1F040684,0x1FFFFFFF ++ ++#define LPM_MEM_DC_RL1_CH_9__ADDR 0x1F040688 ++#define LPM_MEM_DC_RL1_CH_9__EMPTY 0x1F040688,0x00000000 ++#define LPM_MEM_DC_RL1_CH_9__FULL 0x1F040688,0xffffffff ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1F040688,0xFF000000 ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1F040688,0x0000FF00 ++#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9 0x1F040688,0x0000000F ++ ++#define LPM_MEM_DC_RL2_CH_9__ADDR 0x1F04068C ++#define LPM_MEM_DC_RL2_CH_9__EMPTY 0x1F04068C,0x00000000 ++#define LPM_MEM_DC_RL2_CH_9__FULL 0x1F04068C,0xffffffff ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1F04068C,0xFF000000 ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1F04068C,0x0000FF00 ++#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9 0x1F04068C,0x0000000F ++ ++#define LPM_MEM_DC_RL3_CH_9__ADDR 0x1F040690 ++#define LPM_MEM_DC_RL3_CH_9__EMPTY 0x1F040690,0x00000000 ++#define LPM_MEM_DC_RL3_CH_9__FULL 0x1F040690,0xffffffff ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1F040690,0xFF000000 ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1F040690,0x0000FF00 ++#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9 0x1F040690,0x0000000F ++ ++#define LPM_MEM_DC_RL4_CH_9__ADDR 0x1F040694 ++#define LPM_MEM_DC_RL4_CH_9__EMPTY 0x1F040694,0x00000000 ++#define LPM_MEM_DC_RL4_CH_9__FULL 0x1F040694,0xffffffff ++#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1F040694,0xFF000000 ++#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1F040694,0x0000FF00 ++ ++#define LPM_MEM_DC_RL5_CH_9__ADDR 0x1F040698 ++#define LPM_MEM_DC_RL5_CH_9__EMPTY 0x1F040698,0x00000000 ++#define LPM_MEM_DC_RL5_CH_9__FULL 0x1F040698,0xffffffff ++#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1F040698,0xFF000000 ++#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1F040698,0x0000FF00 ++ ++#define LPM_MEM_DC_RL6_CH_9__ADDR 0x1F04069C ++#define LPM_MEM_DC_RL6_CH_9__EMPTY 0x1F04069C,0x00000000 ++#define LPM_MEM_DC_RL6_CH_9__FULL 0x1F04069C,0xffffffff ++#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1F04069C,0xFF000000 ++#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1F04069C,0x0000FF00 ++ ++#define LPM_MEM_DC_GEN__ADDR 0x1F0406A0 ++#define LPM_MEM_DC_GEN__EMPTY 0x1F0406A0,0x00000000 ++#define LPM_MEM_DC_GEN__FULL 0x1F0406A0,0xffffffff ++#define LPM_MEM_DC_GEN__DC_BK_EN 0x1F0406A0,0x01000000 ++#define LPM_MEM_DC_GEN__DC_BKDIV 0x1F0406A0,0x00FF0000 ++#define LPM_MEM_DC_GEN__DC_CH5_TYPE 0x1F0406A0,0x00000100 ++#define LPM_MEM_DC_GEN__SYNC_PRIORITY_1 0x1F0406A0,0x00000080 ++#define LPM_MEM_DC_GEN__SYNC_PRIORITY_5 0x1F0406A0,0x00000040 ++#define LPM_MEM_DC_GEN__MASK4CHAN_5 0x1F0406A0,0x00000020 ++#define LPM_MEM_DC_GEN__MASK_EN 0x1F0406A0,0x00000010 ++#define LPM_MEM_DC_GEN__SYNC_1_6 0x1F0406A0,0x00000006 ++ ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR 0x1F0406A4 ++#define LPM_MEM_DC_DISP_CONF1_0__EMPTY 0x1F0406A4,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_0__FULL 0x1F0406A4,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1F0406A4,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0 0x1F0406A4,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR_BE_L_INC_0 0x1F0406A4,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_0__ADDR_INCREMENT_0 0x1F0406A4,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_0__DISP_TYP_0 0x1F0406A4,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR 0x1F0406A8 ++#define LPM_MEM_DC_DISP_CONF1_1__EMPTY 0x1F0406A8,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_1__FULL 0x1F0406A8,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1F0406A8,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1 0x1F0406A8,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR_BE_L_INC_1 0x1F0406A8,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_1__ADDR_INCREMENT_1 0x1F0406A8,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_1__DISP_TYP_1 0x1F0406A8,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR 0x1F0406AC ++#define LPM_MEM_DC_DISP_CONF1_2__EMPTY 0x1F0406AC,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_2__FULL 0x1F0406AC,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1F0406AC,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2 0x1F0406AC,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR_BE_L_INC_2 0x1F0406AC,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_2__ADDR_INCREMENT_2 0x1F0406AC,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_2__DISP_TYP_2 0x1F0406AC,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR 0x1F0406B0 ++#define LPM_MEM_DC_DISP_CONF1_3__EMPTY 0x1F0406B0,0x00000000 ++#define LPM_MEM_DC_DISP_CONF1_3__FULL 0x1F0406B0,0xffffffff ++#define LPM_MEM_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1F0406B0,0x00000080 ++#define LPM_MEM_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3 0x1F0406B0,0x00000040 ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR_BE_L_INC_3 0x1F0406B0,0x00000030 ++#define LPM_MEM_DC_DISP_CONF1_3__ADDR_INCREMENT_3 0x1F0406B0,0x0000000C ++#define LPM_MEM_DC_DISP_CONF1_3__DISP_TYP_3 0x1F0406B0,0x00000003 ++ ++#define LPM_MEM_DC_DISP_CONF2_0__ADDR 0x1F0406B4 ++#define LPM_MEM_DC_DISP_CONF2_0__EMPTY 0x1F0406B4,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_0__FULL 0x1F0406B4,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_0__SL_0 0x1F0406B4,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_1__ADDR 0x1F0406B8 ++#define LPM_MEM_DC_DISP_CONF2_1__EMPTY 0x1F0406B8,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_1__FULL 0x1F0406B8,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_1__SL_1 0x1F0406B8,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_2__ADDR 0x1F0406BC ++#define LPM_MEM_DC_DISP_CONF2_2__EMPTY 0x1F0406BC,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_2__FULL 0x1F0406BC,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_2__SL_2 0x1F0406BC,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DISP_CONF2_3__ADDR 0x1F0406C0 ++#define LPM_MEM_DC_DISP_CONF2_3__EMPTY 0x1F0406C0,0x00000000 ++#define LPM_MEM_DC_DISP_CONF2_3__FULL 0x1F0406C0,0xffffffff ++#define LPM_MEM_DC_DISP_CONF2_3__SL_3 0x1F0406C0,0x1FFFFFFF ++ ++#define LPM_MEM_DC_DI0_CONF_1__ADDR 0x1F0406C4 ++#define LPM_MEM_DC_DI0_CONF_1__EMPTY 0x1F0406C4,0x00000000 ++#define LPM_MEM_DC_DI0_CONF_1__FULL 0x1F0406C4,0xffffffff ++#define LPM_MEM_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1F0406C4,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI0_CONF_2__ADDR 0x1F0406C8 ++#define LPM_MEM_DC_DI0_CONF_2__EMPTY 0x1F0406C8,0x00000000 ++#define LPM_MEM_DC_DI0_CONF_2__FULL 0x1F0406C8,0xffffffff ++#define LPM_MEM_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1F0406C8,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI1_CONF_1__ADDR 0x1F0406CC ++#define LPM_MEM_DC_DI1_CONF_1__EMPTY 0x1F0406CC,0x00000000 ++#define LPM_MEM_DC_DI1_CONF_1__FULL 0x1F0406CC,0xffffffff ++#define LPM_MEM_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1F0406CC,0xFFFFFFFF ++ ++#define LPM_MEM_DC_DI1_CONF_2__ADDR 0x1F0406D0 ++#define LPM_MEM_DC_DI1_CONF_2__EMPTY 0x1F0406D0,0x00000000 ++#define LPM_MEM_DC_DI1_CONF_2__FULL 0x1F0406D0,0xffffffff ++#define LPM_MEM_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1F0406D0,0xFFFFFFFF ++ ++#define LPM_MEM_DC_MAP_CONF_0__ADDR 0x1F0406D4 ++#define LPM_MEM_DC_MAP_CONF_0__EMPTY 0x1F0406D4,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_0__FULL 0x1F0406D4,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1F0406D4,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1F0406D4,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1F0406D4,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1F0406D4,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1F0406D4,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1F0406D4,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_1__ADDR 0x1F0406D8 ++#define LPM_MEM_DC_MAP_CONF_1__EMPTY 0x1F0406D8,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_1__FULL 0x1F0406D8,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1F0406D8,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1F0406D8,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1F0406D8,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1F0406D8,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1F0406D8,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1F0406D8,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_2__ADDR 0x1F0406DC ++#define LPM_MEM_DC_MAP_CONF_2__EMPTY 0x1F0406DC,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_2__FULL 0x1F0406DC,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1F0406DC,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1F0406DC,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1F0406DC,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1F0406DC,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1F0406DC,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1F0406DC,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_3__ADDR 0x1F0406E0 ++#define LPM_MEM_DC_MAP_CONF_3__EMPTY 0x1F0406E0,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_3__FULL 0x1F0406E0,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1F0406E0,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1F0406E0,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1F0406E0,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1F0406E0,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1F0406E0,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1F0406E0,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_4__ADDR 0x1F0406E4 ++#define LPM_MEM_DC_MAP_CONF_4__EMPTY 0x1F0406E4,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_4__FULL 0x1F0406E4,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1F0406E4,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1F0406E4,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1F0406E4,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1F0406E4,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1F0406E4,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1F0406E4,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_5__ADDR 0x1F0406E8 ++#define LPM_MEM_DC_MAP_CONF_5__EMPTY 0x1F0406E8,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_5__FULL 0x1F0406E8,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1F0406E8,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1F0406E8,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1F0406E8,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1F0406E8,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1F0406E8,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1F0406E8,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_6__ADDR 0x1F0406EC ++#define LPM_MEM_DC_MAP_CONF_6__EMPTY 0x1F0406EC,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_6__FULL 0x1F0406EC,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1F0406EC,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1F0406EC,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1F0406EC,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1F0406EC,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1F0406EC,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1F0406EC,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_7__ADDR 0x1F0406F0 ++#define LPM_MEM_DC_MAP_CONF_7__EMPTY 0x1F0406F0,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_7__FULL 0x1F0406F0,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1F0406F0,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1F0406F0,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1F0406F0,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1F0406F0,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1F0406F0,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1F0406F0,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_8__ADDR 0x1F0406F4 ++#define LPM_MEM_DC_MAP_CONF_8__EMPTY 0x1F0406F4,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_8__FULL 0x1F0406F4,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1F0406F4,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1F0406F4,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1F0406F4,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1F0406F4,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1F0406F4,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1F0406F4,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_9__ADDR 0x1F0406F8 ++#define LPM_MEM_DC_MAP_CONF_9__EMPTY 0x1F0406F8,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_9__FULL 0x1F0406F8,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1F0406F8,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1F0406F8,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1F0406F8,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1F0406F8,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1F0406F8,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1F0406F8,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_10__ADDR 0x1F0406FC ++#define LPM_MEM_DC_MAP_CONF_10__EMPTY 0x1F0406FC,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_10__FULL 0x1F0406FC,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1F0406FC,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1F0406FC,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1F0406FC,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1F0406FC,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1F0406FC,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1F0406FC,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_11__ADDR 0x1F040700 ++#define LPM_MEM_DC_MAP_CONF_11__EMPTY 0x1F040700,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_11__FULL 0x1F040700,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1F040700,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1F040700,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1F040700,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1F040700,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1F040700,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1F040700,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_12__ADDR 0x1F040704 ++#define LPM_MEM_DC_MAP_CONF_12__EMPTY 0x1F040704,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_12__FULL 0x1F040704,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1F040704,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1F040704,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1F040704,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1F040704,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1F040704,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1F040704,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_13__ADDR 0x1F040708 ++#define LPM_MEM_DC_MAP_CONF_13__EMPTY 0x1F040708,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_13__FULL 0x1F040708,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1F040708,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1F040708,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1F040708,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1F040708,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1F040708,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1F040708,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_14__ADDR 0x1F04070C ++#define LPM_MEM_DC_MAP_CONF_14__EMPTY 0x1F04070C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_14__FULL 0x1F04070C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1F04070C,0x7C000000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1F04070C,0x03E00000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1F04070C,0x001F0000 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1F04070C,0x00007C00 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1F04070C,0x000003E0 ++#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1F04070C,0x0000001F ++ ++#define LPM_MEM_DC_MAP_CONF_15__ADDR 0x1F040710 ++#define LPM_MEM_DC_MAP_CONF_15__EMPTY 0x1F040710,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_15__FULL 0x1F040710,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_1 0x1F040710,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_1 0x1F040710,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_0 0x1F040710,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_0 0x1F040710,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_16__ADDR 0x1F040714 ++#define LPM_MEM_DC_MAP_CONF_16__EMPTY 0x1F040714,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_16__FULL 0x1F040714,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_3 0x1F040714,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_3 0x1F040714,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_2 0x1F040714,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_2 0x1F040714,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_17__ADDR 0x1F040718 ++#define LPM_MEM_DC_MAP_CONF_17__EMPTY 0x1F040718,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_17__FULL 0x1F040718,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_5 0x1F040718,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_5 0x1F040718,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_4 0x1F040718,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_4 0x1F040718,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_18__ADDR 0x1F04071C ++#define LPM_MEM_DC_MAP_CONF_18__EMPTY 0x1F04071C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_18__FULL 0x1F04071C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_7 0x1F04071C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_7 0x1F04071C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_6 0x1F04071C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_6 0x1F04071C,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_19__ADDR 0x1F040720 ++#define LPM_MEM_DC_MAP_CONF_19__EMPTY 0x1F040720,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_19__FULL 0x1F040720,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_9 0x1F040720,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_9 0x1F040720,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_8 0x1F040720,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_8 0x1F040720,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_20__ADDR 0x1F040724 ++#define LPM_MEM_DC_MAP_CONF_20__EMPTY 0x1F040724,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_20__FULL 0x1F040724,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_11 0x1F040724,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_11 0x1F040724,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_10 0x1F040724,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_10 0x1F040724,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_21__ADDR 0x1F040728 ++#define LPM_MEM_DC_MAP_CONF_21__EMPTY 0x1F040728,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_21__FULL 0x1F040728,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_13 0x1F040728,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_13 0x1F040728,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_12 0x1F040728,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_12 0x1F040728,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_22__ADDR 0x1F04072C ++#define LPM_MEM_DC_MAP_CONF_22__EMPTY 0x1F04072C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_22__FULL 0x1F04072C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_15 0x1F04072C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_15 0x1F04072C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_14 0x1F04072C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_14 0x1F04072C,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_23__ADDR 0x1F040730 ++#define LPM_MEM_DC_MAP_CONF_23__EMPTY 0x1F040730,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_23__FULL 0x1F040730,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_17 0x1F040730,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_17 0x1F040730,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_16 0x1F040730,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_16 0x1F040730,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_24__ADDR 0x1F040734 ++#define LPM_MEM_DC_MAP_CONF_24__EMPTY 0x1F040734,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_24__FULL 0x1F040734,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_19 0x1F040734,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_19 0x1F040734,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_18 0x1F040734,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_18 0x1F040734,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_25__ADDR 0x1F040738 ++#define LPM_MEM_DC_MAP_CONF_25__EMPTY 0x1F040738,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_25__FULL 0x1F040738,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_21 0x1F040738,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_21 0x1F040738,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_20 0x1F040738,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_20 0x1F040738,0x000000FF ++ ++#define LPM_MEM_DC_MAP_CONF_26__ADDR 0x1F04073C ++#define LPM_MEM_DC_MAP_CONF_26__EMPTY 0x1F04073C,0x00000000 ++#define LPM_MEM_DC_MAP_CONF_26__FULL 0x1F04073C,0xffffffff ++#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_23 0x1F04073C,0x1F000000 ++#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_23 0x1F04073C,0x00FF0000 ++#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_22 0x1F04073C,0x00001F00 ++#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_22 0x1F04073C,0x000000FF ++ ++#define LPM_MEM_DC_UGDE0_0__ADDR 0x1F040740 ++#define LPM_MEM_DC_UGDE0_0__EMPTY 0x1F040740,0x00000000 ++#define LPM_MEM_DC_UGDE0_0__FULL 0x1F040740,0xffffffff ++#define LPM_MEM_DC_UGDE0_0__NF_NL_0 0x1F040740,0x18000000 ++#define LPM_MEM_DC_UGDE0_0__AUTORESTART_0 0x1F040740,0x04000000 ++#define LPM_MEM_DC_UGDE0_0__ODD_EN_0 0x1F040740,0x02000000 ++#define LPM_MEM_DC_UGDE0_0__COD_ODD_START_0 0x1F040740,0x00FF0000 ++#define LPM_MEM_DC_UGDE0_0__COD_EV_START_0 0x1F040740,0x0000FF00 ++#define LPM_MEM_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1F040740,0x00000078 ++#define LPM_MEM_DC_UGDE0_0__ID_CODED_0 0x1F040740,0x00000007 ++ ++#define LPM_MEM_DC_UGDE0_1__ADDR 0x1F040744 ++#define LPM_MEM_DC_UGDE0_1__EMPTY 0x1F040744,0x00000000 ++#define LPM_MEM_DC_UGDE0_1__FULL 0x1F040744,0xffffffff ++#define LPM_MEM_DC_UGDE0_1__STEP_0 0x1F040744,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE0_2__ADDR 0x1F040748 ++#define LPM_MEM_DC_UGDE0_2__EMPTY 0x1F040748,0x00000000 ++#define LPM_MEM_DC_UGDE0_2__FULL 0x1F040748,0xffffffff ++#define LPM_MEM_DC_UGDE0_2__OFFSET_DT_0 0x1F040748,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE0_3__ADDR 0x1F04074C ++#define LPM_MEM_DC_UGDE0_3__EMPTY 0x1F04074C,0x00000000 ++#define LPM_MEM_DC_UGDE0_3__FULL 0x1F04074C,0xffffffff ++#define LPM_MEM_DC_UGDE0_3__STEP_REPEAT_0 0x1F04074C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_0__ADDR 0x1F040750 ++#define LPM_MEM_DC_UGDE1_0__EMPTY 0x1F040750,0x00000000 ++#define LPM_MEM_DC_UGDE1_0__FULL 0x1F040750,0xffffffff ++#define LPM_MEM_DC_UGDE1_0__NF_NL_1 0x1F040750,0x18000000 ++#define LPM_MEM_DC_UGDE1_0__AUTORESTART_1 0x1F040750,0x04000000 ++#define LPM_MEM_DC_UGDE1_0__ODD_EN_1 0x1F040750,0x02000000 ++#define LPM_MEM_DC_UGDE1_0__COD_ODD_START_1 0x1F040750,0x00FF0000 ++#define LPM_MEM_DC_UGDE1_0__COD_EV_START_1 0x1F040750,0x00007F80 ++#define LPM_MEM_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1F040750,0x00000078 ++#define LPM_MEM_DC_UGDE1_0__ID_CODED_1 0x1F040750,0x00000007 ++ ++#define LPM_MEM_DC_UGDE1_1__ADDR 0x1F040754 ++#define LPM_MEM_DC_UGDE1_1__EMPTY 0x1F040754,0x00000000 ++#define LPM_MEM_DC_UGDE1_1__FULL 0x1F040754,0xffffffff ++#define LPM_MEM_DC_UGDE1_1__STEP_1 0x1F040754,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_2__ADDR 0x1F040758 ++#define LPM_MEM_DC_UGDE1_2__EMPTY 0x1F040758,0x00000000 ++#define LPM_MEM_DC_UGDE1_2__FULL 0x1F040758,0xffffffff ++#define LPM_MEM_DC_UGDE1_2__OFFSET_DT_1 0x1F040758,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE1_3__ADDR 0x1F04075C ++#define LPM_MEM_DC_UGDE1_3__EMPTY 0x1F04075C,0x00000000 ++#define LPM_MEM_DC_UGDE1_3__FULL 0x1F04075C,0xffffffff ++#define LPM_MEM_DC_UGDE1_3__STEP_REPEAT_1 0x1F04075C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_0__ADDR 0x1F040760 ++#define LPM_MEM_DC_UGDE2_0__EMPTY 0x1F040760,0x00000000 ++#define LPM_MEM_DC_UGDE2_0__FULL 0x1F040760,0xffffffff ++#define LPM_MEM_DC_UGDE2_0__NF_NL_2 0x1F040760,0x18000000 ++#define LPM_MEM_DC_UGDE2_0__AUTORESTART_2 0x1F040760,0x04000000 ++#define LPM_MEM_DC_UGDE2_0__ODD_EN_2 0x1F040760,0x02000000 ++#define LPM_MEM_DC_UGDE2_0__COD_ODD_START_2 0x1F040760,0x00FF0000 ++#define LPM_MEM_DC_UGDE2_0__COD_EV_START_2 0x1F040760,0x00007F80 ++#define LPM_MEM_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1F040760,0x00000078 ++#define LPM_MEM_DC_UGDE2_0__ID_CODED_2 0x1F040760,0x00000007 ++ ++#define LPM_MEM_DC_UGDE2_1__ADDR 0x1F040764 ++#define LPM_MEM_DC_UGDE2_1__EMPTY 0x1F040764,0x00000000 ++#define LPM_MEM_DC_UGDE2_1__FULL 0x1F040764,0xffffffff ++#define LPM_MEM_DC_UGDE2_1__STEP_2 0x1F040764,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_2__ADDR 0x1F040768 ++#define LPM_MEM_DC_UGDE2_2__EMPTY 0x1F040768,0x00000000 ++#define LPM_MEM_DC_UGDE2_2__FULL 0x1F040768,0xffffffff ++#define LPM_MEM_DC_UGDE2_2__OFFSET_DT_2 0x1F040768,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE2_3__ADDR 0x1F04076C ++#define LPM_MEM_DC_UGDE2_3__EMPTY 0x1F04076C,0x00000000 ++#define LPM_MEM_DC_UGDE2_3__FULL 0x1F04076C,0xffffffff ++#define LPM_MEM_DC_UGDE2_3__STEP_REPEAT_2 0x1F04076C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_0__ADDR 0x1F040770 ++#define LPM_MEM_DC_UGDE3_0__EMPTY 0x1F040770,0x00000000 ++#define LPM_MEM_DC_UGDE3_0__FULL 0x1F040770,0xffffffff ++#define LPM_MEM_DC_UGDE3_0__NF_NL_3 0x1F040770,0x18000000 ++#define LPM_MEM_DC_UGDE3_0__AUTORESTART_3 0x1F040770,0x04000000 ++#define LPM_MEM_DC_UGDE3_0__ODD_EN_3 0x1F040770,0x02000000 ++#define LPM_MEM_DC_UGDE3_0__COD_ODD_START_3 0x1F040770,0x00FF0000 ++#define LPM_MEM_DC_UGDE3_0__COD_EV_START_3 0x1F040770,0x00007F80 ++#define LPM_MEM_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1F040770,0x00000078 ++#define LPM_MEM_DC_UGDE3_0__ID_CODED_3 0x1F040770,0x00000007 ++ ++#define LPM_MEM_DC_UGDE3_1__ADDR 0x1F040774 ++#define LPM_MEM_DC_UGDE3_1__EMPTY 0x1F040774,0x00000000 ++#define LPM_MEM_DC_UGDE3_1__FULL 0x1F040774,0xffffffff ++#define LPM_MEM_DC_UGDE3_1__STEP_3 0x1F040774,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_2__ADDR 0x1F040778 ++#define LPM_MEM_DC_UGDE3_2__EMPTY 0x1F040778,0x00000000 ++#define LPM_MEM_DC_UGDE3_2__FULL 0x1F040778,0xffffffff ++#define LPM_MEM_DC_UGDE3_2__OFFSET_DT_3 0x1F040778,0x1FFFFFFF ++ ++#define LPM_MEM_DC_UGDE3_3__ADDR 0x1F04077C ++#define LPM_MEM_DC_UGDE3_3__EMPTY 0x1F04077C,0x00000000 ++#define LPM_MEM_DC_UGDE3_3__FULL 0x1F04077C,0xffffffff ++#define LPM_MEM_DC_UGDE3_3__STEP_REPEAT_3 0x1F04077C,0x1FFFFFFF ++ ++#define LPM_MEM_DC_LLA0__ADDR 0x1F040780 ++#define LPM_MEM_DC_LLA0__EMPTY 0x1F040780,0x00000000 ++#define LPM_MEM_DC_LLA0__FULL 0x1F040780,0xffffffff ++#define LPM_MEM_DC_LLA0__MCU_RS_3_0 0x1F040780,0xFF000000 ++#define LPM_MEM_DC_LLA0__MCU_RS_2_0 0x1F040780,0x00FF0000 ++#define LPM_MEM_DC_LLA0__MCU_RS_1_0 0x1F040780,0x0000FF00 ++#define LPM_MEM_DC_LLA0__MCU_RS_0_0 0x1F040780,0x000000FF ++ ++#define LPM_MEM_DC_LLA1__ADDR 0x1F040784 ++#define LPM_MEM_DC_LLA1__EMPTY 0x1F040784,0x00000000 ++#define LPM_MEM_DC_LLA1__FULL 0x1F040784,0xffffffff ++#define LPM_MEM_DC_LLA1__MCU_RS_3_1 0x1F040784,0xFF000000 ++#define LPM_MEM_DC_LLA1__MCU_RS_2_1 0x1F040784,0x00FF0000 ++#define LPM_MEM_DC_LLA1__MCU_RS_1_1 0x1F040784,0x0000FF00 ++#define LPM_MEM_DC_LLA1__MCU_RS_0_1 0x1F040784,0x000000FF ++ ++#define LPM_MEM_DC_R_LLA0__ADDR 0x1F040788 ++#define LPM_MEM_DC_R_LLA0__EMPTY 0x1F040788,0x00000000 ++#define LPM_MEM_DC_R_LLA0__FULL 0x1F040788,0xffffffff ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_3_0 0x1F040788,0xFF000000 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_2_0 0x1F040788,0x00FF0000 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_1_0 0x1F040788,0x0000FF00 ++#define LPM_MEM_DC_R_LLA0__MCU_RS_R_0_0 0x1F040788,0x000000FF ++ ++#define LPM_MEM_DC_R_LLA1__ADDR 0x1F04078C ++#define LPM_MEM_DC_R_LLA1__EMPTY 0x1F04078C,0x00000000 ++#define LPM_MEM_DC_R_LLA1__FULL 0x1F04078C,0xffffffff ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_3_1 0x1F04078C,0xFF000000 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_2_1 0x1F04078C,0x00FF0000 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_1_1 0x1F04078C,0x0000FF00 ++#define LPM_MEM_DC_R_LLA1__MCU_RS_R_0_1 0x1F04078C,0x000000FF ++ ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ADDR 0x1F040790 ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__EMPTY 0x1F040790,0x00000000 ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__FULL 0x1F040790,0xffffffff ++#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1F040790,0x1FFFFFFF ++ ++#define LPM_MEM_IDMAC_CONF__ADDR 0x1F040794 ++#define LPM_MEM_IDMAC_CONF__EMPTY 0x1F040794,0x00000000 ++#define LPM_MEM_IDMAC_CONF__FULL 0x1F040794,0xffffffff ++#define LPM_MEM_IDMAC_CONF__P_ENDIAN 0x1F040794,0x00010000 ++#define LPM_MEM_IDMAC_CONF__RDI 0x1F040794,0x00000020 ++#define LPM_MEM_IDMAC_CONF__WIDPT 0x1F040794,0x00000018 ++#define LPM_MEM_IDMAC_CONF__MAX_REQ_READ 0x1F040794,0x00000007 ++ ++#define LPM_MEM_IDMAC_CH_EN_1__ADDR 0x1F040798 ++#define LPM_MEM_IDMAC_CH_EN_1__EMPTY 0x1F040798,0x00000000 ++#define LPM_MEM_IDMAC_CH_EN_1__FULL 0x1F040798,0xffffffff ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1F040798,0x80000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1F040798,0x20000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1F040798,0x10000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1F040798,0x08000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1F040798,0x01000000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1F040798,0x00800000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1F040798,0x00400000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1F040798,0x00200000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1F040798,0x00100000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1F040798,0x00040000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1F040798,0x00020000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1F040798,0x00008000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1F040798,0x00004000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1F040798,0x00001000 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1F040798,0x00000800 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_7 0x1F040798,0x00000080 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_6 0x1F040798,0x00000040 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_5 0x1F040798,0x00000020 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_4 0x1F040798,0x00000010 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_3 0x1F040798,0x00000008 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_2 0x1F040798,0x00000004 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_1 0x1F040798,0x00000002 ++#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_0 0x1F040798,0x00000001 ++ ++#define LPM_MEM_IDMAC_CH_EN_2__ADDR 0x1F04079C ++#define LPM_MEM_IDMAC_CH_EN_2__EMPTY 0x1F04079C,0x00000000 ++#define LPM_MEM_IDMAC_CH_EN_2__FULL 0x1F04079C,0xffffffff ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1F04079C,0x00100000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1F04079C,0x00080000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1F04079C,0x00040000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1F04079C,0x00020000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1F04079C,0x00010000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1F04079C,0x00008000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1F04079C,0x00004000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1F04079C,0x00002000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1F04079C,0x00001000 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1F04079C,0x00000800 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1F04079C,0x00000400 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1F04079C,0x00000200 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1F04079C,0x00000100 ++#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1F04079C,0x00000002 ++ ++#define LPM_MEM_IDMAC_SEP_ALPHA__ADDR 0x1F0407A0 ++#define LPM_MEM_IDMAC_SEP_ALPHA__EMPTY 0x1F0407A0,0x00000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__FULL 0x1F0407A0,0xffffffff ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1F0407A0,0x20000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1F0407A0,0x08000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1F0407A0,0x01000000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1F0407A0,0x00800000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1F0407A0,0x00008000 ++#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1F0407A0,0x00004000 ++ ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__ADDR 0x1F0407A4 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__EMPTY 0x1F0407A4,0x00000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__FULL 0x1F0407A4,0xffffffff ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1F0407A4,0x20000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1F0407A4,0x01000000 ++#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1F0407A4,0x00800000 ++ ++#define LPM_MEM_IDMAC_CH_PRI_1__ADDR 0x1F0407A8 ++#define LPM_MEM_IDMAC_CH_PRI_1__EMPTY 0x1F0407A8,0x00000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__FULL 0x1F0407A8,0xffffffff ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1F0407A8,0x20000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1F0407A8,0x10000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1F0407A8,0x08000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1F0407A8,0x01000000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1F0407A8,0x00800000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1F0407A8,0x00400000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1F0407A8,0x00200000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1F0407A8,0x00100000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1F0407A8,0x00008000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1F0407A8,0x00004000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1F0407A8,0x00001000 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1F0407A8,0x00000800 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7 0x1F0407A8,0x00000080 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6 0x1F0407A8,0x00000040 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5 0x1F0407A8,0x00000020 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4 0x1F0407A8,0x00000010 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3 0x1F0407A8,0x00000008 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2 0x1F0407A8,0x00000004 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1 0x1F0407A8,0x00000002 ++#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0 0x1F0407A8,0x00000001 ++ ++#define LPM_MEM_IDMAC_CH_PRI_2__ADDR 0x1F0407AC ++#define LPM_MEM_IDMAC_CH_PRI_2__EMPTY 0x1F0407AC,0x00000000 ++#define LPM_MEM_IDMAC_CH_PRI_2__FULL 0x1F0407AC,0xffffffff ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1F0407AC,0x00040000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1F0407AC,0x00020000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1F0407AC,0x00010000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1F0407AC,0x00008000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1F0407AC,0x00004000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1F0407AC,0x00002000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1F0407AC,0x00001000 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1F0407AC,0x00000800 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1F0407AC,0x00000400 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1F0407AC,0x00000200 ++#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1F0407AC,0x00000100 ++ ++#define LPM_MEM_IDMAC_WM_EN_1__ADDR 0x1F0407B0 ++#define LPM_MEM_IDMAC_WM_EN_1__EMPTY 0x1F0407B0,0x00000000 ++#define LPM_MEM_IDMAC_WM_EN_1__FULL 0x1F0407B0,0xffffffff ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1F0407B0,0x20000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1F0407B0,0x10000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1F0407B0,0x08000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1F0407B0,0x01000000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1F0407B0,0x00800000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1F0407B0,0x00004000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1F0407B0,0x00001000 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_3 0x1F0407B0,0x00000008 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_2 0x1F0407B0,0x00000004 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_1 0x1F0407B0,0x00000002 ++#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_0 0x1F0407B0,0x00000001 ++ ++#define LPM_MEM_IDMAC_WM_EN_2__ADDR 0x1F0407B4 ++#define LPM_MEM_IDMAC_WM_EN_2__EMPTY 0x1F0407B4,0x00000000 ++#define LPM_MEM_IDMAC_WM_EN_2__FULL 0x1F0407B4,0xffffffff ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1F0407B4,0x00001000 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1F0407B4,0x00000800 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1F0407B4,0x00000400 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1F0407B4,0x00000200 ++#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1F0407B4,0x00000100 ++ ++#define LPM_MEM_IDMAC_LOCK_EN_2__ADDR 0x1F0407B8 ++#define LPM_MEM_IDMAC_LOCK_EN_2__EMPTY 0x1F0407B8,0x00000000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__FULL 0x1F0407B8,0xffffffff ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1F0407B8,0x00040000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1F0407B8,0x00020000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1F0407B8,0x00010000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1F0407B8,0x00008000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1F0407B8,0x00004000 ++#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1F0407B8,0x00002000 ++ ++#define LPM_MEM_IDMAC_SUB_ADDR_0__ADDR 0x1F0407BC ++#define LPM_MEM_IDMAC_SUB_ADDR_0__EMPTY 0x1F0407BC,0x00000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_0__FULL 0x1F0407BC,0xffffffff ++#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7 0x1F0407BC,0x7F000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6 0x1F0407BC,0x007F0000 ++#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5 0x1F0407BC,0x00007F00 ++#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4 0x1F0407BC,0x0000007F ++ ++#define LPM_MEM_IDMAC_SUB_ADDR_1__ADDR 0x1F0407C0 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__EMPTY 0x1F0407C0,0x00000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__FULL 0x1F0407C0,0xffffffff ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1F0407C0,0x7F000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1F0407C0,0x007F0000 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1F0407C0,0x00007F00 ++#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1F0407C0,0x0000007F ++ ++#define LPM_MEM_IDMAC_SUB_ADDR_2__ADDR 0x1F0407C4 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__EMPTY 0x1F0407C4,0x00000000 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__FULL 0x1F0407C4,0xffffffff ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1F0407C4,0x007F0000 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1F0407C4,0x00007F00 ++#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1F0407C4,0x0000007F ++ ++#define LPM_MEM_IDMAC_BNDM_EN_1__ADDR 0x1F0407C8 ++#define LPM_MEM_IDMAC_BNDM_EN_1__EMPTY 0x1F0407C8,0x00000000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__FULL 0x1F0407C8,0xffffffff ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1F0407C8,0x00400000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1F0407C8,0x00200000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1F0407C8,0x00100000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1F0407C8,0x00001000 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1F0407C8,0x00000800 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5 0x1F0407C8,0x00000020 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3 0x1F0407C8,0x00000008 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2 0x1F0407C8,0x00000004 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1 0x1F0407C8,0x00000002 ++#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0 0x1F0407C8,0x00000001 ++ ++#define LPM_MEM_IDMAC_BNDM_EN_2__ADDR 0x1F0407CC ++#define LPM_MEM_IDMAC_BNDM_EN_2__EMPTY 0x1F0407CC,0x00000000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__FULL 0x1F0407CC,0xffffffff ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1F0407CC,0x00040000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1F0407CC,0x00020000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1F0407CC,0x00010000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1F0407CC,0x00008000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1F0407CC,0x00004000 ++#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1F0407CC,0x00002000 ++ ++#define LPM_MEM_IDMAC_SC_CORD__ADDR 0x1F0407D0 ++#define LPM_MEM_IDMAC_SC_CORD__EMPTY 0x1F0407D0,0x00000000 ++#define LPM_MEM_IDMAC_SC_CORD__FULL 0x1F0407D0,0xffffffff ++#define LPM_MEM_IDMAC_SC_CORD__SX0 0x1F0407D0,0x0FFF0000 ++#define LPM_MEM_IDMAC_SC_CORD__SY0 0x1F0407D0,0x000007FF ++ ++#define LPM_MEM_IPU_CONF__ADDR 0x1F0407D4 ++#define LPM_MEM_IPU_CONF__EMPTY 0x1F0407D4,0x00000000 ++#define LPM_MEM_IPU_CONF__FULL 0x1F0407D4,0xffffffff ++#define LPM_MEM_IPU_CONF__CSI_SEL 0x1F0407D4,0x80000000 ++#define LPM_MEM_IPU_CONF__IC_INPUT 0x1F0407D4,0x40000000 ++#define LPM_MEM_IPU_CONF__CSI1_DATA_SOURCE 0x1F0407D4,0x20000000 ++#define LPM_MEM_IPU_CONF__CSI0_DATA_SOURCE 0x1F0407D4,0x10000000 ++#define LPM_MEM_IPU_CONF__IC_DMFC_SYNC 0x1F0407D4,0x04000000 ++#define LPM_MEM_IPU_CONF__IC_DMFC_SEL 0x1F0407D4,0x02000000 ++#define LPM_MEM_IPU_CONF__ISP_DOUBLE_FLOW 0x1F0407D4,0x01000000 ++#define LPM_MEM_IPU_CONF__IDMAC_DISABLE 0x1F0407D4,0x00400000 ++#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_ON 0x1F0407D4,0x00200000 ++#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_MODE 0x1F0407D4,0x001F0000 ++#define LPM_MEM_IPU_CONF__IPU_HSP_CLK_EN 0x1F0407D4,0x00008000 ++#define LPM_MEM_IPU_CONF__SISG_EN 0x1F0407D4,0x00000800 ++#define LPM_MEM_IPU_CONF__DMFC_EN 0x1F0407D4,0x00000400 ++#define LPM_MEM_IPU_CONF__DC_EN 0x1F0407D4,0x00000200 ++#define LPM_MEM_IPU_CONF__SMFC_EN 0x1F0407D4,0x00000100 ++#define LPM_MEM_IPU_CONF__DI1_EN 0x1F0407D4,0x00000080 ++#define LPM_MEM_IPU_CONF__DI0_EN 0x1F0407D4,0x00000040 ++#define LPM_MEM_IPU_CONF__DP_EN 0x1F0407D4,0x00000020 ++#define LPM_MEM_IPU_CONF__ISP_EN 0x1F0407D4,0x00000010 ++#define LPM_MEM_IPU_CONF__IRT_EN 0x1F0407D4,0x00000008 ++#define LPM_MEM_IPU_CONF__IC_EN 0x1F0407D4,0x00000004 ++#define LPM_MEM_IPU_CONF__CSI1_EN 0x1F0407D4,0x00000002 ++#define LPM_MEM_IPU_CONF__CSI0_EN 0x1F0407D4,0x00000001 ++ ++#define LPM_MEM_SISG_CTRL0__ADDR 0x1F0407D8 ++#define LPM_MEM_SISG_CTRL0__EMPTY 0x1F0407D8,0x00000000 ++#define LPM_MEM_SISG_CTRL0__FULL 0x1F0407D8,0xffffffff ++#define LPM_MEM_SISG_CTRL0__EXT_ACTV 0x1F0407D8,0x40000000 ++#define LPM_MEM_SISG_CTRL0__MCU_ACTV_TRIG 0x1F0407D8,0x20000000 ++#define LPM_MEM_SISG_CTRL0__VAL_STOP_SISG_COUNTER 0x1F0407D8,0x1FFFFFF0 ++#define LPM_MEM_SISG_CTRL0__NO_OF_VSYNC 0x1F0407D8,0x0000000E ++#define LPM_MEM_SISG_CTRL0__VSYNC_RESET_COUNTER 0x1F0407D8,0x00000001 ++ ++#define LPM_MEM_SISG_CTRL1__ADDR 0x1F0407DC ++#define LPM_MEM_SISG_CTRL1__EMPTY 0x1F0407DC,0x00000000 ++#define LPM_MEM_SISG_CTRL1__FULL 0x1F0407DC,0xffffffff ++#define LPM_MEM_SISG_CTRL1__SISG_OUT_POL 0x1F0407DC,0x00003F00 ++#define LPM_MEM_SISG_CTRL1__SISG_STROBE_CNT 0x1F0407DC,0x0000001F ++ ++#define LPM_MEM_SISG_SET_1__ADDR 0x1F0407E0 ++#define LPM_MEM_SISG_SET_1__EMPTY 0x1F0407E0,0x00000000 ++#define LPM_MEM_SISG_SET_1__FULL 0x1F0407E0,0xffffffff ++#define LPM_MEM_SISG_SET_1__SISG_SET_1 0x1F0407E0,0x01FFFFFF ++ ++#define LPM_MEM_SISG_SET_2__ADDR 0x1F0407E4 ++#define LPM_MEM_SISG_SET_2__EMPTY 0x1F0407E4,0x00000000 ++#define LPM_MEM_SISG_SET_2__FULL 0x1F0407E4,0xffffffff ++#define LPM_MEM_SISG_SET_2__SISG_SET_2 0x1F0407E4,0x01FFFFFF ++ ++#define LPM_MEM_SISG_SET_3__ADDR 0x1F0407E8 ++#define LPM_MEM_SISG_SET_3__EMPTY 0x1F0407E8,0x00000000 ++#define LPM_MEM_SISG_SET_3__FULL 0x1F0407E8,0xffffffff ++#define LPM_MEM_SISG_SET_3__SISG_SET_3 0x1F0407E8,0x01FFFFFF ++ ++#define LPM_MEM_SISG_SET_4__ADDR 0x1F0407EC ++#define LPM_MEM_SISG_SET_4__EMPTY 0x1F0407EC,0x00000000 ++#define LPM_MEM_SISG_SET_4__FULL 0x1F0407EC,0xffffffff ++#define LPM_MEM_SISG_SET_4__SISG_SET_4 0x1F0407EC,0x01FFFFFF ++ ++#define LPM_MEM_SISG_SET_5__ADDR 0x1F0407F0 ++#define LPM_MEM_SISG_SET_5__EMPTY 0x1F0407F0,0x00000000 ++#define LPM_MEM_SISG_SET_5__FULL 0x1F0407F0,0xffffffff ++#define LPM_MEM_SISG_SET_5__SISG_SET_5 0x1F0407F0,0x01FFFFFF ++ ++#define LPM_MEM_SISG_SET_6__ADDR 0x1F0407F4 ++#define LPM_MEM_SISG_SET_6__EMPTY 0x1F0407F4,0x00000000 ++#define LPM_MEM_SISG_SET_6__FULL 0x1F0407F4,0xffffffff ++#define LPM_MEM_SISG_SET_6__SISG_SET_6 0x1F0407F4,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_1__ADDR 0x1F0407F8 ++#define LPM_MEM_SISG_CLR_1__EMPTY 0x1F0407F8,0x00000000 ++#define LPM_MEM_SISG_CLR_1__FULL 0x1F0407F8,0xffffffff ++#define LPM_MEM_SISG_CLR_1__SISG_CLEAR_1 0x1F0407F8,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_2__ADDR 0x1F0407FC ++#define LPM_MEM_SISG_CLR_2__EMPTY 0x1F0407FC,0x00000000 ++#define LPM_MEM_SISG_CLR_2__FULL 0x1F0407FC,0xffffffff ++#define LPM_MEM_SISG_CLR_2__SISG_CLEAR_2 0x1F0407FC,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_3__ADDR 0x1F040800 ++#define LPM_MEM_SISG_CLR_3__EMPTY 0x1F040800,0x00000000 ++#define LPM_MEM_SISG_CLR_3__FULL 0x1F040800,0xffffffff ++#define LPM_MEM_SISG_CLR_3__SISG_CLEAR_3 0x1F040800,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_4__ADDR 0x1F040804 ++#define LPM_MEM_SISG_CLR_4__EMPTY 0x1F040804,0x00000000 ++#define LPM_MEM_SISG_CLR_4__FULL 0x1F040804,0xffffffff ++#define LPM_MEM_SISG_CLR_4__SISG_CLEAR_4 0x1F040804,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_5__ADDR 0x1F040808 ++#define LPM_MEM_SISG_CLR_5__EMPTY 0x1F040808,0x00000000 ++#define LPM_MEM_SISG_CLR_5__FULL 0x1F040808,0xffffffff ++#define LPM_MEM_SISG_CLR_5__SISG_CLEAR_5 0x1F040808,0x01FFFFFF ++ ++#define LPM_MEM_SISG_CLR_6__ADDR 0x1F04080C ++#define LPM_MEM_SISG_CLR_6__EMPTY 0x1F04080C,0x00000000 ++#define LPM_MEM_SISG_CLR_6__FULL 0x1F04080C,0xffffffff ++#define LPM_MEM_SISG_CLR_6__SISG_CLEAR_6 0x1F04080C,0x01FFFFFF ++ ++#define LPM_MEM_IPU_INT_CTRL_1__ADDR 0x1F040810 ++#define LPM_MEM_IPU_INT_CTRL_1__EMPTY 0x1F040810,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_1__FULL 0x1F040810,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1F040810,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1F040810,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1F040810,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1F040810,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1F040810,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1F040810,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1F040810,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1F040810,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1F040810,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1F040810,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1F040810,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1F040810,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1F040810,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1F040810,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1F040810,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_7 0x1F040810,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_6 0x1F040810,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_5 0x1F040810,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_4 0x1F040810,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_3 0x1F040810,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_2 0x1F040810,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_1 0x1F040810,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_0 0x1F040810,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_2__ADDR 0x1F040814 ++#define LPM_MEM_IPU_INT_CTRL_2__EMPTY 0x1F040814,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_2__FULL 0x1F040814,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1F040814,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1F040814,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1F040814,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1F040814,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1F040814,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1F040814,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1F040814,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1F040814,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1F040814,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1F040814,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1F040814,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1F040814,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1F040814,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1F040814,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_3__ADDR 0x1F040818 ++#define LPM_MEM_IPU_INT_CTRL_3__EMPTY 0x1F040818,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_3__FULL 0x1F040818,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1F040818,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1F040818,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1F040818,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1F040818,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1F040818,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1F040818,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1F040818,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1F040818,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1F040818,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1F040818,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1F040818,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1F040818,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1F040818,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1F040818,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1F040818,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7 0x1F040818,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6 0x1F040818,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5 0x1F040818,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4 0x1F040818,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3 0x1F040818,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2 0x1F040818,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1 0x1F040818,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0 0x1F040818,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_4__ADDR 0x1F04081C ++#define LPM_MEM_IPU_INT_CTRL_4__EMPTY 0x1F04081C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_4__FULL 0x1F04081C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1F04081C,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1F04081C,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1F04081C,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1F04081C,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1F04081C,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1F04081C,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1F04081C,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1F04081C,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1F04081C,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1F04081C,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1F04081C,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1F04081C,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1F04081C,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1F04081C,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_5__ADDR 0x1F040820 ++#define LPM_MEM_IPU_INT_CTRL_5__EMPTY 0x1F040820,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_5__FULL 0x1F040820,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1F040820,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1F040820,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1F040820,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1F040820,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1F040820,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1F040820,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1F040820,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1F040820,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1F040820,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1F040820,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1F040820,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1F040820,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1F040820,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1F040820,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1F040820,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7 0x1F040820,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6 0x1F040820,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5 0x1F040820,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4 0x1F040820,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3 0x1F040820,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2 0x1F040820,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1 0x1F040820,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0 0x1F040820,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_6__ADDR 0x1F040824 ++#define LPM_MEM_IPU_INT_CTRL_6__EMPTY 0x1F040824,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_6__FULL 0x1F040824,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1F040824,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1F040824,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1F040824,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1F040824,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1F040824,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1F040824,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1F040824,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1F040824,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1F040824,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1F040824,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1F040824,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1F040824,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1F040824,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1F040824,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_7__ADDR 0x1F040828 ++#define LPM_MEM_IPU_INT_CTRL_7__EMPTY 0x1F040828,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_7__FULL 0x1F040828,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1F040828,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1F040828,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1F040828,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1F040828,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1F040828,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1F040828,0x00800000 ++ ++#define LPM_MEM_IPU_INT_CTRL_8__ADDR 0x1F04082C ++#define LPM_MEM_IPU_INT_CTRL_8__EMPTY 0x1F04082C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_8__FULL 0x1F04082C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1F04082C,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1F04082C,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1F04082C,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1F04082C,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1F04082C,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1F04082C,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1F04082C,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_9__ADDR 0x1F040830 ++#define LPM_MEM_IPU_INT_CTRL_9__EMPTY 0x1F040830,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_9__FULL 0x1F040830,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_9__CSI1_PUPE_EN 0x1F040830,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_9__CSI0_PUPE_EN 0x1F040830,0x40000000 ++#define LPM_MEM_IPU_INT_CTRL_9__ISP_PUPE_EN 0x1F040830,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN 0x1F040830,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN 0x1F040830,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN 0x1F040830,0x04000000 ++ ++#define LPM_MEM_IPU_INT_CTRL_10__ADDR 0x1F040834 ++#define LPM_MEM_IPU_INT_CTRL_10__EMPTY 0x1F040834,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_10__FULL 0x1F040834,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_10__AXIR_ERR_EN 0x1F040834,0x40000000 ++#define LPM_MEM_IPU_INT_CTRL_10__AXIW_ERR_EN 0x1F040834,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1F040834,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN 0x1F040834,0x04000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN 0x1F040834,0x02000000 ++#define LPM_MEM_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN 0x1F040834,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN 0x1F040834,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN 0x1F040834,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN 0x1F040834,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN 0x1F040834,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN 0x1F040834,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN 0x1F040834,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN 0x1F040834,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN 0x1F040834,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN 0x1F040834,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN 0x1F040834,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN 0x1F040834,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN 0x1F040834,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN 0x1F040834,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_11__ADDR 0x1F040838 ++#define LPM_MEM_IPU_INT_CTRL_11__EMPTY 0x1F040838,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_11__FULL 0x1F040838,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1F040838,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1F040838,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1F040838,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1F040838,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1F040838,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5 0x1F040838,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3 0x1F040838,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2 0x1F040838,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1 0x1F040838,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0 0x1F040838,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_12__ADDR 0x1F04083C ++#define LPM_MEM_IPU_INT_CTRL_12__EMPTY 0x1F04083C,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_12__FULL 0x1F04083C,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1F04083C,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1F04083C,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1F04083C,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1F04083C,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1F04083C,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1F04083C,0x00002000 ++ ++#define LPM_MEM_IPU_INT_CTRL_13__ADDR 0x1F040840 ++#define LPM_MEM_IPU_INT_CTRL_13__EMPTY 0x1F040840,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_13__FULL 0x1F040840,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1F040840,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1F040840,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1F040840,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1F040840,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1F040840,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1F040840,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1F040840,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1F040840,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1F040840,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1F040840,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1F040840,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1F040840,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1F040840,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1F040840,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1F040840,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_7 0x1F040840,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_6 0x1F040840,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_5 0x1F040840,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_4 0x1F040840,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_3 0x1F040840,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_2 0x1F040840,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_1 0x1F040840,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_0 0x1F040840,0x00000001 ++ ++#define LPM_MEM_IPU_INT_CTRL_14__ADDR 0x1F040844 ++#define LPM_MEM_IPU_INT_CTRL_14__EMPTY 0x1F040844,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_14__FULL 0x1F040844,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1F040844,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1F040844,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1F040844,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1F040844,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1F040844,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1F040844,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1F040844,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1F040844,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1F040844,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1F040844,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1F040844,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1F040844,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1F040844,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1F040844,0x00000002 ++ ++#define LPM_MEM_IPU_INT_CTRL_15__ADDR 0x1F040848 ++#define LPM_MEM_IPU_INT_CTRL_15__EMPTY 0x1F040848,0x00000000 ++#define LPM_MEM_IPU_INT_CTRL_15__FULL 0x1F040848,0xffffffff ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN 0x1F040848,0x80000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN 0x1F040848,0x40000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1F040848,0x20000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN 0x1F040848,0x10000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN 0x1F040848,0x08000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN 0x1F040848,0x04000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN 0x1F040848,0x02000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN 0x1F040848,0x01000000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN 0x1F040848,0x00800000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN 0x1F040848,0x00400000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN 0x1F040848,0x00200000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN 0x1F040848,0x00100000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN 0x1F040848,0x00080000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1F040848,0x00040000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN 0x1F040848,0x00020000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_DP_START_EN 0x1F040848,0x00010000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN 0x1F040848,0x00008000 ++#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN 0x1F040848,0x00004000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_6_EN 0x1F040848,0x00002000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_4_EN 0x1F040848,0x00001000 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_3_EN 0x1F040848,0x00000800 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_2_EN 0x1F040848,0x00000400 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_1_EN 0x1F040848,0x00000200 ++#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_0_EN 0x1F040848,0x00000100 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN 0x1F040848,0x00000080 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_BRAKE_EN 0x1F040848,0x00000040 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_END_EN 0x1F040848,0x00000020 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_START_EN 0x1F040848,0x00000010 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_END_EN 0x1F040848,0x00000008 ++#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_START_EN 0x1F040848,0x00000004 ++#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN 0x1F040848,0x00000002 ++#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN 0x1F040848,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_1__ADDR 0x1F04084C ++#define LPM_MEM_IPU_SDMA_EVENT_1__EMPTY 0x1F04084C,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__FULL 0x1F04084C,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1F04084C,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1F04084C,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1F04084C,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1F04084C,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1F04084C,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1F04084C,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1F04084C,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1F04084C,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1F04084C,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1F04084C,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1F04084C,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1F04084C,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1F04084C,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1F04084C,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1F04084C,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7 0x1F04084C,0x00000080 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6 0x1F04084C,0x00000040 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5 0x1F04084C,0x00000020 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4 0x1F04084C,0x00000010 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3 0x1F04084C,0x00000008 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2 0x1F04084C,0x00000004 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1 0x1F04084C,0x00000002 ++#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0 0x1F04084C,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_2__ADDR 0x1F040850 ++#define LPM_MEM_IPU_SDMA_EVENT_2__EMPTY 0x1F040850,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__FULL 0x1F040850,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1F040850,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1F040850,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1F040850,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1F040850,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1F040850,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1F040850,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1F040850,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1F040850,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1F040850,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1F040850,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1F040850,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1F040850,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1F040850,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1F040850,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_3__ADDR 0x1F040854 ++#define LPM_MEM_IPU_SDMA_EVENT_3__EMPTY 0x1F040854,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__FULL 0x1F040854,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1F040854,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1F040854,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1F040854,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1F040854,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1F040854,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1F040854,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1F040854,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1F040854,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1F040854,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1F040854,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1F040854,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1F040854,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1F040854,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1F040854,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1F040854,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7 0x1F040854,0x00000080 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6 0x1F040854,0x00000040 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5 0x1F040854,0x00000020 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4 0x1F040854,0x00000010 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3 0x1F040854,0x00000008 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2 0x1F040854,0x00000004 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1 0x1F040854,0x00000002 ++#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0 0x1F040854,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_4__ADDR 0x1F040858 ++#define LPM_MEM_IPU_SDMA_EVENT_4__EMPTY 0x1F040858,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__FULL 0x1F040858,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1F040858,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1F040858,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1F040858,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1F040858,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1F040858,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1F040858,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1F040858,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1F040858,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1F040858,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1F040858,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1F040858,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1F040858,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1F040858,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1F040858,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_7__ADDR 0x1F04085C ++#define LPM_MEM_IPU_SDMA_EVENT_7__EMPTY 0x1F04085C,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__FULL 0x1F04085C,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1F04085C,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1F04085C,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1F04085C,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1F04085C,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1F04085C,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1F04085C,0x00800000 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_8__ADDR 0x1F040860 ++#define LPM_MEM_IPU_SDMA_EVENT_8__EMPTY 0x1F040860,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__FULL 0x1F040860,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1F040860,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1F040860,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1F040860,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1F040860,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1F040860,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1F040860,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1F040860,0x00000002 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_11__ADDR 0x1F040864 ++#define LPM_MEM_IPU_SDMA_EVENT_11__EMPTY 0x1F040864,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__FULL 0x1F040864,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1F040864,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1F040864,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1F040864,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1F040864,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1F040864,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5 0x1F040864,0x00000020 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3 0x1F040864,0x00000008 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2 0x1F040864,0x00000004 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1 0x1F040864,0x00000002 ++#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0 0x1F040864,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_12__ADDR 0x1F040868 ++#define LPM_MEM_IPU_SDMA_EVENT_12__EMPTY 0x1F040868,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__FULL 0x1F040868,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1F040868,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1F040868,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1F040868,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1F040868,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1F040868,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1F040868,0x00002000 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_13__ADDR 0x1F04086C ++#define LPM_MEM_IPU_SDMA_EVENT_13__EMPTY 0x1F04086C,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__FULL 0x1F04086C,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1F04086C,0x80000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1F04086C,0x20000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1F04086C,0x10000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1F04086C,0x08000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1F04086C,0x01000000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1F04086C,0x00800000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1F04086C,0x00400000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1F04086C,0x00200000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1F04086C,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1F04086C,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1F04086C,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1F04086C,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1F04086C,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1F04086C,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1F04086C,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7 0x1F04086C,0x00000080 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6 0x1F04086C,0x00000040 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5 0x1F04086C,0x00000020 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4 0x1F04086C,0x00000010 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3 0x1F04086C,0x00000008 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2 0x1F04086C,0x00000004 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1 0x1F04086C,0x00000002 ++#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0 0x1F04086C,0x00000001 ++ ++#define LPM_MEM_IPU_SDMA_EVENT_14__ADDR 0x1F040870 ++#define LPM_MEM_IPU_SDMA_EVENT_14__EMPTY 0x1F040870,0x00000000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__FULL 0x1F040870,0xffffffff ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1F040870,0x00100000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1F040870,0x00080000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1F040870,0x00040000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1F040870,0x00020000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1F040870,0x00010000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1F040870,0x00008000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1F040870,0x00004000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1F040870,0x00002000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1F040870,0x00001000 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1F040870,0x00000800 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1F040870,0x00000400 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1F040870,0x00000200 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1F040870,0x00000100 ++#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1F040870,0x00000002 ++ ++#define LPM_MEM_IPU_SRM_PRI1__ADDR 0x1F000874 ++#define LPM_MEM_IPU_SRM_PRI1__EMPTY 0x1F000874,0x00000000 ++#define LPM_MEM_IPU_SRM_PRI1__FULL 0x1F000874,0xffffffff ++#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_MODE 0x1F000874,0x00180000 ++#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_PRI 0x1F000874,0x00070000 ++#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_MODE 0x1F000874,0x00001800 ++#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_PRI 0x1F000874,0x00000700 ++#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_MODE 0x1F000874,0x00000018 ++#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_PRI 0x1F000874,0x00000007 ++ ++#define LPM_MEM_IPU_SRM_PRI2__ADDR 0x1F000878 ++#define LPM_MEM_IPU_SRM_PRI2__EMPTY 0x1F000878,0x00000000 ++#define LPM_MEM_IPU_SRM_PRI2__FULL 0x1F000878,0xffffffff ++#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_MODE 0x1F000878,0x18000000 ++#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_PRI 0x1F000878,0x07000000 ++#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_MODE 0x1F000878,0x00180000 ++#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_PRI 0x1F000878,0x00070000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_6_SRM_MODE 0x1F000878,0x0000C000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_2_SRM_MODE 0x1F000878,0x00003000 ++#define LPM_MEM_IPU_SRM_PRI2__DC_SRM_PRI 0x1F000878,0x00000E00 ++#define LPM_MEM_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1F000878,0x00000180 ++#define LPM_MEM_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1F000878,0x00000060 ++#define LPM_MEM_IPU_SRM_PRI2__DP_S_SRM_MODE 0x1F000878,0x00000018 ++#define LPM_MEM_IPU_SRM_PRI2__DP_SRM_PRI 0x1F000878,0x00000007 ++ ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ADDR 0x1F04087C ++#define LPM_MEM_IPU_FS_PROC_FLOW1__EMPTY 0x1F04087C,0x00000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__FULL 0x1F04087C,0xffffffff ++#define LPM_MEM_IPU_FS_PROC_FLOW1__VF_IN_VALID 0x1F04087C,0x80000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ENC_IN_VALID 0x1F04087C,0x40000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRP_SRC_SEL 0x1F04087C,0x0F000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ISP_SRC_SEL 0x1F04087C,0x00F00000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL 0x1F04087C,0x000F0000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_SRC_SEL 0x1F04087C,0x0000F000 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL 0x1F04087C,0x00000F00 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL 0x1F04087C,0x000000F0 ++#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1F04087C,0x0000000F ++ ++#define LPM_MEM_IPU_FS_PROC_FLOW2__ADDR 0x1F040880 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__EMPTY 0x1F040880,0x00000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__FULL 0x1F040880,0xffffffff ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL 0x1F040880,0xF0000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_DEST_SEL 0x1F040880,0x0F000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1F040880,0x00F00000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL 0x1F040880,0x000F0000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_DEST_SEL 0x1F040880,0x0000F000 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL 0x1F040880,0x00000F00 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL 0x1F040880,0x000000F0 ++#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL 0x1F040880,0x0000000F ++ ++#define LPM_MEM_IPU_FS_PROC_FLOW3__ADDR 0x1F040884 ++#define LPM_MEM_IPU_FS_PROC_FLOW3__EMPTY 0x1F040884,0x00000000 ++#define LPM_MEM_IPU_FS_PROC_FLOW3__FULL 0x1F040884,0xffffffff ++#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL 0x1F040884,0x00003800 ++#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL 0x1F040884,0x00000780 ++#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL 0x1F040884,0x00000070 ++#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL 0x1F040884,0x0000000F ++ ++#define LPM_MEM_IPU_FS_DISP_FLOW1__ADDR 0x1F040888 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__EMPTY 0x1F040888,0x00000000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__FULL 0x1F040888,0xffffffff ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DC1_SRC_SEL 0x1F040888,0x00F00000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DC2_SRC_SEL 0x1F040888,0x000F0000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1F040888,0x0000F000 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1F040888,0x00000F00 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL 0x1F040888,0x000000F0 ++#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL 0x1F040888,0x0000000F ++ ++#define LPM_MEM_IPU_FS_DISP_FLOW2__ADDR 0x1F04088C ++#define LPM_MEM_IPU_FS_DISP_FLOW2__EMPTY 0x1F04088C,0x00000000 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__FULL 0x1F04088C,0xffffffff ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL 0x1F04088C,0x000F0000 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1F04088C,0x000000F0 ++#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1F04088C,0x0000000F ++ ++#define LPM_MEM_IPU_SKIP__ADDR 0x1F040890 ++#define LPM_MEM_IPU_SKIP__EMPTY 0x1F040890,0x00000000 ++#define LPM_MEM_IPU_SKIP__FULL 0x1F040890,0xffffffff ++#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_VF 0x1F040890,0x0000F800 ++#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF 0x1F040890,0x00000700 ++#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_ENC 0x1F040890,0x000000F8 ++#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC 0x1F040890,0x00000007 ++ ++#define LPM_MEM_IPU_DISP_ALT_CONF__ADDR 0x1F040894 ++#define LPM_MEM_IPU_DISP_ALT_CONF__EMPTY 0x1F040894,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT_CONF__FULL 0x1F040894,0xffffffff ++ ++#define LPM_MEM_IPU_DISP_GEN__ADDR 0x1F040898 ++#define LPM_MEM_IPU_DISP_GEN__EMPTY 0x1F040898,0x00000000 ++#define LPM_MEM_IPU_DISP_GEN__FULL 0x1F040898,0xffffffff ++#define LPM_MEM_IPU_DISP_GEN__DI1_COUNTER_RELEASE 0x1F040898,0x02000000 ++#define LPM_MEM_IPU_DISP_GEN__DI0_COUNTER_RELEASE 0x1F040898,0x01000000 ++#define LPM_MEM_IPU_DISP_GEN__CSI_VSYNC_DEST 0x1F040898,0x00800000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_MAX_BURST_STOP 0x1F040898,0x00400000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_T 0x1F040898,0x003C0000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_9 0x1F040898,0x00020000 ++#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_8 0x1F040898,0x00010000 ++#define LPM_MEM_IPU_DISP_GEN__DP_PIPE_CLR 0x1F040898,0x00000040 ++#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC1 0x1F040898,0x00000020 ++#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC0 0x1F040898,0x00000010 ++#define LPM_MEM_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1F040898,0x00000008 ++#define LPM_MEM_IPU_DISP_GEN__DC2_DOUBLE_FLOW 0x1F040898,0x00000004 ++#define LPM_MEM_IPU_DISP_GEN__DI1_DUAL_MODE 0x1F040898,0x00000002 ++#define LPM_MEM_IPU_DISP_GEN__DI0_DUAL_MODE 0x1F040898,0x00000001 ++ ++#define LPM_MEM_IPU_DISP_ALT1__ADDR 0x1F04089C ++#define LPM_MEM_IPU_DISP_ALT1__EMPTY 0x1F04089C,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT1__FULL 0x1F04089C,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT1__SEL_ALT_0 0x1F04089C,0xF0000000 ++#define LPM_MEM_IPU_DISP_ALT1__STEP_REPEAT_ALT_0 0x1F04089C,0x0FFF0000 ++#define LPM_MEM_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1F04089C,0x00008000 ++#define LPM_MEM_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0 0x1F04089C,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0 0x1F04089C,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT2__ADDR 0x1F0408A0 ++#define LPM_MEM_IPU_DISP_ALT2__EMPTY 0x1F0408A0,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT2__FULL 0x1F0408A0,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0 0x1F0408A0,0x00070000 ++#define LPM_MEM_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1F0408A0,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0 0x1F0408A0,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT3__ADDR 0x1F0408A4 ++#define LPM_MEM_IPU_DISP_ALT3__EMPTY 0x1F0408A4,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT3__FULL 0x1F0408A4,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT3__SEL_ALT_1 0x1F0408A4,0xF0000000 ++#define LPM_MEM_IPU_DISP_ALT3__STEP_REPEAT_ALT_1 0x1F0408A4,0x0FFF0000 ++#define LPM_MEM_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1F0408A4,0x00008000 ++#define LPM_MEM_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1 0x1F0408A4,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1 0x1F0408A4,0x00000FFF ++ ++#define LPM_MEM_IPU_DISP_ALT4__ADDR 0x1F0408A8 ++#define LPM_MEM_IPU_DISP_ALT4__EMPTY 0x1F0408A8,0x00000000 ++#define LPM_MEM_IPU_DISP_ALT4__FULL 0x1F0408A8,0xffffffff ++#define LPM_MEM_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1 0x1F0408A8,0x00070000 ++#define LPM_MEM_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1F0408A8,0x00007000 ++#define LPM_MEM_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1 0x1F0408A8,0x00000FFF ++ ++#define LPM_MEM_IPU_SNOOP__ADDR 0x1F0408AC ++#define LPM_MEM_IPU_SNOOP__EMPTY 0x1F0408AC,0x00000000 ++#define LPM_MEM_IPU_SNOOP__FULL 0x1F0408AC,0xffffffff ++#define LPM_MEM_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1F0408AC,0x00010000 ++#define LPM_MEM_IPU_SNOOP__AUTOREF_PER 0x1F0408AC,0x000003FF ++ ++#define LPM_MEM_IPU_MEM_RST__ADDR 0x1F0408B0 ++#define LPM_MEM_IPU_MEM_RST__EMPTY 0x1F0408B0,0x00000000 ++#define LPM_MEM_IPU_MEM_RST__FULL 0x1F0408B0,0xffffffff ++#define LPM_MEM_IPU_MEM_RST__RST_MEM_START 0x1F0408B0,0x80000000 ++#define LPM_MEM_IPU_MEM_RST__RST_MEM_EN 0x1F0408B0,0x007FFFFF ++ ++#define LPM_MEM_IPU_PM__ADDR 0x1F0408B4 ++#define LPM_MEM_IPU_PM__EMPTY 0x1F0408B4,0x00000000 ++#define LPM_MEM_IPU_PM__FULL 0x1F0408B4,0xffffffff ++#define LPM_MEM_IPU_PM__LPSR_MODE 0x1F0408B4,0x80000000 ++#define LPM_MEM_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1F0408B4,0x40000000 ++#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_1 0x1F0408B4,0x3F800000 ++#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_0 0x1F0408B4,0x007F0000 ++#define LPM_MEM_IPU_PM__CLOCK_MODE_STAT 0x1F0408B4,0x00008000 ++#define LPM_MEM_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1F0408B4,0x00004000 ++#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_1 0x1F0408B4,0x00003F80 ++#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_0 0x1F0408B4,0x0000007F ++ ++#define LPM_MEM_IPU_GPR__ADDR 0x1F0408B8 ++#define LPM_MEM_IPU_GPR__EMPTY 0x1F0408B8,0x00000000 ++#define LPM_MEM_IPU_GPR__FULL 0x1F0408B8,0xffffffff ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY1_CLR 0x1F0408B8,0x80000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY0_CLR 0x1F0408B8,0x40000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY1_CLR 0x1F0408B8,0x20000000 ++#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY0_CLR 0x1F0408B8,0x10000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1F0408B8,0x08000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1F0408B8,0x04000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1F0408B8,0x02000000 ++#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1F0408B8,0x01000000 ++#define LPM_MEM_IPU_GPR__IPU_GP23 0x1F0408B8,0x00800000 ++#define LPM_MEM_IPU_GPR__IPU_GP22 0x1F0408B8,0x00400000 ++#define LPM_MEM_IPU_GPR__IPU_GP21 0x1F0408B8,0x00200000 ++#define LPM_MEM_IPU_GPR__IPU_GP20 0x1F0408B8,0x00100000 ++#define LPM_MEM_IPU_GPR__IPU_GP19 0x1F0408B8,0x00080000 ++#define LPM_MEM_IPU_GPR__IPU_GP18 0x1F0408B8,0x00040000 ++#define LPM_MEM_IPU_GPR__IPU_GP17 0x1F0408B8,0x00020000 ++#define LPM_MEM_IPU_GPR__IPU_GP16 0x1F0408B8,0x00010000 ++#define LPM_MEM_IPU_GPR__IPU_GP15 0x1F0408B8,0x00008000 ++#define LPM_MEM_IPU_GPR__IPU_GP14 0x1F0408B8,0x00004000 ++#define LPM_MEM_IPU_GPR__IPU_GP13 0x1F0408B8,0x00002000 ++#define LPM_MEM_IPU_GPR__IPU_GP12 0x1F0408B8,0x00001000 ++#define LPM_MEM_IPU_GPR__IPU_GP11 0x1F0408B8,0x00000800 ++#define LPM_MEM_IPU_GPR__IPU_GP10 0x1F0408B8,0x00000400 ++#define LPM_MEM_IPU_GPR__IPU_GP9 0x1F0408B8,0x00000200 ++#define LPM_MEM_IPU_GPR__IPU_GP8 0x1F0408B8,0x00000100 ++#define LPM_MEM_IPU_GPR__IPU_GP7 0x1F0408B8,0x00000080 ++#define LPM_MEM_IPU_GPR__IPU_GP6 0x1F0408B8,0x00000040 ++#define LPM_MEM_IPU_GPR__IPU_GP5 0x1F0408B8,0x00000020 ++#define LPM_MEM_IPU_GPR__IPU_GP4 0x1F0408B8,0x00000010 ++#define LPM_MEM_IPU_GPR__IPU_GP3 0x1F0408B8,0x00000008 ++#define LPM_MEM_IPU_GPR__IPU_GP2 0x1F0408B8,0x00000004 ++#define LPM_MEM_IPU_GPR__IPU_GP1 0x1F0408B8,0x00000002 ++#define LPM_MEM_IPU_GPR__IPU_GP0 0x1F0408B8,0x00000001 ++ ++#define LPM_MEM_IC_CONF__ADDR 0x1F0408BC ++#define LPM_MEM_IC_CONF__EMPTY 0x1F0408BC,0x00000000 ++#define LPM_MEM_IC_CONF__FULL 0x1F0408BC,0xffffffff ++#define LPM_MEM_IC_CONF__CSI_MEM_WR_EN 0x1F0408BC,0x80000000 ++#define LPM_MEM_IC_CONF__RWS_EN 0x1F0408BC,0x40000000 ++#define LPM_MEM_IC_CONF__IC_KEY_COLOR_EN 0x1F0408BC,0x20000000 ++#define LPM_MEM_IC_CONF__IC_GLB_LOC_A 0x1F0408BC,0x10000000 ++#define LPM_MEM_IC_CONF__PP_ROT_EN 0x1F0408BC,0x00100000 ++#define LPM_MEM_IC_CONF__PP_CMB 0x1F0408BC,0x00080000 ++#define LPM_MEM_IC_CONF__PP_CSC2 0x1F0408BC,0x00040000 ++#define LPM_MEM_IC_CONF__PP_CSC1 0x1F0408BC,0x00020000 ++#define LPM_MEM_IC_CONF__PP_EN 0x1F0408BC,0x00010000 ++#define LPM_MEM_IC_CONF__PRPVF_ROT_EN 0x1F0408BC,0x00001000 ++#define LPM_MEM_IC_CONF__PRPVF_CMB 0x1F0408BC,0x00000800 ++#define LPM_MEM_IC_CONF__PRPVF_CSC2 0x1F0408BC,0x00000400 ++#define LPM_MEM_IC_CONF__PRPVF_CSC1 0x1F0408BC,0x00000200 ++#define LPM_MEM_IC_CONF__PRPVF_EN 0x1F0408BC,0x00000100 ++#define LPM_MEM_IC_CONF__PRPENC_ROT_EN 0x1F0408BC,0x00000004 ++#define LPM_MEM_IC_CONF__PRPENC_CSC1 0x1F0408BC,0x00000002 ++#define LPM_MEM_IC_CONF__PRPENC_EN 0x1F0408BC,0x00000001 ++ ++#define LPM_MEM_IC_PRP_ENC_RSC__ADDR 0x1F0408C0 ++#define LPM_MEM_IC_PRP_ENC_RSC__EMPTY 0x1F0408C0,0x00000000 ++#define LPM_MEM_IC_PRP_ENC_RSC__FULL 0x1F0408C0,0xffffffff ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1F0408C0,0xC0000000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1F0408C0,0x3FFF0000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1F0408C0,0x0000C000 ++#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1F0408C0,0x00003FFF ++ ++#define LPM_MEM_IC_PRP_VF_RSC__ADDR 0x1F0408C4 ++#define LPM_MEM_IC_PRP_VF_RSC__EMPTY 0x1F0408C4,0x00000000 ++#define LPM_MEM_IC_PRP_VF_RSC__FULL 0x1F0408C4,0xffffffff ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1F0408C4,0xC0000000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1F0408C4,0x3FFF0000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1F0408C4,0x0000C000 ++#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1F0408C4,0x00003FFF ++ ++#define LPM_MEM_IC_PP_RSC__ADDR 0x1F0408C8 ++#define LPM_MEM_IC_PP_RSC__EMPTY 0x1F0408C8,0x00000000 ++#define LPM_MEM_IC_PP_RSC__FULL 0x1F0408C8,0xffffffff ++#define LPM_MEM_IC_PP_RSC__PP_DS_R_V 0x1F0408C8,0xC0000000 ++#define LPM_MEM_IC_PP_RSC__PP_RS_R_V 0x1F0408C8,0x3FFF0000 ++#define LPM_MEM_IC_PP_RSC__PP_DS_R_H 0x1F0408C8,0x0000C000 ++#define LPM_MEM_IC_PP_RSC__PP_RS_R_H 0x1F0408C8,0x00003FFF ++ ++#define LPM_MEM_IC_CMBP_1__ADDR 0x1F0408CC ++#define LPM_MEM_IC_CMBP_1__EMPTY 0x1F0408CC,0x00000000 ++#define LPM_MEM_IC_CMBP_1__FULL 0x1F0408CC,0xffffffff ++#define LPM_MEM_IC_CMBP_1__IC_PP_ALPHA_V 0x1F0408CC,0x0000FF00 ++#define LPM_MEM_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1F0408CC,0x000000FF ++ ++#define LPM_MEM_IC_CMBP_2__ADDR 0x1F0408D0 ++#define LPM_MEM_IC_CMBP_2__EMPTY 0x1F0408D0,0x00000000 ++#define LPM_MEM_IC_CMBP_2__FULL 0x1F0408D0,0xffffffff ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_R 0x1F0408D0,0x00FF0000 ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_G 0x1F0408D0,0x0000FF00 ++#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_B 0x1F0408D0,0x000000FF ++ ++#define LPM_MEM_IC_IDMAC_1__ADDR 0x1F0408D4 ++#define LPM_MEM_IC_IDMAC_1__EMPTY 0x1F0408D4,0x00000000 ++#define LPM_MEM_IC_IDMAC_1__FULL 0x1F0408D4,0xffffffff ++#define LPM_MEM_IC_IDMAC_1__ALT_CB7_BURST_16 0x1F0408D4,0x02000000 ++#define LPM_MEM_IC_IDMAC_1__ALT_CB6_BURST_16 0x1F0408D4,0x01000000 ++#define LPM_MEM_IC_IDMAC_1__T3_FLIP_RS 0x1F0408D4,0x00400000 ++#define LPM_MEM_IC_IDMAC_1__T2_FLIP_RS 0x1F0408D4,0x00200000 ++#define LPM_MEM_IC_IDMAC_1__T1_FLIP_RS 0x1F0408D4,0x00100000 ++#define LPM_MEM_IC_IDMAC_1__T3_FLIP_UD 0x1F0408D4,0x00080000 ++#define LPM_MEM_IC_IDMAC_1__T3_FLIP_LR 0x1F0408D4,0x00040000 ++#define LPM_MEM_IC_IDMAC_1__T3_ROT 0x1F0408D4,0x00020000 ++#define LPM_MEM_IC_IDMAC_1__T2_FLIP_UD 0x1F0408D4,0x00010000 ++#define LPM_MEM_IC_IDMAC_1__T2_FLIP_LR 0x1F0408D4,0x00008000 ++#define LPM_MEM_IC_IDMAC_1__T2_ROT 0x1F0408D4,0x00004000 ++#define LPM_MEM_IC_IDMAC_1__T1_FLIP_UD 0x1F0408D4,0x00002000 ++#define LPM_MEM_IC_IDMAC_1__T1_FLIP_LR 0x1F0408D4,0x00001000 ++#define LPM_MEM_IC_IDMAC_1__T1_ROT 0x1F0408D4,0x00000800 ++#define LPM_MEM_IC_IDMAC_1__CB7_BURST_16 0x1F0408D4,0x00000080 ++#define LPM_MEM_IC_IDMAC_1__CB6_BURST_16 0x1F0408D4,0x00000040 ++#define LPM_MEM_IC_IDMAC_1__CB5_BURST_16 0x1F0408D4,0x00000020 ++#define LPM_MEM_IC_IDMAC_1__CB4_BURST_16 0x1F0408D4,0x00000010 ++#define LPM_MEM_IC_IDMAC_1__CB3_BURST_16 0x1F0408D4,0x00000008 ++#define LPM_MEM_IC_IDMAC_1__CB2_BURST_16 0x1F0408D4,0x00000004 ++#define LPM_MEM_IC_IDMAC_1__CB1_BURST_16 0x1F0408D4,0x00000002 ++#define LPM_MEM_IC_IDMAC_1__CB0_BURST_16 0x1F0408D4,0x00000001 ++ ++#define LPM_MEM_IC_IDMAC_2__ADDR 0x1F0408D8 ++#define LPM_MEM_IC_IDMAC_2__EMPTY 0x1F0408D8,0x00000000 ++#define LPM_MEM_IC_IDMAC_2__FULL 0x1F0408D8,0xffffffff ++#define LPM_MEM_IC_IDMAC_2__T3_FR_HEIGHT 0x1F0408D8,0x3FF00000 ++#define LPM_MEM_IC_IDMAC_2__T2_FR_HEIGHT 0x1F0408D8,0x000FFC00 ++#define LPM_MEM_IC_IDMAC_2__T1_FR_HEIGHT 0x1F0408D8,0x000003FF ++ ++#define LPM_MEM_IC_IDMAC_3__ADDR 0x1F0408DC ++#define LPM_MEM_IC_IDMAC_3__EMPTY 0x1F0408DC,0x00000000 ++#define LPM_MEM_IC_IDMAC_3__FULL 0x1F0408DC,0xffffffff ++#define LPM_MEM_IC_IDMAC_3__T3_FR_WIDTH 0x1F0408DC,0x3FF00000 ++#define LPM_MEM_IC_IDMAC_3__T2_FR_WIDTH 0x1F0408DC,0x000FFC00 ++#define LPM_MEM_IC_IDMAC_3__T1_FR_WIDTH 0x1F0408DC,0x000003FF ++ ++#define LPM_MEM_IC_IDMAC_4__ADDR 0x1F0408E0 ++#define LPM_MEM_IC_IDMAC_4__EMPTY 0x1F0408E0,0x00000000 ++#define LPM_MEM_IC_IDMAC_4__FULL 0x1F0408E0,0xffffffff ++#define LPM_MEM_IC_IDMAC_4__RM_BRDG_MAX_RQ 0x1F0408E0,0x0000F000 ++#define LPM_MEM_IC_IDMAC_4__IBM_BRDG_MAX_RQ 0x1F0408E0,0x00000F00 ++#define LPM_MEM_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1F0408E0,0x000000F0 ++#define LPM_MEM_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ 0x1F0408E0,0x0000000F ++ ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/rgb2ipt_lut.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/rgb2ipt_lut.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/rgb2ipt_lut.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/rgb2ipt_lut.h 2010-01-26 17:33:14.092968002 +0000 +@@ -0,0 +1,65545 @@ ++#ifndef __RGB2IPT_H__ ++#define __RGB2IPT_H__ ++ ++typedef unsigned char Mrgb2ipt[65536][3]; ++ ++ ++Mrgb2ipt RGB2IPT0 = { ++{80, 104, 119}, ++{90, 101, 123}, ++{106, 94, 129}, ++{124, 87, 135}, ++{141, 81, 140}, ++{158, 74, 144}, ++{175, 68, 149}, ++{189, 62, 152}, ++{81, 105, 120}, ++{91, 101, 124}, ++{107, 94, 129}, ++{124, 87, 135}, ++{141, 81, 140}, ++{158, 74, 144}, ++{175, 68, 149}, ++{189, 62, 152}, ++{82, 105, 120}, ++{91, 101, 124}, ++{107, 95, 129}, ++{124, 88, 135}, ++{142, 81, 140}, ++{159, 74, 145}, ++{175, 68, 149}, ++{190, 63, 152}, ++{83, 106, 120}, ++{93, 102, 124}, ++{108, 95, 130}, ++{125, 88, 135}, ++{142, 81, 140}, ++{159, 75, 145}, ++{176, 68, 149}, ++{190, 63, 152}, ++{85, 106, 121}, ++{94, 102, 124}, ++{109, 96, 130}, ++{126, 88, 135}, ++{143, 82, 140}, ++{160, 75, 145}, ++{177, 68, 149}, ++{191, 63, 152}, ++{87, 107, 121}, ++{96, 103, 125}, ++{111, 96, 130}, ++{127, 89, 135}, ++{144, 82, 140}, ++{161, 75, 145}, ++{177, 69, 149}, ++{191, 63, 152}, ++{89, 108, 122}, ++{98, 104, 125}, ++{113, 97, 130}, ++{129, 90, 135}, ++{146, 83, 140}, ++{162, 76, 145}, ++{178, 69, 149}, ++{192, 64, 152}, ++{92, 109, 123}, ++{100, 105, 126}, ++{115, 98, 131}, ++{131, 90, 136}, ++{147, 83, 140}, ++{163, 76, 145}, ++{179, 70, 149}, ++{193, 64, 152}, ++{95, 110, 123}, ++{103, 106, 126}, ++{117, 99, 131}, ++{132, 91, 136}, ++{148, 84, 141}, ++{165, 77, 145}, ++{181, 70, 149}, ++{194, 65, 152}, ++{98, 111, 124}, ++{106, 107, 127}, ++{119, 99, 131}, ++{134, 92, 136}, ++{150, 85, 141}, ++{166, 78, 145}, ++{182, 71, 149}, ++{195, 65, 152}, ++{101, 112, 125}, ++{109, 107, 127}, ++{122, 100, 132}, ++{136, 93, 136}, ++{152, 85, 141}, ++{168, 78, 145}, ++{183, 71, 149}, ++{197, 66, 152}, ++{105, 113, 126}, ++{112, 108, 128}, ++{124, 101, 132}, ++{139, 94, 137}, ++{154, 86, 141}, ++{170, 79, 145}, ++{185, 72, 149}, ++{198, 66, 152}, ++{108, 114, 126}, ++{115, 109, 129}, ++{127, 102, 133}, ++{141, 94, 137}, ++{156, 87, 141}, ++{171, 80, 145}, ++{187, 73, 149}, ++{200, 67, 152}, ++{112, 114, 127}, ++{118, 110, 129}, ++{130, 103, 133}, ++{144, 95, 137}, ++{158, 88, 141}, ++{173, 80, 145}, ++{188, 74, 149}, ++{201, 68, 152}, ++{115, 115, 128}, ++{122, 111, 130}, ++{133, 104, 133}, ++{146, 96, 138}, ++{161, 89, 142}, ++{175, 81, 146}, ++{190, 74, 149}, ++{203, 68, 152}, ++{119, 116, 128}, ++{125, 112, 130}, ++{136, 105, 134}, ++{149, 97, 138}, ++{163, 89, 142}, ++{178, 82, 146}, ++{192, 75, 149}, ++{205, 69, 153}, ++{123, 116, 129}, ++{129, 112, 131}, ++{139, 106, 134}, ++{152, 98, 138}, ++{166, 90, 142}, ++{180, 83, 146}, ++{194, 76, 150}, ++{207, 70, 153}, ++{127, 117, 130}, ++{132, 113, 132}, ++{142, 106, 135}, ++{155, 99, 138}, ++{168, 91, 142}, ++{182, 84, 146}, ++{196, 77, 150}, ++{209, 71, 153}, ++{131, 118, 130}, ++{136, 114, 132}, ++{146, 107, 135}, ++{158, 100, 139}, ++{171, 92, 143}, ++{185, 85, 146}, ++{199, 77, 150}, ++{211, 71, 153}, ++{134, 118, 131}, ++{140, 114, 133}, ++{149, 108, 136}, ++{161, 100, 139}, ++{174, 93, 143}, ++{187, 85, 146}, ++{201, 78, 150}, ++{213, 72, 153}, ++{138, 119, 132}, ++{143, 115, 133}, ++{153, 109, 136}, ++{164, 101, 139}, ++{177, 94, 143}, ++{190, 86, 147}, ++{203, 79, 150}, ++{215, 73, 153}, ++{142, 119, 132}, ++{147, 116, 134}, ++{156, 109, 137}, ++{167, 102, 140}, ++{179, 94, 143}, ++{192, 87, 147}, ++{206, 80, 150}, ++{217, 74, 153}, ++{146, 120, 133}, ++{151, 116, 134}, ++{160, 110, 137}, ++{170, 103, 140}, ++{182, 95, 143}, ++{195, 88, 147}, ++{208, 81, 150}, ++{220, 75, 153}, ++{150, 120, 133}, ++{155, 117, 135}, ++{163, 111, 137}, ++{174, 103, 140}, ++{185, 96, 144}, ++{198, 89, 147}, ++{210, 82, 150}, ++{222, 75, 153}, ++{154, 121, 134}, ++{159, 117, 135}, ++{167, 111, 138}, ++{177, 104, 141}, ++{188, 97, 144}, ++{200, 89, 147}, ++{213, 82, 151}, ++{224, 76, 153}, ++{158, 121, 135}, ++{162, 118, 136}, ++{170, 112, 138}, ++{180, 105, 141}, ++{191, 98, 144}, ++{203, 90, 147}, ++{216, 83, 151}, ++{227, 77, 153}, ++{162, 121, 135}, ++{166, 118, 136}, ++{174, 112, 139}, ++{184, 106, 141}, ++{195, 98, 145}, ++{206, 91, 148}, ++{218, 84, 151}, ++{229, 78, 154}, ++{166, 122, 136}, ++{170, 119, 137}, ++{178, 113, 139}, ++{187, 106, 142}, ++{198, 99, 145}, ++{209, 92, 148}, ++{221, 85, 151}, ++{232, 79, 154}, ++{168, 122, 136}, ++{172, 119, 137}, ++{179, 113, 139}, ++{189, 107, 142}, ++{199, 99, 145}, ++{211, 92, 148}, ++{222, 85, 151}, ++{233, 79, 154}, ++{168, 122, 136}, ++{172, 119, 137}, ++{179, 113, 139}, ++{189, 107, 142}, ++{199, 99, 145}, ++{211, 92, 148}, ++{222, 85, 151}, ++{233, 79, 154}, ++{168, 122, 136}, ++{172, 119, 137}, ++{179, 113, 139}, ++{189, 107, 142}, ++{199, 99, 145}, ++{211, 92, 148}, ++{222, 85, 151}, ++{233, 79, 154}, ++{168, 122, 136}, ++{172, 119, 137}, ++{179, 113, 139}, ++{189, 107, 142}, ++{199, 99, 145}, ++{211, 92, 148}, ++{222, 85, 151}, ++{233, 79, 154}, ++{82, 103, 118}, ++{91, 100, 122}, ++{107, 94, 128}, ++{124, 87, 134}, ++{142, 80, 139}, ++{159, 74, 144}, ++{176, 67, 148}, ++{190, 62, 151}, ++{82, 104, 118}, ++{92, 100, 122}, ++{107, 94, 128}, ++{125, 87, 134}, ++{142, 80, 139}, ++{159, 74, 144}, ++{176, 68, 148}, ++{190, 62, 151}, ++{83, 104, 119}, ++{92, 100, 123}, ++{108, 94, 128}, ++{125, 87, 134}, ++{142, 81, 139}, ++{159, 74, 144}, ++{176, 68, 148}, ++{190, 62, 151}, ++{84, 105, 119}, ++{94, 101, 123}, ++{109, 94, 128}, ++{126, 88, 134}, ++{143, 81, 139}, ++{160, 74, 144}, ++{176, 68, 148}, ++{191, 63, 151}, ++{86, 105, 120}, ++{95, 101, 123}, ++{110, 95, 129}, ++{127, 88, 134}, ++{144, 81, 139}, ++{161, 75, 144}, ++{177, 68, 148}, ++{191, 63, 151}, ++{88, 106, 120}, ++{97, 102, 124}, ++{112, 96, 129}, ++{128, 89, 134}, ++{145, 82, 139}, ++{162, 75, 144}, ++{178, 69, 148}, ++{192, 63, 151}, ++{90, 107, 121}, ++{99, 103, 124}, ++{113, 96, 129}, ++{130, 89, 135}, ++{146, 82, 139}, ++{163, 75, 144}, ++{179, 69, 148}, ++{193, 64, 151}, ++{93, 108, 121}, ++{101, 104, 125}, ++{115, 97, 130}, ++{131, 90, 135}, ++{148, 83, 140}, ++{164, 76, 144}, ++{180, 70, 148}, ++{194, 64, 151}, ++{96, 109, 122}, ++{104, 105, 125}, ++{117, 98, 130}, ++{133, 91, 135}, ++{149, 84, 140}, ++{165, 77, 144}, ++{181, 70, 148}, ++{195, 64, 152}, ++{99, 110, 123}, ++{107, 106, 126}, ++{120, 99, 130}, ++{135, 92, 135}, ++{151, 84, 140}, ++{167, 77, 144}, ++{182, 71, 148}, ++{196, 65, 152}, ++{102, 111, 124}, ++{109, 107, 126}, ++{122, 100, 131}, ++{137, 92, 135}, ++{153, 85, 140}, ++{168, 78, 144}, ++{184, 71, 148}, ++{197, 66, 152}, ++{105, 112, 124}, ++{113, 108, 127}, ++{125, 101, 131}, ++{139, 93, 136}, ++{155, 86, 140}, ++{170, 79, 144}, ++{185, 72, 148}, ++{199, 66, 152}, ++{109, 113, 125}, ++{116, 109, 128}, ++{128, 102, 132}, ++{142, 94, 136}, ++{157, 87, 140}, ++{172, 79, 145}, ++{187, 73, 148}, ++{200, 67, 152}, ++{112, 114, 126}, ++{119, 110, 128}, ++{131, 103, 132}, ++{144, 95, 136}, ++{159, 87, 141}, ++{174, 80, 145}, ++{189, 73, 149}, ++{202, 68, 152}, ++{116, 114, 127}, ++{122, 110, 129}, ++{134, 103, 133}, ++{147, 96, 137}, ++{161, 88, 141}, ++{176, 81, 145}, ++{191, 74, 149}, ++{203, 68, 152}, ++{120, 115, 127}, ++{126, 111, 129}, ++{137, 104, 133}, ++{150, 97, 137}, ++{164, 89, 141}, ++{178, 82, 145}, ++{193, 75, 149}, ++{205, 69, 152}, ++{124, 116, 128}, ++{129, 112, 130}, ++{140, 105, 134}, ++{152, 98, 137}, ++{166, 90, 141}, ++{180, 83, 145}, ++{195, 76, 149}, ++{207, 70, 152}, ++{127, 117, 129}, ++{133, 113, 131}, ++{143, 106, 134}, ++{155, 98, 138}, ++{169, 91, 142}, ++{183, 83, 145}, ++{197, 76, 149}, ++{209, 70, 152}, ++{131, 117, 130}, ++{137, 113, 131}, ++{146, 107, 134}, ++{158, 99, 138}, ++{171, 92, 142}, ++{185, 84, 146}, ++{199, 77, 149}, ++{211, 71, 152}, ++{135, 118, 130}, ++{140, 114, 132}, ++{150, 107, 135}, ++{161, 100, 138}, ++{174, 93, 142}, ++{188, 85, 146}, ++{201, 78, 149}, ++{213, 72, 152}, ++{139, 118, 131}, ++{144, 115, 132}, ++{153, 108, 135}, ++{164, 101, 139}, ++{177, 93, 142}, ++{190, 86, 146}, ++{204, 79, 149}, ++{215, 73, 152}, ++{143, 119, 131}, ++{148, 115, 133}, ++{157, 109, 136}, ++{168, 102, 139}, ++{180, 94, 143}, ++{193, 87, 146}, ++{206, 80, 150}, ++{218, 74, 152}, ++{147, 119, 132}, ++{151, 116, 134}, ++{160, 110, 136}, ++{171, 102, 139}, ++{183, 95, 143}, ++{195, 88, 146}, ++{208, 80, 150}, ++{220, 74, 153}, ++{151, 120, 133}, ++{155, 116, 134}, ++{164, 110, 137}, ++{174, 103, 140}, ++{186, 96, 143}, ++{198, 88, 146}, ++{211, 81, 150}, ++{222, 75, 153}, ++{155, 120, 133}, ++{159, 117, 135}, ++{167, 111, 137}, ++{177, 104, 140}, ++{189, 97, 143}, ++{201, 89, 147}, ++{213, 82, 150}, ++{225, 76, 153}, ++{159, 121, 134}, ++{163, 117, 135}, ++{171, 111, 138}, ++{181, 105, 141}, ++{192, 97, 144}, ++{204, 90, 147}, ++{216, 83, 150}, ++{227, 77, 153}, ++{163, 121, 134}, ++{167, 118, 136}, ++{174, 112, 138}, ++{184, 105, 141}, ++{195, 98, 144}, ++{207, 91, 147}, ++{219, 84, 150}, ++{230, 78, 153}, ++{167, 121, 135}, ++{171, 118, 136}, ++{178, 113, 138}, ++{187, 106, 141}, ++{198, 99, 144}, ++{210, 92, 147}, ++{221, 85, 151}, ++{232, 78, 153}, ++{169, 121, 135}, ++{172, 118, 136}, ++{180, 113, 139}, ++{189, 106, 141}, ++{200, 99, 144}, ++{211, 92, 147}, ++{223, 85, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{172, 118, 136}, ++{180, 113, 139}, ++{189, 106, 141}, ++{200, 99, 144}, ++{211, 92, 147}, ++{223, 85, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{172, 118, 136}, ++{180, 113, 139}, ++{189, 106, 141}, ++{200, 99, 144}, ++{211, 92, 147}, ++{223, 85, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{172, 118, 136}, ++{180, 113, 139}, ++{189, 106, 141}, ++{200, 99, 144}, ++{211, 92, 147}, ++{223, 85, 151}, ++{233, 79, 153}, ++{84, 102, 116}, ++{93, 98, 120}, ++{109, 93, 126}, ++{126, 86, 132}, ++{143, 80, 137}, ++{160, 73, 142}, ++{176, 67, 147}, ++{190, 62, 150}, ++{84, 102, 116}, ++{93, 99, 120}, ++{109, 93, 126}, ++{126, 86, 132}, ++{143, 80, 137}, ++{160, 73, 142}, ++{176, 67, 147}, ++{191, 62, 150}, ++{85, 102, 117}, ++{94, 99, 121}, ++{109, 93, 126}, ++{126, 87, 132}, ++{143, 80, 138}, ++{160, 74, 142}, ++{177, 67, 147}, ++{191, 62, 150}, ++{86, 103, 117}, ++{95, 99, 121}, ++{110, 94, 127}, ++{127, 87, 132}, ++{144, 80, 138}, ++{161, 74, 142}, ++{177, 68, 147}, ++{191, 62, 150}, ++{88, 104, 118}, ++{97, 100, 121}, ++{112, 94, 127}, ++{128, 87, 133}, ++{145, 81, 138}, ++{162, 74, 142}, ++{178, 68, 147}, ++{192, 63, 150}, ++{90, 105, 118}, ++{98, 101, 122}, ++{113, 95, 127}, ++{129, 88, 133}, ++{146, 81, 138}, ++{162, 75, 142}, ++{179, 68, 147}, ++{193, 63, 150}, ++{92, 106, 119}, ++{100, 102, 122}, ++{115, 95, 128}, ++{131, 89, 133}, ++{147, 82, 138}, ++{164, 75, 143}, ++{180, 69, 147}, ++{193, 63, 150}, ++{95, 107, 120}, ++{103, 103, 123}, ++{117, 96, 128}, ++{132, 89, 133}, ++{149, 82, 138}, ++{165, 76, 143}, ++{181, 69, 147}, ++{194, 64, 150}, ++{97, 108, 120}, ++{105, 104, 123}, ++{119, 97, 128}, ++{134, 90, 133}, ++{150, 83, 138}, ++{166, 76, 143}, ++{182, 70, 147}, ++{195, 64, 150}, ++{100, 109, 121}, ++{108, 105, 124}, ++{121, 98, 129}, ++{136, 91, 134}, ++{152, 84, 138}, ++{168, 77, 143}, ++{183, 70, 147}, ++{197, 65, 150}, ++{104, 110, 122}, ++{111, 106, 125}, ++{124, 99, 129}, ++{138, 92, 134}, ++{154, 84, 139}, ++{169, 78, 143}, ++{185, 71, 147}, ++{198, 65, 151}, ++{107, 111, 123}, ++{114, 107, 125}, ++{126, 100, 130}, ++{140, 93, 134}, ++{156, 85, 139}, ++{171, 78, 143}, ++{186, 72, 147}, ++{199, 66, 151}, ++{110, 112, 124}, ++{117, 108, 126}, ++{129, 101, 130}, ++{143, 93, 135}, ++{158, 86, 139}, ++{173, 79, 143}, ++{188, 72, 147}, ++{201, 67, 151}, ++{114, 113, 124}, ++{120, 109, 127}, ++{132, 102, 131}, ++{145, 94, 135}, ++{160, 87, 139}, ++{175, 80, 144}, ++{190, 73, 147}, ++{202, 67, 151}, ++{117, 113, 125}, ++{124, 109, 127}, ++{135, 103, 131}, ++{148, 95, 135}, ++{162, 88, 140}, ++{177, 81, 144}, ++{191, 74, 148}, ++{204, 68, 151}, ++{121, 114, 126}, ++{127, 110, 128}, ++{138, 103, 132}, ++{151, 96, 136}, ++{165, 89, 140}, ++{179, 81, 144}, ++{193, 74, 148}, ++{206, 69, 151}, ++{125, 115, 127}, ++{130, 111, 129}, ++{141, 104, 132}, ++{153, 97, 136}, ++{167, 89, 140}, ++{181, 82, 144}, ++{195, 75, 148}, ++{208, 69, 151}, ++{129, 116, 127}, ++{134, 112, 129}, ++{144, 105, 133}, ++{156, 98, 136}, ++{170, 90, 140}, ++{183, 83, 144}, ++{197, 76, 148}, ++{210, 70, 151}, ++{132, 116, 128}, ++{138, 112, 130}, ++{147, 106, 133}, ++{159, 99, 137}, ++{172, 91, 141}, ++{186, 84, 144}, ++{200, 77, 148}, ++{212, 71, 151}, ++{136, 117, 129}, ++{141, 113, 131}, ++{151, 107, 134}, ++{162, 99, 137}, ++{175, 92, 141}, ++{188, 85, 145}, ++{202, 78, 148}, ++{214, 72, 151}, ++{140, 117, 130}, ++{145, 114, 131}, ++{154, 108, 134}, ++{165, 100, 138}, ++{178, 93, 141}, ++{191, 86, 145}, ++{204, 78, 148}, ++{216, 73, 151}, ++{144, 118, 130}, ++{149, 114, 132}, ++{158, 108, 135}, ++{168, 101, 138}, ++{181, 94, 141}, ++{193, 86, 145}, ++{207, 79, 149}, ++{218, 73, 152}, ++{148, 118, 131}, ++{152, 115, 132}, ++{161, 109, 135}, ++{172, 102, 138}, ++{184, 95, 142}, ++{196, 87, 145}, ++{209, 80, 149}, ++{220, 74, 152}, ++{152, 119, 132}, ++{156, 116, 133}, ++{165, 110, 136}, ++{175, 103, 139}, ++{187, 95, 142}, ++{199, 88, 145}, ++{212, 81, 149}, ++{223, 75, 152}, ++{156, 119, 132}, ++{160, 116, 134}, ++{168, 110, 136}, ++{178, 103, 139}, ++{190, 96, 142}, ++{202, 89, 146}, ++{214, 82, 149}, ++{225, 76, 152}, ++{160, 120, 133}, ++{164, 117, 134}, ++{172, 111, 137}, ++{181, 104, 139}, ++{193, 97, 143}, ++{204, 90, 146}, ++{217, 83, 149}, ++{228, 77, 152}, ++{164, 120, 133}, ++{168, 117, 135}, ++{175, 111, 137}, ++{185, 105, 140}, ++{196, 98, 143}, ++{207, 90, 146}, ++{219, 83, 149}, ++{230, 77, 152}, ++{168, 121, 134}, ++{171, 118, 135}, ++{179, 112, 137}, ++{188, 105, 140}, ++{199, 98, 143}, ++{210, 91, 146}, ++{222, 84, 150}, ++{233, 78, 152}, ++{169, 121, 134}, ++{173, 118, 135}, ++{181, 112, 138}, ++{190, 106, 140}, ++{200, 99, 143}, ++{212, 92, 147}, ++{223, 85, 150}, ++{234, 79, 152}, ++{169, 121, 134}, ++{173, 118, 135}, ++{181, 112, 138}, ++{190, 106, 140}, ++{200, 99, 143}, ++{212, 92, 147}, ++{223, 85, 150}, ++{234, 79, 152}, ++{169, 121, 134}, ++{173, 118, 135}, ++{181, 112, 138}, ++{190, 106, 140}, ++{200, 99, 143}, ++{212, 92, 147}, ++{223, 85, 150}, ++{234, 79, 152}, ++{169, 121, 134}, ++{173, 118, 135}, ++{181, 112, 138}, ++{190, 106, 140}, ++{200, 99, 143}, ++{212, 92, 147}, ++{223, 85, 150}, ++{234, 79, 152}, ++{86, 100, 114}, ++{95, 97, 118}, ++{110, 91, 124}, ++{127, 85, 130}, ++{144, 79, 136}, ++{161, 73, 141}, ++{177, 67, 145}, ++{191, 61, 149}, ++{86, 100, 114}, ++{95, 97, 118}, ++{111, 92, 124}, ++{127, 85, 130}, ++{144, 79, 136}, ++{161, 73, 141}, ++{177, 67, 145}, ++{191, 61, 149}, ++{87, 100, 114}, ++{96, 97, 118}, ++{111, 92, 124}, ++{128, 86, 130}, ++{145, 79, 136}, ++{161, 73, 141}, ++{178, 67, 145}, ++{192, 62, 149}, ++{88, 101, 115}, ++{97, 98, 119}, ++{112, 92, 125}, ++{129, 86, 130}, ++{145, 80, 136}, ++{162, 73, 141}, ++{178, 67, 145}, ++{192, 62, 149}, ++{90, 102, 115}, ++{99, 99, 119}, ++{113, 93, 125}, ++{130, 86, 131}, ++{146, 80, 136}, ++{163, 74, 141}, ++{179, 67, 145}, ++{193, 62, 149}, ++{92, 103, 116}, ++{100, 99, 120}, ++{115, 94, 125}, ++{131, 87, 131}, ++{147, 80, 136}, ++{164, 74, 141}, ++{180, 68, 145}, ++{193, 62, 149}, ++{94, 104, 117}, ++{102, 100, 120}, ++{116, 94, 126}, ++{132, 88, 131}, ++{148, 81, 136}, ++{165, 75, 141}, ++{181, 68, 145}, ++{194, 63, 149}, ++{97, 105, 118}, ++{105, 101, 121}, ++{118, 95, 126}, ++{134, 88, 131}, ++{150, 82, 136}, ++{166, 75, 141}, ++{182, 69, 145}, ++{195, 63, 149}, ++{99, 106, 118}, ++{107, 102, 121}, ++{120, 96, 126}, ++{136, 89, 132}, ++{151, 82, 137}, ++{167, 76, 141}, ++{183, 69, 146}, ++{196, 64, 149}, ++{102, 107, 119}, ++{110, 103, 122}, ++{123, 97, 127}, ++{137, 90, 132}, ++{153, 83, 137}, ++{169, 76, 141}, ++{184, 70, 146}, ++{198, 64, 149}, ++{105, 108, 120}, ++{113, 104, 123}, ++{125, 98, 127}, ++{140, 91, 132}, ++{155, 84, 137}, ++{170, 77, 142}, ++{186, 70, 146}, ++{199, 65, 149}, ++{109, 109, 121}, ++{115, 105, 123}, ++{128, 99, 128}, ++{142, 92, 133}, ++{157, 85, 137}, ++{172, 78, 142}, ++{187, 71, 146}, ++{200, 65, 149}, ++{112, 110, 122}, ++{119, 106, 124}, ++{130, 100, 128}, ++{144, 93, 133}, ++{159, 85, 137}, ++{174, 78, 142}, ++{189, 72, 146}, ++{202, 66, 149}, ++{115, 111, 123}, ++{122, 107, 125}, ++{133, 101, 129}, ++{147, 93, 133}, ++{161, 86, 138}, ++{176, 79, 142}, ++{191, 72, 146}, ++{203, 67, 149}, ++{119, 112, 123}, ++{125, 108, 126}, ++{136, 102, 129}, ++{149, 94, 134}, ++{163, 87, 138}, ++{178, 80, 142}, ++{192, 73, 146}, ++{205, 68, 150}, ++{123, 113, 124}, ++{128, 109, 126}, ++{139, 103, 130}, ++{152, 95, 134}, ++{166, 88, 138}, ++{180, 81, 142}, ++{194, 74, 146}, ++{207, 68, 150}, ++{126, 114, 125}, ++{132, 110, 127}, ++{142, 103, 130}, ++{155, 96, 134}, ++{168, 89, 139}, ++{182, 82, 143}, ++{196, 75, 147}, ++{209, 69, 150}, ++{130, 114, 126}, ++{135, 111, 128}, ++{145, 104, 131}, ++{157, 97, 135}, ++{171, 90, 139}, ++{184, 83, 143}, ++{198, 76, 147}, ++{211, 70, 150}, ++{134, 115, 126}, ++{139, 111, 128}, ++{149, 105, 132}, ++{160, 98, 135}, ++{173, 91, 139}, ++{187, 83, 143}, ++{201, 76, 147}, ++{213, 71, 150}, ++{138, 116, 127}, ++{143, 112, 129}, ++{152, 106, 132}, ++{163, 99, 136}, ++{176, 91, 140}, ++{189, 84, 143}, ++{203, 77, 147}, ++{215, 71, 150}, ++{141, 116, 128}, ++{146, 113, 130}, ++{155, 107, 133}, ++{166, 100, 136}, ++{179, 92, 140}, ++{192, 85, 144}, ++{205, 78, 147}, ++{217, 72, 150}, ++{145, 117, 129}, ++{150, 113, 130}, ++{159, 107, 133}, ++{170, 100, 137}, ++{182, 93, 140}, ++{194, 86, 144}, ++{207, 79, 147}, ++{219, 73, 150}, ++{149, 117, 129}, ++{154, 114, 131}, ++{162, 108, 134}, ++{173, 101, 137}, ++{184, 94, 140}, ++{197, 87, 144}, ++{210, 80, 148}, ++{221, 74, 151}, ++{153, 118, 130}, ++{157, 115, 131}, ++{166, 109, 134}, ++{176, 102, 137}, ++{187, 95, 141}, ++{200, 88, 144}, ++{212, 81, 148}, ++{224, 75, 151}, ++{157, 118, 131}, ++{161, 115, 132}, ++{169, 109, 135}, ++{179, 103, 138}, ++{190, 96, 141}, ++{202, 88, 145}, ++{215, 81, 148}, ++{226, 75, 151}, ++{161, 119, 131}, ++{165, 116, 133}, ++{173, 110, 135}, ++{182, 103, 138}, ++{193, 96, 141}, ++{205, 89, 145}, ++{217, 82, 148}, ++{228, 76, 151}, ++{165, 119, 132}, ++{169, 116, 133}, ++{176, 111, 136}, ++{186, 104, 139}, ++{197, 97, 142}, ++{208, 90, 145}, ++{220, 83, 148}, ++{231, 77, 151}, ++{169, 120, 133}, ++{172, 117, 134}, ++{180, 111, 136}, ++{189, 105, 139}, ++{200, 98, 142}, ++{211, 91, 145}, ++{223, 84, 149}, ++{233, 78, 151}, ++{171, 120, 133}, ++{174, 117, 134}, ++{182, 112, 136}, ++{191, 105, 139}, ++{201, 98, 142}, ++{212, 91, 145}, ++{224, 84, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{174, 117, 134}, ++{182, 112, 136}, ++{191, 105, 139}, ++{201, 98, 142}, ++{212, 91, 145}, ++{224, 84, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{174, 117, 134}, ++{182, 112, 136}, ++{191, 105, 139}, ++{201, 98, 142}, ++{212, 91, 145}, ++{224, 84, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{174, 117, 134}, ++{182, 112, 136}, ++{191, 105, 139}, ++{201, 98, 142}, ++{212, 91, 145}, ++{224, 84, 149}, ++{235, 78, 151}, ++{88, 98, 112}, ++{97, 95, 116}, ++{112, 90, 122}, ++{129, 84, 128}, ++{146, 78, 134}, ++{162, 72, 139}, ++{179, 66, 143}, ++{192, 61, 147}, ++{89, 98, 112}, ++{98, 95, 116}, ++{113, 90, 122}, ++{129, 84, 128}, ++{146, 78, 134}, ++{162, 72, 139}, ++{179, 66, 143}, ++{193, 61, 147}, ++{89, 98, 112}, ++{98, 95, 116}, ++{113, 91, 122}, ++{130, 85, 128}, ++{146, 78, 134}, ++{163, 72, 139}, ++{179, 66, 143}, ++{193, 61, 147}, ++{91, 99, 113}, ++{99, 96, 116}, ++{114, 91, 122}, ++{130, 85, 128}, ++{147, 79, 134}, ++{163, 73, 139}, ++{179, 67, 143}, ++{193, 61, 147}, ++{92, 100, 113}, ++{101, 97, 117}, ++{115, 92, 123}, ++{131, 85, 128}, ++{148, 79, 134}, ++{164, 73, 139}, ++{180, 67, 144}, ++{194, 62, 147}, ++{94, 101, 114}, ++{102, 98, 117}, ++{117, 92, 123}, ++{132, 86, 129}, ++{149, 80, 134}, ++{165, 73, 139}, ++{181, 67, 144}, ++{195, 62, 147}, ++{96, 102, 114}, ++{104, 99, 118}, ++{118, 93, 123}, ++{134, 87, 129}, ++{150, 80, 134}, ++{166, 74, 139}, ++{182, 68, 144}, ++{195, 62, 147}, ++{99, 103, 115}, ++{107, 100, 118}, ++{120, 94, 124}, ++{135, 87, 129}, ++{151, 81, 134}, ++{167, 74, 139}, ++{183, 68, 144}, ++{196, 63, 147}, ++{102, 104, 116}, ++{109, 101, 119}, ++{122, 95, 124}, ++{137, 88, 130}, ++{153, 82, 135}, ++{168, 75, 139}, ++{184, 69, 144}, ++{197, 63, 148}, ++{104, 105, 117}, ++{112, 102, 120}, ++{124, 96, 125}, ++{139, 89, 130}, ++{154, 82, 135}, ++{170, 76, 140}, ++{185, 69, 144}, ++{199, 64, 148}, ++{107, 106, 118}, ++{114, 103, 121}, ++{127, 97, 125}, ++{141, 90, 130}, ++{156, 83, 135}, ++{171, 76, 140}, ++{187, 70, 144}, ++{200, 64, 148}, ++{111, 107, 119}, ++{117, 104, 121}, ++{129, 98, 126}, ++{143, 91, 131}, ++{158, 84, 135}, ++{173, 77, 140}, ++{188, 71, 144}, ++{201, 65, 148}, ++{114, 109, 120}, ++{120, 105, 122}, ++{132, 99, 126}, ++{146, 92, 131}, ++{160, 85, 136}, ++{175, 78, 140}, ++{190, 71, 144}, ++{203, 66, 148}, ++{117, 110, 120}, ++{124, 106, 123}, ++{135, 100, 127}, ++{148, 93, 131}, ++{162, 85, 136}, ++{177, 79, 140}, ++{192, 72, 145}, ++{204, 66, 148}, ++{121, 110, 121}, ++{127, 107, 124}, ++{138, 100, 127}, ++{151, 93, 132}, ++{165, 86, 136}, ++{179, 79, 141}, ++{193, 73, 145}, ++{206, 67, 148}, ++{124, 111, 122}, ++{130, 108, 124}, ++{141, 101, 128}, ++{153, 94, 132}, ++{167, 87, 137}, ++{181, 80, 141}, ++{195, 73, 145}, ++{208, 68, 148}, ++{128, 112, 123}, ++{133, 109, 125}, ++{144, 102, 129}, ++{156, 95, 133}, ++{169, 88, 137}, ++{183, 81, 141}, ++{197, 74, 145}, ++{210, 69, 148}, ++{132, 113, 124}, ++{137, 109, 126}, ++{147, 103, 129}, ++{159, 96, 133}, ++{172, 89, 137}, ++{186, 82, 141}, ++{199, 75, 145}, ++{212, 69, 148}, ++{135, 114, 125}, ++{140, 110, 126}, ++{150, 104, 130}, ++{162, 97, 134}, ++{174, 90, 138}, ++{188, 83, 142}, ++{202, 76, 145}, ++{214, 70, 149}, ++{139, 114, 125}, ++{144, 111, 127}, ++{153, 105, 130}, ++{165, 98, 134}, ++{177, 91, 138}, ++{190, 84, 142}, ++{204, 77, 146}, ++{216, 71, 149}, ++{143, 115, 126}, ++{148, 112, 128}, ++{157, 106, 131}, ++{168, 99, 134}, ++{180, 92, 138}, ++{193, 84, 142}, ++{206, 78, 146}, ++{218, 72, 149}, ++{147, 116, 127}, ++{151, 112, 129}, ++{160, 106, 131}, ++{171, 100, 135}, ++{183, 92, 139}, ++{195, 85, 142}, ++{208, 78, 146}, ++{220, 72, 149}, ++{150, 116, 128}, ++{155, 113, 129}, ++{163, 107, 132}, ++{174, 100, 135}, ++{186, 93, 139}, ++{198, 86, 143}, ++{211, 79, 146}, ++{222, 73, 149}, ++{154, 117, 128}, ++{159, 114, 130}, ++{167, 108, 133}, ++{177, 101, 136}, ++{188, 94, 139}, ++{201, 87, 143}, ++{213, 80, 146}, ++{224, 74, 149}, ++{158, 117, 129}, ++{162, 114, 131}, ++{170, 109, 133}, ++{180, 102, 136}, ++{191, 95, 140}, ++{203, 88, 143}, ++{216, 81, 147}, ++{227, 75, 150}, ++{162, 118, 130}, ++{166, 115, 131}, ++{174, 109, 134}, ++{184, 103, 137}, ++{194, 96, 140}, ++{206, 89, 143}, ++{218, 82, 147}, ++{229, 76, 150}, ++{166, 118, 130}, ++{170, 115, 132}, ++{177, 110, 134}, ++{187, 103, 137}, ++{198, 96, 140}, ++{209, 89, 144}, ++{221, 82, 147}, ++{232, 77, 150}, ++{170, 119, 131}, ++{174, 116, 132}, ++{181, 110, 135}, ++{190, 104, 138}, ++{201, 97, 141}, ++{212, 90, 144}, ++{224, 83, 147}, ++{234, 77, 150}, ++{172, 119, 131}, ++{175, 116, 133}, ++{183, 111, 135}, ++{192, 104, 138}, ++{202, 98, 141}, ++{213, 91, 144}, ++{225, 84, 147}, ++{235, 78, 150}, ++{172, 119, 131}, ++{175, 116, 133}, ++{183, 111, 135}, ++{192, 104, 138}, ++{202, 98, 141}, ++{213, 91, 144}, ++{225, 84, 147}, ++{235, 78, 150}, ++{172, 119, 131}, ++{175, 116, 133}, ++{183, 111, 135}, ++{192, 104, 138}, ++{202, 98, 141}, ++{213, 91, 144}, ++{225, 84, 147}, ++{235, 78, 150}, ++{172, 119, 131}, ++{175, 116, 133}, ++{183, 111, 135}, ++{192, 104, 138}, ++{202, 98, 141}, ++{213, 91, 144}, ++{225, 84, 147}, ++{235, 78, 150}, ++{91, 95, 109}, ++{100, 93, 113}, ++{114, 89, 120}, ++{131, 83, 126}, ++{147, 77, 132}, ++{164, 71, 137}, ++{180, 65, 142}, ++{194, 60, 145}, ++{91, 95, 109}, ++{100, 93, 113}, ++{115, 89, 120}, ++{131, 83, 126}, ++{147, 77, 132}, ++{164, 71, 137}, ++{180, 66, 142}, ++{194, 60, 145}, ++{92, 96, 110}, ++{101, 93, 114}, ++{115, 89, 120}, ++{131, 83, 126}, ++{148, 78, 132}, ++{164, 72, 137}, ++{180, 66, 142}, ++{194, 61, 145}, ++{93, 97, 110}, ++{102, 94, 114}, ++{116, 89, 120}, ++{132, 84, 126}, ++{148, 78, 132}, ++{165, 72, 137}, ++{181, 66, 142}, ++{194, 61, 146}, ++{95, 97, 111}, ++{103, 95, 114}, ++{117, 90, 120}, ++{133, 84, 126}, ++{149, 78, 132}, ++{165, 72, 137}, ++{181, 66, 142}, ++{195, 61, 146}, ++{97, 99, 111}, ++{105, 96, 115}, ++{119, 91, 121}, ++{134, 85, 126}, ++{150, 79, 132}, ++{166, 73, 137}, ++{182, 67, 142}, ++{196, 61, 146}, ++{99, 100, 112}, ++{107, 97, 115}, ++{120, 92, 121}, ++{136, 86, 127}, ++{151, 79, 132}, ++{167, 73, 137}, ++{183, 67, 142}, ++{197, 62, 146}, ++{101, 101, 113}, ++{109, 98, 116}, ++{122, 92, 121}, ++{137, 86, 127}, ++{153, 80, 132}, ++{168, 74, 137}, ++{184, 67, 142}, ++{197, 62, 146}, ++{104, 102, 114}, ++{111, 99, 117}, ++{124, 93, 122}, ++{139, 87, 127}, ++{154, 81, 133}, ++{170, 74, 138}, ++{185, 68, 142}, ++{199, 63, 146}, ++{107, 103, 115}, ++{114, 100, 118}, ++{126, 94, 123}, ++{141, 88, 128}, ++{156, 81, 133}, ++{171, 75, 138}, ++{187, 69, 142}, ++{200, 63, 146}, ++{110, 104, 116}, ++{116, 101, 118}, ++{129, 95, 123}, ++{143, 89, 128}, ++{158, 82, 133}, ++{173, 76, 138}, ++{188, 69, 142}, ++{201, 64, 146}, ++{113, 106, 116}, ++{119, 102, 119}, ++{131, 96, 124}, ++{145, 90, 129}, ++{160, 83, 133}, ++{174, 76, 138}, ++{189, 70, 143}, ++{202, 64, 146}, ++{116, 107, 117}, ++{122, 103, 120}, ++{134, 97, 124}, ++{147, 91, 129}, ++{162, 84, 134}, ++{176, 77, 138}, ++{191, 71, 143}, ++{204, 65, 146}, ++{119, 108, 118}, ++{125, 104, 121}, ++{136, 98, 125}, ++{150, 91, 129}, ++{164, 85, 134}, ++{178, 78, 139}, ++{193, 71, 143}, ++{205, 66, 146}, ++{123, 109, 119}, ++{129, 105, 121}, ++{139, 99, 125}, ++{152, 92, 130}, ++{166, 85, 134}, ++{180, 79, 139}, ++{195, 72, 143}, ++{207, 67, 147}, ++{126, 110, 120}, ++{132, 106, 122}, ++{142, 100, 126}, ++{155, 93, 130}, ++{168, 86, 135}, ++{182, 79, 139}, ++{196, 73, 143}, ++{209, 67, 147}, ++{130, 111, 121}, ++{135, 107, 123}, ++{145, 101, 127}, ++{157, 94, 131}, ++{171, 87, 135}, ++{184, 80, 139}, ++{198, 74, 143}, ++{211, 68, 147}, ++{133, 111, 122}, ++{139, 108, 124}, ++{148, 102, 127}, ++{160, 95, 131}, ++{173, 88, 136}, ++{187, 81, 140}, ++{200, 74, 144}, ++{213, 69, 147}, ++{137, 112, 123}, ++{142, 109, 125}, ++{152, 103, 128}, ++{163, 96, 132}, ++{176, 89, 136}, ++{189, 82, 140}, ++{203, 75, 144}, ++{215, 70, 147}, ++{141, 113, 123}, ++{146, 110, 125}, ++{155, 104, 128}, ++{166, 97, 132}, ++{178, 90, 136}, ++{191, 83, 140}, ++{205, 76, 144}, ++{217, 70, 147}, ++{144, 114, 124}, ++{149, 110, 126}, ++{158, 105, 129}, ++{169, 98, 133}, ++{181, 91, 137}, ++{194, 84, 140}, ++{207, 77, 144}, ++{219, 71, 148}, ++{148, 114, 125}, ++{153, 111, 127}, ++{161, 105, 130}, ++{172, 99, 133}, ++{184, 92, 137}, ++{196, 85, 141}, ++{209, 78, 145}, ++{221, 72, 148}, ++{152, 115, 126}, ++{156, 112, 127}, ++{165, 106, 130}, ++{175, 99, 134}, ++{187, 92, 137}, ++{199, 85, 141}, ++{212, 79, 145}, ++{223, 73, 148}, ++{156, 116, 127}, ++{160, 112, 128}, ++{168, 107, 131}, ++{178, 100, 134}, ++{190, 93, 138}, ++{202, 86, 141}, ++{214, 79, 145}, ++{225, 74, 148}, ++{160, 116, 127}, ++{164, 113, 129}, ++{172, 108, 131}, ++{181, 101, 135}, ++{193, 94, 138}, ++{204, 87, 142}, ++{217, 80, 145}, ++{228, 74, 148}, ++{163, 117, 128}, ++{167, 114, 129}, ++{175, 108, 132}, ++{185, 102, 135}, ++{196, 95, 139}, ++{207, 88, 142}, ++{219, 81, 145}, ++{230, 75, 148}, ++{167, 117, 129}, ++{171, 114, 130}, ++{179, 109, 133}, ++{188, 103, 136}, ++{199, 96, 139}, ++{210, 89, 142}, ++{222, 82, 146}, ++{233, 76, 149}, ++{171, 118, 130}, ++{175, 115, 131}, ++{182, 110, 133}, ++{191, 103, 136}, ++{202, 96, 139}, ++{213, 90, 143}, ++{225, 83, 146}, ++{235, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{184, 110, 133}, ++{193, 104, 136}, ++{203, 97, 139}, ++{214, 90, 143}, ++{226, 83, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{184, 110, 133}, ++{193, 104, 136}, ++{203, 97, 139}, ++{214, 90, 143}, ++{226, 83, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{184, 110, 133}, ++{193, 104, 136}, ++{203, 97, 139}, ++{214, 90, 143}, ++{226, 83, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{184, 110, 133}, ++{193, 104, 136}, ++{203, 97, 139}, ++{214, 90, 143}, ++{226, 83, 146}, ++{236, 77, 149}, ++{94, 93, 107}, ++{102, 91, 111}, ++{117, 87, 117}, ++{133, 82, 123}, ++{149, 76, 129}, ++{165, 71, 135}, ++{181, 65, 140}, ++{195, 60, 144}, ++{94, 93, 107}, ++{103, 91, 111}, ++{117, 87, 117}, ++{133, 82, 123}, ++{149, 76, 129}, ++{165, 71, 135}, ++{181, 65, 140}, ++{195, 60, 144}, ++{95, 93, 107}, ++{103, 91, 111}, ++{117, 87, 117}, ++{133, 82, 124}, ++{150, 77, 129}, ++{166, 71, 135}, ++{182, 65, 140}, ++{195, 60, 144}, ++{96, 94, 108}, ++{104, 92, 111}, ++{118, 88, 118}, ++{134, 83, 124}, ++{150, 77, 130}, ++{166, 71, 135}, ++{182, 65, 140}, ++{196, 60, 144}, ++{98, 95, 108}, ++{106, 93, 112}, ++{119, 88, 118}, ++{135, 83, 124}, ++{151, 77, 130}, ++{167, 71, 135}, ++{183, 66, 140}, ++{196, 60, 144}, ++{99, 96, 109}, ++{107, 94, 112}, ++{121, 89, 118}, ++{136, 84, 124}, ++{152, 78, 130}, ++{168, 72, 135}, ++{183, 66, 140}, ++{197, 61, 144}, ++{101, 97, 110}, ++{109, 95, 113}, ++{122, 90, 119}, ++{137, 84, 124}, ++{153, 78, 130}, ++{169, 72, 135}, ++{184, 66, 140}, ++{198, 61, 144}, ++{104, 99, 110}, ++{111, 96, 114}, ++{124, 91, 119}, ++{139, 85, 125}, ++{154, 79, 130}, ++{170, 73, 135}, ++{185, 67, 140}, ++{199, 62, 144}, ++{106, 100, 111}, ++{113, 97, 114}, ++{126, 92, 120}, ++{141, 86, 125}, ++{156, 80, 131}, ++{171, 73, 136}, ++{187, 67, 140}, ++{200, 62, 144}, ++{109, 101, 112}, ++{116, 98, 115}, ++{128, 93, 120}, ++{142, 87, 126}, ++{157, 80, 131}, ++{173, 74, 136}, ++{188, 68, 140}, ++{201, 63, 144}, ++{112, 102, 113}, ++{119, 99, 116}, ++{131, 94, 121}, ++{144, 88, 126}, ++{159, 81, 131}, ++{174, 75, 136}, ++{189, 69, 141}, ++{202, 63, 144}, ++{115, 104, 114}, ++{121, 100, 117}, ++{133, 95, 121}, ++{147, 88, 126}, ++{161, 82, 131}, ++{176, 76, 136}, ++{191, 69, 141}, ++{204, 64, 144}, ++{118, 105, 115}, ++{124, 101, 118}, ++{136, 96, 122}, ++{149, 89, 127}, ++{163, 83, 132}, ++{178, 76, 136}, ++{192, 70, 141}, ++{205, 65, 145}, ++{121, 106, 116}, ++{127, 103, 118}, ++{138, 97, 123}, ++{151, 90, 127}, ++{165, 84, 132}, ++{180, 77, 137}, ++{194, 71, 141}, ++{207, 65, 145}, ++{125, 107, 117}, ++{130, 104, 119}, ++{141, 98, 123}, ++{154, 91, 128}, ++{167, 85, 133}, ++{182, 78, 137}, ++{196, 71, 141}, ++{208, 66, 145}, ++{128, 108, 118}, ++{134, 105, 120}, ++{144, 99, 124}, ++{156, 92, 128}, ++{170, 85, 133}, ++{184, 79, 137}, ++{198, 72, 142}, ++{210, 67, 145}, ++{132, 109, 119}, ++{137, 106, 121}, ++{147, 100, 125}, ++{159, 93, 129}, ++{172, 86, 133}, ++{186, 80, 138}, ++{200, 73, 142}, ++{212, 67, 145}, ++{135, 110, 120}, ++{140, 106, 122}, ++{150, 101, 125}, ++{162, 94, 129}, ++{175, 87, 134}, ++{188, 80, 138}, ++{202, 74, 142}, ++{214, 68, 145}, ++{139, 111, 121}, ++{144, 107, 123}, ++{153, 102, 126}, ++{165, 95, 130}, ++{177, 88, 134}, ++{190, 81, 138}, ++{204, 75, 142}, ++{216, 69, 146}, ++{142, 111, 121}, ++{147, 108, 123}, ++{156, 102, 127}, ++{167, 96, 130}, ++{180, 89, 134}, ++{193, 82, 138}, ++{206, 75, 142}, ++{218, 70, 146}, ++{146, 112, 122}, ++{151, 109, 124}, ++{160, 103, 127}, ++{170, 97, 131}, ++{182, 90, 135}, ++{195, 83, 139}, ++{208, 76, 143}, ++{220, 71, 146}, ++{150, 113, 123}, ++{154, 110, 125}, ++{163, 104, 128}, ++{173, 98, 131}, ++{185, 91, 135}, ++{198, 84, 139}, ++{211, 77, 143}, ++{222, 71, 146}, ++{154, 114, 124}, ++{158, 111, 126}, ++{166, 105, 128}, ++{177, 98, 132}, ++{188, 92, 136}, ++{200, 85, 139}, ++{213, 78, 143}, ++{224, 72, 146}, ++{157, 114, 125}, ++{162, 111, 126}, ++{170, 106, 129}, ++{180, 99, 132}, ++{191, 92, 136}, ++{203, 86, 140}, ++{215, 79, 143}, ++{226, 73, 147}, ++{161, 115, 126}, ++{165, 112, 127}, ++{173, 106, 130}, ++{183, 100, 133}, ++{194, 93, 136}, ++{206, 86, 140}, ++{218, 80, 144}, ++{229, 74, 147}, ++{165, 115, 126}, ++{169, 113, 128}, ++{176, 107, 130}, ++{186, 101, 133}, ++{197, 94, 137}, ++{208, 87, 140}, ++{220, 80, 144}, ++{231, 75, 147}, ++{169, 116, 127}, ++{172, 113, 128}, ++{180, 108, 131}, ++{189, 102, 134}, ++{200, 95, 137}, ++{211, 88, 141}, ++{223, 81, 144}, ++{234, 75, 147}, ++{172, 117, 128}, ++{176, 114, 129}, ++{183, 109, 132}, ++{192, 102, 134}, ++{203, 96, 138}, ++{214, 89, 141}, ++{226, 82, 145}, ++{236, 76, 147}, ++{174, 117, 128}, ++{178, 114, 129}, ++{185, 109, 132}, ++{194, 103, 135}, ++{204, 96, 138}, ++{215, 89, 141}, ++{227, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{178, 114, 129}, ++{185, 109, 132}, ++{194, 103, 135}, ++{204, 96, 138}, ++{215, 89, 141}, ++{227, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{178, 114, 129}, ++{185, 109, 132}, ++{194, 103, 135}, ++{204, 96, 138}, ++{215, 89, 141}, ++{227, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{178, 114, 129}, ++{185, 109, 132}, ++{194, 103, 135}, ++{204, 96, 138}, ++{215, 89, 141}, ++{227, 82, 145}, ++{237, 77, 148}, ++{97, 90, 104}, ++{105, 89, 108}, ++{119, 85, 115}, ++{135, 80, 121}, ++{151, 75, 127}, ++{167, 70, 133}, ++{183, 64, 138}, ++{196, 59, 142}, ++{97, 90, 104}, ++{105, 89, 108}, ++{119, 85, 115}, ++{135, 81, 121}, ++{151, 75, 127}, ++{167, 70, 133}, ++{183, 64, 138}, ++{196, 59, 142}, ++{98, 91, 105}, ++{106, 89, 109}, ++{120, 86, 115}, ++{135, 81, 121}, ++{151, 75, 127}, ++{167, 70, 133}, ++{183, 64, 138}, ++{197, 59, 142}, ++{99, 92, 105}, ++{107, 90, 109}, ++{120, 86, 115}, ++{136, 81, 121}, ++{152, 76, 127}, ++{168, 70, 133}, ++{184, 64, 138}, ++{197, 60, 142}, ++{100, 93, 106}, ++{108, 91, 109}, ++{122, 87, 115}, ++{137, 82, 122}, ++{153, 76, 127}, ++{168, 70, 133}, ++{184, 65, 138}, ++{198, 60, 142}, ++{102, 94, 106}, ++{110, 92, 110}, ++{123, 87, 116}, ++{138, 82, 122}, ++{154, 77, 128}, ++{169, 71, 133}, ++{185, 65, 138}, ++{198, 60, 142}, ++{104, 95, 107}, ++{111, 93, 111}, ++{124, 88, 116}, ++{139, 83, 122}, ++{155, 77, 128}, ++{170, 71, 133}, ++{186, 66, 138}, ++{199, 61, 142}, ++{106, 96, 108}, ++{114, 94, 111}, ++{126, 89, 117}, ++{141, 84, 123}, ++{156, 78, 128}, ++{171, 72, 133}, ++{187, 66, 138}, ++{200, 61, 142}, ++{109, 97, 109}, ++{116, 95, 112}, ++{128, 90, 117}, ++{142, 84, 123}, ++{158, 79, 128}, ++{173, 73, 134}, ++{188, 67, 138}, ++{201, 61, 142}, ++{111, 99, 110}, ++{118, 96, 113}, ++{130, 91, 118}, ++{144, 85, 123}, ++{159, 79, 129}, ++{174, 73, 134}, ++{189, 67, 138}, ++{202, 62, 142}, ++{114, 100, 111}, ++{121, 97, 114}, ++{133, 92, 119}, ++{146, 86, 124}, ++{161, 80, 129}, ++{176, 74, 134}, ++{191, 68, 139}, ++{203, 63, 143}, ++{117, 101, 112}, ++{124, 98, 115}, ++{135, 93, 119}, ++{148, 87, 124}, ++{163, 81, 129}, ++{177, 75, 134}, ++{192, 68, 139}, ++{205, 63, 143}, ++{120, 103, 113}, ++{126, 100, 115}, ++{137, 94, 120}, ++{151, 88, 125}, ++{165, 82, 130}, ++{179, 75, 135}, ++{194, 69, 139}, ++{206, 64, 143}, ++{124, 104, 114}, ++{129, 101, 116}, ++{140, 95, 120}, ++{153, 89, 125}, ++{167, 83, 130}, ++{181, 76, 135}, ++{195, 70, 139}, ++{208, 65, 143}, ++{127, 105, 115}, ++{132, 102, 117}, ++{143, 96, 121}, ++{155, 90, 126}, ++{169, 83, 131}, ++{183, 77, 135}, ++{197, 71, 139}, ++{209, 65, 143}, ++{130, 106, 116}, ++{136, 103, 118}, ++{146, 97, 122}, ++{158, 91, 126}, ++{171, 84, 131}, ++{185, 78, 135}, ++{199, 71, 140}, ++{211, 66, 143}, ++{134, 107, 117}, ++{139, 104, 119}, ++{149, 98, 123}, ++{161, 92, 127}, ++{174, 85, 131}, ++{187, 79, 136}, ++{201, 72, 140}, ++{213, 67, 144}, ++{137, 108, 118}, ++{142, 105, 120}, ++{152, 99, 123}, ++{163, 93, 127}, ++{176, 86, 132}, ++{189, 80, 136}, ++{203, 73, 140}, ++{215, 68, 144}, ++{141, 109, 119}, ++{146, 106, 120}, ++{155, 100, 124}, ++{166, 94, 128}, ++{179, 87, 132}, ++{192, 80, 136}, ++{205, 74, 140}, ++{217, 68, 144}, ++{144, 110, 119}, ++{149, 107, 121}, ++{158, 101, 125}, ++{169, 95, 128}, ++{181, 88, 133}, ++{194, 81, 137}, ++{207, 75, 141}, ++{219, 69, 144}, ++{148, 111, 120}, ++{152, 108, 122}, ++{161, 102, 125}, ++{172, 96, 129}, ++{184, 89, 133}, ++{196, 82, 137}, ++{209, 76, 141}, ++{221, 70, 144}, ++{151, 111, 121}, ++{156, 108, 123}, ++{164, 103, 126}, ++{175, 97, 130}, ++{187, 90, 133}, ++{199, 83, 137}, ++{212, 76, 141}, ++{223, 71, 145}, ++{155, 112, 122}, ++{160, 109, 124}, ++{168, 104, 127}, ++{178, 97, 130}, ++{189, 91, 134}, ++{202, 84, 138}, ++{214, 77, 142}, ++{225, 72, 145}, ++{159, 113, 123}, ++{163, 110, 124}, ++{171, 105, 127}, ++{181, 98, 131}, ++{192, 92, 134}, ++{204, 85, 138}, ++{217, 78, 142}, ++{228, 72, 145}, ++{163, 113, 124}, ++{167, 111, 125}, ++{174, 105, 128}, ++{184, 99, 131}, ++{195, 92, 135}, ++{207, 86, 138}, ++{219, 79, 142}, ++{230, 73, 145}, ++{166, 114, 124}, ++{170, 111, 126}, ++{178, 106, 129}, ++{187, 100, 132}, ++{198, 93, 135}, ++{210, 86, 139}, ++{222, 80, 142}, ++{232, 74, 146}, ++{170, 115, 125}, ++{174, 112, 127}, ++{181, 107, 129}, ++{191, 101, 132}, ++{201, 94, 136}, ++{212, 87, 139}, ++{224, 81, 143}, ++{235, 75, 146}, ++{174, 115, 126}, ++{178, 112, 127}, ++{185, 107, 130}, ++{194, 101, 133}, ++{204, 95, 136}, ++{215, 88, 140}, ++{227, 81, 143}, ++{237, 76, 146}, ++{176, 116, 126}, ++{179, 113, 128}, ++{186, 108, 130}, ++{195, 102, 133}, ++{206, 95, 136}, ++{217, 88, 140}, ++{228, 82, 143}, ++{238, 76, 146}, ++{176, 116, 126}, ++{179, 113, 128}, ++{186, 108, 130}, ++{195, 102, 133}, ++{206, 95, 136}, ++{217, 88, 140}, ++{228, 82, 143}, ++{238, 76, 146}, ++{176, 116, 126}, ++{179, 113, 128}, ++{186, 108, 130}, ++{195, 102, 133}, ++{206, 95, 136}, ++{217, 88, 140}, ++{228, 82, 143}, ++{238, 76, 146}, ++{176, 116, 126}, ++{179, 113, 128}, ++{186, 108, 130}, ++{195, 102, 133}, ++{206, 95, 136}, ++{217, 88, 140}, ++{228, 82, 143}, ++{238, 76, 146}, ++{100, 87, 102}, ++{108, 86, 106}, ++{121, 83, 112}, ++{137, 79, 119}, ++{153, 74, 125}, ++{168, 69, 130}, ++{184, 63, 136}, ++{198, 58, 140}, ++{100, 88, 102}, ++{108, 86, 106}, ++{121, 83, 112}, ++{137, 79, 119}, ++{153, 74, 125}, ++{169, 69, 130}, ++{184, 63, 136}, ++{198, 58, 140}, ++{101, 88, 102}, ++{108, 87, 106}, ++{122, 84, 112}, ++{137, 79, 119}, ++{153, 74, 125}, ++{169, 69, 131}, ++{185, 63, 136}, ++{198, 59, 140}, ++{102, 89, 103}, ++{109, 87, 107}, ++{123, 84, 113}, ++{138, 80, 119}, ++{154, 75, 125}, ++{169, 69, 131}, ++{185, 64, 136}, ++{198, 59, 140}, ++{103, 90, 103}, ++{111, 88, 107}, ++{124, 85, 113}, ++{139, 80, 119}, ++{154, 75, 125}, ++{170, 69, 131}, ++{186, 64, 136}, ++{199, 59, 140}, ++{105, 91, 104}, ++{112, 89, 108}, ++{125, 86, 113}, ++{140, 81, 120}, ++{155, 75, 125}, ++{171, 70, 131}, ++{186, 64, 136}, ++{200, 59, 140}, ++{107, 92, 105}, ++{114, 90, 108}, ++{127, 86, 114}, ++{141, 81, 120}, ++{157, 76, 126}, ++{172, 70, 131}, ++{187, 65, 136}, ++{200, 60, 140}, ++{109, 94, 106}, ++{116, 91, 109}, ++{128, 87, 114}, ++{143, 82, 120}, ++{158, 77, 126}, ++{173, 71, 131}, ++{188, 65, 136}, ++{201, 60, 140}, ++{111, 95, 107}, ++{118, 93, 110}, ++{130, 88, 115}, ++{144, 83, 121}, ++{159, 77, 126}, ++{174, 72, 131}, ++{189, 66, 136}, ++{202, 61, 140}, ++{114, 96, 108}, ++{121, 94, 111}, ++{132, 89, 116}, ++{146, 84, 121}, ++{161, 78, 127}, ++{176, 72, 132}, ++{191, 66, 137}, ++{204, 61, 141}, ++{117, 98, 108}, ++{123, 95, 111}, ++{135, 90, 116}, ++{148, 85, 122}, ++{163, 79, 127}, ++{177, 73, 132}, ++{192, 67, 137}, ++{205, 62, 141}, ++{120, 99, 109}, ++{126, 96, 112}, ++{137, 91, 117}, ++{150, 86, 122}, ++{164, 80, 127}, ++{179, 74, 132}, ++{193, 68, 137}, ++{206, 63, 141}, ++{123, 100, 110}, ++{129, 98, 113}, ++{139, 93, 118}, ++{152, 87, 123}, ++{166, 81, 128}, ++{181, 74, 133}, ++{195, 68, 137}, ++{208, 63, 141}, ++{126, 102, 111}, ++{132, 99, 114}, ++{142, 94, 118}, ++{155, 88, 123}, ++{168, 81, 128}, ++{182, 75, 133}, ++{197, 69, 137}, ++{209, 64, 141}, ++{129, 103, 112}, ++{135, 100, 115}, ++{145, 95, 119}, ++{157, 89, 124}, ++{171, 82, 128}, ++{184, 76, 133}, ++{198, 70, 138}, ++{211, 65, 141}, ++{132, 104, 113}, ++{138, 101, 116}, ++{148, 96, 120}, ++{160, 90, 124}, ++{173, 83, 129}, ++{186, 77, 133}, ++{200, 71, 138}, ++{212, 65, 142}, ++{136, 105, 114}, ++{141, 102, 117}, ++{151, 97, 120}, ++{162, 91, 125}, ++{175, 84, 129}, ++{189, 78, 134}, ++{202, 71, 138}, ++{214, 66, 142}, ++{139, 106, 115}, ++{144, 103, 117}, ++{154, 98, 121}, ++{165, 92, 125}, ++{178, 85, 130}, ++{191, 79, 134}, ++{204, 72, 138}, ++{216, 67, 142}, ++{143, 107, 116}, ++{147, 104, 118}, ++{157, 99, 122}, ++{168, 93, 126}, ++{180, 86, 130}, ++{193, 80, 135}, ++{206, 73, 139}, ++{218, 68, 142}, ++{146, 108, 117}, ++{151, 105, 119}, ++{160, 100, 123}, ++{171, 94, 126}, ++{183, 87, 131}, ++{195, 80, 135}, ++{208, 74, 139}, ++{220, 68, 142}, ++{150, 109, 118}, ++{154, 106, 120}, ++{163, 101, 123}, ++{173, 94, 127}, ++{185, 88, 131}, ++{198, 81, 135}, ++{211, 75, 139}, ++{222, 69, 143}, ++{153, 110, 119}, ++{158, 107, 121}, ++{166, 102, 124}, ++{176, 95, 128}, ++{188, 89, 132}, ++{200, 82, 136}, ++{213, 76, 140}, ++{224, 70, 143}, ++{157, 111, 120}, ++{161, 108, 122}, ++{169, 102, 125}, ++{179, 96, 128}, ++{191, 90, 132}, ++{203, 83, 136}, ++{215, 76, 140}, ++{226, 71, 143}, ++{161, 111, 121}, ++{165, 108, 122}, ++{173, 103, 125}, ++{183, 97, 129}, ++{194, 91, 133}, ++{205, 84, 136}, ++{218, 77, 140}, ++{229, 72, 143}, ++{164, 112, 122}, ++{168, 109, 123}, ++{176, 104, 126}, ++{186, 98, 129}, ++{196, 91, 133}, ++{208, 85, 137}, ++{220, 78, 140}, ++{231, 73, 144}, ++{168, 113, 123}, ++{172, 110, 124}, ++{179, 105, 127}, ++{189, 99, 130}, ++{199, 92, 133}, ++{211, 86, 137}, ++{223, 79, 141}, ++{233, 73, 144}, ++{172, 113, 123}, ++{175, 111, 125}, ++{183, 106, 127}, ++{192, 100, 131}, ++{202, 93, 134}, ++{214, 86, 138}, ++{225, 80, 141}, ++{236, 74, 144}, ++{175, 114, 124}, ++{179, 111, 126}, ++{186, 106, 128}, ++{195, 100, 131}, ++{205, 94, 134}, ++{216, 87, 138}, ++{228, 81, 141}, ++{238, 75, 144}, ++{177, 114, 125}, ++{181, 112, 126}, ++{188, 107, 128}, ++{197, 101, 131}, ++{207, 94, 135}, ++{218, 88, 138}, ++{229, 81, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{181, 112, 126}, ++{188, 107, 128}, ++{197, 101, 131}, ++{207, 94, 135}, ++{218, 88, 138}, ++{229, 81, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{181, 112, 126}, ++{188, 107, 128}, ++{197, 101, 131}, ++{207, 94, 135}, ++{218, 88, 138}, ++{229, 81, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{181, 112, 126}, ++{188, 107, 128}, ++{197, 101, 131}, ++{207, 94, 135}, ++{218, 88, 138}, ++{229, 81, 142}, ++{239, 75, 145}, ++{102, 85, 100}, ++{110, 84, 104}, ++{124, 81, 110}, ++{139, 77, 116}, ++{154, 73, 122}, ++{170, 68, 128}, ++{186, 62, 134}, ++{199, 58, 138}, ++{103, 85, 100}, ++{111, 84, 104}, ++{124, 81, 110}, ++{139, 78, 116}, ++{155, 73, 123}, ++{170, 68, 128}, ++{186, 62, 134}, ++{199, 58, 138}, ++{103, 85, 100}, ++{111, 84, 104}, ++{124, 82, 110}, ++{139, 78, 116}, ++{155, 73, 123}, ++{171, 68, 128}, ++{186, 63, 134}, ++{199, 58, 138}, ++{104, 86, 100}, ++{112, 85, 104}, ++{125, 82, 110}, ++{140, 78, 117}, ++{156, 73, 123}, ++{171, 68, 128}, ++{187, 63, 134}, ++{200, 58, 138}, ++{106, 87, 101}, ++{113, 86, 105}, ++{126, 83, 111}, ++{141, 79, 117}, ++{156, 74, 123}, ++{172, 68, 129}, ++{187, 63, 134}, ++{200, 58, 138}, ++{108, 88, 102}, ++{115, 87, 105}, ++{127, 84, 111}, ++{142, 79, 117}, ++{157, 74, 123}, ++{173, 69, 129}, ++{188, 63, 134}, ++{201, 59, 138}, ++{109, 90, 102}, ++{117, 88, 106}, ++{129, 85, 112}, ++{143, 80, 118}, ++{158, 75, 123}, ++{174, 69, 129}, ++{189, 64, 134}, ++{202, 59, 138}, ++{112, 91, 103}, ++{118, 89, 107}, ++{131, 85, 112}, ++{145, 81, 118}, ++{160, 75, 124}, ++{175, 70, 129}, ++{190, 64, 134}, ++{203, 60, 138}, ++{114, 93, 104}, ++{121, 90, 107}, ++{133, 87, 113}, ++{146, 82, 118}, ++{161, 76, 124}, ++{176, 71, 129}, ++{191, 65, 134}, ++{204, 60, 138}, ++{116, 94, 105}, ++{123, 92, 108}, ++{135, 88, 113}, ++{148, 82, 119}, ++{163, 77, 124}, ++{177, 71, 130}, ++{192, 66, 135}, ++{205, 61, 139}, ++{119, 95, 106}, ++{125, 93, 109}, ++{137, 89, 114}, ++{150, 83, 119}, ++{164, 78, 125}, ++{179, 72, 130}, ++{193, 66, 135}, ++{206, 61, 139}, ++{122, 97, 107}, ++{128, 94, 110}, ++{139, 90, 115}, ++{152, 84, 120}, ++{166, 79, 125}, ++{180, 73, 130}, ++{195, 67, 135}, ++{208, 62, 139}, ++{125, 98, 108}, ++{131, 96, 111}, ++{142, 91, 115}, ++{154, 85, 120}, ++{168, 79, 126}, ++{182, 73, 130}, ++{196, 68, 135}, ++{209, 62, 139}, ++{128, 99, 109}, ++{134, 97, 112}, ++{144, 92, 116}, ++{157, 86, 121}, ++{170, 80, 126}, ++{184, 74, 131}, ++{198, 68, 135}, ++{210, 63, 139}, ++{131, 101, 110}, ++{137, 98, 113}, ++{147, 93, 117}, ++{159, 87, 122}, ++{172, 81, 126}, ++{186, 75, 131}, ++{200, 69, 136}, ++{212, 64, 140}, ++{134, 102, 111}, ++{140, 99, 114}, ++{150, 94, 117}, ++{161, 88, 122}, ++{174, 82, 127}, ++{188, 76, 131}, ++{202, 70, 136}, ++{214, 65, 140}, ++{138, 103, 112}, ++{143, 100, 114}, ++{152, 95, 118}, ++{164, 89, 123}, ++{177, 83, 127}, ++{190, 77, 132}, ++{204, 71, 136}, ++{216, 65, 140}, ++{141, 104, 113}, ++{146, 101, 115}, ++{155, 96, 119}, ++{167, 90, 123}, ++{179, 84, 128}, ++{192, 78, 132}, ++{206, 71, 137}, ++{217, 66, 140}, ++{145, 105, 114}, ++{149, 102, 116}, ++{158, 97, 120}, ++{169, 91, 124}, ++{182, 85, 128}, ++{195, 79, 133}, ++{208, 72, 137}, ++{219, 67, 140}, ++{148, 106, 115}, ++{153, 103, 117}, ++{161, 98, 120}, ++{172, 92, 124}, ++{184, 86, 129}, ++{197, 79, 133}, ++{210, 73, 137}, ++{221, 68, 141}, ++{152, 107, 116}, ++{156, 104, 118}, ++{165, 99, 121}, ++{175, 93, 125}, ++{187, 87, 129}, ++{199, 80, 133}, ++{212, 74, 137}, ++{223, 68, 141}, ++{155, 108, 117}, ++{159, 105, 119}, ++{168, 100, 122}, ++{178, 94, 126}, ++{190, 88, 130}, ++{202, 81, 134}, ++{214, 75, 138}, ++{225, 69, 141}, ++{159, 109, 118}, ++{163, 106, 120}, ++{171, 101, 123}, ++{181, 95, 126}, ++{192, 89, 130}, ++{204, 82, 134}, ++{217, 76, 138}, ++{228, 70, 142}, ++{162, 110, 119}, ++{166, 107, 121}, ++{174, 102, 123}, ++{184, 96, 127}, ++{195, 89, 131}, ++{207, 83, 135}, ++{219, 77, 138}, ++{230, 71, 142}, ++{166, 110, 120}, ++{170, 108, 121}, ++{178, 103, 124}, ++{187, 97, 128}, ++{198, 90, 131}, ++{209, 84, 135}, ++{221, 77, 139}, ++{232, 72, 142}, ++{170, 111, 121}, ++{173, 108, 122}, ++{181, 104, 125}, ++{190, 98, 128}, ++{201, 91, 132}, ++{212, 85, 135}, ++{224, 78, 139}, ++{235, 73, 142}, ++{173, 112, 122}, ++{177, 109, 123}, ++{184, 104, 126}, ++{193, 98, 129}, ++{204, 92, 132}, ++{215, 86, 136}, ++{226, 79, 139}, ++{237, 73, 143}, ++{177, 112, 122}, ++{181, 110, 124}, ++{188, 105, 126}, ++{197, 99, 129}, ++{207, 93, 133}, ++{218, 86, 136}, ++{229, 80, 140}, ++{239, 74, 143}, ++{179, 113, 123}, ++{182, 110, 124}, ++{189, 105, 127}, ++{198, 100, 130}, ++{208, 93, 133}, ++{219, 87, 136}, ++{230, 80, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{182, 110, 124}, ++{189, 105, 127}, ++{198, 100, 130}, ++{208, 93, 133}, ++{219, 87, 136}, ++{230, 80, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{182, 110, 124}, ++{189, 105, 127}, ++{198, 100, 130}, ++{208, 93, 133}, ++{219, 87, 136}, ++{230, 80, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{182, 110, 124}, ++{189, 105, 127}, ++{198, 100, 130}, ++{208, 93, 133}, ++{219, 87, 136}, ++{230, 80, 140}, ++{241, 75, 143}, ++{105, 82, 97}, ++{113, 81, 101}, ++{126, 79, 107}, ++{141, 76, 114}, ++{156, 71, 120}, ++{172, 66, 126}, ++{187, 61, 131}, ++{201, 57, 136}, ++{106, 82, 97}, ++{113, 82, 101}, ++{126, 79, 107}, ++{141, 76, 114}, ++{157, 71, 120}, ++{172, 67, 126}, ++{187, 61, 131}, ++{201, 57, 136}, ++{106, 83, 98}, ++{114, 82, 101}, ++{127, 80, 108}, ++{142, 76, 114}, ++{157, 72, 120}, ++{172, 67, 126}, ++{188, 62, 131}, ++{201, 57, 136}, ++{107, 84, 98}, ++{115, 83, 102}, ++{128, 80, 108}, ++{142, 77, 114}, ++{157, 72, 120}, ++{173, 67, 126}, ++{188, 62, 132}, ++{201, 57, 136}, ++{109, 85, 99}, ++{116, 84, 102}, ++{129, 81, 108}, ++{143, 77, 115}, ++{158, 72, 121}, ++{174, 67, 126}, ++{189, 62, 132}, ++{202, 58, 136}, ++{110, 86, 99}, ++{117, 85, 103}, ++{130, 82, 109}, ++{144, 78, 115}, ++{159, 73, 121}, ++{174, 68, 127}, ++{189, 63, 132}, ++{203, 58, 136}, ++{112, 87, 100}, ++{119, 86, 104}, ++{131, 83, 109}, ++{145, 78, 115}, ++{160, 73, 121}, ++{175, 68, 127}, ++{190, 63, 132}, ++{203, 58, 136}, ++{114, 89, 101}, ++{121, 87, 104}, ++{133, 84, 110}, ++{147, 79, 116}, ++{162, 74, 121}, ++{176, 69, 127}, ++{191, 63, 132}, ++{204, 59, 136}, ++{117, 90, 102}, ++{123, 88, 105}, ++{135, 85, 110}, ++{148, 80, 116}, ++{163, 75, 122}, ++{178, 69, 127}, ++{192, 64, 132}, ++{205, 59, 136}, ++{119, 92, 103}, ++{125, 90, 106}, ++{137, 86, 111}, ++{150, 81, 117}, ++{164, 76, 122}, ++{179, 70, 127}, ++{194, 65, 133}, ++{206, 60, 137}, ++{122, 93, 104}, ++{128, 91, 107}, ++{139, 87, 112}, ++{152, 82, 117}, ++{166, 76, 123}, ++{181, 71, 128}, ++{195, 65, 133}, ++{208, 60, 137}, ++{124, 94, 105}, ++{130, 92, 108}, ++{141, 88, 112}, ++{154, 83, 118}, ++{168, 77, 123}, ++{182, 72, 128}, ++{196, 66, 133}, ++{209, 61, 137}, ++{127, 96, 106}, ++{133, 93, 109}, ++{144, 89, 113}, ++{156, 84, 118}, ++{170, 78, 123}, ++{184, 72, 128}, ++{198, 67, 133}, ++{210, 62, 137}, ++{130, 97, 107}, ++{136, 95, 109}, ++{146, 90, 114}, ++{158, 85, 119}, ++{172, 79, 124}, ++{186, 73, 129}, ++{200, 67, 134}, ++{212, 62, 137}, ++{133, 99, 108}, ++{139, 96, 110}, ++{149, 91, 115}, ++{161, 86, 119}, ++{174, 80, 124}, ++{188, 74, 129}, ++{201, 68, 134}, ++{213, 63, 138}, ++{137, 100, 109}, ++{142, 97, 111}, ++{152, 92, 115}, ++{163, 87, 120}, ++{176, 81, 125}, ++{190, 75, 130}, ++{203, 69, 134}, ++{215, 64, 138}, ++{140, 101, 110}, ++{145, 98, 112}, ++{154, 94, 116}, ++{166, 88, 121}, ++{178, 82, 125}, ++{192, 76, 130}, ++{205, 70, 134}, ++{217, 65, 138}, ++{143, 102, 111}, ++{148, 99, 113}, ++{157, 95, 117}, ++{168, 89, 121}, ++{181, 83, 126}, ++{194, 77, 130}, ++{207, 71, 135}, ++{219, 65, 138}, ++{147, 103, 112}, ++{151, 101, 114}, ++{160, 96, 118}, ++{171, 90, 122}, ++{183, 84, 126}, ++{196, 78, 131}, ++{209, 71, 135}, ++{221, 66, 139}, ++{150, 104, 113}, ++{155, 102, 115}, ++{163, 97, 118}, ++{174, 91, 122}, ++{186, 85, 127}, ++{198, 78, 131}, ++{211, 72, 135}, ++{223, 67, 139}, ++{154, 105, 114}, ++{158, 103, 116}, ++{166, 98, 119}, ++{177, 92, 123}, ++{188, 86, 127}, ++{201, 79, 132}, ++{213, 73, 136}, ++{225, 68, 139}, ++{157, 106, 115}, ++{161, 104, 117}, ++{169, 99, 120}, ++{180, 93, 124}, ++{191, 87, 128}, ++{203, 80, 132}, ++{216, 74, 136}, ++{227, 69, 140}, ++{161, 107, 116}, ++{165, 104, 118}, ++{173, 100, 121}, ++{183, 94, 124}, ++{194, 88, 128}, ++{206, 81, 132}, ++{218, 75, 136}, ++{229, 69, 140}, ++{164, 108, 117}, ++{168, 105, 119}, ++{176, 100, 121}, ++{186, 95, 125}, ++{197, 88, 129}, ++{208, 82, 133}, ++{220, 76, 137}, ++{231, 70, 140}, ++{168, 109, 118}, ++{172, 106, 119}, ++{179, 101, 122}, ++{189, 96, 126}, ++{199, 89, 129}, ++{211, 83, 133}, ++{223, 77, 137}, ++{233, 71, 140}, ++{171, 110, 119}, ++{175, 107, 120}, ++{182, 102, 123}, ++{192, 96, 126}, ++{202, 90, 130}, ++{213, 84, 134}, ++{225, 77, 137}, ++{236, 72, 141}, ++{175, 110, 120}, ++{179, 108, 121}, ++{186, 103, 124}, ++{195, 97, 127}, ++{205, 91, 130}, ++{216, 85, 134}, ++{228, 78, 138}, ++{238, 73, 141}, ++{179, 111, 120}, ++{182, 108, 122}, ++{189, 104, 124}, ++{198, 98, 127}, ++{208, 92, 131}, ++{219, 85, 135}, ++{230, 79, 138}, ++{241, 74, 141}, ++{180, 111, 121}, ++{184, 109, 122}, ++{191, 104, 125}, ++{200, 98, 128}, ++{210, 92, 131}, ++{220, 86, 135}, ++{232, 79, 138}, ++{242, 74, 141}, ++{180, 111, 121}, ++{184, 109, 122}, ++{191, 104, 125}, ++{200, 98, 128}, ++{210, 92, 131}, ++{220, 86, 135}, ++{232, 79, 138}, ++{242, 74, 141}, ++{180, 111, 121}, ++{184, 109, 122}, ++{191, 104, 125}, ++{200, 98, 128}, ++{210, 92, 131}, ++{220, 86, 135}, ++{232, 79, 138}, ++{242, 74, 141}, ++{180, 111, 121}, ++{184, 109, 122}, ++{191, 104, 125}, ++{200, 98, 128}, ++{210, 92, 131}, ++{220, 86, 135}, ++{232, 79, 138}, ++{242, 74, 141}, ++{108, 79, 95}, ++{116, 79, 99}, ++{129, 77, 105}, ++{143, 74, 112}, ++{158, 70, 118}, ++{174, 65, 124}, ++{189, 60, 129}, ++{202, 56, 134}, ++{109, 80, 95}, ++{116, 79, 99}, ++{129, 77, 105}, ++{143, 74, 112}, ++{159, 70, 118}, ++{174, 65, 124}, ++{189, 60, 129}, ++{202, 56, 134}, ++{109, 80, 95}, ++{117, 80, 99}, ++{129, 78, 105}, ++{144, 74, 112}, ++{159, 70, 118}, ++{174, 66, 124}, ++{189, 61, 129}, ++{202, 56, 134}, ++{110, 81, 96}, ++{117, 80, 100}, ++{130, 78, 106}, ++{144, 75, 112}, ++{159, 71, 118}, ++{175, 66, 124}, ++{190, 61, 129}, ++{203, 56, 134}, ++{112, 82, 96}, ++{119, 81, 100}, ++{131, 79, 106}, ++{145, 75, 112}, ++{160, 71, 118}, ++{175, 66, 124}, ++{190, 61, 130}, ++{203, 57, 134}, ++{113, 83, 97}, ++{120, 82, 101}, ++{132, 80, 106}, ++{146, 76, 113}, ++{161, 72, 119}, ++{176, 67, 124}, ++{191, 62, 130}, ++{204, 57, 134}, ++{115, 85, 98}, ++{122, 83, 101}, ++{134, 81, 107}, ++{148, 77, 113}, ++{162, 72, 119}, ++{177, 67, 125}, ++{192, 62, 130}, ++{205, 57, 134}, ++{117, 86, 99}, ++{124, 85, 102}, ++{135, 82, 107}, ++{149, 78, 113}, ++{163, 73, 119}, ++{178, 68, 125}, ++{193, 62, 130}, ++{206, 58, 134}, ++{119, 88, 100}, ++{126, 86, 103}, ++{137, 83, 108}, ++{150, 78, 114}, ++{165, 74, 120}, ++{179, 68, 125}, ++{194, 63, 130}, ++{207, 58, 135}, ++{122, 89, 101}, ++{128, 87, 104}, ++{139, 84, 109}, ++{152, 79, 114}, ++{166, 74, 120}, ++{181, 69, 125}, ++{195, 64, 130}, ++{208, 59, 135}, ++{124, 91, 102}, ++{130, 89, 104}, ++{141, 85, 109}, ++{154, 80, 115}, ++{168, 75, 120}, ++{182, 70, 126}, ++{197, 64, 131}, ++{209, 59, 135}, ++{127, 92, 103}, ++{133, 90, 105}, ++{143, 86, 110}, ++{156, 81, 115}, ++{170, 76, 121}, ++{184, 70, 126}, ++{198, 65, 131}, ++{210, 60, 135}, ++{130, 94, 104}, ++{135, 91, 106}, ++{146, 87, 111}, ++{158, 82, 116}, ++{172, 77, 121}, ++{185, 71, 126}, ++{200, 66, 131}, ++{212, 61, 135}, ++{133, 95, 105}, ++{138, 93, 107}, ++{148, 88, 112}, ++{160, 83, 117}, ++{174, 78, 122}, ++{187, 72, 127}, ++{201, 66, 132}, ++{213, 61, 136}, ++{136, 96, 106}, ++{141, 94, 108}, ++{151, 90, 112}, ++{163, 84, 117}, ++{176, 79, 122}, ++{189, 73, 127}, ++{203, 67, 132}, ++{215, 62, 136}, ++{139, 98, 107}, ++{144, 95, 109}, ++{154, 91, 113}, ++{165, 85, 118}, ++{178, 80, 123}, ++{191, 74, 127}, ++{205, 68, 132}, ++{217, 63, 136}, ++{142, 99, 108}, ++{147, 96, 110}, ++{156, 92, 114}, ++{168, 86, 118}, ++{180, 81, 123}, ++{193, 75, 128}, ++{207, 69, 132}, ++{218, 64, 136}, ++{145, 100, 109}, ++{150, 98, 111}, ++{159, 93, 115}, ++{170, 87, 119}, ++{182, 82, 124}, ++{195, 76, 128}, ++{208, 70, 133}, ++{220, 64, 137}, ++{149, 101, 110}, ++{153, 99, 112}, ++{162, 94, 116}, ++{173, 89, 120}, ++{185, 83, 124}, ++{198, 77, 129}, ++{211, 70, 133}, ++{222, 65, 137}, ++{152, 102, 111}, ++{157, 100, 113}, ++{165, 95, 116}, ++{176, 90, 120}, ++{187, 84, 125}, ++{200, 77, 129}, ++{213, 71, 133}, ++{224, 66, 137}, ++{155, 103, 112}, ++{160, 101, 114}, ++{168, 96, 117}, ++{178, 91, 121}, ++{190, 84, 125}, ++{202, 78, 130}, ++{215, 72, 134}, ++{226, 67, 137}, ++{159, 104, 113}, ++{163, 102, 115}, ++{171, 97, 118}, ++{181, 91, 122}, ++{193, 85, 126}, ++{205, 79, 130}, ++{217, 73, 134}, ++{228, 68, 138}, ++{162, 105, 114}, ++{167, 103, 116}, ++{174, 98, 119}, ++{184, 92, 122}, ++{195, 86, 126}, ++{207, 80, 131}, ++{219, 74, 135}, ++{230, 69, 138}, ++{166, 106, 115}, ++{170, 104, 117}, ++{178, 99, 119}, ++{187, 93, 123}, ++{198, 87, 127}, ++{210, 81, 131}, ++{222, 75, 135}, ++{232, 69, 138}, ++{170, 107, 116}, ++{173, 105, 117}, ++{181, 100, 120}, ++{190, 94, 124}, ++{201, 88, 128}, ++{212, 82, 131}, ++{224, 76, 135}, ++{235, 70, 139}, ++{173, 108, 117}, ++{177, 105, 118}, ++{184, 101, 121}, ++{193, 95, 124}, ++{204, 89, 128}, ++{215, 83, 132}, ++{227, 77, 136}, ++{237, 71, 139}, ++{177, 109, 118}, ++{180, 106, 119}, ++{187, 102, 122}, ++{196, 96, 125}, ++{207, 90, 129}, ++{218, 84, 132}, ++{229, 77, 136}, ++{239, 72, 139}, ++{180, 109, 119}, ++{184, 107, 120}, ++{191, 102, 123}, ++{200, 97, 126}, ++{209, 91, 129}, ++{220, 85, 133}, ++{232, 78, 136}, ++{242, 73, 140}, ++{182, 110, 119}, ++{186, 107, 120}, ++{192, 103, 123}, ++{201, 97, 126}, ++{211, 91, 129}, ++{222, 85, 133}, ++{233, 79, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 120}, ++{192, 103, 123}, ++{201, 97, 126}, ++{211, 91, 129}, ++{222, 85, 133}, ++{233, 79, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 120}, ++{192, 103, 123}, ++{201, 97, 126}, ++{211, 91, 129}, ++{222, 85, 133}, ++{233, 79, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 120}, ++{192, 103, 123}, ++{201, 97, 126}, ++{211, 91, 129}, ++{222, 85, 133}, ++{233, 79, 137}, ++{243, 73, 140}, ++{111, 77, 93}, ++{118, 77, 97}, ++{131, 75, 103}, ++{145, 72, 109}, ++{160, 69, 116}, ++{176, 64, 122}, ++{191, 59, 127}, ++{204, 55, 132}, ++{112, 77, 93}, ++{119, 77, 97}, ++{131, 75, 103}, ++{145, 72, 109}, ++{160, 69, 116}, ++{176, 64, 122}, ++{191, 59, 127}, ++{204, 55, 132}, ++{112, 78, 93}, ++{119, 77, 97}, ++{132, 76, 103}, ++{146, 73, 110}, ++{161, 69, 116}, ++{176, 64, 122}, ++{191, 60, 127}, ++{204, 55, 132}, ++{113, 78, 94}, ++{120, 78, 97}, ++{132, 76, 103}, ++{147, 73, 110}, ++{161, 69, 116}, ++{176, 65, 122}, ++{191, 60, 127}, ++{204, 55, 132}, ++{114, 79, 94}, ++{121, 79, 98}, ++{133, 77, 104}, ++{147, 74, 110}, ++{162, 70, 116}, ++{177, 65, 122}, ++{192, 60, 127}, ++{205, 56, 132}, ++{116, 81, 95}, ++{123, 80, 98}, ++{135, 78, 104}, ++{148, 74, 110}, ++{163, 70, 116}, ++{178, 65, 122}, ++{193, 61, 128}, ++{206, 56, 132}, ++{118, 82, 96}, ++{124, 81, 99}, ++{136, 79, 105}, ++{150, 75, 111}, ++{164, 71, 117}, ++{179, 66, 122}, ++{194, 61, 128}, ++{206, 57, 132}, ++{120, 83, 97}, ++{126, 82, 100}, ++{138, 80, 105}, ++{151, 76, 111}, ++{165, 71, 117}, ++{180, 67, 123}, ++{195, 61, 128}, ++{207, 57, 132}, ++{122, 85, 97}, ++{128, 84, 101}, ++{139, 81, 106}, ++{153, 77, 112}, ++{167, 72, 117}, ++{181, 67, 123}, ++{196, 62, 128}, ++{208, 57, 133}, ++{124, 87, 98}, ++{130, 85, 101}, ++{141, 82, 106}, ++{154, 78, 112}, ++{168, 73, 118}, ++{182, 68, 123}, ++{197, 63, 128}, ++{209, 58, 133}, ++{127, 88, 99}, ++{133, 86, 102}, ++{143, 83, 107}, ++{156, 79, 113}, ++{170, 74, 118}, ++{184, 69, 124}, ++{198, 63, 129}, ++{211, 59, 133}, ++{129, 90, 100}, ++{135, 88, 103}, ++{146, 84, 108}, ++{158, 80, 113}, ++{172, 75, 119}, ++{185, 69, 124}, ++{200, 64, 129}, ++{212, 59, 133}, ++{132, 91, 102}, ++{138, 89, 104}, ++{148, 85, 109}, ++{160, 81, 114}, ++{173, 76, 119}, ++{187, 70, 124}, ++{201, 65, 129}, ++{213, 60, 133}, ++{135, 93, 103}, ++{140, 91, 105}, ++{150, 87, 109}, ++{162, 82, 114}, ++{175, 76, 120}, ++{189, 71, 125}, ++{203, 65, 130}, ++{215, 61, 134}, ++{138, 94, 104}, ++{143, 92, 106}, ++{153, 88, 110}, ++{165, 83, 115}, ++{177, 77, 120}, ++{191, 72, 125}, ++{204, 66, 130}, ++{216, 61, 134}, ++{141, 95, 105}, ++{146, 93, 107}, ++{156, 89, 111}, ++{167, 84, 116}, ++{180, 78, 121}, ++{193, 73, 125}, ++{206, 67, 130}, ++{218, 62, 134}, ++{144, 97, 106}, ++{149, 94, 108}, ++{158, 90, 112}, ++{170, 85, 116}, ++{182, 79, 121}, ++{195, 74, 126}, ++{208, 68, 131}, ++{220, 63, 134}, ++{148, 98, 107}, ++{152, 96, 109}, ++{161, 91, 113}, ++{172, 86, 117}, ++{184, 80, 122}, ++{197, 75, 126}, ++{210, 69, 131}, ++{221, 64, 135}, ++{151, 99, 108}, ++{155, 97, 110}, ++{164, 92, 113}, ++{175, 87, 118}, ++{187, 81, 122}, ++{199, 75, 127}, ++{212, 70, 131}, ++{223, 64, 135}, ++{154, 100, 109}, ++{159, 98, 111}, ++{167, 93, 114}, ++{177, 88, 118}, ++{189, 82, 123}, ++{201, 76, 127}, ++{214, 70, 132}, ++{225, 65, 135}, ++{157, 101, 110}, ++{162, 99, 112}, ++{170, 95, 115}, ++{180, 89, 119}, ++{192, 83, 123}, ++{204, 77, 128}, ++{216, 71, 132}, ++{227, 66, 136}, ++{161, 103, 111}, ++{165, 100, 113}, ++{173, 96, 116}, ++{183, 90, 120}, ++{194, 84, 124}, ++{206, 78, 128}, ++{218, 72, 132}, ++{229, 67, 136}, ++{164, 104, 112}, ++{168, 101, 114}, ++{176, 97, 117}, ++{186, 91, 120}, ++{197, 85, 124}, ++{209, 79, 129}, ++{221, 73, 133}, ++{232, 68, 136}, ++{168, 104, 113}, ++{172, 102, 115}, ++{179, 98, 118}, ++{189, 92, 121}, ++{200, 86, 125}, ++{211, 80, 129}, ++{223, 74, 133}, ++{234, 69, 137}, ++{171, 105, 114}, ++{175, 103, 115}, ++{183, 98, 118}, ++{192, 93, 122}, ++{202, 87, 126}, ++{214, 81, 130}, ++{225, 75, 134}, ++{236, 69, 137}, ++{175, 106, 115}, ++{179, 104, 116}, ++{186, 99, 119}, ++{195, 94, 122}, ++{205, 88, 126}, ++{216, 82, 130}, ++{228, 76, 134}, ++{238, 70, 137}, ++{178, 107, 116}, ++{182, 105, 117}, ++{189, 100, 120}, ++{198, 95, 123}, ++{208, 89, 127}, ++{219, 83, 131}, ++{230, 76, 134}, ++{241, 71, 138}, ++{182, 108, 117}, ++{186, 105, 118}, ++{192, 101, 121}, ++{201, 96, 124}, ++{211, 90, 127}, ++{222, 84, 131}, ++{233, 77, 135}, ++{243, 72, 138}, ++{184, 108, 117}, ++{187, 106, 118}, ++{194, 101, 121}, ++{203, 96, 124}, ++{212, 90, 128}, ++{223, 84, 131}, ++{234, 78, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{187, 106, 118}, ++{194, 101, 121}, ++{203, 96, 124}, ++{212, 90, 128}, ++{223, 84, 131}, ++{234, 78, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{187, 106, 118}, ++{194, 101, 121}, ++{203, 96, 124}, ++{212, 90, 128}, ++{223, 84, 131}, ++{234, 78, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{187, 106, 118}, ++{194, 101, 121}, ++{203, 96, 124}, ++{212, 90, 128}, ++{223, 84, 131}, ++{234, 78, 135}, ++{244, 72, 138}, ++{114, 74, 91}, ++{121, 74, 94}, ++{133, 73, 100}, ++{148, 71, 107}, ++{162, 67, 113}, ++{177, 63, 119}, ++{192, 58, 125}, ++{205, 54, 130}, ++{115, 74, 91}, ++{121, 74, 95}, ++{134, 73, 101}, ++{148, 71, 107}, ++{163, 67, 113}, ++{177, 63, 120}, ++{192, 58, 125}, ++{205, 54, 130}, ++{115, 75, 91}, ++{122, 75, 95}, ++{134, 74, 101}, ++{148, 71, 107}, ++{163, 67, 114}, ++{178, 63, 120}, ++{193, 59, 125}, ++{206, 54, 130}, ++{116, 76, 92}, ++{123, 76, 95}, ++{135, 74, 101}, ++{149, 71, 107}, ++{163, 68, 114}, ++{178, 63, 120}, ++{193, 59, 125}, ++{206, 55, 130}, ++{117, 77, 92}, ++{124, 76, 96}, ++{136, 75, 101}, ++{150, 72, 108}, ++{164, 68, 114}, ++{179, 64, 120}, ++{194, 59, 125}, ++{206, 55, 130}, ++{119, 78, 93}, ++{125, 77, 96}, ++{137, 76, 102}, ++{151, 73, 108}, ++{165, 69, 114}, ++{180, 64, 120}, ++{194, 59, 126}, ++{207, 55, 130}, ++{120, 79, 94}, ++{127, 79, 97}, ++{138, 77, 102}, ++{152, 73, 108}, ++{166, 69, 115}, ++{181, 65, 120}, ++{195, 60, 126}, ++{208, 56, 130}, ++{122, 81, 94}, ++{129, 80, 98}, ++{140, 78, 103}, ++{153, 74, 109}, ++{167, 70, 115}, ++{182, 65, 121}, ++{196, 60, 126}, ++{209, 56, 130}, ++{125, 82, 95}, ++{131, 81, 98}, ++{142, 79, 104}, ++{155, 75, 109}, ++{169, 71, 115}, ++{183, 66, 121}, ++{197, 61, 126}, ++{210, 57, 131}, ++{127, 84, 96}, ++{133, 83, 99}, ++{144, 80, 104}, ++{156, 76, 110}, ++{170, 71, 116}, ++{184, 67, 121}, ++{198, 62, 126}, ++{211, 57, 131}, ++{129, 86, 97}, ++{135, 84, 100}, ++{146, 81, 105}, ++{158, 77, 110}, ++{172, 72, 116}, ++{186, 67, 121}, ++{200, 62, 127}, ++{212, 58, 131}, ++{132, 87, 98}, ++{138, 86, 101}, ++{148, 82, 106}, ++{160, 78, 111}, ++{173, 73, 117}, ++{187, 68, 122}, ++{201, 63, 127}, ++{213, 58, 131}, ++{135, 89, 99}, ++{140, 87, 102}, ++{150, 83, 106}, ++{162, 79, 112}, ++{175, 74, 117}, ++{189, 69, 122}, ++{203, 64, 127}, ++{215, 59, 131}, ++{137, 90, 100}, ++{143, 88, 103}, ++{153, 85, 107}, ++{164, 80, 112}, ++{177, 75, 117}, ++{191, 70, 123}, ++{204, 64, 128}, ++{216, 60, 132}, ++{140, 92, 101}, ++{146, 90, 104}, ++{155, 86, 108}, ++{167, 81, 113}, ++{179, 76, 118}, ++{192, 71, 123}, ++{206, 65, 128}, ++{218, 60, 132}, ++{143, 93, 103}, ++{148, 91, 105}, ++{158, 87, 109}, ++{169, 82, 114}, ++{181, 77, 119}, ++{194, 72, 123}, ++{208, 66, 128}, ++{219, 61, 132}, ++{147, 95, 104}, ++{151, 92, 106}, ++{160, 88, 110}, ++{171, 83, 114}, ++{184, 78, 119}, ++{196, 72, 124}, ++{210, 67, 129}, ++{221, 62, 133}, ++{150, 96, 105}, ++{154, 94, 107}, ++{163, 89, 111}, ++{174, 84, 115}, ++{186, 79, 120}, ++{199, 73, 124}, ++{211, 68, 129}, ++{223, 63, 133}, ++{153, 97, 106}, ++{157, 95, 108}, ++{166, 91, 111}, ++{177, 86, 116}, ++{188, 80, 120}, ++{201, 74, 125}, ++{213, 69, 129}, ++{225, 64, 133}, ++{156, 98, 107}, ++{161, 96, 109}, ++{169, 92, 112}, ++{179, 87, 116}, ++{191, 81, 121}, ++{203, 75, 125}, ++{216, 69, 130}, ++{227, 64, 134}, ++{160, 100, 108}, ++{164, 97, 110}, ++{172, 93, 113}, ++{182, 88, 117}, ++{193, 82, 121}, ++{205, 76, 126}, ++{218, 70, 130}, ++{229, 65, 134}, ++{163, 101, 109}, ++{167, 98, 111}, ++{175, 94, 114}, ++{185, 89, 118}, ++{196, 83, 122}, ++{208, 77, 126}, ++{220, 71, 131}, ++{231, 66, 134}, ++{166, 102, 110}, ++{170, 99, 112}, ++{178, 95, 115}, ++{188, 90, 118}, ++{198, 84, 123}, ++{210, 78, 127}, ++{222, 72, 131}, ++{233, 67, 135}, ++{170, 103, 111}, ++{174, 100, 113}, ++{181, 96, 116}, ++{191, 91, 119}, ++{201, 85, 123}, ++{213, 79, 127}, ++{224, 73, 131}, ++{235, 68, 135}, ++{173, 104, 112}, ++{177, 101, 113}, ++{184, 97, 116}, ++{193, 92, 120}, ++{204, 86, 124}, ++{215, 80, 128}, ++{227, 74, 132}, ++{237, 69, 135}, ++{177, 105, 113}, ++{180, 102, 114}, ++{187, 98, 117}, ++{196, 93, 121}, ++{207, 87, 124}, ++{218, 81, 128}, ++{229, 75, 132}, ++{240, 69, 136}, ++{180, 105, 114}, ++{184, 103, 115}, ++{191, 99, 118}, ++{200, 93, 121}, ++{210, 88, 125}, ++{220, 82, 129}, ++{232, 76, 133}, ++{242, 70, 136}, ++{184, 106, 115}, ++{187, 104, 116}, ++{194, 100, 119}, ++{203, 94, 122}, ++{212, 89, 126}, ++{223, 83, 129}, ++{234, 76, 133}, ++{244, 71, 136}, ++{185, 107, 115}, ++{189, 104, 117}, ++{196, 100, 119}, ++{204, 95, 122}, ++{214, 89, 126}, ++{224, 83, 130}, ++{235, 77, 133}, ++{245, 72, 137}, ++{185, 107, 115}, ++{189, 104, 117}, ++{196, 100, 119}, ++{204, 95, 122}, ++{214, 89, 126}, ++{224, 83, 130}, ++{235, 77, 133}, ++{245, 72, 137}, ++{185, 107, 115}, ++{189, 104, 117}, ++{196, 100, 119}, ++{204, 95, 122}, ++{214, 89, 126}, ++{224, 83, 130}, ++{235, 77, 133}, ++{245, 72, 137}, ++{185, 107, 115}, ++{189, 104, 117}, ++{196, 100, 119}, ++{204, 95, 122}, ++{214, 89, 126}, ++{224, 83, 130}, ++{235, 77, 133}, ++{245, 72, 137}, ++{117, 72, 89}, ++{124, 72, 92}, ++{136, 71, 98}, ++{150, 69, 105}, ++{164, 66, 111}, ++{179, 62, 117}, ++{194, 57, 123}, ++{207, 53, 128}, ++{117, 72, 89}, ++{124, 72, 92}, ++{136, 71, 98}, ++{150, 69, 105}, ++{165, 66, 111}, ++{179, 62, 117}, ++{194, 57, 123}, ++{207, 53, 128}, ++{118, 72, 89}, ++{125, 72, 93}, ++{137, 72, 99}, ++{150, 69, 105}, ++{165, 66, 111}, ++{180, 62, 117}, ++{194, 57, 123}, ++{207, 53, 128}, ++{119, 73, 89}, ++{126, 73, 93}, ++{137, 72, 99}, ++{151, 70, 105}, ++{165, 66, 112}, ++{180, 62, 118}, ++{195, 58, 123}, ++{208, 54, 128}, ++{120, 74, 90}, ++{127, 74, 93}, ++{138, 73, 99}, ++{152, 70, 106}, ++{166, 67, 112}, ++{181, 62, 118}, ++{195, 58, 123}, ++{208, 54, 128}, ++{122, 75, 91}, ++{128, 75, 94}, ++{139, 74, 100}, ++{153, 71, 106}, ++{167, 67, 112}, ++{182, 63, 118}, ++{196, 58, 123}, ++{209, 54, 128}, ++{123, 77, 91}, ++{130, 76, 95}, ++{141, 74, 100}, ++{154, 72, 106}, ++{168, 68, 112}, ++{182, 63, 118}, ++{197, 59, 124}, ++{209, 55, 128}, ++{125, 78, 92}, ++{131, 78, 95}, ++{142, 76, 101}, ++{155, 72, 107}, ++{169, 68, 113}, ++{184, 64, 118}, ++{198, 59, 124}, ++{210, 55, 128}, ++{127, 80, 93}, ++{133, 79, 96}, ++{144, 77, 101}, ++{157, 73, 107}, ++{171, 69, 113}, ++{185, 65, 119}, ++{199, 60, 124}, ++{211, 56, 129}, ++{129, 82, 94}, ++{135, 80, 97}, ++{146, 78, 102}, ++{158, 74, 108}, ++{172, 70, 113}, ++{186, 65, 119}, ++{200, 60, 124}, ++{212, 56, 129}, ++{132, 83, 95}, ++{138, 82, 98}, ++{148, 79, 103}, ++{160, 75, 108}, ++{174, 71, 114}, ++{187, 66, 119}, ++{201, 61, 125}, ++{214, 57, 129}, ++{134, 85, 96}, ++{140, 83, 99}, ++{150, 80, 103}, ++{162, 76, 109}, ++{175, 72, 114}, ++{189, 67, 120}, ++{203, 62, 125}, ++{215, 57, 129}, ++{137, 86, 97}, ++{142, 85, 100}, ++{152, 81, 104}, ++{164, 77, 109}, ++{177, 73, 115}, ++{191, 68, 120}, ++{204, 63, 125}, ++{216, 58, 129}, ++{140, 88, 98}, ++{145, 86, 101}, ++{155, 83, 105}, ++{166, 78, 110}, ++{179, 74, 115}, ++{192, 69, 121}, ++{206, 63, 126}, ++{218, 59, 130}, ++{143, 89, 99}, ++{148, 88, 102}, ++{157, 84, 106}, ++{169, 80, 111}, ++{181, 75, 116}, ++{194, 69, 121}, ++{208, 64, 126}, ++{219, 59, 130}, ++{146, 91, 100}, ++{151, 89, 103}, ++{160, 85, 107}, ++{171, 81, 111}, ++{183, 76, 116}, ++{196, 70, 121}, ++{209, 65, 126}, ++{221, 60, 130}, ++{149, 92, 102}, ++{154, 90, 104}, ++{162, 86, 108}, ++{173, 82, 112}, ++{185, 77, 117}, ++{198, 71, 122}, ++{211, 66, 127}, ++{223, 61, 131}, ++{152, 94, 103}, ++{156, 92, 105}, ++{165, 88, 108}, ++{176, 83, 113}, ++{188, 78, 118}, ++{200, 72, 122}, ++{213, 67, 127}, ++{224, 62, 131}, ++{155, 95, 104}, ++{160, 93, 106}, ++{168, 89, 109}, ++{178, 84, 114}, ++{190, 79, 118}, ++{202, 73, 123}, ++{215, 67, 127}, ++{226, 63, 131}, ++{158, 96, 105}, ++{163, 94, 107}, ++{171, 90, 110}, ++{181, 85, 114}, ++{192, 80, 119}, ++{205, 74, 123}, ++{217, 68, 128}, ++{228, 63, 132}, ++{162, 98, 106}, ++{166, 95, 108}, ++{174, 91, 111}, ++{184, 86, 115}, ++{195, 81, 119}, ++{207, 75, 124}, ++{219, 69, 128}, ++{230, 64, 132}, ++{165, 99, 107}, ++{169, 96, 109}, ++{177, 92, 112}, ++{187, 87, 116}, ++{197, 82, 120}, ++{209, 76, 124}, ++{221, 70, 129}, ++{232, 65, 132}, ++{168, 100, 108}, ++{172, 98, 110}, ++{180, 93, 113}, ++{189, 88, 117}, ++{200, 83, 121}, ++{212, 77, 125}, ++{224, 71, 129}, ++{234, 66, 133}, ++{172, 101, 109}, ++{176, 99, 111}, ++{183, 94, 114}, ++{192, 89, 117}, ++{203, 84, 121}, ++{214, 78, 125}, ++{226, 72, 130}, ++{236, 67, 133}, ++{175, 102, 110}, ++{179, 100, 111}, ++{186, 95, 114}, ++{195, 90, 118}, ++{206, 85, 122}, ++{217, 79, 126}, ++{228, 73, 130}, ++{239, 68, 133}, ++{179, 103, 111}, ++{182, 101, 112}, ++{189, 96, 115}, ++{198, 91, 119}, ++{208, 85, 122}, ++{219, 80, 126}, ++{231, 74, 130}, ++{241, 69, 134}, ++{182, 104, 112}, ++{186, 101, 113}, ++{192, 97, 116}, ++{201, 92, 119}, ++{211, 86, 123}, ++{222, 81, 127}, ++{233, 75, 131}, ++{243, 69, 134}, ++{185, 105, 113}, ++{189, 102, 114}, ++{196, 98, 117}, ++{204, 93, 120}, ++{214, 87, 124}, ++{224, 81, 127}, ++{236, 75, 131}, ++{246, 70, 135}, ++{187, 105, 113}, ++{191, 103, 115}, ++{197, 99, 117}, ++{206, 93, 120}, ++{215, 88, 124}, ++{226, 82, 128}, ++{237, 76, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 103, 115}, ++{197, 99, 117}, ++{206, 93, 120}, ++{215, 88, 124}, ++{226, 82, 128}, ++{237, 76, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 103, 115}, ++{197, 99, 117}, ++{206, 93, 120}, ++{215, 88, 124}, ++{226, 82, 128}, ++{237, 76, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 103, 115}, ++{197, 99, 117}, ++{206, 93, 120}, ++{215, 88, 124}, ++{226, 82, 128}, ++{237, 76, 132}, ++{247, 71, 135}, ++{120, 69, 87}, ++{127, 69, 90}, ++{138, 69, 96}, ++{152, 67, 103}, ++{166, 64, 109}, ++{181, 60, 115}, ++{196, 56, 121}, ++{208, 52, 126}, ++{120, 69, 87}, ++{127, 70, 90}, ++{139, 69, 96}, ++{152, 67, 103}, ++{167, 64, 109}, ++{181, 60, 115}, ++{196, 56, 121}, ++{209, 52, 126}, ++{121, 70, 87}, ++{127, 70, 90}, ++{139, 69, 96}, ++{153, 67, 103}, ++{167, 64, 109}, ++{182, 60, 115}, ++{196, 56, 121}, ++{209, 52, 126}, ++{122, 71, 87}, ++{128, 71, 91}, ++{140, 70, 97}, ++{153, 68, 103}, ++{167, 65, 109}, ++{182, 61, 115}, ++{197, 57, 121}, ++{209, 53, 126}, ++{123, 72, 88}, ++{129, 72, 91}, ++{141, 71, 97}, ++{154, 68, 103}, ++{168, 65, 110}, ++{183, 61, 116}, ++{197, 57, 121}, ++{210, 53, 126}, ++{124, 73, 89}, ++{131, 73, 92}, ++{142, 71, 97}, ++{155, 69, 104}, ++{169, 66, 110}, ++{183, 62, 116}, ++{198, 57, 121}, ++{210, 53, 126}, ++{126, 74, 89}, ++{132, 74, 93}, ++{143, 72, 98}, ++{156, 70, 104}, ++{170, 66, 110}, ++{184, 62, 116}, ++{199, 58, 122}, ++{211, 54, 126}, ++{128, 76, 90}, ++{134, 75, 93}, ++{145, 73, 99}, ++{157, 71, 105}, ++{171, 67, 111}, ++{185, 63, 116}, ++{200, 58, 122}, ++{212, 54, 126}, ++{130, 77, 91}, ++{136, 77, 94}, ++{146, 75, 99}, ++{159, 71, 105}, ++{173, 68, 111}, ++{187, 63, 117}, ++{201, 59, 122}, ++{213, 55, 127}, ++{132, 79, 92}, ++{138, 78, 95}, ++{148, 76, 100}, ++{161, 72, 106}, ++{174, 68, 111}, ++{188, 64, 117}, ++{202, 59, 122}, ++{214, 55, 127}, ++{134, 81, 93}, ++{140, 79, 96}, ++{150, 77, 101}, ++{162, 73, 106}, ++{176, 69, 112}, ++{189, 65, 117}, ++{203, 60, 123}, ++{215, 56, 127}, ++{137, 82, 94}, ++{142, 81, 97}, ++{152, 78, 101}, ++{164, 75, 107}, ++{177, 70, 112}, ++{191, 66, 118}, ++{204, 61, 123}, ++{216, 56, 127}, ++{140, 84, 95}, ++{145, 82, 98}, ++{154, 80, 102}, ++{166, 76, 107}, ++{179, 71, 113}, ++{192, 66, 118}, ++{206, 61, 123}, ++{218, 57, 128}, ++{142, 86, 96}, ++{147, 84, 99}, ++{157, 81, 103}, ++{168, 77, 108}, ++{181, 72, 113}, ++{194, 67, 119}, ++{207, 62, 124}, ++{219, 58, 128}, ++{145, 87, 97}, ++{150, 85, 100}, ++{159, 82, 104}, ++{171, 78, 109}, ++{183, 73, 114}, ++{196, 68, 119}, ++{209, 63, 124}, ++{221, 58, 128}, ++{148, 89, 98}, ++{153, 87, 101}, ++{162, 83, 105}, ++{173, 79, 109}, ++{185, 74, 114}, ++{198, 69, 119}, ++{211, 64, 124}, ++{222, 59, 128}, ++{151, 90, 99}, ++{156, 88, 102}, ++{164, 85, 106}, ++{175, 80, 110}, ++{187, 75, 115}, ++{200, 70, 120}, ++{213, 65, 125}, ++{224, 60, 129}, ++{154, 92, 101}, ++{159, 90, 103}, ++{167, 86, 106}, ++{178, 81, 111}, ++{189, 76, 116}, ++{202, 71, 120}, ++{215, 66, 125}, ++{226, 61, 129}, ++{157, 93, 102}, ++{162, 91, 104}, ++{170, 87, 107}, ++{180, 82, 112}, ++{192, 77, 116}, ++{204, 72, 121}, ++{217, 66, 126}, ++{228, 62, 129}, ++{160, 94, 103}, ++{165, 92, 105}, ++{173, 88, 108}, ++{183, 84, 112}, ++{194, 78, 117}, ++{206, 73, 121}, ++{219, 67, 126}, ++{230, 62, 130}, ++{164, 95, 104}, ++{168, 93, 106}, ++{176, 89, 109}, ++{186, 85, 113}, ++{197, 79, 117}, ++{208, 74, 122}, ++{221, 68, 126}, ++{232, 63, 130}, ++{167, 97, 105}, ++{171, 95, 107}, ++{179, 91, 110}, ++{188, 86, 114}, ++{199, 80, 118}, ++{211, 75, 122}, ++{223, 69, 127}, ++{234, 64, 131}, ++{170, 98, 106}, ++{174, 96, 108}, ++{182, 92, 111}, ++{191, 87, 115}, ++{202, 81, 119}, ++{213, 76, 123}, ++{225, 70, 127}, ++{236, 65, 131}, ++{174, 99, 107}, ++{177, 97, 109}, ++{185, 93, 112}, ++{194, 88, 115}, ++{204, 82, 119}, ++{216, 77, 124}, ++{227, 71, 128}, ++{238, 66, 131}, ++{177, 100, 108}, ++{181, 98, 110}, ++{188, 94, 112}, ++{197, 89, 116}, ++{207, 83, 120}, ++{218, 78, 124}, ++{230, 72, 128}, ++{240, 67, 132}, ++{180, 101, 109}, ++{184, 99, 110}, ++{191, 95, 113}, ++{200, 90, 117}, ++{210, 84, 121}, ++{221, 79, 125}, ++{232, 73, 129}, ++{242, 68, 132}, ++{184, 102, 110}, ++{187, 100, 111}, ++{194, 96, 114}, ++{203, 91, 118}, ++{213, 85, 121}, ++{223, 79, 125}, ++{234, 74, 129}, ++{245, 68, 132}, ++{187, 103, 111}, ++{191, 101, 112}, ++{197, 97, 115}, ++{206, 92, 118}, ++{215, 86, 122}, ++{226, 80, 126}, ++{237, 74, 130}, ++{247, 69, 133}, ++{189, 103, 111}, ++{192, 101, 113}, ++{199, 97, 115}, ++{207, 92, 119}, ++{217, 87, 122}, ++{227, 81, 126}, ++{238, 75, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{192, 101, 113}, ++{199, 97, 115}, ++{207, 92, 119}, ++{217, 87, 122}, ++{227, 81, 126}, ++{238, 75, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{192, 101, 113}, ++{199, 97, 115}, ++{207, 92, 119}, ++{217, 87, 122}, ++{227, 81, 126}, ++{238, 75, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{192, 101, 113}, ++{199, 97, 115}, ++{207, 92, 119}, ++{217, 87, 122}, ++{227, 81, 126}, ++{238, 75, 130}, ++{248, 70, 133}, ++{123, 66, 85}, ++{129, 67, 88}, ++{141, 67, 94}, ++{154, 65, 100}, ++{169, 62, 107}, ++{183, 59, 113}, ++{197, 55, 119}, ++{210, 51, 124}, ++{123, 67, 85}, ++{130, 67, 88}, ++{141, 67, 94}, ++{154, 65, 101}, ++{169, 62, 107}, ++{183, 59, 113}, ++{198, 55, 119}, ++{210, 51, 124}, ++{124, 67, 85}, ++{130, 68, 88}, ++{142, 67, 94}, ++{155, 66, 101}, ++{169, 63, 107}, ++{183, 59, 113}, ++{198, 55, 119}, ++{210, 51, 124}, ++{125, 68, 85}, ++{131, 68, 89}, ++{142, 68, 95}, ++{155, 66, 101}, ++{170, 63, 107}, ++{184, 59, 113}, ++{198, 55, 119}, ++{211, 52, 124}, ++{126, 69, 86}, ++{132, 69, 89}, ++{143, 68, 95}, ++{156, 66, 101}, ++{170, 63, 107}, ++{184, 60, 113}, ++{199, 56, 119}, ++{211, 52, 124}, ++{127, 70, 87}, ++{133, 70, 90}, ++{144, 69, 95}, ++{157, 67, 102}, ++{171, 64, 108}, ++{185, 60, 114}, ++{200, 56, 119}, ++{212, 52, 124}, ++{129, 72, 87}, ++{135, 71, 90}, ++{146, 70, 96}, ++{158, 68, 102}, ++{172, 65, 108}, ++{186, 61, 114}, ++{200, 56, 120}, ++{213, 53, 124}, ++{131, 73, 88}, ++{136, 73, 91}, ++{147, 71, 96}, ++{160, 69, 102}, ++{173, 65, 108}, ++{187, 61, 114}, ++{201, 57, 120}, ++{214, 53, 124}, ++{133, 75, 89}, ++{138, 74, 92}, ++{149, 72, 97}, ++{161, 70, 103}, ++{175, 66, 109}, ++{188, 62, 115}, ++{202, 58, 120}, ++{215, 54, 125}, ++{135, 76, 90}, ++{140, 76, 93}, ++{150, 74, 98}, ++{163, 71, 103}, ++{176, 67, 109}, ++{190, 63, 115}, ++{203, 58, 120}, ++{216, 54, 125}, ++{137, 78, 91}, ++{142, 77, 94}, ++{152, 75, 98}, ++{164, 72, 104}, ++{177, 68, 110}, ++{191, 63, 115}, ++{205, 59, 121}, ++{217, 55, 125}, ++{139, 80, 92}, ++{145, 79, 95}, ++{155, 76, 99}, ++{166, 73, 105}, ++{179, 69, 110}, ++{193, 64, 116}, ++{206, 60, 121}, ++{218, 55, 125}, ++{142, 82, 93}, ++{147, 80, 96}, ++{157, 77, 100}, ++{168, 74, 105}, ++{181, 70, 111}, ++{194, 65, 116}, ++{208, 60, 121}, ++{219, 56, 126}, ++{145, 83, 94}, ++{150, 82, 97}, ++{159, 79, 101}, ++{170, 75, 106}, ++{183, 71, 111}, ++{196, 66, 117}, ++{209, 61, 122}, ++{221, 57, 126}, ++{148, 85, 95}, ++{152, 83, 98}, ++{161, 80, 102}, ++{173, 76, 107}, ++{185, 72, 112}, ++{198, 67, 117}, ++{211, 62, 122}, ++{222, 57, 126}, ++{150, 86, 96}, ++{155, 85, 99}, ++{164, 81, 103}, ++{175, 77, 107}, ++{187, 73, 112}, ++{199, 68, 117}, ++{212, 63, 122}, ++{224, 58, 127}, ++{153, 88, 97}, ++{158, 86, 100}, ++{167, 83, 103}, ++{177, 78, 108}, ++{189, 74, 113}, ++{201, 69, 118}, ++{214, 64, 123}, ++{226, 59, 127}, ++{156, 89, 99}, ++{161, 87, 101}, ++{169, 84, 104}, ++{180, 80, 109}, ++{191, 75, 114}, ++{203, 70, 118}, ++{216, 64, 123}, ++{227, 60, 127}, ++{159, 91, 100}, ++{164, 89, 102}, ++{172, 85, 105}, ++{182, 81, 110}, ++{194, 76, 114}, ++{206, 71, 119}, ++{218, 65, 124}, ++{229, 61, 128}, ++{163, 92, 101}, ++{167, 90, 103}, ++{175, 86, 106}, ++{185, 82, 110}, ++{196, 77, 115}, ++{208, 72, 119}, ++{220, 66, 124}, ++{231, 61, 128}, ++{166, 93, 102}, ++{170, 91, 104}, ++{178, 88, 107}, ++{187, 83, 111}, ++{198, 78, 115}, ++{210, 73, 120}, ++{222, 67, 124}, ++{233, 62, 128}, ++{169, 95, 103}, ++{173, 93, 105}, ++{181, 89, 108}, ++{190, 84, 112}, ++{201, 79, 116}, ++{212, 74, 121}, ++{224, 68, 125}, ++{235, 63, 129}, ++{172, 96, 104}, ++{176, 94, 106}, ++{184, 90, 109}, ++{193, 85, 113}, ++{203, 80, 117}, ++{215, 74, 121}, ++{227, 69, 125}, ++{237, 64, 129}, ++{176, 97, 105}, ++{179, 95, 107}, ++{187, 91, 110}, ++{196, 86, 113}, ++{206, 81, 117}, ++{217, 75, 122}, ++{229, 70, 126}, ++{239, 65, 130}, ++{179, 98, 106}, ++{183, 96, 108}, ++{190, 92, 111}, ++{199, 87, 114}, ++{209, 82, 118}, ++{220, 76, 122}, ++{231, 71, 126}, ++{241, 66, 130}, ++{182, 99, 107}, ++{186, 97, 109}, ++{193, 93, 111}, ++{201, 88, 115}, ++{211, 83, 119}, ++{222, 77, 123}, ++{233, 72, 127}, ++{244, 67, 130}, ++{186, 100, 108}, ++{189, 98, 110}, ++{196, 94, 112}, ++{204, 89, 116}, ++{214, 84, 119}, ++{225, 78, 123}, ++{236, 73, 127}, ++{246, 68, 131}, ++{189, 101, 109}, ++{192, 99, 110}, ++{199, 95, 113}, ++{207, 90, 116}, ++{217, 85, 120}, ++{227, 79, 124}, ++{238, 73, 128}, ++{248, 68, 131}, ++{191, 102, 110}, ++{194, 99, 111}, ++{201, 96, 114}, ++{209, 91, 117}, ++{218, 85, 120}, ++{229, 80, 124}, ++{240, 74, 128}, ++{249, 69, 131}, ++{191, 102, 110}, ++{194, 99, 111}, ++{201, 96, 114}, ++{209, 91, 117}, ++{218, 85, 120}, ++{229, 80, 124}, ++{240, 74, 128}, ++{249, 69, 131}, ++{191, 102, 110}, ++{194, 99, 111}, ++{201, 96, 114}, ++{209, 91, 117}, ++{218, 85, 120}, ++{229, 80, 124}, ++{240, 74, 128}, ++{249, 69, 131}, ++{191, 102, 110}, ++{194, 99, 111}, ++{201, 96, 114}, ++{209, 91, 117}, ++{218, 85, 120}, ++{229, 80, 124}, ++{240, 74, 128}, ++{249, 69, 131}, ++{126, 64, 83}, ++{132, 65, 86}, ++{143, 65, 92}, ++{157, 63, 98}, ++{171, 61, 105}, ++{185, 57, 111}, ++{199, 54, 117}, ++{212, 50, 122}, ++{126, 64, 83}, ++{132, 65, 86}, ++{144, 65, 92}, ++{157, 63, 98}, ++{171, 61, 105}, ++{185, 58, 111}, ++{199, 54, 117}, ++{212, 50, 122}, ++{127, 65, 83}, ++{133, 65, 86}, ++{144, 65, 92}, ++{157, 64, 99}, ++{171, 61, 105}, ++{185, 58, 111}, ++{200, 54, 117}, ++{212, 50, 122}, ++{128, 65, 83}, ++{134, 66, 87}, ++{145, 66, 92}, ++{158, 64, 99}, ++{172, 61, 105}, ++{186, 58, 111}, ++{200, 54, 117}, ++{212, 50, 122}, ++{129, 67, 84}, ++{135, 67, 87}, ++{146, 66, 93}, ++{158, 65, 99}, ++{172, 62, 105}, ++{186, 58, 111}, ++{201, 54, 117}, ++{213, 51, 122}, ++{130, 68, 85}, ++{136, 68, 88}, ++{147, 67, 93}, ++{159, 65, 99}, ++{173, 62, 106}, ++{187, 59, 112}, ++{201, 55, 117}, ++{214, 51, 122}, ++{132, 69, 85}, ++{137, 69, 88}, ++{148, 68, 94}, ++{161, 66, 100}, ++{174, 63, 106}, ++{188, 59, 112}, ++{202, 55, 118}, ++{214, 51, 122}, ++{133, 71, 86}, ++{139, 70, 89}, ++{149, 69, 94}, ++{162, 67, 100}, ++{175, 64, 106}, ++{189, 60, 112}, ++{203, 56, 118}, ++{215, 52, 122}, ++{135, 72, 87}, ++{141, 72, 90}, ++{151, 70, 95}, ++{163, 68, 101}, ++{177, 65, 107}, ++{190, 61, 112}, ++{204, 56, 118}, ++{216, 52, 123}, ++{137, 74, 88}, ++{143, 73, 91}, ++{153, 72, 96}, ++{165, 69, 101}, ++{178, 65, 107}, ++{191, 61, 113}, ++{205, 57, 118}, ++{217, 53, 123}, ++{140, 76, 89}, ++{145, 75, 92}, ++{155, 73, 96}, ++{167, 70, 102}, ++{179, 66, 108}, ++{193, 62, 113}, ++{206, 58, 119}, ++{218, 54, 123}, ++{142, 77, 90}, ++{147, 76, 93}, ++{157, 74, 97}, ++{168, 71, 103}, ++{181, 67, 108}, ++{194, 63, 114}, ++{208, 58, 119}, ++{220, 54, 123}, ++{145, 79, 91}, ++{150, 78, 94}, ++{159, 75, 98}, ++{170, 72, 103}, ++{183, 68, 109}, ++{196, 64, 114}, ++{209, 59, 119}, ++{221, 55, 124}, ++{147, 81, 92}, ++{152, 79, 94}, ++{161, 77, 99}, ++{172, 73, 104}, ++{185, 69, 109}, ++{198, 65, 114}, ++{211, 60, 120}, ++{222, 56, 124}, ++{150, 82, 93}, ++{155, 81, 95}, ++{164, 78, 100}, ++{175, 74, 105}, ++{187, 70, 110}, ++{199, 66, 115}, ++{212, 61, 120}, ++{224, 56, 124}, ++{153, 84, 94}, ++{157, 82, 96}, ++{166, 79, 101}, ++{177, 76, 105}, ++{189, 71, 110}, ++{201, 66, 115}, ++{214, 62, 120}, ++{225, 57, 125}, ++{156, 86, 95}, ++{160, 84, 98}, ++{169, 81, 101}, ++{179, 77, 106}, ++{191, 72, 111}, ++{203, 67, 116}, ++{216, 62, 121}, ++{227, 58, 125}, ++{159, 87, 96}, ++{163, 85, 99}, ++{171, 82, 102}, ++{182, 78, 107}, ++{193, 73, 112}, ++{205, 68, 116}, ++{218, 63, 121}, ++{229, 59, 125}, ++{162, 89, 98}, ++{166, 87, 100}, ++{174, 83, 103}, ++{184, 79, 108}, ++{195, 74, 112}, ++{207, 69, 117}, ++{220, 64, 122}, ++{231, 60, 126}, ++{165, 90, 99}, ++{169, 88, 101}, ++{177, 85, 104}, ++{187, 80, 108}, ++{198, 75, 113}, ++{209, 70, 118}, ++{222, 65, 122}, ++{233, 60, 126}, ++{168, 91, 100}, ++{172, 89, 102}, ++{180, 86, 105}, ++{189, 81, 109}, ++{200, 76, 114}, ++{212, 71, 118}, ++{224, 66, 123}, ++{234, 61, 127}, ++{171, 93, 101}, ++{175, 91, 103}, ++{182, 87, 106}, ++{192, 83, 110}, ++{203, 78, 114}, ++{214, 72, 119}, ++{226, 67, 123}, ++{236, 62, 127}, ++{174, 94, 102}, ++{178, 92, 104}, ++{185, 88, 107}, ++{195, 84, 111}, ++{205, 79, 115}, ++{216, 73, 119}, ++{228, 68, 124}, ++{239, 63, 127}, ++{177, 95, 103}, ++{181, 93, 105}, ++{188, 89, 108}, ++{197, 85, 111}, ++{208, 80, 116}, ++{219, 74, 120}, ++{230, 69, 124}, ++{241, 64, 128}, ++{181, 96, 104}, ++{184, 94, 106}, ++{191, 90, 109}, ++{200, 86, 112}, ++{210, 81, 116}, ++{221, 75, 120}, ++{233, 70, 125}, ++{243, 65, 128}, ++{184, 97, 105}, ++{188, 95, 107}, ++{194, 92, 109}, ++{203, 87, 113}, ++{213, 82, 117}, ++{224, 76, 121}, ++{235, 71, 125}, ++{245, 66, 129}, ++{187, 98, 106}, ++{191, 96, 108}, ++{198, 93, 110}, ++{206, 88, 114}, ++{216, 83, 118}, ++{226, 77, 122}, ++{237, 72, 126}, ++{247, 67, 129}, ++{191, 99, 107}, ++{194, 97, 109}, ++{201, 94, 111}, ++{209, 89, 115}, ++{219, 84, 118}, ++{229, 78, 122}, ++{240, 72, 126}, ++{250, 67, 129}, ++{193, 100, 108}, ++{196, 98, 109}, ++{202, 94, 112}, ++{211, 89, 115}, ++{220, 84, 119}, ++{230, 79, 122}, ++{241, 73, 126}, ++{251, 68, 130}, ++{193, 100, 108}, ++{196, 98, 109}, ++{202, 94, 112}, ++{211, 89, 115}, ++{220, 84, 119}, ++{230, 79, 122}, ++{241, 73, 126}, ++{251, 68, 130}, ++{193, 100, 108}, ++{196, 98, 109}, ++{202, 94, 112}, ++{211, 89, 115}, ++{220, 84, 119}, ++{230, 79, 122}, ++{241, 73, 126}, ++{251, 68, 130}, ++{193, 100, 108}, ++{196, 98, 109}, ++{202, 94, 112}, ++{211, 89, 115}, ++{220, 84, 119}, ++{230, 79, 122}, ++{241, 73, 126}, ++{251, 68, 130}, ++{129, 61, 81}, ++{135, 62, 84}, ++{146, 62, 90}, ++{159, 61, 96}, ++{173, 59, 103}, ++{187, 56, 109}, ++{201, 52, 115}, ++{213, 49, 120}, ++{129, 62, 81}, ++{135, 62, 84}, ++{146, 63, 90}, ++{159, 61, 96}, ++{173, 59, 103}, ++{187, 56, 109}, ++{201, 52, 115}, ++{213, 49, 120}, ++{130, 62, 81}, ++{136, 63, 84}, ++{146, 63, 90}, ++{159, 62, 96}, ++{173, 59, 103}, ++{187, 56, 109}, ++{201, 53, 115}, ++{214, 49, 120}, ++{130, 63, 82}, ++{136, 64, 85}, ++{147, 63, 90}, ++{160, 62, 97}, ++{174, 60, 103}, ++{188, 57, 109}, ++{202, 53, 115}, ++{214, 49, 120}, ++{131, 64, 82}, ++{137, 64, 85}, ++{148, 64, 91}, ++{161, 63, 97}, ++{174, 60, 103}, ++{188, 57, 109}, ++{202, 53, 115}, ++{215, 50, 120}, ++{133, 65, 83}, ++{139, 66, 86}, ++{149, 65, 91}, ++{162, 63, 97}, ++{175, 61, 104}, ++{189, 57, 110}, ++{203, 54, 115}, ++{215, 50, 120}, ++{134, 67, 83}, ++{140, 67, 86}, ++{150, 66, 92}, ++{163, 64, 98}, ++{176, 61, 104}, ++{190, 58, 110}, ++{204, 54, 115}, ++{216, 50, 120}, ++{136, 68, 84}, ++{142, 68, 87}, ++{152, 67, 92}, ++{164, 65, 98}, ++{177, 62, 104}, ++{191, 59, 110}, ++{205, 55, 116}, ++{217, 51, 120}, ++{138, 70, 85}, ++{143, 69, 88}, ++{153, 68, 93}, ++{165, 66, 99}, ++{179, 63, 105}, ++{192, 59, 110}, ++{206, 55, 116}, ++{218, 51, 121}, ++{140, 72, 86}, ++{145, 71, 89}, ++{155, 69, 94}, ++{167, 67, 99}, ++{180, 64, 105}, ++{193, 60, 111}, ++{207, 56, 116}, ++{219, 52, 121}, ++{142, 73, 87}, ++{147, 73, 90}, ++{157, 71, 94}, ++{169, 68, 100}, ++{181, 65, 106}, ++{195, 61, 111}, ++{208, 56, 117}, ++{220, 53, 121}, ++{145, 75, 88}, ++{150, 74, 91}, ++{159, 72, 95}, ++{171, 69, 101}, ++{183, 66, 106}, ++{196, 62, 112}, ++{209, 57, 117}, ++{221, 53, 121}, ++{147, 77, 89}, ++{152, 76, 91}, ++{161, 73, 96}, ++{172, 70, 101}, ++{185, 67, 107}, ++{198, 62, 112}, ++{211, 58, 117}, ++{223, 54, 122}, ++{150, 78, 90}, ++{154, 77, 92}, ++{163, 75, 97}, ++{174, 72, 102}, ++{187, 68, 107}, ++{199, 63, 112}, ++{212, 59, 118}, ++{224, 55, 122}, ++{152, 80, 91}, ++{157, 79, 93}, ++{166, 76, 98}, ++{177, 73, 103}, ++{189, 69, 108}, ++{201, 64, 113}, ++{214, 60, 118}, ++{225, 55, 122}, ++{155, 82, 92}, ++{160, 80, 94}, ++{168, 78, 99}, ++{179, 74, 103}, ++{191, 70, 108}, ++{203, 65, 113}, ++{216, 60, 118}, ++{227, 56, 123}, ++{158, 83, 93}, ++{162, 82, 96}, ++{171, 79, 99}, ++{181, 75, 104}, ++{193, 71, 109}, ++{205, 66, 114}, ++{217, 61, 119}, ++{229, 57, 123}, ++{161, 85, 95}, ++{165, 83, 97}, ++{173, 80, 100}, ++{183, 76, 105}, ++{195, 72, 110}, ++{207, 67, 115}, ++{219, 62, 119}, ++{230, 58, 123}, ++{164, 86, 96}, ++{168, 85, 98}, ++{176, 82, 101}, ++{186, 77, 106}, ++{197, 73, 110}, ++{209, 68, 115}, ++{221, 63, 120}, ++{232, 59, 124}, ++{167, 88, 97}, ++{171, 86, 99}, ++{179, 83, 102}, ++{188, 79, 106}, ++{199, 74, 111}, ++{211, 69, 116}, ++{223, 64, 120}, ++{234, 59, 124}, ++{170, 89, 98}, ++{174, 87, 100}, ++{182, 84, 103}, ++{191, 80, 107}, ++{202, 75, 112}, ++{213, 70, 116}, ++{225, 65, 121}, ++{236, 60, 125}, ++{173, 91, 99}, ++{177, 89, 101}, ++{184, 85, 104}, ++{194, 81, 108}, ++{204, 76, 112}, ++{216, 71, 117}, ++{227, 66, 121}, ++{238, 61, 125}, ++{176, 92, 100}, ++{180, 90, 102}, ++{187, 86, 105}, ++{196, 82, 109}, ++{207, 77, 113}, ++{218, 72, 117}, ++{230, 67, 122}, ++{240, 62, 126}, ++{179, 93, 101}, ++{183, 91, 103}, ++{190, 88, 106}, ++{199, 83, 110}, ++{209, 78, 114}, ++{220, 73, 118}, ++{232, 68, 122}, ++{242, 63, 126}, ++{183, 94, 102}, ++{186, 92, 104}, ++{193, 89, 107}, ++{202, 84, 110}, ++{212, 79, 114}, ++{223, 74, 119}, ++{234, 69, 123}, ++{244, 64, 126}, ++{186, 95, 103}, ++{190, 93, 105}, ++{196, 90, 108}, ++{205, 85, 111}, ++{215, 80, 115}, ++{225, 75, 119}, ++{236, 70, 123}, ++{246, 65, 127}, ++{189, 97, 104}, ++{193, 95, 106}, ++{199, 91, 108}, ++{208, 86, 112}, ++{217, 81, 116}, ++{228, 76, 120}, ++{239, 70, 124}, ++{249, 66, 127}, ++{193, 98, 105}, ++{196, 96, 107}, ++{202, 92, 109}, ++{211, 87, 113}, ++{220, 82, 116}, ++{230, 77, 120}, ++{241, 71, 124}, ++{251, 66, 128}, ++{194, 98, 106}, ++{198, 96, 107}, ++{204, 92, 110}, ++{212, 88, 113}, ++{222, 83, 117}, ++{232, 77, 121}, ++{242, 72, 125}, ++{252, 67, 128}, ++{194, 98, 106}, ++{198, 96, 107}, ++{204, 92, 110}, ++{212, 88, 113}, ++{222, 83, 117}, ++{232, 77, 121}, ++{242, 72, 125}, ++{252, 67, 128}, ++{194, 98, 106}, ++{198, 96, 107}, ++{204, 92, 110}, ++{212, 88, 113}, ++{222, 83, 117}, ++{232, 77, 121}, ++{242, 72, 125}, ++{252, 67, 128}, ++{194, 98, 106}, ++{198, 96, 107}, ++{204, 92, 110}, ++{212, 88, 113}, ++{222, 83, 117}, ++{232, 77, 121}, ++{242, 72, 125}, ++{252, 67, 128}, ++{132, 59, 79}, ++{138, 60, 82}, ++{148, 60, 88}, ++{161, 59, 94}, ++{175, 57, 101}, ++{189, 55, 107}, ++{203, 51, 113}, ++{215, 48, 118}, ++{132, 59, 79}, ++{138, 60, 82}, ++{149, 60, 88}, ++{161, 60, 94}, ++{175, 58, 101}, ++{189, 55, 107}, ++{203, 51, 113}, ++{215, 48, 118}, ++{132, 60, 79}, ++{138, 60, 82}, ++{149, 61, 88}, ++{162, 60, 94}, ++{175, 58, 101}, ++{189, 55, 107}, ++{203, 51, 113}, ++{215, 48, 118}, ++{133, 61, 80}, ++{139, 61, 83}, ++{150, 61, 88}, ++{162, 60, 95}, ++{176, 58, 101}, ++{190, 55, 107}, ++{204, 52, 113}, ++{216, 48, 118}, ++{134, 62, 80}, ++{140, 62, 83}, ++{150, 62, 89}, ++{163, 61, 95}, ++{176, 59, 101}, ++{190, 56, 107}, ++{204, 52, 113}, ++{216, 48, 118}, ++{136, 63, 81}, ++{141, 63, 84}, ++{152, 63, 89}, ++{164, 62, 95}, ++{177, 59, 101}, ++{191, 56, 107}, ++{205, 52, 113}, ++{217, 49, 118}, ++{137, 64, 81}, ++{143, 64, 84}, ++{153, 64, 90}, ++{165, 62, 96}, ++{178, 60, 102}, ++{192, 57, 108}, ++{206, 53, 113}, ++{218, 49, 118}, ++{139, 66, 82}, ++{144, 66, 85}, ++{154, 65, 90}, ++{166, 63, 96}, ++{179, 60, 102}, ++{193, 57, 108}, ++{206, 53, 114}, ++{218, 50, 118}, ++{141, 67, 83}, ++{146, 67, 86}, ++{156, 66, 91}, ++{168, 64, 97}, ++{181, 61, 103}, ++{194, 58, 108}, ++{207, 54, 114}, ++{219, 50, 119}, ++{143, 69, 84}, ++{148, 69, 87}, ++{157, 67, 92}, ++{169, 65, 97}, ++{182, 62, 103}, ++{195, 59, 109}, ++{209, 55, 114}, ++{220, 51, 119}, ++{145, 71, 85}, ++{150, 70, 88}, ++{159, 69, 92}, ++{171, 66, 98}, ++{183, 63, 104}, ++{197, 59, 109}, ++{210, 55, 115}, ++{222, 51, 119}, ++{147, 73, 86}, ++{152, 72, 89}, ++{161, 70, 93}, ++{173, 67, 98}, ++{185, 64, 104}, ++{198, 60, 110}, ++{211, 56, 115}, ++{223, 52, 119}, ++{149, 74, 87}, ++{154, 73, 90}, ++{163, 71, 94}, ++{175, 69, 99}, ++{187, 65, 105}, ++{200, 61, 110}, ++{213, 57, 115}, ++{224, 53, 120}, ++{152, 76, 88}, ++{157, 75, 90}, ++{166, 73, 95}, ++{177, 70, 100}, ++{189, 66, 105}, ++{201, 62, 111}, ++{214, 57, 116}, ++{226, 53, 120}, ++{155, 78, 89}, ++{159, 77, 92}, ++{168, 74, 96}, ++{179, 71, 101}, ++{190, 67, 106}, ++{203, 63, 111}, ++{216, 58, 116}, ++{227, 54, 120}, ++{157, 79, 90}, ++{162, 78, 93}, ++{170, 76, 97}, ++{181, 72, 101}, ++{192, 68, 106}, ++{205, 64, 112}, ++{217, 59, 117}, ++{229, 55, 121}, ++{160, 81, 91}, ++{165, 80, 94}, ++{173, 77, 97}, ++{183, 73, 102}, ++{195, 69, 107}, ++{207, 65, 112}, ++{219, 60, 117}, ++{230, 56, 121}, ++{163, 83, 93}, ++{167, 81, 95}, ++{175, 78, 98}, ++{185, 75, 103}, ++{197, 70, 108}, ++{209, 66, 113}, ++{221, 61, 117}, ++{232, 57, 122}, ++{166, 84, 94}, ++{170, 83, 96}, ++{178, 80, 99}, ++{188, 76, 104}, ++{199, 71, 108}, ++{211, 67, 113}, ++{223, 62, 118}, ++{234, 57, 122}, ++{169, 86, 95}, ++{173, 84, 97}, ++{181, 81, 100}, ++{190, 77, 104}, ++{201, 72, 109}, ++{213, 68, 114}, ++{225, 63, 118}, ++{236, 58, 122}, ++{172, 87, 96}, ++{176, 85, 98}, ++{183, 82, 101}, ++{193, 78, 105}, ++{204, 74, 110}, ++{215, 69, 114}, ++{227, 64, 119}, ++{237, 59, 123}, ++{175, 89, 97}, ++{179, 87, 99}, ++{186, 83, 102}, ++{196, 79, 106}, ++{206, 75, 110}, ++{217, 70, 115}, ++{229, 65, 119}, ++{239, 60, 123}, ++{178, 90, 98}, ++{182, 88, 100}, ++{189, 85, 103}, ++{198, 80, 107}, ++{209, 76, 111}, ++{220, 71, 115}, ++{231, 66, 120}, ++{241, 61, 124}, ++{181, 91, 99}, ++{185, 89, 101}, ++{192, 86, 104}, ++{201, 82, 108}, ++{211, 77, 112}, ++{222, 72, 116}, ++{233, 67, 120}, ++{244, 62, 124}, ++{185, 92, 100}, ++{188, 91, 102}, ++{195, 87, 105}, ++{204, 83, 108}, ++{214, 78, 112}, ++{224, 73, 117}, ++{236, 67, 121}, ++{246, 63, 125}, ++{188, 94, 101}, ++{191, 92, 103}, ++{198, 88, 106}, ++{207, 84, 109}, ++{216, 79, 113}, ++{227, 74, 117}, ++{238, 68, 121}, ++{248, 64, 125}, ++{191, 95, 102}, ++{195, 93, 104}, ++{201, 89, 107}, ++{209, 85, 110}, ++{219, 80, 114}, ++{229, 75, 118}, ++{240, 69, 122}, ++{250, 65, 126}, ++{195, 96, 103}, ++{198, 94, 105}, ++{204, 90, 108}, ++{212, 86, 111}, ++{222, 81, 115}, ++{232, 76, 118}, ++{243, 70, 122}, ++{252, 65, 126}, ++{196, 96, 104}, ++{199, 94, 105}, ++{206, 91, 108}, ++{214, 86, 111}, ++{223, 81, 115}, ++{233, 76, 119}, ++{244, 71, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{199, 94, 105}, ++{206, 91, 108}, ++{214, 86, 111}, ++{223, 81, 115}, ++{233, 76, 119}, ++{244, 71, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{199, 94, 105}, ++{206, 91, 108}, ++{214, 86, 111}, ++{223, 81, 115}, ++{233, 76, 119}, ++{244, 71, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{199, 94, 105}, ++{206, 91, 108}, ++{214, 86, 111}, ++{223, 81, 115}, ++{233, 76, 119}, ++{244, 71, 123}, ++{254, 66, 126}, ++{135, 57, 77}, ++{140, 58, 80}, ++{151, 58, 86}, ++{163, 58, 92}, ++{177, 56, 99}, ++{191, 53, 105}, ++{205, 50, 111}, ++{217, 47, 116}, ++{135, 57, 77}, ++{141, 58, 80}, ++{151, 58, 86}, ++{164, 58, 92}, ++{177, 56, 99}, ++{191, 53, 105}, ++{205, 50, 111}, ++{217, 47, 116}, ++{135, 57, 77}, ++{141, 58, 81}, ++{151, 59, 86}, ++{164, 58, 92}, ++{177, 56, 99}, ++{191, 53, 105}, ++{205, 50, 111}, ++{217, 47, 116}, ++{136, 58, 78}, ++{142, 59, 81}, ++{152, 59, 86}, ++{164, 58, 93}, ++{178, 56, 99}, ++{192, 54, 105}, ++{205, 50, 111}, ++{217, 47, 116}, ++{137, 59, 78}, ++{143, 60, 81}, ++{153, 60, 87}, ++{165, 59, 93}, ++{178, 57, 99}, ++{192, 54, 105}, ++{206, 51, 111}, ++{218, 47, 116}, ++{138, 60, 79}, ++{144, 61, 82}, ++{154, 61, 87}, ++{166, 60, 93}, ++{179, 57, 99}, ++{193, 55, 105}, ++{207, 51, 111}, ++{219, 48, 116}, ++{140, 62, 80}, ++{145, 62, 83}, ++{155, 62, 88}, ++{167, 60, 94}, ++{180, 58, 100}, ++{194, 55, 106}, ++{207, 51, 111}, ++{219, 48, 116}, ++{141, 63, 80}, ++{147, 63, 83}, ++{157, 63, 88}, ++{168, 61, 94}, ++{181, 59, 100}, ++{195, 56, 106}, ++{208, 52, 112}, ++{220, 49, 116}, ++{143, 65, 81}, ++{148, 65, 84}, ++{158, 64, 89}, ++{170, 62, 95}, ++{183, 60, 101}, ++{196, 56, 106}, ++{209, 53, 112}, ++{221, 49, 117}, ++{145, 67, 82}, ++{150, 66, 85}, ++{160, 65, 90}, ++{171, 63, 95}, ++{184, 60, 101}, ++{197, 57, 107}, ++{210, 53, 112}, ++{222, 50, 117}, ++{147, 68, 83}, ++{152, 68, 86}, ++{162, 67, 90}, ++{173, 64, 96}, ++{185, 61, 102}, ++{198, 58, 107}, ++{212, 54, 113}, ++{223, 50, 117}, ++{150, 70, 84}, ++{154, 70, 87}, ++{164, 68, 91}, ++{175, 66, 96}, ++{187, 62, 102}, ++{200, 59, 108}, ++{213, 55, 113}, ++{224, 51, 118}, ++{152, 72, 85}, ++{157, 71, 88}, ++{166, 69, 92}, ++{177, 67, 97}, ++{189, 63, 103}, ++{201, 60, 108}, ++{214, 55, 113}, ++{226, 52, 118}, ++{154, 74, 86}, ++{159, 73, 89}, ++{168, 71, 93}, ++{179, 68, 98}, ++{190, 64, 103}, ++{203, 60, 109}, ++{216, 56, 114}, ++{227, 52, 118}, ++{157, 75, 87}, ++{162, 74, 90}, ++{170, 72, 94}, ++{181, 69, 99}, ++{192, 65, 104}, ++{205, 61, 109}, ++{217, 57, 114}, ++{229, 53, 119}, ++{160, 77, 88}, ++{164, 76, 91}, ++{172, 74, 95}, ++{183, 70, 99}, ++{194, 67, 104}, ++{206, 62, 110}, ++{219, 58, 115}, ++{230, 54, 119}, ++{162, 79, 90}, ++{167, 78, 92}, ++{175, 75, 95}, ++{185, 72, 100}, ++{196, 68, 105}, ++{208, 63, 110}, ++{221, 59, 115}, ++{232, 55, 119}, ++{165, 80, 91}, ++{169, 79, 93}, ++{177, 76, 96}, ++{187, 73, 101}, ++{199, 69, 106}, ++{210, 64, 111}, ++{223, 60, 116}, ++{233, 56, 120}, ++{168, 82, 92}, ++{172, 81, 94}, ++{180, 78, 97}, ++{190, 74, 102}, ++{201, 70, 106}, ++{212, 65, 111}, ++{224, 61, 116}, ++{235, 56, 120}, ++{171, 84, 93}, ++{175, 82, 95}, ++{183, 79, 98}, ++{192, 75, 102}, ++{203, 71, 107}, ++{215, 66, 112}, ++{226, 62, 117}, ++{237, 57, 121}, ++{174, 85, 94}, ++{178, 83, 96}, ++{185, 80, 99}, ++{195, 76, 103}, ++{205, 72, 108}, ++{217, 67, 112}, ++{228, 62, 117}, ++{239, 58, 121}, ++{177, 86, 95}, ++{181, 85, 97}, ++{188, 82, 100}, ++{197, 78, 104}, ++{208, 73, 108}, ++{219, 68, 113}, ++{231, 63, 118}, ++{241, 59, 121}, ++{180, 88, 96}, ++{184, 86, 98}, ++{191, 83, 101}, ++{200, 79, 105}, ++{210, 74, 109}, ++{221, 69, 114}, ++{233, 64, 118}, ++{243, 60, 122}, ++{183, 89, 97}, ++{187, 87, 99}, ++{194, 84, 102}, ++{203, 80, 106}, ++{213, 75, 110}, ++{224, 70, 114}, ++{235, 65, 119}, ++{245, 61, 122}, ++{187, 90, 98}, ++{190, 89, 100}, ++{197, 85, 103}, ++{206, 81, 107}, ++{215, 76, 111}, ++{226, 71, 115}, ++{237, 66, 119}, ++{247, 62, 123}, ++{190, 92, 99}, ++{193, 90, 101}, ++{200, 86, 104}, ++{208, 82, 107}, ++{218, 77, 111}, ++{228, 72, 115}, ++{239, 67, 120}, ++{249, 63, 123}, ++{193, 93, 101}, ++{196, 91, 102}, ++{203, 88, 105}, ++{211, 83, 108}, ++{221, 79, 112}, ++{231, 73, 116}, ++{242, 68, 120}, ++{252, 64, 124}, ++{196, 94, 102}, ++{200, 92, 103}, ++{206, 89, 106}, ++{214, 84, 109}, ++{223, 80, 113}, ++{234, 74, 117}, ++{244, 69, 121}, ++{254, 64, 124}, ++{198, 94, 102}, ++{201, 93, 103}, ++{208, 89, 106}, ++{216, 85, 109}, ++{225, 80, 113}, ++{235, 75, 117}, ++{245, 70, 121}, ++{255, 65, 124}, ++{198, 94, 102}, ++{201, 93, 103}, ++{208, 89, 106}, ++{216, 85, 109}, ++{225, 80, 113}, ++{235, 75, 117}, ++{245, 70, 121}, ++{255, 65, 124}, ++{198, 94, 102}, ++{201, 93, 103}, ++{208, 89, 106}, ++{216, 85, 109}, ++{225, 80, 113}, ++{235, 75, 117}, ++{245, 70, 121}, ++{255, 65, 124}, ++{198, 94, 102}, ++{201, 93, 103}, ++{208, 89, 106}, ++{216, 85, 109}, ++{225, 80, 113}, ++{235, 75, 117}, ++{245, 70, 121}, ++{255, 65, 124}, ++{137, 54, 75}, ++{143, 55, 78}, ++{153, 56, 84}, ++{166, 56, 90}, ++{179, 54, 97}, ++{193, 52, 103}, ++{206, 49, 109}, ++{218, 45, 114}, ++{138, 54, 75}, ++{143, 55, 78}, ++{153, 56, 84}, ++{166, 56, 90}, ++{179, 54, 97}, ++{193, 52, 103}, ++{206, 49, 109}, ++{219, 45, 114}, ++{138, 55, 76}, ++{144, 56, 79}, ++{154, 57, 84}, ++{166, 56, 90}, ++{179, 54, 97}, ++{193, 52, 103}, ++{207, 49, 109}, ++{219, 46, 114}, ++{139, 56, 76}, ++{144, 57, 79}, ++{155, 57, 84}, ++{167, 56, 91}, ++{180, 55, 97}, ++{193, 52, 103}, ++{207, 49, 109}, ++{219, 46, 114}, ++{140, 57, 76}, ++{145, 57, 79}, ++{155, 58, 85}, ++{167, 57, 91}, ++{181, 55, 97}, ++{194, 53, 103}, ++{208, 49, 109}, ++{220, 46, 114}, ++{141, 58, 77}, ++{146, 59, 80}, ++{156, 59, 85}, ++{168, 58, 91}, ++{181, 56, 97}, ++{195, 53, 103}, ++{208, 50, 109}, ++{220, 46, 114}, ++{142, 59, 78}, ++{148, 60, 81}, ++{158, 60, 86}, ++{169, 59, 92}, ++{182, 56, 98}, ++{196, 54, 104}, ++{209, 50, 110}, ++{221, 47, 114}, ++{144, 61, 79}, ++{149, 61, 81}, ++{159, 61, 86}, ++{171, 59, 92}, ++{183, 57, 98}, ++{197, 54, 104}, ++{210, 51, 110}, ++{222, 47, 115}, ++{146, 63, 79}, ++{151, 63, 82}, ++{160, 62, 87}, ++{172, 60, 93}, ++{185, 58, 99}, ++{198, 55, 104}, ++{211, 51, 110}, ++{223, 48, 115}, ++{148, 64, 80}, ++{153, 64, 83}, ++{162, 63, 88}, ++{173, 61, 93}, ++{186, 59, 99}, ++{199, 56, 105}, ++{212, 52, 110}, ++{224, 48, 115}, ++{150, 66, 81}, ++{155, 66, 84}, ++{164, 65, 88}, ++{175, 63, 94}, ++{187, 60, 100}, ++{200, 56, 105}, ++{213, 53, 111}, ++{225, 49, 115}, ++{152, 68, 82}, ++{157, 67, 85}, ++{166, 66, 89}, ++{177, 64, 95}, ++{189, 61, 100}, ++{202, 57, 106}, ++{215, 53, 111}, ++{226, 50, 116}, ++{154, 70, 83}, ++{159, 69, 86}, ++{168, 67, 90}, ++{179, 65, 95}, ++{191, 62, 101}, ++{203, 58, 106}, ++{216, 54, 111}, ++{227, 50, 116}, ++{157, 71, 84}, ++{161, 71, 87}, ++{170, 69, 91}, ++{181, 66, 96}, ++{192, 63, 101}, ++{205, 59, 107}, ++{217, 55, 112}, ++{229, 51, 116}, ++{159, 73, 85}, ++{164, 72, 88}, ++{172, 70, 92}, ++{183, 67, 97}, ++{194, 64, 102}, ++{206, 60, 107}, ++{219, 56, 112}, ++{230, 52, 117}, ++{162, 75, 86}, ++{166, 74, 89}, ++{175, 72, 93}, ++{185, 69, 97}, ++{196, 65, 102}, ++{208, 61, 108}, ++{221, 57, 113}, ++{232, 53, 117}, ++{165, 77, 88}, ++{169, 75, 90}, ++{177, 73, 94}, ++{187, 70, 98}, ++{198, 66, 103}, ++{210, 62, 108}, ++{222, 58, 113}, ++{233, 54, 117}, ++{168, 78, 89}, ++{172, 77, 91}, ++{180, 74, 94}, ++{189, 71, 99}, ++{200, 67, 104}, ++{212, 63, 109}, ++{224, 58, 114}, ++{235, 54, 118}, ++{170, 80, 90}, ++{174, 78, 92}, ++{182, 76, 95}, ++{192, 72, 100}, ++{203, 68, 104}, ++{214, 64, 109}, ++{226, 59, 114}, ++{237, 55, 118}, ++{173, 81, 91}, ++{177, 80, 93}, ++{185, 77, 96}, ++{194, 74, 101}, ++{205, 69, 105}, ++{216, 65, 110}, ++{228, 60, 115}, ++{239, 56, 119}, ++{176, 83, 92}, ++{180, 81, 94}, ++{187, 78, 97}, ++{197, 75, 101}, ++{207, 71, 106}, ++{218, 66, 111}, ++{230, 61, 115}, ++{240, 57, 119}, ++{179, 84, 93}, ++{183, 83, 95}, ++{190, 80, 98}, ++{199, 76, 102}, ++{210, 72, 107}, ++{221, 67, 111}, ++{232, 62, 116}, ++{242, 58, 120}, ++{182, 86, 94}, ++{186, 84, 96}, ++{193, 81, 99}, ++{202, 77, 103}, ++{212, 73, 107}, ++{223, 68, 112}, ++{234, 63, 116}, ++{244, 59, 120}, ++{185, 87, 95}, ++{189, 85, 97}, ++{196, 82, 100}, ++{205, 78, 104}, ++{215, 74, 108}, ++{225, 69, 112}, ++{236, 64, 117}, ++{246, 60, 121}, ++{189, 88, 97}, ++{192, 87, 98}, ++{199, 84, 101}, ++{207, 80, 105}, ++{217, 75, 109}, ++{228, 70, 113}, ++{239, 65, 117}, ++{249, 61, 121}, ++{192, 90, 98}, ++{195, 88, 99}, ++{202, 85, 102}, ++{210, 81, 106}, ++{220, 76, 109}, ++{230, 71, 114}, ++{241, 66, 118}, ++{251, 62, 122}, ++{195, 91, 99}, ++{198, 89, 100}, ++{205, 86, 103}, ++{213, 82, 106}, ++{222, 77, 110}, ++{233, 72, 114}, ++{243, 67, 118}, ++{253, 62, 122}, ++{198, 92, 100}, ++{202, 90, 101}, ++{208, 87, 104}, ++{216, 83, 107}, ++{225, 78, 111}, ++{235, 73, 115}, ++{246, 68, 119}, ++{255, 63, 123}, ++{200, 93, 100}, ++{203, 91, 102}, ++{209, 88, 104}, ++{217, 83, 108}, ++{226, 79, 111}, ++{236, 74, 115}, ++{247, 68, 119}, ++{255, 64, 123}, ++{200, 93, 100}, ++{203, 91, 102}, ++{209, 88, 104}, ++{217, 83, 108}, ++{226, 79, 111}, ++{236, 74, 115}, ++{247, 68, 119}, ++{255, 64, 123}, ++{200, 93, 100}, ++{203, 91, 102}, ++{209, 88, 104}, ++{217, 83, 108}, ++{226, 79, 111}, ++{236, 74, 115}, ++{247, 68, 119}, ++{255, 64, 123}, ++{200, 93, 100}, ++{203, 91, 102}, ++{209, 88, 104}, ++{217, 83, 108}, ++{226, 79, 111}, ++{236, 74, 115}, ++{247, 68, 119}, ++{255, 64, 123}, ++{140, 52, 73}, ++{146, 53, 77}, ++{156, 54, 82}, ++{168, 54, 88}, ++{181, 52, 95}, ++{195, 50, 101}, ++{208, 47, 107}, ++{220, 44, 112}, ++{140, 52, 74}, ++{146, 53, 77}, ++{156, 54, 82}, ++{168, 54, 88}, ++{181, 52, 95}, ++{195, 50, 101}, ++{208, 47, 107}, ++{220, 44, 112}, ++{141, 53, 74}, ++{146, 54, 77}, ++{156, 54, 82}, ++{168, 54, 88}, ++{181, 53, 95}, ++{195, 50, 101}, ++{209, 47, 107}, ++{220, 44, 112}, ++{142, 53, 74}, ++{147, 54, 77}, ++{157, 55, 83}, ++{169, 55, 89}, ++{182, 53, 95}, ++{195, 51, 101}, ++{209, 48, 107}, ++{221, 45, 112}, ++{143, 54, 75}, ++{148, 55, 78}, ++{158, 56, 83}, ++{170, 55, 89}, ++{183, 54, 95}, ++{196, 51, 101}, ++{209, 48, 107}, ++{221, 45, 112}, ++{144, 56, 75}, ++{149, 56, 78}, ++{159, 57, 83}, ++{171, 56, 89}, ++{183, 54, 95}, ++{197, 52, 102}, ++{210, 48, 107}, ++{222, 45, 112}, ++{145, 57, 76}, ++{150, 57, 79}, ++{160, 58, 84}, ++{172, 57, 90}, ++{184, 55, 96}, ++{198, 52, 102}, ++{211, 49, 108}, ++{223, 46, 112}, ++{147, 58, 77}, ++{152, 59, 79}, ++{161, 59, 84}, ++{173, 58, 90}, ++{185, 55, 96}, ++{198, 53, 102}, ++{212, 49, 108}, ++{223, 46, 113}, ++{148, 60, 78}, ++{153, 60, 80}, ++{163, 60, 85}, ++{174, 58, 91}, ++{187, 56, 97}, ++{200, 53, 102}, ++{213, 50, 108}, ++{224, 47, 113}, ++{150, 62, 78}, ++{155, 62, 81}, ++{164, 61, 86}, ++{176, 60, 91}, ++{188, 57, 97}, ++{201, 54, 103}, ++{214, 51, 108}, ++{225, 47, 113}, ++{152, 64, 79}, ++{157, 63, 82}, ++{166, 62, 87}, ++{177, 61, 92}, ++{189, 58, 98}, ++{202, 55, 103}, ++{215, 51, 109}, ++{227, 48, 113}, ++{155, 65, 80}, ++{159, 65, 83}, ++{168, 64, 87}, ++{179, 62, 93}, ++{191, 59, 98}, ++{203, 56, 104}, ++{216, 52, 109}, ++{228, 49, 114}, ++{157, 67, 81}, ++{161, 67, 84}, ++{170, 65, 88}, ++{181, 63, 93}, ++{193, 60, 99}, ++{205, 57, 104}, ++{218, 53, 110}, ++{229, 49, 114}, ++{159, 69, 82}, ++{164, 68, 85}, ++{172, 67, 89}, ++{183, 64, 94}, ++{194, 61, 99}, ++{207, 58, 105}, ++{219, 54, 110}, ++{230, 50, 114}, ++{162, 71, 84}, ++{166, 70, 86}, ++{174, 68, 90}, ++{185, 65, 95}, ++{196, 62, 100}, ++{208, 59, 105}, ++{221, 54, 110}, ++{232, 51, 115}, ++{164, 73, 85}, ++{169, 72, 87}, ++{177, 70, 91}, ++{187, 67, 95}, ++{198, 63, 101}, ++{210, 60, 106}, ++{222, 55, 111}, ++{233, 52, 115}, ++{167, 74, 86}, ++{171, 73, 88}, ++{179, 71, 92}, ++{189, 68, 96}, ++{200, 64, 101}, ++{212, 61, 106}, ++{224, 56, 111}, ++{235, 52, 116}, ++{170, 76, 87}, ++{174, 75, 89}, ++{182, 72, 93}, ++{191, 69, 97}, ++{202, 66, 102}, ++{214, 62, 107}, ++{226, 57, 112}, ++{237, 53, 116}, ++{173, 78, 88}, ++{177, 76, 90}, ++{184, 74, 93}, ++{194, 71, 98}, ++{204, 67, 103}, ++{216, 63, 107}, ++{228, 58, 112}, ++{238, 54, 116}, ++{175, 79, 89}, ++{179, 78, 91}, ++{187, 75, 94}, ++{196, 72, 99}, ++{207, 68, 103}, ++{218, 64, 108}, ++{230, 59, 113}, ++{240, 55, 117}, ++{178, 81, 90}, ++{182, 79, 92}, ++{189, 77, 95}, ++{199, 73, 100}, ++{209, 69, 104}, ++{220, 65, 109}, ++{232, 60, 113}, ++{242, 56, 117}, ++{181, 82, 91}, ++{185, 81, 93}, ++{192, 78, 96}, ++{201, 74, 100}, ++{211, 70, 105}, ++{222, 66, 109}, ++{234, 61, 114}, ++{244, 57, 118}, ++{184, 84, 92}, ++{188, 82, 94}, ++{195, 79, 97}, ++{204, 76, 101}, ++{214, 71, 105}, ++{225, 67, 110}, ++{236, 62, 114}, ++{246, 58, 118}, ++{187, 85, 94}, ++{191, 84, 95}, ++{198, 81, 98}, ++{206, 77, 102}, ++{216, 72, 106}, ++{227, 68, 111}, ++{238, 63, 115}, ++{248, 59, 119}, ++{191, 86, 95}, ++{194, 85, 96}, ++{201, 82, 99}, ++{209, 78, 103}, ++{219, 74, 107}, ++{229, 69, 111}, ++{240, 64, 116}, ++{250, 60, 119}, ++{194, 88, 96}, ++{197, 86, 97}, ++{204, 83, 100}, ++{212, 79, 104}, ++{221, 75, 108}, ++{232, 70, 112}, ++{242, 65, 116}, ++{252, 60, 120}, ++{197, 89, 97}, ++{200, 87, 98}, ++{207, 84, 101}, ++{215, 80, 105}, ++{224, 76, 108}, ++{234, 71, 112}, ++{245, 66, 117}, ++{254, 61, 120}, ++{200, 90, 98}, ++{203, 89, 99}, ++{210, 85, 102}, ++{218, 81, 105}, ++{227, 77, 109}, ++{237, 72, 113}, ++{247, 67, 117}, ++{255, 62, 121}, ++{202, 91, 98}, ++{205, 89, 100}, ++{211, 86, 102}, ++{219, 82, 106}, ++{228, 77, 110}, ++{238, 72, 113}, ++{248, 67, 118}, ++{255, 63, 121}, ++{202, 91, 98}, ++{205, 89, 100}, ++{211, 86, 102}, ++{219, 82, 106}, ++{228, 77, 110}, ++{238, 72, 113}, ++{248, 67, 118}, ++{255, 63, 121}, ++{202, 91, 98}, ++{205, 89, 100}, ++{211, 86, 102}, ++{219, 82, 106}, ++{228, 77, 110}, ++{238, 72, 113}, ++{248, 67, 118}, ++{255, 63, 121}, ++{202, 91, 98}, ++{205, 89, 100}, ++{211, 86, 102}, ++{219, 82, 106}, ++{228, 77, 110}, ++{238, 72, 113}, ++{248, 67, 118}, ++{255, 63, 121}, ++{143, 49, 72}, ++{148, 51, 75}, ++{158, 52, 80}, ++{170, 52, 86}, ++{183, 51, 93}, ++{196, 49, 99}, ++{210, 46, 105}, ++{222, 43, 110}, ++{143, 50, 72}, ++{149, 51, 75}, ++{158, 52, 80}, ++{170, 52, 86}, ++{183, 51, 93}, ++{197, 49, 99}, ++{210, 46, 105}, ++{222, 43, 110}, ++{144, 50, 72}, ++{149, 51, 75}, ++{159, 52, 80}, ++{171, 52, 87}, ++{184, 51, 93}, ++{197, 49, 99}, ++{210, 46, 105}, ++{222, 43, 110}, ++{144, 51, 72}, ++{150, 52, 75}, ++{159, 53, 81}, ++{171, 53, 87}, ++{184, 51, 93}, ++{197, 49, 99}, ++{211, 46, 105}, ++{223, 43, 110}, ++{145, 52, 73}, ++{151, 53, 76}, ++{160, 54, 81}, ++{172, 53, 87}, ++{185, 52, 93}, ++{198, 50, 99}, ++{211, 47, 105}, ++{223, 44, 110}, ++{146, 53, 73}, ++{152, 54, 76}, ++{161, 54, 81}, ++{173, 54, 87}, ++{185, 52, 94}, ++{199, 50, 100}, ++{212, 47, 105}, ++{224, 44, 110}, ++{148, 55, 74}, ++{153, 55, 77}, ++{162, 55, 82}, ++{174, 55, 88}, ++{186, 53, 94}, ++{199, 51, 100}, ++{213, 47, 106}, ++{224, 44, 111}, ++{149, 56, 75}, ++{154, 57, 78}, ++{164, 57, 83}, ++{175, 56, 88}, ++{187, 54, 94}, ++{200, 51, 100}, ++{214, 48, 106}, ++{225, 45, 111}, ++{151, 58, 76}, ++{156, 58, 78}, ++{165, 58, 83}, ++{176, 57, 89}, ++{189, 55, 95}, ++{201, 52, 101}, ++{215, 49, 106}, ++{226, 45, 111}, ++{153, 59, 77}, ++{158, 59, 79}, ++{167, 59, 84}, ++{178, 58, 89}, ++{190, 55, 95}, ++{203, 53, 101}, ++{216, 49, 107}, ++{227, 46, 111}, ++{155, 61, 78}, ++{160, 61, 80}, ++{169, 60, 85}, ++{179, 59, 90}, ++{191, 56, 96}, ++{204, 53, 101}, ++{217, 50, 107}, ++{228, 47, 112}, ++{157, 63, 79}, ++{162, 63, 81}, ++{170, 62, 85}, ++{181, 60, 91}, ++{193, 57, 96}, ++{205, 54, 102}, ++{218, 51, 107}, ++{229, 47, 112}, ++{159, 65, 80}, ++{164, 64, 82}, ++{172, 63, 86}, ++{183, 61, 91}, ++{195, 58, 97}, ++{207, 55, 102}, ++{219, 52, 108}, ++{231, 48, 112}, ++{162, 67, 81}, ++{166, 66, 83}, ++{174, 65, 87}, ++{185, 62, 92}, ++{196, 60, 97}, ++{208, 56, 103}, ++{221, 52, 108}, ++{232, 49, 113}, ++{164, 68, 82}, ++{168, 68, 84}, ++{177, 66, 88}, ++{187, 64, 93}, ++{198, 61, 98}, ++{210, 57, 103}, ++{222, 53, 109}, ++{233, 50, 113}, ++{167, 70, 83}, ++{171, 69, 85}, ++{179, 68, 89}, ++{189, 65, 94}, ++{200, 62, 99}, ++{212, 58, 104}, ++{224, 54, 109}, ++{235, 50, 113}, ++{169, 72, 84}, ++{173, 71, 86}, ++{181, 69, 90}, ++{191, 66, 94}, ++{202, 63, 99}, ++{214, 59, 104}, ++{226, 55, 109}, ++{237, 51, 114}, ++{172, 74, 85}, ++{176, 73, 87}, ++{184, 70, 91}, ++{193, 68, 95}, ++{204, 64, 100}, ++{216, 60, 105}, ++{228, 56, 110}, ++{238, 52, 114}, ++{175, 75, 86}, ++{179, 74, 88}, ++{186, 72, 92}, ++{196, 69, 96}, ++{206, 65, 101}, ++{218, 61, 106}, ++{229, 57, 110}, ++{240, 53, 115}, ++{178, 77, 87}, ++{181, 76, 89}, ++{189, 73, 93}, ++{198, 70, 97}, ++{208, 66, 101}, ++{220, 62, 106}, ++{231, 58, 111}, ++{242, 54, 115}, ++{181, 79, 88}, ++{184, 77, 90}, ++{191, 75, 94}, ++{200, 71, 98}, ++{211, 67, 102}, ++{222, 63, 107}, ++{233, 59, 112}, ++{244, 55, 116}, ++{183, 80, 90}, ++{187, 79, 91}, ++{194, 76, 94}, ++{203, 73, 98}, ++{213, 69, 103}, ++{224, 64, 107}, ++{235, 60, 112}, ++{245, 56, 116}, ++{186, 82, 91}, ++{190, 80, 92}, ++{197, 77, 95}, ++{206, 74, 99}, ++{216, 70, 104}, ++{226, 65, 108}, ++{237, 61, 113}, ++{247, 57, 117}, ++{189, 83, 92}, ++{193, 82, 93}, ++{200, 79, 96}, ++{208, 75, 100}, ++{218, 71, 104}, ++{228, 66, 109}, ++{240, 62, 113}, ++{249, 57, 117}, ++{193, 84, 93}, ++{196, 83, 94}, ++{203, 80, 97}, ++{211, 76, 101}, ++{220, 72, 105}, ++{231, 67, 109}, ++{242, 63, 114}, ++{252, 58, 118}, ++{196, 86, 94}, ++{199, 84, 95}, ++{205, 81, 98}, ++{214, 77, 102}, ++{223, 73, 106}, ++{233, 68, 110}, ++{244, 64, 114}, ++{254, 59, 118}, ++{199, 87, 95}, ++{202, 85, 97}, ++{208, 82, 99}, ++{216, 79, 103}, ++{226, 74, 107}, ++{236, 70, 111}, ++{246, 65, 115}, ++{255, 60, 119}, ++{202, 88, 96}, ++{205, 87, 98}, ++{211, 84, 100}, ++{219, 80, 104}, ++{228, 75, 107}, ++{238, 71, 111}, ++{249, 66, 115}, ++{255, 61, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{213, 84, 101}, ++{221, 80, 104}, ++{230, 76, 108}, ++{239, 71, 112}, ++{250, 66, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{213, 84, 101}, ++{221, 80, 104}, ++{230, 76, 108}, ++{239, 71, 112}, ++{250, 66, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{213, 84, 101}, ++{221, 80, 104}, ++{230, 76, 108}, ++{239, 71, 112}, ++{250, 66, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{213, 84, 101}, ++{221, 80, 104}, ++{230, 76, 108}, ++{239, 71, 112}, ++{250, 66, 116}, ++{255, 62, 119}, ++{146, 47, 70}, ++{151, 48, 73}, ++{161, 50, 78}, ++{172, 50, 84}, ++{185, 49, 91}, ++{198, 47, 97}, ++{212, 44, 103}, ++{224, 42, 108}, ++{146, 47, 70}, ++{151, 49, 73}, ++{161, 50, 78}, ++{173, 50, 84}, ++{185, 49, 91}, ++{199, 47, 97}, ++{212, 44, 103}, ++{224, 42, 108}, ++{146, 48, 70}, ++{152, 49, 73}, ++{161, 50, 79}, ++{173, 50, 85}, ++{186, 49, 91}, ++{199, 47, 97}, ++{212, 45, 103}, ++{224, 42, 108}, ++{147, 49, 71}, ++{152, 50, 74}, ++{162, 51, 79}, ++{173, 51, 85}, ++{186, 50, 91}, ++{199, 48, 97}, ++{213, 45, 103}, ++{224, 42, 108}, ++{148, 50, 71}, ++{153, 51, 74}, ++{163, 51, 79}, ++{174, 51, 85}, ++{187, 50, 91}, ++{200, 48, 97}, ++{213, 45, 103}, ++{225, 42, 108}, ++{149, 51, 72}, ++{154, 52, 75}, ++{164, 52, 80}, ++{175, 52, 86}, ++{188, 51, 92}, ++{201, 48, 98}, ++{214, 46, 104}, ++{225, 43, 108}, ++{150, 52, 72}, ++{155, 53, 75}, ++{165, 53, 80}, ++{176, 53, 86}, ++{188, 51, 92}, ++{201, 49, 98}, ++{214, 46, 104}, ++{226, 43, 109}, ++{152, 54, 73}, ++{157, 54, 76}, ++{166, 54, 81}, ++{177, 54, 86}, ++{189, 52, 92}, ++{202, 50, 98}, ++{215, 47, 104}, ++{227, 44, 109}, ++{154, 55, 74}, ++{158, 56, 77}, ++{167, 56, 81}, ++{179, 55, 87}, ++{191, 53, 93}, ++{203, 50, 99}, ++{216, 47, 104}, ++{228, 44, 109}, ++{155, 57, 75}, ++{160, 57, 77}, ++{169, 57, 82}, ++{180, 56, 88}, ++{192, 54, 93}, ++{205, 51, 99}, ++{217, 48, 105}, ++{229, 45, 109}, ++{157, 59, 76}, ++{162, 59, 78}, ++{171, 58, 83}, ++{182, 57, 88}, ++{193, 55, 94}, ++{206, 52, 99}, ++{219, 49, 105}, ++{230, 45, 110}, ++{160, 61, 77}, ++{164, 60, 79}, ++{173, 60, 84}, ++{183, 58, 89}, ++{195, 56, 94}, ++{207, 53, 100}, ++{220, 49, 105}, ++{231, 46, 110}, ++{162, 63, 78}, ++{166, 62, 80}, ++{175, 61, 84}, ++{185, 59, 89}, ++{197, 57, 95}, ++{209, 54, 100}, ++{221, 50, 106}, ++{232, 47, 110}, ++{164, 64, 79}, ++{168, 64, 81}, ++{177, 63, 85}, ++{187, 61, 90}, ++{198, 58, 96}, ++{210, 55, 101}, ++{223, 51, 106}, ++{234, 48, 111}, ++{166, 66, 80}, ++{171, 66, 82}, ++{179, 64, 86}, ++{189, 62, 91}, ++{200, 59, 96}, ++{212, 56, 101}, ++{224, 52, 107}, ++{235, 48, 111}, ++{169, 68, 81}, ++{173, 67, 83}, ++{181, 66, 87}, ++{191, 63, 92}, ++{202, 60, 97}, ++{214, 57, 102}, ++{226, 53, 107}, ++{237, 49, 112}, ++{172, 70, 82}, ++{176, 69, 84}, ++{183, 67, 88}, ++{193, 64, 92}, ++{204, 61, 97}, ++{215, 58, 103}, ++{227, 54, 108}, ++{238, 50, 112}, ++{174, 72, 83}, ++{178, 71, 85}, ++{186, 68, 89}, ++{195, 66, 93}, ++{206, 62, 98}, ++{217, 59, 103}, ++{229, 55, 108}, ++{240, 51, 112}, ++{177, 73, 84}, ++{181, 72, 86}, ++{188, 70, 90}, ++{198, 67, 94}, ++{208, 64, 99}, ++{219, 60, 104}, ++{231, 56, 109}, ++{241, 52, 113}, ++{180, 75, 85}, ++{184, 74, 87}, ++{191, 71, 91}, ++{200, 68, 95}, ++{210, 65, 100}, ++{221, 61, 104}, ++{233, 57, 109}, ++{243, 53, 113}, ++{183, 76, 87}, ++{186, 75, 88}, ++{193, 73, 92}, ++{202, 70, 96}, ++{213, 66, 100}, ++{223, 62, 105}, ++{235, 57, 110}, ++{245, 54, 114}, ++{186, 78, 88}, ++{189, 77, 89}, ++{196, 74, 93}, ++{205, 71, 97}, ++{215, 67, 101}, ++{226, 63, 106}, ++{237, 58, 110}, ++{247, 54, 114}, ++{189, 80, 89}, ++{192, 78, 90}, ++{199, 76, 94}, ++{207, 72, 98}, ++{217, 68, 102}, ++{228, 64, 106}, ++{239, 59, 111}, ++{249, 55, 115}, ++{192, 81, 90}, ++{195, 80, 92}, ++{202, 77, 95}, ++{210, 73, 98}, ++{220, 69, 103}, ++{230, 65, 107}, ++{241, 60, 111}, ++{251, 56, 115}, ++{195, 82, 91}, ++{198, 81, 93}, ++{204, 78, 96}, ++{213, 75, 99}, ++{222, 71, 103}, ++{232, 66, 108}, ++{243, 61, 112}, ++{253, 57, 116}, ++{198, 84, 92}, ++{201, 82, 94}, ++{207, 79, 97}, ++{215, 76, 100}, ++{225, 72, 104}, ++{235, 67, 108}, ++{246, 62, 113}, ++{255, 58, 116}, ++{201, 85, 93}, ++{204, 84, 95}, ++{210, 81, 97}, ++{218, 77, 101}, ++{227, 73, 105}, ++{237, 68, 109}, ++{248, 63, 113}, ++{255, 59, 117}, ++{204, 86, 94}, ++{207, 85, 96}, ++{213, 82, 98}, ++{221, 78, 102}, ++{230, 74, 106}, ++{240, 69, 110}, ++{250, 64, 114}, ++{255, 60, 117}, ++{205, 87, 95}, ++{209, 85, 96}, ++{215, 82, 99}, ++{222, 79, 102}, ++{231, 74, 106}, ++{241, 70, 110}, ++{251, 65, 114}, ++{255, 61, 118}, ++{205, 87, 95}, ++{209, 85, 96}, ++{215, 82, 99}, ++{222, 79, 102}, ++{231, 74, 106}, ++{241, 70, 110}, ++{251, 65, 114}, ++{255, 61, 118}, ++{205, 87, 95}, ++{209, 85, 96}, ++{215, 82, 99}, ++{222, 79, 102}, ++{231, 74, 106}, ++{241, 70, 110}, ++{251, 65, 114}, ++{255, 61, 118}, ++{205, 87, 95}, ++{209, 85, 96}, ++{215, 82, 99}, ++{222, 79, 102}, ++{231, 74, 106}, ++{241, 70, 110}, ++{251, 65, 114}, ++{255, 61, 118}, ++{148, 45, 68}, ++{154, 46, 71}, ++{163, 48, 77}, ++{175, 48, 83}, ++{187, 47, 89}, ++{200, 45, 95}, ++{214, 43, 101}, ++{225, 40, 106}, ++{149, 45, 68}, ++{154, 46, 71}, ++{163, 48, 77}, ++{175, 48, 83}, ++{187, 47, 89}, ++{200, 46, 95}, ++{214, 43, 101}, ++{225, 40, 106}, ++{149, 46, 69}, ++{154, 47, 72}, ++{164, 48, 77}, ++{175, 48, 83}, ++{188, 48, 89}, ++{201, 46, 95}, ++{214, 43, 101}, ++{226, 41, 106}, ++{150, 46, 69}, ++{155, 47, 72}, ++{164, 49, 77}, ++{176, 49, 83}, ++{188, 48, 89}, ++{201, 46, 95}, ++{214, 43, 101}, ++{226, 41, 106}, ++{151, 47, 69}, ++{156, 48, 72}, ++{165, 49, 77}, ++{176, 49, 83}, ++{189, 48, 89}, ++{202, 46, 96}, ++{215, 44, 101}, ++{226, 41, 106}, ++{152, 49, 70}, ++{157, 49, 73}, ++{166, 50, 78}, ++{177, 50, 84}, ++{190, 49, 90}, ++{202, 47, 96}, ++{216, 44, 102}, ++{227, 42, 107}, ++{153, 50, 71}, ++{158, 51, 73}, ++{167, 51, 78}, ++{178, 51, 84}, ++{191, 50, 90}, ++{203, 47, 96}, ++{216, 45, 102}, ++{228, 42, 107}, ++{155, 51, 71}, ++{159, 52, 74}, ++{168, 52, 79}, ++{179, 52, 85}, ++{192, 50, 90}, ++{204, 48, 96}, ++{217, 45, 102}, ++{229, 42, 107}, ++{156, 53, 72}, ++{161, 53, 75}, ++{170, 54, 80}, ++{181, 53, 85}, ++{193, 51, 91}, ++{205, 49, 97}, ++{218, 46, 102}, ++{229, 43, 107}, ++{158, 55, 73}, ++{163, 55, 76}, ++{171, 55, 80}, ++{182, 54, 86}, ++{194, 52, 91}, ++{206, 50, 97}, ++{219, 47, 103}, ++{230, 44, 108}, ++{160, 57, 74}, ++{165, 57, 76}, ++{173, 56, 81}, ++{184, 55, 86}, ++{195, 53, 92}, ++{208, 50, 98}, ++{220, 47, 103}, ++{232, 44, 108}, ++{162, 58, 75}, ++{166, 58, 77}, ++{175, 58, 82}, ++{185, 56, 87}, ++{197, 54, 92}, ++{209, 51, 98}, ++{222, 48, 104}, ++{233, 45, 108}, ++{164, 60, 76}, ++{169, 60, 78}, ++{177, 59, 83}, ++{187, 57, 88}, ++{198, 55, 93}, ++{211, 52, 99}, ++{223, 49, 104}, ++{234, 46, 109}, ++{166, 62, 77}, ++{171, 62, 79}, ++{179, 61, 83}, ++{189, 59, 88}, ++{200, 56, 94}, ++{212, 53, 99}, ++{224, 50, 104}, ++{235, 46, 109}, ++{169, 64, 78}, ++{173, 63, 80}, ++{181, 62, 84}, ++{191, 60, 89}, ++{202, 57, 94}, ++{214, 54, 100}, ++{226, 51, 105}, ++{237, 47, 109}, ++{171, 66, 79}, ++{175, 65, 81}, ++{183, 64, 85}, ++{193, 61, 90}, ++{204, 58, 95}, ++{215, 55, 100}, ++{227, 51, 105}, ++{238, 48, 110}, ++{174, 68, 80}, ++{178, 67, 82}, ++{185, 65, 86}, ++{195, 63, 91}, ++{206, 60, 96}, ++{217, 56, 101}, ++{229, 52, 106}, ++{240, 49, 110}, ++{176, 69, 81}, ++{180, 68, 83}, ++{188, 67, 87}, ++{197, 64, 91}, ++{208, 61, 96}, ++{219, 57, 101}, ++{231, 53, 106}, ++{241, 50, 111}, ++{179, 71, 83}, ++{183, 70, 84}, ++{190, 68, 88}, ++{200, 65, 92}, ++{210, 62, 97}, ++{221, 58, 102}, ++{233, 54, 107}, ++{243, 51, 111}, ++{182, 73, 84}, ++{186, 72, 85}, ++{193, 69, 89}, ++{202, 67, 93}, ++{212, 63, 98}, ++{223, 59, 103}, ++{235, 55, 107}, ++{245, 51, 112}, ++{185, 74, 85}, ++{188, 73, 87}, ++{195, 71, 90}, ++{204, 68, 94}, ++{214, 64, 98}, ++{225, 60, 103}, ++{237, 56, 108}, ++{247, 52, 112}, ++{188, 76, 86}, ++{191, 75, 88}, ++{198, 72, 91}, ++{207, 69, 95}, ++{217, 65, 99}, ++{227, 61, 104}, ++{239, 57, 108}, ++{249, 53, 113}, ++{191, 78, 87}, ++{194, 76, 89}, ++{201, 74, 92}, ++{209, 70, 96}, ++{219, 67, 100}, ++{230, 63, 104}, ++{241, 58, 109}, ++{251, 54, 113}, ++{194, 79, 88}, ++{197, 78, 90}, ++{204, 75, 93}, ++{212, 72, 97}, ++{221, 68, 101}, ++{232, 64, 105}, ++{243, 59, 110}, ++{253, 55, 114}, ++{197, 80, 89}, ++{200, 79, 91}, ++{206, 76, 94}, ++{215, 73, 97}, ++{224, 69, 102}, ++{234, 65, 106}, ++{245, 60, 110}, ++{255, 56, 114}, ++{200, 82, 90}, ++{203, 80, 92}, ++{209, 78, 95}, ++{217, 74, 98}, ++{226, 70, 102}, ++{236, 66, 107}, ++{247, 61, 111}, ++{255, 57, 115}, ++{203, 83, 91}, ++{206, 82, 93}, ++{212, 79, 96}, ++{220, 75, 99}, ++{229, 71, 103}, ++{239, 67, 107}, ++{249, 62, 111}, ++{255, 58, 115}, ++{206, 85, 93}, ++{209, 83, 94}, ++{215, 80, 97}, ++{223, 77, 100}, ++{232, 72, 104}, ++{241, 68, 108}, ++{252, 63, 112}, ++{255, 59, 116}, ++{207, 85, 93}, ++{210, 84, 95}, ++{216, 81, 97}, ++{224, 77, 100}, ++{233, 73, 104}, ++{243, 68, 108}, ++{253, 64, 112}, ++{255, 59, 116}, ++{207, 85, 93}, ++{210, 84, 95}, ++{216, 81, 97}, ++{224, 77, 100}, ++{233, 73, 104}, ++{243, 68, 108}, ++{253, 64, 112}, ++{255, 59, 116}, ++{207, 85, 93}, ++{210, 84, 95}, ++{216, 81, 97}, ++{224, 77, 100}, ++{233, 73, 104}, ++{243, 68, 108}, ++{253, 64, 112}, ++{255, 59, 116}, ++{207, 85, 93}, ++{210, 84, 95}, ++{216, 81, 97}, ++{224, 77, 100}, ++{233, 73, 104}, ++{243, 68, 108}, ++{253, 64, 112}, ++{255, 59, 116}, ++{151, 43, 67}, ++{156, 44, 70}, ++{166, 45, 75}, ++{177, 46, 81}, ++{189, 45, 87}, ++{202, 44, 93}, ++{215, 42, 99}, ++{227, 39, 104}, ++{151, 43, 67}, ++{156, 44, 70}, ++{166, 46, 75}, ++{177, 46, 81}, ++{190, 46, 87}, ++{202, 44, 93}, ++{216, 42, 99}, ++{227, 39, 104}, ++{152, 43, 67}, ++{157, 45, 70}, ++{166, 46, 75}, ++{177, 46, 81}, ++{190, 46, 87}, ++{203, 44, 93}, ++{216, 42, 99}, ++{227, 39, 104}, ++{152, 44, 67}, ++{157, 45, 70}, ++{167, 47, 75}, ++{178, 47, 81}, ++{190, 46, 87}, ++{203, 44, 93}, ++{216, 42, 99}, ++{228, 40, 104}, ++{153, 45, 68}, ++{158, 46, 71}, ++{167, 47, 76}, ++{179, 47, 81}, ++{191, 47, 88}, ++{204, 45, 94}, ++{217, 42, 100}, ++{228, 40, 105}, ++{154, 46, 68}, ++{159, 47, 71}, ++{168, 48, 76}, ++{180, 48, 82}, ++{192, 47, 88}, ++{204, 45, 94}, ++{217, 43, 100}, ++{229, 40, 105}, ++{156, 48, 69}, ++{161, 48, 72}, ++{170, 49, 77}, ++{180, 49, 82}, ++{193, 48, 88}, ++{205, 46, 94}, ++{218, 43, 100}, ++{229, 41, 105}, ++{157, 49, 70}, ++{162, 50, 72}, ++{171, 50, 77}, ++{182, 50, 83}, ++{194, 49, 89}, ++{206, 47, 94}, ++{219, 44, 100}, ++{230, 41, 105}, ++{159, 51, 71}, ++{163, 51, 73}, ++{172, 51, 78}, ++{183, 51, 83}, ++{195, 49, 89}, ++{207, 47, 95}, ++{220, 44, 101}, ++{231, 42, 105}, ++{160, 53, 71}, ++{165, 53, 74}, ++{174, 53, 78}, ++{184, 52, 84}, ++{196, 50, 90}, ++{208, 48, 95}, ++{221, 45, 101}, ++{232, 42, 106}, ++{162, 54, 72}, ++{167, 54, 75}, ++{175, 54, 79}, ++{186, 53, 84}, ++{197, 51, 90}, ++{210, 49, 96}, ++{222, 46, 101}, ++{233, 43, 106}, ++{164, 56, 73}, ++{169, 56, 76}, ++{177, 56, 80}, ++{187, 54, 85}, ++{199, 52, 91}, ++{211, 50, 96}, ++{223, 47, 102}, ++{234, 44, 106}, ++{167, 58, 74}, ++{171, 58, 77}, ++{179, 57, 81}, ++{189, 56, 86}, ++{200, 53, 91}, ++{212, 51, 97}, ++{225, 47, 102}, ++{236, 44, 107}, ++{169, 60, 75}, ++{173, 59, 77}, ++{181, 58, 82}, ++{191, 57, 87}, ++{202, 54, 92}, ++{214, 52, 97}, ++{226, 48, 103}, ++{237, 45, 107}, ++{171, 62, 76}, ++{175, 61, 78}, ++{183, 60, 82}, ++{193, 58, 87}, ++{204, 56, 92}, ++{216, 53, 98}, ++{228, 49, 103}, ++{238, 46, 107}, ++{174, 63, 77}, ++{178, 63, 79}, ++{185, 61, 83}, ++{195, 59, 88}, ++{206, 57, 93}, ++{217, 54, 98}, ++{229, 50, 103}, ++{240, 47, 108}, ++{176, 65, 78}, ++{180, 65, 81}, ++{188, 63, 84}, ++{197, 61, 89}, ++{208, 58, 94}, ++{219, 55, 99}, ++{231, 51, 104}, ++{241, 48, 108}, ++{179, 67, 80}, ++{183, 66, 82}, ++{190, 65, 85}, ++{199, 62, 90}, ++{210, 59, 94}, ++{221, 56, 99}, ++{233, 52, 104}, ++{243, 48, 109}, ++{181, 69, 81}, ++{185, 68, 83}, ++{192, 66, 86}, ++{201, 63, 90}, ++{212, 60, 95}, ++{223, 57, 100}, ++{234, 53, 105}, ++{245, 49, 109}, ++{184, 71, 82}, ++{188, 70, 84}, ++{195, 68, 87}, ++{204, 65, 91}, ++{214, 62, 96}, ++{225, 58, 101}, ++{236, 54, 106}, ++{246, 50, 110}, ++{187, 72, 83}, ++{191, 71, 85}, ++{197, 69, 88}, ++{206, 66, 92}, ++{216, 63, 97}, ++{227, 59, 101}, ++{238, 55, 106}, ++{248, 51, 110}, ++{190, 74, 84}, ++{193, 73, 86}, ++{200, 70, 89}, ++{209, 67, 93}, ++{218, 64, 97}, ++{229, 60, 102}, ++{240, 56, 107}, ++{250, 52, 111}, ++{193, 75, 85}, ++{196, 74, 87}, ++{203, 72, 90}, ++{211, 69, 94}, ++{221, 65, 98}, ++{231, 61, 103}, ++{242, 57, 107}, ++{252, 53, 111}, ++{196, 77, 86}, ++{199, 76, 88}, ++{205, 73, 91}, ++{214, 70, 95}, ++{223, 66, 99}, ++{233, 62, 103}, ++{244, 58, 108}, ++{254, 54, 112}, ++{199, 78, 87}, ++{202, 77, 89}, ++{208, 75, 92}, ++{216, 71, 96}, ++{226, 67, 100}, ++{236, 63, 104}, ++{246, 59, 108}, ++{255, 55, 112}, ++{202, 80, 89}, ++{205, 79, 90}, ++{211, 76, 93}, ++{219, 73, 97}, ++{228, 69, 101}, ++{238, 64, 105}, ++{249, 60, 109}, ++{255, 56, 113}, ++{205, 81, 90}, ++{208, 80, 91}, ++{214, 77, 94}, ++{222, 74, 97}, ++{231, 70, 101}, ++{241, 65, 105}, ++{251, 61, 110}, ++{255, 57, 113}, ++{208, 83, 91}, ++{211, 81, 92}, ++{217, 78, 95}, ++{224, 75, 98}, ++{233, 71, 102}, ++{243, 67, 106}, ++{253, 62, 110}, ++{255, 58, 114}, ++{209, 83, 91}, ++{212, 82, 93}, ++{218, 79, 95}, ++{226, 76, 99}, ++{235, 71, 102}, ++{244, 67, 106}, ++{254, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{212, 82, 93}, ++{218, 79, 95}, ++{226, 76, 99}, ++{235, 71, 102}, ++{244, 67, 106}, ++{254, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{212, 82, 93}, ++{218, 79, 95}, ++{226, 76, 99}, ++{235, 71, 102}, ++{244, 67, 106}, ++{254, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{212, 82, 93}, ++{218, 79, 95}, ++{226, 76, 99}, ++{235, 71, 102}, ++{244, 67, 106}, ++{254, 62, 111}, ++{255, 58, 114}, ++{154, 40, 65}, ++{159, 42, 68}, ++{168, 43, 73}, ++{179, 44, 79}, ++{192, 44, 85}, ++{204, 42, 91}, ++{217, 40, 97}, ++{229, 38, 102}, ++{154, 41, 65}, ++{159, 42, 68}, ++{168, 44, 73}, ++{179, 44, 79}, ++{192, 44, 85}, ++{204, 42, 91}, ++{217, 40, 97}, ++{229, 38, 102}, ++{154, 41, 65}, ++{159, 42, 68}, ++{169, 44, 73}, ++{180, 45, 79}, ++{192, 44, 85}, ++{205, 43, 91}, ++{218, 40, 97}, ++{229, 38, 102}, ++{155, 42, 66}, ++{160, 43, 69}, ++{169, 44, 74}, ++{180, 45, 79}, ++{192, 44, 85}, ++{205, 43, 92}, ++{218, 41, 98}, ++{229, 38, 103}, ++{156, 43, 66}, ++{161, 44, 69}, ++{170, 45, 74}, ++{181, 46, 80}, ++{193, 45, 86}, ++{206, 43, 92}, ++{219, 41, 98}, ++{230, 39, 103}, ++{157, 44, 67}, ++{162, 45, 69}, ++{171, 46, 74}, ++{182, 46, 80}, ++{194, 45, 86}, ++{206, 44, 92}, ++{219, 41, 98}, ++{230, 39, 103}, ++{158, 45, 67}, ++{163, 46, 70}, ++{172, 47, 75}, ++{183, 47, 80}, ++{195, 46, 86}, ++{207, 44, 92}, ++{220, 42, 98}, ++{231, 39, 103}, ++{160, 47, 68}, ++{164, 48, 71}, ++{173, 48, 75}, ++{184, 48, 81}, ++{196, 47, 87}, ++{208, 45, 93}, ++{221, 42, 98}, ++{232, 40, 103}, ++{161, 49, 69}, ++{166, 49, 71}, ++{174, 49, 76}, ++{185, 49, 81}, ++{197, 48, 87}, ++{209, 46, 93}, ++{222, 43, 99}, ++{233, 40, 104}, ++{163, 50, 70}, ++{168, 51, 72}, ++{176, 51, 77}, ++{186, 50, 82}, ++{198, 49, 88}, ++{210, 46, 93}, ++{223, 44, 99}, ++{234, 41, 104}, ++{165, 52, 71}, ++{169, 52, 73}, ++{178, 52, 77}, ++{188, 51, 83}, ++{199, 50, 88}, ++{211, 47, 94}, ++{224, 44, 99}, ++{235, 42, 104}, ++{167, 54, 72}, ++{171, 54, 74}, ++{179, 53, 78}, ++{190, 52, 83}, ++{201, 51, 89}, ++{213, 48, 94}, ++{225, 45, 100}, ++{236, 42, 105}, ++{169, 56, 73}, ++{173, 56, 75}, ++{181, 55, 79}, ++{191, 54, 84}, ++{202, 52, 89}, ++{214, 49, 95}, ++{226, 46, 100}, ++{237, 43, 105}, ++{171, 58, 74}, ++{175, 57, 76}, ++{183, 56, 80}, ++{193, 55, 85}, ++{204, 53, 90}, ++{216, 50, 95}, ++{228, 47, 101}, ++{239, 44, 105}, ++{173, 59, 75}, ++{178, 59, 77}, ++{185, 58, 81}, ++{195, 56, 85}, ++{206, 54, 91}, ++{217, 51, 96}, ++{229, 48, 101}, ++{240, 45, 106}, ++{176, 61, 76}, ++{180, 61, 78}, ++{187, 59, 82}, ++{197, 58, 86}, ++{208, 55, 91}, ++{219, 52, 96}, ++{231, 49, 102}, ++{241, 45, 106}, ++{178, 63, 77}, ++{182, 62, 79}, ++{190, 61, 82}, ++{199, 59, 87}, ++{210, 56, 92}, ++{221, 53, 97}, ++{233, 50, 102}, ++{243, 46, 107}, ++{181, 65, 78}, ++{185, 64, 80}, ++{192, 63, 83}, ++{201, 60, 88}, ++{212, 57, 93}, ++{223, 54, 98}, ++{234, 51, 103}, ++{245, 47, 107}, ++{184, 67, 79}, ++{187, 66, 81}, ++{194, 64, 84}, ++{203, 62, 89}, ++{214, 59, 93}, ++{225, 55, 98}, ++{236, 52, 103}, ++{246, 48, 107}, ++{186, 68, 80}, ++{190, 67, 82}, ++{197, 66, 85}, ++{206, 63, 90}, ++{216, 60, 94}, ++{227, 56, 99}, ++{238, 53, 104}, ++{248, 49, 108}, ++{189, 70, 81}, ++{193, 69, 83}, ++{199, 67, 86}, ++{208, 64, 90}, ++{218, 61, 95}, ++{229, 57, 100}, ++{240, 54, 104}, ++{250, 50, 108}, ++{192, 72, 82}, ++{195, 71, 84}, ++{202, 69, 87}, ++{211, 66, 91}, ++{220, 62, 96}, ++{231, 59, 100}, ++{242, 55, 105}, ++{252, 51, 109}, ++{195, 73, 83}, ++{198, 72, 85}, ++{205, 70, 88}, ++{213, 67, 92}, ++{223, 64, 96}, ++{233, 60, 101}, ++{244, 56, 106}, ++{254, 52, 110}, ++{198, 75, 85}, ++{201, 74, 86}, ++{207, 71, 89}, ++{216, 68, 93}, ++{225, 65, 97}, ++{235, 61, 102}, ++{246, 57, 106}, ++{255, 53, 110}, ++{201, 76, 86}, ++{204, 75, 87}, ++{210, 73, 90}, ++{218, 70, 94}, ++{227, 66, 98}, ++{237, 62, 102}, ++{248, 58, 107}, ++{255, 54, 111}, ++{203, 78, 87}, ++{207, 77, 88}, ++{213, 74, 91}, ++{221, 71, 95}, ++{230, 67, 99}, ++{240, 63, 103}, ++{250, 59, 107}, ++{255, 55, 111}, ++{207, 79, 88}, ++{210, 78, 89}, ++{216, 75, 92}, ++{223, 72, 96}, ++{232, 68, 100}, ++{242, 64, 104}, ++{252, 60, 108}, ++{255, 56, 112}, ++{210, 81, 89}, ++{213, 79, 90}, ++{219, 77, 93}, ++{226, 73, 97}, ++{235, 69, 100}, ++{245, 65, 104}, ++{255, 61, 109}, ++{255, 57, 112}, ++{211, 81, 90}, ++{214, 80, 91}, ++{220, 77, 94}, ++{228, 74, 97}, ++{236, 70, 101}, ++{246, 66, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{214, 80, 91}, ++{220, 77, 94}, ++{228, 74, 97}, ++{236, 70, 101}, ++{246, 66, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{214, 80, 91}, ++{220, 77, 94}, ++{228, 74, 97}, ++{236, 70, 101}, ++{246, 66, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{214, 80, 91}, ++{220, 77, 94}, ++{228, 74, 97}, ++{236, 70, 101}, ++{246, 66, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{155, 39, 64}, ++{160, 41, 67}, ++{169, 42, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 39, 96}, ++{230, 37, 101}, ++{155, 40, 64}, ++{160, 41, 67}, ++{169, 43, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 40, 96}, ++{230, 37, 101}, ++{156, 40, 65}, ++{161, 41, 67}, ++{170, 43, 72}, ++{181, 44, 78}, ++{193, 43, 84}, ++{206, 42, 91}, ++{219, 40, 96}, ++{230, 37, 102}, ++{156, 41, 65}, ++{161, 42, 68}, ++{170, 43, 73}, ++{181, 44, 78}, ++{193, 43, 85}, ++{206, 42, 91}, ++{219, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{162, 43, 68}, ++{171, 44, 73}, ++{182, 45, 79}, ++{194, 44, 85}, ++{207, 42, 91}, ++{219, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{163, 44, 69}, ++{172, 45, 73}, ++{183, 45, 79}, ++{195, 45, 85}, ++{207, 43, 91}, ++{220, 41, 97}, ++{231, 38, 102}, ++{160, 44, 67}, ++{164, 45, 69}, ++{173, 46, 74}, ++{184, 46, 80}, ++{196, 45, 85}, ++{208, 44, 91}, ++{221, 41, 97}, ++{232, 39, 102}, ++{161, 46, 67}, ++{166, 46, 70}, ++{174, 47, 74}, ++{185, 47, 80}, ++{197, 46, 86}, ++{209, 44, 92}, ++{222, 42, 97}, ++{233, 39, 102}, ++{163, 47, 68}, ++{167, 48, 71}, ++{176, 48, 75}, ++{186, 48, 81}, ++{198, 47, 86}, ++{210, 45, 92}, ++{223, 42, 98}, ++{234, 40, 103}, ++{164, 49, 69}, ++{169, 49, 71}, ++{177, 50, 76}, ++{188, 49, 81}, ++{199, 48, 87}, ++{211, 46, 93}, ++{224, 43, 98}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 72}, ++{179, 51, 77}, ++{189, 50, 82}, ++{200, 49, 87}, ++{212, 47, 93}, ++{225, 44, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{172, 53, 73}, ++{181, 52, 77}, ++{191, 51, 82}, ++{202, 50, 88}, ++{214, 47, 93}, ++{226, 45, 99}, ++{237, 42, 104}, ++{170, 55, 72}, ++{174, 54, 74}, ++{182, 54, 78}, ++{192, 53, 83}, ++{203, 51, 88}, ++{215, 48, 94}, ++{227, 45, 99}, ++{238, 42, 104}, ++{172, 56, 73}, ++{177, 56, 75}, ++{184, 55, 79}, ++{194, 54, 84}, ++{205, 52, 89}, ++{217, 49, 94}, ++{229, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{179, 58, 76}, ++{186, 57, 80}, ++{196, 55, 85}, ++{207, 53, 90}, ++{218, 50, 95}, ++{230, 47, 100}, ++{241, 44, 105}, ++{177, 60, 75}, ++{181, 60, 77}, ++{189, 58, 81}, ++{198, 57, 85}, ++{209, 54, 90}, ++{220, 51, 96}, ++{232, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{183, 61, 78}, ++{191, 60, 82}, ++{200, 58, 86}, ++{211, 55, 91}, ++{222, 52, 96}, ++{233, 49, 101}, ++{244, 46, 106}, ++{182, 64, 77}, ++{186, 63, 79}, ++{193, 62, 83}, ++{202, 59, 87}, ++{213, 57, 92}, ++{224, 53, 97}, ++{235, 50, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{188, 65, 80}, ++{195, 63, 83}, ++{204, 61, 88}, ++{215, 58, 93}, ++{225, 55, 97}, ++{237, 51, 102}, ++{247, 47, 107}, ++{187, 67, 79}, ++{191, 66, 81}, ++{198, 65, 84}, ++{207, 62, 89}, ++{217, 59, 93}, ++{227, 56, 98}, ++{239, 52, 103}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{200, 66, 85}, ++{209, 63, 89}, ++{219, 60, 94}, ++{230, 57, 99}, ++{241, 53, 103}, ++{251, 49, 108}, ++{193, 71, 81}, ++{196, 70, 83}, ++{203, 68, 86}, ++{211, 65, 90}, ++{221, 62, 95}, ++{232, 58, 99}, ++{243, 54, 104}, ++{252, 50, 108}, ++{196, 72, 83}, ++{199, 71, 84}, ++{206, 69, 87}, ++{214, 66, 91}, ++{223, 63, 96}, ++{234, 59, 100}, ++{245, 55, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{202, 73, 85}, ++{208, 70, 88}, ++{216, 67, 92}, ++{226, 64, 96}, ++{236, 60, 101}, ++{247, 56, 105}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 86}, ++{211, 72, 89}, ++{219, 69, 93}, ++{228, 65, 97}, ++{238, 61, 101}, ++{249, 57, 106}, ++{255, 53, 110}, ++{204, 77, 86}, ++{208, 76, 87}, ++{214, 73, 90}, ++{222, 70, 94}, ++{231, 66, 98}, ++{241, 62, 102}, ++{251, 58, 106}, ++{255, 54, 110}, ++{207, 78, 87}, ++{211, 77, 89}, ++{217, 75, 91}, ++{224, 71, 95}, ++{233, 67, 99}, ++{243, 63, 103}, ++{253, 59, 107}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{219, 76, 92}, ++{227, 72, 96}, ++{236, 69, 100}, ++{245, 64, 104}, ++{255, 60, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{155, 39, 64}, ++{160, 41, 67}, ++{169, 42, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 39, 96}, ++{230, 37, 101}, ++{155, 40, 64}, ++{160, 41, 67}, ++{169, 43, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 40, 96}, ++{230, 37, 101}, ++{156, 40, 65}, ++{161, 41, 67}, ++{170, 43, 72}, ++{181, 44, 78}, ++{193, 43, 84}, ++{206, 42, 91}, ++{219, 40, 96}, ++{230, 37, 102}, ++{156, 41, 65}, ++{161, 42, 68}, ++{170, 43, 73}, ++{181, 44, 78}, ++{193, 43, 85}, ++{206, 42, 91}, ++{219, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{162, 43, 68}, ++{171, 44, 73}, ++{182, 45, 79}, ++{194, 44, 85}, ++{207, 42, 91}, ++{219, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{163, 44, 69}, ++{172, 45, 73}, ++{183, 45, 79}, ++{195, 45, 85}, ++{207, 43, 91}, ++{220, 41, 97}, ++{231, 38, 102}, ++{160, 44, 67}, ++{164, 45, 69}, ++{173, 46, 74}, ++{184, 46, 80}, ++{196, 45, 85}, ++{208, 44, 91}, ++{221, 41, 97}, ++{232, 39, 102}, ++{161, 46, 67}, ++{166, 46, 70}, ++{174, 47, 74}, ++{185, 47, 80}, ++{197, 46, 86}, ++{209, 44, 92}, ++{222, 42, 97}, ++{233, 39, 102}, ++{163, 47, 68}, ++{167, 48, 71}, ++{176, 48, 75}, ++{186, 48, 81}, ++{198, 47, 86}, ++{210, 45, 92}, ++{223, 42, 98}, ++{234, 40, 103}, ++{164, 49, 69}, ++{169, 49, 71}, ++{177, 50, 76}, ++{188, 49, 81}, ++{199, 48, 87}, ++{211, 46, 93}, ++{224, 43, 98}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 72}, ++{179, 51, 77}, ++{189, 50, 82}, ++{200, 49, 87}, ++{212, 47, 93}, ++{225, 44, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{172, 53, 73}, ++{181, 52, 77}, ++{191, 51, 82}, ++{202, 50, 88}, ++{214, 47, 93}, ++{226, 45, 99}, ++{237, 42, 104}, ++{170, 55, 72}, ++{174, 54, 74}, ++{182, 54, 78}, ++{192, 53, 83}, ++{203, 51, 88}, ++{215, 48, 94}, ++{227, 45, 99}, ++{238, 42, 104}, ++{172, 56, 73}, ++{177, 56, 75}, ++{184, 55, 79}, ++{194, 54, 84}, ++{205, 52, 89}, ++{217, 49, 94}, ++{229, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{179, 58, 76}, ++{186, 57, 80}, ++{196, 55, 85}, ++{207, 53, 90}, ++{218, 50, 95}, ++{230, 47, 100}, ++{241, 44, 105}, ++{177, 60, 75}, ++{181, 60, 77}, ++{189, 58, 81}, ++{198, 57, 85}, ++{209, 54, 90}, ++{220, 51, 96}, ++{232, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{183, 61, 78}, ++{191, 60, 82}, ++{200, 58, 86}, ++{211, 55, 91}, ++{222, 52, 96}, ++{233, 49, 101}, ++{244, 46, 106}, ++{182, 64, 77}, ++{186, 63, 79}, ++{193, 62, 83}, ++{202, 59, 87}, ++{213, 57, 92}, ++{224, 53, 97}, ++{235, 50, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{188, 65, 80}, ++{195, 63, 83}, ++{204, 61, 88}, ++{215, 58, 93}, ++{225, 55, 97}, ++{237, 51, 102}, ++{247, 47, 107}, ++{187, 67, 79}, ++{191, 66, 81}, ++{198, 65, 84}, ++{207, 62, 89}, ++{217, 59, 93}, ++{227, 56, 98}, ++{239, 52, 103}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{200, 66, 85}, ++{209, 63, 89}, ++{219, 60, 94}, ++{230, 57, 99}, ++{241, 53, 103}, ++{251, 49, 108}, ++{193, 71, 81}, ++{196, 70, 83}, ++{203, 68, 86}, ++{211, 65, 90}, ++{221, 62, 95}, ++{232, 58, 99}, ++{243, 54, 104}, ++{252, 50, 108}, ++{196, 72, 83}, ++{199, 71, 84}, ++{206, 69, 87}, ++{214, 66, 91}, ++{223, 63, 96}, ++{234, 59, 100}, ++{245, 55, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{202, 73, 85}, ++{208, 70, 88}, ++{216, 67, 92}, ++{226, 64, 96}, ++{236, 60, 101}, ++{247, 56, 105}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 86}, ++{211, 72, 89}, ++{219, 69, 93}, ++{228, 65, 97}, ++{238, 61, 101}, ++{249, 57, 106}, ++{255, 53, 110}, ++{204, 77, 86}, ++{208, 76, 87}, ++{214, 73, 90}, ++{222, 70, 94}, ++{231, 66, 98}, ++{241, 62, 102}, ++{251, 58, 106}, ++{255, 54, 110}, ++{207, 78, 87}, ++{211, 77, 89}, ++{217, 75, 91}, ++{224, 71, 95}, ++{233, 67, 99}, ++{243, 63, 103}, ++{253, 59, 107}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{219, 76, 92}, ++{227, 72, 96}, ++{236, 69, 100}, ++{245, 64, 104}, ++{255, 60, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{155, 39, 64}, ++{160, 41, 67}, ++{169, 42, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 39, 96}, ++{230, 37, 101}, ++{155, 40, 64}, ++{160, 41, 67}, ++{169, 43, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 40, 96}, ++{230, 37, 101}, ++{156, 40, 65}, ++{161, 41, 67}, ++{170, 43, 72}, ++{181, 44, 78}, ++{193, 43, 84}, ++{206, 42, 91}, ++{219, 40, 96}, ++{230, 37, 102}, ++{156, 41, 65}, ++{161, 42, 68}, ++{170, 43, 73}, ++{181, 44, 78}, ++{193, 43, 85}, ++{206, 42, 91}, ++{219, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{162, 43, 68}, ++{171, 44, 73}, ++{182, 45, 79}, ++{194, 44, 85}, ++{207, 42, 91}, ++{219, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{163, 44, 69}, ++{172, 45, 73}, ++{183, 45, 79}, ++{195, 45, 85}, ++{207, 43, 91}, ++{220, 41, 97}, ++{231, 38, 102}, ++{160, 44, 67}, ++{164, 45, 69}, ++{173, 46, 74}, ++{184, 46, 80}, ++{196, 45, 85}, ++{208, 44, 91}, ++{221, 41, 97}, ++{232, 39, 102}, ++{161, 46, 67}, ++{166, 46, 70}, ++{174, 47, 74}, ++{185, 47, 80}, ++{197, 46, 86}, ++{209, 44, 92}, ++{222, 42, 97}, ++{233, 39, 102}, ++{163, 47, 68}, ++{167, 48, 71}, ++{176, 48, 75}, ++{186, 48, 81}, ++{198, 47, 86}, ++{210, 45, 92}, ++{223, 42, 98}, ++{234, 40, 103}, ++{164, 49, 69}, ++{169, 49, 71}, ++{177, 50, 76}, ++{188, 49, 81}, ++{199, 48, 87}, ++{211, 46, 93}, ++{224, 43, 98}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 72}, ++{179, 51, 77}, ++{189, 50, 82}, ++{200, 49, 87}, ++{212, 47, 93}, ++{225, 44, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{172, 53, 73}, ++{181, 52, 77}, ++{191, 51, 82}, ++{202, 50, 88}, ++{214, 47, 93}, ++{226, 45, 99}, ++{237, 42, 104}, ++{170, 55, 72}, ++{174, 54, 74}, ++{182, 54, 78}, ++{192, 53, 83}, ++{203, 51, 88}, ++{215, 48, 94}, ++{227, 45, 99}, ++{238, 42, 104}, ++{172, 56, 73}, ++{177, 56, 75}, ++{184, 55, 79}, ++{194, 54, 84}, ++{205, 52, 89}, ++{217, 49, 94}, ++{229, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{179, 58, 76}, ++{186, 57, 80}, ++{196, 55, 85}, ++{207, 53, 90}, ++{218, 50, 95}, ++{230, 47, 100}, ++{241, 44, 105}, ++{177, 60, 75}, ++{181, 60, 77}, ++{189, 58, 81}, ++{198, 57, 85}, ++{209, 54, 90}, ++{220, 51, 96}, ++{232, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{183, 61, 78}, ++{191, 60, 82}, ++{200, 58, 86}, ++{211, 55, 91}, ++{222, 52, 96}, ++{233, 49, 101}, ++{244, 46, 106}, ++{182, 64, 77}, ++{186, 63, 79}, ++{193, 62, 83}, ++{202, 59, 87}, ++{213, 57, 92}, ++{224, 53, 97}, ++{235, 50, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{188, 65, 80}, ++{195, 63, 83}, ++{204, 61, 88}, ++{215, 58, 93}, ++{225, 55, 97}, ++{237, 51, 102}, ++{247, 47, 107}, ++{187, 67, 79}, ++{191, 66, 81}, ++{198, 65, 84}, ++{207, 62, 89}, ++{217, 59, 93}, ++{227, 56, 98}, ++{239, 52, 103}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{200, 66, 85}, ++{209, 63, 89}, ++{219, 60, 94}, ++{230, 57, 99}, ++{241, 53, 103}, ++{251, 49, 108}, ++{193, 71, 81}, ++{196, 70, 83}, ++{203, 68, 86}, ++{211, 65, 90}, ++{221, 62, 95}, ++{232, 58, 99}, ++{243, 54, 104}, ++{252, 50, 108}, ++{196, 72, 83}, ++{199, 71, 84}, ++{206, 69, 87}, ++{214, 66, 91}, ++{223, 63, 96}, ++{234, 59, 100}, ++{245, 55, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{202, 73, 85}, ++{208, 70, 88}, ++{216, 67, 92}, ++{226, 64, 96}, ++{236, 60, 101}, ++{247, 56, 105}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 86}, ++{211, 72, 89}, ++{219, 69, 93}, ++{228, 65, 97}, ++{238, 61, 101}, ++{249, 57, 106}, ++{255, 53, 110}, ++{204, 77, 86}, ++{208, 76, 87}, ++{214, 73, 90}, ++{222, 70, 94}, ++{231, 66, 98}, ++{241, 62, 102}, ++{251, 58, 106}, ++{255, 54, 110}, ++{207, 78, 87}, ++{211, 77, 89}, ++{217, 75, 91}, ++{224, 71, 95}, ++{233, 67, 99}, ++{243, 63, 103}, ++{253, 59, 107}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{219, 76, 92}, ++{227, 72, 96}, ++{236, 69, 100}, ++{245, 64, 104}, ++{255, 60, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{155, 39, 64}, ++{160, 41, 67}, ++{169, 42, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 39, 96}, ++{230, 37, 101}, ++{155, 40, 64}, ++{160, 41, 67}, ++{169, 43, 72}, ++{180, 43, 78}, ++{193, 43, 84}, ++{205, 42, 90}, ++{218, 40, 96}, ++{230, 37, 101}, ++{156, 40, 65}, ++{161, 41, 67}, ++{170, 43, 72}, ++{181, 44, 78}, ++{193, 43, 84}, ++{206, 42, 91}, ++{219, 40, 96}, ++{230, 37, 102}, ++{156, 41, 65}, ++{161, 42, 68}, ++{170, 43, 73}, ++{181, 44, 78}, ++{193, 43, 85}, ++{206, 42, 91}, ++{219, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{162, 43, 68}, ++{171, 44, 73}, ++{182, 45, 79}, ++{194, 44, 85}, ++{207, 42, 91}, ++{219, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{163, 44, 69}, ++{172, 45, 73}, ++{183, 45, 79}, ++{195, 45, 85}, ++{207, 43, 91}, ++{220, 41, 97}, ++{231, 38, 102}, ++{160, 44, 67}, ++{164, 45, 69}, ++{173, 46, 74}, ++{184, 46, 80}, ++{196, 45, 85}, ++{208, 44, 91}, ++{221, 41, 97}, ++{232, 39, 102}, ++{161, 46, 67}, ++{166, 46, 70}, ++{174, 47, 74}, ++{185, 47, 80}, ++{197, 46, 86}, ++{209, 44, 92}, ++{222, 42, 97}, ++{233, 39, 102}, ++{163, 47, 68}, ++{167, 48, 71}, ++{176, 48, 75}, ++{186, 48, 81}, ++{198, 47, 86}, ++{210, 45, 92}, ++{223, 42, 98}, ++{234, 40, 103}, ++{164, 49, 69}, ++{169, 49, 71}, ++{177, 50, 76}, ++{188, 49, 81}, ++{199, 48, 87}, ++{211, 46, 93}, ++{224, 43, 98}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 72}, ++{179, 51, 77}, ++{189, 50, 82}, ++{200, 49, 87}, ++{212, 47, 93}, ++{225, 44, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{172, 53, 73}, ++{181, 52, 77}, ++{191, 51, 82}, ++{202, 50, 88}, ++{214, 47, 93}, ++{226, 45, 99}, ++{237, 42, 104}, ++{170, 55, 72}, ++{174, 54, 74}, ++{182, 54, 78}, ++{192, 53, 83}, ++{203, 51, 88}, ++{215, 48, 94}, ++{227, 45, 99}, ++{238, 42, 104}, ++{172, 56, 73}, ++{177, 56, 75}, ++{184, 55, 79}, ++{194, 54, 84}, ++{205, 52, 89}, ++{217, 49, 94}, ++{229, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{179, 58, 76}, ++{186, 57, 80}, ++{196, 55, 85}, ++{207, 53, 90}, ++{218, 50, 95}, ++{230, 47, 100}, ++{241, 44, 105}, ++{177, 60, 75}, ++{181, 60, 77}, ++{189, 58, 81}, ++{198, 57, 85}, ++{209, 54, 90}, ++{220, 51, 96}, ++{232, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{183, 61, 78}, ++{191, 60, 82}, ++{200, 58, 86}, ++{211, 55, 91}, ++{222, 52, 96}, ++{233, 49, 101}, ++{244, 46, 106}, ++{182, 64, 77}, ++{186, 63, 79}, ++{193, 62, 83}, ++{202, 59, 87}, ++{213, 57, 92}, ++{224, 53, 97}, ++{235, 50, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{188, 65, 80}, ++{195, 63, 83}, ++{204, 61, 88}, ++{215, 58, 93}, ++{225, 55, 97}, ++{237, 51, 102}, ++{247, 47, 107}, ++{187, 67, 79}, ++{191, 66, 81}, ++{198, 65, 84}, ++{207, 62, 89}, ++{217, 59, 93}, ++{227, 56, 98}, ++{239, 52, 103}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{200, 66, 85}, ++{209, 63, 89}, ++{219, 60, 94}, ++{230, 57, 99}, ++{241, 53, 103}, ++{251, 49, 108}, ++{193, 71, 81}, ++{196, 70, 83}, ++{203, 68, 86}, ++{211, 65, 90}, ++{221, 62, 95}, ++{232, 58, 99}, ++{243, 54, 104}, ++{252, 50, 108}, ++{196, 72, 83}, ++{199, 71, 84}, ++{206, 69, 87}, ++{214, 66, 91}, ++{223, 63, 96}, ++{234, 59, 100}, ++{245, 55, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{202, 73, 85}, ++{208, 70, 88}, ++{216, 67, 92}, ++{226, 64, 96}, ++{236, 60, 101}, ++{247, 56, 105}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 86}, ++{211, 72, 89}, ++{219, 69, 93}, ++{228, 65, 97}, ++{238, 61, 101}, ++{249, 57, 106}, ++{255, 53, 110}, ++{204, 77, 86}, ++{208, 76, 87}, ++{214, 73, 90}, ++{222, 70, 94}, ++{231, 66, 98}, ++{241, 62, 102}, ++{251, 58, 106}, ++{255, 54, 110}, ++{207, 78, 87}, ++{211, 77, 89}, ++{217, 75, 91}, ++{224, 71, 95}, ++{233, 67, 99}, ++{243, 63, 103}, ++{253, 59, 107}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{219, 76, 92}, ++{227, 72, 96}, ++{236, 69, 100}, ++{245, 64, 104}, ++{255, 60, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{212, 80, 89}, ++{215, 79, 90}, ++{221, 76, 93}, ++{228, 73, 96}, ++{237, 69, 100}, ++{247, 65, 104}, ++{255, 61, 108}, ++{255, 57, 112}, ++{81, 104, 120}, ++{92, 100, 124}, ++{108, 93, 130}, ++{126, 87, 135}, ++{143, 80, 141}, ++{160, 73, 145}, ++{177, 67, 149}, ++{189, 62, 152}, ++{81, 104, 120}, ++{92, 100, 124}, ++{109, 93, 130}, ++{126, 87, 136}, ++{144, 80, 141}, ++{161, 73, 145}, ++{177, 67, 149}, ++{189, 62, 152}, ++{82, 105, 120}, ++{93, 100, 124}, ++{109, 94, 130}, ++{127, 87, 136}, ++{144, 80, 141}, ++{161, 73, 145}, ++{177, 67, 149}, ++{190, 63, 152}, ++{83, 105, 120}, ++{94, 101, 125}, ++{110, 94, 130}, ++{127, 87, 136}, ++{145, 80, 141}, ++{161, 74, 145}, ++{178, 67, 149}, ++{190, 63, 152}, ++{85, 106, 121}, ++{96, 101, 125}, ++{111, 95, 130}, ++{128, 88, 136}, ++{145, 81, 141}, ++{162, 74, 145}, ++{179, 68, 149}, ++{191, 63, 152}, ++{87, 107, 121}, ++{98, 102, 125}, ++{113, 95, 131}, ++{130, 88, 136}, ++{146, 81, 141}, ++{163, 74, 145}, ++{179, 68, 149}, ++{191, 63, 152}, ++{90, 108, 122}, ++{100, 103, 126}, ++{115, 96, 131}, ++{131, 89, 136}, ++{148, 82, 141}, ++{164, 75, 145}, ++{180, 68, 149}, ++{192, 64, 152}, ++{92, 109, 123}, ++{102, 104, 126}, ++{116, 97, 131}, ++{133, 89, 136}, ++{149, 82, 141}, ++{165, 75, 145}, ++{181, 69, 149}, ++{193, 64, 152}, ++{95, 110, 123}, ++{104, 105, 127}, ++{119, 98, 132}, ++{134, 90, 136}, ++{151, 83, 141}, ++{167, 76, 145}, ++{183, 69, 149}, ++{194, 65, 152}, ++{98, 111, 124}, ++{107, 106, 127}, ++{121, 98, 132}, ++{136, 91, 137}, ++{152, 84, 141}, ++{168, 77, 145}, ++{184, 70, 149}, ++{195, 65, 152}, ++{102, 112, 125}, ++{110, 107, 128}, ++{123, 99, 132}, ++{138, 92, 137}, ++{154, 84, 141}, ++{170, 77, 146}, ++{185, 71, 149}, ++{197, 66, 152}, ++{105, 113, 126}, ++{113, 108, 128}, ++{126, 100, 133}, ++{141, 93, 137}, ++{156, 85, 142}, ++{171, 78, 146}, ++{187, 71, 150}, ++{198, 66, 152}, ++{108, 113, 126}, ++{116, 108, 129}, ++{129, 101, 133}, ++{143, 93, 137}, ++{158, 86, 142}, ++{173, 79, 146}, ++{188, 72, 150}, ++{200, 67, 152}, ++{112, 114, 127}, ++{119, 109, 130}, ++{132, 102, 134}, ++{146, 94, 138}, ++{160, 87, 142}, ++{175, 80, 146}, ++{190, 73, 150}, ++{201, 68, 152}, ++{116, 115, 128}, ++{123, 110, 130}, ++{135, 103, 134}, ++{148, 95, 138}, ++{163, 88, 142}, ++{177, 80, 146}, ++{192, 73, 150}, ++{203, 68, 152}, ++{119, 116, 128}, ++{126, 111, 131}, ++{138, 104, 134}, ++{151, 96, 138}, ++{165, 88, 142}, ++{179, 81, 146}, ++{194, 74, 150}, ++{205, 69, 153}, ++{123, 116, 129}, ++{130, 112, 131}, ++{141, 105, 135}, ++{154, 97, 139}, ++{167, 89, 143}, ++{182, 82, 146}, ++{196, 75, 150}, ++{207, 70, 153}, ++{127, 117, 130}, ++{133, 112, 132}, ++{144, 105, 135}, ++{156, 98, 139}, ++{170, 90, 143}, ++{184, 83, 146}, ++{198, 76, 150}, ++{209, 71, 153}, ++{131, 118, 130}, ++{137, 113, 132}, ++{147, 106, 136}, ++{159, 99, 139}, ++{173, 91, 143}, ++{186, 84, 147}, ++{200, 77, 150}, ++{211, 71, 153}, ++{135, 118, 131}, ++{141, 114, 133}, ++{151, 107, 136}, ++{162, 99, 140}, ++{175, 92, 143}, ++{189, 84, 147}, ++{202, 77, 150}, ++{213, 72, 153}, ++{139, 119, 132}, ++{144, 114, 134}, ++{154, 108, 136}, ++{165, 100, 140}, ++{178, 93, 143}, ++{191, 85, 147}, ++{205, 78, 150}, ++{215, 73, 153}, ++{143, 119, 132}, ++{148, 115, 134}, ++{157, 108, 137}, ++{169, 101, 140}, ++{181, 94, 144}, ++{194, 86, 147}, ++{207, 79, 151}, ++{217, 74, 153}, ++{146, 120, 133}, ++{152, 116, 135}, ++{161, 109, 137}, ++{172, 102, 141}, ++{184, 94, 144}, ++{197, 87, 147}, ++{210, 80, 151}, ++{220, 75, 153}, ++{150, 120, 134}, ++{156, 116, 135}, ++{164, 110, 138}, ++{175, 103, 141}, ++{187, 95, 144}, ++{199, 88, 148}, ++{212, 81, 151}, ++{222, 75, 153}, ++{154, 120, 134}, ++{159, 117, 136}, ++{168, 110, 138}, ++{178, 103, 141}, ++{190, 96, 144}, ++{202, 89, 148}, ++{215, 81, 151}, ++{224, 76, 153}, ++{158, 121, 135}, ++{163, 117, 136}, ++{171, 111, 139}, ++{182, 104, 142}, ++{193, 97, 145}, ++{205, 89, 148}, ++{217, 82, 151}, ++{227, 77, 153}, ++{162, 121, 135}, ++{167, 118, 137}, ++{175, 112, 139}, ++{185, 105, 142}, ++{196, 97, 145}, ++{208, 90, 148}, ++{220, 83, 151}, ++{229, 78, 154}, ++{166, 122, 136}, ++{171, 118, 137}, ++{179, 112, 139}, ++{188, 105, 142}, ++{199, 98, 145}, ++{211, 91, 148}, ++{223, 84, 151}, ++{232, 79, 154}, ++{168, 122, 136}, ++{173, 118, 137}, ++{180, 112, 140}, ++{190, 106, 142}, ++{201, 99, 145}, ++{212, 91, 148}, ++{224, 84, 152}, ++{233, 79, 154}, ++{168, 122, 136}, ++{173, 118, 137}, ++{180, 112, 140}, ++{190, 106, 142}, ++{201, 99, 145}, ++{212, 91, 148}, ++{224, 84, 152}, ++{233, 79, 154}, ++{168, 122, 136}, ++{173, 118, 137}, ++{180, 112, 140}, ++{190, 106, 142}, ++{201, 99, 145}, ++{212, 91, 148}, ++{224, 84, 152}, ++{233, 79, 154}, ++{168, 122, 136}, ++{173, 118, 137}, ++{180, 112, 140}, ++{190, 106, 142}, ++{201, 99, 145}, ++{212, 91, 148}, ++{224, 84, 152}, ++{233, 79, 154}, ++{82, 103, 118}, ++{93, 99, 123}, ++{109, 93, 129}, ++{127, 86, 134}, ++{144, 79, 140}, ++{161, 73, 144}, ++{178, 67, 148}, ++{190, 62, 151}, ++{82, 103, 119}, ++{93, 99, 123}, ++{110, 93, 129}, ++{127, 86, 135}, ++{144, 80, 140}, ++{161, 73, 144}, ++{178, 67, 148}, ++{190, 62, 151}, ++{83, 104, 119}, ++{94, 100, 123}, ++{110, 93, 129}, ++{127, 86, 135}, ++{145, 80, 140}, ++{161, 73, 144}, ++{178, 67, 148}, ++{190, 62, 151}, ++{85, 104, 119}, ++{95, 100, 123}, ++{111, 94, 129}, ++{128, 87, 135}, ++{145, 80, 140}, ++{162, 73, 144}, ++{178, 67, 148}, ++{191, 63, 151}, ++{86, 105, 120}, ++{97, 101, 124}, ++{112, 94, 129}, ++{129, 87, 135}, ++{146, 80, 140}, ++{163, 74, 144}, ++{179, 67, 148}, ++{191, 63, 151}, ++{88, 106, 120}, ++{99, 101, 124}, ++{114, 95, 130}, ++{130, 88, 135}, ++{147, 81, 140}, ++{164, 74, 144}, ++{180, 68, 149}, ++{192, 63, 151}, ++{91, 107, 121}, ++{101, 102, 125}, ++{115, 96, 130}, ++{132, 88, 135}, ++{148, 81, 140}, ++{165, 75, 144}, ++{181, 68, 149}, ++{193, 64, 151}, ++{93, 108, 122}, ++{103, 103, 125}, ++{117, 96, 130}, ++{133, 89, 135}, ++{150, 82, 140}, ++{166, 75, 145}, ++{182, 69, 149}, ++{194, 64, 151}, ++{96, 109, 122}, ++{105, 104, 126}, ++{119, 97, 131}, ++{135, 90, 136}, ++{151, 83, 140}, ++{167, 76, 145}, ++{183, 69, 149}, ++{195, 64, 152}, ++{99, 110, 123}, ++{108, 105, 126}, ++{122, 98, 131}, ++{137, 91, 136}, ++{153, 83, 140}, ++{169, 76, 145}, ++{184, 70, 149}, ++{196, 65, 152}, ++{102, 111, 124}, ++{111, 106, 127}, ++{124, 99, 131}, ++{139, 91, 136}, ++{155, 84, 141}, ++{170, 77, 145}, ++{186, 70, 149}, ++{197, 66, 152}, ++{106, 112, 125}, ++{114, 107, 127}, ++{127, 100, 132}, ++{141, 92, 136}, ++{157, 85, 141}, ++{172, 78, 145}, ++{187, 71, 149}, ++{199, 66, 152}, ++{109, 113, 125}, ++{117, 108, 128}, ++{129, 101, 132}, ++{144, 93, 137}, ++{159, 86, 141}, ++{174, 79, 145}, ++{189, 72, 149}, ++{200, 67, 152}, ++{113, 114, 126}, ++{120, 109, 129}, ++{132, 102, 133}, ++{146, 94, 137}, ++{161, 87, 141}, ++{176, 79, 145}, ++{191, 72, 149}, ++{202, 68, 152}, ++{116, 114, 127}, ++{124, 110, 129}, ++{135, 102, 133}, ++{149, 95, 137}, ++{163, 87, 141}, ++{178, 80, 145}, ++{192, 73, 149}, ++{203, 68, 152}, ++{120, 115, 128}, ++{127, 110, 130}, ++{138, 103, 134}, ++{151, 96, 138}, ++{165, 88, 142}, ++{180, 81, 145}, ++{194, 74, 149}, ++{205, 69, 152}, ++{124, 116, 128}, ++{130, 111, 130}, ++{141, 104, 134}, ++{154, 97, 138}, ++{168, 89, 142}, ++{182, 82, 146}, ++{196, 75, 149}, ++{207, 70, 152}, ++{128, 116, 129}, ++{134, 112, 131}, ++{145, 105, 134}, ++{157, 97, 138}, ++{170, 90, 142}, ++{184, 83, 146}, ++{199, 76, 149}, ++{209, 70, 152}, ++{131, 117, 130}, ++{138, 113, 132}, ++{148, 106, 135}, ++{160, 98, 139}, ++{173, 91, 142}, ++{187, 83, 146}, ++{201, 76, 150}, ++{211, 71, 152}, ++{135, 118, 130}, ++{141, 113, 132}, ++{151, 107, 135}, ++{163, 99, 139}, ++{176, 92, 143}, ++{189, 84, 146}, ++{203, 77, 150}, ++{213, 72, 152}, ++{139, 118, 131}, ++{145, 114, 133}, ++{154, 107, 136}, ++{166, 100, 139}, ++{179, 92, 143}, ++{192, 85, 146}, ++{205, 78, 150}, ++{215, 73, 152}, ++{143, 119, 132}, ++{149, 115, 133}, ++{158, 108, 136}, ++{169, 101, 140}, ++{181, 93, 143}, ++{194, 86, 147}, ++{208, 79, 150}, ++{218, 74, 152}, ++{147, 119, 132}, ++{152, 115, 134}, ++{161, 109, 137}, ++{172, 101, 140}, ++{184, 94, 143}, ++{197, 87, 147}, ++{210, 80, 150}, ++{220, 74, 153}, ++{151, 120, 133}, ++{156, 116, 134}, ++{165, 109, 137}, ++{175, 102, 140}, ++{187, 95, 144}, ++{200, 88, 147}, ++{212, 80, 150}, ++{222, 75, 153}, ++{155, 120, 133}, ++{160, 116, 135}, ++{168, 110, 138}, ++{179, 103, 141}, ++{190, 96, 144}, ++{202, 88, 147}, ++{215, 81, 150}, ++{225, 76, 153}, ++{159, 120, 134}, ++{164, 117, 135}, ++{172, 111, 138}, ++{182, 104, 141}, ++{193, 96, 144}, ++{205, 89, 147}, ++{218, 82, 151}, ++{227, 77, 153}, ++{163, 121, 135}, ++{168, 117, 136}, ++{176, 111, 138}, ++{185, 104, 141}, ++{196, 97, 144}, ++{208, 90, 148}, ++{220, 83, 151}, ++{230, 78, 153}, ++{167, 121, 135}, ++{171, 118, 136}, ++{179, 112, 139}, ++{189, 105, 142}, ++{199, 98, 145}, ++{211, 91, 148}, ++{223, 84, 151}, ++{232, 78, 153}, ++{169, 121, 135}, ++{173, 118, 137}, ++{181, 112, 139}, ++{190, 105, 142}, ++{201, 98, 145}, ++{212, 91, 148}, ++{224, 84, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{173, 118, 137}, ++{181, 112, 139}, ++{190, 105, 142}, ++{201, 98, 145}, ++{212, 91, 148}, ++{224, 84, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{173, 118, 137}, ++{181, 112, 139}, ++{190, 105, 142}, ++{201, 98, 145}, ++{212, 91, 148}, ++{224, 84, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{173, 118, 137}, ++{181, 112, 139}, ++{190, 105, 142}, ++{201, 98, 145}, ++{212, 91, 148}, ++{224, 84, 151}, ++{233, 79, 153}, ++{84, 102, 116}, ++{95, 98, 121}, ++{111, 92, 127}, ++{128, 85, 133}, ++{145, 79, 138}, ++{162, 73, 143}, ++{178, 66, 147}, ++{190, 62, 150}, ++{84, 102, 117}, ++{95, 98, 121}, ++{111, 92, 127}, ++{128, 86, 133}, ++{145, 79, 138}, ++{162, 73, 143}, ++{178, 66, 147}, ++{191, 62, 150}, ++{85, 102, 117}, ++{96, 98, 121}, ++{112, 92, 127}, ++{129, 86, 133}, ++{146, 79, 138}, ++{162, 73, 143}, ++{179, 67, 147}, ++{191, 62, 150}, ++{86, 103, 117}, ++{97, 99, 122}, ++{112, 93, 127}, ++{129, 86, 133}, ++{146, 79, 138}, ++{163, 73, 143}, ++{179, 67, 147}, ++{191, 62, 150}, ++{88, 104, 118}, ++{98, 99, 122}, ++{114, 93, 128}, ++{130, 87, 133}, ++{147, 80, 138}, ++{164, 73, 143}, ++{180, 67, 147}, ++{192, 63, 150}, ++{90, 105, 118}, ++{100, 100, 122}, ++{115, 94, 128}, ++{131, 87, 133}, ++{148, 80, 138}, ++{165, 74, 143}, ++{181, 67, 147}, ++{193, 63, 150}, ++{92, 106, 119}, ++{102, 101, 123}, ++{117, 95, 128}, ++{133, 88, 134}, ++{149, 81, 139}, ++{166, 74, 143}, ++{182, 68, 147}, ++{193, 63, 150}, ++{95, 107, 120}, ++{104, 102, 123}, ++{119, 95, 129}, ++{134, 88, 134}, ++{151, 81, 139}, ++{167, 75, 143}, ++{183, 68, 147}, ++{194, 64, 150}, ++{98, 108, 121}, ++{107, 103, 124}, ++{121, 96, 129}, ++{136, 89, 134}, ++{152, 82, 139}, ++{168, 75, 143}, ++{184, 69, 147}, ++{195, 64, 150}, ++{101, 109, 121}, ++{109, 104, 125}, ++{123, 97, 129}, ++{138, 90, 134}, ++{154, 83, 139}, ++{170, 76, 143}, ++{185, 69, 148}, ++{197, 65, 150}, ++{104, 110, 122}, ++{112, 105, 125}, ++{125, 98, 130}, ++{140, 91, 135}, ++{156, 84, 139}, ++{171, 77, 144}, ++{187, 70, 148}, ++{198, 65, 151}, ++{107, 111, 123}, ++{115, 106, 126}, ++{128, 99, 130}, ++{142, 92, 135}, ++{157, 84, 139}, ++{173, 77, 144}, ++{188, 71, 148}, ++{199, 66, 151}, ++{111, 112, 124}, ++{118, 107, 127}, ++{131, 100, 131}, ++{145, 92, 135}, ++{160, 85, 140}, ++{175, 78, 144}, ++{190, 71, 148}, ++{201, 67, 151}, ++{114, 112, 124}, ++{121, 108, 127}, ++{133, 101, 131}, ++{147, 93, 136}, ++{162, 86, 140}, ++{177, 79, 144}, ++{191, 72, 148}, ++{202, 67, 151}, ++{118, 113, 125}, ++{125, 109, 128}, ++{136, 102, 132}, ++{150, 94, 136}, ++{164, 87, 140}, ++{179, 80, 144}, ++{193, 73, 148}, ++{204, 68, 151}, ++{121, 114, 126}, ++{128, 109, 128}, ++{139, 103, 132}, ++{152, 95, 136}, ++{166, 88, 140}, ++{181, 81, 144}, ++{195, 74, 148}, ++{206, 69, 151}, ++{125, 115, 127}, ++{132, 110, 129}, ++{142, 103, 133}, ++{155, 96, 137}, ++{169, 89, 141}, ++{183, 81, 145}, ++{197, 74, 148}, ++{208, 69, 151}, ++{129, 115, 128}, ++{135, 111, 130}, ++{146, 104, 133}, ++{158, 97, 137}, ++{171, 89, 141}, ++{185, 82, 145}, ++{199, 75, 148}, ++{210, 70, 151}, ++{133, 116, 128}, ++{139, 112, 130}, ++{149, 105, 134}, ++{161, 98, 137}, ++{174, 90, 141}, ++{188, 83, 145}, ++{201, 76, 149}, ++{212, 71, 151}, ++{136, 117, 129}, ++{142, 112, 131}, ++{152, 106, 134}, ++{164, 99, 138}, ++{177, 91, 141}, ++{190, 84, 145}, ++{204, 77, 149}, ++{214, 72, 151}, ++{140, 117, 130}, ++{146, 113, 131}, ++{155, 107, 135}, ++{167, 99, 138}, ++{179, 92, 142}, ++{193, 85, 145}, ++{206, 78, 149}, ++{216, 73, 151}, ++{144, 118, 130}, ++{150, 114, 132}, ++{159, 107, 135}, ++{170, 100, 138}, ++{182, 93, 142}, ++{195, 85, 145}, ++{208, 78, 149}, ++{218, 73, 152}, ++{148, 118, 131}, ++{153, 114, 133}, ++{162, 108, 135}, ++{173, 101, 139}, ++{185, 94, 142}, ++{198, 86, 146}, ++{211, 79, 149}, ++{220, 74, 152}, ++{152, 119, 132}, ++{157, 115, 133}, ++{166, 109, 136}, ++{176, 102, 139}, ++{188, 94, 142}, ++{200, 87, 146}, ++{213, 80, 149}, ++{223, 75, 152}, ++{156, 119, 132}, ++{161, 115, 134}, ++{169, 109, 136}, ++{180, 102, 139}, ++{191, 95, 143}, ++{203, 88, 146}, ++{216, 81, 149}, ++{225, 76, 152}, ++{160, 120, 133}, ++{165, 116, 134}, ++{173, 110, 137}, ++{183, 103, 140}, ++{194, 96, 143}, ++{206, 89, 146}, ++{218, 82, 150}, ++{228, 77, 152}, ++{164, 120, 133}, ++{168, 117, 135}, ++{176, 111, 137}, ++{186, 104, 140}, ++{197, 97, 143}, ++{209, 90, 147}, ++{221, 83, 150}, ++{230, 77, 152}, ++{168, 120, 134}, ++{172, 117, 135}, ++{180, 111, 138}, ++{189, 105, 141}, ++{200, 97, 144}, ++{212, 90, 147}, ++{224, 83, 150}, ++{233, 78, 152}, ++{170, 121, 134}, ++{174, 117, 136}, ++{182, 112, 138}, ++{191, 105, 141}, ++{202, 98, 144}, ++{213, 91, 147}, ++{225, 84, 150}, ++{234, 79, 152}, ++{170, 121, 134}, ++{174, 117, 136}, ++{182, 112, 138}, ++{191, 105, 141}, ++{202, 98, 144}, ++{213, 91, 147}, ++{225, 84, 150}, ++{234, 79, 152}, ++{170, 121, 134}, ++{174, 117, 136}, ++{182, 112, 138}, ++{191, 105, 141}, ++{202, 98, 144}, ++{213, 91, 147}, ++{225, 84, 150}, ++{234, 79, 152}, ++{170, 121, 134}, ++{174, 117, 136}, ++{182, 112, 138}, ++{191, 105, 141}, ++{202, 98, 144}, ++{213, 91, 147}, ++{225, 84, 150}, ++{234, 79, 152}, ++{86, 100, 114}, ++{97, 96, 119}, ++{112, 91, 125}, ++{129, 85, 131}, ++{146, 78, 136}, ++{163, 72, 141}, ++{179, 66, 146}, ++{191, 61, 149}, ++{87, 100, 114}, ++{97, 96, 119}, ++{113, 91, 125}, ++{130, 85, 131}, ++{146, 78, 136}, ++{163, 72, 141}, ++{180, 66, 146}, ++{191, 61, 149}, ++{87, 100, 115}, ++{98, 97, 119}, ++{113, 91, 125}, ++{130, 85, 131}, ++{147, 79, 136}, ++{164, 72, 141}, ++{180, 66, 146}, ++{192, 62, 149}, ++{89, 101, 115}, ++{99, 97, 119}, ++{114, 92, 125}, ++{131, 85, 131}, ++{147, 79, 136}, ++{164, 72, 141}, ++{180, 66, 146}, ++{192, 62, 149}, ++{90, 102, 116}, ++{100, 98, 120}, ++{115, 92, 126}, ++{132, 86, 131}, ++{148, 79, 137}, ++{165, 73, 141}, ++{181, 67, 146}, ++{193, 62, 149}, ++{92, 103, 116}, ++{102, 99, 120}, ++{117, 93, 126}, ++{133, 86, 131}, ++{149, 80, 137}, ++{166, 73, 141}, ++{182, 67, 146}, ++{193, 62, 149}, ++{94, 104, 117}, ++{104, 100, 121}, ++{118, 94, 126}, ++{134, 87, 132}, ++{150, 80, 137}, ++{167, 74, 142}, ++{183, 67, 146}, ++{194, 63, 149}, ++{97, 105, 118}, ++{106, 101, 121}, ++{120, 94, 127}, ++{136, 88, 132}, ++{152, 81, 137}, ++{168, 74, 142}, ++{184, 68, 146}, ++{195, 63, 149}, ++{100, 106, 118}, ++{109, 102, 122}, ++{122, 95, 127}, ++{137, 88, 132}, ++{153, 81, 137}, ++{169, 75, 142}, ++{185, 68, 146}, ++{196, 64, 149}, ++{103, 107, 119}, ++{111, 103, 123}, ++{124, 96, 127}, ++{139, 89, 133}, ++{155, 82, 137}, ++{171, 75, 142}, ++{186, 69, 146}, ++{198, 64, 149}, ++{106, 108, 120}, ++{114, 104, 123}, ++{127, 97, 128}, ++{141, 90, 133}, ++{157, 83, 138}, ++{172, 76, 142}, ++{187, 70, 146}, ++{199, 65, 149}, ++{109, 109, 121}, ++{117, 105, 124}, ++{129, 98, 128}, ++{144, 91, 133}, ++{159, 84, 138}, ++{174, 77, 142}, ++{189, 70, 146}, ++{200, 65, 149}, ++{112, 110, 122}, ++{120, 106, 125}, ++{132, 99, 129}, ++{146, 92, 134}, ++{161, 85, 138}, ++{176, 78, 142}, ++{191, 71, 146}, ++{202, 66, 149}, ++{116, 111, 123}, ++{123, 107, 125}, ++{135, 100, 129}, ++{148, 93, 134}, ++{163, 85, 138}, ++{178, 78, 143}, ++{192, 72, 147}, ++{203, 67, 149}, ++{119, 112, 123}, ++{126, 107, 126}, ++{138, 101, 130}, ++{151, 93, 134}, ++{165, 86, 139}, ++{180, 79, 143}, ++{194, 72, 147}, ++{205, 68, 150}, ++{123, 113, 124}, ++{130, 108, 127}, ++{141, 102, 130}, ++{154, 94, 135}, ++{167, 87, 139}, ++{182, 80, 143}, ++{196, 73, 147}, ++{207, 68, 150}, ++{126, 113, 125}, ++{133, 109, 127}, ++{144, 103, 131}, ++{156, 95, 135}, ++{170, 88, 139}, ++{184, 81, 143}, ++{198, 74, 147}, ++{209, 69, 150}, ++{130, 114, 126}, ++{136, 110, 128}, ++{147, 103, 131}, ++{159, 96, 135}, ++{172, 89, 139}, ++{186, 82, 143}, ++{200, 75, 147}, ++{211, 70, 150}, ++{134, 115, 127}, ++{140, 111, 129}, ++{150, 104, 132}, ++{162, 97, 136}, ++{175, 90, 140}, ++{188, 82, 144}, ++{202, 76, 147}, ++{213, 71, 150}, ++{138, 116, 127}, ++{144, 111, 129}, ++{153, 105, 133}, ++{165, 98, 136}, ++{178, 90, 140}, ++{191, 83, 144}, ++{204, 76, 147}, ++{215, 71, 150}, ++{142, 116, 128}, ++{147, 112, 130}, ++{157, 106, 133}, ++{168, 99, 137}, ++{180, 91, 140}, ++{193, 84, 144}, ++{207, 77, 148}, ++{217, 72, 150}, ++{145, 117, 129}, ++{151, 113, 131}, ++{160, 107, 134}, ++{171, 99, 137}, ++{183, 92, 141}, ++{196, 85, 144}, ++{209, 78, 148}, ++{219, 73, 150}, ++{149, 117, 129}, ++{154, 113, 131}, ++{163, 107, 134}, ++{174, 100, 137}, ++{186, 93, 141}, ++{199, 86, 144}, ++{211, 79, 148}, ++{221, 74, 151}, ++{153, 118, 130}, ++{158, 114, 132}, ++{167, 108, 135}, ++{177, 101, 138}, ++{189, 94, 141}, ++{201, 87, 145}, ++{214, 80, 148}, ++{224, 75, 151}, ++{157, 118, 131}, ++{162, 115, 132}, ++{170, 109, 135}, ++{180, 102, 138}, ++{192, 95, 142}, ++{204, 87, 145}, ++{216, 80, 148}, ++{226, 75, 151}, ++{161, 119, 131}, ++{166, 115, 133}, ++{174, 109, 136}, ++{184, 103, 139}, ++{195, 95, 142}, ++{207, 88, 145}, ++{219, 81, 149}, ++{228, 76, 151}, ++{165, 119, 132}, ++{169, 116, 134}, ++{177, 110, 136}, ++{187, 103, 139}, ++{198, 96, 142}, ++{210, 89, 145}, ++{222, 82, 149}, ++{231, 77, 151}, ++{169, 120, 133}, ++{173, 116, 134}, ++{181, 111, 136}, ++{190, 104, 139}, ++{201, 97, 142}, ++{212, 90, 146}, ++{224, 83, 149}, ++{233, 78, 151}, ++{171, 120, 133}, ++{175, 116, 134}, ++{183, 111, 137}, ++{192, 104, 140}, ++{203, 97, 143}, ++{214, 90, 146}, ++{226, 83, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{175, 116, 134}, ++{183, 111, 137}, ++{192, 104, 140}, ++{203, 97, 143}, ++{214, 90, 146}, ++{226, 83, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{175, 116, 134}, ++{183, 111, 137}, ++{192, 104, 140}, ++{203, 97, 143}, ++{214, 90, 146}, ++{226, 83, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{175, 116, 134}, ++{183, 111, 137}, ++{192, 104, 140}, ++{203, 97, 143}, ++{214, 90, 146}, ++{226, 83, 149}, ++{235, 78, 151}, ++{89, 97, 112}, ++{99, 94, 116}, ++{114, 89, 123}, ++{131, 84, 129}, ++{148, 77, 134}, ++{164, 71, 139}, ++{181, 65, 144}, ++{192, 61, 147}, ++{89, 98, 112}, ++{99, 95, 117}, ++{115, 90, 123}, ++{131, 84, 129}, ++{148, 78, 134}, ++{164, 71, 139}, ++{181, 65, 144}, ++{193, 61, 147}, ++{90, 98, 112}, ++{100, 95, 117}, ++{115, 90, 123}, ++{132, 84, 129}, ++{148, 78, 134}, ++{165, 72, 139}, ++{181, 66, 144}, ++{193, 61, 147}, ++{91, 99, 113}, ++{101, 96, 117}, ++{116, 90, 123}, ++{132, 84, 129}, ++{149, 78, 134}, ++{165, 72, 139}, ++{181, 66, 144}, ++{193, 61, 147}, ++{93, 100, 113}, ++{102, 96, 117}, ++{117, 91, 123}, ++{133, 85, 129}, ++{150, 78, 135}, ++{166, 72, 140}, ++{182, 66, 144}, ++{194, 62, 147}, ++{95, 101, 114}, ++{104, 97, 118}, ++{118, 91, 124}, ++{134, 85, 129}, ++{151, 79, 135}, ++{167, 73, 140}, ++{183, 66, 144}, ++{195, 62, 147}, ++{97, 102, 115}, ++{106, 98, 119}, ++{120, 92, 124}, ++{136, 86, 130}, ++{152, 79, 135}, ++{168, 73, 140}, ++{184, 67, 144}, ++{195, 62, 147}, ++{99, 103, 115}, ++{108, 99, 119}, ++{122, 93, 124}, ++{137, 87, 130}, ++{153, 80, 135}, ++{169, 74, 140}, ++{185, 67, 144}, ++{196, 63, 147}, ++{102, 104, 116}, ++{111, 100, 120}, ++{124, 94, 125}, ++{139, 87, 130}, ++{155, 81, 135}, ++{170, 74, 140}, ++{186, 68, 144}, ++{197, 63, 148}, ++{105, 105, 117}, ++{113, 101, 120}, ++{126, 95, 125}, ++{141, 88, 131}, ++{156, 81, 136}, ++{172, 75, 140}, ++{187, 68, 145}, ++{199, 64, 148}, ++{108, 106, 118}, ++{116, 102, 121}, ++{128, 96, 126}, ++{143, 89, 131}, ++{158, 82, 136}, ++{173, 76, 140}, ++{189, 69, 145}, ++{200, 64, 148}, ++{111, 107, 119}, ++{119, 103, 122}, ++{131, 97, 126}, ++{145, 90, 131}, ++{160, 83, 136}, ++{175, 76, 141}, ++{190, 70, 145}, ++{201, 65, 148}, ++{114, 108, 120}, ++{122, 104, 123}, ++{134, 98, 127}, ++{147, 91, 132}, ++{162, 84, 136}, ++{177, 77, 141}, ++{192, 70, 145}, ++{203, 66, 148}, ++{118, 109, 121}, ++{125, 105, 123}, ++{136, 99, 127}, ++{150, 92, 132}, ++{164, 85, 137}, ++{179, 78, 141}, ++{193, 71, 145}, ++{204, 66, 148}, ++{121, 110, 121}, ++{128, 106, 124}, ++{139, 100, 128}, ++{152, 93, 132}, ++{166, 85, 137}, ++{181, 79, 141}, ++{195, 72, 145}, ++{206, 67, 148}, ++{125, 111, 122}, ++{131, 107, 125}, ++{142, 101, 129}, ++{155, 93, 133}, ++{169, 86, 137}, ++{183, 79, 141}, ++{197, 73, 145}, ++{208, 68, 148}, ++{128, 112, 123}, ++{135, 108, 125}, ++{145, 101, 129}, ++{158, 94, 133}, ++{171, 87, 137}, ++{185, 80, 142}, ++{199, 73, 146}, ++{210, 69, 148}, ++{132, 113, 124}, ++{138, 109, 126}, ++{148, 102, 130}, ++{160, 95, 134}, ++{174, 88, 138}, ++{187, 81, 142}, ++{201, 74, 146}, ++{212, 69, 148}, ++{135, 114, 125}, ++{141, 110, 127}, ++{151, 103, 130}, ++{163, 96, 134}, ++{176, 89, 138}, ++{190, 82, 142}, ++{203, 75, 146}, ++{214, 70, 149}, ++{139, 114, 125}, ++{145, 110, 128}, ++{155, 104, 131}, ++{166, 97, 135}, ++{179, 90, 138}, ++{192, 83, 142}, ++{205, 76, 146}, ++{216, 71, 149}, ++{143, 115, 126}, ++{149, 111, 128}, ++{158, 105, 131}, ++{169, 98, 135}, ++{181, 91, 139}, ++{194, 84, 143}, ++{208, 77, 146}, ++{218, 72, 149}, ++{147, 116, 127}, ++{152, 112, 129}, ++{161, 106, 132}, ++{172, 99, 135}, ++{184, 91, 139}, ++{197, 84, 143}, ++{210, 77, 146}, ++{220, 72, 149}, ++{151, 116, 128}, ++{156, 112, 130}, ++{165, 106, 132}, ++{175, 99, 136}, ++{187, 92, 139}, ++{200, 85, 143}, ++{212, 78, 147}, ++{222, 73, 149}, ++{154, 117, 128}, ++{159, 113, 130}, ++{168, 107, 133}, ++{178, 100, 136}, ++{190, 93, 140}, ++{202, 86, 143}, ++{215, 79, 147}, ++{224, 74, 149}, ++{158, 117, 129}, ++{163, 114, 131}, ++{171, 108, 133}, ++{182, 101, 137}, ++{193, 94, 140}, ++{205, 87, 144}, ++{217, 80, 147}, ++{227, 75, 150}, ++{162, 118, 130}, ++{167, 114, 131}, ++{175, 108, 134}, ++{185, 102, 137}, ++{196, 95, 140}, ++{208, 88, 144}, ++{220, 81, 147}, ++{229, 76, 150}, ++{166, 118, 131}, ++{171, 115, 132}, ++{178, 109, 135}, ++{188, 102, 138}, ++{199, 96, 141}, ++{210, 88, 144}, ++{223, 82, 147}, ++{232, 77, 150}, ++{170, 119, 131}, ++{174, 115, 133}, ++{182, 110, 135}, ++{191, 103, 138}, ++{202, 96, 141}, ++{213, 89, 144}, ++{225, 82, 148}, ++{234, 77, 150}, ++{172, 119, 131}, ++{176, 116, 133}, ++{184, 110, 135}, ++{193, 104, 138}, ++{204, 97, 141}, ++{215, 90, 145}, ++{226, 83, 148}, ++{235, 78, 150}, ++{172, 119, 131}, ++{176, 116, 133}, ++{184, 110, 135}, ++{193, 104, 138}, ++{204, 97, 141}, ++{215, 90, 145}, ++{226, 83, 148}, ++{235, 78, 150}, ++{172, 119, 131}, ++{176, 116, 133}, ++{184, 110, 135}, ++{193, 104, 138}, ++{204, 97, 141}, ++{215, 90, 145}, ++{226, 83, 148}, ++{235, 78, 150}, ++{172, 119, 131}, ++{176, 116, 133}, ++{184, 110, 135}, ++{193, 104, 138}, ++{204, 97, 141}, ++{215, 90, 145}, ++{226, 83, 148}, ++{235, 78, 150}, ++{91, 95, 109}, ++{101, 92, 114}, ++{116, 88, 120}, ++{133, 82, 126}, ++{149, 77, 132}, ++{166, 71, 137}, ++{182, 65, 142}, ++{194, 60, 145}, ++{92, 95, 110}, ++{102, 93, 114}, ++{117, 88, 120}, ++{133, 82, 127}, ++{149, 77, 132}, ++{166, 71, 137}, ++{182, 65, 142}, ++{194, 60, 145}, ++{92, 96, 110}, ++{102, 93, 114}, ++{117, 88, 120}, ++{133, 83, 127}, ++{150, 77, 132}, ++{166, 71, 137}, ++{182, 65, 142}, ++{194, 61, 145}, ++{94, 96, 110}, ++{103, 94, 115}, ++{118, 89, 121}, ++{134, 83, 127}, ++{150, 77, 132}, ++{167, 71, 138}, ++{183, 65, 142}, ++{194, 61, 146}, ++{95, 97, 111}, ++{105, 94, 115}, ++{119, 89, 121}, ++{135, 84, 127}, ++{151, 77, 133}, ++{167, 71, 138}, ++{183, 65, 142}, ++{195, 61, 146}, ++{97, 98, 111}, ++{106, 95, 116}, ++{120, 90, 121}, ++{136, 84, 127}, ++{152, 78, 133}, ++{168, 72, 138}, ++{184, 66, 142}, ++{196, 61, 146}, ++{99, 100, 112}, ++{108, 96, 116}, ++{122, 91, 122}, ++{138, 85, 127}, ++{153, 79, 133}, ++{169, 72, 138}, ++{185, 66, 142}, ++{197, 62, 146}, ++{102, 101, 113}, ++{110, 97, 117}, ++{124, 92, 122}, ++{139, 85, 128}, ++{155, 79, 133}, ++{170, 73, 138}, ++{186, 67, 143}, ++{197, 62, 146}, ++{104, 102, 114}, ++{113, 98, 117}, ++{126, 93, 123}, ++{141, 86, 128}, ++{156, 80, 133}, ++{172, 73, 138}, ++{187, 67, 143}, ++{199, 63, 146}, ++{107, 103, 115}, ++{115, 99, 118}, ++{128, 93, 123}, ++{143, 87, 128}, ++{158, 81, 134}, ++{173, 74, 138}, ++{188, 68, 143}, ++{200, 63, 146}, ++{110, 104, 116}, ++{118, 100, 119}, ++{130, 94, 124}, ++{145, 88, 129}, ++{160, 81, 134}, ++{175, 75, 139}, ++{190, 68, 143}, ++{201, 64, 146}, ++{113, 105, 117}, ++{121, 101, 120}, ++{133, 95, 124}, ++{147, 89, 129}, ++{161, 82, 134}, ++{176, 76, 139}, ++{191, 69, 143}, ++{202, 64, 146}, ++{116, 107, 117}, ++{124, 103, 120}, ++{135, 96, 125}, ++{149, 90, 130}, ++{163, 83, 134}, ++{178, 76, 139}, ++{193, 70, 143}, ++{204, 65, 146}, ++{120, 108, 118}, ++{127, 104, 121}, ++{138, 97, 125}, ++{151, 91, 130}, ++{165, 84, 135}, ++{180, 77, 139}, ++{195, 71, 143}, ++{205, 66, 146}, ++{123, 109, 119}, ++{130, 105, 122}, ++{141, 98, 126}, ++{154, 92, 130}, ++{168, 85, 135}, ++{182, 78, 139}, ++{196, 71, 144}, ++{207, 67, 147}, ++{126, 110, 120}, ++{133, 106, 123}, ++{144, 99, 127}, ++{156, 92, 131}, ++{170, 85, 135}, ++{184, 79, 140}, ++{198, 72, 144}, ++{209, 67, 147}, ++{130, 110, 121}, ++{136, 106, 123}, ++{147, 100, 127}, ++{159, 93, 131}, ++{172, 86, 136}, ++{186, 79, 140}, ++{200, 73, 144}, ++{211, 68, 147}, ++{134, 111, 122}, ++{140, 107, 124}, ++{150, 101, 128}, ++{162, 94, 132}, ++{175, 87, 136}, ++{188, 80, 140}, ++{202, 74, 144}, ++{213, 69, 147}, ++{137, 112, 123}, ++{143, 108, 125}, ++{153, 102, 128}, ++{165, 95, 132}, ++{177, 88, 136}, ++{191, 81, 140}, ++{204, 74, 144}, ++{215, 70, 147}, ++{141, 113, 124}, ++{147, 109, 126}, ++{156, 103, 129}, ++{168, 96, 133}, ++{180, 89, 137}, ++{193, 82, 141}, ++{206, 75, 145}, ++{217, 70, 147}, ++{145, 114, 124}, ++{150, 110, 126}, ++{159, 104, 130}, ++{170, 97, 133}, ++{183, 90, 137}, ++{196, 83, 141}, ++{209, 76, 145}, ++{219, 71, 148}, ++{148, 114, 125}, ++{154, 110, 127}, ++{163, 105, 130}, ++{173, 98, 134}, ++{185, 91, 137}, ++{198, 84, 141}, ++{211, 77, 145}, ++{221, 72, 148}, ++{152, 115, 126}, ++{157, 111, 128}, ++{166, 105, 131}, ++{177, 99, 134}, ++{188, 92, 138}, ++{201, 85, 142}, ++{213, 78, 145}, ++{223, 73, 148}, ++{156, 115, 127}, ++{161, 112, 128}, ++{169, 106, 131}, ++{180, 99, 135}, ++{191, 92, 138}, ++{203, 85, 142}, ++{216, 79, 145}, ++{225, 74, 148}, ++{160, 116, 127}, ++{165, 112, 129}, ++{173, 107, 132}, ++{183, 100, 135}, ++{194, 93, 139}, ++{206, 86, 142}, ++{218, 79, 146}, ++{228, 74, 148}, ++{163, 117, 128}, ++{168, 113, 130}, ++{176, 107, 132}, ++{186, 101, 136}, ++{197, 94, 139}, ++{209, 87, 142}, ++{221, 80, 146}, ++{230, 75, 148}, ++{167, 117, 129}, ++{172, 114, 130}, ++{180, 108, 133}, ++{189, 102, 136}, ++{200, 95, 139}, ++{212, 88, 143}, ++{223, 81, 146}, ++{233, 76, 149}, ++{171, 118, 130}, ++{176, 114, 131}, ++{183, 109, 134}, ++{193, 102, 136}, ++{203, 96, 140}, ++{214, 89, 143}, ++{226, 82, 146}, ++{235, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{185, 109, 134}, ++{194, 103, 137}, ++{205, 96, 140}, ++{216, 89, 143}, ++{227, 82, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{185, 109, 134}, ++{194, 103, 137}, ++{205, 96, 140}, ++{216, 89, 143}, ++{227, 82, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{185, 109, 134}, ++{194, 103, 137}, ++{205, 96, 140}, ++{216, 89, 143}, ++{227, 82, 146}, ++{236, 77, 149}, ++{173, 118, 130}, ++{177, 115, 131}, ++{185, 109, 134}, ++{194, 103, 137}, ++{205, 96, 140}, ++{216, 89, 143}, ++{227, 82, 146}, ++{236, 77, 149}, ++{94, 93, 107}, ++{104, 90, 112}, ++{119, 86, 118}, ++{135, 81, 124}, ++{151, 76, 130}, ++{167, 70, 135}, ++{183, 64, 140}, ++{195, 60, 144}, ++{94, 93, 107}, ++{104, 91, 112}, ++{119, 86, 118}, ++{135, 81, 124}, ++{151, 76, 130}, ++{167, 70, 135}, ++{183, 64, 140}, ++{195, 60, 144}, ++{95, 93, 107}, ++{105, 91, 112}, ++{119, 87, 118}, ++{135, 81, 124}, ++{152, 76, 130}, ++{168, 70, 135}, ++{184, 64, 140}, ++{195, 60, 144}, ++{96, 94, 108}, ++{106, 92, 112}, ++{120, 87, 118}, ++{136, 82, 124}, ++{152, 76, 130}, ++{168, 70, 135}, ++{184, 64, 140}, ++{196, 60, 144}, ++{98, 95, 108}, ++{107, 92, 113}, ++{121, 88, 119}, ++{137, 82, 125}, ++{153, 77, 130}, ++{169, 71, 136}, ++{185, 65, 140}, ++{196, 60, 144}, ++{100, 96, 109}, ++{109, 93, 113}, ++{123, 88, 119}, ++{138, 83, 125}, ++{154, 77, 131}, ++{170, 71, 136}, ++{185, 65, 140}, ++{197, 61, 144}, ++{102, 97, 110}, ++{111, 94, 114}, ++{124, 89, 119}, ++{139, 84, 125}, ++{155, 78, 131}, ++{171, 72, 136}, ++{186, 66, 141}, ++{198, 61, 144}, ++{104, 98, 111}, ++{113, 95, 114}, ++{126, 90, 120}, ++{141, 84, 126}, ++{156, 78, 131}, ++{172, 72, 136}, ++{187, 66, 141}, ++{199, 62, 144}, ++{107, 100, 111}, ++{115, 96, 115}, ++{128, 91, 120}, ++{142, 85, 126}, ++{158, 79, 131}, ++{173, 73, 136}, ++{188, 67, 141}, ++{200, 62, 144}, ++{109, 101, 112}, ++{117, 97, 116}, ++{130, 92, 121}, ++{144, 86, 126}, ++{159, 80, 131}, ++{175, 73, 136}, ++{190, 67, 141}, ++{201, 63, 144}, ++{112, 102, 113}, ++{120, 99, 117}, ++{132, 93, 121}, ++{146, 87, 127}, ++{161, 80, 132}, ++{176, 74, 137}, ++{191, 68, 141}, ++{202, 63, 144}, ++{115, 103, 114}, ++{123, 100, 117}, ++{135, 94, 122}, ++{148, 88, 127}, ++{163, 81, 132}, ++{178, 75, 137}, ++{193, 68, 141}, ++{204, 64, 144}, ++{118, 105, 115}, ++{126, 101, 118}, ++{137, 95, 123}, ++{151, 89, 128}, ++{165, 82, 132}, ++{179, 75, 137}, ++{194, 69, 141}, ++{205, 65, 145}, ++{122, 106, 116}, ++{129, 102, 119}, ++{140, 96, 123}, ++{153, 89, 128}, ++{167, 83, 133}, ++{181, 76, 137}, ++{196, 70, 142}, ++{207, 65, 145}, ++{125, 107, 117}, ++{132, 103, 120}, ++{143, 97, 124}, ++{155, 90, 128}, ++{169, 84, 133}, ++{183, 77, 138}, ++{198, 71, 142}, ++{208, 66, 145}, ++{128, 108, 118}, ++{135, 104, 121}, ++{145, 98, 124}, ++{158, 91, 129}, ++{171, 85, 133}, ++{185, 78, 138}, ++{199, 71, 142}, ++{210, 67, 145}, ++{132, 109, 119}, ++{138, 105, 121}, ++{148, 99, 125}, ++{161, 92, 129}, ++{174, 85, 134}, ++{187, 79, 138}, ++{201, 72, 142}, ++{212, 67, 145}, ++{135, 110, 120}, ++{141, 106, 122}, ++{151, 100, 126}, ++{163, 93, 130}, ++{176, 86, 134}, ++{190, 80, 138}, ++{203, 73, 142}, ++{214, 68, 145}, ++{139, 110, 121}, ++{145, 107, 123}, ++{154, 101, 126}, ++{166, 94, 130}, ++{179, 87, 135}, ++{192, 80, 139}, ++{205, 74, 143}, ++{216, 69, 146}, ++{143, 111, 122}, ++{148, 108, 124}, ++{158, 102, 127}, ++{169, 95, 131}, ++{181, 88, 135}, ++{194, 81, 139}, ++{208, 75, 143}, ++{218, 70, 146}, ++{146, 112, 122}, ++{152, 108, 124}, ++{161, 103, 128}, ++{172, 96, 131}, ++{184, 89, 135}, ++{197, 82, 139}, ++{210, 75, 143}, ++{220, 71, 146}, ++{150, 113, 123}, ++{155, 109, 125}, ++{164, 103, 128}, ++{175, 97, 132}, ++{187, 90, 136}, ++{199, 83, 140}, ++{212, 76, 143}, ++{222, 71, 146}, ++{154, 113, 124}, ++{159, 110, 126}, ++{167, 104, 129}, ++{178, 98, 132}, ++{190, 91, 136}, ++{202, 84, 140}, ++{215, 77, 144}, ++{224, 72, 146}, ++{157, 114, 125}, ++{162, 111, 127}, ++{171, 105, 129}, ++{181, 98, 133}, ++{192, 92, 137}, ++{204, 85, 140}, ++{217, 78, 144}, ++{226, 73, 147}, ++{161, 115, 126}, ++{166, 111, 127}, ++{174, 106, 130}, ++{184, 99, 133}, ++{195, 92, 137}, ++{207, 86, 141}, ++{219, 79, 144}, ++{229, 74, 147}, ++{165, 115, 126}, ++{170, 112, 128}, ++{178, 106, 131}, ++{187, 100, 134}, ++{198, 93, 137}, ++{210, 86, 141}, ++{222, 80, 144}, ++{231, 75, 147}, ++{169, 116, 127}, ++{173, 113, 129}, ++{181, 107, 131}, ++{190, 101, 134}, ++{201, 94, 138}, ++{213, 87, 141}, ++{225, 80, 145}, ++{234, 75, 147}, ++{173, 116, 128}, ++{177, 113, 129}, ++{184, 108, 132}, ++{194, 101, 135}, ++{204, 95, 138}, ++{215, 88, 142}, ++{227, 81, 145}, ++{236, 76, 147}, ++{174, 117, 128}, ++{179, 113, 130}, ++{186, 108, 132}, ++{195, 102, 135}, ++{206, 95, 138}, ++{217, 88, 142}, ++{228, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{179, 113, 130}, ++{186, 108, 132}, ++{195, 102, 135}, ++{206, 95, 138}, ++{217, 88, 142}, ++{228, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{179, 113, 130}, ++{186, 108, 132}, ++{195, 102, 135}, ++{206, 95, 138}, ++{217, 88, 142}, ++{228, 82, 145}, ++{237, 77, 148}, ++{174, 117, 128}, ++{179, 113, 130}, ++{186, 108, 132}, ++{195, 102, 135}, ++{206, 95, 138}, ++{217, 88, 142}, ++{228, 82, 145}, ++{237, 77, 148}, ++{97, 90, 105}, ++{106, 88, 109}, ++{121, 85, 115}, ++{137, 80, 122}, ++{153, 74, 128}, ++{169, 69, 133}, ++{185, 63, 138}, ++{196, 59, 142}, ++{97, 90, 105}, ++{107, 88, 109}, ++{121, 85, 115}, ++{137, 80, 122}, ++{153, 75, 128}, ++{169, 69, 133}, ++{185, 63, 138}, ++{196, 59, 142}, ++{98, 91, 105}, ++{107, 89, 109}, ++{122, 85, 116}, ++{137, 80, 122}, ++{153, 75, 128}, ++{169, 69, 133}, ++{185, 64, 138}, ++{197, 59, 142}, ++{99, 91, 105}, ++{108, 89, 110}, ++{122, 85, 116}, ++{138, 80, 122}, ++{154, 75, 128}, ++{170, 69, 133}, ++{185, 64, 138}, ++{197, 60, 142}, ++{101, 92, 106}, ++{110, 90, 110}, ++{123, 86, 116}, ++{139, 81, 122}, ++{155, 75, 128}, ++{170, 70, 134}, ++{186, 64, 138}, ++{198, 60, 142}, ++{102, 94, 107}, ++{111, 91, 111}, ++{125, 87, 117}, ++{140, 82, 123}, ++{156, 76, 128}, ++{171, 70, 134}, ++{187, 64, 139}, ++{198, 60, 142}, ++{104, 95, 107}, ++{113, 92, 111}, ++{126, 88, 117}, ++{141, 82, 123}, ++{157, 76, 129}, ++{172, 71, 134}, ++{188, 65, 139}, ++{199, 61, 142}, ++{107, 96, 108}, ++{115, 93, 112}, ++{128, 88, 117}, ++{143, 83, 123}, ++{158, 77, 129}, ++{173, 71, 134}, ++{189, 65, 139}, ++{200, 61, 142}, ++{109, 97, 109}, ++{117, 94, 113}, ++{130, 89, 118}, ++{144, 84, 124}, ++{159, 78, 129}, ++{175, 72, 134}, ++{190, 66, 139}, ++{201, 61, 142}, ++{112, 99, 110}, ++{120, 95, 113}, ++{132, 90, 119}, ++{146, 85, 124}, ++{161, 79, 129}, ++{176, 72, 134}, ++{191, 66, 139}, ++{202, 62, 142}, ++{115, 100, 111}, ++{122, 97, 114}, ++{134, 91, 119}, ++{148, 85, 124}, ++{163, 79, 130}, ++{178, 73, 135}, ++{192, 67, 139}, ++{203, 63, 143}, ++{117, 101, 112}, ++{125, 98, 115}, ++{137, 92, 120}, ++{150, 86, 125}, ++{165, 80, 130}, ++{179, 74, 135}, ++{194, 68, 139}, ++{205, 63, 143}, ++{121, 102, 113}, ++{128, 99, 116}, ++{139, 93, 120}, ++{152, 87, 125}, ++{166, 81, 130}, ++{181, 75, 135}, ++{195, 68, 140}, ++{206, 64, 143}, ++{124, 104, 114}, ++{131, 100, 117}, ++{142, 95, 121}, ++{155, 88, 126}, ++{169, 82, 131}, ++{183, 75, 135}, ++{197, 69, 140}, ++{208, 65, 143}, ++{127, 105, 115}, ++{134, 101, 118}, ++{144, 96, 122}, ++{157, 89, 126}, ++{171, 83, 131}, ++{185, 76, 136}, ++{199, 70, 140}, ++{209, 65, 143}, ++{130, 106, 116}, ++{137, 102, 118}, ++{147, 97, 122}, ++{160, 90, 127}, ++{173, 84, 131}, ++{187, 77, 136}, ++{201, 71, 140}, ++{211, 66, 143}, ++{134, 107, 117}, ++{140, 103, 119}, ++{150, 98, 123}, ++{162, 91, 127}, ++{175, 84, 132}, ++{189, 78, 136}, ++{203, 71, 140}, ++{213, 67, 144}, ++{137, 108, 118}, ++{143, 104, 120}, ++{153, 99, 124}, ++{165, 92, 128}, ++{178, 85, 132}, ++{191, 79, 137}, ++{205, 72, 141}, ++{215, 68, 144}, ++{141, 109, 119}, ++{147, 105, 121}, ++{156, 99, 124}, ++{168, 93, 128}, ++{180, 86, 133}, ++{193, 80, 137}, ++{207, 73, 141}, ++{217, 68, 144}, ++{144, 110, 119}, ++{150, 106, 122}, ++{159, 100, 125}, ++{170, 94, 129}, ++{183, 87, 133}, ++{196, 80, 137}, ++{209, 74, 141}, ++{219, 69, 144}, ++{148, 110, 120}, ++{153, 107, 122}, ++{162, 101, 126}, ++{173, 95, 130}, ++{185, 88, 134}, ++{198, 81, 138}, ++{211, 75, 141}, ++{221, 70, 144}, ++{152, 111, 121}, ++{157, 108, 123}, ++{166, 102, 126}, ++{176, 96, 130}, ++{188, 89, 134}, ++{201, 82, 138}, ++{213, 76, 142}, ++{223, 71, 145}, ++{155, 112, 122}, ++{160, 109, 124}, ++{169, 103, 127}, ++{179, 97, 131}, ++{191, 90, 134}, ++{203, 83, 138}, ++{216, 76, 142}, ++{225, 72, 145}, ++{159, 113, 123}, ++{164, 109, 125}, ++{172, 104, 128}, ++{182, 97, 131}, ++{194, 91, 135}, ++{206, 84, 139}, ++{218, 77, 142}, ++{228, 72, 145}, ++{163, 113, 124}, ++{168, 110, 125}, ++{176, 105, 128}, ++{185, 98, 132}, ++{197, 91, 135}, ++{208, 85, 139}, ++{221, 78, 143}, ++{230, 73, 145}, ++{167, 114, 125}, ++{171, 111, 126}, ++{179, 105, 129}, ++{189, 99, 132}, ++{199, 92, 136}, ++{211, 86, 139}, ++{223, 79, 143}, ++{232, 74, 146}, ++{170, 115, 125}, ++{175, 111, 127}, ++{182, 106, 130}, ++{192, 100, 133}, ++{202, 93, 136}, ++{214, 86, 140}, ++{226, 80, 143}, ++{235, 75, 146}, ++{174, 115, 126}, ++{178, 112, 128}, ++{186, 107, 130}, ++{195, 101, 133}, ++{205, 94, 137}, ++{217, 87, 140}, ++{228, 81, 143}, ++{237, 76, 146}, ++{176, 115, 126}, ++{180, 112, 128}, ++{188, 107, 130}, ++{197, 101, 133}, ++{207, 94, 137}, ++{218, 88, 140}, ++{230, 81, 144}, ++{238, 76, 146}, ++{176, 115, 126}, ++{180, 112, 128}, ++{188, 107, 130}, ++{197, 101, 133}, ++{207, 94, 137}, ++{218, 88, 140}, ++{230, 81, 144}, ++{238, 76, 146}, ++{176, 115, 126}, ++{180, 112, 128}, ++{188, 107, 130}, ++{197, 101, 133}, ++{207, 94, 137}, ++{218, 88, 140}, ++{230, 81, 144}, ++{238, 76, 146}, ++{176, 115, 126}, ++{180, 112, 128}, ++{188, 107, 130}, ++{197, 101, 133}, ++{207, 94, 137}, ++{218, 88, 140}, ++{230, 81, 144}, ++{238, 76, 146}, ++{100, 87, 102}, ++{109, 86, 107}, ++{123, 83, 113}, ++{139, 78, 119}, ++{155, 73, 126}, ++{170, 68, 131}, ++{186, 63, 136}, ++{198, 58, 140}, ++{100, 88, 102}, ++{109, 86, 107}, ++{123, 83, 113}, ++{139, 78, 119}, ++{155, 73, 126}, ++{171, 68, 131}, ++{186, 63, 136}, ++{198, 58, 140}, ++{101, 88, 103}, ++{110, 87, 107}, ++{124, 83, 113}, ++{139, 79, 120}, ++{155, 74, 126}, ++{171, 68, 131}, ++{187, 63, 136}, ++{198, 59, 140}, ++{102, 89, 103}, ++{111, 87, 107}, ++{125, 84, 113}, ++{140, 79, 120}, ++{156, 74, 126}, ++{171, 68, 131}, ++{187, 63, 136}, ++{198, 59, 140}, ++{103, 90, 104}, ++{112, 88, 108}, ++{126, 84, 114}, ++{141, 80, 120}, ++{156, 74, 126}, ++{172, 69, 131}, ++{188, 63, 136}, ++{199, 59, 140}, ++{105, 91, 104}, ++{114, 89, 108}, ++{127, 85, 114}, ++{142, 80, 120}, ++{157, 75, 126}, ++{173, 69, 132}, ++{188, 64, 137}, ++{200, 59, 140}, ++{107, 92, 105}, ++{115, 90, 109}, ++{128, 86, 115}, ++{143, 81, 121}, ++{158, 75, 126}, ++{174, 70, 132}, ++{189, 64, 137}, ++{200, 60, 140}, ++{109, 94, 106}, ++{117, 91, 110}, ++{130, 87, 115}, ++{145, 82, 121}, ++{160, 76, 127}, ++{175, 70, 132}, ++{190, 65, 137}, ++{201, 60, 140}, ++{112, 95, 107}, ++{120, 92, 110}, ++{132, 88, 116}, ++{146, 82, 121}, ++{161, 77, 127}, ++{176, 71, 132}, ++{191, 65, 137}, ++{202, 61, 140}, ++{114, 96, 108}, ++{122, 93, 111}, ++{134, 89, 116}, ++{148, 83, 122}, ++{163, 77, 127}, ++{178, 71, 132}, ++{192, 66, 137}, ++{204, 61, 141}, ++{117, 98, 109}, ++{124, 95, 112}, ++{136, 90, 117}, ++{150, 84, 122}, ++{164, 78, 128}, ++{179, 72, 133}, ++{194, 66, 137}, ++{205, 62, 141}, ++{120, 99, 110}, ++{127, 96, 113}, ++{139, 91, 118}, ++{152, 85, 123}, ++{166, 79, 128}, ++{181, 73, 133}, ++{195, 67, 138}, ++{206, 63, 141}, ++{123, 100, 111}, ++{130, 97, 114}, ++{141, 92, 118}, ++{154, 86, 123}, ++{168, 80, 128}, ++{182, 74, 133}, ++{197, 68, 138}, ++{208, 63, 141}, ++{126, 102, 112}, ++{133, 98, 114}, ++{144, 93, 119}, ++{156, 87, 124}, ++{170, 81, 129}, ++{184, 74, 133}, ++{198, 68, 138}, ++{209, 64, 141}, ++{129, 103, 113}, ++{136, 99, 115}, ++{146, 94, 120}, ++{159, 88, 124}, ++{172, 82, 129}, ++{186, 75, 134}, ++{200, 69, 138}, ++{211, 65, 141}, ++{132, 104, 114}, ++{139, 100, 116}, ++{149, 95, 120}, ++{161, 89, 125}, ++{175, 83, 129}, ++{188, 76, 134}, ++{202, 70, 138}, ++{212, 65, 142}, ++{136, 105, 115}, ++{142, 102, 117}, ++{152, 96, 121}, ++{164, 90, 125}, ++{177, 83, 130}, ++{190, 77, 134}, ++{204, 71, 139}, ++{214, 66, 142}, ++{139, 106, 116}, ++{145, 103, 118}, ++{155, 97, 122}, ++{167, 91, 126}, ++{179, 84, 130}, ++{192, 78, 135}, ++{206, 71, 139}, ++{216, 67, 142}, ++{143, 107, 116}, ++{148, 104, 119}, ++{158, 98, 122}, ++{169, 92, 126}, ++{182, 85, 131}, ++{195, 79, 135}, ++{208, 72, 139}, ++{218, 68, 142}, ++{146, 108, 117}, ++{152, 104, 120}, ++{161, 99, 123}, ++{172, 93, 127}, ++{184, 86, 131}, ++{197, 80, 135}, ++{210, 73, 139}, ++{220, 68, 142}, ++{150, 109, 118}, ++{155, 105, 120}, ++{164, 100, 124}, ++{175, 94, 128}, ++{187, 87, 132}, ++{199, 80, 136}, ++{212, 74, 140}, ++{222, 69, 143}, ++{153, 110, 119}, ++{159, 106, 121}, ++{167, 101, 124}, ++{178, 95, 128}, ++{190, 88, 132}, ++{202, 81, 136}, ++{215, 75, 140}, ++{224, 70, 143}, ++{157, 110, 120}, ++{162, 107, 122}, ++{170, 102, 125}, ++{181, 95, 129}, ++{192, 89, 133}, ++{204, 82, 136}, ++{217, 76, 140}, ++{226, 71, 143}, ++{161, 111, 121}, ++{166, 108, 123}, ++{174, 103, 126}, ++{184, 96, 129}, ++{195, 90, 133}, ++{207, 83, 137}, ++{219, 76, 141}, ++{229, 72, 143}, ++{164, 112, 122}, ++{169, 109, 124}, ++{177, 103, 126}, ++{187, 97, 130}, ++{198, 91, 133}, ++{210, 84, 137}, ++{222, 77, 141}, ++{231, 73, 144}, ++{168, 113, 123}, ++{173, 109, 124}, ++{180, 104, 127}, ++{190, 98, 130}, ++{201, 91, 134}, ++{212, 85, 138}, ++{224, 78, 141}, ++{233, 73, 144}, ++{172, 113, 123}, ++{176, 110, 125}, ++{184, 105, 128}, ++{193, 99, 131}, ++{204, 92, 134}, ++{215, 86, 138}, ++{227, 79, 142}, ++{236, 74, 144}, ++{176, 114, 124}, ++{180, 111, 126}, ++{187, 106, 128}, ++{196, 100, 131}, ++{207, 93, 135}, ++{218, 86, 138}, ++{229, 80, 142}, ++{238, 75, 144}, ++{177, 114, 125}, ++{182, 111, 126}, ++{189, 106, 129}, ++{198, 100, 132}, ++{208, 93, 135}, ++{219, 87, 139}, ++{231, 80, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{182, 111, 126}, ++{189, 106, 129}, ++{198, 100, 132}, ++{208, 93, 135}, ++{219, 87, 139}, ++{231, 80, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{182, 111, 126}, ++{189, 106, 129}, ++{198, 100, 132}, ++{208, 93, 135}, ++{219, 87, 139}, ++{231, 80, 142}, ++{239, 75, 145}, ++{177, 114, 125}, ++{182, 111, 126}, ++{189, 106, 129}, ++{198, 100, 132}, ++{208, 93, 135}, ++{219, 87, 139}, ++{231, 80, 142}, ++{239, 75, 145}, ++{103, 85, 100}, ++{112, 84, 104}, ++{125, 81, 111}, ++{141, 77, 117}, ++{156, 72, 123}, ++{172, 67, 129}, ++{188, 62, 134}, ++{199, 58, 138}, ++{103, 85, 100}, ++{112, 84, 104}, ++{126, 81, 111}, ++{141, 77, 117}, ++{157, 72, 123}, ++{172, 67, 129}, ++{188, 62, 134}, ++{199, 58, 138}, ++{104, 85, 100}, ++{113, 84, 105}, ++{126, 81, 111}, ++{141, 77, 117}, ++{157, 72, 123}, ++{173, 67, 129}, ++{188, 62, 134}, ++{199, 58, 138}, ++{105, 86, 101}, ++{114, 85, 105}, ++{127, 82, 111}, ++{142, 78, 117}, ++{158, 73, 123}, ++{173, 67, 129}, ++{188, 62, 134}, ++{200, 58, 138}, ++{106, 87, 101}, ++{115, 86, 105}, ++{128, 82, 111}, ++{143, 78, 118}, ++{158, 73, 124}, ++{174, 68, 129}, ++{189, 62, 134}, ++{200, 58, 138}, ++{108, 88, 102}, ++{116, 87, 106}, ++{129, 83, 112}, ++{144, 79, 118}, ++{159, 74, 124}, ++{175, 68, 129}, ++{190, 63, 134}, ++{201, 59, 138}, ++{110, 90, 103}, ++{118, 88, 107}, ++{131, 84, 112}, ++{145, 79, 118}, ++{160, 74, 124}, ++{176, 69, 130}, ++{191, 63, 135}, ++{202, 59, 138}, ++{112, 91, 103}, ++{120, 89, 107}, ++{132, 85, 113}, ++{147, 80, 119}, ++{162, 75, 124}, ++{177, 69, 130}, ++{192, 64, 135}, ++{203, 60, 138}, ++{114, 92, 104}, ++{122, 90, 108}, ++{134, 86, 113}, ++{148, 81, 119}, ++{163, 75, 125}, ++{178, 70, 130}, ++{193, 64, 135}, ++{204, 60, 138}, ++{117, 94, 105}, ++{124, 91, 109}, ++{136, 87, 114}, ++{150, 82, 120}, ++{164, 76, 125}, ++{179, 70, 130}, ++{194, 65, 135}, ++{205, 61, 139}, ++{119, 95, 106}, ++{127, 93, 110}, ++{138, 88, 115}, ++{152, 83, 120}, ++{166, 77, 125}, ++{181, 71, 131}, ++{195, 65, 135}, ++{206, 61, 139}, ++{122, 97, 107}, ++{129, 94, 110}, ++{141, 89, 115}, ++{154, 84, 121}, ++{168, 78, 126}, ++{182, 72, 131}, ++{197, 66, 136}, ++{208, 62, 139}, ++{125, 98, 108}, ++{132, 95, 111}, ++{143, 90, 116}, ++{156, 85, 121}, ++{170, 79, 126}, ++{184, 73, 131}, ++{198, 67, 136}, ++{209, 62, 139}, ++{128, 99, 109}, ++{135, 96, 112}, ++{146, 91, 117}, ++{158, 86, 122}, ++{172, 80, 127}, ++{186, 74, 131}, ++{200, 68, 136}, ++{210, 63, 139}, ++{131, 101, 110}, ++{138, 97, 113}, ++{148, 92, 117}, ++{161, 87, 122}, ++{174, 80, 127}, ++{188, 74, 132}, ++{202, 68, 136}, ++{212, 64, 140}, ++{135, 102, 111}, ++{141, 99, 114}, ++{151, 93, 118}, ++{163, 88, 123}, ++{176, 81, 127}, ++{190, 75, 132}, ++{203, 69, 137}, ++{214, 65, 140}, ++{138, 103, 112}, ++{144, 100, 115}, ++{154, 95, 119}, ++{166, 89, 123}, ++{178, 82, 128}, ++{192, 76, 132}, ++{205, 70, 137}, ++{216, 65, 140}, ++{141, 104, 113}, ++{147, 101, 116}, ++{157, 96, 119}, ++{168, 90, 124}, ++{181, 83, 128}, ++{194, 77, 133}, ++{207, 71, 137}, ++{217, 66, 140}, ++{145, 105, 114}, ++{150, 102, 117}, ++{160, 97, 120}, ++{171, 90, 124}, ++{183, 84, 129}, ++{196, 78, 133}, ++{209, 71, 137}, ++{219, 67, 140}, ++{148, 106, 115}, ++{154, 103, 117}, ++{163, 98, 121}, ++{174, 91, 125}, ++{186, 85, 129}, ++{198, 79, 134}, ++{211, 72, 138}, ++{221, 68, 141}, ++{152, 107, 116}, ++{157, 104, 118}, ++{166, 98, 122}, ++{177, 92, 126}, ++{188, 86, 130}, ++{201, 80, 134}, ++{214, 73, 138}, ++{223, 68, 141}, ++{155, 108, 117}, ++{160, 105, 119}, ++{169, 99, 122}, ++{179, 93, 126}, ++{191, 87, 130}, ++{203, 80, 134}, ++{216, 74, 138}, ++{225, 69, 141}, ++{159, 109, 118}, ++{164, 106, 120}, ++{172, 100, 123}, ++{182, 94, 127}, ++{194, 88, 131}, ++{206, 81, 135}, ++{218, 75, 139}, ++{228, 70, 142}, ++{162, 110, 119}, ++{167, 106, 121}, ++{175, 101, 124}, ++{185, 95, 127}, ++{196, 89, 131}, ++{208, 82, 135}, ++{221, 76, 139}, ++{230, 71, 142}, ++{166, 110, 120}, ++{171, 107, 122}, ++{179, 102, 125}, ++{188, 96, 128}, ++{199, 90, 132}, ++{211, 83, 135}, ++{223, 77, 139}, ++{232, 72, 142}, ++{170, 111, 121}, ++{174, 108, 122}, ++{182, 103, 125}, ++{191, 97, 129}, ++{202, 90, 132}, ++{214, 84, 136}, ++{225, 77, 140}, ++{235, 73, 142}, ++{173, 112, 122}, ++{178, 109, 123}, ++{185, 104, 126}, ++{195, 98, 129}, ++{205, 91, 133}, ++{216, 85, 136}, ++{228, 78, 140}, ++{237, 73, 143}, ++{177, 112, 122}, ++{181, 109, 124}, ++{189, 104, 127}, ++{198, 98, 130}, ++{208, 92, 133}, ++{219, 86, 137}, ++{231, 79, 140}, ++{239, 74, 143}, ++{179, 113, 123}, ++{183, 110, 124}, ++{190, 105, 127}, ++{199, 99, 130}, ++{210, 92, 133}, ++{220, 86, 137}, ++{232, 79, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{183, 110, 124}, ++{190, 105, 127}, ++{199, 99, 130}, ++{210, 92, 133}, ++{220, 86, 137}, ++{232, 79, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{183, 110, 124}, ++{190, 105, 127}, ++{199, 99, 130}, ++{210, 92, 133}, ++{220, 86, 137}, ++{232, 79, 140}, ++{241, 75, 143}, ++{179, 113, 123}, ++{183, 110, 124}, ++{190, 105, 127}, ++{199, 99, 130}, ++{210, 92, 133}, ++{220, 86, 137}, ++{232, 79, 140}, ++{241, 75, 143}, ++{106, 82, 97}, ++{114, 81, 102}, ++{128, 79, 108}, ++{143, 75, 115}, ++{158, 71, 121}, ++{174, 66, 127}, ++{189, 61, 132}, ++{201, 57, 136}, ++{106, 82, 98}, ++{115, 81, 102}, ++{128, 79, 108}, ++{143, 75, 115}, ++{158, 71, 121}, ++{174, 66, 127}, ++{189, 61, 132}, ++{201, 57, 136}, ++{107, 83, 98}, ++{115, 82, 102}, ++{129, 79, 108}, ++{143, 76, 115}, ++{159, 71, 121}, ++{174, 66, 127}, ++{190, 61, 132}, ++{201, 57, 136}, ++{108, 84, 98}, ++{116, 83, 103}, ++{129, 80, 109}, ++{144, 76, 115}, ++{159, 71, 121}, ++{175, 66, 127}, ++{190, 61, 132}, ++{201, 57, 136}, ++{109, 85, 99}, ++{117, 83, 103}, ++{130, 81, 109}, ++{145, 76, 115}, ++{160, 72, 121}, ++{175, 67, 127}, ++{191, 61, 132}, ++{202, 58, 136}, ++{111, 86, 100}, ++{119, 84, 104}, ++{132, 81, 109}, ++{146, 77, 116}, ++{161, 72, 122}, ++{176, 67, 127}, ++{191, 62, 132}, ++{203, 58, 136}, ++{112, 87, 100}, ++{120, 85, 104}, ++{133, 82, 110}, ++{147, 78, 116}, ++{162, 73, 122}, ++{177, 68, 127}, ++{192, 62, 133}, ++{203, 58, 136}, ++{115, 89, 101}, ++{122, 87, 105}, ++{135, 83, 110}, ++{149, 79, 116}, ++{163, 73, 122}, ++{178, 68, 128}, ++{193, 63, 133}, ++{204, 59, 136}, ++{117, 90, 102}, ++{124, 88, 106}, ++{136, 84, 111}, ++{150, 79, 117}, ++{165, 74, 122}, ++{180, 69, 128}, ++{194, 63, 133}, ++{205, 59, 136}, ++{119, 91, 103}, ++{127, 89, 106}, ++{138, 85, 112}, ++{152, 80, 117}, ++{166, 75, 123}, ++{181, 69, 128}, ++{195, 64, 133}, ++{206, 60, 137}, ++{122, 93, 104}, ++{129, 90, 107}, ++{140, 86, 112}, ++{154, 81, 118}, ++{168, 76, 123}, ++{182, 70, 128}, ++{197, 65, 133}, ++{208, 60, 137}, ++{125, 94, 105}, ++{132, 92, 108}, ++{143, 87, 113}, ++{156, 82, 118}, ++{170, 77, 124}, ++{184, 71, 129}, ++{198, 65, 134}, ++{209, 61, 137}, ++{128, 96, 106}, ++{134, 93, 109}, ++{145, 88, 114}, ++{158, 83, 119}, ++{172, 77, 124}, ++{186, 72, 129}, ++{200, 66, 134}, ++{210, 62, 137}, ++{131, 97, 107}, ++{137, 94, 110}, ++{148, 90, 114}, ++{160, 84, 119}, ++{174, 78, 124}, ++{187, 72, 129}, ++{201, 67, 134}, ++{212, 62, 137}, ++{134, 98, 108}, ++{140, 95, 111}, ++{150, 91, 115}, ++{162, 85, 120}, ++{176, 79, 125}, ++{189, 73, 130}, ++{203, 67, 134}, ++{213, 63, 138}, ++{137, 100, 109}, ++{143, 97, 112}, ++{153, 92, 116}, ++{165, 86, 121}, ++{178, 80, 125}, ++{191, 74, 130}, ++{205, 68, 135}, ++{215, 64, 138}, ++{140, 101, 110}, ++{146, 98, 113}, ++{156, 93, 117}, ++{167, 87, 121}, ++{180, 81, 126}, ++{193, 75, 130}, ++{207, 69, 135}, ++{217, 65, 138}, ++{143, 102, 111}, ++{149, 99, 114}, ++{159, 94, 117}, ++{170, 88, 122}, ++{182, 82, 126}, ++{195, 76, 131}, ++{209, 70, 135}, ++{219, 65, 138}, ++{147, 103, 112}, ++{152, 100, 114}, ++{161, 95, 118}, ++{173, 89, 122}, ++{185, 83, 127}, ++{198, 77, 131}, ++{211, 71, 136}, ++{221, 66, 139}, ++{150, 104, 113}, ++{156, 101, 115}, ++{164, 96, 119}, ++{175, 90, 123}, ++{187, 84, 127}, ++{200, 78, 132}, ++{213, 71, 136}, ++{223, 67, 139}, ++{154, 105, 114}, ++{159, 102, 116}, ++{168, 97, 120}, ++{178, 91, 124}, ++{190, 85, 128}, ++{202, 79, 132}, ++{215, 72, 136}, ++{225, 68, 139}, ++{157, 106, 115}, ++{162, 103, 117}, ++{171, 98, 120}, ++{181, 92, 124}, ++{193, 86, 128}, ++{205, 79, 132}, ++{217, 73, 137}, ++{227, 69, 140}, ++{161, 107, 116}, ++{166, 104, 118}, ++{174, 99, 121}, ++{184, 93, 125}, ++{195, 87, 129}, ++{207, 80, 133}, ++{220, 74, 137}, ++{229, 69, 140}, ++{164, 108, 117}, ++{169, 105, 119}, ++{177, 100, 122}, ++{187, 94, 125}, ++{198, 88, 129}, ++{210, 81, 133}, ++{222, 75, 137}, ++{231, 70, 140}, ++{168, 109, 118}, ++{172, 106, 120}, ++{180, 101, 123}, ++{190, 95, 126}, ++{201, 88, 130}, ++{212, 82, 134}, ++{224, 76, 138}, ++{233, 71, 140}, ++{171, 109, 119}, ++{176, 106, 120}, ++{184, 101, 123}, ++{193, 96, 127}, ++{204, 89, 130}, ++{215, 83, 134}, ++{227, 77, 138}, ++{236, 72, 141}, ++{175, 110, 120}, ++{179, 107, 121}, ++{187, 102, 124}, ++{196, 96, 127}, ++{206, 90, 131}, ++{218, 84, 135}, ++{229, 77, 138}, ++{238, 73, 141}, ++{179, 111, 121}, ++{183, 108, 122}, ++{190, 103, 125}, ++{199, 97, 128}, ++{209, 91, 131}, ++{220, 85, 135}, ++{232, 78, 139}, ++{241, 74, 141}, ++{181, 111, 121}, ++{185, 108, 122}, ++{192, 103, 125}, ++{201, 98, 128}, ++{211, 91, 132}, ++{222, 85, 135}, ++{233, 79, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{185, 108, 122}, ++{192, 103, 125}, ++{201, 98, 128}, ++{211, 91, 132}, ++{222, 85, 135}, ++{233, 79, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{185, 108, 122}, ++{192, 103, 125}, ++{201, 98, 128}, ++{211, 91, 132}, ++{222, 85, 135}, ++{233, 79, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{185, 108, 122}, ++{192, 103, 125}, ++{201, 98, 128}, ++{211, 91, 132}, ++{222, 85, 135}, ++{233, 79, 139}, ++{242, 74, 141}, ++{109, 79, 95}, ++{117, 79, 100}, ++{130, 77, 106}, ++{145, 74, 112}, ++{160, 69, 119}, ++{176, 65, 125}, ++{191, 60, 130}, ++{202, 56, 134}, ++{109, 80, 95}, ++{117, 79, 100}, ++{130, 77, 106}, ++{145, 74, 112}, ++{160, 70, 119}, ++{176, 65, 125}, ++{191, 60, 130}, ++{202, 56, 134}, ++{110, 80, 96}, ++{118, 80, 100}, ++{131, 77, 106}, ++{146, 74, 113}, ++{161, 70, 119}, ++{176, 65, 125}, ++{191, 60, 130}, ++{202, 56, 134}, ++{111, 81, 96}, ++{119, 80, 100}, ++{132, 78, 106}, ++{146, 74, 113}, ++{161, 70, 119}, ++{177, 65, 125}, ++{192, 60, 130}, ++{203, 56, 134}, ++{112, 82, 97}, ++{120, 81, 101}, ++{133, 79, 107}, ++{147, 75, 113}, ++{162, 70, 119}, ++{177, 66, 125}, ++{192, 61, 130}, ++{203, 57, 134}, ++{113, 83, 97}, ++{121, 82, 101}, ++{134, 79, 107}, ++{148, 75, 113}, ++{163, 71, 119}, ++{178, 66, 125}, ++{193, 61, 130}, ++{204, 57, 134}, ++{115, 85, 98}, ++{123, 83, 102}, ++{135, 80, 108}, ++{149, 76, 114}, ++{164, 72, 120}, ++{179, 66, 125}, ++{194, 61, 131}, ++{205, 57, 134}, ++{117, 86, 99}, ++{125, 84, 103}, ++{137, 81, 108}, ++{151, 77, 114}, ++{165, 72, 120}, ++{180, 67, 125}, ++{195, 62, 131}, ++{206, 58, 134}, ++{119, 87, 100}, ++{127, 86, 103}, ++{139, 82, 109}, ++{152, 78, 115}, ++{167, 73, 120}, ++{181, 68, 126}, ++{196, 62, 131}, ++{207, 58, 135}, ++{122, 89, 101}, ++{129, 87, 104}, ++{141, 83, 109}, ++{154, 79, 115}, ++{168, 74, 121}, ++{183, 68, 126}, ++{197, 63, 131}, ++{208, 59, 135}, ++{124, 90, 102}, ++{131, 88, 105}, ++{143, 84, 110}, ++{156, 80, 116}, ++{170, 74, 121}, ++{184, 69, 126}, ++{198, 64, 131}, ++{209, 59, 135}, ++{127, 92, 103}, ++{134, 90, 106}, ++{145, 86, 111}, ++{158, 81, 116}, ++{171, 75, 121}, ++{186, 70, 127}, ++{200, 64, 132}, ++{210, 60, 135}, ++{130, 93, 104}, ++{137, 91, 107}, ++{147, 87, 111}, ++{160, 82, 117}, ++{173, 76, 122}, ++{187, 71, 127}, ++{201, 65, 132}, ++{212, 61, 135}, ++{133, 95, 105}, ++{139, 92, 108}, ++{150, 88, 112}, ++{162, 83, 117}, ++{175, 77, 122}, ++{189, 71, 127}, ++{203, 66, 132}, ++{213, 61, 136}, ++{136, 96, 106}, ++{142, 93, 109}, ++{152, 89, 113}, ++{164, 84, 118}, ++{177, 78, 123}, ++{191, 72, 128}, ++{205, 66, 132}, ++{215, 62, 136}, ++{139, 98, 107}, ++{145, 95, 110}, ++{155, 90, 114}, ++{167, 85, 118}, ++{179, 79, 123}, ++{193, 73, 128}, ++{206, 67, 133}, ++{217, 63, 136}, ++{142, 99, 108}, ++{148, 96, 110}, ++{158, 91, 114}, ++{169, 86, 119}, ++{182, 80, 124}, ++{195, 74, 128}, ++{208, 68, 133}, ++{218, 64, 136}, ++{146, 100, 109}, ++{151, 97, 111}, ++{160, 92, 115}, ++{172, 87, 120}, ++{184, 81, 124}, ++{197, 75, 129}, ++{210, 69, 133}, ++{220, 64, 137}, ++{149, 101, 110}, ++{154, 98, 112}, ++{163, 93, 116}, ++{174, 88, 120}, ++{186, 82, 125}, ++{199, 76, 129}, ++{212, 70, 134}, ++{222, 65, 137}, ++{152, 102, 111}, ++{157, 99, 113}, ++{166, 94, 117}, ++{177, 89, 121}, ++{189, 83, 125}, ++{201, 77, 130}, ++{214, 71, 134}, ++{224, 66, 137}, ++{156, 103, 112}, ++{161, 100, 114}, ++{169, 95, 118}, ++{180, 90, 122}, ++{191, 84, 126}, ++{204, 78, 130}, ++{216, 71, 134}, ++{226, 67, 137}, ++{159, 104, 113}, ++{164, 101, 115}, ++{172, 96, 118}, ++{183, 91, 122}, ++{194, 85, 126}, ++{206, 78, 131}, ++{219, 72, 135}, ++{228, 68, 138}, ++{163, 105, 114}, ++{167, 102, 116}, ++{176, 97, 119}, ++{186, 92, 123}, ++{197, 86, 127}, ++{209, 79, 131}, ++{221, 73, 135}, ++{230, 69, 138}, ++{166, 106, 115}, ++{171, 103, 117}, ++{179, 98, 120}, ++{189, 93, 124}, ++{199, 86, 127}, ++{211, 80, 131}, ++{223, 74, 135}, ++{232, 69, 138}, ++{170, 107, 116}, ++{174, 104, 118}, ++{182, 99, 121}, ++{192, 94, 124}, ++{202, 87, 128}, ++{214, 81, 132}, ++{226, 75, 136}, ++{235, 70, 139}, ++{173, 108, 117}, ++{178, 105, 119}, ++{185, 100, 121}, ++{195, 94, 125}, ++{205, 88, 129}, ++{216, 82, 132}, ++{228, 76, 136}, ++{237, 71, 139}, ++{177, 109, 118}, ++{181, 106, 119}, ++{188, 101, 122}, ++{198, 95, 125}, ++{208, 89, 129}, ++{219, 83, 133}, ++{230, 77, 137}, ++{239, 72, 139}, ++{180, 109, 119}, ++{185, 106, 120}, ++{192, 102, 123}, ++{201, 96, 126}, ++{211, 90, 130}, ++{222, 84, 133}, ++{233, 77, 137}, ++{242, 73, 140}, ++{182, 110, 119}, ++{186, 107, 121}, ++{193, 102, 123}, ++{202, 97, 126}, ++{212, 90, 130}, ++{223, 84, 133}, ++{234, 78, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 121}, ++{193, 102, 123}, ++{202, 97, 126}, ++{212, 90, 130}, ++{223, 84, 133}, ++{234, 78, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 121}, ++{193, 102, 123}, ++{202, 97, 126}, ++{212, 90, 130}, ++{223, 84, 133}, ++{234, 78, 137}, ++{243, 73, 140}, ++{182, 110, 119}, ++{186, 107, 121}, ++{193, 102, 123}, ++{202, 97, 126}, ++{212, 90, 130}, ++{223, 84, 133}, ++{234, 78, 137}, ++{243, 73, 140}, ++{112, 77, 93}, ++{120, 77, 97}, ++{133, 75, 104}, ++{147, 72, 110}, ++{162, 68, 116}, ++{177, 64, 122}, ++{192, 59, 128}, ++{204, 55, 132}, ++{112, 77, 93}, ++{120, 77, 97}, ++{133, 75, 104}, ++{147, 72, 110}, ++{162, 68, 116}, ++{178, 64, 122}, ++{193, 59, 128}, ++{204, 55, 132}, ++{112, 78, 93}, ++{121, 77, 98}, ++{133, 75, 104}, ++{148, 72, 110}, ++{163, 68, 117}, ++{178, 64, 122}, ++{193, 59, 128}, ++{204, 55, 132}, ++{113, 78, 94}, ++{121, 78, 98}, ++{134, 76, 104}, ++{148, 73, 111}, ++{163, 69, 117}, ++{178, 64, 123}, ++{193, 59, 128}, ++{204, 55, 132}, ++{115, 79, 94}, ++{123, 79, 98}, ++{135, 77, 104}, ++{149, 73, 111}, ++{164, 69, 117}, ++{179, 64, 123}, ++{194, 60, 128}, ++{205, 56, 132}, ++{116, 81, 95}, ++{124, 80, 99}, ++{136, 77, 105}, ++{150, 74, 111}, ++{165, 70, 117}, ++{180, 65, 123}, ++{195, 60, 128}, ++{206, 56, 132}, ++{118, 82, 96}, ++{126, 81, 100}, ++{138, 78, 105}, ++{151, 75, 111}, ++{166, 70, 117}, ++{181, 65, 123}, ++{195, 60, 128}, ++{206, 57, 132}, ++{120, 83, 97}, ++{127, 82, 100}, ++{139, 79, 106}, ++{153, 75, 112}, ++{167, 71, 118}, ++{182, 66, 123}, ++{196, 61, 129}, ++{207, 57, 132}, ++{122, 85, 98}, ++{129, 83, 101}, ++{141, 80, 106}, ++{154, 76, 112}, ++{168, 72, 118}, ++{183, 67, 124}, ++{197, 61, 129}, ++{208, 57, 133}, ++{124, 86, 99}, ++{132, 85, 102}, ++{143, 81, 107}, ++{156, 77, 113}, ++{170, 72, 118}, ++{184, 67, 124}, ++{199, 62, 129}, ++{209, 58, 133}, ++{127, 88, 100}, ++{134, 86, 103}, ++{145, 82, 108}, ++{158, 78, 113}, ++{172, 73, 119}, ++{186, 68, 124}, ++{200, 63, 129}, ++{211, 59, 133}, ++{130, 90, 101}, ++{136, 87, 104}, ++{147, 84, 109}, ++{160, 79, 114}, ++{173, 74, 119}, ++{187, 69, 125}, ++{201, 63, 130}, ++{212, 59, 133}, ++{132, 91, 102}, ++{139, 89, 105}, ++{149, 85, 109}, ++{162, 80, 114}, ++{175, 75, 120}, ++{189, 69, 125}, ++{203, 64, 130}, ++{213, 60, 133}, ++{135, 93, 103}, ++{142, 90, 106}, ++{152, 86, 110}, ++{164, 81, 115}, ++{177, 76, 120}, ++{191, 70, 125}, ++{204, 65, 130}, ++{215, 61, 134}, ++{138, 94, 104}, ++{144, 91, 106}, ++{154, 87, 111}, ++{166, 82, 116}, ++{179, 77, 121}, ++{192, 71, 126}, ++{206, 66, 130}, ++{216, 61, 134}, ++{141, 95, 105}, ++{147, 93, 107}, ++{157, 88, 112}, ++{169, 83, 116}, ++{181, 78, 121}, ++{194, 72, 126}, ++{208, 66, 131}, ++{218, 62, 134}, ++{144, 97, 106}, ++{150, 94, 108}, ++{160, 90, 112}, ++{171, 84, 117}, ++{183, 79, 122}, ++{196, 73, 126}, ++{210, 67, 131}, ++{220, 63, 134}, ++{148, 98, 107}, ++{153, 95, 109}, ++{162, 91, 113}, ++{174, 85, 118}, ++{186, 80, 122}, ++{199, 74, 127}, ++{212, 68, 131}, ++{221, 64, 135}, ++{151, 99, 108}, ++{156, 96, 110}, ++{165, 92, 114}, ++{176, 86, 118}, ++{188, 81, 123}, ++{201, 75, 127}, ++{214, 69, 132}, ++{223, 64, 135}, ++{154, 100, 109}, ++{159, 97, 111}, ++{168, 93, 115}, ++{179, 87, 119}, ++{191, 82, 123}, ++{203, 76, 128}, ++{216, 70, 132}, ++{225, 65, 135}, ++{158, 101, 110}, ++{163, 99, 112}, ++{171, 94, 116}, ++{182, 88, 120}, ++{193, 83, 124}, ++{205, 77, 128}, ++{218, 71, 133}, ++{227, 66, 136}, ++{161, 102, 111}, ++{166, 100, 113}, ++{174, 95, 116}, ++{184, 89, 120}, ++{196, 83, 124}, ++{208, 77, 129}, ++{220, 71, 133}, ++{229, 67, 136}, ++{164, 103, 112}, ++{169, 101, 114}, ++{177, 96, 117}, ++{187, 90, 121}, ++{198, 84, 125}, ++{210, 78, 129}, ++{222, 72, 133}, ++{232, 68, 136}, ++{168, 104, 113}, ++{173, 102, 115}, ++{180, 97, 118}, ++{190, 91, 122}, ++{201, 85, 126}, ++{213, 79, 130}, ++{225, 73, 134}, ++{234, 69, 137}, ++{171, 105, 114}, ++{176, 102, 116}, ++{184, 98, 119}, ++{193, 92, 122}, ++{204, 86, 126}, ++{215, 80, 130}, ++{227, 74, 134}, ++{236, 69, 137}, ++{175, 106, 115}, ++{179, 103, 117}, ++{187, 99, 119}, ++{196, 93, 123}, ++{207, 87, 127}, ++{218, 81, 131}, ++{229, 75, 134}, ++{238, 70, 137}, ++{179, 107, 116}, ++{183, 104, 117}, ++{190, 100, 120}, ++{199, 94, 124}, ++{209, 88, 127}, ++{220, 82, 131}, ++{232, 76, 135}, ++{241, 71, 138}, ++{182, 108, 117}, ++{186, 105, 118}, ++{193, 100, 121}, ++{202, 95, 124}, ++{212, 89, 128}, ++{223, 83, 131}, ++{234, 77, 135}, ++{243, 72, 138}, ++{184, 108, 117}, ++{188, 105, 119}, ++{195, 101, 121}, ++{204, 95, 125}, ++{214, 89, 128}, ++{224, 83, 132}, ++{236, 77, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{188, 105, 119}, ++{195, 101, 121}, ++{204, 95, 125}, ++{214, 89, 128}, ++{224, 83, 132}, ++{236, 77, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{188, 105, 119}, ++{195, 101, 121}, ++{204, 95, 125}, ++{214, 89, 128}, ++{224, 83, 132}, ++{236, 77, 135}, ++{244, 72, 138}, ++{184, 108, 117}, ++{188, 105, 119}, ++{195, 101, 121}, ++{204, 95, 125}, ++{214, 89, 128}, ++{224, 83, 132}, ++{236, 77, 135}, ++{244, 72, 138}, ++{115, 74, 91}, ++{123, 74, 95}, ++{135, 73, 101}, ++{149, 70, 108}, ++{164, 67, 114}, ++{179, 62, 120}, ++{194, 58, 126}, ++{205, 54, 130}, ++{115, 74, 91}, ++{123, 74, 95}, ++{135, 73, 101}, ++{150, 70, 108}, ++{164, 67, 114}, ++{179, 62, 120}, ++{194, 58, 126}, ++{205, 54, 130}, ++{115, 75, 91}, ++{123, 75, 95}, ++{136, 73, 102}, ++{150, 71, 108}, ++{165, 67, 114}, ++{180, 63, 120}, ++{195, 58, 126}, ++{206, 54, 130}, ++{116, 76, 92}, ++{124, 75, 96}, ++{136, 74, 102}, ++{151, 71, 108}, ++{165, 67, 115}, ++{180, 63, 120}, ++{195, 58, 126}, ++{206, 55, 130}, ++{118, 77, 92}, ++{125, 76, 96}, ++{137, 75, 102}, ++{151, 71, 109}, ++{166, 68, 115}, ++{181, 63, 121}, ++{196, 58, 126}, ++{206, 55, 130}, ++{119, 78, 93}, ++{127, 77, 97}, ++{139, 75, 103}, ++{152, 72, 109}, ++{167, 68, 115}, ++{182, 64, 121}, ++{196, 59, 126}, ++{207, 55, 130}, ++{121, 79, 94}, ++{128, 78, 97}, ++{140, 76, 103}, ++{154, 73, 109}, ++{168, 69, 115}, ++{182, 64, 121}, ++{197, 59, 126}, ++{208, 56, 130}, ++{123, 81, 95}, ++{130, 80, 98}, ++{141, 77, 104}, ++{155, 74, 110}, ++{169, 69, 116}, ++{184, 65, 121}, ++{198, 60, 127}, ++{209, 56, 130}, ++{125, 82, 95}, ++{132, 81, 99}, ++{143, 78, 104}, ++{156, 75, 110}, ++{170, 70, 116}, ++{185, 65, 122}, ++{199, 60, 127}, ++{210, 57, 131}, ++{127, 84, 96}, ++{134, 82, 100}, ++{145, 79, 105}, ++{158, 75, 111}, ++{172, 71, 116}, ++{186, 66, 122}, ++{200, 61, 127}, ++{211, 57, 131}, ++{130, 86, 97}, ++{136, 84, 101}, ++{147, 81, 106}, ++{160, 76, 111}, ++{173, 72, 117}, ++{187, 67, 122}, ++{202, 62, 127}, ++{212, 58, 131}, ++{132, 87, 98}, ++{139, 85, 101}, ++{149, 82, 106}, ++{162, 77, 112}, ++{175, 73, 117}, ++{189, 67, 122}, ++{203, 62, 128}, ++{213, 58, 131}, ++{135, 89, 99}, ++{141, 87, 102}, ++{152, 83, 107}, ++{164, 78, 112}, ++{177, 73, 118}, ++{191, 68, 123}, ++{204, 63, 128}, ++{215, 59, 131}, ++{138, 90, 100}, ++{144, 88, 103}, ++{154, 84, 108}, ++{166, 80, 113}, ++{179, 74, 118}, ++{192, 69, 123}, ++{206, 64, 128}, ++{216, 60, 132}, ++{141, 92, 102}, ++{147, 89, 104}, ++{156, 85, 109}, ++{168, 81, 114}, ++{181, 75, 119}, ++{194, 70, 124}, ++{208, 64, 128}, ++{218, 60, 132}, ++{144, 93, 103}, ++{149, 91, 105}, ++{159, 87, 109}, ++{170, 82, 114}, ++{183, 76, 119}, ++{196, 71, 124}, ++{209, 65, 129}, ++{219, 61, 132}, ++{147, 94, 104}, ++{152, 92, 106}, ++{162, 88, 110}, ++{173, 83, 115}, ++{185, 77, 120}, ++{198, 72, 124}, ++{211, 66, 129}, ++{221, 62, 133}, ++{150, 96, 105}, ++{155, 93, 107}, ++{164, 89, 111}, ++{175, 84, 116}, ++{187, 78, 120}, ++{200, 73, 125}, ++{213, 67, 130}, ++{223, 63, 133}, ++{153, 97, 106}, ++{158, 94, 108}, ++{167, 90, 112}, ++{178, 85, 116}, ++{190, 79, 121}, ++{202, 74, 125}, ++{215, 68, 130}, ++{225, 64, 133}, ++{156, 98, 107}, ++{161, 96, 109}, ++{170, 91, 113}, ++{181, 86, 117}, ++{192, 80, 121}, ++{205, 74, 126}, ++{217, 69, 130}, ++{227, 64, 134}, ++{160, 99, 108}, ++{165, 97, 110}, ++{173, 92, 114}, ++{183, 87, 118}, ++{195, 81, 122}, ++{207, 75, 126}, ++{219, 70, 131}, ++{229, 65, 134}, ++{163, 101, 109}, ++{168, 98, 111}, ++{176, 93, 114}, ++{186, 88, 118}, ++{197, 82, 123}, ++{209, 76, 127}, ++{221, 70, 131}, ++{231, 66, 134}, ++{166, 102, 110}, ++{171, 99, 112}, ++{179, 94, 115}, ++{189, 89, 119}, ++{200, 83, 123}, ++{212, 77, 127}, ++{224, 71, 131}, ++{233, 67, 135}, ++{170, 103, 111}, ++{174, 100, 113}, ++{182, 95, 116}, ++{192, 90, 120}, ++{203, 84, 124}, ++{214, 78, 128}, ++{226, 72, 132}, ++{235, 68, 135}, ++{173, 104, 112}, ++{178, 101, 114}, ++{185, 96, 117}, ++{195, 91, 120}, ++{205, 85, 124}, ++{217, 79, 128}, ++{228, 73, 132}, ++{237, 69, 135}, ++{177, 104, 113}, ++{181, 102, 115}, ++{189, 97, 118}, ++{198, 92, 121}, ++{208, 86, 125}, ++{219, 80, 129}, ++{231, 74, 133}, ++{240, 69, 136}, ++{180, 105, 114}, ++{185, 103, 116}, ++{192, 98, 118}, ++{201, 93, 122}, ++{211, 87, 125}, ++{222, 81, 129}, ++{233, 75, 133}, ++{242, 70, 136}, ++{184, 106, 115}, ++{188, 103, 116}, ++{195, 99, 119}, ++{204, 94, 122}, ++{214, 88, 126}, ++{224, 82, 130}, ++{236, 76, 133}, ++{244, 71, 136}, ++{186, 107, 115}, ++{190, 104, 117}, ++{197, 99, 120}, ++{205, 94, 123}, ++{215, 88, 126}, ++{226, 82, 130}, ++{237, 76, 134}, ++{245, 72, 137}, ++{186, 107, 115}, ++{190, 104, 117}, ++{197, 99, 120}, ++{205, 94, 123}, ++{215, 88, 126}, ++{226, 82, 130}, ++{237, 76, 134}, ++{245, 72, 137}, ++{186, 107, 115}, ++{190, 104, 117}, ++{197, 99, 120}, ++{205, 94, 123}, ++{215, 88, 126}, ++{226, 82, 130}, ++{237, 76, 134}, ++{245, 72, 137}, ++{186, 107, 115}, ++{190, 104, 117}, ++{197, 99, 120}, ++{205, 94, 123}, ++{215, 88, 126}, ++{226, 82, 130}, ++{237, 76, 134}, ++{245, 72, 137}, ++{117, 72, 89}, ++{125, 72, 93}, ++{138, 71, 99}, ++{152, 68, 106}, ++{166, 65, 112}, ++{181, 61, 118}, ++{196, 57, 124}, ++{207, 53, 128}, ++{118, 72, 89}, ++{126, 72, 93}, ++{138, 71, 99}, ++{152, 69, 106}, ++{166, 65, 112}, ++{181, 61, 118}, ++{196, 57, 124}, ++{207, 53, 128}, ++{118, 72, 89}, ++{126, 72, 93}, ++{138, 71, 99}, ++{152, 69, 106}, ++{167, 65, 112}, ++{181, 61, 118}, ++{196, 57, 124}, ++{207, 53, 128}, ++{119, 73, 90}, ++{127, 73, 94}, ++{139, 72, 100}, ++{153, 69, 106}, ++{167, 66, 112}, ++{182, 62, 118}, ++{197, 57, 124}, ++{208, 54, 128}, ++{120, 74, 90}, ++{128, 74, 94}, ++{140, 72, 100}, ++{154, 70, 106}, ++{168, 66, 113}, ++{183, 62, 118}, ++{197, 57, 124}, ++{208, 54, 128}, ++{122, 75, 91}, ++{129, 75, 95}, ++{141, 73, 100}, ++{155, 70, 107}, ++{169, 67, 113}, ++{183, 62, 119}, ++{198, 58, 124}, ++{209, 54, 128}, ++{124, 77, 92}, ++{131, 76, 95}, ++{142, 74, 101}, ++{156, 71, 107}, ++{170, 67, 113}, ++{184, 63, 119}, ++{199, 58, 124}, ++{209, 55, 128}, ++{125, 78, 92}, ++{132, 77, 96}, ++{144, 75, 101}, ++{157, 72, 107}, ++{171, 68, 113}, ++{185, 63, 119}, ++{200, 59, 125}, ++{210, 55, 128}, ++{127, 80, 93}, ++{134, 79, 97}, ++{146, 76, 102}, ++{159, 73, 108}, ++{172, 69, 114}, ++{186, 64, 119}, ++{201, 59, 125}, ++{211, 56, 129}, ++{130, 81, 94}, ++{136, 80, 98}, ++{147, 77, 103}, ++{160, 74, 108}, ++{174, 69, 114}, ++{188, 65, 120}, ++{202, 60, 125}, ++{212, 56, 129}, ++{132, 83, 95}, ++{139, 81, 98}, ++{149, 79, 103}, ++{162, 75, 109}, ++{175, 70, 115}, ++{189, 65, 120}, ++{203, 60, 125}, ++{214, 57, 129}, ++{135, 85, 96}, ++{141, 83, 99}, ++{151, 80, 104}, ++{164, 76, 110}, ++{177, 71, 115}, ++{191, 66, 120}, ++{205, 61, 126}, ++{215, 57, 129}, ++{137, 86, 97}, ++{144, 84, 100}, ++{154, 81, 105}, ++{166, 77, 110}, ++{179, 72, 116}, ++{192, 67, 121}, ++{206, 62, 126}, ++{216, 58, 129}, ++{140, 88, 98}, ++{146, 86, 101}, ++{156, 82, 106}, ++{168, 78, 111}, ++{181, 73, 116}, ++{194, 68, 121}, ++{208, 63, 126}, ++{218, 59, 130}, ++{143, 89, 99}, ++{149, 87, 102}, ++{158, 83, 106}, ++{170, 79, 111}, ++{183, 74, 117}, ++{196, 69, 122}, ++{209, 63, 127}, ++{219, 59, 130}, ++{146, 91, 101}, ++{152, 89, 103}, ++{161, 85, 107}, ++{172, 80, 112}, ++{185, 75, 117}, ++{198, 70, 122}, ++{211, 64, 127}, ++{221, 60, 130}, ++{149, 92, 102}, ++{154, 90, 104}, ++{164, 86, 108}, ++{175, 81, 113}, ++{187, 76, 118}, ++{200, 71, 123}, ++{213, 65, 127}, ++{223, 61, 131}, ++{152, 94, 103}, ++{157, 91, 105}, ++{166, 87, 109}, ++{177, 82, 113}, ++{189, 77, 118}, ++{202, 71, 123}, ++{215, 66, 128}, ++{224, 62, 131}, ++{155, 95, 104}, ++{160, 92, 106}, ++{169, 88, 110}, ++{180, 83, 114}, ++{192, 78, 119}, ++{204, 72, 123}, ++{217, 67, 128}, ++{226, 63, 131}, ++{158, 96, 105}, ++{164, 94, 107}, ++{172, 89, 111}, ++{182, 84, 115}, ++{194, 79, 119}, ++{206, 73, 124}, ++{219, 68, 128}, ++{228, 63, 132}, ++{162, 97, 106}, ++{167, 95, 108}, ++{175, 91, 111}, ++{185, 85, 116}, ++{196, 80, 120}, ++{208, 74, 124}, ++{221, 69, 129}, ++{230, 64, 132}, ++{165, 99, 107}, ++{170, 96, 109}, ++{178, 92, 112}, ++{188, 87, 116}, ++{199, 81, 121}, ++{211, 75, 125}, ++{223, 69, 129}, ++{232, 65, 132}, ++{168, 100, 108}, ++{173, 97, 110}, ++{181, 93, 113}, ++{191, 88, 117}, ++{202, 82, 121}, ++{213, 76, 125}, ++{225, 70, 130}, ++{234, 66, 133}, ++{172, 101, 109}, ++{176, 98, 111}, ++{184, 94, 114}, ++{193, 89, 118}, ++{204, 83, 122}, ++{216, 77, 126}, ++{227, 71, 130}, ++{236, 67, 133}, ++{175, 102, 110}, ++{180, 99, 112}, ++{187, 95, 115}, ++{196, 90, 118}, ++{207, 84, 122}, ++{218, 78, 126}, ++{230, 72, 130}, ++{239, 68, 133}, ++{179, 103, 111}, ++{183, 100, 113}, ++{190, 96, 116}, ++{199, 90, 119}, ++{210, 85, 123}, ++{221, 79, 127}, ++{232, 73, 131}, ++{241, 69, 134}, ++{182, 104, 112}, ++{186, 101, 114}, ++{193, 97, 116}, ++{202, 91, 120}, ++{212, 86, 124}, ++{223, 80, 127}, ++{235, 74, 131}, ++{243, 69, 134}, ++{186, 104, 113}, ++{190, 102, 115}, ++{197, 98, 117}, ++{205, 92, 121}, ++{215, 87, 124}, ++{226, 81, 128}, ++{237, 75, 132}, ++{246, 70, 135}, ++{187, 105, 113}, ++{191, 102, 115}, ++{198, 98, 118}, ++{207, 93, 121}, ++{217, 87, 124}, ++{227, 81, 128}, ++{238, 75, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 102, 115}, ++{198, 98, 118}, ++{207, 93, 121}, ++{217, 87, 124}, ++{227, 81, 128}, ++{238, 75, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 102, 115}, ++{198, 98, 118}, ++{207, 93, 121}, ++{217, 87, 124}, ++{227, 81, 128}, ++{238, 75, 132}, ++{247, 71, 135}, ++{187, 105, 113}, ++{191, 102, 115}, ++{198, 98, 118}, ++{207, 93, 121}, ++{217, 87, 124}, ++{227, 81, 128}, ++{238, 75, 132}, ++{247, 71, 135}, ++{120, 69, 87}, ++{128, 69, 91}, ++{140, 69, 97}, ++{154, 67, 103}, ++{168, 64, 110}, ++{183, 60, 116}, ++{198, 56, 122}, ++{208, 52, 126}, ++{121, 69, 87}, ++{128, 70, 91}, ++{140, 69, 97}, ++{154, 67, 103}, ++{168, 64, 110}, ++{183, 60, 116}, ++{198, 56, 122}, ++{209, 52, 126}, ++{121, 70, 87}, ++{129, 70, 91}, ++{141, 69, 97}, ++{154, 67, 104}, ++{169, 64, 110}, ++{183, 60, 116}, ++{198, 56, 122}, ++{209, 52, 126}, ++{122, 71, 88}, ++{130, 71, 91}, ++{141, 70, 97}, ++{155, 67, 104}, ++{169, 64, 110}, ++{184, 60, 116}, ++{198, 56, 122}, ++{209, 53, 126}, ++{123, 72, 88}, ++{131, 72, 92}, ++{142, 70, 98}, ++{156, 68, 104}, ++{170, 65, 110}, ++{184, 61, 116}, ++{199, 56, 122}, ++{210, 53, 126}, ++{125, 73, 89}, ++{132, 73, 92}, ++{143, 71, 98}, ++{157, 69, 104}, ++{171, 65, 111}, ++{185, 61, 117}, ++{200, 57, 122}, ++{210, 53, 126}, ++{126, 74, 89}, ++{133, 74, 93}, ++{145, 72, 99}, ++{158, 69, 105}, ++{172, 66, 111}, ++{186, 62, 117}, ++{200, 57, 122}, ++{211, 54, 126}, ++{128, 76, 90}, ++{135, 75, 94}, ++{146, 73, 99}, ++{159, 70, 105}, ++{173, 66, 111}, ++{187, 62, 117}, ++{201, 58, 122}, ++{212, 54, 126}, ++{130, 77, 91}, ++{137, 76, 95}, ++{148, 74, 100}, ++{161, 71, 106}, ++{174, 67, 112}, ++{188, 63, 117}, ++{202, 58, 123}, ++{213, 55, 127}, ++{132, 79, 92}, ++{139, 78, 95}, ++{150, 75, 101}, ++{162, 72, 106}, ++{176, 68, 112}, ++{190, 63, 118}, ++{204, 59, 123}, ++{214, 55, 127}, ++{135, 81, 93}, ++{141, 79, 96}, ++{152, 77, 101}, ++{164, 73, 107}, ++{177, 69, 112}, ++{191, 64, 118}, ++{205, 59, 123}, ++{215, 56, 127}, ++{137, 82, 94}, ++{143, 81, 97}, ++{154, 78, 102}, ++{166, 74, 107}, ++{179, 70, 113}, ++{192, 65, 118}, ++{206, 60, 124}, ++{216, 56, 127}, ++{140, 84, 95}, ++{146, 82, 98}, ++{156, 79, 103}, ++{168, 75, 108}, ++{181, 71, 113}, ++{194, 66, 119}, ++{208, 61, 124}, ++{218, 57, 128}, ++{143, 85, 96}, ++{148, 84, 99}, ++{158, 80, 104}, ++{170, 76, 109}, ++{183, 72, 114}, ++{196, 67, 119}, ++{209, 62, 124}, ++{219, 58, 128}, ++{145, 87, 97}, ++{151, 85, 100}, ++{161, 82, 104}, ++{172, 77, 109}, ++{185, 73, 115}, ++{198, 68, 120}, ++{211, 62, 125}, ++{221, 58, 128}, ++{148, 89, 98}, ++{154, 86, 101}, ++{163, 83, 105}, ++{174, 78, 110}, ++{187, 74, 115}, ++{199, 68, 120}, ++{212, 63, 125}, ++{222, 59, 128}, ++{151, 90, 100}, ++{157, 88, 102}, ++{166, 84, 106}, ++{177, 80, 111}, ++{189, 75, 116}, ++{201, 69, 121}, ++{214, 64, 125}, ++{224, 60, 129}, ++{154, 91, 101}, ++{160, 89, 103}, ++{168, 85, 107}, ++{179, 81, 111}, ++{191, 76, 116}, ++{203, 70, 121}, ++{216, 65, 126}, ++{226, 61, 129}, ++{157, 93, 102}, ++{163, 90, 104}, ++{171, 87, 108}, ++{182, 82, 112}, ++{193, 77, 117}, ++{206, 71, 121}, ++{218, 66, 126}, ++{228, 62, 129}, ++{161, 94, 103}, ++{166, 92, 105}, ++{174, 88, 109}, ++{184, 83, 113}, ++{196, 78, 117}, ++{208, 72, 122}, ++{220, 67, 126}, ++{230, 62, 130}, ++{164, 95, 104}, ++{169, 93, 106}, ++{177, 89, 109}, ++{187, 84, 114}, ++{198, 79, 118}, ++{210, 73, 122}, ++{222, 68, 127}, ++{232, 63, 130}, ++{167, 97, 105}, ++{172, 94, 107}, ++{180, 90, 110}, ++{190, 85, 114}, ++{201, 80, 119}, ++{212, 74, 123}, ++{224, 68, 127}, ++{234, 64, 131}, ++{170, 98, 106}, ++{175, 95, 108}, ++{183, 91, 111}, ++{192, 86, 115}, ++{203, 81, 119}, ++{215, 75, 124}, ++{227, 69, 128}, ++{236, 65, 131}, ++{174, 99, 107}, ++{178, 96, 109}, ++{186, 92, 112}, ++{195, 87, 116}, ++{206, 82, 120}, ++{217, 76, 124}, ++{229, 70, 128}, ++{238, 66, 131}, ++{177, 100, 108}, ++{181, 97, 110}, ++{189, 93, 113}, ++{198, 88, 117}, ++{208, 83, 120}, ++{220, 77, 125}, ++{231, 71, 129}, ++{240, 67, 132}, ++{180, 101, 109}, ++{185, 98, 111}, ++{192, 94, 114}, ++{201, 89, 117}, ++{211, 84, 121}, ++{222, 78, 125}, ++{233, 72, 129}, ++{242, 68, 132}, ++{184, 102, 110}, ++{188, 99, 112}, ++{195, 95, 115}, ++{204, 90, 118}, ++{214, 84, 122}, ++{225, 79, 126}, ++{236, 73, 130}, ++{245, 68, 132}, ++{187, 103, 111}, ++{191, 100, 113}, ++{198, 96, 115}, ++{207, 91, 119}, ++{217, 85, 122}, ++{227, 80, 126}, ++{238, 74, 130}, ++{247, 69, 133}, ++{189, 103, 111}, ++{193, 101, 113}, ++{200, 97, 116}, ++{208, 91, 119}, ++{218, 86, 123}, ++{229, 80, 126}, ++{240, 74, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{193, 101, 113}, ++{200, 97, 116}, ++{208, 91, 119}, ++{218, 86, 123}, ++{229, 80, 126}, ++{240, 74, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{193, 101, 113}, ++{200, 97, 116}, ++{208, 91, 119}, ++{218, 86, 123}, ++{229, 80, 126}, ++{240, 74, 130}, ++{248, 70, 133}, ++{189, 103, 111}, ++{193, 101, 113}, ++{200, 97, 116}, ++{208, 91, 119}, ++{218, 86, 123}, ++{229, 80, 126}, ++{240, 74, 130}, ++{248, 70, 133}, ++{123, 66, 85}, ++{131, 67, 89}, ++{143, 67, 95}, ++{156, 65, 101}, ++{170, 62, 108}, ++{185, 58, 114}, ++{199, 54, 120}, ++{210, 51, 124}, ++{124, 67, 85}, ++{131, 67, 89}, ++{143, 67, 95}, ++{156, 65, 101}, ++{170, 62, 108}, ++{185, 58, 114}, ++{199, 54, 120}, ++{210, 51, 124}, ++{124, 67, 85}, ++{131, 68, 89}, ++{143, 67, 95}, ++{157, 65, 101}, ++{171, 62, 108}, ++{185, 59, 114}, ++{200, 55, 120}, ++{210, 51, 124}, ++{125, 68, 86}, ++{132, 68, 89}, ++{144, 68, 95}, ++{157, 66, 102}, ++{171, 63, 108}, ++{186, 59, 114}, ++{200, 55, 120}, ++{211, 52, 124}, ++{126, 69, 86}, ++{133, 69, 90}, ++{145, 68, 96}, ++{158, 66, 102}, ++{172, 63, 108}, ++{186, 59, 114}, ++{201, 55, 120}, ++{211, 52, 124}, ++{127, 70, 87}, ++{134, 70, 90}, ++{146, 69, 96}, ++{159, 67, 102}, ++{173, 64, 108}, ++{187, 60, 114}, ++{201, 55, 120}, ++{212, 52, 124}, ++{129, 72, 87}, ++{136, 71, 91}, ++{147, 70, 97}, ++{160, 68, 103}, ++{174, 64, 109}, ++{188, 60, 115}, ++{202, 56, 120}, ++{213, 53, 124}, ++{131, 73, 88}, ++{138, 73, 92}, ++{149, 71, 97}, ++{161, 68, 103}, ++{175, 65, 109}, ++{189, 61, 115}, ++{203, 56, 120}, ++{214, 53, 124}, ++{133, 75, 89}, ++{139, 74, 93}, ++{150, 72, 98}, ++{163, 69, 104}, ++{176, 66, 110}, ++{190, 61, 115}, ++{204, 57, 121}, ++{215, 54, 125}, ++{135, 76, 90}, ++{141, 75, 93}, ++{152, 73, 98}, ++{164, 70, 104}, ++{178, 66, 110}, ++{191, 62, 116}, ++{205, 58, 121}, ++{216, 54, 125}, ++{137, 78, 91}, ++{144, 77, 94}, ++{154, 75, 99}, ++{166, 71, 105}, ++{179, 67, 110}, ++{193, 63, 116}, ++{206, 58, 121}, ++{217, 55, 125}, ++{140, 80, 92}, ++{146, 78, 95}, ++{156, 76, 100}, ++{168, 72, 105}, ++{181, 68, 111}, ++{194, 64, 116}, ++{208, 59, 122}, ++{218, 55, 125}, ++{142, 81, 93}, ++{148, 80, 96}, ++{158, 77, 101}, ++{170, 73, 106}, ++{183, 69, 111}, ++{196, 65, 117}, ++{209, 60, 122}, ++{219, 56, 126}, ++{145, 83, 94}, ++{151, 81, 97}, ++{160, 78, 101}, ++{172, 75, 107}, ++{184, 70, 112}, ++{197, 65, 117}, ++{211, 60, 122}, ++{221, 57, 126}, ++{148, 85, 95}, ++{153, 83, 98}, ++{163, 80, 102}, ++{174, 76, 107}, ++{186, 71, 112}, ++{199, 66, 118}, ++{212, 61, 123}, ++{222, 57, 126}, ++{151, 86, 96}, ++{156, 84, 99}, ++{165, 81, 103}, ++{176, 77, 108}, ++{188, 72, 113}, ++{201, 67, 118}, ++{214, 62, 123}, ++{224, 58, 127}, ++{153, 88, 97}, ++{159, 86, 100}, ++{168, 82, 104}, ++{179, 78, 109}, ++{191, 73, 114}, ++{203, 68, 119}, ++{216, 63, 123}, ++{226, 59, 127}, ++{156, 89, 99}, ++{162, 87, 101}, ++{170, 83, 105}, ++{181, 79, 109}, ++{193, 74, 114}, ++{205, 69, 119}, ++{218, 64, 124}, ++{227, 60, 127}, ++{160, 91, 100}, ++{165, 88, 102}, ++{173, 85, 106}, ++{184, 80, 110}, ++{195, 75, 115}, ++{207, 70, 120}, ++{220, 65, 124}, ++{229, 61, 128}, ++{163, 92, 101}, ++{168, 90, 103}, ++{176, 86, 107}, ++{186, 81, 111}, ++{197, 76, 115}, ++{209, 71, 120}, ++{222, 66, 125}, ++{231, 61, 128}, ++{166, 93, 102}, ++{171, 91, 104}, ++{179, 87, 107}, ++{189, 82, 112}, ++{200, 77, 116}, ++{212, 72, 121}, ++{224, 66, 125}, ++{233, 62, 128}, ++{169, 95, 103}, ++{174, 92, 105}, ++{182, 88, 108}, ++{191, 83, 112}, ++{202, 78, 117}, ++{214, 73, 121}, ++{226, 67, 125}, ++{235, 63, 129}, ++{172, 96, 104}, ++{177, 93, 106}, ++{185, 89, 109}, ++{194, 85, 113}, ++{205, 79, 117}, ++{216, 74, 122}, ++{228, 68, 126}, ++{237, 64, 129}, ++{176, 97, 105}, ++{180, 95, 107}, ++{188, 90, 110}, ++{197, 86, 114}, ++{207, 80, 118}, ++{219, 75, 122}, ++{230, 69, 126}, ++{239, 65, 130}, ++{179, 98, 106}, ++{183, 96, 108}, ++{191, 92, 111}, ++{200, 87, 115}, ++{210, 81, 119}, ++{221, 76, 123}, ++{233, 70, 127}, ++{241, 66, 130}, ++{182, 99, 107}, ++{187, 97, 109}, ++{194, 93, 112}, ++{203, 88, 115}, ++{213, 82, 119}, ++{224, 77, 123}, ++{235, 71, 127}, ++{244, 67, 130}, ++{186, 100, 108}, ++{190, 98, 110}, ++{197, 94, 113}, ++{206, 89, 116}, ++{215, 83, 120}, ++{226, 78, 124}, ++{237, 72, 128}, ++{246, 68, 131}, ++{189, 101, 109}, ++{193, 99, 111}, ++{200, 95, 113}, ++{209, 90, 117}, ++{218, 84, 121}, ++{229, 78, 124}, ++{240, 73, 128}, ++{248, 68, 131}, ++{191, 102, 110}, ++{195, 99, 111}, ++{202, 95, 114}, ++{210, 90, 117}, ++{220, 85, 121}, ++{230, 79, 125}, ++{241, 73, 129}, ++{249, 69, 131}, ++{191, 102, 110}, ++{195, 99, 111}, ++{202, 95, 114}, ++{210, 90, 117}, ++{220, 85, 121}, ++{230, 79, 125}, ++{241, 73, 129}, ++{249, 69, 131}, ++{191, 102, 110}, ++{195, 99, 111}, ++{202, 95, 114}, ++{210, 90, 117}, ++{220, 85, 121}, ++{230, 79, 125}, ++{241, 73, 129}, ++{249, 69, 131}, ++{191, 102, 110}, ++{195, 99, 111}, ++{202, 95, 114}, ++{210, 90, 117}, ++{220, 85, 121}, ++{230, 79, 125}, ++{241, 73, 129}, ++{249, 69, 131}, ++{126, 64, 83}, ++{133, 65, 87}, ++{145, 65, 93}, ++{158, 63, 99}, ++{172, 60, 106}, ++{187, 57, 112}, ++{201, 53, 117}, ++{212, 50, 122}, ++{126, 64, 83}, ++{134, 65, 87}, ++{145, 65, 93}, ++{158, 63, 99}, ++{172, 60, 106}, ++{187, 57, 112}, ++{201, 53, 118}, ++{212, 50, 122}, ++{127, 65, 83}, ++{134, 65, 87}, ++{146, 65, 93}, ++{159, 63, 99}, ++{173, 61, 106}, ++{187, 57, 112}, ++{201, 53, 118}, ++{212, 50, 122}, ++{128, 66, 84}, ++{135, 66, 87}, ++{146, 66, 93}, ++{159, 64, 100}, ++{173, 61, 106}, ++{188, 58, 112}, ++{202, 54, 118}, ++{212, 50, 122}, ++{129, 67, 84}, ++{136, 67, 88}, ++{147, 66, 94}, ++{160, 64, 100}, ++{174, 61, 106}, ++{188, 58, 112}, ++{202, 54, 118}, ++{213, 51, 122}, ++{130, 68, 85}, ++{137, 68, 88}, ++{148, 67, 94}, ++{161, 65, 100}, ++{175, 62, 106}, ++{189, 58, 112}, ++{203, 54, 118}, ++{214, 51, 122}, ++{132, 69, 85}, ++{139, 69, 89}, ++{149, 68, 95}, ++{162, 66, 101}, ++{176, 63, 107}, ++{190, 59, 113}, ++{204, 55, 118}, ++{214, 51, 122}, ++{134, 71, 86}, ++{140, 70, 90}, ++{151, 69, 95}, ++{163, 67, 101}, ++{177, 63, 107}, ++{191, 59, 113}, ++{205, 55, 118}, ++{215, 52, 122}, ++{135, 72, 87}, ++{142, 72, 90}, ++{152, 70, 96}, ++{165, 67, 102}, ++{178, 64, 107}, ++{192, 60, 113}, ++{206, 56, 119}, ++{216, 52, 123}, ++{138, 74, 88}, ++{144, 73, 91}, ++{154, 71, 96}, ++{166, 68, 102}, ++{180, 65, 108}, ++{193, 61, 114}, ++{207, 56, 119}, ++{217, 53, 123}, ++{140, 76, 89}, ++{146, 75, 92}, ++{156, 73, 97}, ++{168, 69, 103}, ++{181, 66, 108}, ++{195, 62, 114}, ++{208, 57, 119}, ++{218, 54, 123}, ++{142, 77, 90}, ++{148, 76, 93}, ++{158, 74, 98}, ++{170, 71, 103}, ++{183, 67, 109}, ++{196, 62, 114}, ++{209, 58, 120}, ++{220, 54, 123}, ++{145, 79, 91}, ++{151, 78, 94}, ++{160, 75, 99}, ++{172, 72, 104}, ++{184, 68, 109}, ++{198, 63, 115}, ++{211, 59, 120}, ++{221, 55, 124}, ++{147, 81, 92}, ++{153, 79, 95}, ++{163, 76, 99}, ++{174, 73, 105}, ++{186, 69, 110}, ++{199, 64, 115}, ++{212, 59, 120}, ++{222, 56, 124}, ++{150, 82, 93}, ++{156, 81, 96}, ++{165, 78, 100}, ++{176, 74, 105}, ++{188, 70, 110}, ++{201, 65, 116}, ++{214, 60, 121}, ++{224, 56, 124}, ++{153, 84, 94}, ++{158, 82, 97}, ++{167, 79, 101}, ++{178, 75, 106}, ++{190, 71, 111}, ++{203, 66, 116}, ++{216, 61, 121}, ++{225, 57, 125}, ++{156, 86, 95}, ++{161, 84, 98}, ++{170, 80, 102}, ++{181, 76, 107}, ++{192, 72, 112}, ++{205, 67, 117}, ++{217, 62, 121}, ++{227, 58, 125}, ++{159, 87, 97}, ++{164, 85, 99}, ++{172, 82, 103}, ++{183, 77, 107}, ++{195, 73, 112}, ++{207, 68, 117}, ++{219, 63, 122}, ++{229, 59, 125}, ++{162, 89, 98}, ++{167, 86, 100}, ++{175, 83, 104}, ++{185, 79, 108}, ++{197, 74, 113}, ++{209, 69, 118}, ++{221, 64, 122}, ++{231, 60, 126}, ++{165, 90, 99}, ++{170, 88, 101}, ++{178, 84, 105}, ++{188, 80, 109}, ++{199, 75, 113}, ++{211, 70, 118}, ++{223, 64, 123}, ++{233, 60, 126}, ++{168, 91, 100}, ++{173, 89, 102}, ++{181, 85, 105}, ++{191, 81, 110}, ++{202, 76, 114}, ++{213, 71, 119}, ++{225, 65, 123}, ++{234, 61, 127}, ++{171, 93, 101}, ++{176, 90, 103}, ++{184, 87, 106}, ++{193, 82, 110}, ++{204, 77, 115}, ++{215, 72, 119}, ++{227, 66, 124}, ++{236, 62, 127}, ++{174, 94, 102}, ++{179, 92, 104}, ++{186, 88, 107}, ++{196, 83, 111}, ++{206, 78, 115}, ++{218, 73, 120}, ++{230, 67, 124}, ++{239, 63, 127}, ++{178, 95, 103}, ++{182, 93, 105}, ++{189, 89, 108}, ++{199, 84, 112}, ++{209, 79, 116}, ++{220, 74, 120}, ++{232, 68, 125}, ++{241, 64, 128}, ++{181, 96, 104}, ++{185, 94, 106}, ++{192, 90, 109}, ++{201, 85, 113}, ++{212, 80, 117}, ++{223, 75, 121}, ++{234, 69, 125}, ++{243, 65, 128}, ++{184, 97, 105}, ++{188, 95, 107}, ++{195, 91, 110}, ++{204, 86, 113}, ++{214, 81, 117}, ++{225, 75, 121}, ++{236, 70, 126}, ++{245, 66, 129}, ++{188, 98, 106}, ++{192, 96, 108}, ++{199, 92, 111}, ++{207, 87, 114}, ++{217, 82, 118}, ++{228, 76, 122}, ++{239, 71, 126}, ++{247, 67, 129}, ++{191, 99, 107}, ++{195, 97, 109}, ++{202, 93, 112}, ++{210, 88, 115}, ++{220, 83, 119}, ++{230, 77, 123}, ++{241, 72, 127}, ++{250, 67, 129}, ++{193, 100, 108}, ++{197, 97, 109}, ++{203, 93, 112}, ++{212, 89, 115}, ++{221, 83, 119}, ++{232, 78, 123}, ++{242, 72, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 109}, ++{203, 93, 112}, ++{212, 89, 115}, ++{221, 83, 119}, ++{232, 78, 123}, ++{242, 72, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 109}, ++{203, 93, 112}, ++{212, 89, 115}, ++{221, 83, 119}, ++{232, 78, 123}, ++{242, 72, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 109}, ++{203, 93, 112}, ++{212, 89, 115}, ++{221, 83, 119}, ++{232, 78, 123}, ++{242, 72, 127}, ++{251, 68, 130}, ++{129, 61, 81}, ++{136, 62, 85}, ++{147, 62, 91}, ++{161, 61, 97}, ++{174, 59, 103}, ++{189, 56, 110}, ++{203, 52, 115}, ++{213, 49, 120}, ++{129, 62, 81}, ++{136, 62, 85}, ++{148, 63, 91}, ++{161, 61, 97}, ++{175, 59, 104}, ++{189, 56, 110}, ++{203, 52, 115}, ++{213, 49, 120}, ++{130, 62, 81}, ++{137, 63, 85}, ++{148, 63, 91}, ++{161, 62, 97}, ++{175, 59, 104}, ++{189, 56, 110}, ++{203, 52, 116}, ++{214, 49, 120}, ++{131, 63, 82}, ++{138, 64, 85}, ++{149, 63, 91}, ++{162, 62, 97}, ++{175, 59, 104}, ++{189, 56, 110}, ++{204, 52, 116}, ++{214, 49, 120}, ++{132, 64, 82}, ++{139, 64, 86}, ++{150, 64, 92}, ++{162, 62, 98}, ++{176, 60, 104}, ++{190, 57, 110}, ++{204, 53, 116}, ++{215, 50, 120}, ++{133, 65, 83}, ++{140, 66, 86}, ++{151, 65, 92}, ++{163, 63, 98}, ++{177, 60, 104}, ++{191, 57, 110}, ++{205, 53, 116}, ++{215, 50, 120}, ++{134, 67, 83}, ++{141, 67, 87}, ++{152, 66, 92}, ++{164, 64, 98}, ++{178, 61, 105}, ++{192, 57, 111}, ++{206, 54, 116}, ++{216, 50, 120}, ++{136, 68, 84}, ++{143, 68, 88}, ++{153, 67, 93}, ++{166, 65, 99}, ++{179, 62, 105}, ++{193, 58, 111}, ++{206, 54, 116}, ++{217, 51, 120}, ++{138, 70, 85}, ++{144, 69, 88}, ++{155, 68, 94}, ++{167, 66, 99}, ++{180, 62, 105}, ++{194, 59, 111}, ++{207, 55, 117}, ++{218, 51, 121}, ++{140, 72, 86}, ++{146, 71, 89}, ++{157, 69, 94}, ++{169, 67, 100}, ++{182, 63, 106}, ++{195, 59, 111}, ++{209, 55, 117}, ++{219, 52, 121}, ++{142, 73, 87}, ++{148, 72, 90}, ++{158, 70, 95}, ++{170, 68, 101}, ++{183, 64, 106}, ++{196, 60, 112}, ++{210, 56, 117}, ++{220, 53, 121}, ++{145, 75, 88}, ++{151, 74, 91}, ++{160, 72, 96}, ++{172, 69, 101}, ++{185, 65, 107}, ++{198, 61, 112}, ++{211, 57, 118}, ++{221, 53, 121}, ++{147, 77, 89}, ++{153, 75, 92}, ++{162, 73, 97}, ++{174, 70, 102}, ++{186, 66, 107}, ++{199, 62, 113}, ++{213, 57, 118}, ++{223, 54, 122}, ++{150, 78, 90}, ++{155, 77, 93}, ++{165, 74, 97}, ++{176, 71, 103}, ++{188, 67, 108}, ++{201, 63, 113}, ++{214, 58, 118}, ++{224, 55, 122}, ++{152, 80, 91}, ++{158, 79, 94}, ++{167, 76, 98}, ++{178, 72, 103}, ++{190, 68, 108}, ++{203, 64, 114}, ++{216, 59, 119}, ++{225, 55, 122}, ++{155, 82, 92}, ++{161, 80, 95}, ++{169, 77, 99}, ++{180, 73, 104}, ++{192, 69, 109}, ++{205, 65, 114}, ++{217, 60, 119}, ++{227, 56, 123}, ++{158, 83, 93}, ++{163, 82, 96}, ++{172, 78, 100}, ++{183, 75, 105}, ++{194, 70, 110}, ++{206, 65, 115}, ++{219, 61, 120}, ++{229, 57, 123}, ++{161, 85, 95}, ++{166, 83, 97}, ++{174, 80, 101}, ++{185, 76, 105}, ++{196, 71, 110}, ++{208, 66, 115}, ++{221, 62, 120}, ++{230, 58, 123}, ++{164, 86, 96}, ++{169, 84, 98}, ++{177, 81, 102}, ++{187, 77, 106}, ++{199, 72, 111}, ++{210, 67, 116}, ++{223, 62, 120}, ++{232, 59, 124}, ++{167, 88, 97}, ++{172, 86, 99}, ++{180, 82, 103}, ++{190, 78, 107}, ++{201, 73, 112}, ++{213, 68, 116}, ++{225, 63, 121}, ++{234, 59, 124}, ++{170, 89, 98}, ++{175, 87, 100}, ++{183, 84, 104}, ++{192, 79, 108}, ++{203, 74, 112}, ++{215, 69, 117}, ++{227, 64, 121}, ++{236, 60, 125}, ++{173, 91, 99}, ++{178, 88, 101}, ++{185, 85, 104}, ++{195, 80, 108}, ++{206, 75, 113}, ++{217, 70, 117}, ++{229, 65, 122}, ++{238, 61, 125}, ++{176, 92, 100}, ++{181, 90, 102}, ++{188, 86, 105}, ++{198, 81, 109}, ++{208, 77, 114}, ++{219, 71, 118}, ++{231, 66, 122}, ++{240, 62, 126}, ++{180, 93, 101}, ++{184, 91, 103}, ++{191, 87, 106}, ++{200, 83, 110}, ++{211, 78, 114}, ++{222, 72, 118}, ++{233, 67, 123}, ++{242, 63, 126}, ++{183, 94, 102}, ++{187, 92, 104}, ++{194, 88, 107}, ++{203, 84, 111}, ++{213, 79, 115}, ++{224, 73, 119}, ++{236, 68, 123}, ++{244, 64, 126}, ++{186, 95, 103}, ++{190, 93, 105}, ++{197, 89, 108}, ++{206, 85, 112}, ++{216, 80, 116}, ++{227, 74, 120}, ++{238, 69, 124}, ++{246, 65, 127}, ++{189, 96, 104}, ++{193, 94, 106}, ++{200, 90, 109}, ++{209, 86, 112}, ++{219, 81, 116}, ++{229, 75, 120}, ++{240, 70, 124}, ++{249, 66, 127}, ++{193, 97, 105}, ++{197, 95, 107}, ++{203, 91, 110}, ++{212, 87, 113}, ++{221, 82, 117}, ++{232, 76, 121}, ++{243, 71, 125}, ++{251, 66, 128}, ++{195, 98, 106}, ++{198, 96, 107}, ++{205, 92, 110}, ++{213, 87, 114}, ++{223, 82, 117}, ++{233, 77, 121}, ++{244, 71, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{198, 96, 107}, ++{205, 92, 110}, ++{213, 87, 114}, ++{223, 82, 117}, ++{233, 77, 121}, ++{244, 71, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{198, 96, 107}, ++{205, 92, 110}, ++{213, 87, 114}, ++{223, 82, 117}, ++{233, 77, 121}, ++{244, 71, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{198, 96, 107}, ++{205, 92, 110}, ++{213, 87, 114}, ++{223, 82, 117}, ++{233, 77, 121}, ++{244, 71, 125}, ++{252, 67, 128}, ++{132, 59, 79}, ++{139, 60, 83}, ++{150, 60, 89}, ++{163, 59, 95}, ++{176, 57, 101}, ++{190, 54, 108}, ++{205, 51, 113}, ++{215, 48, 118}, ++{132, 59, 79}, ++{139, 60, 83}, ++{150, 60, 89}, ++{163, 59, 95}, ++{177, 57, 101}, ++{191, 54, 108}, ++{205, 51, 113}, ++{215, 48, 118}, ++{133, 60, 79}, ++{139, 61, 83}, ++{150, 61, 89}, ++{163, 60, 95}, ++{177, 57, 102}, ++{191, 54, 108}, ++{205, 51, 114}, ++{215, 48, 118}, ++{133, 61, 80}, ++{140, 61, 83}, ++{151, 61, 89}, ++{164, 60, 95}, ++{177, 58, 102}, ++{191, 55, 108}, ++{205, 51, 114}, ++{216, 48, 118}, ++{134, 62, 80}, ++{141, 62, 84}, ++{152, 62, 89}, ++{165, 61, 96}, ++{178, 58, 102}, ++{192, 55, 108}, ++{206, 51, 114}, ++{216, 48, 118}, ++{136, 63, 81}, ++{142, 63, 84}, ++{153, 63, 90}, ++{166, 61, 96}, ++{179, 59, 102}, ++{193, 56, 108}, ++{207, 52, 114}, ++{217, 49, 118}, ++{137, 64, 82}, ++{144, 64, 85}, ++{154, 64, 90}, ++{167, 62, 96}, ++{180, 59, 103}, ++{194, 56, 108}, ++{207, 52, 114}, ++{218, 49, 118}, ++{139, 66, 82}, ++{145, 66, 86}, ++{156, 65, 91}, ++{168, 63, 97}, ++{181, 60, 103}, ++{194, 57, 109}, ++{208, 53, 114}, ++{218, 50, 118}, ++{141, 67, 83}, ++{147, 67, 86}, ++{157, 66, 92}, ++{169, 64, 97}, ++{182, 61, 103}, ++{196, 57, 109}, ++{209, 53, 115}, ++{219, 50, 119}, ++{143, 69, 84}, ++{149, 69, 87}, ++{159, 67, 92}, ++{171, 65, 98}, ++{184, 62, 104}, ++{197, 58, 109}, ++{210, 54, 115}, ++{220, 51, 119}, ++{145, 71, 85}, ++{151, 70, 88}, ++{161, 68, 93}, ++{172, 66, 99}, ++{185, 63, 104}, ++{198, 59, 110}, ++{212, 55, 115}, ++{222, 51, 119}, ++{147, 73, 86}, ++{153, 72, 89}, ++{163, 70, 94}, ++{174, 67, 99}, ++{187, 64, 105}, ++{200, 60, 110}, ++{213, 55, 116}, ++{223, 52, 119}, ++{150, 74, 87}, ++{155, 73, 90}, ++{165, 71, 95}, ++{176, 68, 100}, ++{188, 65, 105}, ++{201, 60, 111}, ++{214, 56, 116}, ++{224, 53, 120}, ++{152, 76, 88}, ++{158, 75, 91}, ++{167, 72, 95}, ++{178, 69, 101}, ++{190, 66, 106}, ++{203, 61, 111}, ++{216, 57, 116}, ++{226, 53, 120}, ++{155, 78, 89}, ++{160, 76, 92}, ++{169, 74, 96}, ++{180, 70, 101}, ++{192, 67, 106}, ++{204, 62, 112}, ++{217, 58, 117}, ++{227, 54, 120}, ++{158, 79, 90}, ++{163, 78, 93}, ++{172, 75, 97}, ++{182, 72, 102}, ++{194, 68, 107}, ++{206, 63, 112}, ++{219, 59, 117}, ++{229, 55, 121}, ++{160, 81, 92}, ++{165, 79, 94}, ++{174, 77, 98}, ++{184, 73, 103}, ++{196, 69, 108}, ++{208, 64, 113}, ++{221, 59, 118}, ++{230, 56, 121}, ++{163, 83, 93}, ++{168, 81, 95}, ++{177, 78, 99}, ++{187, 74, 103}, ++{198, 70, 108}, ++{210, 65, 113}, ++{223, 60, 118}, ++{232, 57, 122}, ++{166, 84, 94}, ++{171, 82, 96}, ++{179, 79, 100}, ++{189, 75, 104}, ++{200, 71, 109}, ++{212, 66, 114}, ++{224, 61, 119}, ++{234, 57, 122}, ++{169, 86, 95}, ++{174, 84, 97}, ++{182, 80, 101}, ++{192, 76, 105}, ++{203, 72, 110}, ++{214, 67, 114}, ++{226, 62, 119}, ++{236, 58, 122}, ++{172, 87, 96}, ++{177, 85, 98}, ++{185, 82, 102}, ++{194, 78, 106}, ++{205, 73, 110}, ++{216, 68, 115}, ++{228, 63, 119}, ++{237, 59, 123}, ++{175, 88, 97}, ++{180, 86, 99}, ++{187, 83, 102}, ++{197, 79, 107}, ++{207, 74, 111}, ++{219, 69, 115}, ++{230, 64, 120}, ++{239, 60, 123}, ++{178, 90, 98}, ++{183, 88, 100}, ++{190, 84, 103}, ++{199, 80, 107}, ++{210, 75, 112}, ++{221, 70, 116}, ++{233, 65, 120}, ++{241, 61, 124}, ++{182, 91, 99}, ++{186, 89, 101}, ++{193, 85, 104}, ++{202, 81, 108}, ++{212, 76, 112}, ++{223, 71, 117}, ++{235, 66, 121}, ++{244, 62, 124}, ++{185, 92, 100}, ++{189, 90, 102}, ++{196, 87, 105}, ++{205, 82, 109}, ++{215, 77, 113}, ++{226, 72, 117}, ++{237, 67, 121}, ++{246, 63, 125}, ++{188, 93, 101}, ++{192, 91, 103}, ++{199, 88, 106}, ++{208, 83, 110}, ++{218, 78, 114}, ++{228, 73, 118}, ++{239, 68, 122}, ++{248, 64, 125}, ++{191, 95, 102}, ++{195, 92, 104}, ++{202, 89, 107}, ++{211, 84, 111}, ++{220, 79, 114}, ++{231, 74, 118}, ++{242, 69, 122}, ++{250, 65, 126}, ++{195, 96, 103}, ++{199, 93, 105}, ++{205, 90, 108}, ++{214, 85, 111}, ++{223, 80, 115}, ++{233, 75, 119}, ++{244, 70, 123}, ++{252, 65, 126}, ++{196, 96, 104}, ++{200, 94, 106}, ++{207, 90, 108}, ++{215, 86, 112}, ++{224, 81, 115}, ++{235, 75, 119}, ++{245, 70, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{200, 94, 106}, ++{207, 90, 108}, ++{215, 86, 112}, ++{224, 81, 115}, ++{235, 75, 119}, ++{245, 70, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{200, 94, 106}, ++{207, 90, 108}, ++{215, 86, 112}, ++{224, 81, 115}, ++{235, 75, 119}, ++{245, 70, 123}, ++{254, 66, 126}, ++{196, 96, 104}, ++{200, 94, 106}, ++{207, 90, 108}, ++{215, 86, 112}, ++{224, 81, 115}, ++{235, 75, 119}, ++{245, 70, 123}, ++{254, 66, 126}, ++{135, 57, 77}, ++{141, 58, 81}, ++{152, 58, 87}, ++{165, 57, 93}, ++{179, 56, 99}, ++{192, 53, 106}, ++{206, 49, 111}, ++{217, 47, 116}, ++{135, 57, 77}, ++{142, 58, 81}, ++{153, 58, 87}, ++{165, 58, 93}, ++{179, 56, 99}, ++{193, 53, 106}, ++{206, 49, 111}, ++{217, 47, 116}, ++{135, 57, 78}, ++{142, 58, 81}, ++{153, 59, 87}, ++{166, 58, 93}, ++{179, 56, 100}, ++{193, 53, 106}, ++{207, 50, 112}, ++{217, 47, 116}, ++{136, 58, 78}, ++{143, 59, 82}, ++{154, 59, 87}, ++{166, 58, 93}, ++{179, 56, 100}, ++{193, 53, 106}, ++{207, 50, 112}, ++{217, 47, 116}, ++{137, 59, 78}, ++{144, 60, 82}, ++{154, 60, 88}, ++{167, 59, 94}, ++{180, 57, 100}, ++{194, 54, 106}, ++{208, 50, 112}, ++{218, 47, 116}, ++{138, 60, 79}, ++{145, 61, 82}, ++{155, 61, 88}, ++{168, 59, 94}, ++{181, 57, 100}, ++{195, 54, 106}, ++{208, 51, 112}, ++{219, 48, 116}, ++{140, 62, 80}, ++{146, 62, 83}, ++{157, 62, 88}, ++{169, 60, 94}, ++{182, 58, 101}, ++{195, 55, 106}, ++{209, 51, 112}, ++{219, 48, 116}, ++{142, 63, 80}, ++{148, 63, 84}, ++{158, 63, 89}, ++{170, 61, 95}, ++{183, 58, 101}, ++{196, 55, 107}, ++{210, 52, 112}, ++{220, 49, 116}, ++{143, 65, 81}, ++{149, 65, 85}, ++{159, 64, 90}, ++{171, 62, 95}, ++{184, 59, 101}, ++{197, 56, 107}, ++{211, 52, 113}, ++{221, 49, 117}, ++{145, 67, 82}, ++{151, 66, 85}, ++{161, 65, 90}, ++{173, 63, 96}, ++{186, 60, 102}, ++{199, 57, 107}, ++{212, 53, 113}, ++{222, 50, 117}, ++{147, 68, 83}, ++{153, 68, 86}, ++{163, 66, 91}, ++{174, 64, 97}, ++{187, 61, 102}, ++{200, 57, 108}, ++{213, 53, 113}, ++{223, 50, 117}, ++{150, 70, 84}, ++{155, 69, 87}, ++{165, 68, 92}, ++{176, 65, 97}, ++{189, 62, 103}, ++{201, 58, 108}, ++{215, 54, 114}, ++{224, 51, 118}, ++{152, 72, 85}, ++{158, 71, 88}, ++{167, 69, 93}, ++{178, 66, 98}, ++{190, 63, 103}, ++{203, 59, 109}, ++{216, 55, 114}, ++{226, 52, 118}, ++{155, 74, 86}, ++{160, 73, 89}, ++{169, 70, 93}, ++{180, 67, 99}, ++{192, 64, 104}, ++{205, 60, 109}, ++{217, 56, 114}, ++{227, 52, 118}, ++{157, 75, 87}, ++{162, 74, 90}, ++{171, 72, 94}, ++{182, 69, 99}, ++{194, 65, 104}, ++{206, 61, 110}, ++{219, 57, 115}, ++{229, 53, 119}, ++{160, 77, 88}, ++{165, 76, 91}, ++{174, 73, 95}, ++{184, 70, 100}, ++{196, 66, 105}, ++{208, 62, 110}, ++{221, 57, 115}, ++{230, 54, 119}, ++{163, 79, 90}, ++{168, 77, 92}, ++{176, 75, 96}, ++{186, 71, 101}, ++{198, 67, 106}, ++{210, 63, 111}, ++{222, 58, 116}, ++{232, 55, 119}, ++{165, 80, 91}, ++{170, 79, 93}, ++{179, 76, 97}, ++{189, 72, 101}, ++{200, 68, 106}, ++{212, 64, 111}, ++{224, 59, 116}, ++{233, 56, 120}, ++{168, 82, 92}, ++{173, 80, 94}, ++{181, 77, 98}, ++{191, 74, 102}, ++{202, 69, 107}, ++{214, 65, 112}, ++{226, 60, 117}, ++{235, 56, 120}, ++{171, 83, 93}, ++{176, 82, 95}, ++{184, 79, 99}, ++{194, 75, 103}, ++{204, 70, 108}, ++{216, 66, 112}, ++{228, 61, 117}, ++{237, 57, 121}, ++{174, 85, 94}, ++{179, 83, 96}, ++{187, 80, 100}, ++{196, 76, 104}, ++{207, 72, 108}, ++{218, 67, 113}, ++{230, 62, 118}, ++{239, 58, 121}, ++{177, 86, 95}, ++{182, 84, 97}, ++{189, 81, 101}, ++{199, 77, 105}, ++{209, 73, 109}, ++{220, 68, 114}, ++{232, 63, 118}, ++{241, 59, 121}, ++{180, 88, 96}, ++{185, 86, 98}, ++{192, 82, 101}, ++{201, 78, 105}, ++{212, 74, 110}, ++{223, 69, 114}, ++{234, 64, 119}, ++{243, 60, 122}, ++{184, 89, 97}, ++{188, 87, 99}, ++{195, 84, 102}, ++{204, 79, 106}, ++{214, 75, 110}, ++{225, 70, 115}, ++{236, 65, 119}, ++{245, 61, 122}, ++{187, 90, 98}, ++{191, 88, 100}, ++{198, 85, 103}, ++{207, 81, 107}, ++{217, 76, 111}, ++{227, 71, 115}, ++{239, 66, 120}, ++{247, 62, 123}, ++{190, 92, 100}, ++{194, 89, 101}, ++{201, 86, 104}, ++{210, 82, 108}, ++{219, 77, 112}, ++{230, 72, 116}, ++{241, 67, 120}, ++{249, 63, 123}, ++{193, 93, 101}, ++{197, 91, 102}, ++{204, 87, 105}, ++{212, 83, 109}, ++{222, 78, 113}, ++{232, 73, 117}, ++{243, 68, 121}, ++{252, 64, 124}, ++{197, 94, 102}, ++{200, 92, 103}, ++{207, 88, 106}, ++{215, 84, 109}, ++{225, 79, 113}, ++{235, 74, 117}, ++{246, 68, 121}, ++{254, 64, 124}, ++{198, 94, 102}, ++{202, 92, 104}, ++{208, 89, 107}, ++{217, 84, 110}, ++{226, 79, 114}, ++{236, 74, 118}, ++{247, 69, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{202, 92, 104}, ++{208, 89, 107}, ++{217, 84, 110}, ++{226, 79, 114}, ++{236, 74, 118}, ++{247, 69, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{202, 92, 104}, ++{208, 89, 107}, ++{217, 84, 110}, ++{226, 79, 114}, ++{236, 74, 118}, ++{247, 69, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{202, 92, 104}, ++{208, 89, 107}, ++{217, 84, 110}, ++{226, 79, 114}, ++{236, 74, 118}, ++{247, 69, 122}, ++{255, 65, 124}, ++{138, 54, 75}, ++{144, 55, 79}, ++{155, 56, 85}, ++{167, 56, 91}, ++{181, 54, 97}, ++{194, 51, 104}, ++{208, 48, 109}, ++{218, 45, 114}, ++{138, 54, 75}, ++{144, 56, 79}, ++{155, 56, 85}, ++{167, 56, 91}, ++{181, 54, 97}, ++{194, 51, 104}, ++{208, 48, 109}, ++{219, 45, 114}, ++{138, 55, 76}, ++{145, 56, 79}, ++{155, 57, 85}, ++{168, 56, 91}, ++{181, 54, 98}, ++{195, 52, 104}, ++{208, 48, 110}, ++{219, 46, 114}, ++{139, 56, 76}, ++{145, 57, 80}, ++{156, 57, 85}, ++{168, 56, 91}, ++{182, 54, 98}, ++{195, 52, 104}, ++{209, 49, 110}, ++{219, 46, 114}, ++{140, 57, 77}, ++{146, 58, 80}, ++{157, 58, 86}, ++{169, 57, 92}, ++{182, 55, 98}, ++{196, 52, 104}, ++{209, 49, 110}, ++{220, 46, 114}, ++{141, 58, 77}, ++{148, 59, 81}, ++{158, 59, 86}, ++{170, 58, 92}, ++{183, 55, 98}, ++{196, 53, 104}, ++{210, 49, 110}, ++{220, 46, 114}, ++{143, 59, 78}, ++{149, 60, 81}, ++{159, 60, 86}, ++{171, 58, 92}, ++{184, 56, 99}, ++{197, 53, 104}, ++{211, 50, 110}, ++{221, 47, 114}, ++{144, 61, 79}, ++{150, 61, 82}, ++{160, 61, 87}, ++{172, 59, 93}, ++{185, 57, 99}, ++{198, 54, 105}, ++{212, 50, 110}, ++{222, 47, 115}, ++{146, 63, 79}, ++{152, 62, 83}, ++{162, 62, 88}, ++{174, 60, 93}, ++{186, 58, 99}, ++{199, 54, 105}, ++{213, 51, 111}, ++{223, 48, 115}, ++{148, 64, 80}, ++{154, 64, 83}, ++{163, 63, 88}, ++{175, 61, 94}, ++{188, 58, 100}, ++{201, 55, 106}, ++{214, 51, 111}, ++{224, 48, 115}, ++{150, 66, 81}, ++{156, 66, 84}, ++{165, 64, 89}, ++{177, 62, 95}, ++{189, 59, 100}, ++{202, 56, 106}, ++{215, 52, 111}, ++{225, 49, 115}, ++{152, 68, 82}, ++{158, 67, 85}, ++{167, 66, 90}, ++{178, 63, 95}, ++{191, 60, 101}, ++{203, 57, 106}, ++{216, 53, 112}, ++{226, 50, 116}, ++{155, 70, 83}, ++{160, 69, 86}, ++{169, 67, 91}, ++{180, 65, 96}, ++{192, 61, 101}, ++{205, 58, 107}, ++{218, 54, 112}, ++{227, 50, 116}, ++{157, 71, 84}, ++{162, 70, 87}, ++{171, 68, 91}, ++{182, 66, 97}, ++{194, 62, 102}, ++{206, 59, 107}, ++{219, 54, 113}, ++{229, 51, 116}, ++{160, 73, 85}, ++{165, 72, 88}, ++{173, 70, 92}, ++{184, 67, 97}, ++{196, 63, 103}, ++{208, 59, 108}, ++{221, 55, 113}, ++{230, 52, 117}, ++{162, 75, 87}, ++{167, 74, 89}, ++{176, 71, 93}, ++{186, 68, 98}, ++{198, 64, 103}, ++{210, 60, 108}, ++{222, 56, 113}, ++{232, 53, 117}, ++{165, 76, 88}, ++{170, 75, 90}, ++{178, 73, 94}, ++{188, 69, 99}, ++{200, 66, 104}, ++{212, 61, 109}, ++{224, 57, 114}, ++{233, 54, 117}, ++{168, 78, 89}, ++{173, 77, 91}, ++{181, 74, 95}, ++{191, 71, 100}, ++{202, 67, 104}, ++{214, 62, 109}, ++{226, 58, 114}, ++{235, 54, 118}, ++{171, 80, 90}, ++{175, 78, 92}, ++{183, 75, 96}, ++{193, 72, 100}, ++{204, 68, 105}, ++{216, 63, 110}, ++{228, 59, 115}, ++{237, 55, 118}, ++{173, 81, 91}, ++{178, 80, 93}, ++{186, 77, 97}, ++{195, 73, 101}, ++{206, 69, 106}, ++{218, 64, 111}, ++{230, 60, 115}, ++{239, 56, 119}, ++{176, 83, 92}, ++{181, 81, 94}, ++{189, 78, 98}, ++{198, 74, 102}, ++{209, 70, 106}, ++{220, 65, 111}, ++{232, 61, 116}, ++{240, 57, 119}, ++{179, 84, 93}, ++{184, 82, 95}, ++{191, 79, 99}, ++{201, 75, 103}, ++{211, 71, 107}, ++{222, 66, 112}, ++{234, 62, 116}, ++{242, 58, 120}, ++{182, 86, 94}, ++{187, 84, 96}, ++{194, 81, 100}, ++{203, 77, 104}, ++{213, 72, 108}, ++{224, 67, 112}, ++{236, 63, 117}, ++{244, 59, 120}, ++{186, 87, 95}, ++{190, 85, 97}, ++{197, 82, 101}, ++{206, 78, 104}, ++{216, 73, 109}, ++{227, 68, 113}, ++{238, 64, 117}, ++{246, 60, 121}, ++{189, 88, 97}, ++{193, 86, 98}, ++{200, 83, 101}, ++{208, 79, 105}, ++{218, 74, 109}, ++{229, 70, 114}, ++{240, 64, 118}, ++{249, 61, 121}, ++{192, 90, 98}, ++{196, 88, 99}, ++{203, 84, 102}, ++{211, 80, 106}, ++{221, 75, 110}, ++{231, 71, 114}, ++{242, 65, 118}, ++{251, 62, 122}, ++{195, 91, 99}, ++{199, 89, 100}, ++{206, 85, 103}, ++{214, 81, 107}, ++{224, 76, 111}, ++{234, 72, 115}, ++{245, 66, 119}, ++{253, 62, 122}, ++{198, 92, 100}, ++{202, 90, 101}, ++{209, 87, 104}, ++{217, 82, 108}, ++{226, 78, 111}, ++{236, 73, 115}, ++{247, 67, 119}, ++{255, 63, 123}, ++{200, 93, 100}, ++{204, 91, 102}, ++{210, 87, 105}, ++{218, 83, 108}, ++{228, 78, 112}, ++{238, 73, 116}, ++{248, 68, 120}, ++{255, 64, 123}, ++{200, 93, 100}, ++{204, 91, 102}, ++{210, 87, 105}, ++{218, 83, 108}, ++{228, 78, 112}, ++{238, 73, 116}, ++{248, 68, 120}, ++{255, 64, 123}, ++{200, 93, 100}, ++{204, 91, 102}, ++{210, 87, 105}, ++{218, 83, 108}, ++{228, 78, 112}, ++{238, 73, 116}, ++{248, 68, 120}, ++{255, 64, 123}, ++{200, 93, 100}, ++{204, 91, 102}, ++{210, 87, 105}, ++{218, 83, 108}, ++{228, 78, 112}, ++{238, 73, 116}, ++{248, 68, 120}, ++{255, 64, 123}, ++{140, 52, 74}, ++{147, 53, 77}, ++{157, 54, 83}, ++{170, 54, 89}, ++{183, 52, 95}, ++{196, 50, 102}, ++{210, 47, 107}, ++{220, 44, 112}, ++{141, 52, 74}, ++{147, 53, 77}, ++{157, 54, 83}, ++{170, 54, 89}, ++{183, 52, 95}, ++{196, 50, 102}, ++{210, 47, 108}, ++{220, 44, 112}, ++{141, 53, 74}, ++{147, 54, 77}, ++{158, 54, 83}, ++{170, 54, 89}, ++{183, 52, 96}, ++{197, 50, 102}, ++{210, 47, 108}, ++{220, 44, 112}, ++{142, 53, 74}, ++{148, 54, 78}, ++{158, 55, 83}, ++{171, 54, 89}, ++{184, 53, 96}, ++{197, 50, 102}, ++{211, 47, 108}, ++{221, 45, 112}, ++{143, 54, 75}, ++{149, 55, 78}, ++{159, 56, 84}, ++{171, 55, 90}, ++{184, 53, 96}, ++{198, 51, 102}, ++{211, 48, 108}, ++{221, 45, 112}, ++{144, 56, 75}, ++{150, 56, 79}, ++{160, 56, 84}, ++{172, 56, 90}, ++{185, 54, 96}, ++{198, 51, 102}, ++{212, 48, 108}, ++{222, 45, 112}, ++{145, 57, 76}, ++{151, 57, 79}, ++{161, 57, 85}, ++{173, 56, 91}, ++{186, 54, 97}, ++{199, 52, 103}, ++{213, 48, 108}, ++{223, 46, 112}, ++{147, 59, 77}, ++{153, 59, 80}, ++{163, 59, 85}, ++{174, 57, 91}, ++{187, 55, 97}, ++{200, 52, 103}, ++{213, 49, 109}, ++{223, 46, 113}, ++{149, 60, 78}, ++{154, 60, 81}, ++{164, 60, 86}, ++{176, 58, 91}, ++{188, 56, 97}, ++{201, 53, 103}, ++{214, 50, 109}, ++{224, 47, 113}, ++{151, 62, 79}, ++{156, 62, 82}, ++{166, 61, 86}, ++{177, 59, 92}, ++{190, 57, 98}, ++{202, 54, 104}, ++{216, 50, 109}, ++{225, 47, 113}, ++{153, 64, 79}, ++{158, 63, 82}, ++{168, 62, 87}, ++{179, 60, 93}, ++{191, 58, 98}, ++{204, 54, 104}, ++{217, 51, 109}, ++{227, 48, 113}, ++{155, 65, 80}, ++{160, 65, 83}, ++{169, 64, 88}, ++{180, 62, 93}, ++{192, 59, 99}, ++{205, 55, 104}, ++{218, 52, 110}, ++{228, 49, 114}, ++{157, 67, 81}, ++{162, 66, 84}, ++{171, 65, 89}, ++{182, 63, 94}, ++{194, 60, 99}, ++{207, 56, 105}, ++{219, 52, 110}, ++{229, 49, 114}, ++{159, 69, 83}, ++{165, 68, 85}, ++{173, 66, 90}, ++{184, 64, 95}, ++{196, 61, 100}, ++{208, 57, 105}, ++{221, 53, 111}, ++{230, 50, 114}, ++{162, 71, 84}, ++{167, 70, 86}, ++{176, 68, 90}, ++{186, 65, 95}, ++{198, 62, 101}, ++{210, 58, 106}, ++{222, 54, 111}, ++{232, 51, 115}, ++{164, 73, 85}, ++{170, 71, 87}, ++{178, 69, 91}, ++{188, 66, 96}, ++{200, 63, 101}, ++{212, 59, 106}, ++{224, 55, 111}, ++{233, 52, 115}, ++{167, 74, 86}, ++{172, 73, 88}, ++{180, 71, 92}, ++{190, 68, 97}, ++{202, 64, 102}, ++{213, 60, 107}, ++{226, 56, 112}, ++{235, 52, 116}, ++{170, 76, 87}, ++{175, 75, 89}, ++{183, 72, 93}, ++{193, 69, 98}, ++{204, 65, 103}, ++{215, 61, 107}, ++{227, 57, 112}, ++{237, 53, 116}, ++{173, 78, 88}, ++{177, 76, 90}, ++{185, 73, 94}, ++{195, 70, 98}, ++{206, 66, 103}, ++{217, 62, 108}, ++{229, 58, 113}, ++{238, 54, 116}, ++{176, 79, 89}, ++{180, 78, 91}, ++{188, 75, 95}, ++{197, 71, 99}, ++{208, 67, 104}, ++{219, 63, 109}, ++{231, 58, 113}, ++{240, 55, 117}, ++{179, 81, 90}, ++{183, 79, 92}, ++{190, 76, 96}, ++{200, 73, 100}, ++{210, 68, 105}, ++{221, 64, 109}, ++{233, 59, 114}, ++{242, 56, 117}, ++{182, 82, 91}, ++{186, 80, 93}, ++{193, 78, 97}, ++{202, 74, 101}, ++{213, 70, 105}, ++{224, 65, 110}, ++{235, 60, 114}, ++{244, 57, 118}, ++{185, 84, 93}, ++{189, 82, 94}, ++{196, 79, 98}, ++{205, 75, 102}, ++{215, 71, 106}, ++{226, 66, 110}, ++{237, 61, 115}, ++{246, 58, 118}, ++{188, 85, 94}, ++{192, 83, 96}, ++{199, 80, 99}, ++{208, 76, 103}, ++{218, 72, 107}, ++{228, 67, 111}, ++{239, 62, 116}, ++{248, 59, 119}, ++{191, 86, 95}, ++{195, 85, 97}, ++{202, 81, 100}, ++{210, 77, 103}, ++{220, 73, 107}, ++{231, 68, 112}, ++{242, 63, 116}, ++{250, 60, 119}, ++{194, 88, 96}, ++{198, 86, 98}, ++{205, 83, 101}, ++{213, 79, 104}, ++{223, 74, 108}, ++{233, 69, 112}, ++{244, 64, 117}, ++{252, 60, 120}, ++{197, 89, 97}, ++{201, 87, 99}, ++{207, 84, 101}, ++{216, 80, 105}, ++{225, 75, 109}, ++{235, 70, 113}, ++{246, 65, 117}, ++{254, 61, 120}, ++{200, 90, 98}, ++{204, 88, 100}, ++{210, 85, 102}, ++{219, 81, 106}, ++{228, 76, 110}, ++{238, 71, 114}, ++{248, 66, 118}, ++{255, 62, 121}, ++{202, 91, 99}, ++{206, 89, 100}, ++{212, 85, 103}, ++{220, 81, 106}, ++{229, 77, 110}, ++{239, 72, 114}, ++{250, 67, 118}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 89, 100}, ++{212, 85, 103}, ++{220, 81, 106}, ++{229, 77, 110}, ++{239, 72, 114}, ++{250, 67, 118}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 89, 100}, ++{212, 85, 103}, ++{220, 81, 106}, ++{229, 77, 110}, ++{239, 72, 114}, ++{250, 67, 118}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 89, 100}, ++{212, 85, 103}, ++{220, 81, 106}, ++{229, 77, 110}, ++{239, 72, 114}, ++{250, 67, 118}, ++{255, 63, 121}, ++{143, 50, 72}, ++{149, 51, 75}, ++{160, 52, 81}, ++{172, 52, 87}, ++{185, 50, 93}, ++{198, 48, 100}, ++{212, 45, 106}, ++{222, 43, 110}, ++{143, 50, 72}, ++{150, 51, 75}, ++{160, 52, 81}, ++{172, 52, 87}, ++{185, 51, 93}, ++{198, 48, 100}, ++{212, 45, 106}, ++{222, 43, 110}, ++{144, 50, 72}, ++{150, 51, 76}, ++{160, 52, 81}, ++{172, 52, 87}, ++{185, 51, 94}, ++{199, 49, 100}, ++{212, 46, 106}, ++{222, 43, 110}, ++{144, 51, 73}, ++{151, 52, 76}, ++{161, 53, 81}, ++{173, 53, 88}, ++{186, 51, 94}, ++{199, 49, 100}, ++{212, 46, 106}, ++{223, 43, 110}, ++{145, 52, 73}, ++{152, 53, 76}, ++{162, 54, 82}, ++{173, 53, 88}, ++{186, 52, 94}, ++{200, 49, 100}, ++{213, 46, 106}, ++{223, 44, 110}, ++{147, 53, 74}, ++{153, 54, 77}, ++{163, 54, 82}, ++{174, 54, 88}, ++{187, 52, 94}, ++{200, 50, 100}, ++{214, 47, 106}, ++{224, 44, 110}, ++{148, 55, 74}, ++{154, 55, 78}, ++{164, 55, 83}, ++{175, 55, 89}, ++{188, 53, 95}, ++{201, 50, 101}, ++{214, 47, 106}, ++{224, 44, 111}, ++{149, 56, 75}, ++{155, 57, 78}, ++{165, 56, 83}, ++{177, 55, 89}, ++{189, 53, 95}, ++{202, 51, 101}, ++{215, 48, 107}, ++{225, 45, 111}, ++{151, 58, 76}, ++{157, 58, 79}, ++{166, 58, 84}, ++{178, 56, 90}, ++{190, 54, 95}, ++{203, 51, 101}, ++{216, 48, 107}, ++{226, 45, 111}, ++{153, 59, 77}, ++{159, 59, 80}, ++{168, 59, 85}, ++{179, 57, 90}, ++{192, 55, 96}, ++{204, 52, 102}, ++{217, 49, 107}, ++{227, 46, 111}, ++{155, 61, 78}, ++{161, 61, 81}, ++{170, 60, 85}, ++{181, 59, 91}, ++{193, 56, 96}, ++{206, 53, 102}, ++{218, 50, 108}, ++{228, 47, 112}, ++{157, 63, 79}, ++{163, 63, 81}, ++{172, 62, 86}, ++{183, 60, 91}, ++{194, 57, 97}, ++{207, 54, 102}, ++{220, 50, 108}, ++{229, 47, 112}, ++{159, 65, 80}, ++{165, 64, 82}, ++{174, 63, 87}, ++{184, 61, 92}, ++{196, 58, 97}, ++{208, 55, 103}, ++{221, 51, 108}, ++{231, 48, 112}, ++{162, 67, 81}, ++{167, 66, 83}, ++{176, 64, 88}, ++{186, 62, 93}, ++{198, 59, 98}, ++{210, 56, 103}, ++{222, 52, 109}, ++{232, 49, 113}, ++{164, 68, 82}, ++{169, 68, 84}, ++{178, 66, 89}, ++{188, 63, 93}, ++{200, 60, 99}, ++{212, 57, 104}, ++{224, 53, 109}, ++{233, 50, 113}, ++{167, 70, 83}, ++{172, 69, 85}, ++{180, 67, 89}, ++{190, 65, 94}, ++{201, 61, 99}, ++{213, 58, 104}, ++{226, 54, 110}, ++{235, 50, 113}, ++{169, 72, 84}, ++{174, 71, 86}, ++{182, 69, 90}, ++{192, 66, 95}, ++{203, 62, 100}, ++{215, 59, 105}, ++{227, 54, 110}, ++{237, 51, 114}, ++{172, 74, 85}, ++{177, 72, 87}, ++{185, 70, 91}, ++{195, 67, 96}, ++{206, 64, 101}, ++{217, 60, 106}, ++{229, 55, 111}, ++{238, 52, 114}, ++{175, 75, 86}, ++{180, 74, 88}, ++{187, 72, 92}, ++{197, 68, 97}, ++{208, 65, 101}, ++{219, 61, 106}, ++{231, 56, 111}, ++{240, 53, 115}, ++{178, 77, 87}, ++{182, 76, 89}, ++{190, 73, 93}, ++{199, 70, 97}, ++{210, 66, 102}, ++{221, 62, 107}, ++{233, 57, 112}, ++{242, 54, 115}, ++{181, 79, 88}, ++{185, 77, 91}, ++{192, 74, 94}, ++{202, 71, 98}, ++{212, 67, 103}, ++{223, 63, 107}, ++{235, 58, 112}, ++{244, 55, 116}, ++{184, 80, 90}, ++{188, 78, 92}, ++{195, 76, 95}, ++{204, 72, 99}, ++{214, 68, 103}, ++{225, 64, 108}, ++{237, 59, 113}, ++{245, 56, 116}, ++{187, 82, 91}, ++{191, 80, 93}, ++{198, 77, 96}, ++{207, 73, 100}, ++{217, 69, 104}, ++{228, 65, 109}, ++{239, 60, 113}, ++{247, 57, 117}, ++{190, 83, 92}, ++{194, 81, 94}, ++{201, 78, 97}, ++{209, 75, 101}, ++{219, 70, 105}, ++{230, 66, 109}, ++{241, 61, 114}, ++{249, 57, 117}, ++{193, 84, 93}, ++{197, 83, 95}, ++{204, 80, 98}, ++{212, 76, 102}, ++{222, 71, 106}, ++{232, 67, 110}, ++{243, 62, 114}, ++{252, 58, 118}, ++{196, 86, 94}, ++{200, 84, 96}, ++{206, 81, 99}, ++{215, 77, 102}, ++{224, 73, 106}, ++{235, 68, 111}, ++{245, 63, 115}, ++{254, 59, 118}, ++{199, 87, 95}, ++{203, 85, 97}, ++{209, 82, 100}, ++{218, 78, 103}, ++{227, 74, 107}, ++{237, 69, 111}, ++{248, 64, 115}, ++{255, 60, 119}, ++{202, 88, 96}, ++{206, 86, 98}, ++{212, 83, 101}, ++{220, 79, 104}, ++{230, 75, 108}, ++{239, 70, 112}, ++{250, 65, 116}, ++{255, 61, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{214, 84, 101}, ++{222, 80, 104}, ++{231, 75, 108}, ++{241, 70, 112}, ++{251, 65, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{214, 84, 101}, ++{222, 80, 104}, ++{231, 75, 108}, ++{241, 70, 112}, ++{251, 65, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{214, 84, 101}, ++{222, 80, 104}, ++{231, 75, 108}, ++{241, 70, 112}, ++{251, 65, 116}, ++{255, 62, 119}, ++{204, 89, 97}, ++{207, 87, 98}, ++{214, 84, 101}, ++{222, 80, 104}, ++{231, 75, 108}, ++{241, 70, 112}, ++{251, 65, 116}, ++{255, 62, 119}, ++{146, 47, 70}, ++{152, 49, 74}, ++{162, 50, 79}, ++{174, 50, 85}, ++{187, 49, 92}, ++{200, 47, 98}, ++{214, 44, 104}, ++{224, 42, 108}, ++{146, 47, 70}, ++{152, 49, 74}, ++{162, 50, 79}, ++{174, 50, 85}, ++{187, 49, 92}, ++{200, 47, 98}, ++{214, 44, 104}, ++{224, 42, 108}, ++{146, 48, 70}, ++{153, 49, 74}, ++{163, 50, 79}, ++{174, 50, 85}, ++{187, 49, 92}, ++{200, 47, 98}, ++{214, 44, 104}, ++{224, 42, 108}, ++{147, 49, 71}, ++{153, 50, 74}, ++{163, 51, 80}, ++{175, 51, 86}, ++{188, 49, 92}, ++{201, 47, 98}, ++{214, 45, 104}, ++{224, 42, 108}, ++{148, 50, 71}, ++{154, 51, 75}, ++{164, 51, 80}, ++{176, 51, 86}, ++{188, 50, 92}, ++{201, 48, 98}, ++{215, 45, 104}, ++{225, 42, 108}, ++{149, 51, 72}, ++{155, 52, 75}, ++{165, 52, 80}, ++{177, 52, 86}, ++{189, 50, 92}, ++{202, 48, 98}, ++{215, 45, 104}, ++{225, 43, 108}, ++{151, 52, 73}, ++{156, 53, 76}, ++{166, 53, 81}, ++{178, 53, 87}, ++{190, 51, 93}, ++{203, 49, 99}, ++{216, 46, 104}, ++{226, 43, 109}, ++{152, 54, 73}, ++{158, 54, 76}, ++{167, 54, 81}, ++{179, 54, 87}, ++{191, 52, 93}, ++{204, 49, 99}, ++{217, 46, 105}, ++{227, 44, 109}, ++{154, 55, 74}, ++{159, 56, 77}, ++{169, 56, 82}, ++{180, 55, 88}, ++{192, 53, 94}, ++{205, 50, 99}, ++{218, 47, 105}, ++{228, 44, 109}, ++{156, 57, 75}, ++{161, 57, 78}, ++{170, 57, 83}, ++{181, 56, 88}, ++{194, 53, 94}, ++{206, 51, 100}, ++{219, 47, 105}, ++{229, 45, 109}, ++{158, 59, 76}, ++{163, 59, 79}, ++{172, 58, 83}, ++{183, 57, 89}, ++{195, 54, 94}, ++{207, 52, 100}, ++{220, 48, 106}, ++{230, 45, 110}, ++{160, 61, 77}, ++{165, 60, 80}, ++{174, 59, 84}, ++{185, 58, 89}, ++{196, 55, 95}, ++{209, 52, 101}, ++{221, 49, 106}, ++{231, 46, 110}, ++{162, 63, 78}, ++{167, 62, 81}, ++{176, 61, 85}, ++{186, 59, 90}, ++{198, 56, 96}, ++{210, 53, 101}, ++{223, 50, 106}, ++{232, 47, 110}, ++{164, 64, 79}, ++{169, 64, 82}, ++{178, 62, 86}, ++{188, 60, 91}, ++{200, 57, 96}, ++{212, 54, 102}, ++{224, 51, 107}, ++{234, 48, 111}, ++{167, 66, 80}, ++{172, 65, 82}, ++{180, 64, 87}, ++{190, 61, 92}, ++{201, 59, 97}, ++{213, 55, 102}, ++{226, 51, 107}, ++{235, 48, 111}, ++{169, 68, 81}, ++{174, 67, 83}, ++{182, 65, 88}, ++{192, 63, 92}, ++{203, 60, 97}, ++{215, 56, 103}, ++{227, 52, 108}, ++{237, 49, 112}, ++{172, 70, 82}, ++{176, 69, 85}, ++{184, 67, 88}, ++{194, 64, 93}, ++{205, 61, 98}, ++{217, 57, 103}, ++{229, 53, 108}, ++{238, 50, 112}, ++{174, 71, 83}, ++{179, 70, 86}, ++{187, 68, 89}, ++{197, 65, 94}, ++{207, 62, 99}, ++{219, 58, 104}, ++{231, 54, 109}, ++{240, 51, 112}, ++{177, 73, 84}, ++{182, 72, 87}, ++{189, 70, 90}, ++{199, 67, 95}, ++{209, 63, 99}, ++{221, 59, 104}, ++{233, 55, 109}, ++{241, 52, 113}, ++{180, 75, 86}, ++{184, 73, 88}, ++{192, 71, 91}, ++{201, 68, 96}, ++{212, 64, 100}, ++{223, 60, 105}, ++{234, 56, 110}, ++{243, 53, 113}, ++{183, 76, 87}, ++{187, 75, 89}, ++{194, 72, 92}, ++{204, 69, 96}, ++{214, 65, 101}, ++{225, 61, 106}, ++{236, 57, 110}, ++{245, 54, 114}, ++{186, 78, 88}, ++{190, 76, 90}, ++{197, 74, 93}, ++{206, 70, 97}, ++{216, 67, 102}, ++{227, 62, 106}, ++{238, 58, 111}, ++{247, 54, 114}, ++{189, 80, 89}, ++{193, 78, 91}, ++{200, 75, 94}, ++{209, 72, 98}, ++{219, 68, 102}, ++{229, 63, 107}, ++{240, 59, 111}, ++{249, 55, 115}, ++{192, 81, 90}, ++{196, 79, 92}, ++{203, 76, 95}, ++{211, 73, 99}, ++{221, 69, 103}, ++{232, 64, 107}, ++{243, 60, 112}, ++{251, 56, 115}, ++{195, 82, 91}, ++{199, 81, 93}, ++{205, 78, 96}, ++{214, 74, 100}, ++{223, 70, 104}, ++{234, 66, 108}, ++{245, 61, 113}, ++{253, 57, 116}, ++{198, 84, 92}, ++{202, 82, 94}, ++{208, 79, 97}, ++{217, 75, 101}, ++{226, 71, 105}, ++{236, 67, 109}, ++{247, 62, 113}, ++{255, 58, 116}, ++{201, 85, 93}, ++{205, 83, 95}, ++{211, 80, 98}, ++{219, 76, 101}, ++{229, 72, 105}, ++{239, 68, 109}, ++{249, 63, 114}, ++{255, 59, 117}, ++{204, 86, 94}, ++{208, 85, 96}, ++{214, 81, 99}, ++{222, 78, 102}, ++{231, 73, 106}, ++{241, 69, 110}, ++{251, 64, 114}, ++{255, 60, 117}, ++{206, 87, 95}, ++{209, 85, 97}, ++{215, 82, 99}, ++{223, 78, 103}, ++{232, 74, 106}, ++{242, 69, 110}, ++{253, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{209, 85, 97}, ++{215, 82, 99}, ++{223, 78, 103}, ++{232, 74, 106}, ++{242, 69, 110}, ++{253, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{209, 85, 97}, ++{215, 82, 99}, ++{223, 78, 103}, ++{232, 74, 106}, ++{242, 69, 110}, ++{253, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{209, 85, 97}, ++{215, 82, 99}, ++{223, 78, 103}, ++{232, 74, 106}, ++{242, 69, 110}, ++{253, 64, 115}, ++{255, 61, 118}, ++{149, 45, 68}, ++{155, 46, 72}, ++{165, 48, 77}, ++{176, 48, 83}, ++{189, 47, 90}, ++{202, 45, 96}, ++{215, 43, 102}, ++{225, 40, 106}, ++{149, 45, 69}, ++{155, 47, 72}, ++{165, 48, 77}, ++{176, 48, 83}, ++{189, 47, 90}, ++{202, 45, 96}, ++{215, 43, 102}, ++{225, 40, 106}, ++{149, 46, 69}, ++{155, 47, 72}, ++{165, 48, 77}, ++{177, 48, 84}, ++{189, 47, 90}, ++{202, 45, 96}, ++{216, 43, 102}, ++{226, 41, 106}, ++{150, 46, 69}, ++{156, 48, 72}, ++{166, 49, 78}, ++{177, 49, 84}, ++{190, 48, 90}, ++{203, 46, 96}, ++{216, 43, 102}, ++{226, 41, 106}, ++{151, 47, 70}, ++{157, 49, 73}, ++{166, 49, 78}, ++{178, 49, 84}, ++{190, 48, 90}, ++{203, 46, 96}, ++{217, 43, 102}, ++{226, 41, 106}, ++{152, 49, 70}, ++{158, 50, 73}, ++{167, 50, 79}, ++{179, 50, 84}, ++{191, 49, 90}, ++{204, 47, 96}, ++{217, 44, 102}, ++{227, 42, 107}, ++{153, 50, 71}, ++{159, 51, 74}, ++{168, 51, 79}, ++{180, 51, 85}, ++{192, 49, 91}, ++{205, 47, 97}, ++{218, 44, 103}, ++{228, 42, 107}, ++{155, 52, 72}, ++{160, 52, 75}, ++{170, 52, 80}, ++{181, 52, 85}, ++{193, 50, 91}, ++{206, 48, 97}, ++{219, 45, 103}, ++{229, 42, 107}, ++{156, 53, 72}, ++{162, 53, 75}, ++{171, 53, 80}, ++{182, 53, 86}, ++{194, 51, 92}, ++{207, 48, 97}, ++{220, 45, 103}, ++{229, 43, 107}, ++{158, 55, 73}, ++{164, 55, 76}, ++{173, 55, 81}, ++{184, 54, 86}, ++{196, 52, 92}, ++{208, 49, 98}, ++{221, 46, 103}, ++{230, 44, 108}, ++{160, 57, 74}, ++{165, 57, 77}, ++{174, 56, 82}, ++{185, 55, 87}, ++{197, 53, 93}, ++{209, 50, 98}, ++{222, 47, 104}, ++{232, 44, 108}, ++{162, 58, 75}, ++{167, 58, 78}, ++{176, 57, 82}, ++{187, 56, 88}, ++{198, 54, 93}, ++{211, 51, 99}, ++{223, 48, 104}, ++{233, 45, 108}, ++{164, 60, 76}, ++{169, 60, 79}, ++{178, 59, 83}, ++{188, 57, 88}, ++{200, 55, 94}, ++{212, 52, 99}, ++{224, 48, 105}, ++{234, 46, 109}, ++{167, 62, 77}, ++{172, 62, 80}, ++{180, 60, 84}, ++{190, 58, 89}, ++{202, 56, 94}, ++{214, 53, 100}, ++{226, 49, 105}, ++{235, 46, 109}, ++{169, 64, 78}, ++{174, 63, 81}, ++{182, 62, 85}, ++{192, 60, 90}, ++{203, 57, 95}, ++{215, 54, 100}, ++{227, 50, 105}, ++{237, 47, 109}, ++{171, 66, 79}, ++{176, 65, 82}, ++{184, 63, 86}, ++{194, 61, 90}, ++{205, 58, 96}, ++{217, 55, 101}, ++{229, 51, 106}, ++{238, 48, 110}, ++{174, 67, 80}, ++{179, 67, 83}, ++{187, 65, 87}, ++{196, 62, 91}, ++{207, 59, 96}, ++{219, 56, 101}, ++{231, 52, 106}, ++{240, 49, 110}, ++{177, 69, 81}, ++{181, 68, 84}, ++{189, 66, 88}, ++{199, 64, 92}, ++{209, 60, 97}, ++{221, 57, 102}, ++{232, 53, 107}, ++{241, 50, 111}, ++{179, 71, 83}, ++{184, 70, 85}, ++{191, 68, 88}, ++{201, 65, 93}, ++{211, 61, 98}, ++{223, 58, 103}, ++{234, 54, 107}, ++{243, 51, 111}, ++{182, 73, 84}, ++{186, 71, 86}, ++{194, 69, 89}, ++{203, 66, 94}, ++{213, 63, 98}, ++{225, 59, 103}, ++{236, 55, 108}, ++{245, 51, 112}, ++{185, 74, 85}, ++{189, 73, 87}, ++{196, 71, 90}, ++{206, 67, 95}, ++{216, 64, 99}, ++{227, 60, 104}, ++{238, 56, 108}, ++{247, 52, 112}, ++{188, 76, 86}, ++{192, 74, 88}, ++{199, 72, 91}, ++{208, 69, 95}, ++{218, 65, 100}, ++{229, 61, 104}, ++{240, 57, 109}, ++{249, 53, 113}, ++{191, 77, 87}, ++{195, 76, 89}, ++{202, 73, 92}, ++{210, 70, 96}, ++{220, 66, 101}, ++{231, 62, 105}, ++{242, 58, 110}, ++{251, 54, 113}, ++{194, 79, 88}, ++{198, 77, 90}, ++{204, 75, 93}, ++{213, 71, 97}, ++{223, 67, 101}, ++{233, 63, 106}, ++{244, 59, 110}, ++{253, 55, 114}, ++{197, 80, 89}, ++{201, 79, 91}, ++{207, 76, 94}, ++{216, 72, 98}, ++{225, 68, 102}, ++{235, 64, 106}, ++{246, 60, 111}, ++{255, 56, 114}, ++{200, 82, 90}, ++{204, 80, 92}, ++{210, 77, 95}, ++{218, 74, 99}, ++{228, 70, 103}, ++{238, 65, 107}, ++{248, 61, 111}, ++{255, 57, 115}, ++{203, 83, 92}, ++{207, 81, 93}, ++{213, 79, 96}, ++{221, 75, 100}, ++{230, 71, 104}, ++{240, 66, 108}, ++{251, 62, 112}, ++{255, 58, 115}, ++{206, 84, 93}, ++{210, 83, 94}, ++{216, 80, 97}, ++{224, 76, 101}, ++{233, 72, 104}, ++{243, 67, 108}, ++{253, 63, 113}, ++{255, 59, 116}, ++{207, 85, 93}, ++{211, 83, 95}, ++{217, 80, 98}, ++{225, 77, 101}, ++{234, 72, 105}, ++{244, 68, 109}, ++{254, 63, 113}, ++{255, 59, 116}, ++{207, 85, 93}, ++{211, 83, 95}, ++{217, 80, 98}, ++{225, 77, 101}, ++{234, 72, 105}, ++{244, 68, 109}, ++{254, 63, 113}, ++{255, 59, 116}, ++{207, 85, 93}, ++{211, 83, 95}, ++{217, 80, 98}, ++{225, 77, 101}, ++{234, 72, 105}, ++{244, 68, 109}, ++{254, 63, 113}, ++{255, 59, 116}, ++{207, 85, 93}, ++{211, 83, 95}, ++{217, 80, 98}, ++{225, 77, 101}, ++{234, 72, 105}, ++{244, 68, 109}, ++{254, 63, 113}, ++{255, 59, 116}, ++{151, 43, 67}, ++{157, 44, 70}, ++{167, 46, 75}, ++{179, 46, 82}, ++{191, 45, 88}, ++{204, 44, 94}, ++{217, 41, 100}, ++{227, 39, 104}, ++{151, 43, 67}, ++{157, 44, 70}, ++{167, 46, 76}, ++{179, 46, 82}, ++{191, 45, 88}, ++{204, 44, 94}, ++{217, 41, 100}, ++{227, 39, 104}, ++{152, 43, 67}, ++{158, 45, 70}, ++{167, 46, 76}, ++{179, 46, 82}, ++{191, 46, 88}, ++{204, 44, 94}, ++{217, 41, 100}, ++{227, 39, 104}, ++{153, 44, 67}, ++{158, 45, 71}, ++{168, 47, 76}, ++{179, 47, 82}, ++{192, 46, 88}, ++{205, 44, 94}, ++{218, 42, 100}, ++{228, 40, 104}, ++{153, 45, 68}, ++{159, 46, 71}, ++{169, 47, 76}, ++{180, 47, 82}, ++{192, 46, 88}, ++{205, 45, 94}, ++{218, 42, 100}, ++{228, 40, 105}, ++{155, 46, 68}, ++{160, 47, 72}, ++{170, 48, 77}, ++{181, 48, 83}, ++{193, 47, 89}, ++{206, 45, 95}, ++{219, 42, 100}, ++{229, 40, 105}, ++{156, 48, 69}, ++{161, 49, 72}, ++{171, 49, 77}, ++{182, 49, 83}, ++{194, 48, 89}, ++{207, 46, 95}, ++{220, 43, 101}, ++{229, 41, 105}, ++{157, 49, 70}, ++{163, 50, 73}, ++{172, 50, 78}, ++{183, 50, 83}, ++{195, 48, 89}, ++{208, 46, 95}, ++{221, 43, 101}, ++{230, 41, 105}, ++{159, 51, 71}, ++{164, 51, 74}, ++{173, 51, 78}, ++{184, 51, 84}, ++{196, 49, 90}, ++{209, 47, 96}, ++{221, 44, 101}, ++{231, 42, 105}, ++{161, 53, 71}, ++{166, 53, 74}, ++{175, 53, 79}, ++{186, 52, 85}, ++{198, 50, 90}, ++{210, 48, 96}, ++{223, 45, 102}, ++{232, 42, 106}, ++{163, 54, 72}, ++{168, 54, 75}, ++{177, 54, 80}, ++{187, 53, 85}, ++{199, 51, 91}, ++{211, 48, 96}, ++{224, 45, 102}, ++{233, 43, 106}, ++{165, 56, 73}, ++{170, 56, 76}, ++{178, 55, 81}, ++{189, 54, 86}, ++{200, 52, 91}, ++{212, 49, 97}, ++{225, 46, 102}, ++{234, 44, 106}, ++{167, 58, 74}, ++{172, 58, 77}, ++{180, 57, 81}, ++{191, 55, 86}, ++{202, 53, 92}, ++{214, 50, 97}, ++{226, 47, 103}, ++{236, 44, 107}, ++{169, 60, 75}, ++{174, 59, 78}, ++{182, 58, 82}, ++{192, 57, 87}, ++{204, 54, 92}, ++{215, 51, 98}, ++{228, 48, 103}, ++{237, 45, 107}, ++{171, 62, 76}, ++{176, 61, 79}, ++{184, 60, 83}, ++{194, 58, 88}, ++{205, 55, 93}, ++{217, 52, 98}, ++{229, 49, 104}, ++{238, 46, 107}, ++{174, 63, 77}, ++{178, 63, 80}, ++{186, 61, 84}, ++{196, 59, 89}, ++{207, 56, 94}, ++{219, 53, 99}, ++{231, 50, 104}, ++{240, 47, 108}, ++{176, 65, 79}, ++{181, 64, 81}, ++{189, 63, 85}, ++{198, 60, 89}, ++{209, 58, 94}, ++{221, 54, 100}, ++{232, 50, 105}, ++{241, 48, 108}, ++{179, 67, 80}, ++{183, 66, 82}, ++{191, 64, 86}, ++{200, 62, 90}, ++{211, 59, 95}, ++{222, 55, 100}, ++{234, 51, 105}, ++{243, 48, 109}, ++{182, 69, 81}, ++{186, 68, 83}, ++{193, 66, 87}, ++{203, 63, 91}, ++{213, 60, 96}, ++{224, 56, 101}, ++{236, 52, 106}, ++{245, 49, 109}, ++{184, 71, 82}, ++{189, 69, 84}, ++{196, 67, 88}, ++{205, 64, 92}, ++{215, 61, 97}, ++{226, 57, 101}, ++{238, 53, 106}, ++{246, 50, 110}, ++{187, 72, 83}, ++{191, 71, 85}, ++{198, 69, 89}, ++{207, 66, 93}, ++{217, 62, 97}, ++{228, 58, 102}, ++{240, 54, 107}, ++{248, 51, 110}, ++{190, 74, 84}, ++{194, 72, 86}, ++{201, 70, 90}, ++{210, 67, 94}, ++{220, 63, 98}, ++{230, 60, 103}, ++{242, 55, 107}, ++{250, 52, 111}, ++{193, 75, 85}, ++{197, 74, 87}, ++{204, 71, 90}, ++{212, 68, 94}, ++{222, 65, 99}, ++{233, 61, 103}, ++{244, 56, 108}, ++{252, 53, 111}, ++{196, 77, 86}, ++{200, 75, 88}, ++{206, 73, 91}, ++{215, 70, 95}, ++{224, 66, 100}, ++{235, 62, 104}, ++{246, 57, 108}, ++{254, 54, 112}, ++{199, 78, 88}, ++{202, 77, 89}, ++{209, 74, 92}, ++{217, 71, 96}, ++{227, 67, 100}, ++{237, 63, 105}, ++{248, 58, 109}, ++{255, 55, 112}, ++{202, 80, 89}, ++{205, 78, 90}, ++{212, 76, 93}, ++{220, 72, 97}, ++{229, 68, 101}, ++{239, 64, 105}, ++{250, 59, 110}, ++{255, 56, 113}, ++{205, 81, 90}, ++{208, 80, 91}, ++{215, 77, 94}, ++{223, 73, 98}, ++{232, 69, 102}, ++{242, 65, 106}, ++{252, 60, 110}, ++{255, 57, 113}, ++{208, 83, 91}, ++{211, 81, 93}, ++{218, 78, 95}, ++{225, 74, 99}, ++{234, 70, 103}, ++{244, 66, 107}, ++{255, 61, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{213, 82, 93}, ++{219, 79, 96}, ++{227, 75, 99}, ++{236, 71, 103}, ++{245, 66, 107}, ++{255, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{213, 82, 93}, ++{219, 79, 96}, ++{227, 75, 99}, ++{236, 71, 103}, ++{245, 66, 107}, ++{255, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{213, 82, 93}, ++{219, 79, 96}, ++{227, 75, 99}, ++{236, 71, 103}, ++{245, 66, 107}, ++{255, 62, 111}, ++{255, 58, 114}, ++{209, 83, 91}, ++{213, 82, 93}, ++{219, 79, 96}, ++{227, 75, 99}, ++{236, 71, 103}, ++{245, 66, 107}, ++{255, 62, 111}, ++{255, 58, 114}, ++{154, 41, 65}, ++{160, 42, 68}, ++{169, 44, 74}, ++{181, 44, 80}, ++{193, 44, 86}, ++{206, 42, 92}, ++{219, 40, 98}, ++{229, 38, 102}, ++{154, 41, 65}, ++{160, 42, 69}, ++{169, 44, 74}, ++{181, 44, 80}, ++{193, 44, 86}, ++{206, 42, 92}, ++{219, 40, 98}, ++{229, 38, 102}, ++{155, 41, 65}, ++{160, 43, 69}, ++{170, 44, 74}, ++{181, 44, 80}, ++{193, 44, 86}, ++{206, 42, 92}, ++{219, 40, 98}, ++{229, 38, 102}, ++{155, 42, 66}, ++{161, 43, 69}, ++{170, 45, 74}, ++{182, 45, 80}, ++{194, 44, 86}, ++{207, 43, 92}, ++{220, 40, 98}, ++{229, 38, 103}, ++{156, 43, 66}, ++{162, 44, 69}, ++{171, 45, 75}, ++{182, 45, 80}, ++{195, 45, 86}, ++{207, 43, 93}, ++{220, 41, 98}, ++{230, 39, 103}, ++{157, 44, 67}, ++{163, 45, 70}, ++{172, 46, 75}, ++{183, 46, 81}, ++{195, 45, 87}, ++{208, 44, 93}, ++{221, 41, 99}, ++{230, 39, 103}, ++{158, 45, 67}, ++{164, 46, 71}, ++{173, 47, 75}, ++{184, 47, 81}, ++{196, 46, 87}, ++{209, 44, 93}, ++{221, 42, 99}, ++{231, 39, 103}, ++{160, 47, 68}, ++{165, 48, 71}, ++{174, 48, 76}, ++{185, 48, 82}, ++{197, 47, 88}, ++{210, 45, 93}, ++{222, 42, 99}, ++{232, 40, 103}, ++{161, 49, 69}, ++{167, 49, 72}, ++{176, 49, 77}, ++{186, 49, 82}, ++{198, 47, 88}, ++{211, 45, 94}, ++{223, 43, 99}, ++{233, 40, 104}, ++{163, 50, 70}, ++{168, 51, 73}, ++{177, 51, 77}, ++{188, 50, 83}, ++{200, 48, 88}, ++{212, 46, 94}, ++{224, 43, 100}, ++{234, 41, 104}, ++{165, 52, 71}, ++{170, 52, 73}, ++{179, 52, 78}, ++{189, 51, 83}, ++{201, 49, 89}, ++{213, 47, 95}, ++{225, 44, 100}, ++{235, 42, 104}, ++{167, 54, 72}, ++{172, 54, 74}, ++{181, 53, 79}, ++{191, 52, 84}, ++{202, 50, 89}, ++{214, 48, 95}, ++{227, 45, 101}, ++{236, 42, 105}, ++{169, 56, 73}, ++{174, 55, 75}, ++{182, 55, 80}, ++{193, 53, 85}, ++{204, 51, 90}, ++{216, 49, 96}, ++{228, 46, 101}, ++{237, 43, 105}, ++{171, 58, 74}, ++{176, 57, 76}, ++{184, 56, 80}, ++{194, 55, 85}, ++{206, 52, 91}, ++{217, 50, 96}, ++{229, 46, 101}, ++{239, 44, 105}, ++{174, 59, 75}, ++{178, 59, 77}, ++{186, 58, 81}, ++{196, 56, 86}, ++{207, 54, 91}, ++{219, 51, 97}, ++{231, 47, 102}, ++{240, 45, 106}, ++{176, 61, 76}, ++{181, 61, 78}, ++{189, 59, 82}, ++{198, 57, 87}, ++{209, 55, 92}, ++{221, 52, 97}, ++{232, 48, 102}, ++{241, 45, 106}, ++{179, 63, 77}, ++{183, 62, 79}, ++{191, 61, 83}, ++{200, 59, 88}, ++{211, 56, 93}, ++{222, 53, 98}, ++{234, 49, 103}, ++{243, 46, 107}, ++{181, 65, 78}, ++{186, 64, 80}, ++{193, 62, 84}, ++{202, 60, 88}, ++{213, 57, 93}, ++{224, 54, 98}, ++{236, 50, 103}, ++{245, 47, 107}, ++{184, 67, 79}, ++{188, 66, 81}, ++{195, 64, 85}, ++{205, 61, 89}, ++{215, 58, 94}, ++{226, 55, 99}, ++{237, 51, 104}, ++{246, 48, 107}, ++{186, 68, 80}, ++{191, 67, 82}, ++{198, 65, 86}, ++{207, 63, 90}, ++{217, 59, 95}, ++{228, 56, 100}, ++{239, 52, 104}, ++{248, 49, 108}, ++{189, 70, 81}, ++{193, 69, 83}, ++{200, 67, 87}, ++{209, 64, 91}, ++{219, 61, 95}, ++{230, 57, 100}, ++{241, 53, 105}, ++{250, 50, 108}, ++{192, 72, 82}, ++{196, 70, 84}, ++{203, 68, 88}, ++{212, 65, 92}, ++{222, 62, 96}, ++{232, 58, 101}, ++{243, 54, 106}, ++{252, 51, 109}, ++{195, 73, 84}, ++{199, 72, 85}, ++{206, 70, 89}, ++{214, 67, 93}, ++{224, 63, 97}, ++{234, 59, 102}, ++{245, 55, 106}, ++{254, 52, 110}, ++{198, 75, 85}, ++{202, 73, 87}, ++{208, 71, 90}, ++{217, 68, 94}, ++{226, 64, 98}, ++{236, 60, 102}, ++{247, 56, 107}, ++{255, 53, 110}, ++{201, 76, 86}, ++{204, 75, 88}, ++{211, 72, 91}, ++{219, 69, 94}, ++{229, 65, 99}, ++{239, 61, 103}, ++{249, 57, 107}, ++{255, 54, 111}, ++{204, 78, 87}, ++{207, 76, 89}, ++{214, 74, 92}, ++{222, 70, 95}, ++{231, 67, 99}, ++{241, 62, 104}, ++{252, 58, 108}, ++{255, 55, 111}, ++{207, 79, 88}, ++{210, 78, 90}, ++{217, 75, 93}, ++{225, 72, 96}, ++{234, 68, 100}, ++{243, 64, 104}, ++{254, 59, 108}, ++{255, 56, 112}, ++{210, 81, 89}, ++{213, 79, 91}, ++{219, 76, 94}, ++{227, 73, 97}, ++{236, 69, 101}, ++{246, 65, 105}, ++{255, 60, 109}, ++{255, 57, 112}, ++{211, 81, 90}, ++{215, 80, 91}, ++{221, 77, 94}, ++{229, 73, 97}, ++{237, 69, 101}, ++{247, 65, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 80, 91}, ++{221, 77, 94}, ++{229, 73, 97}, ++{237, 69, 101}, ++{247, 65, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 80, 91}, ++{221, 77, 94}, ++{229, 73, 97}, ++{237, 69, 101}, ++{247, 65, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 80, 91}, ++{221, 77, 94}, ++{229, 73, 97}, ++{237, 69, 101}, ++{247, 65, 105}, ++{255, 61, 109}, ++{255, 57, 113}, ++{155, 39, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{155, 40, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 42, 68}, ++{171, 43, 73}, ++{182, 44, 79}, ++{195, 43, 85}, ++{207, 42, 91}, ++{220, 39, 97}, ++{230, 37, 102}, ++{157, 41, 65}, ++{162, 42, 68}, ++{172, 44, 73}, ++{183, 44, 79}, ++{195, 43, 85}, ++{208, 42, 91}, ++{221, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{163, 43, 69}, ++{172, 44, 74}, ++{183, 45, 80}, ++{196, 44, 86}, ++{208, 42, 92}, ++{221, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{164, 44, 69}, ++{173, 45, 74}, ++{184, 45, 80}, ++{196, 44, 86}, ++{209, 43, 92}, ++{222, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{165, 45, 70}, ++{174, 46, 75}, ++{185, 46, 80}, ++{197, 45, 86}, ++{210, 43, 92}, ++{222, 41, 98}, ++{232, 39, 102}, ++{161, 46, 67}, ++{167, 47, 70}, ++{176, 47, 75}, ++{186, 47, 81}, ++{198, 46, 87}, ++{211, 44, 92}, ++{223, 41, 98}, ++{233, 39, 102}, ++{163, 47, 68}, ++{168, 48, 71}, ++{177, 48, 76}, ++{188, 48, 81}, ++{199, 47, 87}, ++{212, 45, 93}, ++{224, 42, 99}, ++{234, 40, 103}, ++{164, 49, 69}, ++{170, 50, 72}, ++{178, 50, 76}, ++{189, 49, 82}, ++{201, 48, 88}, ++{213, 45, 93}, ++{225, 43, 99}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 73}, ++{180, 51, 77}, ++{190, 50, 82}, ++{202, 48, 88}, ++{214, 46, 94}, ++{226, 43, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{173, 53, 73}, ++{182, 52, 78}, ++{192, 51, 83}, ++{203, 49, 89}, ++{215, 47, 94}, ++{228, 44, 100}, ++{237, 42, 104}, ++{170, 55, 72}, ++{175, 54, 74}, ++{184, 54, 79}, ++{194, 53, 84}, ++{205, 51, 89}, ++{217, 48, 95}, ++{229, 45, 100}, ++{238, 42, 104}, ++{173, 56, 73}, ++{177, 56, 75}, ++{185, 55, 79}, ++{195, 54, 84}, ++{206, 52, 90}, ++{218, 49, 95}, ++{230, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 76}, ++{188, 57, 80}, ++{197, 55, 85}, ++{208, 53, 90}, ++{220, 50, 96}, ++{232, 47, 101}, ++{241, 44, 105}, ++{177, 60, 75}, ++{182, 60, 77}, ++{190, 58, 81}, ++{199, 56, 86}, ++{210, 54, 91}, ++{221, 51, 96}, ++{233, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{184, 61, 78}, ++{192, 60, 82}, ++{201, 58, 87}, ++{212, 55, 92}, ++{223, 52, 97}, ++{235, 48, 102}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 79}, ++{194, 61, 83}, ++{203, 59, 88}, ++{214, 56, 92}, ++{225, 53, 97}, ++{237, 49, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{189, 65, 80}, ++{197, 63, 84}, ++{206, 60, 88}, ++{216, 57, 93}, ++{227, 54, 98}, ++{238, 50, 103}, ++{247, 47, 107}, ++{187, 67, 79}, ++{192, 66, 81}, ++{199, 64, 85}, ++{208, 62, 89}, ++{218, 59, 94}, ++{229, 55, 99}, ++{240, 51, 104}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{201, 66, 86}, ++{210, 63, 90}, ++{220, 60, 95}, ++{231, 56, 99}, ++{242, 52, 104}, ++{251, 49, 108}, ++{193, 71, 82}, ++{197, 69, 84}, ++{204, 67, 87}, ++{213, 64, 91}, ++{222, 61, 95}, ++{233, 57, 100}, ++{244, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{200, 71, 85}, ++{207, 69, 88}, ++{215, 66, 92}, ++{225, 62, 96}, ++{235, 58, 101}, ++{246, 54, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{209, 70, 89}, ++{218, 67, 93}, ++{227, 63, 97}, ++{237, 60, 101}, ++{248, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 87}, ++{212, 71, 90}, ++{220, 68, 94}, ++{229, 65, 98}, ++{240, 61, 102}, ++{250, 56, 106}, ++{255, 53, 110}, ++{205, 77, 86}, ++{208, 75, 88}, ++{215, 73, 91}, ++{223, 70, 94}, ++{232, 66, 98}, ++{242, 62, 103}, ++{252, 57, 107}, ++{255, 54, 110}, ++{208, 78, 87}, ++{211, 77, 89}, ++{217, 74, 92}, ++{225, 71, 95}, ++{234, 67, 99}, ++{244, 63, 103}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{220, 75, 93}, ++{228, 72, 96}, ++{237, 68, 100}, ++{247, 64, 104}, ++{255, 59, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{155, 39, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{155, 40, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 42, 68}, ++{171, 43, 73}, ++{182, 44, 79}, ++{195, 43, 85}, ++{207, 42, 91}, ++{220, 39, 97}, ++{230, 37, 102}, ++{157, 41, 65}, ++{162, 42, 68}, ++{172, 44, 73}, ++{183, 44, 79}, ++{195, 43, 85}, ++{208, 42, 91}, ++{221, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{163, 43, 69}, ++{172, 44, 74}, ++{183, 45, 80}, ++{196, 44, 86}, ++{208, 42, 92}, ++{221, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{164, 44, 69}, ++{173, 45, 74}, ++{184, 45, 80}, ++{196, 44, 86}, ++{209, 43, 92}, ++{222, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{165, 45, 70}, ++{174, 46, 75}, ++{185, 46, 80}, ++{197, 45, 86}, ++{210, 43, 92}, ++{222, 41, 98}, ++{232, 39, 102}, ++{161, 46, 67}, ++{167, 47, 70}, ++{176, 47, 75}, ++{186, 47, 81}, ++{198, 46, 87}, ++{211, 44, 92}, ++{223, 41, 98}, ++{233, 39, 102}, ++{163, 47, 68}, ++{168, 48, 71}, ++{177, 48, 76}, ++{188, 48, 81}, ++{199, 47, 87}, ++{212, 45, 93}, ++{224, 42, 99}, ++{234, 40, 103}, ++{164, 49, 69}, ++{170, 50, 72}, ++{178, 50, 76}, ++{189, 49, 82}, ++{201, 48, 88}, ++{213, 45, 93}, ++{225, 43, 99}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 73}, ++{180, 51, 77}, ++{190, 50, 82}, ++{202, 48, 88}, ++{214, 46, 94}, ++{226, 43, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{173, 53, 73}, ++{182, 52, 78}, ++{192, 51, 83}, ++{203, 49, 89}, ++{215, 47, 94}, ++{228, 44, 100}, ++{237, 42, 104}, ++{170, 55, 72}, ++{175, 54, 74}, ++{184, 54, 79}, ++{194, 53, 84}, ++{205, 51, 89}, ++{217, 48, 95}, ++{229, 45, 100}, ++{238, 42, 104}, ++{173, 56, 73}, ++{177, 56, 75}, ++{185, 55, 79}, ++{195, 54, 84}, ++{206, 52, 90}, ++{218, 49, 95}, ++{230, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 76}, ++{188, 57, 80}, ++{197, 55, 85}, ++{208, 53, 90}, ++{220, 50, 96}, ++{232, 47, 101}, ++{241, 44, 105}, ++{177, 60, 75}, ++{182, 60, 77}, ++{190, 58, 81}, ++{199, 56, 86}, ++{210, 54, 91}, ++{221, 51, 96}, ++{233, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{184, 61, 78}, ++{192, 60, 82}, ++{201, 58, 87}, ++{212, 55, 92}, ++{223, 52, 97}, ++{235, 48, 102}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 79}, ++{194, 61, 83}, ++{203, 59, 88}, ++{214, 56, 92}, ++{225, 53, 97}, ++{237, 49, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{189, 65, 80}, ++{197, 63, 84}, ++{206, 60, 88}, ++{216, 57, 93}, ++{227, 54, 98}, ++{238, 50, 103}, ++{247, 47, 107}, ++{187, 67, 79}, ++{192, 66, 81}, ++{199, 64, 85}, ++{208, 62, 89}, ++{218, 59, 94}, ++{229, 55, 99}, ++{240, 51, 104}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{201, 66, 86}, ++{210, 63, 90}, ++{220, 60, 95}, ++{231, 56, 99}, ++{242, 52, 104}, ++{251, 49, 108}, ++{193, 71, 82}, ++{197, 69, 84}, ++{204, 67, 87}, ++{213, 64, 91}, ++{222, 61, 95}, ++{233, 57, 100}, ++{244, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{200, 71, 85}, ++{207, 69, 88}, ++{215, 66, 92}, ++{225, 62, 96}, ++{235, 58, 101}, ++{246, 54, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{209, 70, 89}, ++{218, 67, 93}, ++{227, 63, 97}, ++{237, 60, 101}, ++{248, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 87}, ++{212, 71, 90}, ++{220, 68, 94}, ++{229, 65, 98}, ++{240, 61, 102}, ++{250, 56, 106}, ++{255, 53, 110}, ++{205, 77, 86}, ++{208, 75, 88}, ++{215, 73, 91}, ++{223, 70, 94}, ++{232, 66, 98}, ++{242, 62, 103}, ++{252, 57, 107}, ++{255, 54, 110}, ++{208, 78, 87}, ++{211, 77, 89}, ++{217, 74, 92}, ++{225, 71, 95}, ++{234, 67, 99}, ++{244, 63, 103}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{220, 75, 93}, ++{228, 72, 96}, ++{237, 68, 100}, ++{247, 64, 104}, ++{255, 59, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{155, 39, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{155, 40, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 42, 68}, ++{171, 43, 73}, ++{182, 44, 79}, ++{195, 43, 85}, ++{207, 42, 91}, ++{220, 39, 97}, ++{230, 37, 102}, ++{157, 41, 65}, ++{162, 42, 68}, ++{172, 44, 73}, ++{183, 44, 79}, ++{195, 43, 85}, ++{208, 42, 91}, ++{221, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{163, 43, 69}, ++{172, 44, 74}, ++{183, 45, 80}, ++{196, 44, 86}, ++{208, 42, 92}, ++{221, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{164, 44, 69}, ++{173, 45, 74}, ++{184, 45, 80}, ++{196, 44, 86}, ++{209, 43, 92}, ++{222, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{165, 45, 70}, ++{174, 46, 75}, ++{185, 46, 80}, ++{197, 45, 86}, ++{210, 43, 92}, ++{222, 41, 98}, ++{232, 39, 102}, ++{161, 46, 67}, ++{167, 47, 70}, ++{176, 47, 75}, ++{186, 47, 81}, ++{198, 46, 87}, ++{211, 44, 92}, ++{223, 41, 98}, ++{233, 39, 102}, ++{163, 47, 68}, ++{168, 48, 71}, ++{177, 48, 76}, ++{188, 48, 81}, ++{199, 47, 87}, ++{212, 45, 93}, ++{224, 42, 99}, ++{234, 40, 103}, ++{164, 49, 69}, ++{170, 50, 72}, ++{178, 50, 76}, ++{189, 49, 82}, ++{201, 48, 88}, ++{213, 45, 93}, ++{225, 43, 99}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 73}, ++{180, 51, 77}, ++{190, 50, 82}, ++{202, 48, 88}, ++{214, 46, 94}, ++{226, 43, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{173, 53, 73}, ++{182, 52, 78}, ++{192, 51, 83}, ++{203, 49, 89}, ++{215, 47, 94}, ++{228, 44, 100}, ++{237, 42, 104}, ++{170, 55, 72}, ++{175, 54, 74}, ++{184, 54, 79}, ++{194, 53, 84}, ++{205, 51, 89}, ++{217, 48, 95}, ++{229, 45, 100}, ++{238, 42, 104}, ++{173, 56, 73}, ++{177, 56, 75}, ++{185, 55, 79}, ++{195, 54, 84}, ++{206, 52, 90}, ++{218, 49, 95}, ++{230, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 76}, ++{188, 57, 80}, ++{197, 55, 85}, ++{208, 53, 90}, ++{220, 50, 96}, ++{232, 47, 101}, ++{241, 44, 105}, ++{177, 60, 75}, ++{182, 60, 77}, ++{190, 58, 81}, ++{199, 56, 86}, ++{210, 54, 91}, ++{221, 51, 96}, ++{233, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{184, 61, 78}, ++{192, 60, 82}, ++{201, 58, 87}, ++{212, 55, 92}, ++{223, 52, 97}, ++{235, 48, 102}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 79}, ++{194, 61, 83}, ++{203, 59, 88}, ++{214, 56, 92}, ++{225, 53, 97}, ++{237, 49, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{189, 65, 80}, ++{197, 63, 84}, ++{206, 60, 88}, ++{216, 57, 93}, ++{227, 54, 98}, ++{238, 50, 103}, ++{247, 47, 107}, ++{187, 67, 79}, ++{192, 66, 81}, ++{199, 64, 85}, ++{208, 62, 89}, ++{218, 59, 94}, ++{229, 55, 99}, ++{240, 51, 104}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{201, 66, 86}, ++{210, 63, 90}, ++{220, 60, 95}, ++{231, 56, 99}, ++{242, 52, 104}, ++{251, 49, 108}, ++{193, 71, 82}, ++{197, 69, 84}, ++{204, 67, 87}, ++{213, 64, 91}, ++{222, 61, 95}, ++{233, 57, 100}, ++{244, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{200, 71, 85}, ++{207, 69, 88}, ++{215, 66, 92}, ++{225, 62, 96}, ++{235, 58, 101}, ++{246, 54, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{209, 70, 89}, ++{218, 67, 93}, ++{227, 63, 97}, ++{237, 60, 101}, ++{248, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 87}, ++{212, 71, 90}, ++{220, 68, 94}, ++{229, 65, 98}, ++{240, 61, 102}, ++{250, 56, 106}, ++{255, 53, 110}, ++{205, 77, 86}, ++{208, 75, 88}, ++{215, 73, 91}, ++{223, 70, 94}, ++{232, 66, 98}, ++{242, 62, 103}, ++{252, 57, 107}, ++{255, 54, 110}, ++{208, 78, 87}, ++{211, 77, 89}, ++{217, 74, 92}, ++{225, 71, 95}, ++{234, 67, 99}, ++{244, 63, 103}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{220, 75, 93}, ++{228, 72, 96}, ++{237, 68, 100}, ++{247, 64, 104}, ++{255, 59, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{155, 39, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{155, 40, 64}, ++{161, 41, 68}, ++{171, 43, 73}, ++{182, 43, 79}, ++{194, 43, 85}, ++{207, 41, 91}, ++{220, 39, 97}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 42, 68}, ++{171, 43, 73}, ++{182, 44, 79}, ++{195, 43, 85}, ++{207, 42, 91}, ++{220, 39, 97}, ++{230, 37, 102}, ++{157, 41, 65}, ++{162, 42, 68}, ++{172, 44, 73}, ++{183, 44, 79}, ++{195, 43, 85}, ++{208, 42, 91}, ++{221, 40, 97}, ++{230, 38, 102}, ++{157, 42, 65}, ++{163, 43, 69}, ++{172, 44, 74}, ++{183, 45, 80}, ++{196, 44, 86}, ++{208, 42, 92}, ++{221, 40, 97}, ++{231, 38, 102}, ++{158, 43, 66}, ++{164, 44, 69}, ++{173, 45, 74}, ++{184, 45, 80}, ++{196, 44, 86}, ++{209, 43, 92}, ++{222, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{165, 45, 70}, ++{174, 46, 75}, ++{185, 46, 80}, ++{197, 45, 86}, ++{210, 43, 92}, ++{222, 41, 98}, ++{232, 39, 102}, ++{161, 46, 67}, ++{167, 47, 70}, ++{176, 47, 75}, ++{186, 47, 81}, ++{198, 46, 87}, ++{211, 44, 92}, ++{223, 41, 98}, ++{233, 39, 102}, ++{163, 47, 68}, ++{168, 48, 71}, ++{177, 48, 76}, ++{188, 48, 81}, ++{199, 47, 87}, ++{212, 45, 93}, ++{224, 42, 99}, ++{234, 40, 103}, ++{164, 49, 69}, ++{170, 50, 72}, ++{178, 50, 76}, ++{189, 49, 82}, ++{201, 48, 88}, ++{213, 45, 93}, ++{225, 43, 99}, ++{235, 40, 103}, ++{166, 51, 70}, ++{171, 51, 73}, ++{180, 51, 77}, ++{190, 50, 82}, ++{202, 48, 88}, ++{214, 46, 94}, ++{226, 43, 99}, ++{236, 41, 103}, ++{168, 53, 71}, ++{173, 53, 73}, ++{182, 52, 78}, ++{192, 51, 83}, ++{203, 49, 89}, ++{215, 47, 94}, ++{228, 44, 100}, ++{237, 42, 104}, ++{170, 55, 72}, ++{175, 54, 74}, ++{184, 54, 79}, ++{194, 53, 84}, ++{205, 51, 89}, ++{217, 48, 95}, ++{229, 45, 100}, ++{238, 42, 104}, ++{173, 56, 73}, ++{177, 56, 75}, ++{185, 55, 79}, ++{195, 54, 84}, ++{206, 52, 90}, ++{218, 49, 95}, ++{230, 46, 100}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 76}, ++{188, 57, 80}, ++{197, 55, 85}, ++{208, 53, 90}, ++{220, 50, 96}, ++{232, 47, 101}, ++{241, 44, 105}, ++{177, 60, 75}, ++{182, 60, 77}, ++{190, 58, 81}, ++{199, 56, 86}, ++{210, 54, 91}, ++{221, 51, 96}, ++{233, 48, 101}, ++{242, 45, 105}, ++{180, 62, 76}, ++{184, 61, 78}, ++{192, 60, 82}, ++{201, 58, 87}, ++{212, 55, 92}, ++{223, 52, 97}, ++{235, 48, 102}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 79}, ++{194, 61, 83}, ++{203, 59, 88}, ++{214, 56, 92}, ++{225, 53, 97}, ++{237, 49, 102}, ++{245, 47, 106}, ++{185, 66, 78}, ++{189, 65, 80}, ++{197, 63, 84}, ++{206, 60, 88}, ++{216, 57, 93}, ++{227, 54, 98}, ++{238, 50, 103}, ++{247, 47, 107}, ++{187, 67, 79}, ++{192, 66, 81}, ++{199, 64, 85}, ++{208, 62, 89}, ++{218, 59, 94}, ++{229, 55, 99}, ++{240, 51, 104}, ++{249, 48, 107}, ++{190, 69, 80}, ++{194, 68, 82}, ++{201, 66, 86}, ++{210, 63, 90}, ++{220, 60, 95}, ++{231, 56, 99}, ++{242, 52, 104}, ++{251, 49, 108}, ++{193, 71, 82}, ++{197, 69, 84}, ++{204, 67, 87}, ++{213, 64, 91}, ++{222, 61, 95}, ++{233, 57, 100}, ++{244, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{200, 71, 85}, ++{207, 69, 88}, ++{215, 66, 92}, ++{225, 62, 96}, ++{235, 58, 101}, ++{246, 54, 105}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{209, 70, 89}, ++{218, 67, 93}, ++{227, 63, 97}, ++{237, 60, 101}, ++{248, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{205, 74, 87}, ++{212, 71, 90}, ++{220, 68, 94}, ++{229, 65, 98}, ++{240, 61, 102}, ++{250, 56, 106}, ++{255, 53, 110}, ++{205, 77, 86}, ++{208, 75, 88}, ++{215, 73, 91}, ++{223, 70, 94}, ++{232, 66, 98}, ++{242, 62, 103}, ++{252, 57, 107}, ++{255, 54, 110}, ++{208, 78, 87}, ++{211, 77, 89}, ++{217, 74, 92}, ++{225, 71, 95}, ++{234, 67, 99}, ++{244, 63, 103}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{214, 78, 90}, ++{220, 75, 93}, ++{228, 72, 96}, ++{237, 68, 100}, ++{247, 64, 104}, ++{255, 59, 108}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 79, 90}, ++{222, 76, 93}, ++{229, 73, 97}, ++{238, 69, 100}, ++{248, 64, 104}, ++{255, 60, 109}, ++{255, 57, 112}, ++{82, 104, 120}, ++{94, 99, 125}, ++{111, 92, 131}, ++{128, 86, 136}, ++{146, 79, 141}, ++{163, 72, 146}, ++{179, 66, 150}, ++{189, 62, 152}, ++{82, 104, 120}, ++{94, 99, 125}, ++{111, 93, 131}, ++{128, 86, 136}, ++{146, 79, 141}, ++{163, 72, 146}, ++{179, 66, 150}, ++{189, 62, 152}, ++{83, 104, 120}, ++{95, 100, 125}, ++{111, 93, 131}, ++{129, 86, 136}, ++{146, 79, 141}, ++{163, 73, 146}, ++{180, 66, 150}, ++{190, 63, 152}, ++{84, 105, 121}, ++{96, 100, 125}, ++{112, 93, 131}, ++{129, 86, 136}, ++{147, 79, 141}, ++{164, 73, 146}, ++{180, 67, 150}, ++{190, 63, 152}, ++{86, 106, 121}, ++{98, 101, 126}, ++{113, 94, 131}, ++{130, 87, 136}, ++{147, 80, 141}, ++{164, 73, 146}, ++{181, 67, 150}, ++{191, 63, 152}, ++{88, 107, 122}, ++{99, 101, 126}, ++{115, 94, 131}, ++{132, 87, 137}, ++{149, 80, 141}, ++{165, 74, 146}, ++{181, 67, 150}, ++{191, 63, 152}, ++{90, 108, 122}, ++{101, 102, 126}, ++{117, 95, 132}, ++{133, 88, 137}, ++{150, 81, 141}, ++{166, 74, 146}, ++{182, 68, 150}, ++{192, 64, 152}, ++{93, 109, 123}, ++{104, 103, 127}, ++{118, 96, 132}, ++{135, 89, 137}, ++{151, 81, 142}, ++{167, 75, 146}, ++{183, 68, 150}, ++{193, 64, 152}, ++{96, 109, 124}, ++{106, 104, 127}, ++{121, 97, 132}, ++{136, 89, 137}, ++{153, 82, 142}, ++{169, 75, 146}, ++{185, 69, 150}, ++{194, 65, 152}, ++{99, 110, 124}, ++{109, 105, 128}, ++{123, 98, 133}, ++{138, 90, 137}, ++{154, 83, 142}, ++{170, 76, 146}, ++{186, 69, 150}, ++{195, 65, 152}, ++{102, 111, 125}, ++{112, 106, 128}, ++{125, 98, 133}, ++{140, 91, 138}, ++{156, 84, 142}, ++{172, 77, 146}, ++{187, 70, 150}, ++{197, 66, 152}, ++{105, 112, 126}, ++{115, 107, 129}, ++{128, 99, 133}, ++{143, 92, 138}, ++{158, 84, 142}, ++{173, 77, 146}, ++{189, 70, 150}, ++{198, 66, 152}, ++{109, 113, 127}, ++{118, 108, 130}, ++{130, 100, 134}, ++{145, 93, 138}, ++{160, 85, 142}, ++{175, 78, 146}, ++{190, 71, 150}, ++{200, 67, 152}, ++{112, 114, 127}, ++{121, 108, 130}, ++{133, 101, 134}, ++{147, 93, 138}, ++{162, 86, 142}, ++{177, 79, 146}, ++{192, 72, 150}, ++{201, 68, 152}, ++{116, 115, 128}, ++{124, 109, 131}, ++{136, 102, 134}, ++{150, 94, 139}, ++{164, 87, 143}, ++{179, 79, 147}, ++{194, 73, 150}, ++{203, 68, 152}, ++{120, 115, 129}, ++{128, 110, 131}, ++{139, 103, 135}, ++{153, 95, 139}, ++{167, 88, 143}, ++{181, 80, 147}, ++{196, 73, 150}, ++{205, 69, 153}, ++{124, 116, 129}, ++{131, 111, 132}, ++{142, 104, 135}, ++{155, 96, 139}, ++{169, 88, 143}, ++{183, 81, 147}, ++{198, 74, 150}, ++{207, 70, 153}, ++{127, 117, 130}, ++{135, 112, 132}, ++{145, 104, 136}, ++{158, 97, 139}, ++{172, 89, 143}, ++{186, 82, 147}, ++{200, 75, 151}, ++{209, 71, 153}, ++{131, 117, 131}, ++{138, 112, 133}, ++{149, 105, 136}, ++{161, 98, 140}, ++{174, 90, 143}, ++{188, 83, 147}, ++{202, 76, 151}, ++{211, 71, 153}, ++{135, 118, 131}, ++{142, 113, 133}, ++{152, 106, 136}, ++{164, 98, 140}, ++{177, 91, 144}, ++{191, 84, 147}, ++{204, 77, 151}, ++{213, 72, 153}, ++{139, 118, 132}, ++{145, 114, 134}, ++{155, 107, 137}, ++{167, 99, 140}, ++{180, 92, 144}, ++{193, 84, 147}, ++{207, 77, 151}, ++{215, 73, 153}, ++{143, 119, 132}, ++{149, 114, 134}, ++{159, 108, 137}, ++{170, 100, 141}, ++{183, 93, 144}, ++{196, 85, 148}, ++{209, 78, 151}, ++{217, 74, 153}, ++{147, 119, 133}, ++{153, 115, 135}, ++{162, 108, 138}, ++{173, 101, 141}, ++{185, 93, 144}, ++{198, 86, 148}, ++{211, 79, 151}, ++{220, 75, 153}, ++{151, 120, 134}, ++{157, 115, 135}, ++{166, 109, 138}, ++{176, 102, 141}, ++{188, 94, 145}, ++{201, 87, 148}, ++{214, 80, 151}, ++{222, 75, 153}, ++{155, 120, 134}, ++{160, 116, 136}, ++{169, 110, 139}, ++{180, 102, 142}, ++{191, 95, 145}, ++{204, 88, 148}, ++{216, 81, 151}, ++{224, 76, 153}, ++{159, 121, 135}, ++{164, 116, 136}, ++{173, 110, 139}, ++{183, 103, 142}, ++{194, 96, 145}, ++{206, 88, 148}, ++{219, 81, 152}, ++{227, 77, 153}, ++{163, 121, 135}, ++{168, 117, 137}, ++{176, 111, 139}, ++{186, 104, 142}, ++{197, 97, 145}, ++{209, 89, 148}, ++{221, 82, 152}, ++{229, 78, 154}, ++{167, 121, 136}, ++{172, 117, 137}, ++{180, 111, 140}, ++{190, 104, 143}, ++{200, 97, 146}, ++{212, 90, 149}, ++{224, 83, 152}, ++{232, 79, 154}, ++{169, 122, 136}, ++{174, 118, 138}, ++{182, 112, 140}, ++{191, 105, 143}, ++{202, 98, 146}, ++{214, 90, 149}, ++{225, 83, 152}, ++{233, 79, 154}, ++{169, 122, 136}, ++{174, 118, 138}, ++{182, 112, 140}, ++{191, 105, 143}, ++{202, 98, 146}, ++{214, 90, 149}, ++{225, 83, 152}, ++{233, 79, 154}, ++{169, 122, 136}, ++{174, 118, 138}, ++{182, 112, 140}, ++{191, 105, 143}, ++{202, 98, 146}, ++{214, 90, 149}, ++{225, 83, 152}, ++{233, 79, 154}, ++{169, 122, 136}, ++{174, 118, 138}, ++{182, 112, 140}, ++{191, 105, 143}, ++{202, 98, 146}, ++{214, 90, 149}, ++{225, 83, 152}, ++{233, 79, 154}, ++{83, 103, 119}, ++{95, 98, 124}, ++{111, 92, 130}, ++{129, 85, 135}, ++{146, 79, 140}, ++{163, 72, 145}, ++{180, 66, 149}, ++{190, 62, 151}, ++{83, 103, 119}, ++{95, 98, 124}, ++{112, 92, 130}, ++{129, 85, 135}, ++{146, 79, 140}, ++{163, 72, 145}, ++{180, 66, 149}, ++{190, 62, 151}, ++{84, 104, 119}, ++{96, 99, 124}, ++{112, 92, 130}, ++{129, 86, 135}, ++{147, 79, 140}, ++{164, 72, 145}, ++{180, 66, 149}, ++{190, 62, 151}, ++{85, 104, 119}, ++{97, 99, 124}, ++{113, 93, 130}, ++{130, 86, 135}, ++{147, 79, 140}, ++{164, 73, 145}, ++{180, 66, 149}, ++{191, 63, 151}, ++{87, 105, 120}, ++{99, 100, 124}, ++{114, 93, 130}, ++{131, 86, 135}, ++{148, 80, 140}, ++{165, 73, 145}, ++{181, 67, 149}, ++{191, 63, 151}, ++{89, 106, 121}, ++{100, 101, 125}, ++{116, 94, 130}, ++{132, 87, 136}, ++{149, 80, 140}, ++{166, 73, 145}, ++{182, 67, 149}, ++{192, 63, 151}, ++{91, 107, 121}, ++{102, 102, 125}, ++{117, 95, 131}, ++{134, 87, 136}, ++{150, 81, 141}, ++{167, 74, 145}, ++{183, 67, 149}, ++{193, 64, 151}, ++{94, 108, 122}, ++{104, 102, 126}, ++{119, 95, 131}, ++{135, 88, 136}, ++{152, 81, 141}, ++{168, 74, 145}, ++{184, 68, 149}, ++{194, 64, 151}, ++{97, 109, 123}, ++{107, 103, 126}, ++{121, 96, 131}, ++{137, 89, 136}, ++{153, 82, 141}, ++{169, 75, 145}, ++{185, 68, 149}, ++{195, 64, 152}, ++{100, 110, 123}, ++{110, 104, 127}, ++{123, 97, 132}, ++{139, 90, 136}, ++{155, 82, 141}, ++{171, 76, 145}, ++{186, 69, 149}, ++{196, 65, 152}, ++{103, 111, 124}, ++{112, 105, 127}, ++{126, 98, 132}, ++{141, 90, 137}, ++{157, 83, 141}, ++{172, 76, 145}, ++{188, 70, 149}, ++{197, 66, 152}, ++{106, 112, 125}, ++{115, 106, 128}, ++{128, 99, 132}, ++{143, 91, 137}, ++{158, 84, 141}, ++{174, 77, 145}, ++{189, 70, 149}, ++{199, 66, 152}, ++{110, 112, 126}, ++{118, 107, 129}, ++{131, 100, 133}, ++{145, 92, 137}, ++{161, 85, 141}, ++{176, 78, 146}, ++{191, 71, 149}, ++{200, 67, 152}, ++{113, 113, 126}, ++{122, 108, 129}, ++{134, 101, 133}, ++{148, 93, 137}, ++{163, 86, 142}, ++{178, 78, 146}, ++{193, 72, 150}, ++{202, 68, 152}, ++{117, 114, 127}, ++{125, 109, 130}, ++{137, 102, 134}, ++{150, 94, 138}, ++{165, 86, 142}, ++{180, 79, 146}, ++{194, 72, 150}, ++{203, 68, 152}, ++{121, 115, 128}, ++{128, 110, 130}, ++{140, 102, 134}, ++{153, 95, 138}, ++{167, 87, 142}, ++{182, 80, 146}, ++{196, 73, 150}, ++{205, 69, 152}, ++{124, 115, 128}, ++{132, 110, 131}, ++{143, 103, 134}, ++{156, 96, 138}, ++{170, 88, 142}, ++{184, 81, 146}, ++{198, 74, 150}, ++{207, 70, 152}, ++{128, 116, 129}, ++{135, 111, 131}, ++{146, 104, 135}, ++{159, 96, 139}, ++{172, 89, 143}, ++{186, 82, 146}, ++{200, 75, 150}, ++{209, 70, 152}, ++{132, 117, 130}, ++{139, 112, 132}, ++{149, 105, 135}, ++{162, 97, 139}, ++{175, 90, 143}, ++{189, 83, 146}, ++{202, 75, 150}, ++{211, 71, 152}, ++{136, 117, 130}, ++{142, 112, 133}, ++{153, 106, 136}, ++{165, 98, 139}, ++{177, 91, 143}, ++{191, 83, 147}, ++{205, 76, 150}, ++{213, 72, 152}, ++{140, 118, 131}, ++{146, 113, 133}, ++{156, 106, 136}, ++{168, 99, 140}, ++{180, 91, 143}, ++{193, 84, 147}, ++{207, 77, 150}, ++{215, 73, 152}, ++{143, 118, 132}, ++{150, 114, 134}, ++{159, 107, 137}, ++{171, 100, 140}, ++{183, 92, 143}, ++{196, 85, 147}, ++{209, 78, 150}, ++{218, 74, 152}, ++{147, 119, 132}, ++{153, 114, 134}, ++{163, 108, 137}, ++{174, 101, 140}, ++{186, 93, 144}, ++{199, 86, 147}, ++{212, 79, 151}, ++{220, 74, 153}, ++{151, 119, 133}, ++{157, 115, 135}, ++{166, 109, 137}, ++{177, 101, 141}, ++{189, 94, 144}, ++{201, 87, 147}, ++{214, 80, 151}, ++{222, 75, 153}, ++{155, 120, 133}, ++{161, 115, 135}, ++{170, 109, 138}, ++{180, 102, 141}, ++{192, 95, 144}, ++{204, 87, 148}, ++{217, 80, 151}, ++{225, 76, 153}, ++{159, 120, 134}, ++{165, 116, 136}, ++{173, 110, 138}, ++{183, 103, 141}, ++{195, 96, 144}, ++{207, 88, 148}, ++{219, 81, 151}, ++{227, 77, 153}, ++{163, 121, 135}, ++{168, 117, 136}, ++{177, 110, 139}, ++{187, 103, 142}, ++{198, 96, 145}, ++{210, 89, 148}, ++{222, 82, 151}, ++{230, 78, 153}, ++{167, 121, 135}, ++{172, 117, 137}, ++{180, 111, 139}, ++{190, 104, 142}, ++{201, 97, 145}, ++{212, 90, 148}, ++{224, 83, 151}, ++{232, 78, 153}, ++{169, 121, 135}, ++{174, 117, 137}, ++{182, 111, 139}, ++{192, 104, 142}, ++{202, 97, 145}, ++{214, 90, 148}, ++{226, 83, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{174, 117, 137}, ++{182, 111, 139}, ++{192, 104, 142}, ++{202, 97, 145}, ++{214, 90, 148}, ++{226, 83, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{174, 117, 137}, ++{182, 111, 139}, ++{192, 104, 142}, ++{202, 97, 145}, ++{214, 90, 148}, ++{226, 83, 151}, ++{233, 79, 153}, ++{169, 121, 135}, ++{174, 117, 137}, ++{182, 111, 139}, ++{192, 104, 142}, ++{202, 97, 145}, ++{214, 90, 148}, ++{226, 83, 151}, ++{233, 79, 153}, ++{85, 101, 117}, ++{97, 97, 122}, ++{113, 91, 128}, ++{130, 85, 134}, ++{147, 78, 139}, ++{164, 72, 143}, ++{180, 66, 148}, ++{190, 62, 150}, ++{85, 102, 117}, ++{97, 97, 122}, ++{113, 91, 128}, ++{130, 85, 134}, ++{147, 78, 139}, ++{164, 72, 143}, ++{181, 66, 148}, ++{191, 62, 150}, ++{86, 102, 117}, ++{98, 98, 122}, ++{114, 91, 128}, ++{131, 85, 134}, ++{148, 78, 139}, ++{164, 72, 143}, ++{181, 66, 148}, ++{191, 62, 150}, ++{87, 103, 118}, ++{99, 98, 122}, ++{114, 92, 128}, ++{131, 85, 134}, ++{148, 79, 139}, ++{165, 72, 143}, ++{181, 66, 148}, ++{191, 62, 150}, ++{89, 103, 118}, ++{100, 99, 123}, ++{116, 92, 128}, ++{132, 86, 134}, ++{149, 79, 139}, ++{166, 73, 144}, ++{182, 66, 148}, ++{192, 63, 150}, ++{91, 104, 119}, ++{102, 100, 123}, ++{117, 93, 129}, ++{133, 86, 134}, ++{150, 79, 139}, ++{167, 73, 144}, ++{183, 67, 148}, ++{193, 63, 150}, ++{93, 105, 119}, ++{104, 100, 124}, ++{119, 94, 129}, ++{135, 87, 134}, ++{151, 80, 139}, ++{168, 73, 144}, ++{184, 67, 148}, ++{193, 63, 150}, ++{96, 106, 120}, ++{106, 101, 124}, ++{120, 95, 129}, ++{136, 88, 134}, ++{153, 81, 139}, ++{169, 74, 144}, ++{185, 68, 148}, ++{194, 64, 150}, ++{98, 107, 121}, ++{108, 102, 125}, ++{123, 95, 130}, ++{138, 88, 135}, ++{154, 81, 139}, ++{170, 75, 144}, ++{186, 68, 148}, ++{195, 64, 150}, ++{101, 108, 122}, ++{111, 103, 125}, ++{125, 96, 130}, ++{140, 89, 135}, ++{156, 82, 140}, ++{171, 75, 144}, ++{187, 69, 148}, ++{197, 65, 150}, ++{104, 109, 122}, ++{114, 104, 126}, ++{127, 97, 130}, ++{142, 90, 135}, ++{158, 83, 140}, ++{173, 76, 144}, ++{188, 69, 148}, ++{198, 65, 151}, ++{108, 110, 123}, ++{117, 105, 126}, ++{130, 98, 131}, ++{144, 91, 135}, ++{159, 83, 140}, ++{175, 77, 144}, ++{190, 70, 148}, ++{199, 66, 151}, ++{111, 111, 124}, ++{120, 106, 127}, ++{132, 99, 131}, ++{147, 92, 136}, ++{161, 84, 140}, ++{177, 77, 144}, ++{192, 71, 148}, ++{201, 67, 151}, ++{115, 112, 125}, ++{123, 107, 128}, ++{135, 100, 132}, ++{149, 92, 136}, ++{164, 85, 140}, ++{178, 78, 145}, ++{193, 71, 148}, ++{202, 67, 151}, ++{118, 113, 125}, ++{126, 108, 128}, ++{138, 101, 132}, ++{151, 93, 136}, ++{166, 86, 141}, ++{180, 79, 145}, ++{195, 72, 149}, ++{204, 68, 151}, ++{122, 114, 126}, ++{129, 109, 129}, ++{141, 102, 133}, ++{154, 94, 137}, ++{168, 87, 141}, ++{183, 80, 145}, ++{197, 73, 149}, ++{206, 69, 151}, ++{125, 114, 127}, ++{133, 109, 129}, ++{144, 103, 133}, ++{157, 95, 137}, ++{171, 88, 141}, ++{185, 80, 145}, ++{199, 74, 149}, ++{208, 69, 151}, ++{129, 115, 128}, ++{136, 110, 130}, ++{147, 103, 134}, ++{160, 96, 137}, ++{173, 88, 141}, ++{187, 81, 145}, ++{201, 74, 149}, ++{210, 70, 151}, ++{133, 116, 128}, ++{140, 111, 131}, ++{150, 104, 134}, ++{162, 97, 138}, ++{176, 89, 142}, ++{189, 82, 145}, ++{203, 75, 149}, ++{212, 71, 151}, ++{137, 116, 129}, ++{143, 112, 131}, ++{153, 105, 134}, ++{165, 98, 138}, ++{178, 90, 142}, ++{192, 83, 146}, ++{205, 76, 149}, ++{214, 72, 151}, ++{141, 117, 130}, ++{147, 112, 132}, ++{157, 106, 135}, ++{168, 98, 138}, ++{181, 91, 142}, ++{194, 84, 146}, ++{208, 77, 149}, ++{216, 73, 151}, ++{144, 118, 130}, ++{151, 113, 132}, ++{160, 106, 135}, ++{171, 99, 139}, ++{184, 92, 142}, ++{197, 85, 146}, ++{210, 78, 149}, ++{218, 73, 152}, ++{148, 118, 131}, ++{154, 114, 133}, ++{164, 107, 136}, ++{175, 100, 139}, ++{187, 93, 143}, ++{199, 85, 146}, ++{212, 78, 150}, ++{220, 74, 152}, ++{152, 119, 132}, ++{158, 114, 134}, ++{167, 108, 136}, ++{178, 101, 140}, ++{190, 93, 143}, ++{202, 86, 146}, ++{215, 79, 150}, ++{223, 75, 152}, ++{156, 119, 132}, ++{162, 115, 134}, ++{170, 109, 137}, ++{181, 102, 140}, ++{192, 94, 143}, ++{205, 87, 147}, ++{217, 80, 150}, ++{225, 76, 152}, ++{160, 119, 133}, ++{165, 115, 135}, ++{174, 109, 137}, ++{184, 102, 140}, ++{195, 95, 143}, ++{207, 88, 147}, ++{220, 81, 150}, ++{228, 77, 152}, ++{164, 120, 134}, ++{169, 116, 135}, ++{177, 110, 138}, ++{187, 103, 141}, ++{198, 96, 144}, ++{210, 89, 147}, ++{222, 82, 150}, ++{230, 77, 152}, ++{168, 120, 134}, ++{173, 116, 136}, ++{181, 110, 138}, ++{191, 104, 141}, ++{202, 97, 144}, ++{213, 89, 147}, ++{225, 82, 150}, ++{233, 78, 152}, ++{170, 120, 134}, ++{175, 117, 136}, ++{183, 111, 138}, ++{192, 104, 141}, ++{203, 97, 144}, ++{215, 90, 147}, ++{226, 83, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{175, 117, 136}, ++{183, 111, 138}, ++{192, 104, 141}, ++{203, 97, 144}, ++{215, 90, 147}, ++{226, 83, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{175, 117, 136}, ++{183, 111, 138}, ++{192, 104, 141}, ++{203, 97, 144}, ++{215, 90, 147}, ++{226, 83, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{175, 117, 136}, ++{183, 111, 138}, ++{192, 104, 141}, ++{203, 97, 144}, ++{215, 90, 147}, ++{226, 83, 151}, ++{234, 79, 152}, ++{87, 99, 115}, ++{99, 96, 120}, ++{115, 90, 126}, ++{131, 84, 132}, ++{148, 77, 137}, ++{165, 71, 142}, ++{181, 65, 146}, ++{191, 61, 149}, ++{87, 100, 115}, ++{99, 96, 120}, ++{115, 90, 126}, ++{132, 84, 132}, ++{149, 78, 137}, ++{165, 71, 142}, ++{182, 65, 146}, ++{191, 61, 149}, ++{88, 100, 115}, ++{100, 96, 120}, ++{115, 90, 126}, ++{132, 84, 132}, ++{149, 78, 137}, ++{166, 71, 142}, ++{182, 65, 146}, ++{192, 62, 149}, ++{89, 101, 115}, ++{101, 97, 120}, ++{116, 91, 126}, ++{133, 84, 132}, ++{150, 78, 137}, ++{166, 72, 142}, ++{182, 66, 146}, ++{192, 62, 149}, ++{91, 102, 116}, ++{102, 97, 120}, ++{117, 91, 126}, ++{134, 85, 132}, ++{150, 78, 137}, ++{167, 72, 142}, ++{183, 66, 146}, ++{193, 62, 149}, ++{93, 102, 116}, ++{104, 98, 121}, ++{119, 92, 127}, ++{135, 85, 132}, ++{151, 79, 137}, ++{168, 72, 142}, ++{184, 66, 146}, ++{193, 62, 149}, ++{95, 104, 117}, ++{106, 99, 121}, ++{120, 93, 127}, ++{136, 86, 132}, ++{153, 79, 137}, ++{169, 73, 142}, ++{185, 67, 146}, ++{194, 63, 149}, ++{98, 105, 118}, ++{108, 100, 122}, ++{122, 93, 127}, ++{138, 87, 133}, ++{154, 80, 138}, ++{170, 73, 142}, ++{186, 67, 146}, ++{195, 63, 149}, ++{100, 106, 119}, ++{110, 101, 123}, ++{124, 94, 128}, ++{139, 87, 133}, ++{155, 81, 138}, ++{171, 74, 142}, ++{187, 68, 147}, ++{196, 64, 149}, ++{103, 107, 119}, ++{113, 102, 123}, ++{126, 95, 128}, ++{141, 88, 133}, ++{157, 81, 138}, ++{173, 75, 142}, ++{188, 68, 147}, ++{198, 64, 149}, ++{106, 108, 120}, ++{115, 103, 124}, ++{129, 96, 129}, ++{143, 89, 133}, ++{159, 82, 138}, ++{174, 75, 143}, ++{189, 69, 147}, ++{199, 65, 149}, ++{109, 109, 121}, ++{118, 104, 124}, ++{131, 97, 129}, ++{145, 90, 134}, ++{161, 83, 138}, ++{176, 76, 143}, ++{191, 69, 147}, ++{200, 65, 149}, ++{113, 110, 122}, ++{121, 105, 125}, ++{134, 98, 129}, ++{148, 91, 134}, ++{163, 84, 139}, ++{178, 77, 143}, ++{192, 70, 147}, ++{202, 66, 149}, ++{116, 111, 123}, ++{124, 106, 126}, ++{136, 99, 130}, ++{150, 92, 134}, ++{165, 84, 139}, ++{179, 78, 143}, ++{194, 71, 147}, ++{203, 67, 149}, ++{120, 112, 124}, ++{128, 107, 126}, ++{139, 100, 130}, ++{153, 93, 135}, ++{167, 85, 139}, ++{181, 78, 143}, ++{196, 72, 147}, ++{205, 68, 150}, ++{123, 112, 124}, ++{131, 108, 127}, ++{142, 101, 131}, ++{155, 93, 135}, ++{169, 86, 139}, ++{183, 79, 143}, ++{198, 72, 147}, ++{207, 68, 150}, ++{127, 113, 125}, ++{134, 108, 128}, ++{145, 102, 131}, ++{158, 94, 136}, ++{172, 87, 140}, ++{186, 80, 144}, ++{200, 73, 147}, ++{209, 69, 150}, ++{131, 114, 126}, ++{138, 109, 128}, ++{148, 102, 132}, ++{161, 95, 136}, ++{174, 88, 140}, ++{188, 81, 144}, ++{202, 74, 148}, ++{211, 70, 150}, ++{134, 115, 127}, ++{141, 110, 129}, ++{151, 103, 132}, ++{164, 96, 136}, ++{177, 89, 140}, ++{190, 82, 144}, ++{204, 75, 148}, ++{213, 71, 150}, ++{138, 115, 127}, ++{145, 111, 130}, ++{155, 104, 133}, ++{166, 97, 137}, ++{179, 90, 140}, ++{193, 82, 144}, ++{206, 76, 148}, ++{215, 71, 150}, ++{142, 116, 128}, ++{148, 111, 130}, ++{158, 105, 133}, ++{169, 98, 137}, ++{182, 90, 141}, ++{195, 83, 144}, ++{208, 76, 148}, ++{217, 72, 150}, ++{146, 116, 129}, ++{152, 112, 131}, ++{161, 106, 134}, ++{172, 99, 137}, ++{185, 91, 141}, ++{198, 84, 145}, ++{211, 77, 148}, ++{219, 73, 150}, ++{150, 117, 130}, ++{155, 113, 131}, ++{165, 106, 134}, ++{176, 99, 138}, ++{188, 92, 141}, ++{200, 85, 145}, ++{213, 78, 148}, ++{221, 74, 151}, ++{153, 118, 130}, ++{159, 113, 132}, ++{168, 107, 135}, ++{179, 100, 138}, ++{190, 93, 142}, ++{203, 86, 145}, ++{216, 79, 149}, ++{224, 75, 151}, ++{157, 118, 131}, ++{163, 114, 133}, ++{171, 108, 135}, ++{182, 101, 139}, ++{193, 94, 142}, ++{206, 87, 145}, ++{218, 80, 149}, ++{226, 75, 151}, ++{161, 119, 132}, ++{167, 115, 133}, ++{175, 108, 136}, ++{185, 102, 139}, ++{196, 95, 142}, ++{208, 87, 146}, ++{221, 80, 149}, ++{228, 76, 151}, ++{165, 119, 132}, ++{170, 115, 134}, ++{178, 109, 136}, ++{188, 102, 139}, ++{199, 95, 143}, ++{211, 88, 146}, ++{223, 81, 149}, ++{231, 77, 151}, ++{169, 119, 133}, ++{174, 116, 134}, ++{182, 110, 137}, ++{192, 103, 140}, ++{202, 96, 143}, ++{214, 89, 146}, ++{226, 82, 149}, ++{233, 78, 151}, ++{171, 120, 133}, ++{176, 116, 135}, ++{184, 110, 137}, ++{193, 103, 140}, ++{204, 96, 143}, ++{215, 89, 146}, ++{227, 82, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{176, 116, 135}, ++{184, 110, 137}, ++{193, 103, 140}, ++{204, 96, 143}, ++{215, 89, 146}, ++{227, 82, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{176, 116, 135}, ++{184, 110, 137}, ++{193, 103, 140}, ++{204, 96, 143}, ++{215, 89, 146}, ++{227, 82, 149}, ++{235, 78, 151}, ++{171, 120, 133}, ++{176, 116, 135}, ++{184, 110, 137}, ++{193, 103, 140}, ++{204, 96, 143}, ++{215, 89, 146}, ++{227, 82, 149}, ++{235, 78, 151}, ++{89, 97, 112}, ++{101, 94, 117}, ++{116, 89, 123}, ++{133, 83, 129}, ++{150, 77, 135}, ++{166, 71, 140}, ++{183, 65, 145}, ++{192, 61, 147}, ++{90, 97, 112}, ++{101, 94, 117}, ++{117, 89, 124}, ++{133, 83, 130}, ++{150, 77, 135}, ++{167, 71, 140}, ++{183, 65, 145}, ++{193, 61, 147}, ++{91, 98, 113}, ++{102, 94, 117}, ++{117, 89, 124}, ++{134, 83, 130}, ++{150, 77, 135}, ++{167, 71, 140}, ++{183, 65, 145}, ++{193, 61, 147}, ++{92, 99, 113}, ++{103, 95, 118}, ++{118, 90, 124}, ++{134, 83, 130}, ++{151, 77, 135}, ++{167, 71, 140}, ++{183, 65, 145}, ++{193, 61, 147}, ++{93, 99, 114}, ++{104, 96, 118}, ++{119, 90, 124}, ++{135, 84, 130}, ++{152, 78, 135}, ++{168, 71, 140}, ++{184, 65, 145}, ++{194, 62, 147}, ++{95, 100, 114}, ++{106, 96, 119}, ++{120, 91, 124}, ++{136, 84, 130}, ++{153, 78, 135}, ++{169, 72, 140}, ++{185, 66, 145}, ++{195, 62, 147}, ++{97, 102, 115}, ++{108, 97, 119}, ++{122, 91, 125}, ++{138, 85, 130}, ++{154, 79, 136}, ++{170, 72, 140}, ++{186, 66, 145}, ++{195, 62, 147}, ++{100, 103, 116}, ++{110, 98, 120}, ++{124, 92, 125}, ++{139, 86, 131}, ++{155, 79, 136}, ++{171, 73, 140}, ++{187, 67, 145}, ++{196, 63, 147}, ++{102, 104, 116}, ++{112, 99, 120}, ++{126, 93, 126}, ++{141, 86, 131}, ++{157, 80, 136}, ++{172, 73, 141}, ++{188, 67, 145}, ++{197, 63, 148}, ++{105, 105, 117}, ++{115, 100, 121}, ++{128, 94, 126}, ++{143, 87, 131}, ++{158, 81, 136}, ++{174, 74, 141}, ++{189, 68, 145}, ++{199, 64, 148}, ++{108, 106, 118}, ++{117, 101, 122}, ++{130, 95, 126}, ++{145, 88, 132}, ++{160, 81, 136}, ++{175, 75, 141}, ++{190, 68, 145}, ++{200, 64, 148}, ++{111, 107, 119}, ++{120, 102, 122}, ++{133, 96, 127}, ++{147, 89, 132}, ++{162, 82, 137}, ++{177, 75, 141}, ++{192, 69, 145}, ++{201, 65, 148}, ++{115, 108, 120}, ++{123, 103, 123}, ++{135, 97, 128}, ++{149, 90, 132}, ++{164, 83, 137}, ++{179, 76, 141}, ++{194, 70, 145}, ++{203, 66, 148}, ++{118, 109, 121}, ++{126, 104, 124}, ++{138, 98, 128}, ++{152, 91, 133}, ++{166, 84, 137}, ++{181, 77, 141}, ++{195, 70, 146}, ++{204, 66, 148}, ++{121, 110, 122}, ++{129, 105, 124}, ++{141, 99, 129}, ++{154, 92, 133}, ++{168, 85, 137}, ++{183, 78, 142}, ++{197, 71, 146}, ++{206, 67, 148}, ++{125, 111, 122}, ++{132, 106, 125}, ++{144, 100, 129}, ++{157, 93, 133}, ++{170, 85, 138}, ++{185, 79, 142}, ++{199, 72, 146}, ++{208, 68, 148}, ++{129, 112, 123}, ++{136, 107, 126}, ++{147, 101, 130}, ++{159, 93, 134}, ++{173, 86, 138}, ++{187, 79, 142}, ++{201, 73, 146}, ++{210, 69, 148}, ++{132, 113, 124}, ++{139, 108, 127}, ++{150, 101, 130}, ++{162, 94, 134}, ++{175, 87, 138}, ++{189, 80, 142}, ++{203, 73, 146}, ++{212, 69, 148}, ++{136, 113, 125}, ++{143, 109, 127}, ++{153, 102, 131}, ++{165, 95, 135}, ++{178, 88, 139}, ++{191, 81, 143}, ++{205, 74, 146}, ++{214, 70, 149}, ++{140, 114, 126}, ++{146, 110, 128}, ++{156, 103, 131}, ++{168, 96, 135}, ++{180, 89, 139}, ++{194, 82, 143}, ++{207, 75, 147}, ++{216, 71, 149}, ++{143, 115, 126}, ++{150, 110, 129}, ++{159, 104, 132}, ++{171, 97, 135}, ++{183, 90, 139}, ++{196, 83, 143}, ++{209, 76, 147}, ++{218, 72, 149}, ++{147, 115, 127}, ++{153, 111, 129}, ++{162, 105, 132}, ++{174, 98, 136}, ++{186, 91, 140}, ++{199, 84, 143}, ++{212, 77, 147}, ++{220, 72, 149}, ++{151, 116, 128}, ++{157, 112, 130}, ++{166, 106, 133}, ++{177, 99, 136}, ++{189, 91, 140}, ++{201, 84, 144}, ++{214, 77, 147}, ++{222, 73, 149}, ++{155, 116, 129}, ++{160, 112, 130}, ++{169, 106, 133}, ++{180, 99, 137}, ++{191, 92, 140}, ++{204, 85, 144}, ++{216, 78, 147}, ++{224, 74, 149}, ++{159, 117, 129}, ++{164, 113, 131}, ++{173, 107, 134}, ++{183, 100, 137}, ++{194, 93, 141}, ++{206, 86, 144}, ++{219, 79, 147}, ++{227, 75, 150}, ++{162, 118, 130}, ++{168, 114, 132}, ++{176, 108, 134}, ++{186, 101, 138}, ++{197, 94, 141}, ++{209, 87, 144}, ++{221, 80, 148}, ++{229, 76, 150}, ++{166, 118, 131}, ++{171, 114, 132}, ++{180, 108, 135}, ++{189, 102, 138}, ++{200, 95, 141}, ++{212, 88, 145}, ++{224, 81, 148}, ++{232, 77, 150}, ++{170, 118, 131}, ++{175, 115, 133}, ++{183, 109, 135}, ++{193, 102, 138}, ++{203, 95, 142}, ++{215, 88, 145}, ++{227, 82, 148}, ++{234, 77, 150}, ++{172, 119, 132}, ++{177, 115, 133}, ++{185, 109, 136}, ++{194, 103, 139}, ++{205, 96, 142}, ++{216, 89, 145}, ++{228, 82, 148}, ++{235, 78, 150}, ++{172, 119, 132}, ++{177, 115, 133}, ++{185, 109, 136}, ++{194, 103, 139}, ++{205, 96, 142}, ++{216, 89, 145}, ++{228, 82, 148}, ++{235, 78, 150}, ++{172, 119, 132}, ++{177, 115, 133}, ++{185, 109, 136}, ++{194, 103, 139}, ++{205, 96, 142}, ++{216, 89, 145}, ++{228, 82, 148}, ++{235, 78, 150}, ++{172, 119, 132}, ++{177, 115, 133}, ++{185, 109, 136}, ++{194, 103, 139}, ++{205, 96, 142}, ++{216, 89, 145}, ++{228, 82, 148}, ++{235, 78, 150}, ++{92, 95, 110}, ++{103, 92, 115}, ++{118, 87, 121}, ++{135, 82, 127}, ++{151, 76, 133}, ++{168, 70, 138}, ++{184, 64, 143}, ++{194, 60, 145}, ++{92, 95, 110}, ++{103, 92, 115}, ++{119, 87, 121}, ++{135, 82, 127}, ++{152, 76, 133}, ++{168, 70, 138}, ++{184, 64, 143}, ++{194, 60, 145}, ++{93, 96, 110}, ++{104, 93, 115}, ++{119, 88, 121}, ++{135, 82, 127}, ++{152, 76, 133}, ++{168, 70, 138}, ++{184, 64, 143}, ++{194, 61, 145}, ++{94, 96, 111}, ++{105, 93, 115}, ++{120, 88, 121}, ++{136, 82, 128}, ++{153, 76, 133}, ++{169, 70, 138}, ++{185, 64, 143}, ++{194, 61, 146}, ++{96, 97, 111}, ++{106, 94, 116}, ++{121, 89, 122}, ++{137, 83, 128}, ++{153, 77, 133}, ++{169, 71, 138}, ++{185, 65, 143}, ++{195, 61, 146}, ++{98, 98, 112}, ++{108, 95, 116}, ++{122, 89, 122}, ++{138, 83, 128}, ++{154, 77, 133}, ++{170, 71, 138}, ++{186, 65, 143}, ++{196, 61, 146}, ++{100, 99, 112}, ++{110, 96, 117}, ++{124, 90, 122}, ++{139, 84, 128}, ++{155, 78, 134}, ++{171, 72, 138}, ++{187, 66, 143}, ++{197, 62, 146}, ++{102, 100, 113}, ++{112, 97, 117}, ++{126, 91, 123}, ++{141, 85, 128}, ++{157, 78, 134}, ++{172, 72, 139}, ++{188, 66, 143}, ++{197, 62, 146}, ++{105, 102, 114}, ++{114, 98, 118}, ++{128, 92, 123}, ++{143, 85, 129}, ++{158, 79, 134}, ++{174, 73, 139}, ++{189, 67, 143}, ++{199, 63, 146}, ++{107, 103, 115}, ++{117, 99, 119}, ++{130, 93, 124}, ++{144, 86, 129}, ++{160, 80, 134}, ++{175, 73, 139}, ++{190, 67, 143}, ++{200, 63, 146}, ++{110, 104, 116}, ++{119, 100, 119}, ++{132, 94, 124}, ++{146, 87, 129}, ++{161, 80, 134}, ++{177, 74, 139}, ++{192, 68, 143}, ++{201, 64, 146}, ++{113, 105, 117}, ++{122, 101, 120}, ++{134, 95, 125}, ++{148, 88, 130}, ++{163, 81, 135}, ++{178, 75, 139}, ++{193, 68, 144}, ++{202, 64, 146}, ++{117, 106, 118}, ++{125, 102, 121}, ++{137, 96, 125}, ++{151, 89, 130}, ++{165, 82, 135}, ++{180, 75, 139}, ++{195, 69, 144}, ++{204, 65, 146}, ++{120, 107, 119}, ++{128, 103, 122}, ++{140, 97, 126}, ++{153, 90, 131}, ++{167, 83, 135}, ++{182, 76, 140}, ++{196, 70, 144}, ++{205, 66, 146}, ++{123, 108, 119}, ++{131, 104, 122}, ++{142, 98, 127}, ++{155, 91, 131}, ++{169, 84, 136}, ++{184, 77, 140}, ++{198, 70, 144}, ++{207, 67, 147}, ++{127, 109, 120}, ++{134, 105, 123}, ++{145, 98, 127}, ++{158, 92, 131}, ++{172, 85, 136}, ++{186, 78, 140}, ++{200, 71, 144}, ++{209, 67, 147}, ++{130, 110, 121}, ++{137, 106, 124}, ++{148, 99, 128}, ++{161, 92, 132}, ++{174, 85, 136}, ++{188, 79, 140}, ++{202, 72, 144}, ++{211, 68, 147}, ++{134, 111, 122}, ++{141, 107, 125}, ++{151, 100, 128}, ++{163, 93, 132}, ++{177, 86, 137}, ++{190, 79, 141}, ++{204, 73, 145}, ++{213, 69, 147}, ++{138, 112, 123}, ++{144, 107, 125}, ++{154, 101, 129}, ++{166, 94, 133}, ++{179, 87, 137}, ++{192, 80, 141}, ++{206, 74, 145}, ++{215, 70, 147}, ++{141, 113, 124}, ++{148, 108, 126}, ++{157, 102, 129}, ++{169, 95, 133}, ++{182, 88, 137}, ++{195, 81, 141}, ++{208, 74, 145}, ++{217, 70, 147}, ++{145, 113, 125}, ++{151, 109, 127}, ++{161, 103, 130}, ++{172, 96, 134}, ++{184, 89, 138}, ++{197, 82, 141}, ++{210, 75, 145}, ++{219, 71, 148}, ++{149, 114, 125}, ++{155, 110, 127}, ++{164, 104, 131}, ++{175, 97, 134}, ++{187, 90, 138}, ++{200, 83, 142}, ++{213, 76, 145}, ++{221, 72, 148}, ++{152, 115, 126}, ++{158, 111, 128}, ++{167, 105, 131}, ++{178, 98, 135}, ++{190, 91, 138}, ++{202, 84, 142}, ++{215, 77, 146}, ++{223, 73, 148}, ++{156, 115, 127}, ++{162, 111, 129}, ++{171, 105, 132}, ++{181, 99, 135}, ++{193, 92, 139}, ++{205, 85, 142}, ++{217, 78, 146}, ++{225, 74, 148}, ++{160, 116, 128}, ++{165, 112, 129}, ++{174, 106, 132}, ++{184, 99, 136}, ++{196, 92, 139}, ++{208, 85, 143}, ++{220, 79, 146}, ++{228, 74, 148}, ++{164, 116, 128}, ++{169, 112, 130}, ++{177, 107, 133}, ++{187, 100, 136}, ++{198, 93, 139}, ++{210, 86, 143}, ++{222, 79, 146}, ++{230, 75, 148}, ++{168, 117, 129}, ++{173, 113, 131}, ++{181, 107, 133}, ++{191, 101, 136}, ++{201, 94, 140}, ++{213, 87, 143}, ++{225, 80, 147}, ++{233, 76, 149}, ++{171, 117, 130}, ++{176, 114, 131}, ++{184, 108, 134}, ++{194, 102, 137}, ++{204, 95, 140}, ++{216, 88, 143}, ++{228, 81, 147}, ++{235, 77, 149}, ++{173, 118, 130}, ++{178, 114, 132}, ++{186, 108, 134}, ++{195, 102, 137}, ++{206, 95, 140}, ++{217, 88, 144}, ++{229, 81, 147}, ++{236, 77, 149}, ++{173, 118, 130}, ++{178, 114, 132}, ++{186, 108, 134}, ++{195, 102, 137}, ++{206, 95, 140}, ++{217, 88, 144}, ++{229, 81, 147}, ++{236, 77, 149}, ++{173, 118, 130}, ++{178, 114, 132}, ++{186, 108, 134}, ++{195, 102, 137}, ++{206, 95, 140}, ++{217, 88, 144}, ++{229, 81, 147}, ++{236, 77, 149}, ++{173, 118, 130}, ++{178, 114, 132}, ++{186, 108, 134}, ++{195, 102, 137}, ++{206, 95, 140}, ++{217, 88, 144}, ++{229, 81, 147}, ++{236, 77, 149}, ++{95, 92, 107}, ++{106, 90, 112}, ++{121, 86, 119}, ++{137, 80, 125}, ++{153, 75, 131}, ++{169, 69, 136}, ++{185, 63, 141}, ++{195, 60, 144}, ++{95, 93, 107}, ++{106, 90, 112}, ++{121, 86, 119}, ++{137, 81, 125}, ++{153, 75, 131}, ++{169, 69, 136}, ++{185, 63, 141}, ++{195, 60, 144}, ++{96, 93, 108}, ++{106, 91, 113}, ++{121, 86, 119}, ++{137, 81, 125}, ++{154, 75, 131}, ++{170, 69, 136}, ++{186, 64, 141}, ++{195, 60, 144}, ++{97, 94, 108}, ++{107, 91, 113}, ++{122, 87, 119}, ++{138, 81, 125}, ++{154, 75, 131}, ++{170, 70, 136}, ++{186, 64, 141}, ++{196, 60, 144}, ++{98, 95, 109}, ++{109, 92, 113}, ++{123, 87, 119}, ++{139, 82, 125}, ++{155, 76, 131}, ++{171, 70, 136}, ++{187, 64, 141}, ++{196, 60, 144}, ++{100, 96, 109}, ++{110, 93, 114}, ++{124, 88, 120}, ++{140, 82, 126}, ++{156, 76, 131}, ++{172, 70, 136}, ++{187, 64, 141}, ++{197, 61, 144}, ++{102, 97, 110}, ++{112, 94, 114}, ++{126, 89, 120}, ++{141, 83, 126}, ++{157, 77, 131}, ++{173, 71, 136}, ++{188, 65, 141}, ++{198, 61, 144}, ++{105, 98, 111}, ++{114, 95, 115}, ++{128, 89, 121}, ++{143, 83, 126}, ++{158, 77, 132}, ++{174, 71, 137}, ++{189, 65, 141}, ++{199, 62, 144}, ++{107, 99, 112}, ++{116, 96, 116}, ++{130, 90, 121}, ++{144, 84, 127}, ++{160, 78, 132}, ++{175, 72, 137}, ++{190, 66, 141}, ++{200, 62, 144}, ++{110, 101, 113}, ++{119, 97, 116}, ++{132, 91, 122}, ++{146, 85, 127}, ++{161, 79, 132}, ++{176, 73, 137}, ++{192, 66, 142}, ++{201, 63, 144}, ++{113, 102, 114}, ++{121, 98, 117}, ++{134, 92, 122}, ++{148, 86, 127}, ++{163, 80, 132}, ++{178, 73, 137}, ++{193, 67, 142}, ++{202, 63, 144}, ++{116, 103, 114}, ++{124, 99, 118}, ++{136, 93, 123}, ++{150, 87, 128}, ++{165, 80, 133}, ++{180, 74, 137}, ++{194, 68, 142}, ++{204, 64, 144}, ++{119, 104, 115}, ++{127, 100, 119}, ++{139, 94, 123}, ++{152, 88, 128}, ++{167, 81, 133}, ++{181, 75, 138}, ++{196, 68, 142}, ++{205, 65, 145}, ++{122, 105, 116}, ++{130, 101, 119}, ++{141, 95, 124}, ++{155, 89, 129}, ++{169, 82, 133}, ++{183, 75, 138}, ++{198, 69, 142}, ++{207, 65, 145}, ++{125, 106, 117}, ++{133, 102, 120}, ++{144, 96, 124}, ++{157, 90, 129}, ++{171, 83, 134}, ++{185, 76, 138}, ++{199, 70, 142}, ++{208, 66, 145}, ++{129, 107, 118}, ++{136, 103, 121}, ++{147, 97, 125}, ++{160, 90, 130}, ++{173, 84, 134}, ++{187, 77, 138}, ++{201, 71, 143}, ++{210, 67, 145}, ++{132, 108, 119}, ++{139, 104, 122}, ++{150, 98, 126}, ++{162, 91, 130}, ++{175, 85, 134}, ++{189, 78, 139}, ++{203, 71, 143}, ++{212, 67, 145}, ++{136, 109, 120}, ++{142, 105, 123}, ++{153, 99, 126}, ++{165, 92, 130}, ++{178, 85, 135}, ++{191, 79, 139}, ++{205, 72, 143}, ++{214, 68, 145}, ++{139, 110, 121}, ++{146, 106, 123}, ++{156, 100, 127}, ++{168, 93, 131}, ++{180, 86, 135}, ++{194, 80, 139}, ++{207, 73, 143}, ++{216, 69, 146}, ++{143, 111, 122}, ++{149, 107, 124}, ++{159, 101, 127}, ++{170, 94, 131}, ++{183, 87, 135}, ++{196, 80, 139}, ++{209, 74, 143}, ++{218, 70, 146}, ++{147, 112, 123}, ++{153, 108, 125}, ++{162, 102, 128}, ++{173, 95, 132}, ++{186, 88, 136}, ++{198, 81, 140}, ++{212, 75, 144}, ++{220, 71, 146}, ++{150, 113, 123}, ++{156, 109, 125}, ++{165, 103, 129}, ++{176, 96, 132}, ++{188, 89, 136}, ++{201, 82, 140}, ++{214, 75, 144}, ++{222, 71, 146}, ++{154, 113, 124}, ++{160, 109, 126}, ++{169, 103, 129}, ++{179, 97, 133}, ++{191, 90, 137}, ++{203, 83, 140}, ++{216, 76, 144}, ++{224, 72, 146}, ++{158, 114, 125}, ++{163, 110, 127}, ++{172, 104, 130}, ++{182, 98, 133}, ++{194, 91, 137}, ++{206, 84, 141}, ++{219, 77, 144}, ++{226, 73, 147}, ++{161, 115, 126}, ++{167, 111, 128}, ++{175, 105, 130}, ++{185, 98, 134}, ++{197, 92, 137}, ++{209, 85, 141}, ++{221, 78, 145}, ++{229, 74, 147}, ++{165, 115, 126}, ++{170, 111, 128}, ++{179, 106, 131}, ++{189, 99, 134}, ++{200, 92, 138}, ++{211, 85, 141}, ++{223, 79, 145}, ++{231, 75, 147}, ++{169, 116, 127}, ++{174, 112, 129}, ++{182, 106, 132}, ++{192, 100, 135}, ++{203, 93, 138}, ++{214, 86, 142}, ++{226, 80, 145}, ++{234, 75, 147}, ++{173, 116, 128}, ++{178, 113, 130}, ++{185, 107, 132}, ++{195, 101, 135}, ++{206, 94, 139}, ++{217, 87, 142}, ++{229, 80, 145}, ++{236, 76, 147}, ++{175, 116, 128}, ++{180, 113, 130}, ++{187, 107, 132}, ++{197, 101, 136}, ++{207, 94, 139}, ++{218, 88, 142}, ++{230, 81, 145}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 113, 130}, ++{187, 107, 132}, ++{197, 101, 136}, ++{207, 94, 139}, ++{218, 88, 142}, ++{230, 81, 145}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 113, 130}, ++{187, 107, 132}, ++{197, 101, 136}, ++{207, 94, 139}, ++{218, 88, 142}, ++{230, 81, 145}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 113, 130}, ++{187, 107, 132}, ++{197, 101, 136}, ++{207, 94, 139}, ++{218, 88, 142}, ++{230, 81, 145}, ++{237, 77, 148}, ++{98, 90, 105}, ++{108, 88, 110}, ++{123, 84, 116}, ++{139, 79, 123}, ++{155, 74, 128}, ++{171, 68, 134}, ++{187, 63, 139}, ++{196, 59, 142}, ++{98, 90, 105}, ++{108, 88, 110}, ++{123, 84, 116}, ++{139, 79, 123}, ++{155, 74, 129}, ++{171, 68, 134}, ++{187, 63, 139}, ++{196, 59, 142}, ++{99, 91, 105}, ++{109, 88, 110}, ++{123, 84, 116}, ++{139, 79, 123}, ++{155, 74, 129}, ++{171, 68, 134}, ++{187, 63, 139}, ++{197, 59, 142}, ++{100, 91, 106}, ++{110, 89, 110}, ++{124, 85, 117}, ++{140, 80, 123}, ++{156, 74, 129}, ++{172, 69, 134}, ++{187, 63, 139}, ++{197, 60, 142}, ++{101, 92, 106}, ++{111, 90, 111}, ++{125, 85, 117}, ++{141, 80, 123}, ++{157, 75, 129}, ++{172, 69, 134}, ++{188, 63, 139}, ++{198, 60, 142}, ++{103, 93, 107}, ++{113, 91, 111}, ++{127, 86, 117}, ++{142, 81, 123}, ++{158, 75, 129}, ++{173, 69, 134}, ++{189, 64, 139}, ++{198, 60, 142}, ++{105, 95, 108}, ++{114, 92, 112}, ++{128, 87, 118}, ++{143, 82, 124}, ++{159, 76, 129}, ++{174, 70, 134}, ++{190, 64, 139}, ++{199, 61, 142}, ++{107, 96, 108}, ++{116, 93, 113}, ++{130, 88, 118}, ++{145, 82, 124}, ++{160, 76, 129}, ++{175, 70, 135}, ++{191, 65, 139}, ++{200, 61, 142}, ++{110, 97, 109}, ++{119, 94, 113}, ++{132, 89, 119}, ++{146, 83, 124}, ++{161, 77, 130}, ++{177, 71, 135}, ++{192, 65, 139}, ++{201, 61, 142}, ++{112, 98, 110}, ++{121, 95, 114}, ++{134, 90, 119}, ++{148, 84, 125}, ++{163, 78, 130}, ++{178, 72, 135}, ++{193, 66, 140}, ++{202, 62, 142}, ++{115, 100, 111}, ++{123, 96, 115}, ++{136, 91, 120}, ++{150, 85, 125}, ++{165, 79, 130}, ++{179, 72, 135}, ++{194, 66, 140}, ++{203, 63, 143}, ++{118, 101, 112}, ++{126, 97, 116}, ++{138, 92, 120}, ++{152, 86, 126}, ++{166, 79, 131}, ++{181, 73, 135}, ++{196, 67, 140}, ++{205, 63, 143}, ++{121, 102, 113}, ++{129, 98, 116}, ++{141, 93, 121}, ++{154, 87, 126}, ++{168, 80, 131}, ++{183, 74, 136}, ++{197, 68, 140}, ++{206, 64, 143}, ++{124, 103, 114}, ++{132, 99, 117}, ++{143, 94, 122}, ++{156, 87, 126}, ++{170, 81, 131}, ++{185, 75, 136}, ++{199, 68, 140}, ++{208, 65, 143}, ++{127, 105, 115}, ++{135, 101, 118}, ++{146, 95, 122}, ++{159, 88, 127}, ++{172, 82, 132}, ++{186, 75, 136}, ++{201, 69, 141}, ++{209, 65, 143}, ++{131, 106, 116}, ++{138, 102, 119}, ++{149, 96, 123}, ++{161, 89, 127}, ++{175, 83, 132}, ++{188, 76, 137}, ++{202, 70, 141}, ++{211, 66, 143}, ++{134, 107, 117}, ++{141, 103, 120}, ++{152, 97, 124}, ++{164, 90, 128}, ++{177, 84, 132}, ++{191, 77, 137}, ++{204, 71, 141}, ++{213, 67, 144}, ++{138, 108, 118}, ++{144, 104, 120}, ++{154, 98, 124}, ++{166, 91, 128}, ++{179, 85, 133}, ++{193, 78, 137}, ++{206, 71, 141}, ++{215, 68, 144}, ++{141, 109, 119}, ++{148, 105, 121}, ++{157, 99, 125}, ++{169, 92, 129}, ++{182, 85, 133}, ++{195, 79, 137}, ++{208, 72, 141}, ++{217, 68, 144}, ++{145, 109, 120}, ++{151, 105, 122}, ++{161, 100, 126}, ++{172, 93, 129}, ++{184, 86, 134}, ++{197, 80, 138}, ++{211, 73, 142}, ++{219, 69, 144}, ++{148, 110, 121}, ++{154, 106, 123}, ++{164, 100, 126}, ++{175, 94, 130}, ++{187, 87, 134}, ++{200, 80, 138}, ++{213, 74, 142}, ++{221, 70, 144}, ++{152, 111, 121}, ++{158, 107, 124}, ++{167, 101, 127}, ++{178, 95, 131}, ++{190, 88, 134}, ++{202, 81, 138}, ++{215, 75, 142}, ++{223, 71, 145}, ++{156, 112, 122}, ++{161, 108, 124}, ++{170, 102, 127}, ++{181, 96, 131}, ++{192, 89, 135}, ++{205, 82, 139}, ++{217, 76, 142}, ++{225, 72, 145}, ++{159, 112, 123}, ++{165, 109, 125}, ++{173, 103, 128}, ++{184, 97, 132}, ++{195, 90, 135}, ++{207, 83, 139}, ++{220, 76, 143}, ++{228, 72, 145}, ++{163, 113, 124}, ++{168, 109, 126}, ++{177, 104, 129}, ++{187, 97, 132}, ++{198, 91, 136}, ++{210, 84, 139}, ++{222, 77, 143}, ++{230, 73, 145}, ++{167, 114, 125}, ++{172, 110, 126}, ++{180, 105, 129}, ++{190, 98, 133}, ++{201, 91, 136}, ++{213, 85, 140}, ++{225, 78, 143}, ++{232, 74, 146}, ++{171, 114, 125}, ++{176, 111, 127}, ++{183, 105, 130}, ++{193, 99, 133}, ++{204, 92, 137}, ++{215, 86, 140}, ++{227, 79, 144}, ++{235, 75, 146}, ++{174, 115, 126}, ++{179, 111, 128}, ++{187, 106, 130}, ++{196, 100, 134}, ++{207, 93, 137}, ++{218, 86, 140}, ++{230, 80, 144}, ++{237, 76, 146}, ++{176, 115, 127}, ++{181, 112, 128}, ++{189, 106, 131}, ++{198, 100, 134}, ++{208, 93, 137}, ++{219, 87, 141}, ++{231, 80, 144}, ++{238, 76, 146}, ++{176, 115, 127}, ++{181, 112, 128}, ++{189, 106, 131}, ++{198, 100, 134}, ++{208, 93, 137}, ++{219, 87, 141}, ++{231, 80, 144}, ++{238, 76, 146}, ++{176, 115, 127}, ++{181, 112, 128}, ++{189, 106, 131}, ++{198, 100, 134}, ++{208, 93, 137}, ++{219, 87, 141}, ++{231, 80, 144}, ++{238, 76, 146}, ++{176, 115, 127}, ++{181, 112, 128}, ++{189, 106, 131}, ++{198, 100, 134}, ++{208, 93, 137}, ++{219, 87, 141}, ++{231, 80, 144}, ++{238, 76, 146}, ++{101, 87, 102}, ++{111, 86, 107}, ++{125, 82, 114}, ++{141, 78, 120}, ++{157, 73, 126}, ++{172, 67, 132}, ++{188, 62, 137}, ++{198, 58, 140}, ++{101, 87, 103}, ++{111, 86, 107}, ++{125, 82, 114}, ++{141, 78, 120}, ++{157, 73, 126}, ++{173, 67, 132}, ++{188, 62, 137}, ++{198, 58, 140}, ++{101, 88, 103}, ++{112, 86, 108}, ++{126, 83, 114}, ++{141, 78, 120}, ++{157, 73, 126}, ++{173, 68, 132}, ++{188, 62, 137}, ++{198, 59, 140}, ++{103, 89, 103}, ++{112, 87, 108}, ++{126, 83, 114}, ++{142, 78, 121}, ++{158, 73, 126}, ++{173, 68, 132}, ++{189, 62, 137}, ++{198, 59, 140}, ++{104, 90, 104}, ++{114, 88, 108}, ++{128, 84, 115}, ++{143, 79, 121}, ++{158, 74, 127}, ++{174, 68, 132}, ++{189, 63, 137}, ++{199, 59, 140}, ++{106, 91, 104}, ++{115, 88, 109}, ++{129, 84, 115}, ++{144, 79, 121}, ++{159, 74, 127}, ++{175, 69, 132}, ++{190, 63, 137}, ++{200, 59, 140}, ++{108, 92, 105}, ++{117, 90, 110}, ++{130, 85, 115}, ++{145, 80, 121}, ++{160, 75, 127}, ++{176, 69, 132}, ++{191, 63, 137}, ++{200, 60, 140}, ++{110, 93, 106}, ++{119, 91, 110}, ++{132, 86, 116}, ++{146, 81, 122}, ++{162, 75, 127}, ++{177, 70, 133}, ++{192, 64, 137}, ++{201, 60, 140}, ++{112, 95, 107}, ++{121, 92, 111}, ++{134, 87, 116}, ++{148, 82, 122}, ++{163, 76, 128}, ++{178, 70, 133}, ++{193, 64, 138}, ++{202, 61, 140}, ++{115, 96, 108}, ++{123, 93, 112}, ++{136, 88, 117}, ++{150, 82, 122}, ++{165, 77, 128}, ++{179, 71, 133}, ++{194, 65, 138}, ++{204, 61, 141}, ++{117, 97, 109}, ++{126, 94, 112}, ++{138, 89, 118}, ++{152, 83, 123}, ++{166, 77, 128}, ++{181, 71, 133}, ++{196, 66, 138}, ++{205, 62, 141}, ++{120, 99, 110}, ++{128, 95, 113}, ++{140, 90, 118}, ++{154, 84, 123}, ++{168, 78, 129}, ++{183, 72, 133}, ++{197, 66, 138}, ++{206, 63, 141}, ++{123, 100, 111}, ++{131, 96, 114}, ++{143, 91, 119}, ++{156, 85, 124}, ++{170, 79, 129}, ++{184, 73, 134}, ++{199, 67, 138}, ++{208, 63, 141}, ++{126, 101, 112}, ++{134, 98, 115}, ++{145, 92, 119}, ++{158, 86, 124}, ++{172, 80, 129}, ++{186, 74, 134}, ++{200, 68, 138}, ++{209, 64, 141}, ++{130, 103, 113}, ++{137, 99, 116}, ++{148, 93, 120}, ++{160, 87, 125}, ++{174, 81, 130}, ++{188, 75, 134}, ++{202, 68, 139}, ++{211, 65, 141}, ++{133, 104, 114}, ++{140, 100, 117}, ++{150, 94, 121}, ++{163, 88, 125}, ++{176, 82, 130}, ++{190, 75, 135}, ++{204, 69, 139}, ++{212, 65, 142}, ++{136, 105, 115}, ++{143, 101, 117}, ++{153, 95, 121}, ++{165, 89, 126}, ++{178, 83, 130}, ++{192, 76, 135}, ++{206, 70, 139}, ++{214, 66, 142}, ++{140, 106, 116}, ++{146, 102, 118}, ++{156, 96, 122}, ++{168, 90, 126}, ++{181, 84, 131}, ++{194, 77, 135}, ++{208, 71, 139}, ++{216, 67, 142}, ++{143, 107, 117}, ++{149, 103, 119}, ++{159, 97, 123}, ++{171, 91, 127}, ++{183, 84, 131}, ++{196, 78, 136}, ++{210, 72, 140}, ++{218, 68, 142}, ++{147, 108, 118}, ++{153, 104, 120}, ++{162, 98, 123}, ++{174, 92, 128}, ++{186, 85, 132}, ++{199, 79, 136}, ++{212, 72, 140}, ++{220, 68, 142}, ++{150, 109, 118}, ++{156, 105, 121}, ++{165, 99, 124}, ++{176, 93, 128}, ++{188, 86, 132}, ++{201, 80, 136}, ++{214, 73, 140}, ++{222, 69, 143}, ++{154, 109, 119}, ++{160, 106, 122}, ++{168, 100, 125}, ++{179, 94, 129}, ++{191, 87, 133}, ++{203, 81, 137}, ++{216, 74, 141}, ++{224, 70, 143}, ++{157, 110, 120}, ++{163, 106, 122}, ++{172, 101, 125}, ++{182, 95, 129}, ++{194, 88, 133}, ++{206, 81, 137}, ++{219, 75, 141}, ++{226, 71, 143}, ++{161, 111, 121}, ++{166, 107, 123}, ++{175, 102, 126}, ++{185, 95, 130}, ++{197, 89, 133}, ++{209, 82, 137}, ++{221, 76, 141}, ++{229, 72, 143}, ++{165, 112, 122}, ++{170, 108, 124}, ++{178, 103, 127}, ++{188, 96, 130}, ++{199, 90, 134}, ++{211, 83, 138}, ++{223, 77, 141}, ++{231, 73, 144}, ++{168, 112, 123}, ++{173, 109, 125}, ++{182, 103, 127}, ++{191, 97, 131}, ++{202, 91, 134}, ++{214, 84, 138}, ++{226, 77, 142}, ++{233, 73, 144}, ++{172, 113, 124}, ++{177, 109, 125}, ++{185, 104, 128}, ++{194, 98, 131}, ++{205, 91, 135}, ++{216, 85, 138}, ++{228, 78, 142}, ++{236, 74, 144}, ++{176, 114, 124}, ++{181, 110, 126}, ++{188, 105, 129}, ++{198, 99, 132}, ++{208, 92, 135}, ++{219, 86, 139}, ++{231, 79, 142}, ++{238, 75, 144}, ++{178, 114, 125}, ++{182, 110, 126}, ++{190, 105, 129}, ++{199, 99, 132}, ++{210, 93, 136}, ++{221, 86, 139}, ++{232, 79, 142}, ++{239, 75, 145}, ++{178, 114, 125}, ++{182, 110, 126}, ++{190, 105, 129}, ++{199, 99, 132}, ++{210, 93, 136}, ++{221, 86, 139}, ++{232, 79, 142}, ++{239, 75, 145}, ++{178, 114, 125}, ++{182, 110, 126}, ++{190, 105, 129}, ++{199, 99, 132}, ++{210, 93, 136}, ++{221, 86, 139}, ++{232, 79, 142}, ++{239, 75, 145}, ++{178, 114, 125}, ++{182, 110, 126}, ++{190, 105, 129}, ++{199, 99, 132}, ++{210, 93, 136}, ++{221, 86, 139}, ++{232, 79, 142}, ++{239, 75, 145}, ++{103, 85, 100}, ++{113, 83, 105}, ++{127, 80, 111}, ++{143, 76, 118}, ++{158, 71, 124}, ++{174, 66, 130}, ++{190, 61, 135}, ++{199, 58, 138}, ++{104, 85, 100}, ++{114, 84, 105}, ++{128, 81, 111}, ++{143, 76, 118}, ++{159, 72, 124}, ++{174, 66, 130}, ++{190, 61, 135}, ++{199, 58, 138}, ++{104, 85, 100}, ++{114, 84, 105}, ++{128, 81, 112}, ++{143, 77, 118}, ++{159, 72, 124}, ++{175, 67, 130}, ++{190, 61, 135}, ++{199, 58, 138}, ++{105, 86, 101}, ++{115, 85, 106}, ++{129, 81, 112}, ++{144, 77, 118}, ++{159, 72, 124}, ++{175, 67, 130}, ++{190, 61, 135}, ++{200, 58, 138}, ++{107, 87, 101}, ++{116, 85, 106}, ++{130, 82, 112}, ++{145, 77, 118}, ++{160, 72, 124}, ++{176, 67, 130}, ++{191, 62, 135}, ++{200, 58, 138}, ++{108, 88, 102}, ++{118, 86, 107}, ++{131, 83, 113}, ++{146, 78, 119}, ++{161, 73, 125}, ++{176, 68, 130}, ++{192, 62, 135}, ++{201, 59, 138}, ++{110, 90, 103}, ++{119, 87, 107}, ++{132, 83, 113}, ++{147, 79, 119}, ++{162, 73, 125}, ++{177, 68, 130}, ++{193, 62, 135}, ++{202, 59, 138}, ++{112, 91, 104}, ++{121, 88, 108}, ++{134, 84, 114}, ++{148, 79, 119}, ++{163, 74, 125}, ++{179, 69, 130}, ++{194, 63, 135}, ++{203, 60, 138}, ++{115, 92, 105}, ++{123, 90, 109}, ++{136, 85, 114}, ++{150, 80, 120}, ++{165, 75, 125}, ++{180, 69, 131}, ++{195, 64, 136}, ++{204, 60, 138}, ++{117, 94, 106}, ++{126, 91, 109}, ++{138, 86, 115}, ++{152, 81, 120}, ++{166, 75, 126}, ++{181, 70, 131}, ++{196, 64, 136}, ++{205, 61, 139}, ++{120, 95, 107}, ++{128, 92, 110}, ++{140, 87, 115}, ++{154, 82, 121}, ++{168, 76, 126}, ++{183, 70, 131}, ++{197, 65, 136}, ++{206, 61, 139}, ++{123, 97, 108}, ++{131, 93, 111}, ++{142, 88, 116}, ++{156, 83, 121}, ++{170, 77, 126}, ++{184, 71, 131}, ++{199, 65, 136}, ++{208, 62, 139}, ++{126, 98, 109}, ++{133, 95, 112}, ++{145, 90, 117}, ++{158, 84, 122}, ++{172, 78, 127}, ++{186, 72, 132}, ++{200, 66, 136}, ++{209, 62, 139}, ++{129, 99, 110}, ++{136, 96, 113}, ++{147, 91, 117}, ++{160, 85, 122}, ++{174, 79, 127}, ++{188, 73, 132}, ++{202, 67, 137}, ++{210, 63, 139}, ++{132, 100, 111}, ++{139, 97, 114}, ++{150, 92, 118}, ++{162, 86, 123}, ++{176, 80, 128}, ++{189, 74, 132}, ++{203, 68, 137}, ++{212, 64, 140}, ++{135, 102, 112}, ++{142, 98, 114}, ++{152, 93, 119}, ++{165, 87, 123}, ++{178, 81, 128}, ++{191, 74, 133}, ++{205, 68, 137}, ++{214, 65, 140}, ++{138, 103, 113}, ++{145, 99, 115}, ++{155, 94, 119}, ++{167, 88, 124}, ++{180, 82, 128}, ++{193, 75, 133}, ++{207, 69, 137}, ++{216, 65, 140}, ++{142, 104, 114}, ++{148, 100, 116}, ++{158, 95, 120}, ++{170, 89, 124}, ++{182, 82, 129}, ++{196, 76, 133}, ++{209, 70, 138}, ++{217, 66, 140}, ++{145, 105, 114}, ++{151, 101, 117}, ++{161, 96, 121}, ++{172, 90, 125}, ++{185, 83, 129}, ++{198, 77, 134}, ++{211, 71, 138}, ++{219, 67, 140}, ++{149, 106, 115}, ++{155, 102, 118}, ++{164, 97, 121}, ++{175, 91, 126}, ++{187, 84, 130}, ++{200, 78, 134}, ++{213, 72, 138}, ++{221, 68, 141}, ++{152, 107, 116}, ++{158, 103, 119}, ++{167, 98, 122}, ++{178, 92, 126}, ++{190, 85, 130}, ++{202, 79, 134}, ++{215, 72, 138}, ++{223, 68, 141}, ++{156, 108, 117}, ++{161, 104, 120}, ++{170, 99, 123}, ++{181, 93, 127}, ++{193, 86, 131}, ++{205, 80, 135}, ++{217, 73, 139}, ++{225, 69, 141}, ++{159, 109, 118}, ++{165, 105, 120}, ++{173, 100, 124}, ++{184, 93, 127}, ++{195, 87, 131}, ++{207, 80, 135}, ++{220, 74, 139}, ++{228, 70, 142}, ++{163, 109, 119}, ++{168, 106, 121}, ++{177, 100, 124}, ++{187, 94, 128}, ++{198, 88, 132}, ++{210, 81, 136}, ++{222, 75, 139}, ++{230, 71, 142}, ++{166, 110, 120}, ++{172, 107, 122}, ++{180, 101, 125}, ++{190, 95, 128}, ++{201, 89, 132}, ++{212, 82, 136}, ++{225, 76, 140}, ++{232, 72, 142}, ++{170, 111, 121}, ++{175, 107, 123}, ++{183, 102, 126}, ++{193, 96, 129}, ++{204, 90, 133}, ++{215, 83, 136}, ++{227, 77, 140}, ++{235, 73, 142}, ++{174, 112, 122}, ++{179, 108, 123}, ++{186, 103, 126}, ++{196, 97, 130}, ++{206, 90, 133}, ++{218, 84, 137}, ++{229, 77, 140}, ++{237, 73, 143}, ++{177, 112, 123}, ++{182, 109, 124}, ++{190, 104, 127}, ++{199, 98, 130}, ++{209, 91, 134}, ++{220, 85, 137}, ++{232, 78, 141}, ++{239, 74, 143}, ++{179, 112, 123}, ++{184, 109, 125}, ++{191, 104, 127}, ++{201, 98, 130}, ++{211, 92, 134}, ++{222, 85, 137}, ++{233, 79, 141}, ++{241, 75, 143}, ++{179, 112, 123}, ++{184, 109, 125}, ++{191, 104, 127}, ++{201, 98, 130}, ++{211, 92, 134}, ++{222, 85, 137}, ++{233, 79, 141}, ++{241, 75, 143}, ++{179, 112, 123}, ++{184, 109, 125}, ++{191, 104, 127}, ++{201, 98, 130}, ++{211, 92, 134}, ++{222, 85, 137}, ++{233, 79, 141}, ++{241, 75, 143}, ++{179, 112, 123}, ++{184, 109, 125}, ++{191, 104, 127}, ++{201, 98, 130}, ++{211, 92, 134}, ++{222, 85, 137}, ++{233, 79, 141}, ++{241, 75, 143}, ++{106, 82, 98}, ++{116, 81, 103}, ++{130, 79, 109}, ++{145, 75, 116}, ++{160, 70, 122}, ++{176, 65, 127}, ++{191, 60, 133}, ++{201, 57, 136}, ++{107, 82, 98}, ++{116, 81, 103}, ++{130, 79, 109}, ++{145, 75, 116}, ++{160, 70, 122}, ++{176, 65, 127}, ++{191, 60, 133}, ++{201, 57, 136}, ++{107, 83, 98}, ++{117, 82, 103}, ++{130, 79, 109}, ++{145, 75, 116}, ++{161, 70, 122}, ++{176, 65, 128}, ++{192, 60, 133}, ++{201, 57, 136}, ++{108, 84, 99}, ++{118, 82, 103}, ++{131, 79, 110}, ++{146, 75, 116}, ++{161, 71, 122}, ++{177, 66, 128}, ++{192, 61, 133}, ++{201, 57, 136}, ++{110, 85, 99}, ++{119, 83, 104}, ++{132, 80, 110}, ++{147, 76, 116}, ++{162, 71, 122}, ++{177, 66, 128}, ++{193, 61, 133}, ++{202, 58, 136}, ++{111, 86, 100}, ++{120, 84, 104}, ++{133, 81, 110}, ++{148, 77, 116}, ++{163, 72, 122}, ++{178, 66, 128}, ++{193, 61, 133}, ++{203, 58, 136}, ++{113, 87, 101}, ++{122, 85, 105}, ++{135, 82, 111}, ++{149, 77, 117}, ++{164, 72, 123}, ++{179, 67, 128}, ++{194, 62, 133}, ++{203, 58, 136}, ++{115, 88, 101}, ++{124, 86, 106}, ++{136, 83, 111}, ++{150, 78, 117}, ++{165, 73, 123}, ++{180, 67, 128}, ++{195, 62, 133}, ++{204, 59, 136}, ++{117, 90, 102}, ++{126, 87, 106}, ++{138, 84, 112}, ++{152, 79, 118}, ++{167, 74, 123}, ++{181, 68, 129}, ++{196, 63, 134}, ++{205, 59, 136}, ++{120, 91, 103}, ++{128, 89, 107}, ++{140, 85, 112}, ++{154, 80, 118}, ++{168, 74, 124}, ++{183, 69, 129}, ++{197, 63, 134}, ++{206, 60, 137}, ++{122, 93, 104}, ++{130, 90, 108}, ++{142, 86, 113}, ++{156, 81, 118}, ++{170, 75, 124}, ++{184, 69, 129}, ++{199, 64, 134}, ++{208, 60, 137}, ++{125, 94, 105}, ++{133, 91, 109}, ++{144, 87, 114}, ++{157, 81, 119}, ++{171, 76, 124}, ++{186, 70, 129}, ++{200, 64, 134}, ++{209, 61, 137}, ++{128, 96, 106}, ++{135, 92, 110}, ++{147, 88, 114}, ++{160, 82, 119}, ++{173, 77, 125}, ++{187, 71, 130}, ++{202, 65, 134}, ++{210, 62, 137}, ++{131, 97, 107}, ++{138, 94, 110}, ++{149, 89, 115}, ++{162, 83, 120}, ++{175, 78, 125}, ++{189, 72, 130}, ++{203, 66, 135}, ++{212, 62, 137}, ++{134, 98, 108}, ++{141, 95, 111}, ++{152, 90, 116}, ++{164, 84, 121}, ++{177, 79, 126}, ++{191, 73, 130}, ++{205, 67, 135}, ++{213, 63, 138}, ++{137, 100, 109}, ++{144, 96, 112}, ++{154, 91, 116}, ++{166, 85, 121}, ++{179, 79, 126}, ++{193, 73, 131}, ++{207, 67, 135}, ++{215, 64, 138}, ++{140, 101, 110}, ++{147, 97, 113}, ++{157, 92, 117}, ++{169, 86, 122}, ++{182, 80, 126}, ++{195, 74, 131}, ++{208, 68, 135}, ++{217, 65, 138}, ++{144, 102, 111}, ++{150, 98, 114}, ++{160, 93, 118}, ++{171, 87, 122}, ++{184, 81, 127}, ++{197, 75, 131}, ++{210, 69, 136}, ++{219, 65, 138}, ++{147, 103, 112}, ++{153, 99, 115}, ++{163, 94, 119}, ++{174, 88, 123}, ++{186, 82, 127}, ++{199, 76, 132}, ++{212, 70, 136}, ++{221, 66, 139}, ++{151, 104, 113}, ++{157, 101, 116}, ++{166, 95, 119}, ++{177, 89, 124}, ++{189, 83, 128}, ++{202, 77, 132}, ++{214, 71, 136}, ++{223, 67, 139}, ++{154, 105, 114}, ++{160, 102, 117}, ++{169, 96, 120}, ++{180, 90, 124}, ++{191, 84, 128}, ++{204, 78, 133}, ++{217, 72, 137}, ++{225, 68, 139}, ++{158, 106, 115}, ++{163, 102, 117}, ++{172, 97, 121}, ++{182, 91, 125}, ++{194, 85, 129}, ++{206, 79, 133}, ++{219, 72, 137}, ++{227, 69, 140}, ++{161, 107, 116}, ++{166, 103, 118}, ++{175, 98, 122}, ++{185, 92, 125}, ++{197, 86, 129}, ++{209, 80, 133}, ++{221, 73, 137}, ++{229, 69, 140}, ++{165, 108, 117}, ++{170, 104, 119}, ++{178, 99, 122}, ++{188, 93, 126}, ++{199, 87, 130}, ++{211, 80, 134}, ++{223, 74, 138}, ++{231, 70, 140}, ++{168, 108, 118}, ++{173, 105, 120}, ++{181, 100, 123}, ++{191, 94, 127}, ++{202, 88, 130}, ++{214, 81, 134}, ++{226, 75, 138}, ++{233, 71, 140}, ++{172, 109, 119}, ++{177, 106, 121}, ++{185, 101, 124}, ++{194, 95, 127}, ++{205, 89, 131}, ++{216, 82, 135}, ++{228, 76, 138}, ++{236, 72, 141}, ++{175, 110, 120}, ++{180, 107, 122}, ++{188, 102, 124}, ++{197, 96, 128}, ++{208, 89, 131}, ++{219, 83, 135}, ++{231, 77, 139}, ++{238, 73, 141}, ++{179, 111, 121}, ++{184, 107, 122}, ++{191, 102, 125}, ++{200, 97, 128}, ++{211, 90, 132}, ++{222, 84, 135}, ++{233, 77, 139}, ++{241, 74, 141}, ++{181, 111, 121}, ++{186, 108, 123}, ++{193, 103, 125}, ++{202, 97, 129}, ++{212, 91, 132}, ++{223, 84, 136}, ++{234, 78, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 108, 123}, ++{193, 103, 125}, ++{202, 97, 129}, ++{212, 91, 132}, ++{223, 84, 136}, ++{234, 78, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 108, 123}, ++{193, 103, 125}, ++{202, 97, 129}, ++{212, 91, 132}, ++{223, 84, 136}, ++{234, 78, 139}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 108, 123}, ++{193, 103, 125}, ++{202, 97, 129}, ++{212, 91, 132}, ++{223, 84, 136}, ++{234, 78, 139}, ++{242, 74, 141}, ++{109, 79, 96}, ++{119, 79, 100}, ++{132, 77, 107}, ++{147, 73, 113}, ++{162, 69, 119}, ++{178, 64, 125}, ++{193, 59, 131}, ++{202, 56, 134}, ++{109, 80, 96}, ++{119, 79, 100}, ++{132, 77, 107}, ++{147, 73, 113}, ++{162, 69, 119}, ++{178, 64, 125}, ++{193, 59, 131}, ++{202, 56, 134}, ++{110, 80, 96}, ++{119, 79, 101}, ++{133, 77, 107}, ++{147, 73, 113}, ++{163, 69, 120}, ++{178, 64, 125}, ++{193, 59, 131}, ++{202, 56, 134}, ++{111, 81, 96}, ++{120, 80, 101}, ++{133, 78, 107}, ++{148, 74, 114}, ++{163, 69, 120}, ++{178, 65, 125}, ++{194, 60, 131}, ++{203, 56, 134}, ++{112, 82, 97}, ++{121, 81, 101}, ++{134, 78, 108}, ++{149, 74, 114}, ++{164, 70, 120}, ++{179, 65, 126}, ++{194, 60, 131}, ++{203, 57, 134}, ++{114, 83, 98}, ++{123, 82, 102}, ++{136, 79, 108}, ++{150, 75, 114}, ++{165, 70, 120}, ++{180, 65, 126}, ++{195, 60, 131}, ++{204, 57, 134}, ++{116, 84, 98}, ++{124, 83, 103}, ++{137, 80, 108}, ++{151, 76, 114}, ++{166, 71, 120}, ++{181, 66, 126}, ++{196, 61, 131}, ++{205, 57, 134}, ++{118, 86, 99}, ++{126, 84, 103}, ++{139, 81, 109}, ++{152, 76, 115}, ++{167, 72, 121}, ++{182, 66, 126}, ++{197, 61, 131}, ++{206, 58, 134}, ++{120, 87, 100}, ++{128, 85, 104}, ++{140, 82, 109}, ++{154, 77, 115}, ++{168, 72, 121}, ++{183, 67, 126}, ++{198, 62, 132}, ++{207, 58, 135}, ++{122, 89, 101}, ++{130, 87, 105}, ++{142, 83, 110}, ++{156, 78, 116}, ++{170, 73, 121}, ++{184, 68, 127}, ++{199, 62, 132}, ++{208, 59, 135}, ++{125, 90, 102}, ++{133, 88, 106}, ++{144, 84, 111}, ++{157, 79, 116}, ++{171, 74, 122}, ++{186, 68, 127}, ++{200, 63, 132}, ++{209, 59, 135}, ++{128, 92, 103}, ++{135, 89, 106}, ++{146, 85, 111}, ++{159, 80, 117}, ++{173, 75, 122}, ++{187, 69, 127}, ++{202, 64, 132}, ++{210, 60, 135}, ++{130, 93, 104}, ++{138, 90, 107}, ++{149, 86, 112}, ++{161, 81, 117}, ++{175, 75, 123}, ++{189, 70, 128}, ++{203, 64, 132}, ++{212, 61, 135}, ++{133, 95, 105}, ++{140, 92, 108}, ++{151, 87, 113}, ++{164, 82, 118}, ++{177, 76, 123}, ++{191, 71, 128}, ++{205, 65, 133}, ++{213, 61, 136}, ++{136, 96, 106}, ++{143, 93, 109}, ++{154, 88, 114}, ++{166, 83, 118}, ++{179, 77, 123}, ++{193, 72, 128}, ++{206, 66, 133}, ++{215, 62, 136}, ++{139, 97, 107}, ++{146, 94, 110}, ++{156, 89, 114}, ++{168, 84, 119}, ++{181, 78, 124}, ++{194, 72, 129}, ++{208, 67, 133}, ++{217, 63, 136}, ++{143, 99, 108}, ++{149, 95, 111}, ++{159, 91, 115}, ++{171, 85, 120}, ++{183, 79, 124}, ++{196, 73, 129}, ++{210, 67, 134}, ++{218, 64, 136}, ++{146, 100, 109}, ++{152, 97, 112}, ++{162, 92, 116}, ++{173, 86, 120}, ++{186, 80, 125}, ++{199, 74, 129}, ++{212, 68, 134}, ++{220, 64, 137}, ++{149, 101, 110}, ++{155, 98, 113}, ++{165, 93, 117}, ++{176, 87, 121}, ++{188, 81, 125}, ++{201, 75, 130}, ++{214, 69, 134}, ++{222, 65, 137}, ++{153, 102, 111}, ++{158, 99, 114}, ++{168, 94, 117}, ++{179, 88, 122}, ++{190, 82, 126}, ++{203, 76, 130}, ++{216, 70, 135}, ++{224, 66, 137}, ++{156, 103, 112}, ++{162, 100, 115}, ++{171, 95, 118}, ++{181, 89, 122}, ++{193, 83, 126}, ++{205, 77, 131}, ++{218, 71, 135}, ++{226, 67, 137}, ++{159, 104, 113}, ++{165, 101, 115}, ++{174, 96, 119}, ++{184, 90, 123}, ++{196, 84, 127}, ++{208, 78, 131}, ++{220, 72, 135}, ++{228, 68, 138}, ++{163, 105, 114}, ++{168, 102, 116}, ++{177, 97, 120}, ++{187, 91, 123}, ++{198, 85, 127}, ++{210, 79, 132}, ++{222, 72, 136}, ++{230, 69, 138}, ++{166, 106, 115}, ++{172, 103, 117}, ++{180, 98, 120}, ++{190, 92, 124}, ++{201, 86, 128}, ++{213, 79, 132}, ++{225, 73, 136}, ++{232, 69, 138}, ++{170, 107, 116}, ++{175, 104, 118}, ++{183, 99, 121}, ++{193, 93, 125}, ++{204, 87, 128}, ++{215, 80, 132}, ++{227, 74, 136}, ++{235, 70, 139}, ++{174, 108, 117}, ++{178, 104, 119}, ++{186, 99, 122}, ++{196, 94, 125}, ++{206, 88, 129}, ++{218, 81, 133}, ++{229, 75, 137}, ++{237, 71, 139}, ++{177, 108, 118}, ++{182, 105, 120}, ++{190, 100, 123}, ++{199, 95, 126}, ++{209, 88, 130}, ++{220, 82, 133}, ++{232, 76, 137}, ++{239, 72, 139}, ++{181, 109, 119}, ++{185, 106, 121}, ++{193, 101, 123}, ++{202, 95, 127}, ++{212, 89, 130}, ++{223, 83, 134}, ++{234, 77, 137}, ++{242, 73, 140}, ++{182, 110, 119}, ++{187, 106, 121}, ++{194, 101, 124}, ++{203, 96, 127}, ++{214, 90, 130}, ++{224, 83, 134}, ++{236, 77, 138}, ++{243, 73, 140}, ++{182, 110, 119}, ++{187, 106, 121}, ++{194, 101, 124}, ++{203, 96, 127}, ++{214, 90, 130}, ++{224, 83, 134}, ++{236, 77, 138}, ++{243, 73, 140}, ++{182, 110, 119}, ++{187, 106, 121}, ++{194, 101, 124}, ++{203, 96, 127}, ++{214, 90, 130}, ++{224, 83, 134}, ++{236, 77, 138}, ++{243, 73, 140}, ++{182, 110, 119}, ++{187, 106, 121}, ++{194, 101, 124}, ++{203, 96, 127}, ++{214, 90, 130}, ++{224, 83, 134}, ++{236, 77, 138}, ++{243, 73, 140}, ++{112, 77, 93}, ++{121, 76, 98}, ++{134, 75, 104}, ++{149, 72, 111}, ++{164, 67, 117}, ++{179, 63, 123}, ++{194, 58, 129}, ++{204, 55, 132}, ++{112, 77, 93}, ++{122, 77, 98}, ++{135, 75, 104}, ++{149, 72, 111}, ++{164, 68, 117}, ++{179, 63, 123}, ++{194, 58, 129}, ++{204, 55, 132}, ++{113, 78, 94}, ++{122, 77, 98}, ++{135, 75, 105}, ++{150, 72, 111}, ++{165, 68, 117}, ++{180, 63, 123}, ++{195, 58, 129}, ++{204, 55, 132}, ++{114, 78, 94}, ++{123, 78, 99}, ++{136, 76, 105}, ++{150, 72, 111}, ++{165, 68, 117}, ++{180, 63, 123}, ++{195, 59, 129}, ++{204, 55, 132}, ++{115, 79, 95}, ++{124, 78, 99}, ++{137, 76, 105}, ++{151, 73, 112}, ++{166, 68, 118}, ++{181, 64, 123}, ++{196, 59, 129}, ++{205, 56, 132}, ++{117, 81, 95}, ++{125, 79, 100}, ++{138, 77, 106}, ++{152, 73, 112}, ++{167, 69, 118}, ++{182, 64, 124}, ++{196, 59, 129}, ++{206, 56, 132}, ++{118, 82, 96}, ++{127, 81, 100}, ++{139, 78, 106}, ++{153, 74, 112}, ++{168, 70, 118}, ++{183, 65, 124}, ++{197, 60, 129}, ++{206, 57, 132}, ++{120, 83, 97}, ++{129, 82, 101}, ++{141, 79, 107}, ++{155, 75, 113}, ++{169, 70, 118}, ++{184, 65, 124}, ++{198, 60, 129}, ++{207, 57, 132}, ++{123, 85, 98}, ++{131, 83, 102}, ++{143, 80, 107}, ++{156, 76, 113}, ++{170, 71, 119}, ++{185, 66, 124}, ++{199, 61, 129}, ++{208, 57, 133}, ++{125, 86, 99}, ++{133, 84, 103}, ++{144, 81, 108}, ++{158, 77, 114}, ++{172, 72, 119}, ++{186, 67, 125}, ++{200, 61, 130}, ++{209, 58, 133}, ++{127, 88, 100}, ++{135, 86, 103}, ++{146, 82, 108}, ++{159, 77, 114}, ++{173, 72, 120}, ++{187, 67, 125}, ++{202, 62, 130}, ++{211, 59, 133}, ++{130, 89, 101}, ++{137, 87, 104}, ++{149, 83, 109}, ++{161, 78, 115}, ++{175, 73, 120}, ++{189, 68, 125}, ++{203, 63, 130}, ++{212, 59, 133}, ++{133, 91, 102}, ++{140, 88, 105}, ++{151, 84, 110}, ++{163, 79, 115}, ++{177, 74, 120}, ++{191, 69, 126}, ++{205, 63, 130}, ++{213, 60, 133}, ++{136, 92, 103}, ++{143, 90, 106}, ++{153, 85, 111}, ++{166, 80, 116}, ++{179, 75, 121}, ++{192, 70, 126}, ++{206, 64, 131}, ++{215, 61, 134}, ++{139, 94, 104}, ++{145, 91, 107}, ++{156, 87, 111}, ++{168, 81, 116}, ++{181, 76, 121}, ++{194, 70, 126}, ++{208, 65, 131}, ++{216, 61, 134}, ++{142, 95, 105}, ++{148, 92, 108}, ++{158, 88, 112}, ++{170, 83, 117}, ++{183, 77, 122}, ++{196, 71, 127}, ++{210, 66, 131}, ++{218, 62, 134}, ++{145, 96, 106}, ++{151, 93, 109}, ++{161, 89, 113}, ++{173, 84, 118}, ++{185, 78, 122}, ++{198, 72, 127}, ++{211, 66, 132}, ++{220, 63, 134}, ++{148, 98, 107}, ++{154, 95, 110}, ++{164, 90, 114}, ++{175, 85, 118}, ++{187, 79, 123}, ++{200, 73, 127}, ++{213, 67, 132}, ++{221, 64, 135}, ++{151, 99, 108}, ++{157, 96, 111}, ++{167, 91, 114}, ++{178, 86, 119}, ++{190, 80, 123}, ++{202, 74, 128}, ++{215, 68, 132}, ++{223, 64, 135}, ++{155, 100, 109}, ++{160, 97, 112}, ++{169, 92, 115}, ++{180, 87, 119}, ++{192, 81, 124}, ++{205, 75, 128}, ++{217, 69, 133}, ++{225, 65, 135}, ++{158, 101, 110}, ++{164, 98, 112}, ++{172, 93, 116}, ++{183, 88, 120}, ++{195, 82, 124}, ++{207, 76, 129}, ++{219, 70, 133}, ++{227, 66, 136}, ++{161, 102, 111}, ++{167, 99, 113}, ++{175, 94, 117}, ++{186, 89, 121}, ++{197, 83, 125}, ++{209, 77, 129}, ++{222, 71, 133}, ++{229, 67, 136}, ++{165, 103, 112}, ++{170, 100, 114}, ++{178, 95, 118}, ++{189, 90, 121}, ++{200, 84, 126}, ++{212, 78, 130}, ++{224, 71, 134}, ++{232, 68, 136}, ++{168, 104, 113}, ++{173, 101, 115}, ++{182, 96, 118}, ++{191, 91, 122}, ++{202, 85, 126}, ++{214, 78, 130}, ++{226, 72, 134}, ++{234, 69, 137}, ++{172, 105, 114}, ++{177, 102, 116}, ++{185, 97, 119}, ++{194, 91, 123}, ++{205, 85, 127}, ++{217, 79, 131}, ++{228, 73, 135}, ++{236, 69, 137}, ++{175, 106, 115}, ++{180, 103, 117}, ++{188, 98, 120}, ++{197, 92, 123}, ++{208, 86, 127}, ++{219, 80, 131}, ++{231, 74, 135}, ++{238, 70, 137}, ++{179, 107, 116}, ++{184, 104, 118}, ++{191, 99, 121}, ++{200, 93, 124}, ++{211, 87, 128}, ++{222, 81, 131}, ++{233, 75, 135}, ++{241, 71, 138}, ++{182, 108, 117}, ++{187, 104, 119}, ++{194, 100, 121}, ++{203, 94, 125}, ++{214, 88, 128}, ++{224, 82, 132}, ++{236, 76, 136}, ++{243, 72, 138}, ++{184, 108, 117}, ++{189, 105, 119}, ++{196, 100, 122}, ++{205, 95, 125}, ++{215, 89, 129}, ++{226, 82, 132}, ++{237, 76, 136}, ++{244, 72, 138}, ++{184, 108, 117}, ++{189, 105, 119}, ++{196, 100, 122}, ++{205, 95, 125}, ++{215, 89, 129}, ++{226, 82, 132}, ++{237, 76, 136}, ++{244, 72, 138}, ++{184, 108, 117}, ++{189, 105, 119}, ++{196, 100, 122}, ++{205, 95, 125}, ++{215, 89, 129}, ++{226, 82, 132}, ++{237, 76, 136}, ++{244, 72, 138}, ++{184, 108, 117}, ++{189, 105, 119}, ++{196, 100, 122}, ++{205, 95, 125}, ++{215, 89, 129}, ++{226, 82, 132}, ++{237, 76, 136}, ++{244, 72, 138}, ++{115, 74, 91}, ++{124, 74, 96}, ++{137, 73, 102}, ++{151, 70, 109}, ++{166, 66, 115}, ++{181, 62, 121}, ++{196, 57, 126}, ++{205, 54, 130}, ++{115, 74, 91}, ++{124, 74, 96}, ++{137, 73, 102}, ++{151, 70, 109}, ++{166, 66, 115}, ++{181, 62, 121}, ++{196, 57, 126}, ++{205, 54, 130}, ++{116, 75, 92}, ++{125, 75, 96}, ++{137, 73, 102}, ++{152, 70, 109}, ++{167, 66, 115}, ++{182, 62, 121}, ++{196, 57, 127}, ++{206, 54, 130}, ++{117, 76, 92}, ++{126, 75, 96}, ++{138, 74, 103}, ++{152, 71, 109}, ++{167, 67, 115}, ++{182, 62, 121}, ++{197, 58, 127}, ++{206, 55, 130}, ++{118, 77, 93}, ++{127, 76, 97}, ++{139, 74, 103}, ++{153, 71, 109}, ++{168, 67, 115}, ++{183, 63, 121}, ++{197, 58, 127}, ++{206, 55, 130}, ++{120, 78, 93}, ++{128, 77, 97}, ++{140, 75, 103}, ++{154, 72, 110}, ++{169, 68, 116}, ++{183, 63, 121}, ++{198, 58, 127}, ++{207, 55, 130}, ++{121, 79, 94}, ++{129, 78, 98}, ++{142, 76, 104}, ++{155, 72, 110}, ++{170, 68, 116}, ++{184, 64, 122}, ++{199, 59, 127}, ++{208, 56, 130}, ++{123, 81, 95}, ++{131, 79, 99}, ++{143, 77, 104}, ++{157, 73, 110}, ++{171, 69, 116}, ++{185, 64, 122}, ++{200, 59, 127}, ++{209, 56, 130}, ++{125, 82, 96}, ++{133, 81, 100}, ++{145, 78, 105}, ++{158, 74, 111}, ++{172, 70, 117}, ++{186, 65, 122}, ++{201, 60, 127}, ++{210, 57, 131}, ++{128, 84, 97}, ++{135, 82, 100}, ++{147, 79, 106}, ++{160, 75, 111}, ++{174, 70, 117}, ++{188, 65, 122}, ++{202, 60, 128}, ++{211, 57, 131}, ++{130, 85, 98}, ++{137, 83, 101}, ++{149, 80, 106}, ++{161, 76, 112}, ++{175, 71, 117}, ++{189, 66, 123}, ++{203, 61, 128}, ++{212, 58, 131}, ++{133, 87, 99}, ++{140, 85, 102}, ++{151, 81, 107}, ++{163, 77, 112}, ++{177, 72, 118}, ++{191, 67, 123}, ++{205, 62, 128}, ++{213, 58, 131}, ++{135, 89, 100}, ++{142, 86, 103}, ++{153, 82, 108}, ++{165, 78, 113}, ++{179, 73, 118}, ++{192, 68, 123}, ++{206, 62, 128}, ++{215, 59, 131}, ++{138, 90, 101}, ++{145, 88, 104}, ++{155, 84, 108}, ++{167, 79, 114}, ++{181, 74, 119}, ++{194, 68, 124}, ++{208, 63, 129}, ++{216, 60, 132}, ++{141, 92, 102}, ++{148, 89, 105}, ++{158, 85, 109}, ++{170, 80, 114}, ++{183, 75, 119}, ++{196, 69, 124}, ++{209, 64, 129}, ++{218, 60, 132}, ++{144, 93, 103}, ++{150, 90, 106}, ++{160, 86, 110}, ++{172, 81, 115}, ++{185, 76, 120}, ++{198, 70, 125}, ++{211, 65, 129}, ++{219, 61, 132}, ++{147, 94, 104}, ++{153, 91, 107}, ++{163, 87, 111}, ++{174, 82, 115}, ++{187, 77, 120}, ++{200, 71, 125}, ++{213, 65, 130}, ++{221, 62, 133}, ++{150, 96, 105}, ++{156, 93, 108}, ++{166, 88, 112}, ++{177, 83, 116}, ++{189, 78, 121}, ++{202, 72, 126}, ++{215, 66, 130}, ++{223, 63, 133}, ++{153, 97, 106}, ++{159, 94, 109}, ++{168, 89, 112}, ++{179, 84, 117}, ++{191, 79, 121}, ++{204, 73, 126}, ++{217, 67, 130}, ++{225, 64, 133}, ++{157, 98, 107}, ++{162, 95, 109}, ++{171, 91, 113}, ++{182, 85, 117}, ++{194, 80, 122}, ++{206, 74, 126}, ++{219, 68, 131}, ++{227, 64, 134}, ++{160, 99, 108}, ++{166, 96, 110}, ++{174, 92, 114}, ++{185, 86, 118}, ++{196, 81, 122}, ++{208, 75, 127}, ++{221, 69, 131}, ++{229, 65, 134}, ++{163, 100, 109}, ++{169, 97, 111}, ++{177, 93, 115}, ++{187, 87, 119}, ++{199, 81, 123}, ++{211, 76, 127}, ++{223, 70, 132}, ++{231, 66, 134}, ++{167, 101, 110}, ++{172, 98, 112}, ++{180, 94, 116}, ++{190, 88, 119}, ++{201, 82, 124}, ++{213, 77, 128}, ++{225, 71, 132}, ++{233, 67, 135}, ++{170, 102, 111}, ++{175, 99, 113}, ++{183, 95, 116}, ++{193, 89, 120}, ++{204, 83, 124}, ++{216, 77, 128}, ++{227, 71, 132}, ++{235, 68, 135}, ++{174, 103, 112}, ++{179, 100, 114}, ++{186, 96, 117}, ++{196, 90, 121}, ++{207, 84, 125}, ++{218, 78, 129}, ++{230, 72, 133}, ++{237, 69, 135}, ++{177, 104, 113}, ++{182, 101, 115}, ++{190, 97, 118}, ++{199, 91, 122}, ++{209, 85, 125}, ++{221, 79, 129}, ++{232, 73, 133}, ++{240, 69, 136}, ++{181, 105, 114}, ++{185, 102, 116}, ++{193, 97, 119}, ++{202, 92, 122}, ++{212, 86, 126}, ++{223, 80, 130}, ++{235, 74, 134}, ++{242, 70, 136}, ++{184, 106, 115}, ++{189, 103, 117}, ++{196, 98, 120}, ++{205, 93, 123}, ++{215, 87, 126}, ++{226, 81, 130}, ++{237, 75, 134}, ++{244, 71, 136}, ++{186, 106, 115}, ++{190, 103, 117}, ++{198, 99, 120}, ++{206, 93, 123}, ++{216, 87, 127}, ++{227, 81, 130}, ++{238, 75, 134}, ++{245, 72, 137}, ++{186, 106, 115}, ++{190, 103, 117}, ++{198, 99, 120}, ++{206, 93, 123}, ++{216, 87, 127}, ++{227, 81, 130}, ++{238, 75, 134}, ++{245, 72, 137}, ++{186, 106, 115}, ++{190, 103, 117}, ++{198, 99, 120}, ++{206, 93, 123}, ++{216, 87, 127}, ++{227, 81, 130}, ++{238, 75, 134}, ++{245, 72, 137}, ++{186, 106, 115}, ++{190, 103, 117}, ++{198, 99, 120}, ++{206, 93, 123}, ++{216, 87, 127}, ++{227, 81, 130}, ++{238, 75, 134}, ++{245, 72, 137}, ++{118, 72, 89}, ++{127, 72, 94}, ++{139, 71, 100}, ++{153, 68, 106}, ++{168, 65, 113}, ++{183, 61, 119}, ++{198, 56, 124}, ++{207, 53, 128}, ++{118, 72, 89}, ++{127, 72, 94}, ++{139, 71, 100}, ++{154, 68, 106}, ++{168, 65, 113}, ++{183, 61, 119}, ++{198, 56, 124}, ++{207, 53, 128}, ++{119, 72, 89}, ++{127, 72, 94}, ++{140, 71, 100}, ++{154, 68, 107}, ++{169, 65, 113}, ++{183, 61, 119}, ++{198, 56, 124}, ++{207, 53, 128}, ++{120, 73, 90}, ++{128, 73, 94}, ++{141, 72, 100}, ++{155, 69, 107}, ++{169, 65, 113}, ++{184, 61, 119}, ++{198, 56, 125}, ++{208, 54, 128}, ++{121, 74, 90}, ++{129, 74, 95}, ++{141, 72, 101}, ++{155, 69, 107}, ++{170, 66, 113}, ++{184, 61, 119}, ++{199, 57, 125}, ++{208, 54, 128}, ++{122, 75, 91}, ++{131, 75, 95}, ++{143, 73, 101}, ++{156, 70, 107}, ++{171, 66, 114}, ++{185, 62, 119}, ++{200, 57, 125}, ++{209, 54, 128}, ++{124, 77, 92}, ++{132, 76, 96}, ++{144, 74, 102}, ++{157, 71, 108}, ++{172, 67, 114}, ++{186, 62, 120}, ++{201, 58, 125}, ++{209, 55, 128}, ++{126, 78, 93}, ++{134, 77, 97}, ++{145, 75, 102}, ++{159, 71, 108}, ++{173, 67, 114}, ++{187, 63, 120}, ++{201, 58, 125}, ++{210, 55, 128}, ++{128, 80, 94}, ++{136, 78, 97}, ++{147, 76, 103}, ++{160, 72, 109}, ++{174, 68, 114}, ++{188, 63, 120}, ++{202, 59, 125}, ++{211, 56, 129}, ++{130, 81, 94}, ++{138, 80, 98}, ++{149, 77, 103}, ++{162, 73, 109}, ++{176, 69, 115}, ++{190, 64, 120}, ++{204, 59, 126}, ++{212, 56, 129}, ++{133, 83, 95}, ++{140, 81, 99}, ++{151, 78, 104}, ++{164, 74, 110}, ++{177, 70, 115}, ++{191, 65, 121}, ++{205, 60, 126}, ++{214, 57, 129}, ++{135, 85, 96}, ++{142, 83, 100}, ++{153, 79, 105}, ++{165, 75, 110}, ++{179, 71, 116}, ++{192, 66, 121}, ++{206, 61, 126}, ++{215, 57, 129}, ++{138, 86, 97}, ++{145, 84, 101}, ++{155, 81, 106}, ++{167, 76, 111}, ++{180, 71, 116}, ++{194, 66, 121}, ++{208, 61, 126}, ++{216, 58, 129}, ++{140, 88, 99}, ++{147, 85, 102}, ++{157, 82, 106}, ++{169, 77, 111}, ++{182, 72, 117}, ++{196, 67, 122}, ++{209, 62, 127}, ++{218, 59, 130}, ++{143, 89, 100}, ++{150, 87, 103}, ++{160, 83, 107}, ++{172, 78, 112}, ++{184, 73, 117}, ++{197, 68, 122}, ++{211, 63, 127}, ++{219, 59, 130}, ++{146, 91, 101}, ++{153, 88, 104}, ++{162, 84, 108}, ++{174, 79, 113}, ++{186, 74, 118}, ++{199, 69, 123}, ++{213, 64, 127}, ++{221, 60, 130}, ++{149, 92, 102}, ++{155, 89, 105}, ++{165, 85, 109}, ++{176, 81, 113}, ++{189, 75, 118}, ++{201, 70, 123}, ++{214, 64, 128}, ++{223, 61, 131}, ++{152, 93, 103}, ++{158, 91, 106}, ++{168, 87, 110}, ++{179, 82, 114}, ++{191, 76, 119}, ++{203, 71, 124}, ++{216, 65, 128}, ++{224, 62, 131}, ++{156, 95, 104}, ++{161, 92, 106}, ++{170, 88, 110}, ++{181, 83, 115}, ++{193, 77, 119}, ++{205, 72, 124}, ++{218, 66, 129}, ++{226, 63, 131}, ++{159, 96, 105}, ++{164, 93, 107}, ++{173, 89, 111}, ++{184, 84, 115}, ++{195, 78, 120}, ++{208, 73, 124}, ++{220, 67, 129}, ++{228, 63, 132}, ++{162, 97, 106}, ++{168, 94, 108}, ++{176, 90, 112}, ++{186, 85, 116}, ++{198, 79, 121}, ++{210, 74, 125}, ++{222, 68, 129}, ++{230, 64, 132}, ++{165, 98, 107}, ++{171, 95, 109}, ++{179, 91, 113}, ++{189, 86, 117}, ++{200, 80, 121}, ++{212, 74, 125}, ++{224, 69, 130}, ++{232, 65, 132}, ++{169, 100, 108}, ++{174, 97, 110}, ++{182, 92, 114}, ++{192, 87, 118}, ++{203, 81, 122}, ++{215, 75, 126}, ++{227, 70, 130}, ++{234, 66, 133}, ++{172, 101, 109}, ++{177, 98, 111}, ++{185, 93, 114}, ++{195, 88, 118}, ++{206, 82, 122}, ++{217, 76, 126}, ++{229, 70, 131}, ++{236, 67, 133}, ++{175, 102, 110}, ++{180, 99, 112}, ++{188, 94, 115}, ++{198, 89, 119}, ++{208, 83, 123}, ++{219, 77, 127}, ++{231, 71, 131}, ++{239, 68, 133}, ++{179, 103, 111}, ++{184, 100, 113}, ++{191, 95, 116}, ++{201, 90, 120}, ++{211, 84, 123}, ++{222, 78, 127}, ++{234, 72, 131}, ++{241, 69, 134}, ++{182, 103, 112}, ++{187, 101, 114}, ++{194, 96, 117}, ++{204, 91, 120}, ++{214, 85, 124}, ++{225, 79, 128}, ++{236, 73, 132}, ++{243, 69, 134}, ++{186, 104, 113}, ++{190, 101, 115}, ++{198, 97, 118}, ++{207, 92, 121}, ++{217, 86, 125}, ++{227, 80, 128}, ++{238, 74, 132}, ++{246, 70, 135}, ++{188, 105, 113}, ++{192, 102, 115}, ++{199, 97, 118}, ++{208, 92, 121}, ++{218, 86, 125}, ++{229, 80, 129}, ++{240, 74, 132}, ++{247, 71, 135}, ++{188, 105, 113}, ++{192, 102, 115}, ++{199, 97, 118}, ++{208, 92, 121}, ++{218, 86, 125}, ++{229, 80, 129}, ++{240, 74, 132}, ++{247, 71, 135}, ++{188, 105, 113}, ++{192, 102, 115}, ++{199, 97, 118}, ++{208, 92, 121}, ++{218, 86, 125}, ++{229, 80, 129}, ++{240, 74, 132}, ++{247, 71, 135}, ++{188, 105, 113}, ++{192, 102, 115}, ++{199, 97, 118}, ++{208, 92, 121}, ++{218, 86, 125}, ++{229, 80, 129}, ++{240, 74, 132}, ++{247, 71, 135}, ++{121, 69, 87}, ++{129, 69, 92}, ++{142, 69, 98}, ++{156, 66, 104}, ++{170, 63, 111}, ++{185, 59, 117}, ++{199, 55, 122}, ++{208, 52, 126}, ++{121, 69, 87}, ++{130, 70, 92}, ++{142, 69, 98}, ++{156, 66, 104}, ++{170, 63, 111}, ++{185, 59, 117}, ++{199, 55, 122}, ++{209, 52, 126}, ++{122, 70, 87}, ++{130, 70, 92}, ++{142, 69, 98}, ++{156, 67, 104}, ++{171, 63, 111}, ++{185, 59, 117}, ++{200, 55, 122}, ++{209, 52, 126}, ++{123, 71, 88}, ++{131, 71, 92}, ++{143, 70, 98}, ++{157, 67, 105}, ++{171, 64, 111}, ++{186, 60, 117}, ++{200, 55, 122}, ++{209, 53, 126}, ++{124, 72, 88}, ++{132, 71, 93}, ++{144, 70, 99}, ++{158, 68, 105}, ++{172, 64, 111}, ++{186, 60, 117}, ++{201, 56, 123}, ++{210, 53, 126}, ++{125, 73, 89}, ++{133, 72, 93}, ++{145, 71, 99}, ++{158, 68, 105}, ++{173, 65, 111}, ++{187, 61, 117}, ++{201, 56, 123}, ++{210, 53, 126}, ++{127, 74, 90}, ++{135, 74, 94}, ++{146, 72, 99}, ++{160, 69, 106}, ++{174, 65, 112}, ++{188, 61, 117}, ++{202, 56, 123}, ++{211, 54, 126}, ++{129, 76, 91}, ++{136, 75, 94}, ++{148, 73, 100}, ++{161, 70, 106}, ++{175, 66, 112}, ++{189, 62, 118}, ++{203, 57, 123}, ++{212, 54, 126}, ++{131, 77, 91}, ++{138, 76, 95}, ++{149, 74, 101}, ++{162, 71, 106}, ++{176, 67, 112}, ++{190, 62, 118}, ++{204, 58, 123}, ++{213, 55, 127}, ++{133, 79, 92}, ++{140, 78, 96}, ++{151, 75, 101}, ++{164, 72, 107}, ++{177, 67, 113}, ++{191, 63, 118}, ++{205, 58, 124}, ++{214, 55, 127}, ++{135, 81, 93}, ++{142, 79, 97}, ++{153, 76, 102}, ++{166, 73, 108}, ++{179, 68, 113}, ++{193, 64, 119}, ++{207, 59, 124}, ++{215, 56, 127}, ++{138, 82, 94}, ++{145, 80, 98}, ++{155, 77, 103}, ++{167, 74, 108}, ++{181, 69, 114}, ++{194, 64, 119}, ++{208, 59, 124}, ++{216, 56, 127}, ++{140, 84, 95}, ++{147, 82, 99}, ++{157, 79, 103}, ++{169, 75, 109}, ++{182, 70, 114}, ++{196, 65, 119}, ++{209, 60, 124}, ++{218, 57, 128}, ++{143, 85, 96}, ++{149, 83, 100}, ++{160, 80, 104}, ++{171, 76, 109}, ++{184, 71, 115}, ++{197, 66, 120}, ++{211, 61, 125}, ++{219, 58, 128}, ++{146, 87, 98}, ++{152, 85, 101}, ++{162, 81, 105}, ++{174, 77, 110}, ++{186, 72, 115}, ++{199, 67, 120}, ++{212, 62, 125}, ++{221, 58, 128}, ++{149, 88, 99}, ++{155, 86, 101}, ++{164, 82, 106}, ++{176, 78, 111}, ++{188, 73, 116}, ++{201, 68, 121}, ++{214, 63, 126}, ++{222, 59, 128}, ++{152, 90, 100}, ++{158, 87, 102}, ++{167, 84, 107}, ++{178, 79, 111}, ++{190, 74, 116}, ++{203, 69, 121}, ++{216, 63, 126}, ++{224, 60, 129}, ++{155, 91, 101}, ++{161, 89, 103}, ++{170, 85, 107}, ++{181, 80, 112}, ++{192, 75, 117}, ++{205, 70, 122}, ++{218, 64, 126}, ++{226, 61, 129}, ++{158, 93, 102}, ++{163, 90, 104}, ++{172, 86, 108}, ++{183, 81, 113}, ++{195, 76, 117}, ++{207, 71, 122}, ++{220, 65, 127}, ++{228, 62, 129}, ++{161, 94, 103}, ++{166, 91, 105}, ++{175, 87, 109}, ++{186, 82, 113}, ++{197, 77, 118}, ++{209, 71, 123}, ++{222, 66, 127}, ++{230, 62, 130}, ++{164, 95, 104}, ++{170, 92, 106}, ++{178, 88, 110}, ++{188, 83, 114}, ++{200, 78, 119}, ++{211, 72, 123}, ++{224, 67, 127}, ++{232, 63, 130}, ++{167, 96, 105}, ++{173, 94, 107}, ++{181, 89, 111}, ++{191, 84, 115}, ++{202, 79, 119}, ++{214, 73, 124}, ++{226, 68, 128}, ++{234, 64, 131}, ++{171, 98, 106}, ++{176, 95, 108}, ++{184, 90, 112}, ++{194, 85, 116}, ++{205, 80, 120}, ++{216, 74, 124}, ++{228, 69, 128}, ++{236, 65, 131}, ++{174, 99, 107}, ++{179, 96, 109}, ++{187, 92, 112}, ++{196, 86, 116}, ++{207, 81, 120}, ++{219, 75, 125}, ++{230, 69, 129}, ++{238, 66, 131}, ++{177, 100, 108}, ++{182, 97, 110}, ++{190, 93, 113}, ++{199, 87, 117}, ++{210, 82, 121}, ++{221, 76, 125}, ++{233, 70, 129}, ++{240, 67, 132}, ++{181, 101, 109}, ++{186, 98, 111}, ++{193, 94, 114}, ++{202, 88, 118}, ++{213, 83, 122}, ++{223, 77, 126}, ++{235, 71, 130}, ++{242, 68, 132}, ++{184, 102, 110}, ++{189, 99, 112}, ++{196, 95, 115}, ++{205, 89, 118}, ++{215, 84, 122}, ++{226, 78, 126}, ++{237, 72, 130}, ++{245, 68, 132}, ++{188, 103, 111}, ++{192, 100, 113}, ++{199, 95, 116}, ++{208, 90, 119}, ++{218, 85, 123}, ++{229, 79, 127}, ++{240, 73, 130}, ++{247, 69, 133}, ++{189, 103, 112}, ++{194, 100, 113}, ++{201, 96, 116}, ++{210, 91, 119}, ++{219, 85, 123}, ++{230, 79, 127}, ++{241, 73, 131}, ++{248, 70, 133}, ++{189, 103, 112}, ++{194, 100, 113}, ++{201, 96, 116}, ++{210, 91, 119}, ++{219, 85, 123}, ++{230, 79, 127}, ++{241, 73, 131}, ++{248, 70, 133}, ++{189, 103, 112}, ++{194, 100, 113}, ++{201, 96, 116}, ++{210, 91, 119}, ++{219, 85, 123}, ++{230, 79, 127}, ++{241, 73, 131}, ++{248, 70, 133}, ++{189, 103, 112}, ++{194, 100, 113}, ++{201, 96, 116}, ++{210, 91, 119}, ++{219, 85, 123}, ++{230, 79, 127}, ++{241, 73, 131}, ++{248, 70, 133}, ++{124, 67, 85}, ++{132, 67, 89}, ++{144, 66, 96}, ++{158, 65, 102}, ++{172, 62, 108}, ++{187, 58, 115}, ++{201, 54, 120}, ++{210, 51, 124}, ++{124, 67, 85}, ++{132, 67, 90}, ++{144, 67, 96}, ++{158, 65, 102}, ++{172, 62, 109}, ++{187, 58, 115}, ++{201, 54, 120}, ++{210, 51, 124}, ++{125, 67, 85}, ++{133, 68, 90}, ++{145, 67, 96}, ++{158, 65, 102}, ++{173, 62, 109}, ++{187, 58, 115}, ++{201, 54, 120}, ++{210, 51, 124}, ++{125, 68, 86}, ++{133, 68, 90}, ++{145, 67, 96}, ++{159, 65, 102}, ++{173, 62, 109}, ++{187, 58, 115}, ++{202, 54, 120}, ++{211, 52, 124}, ++{127, 69, 86}, ++{135, 69, 91}, ++{146, 68, 96}, ++{160, 66, 103}, ++{174, 63, 109}, ++{188, 59, 115}, ++{202, 55, 121}, ++{211, 52, 124}, ++{128, 70, 87}, ++{136, 70, 91}, ++{147, 69, 97}, ++{161, 66, 103}, ++{175, 63, 109}, ++{189, 59, 115}, ++{203, 55, 121}, ++{212, 52, 124}, ++{129, 72, 88}, ++{137, 71, 92}, ++{149, 70, 97}, ++{162, 67, 103}, ++{176, 64, 110}, ++{190, 60, 115}, ++{204, 55, 121}, ++{213, 53, 124}, ++{131, 73, 88}, ++{139, 73, 92}, ++{150, 71, 98}, ++{163, 68, 104}, ++{177, 64, 110}, ++{191, 60, 116}, ++{205, 56, 121}, ++{214, 53, 124}, ++{133, 75, 89}, ++{141, 74, 93}, ++{152, 72, 98}, ++{164, 69, 104}, ++{178, 65, 110}, ++{192, 61, 116}, ++{206, 56, 121}, ++{215, 54, 125}, ++{135, 76, 90}, ++{143, 75, 94}, ++{153, 73, 99}, ++{166, 70, 105}, ++{179, 66, 111}, ++{193, 62, 116}, ++{207, 57, 122}, ++{216, 54, 125}, ++{138, 78, 91}, ++{145, 77, 95}, ++{155, 74, 100}, ++{168, 71, 105}, ++{181, 67, 111}, ++{194, 62, 117}, ++{208, 58, 122}, ++{217, 55, 125}, ++{140, 80, 92}, ++{147, 78, 96}, ++{157, 75, 101}, ++{169, 72, 106}, ++{182, 68, 112}, ++{196, 63, 117}, ++{209, 58, 122}, ++{218, 55, 125}, ++{143, 81, 93}, ++{149, 80, 97}, ++{159, 77, 101}, ++{171, 73, 107}, ++{184, 69, 112}, ++{197, 64, 117}, ++{211, 59, 123}, ++{219, 56, 126}, ++{145, 83, 94}, ++{152, 81, 98}, ++{162, 78, 102}, ++{173, 74, 107}, ++{186, 70, 113}, ++{199, 65, 118}, ++{212, 60, 123}, ++{221, 57, 126}, ++{148, 85, 95}, ++{154, 83, 98}, ++{164, 79, 103}, ++{176, 75, 108}, ++{188, 71, 113}, ++{201, 66, 118}, ++{214, 61, 123}, ++{222, 57, 126}, ++{151, 86, 97}, ++{157, 84, 99}, ++{167, 80, 104}, ++{178, 76, 109}, ++{190, 72, 114}, ++{203, 67, 119}, ++{216, 61, 124}, ++{224, 58, 127}, ++{154, 88, 98}, ++{160, 85, 100}, ++{169, 82, 105}, ++{180, 77, 109}, ++{192, 73, 114}, ++{205, 67, 119}, ++{217, 62, 124}, ++{226, 59, 127}, ++{157, 89, 99}, ++{163, 87, 101}, ++{172, 83, 105}, ++{182, 78, 110}, ++{194, 74, 115}, ++{207, 68, 120}, ++{219, 63, 124}, ++{227, 60, 127}, ++{160, 91, 100}, ++{166, 88, 102}, ++{174, 84, 106}, ++{185, 80, 111}, ++{197, 75, 115}, ++{209, 69, 120}, ++{221, 64, 125}, ++{229, 61, 128}, ++{163, 92, 101}, ++{169, 89, 103}, ++{177, 85, 107}, ++{187, 81, 111}, ++{199, 76, 116}, ++{211, 70, 121}, ++{223, 65, 125}, ++{231, 61, 128}, ++{166, 93, 102}, ++{172, 91, 104}, ++{180, 87, 108}, ++{190, 82, 112}, ++{201, 77, 117}, ++{213, 71, 121}, ++{225, 66, 126}, ++{233, 62, 128}, ++{169, 94, 103}, ++{175, 92, 105}, ++{183, 88, 109}, ++{193, 83, 113}, ++{204, 78, 117}, ++{215, 72, 122}, ++{227, 67, 126}, ++{235, 63, 129}, ++{173, 96, 104}, ++{178, 93, 106}, ++{186, 89, 110}, ++{195, 84, 114}, ++{206, 79, 118}, ++{218, 73, 122}, ++{230, 68, 126}, ++{237, 64, 129}, ++{176, 97, 105}, ++{181, 94, 107}, ++{189, 90, 111}, ++{198, 85, 114}, ++{209, 80, 118}, ++{220, 74, 123}, ++{232, 68, 127}, ++{239, 65, 130}, ++{179, 98, 106}, ++{184, 95, 108}, ++{192, 91, 111}, ++{201, 86, 115}, ++{211, 81, 119}, ++{222, 75, 123}, ++{234, 69, 127}, ++{241, 66, 130}, ++{183, 99, 107}, ++{187, 96, 109}, ++{195, 92, 112}, ++{204, 87, 116}, ++{214, 82, 120}, ++{225, 76, 124}, ++{236, 70, 128}, ++{244, 67, 130}, ++{186, 100, 108}, ++{191, 97, 110}, ++{198, 93, 113}, ++{207, 88, 117}, ++{217, 83, 120}, ++{228, 77, 124}, ++{239, 71, 128}, ++{246, 68, 131}, ++{189, 101, 109}, ++{194, 98, 111}, ++{201, 94, 114}, ++{210, 89, 117}, ++{220, 83, 121}, ++{230, 78, 125}, ++{241, 72, 129}, ++{248, 68, 131}, ++{191, 101, 110}, ++{196, 99, 111}, ++{203, 94, 114}, ++{211, 89, 118}, ++{221, 84, 121}, ++{231, 78, 125}, ++{242, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 99, 111}, ++{203, 94, 114}, ++{211, 89, 118}, ++{221, 84, 121}, ++{231, 78, 125}, ++{242, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 99, 111}, ++{203, 94, 114}, ++{211, 89, 118}, ++{221, 84, 121}, ++{231, 78, 125}, ++{242, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 99, 111}, ++{203, 94, 114}, ++{211, 89, 118}, ++{221, 84, 121}, ++{231, 78, 125}, ++{242, 72, 129}, ++{249, 69, 131}, ++{127, 64, 83}, ++{135, 65, 87}, ++{147, 64, 93}, ++{160, 63, 100}, ++{174, 60, 106}, ++{188, 57, 112}, ++{203, 53, 118}, ++{212, 50, 122}, ++{127, 64, 83}, ++{135, 65, 87}, ++{147, 65, 94}, ++{160, 63, 100}, ++{174, 60, 106}, ++{189, 57, 112}, ++{203, 53, 118}, ++{212, 50, 122}, ++{127, 65, 83}, ++{135, 65, 88}, ++{147, 65, 94}, ++{161, 63, 100}, ++{175, 60, 106}, ++{189, 57, 113}, ++{203, 53, 118}, ++{212, 50, 122}, ++{128, 66, 84}, ++{136, 66, 88}, ++{148, 65, 94}, ++{161, 64, 100}, ++{175, 61, 107}, ++{189, 57, 113}, ++{204, 53, 118}, ++{212, 50, 122}, ++{129, 67, 84}, ++{137, 67, 88}, ++{149, 66, 94}, ++{162, 64, 101}, ++{176, 61, 107}, ++{190, 57, 113}, ++{204, 53, 119}, ++{213, 51, 122}, ++{131, 68, 85}, ++{138, 68, 89}, ++{150, 67, 95}, ++{163, 65, 101}, ++{177, 62, 107}, ++{191, 58, 113}, ++{205, 54, 119}, ++{214, 51, 122}, ++{132, 69, 86}, ++{140, 69, 90}, ++{151, 68, 95}, ++{164, 65, 101}, ++{178, 62, 107}, ++{192, 58, 113}, ++{206, 54, 119}, ++{214, 51, 122}, ++{134, 71, 86}, ++{141, 70, 90}, ++{152, 69, 96}, ++{165, 66, 102}, ++{179, 63, 108}, ++{193, 59, 114}, ++{206, 55, 119}, ++{215, 52, 122}, ++{136, 72, 87}, ++{143, 72, 91}, ++{154, 70, 96}, ++{167, 67, 102}, ++{180, 64, 108}, ++{194, 60, 114}, ++{207, 55, 119}, ++{216, 52, 123}, ++{138, 74, 88}, ++{145, 73, 92}, ++{156, 71, 97}, ++{168, 68, 103}, ++{181, 64, 109}, ++{195, 60, 114}, ++{209, 56, 120}, ++{217, 53, 123}, ++{140, 76, 89}, ++{147, 74, 93}, ++{158, 72, 98}, ++{170, 69, 103}, ++{183, 65, 109}, ++{196, 61, 115}, ++{210, 57, 120}, ++{218, 54, 123}, ++{143, 77, 90}, ++{149, 76, 94}, ++{160, 73, 98}, ++{172, 70, 104}, ++{184, 66, 110}, ++{198, 62, 115}, ++{211, 57, 120}, ++{220, 54, 123}, ++{145, 79, 91}, ++{152, 77, 95}, ++{162, 75, 99}, ++{173, 71, 105}, ++{186, 67, 110}, ++{199, 63, 115}, ++{213, 58, 121}, ++{221, 55, 124}, ++{148, 81, 92}, ++{154, 79, 95}, ++{164, 76, 100}, ++{175, 72, 105}, ++{188, 68, 111}, ++{201, 63, 116}, ++{214, 59, 121}, ++{222, 56, 124}, ++{150, 82, 93}, ++{157, 80, 96}, ++{166, 77, 101}, ++{178, 73, 106}, ++{190, 69, 111}, ++{203, 64, 116}, ++{216, 59, 121}, ++{224, 56, 124}, ++{153, 84, 95}, ++{159, 82, 97}, ++{169, 79, 102}, ++{180, 75, 107}, ++{192, 70, 112}, ++{204, 65, 117}, ++{217, 60, 122}, ++{225, 57, 125}, ++{156, 85, 96}, ++{162, 83, 98}, ++{171, 80, 103}, ++{182, 76, 107}, ++{194, 71, 112}, ++{206, 66, 117}, ++{219, 61, 122}, ++{227, 58, 125}, ++{159, 87, 97}, ++{165, 85, 99}, ++{174, 81, 103}, ++{184, 77, 108}, ++{196, 72, 113}, ++{208, 67, 118}, ++{221, 62, 122}, ++{229, 59, 125}, ++{162, 88, 98}, ++{168, 86, 100}, ++{176, 82, 104}, ++{187, 78, 109}, ++{198, 73, 113}, ++{210, 68, 118}, ++{223, 63, 123}, ++{231, 60, 126}, ++{165, 90, 99}, ++{171, 87, 101}, ++{179, 84, 105}, ++{189, 79, 109}, ++{201, 74, 114}, ++{212, 69, 119}, ++{225, 64, 123}, ++{233, 60, 126}, ++{168, 91, 100}, ++{174, 89, 102}, ++{182, 85, 106}, ++{192, 80, 110}, ++{203, 75, 115}, ++{215, 70, 119}, ++{227, 65, 124}, ++{234, 61, 127}, ++{171, 92, 101}, ++{177, 90, 103}, ++{185, 86, 107}, ++{194, 81, 111}, ++{205, 76, 115}, ++{217, 71, 120}, ++{229, 66, 124}, ++{236, 62, 127}, ++{175, 94, 102}, ++{180, 91, 104}, ++{188, 87, 108}, ++{197, 82, 112}, ++{208, 77, 116}, ++{219, 72, 120}, ++{231, 66, 125}, ++{239, 63, 127}, ++{178, 95, 103}, ++{183, 92, 105}, ++{191, 88, 109}, ++{200, 83, 112}, ++{210, 78, 117}, ++{222, 73, 121}, ++{233, 67, 125}, ++{241, 64, 128}, ++{181, 96, 104}, ++{186, 93, 106}, ++{193, 89, 109}, ++{203, 85, 113}, ++{213, 79, 117}, ++{224, 74, 121}, ++{235, 68, 126}, ++{243, 65, 128}, ++{185, 97, 105}, ++{189, 94, 107}, ++{197, 90, 110}, ++{206, 86, 114}, ++{216, 80, 118}, ++{227, 75, 122}, ++{238, 69, 126}, ++{245, 66, 129}, ++{188, 98, 106}, ++{192, 95, 108}, ++{200, 91, 111}, ++{208, 87, 115}, ++{218, 81, 119}, ++{229, 76, 123}, ++{240, 70, 127}, ++{247, 67, 129}, ++{191, 99, 107}, ++{196, 96, 109}, ++{203, 92, 112}, ++{211, 88, 115}, ++{221, 82, 119}, ++{232, 77, 123}, ++{243, 71, 127}, ++{250, 67, 129}, ++{193, 100, 108}, ++{197, 97, 110}, ++{204, 93, 112}, ++{213, 88, 116}, ++{222, 83, 119}, ++{233, 77, 123}, ++{244, 71, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 110}, ++{204, 93, 112}, ++{213, 88, 116}, ++{222, 83, 119}, ++{233, 77, 123}, ++{244, 71, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 110}, ++{204, 93, 112}, ++{213, 88, 116}, ++{222, 83, 119}, ++{233, 77, 123}, ++{244, 71, 127}, ++{251, 68, 130}, ++{193, 100, 108}, ++{197, 97, 110}, ++{204, 93, 112}, ++{213, 88, 116}, ++{222, 83, 119}, ++{233, 77, 123}, ++{244, 71, 127}, ++{251, 68, 130}, ++{130, 62, 81}, ++{137, 62, 85}, ++{149, 62, 91}, ++{162, 61, 98}, ++{176, 58, 104}, ++{190, 55, 110}, ++{205, 51, 116}, ++{213, 49, 120}, ++{130, 62, 81}, ++{138, 63, 85}, ++{149, 62, 91}, ++{162, 61, 98}, ++{176, 59, 104}, ++{190, 55, 110}, ++{205, 51, 116}, ++{213, 49, 120}, ++{130, 62, 81}, ++{138, 63, 86}, ++{150, 63, 92}, ++{163, 61, 98}, ++{177, 59, 104}, ++{191, 55, 110}, ++{205, 52, 116}, ++{214, 49, 120}, ++{131, 63, 82}, ++{139, 64, 86}, ++{150, 63, 92}, ++{163, 62, 98}, ++{177, 59, 105}, ++{191, 56, 111}, ++{205, 52, 116}, ++{214, 49, 120}, ++{132, 64, 82}, ++{140, 64, 86}, ++{151, 64, 92}, ++{164, 62, 99}, ++{178, 59, 105}, ++{192, 56, 111}, ++{206, 52, 116}, ++{215, 50, 120}, ++{133, 65, 83}, ++{141, 66, 87}, ++{152, 65, 93}, ++{165, 63, 99}, ++{179, 60, 105}, ++{193, 57, 111}, ++{207, 53, 117}, ++{215, 50, 120}, ++{135, 67, 84}, ++{142, 67, 88}, ++{153, 66, 93}, ++{166, 64, 99}, ++{180, 61, 105}, ++{193, 57, 111}, ++{207, 53, 117}, ++{216, 50, 120}, ++{137, 68, 85}, ++{144, 68, 88}, ++{155, 67, 94}, ++{167, 64, 100}, ++{181, 61, 106}, ++{194, 58, 112}, ++{208, 54, 117}, ++{217, 51, 120}, ++{139, 70, 85}, ++{146, 69, 89}, ++{156, 68, 94}, ++{169, 65, 100}, ++{182, 62, 106}, ++{195, 58, 112}, ++{209, 54, 117}, ++{218, 51, 121}, ++{141, 71, 86}, ++{147, 71, 90}, ++{158, 69, 95}, ++{170, 66, 101}, ++{183, 63, 107}, ++{197, 59, 112}, ++{210, 55, 118}, ++{219, 52, 121}, ++{143, 73, 87}, ++{150, 72, 91}, ++{160, 70, 96}, ++{172, 67, 101}, ++{185, 64, 107}, ++{198, 60, 113}, ++{211, 55, 118}, ++{220, 53, 121}, ++{145, 75, 88}, ++{152, 74, 92}, ++{162, 71, 96}, ++{174, 68, 102}, ++{186, 65, 107}, ++{199, 60, 113}, ++{213, 56, 118}, ++{221, 53, 121}, ++{148, 77, 89}, ++{154, 75, 92}, ++{164, 73, 97}, ++{175, 69, 103}, ++{188, 66, 108}, ++{201, 61, 113}, ++{214, 57, 119}, ++{223, 54, 122}, ++{150, 78, 90}, ++{156, 77, 93}, ++{166, 74, 98}, ++{177, 71, 103}, ++{190, 67, 109}, ++{203, 62, 114}, ++{216, 58, 119}, ++{224, 55, 122}, ++{153, 80, 91}, ++{159, 78, 94}, ++{168, 75, 99}, ++{179, 72, 104}, ++{192, 68, 109}, ++{204, 63, 114}, ++{217, 58, 119}, ++{225, 55, 122}, ++{156, 82, 93}, ++{161, 80, 95}, ++{171, 77, 100}, ++{182, 73, 105}, ++{194, 69, 110}, ++{206, 64, 115}, ++{219, 59, 120}, ++{227, 56, 123}, ++{158, 83, 94}, ++{164, 81, 96}, ++{173, 78, 101}, ++{184, 74, 105}, ++{196, 70, 110}, ++{208, 65, 115}, ++{221, 60, 120}, ++{229, 57, 123}, ++{161, 85, 95}, ++{167, 83, 97}, ++{176, 79, 101}, ++{186, 75, 106}, ++{198, 71, 111}, ++{210, 66, 116}, ++{222, 61, 121}, ++{230, 58, 123}, ++{164, 86, 96}, ++{170, 84, 98}, ++{178, 81, 102}, ++{189, 76, 107}, ++{200, 72, 111}, ++{212, 67, 116}, ++{224, 62, 121}, ++{232, 59, 124}, ++{167, 88, 97}, ++{173, 85, 99}, ++{181, 82, 103}, ++{191, 78, 107}, ++{202, 73, 112}, ++{214, 68, 117}, ++{226, 63, 121}, ++{234, 59, 124}, ++{170, 89, 98}, ++{176, 87, 100}, ++{184, 83, 104}, ++{194, 79, 108}, ++{205, 74, 113}, ++{216, 69, 117}, ++{228, 64, 122}, ++{236, 60, 125}, ++{174, 90, 99}, ++{179, 88, 101}, ++{187, 84, 105}, ++{196, 80, 109}, ++{207, 75, 113}, ++{219, 70, 118}, ++{230, 64, 122}, ++{238, 61, 125}, ++{177, 92, 100}, ++{182, 89, 102}, ++{189, 85, 106}, ++{199, 81, 110}, ++{210, 76, 114}, ++{221, 71, 118}, ++{233, 65, 123}, ++{240, 62, 126}, ++{180, 93, 101}, ++{185, 90, 103}, ++{192, 87, 107}, ++{202, 82, 111}, ++{212, 77, 115}, ++{223, 72, 119}, ++{235, 66, 123}, ++{242, 63, 126}, ++{183, 94, 102}, ++{188, 92, 104}, ++{195, 88, 108}, ++{204, 83, 111}, ++{215, 78, 115}, ++{226, 73, 120}, ++{237, 67, 124}, ++{244, 64, 126}, ++{186, 95, 103}, ++{191, 93, 105}, ++{198, 89, 108}, ++{207, 84, 112}, ++{217, 79, 116}, ++{228, 74, 120}, ++{239, 68, 124}, ++{246, 65, 127}, ++{190, 96, 104}, ++{194, 94, 106}, ++{201, 90, 109}, ++{210, 85, 113}, ++{220, 80, 117}, ++{231, 75, 121}, ++{242, 69, 125}, ++{249, 66, 127}, ++{193, 97, 105}, ++{197, 95, 107}, ++{204, 91, 110}, ++{213, 86, 114}, ++{223, 81, 117}, ++{233, 75, 121}, ++{244, 70, 125}, ++{251, 66, 128}, ++{195, 98, 106}, ++{199, 95, 108}, ++{206, 91, 111}, ++{214, 87, 114}, ++{224, 81, 118}, ++{234, 76, 122}, ++{245, 70, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{199, 95, 108}, ++{206, 91, 111}, ++{214, 87, 114}, ++{224, 81, 118}, ++{234, 76, 122}, ++{245, 70, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{199, 95, 108}, ++{206, 91, 111}, ++{214, 87, 114}, ++{224, 81, 118}, ++{234, 76, 122}, ++{245, 70, 125}, ++{252, 67, 128}, ++{195, 98, 106}, ++{199, 95, 108}, ++{206, 91, 111}, ++{214, 87, 114}, ++{224, 81, 118}, ++{234, 76, 122}, ++{245, 70, 125}, ++{252, 67, 128}, ++{132, 59, 79}, ++{140, 60, 83}, ++{151, 60, 89}, ++{164, 59, 96}, ++{178, 57, 102}, ++{192, 54, 108}, ++{206, 50, 114}, ++{215, 48, 118}, ++{133, 59, 79}, ++{140, 60, 84}, ++{152, 60, 89}, ++{165, 59, 96}, ++{178, 57, 102}, ++{192, 54, 108}, ++{206, 50, 114}, ++{215, 48, 118}, ++{133, 60, 80}, ++{141, 61, 84}, ++{152, 61, 90}, ++{165, 59, 96}, ++{179, 57, 102}, ++{193, 54, 108}, ++{207, 50, 114}, ++{215, 48, 118}, ++{134, 61, 80}, ++{141, 61, 84}, ++{153, 61, 90}, ++{166, 60, 96}, ++{179, 57, 103}, ++{193, 54, 109}, ++{207, 51, 114}, ++{216, 48, 118}, ++{135, 62, 80}, ++{142, 62, 85}, ++{153, 62, 90}, ++{166, 60, 96}, ++{180, 58, 103}, ++{194, 55, 109}, ++{208, 51, 114}, ++{216, 48, 118}, ++{136, 63, 81}, ++{144, 63, 85}, ++{154, 63, 91}, ++{167, 61, 97}, ++{181, 58, 103}, ++{194, 55, 109}, ++{208, 51, 115}, ++{217, 49, 118}, ++{138, 64, 82}, ++{145, 64, 86}, ++{156, 64, 91}, ++{168, 62, 97}, ++{182, 59, 103}, ++{195, 56, 109}, ++{209, 52, 115}, ++{218, 49, 118}, ++{139, 66, 83}, ++{146, 66, 86}, ++{157, 65, 92}, ++{169, 63, 98}, ++{183, 60, 104}, ++{196, 56, 110}, ++{210, 52, 115}, ++{218, 50, 118}, ++{141, 67, 83}, ++{148, 67, 87}, ++{159, 66, 92}, ++{171, 64, 98}, ++{184, 60, 104}, ++{197, 57, 110}, ++{211, 53, 115}, ++{219, 50, 119}, ++{143, 69, 84}, ++{150, 68, 88}, ++{160, 67, 93}, ++{172, 64, 99}, ++{185, 61, 104}, ++{199, 58, 110}, ++{212, 53, 116}, ++{220, 51, 119}, ++{145, 71, 85}, ++{152, 70, 89}, ++{162, 68, 94}, ++{174, 66, 99}, ++{187, 62, 105}, ++{200, 58, 111}, ++{213, 54, 116}, ++{222, 51, 119}, ++{148, 72, 86}, ++{154, 71, 90}, ++{164, 69, 94}, ++{176, 67, 100}, ++{188, 63, 105}, ++{201, 59, 111}, ++{214, 55, 116}, ++{223, 52, 119}, ++{150, 74, 87}, ++{156, 73, 91}, ++{166, 71, 95}, ++{177, 68, 101}, ++{190, 64, 106}, ++{203, 60, 111}, ++{216, 56, 117}, ++{224, 53, 120}, ++{153, 76, 88}, ++{159, 75, 91}, ++{168, 72, 96}, ++{179, 69, 101}, ++{192, 65, 107}, ++{204, 61, 112}, ++{217, 56, 117}, ++{226, 53, 120}, ++{155, 78, 89}, ++{161, 76, 92}, ++{170, 73, 97}, ++{181, 70, 102}, ++{194, 66, 107}, ++{206, 62, 112}, ++{219, 57, 117}, ++{227, 54, 120}, ++{158, 79, 91}, ++{164, 78, 93}, ++{173, 75, 98}, ++{184, 71, 103}, ++{195, 67, 108}, ++{208, 63, 113}, ++{221, 58, 118}, ++{229, 55, 121}, ++{161, 81, 92}, ++{166, 79, 94}, ++{175, 76, 99}, ++{186, 72, 103}, ++{198, 68, 108}, ++{210, 64, 113}, ++{222, 59, 118}, ++{230, 56, 121}, ++{164, 82, 93}, ++{169, 81, 95}, ++{178, 77, 99}, ++{188, 74, 104}, ++{200, 69, 109}, ++{212, 65, 114}, ++{224, 60, 119}, ++{232, 57, 122}, ++{166, 84, 94}, ++{172, 82, 96}, ++{180, 79, 100}, ++{191, 75, 105}, ++{202, 70, 110}, ++{214, 66, 114}, ++{226, 61, 119}, ++{234, 57, 122}, ++{169, 86, 95}, ++{175, 83, 97}, ++{183, 80, 101}, ++{193, 76, 106}, ++{204, 71, 110}, ++{216, 66, 115}, ++{228, 62, 120}, ++{236, 58, 122}, ++{172, 87, 96}, ++{178, 85, 98}, ++{186, 81, 102}, ++{196, 77, 106}, ++{206, 72, 111}, ++{218, 67, 115}, ++{230, 62, 120}, ++{237, 59, 123}, ++{176, 88, 97}, ++{181, 86, 99}, ++{188, 82, 103}, ++{198, 78, 107}, ++{209, 73, 111}, ++{220, 68, 116}, ++{232, 63, 120}, ++{239, 60, 123}, ++{179, 90, 98}, ++{184, 87, 100}, ++{191, 84, 104}, ++{201, 79, 108}, ++{211, 75, 112}, ++{222, 69, 117}, ++{234, 64, 121}, ++{241, 61, 124}, ++{182, 91, 99}, ++{187, 89, 101}, ++{194, 85, 105}, ++{203, 80, 109}, ++{214, 76, 113}, ++{225, 70, 117}, ++{236, 65, 121}, ++{244, 62, 124}, ++{185, 92, 100}, ++{190, 90, 102}, ++{197, 86, 106}, ++{206, 82, 109}, ++{216, 77, 114}, ++{227, 71, 118}, ++{238, 66, 122}, ++{246, 63, 125}, ++{188, 93, 102}, ++{193, 91, 103}, ++{200, 87, 107}, ++{209, 83, 110}, ++{219, 78, 114}, ++{230, 72, 118}, ++{241, 67, 122}, ++{248, 64, 125}, ++{192, 94, 103}, ++{196, 92, 104}, ++{203, 88, 107}, ++{212, 84, 111}, ++{222, 79, 115}, ++{232, 73, 119}, ++{243, 68, 123}, ++{250, 65, 126}, ++{195, 96, 104}, ++{199, 93, 105}, ++{206, 89, 108}, ++{215, 85, 112}, ++{224, 80, 116}, ++{235, 74, 119}, ++{245, 69, 123}, ++{252, 65, 126}, ++{197, 96, 104}, ++{201, 94, 106}, ++{208, 90, 109}, ++{216, 85, 112}, ++{226, 80, 116}, ++{236, 75, 120}, ++{247, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{201, 94, 106}, ++{208, 90, 109}, ++{216, 85, 112}, ++{226, 80, 116}, ++{236, 75, 120}, ++{247, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{201, 94, 106}, ++{208, 90, 109}, ++{216, 85, 112}, ++{226, 80, 116}, ++{236, 75, 120}, ++{247, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{201, 94, 106}, ++{208, 90, 109}, ++{216, 85, 112}, ++{226, 80, 116}, ++{236, 75, 120}, ++{247, 69, 124}, ++{254, 66, 126}, ++{135, 57, 77}, ++{143, 58, 82}, ++{154, 58, 87}, ++{167, 57, 94}, ++{180, 55, 100}, ++{194, 52, 106}, ++{208, 49, 112}, ++{217, 47, 116}, ++{135, 57, 78}, ++{143, 58, 82}, ++{154, 58, 87}, ++{167, 57, 94}, ++{180, 55, 100}, ++{194, 52, 106}, ++{208, 49, 112}, ++{217, 47, 116}, ++{136, 57, 78}, ++{143, 58, 82}, ++{154, 59, 88}, ++{167, 58, 94}, ++{181, 55, 100}, ++{195, 53, 106}, ++{208, 49, 112}, ++{217, 47, 116}, ++{137, 58, 78}, ++{144, 59, 82}, ++{155, 59, 88}, ++{168, 58, 94}, ++{181, 56, 100}, ++{195, 53, 107}, ++{209, 49, 112}, ++{217, 47, 116}, ++{138, 59, 79}, ++{145, 60, 83}, ++{156, 60, 88}, ++{168, 59, 94}, ++{182, 56, 101}, ++{196, 53, 107}, ++{209, 50, 112}, ++{218, 47, 116}, ++{139, 60, 79}, ++{146, 61, 83}, ++{157, 61, 89}, ++{169, 59, 95}, ++{183, 57, 101}, ++{196, 54, 107}, ++{210, 50, 113}, ++{219, 48, 116}, ++{140, 62, 80}, ++{147, 62, 84}, ++{158, 62, 89}, ++{170, 60, 95}, ++{184, 57, 101}, ++{197, 54, 107}, ++{211, 51, 113}, ++{219, 48, 116}, ++{142, 63, 81}, ++{149, 63, 84}, ++{159, 63, 90}, ++{172, 61, 96}, ++{185, 58, 102}, ++{198, 55, 108}, ++{212, 51, 113}, ++{220, 49, 116}, ++{144, 65, 82}, ++{151, 65, 85}, ++{161, 64, 90}, ++{173, 62, 96}, ++{186, 59, 102}, ++{199, 55, 108}, ++{213, 52, 113}, ++{221, 49, 117}, ++{146, 67, 82}, ++{152, 66, 86}, ++{163, 65, 91}, ++{174, 63, 97}, ++{187, 60, 102}, ++{200, 56, 108}, ++{214, 52, 114}, ++{222, 50, 117}, ++{148, 68, 83}, ++{154, 68, 87}, ++{164, 66, 92}, ++{176, 64, 97}, ++{189, 61, 103}, ++{202, 57, 109}, ++{215, 53, 114}, ++{223, 50, 117}, ++{150, 70, 84}, ++{156, 69, 88}, ++{166, 67, 92}, ++{178, 65, 98}, ++{190, 62, 103}, ++{203, 58, 109}, ++{216, 54, 114}, ++{224, 51, 118}, ++{152, 72, 85}, ++{159, 71, 89}, ++{168, 69, 93}, ++{180, 66, 99}, ++{192, 62, 104}, ++{205, 59, 109}, ++{218, 54, 115}, ++{226, 52, 118}, ++{155, 74, 86}, ++{161, 72, 90}, ++{170, 70, 94}, ++{181, 67, 99}, ++{194, 63, 105}, ++{206, 59, 110}, ++{219, 55, 115}, ++{227, 52, 118}, ++{158, 75, 88}, ++{163, 74, 90}, ++{173, 71, 95}, ++{183, 68, 100}, ++{195, 64, 105}, ++{208, 60, 110}, ++{221, 56, 115}, ++{229, 53, 119}, ++{160, 77, 89}, ++{166, 75, 91}, ++{175, 73, 96}, ++{186, 69, 101}, ++{197, 66, 106}, ++{210, 61, 111}, ++{222, 57, 116}, ++{230, 54, 119}, ++{163, 79, 90}, ++{169, 77, 92}, ++{177, 74, 97}, ++{188, 71, 101}, ++{199, 67, 106}, ++{211, 62, 111}, ++{224, 58, 116}, ++{232, 55, 119}, ++{166, 80, 91}, ++{171, 78, 93}, ++{180, 76, 97}, ++{190, 72, 102}, ++{201, 68, 107}, ++{213, 63, 112}, ++{226, 59, 117}, ++{233, 56, 120}, ++{169, 82, 92}, ++{174, 80, 94}, ++{182, 77, 98}, ++{192, 73, 103}, ++{204, 69, 108}, ++{215, 64, 112}, ++{228, 59, 117}, ++{235, 56, 120}, ++{172, 83, 93}, ++{177, 81, 96}, ++{185, 78, 99}, ++{195, 74, 104}, ++{206, 70, 108}, ++{217, 65, 113}, ++{229, 60, 118}, ++{237, 57, 121}, ++{175, 85, 94}, ++{180, 83, 97}, ++{188, 79, 100}, ++{197, 75, 104}, ++{208, 71, 109}, ++{220, 66, 114}, ++{231, 61, 118}, ++{239, 58, 121}, ++{178, 86, 95}, ++{183, 84, 98}, ++{190, 81, 101}, ++{200, 77, 105}, ++{211, 72, 110}, ++{222, 67, 114}, ++{233, 62, 119}, ++{241, 59, 121}, ++{181, 88, 96}, ++{186, 85, 99}, ++{193, 82, 102}, ++{203, 78, 106}, ++{213, 73, 110}, ++{224, 68, 115}, ++{236, 63, 119}, ++{243, 60, 122}, ++{184, 89, 97}, ++{189, 87, 100}, ++{196, 83, 103}, ++{205, 79, 107}, ++{215, 74, 111}, ++{226, 69, 115}, ++{238, 64, 120}, ++{245, 61, 122}, ++{187, 90, 99}, ++{192, 88, 101}, ++{199, 84, 104}, ++{208, 80, 108}, ++{218, 75, 112}, ++{229, 70, 116}, ++{240, 65, 120}, ++{247, 62, 123}, ++{190, 91, 100}, ++{195, 89, 102}, ++{202, 85, 105}, ++{211, 81, 108}, ++{221, 76, 112}, ++{231, 71, 116}, ++{242, 66, 121}, ++{249, 63, 123}, ++{193, 93, 101}, ++{198, 90, 103}, ++{205, 87, 106}, ++{213, 82, 109}, ++{223, 77, 113}, ++{234, 72, 117}, ++{245, 67, 121}, ++{252, 64, 124}, ++{197, 94, 102}, ++{201, 91, 104}, ++{208, 88, 106}, ++{216, 83, 110}, ++{226, 78, 114}, ++{236, 73, 118}, ++{247, 68, 122}, ++{254, 64, 124}, ++{198, 94, 102}, ++{203, 92, 104}, ++{209, 88, 107}, ++{218, 84, 110}, ++{227, 79, 114}, ++{237, 74, 118}, ++{248, 68, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{203, 92, 104}, ++{209, 88, 107}, ++{218, 84, 110}, ++{227, 79, 114}, ++{237, 74, 118}, ++{248, 68, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{203, 92, 104}, ++{209, 88, 107}, ++{218, 84, 110}, ++{227, 79, 114}, ++{237, 74, 118}, ++{248, 68, 122}, ++{255, 65, 124}, ++{198, 94, 102}, ++{203, 92, 104}, ++{209, 88, 107}, ++{218, 84, 110}, ++{227, 79, 114}, ++{237, 74, 118}, ++{248, 68, 122}, ++{255, 65, 124}, ++{138, 54, 76}, ++{145, 55, 80}, ++{156, 56, 85}, ++{169, 55, 92}, ++{182, 54, 98}, ++{196, 51, 104}, ++{210, 48, 110}, ++{218, 45, 114}, ++{138, 54, 76}, ++{145, 56, 80}, ++{156, 56, 86}, ++{169, 55, 92}, ++{182, 54, 98}, ++{196, 51, 104}, ++{210, 48, 110}, ++{219, 45, 114}, ++{139, 55, 76}, ++{146, 56, 80}, ++{157, 57, 86}, ++{169, 56, 92}, ++{183, 54, 98}, ++{196, 51, 104}, ++{210, 48, 110}, ++{219, 46, 114}, ++{139, 56, 76}, ++{147, 57, 80}, ++{157, 57, 86}, ++{170, 56, 92}, ++{183, 54, 98}, ++{197, 51, 105}, ++{211, 48, 110}, ++{219, 46, 114}, ++{140, 57, 77}, ++{148, 58, 81}, ++{158, 58, 86}, ++{171, 57, 92}, ++{184, 55, 99}, ++{197, 52, 105}, ++{211, 48, 111}, ++{220, 46, 114}, ++{142, 58, 77}, ++{149, 59, 81}, ++{159, 59, 87}, ++{172, 57, 93}, ++{185, 55, 99}, ++{198, 52, 105}, ++{212, 49, 111}, ++{220, 46, 114}, ++{143, 59, 78}, ++{150, 60, 82}, ++{160, 59, 87}, ++{173, 58, 93}, ++{186, 56, 99}, ++{199, 53, 105}, ++{212, 49, 111}, ++{221, 47, 114}, ++{145, 61, 79}, ++{151, 61, 82}, ++{162, 61, 88}, ++{174, 59, 94}, ++{187, 56, 100}, ++{200, 53, 106}, ++{213, 50, 111}, ++{222, 47, 115}, ++{146, 63, 80}, ++{153, 62, 83}, ++{163, 62, 88}, ++{175, 60, 94}, ++{188, 57, 100}, ++{201, 54, 106}, ++{214, 50, 111}, ++{223, 48, 115}, ++{148, 64, 81}, ++{155, 64, 84}, ++{165, 63, 89}, ++{177, 61, 95}, ++{189, 58, 101}, ++{202, 55, 106}, ++{215, 51, 112}, ++{224, 48, 115}, ++{150, 66, 82}, ++{157, 65, 85}, ++{167, 64, 90}, ++{178, 62, 95}, ++{191, 59, 101}, ++{203, 55, 107}, ++{217, 52, 112}, ++{225, 49, 115}, ++{153, 68, 83}, ++{159, 67, 86}, ++{168, 65, 90}, ++{180, 63, 96}, ++{192, 60, 101}, ++{205, 56, 107}, ++{218, 52, 112}, ++{226, 50, 116}, ++{155, 69, 84}, ++{161, 69, 87}, ++{170, 67, 91}, ++{182, 64, 97}, ++{194, 61, 102}, ++{206, 57, 107}, ++{219, 53, 113}, ++{227, 50, 116}, ++{157, 71, 85}, ++{163, 70, 88}, ++{173, 68, 92}, ++{183, 65, 97}, ++{195, 62, 103}, ++{208, 58, 108}, ++{221, 54, 113}, ++{229, 51, 116}, ++{160, 73, 86}, ++{166, 72, 89}, ++{175, 69, 93}, ++{185, 66, 98}, ++{197, 63, 103}, ++{210, 59, 108}, ++{222, 55, 114}, ++{230, 52, 117}, ++{163, 75, 87}, ++{168, 73, 90}, ++{177, 71, 94}, ++{188, 68, 99}, ++{199, 64, 104}, ++{211, 60, 109}, ++{224, 56, 114}, ++{232, 53, 117}, ++{165, 76, 88}, ++{171, 75, 91}, ++{179, 72, 95}, ++{190, 69, 99}, ++{201, 65, 104}, ++{213, 61, 109}, ++{226, 56, 114}, ++{233, 54, 117}, ++{168, 78, 89}, ++{173, 76, 92}, ++{182, 74, 96}, ++{192, 70, 100}, ++{203, 66, 105}, ++{215, 62, 110}, ++{227, 57, 115}, ++{235, 54, 118}, ++{171, 80, 90}, ++{176, 78, 93}, ++{184, 75, 96}, ++{194, 71, 101}, ++{205, 67, 106}, ++{217, 63, 111}, ++{229, 58, 115}, ++{237, 55, 118}, ++{174, 81, 91}, ++{179, 79, 94}, ++{187, 76, 97}, ++{197, 73, 102}, ++{208, 68, 106}, ++{219, 64, 111}, ++{231, 59, 116}, ++{239, 56, 119}, ++{177, 83, 92}, ++{182, 81, 95}, ++{190, 78, 98}, ++{199, 74, 102}, ++{210, 69, 107}, ++{221, 65, 112}, ++{233, 60, 116}, ++{240, 57, 119}, ++{180, 84, 93}, ++{185, 82, 96}, ++{192, 79, 99}, ++{202, 75, 103}, ++{212, 71, 108}, ++{223, 66, 112}, ++{235, 61, 117}, ++{242, 58, 120}, ++{183, 86, 95}, ++{188, 83, 97}, ++{195, 80, 100}, ++{204, 76, 104}, ++{215, 72, 108}, ++{226, 67, 113}, ++{237, 62, 117}, ++{244, 59, 120}, ++{186, 87, 96}, ++{191, 85, 98}, ++{198, 81, 101}, ++{207, 77, 105}, ++{217, 73, 109}, ++{228, 68, 113}, ++{239, 63, 118}, ++{246, 60, 121}, ++{189, 88, 97}, ++{194, 86, 99}, ++{201, 83, 102}, ++{210, 78, 106}, ++{220, 74, 110}, ++{230, 69, 114}, ++{241, 64, 118}, ++{249, 61, 121}, ++{192, 89, 98}, ++{197, 87, 100}, ++{204, 84, 103}, ++{212, 80, 107}, ++{222, 75, 111}, ++{233, 70, 115}, ++{244, 65, 119}, ++{251, 62, 122}, ++{195, 91, 99}, ++{200, 88, 101}, ++{207, 85, 104}, ++{215, 81, 107}, ++{225, 76, 111}, ++{235, 71, 115}, ++{246, 66, 119}, ++{253, 62, 122}, ++{199, 92, 100}, ++{203, 90, 102}, ++{210, 86, 105}, ++{218, 82, 108}, ++{227, 77, 112}, ++{238, 72, 116}, ++{248, 67, 120}, ++{255, 63, 123}, ++{200, 92, 100}, ++{204, 90, 102}, ++{211, 87, 105}, ++{219, 82, 109}, ++{229, 77, 112}, ++{239, 72, 116}, ++{250, 67, 120}, ++{255, 64, 123}, ++{200, 92, 100}, ++{204, 90, 102}, ++{211, 87, 105}, ++{219, 82, 109}, ++{229, 77, 112}, ++{239, 72, 116}, ++{250, 67, 120}, ++{255, 64, 123}, ++{200, 92, 100}, ++{204, 90, 102}, ++{211, 87, 105}, ++{219, 82, 109}, ++{229, 77, 112}, ++{239, 72, 116}, ++{250, 67, 120}, ++{255, 64, 123}, ++{200, 92, 100}, ++{204, 90, 102}, ++{211, 87, 105}, ++{219, 82, 109}, ++{229, 77, 112}, ++{239, 72, 116}, ++{250, 67, 120}, ++{255, 64, 123}, ++{141, 52, 74}, ++{148, 53, 78}, ++{159, 54, 84}, ++{171, 53, 90}, ++{184, 52, 96}, ++{198, 49, 102}, ++{212, 46, 108}, ++{220, 44, 112}, ++{141, 52, 74}, ++{148, 53, 78}, ++{159, 54, 84}, ++{171, 54, 90}, ++{184, 52, 96}, ++{198, 49, 102}, ++{212, 46, 108}, ++{220, 44, 112}, ++{141, 53, 74}, ++{149, 54, 78}, ++{159, 54, 84}, ++{172, 54, 90}, ++{185, 52, 96}, ++{198, 50, 102}, ++{212, 47, 108}, ++{220, 44, 112}, ++{142, 53, 75}, ++{149, 54, 78}, ++{160, 55, 84}, ++{172, 54, 90}, ++{185, 53, 96}, ++{199, 50, 103}, ++{212, 47, 108}, ++{221, 45, 112}, ++{143, 54, 75}, ++{150, 55, 79}, ++{161, 56, 84}, ++{173, 55, 91}, ++{186, 53, 97}, ++{199, 50, 103}, ++{213, 47, 109}, ++{221, 45, 112}, ++{144, 56, 76}, ++{151, 56, 79}, ++{162, 56, 85}, ++{174, 55, 91}, ++{187, 54, 97}, ++{200, 51, 103}, ++{213, 48, 109}, ++{222, 45, 112}, ++{146, 57, 76}, ++{152, 58, 80}, ++{163, 57, 85}, ++{175, 56, 91}, ++{188, 54, 97}, ++{201, 51, 103}, ++{214, 48, 109}, ++{223, 46, 112}, ++{147, 59, 77}, ++{154, 59, 81}, ++{164, 58, 86}, ++{176, 57, 92}, ++{189, 55, 98}, ++{202, 52, 104}, ++{215, 48, 109}, ++{223, 46, 113}, ++{149, 60, 78}, ++{156, 60, 81}, ++{166, 60, 86}, ++{177, 58, 92}, ++{190, 56, 98}, ++{203, 53, 104}, ++{216, 49, 110}, ++{224, 47, 113}, ++{151, 62, 79}, ++{157, 62, 82}, ++{167, 61, 87}, ++{179, 59, 93}, ++{191, 56, 99}, ++{204, 53, 104}, ++{217, 50, 110}, ++{225, 47, 113}, ++{153, 64, 80}, ++{159, 63, 83}, ++{169, 62, 88}, ++{180, 60, 93}, ++{193, 57, 99}, ++{205, 54, 105}, ++{218, 50, 110}, ++{227, 48, 113}, ++{155, 65, 81}, ++{161, 65, 84}, ++{171, 63, 89}, ++{182, 61, 94}, ++{194, 58, 100}, ++{207, 55, 105}, ++{220, 51, 110}, ++{228, 49, 114}, ++{157, 67, 82}, ++{163, 66, 85}, ++{173, 65, 89}, ++{184, 62, 95}, ++{196, 59, 100}, ++{208, 56, 106}, ++{221, 52, 111}, ++{229, 49, 114}, ++{160, 69, 83}, ++{166, 68, 86}, ++{175, 66, 90}, ++{186, 64, 95}, ++{197, 60, 101}, ++{210, 57, 106}, ++{222, 53, 111}, ++{230, 50, 114}, ++{162, 71, 84}, ++{168, 70, 87}, ++{177, 68, 91}, ++{188, 65, 96}, ++{199, 61, 101}, ++{211, 58, 107}, ++{224, 53, 112}, ++{232, 51, 115}, ++{165, 72, 85}, ++{170, 71, 88}, ++{179, 69, 92}, ++{190, 66, 97}, ++{201, 62, 102}, ++{213, 59, 107}, ++{225, 54, 112}, ++{233, 52, 115}, ++{167, 74, 86}, ++{173, 73, 89}, ++{181, 70, 93}, ++{192, 67, 97}, ++{203, 64, 102}, ++{215, 59, 108}, ++{227, 55, 113}, ++{235, 52, 116}, ++{170, 76, 87}, ++{176, 74, 90}, ++{184, 72, 94}, ++{194, 68, 98}, ++{205, 65, 103}, ++{217, 60, 108}, ++{229, 56, 113}, ++{237, 53, 116}, ++{173, 77, 88}, ++{178, 76, 91}, ++{186, 73, 95}, ++{196, 70, 99}, ++{207, 66, 104}, ++{219, 61, 109}, ++{231, 57, 114}, ++{238, 54, 116}, ++{176, 79, 89}, ++{181, 77, 92}, ++{189, 74, 95}, ++{199, 71, 100}, ++{209, 67, 104}, ++{221, 62, 109}, ++{233, 58, 114}, ++{240, 55, 117}, ++{179, 81, 90}, ++{184, 79, 93}, ++{192, 76, 96}, ++{201, 72, 101}, ++{212, 68, 105}, ++{223, 64, 110}, ++{235, 59, 115}, ++{242, 56, 117}, ++{182, 82, 92}, ++{187, 80, 94}, ++{194, 77, 97}, ++{204, 73, 101}, ++{214, 69, 106}, ++{225, 65, 110}, ++{237, 60, 115}, ++{244, 57, 118}, ++{185, 84, 93}, ++{190, 82, 95}, ++{197, 78, 98}, ++{206, 75, 102}, ++{216, 70, 107}, ++{227, 66, 111}, ++{239, 61, 116}, ++{246, 58, 118}, ++{188, 85, 94}, ++{192, 83, 96}, ++{200, 80, 99}, ++{209, 76, 103}, ++{219, 71, 107}, ++{230, 67, 112}, ++{241, 62, 116}, ++{248, 59, 119}, ++{191, 86, 95}, ++{195, 84, 97}, ++{203, 81, 100}, ++{211, 77, 104}, ++{221, 72, 108}, ++{232, 68, 112}, ++{243, 63, 117}, ++{250, 60, 119}, ++{194, 88, 96}, ++{199, 85, 98}, ++{206, 82, 101}, ++{214, 78, 105}, ++{224, 73, 109}, ++{234, 69, 113}, ++{245, 64, 117}, ++{252, 60, 120}, ++{197, 89, 97}, ++{202, 87, 99}, ++{208, 83, 102}, ++{217, 79, 105}, ++{226, 74, 109}, ++{237, 70, 114}, ++{248, 65, 118}, ++{254, 61, 120}, ++{200, 90, 98}, ++{205, 88, 100}, ++{211, 84, 103}, ++{220, 80, 106}, ++{229, 76, 110}, ++{239, 71, 114}, ++{250, 66, 118}, ++{255, 62, 121}, ++{202, 91, 99}, ++{206, 88, 100}, ++{213, 85, 103}, ++{221, 81, 107}, ++{230, 76, 111}, ++{240, 71, 114}, ++{251, 66, 119}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 88, 100}, ++{213, 85, 103}, ++{221, 81, 107}, ++{230, 76, 111}, ++{240, 71, 114}, ++{251, 66, 119}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 88, 100}, ++{213, 85, 103}, ++{221, 81, 107}, ++{230, 76, 111}, ++{240, 71, 114}, ++{251, 66, 119}, ++{255, 63, 121}, ++{202, 91, 99}, ++{206, 88, 100}, ++{213, 85, 103}, ++{221, 81, 107}, ++{230, 76, 111}, ++{240, 71, 114}, ++{251, 66, 119}, ++{255, 63, 121}, ++{144, 50, 72}, ++{151, 51, 76}, ++{161, 52, 82}, ++{173, 52, 88}, ++{186, 50, 94}, ++{200, 48, 100}, ++{213, 45, 106}, ++{222, 43, 110}, ++{144, 50, 72}, ++{151, 51, 76}, ++{161, 52, 82}, ++{174, 52, 88}, ++{187, 50, 94}, ++{200, 48, 100}, ++{213, 45, 106}, ++{222, 43, 110}, ++{144, 50, 72}, ++{151, 52, 76}, ++{162, 52, 82}, ++{174, 52, 88}, ++{187, 51, 94}, ++{200, 48, 101}, ++{214, 45, 106}, ++{222, 43, 110}, ++{145, 51, 73}, ++{152, 52, 77}, ++{162, 53, 82}, ++{174, 52, 88}, ++{187, 51, 95}, ++{201, 48, 101}, ++{214, 45, 106}, ++{223, 43, 110}, ++{146, 52, 73}, ++{153, 53, 77}, ++{163, 54, 83}, ++{175, 53, 89}, ++{188, 51, 95}, ++{201, 49, 101}, ++{215, 46, 107}, ++{223, 44, 110}, ++{147, 53, 74}, ++{154, 54, 78}, ++{164, 54, 83}, ++{176, 54, 89}, ++{189, 52, 95}, ++{202, 49, 101}, ++{215, 46, 107}, ++{224, 44, 110}, ++{148, 55, 74}, ++{155, 55, 78}, ++{165, 55, 83}, ++{177, 54, 89}, ++{190, 52, 95}, ++{203, 50, 101}, ++{216, 47, 107}, ++{224, 44, 111}, ++{150, 56, 75}, ++{156, 57, 79}, ++{166, 56, 84}, ++{178, 55, 90}, ++{191, 53, 96}, ++{204, 50, 102}, ++{217, 47, 107}, ++{225, 45, 111}, ++{152, 58, 76}, ++{158, 58, 79}, ++{168, 58, 85}, ++{179, 56, 90}, ++{192, 54, 96}, ++{205, 51, 102}, ++{218, 48, 108}, ++{226, 45, 111}, ++{153, 59, 77}, ++{160, 59, 80}, ++{169, 59, 85}, ++{181, 57, 91}, ++{193, 55, 97}, ++{206, 52, 102}, ++{219, 48, 108}, ++{227, 46, 111}, ++{155, 61, 78}, ++{162, 61, 81}, ++{171, 60, 86}, ++{182, 58, 91}, ++{194, 56, 97}, ++{207, 53, 103}, ++{220, 49, 108}, ++{228, 47, 112}, ++{158, 63, 79}, ++{164, 63, 82}, ++{173, 61, 87}, ++{184, 59, 92}, ++{196, 57, 98}, ++{209, 53, 103}, ++{221, 50, 109}, ++{229, 47, 112}, ++{160, 65, 80}, ++{166, 64, 83}, ++{175, 63, 87}, ++{186, 61, 93}, ++{198, 58, 98}, ++{210, 54, 104}, ++{223, 51, 109}, ++{231, 48, 112}, ++{162, 67, 81}, ++{168, 66, 84}, ++{177, 64, 88}, ++{188, 62, 93}, ++{199, 59, 99}, ++{212, 55, 104}, ++{224, 51, 109}, ++{232, 49, 113}, ++{165, 68, 82}, ++{170, 67, 85}, ++{179, 66, 89}, ++{190, 63, 94}, ++{201, 60, 99}, ++{213, 56, 105}, ++{226, 52, 110}, ++{233, 50, 113}, ++{167, 70, 83}, ++{173, 69, 86}, ++{181, 67, 90}, ++{192, 64, 95}, ++{203, 61, 100}, ++{215, 57, 105}, ++{227, 53, 110}, ++{235, 50, 113}, ++{170, 72, 84}, ++{175, 71, 87}, ++{184, 68, 91}, ++{194, 65, 96}, ++{205, 62, 101}, ++{217, 58, 106}, ++{229, 54, 111}, ++{237, 51, 114}, ++{172, 74, 85}, ++{178, 72, 88}, ++{186, 70, 92}, ++{196, 67, 96}, ++{207, 63, 101}, ++{219, 59, 106}, ++{231, 55, 111}, ++{238, 52, 114}, ++{175, 75, 86}, ++{180, 74, 89}, ++{188, 71, 93}, ++{198, 68, 97}, ++{209, 64, 102}, ++{221, 60, 107}, ++{232, 56, 112}, ++{240, 53, 115}, ++{178, 77, 87}, ++{183, 75, 90}, ++{191, 73, 94}, ++{201, 69, 98}, ++{211, 65, 103}, ++{223, 61, 107}, ++{234, 57, 112}, ++{242, 54, 115}, ++{181, 78, 89}, ++{186, 77, 91}, ++{194, 74, 95}, ++{203, 70, 99}, ++{213, 66, 103}, ++{225, 62, 108}, ++{236, 58, 113}, ++{244, 55, 116}, ++{184, 80, 90}, ++{189, 78, 92}, ++{196, 75, 95}, ++{205, 72, 100}, ++{216, 68, 104}, ++{227, 63, 109}, ++{238, 59, 113}, ++{245, 56, 116}, ++{187, 81, 91}, ++{192, 80, 93}, ++{199, 77, 96}, ++{208, 73, 100}, ++{218, 69, 105}, ++{229, 64, 109}, ++{240, 60, 114}, ++{247, 57, 117}, ++{190, 83, 92}, ++{194, 81, 94}, ++{202, 78, 97}, ++{211, 74, 101}, ++{221, 70, 105}, ++{231, 65, 110}, ++{242, 61, 114}, ++{249, 57, 117}, ++{193, 84, 93}, ++{197, 82, 95}, ++{204, 79, 98}, ++{213, 75, 102}, ++{223, 71, 106}, ++{234, 66, 110}, ++{245, 61, 115}, ++{252, 58, 118}, ++{196, 86, 94}, ++{200, 84, 96}, ++{207, 80, 99}, ++{216, 76, 103}, ++{226, 72, 107}, ++{236, 67, 111}, ++{247, 62, 115}, ++{254, 59, 118}, ++{199, 87, 95}, ++{203, 85, 97}, ++{210, 82, 100}, ++{219, 78, 104}, ++{228, 73, 108}, ++{238, 68, 112}, ++{249, 63, 116}, ++{255, 60, 119}, ++{202, 88, 96}, ++{207, 86, 98}, ++{213, 83, 101}, ++{221, 79, 105}, ++{231, 74, 108}, ++{241, 69, 112}, ++{251, 64, 117}, ++{255, 61, 119}, ++{204, 89, 97}, ++{208, 87, 99}, ++{215, 83, 101}, ++{223, 79, 105}, ++{232, 75, 109}, ++{242, 70, 113}, ++{252, 65, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{208, 87, 99}, ++{215, 83, 101}, ++{223, 79, 105}, ++{232, 75, 109}, ++{242, 70, 113}, ++{252, 65, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{208, 87, 99}, ++{215, 83, 101}, ++{223, 79, 105}, ++{232, 75, 109}, ++{242, 70, 113}, ++{252, 65, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{208, 87, 99}, ++{215, 83, 101}, ++{223, 79, 105}, ++{232, 75, 109}, ++{242, 70, 113}, ++{252, 65, 117}, ++{255, 62, 119}, ++{146, 47, 70}, ++{153, 49, 74}, ++{164, 50, 80}, ++{176, 50, 86}, ++{188, 49, 92}, ++{202, 46, 98}, ++{215, 44, 104}, ++{224, 42, 108}, ++{146, 48, 70}, ++{153, 49, 74}, ++{164, 50, 80}, ++{176, 50, 86}, ++{189, 49, 92}, ++{202, 47, 98}, ++{215, 44, 104}, ++{224, 42, 108}, ++{147, 48, 71}, ++{154, 49, 75}, ++{164, 50, 80}, ++{176, 50, 86}, ++{189, 49, 92}, ++{202, 47, 99}, ++{216, 44, 104}, ++{224, 42, 108}, ++{148, 49, 71}, ++{154, 50, 75}, ++{165, 51, 80}, ++{177, 51, 86}, ++{189, 49, 93}, ++{203, 47, 99}, ++{216, 44, 105}, ++{224, 42, 108}, ++{149, 50, 72}, ++{155, 51, 75}, ++{165, 52, 81}, ++{177, 51, 87}, ++{190, 50, 93}, ++{203, 47, 99}, ++{216, 44, 105}, ++{225, 42, 108}, ++{150, 51, 72}, ++{156, 52, 76}, ++{166, 52, 81}, ++{178, 52, 87}, ++{191, 50, 93}, ++{204, 48, 99}, ++{217, 45, 105}, ++{225, 43, 108}, ++{151, 52, 73}, ++{158, 53, 76}, ++{167, 53, 82}, ++{179, 53, 87}, ++{192, 51, 93}, ++{205, 48, 99}, ++{218, 45, 105}, ++{226, 43, 109}, ++{152, 54, 73}, ++{159, 54, 77}, ++{169, 54, 82}, ++{180, 53, 88}, ++{193, 52, 94}, ++{206, 49, 100}, ++{219, 46, 105}, ++{227, 44, 109}, ++{154, 55, 74}, ++{160, 56, 78}, ++{170, 55, 83}, ++{181, 54, 88}, ++{194, 52, 94}, ++{207, 50, 100}, ++{220, 46, 106}, ++{228, 44, 109}, ++{156, 57, 75}, ++{162, 57, 78}, ++{172, 57, 83}, ++{183, 55, 89}, ++{195, 53, 95}, ++{208, 50, 100}, ++{221, 47, 106}, ++{229, 45, 109}, ++{158, 59, 76}, ++{164, 59, 79}, ++{173, 58, 84}, ++{184, 56, 90}, ++{196, 54, 95}, ++{209, 51, 101}, ++{222, 48, 106}, ++{230, 45, 110}, ++{160, 61, 77}, ++{166, 60, 80}, ++{175, 59, 85}, ++{186, 58, 90}, ++{198, 55, 96}, ++{210, 52, 101}, ++{223, 48, 107}, ++{231, 46, 110}, ++{162, 62, 78}, ++{168, 62, 81}, ++{177, 61, 86}, ++{188, 59, 91}, ++{200, 56, 96}, ++{212, 53, 102}, ++{224, 49, 107}, ++{232, 47, 110}, ++{165, 64, 79}, ++{170, 64, 82}, ++{179, 62, 86}, ++{190, 60, 92}, ++{201, 57, 97}, ++{213, 54, 102}, ++{226, 50, 108}, ++{234, 48, 111}, ++{167, 66, 80}, ++{173, 65, 83}, ++{181, 64, 87}, ++{192, 61, 92}, ++{203, 58, 97}, ++{215, 55, 103}, ++{227, 51, 108}, ++{235, 48, 111}, ++{169, 68, 81}, ++{175, 67, 84}, ++{183, 65, 88}, ++{194, 62, 93}, ++{205, 59, 98}, ++{217, 56, 103}, ++{229, 52, 108}, ++{237, 49, 112}, ++{172, 70, 82}, ++{177, 68, 85}, ++{186, 66, 89}, ++{196, 64, 94}, ++{207, 60, 99}, ++{218, 57, 104}, ++{230, 53, 109}, ++{238, 50, 112}, ++{175, 71, 83}, ++{180, 70, 86}, ++{188, 68, 90}, ++{198, 65, 94}, ++{209, 61, 99}, ++{220, 58, 104}, ++{232, 54, 109}, ++{240, 51, 112}, ++{177, 73, 85}, ++{182, 72, 87}, ++{190, 69, 91}, ++{200, 66, 95}, ++{211, 63, 100}, ++{222, 59, 105}, ++{234, 54, 110}, ++{241, 52, 113}, ++{180, 75, 86}, ++{185, 73, 88}, ++{193, 71, 92}, ++{202, 67, 96}, ++{213, 64, 101}, ++{224, 60, 106}, ++{236, 55, 110}, ++{243, 53, 113}, ++{183, 76, 87}, ++{188, 75, 89}, ++{196, 72, 93}, ++{205, 69, 97}, ++{215, 65, 101}, ++{226, 61, 106}, ++{238, 56, 111}, ++{245, 54, 114}, ++{186, 78, 88}, ++{191, 76, 90}, ++{198, 73, 94}, ++{207, 70, 98}, ++{218, 66, 102}, ++{228, 62, 107}, ++{240, 57, 111}, ++{247, 54, 114}, ++{189, 79, 89}, ++{194, 78, 91}, ++{201, 75, 95}, ++{210, 71, 99}, ++{220, 67, 103}, ++{231, 63, 107}, ++{242, 58, 112}, ++{249, 55, 115}, ++{192, 81, 90}, ++{196, 79, 92}, ++{204, 76, 95}, ++{212, 72, 99}, ++{222, 68, 104}, ++{233, 64, 108}, ++{244, 59, 113}, ++{251, 56, 115}, ++{195, 82, 91}, ++{199, 80, 93}, ++{206, 77, 96}, ++{215, 74, 100}, ++{225, 69, 104}, ++{235, 65, 109}, ++{246, 60, 113}, ++{253, 57, 116}, ++{198, 84, 92}, ++{202, 82, 94}, ++{209, 79, 97}, ++{218, 75, 101}, ++{227, 71, 105}, ++{237, 66, 109}, ++{248, 61, 114}, ++{255, 58, 116}, ++{201, 85, 93}, ++{205, 83, 95}, ++{212, 80, 98}, ++{220, 76, 102}, ++{230, 72, 106}, ++{240, 67, 110}, ++{251, 62, 114}, ++{255, 59, 117}, ++{204, 86, 95}, ++{208, 84, 96}, ++{215, 81, 99}, ++{223, 77, 103}, ++{232, 73, 107}, ++{242, 68, 111}, ++{253, 63, 115}, ++{255, 60, 117}, ++{206, 87, 95}, ++{210, 85, 97}, ++{216, 82, 100}, ++{225, 78, 103}, ++{234, 73, 107}, ++{244, 69, 111}, ++{254, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{210, 85, 97}, ++{216, 82, 100}, ++{225, 78, 103}, ++{234, 73, 107}, ++{244, 69, 111}, ++{254, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{210, 85, 97}, ++{216, 82, 100}, ++{225, 78, 103}, ++{234, 73, 107}, ++{244, 69, 111}, ++{254, 64, 115}, ++{255, 61, 118}, ++{206, 87, 95}, ++{210, 85, 97}, ++{216, 82, 100}, ++{225, 78, 103}, ++{234, 73, 107}, ++{244, 69, 111}, ++{254, 64, 115}, ++{255, 61, 118}, ++{149, 45, 69}, ++{156, 47, 72}, ++{166, 48, 78}, ++{178, 48, 84}, ++{191, 47, 90}, ++{204, 45, 97}, ++{217, 42, 102}, ++{225, 40, 106}, ++{149, 45, 69}, ++{156, 47, 73}, ++{166, 48, 78}, ++{178, 48, 84}, ++{191, 47, 90}, ++{204, 45, 97}, ++{217, 42, 102}, ++{225, 40, 106}, ++{150, 46, 69}, ++{156, 47, 73}, ++{166, 48, 78}, ++{178, 48, 84}, ++{191, 47, 91}, ++{204, 45, 97}, ++{217, 43, 103}, ++{226, 41, 106}, ++{150, 47, 69}, ++{157, 48, 73}, ++{167, 49, 78}, ++{179, 49, 85}, ++{191, 47, 91}, ++{204, 45, 97}, ++{218, 43, 103}, ++{226, 41, 106}, ++{151, 48, 70}, ++{158, 49, 73}, ++{168, 49, 79}, ++{179, 49, 85}, ++{192, 48, 91}, ++{205, 46, 97}, ++{218, 43, 103}, ++{226, 41, 106}, ++{152, 49, 70}, ++{159, 50, 74}, ++{169, 50, 79}, ++{180, 50, 85}, ++{193, 48, 91}, ++{206, 46, 97}, ++{219, 43, 103}, ++{227, 42, 107}, ++{154, 50, 71}, ++{160, 51, 75}, ++{170, 51, 80}, ++{181, 51, 86}, ++{194, 49, 92}, ++{207, 47, 98}, ++{220, 44, 103}, ++{228, 42, 107}, ++{155, 52, 72}, ++{161, 52, 75}, ++{171, 52, 80}, ++{182, 52, 86}, ++{195, 50, 92}, ++{207, 47, 98}, ++{220, 44, 104}, ++{229, 42, 107}, ++{157, 53, 73}, ++{163, 54, 76}, ++{172, 53, 81}, ++{184, 52, 87}, ++{196, 51, 92}, ++{208, 48, 98}, ++{221, 45, 104}, ++{229, 43, 107}, ++{159, 55, 73}, ++{165, 55, 77}, ++{174, 55, 82}, ++{185, 53, 87}, ++{197, 51, 93}, ++{210, 49, 99}, ++{222, 46, 104}, ++{230, 44, 108}, ++{160, 57, 74}, ++{166, 57, 77}, ++{176, 56, 82}, ++{187, 55, 88}, ++{198, 52, 93}, ++{211, 50, 99}, ++{224, 46, 104}, ++{232, 44, 108}, ++{162, 58, 75}, ++{168, 58, 78}, ++{177, 57, 83}, ++{188, 56, 88}, ++{200, 53, 94}, ++{212, 50, 99}, ++{225, 47, 105}, ++{233, 45, 108}, ++{165, 60, 76}, ++{170, 60, 79}, ++{179, 59, 84}, ++{190, 57, 89}, ++{201, 54, 94}, ++{214, 51, 100}, ++{226, 48, 105}, ++{234, 46, 109}, ++{167, 62, 77}, ++{173, 61, 80}, ++{181, 60, 85}, ++{192, 58, 90}, ++{203, 55, 95}, ++{215, 52, 100}, ++{227, 49, 106}, ++{235, 46, 109}, ++{169, 64, 78}, ++{175, 63, 81}, ++{183, 62, 85}, ++{194, 59, 90}, ++{205, 57, 96}, ++{217, 53, 101}, ++{229, 50, 106}, ++{237, 47, 109}, ++{172, 66, 79}, ++{177, 65, 82}, ++{185, 63, 86}, ++{196, 61, 91}, ++{207, 58, 96}, ++{218, 54, 101}, ++{231, 50, 107}, ++{238, 48, 110}, ++{174, 67, 80}, ++{180, 66, 83}, ++{188, 64, 87}, ++{198, 62, 92}, ++{209, 59, 97}, ++{220, 55, 102}, ++{232, 51, 107}, ++{240, 49, 110}, ++{177, 69, 82}, ++{182, 68, 84}, ++{190, 66, 88}, ++{200, 63, 93}, ++{211, 60, 98}, ++{222, 56, 103}, ++{234, 52, 108}, ++{241, 50, 111}, ++{180, 71, 83}, ++{185, 70, 85}, ++{192, 67, 89}, ++{202, 64, 93}, ++{213, 61, 98}, ++{224, 57, 103}, ++{236, 53, 108}, ++{243, 51, 111}, ++{182, 73, 84}, ++{187, 71, 86}, ++{195, 69, 90}, ++{204, 66, 94}, ++{215, 62, 99}, ++{226, 58, 104}, ++{237, 54, 109}, ++{245, 51, 112}, ++{185, 74, 85}, ++{190, 73, 87}, ++{198, 70, 91}, ++{207, 67, 95}, ++{217, 63, 100}, ++{228, 59, 104}, ++{239, 55, 109}, ++{247, 52, 112}, ++{188, 76, 86}, ++{193, 74, 88}, ++{200, 72, 92}, ++{209, 68, 96}, ++{219, 65, 100}, ++{230, 60, 105}, ++{241, 56, 110}, ++{249, 53, 113}, ++{191, 77, 87}, ++{196, 76, 89}, ++{203, 73, 93}, ++{212, 70, 97}, ++{222, 66, 101}, ++{232, 61, 106}, ++{243, 57, 110}, ++{251, 54, 113}, ++{194, 79, 88}, ++{198, 77, 90}, ++{205, 74, 94}, ++{214, 71, 98}, ++{224, 67, 102}, ++{234, 63, 106}, ++{245, 58, 111}, ++{253, 55, 114}, ++{197, 80, 89}, ++{201, 78, 91}, ++{208, 76, 95}, ++{217, 72, 98}, ++{226, 68, 103}, ++{237, 64, 107}, ++{248, 59, 111}, ++{255, 56, 114}, ++{200, 82, 91}, ++{204, 80, 93}, ++{211, 77, 96}, ++{219, 73, 99}, ++{229, 69, 103}, ++{239, 65, 108}, ++{250, 60, 112}, ++{255, 57, 115}, ++{203, 83, 92}, ++{207, 81, 94}, ++{214, 78, 97}, ++{222, 74, 100}, ++{231, 70, 104}, ++{241, 66, 108}, ++{252, 61, 112}, ++{255, 58, 115}, ++{206, 84, 93}, ++{210, 82, 95}, ++{217, 79, 97}, ++{225, 76, 101}, ++{234, 71, 105}, ++{244, 67, 109}, ++{254, 62, 113}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{218, 80, 98}, ++{226, 76, 101}, ++{235, 72, 105}, ++{245, 67, 109}, ++{255, 62, 113}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{218, 80, 98}, ++{226, 76, 101}, ++{235, 72, 105}, ++{245, 67, 109}, ++{255, 62, 113}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{218, 80, 98}, ++{226, 76, 101}, ++{235, 72, 105}, ++{245, 67, 109}, ++{255, 62, 113}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{218, 80, 98}, ++{226, 76, 101}, ++{235, 72, 105}, ++{245, 67, 109}, ++{255, 62, 113}, ++{255, 59, 116}, ++{152, 43, 67}, ++{158, 44, 71}, ++{168, 46, 76}, ++{180, 46, 82}, ++{193, 45, 89}, ++{206, 43, 95}, ++{219, 41, 101}, ++{227, 39, 104}, ++{152, 43, 67}, ++{158, 45, 71}, ++{168, 46, 76}, ++{180, 46, 82}, ++{193, 45, 89}, ++{206, 43, 95}, ++{219, 41, 101}, ++{227, 39, 104}, ++{152, 44, 67}, ++{159, 45, 71}, ++{169, 46, 76}, ++{180, 46, 82}, ++{193, 45, 89}, ++{206, 44, 95}, ++{219, 41, 101}, ++{227, 39, 104}, ++{153, 44, 68}, ++{159, 46, 71}, ++{169, 47, 77}, ++{181, 47, 83}, ++{193, 46, 89}, ++{206, 44, 95}, ++{219, 41, 101}, ++{228, 40, 104}, ++{154, 45, 68}, ++{160, 46, 72}, ++{170, 47, 77}, ++{182, 47, 83}, ++{194, 46, 89}, ++{207, 44, 95}, ++{220, 42, 101}, ++{228, 40, 105}, ++{155, 46, 69}, ++{161, 48, 72}, ++{171, 48, 77}, ++{182, 48, 83}, ++{195, 47, 89}, ++{208, 45, 95}, ++{221, 42, 101}, ++{229, 40, 105}, ++{156, 48, 69}, ++{162, 49, 73}, ++{172, 49, 78}, ++{183, 49, 84}, ++{196, 47, 90}, ++{208, 45, 96}, ++{221, 43, 101}, ++{229, 41, 105}, ++{158, 49, 70}, ++{164, 50, 73}, ++{173, 50, 78}, ++{185, 50, 84}, ++{197, 48, 90}, ++{209, 46, 96}, ++{222, 43, 102}, ++{230, 41, 105}, ++{159, 51, 71}, ++{165, 51, 74}, ++{175, 51, 79}, ++{186, 51, 85}, ++{198, 49, 91}, ++{210, 47, 96}, ++{223, 44, 102}, ++{231, 42, 105}, ++{161, 53, 72}, ++{167, 53, 75}, ++{176, 53, 80}, ++{187, 52, 85}, ++{199, 50, 91}, ++{211, 47, 97}, ++{224, 44, 102}, ++{232, 42, 106}, ++{163, 54, 73}, ++{169, 54, 76}, ++{178, 54, 80}, ++{189, 53, 86}, ++{200, 51, 91}, ++{213, 48, 97}, ++{225, 45, 103}, ++{233, 43, 106}, ++{165, 56, 74}, ++{171, 56, 77}, ++{180, 55, 81}, ++{190, 54, 86}, ++{202, 52, 92}, ++{214, 49, 98}, ++{226, 46, 103}, ++{234, 44, 106}, ++{167, 58, 75}, ++{173, 58, 77}, ++{181, 57, 82}, ++{192, 55, 87}, ++{203, 53, 93}, ++{215, 50, 98}, ++{228, 47, 103}, ++{236, 44, 107}, ++{169, 60, 76}, ++{175, 59, 78}, ++{183, 58, 83}, ++{194, 56, 88}, ++{205, 54, 93}, ++{217, 51, 99}, ++{229, 47, 104}, ++{237, 45, 107}, ++{172, 62, 77}, ++{177, 61, 79}, ++{185, 60, 84}, ++{196, 58, 89}, ++{207, 55, 94}, ++{219, 52, 99}, ++{231, 48, 104}, ++{238, 46, 107}, ++{174, 63, 78}, ++{179, 63, 80}, ++{188, 61, 84}, ++{198, 59, 89}, ++{209, 56, 94}, ++{220, 53, 100}, ++{232, 49, 105}, ++{240, 47, 108}, ++{177, 65, 79}, ++{182, 64, 81}, ++{190, 63, 85}, ++{200, 60, 90}, ++{210, 57, 95}, ++{222, 54, 100}, ++{234, 50, 105}, ++{241, 48, 108}, ++{179, 67, 80}, ++{184, 66, 82}, ++{192, 64, 86}, ++{202, 61, 91}, ++{212, 58, 96}, ++{224, 55, 101}, ++{236, 51, 106}, ++{243, 48, 109}, ++{182, 69, 81}, ++{187, 68, 83}, ++{195, 65, 87}, ++{204, 63, 92}, ++{215, 59, 96}, ++{226, 56, 101}, ++{237, 52, 106}, ++{245, 49, 109}, ++{185, 70, 82}, ++{189, 69, 84}, ++{197, 67, 88}, ++{206, 64, 92}, ++{217, 61, 97}, ++{228, 57, 102}, ++{239, 53, 107}, ++{246, 50, 110}, ++{187, 72, 83}, ++{192, 71, 85}, ++{199, 68, 89}, ++{209, 65, 93}, ++{219, 62, 98}, ++{230, 58, 103}, ++{241, 54, 107}, ++{248, 51, 110}, ++{190, 74, 84}, ++{195, 72, 87}, ++{202, 70, 90}, ++{211, 67, 94}, ++{221, 63, 99}, ++{232, 59, 103}, ++{243, 55, 108}, ++{250, 52, 111}, ++{193, 75, 85}, ++{198, 74, 88}, ++{205, 71, 91}, ++{213, 68, 95}, ++{223, 64, 99}, ++{234, 60, 104}, ++{245, 56, 108}, ++{252, 53, 111}, ++{196, 77, 87}, ++{200, 75, 89}, ++{207, 72, 92}, ++{216, 69, 96}, ++{226, 65, 100}, ++{236, 61, 104}, ++{247, 57, 109}, ++{254, 54, 112}, ++{199, 78, 88}, ++{203, 77, 90}, ++{210, 74, 93}, ++{219, 70, 97}, ++{228, 66, 101}, ++{238, 62, 105}, ++{249, 58, 110}, ++{255, 55, 112}, ++{202, 80, 89}, ++{206, 78, 91}, ++{213, 75, 94}, ++{221, 72, 98}, ++{231, 68, 102}, ++{241, 63, 106}, ++{251, 59, 110}, ++{255, 56, 113}, ++{205, 81, 90}, ++{209, 79, 92}, ++{216, 76, 95}, ++{224, 73, 98}, ++{233, 69, 102}, ++{243, 64, 106}, ++{254, 60, 111}, ++{255, 57, 113}, ++{208, 82, 91}, ++{212, 81, 93}, ++{219, 78, 96}, ++{227, 74, 99}, ++{236, 70, 103}, ++{245, 65, 107}, ++{255, 61, 111}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 93}, ++{220, 78, 96}, ++{228, 75, 100}, ++{237, 70, 103}, ++{247, 66, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 93}, ++{220, 78, 96}, ++{228, 75, 100}, ++{237, 70, 103}, ++{247, 66, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 93}, ++{220, 78, 96}, ++{228, 75, 100}, ++{237, 70, 103}, ++{247, 66, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 93}, ++{220, 78, 96}, ++{228, 75, 100}, ++{237, 70, 103}, ++{247, 66, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{154, 41, 65}, ++{161, 42, 69}, ++{171, 44, 74}, ++{182, 44, 80}, ++{195, 43, 87}, ++{208, 42, 93}, ++{221, 40, 99}, ++{229, 38, 102}, ++{155, 41, 65}, ++{161, 42, 69}, ++{171, 44, 75}, ++{182, 44, 81}, ++{195, 44, 87}, ++{208, 42, 93}, ++{221, 40, 99}, ++{229, 38, 102}, ++{155, 41, 66}, ++{161, 43, 69}, ++{171, 44, 75}, ++{183, 44, 81}, ++{195, 44, 87}, ++{208, 42, 93}, ++{221, 40, 99}, ++{229, 38, 102}, ++{156, 42, 66}, ++{162, 43, 70}, ++{172, 45, 75}, ++{183, 45, 81}, ++{196, 44, 87}, ++{208, 42, 93}, ++{221, 40, 99}, ++{229, 38, 103}, ++{156, 43, 66}, ++{163, 44, 70}, ++{172, 45, 75}, ++{184, 45, 81}, ++{196, 45, 87}, ++{209, 43, 93}, ++{222, 40, 99}, ++{230, 39, 103}, ++{158, 44, 67}, ++{164, 45, 71}, ++{173, 46, 76}, ++{185, 46, 82}, ++{197, 45, 88}, ++{210, 43, 94}, ++{222, 41, 99}, ++{230, 39, 103}, ++{159, 46, 68}, ++{165, 46, 71}, ++{174, 47, 76}, ++{186, 47, 82}, ++{198, 46, 88}, ++{210, 44, 94}, ++{223, 41, 100}, ++{231, 39, 103}, ++{160, 47, 68}, ++{166, 48, 72}, ++{176, 48, 77}, ++{187, 48, 82}, ++{199, 46, 88}, ++{211, 44, 94}, ++{224, 42, 100}, ++{232, 40, 103}, ++{162, 49, 69}, ++{168, 49, 72}, ++{177, 49, 77}, ++{188, 49, 83}, ++{200, 47, 89}, ++{212, 45, 94}, ++{225, 42, 100}, ++{233, 40, 104}, ++{164, 50, 70}, ++{169, 51, 73}, ++{178, 51, 78}, ++{189, 50, 83}, ++{201, 48, 89}, ++{213, 46, 95}, ++{226, 43, 100}, ++{234, 41, 104}, ++{165, 52, 71}, ++{171, 52, 74}, ++{180, 52, 79}, ++{191, 51, 84}, ++{202, 49, 90}, ++{215, 47, 95}, ++{227, 44, 101}, ++{235, 42, 104}, ++{167, 54, 72}, ++{173, 54, 75}, ++{182, 53, 79}, ++{192, 52, 85}, ++{204, 50, 90}, ++{216, 47, 96}, ++{228, 44, 101}, ++{236, 42, 105}, ++{169, 56, 73}, ++{175, 55, 76}, ++{184, 55, 80}, ++{194, 53, 85}, ++{205, 51, 91}, ++{217, 48, 96}, ++{230, 45, 102}, ++{237, 43, 105}, ++{172, 58, 74}, ++{177, 57, 77}, ++{186, 56, 81}, ++{196, 54, 86}, ++{207, 52, 91}, ++{219, 49, 97}, ++{231, 46, 102}, ++{239, 44, 105}, ++{174, 59, 75}, ++{179, 59, 78}, ++{188, 58, 82}, ++{198, 56, 87}, ++{209, 53, 92}, ++{220, 50, 97}, ++{232, 47, 102}, ++{240, 45, 106}, ++{176, 61, 76}, ++{182, 60, 79}, ++{190, 59, 83}, ++{200, 57, 87}, ++{210, 54, 93}, ++{222, 51, 98}, ++{234, 48, 103}, ++{241, 45, 106}, ++{179, 63, 77}, ++{184, 62, 80}, ++{192, 61, 84}, ++{202, 58, 88}, ++{212, 56, 93}, ++{224, 52, 98}, ++{236, 49, 103}, ++{243, 46, 107}, ++{181, 65, 78}, ++{186, 64, 81}, ++{194, 62, 84}, ++{204, 60, 89}, ++{214, 57, 94}, ++{226, 53, 99}, ++{237, 50, 104}, ++{245, 47, 107}, ++{184, 67, 79}, ++{189, 65, 82}, ++{197, 64, 85}, ++{206, 61, 90}, ++{216, 58, 95}, ++{227, 54, 100}, ++{239, 51, 104}, ++{246, 48, 107}, ++{187, 68, 80}, ++{191, 67, 83}, ++{199, 65, 86}, ++{208, 62, 91}, ++{218, 59, 95}, ++{229, 55, 100}, ++{241, 52, 105}, ++{248, 49, 108}, ++{189, 70, 81}, ++{194, 69, 84}, ++{201, 66, 87}, ++{210, 64, 91}, ++{221, 60, 96}, ++{231, 57, 101}, ++{243, 53, 106}, ++{250, 50, 108}, ++{192, 72, 83}, ++{197, 70, 85}, ++{204, 68, 88}, ++{213, 65, 92}, ++{223, 61, 97}, ++{233, 58, 101}, ++{245, 54, 106}, ++{252, 51, 109}, ++{195, 73, 84}, ++{200, 72, 86}, ++{207, 69, 89}, ++{215, 66, 93}, ++{225, 63, 98}, ++{236, 59, 102}, ++{247, 55, 107}, ++{254, 52, 110}, ++{198, 75, 85}, ++{202, 73, 87}, ++{209, 71, 90}, ++{218, 67, 94}, ++{227, 64, 98}, ++{238, 60, 103}, ++{249, 56, 107}, ++{255, 53, 110}, ++{201, 76, 86}, ++{205, 75, 88}, ++{212, 72, 91}, ++{220, 69, 95}, ++{230, 65, 99}, ++{240, 61, 103}, ++{251, 57, 108}, ++{255, 54, 111}, ++{204, 78, 87}, ++{208, 76, 89}, ++{215, 73, 92}, ++{223, 70, 96}, ++{232, 66, 100}, ++{242, 62, 104}, ++{253, 58, 108}, ++{255, 55, 111}, ++{207, 79, 88}, ++{211, 77, 90}, ++{217, 75, 93}, ++{226, 71, 97}, ++{235, 67, 101}, ++{245, 63, 105}, ++{255, 59, 109}, ++{255, 56, 112}, ++{210, 81, 89}, ++{214, 79, 91}, ++{220, 76, 94}, ++{228, 72, 97}, ++{237, 68, 101}, ++{247, 64, 105}, ++{255, 60, 110}, ++{255, 57, 112}, ++{211, 81, 90}, ++{215, 79, 92}, ++{222, 77, 94}, ++{230, 73, 98}, ++{239, 69, 102}, ++{248, 65, 106}, ++{255, 60, 110}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 79, 92}, ++{222, 77, 94}, ++{230, 73, 98}, ++{239, 69, 102}, ++{248, 65, 106}, ++{255, 60, 110}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 79, 92}, ++{222, 77, 94}, ++{230, 73, 98}, ++{239, 69, 102}, ++{248, 65, 106}, ++{255, 60, 110}, ++{255, 57, 113}, ++{211, 81, 90}, ++{215, 79, 92}, ++{222, 77, 94}, ++{230, 73, 98}, ++{239, 69, 102}, ++{248, 65, 106}, ++{255, 60, 110}, ++{255, 57, 113}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{208, 41, 92}, ++{221, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 68}, ++{172, 43, 74}, ++{184, 44, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 102}, ++{157, 41, 65}, ++{163, 42, 69}, ++{173, 44, 74}, ++{184, 44, 80}, ++{197, 43, 86}, ++{209, 42, 92}, ++{222, 39, 98}, ++{230, 38, 102}, ++{158, 42, 66}, ++{164, 43, 69}, ++{174, 44, 74}, ++{185, 45, 80}, ++{197, 44, 86}, ++{210, 42, 92}, ++{223, 40, 98}, ++{231, 38, 102}, ++{159, 43, 66}, ++{165, 44, 70}, ++{175, 45, 75}, ++{186, 45, 81}, ++{198, 44, 87}, ++{210, 42, 93}, ++{223, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{166, 45, 70}, ++{176, 46, 75}, ++{187, 46, 81}, ++{199, 45, 87}, ++{211, 43, 93}, ++{224, 41, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{168, 47, 71}, ++{177, 47, 76}, ++{188, 47, 81}, ++{200, 46, 87}, ++{212, 44, 93}, ++{225, 41, 99}, ++{233, 39, 102}, ++{163, 47, 68}, ++{169, 48, 72}, ++{178, 48, 76}, ++{189, 48, 82}, ++{201, 46, 88}, ++{213, 44, 94}, ++{226, 42, 99}, ++{234, 40, 103}, ++{165, 49, 69}, ++{171, 50, 72}, ++{180, 50, 77}, ++{190, 49, 83}, ++{202, 47, 88}, ++{214, 45, 94}, ++{227, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{172, 51, 73}, ++{181, 51, 78}, ++{192, 50, 83}, ++{203, 48, 89}, ++{215, 46, 94}, ++{228, 43, 100}, ++{236, 41, 103}, ++{169, 53, 71}, ++{174, 53, 74}, ++{183, 52, 78}, ++{193, 51, 84}, ++{205, 49, 89}, ++{217, 47, 95}, ++{229, 44, 100}, ++{237, 42, 104}, ++{171, 55, 72}, ++{176, 54, 75}, ++{185, 54, 79}, ++{195, 52, 84}, ++{206, 50, 90}, ++{218, 48, 95}, ++{230, 45, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{178, 56, 76}, ++{187, 55, 80}, ++{197, 54, 85}, ++{208, 51, 90}, ++{220, 49, 96}, ++{232, 45, 101}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 77}, ++{189, 57, 81}, ++{199, 55, 86}, ++{210, 52, 91}, ++{221, 50, 96}, ++{233, 46, 102}, ++{241, 44, 105}, ++{177, 60, 75}, ++{183, 59, 78}, ++{191, 58, 82}, ++{201, 56, 87}, ++{211, 54, 92}, ++{223, 51, 97}, ++{235, 47, 102}, ++{242, 45, 105}, ++{180, 62, 76}, ++{185, 61, 79}, ++{193, 60, 83}, ++{203, 57, 87}, ++{213, 55, 92}, ++{225, 52, 97}, ++{236, 48, 103}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 80}, ++{195, 61, 84}, ++{205, 59, 88}, ++{215, 56, 93}, ++{226, 53, 98}, ++{238, 49, 103}, ++{245, 47, 106}, ++{185, 65, 78}, ++{190, 64, 81}, ++{198, 63, 84}, ++{207, 60, 89}, ++{217, 57, 94}, ++{228, 54, 99}, ++{240, 50, 104}, ++{247, 47, 107}, ++{188, 67, 79}, ++{192, 66, 82}, ++{200, 64, 85}, ++{209, 61, 90}, ++{219, 58, 94}, ++{230, 55, 99}, ++{242, 51, 104}, ++{249, 48, 107}, ++{190, 69, 81}, ++{195, 68, 83}, ++{202, 65, 86}, ++{211, 63, 91}, ++{222, 59, 95}, ++{232, 56, 100}, ++{243, 52, 105}, ++{251, 49, 108}, ++{193, 71, 82}, ++{198, 69, 84}, ++{205, 67, 87}, ++{214, 64, 91}, ++{224, 61, 96}, ++{234, 57, 101}, ++{245, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 71, 85}, ++{208, 68, 88}, ++{216, 65, 92}, ++{226, 62, 97}, ++{236, 58, 101}, ++{247, 54, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{210, 70, 89}, ++{219, 67, 93}, ++{228, 63, 97}, ++{239, 59, 102}, ++{249, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{206, 74, 87}, ++{213, 71, 90}, ++{221, 68, 94}, ++{231, 64, 98}, ++{241, 60, 103}, ++{252, 56, 107}, ++{255, 53, 110}, ++{205, 77, 86}, ++{209, 75, 88}, ++{216, 72, 91}, ++{224, 69, 95}, ++{233, 65, 99}, ++{243, 61, 103}, ++{254, 57, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{212, 76, 89}, ++{218, 74, 92}, ++{226, 70, 96}, ++{236, 66, 100}, ++{245, 62, 104}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{215, 78, 90}, ++{221, 75, 93}, ++{229, 72, 97}, ++{238, 68, 101}, ++{248, 63, 105}, ++{255, 59, 109}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{208, 41, 92}, ++{221, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 68}, ++{172, 43, 74}, ++{184, 44, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 102}, ++{157, 41, 65}, ++{163, 42, 69}, ++{173, 44, 74}, ++{184, 44, 80}, ++{197, 43, 86}, ++{209, 42, 92}, ++{222, 39, 98}, ++{230, 38, 102}, ++{158, 42, 66}, ++{164, 43, 69}, ++{174, 44, 74}, ++{185, 45, 80}, ++{197, 44, 86}, ++{210, 42, 92}, ++{223, 40, 98}, ++{231, 38, 102}, ++{159, 43, 66}, ++{165, 44, 70}, ++{175, 45, 75}, ++{186, 45, 81}, ++{198, 44, 87}, ++{210, 42, 93}, ++{223, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{166, 45, 70}, ++{176, 46, 75}, ++{187, 46, 81}, ++{199, 45, 87}, ++{211, 43, 93}, ++{224, 41, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{168, 47, 71}, ++{177, 47, 76}, ++{188, 47, 81}, ++{200, 46, 87}, ++{212, 44, 93}, ++{225, 41, 99}, ++{233, 39, 102}, ++{163, 47, 68}, ++{169, 48, 72}, ++{178, 48, 76}, ++{189, 48, 82}, ++{201, 46, 88}, ++{213, 44, 94}, ++{226, 42, 99}, ++{234, 40, 103}, ++{165, 49, 69}, ++{171, 50, 72}, ++{180, 50, 77}, ++{190, 49, 83}, ++{202, 47, 88}, ++{214, 45, 94}, ++{227, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{172, 51, 73}, ++{181, 51, 78}, ++{192, 50, 83}, ++{203, 48, 89}, ++{215, 46, 94}, ++{228, 43, 100}, ++{236, 41, 103}, ++{169, 53, 71}, ++{174, 53, 74}, ++{183, 52, 78}, ++{193, 51, 84}, ++{205, 49, 89}, ++{217, 47, 95}, ++{229, 44, 100}, ++{237, 42, 104}, ++{171, 55, 72}, ++{176, 54, 75}, ++{185, 54, 79}, ++{195, 52, 84}, ++{206, 50, 90}, ++{218, 48, 95}, ++{230, 45, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{178, 56, 76}, ++{187, 55, 80}, ++{197, 54, 85}, ++{208, 51, 90}, ++{220, 49, 96}, ++{232, 45, 101}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 77}, ++{189, 57, 81}, ++{199, 55, 86}, ++{210, 52, 91}, ++{221, 50, 96}, ++{233, 46, 102}, ++{241, 44, 105}, ++{177, 60, 75}, ++{183, 59, 78}, ++{191, 58, 82}, ++{201, 56, 87}, ++{211, 54, 92}, ++{223, 51, 97}, ++{235, 47, 102}, ++{242, 45, 105}, ++{180, 62, 76}, ++{185, 61, 79}, ++{193, 60, 83}, ++{203, 57, 87}, ++{213, 55, 92}, ++{225, 52, 97}, ++{236, 48, 103}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 80}, ++{195, 61, 84}, ++{205, 59, 88}, ++{215, 56, 93}, ++{226, 53, 98}, ++{238, 49, 103}, ++{245, 47, 106}, ++{185, 65, 78}, ++{190, 64, 81}, ++{198, 63, 84}, ++{207, 60, 89}, ++{217, 57, 94}, ++{228, 54, 99}, ++{240, 50, 104}, ++{247, 47, 107}, ++{188, 67, 79}, ++{192, 66, 82}, ++{200, 64, 85}, ++{209, 61, 90}, ++{219, 58, 94}, ++{230, 55, 99}, ++{242, 51, 104}, ++{249, 48, 107}, ++{190, 69, 81}, ++{195, 68, 83}, ++{202, 65, 86}, ++{211, 63, 91}, ++{222, 59, 95}, ++{232, 56, 100}, ++{243, 52, 105}, ++{251, 49, 108}, ++{193, 71, 82}, ++{198, 69, 84}, ++{205, 67, 87}, ++{214, 64, 91}, ++{224, 61, 96}, ++{234, 57, 101}, ++{245, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 71, 85}, ++{208, 68, 88}, ++{216, 65, 92}, ++{226, 62, 97}, ++{236, 58, 101}, ++{247, 54, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{210, 70, 89}, ++{219, 67, 93}, ++{228, 63, 97}, ++{239, 59, 102}, ++{249, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{206, 74, 87}, ++{213, 71, 90}, ++{221, 68, 94}, ++{231, 64, 98}, ++{241, 60, 103}, ++{252, 56, 107}, ++{255, 53, 110}, ++{205, 77, 86}, ++{209, 75, 88}, ++{216, 72, 91}, ++{224, 69, 95}, ++{233, 65, 99}, ++{243, 61, 103}, ++{254, 57, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{212, 76, 89}, ++{218, 74, 92}, ++{226, 70, 96}, ++{236, 66, 100}, ++{245, 62, 104}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{215, 78, 90}, ++{221, 75, 93}, ++{229, 72, 97}, ++{238, 68, 101}, ++{248, 63, 105}, ++{255, 59, 109}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{208, 41, 92}, ++{221, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 68}, ++{172, 43, 74}, ++{184, 44, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 102}, ++{157, 41, 65}, ++{163, 42, 69}, ++{173, 44, 74}, ++{184, 44, 80}, ++{197, 43, 86}, ++{209, 42, 92}, ++{222, 39, 98}, ++{230, 38, 102}, ++{158, 42, 66}, ++{164, 43, 69}, ++{174, 44, 74}, ++{185, 45, 80}, ++{197, 44, 86}, ++{210, 42, 92}, ++{223, 40, 98}, ++{231, 38, 102}, ++{159, 43, 66}, ++{165, 44, 70}, ++{175, 45, 75}, ++{186, 45, 81}, ++{198, 44, 87}, ++{210, 42, 93}, ++{223, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{166, 45, 70}, ++{176, 46, 75}, ++{187, 46, 81}, ++{199, 45, 87}, ++{211, 43, 93}, ++{224, 41, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{168, 47, 71}, ++{177, 47, 76}, ++{188, 47, 81}, ++{200, 46, 87}, ++{212, 44, 93}, ++{225, 41, 99}, ++{233, 39, 102}, ++{163, 47, 68}, ++{169, 48, 72}, ++{178, 48, 76}, ++{189, 48, 82}, ++{201, 46, 88}, ++{213, 44, 94}, ++{226, 42, 99}, ++{234, 40, 103}, ++{165, 49, 69}, ++{171, 50, 72}, ++{180, 50, 77}, ++{190, 49, 83}, ++{202, 47, 88}, ++{214, 45, 94}, ++{227, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{172, 51, 73}, ++{181, 51, 78}, ++{192, 50, 83}, ++{203, 48, 89}, ++{215, 46, 94}, ++{228, 43, 100}, ++{236, 41, 103}, ++{169, 53, 71}, ++{174, 53, 74}, ++{183, 52, 78}, ++{193, 51, 84}, ++{205, 49, 89}, ++{217, 47, 95}, ++{229, 44, 100}, ++{237, 42, 104}, ++{171, 55, 72}, ++{176, 54, 75}, ++{185, 54, 79}, ++{195, 52, 84}, ++{206, 50, 90}, ++{218, 48, 95}, ++{230, 45, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{178, 56, 76}, ++{187, 55, 80}, ++{197, 54, 85}, ++{208, 51, 90}, ++{220, 49, 96}, ++{232, 45, 101}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 77}, ++{189, 57, 81}, ++{199, 55, 86}, ++{210, 52, 91}, ++{221, 50, 96}, ++{233, 46, 102}, ++{241, 44, 105}, ++{177, 60, 75}, ++{183, 59, 78}, ++{191, 58, 82}, ++{201, 56, 87}, ++{211, 54, 92}, ++{223, 51, 97}, ++{235, 47, 102}, ++{242, 45, 105}, ++{180, 62, 76}, ++{185, 61, 79}, ++{193, 60, 83}, ++{203, 57, 87}, ++{213, 55, 92}, ++{225, 52, 97}, ++{236, 48, 103}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 80}, ++{195, 61, 84}, ++{205, 59, 88}, ++{215, 56, 93}, ++{226, 53, 98}, ++{238, 49, 103}, ++{245, 47, 106}, ++{185, 65, 78}, ++{190, 64, 81}, ++{198, 63, 84}, ++{207, 60, 89}, ++{217, 57, 94}, ++{228, 54, 99}, ++{240, 50, 104}, ++{247, 47, 107}, ++{188, 67, 79}, ++{192, 66, 82}, ++{200, 64, 85}, ++{209, 61, 90}, ++{219, 58, 94}, ++{230, 55, 99}, ++{242, 51, 104}, ++{249, 48, 107}, ++{190, 69, 81}, ++{195, 68, 83}, ++{202, 65, 86}, ++{211, 63, 91}, ++{222, 59, 95}, ++{232, 56, 100}, ++{243, 52, 105}, ++{251, 49, 108}, ++{193, 71, 82}, ++{198, 69, 84}, ++{205, 67, 87}, ++{214, 64, 91}, ++{224, 61, 96}, ++{234, 57, 101}, ++{245, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 71, 85}, ++{208, 68, 88}, ++{216, 65, 92}, ++{226, 62, 97}, ++{236, 58, 101}, ++{247, 54, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{210, 70, 89}, ++{219, 67, 93}, ++{228, 63, 97}, ++{239, 59, 102}, ++{249, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{206, 74, 87}, ++{213, 71, 90}, ++{221, 68, 94}, ++{231, 64, 98}, ++{241, 60, 103}, ++{252, 56, 107}, ++{255, 53, 110}, ++{205, 77, 86}, ++{209, 75, 88}, ++{216, 72, 91}, ++{224, 69, 95}, ++{233, 65, 99}, ++{243, 61, 103}, ++{254, 57, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{212, 76, 89}, ++{218, 74, 92}, ++{226, 70, 96}, ++{236, 66, 100}, ++{245, 62, 104}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{215, 78, 90}, ++{221, 75, 93}, ++{229, 72, 97}, ++{238, 68, 101}, ++{248, 63, 105}, ++{255, 59, 109}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{208, 41, 92}, ++{221, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{162, 41, 68}, ++{172, 43, 74}, ++{183, 43, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 68}, ++{172, 43, 74}, ++{184, 44, 80}, ++{196, 43, 86}, ++{209, 41, 92}, ++{222, 39, 98}, ++{230, 37, 102}, ++{157, 41, 65}, ++{163, 42, 69}, ++{173, 44, 74}, ++{184, 44, 80}, ++{197, 43, 86}, ++{209, 42, 92}, ++{222, 39, 98}, ++{230, 38, 102}, ++{158, 42, 66}, ++{164, 43, 69}, ++{174, 44, 74}, ++{185, 45, 80}, ++{197, 44, 86}, ++{210, 42, 92}, ++{223, 40, 98}, ++{231, 38, 102}, ++{159, 43, 66}, ++{165, 44, 70}, ++{175, 45, 75}, ++{186, 45, 81}, ++{198, 44, 87}, ++{210, 42, 93}, ++{223, 40, 98}, ++{231, 38, 102}, ++{160, 44, 67}, ++{166, 45, 70}, ++{176, 46, 75}, ++{187, 46, 81}, ++{199, 45, 87}, ++{211, 43, 93}, ++{224, 41, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{168, 47, 71}, ++{177, 47, 76}, ++{188, 47, 81}, ++{200, 46, 87}, ++{212, 44, 93}, ++{225, 41, 99}, ++{233, 39, 102}, ++{163, 47, 68}, ++{169, 48, 72}, ++{178, 48, 76}, ++{189, 48, 82}, ++{201, 46, 88}, ++{213, 44, 94}, ++{226, 42, 99}, ++{234, 40, 103}, ++{165, 49, 69}, ++{171, 50, 72}, ++{180, 50, 77}, ++{190, 49, 83}, ++{202, 47, 88}, ++{214, 45, 94}, ++{227, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{172, 51, 73}, ++{181, 51, 78}, ++{192, 50, 83}, ++{203, 48, 89}, ++{215, 46, 94}, ++{228, 43, 100}, ++{236, 41, 103}, ++{169, 53, 71}, ++{174, 53, 74}, ++{183, 52, 78}, ++{193, 51, 84}, ++{205, 49, 89}, ++{217, 47, 95}, ++{229, 44, 100}, ++{237, 42, 104}, ++{171, 55, 72}, ++{176, 54, 75}, ++{185, 54, 79}, ++{195, 52, 84}, ++{206, 50, 90}, ++{218, 48, 95}, ++{230, 45, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{178, 56, 76}, ++{187, 55, 80}, ++{197, 54, 85}, ++{208, 51, 90}, ++{220, 49, 96}, ++{232, 45, 101}, ++{239, 43, 104}, ++{175, 58, 74}, ++{180, 58, 77}, ++{189, 57, 81}, ++{199, 55, 86}, ++{210, 52, 91}, ++{221, 50, 96}, ++{233, 46, 102}, ++{241, 44, 105}, ++{177, 60, 75}, ++{183, 59, 78}, ++{191, 58, 82}, ++{201, 56, 87}, ++{211, 54, 92}, ++{223, 51, 97}, ++{235, 47, 102}, ++{242, 45, 105}, ++{180, 62, 76}, ++{185, 61, 79}, ++{193, 60, 83}, ++{203, 57, 87}, ++{213, 55, 92}, ++{225, 52, 97}, ++{236, 48, 103}, ++{244, 46, 106}, ++{182, 64, 77}, ++{187, 63, 80}, ++{195, 61, 84}, ++{205, 59, 88}, ++{215, 56, 93}, ++{226, 53, 98}, ++{238, 49, 103}, ++{245, 47, 106}, ++{185, 65, 78}, ++{190, 64, 81}, ++{198, 63, 84}, ++{207, 60, 89}, ++{217, 57, 94}, ++{228, 54, 99}, ++{240, 50, 104}, ++{247, 47, 107}, ++{188, 67, 79}, ++{192, 66, 82}, ++{200, 64, 85}, ++{209, 61, 90}, ++{219, 58, 94}, ++{230, 55, 99}, ++{242, 51, 104}, ++{249, 48, 107}, ++{190, 69, 81}, ++{195, 68, 83}, ++{202, 65, 86}, ++{211, 63, 91}, ++{222, 59, 95}, ++{232, 56, 100}, ++{243, 52, 105}, ++{251, 49, 108}, ++{193, 71, 82}, ++{198, 69, 84}, ++{205, 67, 87}, ++{214, 64, 91}, ++{224, 61, 96}, ++{234, 57, 101}, ++{245, 53, 105}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 71, 85}, ++{208, 68, 88}, ++{216, 65, 92}, ++{226, 62, 97}, ++{236, 58, 101}, ++{247, 54, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{203, 72, 86}, ++{210, 70, 89}, ++{219, 67, 93}, ++{228, 63, 97}, ++{239, 59, 102}, ++{249, 55, 106}, ++{255, 52, 109}, ++{202, 75, 85}, ++{206, 74, 87}, ++{213, 71, 90}, ++{221, 68, 94}, ++{231, 64, 98}, ++{241, 60, 103}, ++{252, 56, 107}, ++{255, 53, 110}, ++{205, 77, 86}, ++{209, 75, 88}, ++{216, 72, 91}, ++{224, 69, 95}, ++{233, 65, 99}, ++{243, 61, 103}, ++{254, 57, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{212, 76, 89}, ++{218, 74, 92}, ++{226, 70, 96}, ++{236, 66, 100}, ++{245, 62, 104}, ++{255, 58, 108}, ++{255, 55, 111}, ++{211, 80, 88}, ++{215, 78, 90}, ++{221, 75, 93}, ++{229, 72, 97}, ++{238, 68, 101}, ++{248, 63, 105}, ++{255, 59, 109}, ++{255, 56, 111}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{212, 80, 89}, ++{216, 78, 91}, ++{223, 76, 94}, ++{230, 72, 97}, ++{239, 68, 101}, ++{249, 64, 105}, ++{255, 59, 109}, ++{255, 57, 112}, ++{83, 103, 120}, ++{96, 98, 126}, ++{113, 92, 131}, ++{130, 85, 137}, ++{148, 78, 142}, ++{165, 72, 146}, ++{181, 65, 150}, ++{189, 62, 152}, ++{83, 104, 120}, ++{96, 98, 126}, ++{113, 92, 131}, ++{130, 85, 137}, ++{148, 78, 142}, ++{165, 72, 146}, ++{181, 65, 150}, ++{189, 62, 152}, ++{84, 104, 121}, ++{97, 99, 126}, ++{114, 92, 132}, ++{131, 85, 137}, ++{148, 78, 142}, ++{165, 72, 146}, ++{182, 66, 150}, ++{190, 63, 152}, ++{85, 105, 121}, ++{98, 99, 126}, ++{114, 92, 132}, ++{132, 85, 137}, ++{149, 79, 142}, ++{166, 72, 146}, ++{182, 66, 150}, ++{190, 63, 152}, ++{87, 105, 122}, ++{99, 100, 126}, ++{116, 93, 132}, ++{133, 86, 137}, ++{150, 79, 142}, ++{166, 72, 146}, ++{183, 66, 150}, ++{191, 63, 152}, ++{89, 106, 122}, ++{101, 101, 127}, ++{117, 94, 132}, ++{134, 86, 137}, ++{151, 79, 142}, ++{167, 73, 146}, ++{183, 66, 150}, ++{191, 63, 152}, ++{91, 107, 123}, ++{103, 101, 127}, ++{119, 94, 132}, ++{135, 87, 137}, ++{152, 80, 142}, ++{168, 73, 146}, ++{184, 67, 150}, ++{192, 64, 152}, ++{94, 108, 123}, ++{105, 102, 128}, ++{120, 95, 133}, ++{137, 88, 137}, ++{153, 81, 142}, ++{169, 74, 146}, ++{185, 67, 150}, ++{193, 64, 152}, ++{97, 109, 124}, ++{108, 103, 128}, ++{122, 96, 133}, ++{138, 88, 138}, ++{155, 81, 142}, ++{171, 74, 146}, ++{186, 68, 150}, ++{194, 65, 152}, ++{100, 110, 125}, ++{110, 104, 128}, ++{125, 97, 133}, ++{140, 89, 138}, ++{156, 82, 142}, ++{172, 75, 146}, ++{188, 68, 150}, ++{195, 65, 152}, ++{103, 111, 125}, ++{113, 105, 129}, ++{127, 97, 134}, ++{142, 90, 138}, ++{158, 83, 142}, ++{174, 76, 147}, ++{189, 69, 150}, ++{197, 66, 152}, ++{106, 112, 126}, ++{116, 106, 129}, ++{130, 98, 134}, ++{144, 91, 138}, ++{160, 83, 143}, ++{175, 76, 147}, ++{191, 70, 150}, ++{198, 66, 152}, ++{110, 113, 127}, ++{119, 107, 130}, ++{132, 99, 134}, ++{147, 92, 139}, ++{162, 84, 143}, ++{177, 77, 147}, ++{192, 70, 151}, ++{200, 67, 152}, ++{113, 113, 127}, ++{122, 108, 131}, ++{135, 100, 135}, ++{149, 92, 139}, ++{164, 85, 143}, ++{179, 78, 147}, ++{194, 71, 151}, ++{201, 68, 152}, ++{117, 114, 128}, ++{125, 108, 131}, ++{138, 101, 135}, ++{152, 93, 139}, ++{166, 86, 143}, ++{181, 79, 147}, ++{196, 72, 151}, ++{203, 68, 152}, ++{120, 115, 129}, ++{129, 109, 132}, ++{141, 102, 135}, ++{154, 94, 139}, ++{169, 87, 143}, ++{183, 79, 147}, ++{198, 72, 151}, ++{205, 69, 153}, ++{124, 116, 129}, ++{132, 110, 132}, ++{144, 103, 136}, ++{157, 95, 140}, ++{171, 87, 143}, ++{185, 80, 147}, ++{200, 73, 151}, ++{207, 70, 153}, ++{128, 116, 130}, ++{136, 111, 133}, ++{147, 104, 136}, ++{160, 96, 140}, ++{173, 88, 144}, ++{187, 81, 147}, ++{202, 74, 151}, ++{209, 71, 153}, ++{132, 117, 131}, ++{139, 111, 133}, ++{150, 104, 137}, ++{163, 97, 140}, ++{176, 89, 144}, ++{190, 82, 148}, ++{204, 75, 151}, ++{211, 71, 153}, ++{136, 117, 131}, ++{143, 112, 134}, ++{153, 105, 137}, ++{166, 98, 140}, ++{179, 90, 144}, ++{192, 83, 148}, ++{206, 76, 151}, ++{213, 72, 153}, ++{139, 118, 132}, ++{146, 113, 134}, ++{157, 106, 137}, ++{169, 98, 141}, ++{181, 91, 144}, ++{195, 84, 148}, ++{208, 76, 151}, ++{215, 73, 153}, ++{143, 118, 133}, ++{150, 113, 135}, ++{160, 107, 138}, ++{172, 99, 141}, ++{184, 92, 145}, ++{197, 84, 148}, ++{211, 77, 151}, ++{217, 74, 153}, ++{147, 119, 133}, ++{154, 114, 135}, ++{163, 107, 138}, ++{175, 100, 141}, ++{187, 92, 145}, ++{200, 85, 148}, ++{213, 78, 152}, ++{220, 75, 153}, ++{151, 119, 134}, ++{158, 115, 136}, ++{167, 108, 139}, ++{178, 101, 142}, ++{190, 93, 145}, ++{202, 86, 148}, ++{215, 79, 152}, ++{222, 75, 153}, ++{155, 120, 134}, ++{161, 115, 136}, ++{170, 109, 139}, ++{181, 101, 142}, ++{193, 94, 145}, ++{205, 87, 149}, ++{218, 80, 152}, ++{224, 76, 153}, ++{159, 120, 135}, ++{165, 116, 137}, ++{174, 109, 139}, ++{184, 102, 142}, ++{196, 95, 145}, ++{208, 88, 149}, ++{220, 80, 152}, ++{227, 77, 153}, ++{163, 121, 135}, ++{169, 116, 137}, ++{177, 110, 140}, ++{188, 103, 143}, ++{199, 96, 146}, ++{211, 88, 149}, ++{223, 81, 152}, ++{229, 78, 154}, ++{167, 121, 136}, ++{173, 117, 138}, ++{181, 111, 140}, ++{191, 104, 143}, ++{202, 96, 146}, ++{214, 89, 149}, ++{226, 82, 152}, ++{232, 79, 154}, ++{169, 121, 136}, ++{174, 117, 138}, ++{183, 111, 140}, ++{193, 104, 143}, ++{203, 97, 146}, ++{215, 90, 149}, ++{227, 82, 152}, ++{233, 79, 154}, ++{169, 121, 136}, ++{174, 117, 138}, ++{183, 111, 140}, ++{193, 104, 143}, ++{203, 97, 146}, ++{215, 90, 149}, ++{227, 82, 152}, ++{233, 79, 154}, ++{169, 121, 136}, ++{174, 117, 138}, ++{183, 111, 140}, ++{193, 104, 143}, ++{203, 97, 146}, ++{215, 90, 149}, ++{227, 82, 152}, ++{233, 79, 154}, ++{169, 121, 136}, ++{174, 117, 138}, ++{183, 111, 140}, ++{193, 104, 143}, ++{203, 97, 146}, ++{215, 90, 149}, ++{227, 82, 152}, ++{233, 79, 154}, ++{84, 103, 119}, ++{97, 98, 124}, ++{114, 91, 130}, ++{131, 84, 136}, ++{148, 78, 141}, ++{165, 71, 145}, ++{182, 65, 149}, ++{190, 62, 151}, ++{84, 103, 119}, ++{97, 98, 124}, ++{114, 91, 130}, ++{131, 85, 136}, ++{148, 78, 141}, ++{165, 71, 145}, ++{182, 65, 149}, ++{190, 62, 151}, ++{85, 103, 120}, ++{98, 98, 125}, ++{114, 92, 130}, ++{132, 85, 136}, ++{149, 78, 141}, ++{166, 72, 145}, ++{182, 65, 149}, ++{190, 62, 151}, ++{86, 104, 120}, ++{99, 99, 125}, ++{115, 92, 131}, ++{132, 85, 136}, ++{149, 78, 141}, ++{166, 72, 145}, ++{182, 66, 149}, ++{191, 63, 151}, ++{88, 105, 120}, ++{100, 99, 125}, ++{116, 92, 131}, ++{133, 85, 136}, ++{150, 79, 141}, ++{167, 72, 145}, ++{183, 66, 149}, ++{191, 63, 151}, ++{90, 105, 121}, ++{102, 100, 126}, ++{118, 93, 131}, ++{134, 86, 136}, ++{151, 79, 141}, ++{168, 73, 145}, ++{184, 66, 150}, ++{192, 63, 151}, ++{92, 106, 122}, ++{104, 101, 126}, ++{119, 94, 131}, ++{136, 87, 136}, ++{152, 80, 141}, ++{169, 73, 146}, ++{185, 67, 150}, ++{193, 64, 151}, ++{95, 107, 122}, ++{106, 102, 126}, ++{121, 94, 132}, ++{137, 87, 137}, ++{154, 80, 141}, ++{170, 74, 146}, ++{186, 67, 150}, ++{194, 64, 151}, ++{98, 108, 123}, ++{109, 102, 127}, ++{123, 95, 132}, ++{139, 88, 137}, ++{155, 81, 141}, ++{171, 74, 146}, ++{187, 68, 150}, ++{195, 64, 152}, ++{101, 109, 124}, ++{111, 103, 127}, ++{125, 96, 132}, ++{141, 89, 137}, ++{157, 82, 142}, ++{173, 75, 146}, ++{188, 68, 150}, ++{196, 65, 152}, ++{104, 110, 124}, ++{114, 104, 128}, ++{128, 97, 133}, ++{143, 90, 137}, ++{159, 82, 142}, ++{174, 75, 146}, ++{190, 69, 150}, ++{197, 66, 152}, ++{107, 111, 125}, ++{117, 105, 129}, ++{130, 98, 133}, ++{145, 90, 137}, ++{160, 83, 142}, ++{176, 76, 146}, ++{191, 69, 150}, ++{199, 66, 152}, ++{110, 112, 126}, ++{120, 106, 129}, ++{133, 99, 133}, ++{147, 91, 138}, ++{162, 84, 142}, ++{178, 77, 146}, ++{193, 70, 150}, ++{200, 67, 152}, ++{114, 113, 126}, ++{123, 107, 130}, ++{136, 100, 134}, ++{150, 92, 138}, ++{165, 85, 142}, ++{179, 78, 146}, ++{194, 71, 150}, ++{202, 68, 152}, ++{117, 114, 127}, ++{126, 108, 130}, ++{138, 101, 134}, ++{152, 93, 138}, ++{167, 86, 142}, ++{181, 78, 146}, ++{196, 72, 150}, ++{203, 68, 152}, ++{121, 114, 128}, ++{130, 109, 131}, ++{141, 101, 135}, ++{155, 94, 139}, ++{169, 86, 143}, ++{184, 79, 146}, ++{198, 72, 150}, ++{205, 69, 152}, ++{125, 115, 129}, ++{133, 110, 131}, ++{144, 102, 135}, ++{158, 95, 139}, ++{171, 87, 143}, ++{186, 80, 147}, ++{200, 73, 150}, ++{207, 70, 152}, ++{129, 116, 129}, ++{136, 110, 132}, ++{148, 103, 135}, ++{160, 96, 139}, ++{174, 88, 143}, ++{188, 81, 147}, ++{202, 74, 150}, ++{209, 70, 152}, ++{132, 116, 130}, ++{140, 111, 132}, ++{151, 104, 136}, ++{163, 96, 139}, ++{177, 89, 143}, ++{190, 82, 147}, ++{204, 75, 150}, ++{211, 71, 152}, ++{136, 117, 131}, ++{143, 112, 133}, ++{154, 105, 136}, ++{166, 97, 140}, ++{179, 90, 143}, ++{193, 82, 147}, ++{206, 75, 151}, ++{213, 72, 152}, ++{140, 117, 131}, ++{147, 112, 133}, ++{157, 105, 137}, ++{169, 98, 140}, ++{182, 91, 144}, ++{195, 83, 147}, ++{209, 76, 151}, ++{215, 73, 152}, ++{144, 118, 132}, ++{151, 113, 134}, ++{161, 106, 137}, ++{172, 99, 140}, ++{185, 91, 144}, ++{198, 84, 147}, ++{211, 77, 151}, ++{218, 74, 152}, ++{148, 118, 132}, ++{154, 114, 134}, ++{164, 107, 137}, ++{175, 100, 141}, ++{187, 92, 144}, ++{200, 85, 148}, ++{213, 78, 151}, ++{220, 74, 153}, ++{152, 119, 133}, ++{158, 114, 135}, ++{167, 108, 138}, ++{178, 100, 141}, ++{190, 93, 144}, ++{203, 86, 148}, ++{216, 79, 151}, ++{222, 75, 153}, ++{156, 119, 134}, ++{162, 115, 136}, ++{171, 108, 138}, ++{182, 101, 141}, ++{193, 94, 145}, ++{206, 87, 148}, ++{218, 79, 151}, ++{225, 76, 153}, ++{160, 120, 134}, ++{166, 115, 136}, ++{174, 109, 139}, ++{185, 102, 142}, ++{196, 95, 145}, ++{208, 87, 148}, ++{221, 80, 151}, ++{227, 77, 153}, ++{164, 120, 135}, ++{169, 116, 137}, ++{178, 110, 139}, ++{188, 103, 142}, ++{199, 95, 145}, ++{211, 88, 148}, ++{223, 81, 152}, ++{230, 78, 153}, ++{168, 121, 135}, ++{173, 116, 137}, ++{181, 110, 139}, ++{191, 103, 142}, ++{202, 96, 145}, ++{214, 89, 149}, ++{226, 82, 152}, ++{232, 78, 153}, ++{169, 121, 136}, ++{175, 117, 137}, ++{183, 110, 140}, ++{193, 104, 143}, ++{204, 96, 146}, ++{215, 89, 149}, ++{227, 82, 152}, ++{233, 79, 153}, ++{169, 121, 136}, ++{175, 117, 137}, ++{183, 110, 140}, ++{193, 104, 143}, ++{204, 96, 146}, ++{215, 89, 149}, ++{227, 82, 152}, ++{233, 79, 153}, ++{169, 121, 136}, ++{175, 117, 137}, ++{183, 110, 140}, ++{193, 104, 143}, ++{204, 96, 146}, ++{215, 89, 149}, ++{227, 82, 152}, ++{233, 79, 153}, ++{169, 121, 136}, ++{175, 117, 137}, ++{183, 110, 140}, ++{193, 104, 143}, ++{204, 96, 146}, ++{215, 89, 149}, ++{227, 82, 152}, ++{233, 79, 153}, ++{86, 101, 117}, ++{99, 96, 123}, ++{115, 90, 129}, ++{132, 84, 134}, ++{149, 77, 139}, ++{166, 71, 144}, ++{182, 65, 148}, ++{190, 62, 150}, ++{86, 101, 117}, ++{99, 97, 123}, ++{115, 90, 129}, ++{132, 84, 134}, ++{149, 77, 139}, ++{166, 71, 144}, ++{183, 65, 148}, ++{191, 62, 150}, ++{87, 102, 118}, ++{100, 97, 123}, ++{116, 91, 129}, ++{133, 84, 134}, ++{150, 78, 139}, ++{167, 71, 144}, ++{183, 65, 148}, ++{191, 62, 150}, ++{88, 102, 118}, ++{101, 97, 123}, ++{117, 91, 129}, ++{133, 84, 134}, ++{150, 78, 139}, ++{167, 71, 144}, ++{183, 65, 148}, ++{191, 62, 150}, ++{90, 103, 118}, ++{102, 98, 123}, ++{118, 92, 129}, ++{134, 85, 135}, ++{151, 78, 140}, ++{168, 72, 144}, ++{184, 66, 148}, ++{192, 63, 150}, ++{92, 104, 119}, ++{104, 99, 124}, ++{119, 92, 129}, ++{136, 85, 135}, ++{152, 79, 140}, ++{169, 72, 144}, ++{185, 66, 148}, ++{193, 63, 150}, ++{94, 105, 120}, ++{105, 100, 124}, ++{121, 93, 130}, ++{137, 86, 135}, ++{153, 79, 140}, ++{170, 73, 144}, ++{186, 66, 148}, ++{193, 63, 150}, ++{96, 106, 120}, ++{108, 100, 125}, ++{122, 94, 130}, ++{138, 87, 135}, ++{155, 80, 140}, ++{171, 73, 144}, ++{187, 67, 148}, ++{194, 64, 150}, ++{99, 107, 121}, ++{110, 101, 125}, ++{124, 94, 130}, ++{140, 87, 135}, ++{156, 80, 140}, ++{172, 74, 144}, ++{188, 67, 148}, ++{195, 64, 150}, ++{102, 108, 122}, ++{113, 102, 126}, ++{127, 95, 131}, ++{142, 88, 136}, ++{158, 81, 140}, ++{173, 74, 145}, ++{189, 68, 149}, ++{197, 65, 150}, ++{105, 109, 123}, ++{115, 103, 126}, ++{129, 96, 131}, ++{144, 89, 136}, ++{159, 82, 140}, ++{175, 75, 145}, ++{190, 68, 149}, ++{198, 65, 151}, ++{108, 110, 123}, ++{118, 104, 127}, ++{131, 97, 131}, ++{146, 90, 136}, ++{161, 83, 141}, ++{177, 76, 145}, ++{192, 69, 149}, ++{199, 66, 151}, ++{112, 111, 124}, ++{121, 105, 127}, ++{134, 98, 132}, ++{148, 91, 136}, ++{163, 83, 141}, ++{178, 76, 145}, ++{193, 70, 149}, ++{201, 67, 151}, ++{115, 112, 125}, ++{124, 106, 128}, ++{137, 99, 132}, ++{151, 91, 137}, ++{165, 84, 141}, ++{180, 77, 145}, ++{195, 70, 149}, ++{202, 67, 151}, ++{119, 112, 126}, ++{127, 107, 129}, ++{140, 100, 133}, ++{153, 92, 137}, ++{168, 85, 141}, ++{182, 78, 145}, ++{197, 71, 149}, ++{204, 68, 151}, ++{122, 113, 126}, ++{131, 108, 129}, ++{142, 101, 133}, ++{156, 93, 137}, ++{170, 86, 141}, ++{184, 79, 145}, ++{199, 72, 149}, ++{206, 69, 151}, ++{126, 114, 127}, ++{134, 109, 130}, ++{145, 102, 134}, ++{158, 94, 138}, ++{172, 87, 142}, ++{186, 80, 145}, ++{201, 73, 149}, ++{208, 69, 151}, ++{130, 115, 128}, ++{137, 109, 130}, ++{149, 102, 134}, ++{161, 95, 138}, ++{175, 88, 142}, ++{189, 80, 146}, ++{203, 74, 149}, ++{210, 70, 151}, ++{134, 115, 129}, ++{141, 110, 131}, ++{152, 103, 134}, ++{164, 96, 138}, ++{177, 88, 142}, ++{191, 81, 146}, ++{205, 74, 149}, ++{212, 71, 151}, ++{137, 116, 129}, ++{144, 111, 132}, ++{155, 104, 135}, ++{167, 97, 139}, ++{180, 89, 142}, ++{193, 82, 146}, ++{207, 75, 150}, ++{214, 72, 151}, ++{141, 117, 130}, ++{148, 112, 132}, ++{158, 105, 135}, ++{170, 98, 139}, ++{183, 90, 143}, ++{196, 83, 146}, ++{209, 76, 150}, ++{216, 73, 151}, ++{145, 117, 131}, ++{152, 112, 133}, ++{161, 106, 136}, ++{173, 98, 139}, ++{185, 91, 143}, ++{198, 84, 146}, ++{212, 77, 150}, ++{218, 73, 152}, ++{149, 118, 131}, ++{155, 113, 133}, ++{165, 106, 136}, ++{176, 99, 140}, ++{188, 92, 143}, ++{201, 85, 147}, ++{214, 78, 150}, ++{220, 74, 152}, ++{153, 118, 132}, ++{159, 114, 134}, ++{168, 107, 137}, ++{179, 100, 140}, ++{191, 93, 143}, ++{204, 85, 147}, ++{216, 78, 150}, ++{223, 75, 152}, ++{157, 119, 132}, ++{163, 114, 134}, ++{172, 108, 137}, ++{182, 101, 140}, ++{194, 93, 144}, ++{206, 86, 147}, ++{219, 79, 150}, ++{225, 76, 152}, ++{161, 119, 133}, ++{166, 115, 135}, ++{175, 108, 138}, ++{186, 101, 141}, ++{197, 94, 144}, ++{209, 87, 147}, ++{221, 80, 150}, ++{228, 77, 152}, ++{164, 120, 134}, ++{170, 115, 135}, ++{179, 109, 138}, ++{189, 102, 141}, ++{200, 95, 144}, ++{212, 88, 147}, ++{224, 81, 151}, ++{230, 77, 152}, ++{168, 120, 134}, ++{174, 116, 136}, ++{182, 110, 138}, ++{192, 103, 141}, ++{203, 96, 144}, ++{215, 89, 148}, ++{227, 82, 151}, ++{233, 78, 152}, ++{170, 120, 134}, ++{176, 116, 136}, ++{184, 110, 139}, ++{194, 103, 142}, ++{204, 96, 145}, ++{216, 89, 148}, ++{228, 82, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{176, 116, 136}, ++{184, 110, 139}, ++{194, 103, 142}, ++{204, 96, 145}, ++{216, 89, 148}, ++{228, 82, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{176, 116, 136}, ++{184, 110, 139}, ++{194, 103, 142}, ++{204, 96, 145}, ++{216, 89, 148}, ++{228, 82, 151}, ++{234, 79, 152}, ++{170, 120, 134}, ++{176, 116, 136}, ++{184, 110, 139}, ++{194, 103, 142}, ++{204, 96, 145}, ++{216, 89, 148}, ++{228, 82, 151}, ++{234, 79, 152}, ++{88, 99, 115}, ++{100, 95, 120}, ++{117, 89, 126}, ++{134, 83, 132}, ++{151, 77, 138}, ++{167, 70, 142}, ++{183, 64, 147}, ++{191, 61, 149}, ++{88, 99, 115}, ++{101, 95, 120}, ++{117, 89, 127}, ++{134, 83, 132}, ++{151, 77, 138}, ++{167, 71, 142}, ++{184, 64, 147}, ++{191, 61, 149}, ++{89, 100, 115}, ++{101, 95, 121}, ++{117, 90, 127}, ++{134, 83, 132}, ++{151, 77, 138}, ++{168, 71, 142}, ++{184, 65, 147}, ++{192, 62, 149}, ++{90, 100, 116}, ++{102, 96, 121}, ++{118, 90, 127}, ++{135, 84, 133}, ++{152, 77, 138}, ++{168, 71, 142}, ++{184, 65, 147}, ++{192, 62, 149}, ++{92, 101, 116}, ++{104, 97, 121}, ++{119, 91, 127}, ++{136, 84, 133}, ++{152, 78, 138}, ++{169, 71, 142}, ++{185, 65, 147}, ++{193, 62, 149}, ++{94, 102, 117}, ++{105, 97, 122}, ++{121, 91, 127}, ++{137, 85, 133}, ++{153, 78, 138}, ++{170, 72, 143}, ++{186, 65, 147}, ++{193, 62, 149}, ++{96, 103, 118}, ++{107, 98, 122}, ++{122, 92, 128}, ++{138, 85, 133}, ++{155, 79, 138}, ++{171, 72, 143}, ++{187, 66, 147}, ++{194, 63, 149}, ++{98, 104, 118}, ++{109, 99, 123}, ++{124, 93, 128}, ++{140, 86, 133}, ++{156, 79, 138}, ++{172, 73, 143}, ++{188, 66, 147}, ++{195, 63, 149}, ++{101, 105, 119}, ++{112, 100, 123}, ++{126, 93, 128}, ++{141, 87, 133}, ++{157, 80, 138}, ++{173, 73, 143}, ++{189, 67, 147}, ++{196, 64, 149}, ++{104, 106, 120}, ++{114, 101, 124}, ++{128, 94, 129}, ++{143, 87, 134}, ++{159, 80, 139}, ++{174, 74, 143}, ++{190, 67, 147}, ++{198, 64, 149}, ++{107, 107, 121}, ++{117, 102, 124}, ++{130, 95, 129}, ++{145, 88, 134}, ++{161, 81, 139}, ++{176, 74, 143}, ++{191, 68, 147}, ++{199, 65, 149}, ++{110, 108, 121}, ++{120, 103, 125}, ++{133, 96, 130}, ++{147, 89, 134}, ++{162, 82, 139}, ++{178, 75, 143}, ++{193, 69, 147}, ++{200, 65, 149}, ++{113, 109, 122}, ++{123, 104, 126}, ++{135, 97, 130}, ++{150, 90, 135}, ++{164, 83, 139}, ++{179, 76, 143}, ++{194, 69, 147}, ++{202, 66, 149}, ++{117, 110, 123}, ++{126, 105, 126}, ++{138, 98, 131}, ++{152, 91, 135}, ++{167, 84, 139}, ++{181, 77, 144}, ++{196, 70, 148}, ++{203, 67, 149}, ++{120, 111, 124}, ++{129, 106, 127}, ++{141, 99, 131}, ++{154, 92, 135}, ++{169, 84, 140}, ++{183, 77, 144}, ++{198, 71, 148}, ++{205, 68, 150}, ++{124, 112, 125}, ++{132, 107, 128}, ++{144, 100, 131}, ++{157, 93, 136}, ++{171, 85, 140}, ++{185, 78, 144}, ++{200, 72, 148}, ++{207, 68, 150}, ++{127, 113, 125}, ++{135, 108, 128}, ++{147, 101, 132}, ++{160, 93, 136}, ++{173, 86, 140}, ++{187, 79, 144}, ++{202, 72, 148}, ++{209, 69, 150}, ++{131, 114, 126}, ++{139, 108, 129}, ++{150, 102, 132}, ++{162, 94, 136}, ++{176, 87, 140}, ++{190, 80, 144}, ++{204, 73, 148}, ++{211, 70, 150}, ++{135, 114, 127}, ++{142, 109, 129}, ++{153, 102, 133}, ++{165, 95, 137}, ++{178, 88, 141}, ++{192, 81, 144}, ++{206, 74, 148}, ++{213, 71, 150}, ++{139, 115, 128}, ++{146, 110, 130}, ++{156, 103, 133}, ++{168, 96, 137}, ++{181, 89, 141}, ++{194, 82, 145}, ++{208, 75, 148}, ++{215, 71, 150}, ++{142, 116, 128}, ++{149, 111, 131}, ++{159, 104, 134}, ++{171, 97, 137}, ++{184, 90, 141}, ++{197, 82, 145}, ++{210, 75, 149}, ++{217, 72, 150}, ++{146, 116, 129}, ++{153, 111, 131}, ++{163, 105, 134}, ++{174, 98, 138}, ++{186, 90, 142}, ++{199, 83, 145}, ++{212, 76, 149}, ++{219, 73, 150}, ++{150, 117, 130}, ++{156, 112, 132}, ++{166, 106, 135}, ++{177, 98, 138}, ++{189, 91, 142}, ++{202, 84, 145}, ++{215, 77, 149}, ++{221, 74, 151}, ++{154, 117, 130}, ++{160, 113, 132}, ++{169, 106, 135}, ++{180, 99, 139}, ++{192, 92, 142}, ++{204, 85, 146}, ++{217, 78, 149}, ++{224, 75, 151}, ++{158, 118, 131}, ++{164, 113, 133}, ++{173, 107, 136}, ++{183, 100, 139}, ++{195, 93, 142}, ++{207, 86, 146}, ++{220, 79, 149}, ++{226, 75, 151}, ++{162, 118, 132}, ++{167, 114, 134}, ++{176, 108, 136}, ++{186, 101, 139}, ++{198, 94, 143}, ++{210, 87, 146}, ++{222, 80, 149}, ++{228, 76, 151}, ++{165, 119, 132}, ++{171, 114, 134}, ++{180, 108, 137}, ++{190, 101, 140}, ++{201, 94, 143}, ++{213, 87, 146}, ++{225, 80, 150}, ++{231, 77, 151}, ++{169, 119, 133}, ++{175, 115, 135}, ++{183, 109, 137}, ++{193, 102, 140}, ++{204, 95, 143}, ++{215, 88, 147}, ++{227, 81, 150}, ++{233, 78, 151}, ++{171, 119, 133}, ++{177, 115, 135}, ++{185, 109, 137}, ++{195, 103, 140}, ++{205, 96, 143}, ++{217, 88, 147}, ++{229, 82, 150}, ++{235, 78, 151}, ++{171, 119, 133}, ++{177, 115, 135}, ++{185, 109, 137}, ++{195, 103, 140}, ++{205, 96, 143}, ++{217, 88, 147}, ++{229, 82, 150}, ++{235, 78, 151}, ++{171, 119, 133}, ++{177, 115, 135}, ++{185, 109, 137}, ++{195, 103, 140}, ++{205, 96, 143}, ++{217, 88, 147}, ++{229, 82, 150}, ++{235, 78, 151}, ++{171, 119, 133}, ++{177, 115, 135}, ++{185, 109, 137}, ++{195, 103, 140}, ++{205, 96, 143}, ++{217, 88, 147}, ++{229, 82, 150}, ++{235, 78, 151}, ++{90, 97, 113}, ++{103, 93, 118}, ++{118, 88, 124}, ++{135, 82, 130}, ++{152, 76, 136}, ++{168, 70, 141}, ++{185, 64, 145}, ++{192, 61, 147}, ++{91, 97, 113}, ++{103, 93, 118}, ++{119, 88, 124}, ++{135, 82, 130}, ++{152, 76, 136}, ++{169, 70, 141}, ++{185, 64, 145}, ++{193, 61, 147}, ++{91, 98, 113}, ++{104, 94, 118}, ++{119, 88, 124}, ++{136, 82, 130}, ++{152, 76, 136}, ++{169, 70, 141}, ++{185, 64, 145}, ++{193, 61, 147}, ++{93, 98, 113}, ++{105, 94, 119}, ++{120, 89, 125}, ++{136, 83, 130}, ++{153, 76, 136}, ++{169, 70, 141}, ++{185, 64, 145}, ++{193, 61, 147}, ++{94, 99, 114}, ++{106, 95, 119}, ++{121, 89, 125}, ++{137, 83, 131}, ++{154, 77, 136}, ++{170, 71, 141}, ++{186, 65, 145}, ++{194, 62, 147}, ++{96, 100, 115}, ++{107, 96, 119}, ++{122, 90, 125}, ++{138, 84, 131}, ++{155, 77, 136}, ++{171, 71, 141}, ++{187, 65, 145}, ++{195, 62, 147}, ++{98, 101, 115}, ++{109, 97, 120}, ++{124, 91, 125}, ++{140, 84, 131}, ++{156, 78, 136}, ++{172, 71, 141}, ++{188, 65, 145}, ++{195, 62, 147}, ++{101, 102, 116}, ++{111, 98, 120}, ++{126, 91, 126}, ++{141, 85, 131}, ++{157, 78, 136}, ++{173, 72, 141}, ++{189, 66, 145}, ++{196, 63, 147}, ++{103, 103, 117}, ++{114, 99, 121}, ++{128, 92, 126}, ++{143, 86, 132}, ++{159, 79, 137}, ++{174, 73, 141}, ++{190, 66, 145}, ++{197, 63, 148}, ++{106, 105, 118}, ++{116, 100, 122}, ++{130, 93, 127}, ++{145, 86, 132}, ++{160, 80, 137}, ++{176, 73, 141}, ++{191, 67, 146}, ++{199, 64, 148}, ++{109, 106, 118}, ++{119, 101, 122}, ++{132, 94, 127}, ++{147, 87, 132}, ++{162, 80, 137}, ++{177, 74, 141}, ++{192, 68, 146}, ++{200, 64, 148}, ++{112, 107, 119}, ++{121, 102, 123}, ++{134, 95, 128}, ++{149, 88, 132}, ++{164, 81, 137}, ++{179, 75, 142}, ++{194, 68, 146}, ++{201, 65, 148}, ++{115, 108, 120}, ++{124, 103, 124}, ++{137, 96, 128}, ++{151, 89, 133}, ++{166, 82, 137}, ++{181, 75, 142}, ++{195, 69, 146}, ++{203, 66, 148}, ++{119, 109, 121}, ++{127, 104, 124}, ++{140, 97, 129}, ++{153, 90, 133}, ++{168, 83, 138}, ++{182, 76, 142}, ++{197, 70, 146}, ++{204, 66, 148}, ++{122, 110, 122}, ++{130, 105, 125}, ++{142, 98, 129}, ++{156, 91, 134}, ++{170, 84, 138}, ++{184, 77, 142}, ++{199, 70, 146}, ++{206, 67, 148}, ++{126, 111, 123}, ++{134, 105, 126}, ++{145, 99, 130}, ++{158, 92, 134}, ++{172, 85, 138}, ++{186, 78, 142}, ++{201, 71, 146}, ++{208, 68, 148}, ++{129, 111, 123}, ++{137, 106, 126}, ++{148, 100, 130}, ++{161, 93, 134}, ++{175, 85, 138}, ++{188, 78, 143}, ++{203, 72, 146}, ++{210, 69, 148}, ++{133, 112, 124}, ++{140, 107, 127}, ++{151, 101, 131}, ++{164, 93, 135}, ++{177, 86, 139}, ++{191, 79, 143}, ++{205, 73, 147}, ++{212, 69, 148}, ++{136, 113, 125}, ++{144, 108, 128}, ++{154, 101, 131}, ++{166, 94, 135}, ++{179, 87, 139}, ++{193, 80, 143}, ++{207, 73, 147}, ++{214, 70, 149}, ++{140, 114, 126}, ++{147, 109, 128}, ++{157, 102, 132}, ++{169, 95, 135}, ++{182, 88, 139}, ++{195, 81, 143}, ++{209, 74, 147}, ++{216, 71, 149}, ++{144, 114, 127}, ++{151, 110, 129}, ++{161, 103, 132}, ++{172, 96, 136}, ++{185, 89, 140}, ++{198, 82, 143}, ++{211, 75, 147}, ++{218, 72, 149}, ++{148, 115, 127}, ++{154, 110, 130}, ++{164, 104, 133}, ++{175, 97, 136}, ++{187, 90, 140}, ++{200, 83, 144}, ++{213, 76, 147}, ++{220, 72, 149}, ++{151, 116, 128}, ++{158, 111, 130}, ++{167, 105, 133}, ++{178, 98, 137}, ++{190, 91, 140}, ++{203, 83, 144}, ++{216, 77, 148}, ++{222, 73, 149}, ++{155, 116, 129}, ++{161, 112, 131}, ++{170, 105, 134}, ++{181, 98, 137}, ++{193, 91, 141}, ++{205, 84, 144}, ++{218, 77, 148}, ++{224, 74, 149}, ++{159, 117, 129}, ++{165, 112, 131}, ++{174, 106, 134}, ++{184, 99, 138}, ++{196, 92, 141}, ++{208, 85, 144}, ++{221, 78, 148}, ++{227, 75, 150}, ++{163, 117, 130}, ++{169, 113, 132}, ++{177, 107, 135}, ++{188, 100, 138}, ++{199, 93, 141}, ++{211, 86, 145}, ++{223, 79, 148}, ++{229, 76, 150}, ++{167, 118, 131}, ++{172, 113, 133}, ++{181, 108, 135}, ++{191, 101, 138}, ++{202, 94, 142}, ++{213, 87, 145}, ++{226, 80, 148}, ++{232, 77, 150}, ++{171, 118, 131}, ++{176, 114, 133}, ++{184, 108, 136}, ++{194, 101, 139}, ++{205, 95, 142}, ++{216, 88, 145}, ++{228, 81, 149}, ++{234, 77, 150}, ++{172, 118, 132}, ++{178, 114, 133}, ++{186, 108, 136}, ++{196, 102, 139}, ++{206, 95, 142}, ++{218, 88, 145}, ++{229, 81, 149}, ++{235, 78, 150}, ++{172, 118, 132}, ++{178, 114, 133}, ++{186, 108, 136}, ++{196, 102, 139}, ++{206, 95, 142}, ++{218, 88, 145}, ++{229, 81, 149}, ++{235, 78, 150}, ++{172, 118, 132}, ++{178, 114, 133}, ++{186, 108, 136}, ++{196, 102, 139}, ++{206, 95, 142}, ++{218, 88, 145}, ++{229, 81, 149}, ++{235, 78, 150}, ++{172, 118, 132}, ++{178, 114, 133}, ++{186, 108, 136}, ++{196, 102, 139}, ++{206, 95, 142}, ++{218, 88, 145}, ++{229, 81, 149}, ++{235, 78, 150}, ++{93, 95, 110}, ++{105, 91, 116}, ++{120, 87, 122}, ++{137, 81, 128}, ++{153, 75, 134}, ++{170, 69, 139}, ++{186, 63, 143}, ++{194, 60, 145}, ++{93, 95, 110}, ++{105, 92, 116}, ++{121, 87, 122}, ++{137, 81, 128}, ++{154, 75, 134}, ++{170, 69, 139}, ++{186, 63, 143}, ++{194, 60, 145}, ++{94, 95, 111}, ++{106, 92, 116}, ++{121, 87, 122}, ++{138, 81, 128}, ++{154, 75, 134}, ++{170, 69, 139}, ++{186, 63, 143}, ++{194, 61, 145}, ++{95, 96, 111}, ++{107, 93, 116}, ++{122, 87, 122}, ++{138, 82, 128}, ++{155, 76, 134}, ++{171, 70, 139}, ++{187, 64, 143}, ++{194, 61, 146}, ++{97, 97, 111}, ++{108, 93, 116}, ++{123, 88, 123}, ++{139, 82, 128}, ++{155, 76, 134}, ++{171, 70, 139}, ++{187, 64, 143}, ++{195, 61, 146}, ++{99, 98, 112}, ++{110, 94, 117}, ++{124, 89, 123}, ++{140, 83, 129}, ++{156, 76, 134}, ++{172, 70, 139}, ++{188, 64, 143}, ++{196, 61, 146}, ++{101, 99, 113}, ++{111, 95, 117}, ++{126, 89, 123}, ++{141, 83, 129}, ++{157, 77, 134}, ++{173, 71, 139}, ++{189, 65, 144}, ++{197, 62, 146}, ++{103, 100, 114}, ++{113, 96, 118}, ++{128, 90, 124}, ++{143, 84, 129}, ++{159, 78, 134}, ++{174, 71, 139}, ++{190, 65, 144}, ++{197, 62, 146}, ++{105, 101, 114}, ++{116, 97, 119}, ++{129, 91, 124}, ++{145, 85, 129}, ++{160, 78, 135}, ++{176, 72, 139}, ++{191, 66, 144}, ++{199, 63, 146}, ++{108, 103, 115}, ++{118, 98, 119}, ++{132, 92, 124}, ++{146, 85, 130}, ++{162, 79, 135}, ++{177, 73, 139}, ++{192, 66, 144}, ++{200, 63, 146}, ++{111, 104, 116}, ++{121, 99, 120}, ++{134, 93, 125}, ++{148, 86, 130}, ++{163, 80, 135}, ++{178, 73, 140}, ++{194, 67, 144}, ++{201, 64, 146}, ++{114, 105, 117}, ++{123, 100, 121}, ++{136, 94, 125}, ++{150, 87, 130}, ++{165, 80, 135}, ++{180, 74, 140}, ++{195, 68, 144}, ++{202, 64, 146}, ++{117, 106, 118}, ++{126, 101, 121}, ++{139, 95, 126}, ++{153, 88, 131}, ++{167, 81, 136}, ++{182, 75, 140}, ++{197, 68, 144}, ++{204, 65, 146}, ++{121, 107, 119}, ++{129, 102, 122}, ++{141, 96, 127}, ++{155, 89, 131}, ++{169, 82, 136}, ++{184, 75, 140}, ++{198, 69, 144}, ++{205, 66, 146}, ++{124, 108, 120}, ++{132, 103, 123}, ++{144, 97, 127}, ++{157, 90, 132}, ++{171, 83, 136}, ++{186, 76, 140}, ++{200, 70, 145}, ++{207, 67, 147}, ++{127, 109, 121}, ++{135, 104, 124}, ++{147, 98, 128}, ++{160, 91, 132}, ++{173, 84, 136}, ++{188, 77, 141}, ++{202, 70, 145}, ++{209, 67, 147}, ++{131, 110, 121}, ++{139, 105, 124}, ++{150, 99, 128}, ++{162, 92, 132}, ++{176, 85, 137}, ++{190, 78, 141}, ++{204, 71, 145}, ++{211, 68, 147}, ++{134, 111, 122}, ++{142, 106, 125}, ++{153, 99, 129}, ++{165, 93, 133}, ++{178, 85, 137}, ++{192, 79, 141}, ++{206, 72, 145}, ++{213, 69, 147}, ++{138, 111, 123}, ++{145, 107, 126}, ++{156, 100, 129}, ++{168, 93, 133}, ++{181, 86, 137}, ++{194, 79, 141}, ++{208, 73, 145}, ++{215, 70, 147}, ++{142, 112, 124}, ++{149, 108, 126}, ++{159, 101, 130}, ++{171, 94, 134}, ++{183, 87, 138}, ++{196, 80, 142}, ++{210, 74, 145}, ++{217, 70, 147}, ++{145, 113, 125}, ++{152, 108, 127}, ++{162, 102, 130}, ++{173, 95, 134}, ++{186, 88, 138}, ++{199, 81, 142}, ++{212, 74, 146}, ++{219, 71, 148}, ++{149, 114, 125}, ++{156, 109, 128}, ++{165, 103, 131}, ++{176, 96, 135}, ++{189, 89, 138}, ++{201, 82, 142}, ++{214, 75, 146}, ++{221, 72, 148}, ++{153, 114, 126}, ++{159, 110, 128}, ++{168, 104, 132}, ++{179, 97, 135}, ++{191, 90, 139}, ++{204, 83, 142}, ++{217, 76, 146}, ++{223, 73, 148}, ++{157, 115, 127}, ++{163, 111, 129}, ++{172, 104, 132}, ++{182, 98, 136}, ++{194, 91, 139}, ++{206, 84, 143}, ++{219, 77, 146}, ++{225, 74, 148}, ++{160, 115, 128}, ++{166, 111, 130}, ++{175, 105, 133}, ++{186, 98, 136}, ++{197, 91, 139}, ++{209, 85, 143}, ++{221, 78, 147}, ++{228, 74, 148}, ++{164, 116, 128}, ++{170, 112, 130}, ++{178, 106, 133}, ++{189, 99, 136}, ++{200, 92, 140}, ++{212, 85, 143}, ++{224, 79, 147}, ++{230, 75, 148}, ++{168, 117, 129}, ++{174, 112, 131}, ++{182, 107, 134}, ++{192, 100, 137}, ++{203, 93, 140}, ++{214, 86, 144}, ++{227, 79, 147}, ++{233, 76, 149}, ++{172, 117, 130}, ++{177, 113, 132}, ++{185, 107, 134}, ++{195, 101, 137}, ++{206, 94, 141}, ++{217, 87, 144}, ++{229, 80, 147}, ++{235, 77, 149}, ++{174, 117, 130}, ++{179, 113, 132}, ++{187, 108, 134}, ++{197, 101, 137}, ++{207, 94, 141}, ++{219, 87, 144}, ++{230, 81, 147}, ++{236, 77, 149}, ++{174, 117, 130}, ++{179, 113, 132}, ++{187, 108, 134}, ++{197, 101, 137}, ++{207, 94, 141}, ++{219, 87, 144}, ++{230, 81, 147}, ++{236, 77, 149}, ++{174, 117, 130}, ++{179, 113, 132}, ++{187, 108, 134}, ++{197, 101, 137}, ++{207, 94, 141}, ++{219, 87, 144}, ++{230, 81, 147}, ++{236, 77, 149}, ++{174, 117, 130}, ++{179, 113, 132}, ++{187, 108, 134}, ++{197, 101, 137}, ++{207, 94, 141}, ++{219, 87, 144}, ++{230, 81, 147}, ++{236, 77, 149}, ++{96, 92, 108}, ++{107, 90, 113}, ++{123, 85, 119}, ++{139, 80, 126}, ++{155, 74, 131}, ++{171, 68, 137}, ++{187, 63, 141}, ++{195, 60, 144}, ++{96, 92, 108}, ++{108, 90, 113}, ++{123, 85, 120}, ++{139, 80, 126}, ++{155, 74, 131}, ++{171, 68, 137}, ++{187, 63, 141}, ++{195, 60, 144}, ++{97, 93, 108}, ++{108, 90, 113}, ++{123, 85, 120}, ++{139, 80, 126}, ++{156, 74, 131}, ++{172, 69, 137}, ++{188, 63, 141}, ++{195, 60, 144}, ++{98, 94, 109}, ++{109, 91, 114}, ++{124, 86, 120}, ++{140, 80, 126}, ++{156, 75, 132}, ++{172, 69, 137}, ++{188, 63, 141}, ++{196, 60, 144}, ++{99, 95, 109}, ++{110, 91, 114}, ++{125, 86, 120}, ++{141, 81, 126}, ++{157, 75, 132}, ++{173, 69, 137}, ++{189, 63, 142}, ++{196, 60, 144}, ++{101, 96, 110}, ++{112, 92, 115}, ++{126, 87, 120}, ++{142, 81, 126}, ++{158, 75, 132}, ++{174, 70, 137}, ++{189, 64, 142}, ++{197, 61, 144}, ++{103, 97, 110}, ++{114, 93, 115}, ++{128, 88, 121}, ++{143, 82, 127}, ++{159, 76, 132}, ++{175, 70, 137}, ++{190, 64, 142}, ++{198, 61, 144}, ++{105, 98, 111}, ++{116, 94, 116}, ++{129, 89, 121}, ++{145, 83, 127}, ++{160, 77, 132}, ++{176, 71, 137}, ++{191, 65, 142}, ++{199, 62, 144}, ++{108, 99, 112}, ++{118, 95, 116}, ++{131, 90, 122}, ++{146, 83, 127}, ++{162, 77, 132}, ++{177, 71, 137}, ++{192, 65, 142}, ++{200, 62, 144}, ++{111, 100, 113}, ++{120, 96, 117}, ++{133, 90, 122}, ++{148, 84, 128}, ++{163, 78, 133}, ++{178, 72, 138}, ++{193, 66, 142}, ++{201, 63, 144}, ++{113, 102, 114}, ++{123, 97, 118}, ++{136, 91, 123}, ++{150, 85, 128}, ++{165, 79, 133}, ++{180, 72, 138}, ++{195, 66, 142}, ++{202, 63, 144}, ++{116, 103, 115}, ++{125, 98, 118}, ++{138, 92, 123}, ++{152, 86, 128}, ++{167, 80, 133}, ++{181, 73, 138}, ++{196, 67, 142}, ++{204, 64, 144}, ++{119, 104, 116}, ++{128, 99, 119}, ++{140, 93, 124}, ++{154, 87, 129}, ++{169, 80, 134}, ++{183, 74, 138}, ++{198, 68, 143}, ++{205, 65, 145}, ++{123, 105, 117}, ++{131, 101, 120}, ++{143, 94, 124}, ++{156, 88, 129}, ++{171, 81, 134}, ++{185, 75, 138}, ++{199, 68, 143}, ++{207, 65, 145}, ++{126, 106, 117}, ++{134, 102, 121}, ++{146, 95, 125}, ++{159, 89, 130}, ++{173, 82, 134}, ++{187, 75, 139}, ++{201, 69, 143}, ++{208, 66, 145}, ++{129, 107, 118}, ++{137, 103, 121}, ++{148, 96, 126}, ++{161, 90, 130}, ++{175, 83, 135}, ++{189, 76, 139}, ++{203, 70, 143}, ++{210, 67, 145}, ++{133, 108, 119}, ++{140, 104, 122}, ++{151, 97, 126}, ++{164, 91, 131}, ++{177, 84, 135}, ++{191, 77, 139}, ++{205, 71, 143}, ++{212, 67, 145}, ++{136, 109, 120}, ++{144, 104, 123}, ++{154, 98, 127}, ++{166, 91, 131}, ++{180, 85, 135}, ++{193, 78, 139}, ++{207, 71, 143}, ++{214, 68, 145}, ++{140, 110, 121}, ++{147, 105, 124}, ++{157, 99, 127}, ++{169, 92, 131}, ++{182, 86, 136}, ++{195, 79, 140}, ++{209, 72, 144}, ++{216, 69, 146}, ++{143, 111, 122}, ++{150, 106, 124}, ++{160, 100, 128}, ++{172, 93, 132}, ++{185, 86, 136}, ++{198, 80, 140}, ++{211, 73, 144}, ++{218, 70, 146}, ++{147, 111, 123}, ++{154, 107, 125}, ++{163, 101, 129}, ++{175, 94, 132}, ++{187, 87, 136}, ++{200, 80, 140}, ++{213, 74, 144}, ++{220, 71, 146}, ++{151, 112, 124}, ++{157, 108, 126}, ++{167, 102, 129}, ++{178, 95, 133}, ++{190, 88, 137}, ++{202, 81, 141}, ++{215, 75, 144}, ++{222, 71, 146}, ++{154, 113, 124}, ++{161, 109, 127}, ++{170, 103, 130}, ++{181, 96, 133}, ++{193, 89, 137}, ++{205, 82, 141}, ++{218, 75, 145}, ++{224, 72, 146}, ++{158, 114, 125}, ++{164, 109, 127}, ++{173, 103, 130}, ++{184, 97, 134}, ++{195, 90, 137}, ++{208, 83, 141}, ++{220, 76, 145}, ++{226, 73, 147}, ++{162, 114, 126}, ++{168, 110, 128}, ++{176, 104, 131}, ++{187, 98, 134}, ++{198, 91, 138}, ++{210, 84, 141}, ++{223, 77, 145}, ++{229, 74, 147}, ++{166, 115, 127}, ++{171, 111, 129}, ++{180, 105, 131}, ++{190, 98, 135}, ++{201, 91, 138}, ++{213, 85, 142}, ++{225, 78, 145}, ++{231, 75, 147}, ++{169, 115, 127}, ++{175, 111, 129}, ++{183, 106, 132}, ++{193, 99, 135}, ++{204, 92, 139}, ++{216, 85, 142}, ++{228, 79, 146}, ++{234, 75, 147}, ++{173, 116, 128}, ++{179, 112, 130}, ++{187, 106, 133}, ++{196, 100, 136}, ++{207, 93, 139}, ++{218, 86, 142}, ++{230, 80, 146}, ++{236, 76, 147}, ++{175, 116, 128}, ++{180, 112, 130}, ++{188, 107, 133}, ++{198, 100, 136}, ++{208, 93, 139}, ++{220, 87, 143}, ++{231, 80, 146}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 112, 130}, ++{188, 107, 133}, ++{198, 100, 136}, ++{208, 93, 139}, ++{220, 87, 143}, ++{231, 80, 146}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 112, 130}, ++{188, 107, 133}, ++{198, 100, 136}, ++{208, 93, 139}, ++{220, 87, 143}, ++{231, 80, 146}, ++{237, 77, 148}, ++{175, 116, 128}, ++{180, 112, 130}, ++{188, 107, 133}, ++{198, 100, 136}, ++{208, 93, 139}, ++{220, 87, 143}, ++{231, 80, 146}, ++{237, 77, 148}, ++{98, 90, 105}, ++{110, 87, 111}, ++{125, 83, 117}, ++{141, 78, 123}, ++{157, 73, 129}, ++{173, 68, 135}, ++{189, 62, 139}, ++{196, 59, 142}, ++{99, 90, 105}, ++{110, 88, 111}, ++{125, 84, 117}, ++{141, 79, 123}, ++{157, 73, 129}, ++{173, 68, 135}, ++{189, 62, 139}, ++{196, 59, 142}, ++{99, 90, 106}, ++{111, 88, 111}, ++{125, 84, 117}, ++{141, 79, 123}, ++{157, 73, 129}, ++{173, 68, 135}, ++{189, 62, 139}, ++{197, 59, 142}, ++{101, 91, 106}, ++{112, 89, 111}, ++{126, 84, 117}, ++{142, 79, 124}, ++{158, 74, 129}, ++{174, 68, 135}, ++{189, 62, 140}, ++{197, 60, 142}, ++{102, 92, 107}, ++{113, 89, 112}, ++{127, 85, 118}, ++{143, 80, 124}, ++{159, 74, 130}, ++{174, 68, 135}, ++{190, 63, 140}, ++{198, 60, 142}, ++{104, 93, 107}, ++{114, 90, 112}, ++{128, 86, 118}, ++{144, 80, 124}, ++{160, 74, 130}, ++{175, 69, 135}, ++{191, 63, 140}, ++{198, 60, 142}, ++{106, 94, 108}, ++{116, 91, 113}, ++{130, 86, 118}, ++{145, 81, 124}, ++{161, 75, 130}, ++{176, 69, 135}, ++{192, 63, 140}, ++{199, 61, 142}, ++{108, 96, 109}, ++{118, 92, 113}, ++{132, 87, 119}, ++{146, 81, 125}, ++{162, 76, 130}, ++{177, 70, 135}, ++{192, 64, 140}, ++{200, 61, 142}, ++{110, 97, 110}, ++{120, 93, 114}, ++{133, 88, 119}, ++{148, 82, 125}, ++{163, 76, 130}, ++{178, 70, 135}, ++{194, 64, 140}, ++{201, 61, 142}, ++{113, 98, 111}, ++{122, 94, 115}, ++{135, 89, 120}, ++{150, 83, 125}, ++{165, 77, 131}, ++{180, 71, 136}, ++{195, 65, 140}, ++{202, 62, 142}, ++{116, 99, 111}, ++{125, 95, 115}, ++{138, 90, 120}, ++{152, 84, 126}, ++{166, 78, 131}, ++{181, 72, 136}, ++{196, 66, 140}, ++{203, 63, 143}, ++{119, 101, 112}, ++{127, 97, 116}, ++{140, 91, 121}, ++{154, 85, 126}, ++{168, 79, 131}, ++{183, 72, 136}, ++{198, 66, 141}, ++{205, 63, 143}, ++{122, 102, 113}, ++{130, 98, 117}, ++{142, 92, 122}, ++{156, 86, 127}, ++{170, 79, 132}, ++{185, 73, 136}, ++{199, 67, 141}, ++{206, 64, 143}, ++{125, 103, 114}, ++{133, 99, 118}, ++{145, 93, 122}, ++{158, 87, 127}, ++{172, 80, 132}, ++{186, 74, 137}, ++{201, 68, 141}, ++{208, 65, 143}, ++{128, 104, 115}, ++{136, 100, 118}, ++{147, 94, 123}, ++{160, 88, 128}, ++{174, 81, 132}, ++{188, 75, 137}, ++{202, 68, 141}, ++{209, 65, 143}, ++{131, 105, 116}, ++{139, 101, 119}, ++{150, 95, 123}, ++{163, 89, 128}, ++{176, 82, 133}, ++{190, 75, 137}, ++{204, 69, 141}, ++{211, 66, 143}, ++{135, 106, 117}, ++{142, 102, 120}, ++{153, 96, 124}, ++{165, 89, 129}, ++{179, 83, 133}, ++{192, 76, 137}, ++{206, 70, 142}, ++{213, 67, 144}, ++{138, 107, 118}, ++{145, 103, 121}, ++{156, 97, 125}, ++{168, 90, 129}, ++{181, 84, 133}, ++{194, 77, 138}, ++{208, 71, 142}, ++{215, 68, 144}, ++{142, 108, 119}, ++{149, 104, 122}, ++{159, 98, 125}, ++{171, 91, 130}, ++{183, 85, 134}, ++{197, 78, 138}, ++{210, 71, 142}, ++{217, 68, 144}, ++{145, 109, 120}, ++{152, 105, 122}, ++{162, 99, 126}, ++{173, 92, 130}, ++{186, 85, 134}, ++{199, 79, 138}, ++{212, 72, 142}, ++{219, 69, 144}, ++{149, 110, 121}, ++{155, 106, 123}, ++{165, 100, 127}, ++{176, 93, 131}, ++{189, 86, 135}, ++{201, 80, 139}, ++{214, 73, 142}, ++{221, 70, 144}, ++{152, 111, 122}, ++{159, 106, 124}, ++{168, 101, 127}, ++{179, 94, 131}, ++{191, 87, 135}, ++{204, 81, 139}, ++{217, 74, 143}, ++{223, 71, 145}, ++{156, 111, 122}, ++{162, 107, 125}, ++{171, 101, 128}, ++{182, 95, 132}, ++{194, 88, 135}, ++{206, 81, 139}, ++{219, 75, 143}, ++{225, 72, 145}, ++{160, 112, 123}, ++{166, 108, 125}, ++{175, 102, 128}, ++{185, 96, 132}, ++{197, 89, 136}, ++{209, 82, 139}, ++{221, 76, 143}, ++{228, 72, 145}, ++{163, 113, 124}, ++{169, 109, 126}, ++{178, 103, 129}, ++{188, 97, 133}, ++{199, 90, 136}, ++{211, 83, 140}, ++{224, 76, 143}, ++{230, 73, 145}, ++{167, 113, 125}, ++{173, 109, 127}, ++{181, 104, 130}, ++{191, 97, 133}, ++{202, 91, 137}, ++{214, 84, 140}, ++{226, 77, 144}, ++{232, 74, 146}, ++{171, 114, 126}, ++{176, 110, 127}, ++{185, 105, 130}, ++{194, 98, 134}, ++{205, 91, 137}, ++{217, 85, 140}, ++{229, 78, 144}, ++{235, 75, 146}, ++{175, 115, 126}, ++{180, 111, 128}, ++{188, 105, 131}, ++{198, 99, 134}, ++{208, 92, 137}, ++{219, 86, 141}, ++{231, 79, 144}, ++{237, 76, 146}, ++{177, 115, 127}, ++{182, 111, 129}, ++{190, 106, 131}, ++{199, 99, 134}, ++{210, 93, 138}, ++{221, 86, 141}, ++{232, 79, 144}, ++{238, 76, 146}, ++{177, 115, 127}, ++{182, 111, 129}, ++{190, 106, 131}, ++{199, 99, 134}, ++{210, 93, 138}, ++{221, 86, 141}, ++{232, 79, 144}, ++{238, 76, 146}, ++{177, 115, 127}, ++{182, 111, 129}, ++{190, 106, 131}, ++{199, 99, 134}, ++{210, 93, 138}, ++{221, 86, 141}, ++{232, 79, 144}, ++{238, 76, 146}, ++{177, 115, 127}, ++{182, 111, 129}, ++{190, 106, 131}, ++{199, 99, 134}, ++{210, 93, 138}, ++{221, 86, 141}, ++{232, 79, 144}, ++{238, 76, 146}, ++{101, 87, 103}, ++{112, 85, 108}, ++{127, 82, 115}, ++{143, 77, 121}, ++{159, 72, 127}, ++{174, 67, 132}, ++{190, 61, 137}, ++{198, 58, 140}, ++{102, 87, 103}, ++{113, 85, 108}, ++{127, 82, 115}, ++{143, 77, 121}, ++{159, 72, 127}, ++{175, 67, 132}, ++{190, 61, 137}, ++{198, 58, 140}, ++{102, 88, 103}, ++{113, 86, 108}, ++{128, 82, 115}, ++{143, 77, 121}, ++{159, 72, 127}, ++{175, 67, 132}, ++{190, 61, 137}, ++{198, 59, 140}, ++{103, 89, 104}, ++{114, 86, 109}, ++{128, 83, 115}, ++{144, 78, 121}, ++{160, 73, 127}, ++{175, 67, 133}, ++{191, 62, 138}, ++{198, 59, 140}, ++{105, 90, 104}, ++{115, 87, 109}, ++{129, 83, 115}, ++{145, 78, 122}, ++{160, 73, 127}, ++{176, 67, 133}, ++{191, 62, 138}, ++{199, 59, 140}, ++{106, 91, 105}, ++{117, 88, 110}, ++{131, 84, 116}, ++{146, 79, 122}, ++{161, 73, 127}, ++{177, 68, 133}, ++{192, 62, 138}, ++{200, 59, 140}, ++{108, 92, 106}, ++{118, 89, 110}, ++{132, 85, 116}, ++{147, 79, 122}, ++{162, 74, 128}, ++{178, 68, 133}, ++{193, 63, 138}, ++{200, 60, 140}, ++{110, 93, 106}, ++{120, 90, 111}, ++{134, 86, 117}, ++{148, 80, 122}, ++{164, 75, 128}, ++{179, 69, 133}, ++{194, 63, 138}, ++{201, 60, 140}, ++{113, 95, 107}, ++{122, 91, 112}, ++{135, 86, 117}, ++{150, 81, 123}, ++{165, 75, 128}, ++{180, 69, 133}, ++{195, 64, 138}, ++{202, 61, 140}, ++{115, 96, 108}, ++{125, 92, 112}, ++{137, 87, 118}, ++{152, 82, 123}, ++{166, 76, 129}, ++{181, 70, 134}, ++{196, 64, 138}, ++{204, 61, 141}, ++{118, 97, 109}, ++{127, 94, 113}, ++{140, 88, 118}, ++{153, 83, 124}, ++{168, 77, 129}, ++{183, 71, 134}, ++{198, 65, 138}, ++{205, 62, 141}, ++{121, 99, 110}, ++{130, 95, 114}, ++{142, 89, 119}, ++{155, 84, 124}, ++{170, 77, 129}, ++{184, 71, 134}, ++{199, 65, 139}, ++{206, 63, 141}, ++{124, 100, 111}, ++{132, 96, 115}, ++{144, 90, 119}, ++{158, 84, 124}, ++{172, 78, 129}, ++{186, 72, 134}, ++{200, 66, 139}, ++{208, 63, 141}, ++{127, 101, 112}, ++{135, 97, 115}, ++{147, 91, 120}, ++{160, 85, 125}, ++{174, 79, 130}, ++{188, 73, 135}, ++{202, 67, 139}, ++{209, 64, 141}, ++{130, 102, 113}, ++{138, 98, 116}, ++{149, 93, 121}, ++{162, 86, 125}, ++{176, 80, 130}, ++{190, 74, 135}, ++{204, 68, 139}, ++{211, 65, 141}, ++{133, 103, 114}, ++{141, 99, 117}, ++{152, 94, 121}, ++{165, 87, 126}, ++{178, 81, 131}, ++{192, 75, 135}, ++{206, 68, 139}, ++{212, 65, 142}, ++{137, 104, 115}, ++{144, 100, 118}, ++{155, 95, 122}, ++{167, 88, 126}, ++{180, 82, 131}, ++{194, 75, 135}, ++{207, 69, 140}, ++{214, 66, 142}, ++{140, 105, 116}, ++{147, 101, 119}, ++{158, 96, 123}, ++{170, 89, 127}, ++{182, 83, 131}, ++{196, 76, 136}, ++{209, 70, 140}, ++{216, 67, 142}, ++{144, 106, 117}, ++{151, 102, 120}, ++{161, 97, 123}, ++{172, 90, 128}, ++{185, 84, 132}, ++{198, 77, 136}, ++{211, 71, 140}, ++{218, 68, 142}, ++{147, 107, 118}, ++{154, 103, 120}, ++{164, 97, 124}, ++{175, 91, 128}, ++{187, 85, 132}, ++{200, 78, 136}, ++{213, 72, 140}, ++{220, 68, 142}, ++{151, 108, 119}, ++{157, 104, 121}, ++{167, 98, 125}, ++{178, 92, 129}, ++{190, 85, 133}, ++{203, 79, 137}, ++{216, 72, 141}, ++{222, 69, 143}, ++{154, 109, 120}, ++{161, 105, 122}, ++{170, 99, 125}, ++{181, 93, 129}, ++{193, 86, 133}, ++{205, 80, 137}, ++{218, 73, 141}, ++{224, 70, 143}, ++{158, 110, 120}, ++{164, 106, 123}, ++{173, 100, 126}, ++{184, 94, 130}, ++{195, 87, 134}, ++{208, 81, 137}, ++{220, 74, 141}, ++{226, 71, 143}, ++{161, 111, 121}, ++{167, 107, 123}, ++{176, 101, 127}, ++{187, 95, 130}, ++{198, 88, 134}, ++{210, 81, 138}, ++{222, 75, 142}, ++{229, 72, 143}, ++{165, 111, 122}, ++{171, 107, 124}, ++{179, 102, 127}, ++{190, 95, 131}, ++{201, 89, 134}, ++{213, 82, 138}, ++{225, 76, 142}, ++{231, 73, 144}, ++{169, 112, 123}, ++{174, 108, 125}, ++{183, 103, 128}, ++{193, 96, 131}, ++{204, 90, 135}, ++{215, 83, 139}, ++{227, 77, 142}, ++{233, 73, 144}, ++{172, 113, 124}, ++{178, 109, 126}, ++{186, 103, 128}, ++{196, 97, 132}, ++{206, 91, 135}, ++{218, 84, 139}, ++{230, 77, 142}, ++{236, 74, 144}, ++{176, 113, 125}, ++{181, 110, 126}, ++{189, 104, 129}, ++{199, 98, 132}, ++{209, 91, 136}, ++{221, 85, 139}, ++{232, 78, 143}, ++{238, 75, 144}, ++{178, 114, 125}, ++{183, 110, 127}, ++{191, 104, 129}, ++{200, 98, 133}, ++{211, 92, 136}, ++{222, 85, 139}, ++{234, 79, 143}, ++{239, 75, 145}, ++{178, 114, 125}, ++{183, 110, 127}, ++{191, 104, 129}, ++{200, 98, 133}, ++{211, 92, 136}, ++{222, 85, 139}, ++{234, 79, 143}, ++{239, 75, 145}, ++{178, 114, 125}, ++{183, 110, 127}, ++{191, 104, 129}, ++{200, 98, 133}, ++{211, 92, 136}, ++{222, 85, 139}, ++{234, 79, 143}, ++{239, 75, 145}, ++{178, 114, 125}, ++{183, 110, 127}, ++{191, 104, 129}, ++{200, 98, 133}, ++{211, 92, 136}, ++{222, 85, 139}, ++{234, 79, 143}, ++{239, 75, 145}, ++{104, 85, 100}, ++{115, 83, 106}, ++{129, 80, 112}, ++{145, 76, 119}, ++{160, 71, 125}, ++{176, 66, 130}, ++{191, 60, 135}, ++{199, 58, 138}, ++{104, 85, 101}, ++{115, 83, 106}, ++{129, 80, 112}, ++{145, 76, 119}, ++{161, 71, 125}, ++{176, 66, 130}, ++{192, 60, 135}, ++{199, 58, 138}, ++{105, 85, 101}, ++{116, 84, 106}, ++{130, 80, 112}, ++{145, 76, 119}, ++{161, 71, 125}, ++{176, 66, 130}, ++{192, 61, 135}, ++{199, 58, 138}, ++{106, 86, 101}, ++{117, 84, 106}, ++{131, 81, 113}, ++{146, 76, 119}, ++{161, 71, 125}, ++{177, 66, 130}, ++{192, 61, 136}, ++{200, 58, 138}, ++{107, 87, 102}, ++{118, 85, 107}, ++{132, 81, 113}, ++{147, 77, 119}, ++{162, 72, 125}, ++{178, 66, 131}, ++{193, 61, 136}, ++{200, 58, 138}, ++{109, 88, 103}, ++{119, 86, 107}, ++{133, 82, 113}, ++{148, 77, 119}, ++{163, 72, 125}, ++{178, 67, 131}, ++{194, 61, 136}, ++{201, 59, 138}, ++{111, 89, 103}, ++{121, 87, 108}, ++{134, 83, 114}, ++{149, 78, 120}, ++{164, 73, 126}, ++{179, 67, 131}, ++{194, 62, 136}, ++{202, 59, 138}, ++{113, 91, 104}, ++{123, 88, 109}, ++{136, 84, 114}, ++{150, 79, 120}, ++{165, 73, 126}, ++{180, 68, 131}, ++{195, 62, 136}, ++{203, 60, 138}, ++{115, 92, 105}, ++{125, 89, 109}, ++{138, 85, 115}, ++{152, 80, 121}, ++{167, 74, 126}, ++{182, 68, 131}, ++{196, 63, 136}, ++{204, 60, 138}, ++{118, 94, 106}, ++{127, 90, 110}, ++{140, 86, 115}, ++{154, 80, 121}, ++{168, 75, 126}, ++{183, 69, 131}, ++{198, 63, 136}, ++{205, 61, 139}, ++{121, 95, 107}, ++{129, 92, 111}, ++{142, 87, 116}, ++{155, 81, 121}, ++{170, 76, 127}, ++{184, 70, 132}, ++{199, 64, 136}, ++{206, 61, 139}, ++{123, 96, 108}, ++{132, 93, 112}, ++{144, 88, 117}, ++{157, 82, 122}, ++{171, 76, 127}, ++{186, 70, 132}, ++{200, 65, 137}, ++{208, 62, 139}, ++{126, 98, 109}, ++{134, 94, 112}, ++{146, 89, 117}, ++{159, 83, 122}, ++{173, 77, 127}, ++{188, 71, 132}, ++{202, 65, 137}, ++{209, 62, 139}, ++{129, 99, 110}, ++{137, 95, 113}, ++{149, 90, 118}, ++{162, 84, 123}, ++{175, 78, 128}, ++{189, 72, 133}, ++{203, 66, 137}, ++{210, 63, 139}, ++{132, 100, 111}, ++{140, 96, 114}, ++{151, 91, 118}, ++{164, 85, 123}, ++{177, 79, 128}, ++{191, 73, 133}, ++{205, 67, 137}, ++{212, 64, 140}, ++{136, 101, 112}, ++{143, 97, 115}, ++{154, 92, 119}, ++{166, 86, 124}, ++{179, 80, 129}, ++{193, 74, 133}, ++{207, 68, 138}, ++{214, 65, 140}, ++{139, 102, 113}, ++{146, 99, 116}, ++{157, 93, 120}, ++{169, 87, 124}, ++{182, 81, 129}, ++{195, 74, 134}, ++{209, 68, 138}, ++{216, 65, 140}, ++{142, 104, 114}, ++{149, 100, 117}, ++{159, 94, 121}, ++{171, 88, 125}, ++{184, 82, 129}, ++{197, 75, 134}, ++{211, 69, 138}, ++{217, 66, 140}, ++{146, 105, 115}, ++{152, 101, 117}, ++{162, 95, 121}, ++{174, 89, 126}, ++{186, 83, 130}, ++{199, 76, 134}, ++{213, 70, 138}, ++{219, 67, 140}, ++{149, 106, 116}, ++{156, 102, 118}, ++{165, 96, 122}, ++{177, 90, 126}, ++{189, 83, 130}, ++{202, 77, 135}, ++{215, 71, 139}, ++{221, 68, 141}, ++{153, 107, 117}, ++{159, 103, 119}, ++{168, 97, 123}, ++{179, 91, 127}, ++{191, 84, 131}, ++{204, 78, 135}, ++{217, 72, 139}, ++{223, 68, 141}, ++{156, 107, 117}, ++{162, 103, 120}, ++{171, 98, 123}, ++{182, 92, 127}, ++{194, 85, 131}, ++{206, 79, 135}, ++{219, 72, 139}, ++{225, 69, 141}, ++{160, 108, 118}, ++{166, 104, 121}, ++{175, 99, 124}, ++{185, 93, 128}, ++{197, 86, 132}, ++{209, 80, 136}, ++{221, 73, 140}, ++{228, 70, 142}, ++{163, 109, 119}, ++{169, 105, 121}, ++{178, 100, 125}, ++{188, 94, 128}, ++{199, 87, 132}, ++{211, 81, 136}, ++{224, 74, 140}, ++{230, 71, 142}, ++{167, 110, 120}, ++{173, 106, 122}, ++{181, 101, 125}, ++{191, 94, 129}, ++{202, 88, 133}, ++{214, 81, 136}, ++{226, 75, 140}, ++{232, 72, 142}, ++{170, 111, 121}, ++{176, 107, 123}, ++{184, 101, 126}, ++{194, 95, 129}, ++{205, 89, 133}, ++{217, 82, 137}, ++{228, 76, 141}, ++{235, 73, 142}, ++{174, 111, 122}, ++{179, 108, 124}, ++{187, 102, 127}, ++{197, 96, 130}, ++{208, 90, 134}, ++{219, 83, 137}, ++{231, 77, 141}, ++{237, 73, 143}, ++{178, 112, 123}, ++{183, 108, 125}, ++{191, 103, 127}, ++{200, 97, 131}, ++{211, 90, 134}, ++{222, 84, 138}, ++{233, 77, 141}, ++{239, 74, 143}, ++{180, 112, 123}, ++{185, 109, 125}, ++{192, 103, 128}, ++{202, 97, 131}, ++{212, 91, 134}, ++{223, 84, 138}, ++{235, 78, 141}, ++{241, 75, 143}, ++{180, 112, 123}, ++{185, 109, 125}, ++{192, 103, 128}, ++{202, 97, 131}, ++{212, 91, 134}, ++{223, 84, 138}, ++{235, 78, 141}, ++{241, 75, 143}, ++{180, 112, 123}, ++{185, 109, 125}, ++{192, 103, 128}, ++{202, 97, 131}, ++{212, 91, 134}, ++{223, 84, 138}, ++{235, 78, 141}, ++{241, 75, 143}, ++{180, 112, 123}, ++{185, 109, 125}, ++{192, 103, 128}, ++{202, 97, 131}, ++{212, 91, 134}, ++{223, 84, 138}, ++{235, 78, 141}, ++{241, 75, 143}, ++{107, 82, 98}, ++{118, 81, 103}, ++{132, 78, 110}, ++{147, 74, 116}, ++{162, 70, 122}, ++{178, 65, 128}, ++{193, 59, 133}, ++{201, 57, 136}, ++{107, 82, 98}, ++{118, 81, 103}, ++{132, 78, 110}, ++{147, 74, 116}, ++{162, 70, 122}, ++{178, 65, 128}, ++{193, 60, 133}, ++{201, 57, 136}, ++{108, 83, 99}, ++{118, 81, 104}, ++{132, 79, 110}, ++{147, 75, 116}, ++{163, 70, 123}, ++{178, 65, 128}, ++{193, 60, 133}, ++{201, 57, 136}, ++{109, 84, 99}, ++{119, 82, 104}, ++{133, 79, 110}, ++{148, 75, 117}, ++{163, 70, 123}, ++{179, 65, 128}, ++{194, 60, 133}, ++{201, 57, 136}, ++{110, 84, 100}, ++{120, 83, 104}, ++{134, 80, 111}, ++{149, 75, 117}, ++{164, 71, 123}, ++{179, 65, 128}, ++{194, 60, 134}, ++{202, 58, 136}, ++{112, 86, 100}, ++{122, 84, 105}, ++{135, 80, 111}, ++{150, 76, 117}, ++{165, 71, 123}, ++{180, 66, 129}, ++{195, 61, 134}, ++{203, 58, 136}, ++{114, 87, 101}, ++{123, 85, 106}, ++{136, 81, 111}, ++{151, 77, 117}, ++{166, 72, 123}, ++{181, 66, 129}, ++{196, 61, 134}, ++{203, 58, 136}, ++{116, 88, 102}, ++{125, 86, 106}, ++{138, 82, 112}, ++{152, 77, 118}, ++{167, 72, 124}, ++{182, 67, 129}, ++{197, 61, 134}, ++{204, 59, 136}, ++{118, 90, 103}, ++{127, 87, 107}, ++{140, 83, 112}, ++{154, 78, 118}, ++{168, 73, 124}, ++{183, 67, 129}, ++{198, 62, 134}, ++{205, 59, 136}, ++{120, 91, 104}, ++{129, 88, 108}, ++{142, 84, 113}, ++{155, 79, 119}, ++{170, 74, 124}, ++{185, 68, 129}, ++{199, 63, 134}, ++{206, 60, 137}, ++{123, 93, 105}, ++{132, 89, 108}, ++{144, 85, 114}, ++{157, 80, 119}, ++{171, 74, 125}, ++{186, 69, 130}, ++{200, 63, 135}, ++{208, 60, 137}, ++{126, 94, 106}, ++{134, 91, 109}, ++{146, 86, 114}, ++{159, 81, 120}, ++{173, 75, 125}, ++{187, 69, 130}, ++{202, 64, 135}, ++{209, 61, 137}, ++{129, 95, 107}, ++{137, 92, 110}, ++{148, 87, 115}, ++{161, 82, 120}, ++{175, 76, 125}, ++{189, 70, 130}, ++{203, 64, 135}, ++{210, 62, 137}, ++{132, 97, 108}, ++{139, 93, 111}, ++{151, 88, 116}, ++{163, 83, 121}, ++{177, 77, 126}, ++{191, 71, 131}, ++{205, 65, 135}, ++{212, 62, 137}, ++{135, 98, 109}, ++{142, 94, 112}, ++{153, 89, 116}, ++{166, 84, 121}, ++{179, 78, 126}, ++{193, 72, 131}, ++{207, 66, 135}, ++{213, 63, 138}, ++{138, 99, 110}, ++{145, 96, 113}, ++{156, 90, 117}, ++{168, 85, 122}, ++{181, 79, 127}, ++{195, 73, 131}, ++{208, 67, 136}, ++{215, 64, 138}, ++{141, 100, 111}, ++{148, 97, 114}, ++{158, 92, 118}, ++{170, 86, 122}, ++{183, 80, 127}, ++{197, 74, 132}, ++{210, 67, 136}, ++{217, 65, 138}, ++{144, 102, 112}, ++{151, 98, 114}, ++{161, 93, 118}, ++{173, 87, 123}, ++{186, 81, 127}, ++{199, 74, 132}, ++{212, 68, 136}, ++{219, 65, 138}, ++{148, 103, 113}, ++{154, 99, 115}, ++{164, 94, 119}, ++{176, 88, 123}, ++{188, 81, 128}, ++{201, 75, 132}, ++{214, 69, 137}, ++{221, 66, 139}, ++{151, 104, 114}, ++{158, 100, 116}, ++{167, 95, 120}, ++{178, 89, 124}, ++{190, 82, 128}, ++{203, 76, 133}, ++{216, 70, 137}, ++{223, 67, 139}, ++{154, 105, 114}, ++{161, 101, 117}, ++{170, 96, 121}, ++{181, 90, 125}, ++{193, 83, 129}, ++{205, 77, 133}, ++{218, 71, 137}, ++{225, 68, 139}, ++{158, 106, 115}, ++{164, 102, 118}, ++{173, 97, 121}, ++{184, 91, 125}, ++{196, 84, 129}, ++{208, 78, 133}, ++{220, 72, 138}, ++{227, 69, 140}, ++{161, 107, 116}, ++{167, 103, 119}, ++{176, 97, 122}, ++{187, 91, 126}, ++{198, 85, 130}, ++{210, 79, 134}, ++{223, 72, 138}, ++{229, 69, 140}, ++{165, 107, 117}, ++{171, 104, 120}, ++{179, 98, 123}, ++{190, 92, 126}, ++{201, 86, 130}, ++{213, 80, 134}, ++{225, 73, 138}, ++{231, 70, 140}, ++{169, 108, 118}, ++{174, 105, 120}, ++{183, 99, 123}, ++{193, 93, 127}, ++{204, 87, 131}, ++{215, 81, 135}, ++{227, 74, 138}, ++{233, 71, 140}, ++{172, 109, 119}, ++{178, 105, 121}, ++{186, 100, 124}, ++{196, 94, 128}, ++{206, 88, 131}, ++{218, 81, 135}, ++{230, 75, 139}, ++{236, 72, 141}, ++{176, 110, 120}, ++{181, 106, 122}, ++{189, 101, 125}, ++{199, 95, 128}, ++{209, 89, 132}, ++{220, 82, 135}, ++{232, 76, 139}, ++{238, 73, 141}, ++{179, 110, 121}, ++{185, 107, 123}, ++{192, 102, 125}, ++{202, 96, 129}, ++{212, 89, 132}, ++{223, 83, 136}, ++{235, 77, 140}, ++{241, 74, 141}, ++{181, 111, 121}, ++{186, 107, 123}, ++{194, 102, 126}, ++{203, 96, 129}, ++{214, 90, 133}, ++{225, 83, 136}, ++{236, 77, 140}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 107, 123}, ++{194, 102, 126}, ++{203, 96, 129}, ++{214, 90, 133}, ++{225, 83, 136}, ++{236, 77, 140}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 107, 123}, ++{194, 102, 126}, ++{203, 96, 129}, ++{214, 90, 133}, ++{225, 83, 136}, ++{236, 77, 140}, ++{242, 74, 141}, ++{181, 111, 121}, ++{186, 107, 123}, ++{194, 102, 126}, ++{203, 96, 129}, ++{214, 90, 133}, ++{225, 83, 136}, ++{236, 77, 140}, ++{242, 74, 141}, ++{110, 79, 96}, ++{120, 79, 101}, ++{134, 76, 108}, ++{149, 73, 114}, ++{164, 68, 120}, ++{179, 64, 126}, ++{195, 59, 131}, ++{202, 56, 134}, ++{110, 80, 96}, ++{120, 79, 101}, ++{134, 76, 108}, ++{149, 73, 114}, ++{164, 68, 120}, ++{180, 64, 126}, ++{195, 59, 131}, ++{202, 56, 134}, ++{111, 80, 96}, ++{121, 79, 101}, ++{135, 77, 108}, ++{149, 73, 114}, ++{165, 69, 120}, ++{180, 64, 126}, ++{195, 59, 131}, ++{202, 56, 134}, ++{112, 81, 97}, ++{122, 80, 102}, ++{135, 77, 108}, ++{150, 73, 114}, ++{165, 69, 120}, ++{180, 64, 126}, ++{195, 59, 131}, ++{203, 56, 134}, ++{113, 82, 97}, ++{123, 81, 102}, ++{136, 78, 108}, ++{151, 74, 115}, ++{166, 69, 121}, ++{181, 64, 126}, ++{196, 59, 131}, ++{203, 57, 134}, ++{115, 83, 98}, ++{124, 81, 103}, ++{137, 78, 109}, ++{152, 74, 115}, ++{167, 70, 121}, ++{182, 65, 126}, ++{197, 60, 132}, ++{204, 57, 134}, ++{116, 84, 99}, ++{126, 83, 103}, ++{139, 79, 109}, ++{153, 75, 115}, ++{168, 70, 121}, ++{183, 65, 127}, ++{197, 60, 132}, ++{205, 57, 134}, ++{118, 86, 99}, ++{128, 84, 104}, ++{140, 80, 110}, ++{154, 76, 116}, ++{169, 71, 121}, ++{184, 66, 127}, ++{198, 60, 132}, ++{206, 58, 134}, ++{121, 87, 100}, ++{130, 85, 105}, ++{142, 81, 110}, ++{156, 77, 116}, ++{170, 72, 122}, ++{185, 66, 127}, ++{199, 61, 132}, ++{207, 58, 135}, ++{123, 89, 101}, ++{132, 86, 105}, ++{144, 82, 111}, ++{157, 77, 116}, ++{172, 72, 122}, ++{186, 67, 127}, ++{201, 62, 132}, ++{208, 59, 135}, ++{126, 90, 102}, ++{134, 87, 106}, ++{146, 83, 111}, ++{159, 78, 117}, ++{173, 73, 122}, ++{188, 68, 128}, ++{202, 62, 133}, ++{209, 59, 135}, ++{128, 92, 103}, ++{136, 89, 107}, ++{148, 84, 112}, ++{161, 79, 117}, ++{175, 74, 123}, ++{189, 68, 128}, ++{203, 63, 133}, ++{210, 60, 135}, ++{131, 93, 104}, ++{139, 90, 108}, ++{150, 85, 113}, ++{163, 80, 118}, ++{177, 75, 123}, ++{191, 69, 128}, ++{205, 64, 133}, ++{212, 61, 135}, ++{134, 94, 105}, ++{142, 91, 109}, ++{153, 87, 113}, ++{165, 81, 119}, ++{179, 76, 124}, ++{192, 70, 129}, ++{206, 64, 133}, ++{213, 61, 136}, ++{137, 96, 106}, ++{144, 92, 110}, ++{155, 88, 114}, ++{167, 82, 119}, ++{181, 77, 124}, ++{194, 71, 129}, ++{208, 65, 134}, ++{215, 62, 136}, ++{140, 97, 107}, ++{147, 94, 111}, ++{158, 89, 115}, ++{170, 83, 120}, ++{183, 77, 125}, ++{196, 72, 129}, ++{210, 66, 134}, ++{217, 63, 136}, ++{143, 98, 108}, ++{150, 95, 111}, ++{160, 90, 116}, ++{172, 84, 120}, ++{185, 78, 125}, ++{198, 72, 130}, ++{212, 67, 134}, ++{218, 64, 136}, ++{146, 100, 109}, ++{153, 96, 112}, ++{163, 91, 116}, ++{175, 85, 121}, ++{187, 79, 125}, ++{200, 73, 130}, ++{213, 67, 134}, ++{220, 64, 137}, ++{150, 101, 110}, ++{156, 97, 113}, ++{166, 92, 117}, ++{177, 86, 121}, ++{190, 80, 126}, ++{202, 74, 130}, ++{215, 68, 135}, ++{222, 65, 137}, ++{153, 102, 111}, ++{159, 98, 114}, ++{169, 93, 118}, ++{180, 87, 122}, ++{192, 81, 126}, ++{205, 75, 131}, ++{217, 69, 135}, ++{224, 66, 137}, ++{156, 103, 112}, ++{163, 99, 115}, ++{172, 94, 119}, ++{183, 88, 123}, ++{194, 82, 127}, ++{207, 76, 131}, ++{220, 70, 135}, ++{226, 67, 137}, ++{160, 104, 113}, ++{166, 100, 116}, ++{175, 95, 119}, ++{185, 89, 123}, ++{197, 83, 127}, ++{209, 77, 132}, ++{222, 71, 136}, ++{228, 68, 138}, ++{163, 105, 114}, ++{169, 101, 117}, ++{178, 96, 120}, ++{188, 90, 124}, ++{200, 84, 128}, ++{212, 78, 132}, ++{224, 72, 136}, ++{230, 69, 138}, ++{167, 106, 115}, ++{173, 102, 118}, ++{181, 97, 121}, ++{191, 91, 125}, ++{202, 85, 128}, ++{214, 79, 132}, ++{226, 72, 136}, ++{232, 69, 138}, ++{170, 107, 116}, ++{176, 103, 118}, ++{184, 98, 121}, ++{194, 92, 125}, ++{205, 86, 129}, ++{217, 80, 133}, ++{229, 73, 137}, ++{235, 70, 139}, ++{174, 107, 117}, ++{179, 104, 119}, ++{187, 99, 122}, ++{197, 93, 126}, ++{208, 87, 129}, ++{219, 80, 133}, ++{231, 74, 137}, ++{237, 71, 139}, ++{177, 108, 118}, ++{183, 105, 120}, ++{191, 100, 123}, ++{200, 94, 126}, ++{211, 88, 130}, ++{222, 81, 134}, ++{233, 75, 137}, ++{239, 72, 139}, ++{181, 109, 119}, ++{186, 105, 121}, ++{194, 100, 124}, ++{203, 95, 127}, ++{213, 88, 131}, ++{224, 82, 134}, ++{236, 76, 138}, ++{242, 73, 140}, ++{183, 109, 119}, ++{188, 106, 121}, ++{195, 101, 124}, ++{205, 95, 127}, ++{215, 89, 131}, ++{226, 83, 134}, ++{237, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{188, 106, 121}, ++{195, 101, 124}, ++{205, 95, 127}, ++{215, 89, 131}, ++{226, 83, 134}, ++{237, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{188, 106, 121}, ++{195, 101, 124}, ++{205, 95, 127}, ++{215, 89, 131}, ++{226, 83, 134}, ++{237, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{188, 106, 121}, ++{195, 101, 124}, ++{205, 95, 127}, ++{215, 89, 131}, ++{226, 83, 134}, ++{237, 76, 138}, ++{243, 73, 140}, ++{113, 77, 94}, ++{123, 76, 99}, ++{136, 74, 105}, ++{151, 71, 112}, ++{166, 67, 118}, ++{181, 62, 124}, ++{196, 58, 129}, ++{204, 55, 132}, ++{113, 77, 94}, ++{123, 76, 99}, ++{136, 74, 105}, ++{151, 71, 112}, ++{166, 67, 118}, ++{181, 62, 124}, ++{196, 58, 129}, ++{204, 55, 132}, ++{114, 78, 94}, ++{124, 77, 99}, ++{137, 75, 105}, ++{151, 71, 112}, ++{167, 67, 118}, ++{182, 63, 124}, ++{197, 58, 129}, ++{204, 55, 132}, ++{115, 78, 95}, ++{124, 77, 99}, ++{138, 75, 106}, ++{152, 72, 112}, ++{167, 68, 118}, ++{182, 63, 124}, ++{197, 58, 129}, ++{204, 55, 132}, ++{116, 79, 95}, ++{125, 78, 100}, ++{138, 76, 106}, ++{153, 72, 112}, ++{168, 68, 118}, ++{183, 63, 124}, ++{198, 58, 129}, ++{205, 56, 132}, ++{117, 81, 96}, ++{127, 79, 100}, ++{140, 77, 106}, ++{154, 73, 113}, ++{169, 68, 119}, ++{183, 64, 124}, ++{198, 59, 130}, ++{206, 56, 132}, ++{119, 82, 96}, ++{128, 80, 101}, ++{141, 77, 107}, ++{155, 73, 113}, ++{170, 69, 119}, ++{184, 64, 124}, ++{199, 59, 130}, ++{206, 57, 132}, ++{121, 83, 97}, ++{130, 81, 102}, ++{142, 78, 107}, ++{156, 74, 113}, ++{171, 70, 119}, ++{185, 65, 125}, ++{200, 60, 130}, ++{207, 57, 132}, ++{123, 85, 98}, ++{132, 83, 102}, ++{144, 79, 108}, ++{158, 75, 114}, ++{172, 70, 120}, ++{187, 65, 125}, ++{201, 60, 130}, ++{208, 57, 133}, ++{126, 86, 99}, ++{134, 84, 103}, ++{146, 80, 109}, ++{159, 76, 114}, ++{174, 71, 120}, ++{188, 66, 125}, ++{202, 61, 130}, ++{209, 58, 133}, ++{128, 88, 100}, ++{136, 85, 104}, ++{148, 81, 109}, ++{161, 77, 115}, ++{175, 72, 120}, ++{189, 67, 126}, ++{203, 61, 131}, ++{211, 59, 133}, ++{131, 89, 101}, ++{139, 87, 105}, ++{150, 83, 110}, ++{163, 78, 115}, ++{177, 73, 121}, ++{191, 67, 126}, ++{205, 62, 131}, ++{212, 59, 133}, ++{133, 91, 102}, ++{141, 88, 106}, ++{152, 84, 111}, ++{165, 79, 116}, ++{179, 74, 121}, ++{192, 68, 126}, ++{206, 63, 131}, ++{213, 60, 133}, ++{136, 92, 103}, ++{144, 89, 107}, ++{155, 85, 111}, ++{167, 80, 116}, ++{180, 74, 122}, ++{194, 69, 127}, ++{208, 63, 131}, ++{215, 61, 134}, ++{139, 94, 104}, ++{147, 90, 107}, ++{157, 86, 112}, ++{169, 81, 117}, ++{182, 75, 122}, ++{196, 70, 127}, ++{209, 64, 132}, ++{216, 61, 134}, ++{142, 95, 105}, ++{149, 92, 108}, ++{160, 87, 113}, ++{172, 82, 118}, ++{184, 76, 122}, ++{198, 71, 127}, ++{211, 65, 132}, ++{218, 62, 134}, ++{145, 96, 106}, ++{152, 93, 109}, ++{162, 88, 113}, ++{174, 83, 118}, ++{187, 77, 123}, ++{200, 71, 128}, ++{213, 66, 132}, ++{220, 63, 134}, ++{149, 97, 107}, ++{155, 94, 110}, ++{165, 89, 114}, ++{177, 84, 119}, ++{189, 78, 123}, ++{202, 72, 128}, ++{215, 66, 133}, ++{221, 64, 135}, ++{152, 99, 108}, ++{158, 95, 111}, ++{168, 90, 115}, ++{179, 85, 119}, ++{191, 79, 124}, ++{204, 73, 128}, ++{217, 67, 133}, ++{223, 64, 135}, ++{155, 100, 109}, ++{161, 96, 112}, ++{171, 92, 116}, ++{182, 86, 120}, ++{194, 80, 124}, ++{206, 74, 129}, ++{219, 68, 133}, ++{225, 65, 135}, ++{158, 101, 110}, ++{165, 97, 113}, ++{174, 93, 117}, ++{184, 87, 121}, ++{196, 81, 125}, ++{208, 75, 129}, ++{221, 69, 134}, ++{227, 66, 136}, ++{162, 102, 111}, ++{168, 99, 114}, ++{177, 94, 117}, ++{187, 88, 121}, ++{199, 82, 126}, ++{211, 76, 130}, ++{223, 70, 134}, ++{229, 67, 136}, ++{165, 103, 112}, ++{171, 100, 115}, ++{180, 95, 118}, ++{190, 89, 122}, ++{201, 83, 126}, ++{213, 77, 130}, ++{225, 71, 134}, ++{232, 68, 136}, ++{169, 104, 113}, ++{174, 100, 116}, ++{183, 96, 119}, ++{193, 90, 123}, ++{204, 84, 127}, ++{216, 78, 131}, ++{228, 72, 135}, ++{234, 69, 137}, ++{172, 105, 114}, ++{178, 101, 116}, ++{186, 96, 120}, ++{196, 91, 123}, ++{207, 85, 127}, ++{218, 79, 131}, ++{230, 72, 135}, ++{236, 69, 137}, ++{176, 106, 115}, ++{181, 102, 117}, ++{189, 97, 120}, ++{199, 92, 124}, ++{209, 86, 128}, ++{221, 79, 132}, ++{232, 73, 135}, ++{238, 70, 137}, ++{179, 107, 116}, ++{184, 103, 118}, ++{192, 98, 121}, ++{202, 93, 124}, ++{212, 87, 128}, ++{223, 80, 132}, ++{235, 74, 136}, ++{241, 71, 138}, ++{183, 107, 117}, ++{188, 104, 119}, ++{195, 99, 122}, ++{205, 93, 125}, ++{215, 87, 129}, ++{226, 81, 132}, ++{237, 75, 136}, ++{243, 72, 138}, ++{185, 108, 117}, ++{190, 104, 119}, ++{197, 99, 122}, ++{206, 94, 125}, ++{216, 88, 129}, ++{227, 82, 133}, ++{238, 75, 136}, ++{244, 72, 138}, ++{185, 108, 117}, ++{190, 104, 119}, ++{197, 99, 122}, ++{206, 94, 125}, ++{216, 88, 129}, ++{227, 82, 133}, ++{238, 75, 136}, ++{244, 72, 138}, ++{185, 108, 117}, ++{190, 104, 119}, ++{197, 99, 122}, ++{206, 94, 125}, ++{216, 88, 129}, ++{227, 82, 133}, ++{238, 75, 136}, ++{244, 72, 138}, ++{185, 108, 117}, ++{190, 104, 119}, ++{197, 99, 122}, ++{206, 94, 125}, ++{216, 88, 129}, ++{227, 82, 133}, ++{238, 75, 136}, ++{244, 72, 138}, ++{116, 74, 92}, ++{125, 74, 97}, ++{139, 72, 103}, ++{153, 69, 109}, ++{168, 66, 116}, ++{183, 61, 122}, ++{198, 57, 127}, ++{205, 54, 130}, ++{116, 74, 92}, ++{126, 74, 97}, ++{139, 72, 103}, ++{153, 69, 110}, ++{168, 66, 116}, ++{183, 61, 122}, ++{198, 57, 127}, ++{205, 54, 130}, ++{117, 75, 92}, ++{126, 75, 97}, ++{139, 73, 103}, ++{154, 70, 110}, ++{168, 66, 116}, ++{183, 61, 122}, ++{198, 57, 127}, ++{206, 54, 130}, ++{118, 76, 92}, ++{127, 75, 97}, ++{140, 73, 103}, ++{154, 70, 110}, ++{169, 66, 116}, ++{184, 62, 122}, ++{199, 57, 127}, ++{206, 55, 130}, ++{119, 77, 93}, ++{128, 76, 98}, ++{141, 74, 104}, ++{155, 71, 110}, ++{170, 67, 116}, ++{184, 62, 122}, ++{199, 57, 127}, ++{206, 55, 130}, ++{120, 78, 94}, ++{129, 77, 98}, ++{142, 75, 104}, ++{156, 71, 110}, ++{171, 67, 116}, ++{185, 62, 122}, ++{200, 58, 128}, ++{207, 55, 130}, ++{122, 79, 94}, ++{131, 78, 99}, ++{143, 75, 105}, ++{157, 72, 111}, ++{172, 68, 117}, ++{186, 63, 122}, ++{201, 58, 128}, ++{208, 56, 130}, ++{124, 81, 95}, ++{133, 79, 99}, ++{145, 76, 105}, ++{158, 73, 111}, ++{173, 68, 117}, ++{187, 63, 123}, ++{202, 59, 128}, ++{209, 56, 130}, ++{126, 82, 96}, ++{134, 80, 100}, ++{146, 77, 106}, ++{160, 73, 112}, ++{174, 69, 117}, ++{188, 64, 123}, ++{203, 59, 128}, ++{210, 57, 131}, ++{128, 84, 97}, ++{136, 82, 101}, ++{148, 78, 106}, ++{161, 74, 112}, ++{175, 70, 118}, ++{190, 65, 123}, ++{204, 60, 128}, ++{211, 57, 131}, ++{131, 85, 98}, ++{139, 83, 102}, ++{150, 80, 107}, ++{163, 75, 113}, ++{177, 70, 118}, ++{191, 65, 123}, ++{205, 60, 129}, ++{212, 58, 131}, ++{133, 87, 99}, ++{141, 84, 103}, ++{152, 81, 108}, ++{165, 76, 113}, ++{179, 71, 119}, ++{192, 66, 124}, ++{206, 61, 129}, ++{213, 58, 131}, ++{136, 88, 100}, ++{143, 86, 103}, ++{154, 82, 108}, ++{167, 77, 114}, ++{180, 72, 119}, ++{194, 67, 124}, ++{208, 62, 129}, ++{215, 59, 131}, ++{139, 90, 101}, ++{146, 87, 104}, ++{157, 83, 109}, ++{169, 78, 114}, ++{182, 73, 119}, ++{196, 68, 124}, ++{209, 62, 129}, ++{216, 60, 132}, ++{142, 91, 102}, ++{149, 88, 105}, ++{159, 84, 110}, ++{171, 79, 115}, ++{184, 74, 120}, ++{197, 69, 125}, ++{211, 63, 130}, ++{218, 60, 132}, ++{145, 93, 103}, ++{152, 90, 106}, ++{162, 85, 111}, ++{174, 80, 115}, ++{186, 75, 120}, ++{199, 69, 125}, ++{213, 64, 130}, ++{219, 61, 132}, ++{148, 94, 104}, ++{154, 91, 107}, ++{164, 87, 111}, ++{176, 81, 116}, ++{188, 76, 121}, ++{201, 70, 126}, ++{214, 65, 130}, ++{221, 62, 133}, ++{151, 95, 105}, ++{157, 92, 108}, ++{167, 88, 112}, ++{178, 82, 117}, ++{191, 77, 121}, ++{203, 71, 126}, ++{216, 66, 131}, ++{223, 63, 133}, ++{154, 97, 106}, ++{160, 93, 109}, ++{170, 89, 113}, ++{181, 83, 117}, ++{193, 78, 122}, ++{205, 72, 127}, ++{218, 66, 131}, ++{225, 64, 133}, ++{157, 98, 107}, ++{163, 95, 110}, ++{173, 90, 114}, ++{183, 85, 118}, ++{195, 79, 122}, ++{208, 73, 127}, ++{220, 67, 131}, ++{227, 64, 134}, ++{160, 99, 108}, ++{167, 96, 111}, ++{175, 91, 114}, ++{186, 86, 119}, ++{198, 80, 123}, ++{210, 74, 127}, ++{222, 68, 132}, ++{229, 65, 134}, ++{164, 100, 109}, ++{170, 97, 112}, ++{178, 92, 115}, ++{189, 87, 119}, ++{200, 81, 124}, ++{212, 75, 128}, ++{225, 69, 132}, ++{231, 66, 134}, ++{167, 101, 110}, ++{173, 98, 113}, ++{181, 93, 116}, ++{192, 88, 120}, ++{203, 82, 124}, ++{215, 76, 128}, ++{227, 70, 132}, ++{233, 67, 135}, ++{171, 102, 111}, ++{176, 99, 114}, ++{184, 94, 117}, ++{194, 89, 121}, ++{205, 83, 125}, ++{217, 77, 129}, ++{229, 71, 133}, ++{235, 68, 135}, ++{174, 103, 112}, ++{179, 100, 114}, ++{188, 95, 118}, ++{197, 89, 121}, ++{208, 84, 125}, ++{219, 78, 129}, ++{231, 72, 133}, ++{237, 69, 135}, ++{177, 104, 113}, ++{183, 101, 115}, ++{191, 96, 118}, ++{200, 90, 122}, ++{211, 84, 126}, ++{222, 78, 130}, ++{234, 72, 134}, ++{240, 69, 136}, ++{181, 105, 114}, ++{186, 102, 116}, ++{194, 97, 119}, ++{203, 91, 123}, ++{214, 85, 126}, ++{225, 79, 130}, ++{236, 73, 134}, ++{242, 70, 136}, ++{184, 106, 115}, ++{189, 102, 117}, ++{197, 98, 120}, ++{206, 92, 123}, ++{216, 86, 127}, ++{227, 80, 131}, ++{239, 74, 134}, ++{244, 71, 136}, ++{186, 106, 116}, ++{191, 103, 117}, ++{199, 98, 120}, ++{208, 93, 124}, ++{218, 87, 127}, ++{229, 81, 131}, ++{240, 75, 135}, ++{245, 72, 137}, ++{186, 106, 116}, ++{191, 103, 117}, ++{199, 98, 120}, ++{208, 93, 124}, ++{218, 87, 127}, ++{229, 81, 131}, ++{240, 75, 135}, ++{245, 72, 137}, ++{186, 106, 116}, ++{191, 103, 117}, ++{199, 98, 120}, ++{208, 93, 124}, ++{218, 87, 127}, ++{229, 81, 131}, ++{240, 75, 135}, ++{245, 72, 137}, ++{186, 106, 116}, ++{191, 103, 117}, ++{199, 98, 120}, ++{208, 93, 124}, ++{218, 87, 127}, ++{229, 81, 131}, ++{240, 75, 135}, ++{245, 72, 137}, ++{119, 72, 89}, ++{128, 72, 94}, ++{141, 70, 101}, ++{155, 68, 107}, ++{170, 64, 114}, ++{185, 60, 119}, ++{200, 55, 125}, ++{207, 53, 128}, ++{119, 72, 90}, ++{128, 72, 94}, ++{141, 70, 101}, ++{155, 68, 107}, ++{170, 64, 114}, ++{185, 60, 120}, ++{200, 56, 125}, ++{207, 53, 128}, ++{120, 72, 90}, ++{129, 72, 95}, ++{142, 71, 101}, ++{156, 68, 107}, ++{170, 64, 114}, ++{185, 60, 120}, ++{200, 56, 125}, ++{207, 53, 128}, ++{120, 73, 90}, ++{130, 73, 95}, ++{142, 71, 101}, ++{156, 68, 108}, ++{171, 65, 114}, ++{186, 60, 120}, ++{200, 56, 125}, ++{208, 54, 128}, ++{122, 74, 91}, ++{131, 74, 95}, ++{143, 72, 102}, ++{157, 69, 108}, ++{172, 65, 114}, ++{186, 61, 120}, ++{201, 56, 125}, ++{208, 54, 128}, ++{123, 75, 91}, ++{132, 75, 96}, ++{144, 73, 102}, ++{158, 70, 108}, ++{172, 66, 114}, ++{187, 61, 120}, ++{202, 57, 125}, ++{209, 54, 128}, ++{125, 77, 92}, ++{133, 76, 97}, ++{146, 73, 102}, ++{159, 70, 109}, ++{173, 66, 115}, ++{188, 62, 120}, ++{202, 57, 126}, ++{209, 55, 128}, ++{126, 78, 93}, ++{135, 77, 97}, ++{147, 74, 103}, ++{160, 71, 109}, ++{175, 67, 115}, ++{189, 62, 120}, ++{203, 57, 126}, ++{210, 55, 128}, ++{129, 80, 94}, ++{137, 78, 98}, ++{149, 75, 104}, ++{162, 72, 109}, ++{176, 68, 115}, ++{190, 63, 121}, ++{204, 58, 126}, ++{211, 56, 129}, ++{131, 81, 95}, ++{139, 80, 99}, ++{150, 77, 104}, ++{163, 73, 110}, ++{177, 68, 116}, ++{191, 64, 121}, ++{205, 59, 126}, ++{212, 56, 129}, ++{133, 83, 96}, ++{141, 81, 100}, ++{152, 78, 105}, ++{165, 74, 110}, ++{179, 69, 116}, ++{193, 64, 121}, ++{207, 59, 127}, ++{214, 57, 129}, ++{136, 84, 97}, ++{143, 82, 100}, ++{154, 79, 105}, ++{167, 75, 111}, ++{180, 70, 116}, ++{194, 65, 122}, ++{208, 60, 127}, ++{215, 57, 129}, ++{138, 86, 98}, ++{146, 84, 101}, ++{157, 80, 106}, ++{169, 76, 112}, ++{182, 71, 117}, ++{196, 66, 122}, ++{209, 61, 127}, ++{216, 58, 129}, ++{141, 88, 99}, ++{148, 85, 102}, ++{159, 81, 107}, ++{171, 77, 112}, ++{184, 72, 117}, ++{197, 67, 122}, ++{211, 61, 127}, ++{218, 59, 130}, ++{144, 89, 100}, ++{151, 86, 103}, ++{161, 82, 108}, ++{173, 78, 113}, ++{186, 73, 118}, ++{199, 67, 123}, ++{213, 62, 128}, ++{219, 59, 130}, ++{147, 90, 101}, ++{154, 88, 104}, ++{164, 84, 108}, ++{175, 79, 113}, ++{188, 74, 118}, ++{201, 68, 123}, ++{214, 63, 128}, ++{221, 60, 130}, ++{150, 92, 102}, ++{157, 89, 105}, ++{166, 85, 109}, ++{178, 80, 114}, ++{190, 75, 119}, ++{203, 69, 124}, ++{216, 64, 128}, ++{223, 61, 131}, ++{153, 93, 103}, ++{159, 90, 106}, ++{169, 86, 110}, ++{180, 81, 115}, ++{192, 76, 119}, ++{205, 70, 124}, ++{218, 65, 129}, ++{224, 62, 131}, ++{156, 95, 104}, ++{162, 92, 107}, ++{172, 87, 111}, ++{183, 82, 115}, ++{195, 77, 120}, ++{207, 71, 125}, ++{220, 65, 129}, ++{226, 63, 131}, ++{159, 96, 105}, ++{165, 93, 108}, ++{174, 88, 112}, ++{185, 83, 116}, ++{197, 78, 121}, ++{209, 72, 125}, ++{222, 66, 129}, ++{228, 63, 132}, ++{162, 97, 106}, ++{168, 94, 109}, ++{177, 89, 112}, ++{188, 84, 117}, ++{199, 79, 121}, ++{211, 73, 126}, ++{224, 67, 130}, ++{230, 64, 132}, ++{166, 98, 107}, ++{172, 95, 110}, ++{180, 90, 113}, ++{191, 85, 117}, ++{202, 80, 122}, ++{214, 74, 126}, ++{226, 68, 130}, ++{232, 65, 132}, ++{169, 99, 108}, ++{175, 96, 111}, ++{183, 91, 114}, ++{193, 86, 118}, ++{204, 80, 122}, ++{216, 75, 126}, ++{228, 69, 131}, ++{234, 66, 133}, ++{172, 100, 109}, ++{178, 97, 112}, ++{186, 92, 115}, ++{196, 87, 119}, ++{207, 81, 123}, ++{218, 76, 127}, ++{230, 70, 131}, ++{236, 67, 133}, ++{176, 101, 110}, ++{181, 98, 112}, ++{189, 93, 116}, ++{199, 88, 119}, ++{210, 82, 123}, ++{221, 77, 127}, ++{233, 71, 131}, ++{239, 68, 133}, ++{179, 102, 111}, ++{185, 99, 113}, ++{192, 94, 116}, ++{202, 89, 120}, ++{212, 83, 124}, ++{223, 77, 128}, ++{235, 71, 132}, ++{241, 69, 134}, ++{183, 103, 112}, ++{188, 100, 114}, ++{196, 95, 117}, ++{205, 90, 121}, ++{215, 84, 125}, ++{226, 78, 128}, ++{237, 72, 132}, ++{243, 69, 134}, ++{186, 104, 113}, ++{191, 101, 115}, ++{199, 96, 118}, ++{208, 91, 121}, ++{218, 85, 125}, ++{229, 79, 129}, ++{240, 73, 133}, ++{246, 70, 135}, ++{188, 105, 114}, ++{193, 101, 116}, ++{200, 97, 118}, ++{209, 91, 122}, ++{219, 86, 125}, ++{230, 80, 129}, ++{241, 74, 133}, ++{247, 71, 135}, ++{188, 105, 114}, ++{193, 101, 116}, ++{200, 97, 118}, ++{209, 91, 122}, ++{219, 86, 125}, ++{230, 80, 129}, ++{241, 74, 133}, ++{247, 71, 135}, ++{188, 105, 114}, ++{193, 101, 116}, ++{200, 97, 118}, ++{209, 91, 122}, ++{219, 86, 125}, ++{230, 80, 129}, ++{241, 74, 133}, ++{247, 71, 135}, ++{188, 105, 114}, ++{193, 101, 116}, ++{200, 97, 118}, ++{209, 91, 122}, ++{219, 86, 125}, ++{230, 80, 129}, ++{241, 74, 133}, ++{247, 71, 135}, ++{122, 69, 87}, ++{131, 69, 92}, ++{143, 68, 99}, ++{157, 66, 105}, ++{172, 63, 111}, ++{187, 59, 117}, ++{201, 54, 123}, ++{208, 52, 126}, ++{122, 69, 88}, ++{131, 70, 92}, ++{144, 68, 99}, ++{158, 66, 105}, ++{172, 63, 111}, ++{187, 59, 117}, ++{201, 54, 123}, ++{209, 52, 126}, ++{122, 70, 88}, ++{131, 70, 93}, ++{144, 69, 99}, ++{158, 66, 105}, ++{172, 63, 112}, ++{187, 59, 117}, ++{202, 55, 123}, ++{209, 52, 126}, ++{123, 71, 88}, ++{132, 71, 93}, ++{145, 69, 99}, ++{158, 67, 105}, ++{173, 63, 112}, ++{187, 59, 118}, ++{202, 55, 123}, ++{209, 53, 126}, ++{124, 72, 89}, ++{133, 71, 93}, ++{146, 70, 99}, ++{159, 67, 106}, ++{174, 64, 112}, ++{188, 60, 118}, ++{202, 55, 123}, ++{210, 53, 126}, ++{126, 73, 89}, ++{134, 72, 94}, ++{147, 71, 100}, ++{160, 68, 106}, ++{174, 64, 112}, ++{189, 60, 118}, ++{203, 55, 123}, ++{210, 53, 126}, ++{127, 74, 90}, ++{136, 73, 94}, ++{148, 72, 100}, ++{161, 69, 106}, ++{175, 65, 112}, ++{190, 60, 118}, ++{204, 56, 124}, ++{211, 54, 126}, ++{129, 76, 91}, ++{138, 75, 95}, ++{149, 72, 101}, ++{163, 69, 107}, ++{177, 65, 113}, ++{191, 61, 118}, ++{205, 56, 124}, ++{212, 54, 126}, ++{131, 77, 92}, ++{139, 76, 96}, ++{151, 74, 101}, ++{164, 70, 107}, ++{178, 66, 113}, ++{192, 62, 119}, ++{206, 57, 124}, ++{213, 55, 127}, ++{133, 79, 93}, ++{141, 77, 97}, ++{153, 75, 102}, ++{166, 71, 108}, ++{179, 67, 113}, ++{193, 62, 119}, ++{207, 58, 124}, ++{214, 55, 127}, ++{136, 80, 94}, ++{143, 79, 97}, ++{155, 76, 103}, ++{167, 72, 108}, ++{181, 68, 114}, ++{194, 63, 119}, ++{208, 58, 125}, ++{215, 56, 127}, ++{138, 82, 95}, ++{146, 80, 98}, ++{157, 77, 103}, ++{169, 73, 109}, ++{182, 69, 114}, ++{196, 64, 120}, ++{210, 59, 125}, ++{216, 56, 127}, ++{141, 84, 96}, ++{148, 81, 99}, ++{159, 78, 104}, ++{171, 74, 109}, ++{184, 69, 115}, ++{197, 65, 120}, ++{211, 60, 125}, ++{218, 57, 128}, ++{143, 85, 97}, ++{151, 83, 100}, ++{161, 79, 105}, ++{173, 75, 110}, ++{186, 70, 115}, ++{199, 65, 120}, ++{213, 60, 125}, ++{219, 58, 128}, ++{146, 87, 98}, ++{153, 84, 101}, ++{163, 81, 106}, ++{175, 76, 111}, ++{188, 71, 116}, ++{201, 66, 121}, ++{214, 61, 126}, ++{221, 58, 128}, ++{149, 88, 99}, ++{156, 86, 102}, ++{166, 82, 106}, ++{177, 77, 111}, ++{190, 72, 116}, ++{203, 67, 121}, ++{216, 62, 126}, ++{222, 59, 128}, ++{152, 90, 100}, ++{159, 87, 103}, ++{168, 83, 107}, ++{180, 78, 112}, ++{192, 73, 117}, ++{205, 68, 122}, ++{218, 63, 126}, ++{224, 60, 129}, ++{155, 91, 101}, ++{162, 88, 104}, ++{171, 84, 108}, ++{182, 79, 113}, ++{194, 74, 117}, ++{207, 69, 122}, ++{219, 64, 127}, ++{226, 61, 129}, ++{158, 92, 102}, ++{164, 90, 105}, ++{174, 85, 109}, ++{184, 81, 113}, ++{196, 75, 118}, ++{209, 70, 123}, ++{221, 64, 127}, ++{228, 62, 129}, ++{161, 94, 103}, ++{167, 91, 106}, ++{176, 87, 110}, ++{187, 82, 114}, ++{199, 76, 119}, ++{211, 71, 123}, ++{223, 65, 128}, ++{230, 62, 130}, ++{165, 95, 104}, ++{170, 92, 107}, ++{179, 88, 110}, ++{190, 83, 115}, ++{201, 77, 119}, ++{213, 72, 124}, ++{225, 66, 128}, ++{232, 63, 130}, ++{168, 96, 105}, ++{174, 93, 108}, ++{182, 89, 111}, ++{192, 84, 115}, ++{203, 78, 120}, ++{215, 73, 124}, ++{227, 67, 128}, ++{234, 64, 131}, ++{171, 97, 106}, ++{177, 94, 109}, ++{185, 90, 112}, ++{195, 85, 116}, ++{206, 79, 120}, ++{218, 74, 125}, ++{230, 68, 129}, ++{236, 65, 131}, ++{174, 98, 107}, ++{180, 95, 110}, ++{188, 91, 113}, ++{198, 86, 117}, ++{209, 80, 121}, ++{220, 74, 125}, ++{232, 69, 129}, ++{238, 66, 131}, ++{178, 100, 108}, ++{183, 96, 111}, ++{191, 92, 114}, ++{201, 87, 117}, ++{211, 81, 121}, ++{222, 75, 126}, ++{234, 70, 130}, ++{240, 67, 132}, ++{181, 101, 109}, ++{186, 97, 111}, ++{194, 93, 115}, ++{203, 88, 118}, ++{214, 82, 122}, ++{225, 76, 126}, ++{236, 71, 130}, ++{242, 68, 132}, ++{185, 101, 110}, ++{190, 98, 112}, ++{197, 94, 115}, ++{206, 89, 119}, ++{217, 83, 123}, ++{227, 77, 127}, ++{239, 71, 131}, ++{245, 68, 132}, ++{188, 102, 111}, ++{193, 99, 113}, ++{200, 95, 116}, ++{209, 90, 120}, ++{219, 84, 123}, ++{230, 78, 127}, ++{241, 72, 131}, ++{247, 69, 133}, ++{190, 103, 112}, ++{195, 100, 114}, ++{202, 95, 117}, ++{211, 90, 120}, ++{221, 84, 124}, ++{231, 79, 127}, ++{242, 73, 131}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 100, 114}, ++{202, 95, 117}, ++{211, 90, 120}, ++{221, 84, 124}, ++{231, 79, 127}, ++{242, 73, 131}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 100, 114}, ++{202, 95, 117}, ++{211, 90, 120}, ++{221, 84, 124}, ++{231, 79, 127}, ++{242, 73, 131}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 100, 114}, ++{202, 95, 117}, ++{211, 90, 120}, ++{221, 84, 124}, ++{231, 79, 127}, ++{242, 73, 131}, ++{248, 70, 133}, ++{124, 67, 85}, ++{133, 67, 90}, ++{146, 66, 96}, ++{160, 64, 103}, ++{174, 61, 109}, ++{188, 57, 115}, ++{203, 53, 121}, ++{210, 51, 124}, ++{125, 67, 85}, ++{134, 67, 90}, ++{146, 66, 96}, ++{160, 64, 103}, ++{174, 61, 109}, ++{189, 57, 115}, ++{203, 53, 121}, ++{210, 51, 124}, ++{125, 67, 86}, ++{134, 68, 90}, ++{146, 67, 97}, ++{160, 65, 103}, ++{174, 61, 109}, ++{189, 58, 115}, ++{203, 53, 121}, ++{210, 51, 124}, ++{126, 68, 86}, ++{135, 68, 91}, ++{147, 67, 97}, ++{161, 65, 103}, ++{175, 62, 110}, ++{189, 58, 115}, ++{204, 54, 121}, ++{211, 52, 124}, ++{127, 69, 87}, ++{136, 69, 91}, ++{148, 68, 97}, ++{161, 65, 104}, ++{176, 62, 110}, ++{190, 58, 116}, ++{204, 54, 121}, ++{211, 52, 124}, ++{129, 70, 87}, ++{137, 70, 92}, ++{149, 69, 98}, ++{162, 66, 104}, ++{176, 63, 110}, ++{191, 59, 116}, ++{205, 54, 121}, ++{212, 52, 124}, ++{130, 72, 88}, ++{138, 71, 92}, ++{150, 70, 98}, ++{163, 67, 104}, ++{177, 63, 110}, ++{191, 59, 116}, ++{206, 55, 122}, ++{213, 53, 124}, ++{132, 73, 89}, ++{140, 72, 93}, ++{152, 70, 99}, ++{165, 68, 105}, ++{178, 64, 111}, ++{192, 60, 116}, ++{207, 55, 122}, ++{214, 53, 124}, ++{134, 75, 90}, ++{142, 74, 94}, ++{153, 72, 99}, ++{166, 68, 105}, ++{180, 65, 111}, ++{194, 60, 117}, ++{208, 56, 122}, ++{215, 54, 125}, ++{136, 76, 91}, ++{144, 75, 95}, ++{155, 73, 100}, ++{168, 69, 106}, ++{181, 65, 111}, ++{195, 61, 117}, ++{209, 56, 122}, ++{216, 54, 125}, ++{138, 78, 92}, ++{146, 76, 95}, ++{157, 74, 101}, ++{169, 70, 106}, ++{183, 66, 112}, ++{196, 62, 117}, ++{210, 57, 123}, ++{217, 55, 125}, ++{141, 80, 93}, ++{148, 78, 96}, ++{159, 75, 101}, ++{171, 71, 107}, ++{184, 67, 112}, ++{198, 63, 118}, ++{211, 58, 123}, ++{218, 55, 125}, ++{143, 81, 94}, ++{150, 79, 97}, ++{161, 76, 102}, ++{173, 72, 107}, ++{186, 68, 113}, ++{199, 63, 118}, ++{213, 58, 123}, ++{219, 56, 126}, ++{146, 83, 95}, ++{153, 81, 98}, ++{163, 77, 103}, ++{175, 73, 108}, ++{188, 69, 113}, ++{201, 64, 118}, ++{214, 59, 123}, ++{221, 57, 126}, ++{149, 84, 96}, ++{155, 82, 99}, ++{165, 79, 104}, ++{177, 75, 109}, ++{190, 70, 114}, ++{203, 65, 119}, ++{216, 60, 124}, ++{222, 57, 126}, ++{151, 86, 97}, ++{158, 84, 100}, ++{168, 80, 104}, ++{179, 76, 109}, ++{192, 71, 114}, ++{204, 66, 119}, ++{217, 61, 124}, ++{224, 58, 127}, ++{154, 87, 98}, ++{161, 85, 101}, ++{170, 81, 105}, ++{182, 77, 110}, ++{194, 72, 115}, ++{206, 67, 120}, ++{219, 62, 125}, ++{226, 59, 127}, ++{157, 89, 99}, ++{164, 86, 102}, ++{173, 82, 106}, ++{184, 78, 111}, ++{196, 73, 115}, ++{208, 68, 120}, ++{221, 62, 125}, ++{227, 60, 127}, ++{160, 90, 100}, ++{167, 88, 103}, ++{176, 84, 107}, ++{186, 79, 111}, ++{198, 74, 116}, ++{210, 69, 121}, ++{223, 63, 125}, ++{229, 61, 128}, ++{163, 92, 101}, ++{169, 89, 104}, ++{178, 85, 108}, ++{189, 80, 112}, ++{200, 75, 117}, ++{212, 70, 121}, ++{225, 64, 126}, ++{231, 61, 128}, ++{167, 93, 102}, ++{172, 90, 105}, ++{181, 86, 108}, ++{191, 81, 113}, ++{203, 76, 117}, ++{215, 71, 122}, ++{227, 65, 126}, ++{233, 62, 128}, ++{170, 94, 103}, ++{175, 91, 106}, ++{184, 87, 109}, ++{194, 82, 113}, ++{205, 77, 118}, ++{217, 71, 122}, ++{229, 66, 127}, ++{235, 63, 129}, ++{173, 95, 104}, ++{179, 92, 107}, ++{187, 88, 110}, ++{197, 83, 114}, ++{208, 78, 118}, ++{219, 72, 123}, ++{231, 67, 127}, ++{237, 64, 129}, ++{176, 97, 105}, ++{182, 94, 108}, ++{190, 89, 111}, ++{199, 84, 115}, ++{210, 79, 119}, ++{221, 73, 123}, ++{233, 68, 127}, ++{239, 65, 130}, ++{180, 98, 106}, ++{185, 95, 109}, ++{193, 90, 112}, ++{202, 85, 116}, ++{213, 80, 120}, ++{224, 74, 124}, ++{236, 69, 128}, ++{241, 66, 130}, ++{183, 99, 107}, ++{188, 96, 110}, ++{196, 91, 113}, ++{205, 86, 116}, ++{215, 81, 120}, ++{226, 75, 124}, ++{238, 70, 128}, ++{244, 67, 130}, ++{186, 100, 108}, ++{191, 97, 110}, ++{199, 92, 113}, ++{208, 87, 117}, ++{218, 82, 121}, ++{229, 76, 125}, ++{240, 70, 129}, ++{246, 68, 131}, ++{190, 101, 109}, ++{195, 98, 111}, ++{202, 93, 114}, ++{211, 88, 118}, ++{221, 83, 121}, ++{231, 77, 125}, ++{243, 71, 129}, ++{248, 68, 131}, ++{191, 101, 110}, ++{196, 98, 112}, ++{204, 94, 115}, ++{212, 89, 118}, ++{222, 83, 122}, ++{233, 78, 126}, ++{244, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 98, 112}, ++{204, 94, 115}, ++{212, 89, 118}, ++{222, 83, 122}, ++{233, 78, 126}, ++{244, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 98, 112}, ++{204, 94, 115}, ++{212, 89, 118}, ++{222, 83, 122}, ++{233, 78, 126}, ++{244, 72, 129}, ++{249, 69, 131}, ++{191, 101, 110}, ++{196, 98, 112}, ++{204, 94, 115}, ++{212, 89, 118}, ++{222, 83, 122}, ++{233, 78, 126}, ++{244, 72, 129}, ++{249, 69, 131}, ++{127, 64, 83}, ++{136, 65, 88}, ++{148, 64, 94}, ++{162, 62, 101}, ++{176, 60, 107}, ++{190, 56, 113}, ++{205, 52, 119}, ++{212, 50, 122}, ++{128, 64, 84}, ++{136, 65, 88}, ++{148, 64, 94}, ++{162, 63, 101}, ++{176, 60, 107}, ++{190, 56, 113}, ++{205, 52, 119}, ++{212, 50, 122}, ++{128, 65, 84}, ++{137, 65, 88}, ++{149, 65, 95}, ++{162, 63, 101}, ++{176, 60, 107}, ++{191, 56, 113}, ++{205, 52, 119}, ++{212, 50, 122}, ++{129, 66, 84}, ++{137, 66, 89}, ++{149, 65, 95}, ++{163, 63, 101}, ++{177, 60, 107}, ++{191, 57, 113}, ++{205, 53, 119}, ++{212, 50, 122}, ++{130, 67, 85}, ++{138, 67, 89}, ++{150, 66, 95}, ++{164, 64, 101}, ++{178, 61, 108}, ++{192, 57, 114}, ++{206, 53, 119}, ++{213, 51, 122}, ++{131, 68, 85}, ++{140, 68, 90}, ++{151, 67, 96}, ++{164, 64, 102}, ++{178, 61, 108}, ++{192, 57, 114}, ++{207, 53, 119}, ++{214, 51, 122}, ++{133, 69, 86}, ++{141, 69, 90}, ++{153, 67, 96}, ++{166, 65, 102}, ++{179, 62, 108}, ++{193, 58, 114}, ++{207, 54, 120}, ++{214, 51, 122}, ++{135, 71, 87}, ++{143, 70, 91}, ++{154, 68, 97}, ++{167, 66, 103}, ++{180, 62, 109}, ++{194, 58, 114}, ++{208, 54, 120}, ++{215, 52, 122}, ++{136, 72, 88}, ++{144, 71, 92}, ++{155, 70, 97}, ++{168, 67, 103}, ++{182, 63, 109}, ++{195, 59, 115}, ++{209, 55, 120}, ++{216, 52, 123}, ++{139, 74, 89}, ++{146, 73, 92}, ++{157, 71, 98}, ++{170, 68, 104}, ++{183, 64, 109}, ++{197, 60, 115}, ++{210, 55, 120}, ++{217, 53, 123}, ++{141, 76, 90}, ++{148, 74, 93}, ++{159, 72, 98}, ++{171, 69, 104}, ++{184, 65, 110}, ++{198, 60, 115}, ++{212, 56, 121}, ++{218, 54, 123}, ++{143, 77, 91}, ++{150, 76, 94}, ++{161, 73, 99}, ++{173, 70, 105}, ++{186, 66, 110}, ++{199, 61, 116}, ++{213, 57, 121}, ++{220, 54, 123}, ++{146, 79, 92}, ++{153, 77, 95}, ++{163, 74, 100}, ++{175, 71, 105}, ++{188, 67, 111}, ++{201, 62, 116}, ++{214, 57, 121}, ++{221, 55, 124}, ++{148, 81, 93}, ++{155, 79, 96}, ++{165, 76, 101}, ++{177, 72, 106}, ++{189, 67, 111}, ++{202, 63, 116}, ++{216, 58, 122}, ++{222, 56, 124}, ++{151, 82, 94}, ++{158, 80, 97}, ++{168, 77, 101}, ++{179, 73, 107}, ++{191, 68, 112}, ++{204, 64, 117}, ++{217, 59, 122}, ++{224, 56, 124}, ++{154, 84, 95}, ++{160, 81, 98}, ++{170, 78, 102}, ++{181, 74, 107}, ++{193, 69, 112}, ++{206, 65, 117}, ++{219, 60, 122}, ++{225, 57, 125}, ++{157, 85, 96}, ++{163, 83, 99}, ++{172, 79, 103}, ++{183, 75, 108}, ++{195, 70, 113}, ++{208, 66, 118}, ++{221, 61, 123}, ++{227, 58, 125}, ++{159, 87, 97}, ++{166, 84, 100}, ++{175, 81, 104}, ++{186, 76, 109}, ++{198, 71, 113}, ++{210, 66, 118}, ++{222, 61, 123}, ++{229, 59, 125}, ++{163, 88, 98}, ++{169, 86, 101}, ++{178, 82, 105}, ++{188, 77, 109}, ++{200, 73, 114}, ++{212, 67, 119}, ++{224, 62, 123}, ++{231, 60, 126}, ++{166, 90, 99}, ++{171, 87, 102}, ++{180, 83, 106}, ++{191, 79, 110}, ++{202, 74, 115}, ++{214, 68, 119}, ++{226, 63, 124}, ++{233, 60, 126}, ++{169, 91, 100}, ++{174, 88, 103}, ++{183, 84, 106}, ++{193, 80, 111}, ++{204, 75, 115}, ++{216, 69, 120}, ++{228, 64, 124}, ++{234, 61, 127}, ++{172, 92, 101}, ++{177, 89, 104}, ++{186, 85, 107}, ++{196, 81, 111}, ++{207, 76, 116}, ++{218, 70, 120}, ++{230, 65, 125}, ++{236, 62, 127}, ++{175, 93, 102}, ++{181, 91, 105}, ++{189, 87, 108}, ++{198, 82, 112}, ++{209, 77, 116}, ++{221, 71, 121}, ++{233, 66, 125}, ++{239, 63, 127}, ++{178, 95, 103}, ++{184, 92, 106}, ++{192, 88, 109}, ++{201, 83, 113}, ++{212, 78, 117}, ++{223, 72, 121}, ++{235, 67, 126}, ++{241, 64, 128}, ++{182, 96, 104}, ++{187, 93, 107}, ++{195, 89, 110}, ++{204, 84, 114}, ++{214, 79, 118}, ++{225, 73, 122}, ++{237, 68, 126}, ++{243, 65, 128}, ++{185, 97, 105}, ++{190, 94, 108}, ++{198, 90, 111}, ++{207, 85, 114}, ++{217, 80, 118}, ++{228, 74, 122}, ++{239, 69, 127}, ++{245, 66, 129}, ++{188, 98, 106}, ++{193, 95, 109}, ++{201, 91, 112}, ++{210, 86, 115}, ++{220, 81, 119}, ++{230, 75, 123}, ++{242, 69, 127}, ++{247, 67, 129}, ++{192, 99, 107}, ++{196, 96, 109}, ++{204, 92, 112}, ++{213, 87, 116}, ++{222, 82, 120}, ++{233, 76, 124}, ++{244, 70, 127}, ++{250, 67, 129}, ++{193, 99, 108}, ++{198, 97, 110}, ++{205, 92, 113}, ++{214, 87, 116}, ++{224, 82, 120}, ++{234, 76, 124}, ++{245, 71, 128}, ++{251, 68, 130}, ++{193, 99, 108}, ++{198, 97, 110}, ++{205, 92, 113}, ++{214, 87, 116}, ++{224, 82, 120}, ++{234, 76, 124}, ++{245, 71, 128}, ++{251, 68, 130}, ++{193, 99, 108}, ++{198, 97, 110}, ++{205, 92, 113}, ++{214, 87, 116}, ++{224, 82, 120}, ++{234, 76, 124}, ++{245, 71, 128}, ++{251, 68, 130}, ++{193, 99, 108}, ++{198, 97, 110}, ++{205, 92, 113}, ++{214, 87, 116}, ++{224, 82, 120}, ++{234, 76, 124}, ++{245, 71, 128}, ++{251, 68, 130}, ++{130, 62, 81}, ++{139, 62, 86}, ++{151, 62, 92}, ++{164, 61, 99}, ++{178, 58, 105}, ++{192, 55, 111}, ++{206, 51, 117}, ++{213, 49, 120}, ++{130, 62, 82}, ++{139, 63, 86}, ++{151, 62, 92}, ++{164, 61, 99}, ++{178, 58, 105}, ++{192, 55, 111}, ++{206, 51, 117}, ++{213, 49, 120}, ++{131, 62, 82}, ++{139, 63, 86}, ++{151, 63, 92}, ++{164, 61, 99}, ++{178, 58, 105}, ++{193, 55, 111}, ++{207, 51, 117}, ++{214, 49, 120}, ++{132, 63, 82}, ++{140, 64, 87}, ++{152, 63, 93}, ++{165, 61, 99}, ++{179, 59, 105}, ++{193, 55, 111}, ++{207, 51, 117}, ++{214, 49, 120}, ++{133, 64, 83}, ++{141, 64, 87}, ++{153, 64, 93}, ++{166, 62, 99}, ++{180, 59, 106}, ++{194, 56, 112}, ++{208, 52, 117}, ++{215, 50, 120}, ++{134, 65, 83}, ++{142, 65, 88}, ++{154, 65, 93}, ++{167, 63, 100}, ++{180, 60, 106}, ++{194, 56, 112}, ++{208, 52, 117}, ++{215, 50, 120}, ++{136, 67, 84}, ++{144, 67, 88}, ++{155, 65, 94}, ++{168, 63, 100}, ++{181, 60, 106}, ++{195, 57, 112}, ++{209, 52, 118}, ++{216, 50, 120}, ++{137, 68, 85}, ++{145, 68, 89}, ++{156, 66, 94}, ++{169, 64, 100}, ++{182, 61, 106}, ++{196, 57, 112}, ++{210, 53, 118}, ++{217, 51, 120}, ++{139, 70, 86}, ++{147, 69, 90}, ++{158, 68, 95}, ++{170, 65, 101}, ++{184, 62, 107}, ++{197, 58, 113}, ++{211, 54, 118}, ++{218, 51, 121}, ++{141, 71, 87}, ++{149, 71, 90}, ++{159, 69, 96}, ++{172, 66, 101}, ++{185, 62, 107}, ++{198, 58, 113}, ++{212, 54, 118}, ++{219, 52, 121}, ++{143, 73, 88}, ++{151, 72, 91}, ++{161, 70, 96}, ++{173, 67, 102}, ++{186, 63, 108}, ++{200, 59, 113}, ++{213, 55, 119}, ++{220, 53, 121}, ++{146, 75, 89}, ++{153, 73, 92}, ++{163, 71, 97}, ++{175, 68, 103}, ++{188, 64, 108}, ++{201, 60, 114}, ++{214, 55, 119}, ++{221, 53, 121}, ++{148, 76, 90}, ++{155, 75, 93}, ++{165, 72, 98}, ++{177, 69, 103}, ++{190, 65, 109}, ++{203, 61, 114}, ++{216, 56, 119}, ++{223, 54, 122}, ++{151, 78, 91}, ++{157, 76, 94}, ++{167, 74, 99}, ++{179, 70, 104}, ++{191, 66, 109}, ++{204, 62, 114}, ++{217, 57, 120}, ++{224, 55, 122}, ++{153, 80, 92}, ++{160, 78, 95}, ++{170, 75, 99}, ++{181, 71, 105}, ++{193, 67, 110}, ++{206, 62, 115}, ++{219, 58, 120}, ++{225, 55, 122}, ++{156, 81, 93}, ++{162, 79, 96}, ++{172, 76, 100}, ++{183, 72, 105}, ++{195, 68, 110}, ++{208, 63, 115}, ++{221, 59, 120}, ++{227, 56, 123}, ++{159, 83, 94}, ++{165, 81, 97}, ++{174, 78, 101}, ++{185, 74, 106}, ++{197, 69, 111}, ++{210, 64, 116}, ++{222, 59, 121}, ++{229, 57, 123}, ++{162, 85, 95}, ++{168, 82, 98}, ++{177, 79, 102}, ++{188, 75, 107}, ++{199, 70, 111}, ++{212, 65, 116}, ++{224, 60, 121}, ++{230, 58, 123}, ++{165, 86, 96}, ++{171, 84, 99}, ++{180, 80, 103}, ++{190, 76, 107}, ++{202, 71, 112}, ++{214, 66, 117}, ++{226, 61, 122}, ++{232, 59, 124}, ++{168, 87, 97}, ++{174, 85, 100}, ++{182, 81, 104}, ++{192, 77, 108}, ++{204, 72, 113}, ++{216, 67, 117}, ++{228, 62, 122}, ++{234, 59, 124}, ++{171, 89, 98}, ++{176, 86, 101}, ++{185, 83, 105}, ++{195, 78, 109}, ++{206, 73, 113}, ++{218, 68, 118}, ++{230, 63, 122}, ++{236, 60, 125}, ++{174, 90, 99}, ++{179, 88, 102}, ++{188, 84, 105}, ++{198, 79, 110}, ++{208, 74, 114}, ++{220, 69, 118}, ++{232, 64, 123}, ++{238, 61, 125}, ++{177, 91, 100}, ++{182, 89, 103}, ++{191, 85, 106}, ++{200, 80, 110}, ++{211, 75, 115}, ++{222, 70, 119}, ++{234, 65, 123}, ++{240, 62, 126}, ++{180, 93, 101}, ++{186, 90, 104}, ++{193, 86, 107}, ++{203, 81, 111}, ++{213, 76, 115}, ++{225, 71, 120}, ++{236, 66, 124}, ++{242, 63, 126}, ++{184, 94, 103}, ++{189, 91, 105}, ++{196, 87, 108}, ++{206, 82, 112}, ++{216, 77, 116}, ++{227, 72, 120}, ++{238, 67, 124}, ++{244, 64, 126}, ++{187, 95, 104}, ++{192, 92, 106}, ++{199, 88, 109}, ++{208, 83, 113}, ++{219, 78, 117}, ++{229, 73, 121}, ++{241, 67, 125}, ++{246, 65, 127}, ++{190, 96, 105}, ++{195, 93, 107}, ++{202, 89, 110}, ++{211, 84, 113}, ++{221, 79, 117}, ++{232, 74, 121}, ++{243, 68, 125}, ++{249, 66, 127}, ++{193, 97, 106}, ++{198, 94, 108}, ++{205, 90, 111}, ++{214, 85, 114}, ++{224, 80, 118}, ++{234, 75, 122}, ++{245, 69, 126}, ++{251, 66, 128}, ++{195, 98, 106}, ++{200, 95, 108}, ++{207, 91, 111}, ++{216, 86, 114}, ++{225, 81, 118}, ++{236, 75, 122}, ++{247, 70, 126}, ++{252, 67, 128}, ++{195, 98, 106}, ++{200, 95, 108}, ++{207, 91, 111}, ++{216, 86, 114}, ++{225, 81, 118}, ++{236, 75, 122}, ++{247, 70, 126}, ++{252, 67, 128}, ++{195, 98, 106}, ++{200, 95, 108}, ++{207, 91, 111}, ++{216, 86, 114}, ++{225, 81, 118}, ++{236, 75, 122}, ++{247, 70, 126}, ++{252, 67, 128}, ++{195, 98, 106}, ++{200, 95, 108}, ++{207, 91, 111}, ++{216, 86, 114}, ++{225, 81, 118}, ++{236, 75, 122}, ++{247, 70, 126}, ++{252, 67, 128}, ++{133, 59, 80}, ++{141, 60, 84}, ++{153, 60, 90}, ++{166, 59, 97}, ++{180, 56, 103}, ++{194, 53, 109}, ++{208, 50, 115}, ++{215, 48, 118}, ++{133, 59, 80}, ++{142, 60, 84}, ++{153, 60, 90}, ++{166, 59, 97}, ++{180, 57, 103}, ++{194, 53, 109}, ++{208, 50, 115}, ++{215, 48, 118}, ++{134, 60, 80}, ++{142, 61, 84}, ++{154, 61, 90}, ++{167, 59, 97}, ++{180, 57, 103}, ++{194, 54, 109}, ++{208, 50, 115}, ++{215, 48, 118}, ++{134, 61, 80}, ++{143, 61, 85}, ++{154, 61, 91}, ++{167, 60, 97}, ++{181, 57, 103}, ++{195, 54, 109}, ++{209, 50, 115}, ++{216, 48, 118}, ++{135, 62, 81}, ++{144, 62, 85}, ++{155, 62, 91}, ++{168, 60, 97}, ++{182, 58, 103}, ++{195, 54, 109}, ++{209, 50, 115}, ++{216, 48, 118}, ++{137, 63, 81}, ++{145, 63, 86}, ++{156, 63, 91}, ++{169, 61, 98}, ++{182, 58, 104}, ++{196, 55, 110}, ++{210, 51, 115}, ++{217, 49, 118}, ++{138, 64, 82}, ++{146, 64, 86}, ++{157, 63, 92}, ++{170, 61, 98}, ++{183, 59, 104}, ++{197, 55, 110}, ++{211, 51, 116}, ++{218, 49, 118}, ++{140, 66, 83}, ++{148, 66, 87}, ++{159, 64, 92}, ++{171, 62, 98}, ++{184, 59, 104}, ++{198, 56, 110}, ++{212, 52, 116}, ++{218, 50, 118}, ++{142, 67, 84}, ++{149, 67, 88}, ++{160, 66, 93}, ++{172, 63, 99}, ++{186, 60, 105}, ++{199, 56, 111}, ++{213, 52, 116}, ++{219, 50, 119}, ++{144, 69, 85}, ++{151, 68, 88}, ++{162, 67, 94}, ++{174, 64, 99}, ++{187, 61, 105}, ++{200, 57, 111}, ++{214, 53, 116}, ++{220, 51, 119}, ++{146, 71, 86}, ++{153, 70, 89}, ++{163, 68, 94}, ++{175, 65, 100}, ++{188, 62, 106}, ++{201, 58, 111}, ++{215, 54, 117}, ++{222, 51, 119}, ++{148, 72, 87}, ++{155, 71, 90}, ++{165, 69, 95}, ++{177, 66, 101}, ++{190, 63, 106}, ++{203, 59, 112}, ++{216, 54, 117}, ++{223, 52, 119}, ++{151, 74, 88}, ++{157, 73, 91}, ++{167, 70, 96}, ++{179, 67, 101}, ++{191, 64, 107}, ++{204, 59, 112}, ++{218, 55, 117}, ++{224, 53, 120}, ++{153, 76, 89}, ++{160, 74, 92}, ++{170, 72, 97}, ++{181, 68, 102}, ++{193, 65, 107}, ++{206, 60, 112}, ++{219, 56, 118}, ++{226, 53, 120}, ++{156, 78, 90}, ++{162, 76, 93}, ++{172, 73, 97}, ++{183, 70, 103}, ++{195, 66, 108}, ++{208, 61, 113}, ++{221, 57, 118}, ++{227, 54, 120}, ++{158, 79, 91}, ++{165, 77, 94}, ++{174, 74, 98}, ++{185, 71, 103}, ++{197, 67, 108}, ++{209, 62, 113}, ++{222, 57, 118}, ++{229, 55, 121}, ++{161, 81, 92}, ++{167, 79, 95}, ++{176, 76, 99}, ++{187, 72, 104}, ++{199, 68, 109}, ++{211, 63, 114}, ++{224, 58, 119}, ++{230, 56, 121}, ++{164, 82, 93}, ++{170, 80, 96}, ++{179, 77, 100}, ++{190, 73, 105}, ++{201, 69, 110}, ++{213, 64, 114}, ++{226, 59, 119}, ++{232, 57, 122}, ++{167, 84, 94}, ++{173, 82, 97}, ++{182, 78, 101}, ++{192, 74, 105}, ++{203, 70, 110}, ++{215, 65, 115}, ++{227, 60, 120}, ++{234, 57, 122}, ++{170, 85, 95}, ++{176, 83, 98}, ++{184, 80, 102}, ++{194, 75, 106}, ++{206, 71, 111}, ++{217, 66, 115}, ++{229, 61, 120}, ++{236, 58, 122}, ++{173, 87, 96}, ++{178, 84, 99}, ++{187, 81, 103}, ++{197, 76, 107}, ++{208, 72, 111}, ++{219, 67, 116}, ++{231, 62, 121}, ++{237, 59, 123}, ++{176, 88, 97}, ++{181, 86, 100}, ++{190, 82, 103}, ++{199, 78, 108}, ++{210, 73, 112}, ++{222, 68, 117}, ++{233, 63, 121}, ++{239, 60, 123}, ++{179, 89, 98}, ++{184, 87, 101}, ++{192, 83, 104}, ++{202, 79, 108}, ++{213, 74, 113}, ++{224, 69, 117}, ++{236, 64, 122}, ++{241, 61, 124}, ++{182, 91, 100}, ++{187, 88, 102}, ++{195, 84, 105}, ++{205, 80, 109}, ++{215, 75, 113}, ++{226, 70, 118}, ++{238, 65, 122}, ++{244, 62, 124}, ++{185, 92, 101}, ++{191, 89, 103}, ++{198, 85, 106}, ++{207, 81, 110}, ++{218, 76, 114}, ++{229, 71, 118}, ++{240, 65, 122}, ++{246, 63, 125}, ++{189, 93, 102}, ++{194, 90, 104}, ++{201, 87, 107}, ++{210, 82, 111}, ++{220, 77, 115}, ++{231, 72, 119}, ++{242, 66, 123}, ++{248, 64, 125}, ++{192, 94, 103}, ++{197, 92, 105}, ++{204, 88, 108}, ++{213, 83, 111}, ++{223, 78, 115}, ++{233, 73, 119}, ++{244, 67, 123}, ++{250, 65, 126}, ++{195, 95, 104}, ++{200, 93, 106}, ++{207, 89, 109}, ++{216, 84, 112}, ++{226, 79, 116}, ++{236, 74, 120}, ++{247, 68, 124}, ++{252, 65, 126}, ++{197, 96, 104}, ++{202, 93, 106}, ++{209, 89, 109}, ++{217, 85, 113}, ++{227, 79, 116}, ++{237, 74, 120}, ++{248, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 106}, ++{209, 89, 109}, ++{217, 85, 113}, ++{227, 79, 116}, ++{237, 74, 120}, ++{248, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 106}, ++{209, 89, 109}, ++{217, 85, 113}, ++{227, 79, 116}, ++{237, 74, 120}, ++{248, 69, 124}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 106}, ++{209, 89, 109}, ++{217, 85, 113}, ++{227, 79, 116}, ++{237, 74, 120}, ++{248, 69, 124}, ++{254, 66, 126}, ++{136, 57, 78}, ++{144, 58, 82}, ++{155, 58, 88}, ++{168, 57, 95}, ++{182, 55, 101}, ++{196, 52, 107}, ++{210, 48, 113}, ++{217, 47, 116}, ++{136, 57, 78}, ++{144, 58, 82}, ++{156, 58, 88}, ++{168, 57, 95}, ++{182, 55, 101}, ++{196, 52, 107}, ++{210, 49, 113}, ++{217, 47, 116}, ++{136, 58, 78}, ++{145, 58, 83}, ++{156, 59, 88}, ++{169, 57, 95}, ++{182, 55, 101}, ++{196, 52, 107}, ++{210, 49, 113}, ++{217, 47, 116}, ++{137, 58, 78}, ++{145, 59, 83}, ++{157, 59, 89}, ++{169, 58, 95}, ++{183, 55, 101}, ++{197, 52, 107}, ++{211, 49, 113}, ++{217, 47, 116}, ++{138, 59, 79}, ++{146, 60, 83}, ++{157, 60, 89}, ++{170, 58, 95}, ++{184, 56, 101}, ++{197, 53, 107}, ++{211, 49, 113}, ++{218, 47, 116}, ++{139, 61, 80}, ++{147, 61, 84}, ++{158, 60, 89}, ++{171, 59, 96}, ++{184, 56, 102}, ++{198, 53, 108}, ++{212, 50, 113}, ++{219, 48, 116}, ++{141, 62, 80}, ++{149, 62, 84}, ++{160, 61, 90}, ++{172, 60, 96}, ++{185, 57, 102}, ++{199, 54, 108}, ++{212, 50, 114}, ++{219, 48, 116}, ++{143, 63, 81}, ++{150, 63, 85}, ++{161, 62, 90}, ++{173, 60, 96}, ++{186, 58, 102}, ++{200, 54, 108}, ++{213, 51, 114}, ++{220, 49, 116}, ++{144, 65, 82}, ++{152, 65, 86}, ++{162, 63, 91}, ++{175, 61, 97}, ++{187, 58, 103}, ++{201, 55, 109}, ++{214, 51, 114}, ++{221, 49, 117}, ++{146, 67, 83}, ++{154, 66, 86}, ++{164, 65, 92}, ++{176, 62, 97}, ++{189, 59, 103}, ++{202, 56, 109}, ++{215, 52, 114}, ++{222, 50, 117}, ++{148, 68, 84}, ++{155, 68, 87}, ++{166, 66, 92}, ++{178, 63, 98}, ++{190, 60, 104}, ++{203, 56, 109}, ++{217, 52, 115}, ++{223, 50, 117}, ++{151, 70, 85}, ++{158, 69, 88}, ++{168, 67, 93}, ++{179, 64, 99}, ++{192, 61, 104}, ++{205, 57, 110}, ++{218, 53, 115}, ++{224, 51, 118}, ++{153, 72, 86}, ++{160, 71, 89}, ++{170, 68, 94}, ++{181, 66, 99}, ++{193, 62, 105}, ++{206, 58, 110}, ++{219, 54, 115}, ++{226, 52, 118}, ++{155, 73, 87}, ++{162, 72, 90}, ++{172, 70, 95}, ++{183, 67, 100}, ++{195, 63, 105}, ++{208, 59, 111}, ++{221, 55, 116}, ++{227, 52, 118}, ++{158, 75, 88}, ++{164, 74, 91}, ++{174, 71, 95}, ++{185, 68, 101}, ++{197, 64, 106}, ++{209, 60, 111}, ++{222, 55, 116}, ++{229, 53, 119}, ++{161, 77, 89}, ++{167, 75, 92}, ++{176, 72, 96}, ++{187, 69, 101}, ++{199, 65, 106}, ++{211, 61, 111}, ++{224, 56, 117}, ++{230, 54, 119}, ++{163, 79, 90}, ++{170, 77, 93}, ++{179, 74, 97}, ++{189, 70, 102}, ++{201, 66, 107}, ++{213, 62, 112}, ++{225, 57, 117}, ++{232, 55, 119}, ++{166, 80, 91}, ++{172, 78, 94}, ++{181, 75, 98}, ++{191, 71, 103}, ++{203, 67, 108}, ++{215, 63, 113}, ++{227, 58, 117}, ++{233, 56, 120}, ++{169, 82, 92}, ++{175, 80, 95}, ++{184, 76, 99}, ++{194, 73, 103}, ++{205, 68, 108}, ++{217, 64, 113}, ++{229, 59, 118}, ++{235, 56, 120}, ++{172, 83, 93}, ++{178, 81, 96}, ++{186, 78, 100}, ++{196, 74, 104}, ++{207, 69, 109}, ++{219, 65, 114}, ++{231, 60, 118}, ++{237, 57, 121}, ++{175, 85, 94}, ++{181, 82, 97}, ++{189, 79, 101}, ++{199, 75, 105}, ++{210, 70, 110}, ++{221, 66, 114}, ++{233, 61, 119}, ++{239, 58, 121}, ++{178, 86, 95}, ++{183, 84, 98}, ++{192, 80, 102}, ++{201, 76, 106}, ++{212, 71, 110}, ++{223, 67, 115}, ++{235, 62, 119}, ++{241, 59, 121}, ++{181, 87, 97}, ++{186, 85, 99}, ++{194, 81, 102}, ++{204, 77, 106}, ++{214, 72, 111}, ++{225, 68, 115}, ++{237, 62, 120}, ++{243, 60, 122}, ++{184, 89, 98}, ++{189, 86, 100}, ++{197, 83, 103}, ++{206, 78, 107}, ++{217, 74, 112}, ++{228, 69, 116}, ++{239, 63, 120}, ++{245, 61, 122}, ++{187, 90, 99}, ++{192, 88, 101}, ++{200, 84, 104}, ++{209, 79, 108}, ++{219, 75, 112}, ++{230, 70, 116}, ++{241, 64, 121}, ++{247, 62, 123}, ++{191, 91, 100}, ++{196, 89, 102}, ++{203, 85, 105}, ++{212, 80, 109}, ++{222, 76, 113}, ++{233, 70, 117}, ++{244, 65, 121}, ++{249, 63, 123}, ++{194, 92, 101}, ++{199, 90, 103}, ++{206, 86, 106}, ++{215, 82, 110}, ++{224, 77, 114}, ++{235, 71, 118}, ++{246, 66, 122}, ++{252, 64, 124}, ++{197, 94, 102}, ++{202, 91, 104}, ++{209, 87, 107}, ++{217, 83, 110}, ++{227, 78, 114}, ++{237, 72, 118}, ++{248, 67, 122}, ++{254, 64, 124}, ++{199, 94, 102}, ++{203, 91, 104}, ++{210, 88, 107}, ++{219, 83, 111}, ++{228, 78, 115}, ++{239, 73, 119}, ++{249, 68, 123}, ++{255, 65, 124}, ++{199, 94, 102}, ++{203, 91, 104}, ++{210, 88, 107}, ++{219, 83, 111}, ++{228, 78, 115}, ++{239, 73, 119}, ++{249, 68, 123}, ++{255, 65, 124}, ++{199, 94, 102}, ++{203, 91, 104}, ++{210, 88, 107}, ++{219, 83, 111}, ++{228, 78, 115}, ++{239, 73, 119}, ++{249, 68, 123}, ++{255, 65, 124}, ++{199, 94, 102}, ++{203, 91, 104}, ++{210, 88, 107}, ++{219, 83, 111}, ++{228, 78, 115}, ++{239, 73, 119}, ++{249, 68, 123}, ++{255, 65, 124}, ++{139, 54, 76}, ++{147, 56, 80}, ++{158, 56, 86}, ++{171, 55, 93}, ++{184, 53, 99}, ++{198, 51, 105}, ++{212, 47, 111}, ++{218, 45, 114}, ++{139, 55, 76}, ++{147, 56, 80}, ++{158, 56, 86}, ++{171, 55, 93}, ++{184, 53, 99}, ++{198, 51, 105}, ++{212, 47, 111}, ++{219, 45, 114}, ++{139, 55, 76}, ++{147, 56, 81}, ++{158, 56, 86}, ++{171, 56, 93}, ++{184, 54, 99}, ++{198, 51, 105}, ++{212, 47, 111}, ++{219, 46, 114}, ++{140, 56, 77}, ++{148, 57, 81}, ++{159, 57, 87}, ++{172, 56, 93}, ++{185, 54, 99}, ++{199, 51, 105}, ++{212, 48, 111}, ++{219, 46, 114}, ++{141, 57, 77}, ++{149, 58, 81}, ++{160, 58, 87}, ++{172, 56, 93}, ++{186, 54, 99}, ++{199, 51, 105}, ++{213, 48, 111}, ++{220, 46, 114}, ++{142, 58, 78}, ++{150, 59, 82}, ++{161, 58, 87}, ++{173, 57, 94}, ++{186, 55, 100}, ++{200, 52, 106}, ++{213, 48, 111}, ++{220, 46, 114}, ++{144, 59, 78}, ++{151, 60, 82}, ++{162, 59, 88}, ++{174, 58, 94}, ++{187, 55, 100}, ++{201, 52, 106}, ++{214, 49, 112}, ++{221, 47, 114}, ++{145, 61, 79}, ++{153, 61, 83}, ++{163, 60, 88}, ++{175, 59, 94}, ++{188, 56, 100}, ++{202, 53, 106}, ++{215, 49, 112}, ++{222, 47, 115}, ++{147, 63, 80}, ++{154, 62, 84}, ++{165, 61, 89}, ++{177, 60, 95}, ++{189, 57, 101}, ++{203, 54, 107}, ++{216, 50, 112}, ++{223, 48, 115}, ++{149, 64, 81}, ++{156, 64, 85}, ++{166, 63, 90}, ++{178, 61, 95}, ++{191, 58, 101}, ++{204, 54, 107}, ++{217, 50, 112}, ++{224, 48, 115}, ++{151, 66, 82}, ++{158, 65, 85}, ++{168, 64, 90}, ++{180, 62, 96}, ++{192, 59, 102}, ++{205, 55, 107}, ++{218, 51, 113}, ++{225, 49, 115}, ++{153, 68, 83}, ++{160, 67, 86}, ++{170, 65, 91}, ++{181, 63, 97}, ++{194, 59, 102}, ++{206, 56, 108}, ++{220, 52, 113}, ++{226, 50, 116}, ++{155, 69, 84}, ++{162, 68, 87}, ++{172, 66, 92}, ++{183, 64, 97}, ++{195, 60, 103}, ++{208, 57, 108}, ++{221, 53, 113}, ++{227, 50, 116}, ++{158, 71, 85}, ++{164, 70, 88}, ++{174, 68, 93}, ++{185, 65, 98}, ++{197, 61, 103}, ++{210, 58, 109}, ++{222, 53, 114}, ++{229, 51, 116}, ++{160, 73, 86}, ++{167, 71, 89}, ++{176, 69, 94}, ++{187, 66, 99}, ++{199, 62, 104}, ++{211, 58, 109}, ++{224, 54, 114}, ++{230, 52, 117}, ++{163, 75, 87}, ++{169, 73, 90}, ++{178, 71, 94}, ++{189, 67, 99}, ++{201, 63, 104}, ++{213, 59, 110}, ++{225, 55, 115}, ++{232, 53, 117}, ++{166, 76, 88}, ++{172, 75, 91}, ++{181, 72, 95}, ++{191, 68, 100}, ++{203, 65, 105}, ++{215, 60, 110}, ++{227, 56, 115}, ++{233, 54, 117}, ++{168, 78, 89}, ++{174, 76, 92}, ++{183, 73, 96}, ++{193, 70, 101}, ++{205, 66, 106}, ++{217, 61, 111}, ++{229, 57, 115}, ++{235, 54, 118}, ++{171, 80, 90}, ++{177, 78, 93}, ++{186, 75, 97}, ++{196, 71, 102}, ++{207, 67, 106}, ++{219, 62, 111}, ++{231, 58, 116}, ++{237, 55, 118}, ++{174, 81, 91}, ++{180, 79, 94}, ++{188, 76, 98}, ++{198, 72, 102}, ++{209, 68, 107}, ++{221, 63, 112}, ++{233, 59, 116}, ++{239, 56, 119}, ++{177, 83, 92}, ++{183, 80, 95}, ++{191, 77, 99}, ++{201, 73, 103}, ++{211, 69, 108}, ++{223, 64, 112}, ++{234, 59, 117}, ++{240, 57, 119}, ++{180, 84, 94}, ++{185, 82, 96}, ++{193, 78, 100}, ++{203, 74, 104}, ++{214, 70, 108}, ++{225, 65, 113}, ++{237, 60, 117}, ++{242, 58, 120}, ++{183, 85, 95}, ++{188, 83, 97}, ++{196, 80, 101}, ++{206, 76, 105}, ++{216, 71, 109}, ++{227, 66, 113}, ++{239, 61, 118}, ++{244, 59, 120}, ++{186, 87, 96}, ++{191, 84, 98}, ++{199, 81, 101}, ++{208, 77, 105}, ++{218, 72, 110}, ++{229, 67, 114}, ++{241, 62, 118}, ++{246, 60, 121}, ++{189, 88, 97}, ++{194, 86, 99}, ++{202, 82, 102}, ++{211, 78, 106}, ++{221, 73, 110}, ++{232, 68, 115}, ++{243, 63, 119}, ++{249, 61, 121}, ++{193, 89, 98}, ++{197, 87, 100}, ++{205, 83, 103}, ++{214, 79, 107}, ++{223, 74, 111}, ++{234, 69, 115}, ++{245, 64, 119}, ++{251, 62, 122}, ++{196, 91, 99}, ++{200, 88, 101}, ++{208, 84, 104}, ++{216, 80, 108}, ++{226, 75, 112}, ++{236, 70, 116}, ++{247, 65, 120}, ++{253, 62, 122}, ++{199, 92, 100}, ++{204, 89, 102}, ++{211, 86, 105}, ++{219, 81, 109}, ++{229, 76, 112}, ++{239, 71, 116}, ++{250, 66, 120}, ++{255, 63, 123}, ++{201, 92, 101}, ++{205, 90, 103}, ++{212, 86, 105}, ++{221, 82, 109}, ++{230, 77, 113}, ++{240, 72, 117}, ++{251, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{205, 90, 103}, ++{212, 86, 105}, ++{221, 82, 109}, ++{230, 77, 113}, ++{240, 72, 117}, ++{251, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{205, 90, 103}, ++{212, 86, 105}, ++{221, 82, 109}, ++{230, 77, 113}, ++{240, 72, 117}, ++{251, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{205, 90, 103}, ++{212, 86, 105}, ++{221, 82, 109}, ++{230, 77, 113}, ++{240, 72, 117}, ++{251, 66, 121}, ++{255, 64, 123}, ++{141, 52, 74}, ++{149, 53, 78}, ++{160, 54, 84}, ++{173, 53, 91}, ++{186, 52, 97}, ++{200, 49, 103}, ++{213, 46, 109}, ++{220, 44, 112}, ++{142, 52, 74}, ++{149, 54, 79}, ++{160, 54, 84}, ++{173, 53, 91}, ++{186, 52, 97}, ++{200, 49, 103}, ++{213, 46, 109}, ++{220, 44, 112}, ++{142, 53, 74}, ++{150, 54, 79}, ++{161, 54, 85}, ++{173, 54, 91}, ++{186, 52, 97}, ++{200, 49, 103}, ++{214, 46, 109}, ++{220, 44, 112}, ++{143, 54, 75}, ++{150, 55, 79}, ++{161, 55, 85}, ++{174, 54, 91}, ++{187, 52, 97}, ++{200, 50, 103}, ++{214, 46, 109}, ++{221, 45, 112}, ++{144, 55, 75}, ++{151, 55, 79}, ++{162, 56, 85}, ++{174, 55, 91}, ++{188, 53, 97}, ++{201, 50, 104}, ++{215, 47, 109}, ++{221, 45, 112}, ++{145, 56, 76}, ++{152, 56, 80}, ++{163, 56, 86}, ++{175, 55, 92}, ++{188, 53, 98}, ++{202, 50, 104}, ++{215, 47, 109}, ++{222, 45, 112}, ++{146, 57, 77}, ++{154, 58, 81}, ++{164, 57, 86}, ++{176, 56, 92}, ++{189, 54, 98}, ++{203, 51, 104}, ++{216, 48, 110}, ++{223, 46, 112}, ++{148, 59, 77}, ++{155, 59, 81}, ++{165, 58, 87}, ++{177, 57, 92}, ++{190, 55, 98}, ++{203, 52, 104}, ++{217, 48, 110}, ++{223, 46, 113}, ++{150, 60, 78}, ++{157, 60, 82}, ++{167, 59, 87}, ++{179, 58, 93}, ++{191, 55, 99}, ++{204, 52, 105}, ++{218, 49, 110}, ++{224, 47, 113}, ++{151, 62, 79}, ++{158, 62, 83}, ++{168, 61, 88}, ++{180, 59, 93}, ++{193, 56, 99}, ++{206, 53, 105}, ++{219, 49, 110}, ++{225, 47, 113}, ++{153, 64, 80}, ++{160, 63, 84}, ++{170, 62, 88}, ++{182, 60, 94}, ++{194, 57, 100}, ++{207, 54, 105}, ++{220, 50, 111}, ++{227, 48, 113}, ++{156, 65, 81}, ++{162, 65, 84}, ++{172, 63, 89}, ++{183, 61, 95}, ++{196, 58, 100}, ++{208, 54, 106}, ++{221, 51, 111}, ++{228, 49, 114}, ++{158, 67, 82}, ++{164, 66, 85}, ++{174, 64, 90}, ++{185, 62, 95}, ++{197, 59, 101}, ++{210, 55, 106}, ++{223, 51, 112}, ++{229, 49, 114}, ++{160, 69, 83}, ++{167, 68, 86}, ++{176, 66, 91}, ++{187, 63, 96}, ++{199, 60, 101}, ++{211, 56, 107}, ++{224, 52, 112}, ++{230, 50, 114}, ++{163, 71, 84}, ++{169, 69, 87}, ++{178, 67, 92}, ++{189, 64, 97}, ++{201, 61, 102}, ++{213, 57, 107}, ++{225, 53, 112}, ++{232, 51, 115}, ++{165, 72, 85}, ++{171, 71, 88}, ++{180, 69, 92}, ++{191, 66, 97}, ++{203, 62, 103}, ++{215, 58, 108}, ++{227, 54, 113}, ++{233, 52, 115}, ++{168, 74, 86}, ++{174, 72, 89}, ++{183, 70, 93}, ++{193, 67, 98}, ++{204, 63, 103}, ++{216, 59, 108}, ++{229, 55, 113}, ++{235, 52, 116}, ++{171, 76, 87}, ++{176, 74, 90}, ++{185, 71, 94}, ++{195, 68, 99}, ++{207, 64, 104}, ++{218, 60, 109}, ++{230, 56, 114}, ++{237, 53, 116}, ++{173, 77, 88}, ++{179, 76, 91}, ++{188, 73, 95}, ++{198, 69, 100}, ++{209, 65, 104}, ++{220, 61, 109}, ++{232, 56, 114}, ++{238, 54, 116}, ++{176, 79, 90}, ++{182, 77, 92}, ++{190, 74, 96}, ++{200, 70, 100}, ++{211, 66, 105}, ++{222, 62, 110}, ++{234, 57, 115}, ++{240, 55, 117}, ++{179, 80, 91}, ++{185, 78, 93}, ++{193, 75, 97}, ++{202, 72, 101}, ++{213, 67, 106}, ++{224, 63, 110}, ++{236, 58, 115}, ++{242, 56, 117}, ++{182, 82, 92}, ++{187, 80, 94}, ++{195, 77, 98}, ++{205, 73, 102}, ++{215, 69, 106}, ++{227, 64, 111}, ++{238, 59, 116}, ++{244, 57, 118}, ++{185, 83, 93}, ++{190, 81, 95}, ++{198, 78, 99}, ++{207, 74, 103}, ++{218, 70, 107}, ++{229, 65, 112}, ++{240, 60, 116}, ++{246, 58, 118}, ++{188, 85, 94}, ++{193, 83, 96}, ++{201, 79, 100}, ++{210, 75, 104}, ++{220, 71, 108}, ++{231, 66, 112}, ++{242, 61, 117}, ++{248, 59, 119}, ++{191, 86, 95}, ++{196, 84, 97}, ++{204, 80, 101}, ++{213, 76, 104}, ++{223, 72, 109}, ++{233, 67, 113}, ++{244, 62, 117}, ++{250, 60, 119}, ++{194, 87, 96}, ++{199, 85, 98}, ++{207, 82, 101}, ++{215, 77, 105}, ++{225, 73, 109}, ++{236, 68, 113}, ++{247, 63, 118}, ++{252, 60, 120}, ++{198, 89, 97}, ++{202, 86, 99}, ++{209, 83, 102}, ++{218, 79, 106}, ++{228, 74, 110}, ++{238, 69, 114}, ++{249, 64, 118}, ++{254, 61, 120}, ++{201, 90, 98}, ++{205, 87, 100}, ++{212, 84, 103}, ++{221, 80, 107}, ++{230, 75, 111}, ++{241, 70, 115}, ++{251, 65, 119}, ++{255, 62, 121}, ++{202, 90, 99}, ++{207, 88, 101}, ++{214, 84, 104}, ++{222, 80, 107}, ++{232, 75, 111}, ++{242, 70, 115}, ++{252, 65, 119}, ++{255, 63, 121}, ++{202, 90, 99}, ++{207, 88, 101}, ++{214, 84, 104}, ++{222, 80, 107}, ++{232, 75, 111}, ++{242, 70, 115}, ++{252, 65, 119}, ++{255, 63, 121}, ++{202, 90, 99}, ++{207, 88, 101}, ++{214, 84, 104}, ++{222, 80, 107}, ++{232, 75, 111}, ++{242, 70, 115}, ++{252, 65, 119}, ++{255, 63, 121}, ++{202, 90, 99}, ++{207, 88, 101}, ++{214, 84, 104}, ++{222, 80, 107}, ++{232, 75, 111}, ++{242, 70, 115}, ++{252, 65, 119}, ++{255, 63, 121}, ++{144, 50, 72}, ++{152, 51, 77}, ++{163, 52, 82}, ++{175, 52, 89}, ++{188, 50, 95}, ++{202, 48, 101}, ++{215, 45, 107}, ++{222, 43, 110}, ++{144, 50, 72}, ++{152, 51, 77}, ++{163, 52, 82}, ++{175, 52, 89}, ++{188, 50, 95}, ++{202, 48, 101}, ++{215, 45, 107}, ++{222, 43, 110}, ++{145, 50, 73}, ++{152, 52, 77}, ++{163, 52, 83}, ++{175, 52, 89}, ++{189, 50, 95}, ++{202, 48, 101}, ++{215, 45, 107}, ++{222, 43, 110}, ++{145, 51, 73}, ++{153, 52, 77}, ++{164, 53, 83}, ++{176, 52, 89}, ++{189, 51, 95}, ++{202, 48, 101}, ++{216, 45, 107}, ++{223, 43, 110}, ++{146, 52, 74}, ++{154, 53, 78}, ++{164, 54, 83}, ++{177, 53, 89}, ++{190, 51, 96}, ++{203, 48, 102}, ++{216, 45, 107}, ++{223, 44, 110}, ++{148, 53, 74}, ++{155, 54, 78}, ++{165, 54, 84}, ++{177, 53, 90}, ++{190, 52, 96}, ++{204, 49, 102}, ++{217, 46, 108}, ++{224, 44, 110}, ++{149, 55, 75}, ++{156, 55, 79}, ++{167, 55, 84}, ++{178, 54, 90}, ++{191, 52, 96}, ++{204, 49, 102}, ++{218, 46, 108}, ++{224, 44, 111}, ++{150, 56, 76}, ++{158, 57, 79}, ++{168, 56, 85}, ++{180, 55, 91}, ++{192, 53, 96}, ++{205, 50, 102}, ++{219, 47, 108}, ++{225, 45, 111}, ++{152, 58, 76}, ++{159, 58, 80}, ++{169, 57, 85}, ++{181, 56, 91}, ++{193, 54, 97}, ++{206, 51, 103}, ++{219, 47, 108}, ++{226, 45, 111}, ++{154, 59, 77}, ++{161, 59, 81}, ++{171, 59, 86}, ++{182, 57, 92}, ++{195, 54, 97}, ++{207, 51, 103}, ++{221, 48, 109}, ++{227, 46, 111}, ++{156, 61, 78}, ++{163, 61, 82}, ++{172, 60, 87}, ++{184, 58, 92}, ++{196, 55, 98}, ++{209, 52, 103}, ++{222, 49, 109}, ++{228, 47, 112}, ++{158, 63, 79}, ++{165, 62, 82}, ++{174, 61, 87}, ++{185, 59, 93}, ++{198, 56, 98}, ++{210, 53, 104}, ++{223, 49, 109}, ++{229, 47, 112}, ++{160, 65, 80}, ++{167, 64, 83}, ++{176, 62, 88}, ++{187, 60, 93}, ++{199, 57, 99}, ++{212, 54, 104}, ++{224, 50, 110}, ++{231, 48, 112}, ++{163, 67, 81}, ++{169, 66, 84}, ++{178, 64, 89}, ++{189, 61, 94}, ++{201, 58, 99}, ++{213, 55, 105}, ++{226, 51, 110}, ++{232, 49, 113}, ++{165, 68, 82}, ++{171, 67, 85}, ++{180, 65, 90}, ++{191, 63, 95}, ++{203, 59, 100}, ++{215, 56, 105}, ++{227, 52, 110}, ++{233, 50, 113}, ++{168, 70, 83}, ++{174, 69, 86}, ++{182, 67, 91}, ++{193, 64, 95}, ++{204, 60, 101}, ++{216, 57, 106}, ++{229, 53, 111}, ++{235, 50, 113}, ++{170, 72, 84}, ++{176, 70, 87}, ++{185, 68, 91}, ++{195, 65, 96}, ++{206, 61, 101}, ++{218, 58, 106}, ++{230, 53, 111}, ++{237, 51, 114}, ++{173, 73, 85}, ++{179, 72, 88}, ++{187, 69, 92}, ++{197, 66, 97}, ++{208, 63, 102}, ++{220, 59, 107}, ++{232, 54, 112}, ++{238, 52, 114}, ++{176, 75, 87}, ++{181, 73, 89}, ++{190, 71, 93}, ++{200, 67, 98}, ++{210, 64, 103}, ++{222, 60, 107}, ++{234, 55, 112}, ++{240, 53, 115}, ++{178, 77, 88}, ++{184, 75, 90}, ++{192, 72, 94}, ++{202, 69, 99}, ++{213, 65, 103}, ++{224, 61, 108}, ++{236, 56, 113}, ++{242, 54, 115}, ++{181, 78, 89}, ++{187, 76, 91}, ++{195, 74, 95}, ++{204, 70, 99}, ++{215, 66, 104}, ++{226, 62, 109}, ++{238, 57, 113}, ++{244, 55, 116}, ++{184, 80, 90}, ++{189, 78, 92}, ++{197, 75, 96}, ++{207, 71, 100}, ++{217, 67, 105}, ++{228, 63, 109}, ++{240, 58, 114}, ++{245, 56, 116}, ++{187, 81, 91}, ++{192, 79, 93}, ++{200, 76, 97}, ++{209, 72, 101}, ++{219, 68, 105}, ++{230, 64, 110}, ++{242, 59, 114}, ++{247, 57, 117}, ++{190, 83, 92}, ++{195, 81, 94}, ++{203, 77, 98}, ++{212, 74, 102}, ++{222, 69, 106}, ++{233, 65, 110}, ++{244, 60, 115}, ++{249, 57, 117}, ++{193, 84, 93}, ++{198, 82, 95}, ++{206, 79, 99}, ++{214, 75, 103}, ++{224, 70, 107}, ++{235, 66, 111}, ++{246, 61, 115}, ++{252, 58, 118}, ++{196, 85, 94}, ++{201, 83, 96}, ++{208, 80, 100}, ++{217, 76, 103}, ++{227, 71, 107}, ++{237, 67, 112}, ++{248, 62, 116}, ++{254, 59, 118}, ++{200, 87, 95}, ++{204, 84, 97}, ++{211, 81, 101}, ++{220, 77, 104}, ++{229, 72, 108}, ++{240, 68, 112}, ++{250, 63, 116}, ++{255, 60, 119}, ++{203, 88, 96}, ++{207, 86, 98}, ++{214, 82, 101}, ++{223, 78, 105}, ++{232, 74, 109}, ++{242, 69, 113}, ++{253, 64, 117}, ++{255, 61, 119}, ++{204, 89, 97}, ++{209, 86, 99}, ++{216, 83, 102}, ++{224, 79, 105}, ++{233, 74, 109}, ++{243, 69, 113}, ++{254, 64, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{209, 86, 99}, ++{216, 83, 102}, ++{224, 79, 105}, ++{233, 74, 109}, ++{243, 69, 113}, ++{254, 64, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{209, 86, 99}, ++{216, 83, 102}, ++{224, 79, 105}, ++{233, 74, 109}, ++{243, 69, 113}, ++{254, 64, 117}, ++{255, 62, 119}, ++{204, 89, 97}, ++{209, 86, 99}, ++{216, 83, 102}, ++{224, 79, 105}, ++{233, 74, 109}, ++{243, 69, 113}, ++{254, 64, 117}, ++{255, 62, 119}, ++{147, 47, 71}, ++{154, 49, 75}, ++{165, 50, 81}, ++{177, 50, 87}, ++{190, 48, 93}, ++{203, 46, 99}, ++{217, 43, 105}, ++{224, 42, 108}, ++{147, 48, 71}, ++{154, 49, 75}, ++{165, 50, 81}, ++{177, 50, 87}, ++{190, 48, 93}, ++{204, 46, 99}, ++{217, 43, 105}, ++{224, 42, 108}, ++{147, 48, 71}, ++{155, 50, 75}, ++{165, 50, 81}, ++{178, 50, 87}, ++{191, 49, 93}, ++{204, 46, 99}, ++{217, 44, 105}, ++{224, 42, 108}, ++{148, 49, 71}, ++{156, 50, 75}, ++{166, 51, 81}, ++{178, 50, 87}, ++{191, 49, 93}, ++{204, 47, 99}, ++{218, 44, 105}, ++{224, 42, 108}, ++{149, 50, 72}, ++{156, 51, 76}, ++{167, 52, 81}, ++{179, 51, 87}, ++{192, 49, 94}, ++{205, 47, 100}, ++{218, 44, 105}, ++{225, 42, 108}, ++{150, 51, 72}, ++{157, 52, 76}, ++{168, 52, 82}, ++{180, 52, 88}, ++{192, 50, 94}, ++{205, 47, 100}, ++{219, 44, 106}, ++{225, 43, 108}, ++{152, 52, 73}, ++{159, 53, 77}, ++{169, 53, 82}, ++{181, 52, 88}, ++{193, 51, 94}, ++{206, 48, 100}, ++{219, 45, 106}, ++{226, 43, 109}, ++{153, 54, 74}, ++{160, 54, 78}, ++{170, 54, 83}, ++{182, 53, 89}, ++{194, 51, 95}, ++{207, 49, 100}, ++{220, 45, 106}, ++{227, 44, 109}, ++{155, 55, 75}, ++{162, 56, 78}, ++{171, 55, 83}, ++{183, 54, 89}, ++{195, 52, 95}, ++{208, 49, 101}, ++{221, 46, 106}, ++{228, 44, 109}, ++{156, 57, 75}, ++{163, 57, 79}, ++{173, 57, 84}, ++{184, 55, 90}, ++{197, 53, 95}, ++{209, 50, 101}, ++{222, 47, 107}, ++{229, 45, 109}, ++{158, 59, 76}, ++{165, 59, 80}, ++{175, 58, 85}, ++{186, 56, 90}, ++{198, 54, 96}, ++{211, 51, 102}, ++{223, 47, 107}, ++{230, 45, 110}, ++{160, 61, 77}, ++{167, 60, 81}, ++{176, 59, 85}, ++{187, 57, 91}, ++{199, 55, 96}, ++{212, 52, 102}, ++{225, 48, 107}, ++{231, 46, 110}, ++{163, 62, 78}, ++{169, 62, 82}, ++{178, 61, 86}, ++{189, 58, 91}, ++{201, 56, 97}, ++{213, 52, 102}, ++{226, 49, 108}, ++{232, 47, 110}, ++{165, 64, 79}, ++{171, 63, 82}, ++{180, 62, 87}, ++{191, 60, 92}, ++{203, 57, 98}, ++{215, 53, 103}, ++{227, 50, 108}, ++{234, 48, 111}, ++{167, 66, 80}, ++{173, 65, 83}, ++{182, 63, 88}, ++{193, 61, 93}, ++{204, 58, 98}, ++{216, 54, 103}, ++{229, 50, 109}, ++{235, 48, 111}, ++{170, 68, 81}, ++{176, 67, 84}, ++{185, 65, 89}, ++{195, 62, 94}, ++{206, 59, 99}, ++{218, 55, 104}, ++{230, 51, 109}, ++{237, 49, 112}, ++{172, 70, 83}, ++{178, 68, 85}, ++{187, 66, 90}, ++{197, 63, 94}, ++{208, 60, 99}, ++{220, 56, 104}, ++{232, 52, 109}, ++{238, 50, 112}, ++{175, 71, 84}, ++{181, 70, 86}, ++{189, 68, 90}, ++{199, 65, 95}, ++{210, 61, 100}, ++{222, 57, 105}, ++{234, 53, 110}, ++{240, 51, 112}, ++{178, 73, 85}, ++{183, 71, 87}, ++{192, 69, 91}, ++{201, 66, 96}, ++{212, 62, 101}, ++{224, 58, 106}, ++{235, 54, 110}, ++{241, 52, 113}, ++{181, 75, 86}, ++{186, 73, 88}, ++{194, 70, 92}, ++{204, 67, 97}, ++{214, 63, 101}, ++{226, 59, 106}, ++{237, 55, 111}, ++{243, 53, 113}, ++{183, 76, 87}, ++{189, 74, 89}, ++{197, 72, 93}, ++{206, 68, 97}, ++{217, 64, 102}, ++{228, 60, 107}, ++{239, 56, 111}, ++{245, 54, 114}, ++{186, 78, 88}, ++{191, 76, 91}, ++{199, 73, 94}, ++{209, 70, 98}, ++{219, 66, 103}, ++{230, 61, 107}, ++{241, 57, 112}, ++{247, 54, 114}, ++{189, 79, 89}, ++{194, 77, 92}, ++{202, 74, 95}, ++{211, 71, 99}, ++{221, 67, 103}, ++{232, 62, 108}, ++{243, 58, 113}, ++{249, 55, 115}, ++{192, 81, 90}, ++{197, 79, 93}, ++{205, 76, 96}, ++{214, 72, 100}, ++{224, 68, 104}, ++{234, 63, 109}, ++{245, 59, 113}, ++{251, 56, 115}, ++{195, 82, 91}, ++{200, 80, 94}, ++{207, 77, 97}, ++{216, 73, 101}, ++{226, 69, 105}, ++{236, 64, 109}, ++{247, 60, 114}, ++{253, 57, 116}, ++{198, 84, 92}, ++{203, 81, 95}, ++{210, 78, 98}, ++{219, 74, 102}, ++{228, 70, 106}, ++{239, 65, 110}, ++{250, 61, 114}, ++{255, 58, 116}, ++{201, 85, 94}, ++{206, 83, 96}, ++{213, 79, 99}, ++{221, 75, 102}, ++{231, 71, 106}, ++{241, 66, 111}, ++{252, 62, 115}, ++{255, 59, 117}, ++{205, 86, 95}, ++{209, 84, 97}, ++{216, 81, 100}, ++{224, 77, 103}, ++{234, 72, 107}, ++{244, 67, 111}, ++{254, 63, 115}, ++{255, 60, 117}, ++{206, 87, 95}, ++{211, 84, 97}, ++{217, 81, 100}, ++{226, 77, 104}, ++{235, 73, 107}, ++{245, 68, 111}, ++{255, 63, 116}, ++{255, 61, 118}, ++{206, 87, 95}, ++{211, 84, 97}, ++{217, 81, 100}, ++{226, 77, 104}, ++{235, 73, 107}, ++{245, 68, 111}, ++{255, 63, 116}, ++{255, 61, 118}, ++{206, 87, 95}, ++{211, 84, 97}, ++{217, 81, 100}, ++{226, 77, 104}, ++{235, 73, 107}, ++{245, 68, 111}, ++{255, 63, 116}, ++{255, 61, 118}, ++{206, 87, 95}, ++{211, 84, 97}, ++{217, 81, 100}, ++{226, 77, 104}, ++{235, 73, 107}, ++{245, 68, 111}, ++{255, 63, 116}, ++{255, 61, 118}, ++{150, 45, 69}, ++{157, 47, 73}, ++{167, 48, 79}, ++{179, 48, 85}, ++{192, 47, 91}, ++{205, 45, 97}, ++{219, 42, 103}, ++{225, 40, 106}, ++{150, 45, 69}, ++{157, 47, 73}, ++{167, 48, 79}, ++{179, 48, 85}, ++{192, 47, 91}, ++{205, 45, 97}, ++{219, 42, 103}, ++{225, 40, 106}, ++{150, 46, 69}, ++{157, 47, 73}, ++{168, 48, 79}, ++{180, 48, 85}, ++{193, 47, 91}, ++{206, 45, 97}, ++{219, 42, 103}, ++{226, 41, 106}, ++{151, 47, 70}, ++{158, 48, 74}, ++{168, 49, 79}, ++{180, 49, 85}, ++{193, 47, 92}, ++{206, 45, 98}, ++{219, 42, 103}, ++{226, 41, 106}, ++{152, 48, 70}, ++{159, 49, 74}, ++{169, 49, 80}, ++{181, 49, 86}, ++{194, 48, 92}, ++{207, 46, 98}, ++{220, 43, 104}, ++{226, 41, 106}, ++{153, 49, 71}, ++{160, 50, 75}, ++{170, 50, 80}, ++{182, 50, 86}, ++{194, 48, 92}, ++{207, 46, 98}, ++{220, 43, 104}, ++{227, 42, 107}, ++{154, 50, 71}, ++{161, 51, 75}, ++{171, 51, 80}, ++{183, 50, 86}, ++{195, 49, 92}, ++{208, 46, 98}, ++{221, 44, 104}, ++{228, 42, 107}, ++{156, 52, 72}, ++{162, 52, 76}, ++{172, 52, 81}, ++{184, 51, 87}, ++{196, 50, 93}, ++{209, 47, 99}, ++{222, 44, 104}, ++{229, 42, 107}, ++{157, 53, 73}, ++{164, 54, 76}, ++{174, 53, 82}, ++{185, 52, 87}, ++{197, 50, 93}, ++{210, 48, 99}, ++{223, 45, 105}, ++{229, 43, 107}, ++{159, 55, 74}, ++{166, 55, 77}, ++{175, 55, 82}, ++{186, 53, 88}, ++{199, 51, 94}, ++{211, 48, 99}, ++{224, 45, 105}, ++{230, 44, 108}, ++{161, 57, 75}, ++{167, 57, 78}, ++{177, 56, 83}, ++{188, 54, 88}, ++{200, 52, 94}, ++{212, 49, 100}, ++{225, 46, 105}, ++{232, 44, 108}, ++{163, 58, 76}, ++{169, 58, 79}, ++{179, 57, 84}, ++{190, 55, 89}, ++{201, 53, 95}, ++{214, 50, 100}, ++{226, 47, 106}, ++{233, 45, 108}, ++{165, 60, 76}, ++{171, 60, 80}, ++{180, 59, 84}, ++{191, 57, 90}, ++{203, 54, 95}, ++{215, 51, 101}, ++{228, 47, 106}, ++{234, 46, 109}, ++{167, 62, 78}, ++{173, 61, 81}, ++{182, 60, 85}, ++{193, 58, 90}, ++{205, 55, 96}, ++{217, 52, 101}, ++{229, 48, 106}, ++{235, 46, 109}, ++{170, 64, 79}, ++{176, 63, 82}, ++{185, 61, 86}, ++{195, 59, 91}, ++{206, 56, 96}, ++{218, 53, 102}, ++{230, 49, 107}, ++{237, 47, 109}, ++{172, 66, 80}, ++{178, 65, 83}, ++{187, 63, 87}, ++{197, 60, 92}, ++{208, 57, 97}, ++{220, 54, 102}, ++{232, 50, 107}, ++{238, 48, 110}, ++{175, 67, 81}, ++{180, 66, 84}, ++{189, 64, 88}, ++{199, 62, 92}, ++{210, 58, 98}, ++{222, 55, 103}, ++{234, 51, 108}, ++{240, 49, 110}, ++{177, 69, 82}, ++{183, 68, 85}, ++{191, 66, 89}, ++{201, 63, 93}, ++{212, 59, 98}, ++{224, 56, 103}, ++{235, 52, 108}, ++{241, 50, 111}, ++{180, 71, 83}, ++{185, 69, 86}, ++{194, 67, 90}, ++{203, 64, 94}, ++{214, 61, 99}, ++{225, 57, 104}, ++{237, 53, 109}, ++{243, 51, 111}, ++{183, 72, 84}, ++{188, 71, 87}, ++{196, 68, 90}, ++{206, 65, 95}, ++{216, 62, 100}, ++{227, 58, 104}, ++{239, 54, 109}, ++{245, 51, 112}, ++{186, 74, 85}, ++{191, 72, 88}, ++{199, 70, 91}, ++{208, 67, 96}, ++{218, 63, 100}, ++{229, 59, 105}, ++{241, 55, 110}, ++{247, 52, 112}, ++{188, 76, 86}, ++{194, 74, 89}, ++{201, 71, 92}, ++{210, 68, 96}, ++{221, 64, 101}, ++{231, 60, 106}, ++{243, 56, 110}, ++{249, 53, 113}, ++{191, 77, 87}, ++{196, 75, 90}, ++{204, 73, 93}, ++{213, 69, 97}, ++{223, 65, 102}, ++{234, 61, 106}, ++{245, 57, 111}, ++{251, 54, 113}, ++{194, 79, 88}, ++{199, 77, 91}, ++{206, 74, 94}, ++{215, 70, 98}, ++{225, 66, 102}, ++{236, 62, 107}, ++{247, 57, 111}, ++{253, 55, 114}, ++{197, 80, 90}, ++{202, 78, 92}, ++{209, 75, 95}, ++{218, 72, 99}, ++{228, 67, 103}, ++{238, 63, 107}, ++{249, 58, 112}, ++{255, 56, 114}, ++{200, 82, 91}, ++{205, 80, 93}, ++{212, 76, 96}, ++{221, 73, 100}, ++{230, 69, 104}, ++{240, 64, 108}, ++{251, 59, 112}, ++{255, 57, 115}, ++{203, 83, 92}, ++{208, 81, 94}, ++{215, 78, 97}, ++{223, 74, 101}, ++{233, 70, 105}, ++{243, 65, 109}, ++{253, 60, 113}, ++{255, 58, 115}, ++{206, 84, 93}, ++{211, 82, 95}, ++{218, 79, 98}, ++{226, 75, 101}, ++{235, 71, 105}, ++{245, 66, 109}, ++{255, 61, 114}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{219, 79, 98}, ++{227, 76, 102}, ++{236, 71, 106}, ++{246, 67, 110}, ++{255, 62, 114}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{219, 79, 98}, ++{227, 76, 102}, ++{236, 71, 106}, ++{246, 67, 110}, ++{255, 62, 114}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{219, 79, 98}, ++{227, 76, 102}, ++{236, 71, 106}, ++{246, 67, 110}, ++{255, 62, 114}, ++{255, 59, 116}, ++{208, 85, 93}, ++{212, 83, 95}, ++{219, 79, 98}, ++{227, 76, 102}, ++{236, 71, 106}, ++{246, 67, 110}, ++{255, 62, 114}, ++{255, 59, 116}, ++{152, 43, 67}, ++{159, 45, 71}, ++{170, 46, 77}, ++{182, 46, 83}, ++{194, 45, 89}, ++{207, 43, 95}, ++{220, 41, 101}, ++{227, 39, 104}, ++{152, 43, 67}, ++{160, 45, 71}, ++{170, 46, 77}, ++{182, 46, 83}, ++{194, 45, 89}, ++{207, 43, 95}, ++{221, 41, 101}, ++{227, 39, 104}, ++{153, 44, 68}, ++{160, 45, 72}, ++{170, 46, 77}, ++{182, 46, 83}, ++{195, 45, 89}, ++{208, 43, 96}, ++{221, 41, 101}, ++{227, 39, 104}, ++{153, 44, 68}, ++{161, 46, 72}, ++{171, 47, 77}, ++{183, 47, 83}, ++{195, 46, 90}, ++{208, 44, 96}, ++{221, 41, 102}, ++{228, 40, 104}, ++{154, 45, 68}, ++{161, 47, 72}, ++{171, 47, 78}, ++{183, 47, 84}, ++{196, 46, 90}, ++{209, 44, 96}, ++{222, 41, 102}, ++{228, 40, 105}, ++{155, 47, 69}, ++{162, 48, 73}, ++{172, 48, 78}, ++{184, 48, 84}, ++{196, 47, 90}, ++{209, 44, 96}, ++{222, 42, 102}, ++{229, 40, 105}, ++{157, 48, 70}, ++{164, 49, 73}, ++{173, 49, 79}, ++{185, 49, 84}, ++{197, 47, 90}, ++{210, 45, 96}, ++{223, 42, 102}, ++{229, 41, 105}, ++{158, 49, 70}, ++{165, 50, 74}, ++{175, 50, 79}, ++{186, 49, 85}, ++{198, 48, 91}, ++{211, 46, 97}, ++{224, 43, 102}, ++{230, 41, 105}, ++{160, 51, 71}, ++{166, 51, 75}, ++{176, 51, 80}, ++{187, 50, 85}, ++{199, 49, 91}, ++{212, 46, 97}, ++{225, 43, 103}, ++{231, 42, 105}, ++{161, 53, 72}, ++{168, 53, 75}, ++{177, 53, 80}, ++{189, 51, 86}, ++{201, 50, 92}, ++{213, 47, 97}, ++{226, 44, 103}, ++{232, 42, 106}, ++{163, 54, 73}, ++{170, 54, 76}, ++{179, 54, 81}, ++{190, 53, 87}, ++{202, 50, 92}, ++{214, 48, 98}, ++{227, 45, 103}, ++{233, 43, 106}, ++{165, 56, 74}, ++{172, 56, 77}, ++{181, 55, 82}, ++{192, 54, 87}, ++{203, 51, 93}, ++{216, 49, 98}, ++{228, 45, 104}, ++{234, 44, 106}, ++{167, 58, 75}, ++{174, 58, 78}, ++{183, 57, 83}, ++{193, 55, 88}, ++{205, 52, 93}, ++{217, 49, 99}, ++{229, 46, 104}, ++{236, 44, 107}, ++{170, 60, 76}, ++{176, 59, 79}, ++{185, 58, 83}, ++{195, 56, 88}, ++{206, 53, 94}, ++{218, 50, 99}, ++{231, 47, 104}, ++{237, 45, 107}, ++{172, 62, 77}, ++{178, 61, 80}, ++{187, 59, 84}, ++{197, 57, 89}, ++{208, 55, 94}, ++{220, 51, 100}, ++{232, 48, 105}, ++{238, 46, 107}, ++{174, 63, 78}, ++{180, 62, 81}, ++{189, 61, 85}, ++{199, 58, 90}, ++{210, 56, 95}, ++{222, 52, 100}, ++{234, 49, 105}, ++{240, 47, 108}, ++{177, 65, 79}, ++{183, 64, 82}, ++{191, 62, 86}, ++{201, 60, 91}, ++{212, 57, 96}, ++{223, 53, 101}, ++{235, 50, 106}, ++{241, 48, 108}, ++{180, 67, 80}, ++{185, 66, 83}, ++{193, 64, 87}, ++{203, 61, 91}, ++{214, 58, 96}, ++{225, 54, 101}, ++{237, 50, 106}, ++{243, 48, 109}, ++{182, 69, 81}, ++{188, 67, 84}, ++{196, 65, 88}, ++{205, 62, 92}, ++{216, 59, 97}, ++{227, 55, 102}, ++{239, 51, 107}, ++{245, 49, 109}, ++{185, 70, 82}, ++{190, 69, 85}, ++{198, 67, 89}, ++{208, 64, 93}, ++{218, 60, 98}, ++{229, 56, 103}, ++{241, 52, 107}, ++{246, 50, 110}, ++{188, 72, 83}, ++{193, 70, 86}, ++{201, 68, 90}, ++{210, 65, 94}, ++{220, 61, 98}, ++{231, 57, 103}, ++{242, 53, 108}, ++{248, 51, 110}, ++{190, 74, 84}, ++{196, 72, 87}, ++{203, 69, 90}, ++{212, 66, 95}, ++{222, 62, 99}, ++{233, 58, 104}, ++{244, 54, 108}, ++{250, 52, 111}, ++{193, 75, 86}, ++{198, 73, 88}, ++{206, 71, 91}, ++{215, 67, 95}, ++{225, 64, 100}, ++{235, 60, 104}, ++{246, 55, 109}, ++{252, 53, 111}, ++{196, 77, 87}, ++{201, 75, 89}, ++{208, 72, 92}, ++{217, 69, 96}, ++{227, 65, 101}, ++{237, 61, 105}, ++{248, 56, 110}, ++{254, 54, 112}, ++{199, 78, 88}, ++{204, 76, 90}, ++{211, 73, 93}, ++{220, 70, 97}, ++{229, 66, 101}, ++{240, 62, 106}, ++{251, 57, 110}, ++{255, 55, 112}, ++{202, 80, 89}, ++{207, 78, 91}, ++{214, 75, 94}, ++{222, 71, 98}, ++{232, 67, 102}, ++{242, 63, 106}, ++{253, 58, 111}, ++{255, 56, 113}, ++{205, 81, 90}, ++{210, 79, 92}, ++{217, 76, 95}, ++{225, 72, 99}, ++{234, 68, 103}, ++{244, 64, 107}, ++{255, 59, 111}, ++{255, 57, 113}, ++{208, 82, 91}, ++{213, 80, 93}, ++{219, 77, 96}, ++{228, 73, 100}, ++{237, 69, 104}, ++{247, 65, 108}, ++{255, 60, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 94}, ++{221, 78, 97}, ++{229, 74, 100}, ++{238, 70, 104}, ++{248, 65, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 94}, ++{221, 78, 97}, ++{229, 74, 100}, ++{238, 70, 104}, ++{248, 65, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 94}, ++{221, 78, 97}, ++{229, 74, 100}, ++{238, 70, 104}, ++{248, 65, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{214, 81, 94}, ++{221, 78, 97}, ++{229, 74, 100}, ++{238, 70, 104}, ++{248, 65, 108}, ++{255, 61, 112}, ++{255, 58, 114}, ++{155, 41, 66}, ++{162, 42, 70}, ++{172, 44, 75}, ++{184, 44, 81}, ++{196, 43, 87}, ++{209, 42, 94}, ++{222, 39, 99}, ++{229, 38, 102}, ++{155, 41, 66}, ++{162, 43, 70}, ++{172, 44, 75}, ++{184, 44, 81}, ++{196, 43, 88}, ++{209, 42, 94}, ++{222, 39, 99}, ++{229, 38, 102}, ++{155, 41, 66}, ++{162, 43, 70}, ++{173, 44, 75}, ++{184, 44, 81}, ++{197, 44, 88}, ++{210, 42, 94}, ++{223, 39, 100}, ++{229, 38, 102}, ++{156, 42, 66}, ++{163, 44, 70}, ++{173, 45, 76}, ++{185, 45, 82}, ++{197, 44, 88}, ++{210, 42, 94}, ++{223, 40, 100}, ++{229, 38, 103}, ++{157, 43, 67}, ++{164, 44, 71}, ++{174, 45, 76}, ++{185, 45, 82}, ++{198, 44, 88}, ++{210, 42, 94}, ++{223, 40, 100}, ++{230, 39, 103}, ++{158, 44, 67}, ++{165, 45, 71}, ++{175, 46, 76}, ++{186, 46, 82}, ++{198, 45, 88}, ++{211, 43, 94}, ++{224, 40, 100}, ++{230, 39, 103}, ++{159, 46, 68}, ++{166, 47, 72}, ++{176, 47, 77}, ++{187, 47, 83}, ++{199, 46, 89}, ++{212, 43, 95}, ++{225, 41, 100}, ++{231, 39, 103}, ++{161, 47, 69}, ++{167, 48, 72}, ++{177, 48, 77}, ++{188, 48, 83}, ++{200, 46, 89}, ++{213, 44, 95}, ++{226, 41, 101}, ++{232, 40, 103}, ++{162, 49, 69}, ++{169, 49, 73}, ++{178, 49, 78}, ++{189, 49, 84}, ++{201, 47, 89}, ++{214, 45, 95}, ++{226, 42, 101}, ++{233, 40, 104}, ++{164, 50, 70}, ++{170, 51, 74}, ++{180, 51, 79}, ++{191, 50, 84}, ++{203, 48, 90}, ++{215, 45, 96}, ++{227, 43, 101}, ++{234, 41, 104}, ++{166, 52, 71}, ++{172, 52, 74}, ++{181, 52, 79}, ++{192, 51, 85}, ++{204, 49, 90}, ++{216, 46, 96}, ++{229, 43, 101}, ++{235, 42, 104}, ++{168, 54, 72}, ++{174, 54, 75}, ++{183, 53, 80}, ++{194, 52, 85}, ++{205, 50, 91}, ++{217, 47, 96}, ++{230, 44, 102}, ++{236, 42, 105}, ++{170, 56, 73}, ++{176, 55, 76}, ++{185, 55, 81}, ++{195, 53, 86}, ++{207, 51, 91}, ++{219, 48, 97}, ++{231, 45, 102}, ++{237, 43, 105}, ++{172, 57, 74}, ++{178, 57, 77}, ++{187, 56, 82}, ++{197, 54, 87}, ++{208, 52, 92}, ++{220, 49, 97}, ++{232, 46, 103}, ++{239, 44, 105}, ++{174, 59, 75}, ++{180, 59, 78}, ++{189, 57, 82}, ++{199, 55, 87}, ++{210, 53, 93}, ++{222, 50, 98}, ++{234, 46, 103}, ++{240, 45, 106}, ++{177, 61, 76}, ++{182, 60, 79}, ++{191, 59, 83}, ++{201, 57, 88}, ++{212, 54, 93}, ++{223, 51, 98}, ++{235, 47, 104}, ++{241, 45, 106}, ++{179, 63, 77}, ++{185, 62, 80}, ++{193, 60, 84}, ++{203, 58, 89}, ++{214, 55, 94}, ++{225, 52, 99}, ++{237, 48, 104}, ++{243, 46, 107}, ++{182, 65, 78}, ++{187, 64, 81}, ++{195, 62, 85}, ++{205, 59, 90}, ++{216, 56, 95}, ++{227, 53, 100}, ++{239, 49, 105}, ++{245, 47, 107}, ++{184, 66, 79}, ++{190, 65, 82}, ++{198, 63, 86}, ++{207, 61, 90}, ++{218, 57, 95}, ++{229, 54, 100}, ++{240, 50, 105}, ++{246, 48, 107}, ++{187, 68, 80}, ++{192, 67, 83}, ++{200, 65, 87}, ++{209, 62, 91}, ++{220, 59, 96}, ++{231, 55, 101}, ++{242, 51, 106}, ++{248, 49, 108}, ++{190, 70, 82}, ++{195, 68, 84}, ++{203, 66, 88}, ++{212, 63, 92}, ++{222, 60, 97}, ++{233, 56, 101}, ++{244, 52, 106}, ++{250, 50, 108}, ++{193, 72, 83}, ++{198, 70, 85}, ++{205, 68, 89}, ++{214, 64, 93}, ++{224, 61, 97}, ++{235, 57, 102}, ++{246, 53, 107}, ++{252, 51, 109}, ++{195, 73, 84}, ++{200, 71, 86}, ++{208, 69, 90}, ++{217, 66, 94}, ++{226, 62, 98}, ++{237, 58, 103}, ++{248, 54, 107}, ++{254, 52, 110}, ++{198, 75, 85}, ++{203, 73, 87}, ++{210, 70, 91}, ++{219, 67, 95}, ++{229, 63, 99}, ++{239, 59, 103}, ++{250, 55, 108}, ++{255, 53, 110}, ++{201, 76, 86}, ++{206, 74, 88}, ++{213, 72, 92}, ++{222, 68, 95}, ++{231, 64, 100}, ++{241, 60, 104}, ++{252, 56, 108}, ++{255, 54, 111}, ++{204, 78, 87}, ++{209, 76, 89}, ++{216, 73, 92}, ++{224, 69, 96}, ++{234, 66, 100}, ++{244, 61, 105}, ++{254, 57, 109}, ++{255, 55, 111}, ++{207, 79, 88}, ++{212, 77, 90}, ++{218, 74, 93}, ++{227, 71, 97}, ++{236, 67, 101}, ++{246, 62, 105}, ++{255, 58, 110}, ++{255, 56, 112}, ++{210, 80, 89}, ++{215, 78, 91}, ++{221, 75, 94}, ++{229, 72, 98}, ++{238, 68, 102}, ++{248, 63, 106}, ++{255, 59, 110}, ++{255, 57, 112}, ++{212, 81, 90}, ++{216, 79, 92}, ++{223, 76, 95}, ++{231, 72, 98}, ++{240, 68, 102}, ++{250, 64, 106}, ++{255, 59, 110}, ++{255, 57, 113}, ++{212, 81, 90}, ++{216, 79, 92}, ++{223, 76, 95}, ++{231, 72, 98}, ++{240, 68, 102}, ++{250, 64, 106}, ++{255, 59, 110}, ++{255, 57, 113}, ++{212, 81, 90}, ++{216, 79, 92}, ++{223, 76, 95}, ++{231, 72, 98}, ++{240, 68, 102}, ++{250, 64, 106}, ++{255, 59, 110}, ++{255, 57, 113}, ++{212, 81, 90}, ++{216, 79, 92}, ++{223, 76, 95}, ++{231, 72, 98}, ++{240, 68, 102}, ++{250, 64, 106}, ++{255, 59, 110}, ++{255, 57, 113}, ++{156, 40, 65}, ++{163, 41, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 42, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 69}, ++{174, 43, 75}, ++{185, 44, 81}, ++{198, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 102}, ++{157, 41, 66}, ++{164, 43, 69}, ++{174, 44, 75}, ++{186, 44, 81}, ++{198, 43, 87}, ++{211, 41, 93}, ++{224, 39, 99}, ++{230, 38, 102}, ++{158, 42, 66}, ++{165, 43, 70}, ++{175, 44, 75}, ++{186, 44, 81}, ++{199, 44, 87}, ++{211, 42, 93}, ++{224, 39, 99}, ++{231, 38, 102}, ++{159, 43, 66}, ++{166, 44, 70}, ++{176, 45, 76}, ++{187, 45, 81}, ++{199, 44, 87}, ++{212, 42, 93}, ++{225, 40, 99}, ++{231, 38, 102}, ++{161, 45, 67}, ++{167, 46, 71}, ++{177, 46, 76}, ++{188, 46, 82}, ++{200, 45, 88}, ++{213, 43, 94}, ++{226, 40, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{169, 47, 71}, ++{178, 47, 76}, ++{189, 47, 82}, ++{201, 45, 88}, ++{214, 43, 94}, ++{226, 41, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{170, 48, 72}, ++{179, 48, 77}, ++{190, 48, 83}, ++{202, 46, 88}, ++{215, 44, 94}, ++{227, 41, 100}, ++{234, 40, 103}, ++{165, 49, 69}, ++{172, 50, 73}, ++{181, 50, 78}, ++{192, 49, 83}, ++{204, 47, 89}, ++{216, 45, 95}, ++{228, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{173, 51, 74}, ++{182, 51, 78}, ++{193, 50, 84}, ++{205, 48, 89}, ++{217, 46, 95}, ++{229, 43, 101}, ++{236, 41, 103}, ++{169, 53, 71}, ++{175, 53, 74}, ++{184, 52, 79}, ++{195, 51, 84}, ++{206, 49, 90}, ++{218, 46, 95}, ++{231, 43, 101}, ++{237, 42, 104}, ++{171, 55, 72}, ++{177, 54, 75}, ++{186, 54, 80}, ++{196, 52, 85}, ++{208, 50, 91}, ++{220, 47, 96}, ++{232, 44, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{179, 56, 76}, ++{188, 55, 81}, ++{198, 53, 86}, ++{209, 51, 91}, ++{221, 48, 96}, ++{233, 45, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{181, 58, 77}, ++{190, 56, 82}, ++{200, 55, 86}, ++{211, 52, 92}, ++{223, 49, 97}, ++{235, 46, 102}, ++{241, 44, 105}, ++{178, 60, 75}, ++{184, 59, 78}, ++{192, 58, 82}, ++{202, 56, 87}, ++{213, 53, 92}, ++{224, 50, 98}, ++{236, 47, 103}, ++{242, 45, 105}, ++{180, 62, 76}, ++{186, 61, 79}, ++{194, 59, 83}, ++{204, 57, 88}, ++{215, 54, 93}, ++{226, 51, 98}, ++{238, 48, 103}, ++{244, 46, 106}, ++{183, 64, 77}, ++{188, 63, 80}, ++{196, 61, 84}, ++{206, 58, 89}, ++{217, 55, 94}, ++{228, 52, 99}, ++{239, 48, 104}, ++{245, 47, 106}, ++{185, 65, 79}, ++{191, 64, 81}, ++{199, 62, 85}, ++{208, 60, 90}, ++{219, 57, 94}, ++{230, 53, 99}, ++{241, 49, 104}, ++{247, 47, 107}, ++{188, 67, 80}, ++{193, 66, 82}, ++{201, 64, 86}, ++{210, 61, 90}, ++{221, 58, 95}, ++{232, 54, 100}, ++{243, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{196, 67, 83}, ++{203, 65, 87}, ++{213, 62, 91}, ++{223, 59, 96}, ++{234, 55, 100}, ++{245, 51, 105}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 84}, ++{206, 67, 88}, ++{215, 64, 92}, ++{225, 60, 96}, ++{236, 56, 101}, ++{247, 52, 106}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 70, 85}, ++{209, 68, 89}, ++{217, 65, 93}, ++{227, 61, 97}, ++{238, 57, 102}, ++{249, 53, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{204, 72, 86}, ++{211, 69, 90}, ++{220, 66, 94}, ++{230, 63, 98}, ++{240, 59, 102}, ++{251, 54, 107}, ++{255, 52, 109}, ++{202, 75, 85}, ++{207, 73, 87}, ++{214, 71, 91}, ++{222, 67, 95}, ++{232, 64, 99}, ++{242, 60, 103}, ++{253, 55, 108}, ++{255, 53, 110}, ++{205, 77, 86}, ++{210, 75, 88}, ++{217, 72, 92}, ++{225, 69, 95}, ++{234, 65, 99}, ++{244, 61, 104}, ++{255, 56, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{213, 76, 89}, ++{219, 73, 93}, ++{228, 70, 96}, ++{237, 66, 100}, ++{247, 62, 104}, ++{255, 57, 109}, ++{255, 55, 111}, ++{211, 79, 89}, ++{216, 78, 91}, ++{222, 75, 94}, ++{230, 71, 97}, ++{239, 67, 101}, ++{249, 63, 105}, ++{255, 58, 109}, ++{255, 56, 111}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{156, 40, 65}, ++{163, 41, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 42, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 69}, ++{174, 43, 75}, ++{185, 44, 81}, ++{198, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 102}, ++{157, 41, 66}, ++{164, 43, 69}, ++{174, 44, 75}, ++{186, 44, 81}, ++{198, 43, 87}, ++{211, 41, 93}, ++{224, 39, 99}, ++{230, 38, 102}, ++{158, 42, 66}, ++{165, 43, 70}, ++{175, 44, 75}, ++{186, 44, 81}, ++{199, 44, 87}, ++{211, 42, 93}, ++{224, 39, 99}, ++{231, 38, 102}, ++{159, 43, 66}, ++{166, 44, 70}, ++{176, 45, 76}, ++{187, 45, 81}, ++{199, 44, 87}, ++{212, 42, 93}, ++{225, 40, 99}, ++{231, 38, 102}, ++{161, 45, 67}, ++{167, 46, 71}, ++{177, 46, 76}, ++{188, 46, 82}, ++{200, 45, 88}, ++{213, 43, 94}, ++{226, 40, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{169, 47, 71}, ++{178, 47, 76}, ++{189, 47, 82}, ++{201, 45, 88}, ++{214, 43, 94}, ++{226, 41, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{170, 48, 72}, ++{179, 48, 77}, ++{190, 48, 83}, ++{202, 46, 88}, ++{215, 44, 94}, ++{227, 41, 100}, ++{234, 40, 103}, ++{165, 49, 69}, ++{172, 50, 73}, ++{181, 50, 78}, ++{192, 49, 83}, ++{204, 47, 89}, ++{216, 45, 95}, ++{228, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{173, 51, 74}, ++{182, 51, 78}, ++{193, 50, 84}, ++{205, 48, 89}, ++{217, 46, 95}, ++{229, 43, 101}, ++{236, 41, 103}, ++{169, 53, 71}, ++{175, 53, 74}, ++{184, 52, 79}, ++{195, 51, 84}, ++{206, 49, 90}, ++{218, 46, 95}, ++{231, 43, 101}, ++{237, 42, 104}, ++{171, 55, 72}, ++{177, 54, 75}, ++{186, 54, 80}, ++{196, 52, 85}, ++{208, 50, 91}, ++{220, 47, 96}, ++{232, 44, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{179, 56, 76}, ++{188, 55, 81}, ++{198, 53, 86}, ++{209, 51, 91}, ++{221, 48, 96}, ++{233, 45, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{181, 58, 77}, ++{190, 56, 82}, ++{200, 55, 86}, ++{211, 52, 92}, ++{223, 49, 97}, ++{235, 46, 102}, ++{241, 44, 105}, ++{178, 60, 75}, ++{184, 59, 78}, ++{192, 58, 82}, ++{202, 56, 87}, ++{213, 53, 92}, ++{224, 50, 98}, ++{236, 47, 103}, ++{242, 45, 105}, ++{180, 62, 76}, ++{186, 61, 79}, ++{194, 59, 83}, ++{204, 57, 88}, ++{215, 54, 93}, ++{226, 51, 98}, ++{238, 48, 103}, ++{244, 46, 106}, ++{183, 64, 77}, ++{188, 63, 80}, ++{196, 61, 84}, ++{206, 58, 89}, ++{217, 55, 94}, ++{228, 52, 99}, ++{239, 48, 104}, ++{245, 47, 106}, ++{185, 65, 79}, ++{191, 64, 81}, ++{199, 62, 85}, ++{208, 60, 90}, ++{219, 57, 94}, ++{230, 53, 99}, ++{241, 49, 104}, ++{247, 47, 107}, ++{188, 67, 80}, ++{193, 66, 82}, ++{201, 64, 86}, ++{210, 61, 90}, ++{221, 58, 95}, ++{232, 54, 100}, ++{243, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{196, 67, 83}, ++{203, 65, 87}, ++{213, 62, 91}, ++{223, 59, 96}, ++{234, 55, 100}, ++{245, 51, 105}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 84}, ++{206, 67, 88}, ++{215, 64, 92}, ++{225, 60, 96}, ++{236, 56, 101}, ++{247, 52, 106}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 70, 85}, ++{209, 68, 89}, ++{217, 65, 93}, ++{227, 61, 97}, ++{238, 57, 102}, ++{249, 53, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{204, 72, 86}, ++{211, 69, 90}, ++{220, 66, 94}, ++{230, 63, 98}, ++{240, 59, 102}, ++{251, 54, 107}, ++{255, 52, 109}, ++{202, 75, 85}, ++{207, 73, 87}, ++{214, 71, 91}, ++{222, 67, 95}, ++{232, 64, 99}, ++{242, 60, 103}, ++{253, 55, 108}, ++{255, 53, 110}, ++{205, 77, 86}, ++{210, 75, 88}, ++{217, 72, 92}, ++{225, 69, 95}, ++{234, 65, 99}, ++{244, 61, 104}, ++{255, 56, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{213, 76, 89}, ++{219, 73, 93}, ++{228, 70, 96}, ++{237, 66, 100}, ++{247, 62, 104}, ++{255, 57, 109}, ++{255, 55, 111}, ++{211, 79, 89}, ++{216, 78, 91}, ++{222, 75, 94}, ++{230, 71, 97}, ++{239, 67, 101}, ++{249, 63, 105}, ++{255, 58, 109}, ++{255, 56, 111}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{156, 40, 65}, ++{163, 41, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 42, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 69}, ++{174, 43, 75}, ++{185, 44, 81}, ++{198, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 102}, ++{157, 41, 66}, ++{164, 43, 69}, ++{174, 44, 75}, ++{186, 44, 81}, ++{198, 43, 87}, ++{211, 41, 93}, ++{224, 39, 99}, ++{230, 38, 102}, ++{158, 42, 66}, ++{165, 43, 70}, ++{175, 44, 75}, ++{186, 44, 81}, ++{199, 44, 87}, ++{211, 42, 93}, ++{224, 39, 99}, ++{231, 38, 102}, ++{159, 43, 66}, ++{166, 44, 70}, ++{176, 45, 76}, ++{187, 45, 81}, ++{199, 44, 87}, ++{212, 42, 93}, ++{225, 40, 99}, ++{231, 38, 102}, ++{161, 45, 67}, ++{167, 46, 71}, ++{177, 46, 76}, ++{188, 46, 82}, ++{200, 45, 88}, ++{213, 43, 94}, ++{226, 40, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{169, 47, 71}, ++{178, 47, 76}, ++{189, 47, 82}, ++{201, 45, 88}, ++{214, 43, 94}, ++{226, 41, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{170, 48, 72}, ++{179, 48, 77}, ++{190, 48, 83}, ++{202, 46, 88}, ++{215, 44, 94}, ++{227, 41, 100}, ++{234, 40, 103}, ++{165, 49, 69}, ++{172, 50, 73}, ++{181, 50, 78}, ++{192, 49, 83}, ++{204, 47, 89}, ++{216, 45, 95}, ++{228, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{173, 51, 74}, ++{182, 51, 78}, ++{193, 50, 84}, ++{205, 48, 89}, ++{217, 46, 95}, ++{229, 43, 101}, ++{236, 41, 103}, ++{169, 53, 71}, ++{175, 53, 74}, ++{184, 52, 79}, ++{195, 51, 84}, ++{206, 49, 90}, ++{218, 46, 95}, ++{231, 43, 101}, ++{237, 42, 104}, ++{171, 55, 72}, ++{177, 54, 75}, ++{186, 54, 80}, ++{196, 52, 85}, ++{208, 50, 91}, ++{220, 47, 96}, ++{232, 44, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{179, 56, 76}, ++{188, 55, 81}, ++{198, 53, 86}, ++{209, 51, 91}, ++{221, 48, 96}, ++{233, 45, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{181, 58, 77}, ++{190, 56, 82}, ++{200, 55, 86}, ++{211, 52, 92}, ++{223, 49, 97}, ++{235, 46, 102}, ++{241, 44, 105}, ++{178, 60, 75}, ++{184, 59, 78}, ++{192, 58, 82}, ++{202, 56, 87}, ++{213, 53, 92}, ++{224, 50, 98}, ++{236, 47, 103}, ++{242, 45, 105}, ++{180, 62, 76}, ++{186, 61, 79}, ++{194, 59, 83}, ++{204, 57, 88}, ++{215, 54, 93}, ++{226, 51, 98}, ++{238, 48, 103}, ++{244, 46, 106}, ++{183, 64, 77}, ++{188, 63, 80}, ++{196, 61, 84}, ++{206, 58, 89}, ++{217, 55, 94}, ++{228, 52, 99}, ++{239, 48, 104}, ++{245, 47, 106}, ++{185, 65, 79}, ++{191, 64, 81}, ++{199, 62, 85}, ++{208, 60, 90}, ++{219, 57, 94}, ++{230, 53, 99}, ++{241, 49, 104}, ++{247, 47, 107}, ++{188, 67, 80}, ++{193, 66, 82}, ++{201, 64, 86}, ++{210, 61, 90}, ++{221, 58, 95}, ++{232, 54, 100}, ++{243, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{196, 67, 83}, ++{203, 65, 87}, ++{213, 62, 91}, ++{223, 59, 96}, ++{234, 55, 100}, ++{245, 51, 105}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 84}, ++{206, 67, 88}, ++{215, 64, 92}, ++{225, 60, 96}, ++{236, 56, 101}, ++{247, 52, 106}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 70, 85}, ++{209, 68, 89}, ++{217, 65, 93}, ++{227, 61, 97}, ++{238, 57, 102}, ++{249, 53, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{204, 72, 86}, ++{211, 69, 90}, ++{220, 66, 94}, ++{230, 63, 98}, ++{240, 59, 102}, ++{251, 54, 107}, ++{255, 52, 109}, ++{202, 75, 85}, ++{207, 73, 87}, ++{214, 71, 91}, ++{222, 67, 95}, ++{232, 64, 99}, ++{242, 60, 103}, ++{253, 55, 108}, ++{255, 53, 110}, ++{205, 77, 86}, ++{210, 75, 88}, ++{217, 72, 92}, ++{225, 69, 95}, ++{234, 65, 99}, ++{244, 61, 104}, ++{255, 56, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{213, 76, 89}, ++{219, 73, 93}, ++{228, 70, 96}, ++{237, 66, 100}, ++{247, 62, 104}, ++{255, 57, 109}, ++{255, 55, 111}, ++{211, 79, 89}, ++{216, 78, 91}, ++{222, 75, 94}, ++{230, 71, 97}, ++{239, 67, 101}, ++{249, 63, 105}, ++{255, 58, 109}, ++{255, 56, 111}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{156, 40, 65}, ++{163, 41, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 42, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{156, 40, 65}, ++{163, 42, 69}, ++{173, 43, 74}, ++{185, 43, 80}, ++{197, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 69}, ++{174, 43, 75}, ++{185, 44, 81}, ++{198, 43, 87}, ++{210, 41, 93}, ++{223, 39, 99}, ++{230, 37, 102}, ++{157, 41, 66}, ++{164, 43, 69}, ++{174, 44, 75}, ++{186, 44, 81}, ++{198, 43, 87}, ++{211, 41, 93}, ++{224, 39, 99}, ++{230, 38, 102}, ++{158, 42, 66}, ++{165, 43, 70}, ++{175, 44, 75}, ++{186, 44, 81}, ++{199, 44, 87}, ++{211, 42, 93}, ++{224, 39, 99}, ++{231, 38, 102}, ++{159, 43, 66}, ++{166, 44, 70}, ++{176, 45, 76}, ++{187, 45, 81}, ++{199, 44, 87}, ++{212, 42, 93}, ++{225, 40, 99}, ++{231, 38, 102}, ++{161, 45, 67}, ++{167, 46, 71}, ++{177, 46, 76}, ++{188, 46, 82}, ++{200, 45, 88}, ++{213, 43, 94}, ++{226, 40, 99}, ++{232, 39, 102}, ++{162, 46, 68}, ++{169, 47, 71}, ++{178, 47, 76}, ++{189, 47, 82}, ++{201, 45, 88}, ++{214, 43, 94}, ++{226, 41, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{170, 48, 72}, ++{179, 48, 77}, ++{190, 48, 83}, ++{202, 46, 88}, ++{215, 44, 94}, ++{227, 41, 100}, ++{234, 40, 103}, ++{165, 49, 69}, ++{172, 50, 73}, ++{181, 50, 78}, ++{192, 49, 83}, ++{204, 47, 89}, ++{216, 45, 95}, ++{228, 42, 100}, ++{235, 40, 103}, ++{167, 51, 70}, ++{173, 51, 74}, ++{182, 51, 78}, ++{193, 50, 84}, ++{205, 48, 89}, ++{217, 46, 95}, ++{229, 43, 101}, ++{236, 41, 103}, ++{169, 53, 71}, ++{175, 53, 74}, ++{184, 52, 79}, ++{195, 51, 84}, ++{206, 49, 90}, ++{218, 46, 95}, ++{231, 43, 101}, ++{237, 42, 104}, ++{171, 55, 72}, ++{177, 54, 75}, ++{186, 54, 80}, ++{196, 52, 85}, ++{208, 50, 91}, ++{220, 47, 96}, ++{232, 44, 101}, ++{238, 42, 104}, ++{173, 56, 73}, ++{179, 56, 76}, ++{188, 55, 81}, ++{198, 53, 86}, ++{209, 51, 91}, ++{221, 48, 96}, ++{233, 45, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{181, 58, 77}, ++{190, 56, 82}, ++{200, 55, 86}, ++{211, 52, 92}, ++{223, 49, 97}, ++{235, 46, 102}, ++{241, 44, 105}, ++{178, 60, 75}, ++{184, 59, 78}, ++{192, 58, 82}, ++{202, 56, 87}, ++{213, 53, 92}, ++{224, 50, 98}, ++{236, 47, 103}, ++{242, 45, 105}, ++{180, 62, 76}, ++{186, 61, 79}, ++{194, 59, 83}, ++{204, 57, 88}, ++{215, 54, 93}, ++{226, 51, 98}, ++{238, 48, 103}, ++{244, 46, 106}, ++{183, 64, 77}, ++{188, 63, 80}, ++{196, 61, 84}, ++{206, 58, 89}, ++{217, 55, 94}, ++{228, 52, 99}, ++{239, 48, 104}, ++{245, 47, 106}, ++{185, 65, 79}, ++{191, 64, 81}, ++{199, 62, 85}, ++{208, 60, 90}, ++{219, 57, 94}, ++{230, 53, 99}, ++{241, 49, 104}, ++{247, 47, 107}, ++{188, 67, 80}, ++{193, 66, 82}, ++{201, 64, 86}, ++{210, 61, 90}, ++{221, 58, 95}, ++{232, 54, 100}, ++{243, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{196, 67, 83}, ++{203, 65, 87}, ++{213, 62, 91}, ++{223, 59, 96}, ++{234, 55, 100}, ++{245, 51, 105}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 84}, ++{206, 67, 88}, ++{215, 64, 92}, ++{225, 60, 96}, ++{236, 56, 101}, ++{247, 52, 106}, ++{252, 50, 108}, ++{196, 72, 83}, ++{201, 70, 85}, ++{209, 68, 89}, ++{217, 65, 93}, ++{227, 61, 97}, ++{238, 57, 102}, ++{249, 53, 106}, ++{254, 51, 109}, ++{199, 74, 84}, ++{204, 72, 86}, ++{211, 69, 90}, ++{220, 66, 94}, ++{230, 63, 98}, ++{240, 59, 102}, ++{251, 54, 107}, ++{255, 52, 109}, ++{202, 75, 85}, ++{207, 73, 87}, ++{214, 71, 91}, ++{222, 67, 95}, ++{232, 64, 99}, ++{242, 60, 103}, ++{253, 55, 108}, ++{255, 53, 110}, ++{205, 77, 86}, ++{210, 75, 88}, ++{217, 72, 92}, ++{225, 69, 95}, ++{234, 65, 99}, ++{244, 61, 104}, ++{255, 56, 108}, ++{255, 54, 110}, ++{208, 78, 87}, ++{213, 76, 89}, ++{219, 73, 93}, ++{228, 70, 96}, ++{237, 66, 100}, ++{247, 62, 104}, ++{255, 57, 109}, ++{255, 55, 111}, ++{211, 79, 89}, ++{216, 78, 91}, ++{222, 75, 94}, ++{230, 71, 97}, ++{239, 67, 101}, ++{249, 63, 105}, ++{255, 58, 109}, ++{255, 56, 111}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{217, 78, 91}, ++{224, 75, 94}, ++{232, 72, 98}, ++{241, 68, 101}, ++{250, 63, 105}, ++{255, 59, 110}, ++{255, 57, 112}, ++{84, 103, 121}, ++{98, 97, 126}, ++{115, 91, 132}, ++{132, 84, 137}, ++{150, 77, 142}, ++{167, 71, 147}, ++{183, 65, 151}, ++{189, 62, 152}, ++{84, 103, 121}, ++{98, 98, 126}, ++{115, 91, 132}, ++{133, 84, 137}, ++{150, 77, 142}, ++{167, 71, 147}, ++{183, 65, 151}, ++{189, 62, 152}, ++{85, 104, 121}, ++{99, 98, 127}, ++{116, 91, 132}, ++{133, 84, 138}, ++{150, 78, 142}, ++{167, 71, 147}, ++{184, 65, 151}, ++{190, 63, 152}, ++{86, 104, 122}, ++{100, 98, 127}, ++{117, 92, 132}, ++{134, 85, 138}, ++{151, 78, 142}, ++{168, 71, 147}, ++{184, 65, 151}, ++{190, 63, 152}, ++{88, 105, 122}, ++{101, 99, 127}, ++{118, 92, 133}, ++{135, 85, 138}, ++{152, 78, 142}, ++{168, 72, 147}, ++{185, 65, 151}, ++{191, 63, 152}, ++{90, 106, 123}, ++{103, 100, 127}, ++{119, 93, 133}, ++{136, 86, 138}, ++{153, 79, 142}, ++{169, 72, 147}, ++{185, 66, 151}, ++{191, 63, 152}, ++{92, 107, 123}, ++{105, 100, 128}, ++{121, 93, 133}, ++{137, 86, 138}, ++{154, 79, 143}, ++{170, 72, 147}, ++{186, 66, 151}, ++{192, 64, 152}, ++{95, 108, 124}, ++{107, 101, 128}, ++{122, 94, 133}, ++{139, 87, 138}, ++{155, 80, 143}, ++{171, 73, 147}, ++{187, 67, 151}, ++{193, 64, 152}, ++{98, 108, 124}, ++{109, 102, 129}, ++{124, 95, 133}, ++{140, 87, 138}, ++{157, 80, 143}, ++{173, 74, 147}, ++{188, 67, 151}, ++{194, 65, 152}, ++{101, 109, 125}, ++{112, 103, 129}, ++{127, 96, 134}, ++{142, 88, 138}, ++{158, 81, 143}, ++{174, 74, 147}, ++{190, 68, 151}, ++{195, 65, 152}, ++{104, 110, 126}, ++{115, 104, 130}, ++{129, 97, 134}, ++{144, 89, 139}, ++{160, 82, 143}, ++{176, 75, 147}, ++{191, 68, 151}, ++{197, 66, 152}, ++{107, 111, 126}, ++{118, 105, 130}, ++{131, 97, 134}, ++{146, 90, 139}, ++{162, 82, 143}, ++{177, 75, 147}, ++{193, 69, 151}, ++{198, 66, 152}, ++{110, 112, 127}, ++{121, 106, 131}, ++{134, 98, 135}, ++{149, 91, 139}, ++{164, 83, 143}, ++{179, 76, 147}, ++{194, 69, 151}, ++{200, 67, 152}, ++{114, 113, 128}, ++{124, 107, 131}, ++{137, 99, 135}, ++{151, 91, 139}, ++{166, 84, 143}, ++{181, 77, 147}, ++{196, 70, 151}, ++{201, 68, 152}, ++{117, 114, 128}, ++{127, 108, 132}, ++{139, 100, 135}, ++{153, 92, 140}, ++{168, 85, 144}, ++{183, 78, 147}, ++{198, 71, 151}, ++{203, 68, 152}, ++{121, 114, 129}, ++{130, 108, 132}, ++{142, 101, 136}, ++{156, 93, 140}, ++{170, 86, 144}, ++{185, 79, 148}, ++{199, 72, 151}, ++{205, 69, 153}, ++{125, 115, 130}, ++{134, 109, 133}, ++{145, 102, 136}, ++{159, 94, 140}, ++{173, 87, 144}, ++{187, 79, 148}, ++{201, 72, 151}, ++{207, 70, 153}, ++{129, 116, 130}, ++{137, 110, 133}, ++{148, 103, 137}, ++{161, 95, 140}, ++{175, 87, 144}, ++{189, 80, 148}, ++{203, 73, 151}, ++{209, 71, 153}, ++{132, 116, 131}, ++{140, 111, 134}, ++{152, 103, 137}, ++{164, 96, 141}, ++{178, 88, 144}, ++{192, 81, 148}, ++{205, 74, 151}, ++{211, 71, 153}, ++{136, 117, 132}, ++{144, 111, 134}, ++{155, 104, 137}, ++{167, 97, 141}, ++{180, 89, 145}, ++{194, 82, 148}, ++{208, 75, 152}, ++{213, 72, 153}, ++{140, 117, 132}, ++{148, 112, 135}, ++{158, 105, 138}, ++{170, 97, 141}, ++{183, 90, 145}, ++{196, 83, 148}, ++{210, 76, 152}, ++{215, 73, 153}, ++{144, 118, 133}, ++{151, 113, 135}, ++{161, 106, 138}, ++{173, 98, 142}, ++{186, 91, 145}, ++{199, 83, 148}, ++{212, 76, 152}, ++{217, 74, 153}, ++{148, 119, 133}, ++{155, 113, 136}, ++{165, 106, 139}, ++{176, 99, 142}, ++{189, 92, 145}, ++{201, 84, 149}, ++{215, 77, 152}, ++{220, 75, 153}, ++{152, 119, 134}, ++{159, 114, 136}, ++{168, 107, 139}, ++{179, 100, 142}, ++{191, 92, 145}, ++{204, 85, 149}, ++{217, 78, 152}, ++{222, 75, 153}, ++{156, 119, 134}, ++{162, 114, 137}, ++{172, 108, 139}, ++{183, 101, 142}, ++{194, 93, 146}, ++{207, 86, 149}, ++{219, 79, 152}, ++{224, 76, 153}, ++{160, 120, 135}, ++{166, 115, 137}, ++{175, 108, 140}, ++{186, 101, 143}, ++{197, 94, 146}, ++{209, 87, 149}, ++{222, 80, 152}, ++{227, 77, 153}, ++{164, 120, 136}, ++{170, 115, 137}, ++{179, 109, 140}, ++{189, 102, 143}, ++{200, 95, 146}, ++{212, 87, 149}, ++{225, 80, 152}, ++{229, 78, 154}, ++{167, 121, 136}, ++{174, 116, 138}, ++{182, 110, 140}, ++{192, 103, 143}, ++{203, 95, 146}, ++{215, 88, 149}, ++{227, 81, 153}, ++{232, 79, 154}, ++{169, 121, 136}, ++{175, 116, 138}, ++{184, 110, 141}, ++{194, 103, 143}, ++{205, 96, 146}, ++{216, 89, 150}, ++{228, 82, 153}, ++{233, 79, 154}, ++{169, 121, 136}, ++{175, 116, 138}, ++{184, 110, 141}, ++{194, 103, 143}, ++{205, 96, 146}, ++{216, 89, 150}, ++{228, 82, 153}, ++{233, 79, 154}, ++{169, 121, 136}, ++{175, 116, 138}, ++{184, 110, 141}, ++{194, 103, 143}, ++{205, 96, 146}, ++{216, 89, 150}, ++{228, 82, 153}, ++{233, 79, 154}, ++{169, 121, 136}, ++{175, 116, 138}, ++{184, 110, 141}, ++{194, 103, 143}, ++{205, 96, 146}, ++{216, 89, 150}, ++{228, 82, 153}, ++{233, 79, 154}, ++{85, 102, 120}, ++{99, 97, 125}, ++{116, 90, 131}, ++{133, 84, 136}, ++{150, 77, 141}, ++{167, 71, 146}, ++{184, 64, 150}, ++{190, 62, 151}, ++{85, 102, 120}, ++{99, 97, 125}, ++{116, 90, 131}, ++{133, 84, 136}, ++{151, 77, 141}, ++{167, 71, 146}, ++{184, 64, 150}, ++{190, 62, 151}, ++{86, 103, 120}, ++{100, 97, 125}, ++{117, 91, 131}, ++{134, 84, 137}, ++{151, 77, 141}, ++{168, 71, 146}, ++{184, 65, 150}, ++{190, 62, 151}, ++{87, 103, 120}, ++{101, 98, 126}, ++{117, 91, 131}, ++{134, 84, 137}, ++{152, 78, 141}, ++{168, 71, 146}, ++{185, 65, 150}, ++{191, 63, 151}, ++{89, 104, 121}, ++{102, 98, 126}, ++{118, 92, 131}, ++{135, 85, 137}, ++{152, 78, 142}, ++{169, 71, 146}, ++{185, 65, 150}, ++{191, 63, 151}, ++{91, 105, 121}, ++{104, 99, 126}, ++{120, 92, 132}, ++{137, 85, 137}, ++{153, 78, 142}, ++{170, 72, 146}, ++{186, 65, 150}, ++{192, 63, 151}, ++{93, 106, 122}, ++{106, 100, 127}, ++{121, 93, 132}, ++{138, 86, 137}, ++{154, 79, 142}, ++{171, 72, 146}, ++{187, 66, 150}, ++{193, 64, 151}, ++{96, 107, 123}, ++{108, 101, 127}, ++{123, 94, 132}, ++{139, 86, 137}, ++{156, 79, 142}, ++{172, 73, 146}, ++{188, 66, 150}, ++{194, 64, 151}, ++{99, 108, 123}, ++{110, 102, 128}, ++{125, 94, 132}, ++{141, 87, 137}, ++{157, 80, 142}, ++{173, 73, 146}, ++{189, 67, 150}, ++{195, 64, 152}, ++{102, 109, 124}, ++{113, 103, 128}, ++{127, 95, 133}, ++{143, 88, 138}, ++{159, 81, 142}, ++{175, 74, 146}, ++{190, 67, 150}, ++{196, 65, 152}, ++{105, 110, 125}, ++{115, 103, 129}, ++{130, 96, 133}, ++{145, 89, 138}, ++{160, 81, 142}, ++{176, 75, 146}, ++{192, 68, 150}, ++{197, 66, 152}, ++{108, 111, 125}, ++{118, 104, 129}, ++{132, 97, 134}, ++{147, 89, 138}, ++{162, 82, 142}, ++{178, 75, 146}, ++{193, 69, 150}, ++{199, 66, 152}, ++{111, 111, 126}, ++{121, 105, 130}, ++{135, 98, 134}, ++{149, 90, 138}, ++{164, 83, 143}, ++{179, 76, 147}, ++{195, 69, 150}, ++{200, 67, 152}, ++{115, 112, 127}, ++{124, 106, 130}, ++{137, 99, 134}, ++{152, 91, 139}, ++{166, 84, 143}, ++{181, 77, 147}, ++{196, 70, 150}, ++{202, 68, 152}, ++{118, 113, 127}, ++{128, 107, 131}, ++{140, 100, 135}, ++{154, 92, 139}, ++{169, 85, 143}, ++{183, 78, 147}, ++{198, 71, 151}, ++{203, 68, 152}, ++{122, 114, 128}, ++{131, 108, 131}, ++{143, 100, 135}, ++{157, 93, 139}, ++{171, 85, 143}, ++{185, 78, 147}, ++{200, 71, 151}, ++{205, 69, 152}, ++{126, 114, 129}, ++{134, 109, 132}, ++{146, 101, 135}, ++{159, 94, 139}, ++{173, 86, 143}, ++{187, 79, 147}, ++{202, 72, 151}, ++{207, 70, 152}, ++{129, 115, 129}, ++{138, 109, 132}, ++{149, 102, 136}, ++{162, 95, 140}, ++{176, 87, 143}, ++{190, 80, 147}, ++{204, 73, 151}, ++{209, 70, 152}, ++{133, 116, 130}, ++{141, 110, 133}, ++{152, 103, 136}, ++{165, 95, 140}, ++{178, 88, 144}, ++{192, 81, 147}, ++{206, 74, 151}, ++{211, 71, 152}, ++{137, 116, 131}, ++{145, 111, 133}, ++{155, 104, 137}, ++{168, 96, 140}, ++{181, 89, 144}, ++{194, 82, 148}, ++{208, 75, 151}, ++{213, 72, 152}, ++{141, 117, 131}, ++{148, 112, 134}, ++{159, 105, 137}, ++{171, 97, 141}, ++{183, 90, 144}, ++{197, 82, 148}, ++{210, 75, 151}, ++{215, 73, 152}, ++{145, 118, 132}, ++{152, 112, 134}, ++{162, 105, 137}, ++{174, 98, 141}, ++{186, 90, 144}, ++{199, 83, 148}, ++{213, 76, 151}, ++{218, 74, 152}, ++{148, 118, 133}, ++{155, 113, 135}, ++{165, 106, 138}, ++{177, 99, 141}, ++{189, 91, 145}, ++{202, 84, 148}, ++{215, 77, 151}, ++{220, 74, 153}, ++{152, 119, 133}, ++{159, 113, 135}, ++{169, 107, 138}, ++{180, 99, 141}, ++{192, 92, 145}, ++{204, 85, 148}, ++{217, 78, 151}, ++{222, 75, 153}, ++{156, 119, 134}, ++{163, 114, 136}, ++{172, 107, 139}, ++{183, 100, 142}, ++{195, 93, 145}, ++{207, 86, 148}, ++{220, 79, 152}, ++{225, 76, 153}, ++{160, 119, 134}, ++{167, 115, 136}, ++{176, 108, 139}, ++{186, 101, 142}, ++{198, 94, 145}, ++{210, 86, 149}, ++{222, 79, 152}, ++{227, 77, 153}, ++{164, 120, 135}, ++{170, 115, 137}, ++{179, 109, 139}, ++{189, 102, 142}, ++{201, 94, 146}, ++{213, 87, 149}, ++{225, 80, 152}, ++{230, 78, 153}, ++{168, 120, 135}, ++{174, 116, 137}, ++{183, 109, 140}, ++{193, 102, 143}, ++{204, 95, 146}, ++{215, 88, 149}, ++{227, 81, 152}, ++{232, 78, 153}, ++{170, 120, 136}, ++{176, 116, 138}, ++{184, 110, 140}, ++{194, 103, 143}, ++{205, 96, 146}, ++{217, 88, 149}, ++{229, 81, 152}, ++{233, 79, 153}, ++{170, 120, 136}, ++{176, 116, 138}, ++{184, 110, 140}, ++{194, 103, 143}, ++{205, 96, 146}, ++{217, 88, 149}, ++{229, 81, 152}, ++{233, 79, 153}, ++{170, 120, 136}, ++{176, 116, 138}, ++{184, 110, 140}, ++{194, 103, 143}, ++{205, 96, 146}, ++{217, 88, 149}, ++{229, 81, 152}, ++{233, 79, 153}, ++{170, 120, 136}, ++{176, 116, 138}, ++{184, 110, 140}, ++{194, 103, 143}, ++{205, 96, 146}, ++{217, 88, 149}, ++{229, 81, 152}, ++{233, 79, 153}, ++{87, 101, 118}, ++{101, 96, 123}, ++{117, 89, 129}, ++{134, 83, 135}, ++{151, 77, 140}, ++{168, 70, 145}, ++{184, 64, 149}, ++{190, 62, 150}, ++{87, 101, 118}, ++{101, 96, 123}, ++{117, 90, 129}, ++{134, 83, 135}, ++{152, 77, 140}, ++{168, 70, 145}, ++{185, 64, 149}, ++{191, 62, 150}, ++{88, 101, 118}, ++{101, 96, 124}, ++{118, 90, 129}, ++{135, 83, 135}, ++{152, 77, 140}, ++{169, 70, 145}, ++{185, 64, 149}, ++{191, 62, 150}, ++{89, 102, 118}, ++{102, 97, 124}, ++{119, 90, 130}, ++{136, 84, 135}, ++{153, 77, 140}, ++{169, 71, 145}, ++{185, 64, 149}, ++{191, 62, 150}, ++{91, 103, 119}, ++{104, 97, 124}, ++{120, 91, 130}, ++{137, 84, 135}, ++{153, 77, 140}, ++{170, 71, 145}, ++{186, 65, 149}, ++{192, 63, 150}, ++{93, 103, 119}, ++{105, 98, 124}, ++{121, 91, 130}, ++{138, 85, 135}, ++{154, 78, 140}, ++{171, 71, 145}, ++{187, 65, 149}, ++{193, 63, 150}, ++{95, 104, 120}, ++{107, 99, 125}, ++{123, 92, 130}, ++{139, 85, 135}, ++{155, 78, 140}, ++{172, 72, 145}, ++{188, 66, 149}, ++{193, 63, 150}, ++{97, 105, 121}, ++{109, 100, 125}, ++{124, 93, 131}, ++{140, 86, 136}, ++{157, 79, 140}, ++{173, 72, 145}, ++{189, 66, 149}, ++{194, 64, 150}, ++{100, 106, 121}, ++{112, 101, 126}, ++{126, 94, 131}, ++{142, 86, 136}, ++{158, 80, 141}, ++{174, 73, 145}, ++{190, 67, 149}, ++{195, 64, 150}, ++{103, 107, 122}, ++{114, 102, 126}, ++{128, 94, 131}, ++{144, 87, 136}, ++{160, 80, 141}, ++{175, 74, 145}, ++{191, 67, 149}, ++{197, 65, 150}, ++{106, 108, 123}, ++{117, 102, 127}, ++{131, 95, 132}, ++{146, 88, 136}, ++{161, 81, 141}, ++{177, 74, 145}, ++{192, 68, 149}, ++{198, 65, 151}, ++{109, 109, 124}, ++{120, 103, 127}, ++{133, 96, 132}, ++{148, 89, 137}, ++{163, 82, 141}, ++{179, 75, 145}, ++{194, 68, 149}, ++{199, 66, 151}, ++{113, 110, 124}, ++{123, 104, 128}, ++{136, 97, 132}, ++{150, 90, 137}, ++{165, 83, 141}, ++{180, 76, 145}, ++{195, 69, 149}, ++{201, 67, 151}, ++{116, 111, 125}, ++{126, 105, 129}, ++{138, 98, 133}, ++{153, 91, 137}, ++{167, 83, 141}, ++{182, 76, 146}, ++{197, 70, 149}, ++{202, 67, 151}, ++{120, 112, 126}, ++{129, 106, 129}, ++{141, 99, 133}, ++{155, 91, 137}, ++{169, 84, 142}, ++{184, 77, 146}, ++{199, 70, 149}, ++{204, 68, 151}, ++{123, 113, 127}, ++{132, 107, 130}, ++{144, 100, 134}, ++{158, 92, 138}, ++{172, 85, 142}, ++{186, 78, 146}, ++{201, 71, 150}, ++{206, 69, 151}, ++{127, 114, 127}, ++{135, 108, 130}, ++{147, 101, 134}, ++{160, 93, 138}, ++{174, 86, 142}, ++{188, 79, 146}, ++{202, 72, 150}, ++{208, 69, 151}, ++{130, 114, 128}, ++{139, 109, 131}, ++{150, 102, 134}, ++{163, 94, 138}, ++{176, 87, 142}, ++{190, 80, 146}, ++{204, 73, 150}, ++{210, 70, 151}, ++{134, 115, 129}, ++{142, 109, 131}, ++{153, 102, 135}, ++{166, 95, 139}, ++{179, 88, 143}, ++{193, 80, 146}, ++{207, 73, 150}, ++{212, 71, 151}, ++{138, 116, 129}, ++{146, 110, 132}, ++{156, 103, 135}, ++{169, 96, 139}, ++{182, 88, 143}, ++{195, 81, 146}, ++{209, 74, 150}, ++{214, 72, 151}, ++{142, 116, 130}, ++{149, 111, 133}, ++{160, 104, 136}, ++{171, 97, 139}, ++{184, 89, 143}, ++{198, 82, 147}, ++{211, 75, 150}, ++{216, 73, 151}, ++{146, 117, 131}, ++{153, 112, 133}, ++{163, 105, 136}, ++{174, 97, 140}, ++{187, 90, 143}, ++{200, 83, 147}, ++{213, 76, 150}, ++{218, 73, 152}, ++{149, 117, 131}, ++{156, 112, 134}, ++{166, 105, 137}, ++{177, 98, 140}, ++{190, 91, 144}, ++{203, 84, 147}, ++{216, 77, 150}, ++{220, 74, 152}, ++{153, 118, 132}, ++{160, 113, 134}, ++{170, 106, 137}, ++{181, 99, 140}, ++{193, 92, 144}, ++{205, 84, 147}, ++{218, 77, 151}, ++{223, 75, 152}, ++{157, 118, 133}, ++{164, 113, 135}, ++{173, 107, 138}, ++{184, 100, 141}, ++{195, 92, 144}, ++{208, 85, 147}, ++{220, 78, 151}, ++{225, 76, 152}, ++{161, 119, 133}, ++{167, 114, 135}, ++{176, 108, 138}, ++{187, 100, 141}, ++{198, 93, 144}, ++{211, 86, 148}, ++{223, 79, 151}, ++{228, 77, 152}, ++{165, 119, 134}, ++{171, 114, 136}, ++{180, 108, 138}, ++{190, 101, 141}, ++{201, 94, 145}, ++{213, 87, 148}, ++{225, 80, 151}, ++{230, 77, 152}, ++{169, 120, 134}, ++{175, 115, 136}, ++{183, 109, 139}, ++{193, 102, 142}, ++{204, 95, 145}, ++{216, 88, 148}, ++{228, 81, 151}, ++{233, 78, 152}, ++{171, 120, 135}, ++{177, 115, 136}, ++{185, 109, 139}, ++{195, 102, 142}, ++{206, 95, 145}, ++{217, 88, 148}, ++{229, 81, 151}, ++{234, 79, 152}, ++{171, 120, 135}, ++{177, 115, 136}, ++{185, 109, 139}, ++{195, 102, 142}, ++{206, 95, 145}, ++{217, 88, 148}, ++{229, 81, 151}, ++{234, 79, 152}, ++{171, 120, 135}, ++{177, 115, 136}, ++{185, 109, 139}, ++{195, 102, 142}, ++{206, 95, 145}, ++{217, 88, 148}, ++{229, 81, 151}, ++{234, 79, 152}, ++{171, 120, 135}, ++{177, 115, 136}, ++{185, 109, 139}, ++{195, 102, 142}, ++{206, 95, 145}, ++{217, 88, 148}, ++{229, 81, 151}, ++{234, 79, 152}, ++{89, 99, 116}, ++{102, 94, 121}, ++{119, 88, 127}, ++{136, 82, 133}, ++{153, 76, 138}, ++{169, 70, 143}, ++{185, 64, 147}, ++{191, 61, 149}, ++{89, 99, 116}, ++{103, 94, 121}, ++{119, 89, 127}, ++{136, 82, 133}, ++{153, 76, 138}, ++{169, 70, 143}, ++{186, 64, 147}, ++{191, 61, 149}, ++{90, 99, 116}, ++{103, 95, 121}, ++{119, 89, 127}, ++{136, 82, 133}, ++{153, 76, 138}, ++{170, 70, 143}, ++{186, 64, 147}, ++{192, 62, 149}, ++{91, 100, 116}, ++{104, 95, 122}, ++{120, 89, 128}, ++{137, 83, 133}, ++{154, 76, 138}, ++{170, 70, 143}, ++{186, 64, 147}, ++{192, 62, 149}, ++{93, 101, 117}, ++{106, 96, 122}, ++{121, 90, 128}, ++{138, 83, 133}, ++{155, 77, 138}, ++{171, 70, 143}, ++{187, 64, 147}, ++{193, 62, 149}, ++{95, 102, 117}, ++{107, 97, 122}, ++{123, 90, 128}, ++{139, 84, 133}, ++{155, 77, 139}, ++{172, 71, 143}, ++{188, 65, 147}, ++{193, 62, 149}, ++{97, 103, 118}, ++{109, 97, 123}, ++{124, 91, 128}, ++{140, 84, 134}, ++{157, 78, 139}, ++{173, 71, 143}, ++{188, 65, 147}, ++{194, 63, 149}, ++{99, 104, 119}, ++{111, 98, 123}, ++{126, 92, 129}, ++{142, 85, 134}, ++{158, 78, 139}, ++{174, 72, 143}, ++{189, 66, 147}, ++{195, 63, 149}, ++{102, 105, 119}, ++{113, 99, 124}, ++{128, 93, 129}, ++{143, 86, 134}, ++{159, 79, 139}, ++{175, 72, 143}, ++{191, 66, 148}, ++{196, 64, 149}, ++{105, 106, 120}, ++{116, 100, 124}, ++{130, 93, 129}, ++{145, 86, 134}, ++{161, 80, 139}, ++{176, 73, 144}, ++{192, 67, 148}, ++{198, 64, 149}, ++{108, 107, 121}, ++{118, 101, 125}, ++{132, 94, 130}, ++{147, 87, 135}, ++{163, 80, 139}, ++{178, 74, 144}, ++{193, 67, 148}, ++{199, 65, 149}, ++{111, 108, 122}, ++{121, 102, 126}, ++{135, 95, 130}, ++{149, 88, 135}, ++{164, 81, 139}, ++{180, 74, 144}, ++{195, 68, 148}, ++{200, 65, 149}, ++{114, 109, 123}, ++{124, 103, 126}, ++{137, 96, 131}, ++{151, 89, 135}, ++{166, 82, 140}, ++{181, 75, 144}, ++{196, 69, 148}, ++{202, 66, 149}, ++{118, 110, 123}, ++{127, 104, 127}, ++{140, 97, 131}, ++{154, 90, 136}, ++{168, 83, 140}, ++{183, 76, 144}, ++{198, 69, 148}, ++{203, 67, 149}, ++{121, 111, 124}, ++{130, 105, 127}, ++{142, 98, 132}, ++{156, 91, 136}, ++{170, 84, 140}, ++{185, 77, 144}, ++{200, 70, 148}, ++{205, 68, 150}, ++{125, 112, 125}, ++{133, 106, 128}, ++{145, 99, 132}, ++{159, 92, 136}, ++{173, 84, 140}, ++{187, 77, 144}, ++{201, 71, 148}, ++{207, 68, 150}, ++{128, 112, 126}, ++{137, 107, 129}, ++{148, 100, 132}, ++{161, 92, 137}, ++{175, 85, 141}, ++{189, 78, 145}, ++{203, 71, 148}, ++{209, 69, 150}, ++{132, 113, 126}, ++{140, 108, 129}, ++{151, 101, 133}, ++{164, 93, 137}, ++{178, 86, 141}, ++{191, 79, 145}, ++{205, 72, 149}, ++{211, 70, 150}, ++{136, 114, 127}, ++{143, 108, 130}, ++{154, 102, 133}, ++{167, 94, 137}, ++{180, 87, 141}, ++{194, 80, 145}, ++{207, 73, 149}, ++{213, 71, 150}, ++{139, 114, 128}, ++{147, 109, 130}, ++{157, 102, 134}, ++{170, 95, 138}, ++{183, 88, 141}, ++{196, 81, 145}, ++{210, 74, 149}, ++{215, 71, 150}, ++{143, 115, 129}, ++{150, 110, 131}, ++{161, 103, 134}, ++{173, 96, 138}, ++{185, 89, 142}, ++{198, 82, 145}, ++{212, 75, 149}, ++{217, 72, 150}, ++{147, 116, 129}, ++{154, 111, 132}, ++{164, 104, 135}, ++{175, 97, 138}, ++{188, 89, 142}, ++{201, 82, 146}, ++{214, 75, 149}, ++{219, 73, 150}, ++{151, 116, 130}, ++{158, 111, 132}, ++{167, 105, 135}, ++{178, 98, 139}, ++{191, 90, 142}, ++{203, 83, 146}, ++{216, 76, 149}, ++{221, 74, 151}, ++{154, 117, 131}, ++{161, 112, 133}, ++{171, 105, 136}, ++{182, 98, 139}, ++{193, 91, 143}, ++{206, 84, 146}, ++{219, 77, 149}, ++{224, 75, 151}, ++{158, 117, 131}, ++{165, 113, 133}, ++{174, 106, 136}, ++{185, 99, 139}, ++{196, 92, 143}, ++{209, 85, 146}, ++{221, 78, 150}, ++{226, 75, 151}, ++{162, 118, 132}, ++{168, 113, 134}, ++{177, 107, 137}, ++{188, 100, 140}, ++{199, 93, 143}, ++{211, 86, 146}, ++{224, 79, 150}, ++{228, 76, 151}, ++{166, 118, 132}, ++{172, 114, 134}, ++{181, 107, 137}, ++{191, 101, 140}, ++{202, 94, 143}, ++{214, 86, 147}, ++{226, 80, 150}, ++{231, 77, 151}, ++{170, 119, 133}, ++{176, 114, 135}, ++{184, 108, 138}, ++{194, 101, 141}, ++{205, 94, 144}, ++{217, 87, 147}, ++{229, 80, 150}, ++{233, 78, 151}, ++{172, 119, 133}, ++{178, 115, 135}, ++{186, 108, 138}, ++{196, 102, 141}, ++{207, 95, 144}, ++{218, 88, 147}, ++{230, 81, 150}, ++{235, 78, 151}, ++{172, 119, 133}, ++{178, 115, 135}, ++{186, 108, 138}, ++{196, 102, 141}, ++{207, 95, 144}, ++{218, 88, 147}, ++{230, 81, 150}, ++{235, 78, 151}, ++{172, 119, 133}, ++{178, 115, 135}, ++{186, 108, 138}, ++{196, 102, 141}, ++{207, 95, 144}, ++{218, 88, 147}, ++{230, 81, 150}, ++{235, 78, 151}, ++{172, 119, 133}, ++{178, 115, 135}, ++{186, 108, 138}, ++{196, 102, 141}, ++{207, 95, 144}, ++{218, 88, 147}, ++{230, 81, 150}, ++{235, 78, 151}, ++{92, 97, 113}, ++{105, 93, 119}, ++{121, 87, 125}, ++{137, 81, 131}, ++{154, 75, 136}, ++{170, 69, 141}, ++{187, 63, 146}, ++{192, 61, 147}, ++{92, 97, 113}, ++{105, 93, 119}, ++{121, 87, 125}, ++{137, 81, 131}, ++{154, 75, 136}, ++{171, 69, 141}, ++{187, 63, 146}, ++{193, 61, 147}, ++{93, 97, 113}, ++{105, 93, 119}, ++{121, 88, 125}, ++{138, 82, 131}, ++{155, 75, 136}, ++{171, 69, 141}, ++{187, 63, 146}, ++{193, 61, 147}, ++{94, 98, 114}, ++{106, 94, 119}, ++{122, 88, 125}, ++{139, 82, 131}, ++{155, 76, 136}, ++{171, 70, 141}, ++{187, 64, 146}, ++{193, 61, 147}, ++{95, 99, 114}, ++{108, 94, 120}, ++{123, 89, 126}, ++{139, 82, 131}, ++{156, 76, 137}, ++{172, 70, 141}, ++{188, 64, 146}, ++{194, 62, 147}, ++{97, 100, 115}, ++{109, 95, 120}, ++{124, 89, 126}, ++{141, 83, 131}, ++{157, 76, 137}, ++{173, 70, 141}, ++{189, 64, 146}, ++{195, 62, 147}, ++{99, 101, 116}, ++{111, 96, 121}, ++{126, 90, 126}, ++{142, 83, 132}, ++{158, 77, 137}, ++{174, 71, 141}, ++{190, 65, 146}, ++{195, 62, 147}, ++{102, 102, 116}, ++{113, 97, 121}, ++{128, 91, 127}, ++{143, 84, 132}, ++{159, 78, 137}, ++{175, 71, 142}, ++{191, 65, 146}, ++{196, 63, 147}, ++{104, 103, 117}, ++{115, 98, 122}, ++{129, 91, 127}, ++{145, 85, 132}, ++{161, 78, 137}, ++{176, 72, 142}, ++{192, 66, 146}, ++{197, 63, 148}, ++{107, 104, 118}, ++{118, 99, 122}, ++{132, 92, 127}, ++{147, 86, 132}, ++{162, 79, 137}, ++{178, 72, 142}, ++{193, 66, 146}, ++{199, 64, 148}, ++{110, 105, 119}, ++{120, 100, 123}, ++{134, 93, 128}, ++{149, 86, 133}, ++{164, 80, 138}, ++{179, 73, 142}, ++{194, 67, 146}, ++{200, 64, 148}, ++{113, 106, 120}, ++{123, 101, 123}, ++{136, 94, 128}, ++{151, 87, 133}, ++{166, 80, 138}, ++{181, 74, 142}, ++{196, 67, 146}, ++{201, 65, 148}, ++{116, 107, 120}, ++{126, 102, 124}, ++{139, 95, 129}, ++{153, 88, 133}, ++{168, 81, 138}, ++{182, 74, 142}, ++{197, 68, 146}, ++{203, 66, 148}, ++{119, 108, 121}, ++{129, 103, 125}, ++{141, 96, 129}, ++{155, 89, 134}, ++{170, 82, 138}, ++{184, 75, 142}, ++{199, 69, 147}, ++{204, 66, 148}, ++{123, 109, 122}, ++{132, 104, 125}, ++{144, 97, 130}, ++{157, 90, 134}, ++{172, 83, 138}, ++{186, 76, 143}, ++{201, 69, 147}, ++{206, 67, 148}, ++{126, 110, 123}, ++{135, 105, 126}, ++{147, 98, 130}, ++{160, 91, 134}, ++{174, 84, 139}, ++{188, 77, 143}, ++{202, 70, 147}, ++{208, 68, 148}, ++{130, 111, 124}, ++{138, 106, 127}, ++{150, 99, 131}, ++{163, 92, 135}, ++{176, 85, 139}, ++{190, 78, 143}, ++{204, 71, 147}, ++{210, 69, 148}, ++{133, 112, 124}, ++{141, 106, 127}, ++{153, 100, 131}, ++{165, 93, 135}, ++{179, 85, 139}, ++{192, 78, 143}, ++{206, 72, 147}, ++{212, 69, 148}, ++{137, 112, 125}, ++{145, 107, 128}, ++{156, 101, 132}, ++{168, 93, 136}, ++{181, 86, 140}, ++{195, 79, 143}, ++{208, 73, 147}, ++{214, 70, 149}, ++{141, 113, 126}, ++{148, 108, 129}, ++{159, 101, 132}, ++{171, 94, 136}, ++{184, 87, 140}, ++{197, 80, 144}, ++{210, 73, 147}, ++{216, 71, 149}, ++{144, 114, 127}, ++{152, 109, 129}, ++{162, 102, 133}, ++{174, 95, 136}, ++{186, 88, 140}, ++{199, 81, 144}, ++{213, 74, 148}, ++{218, 72, 149}, ++{148, 115, 127}, ++{155, 110, 130}, ++{165, 103, 133}, ++{177, 96, 137}, ++{189, 89, 140}, ++{202, 82, 144}, ++{215, 75, 148}, ++{220, 72, 149}, ++{152, 115, 128}, ++{159, 110, 131}, ++{168, 104, 134}, ++{180, 97, 137}, ++{192, 90, 141}, ++{204, 83, 144}, ++{217, 76, 148}, ++{222, 73, 149}, ++{156, 116, 129}, ++{162, 111, 131}, ++{172, 105, 134}, ++{183, 98, 138}, ++{195, 90, 141}, ++{207, 83, 145}, ++{220, 77, 148}, ++{224, 74, 149}, ++{160, 116, 130}, ++{166, 112, 132}, ++{175, 105, 135}, ++{186, 98, 138}, ++{197, 91, 141}, ++{210, 84, 145}, ++{222, 77, 148}, ++{227, 75, 150}, ++{163, 117, 130}, ++{170, 112, 132}, ++{178, 106, 135}, ++{189, 99, 138}, ++{200, 92, 142}, ++{212, 85, 145}, ++{225, 78, 149}, ++{229, 76, 150}, ++{167, 117, 131}, ++{173, 113, 133}, ++{182, 107, 136}, ++{192, 100, 139}, ++{203, 93, 142}, ++{215, 86, 145}, ++{227, 79, 149}, ++{232, 77, 150}, ++{171, 118, 132}, ++{177, 113, 133}, ++{185, 107, 136}, ++{195, 101, 139}, ++{206, 94, 142}, ++{218, 87, 146}, ++{230, 80, 149}, ++{234, 77, 150}, ++{173, 118, 132}, ++{179, 114, 134}, ++{187, 108, 136}, ++{197, 101, 139}, ++{208, 94, 143}, ++{219, 87, 146}, ++{231, 80, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{179, 114, 134}, ++{187, 108, 136}, ++{197, 101, 139}, ++{208, 94, 143}, ++{219, 87, 146}, ++{231, 80, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{179, 114, 134}, ++{187, 108, 136}, ++{197, 101, 139}, ++{208, 94, 143}, ++{219, 87, 146}, ++{231, 80, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{179, 114, 134}, ++{187, 108, 136}, ++{197, 101, 139}, ++{208, 94, 143}, ++{219, 87, 146}, ++{231, 80, 149}, ++{235, 78, 150}, ++{94, 94, 111}, ++{107, 91, 116}, ++{122, 86, 123}, ++{139, 80, 129}, ++{156, 74, 134}, ++{172, 68, 139}, ++{188, 63, 144}, ++{194, 60, 145}, ++{94, 95, 111}, ++{107, 91, 116}, ++{123, 86, 123}, ++{139, 80, 129}, ++{156, 74, 134}, ++{172, 68, 139}, ++{188, 63, 144}, ++{194, 60, 145}, ++{95, 95, 111}, ++{108, 91, 117}, ++{123, 86, 123}, ++{140, 81, 129}, ++{156, 75, 134}, ++{172, 69, 139}, ++{188, 63, 144}, ++{194, 61, 145}, ++{96, 96, 111}, ++{109, 92, 117}, ++{124, 87, 123}, ++{140, 81, 129}, ++{157, 75, 134}, ++{173, 69, 139}, ++{189, 63, 144}, ++{194, 61, 146}, ++{98, 97, 112}, ++{110, 93, 117}, ++{125, 87, 123}, ++{141, 81, 129}, ++{157, 75, 134}, ++{173, 69, 139}, ++{189, 63, 144}, ++{195, 61, 146}, ++{100, 98, 113}, ++{111, 93, 118}, ++{126, 88, 124}, ++{142, 82, 129}, ++{158, 76, 135}, ++{174, 70, 140}, ++{190, 64, 144}, ++{196, 61, 146}, ++{102, 99, 113}, ++{113, 94, 118}, ++{128, 89, 124}, ++{143, 82, 130}, ++{159, 76, 135}, ++{175, 70, 140}, ++{191, 64, 144}, ++{197, 62, 146}, ++{104, 100, 114}, ++{115, 95, 119}, ++{129, 89, 124}, ++{145, 83, 130}, ++{161, 77, 135}, ++{176, 71, 140}, ++{192, 64, 144}, ++{197, 62, 146}, ++{106, 101, 115}, ++{117, 96, 119}, ++{131, 90, 125}, ++{146, 84, 130}, ++{162, 77, 135}, ++{178, 71, 140}, ++{193, 65, 144}, ++{199, 63, 146}, ++{109, 102, 116}, ++{120, 97, 120}, ++{133, 91, 125}, ++{148, 85, 130}, ++{164, 78, 135}, ++{179, 72, 140}, ++{194, 66, 144}, ++{200, 63, 146}, ++{112, 103, 116}, ++{122, 98, 121}, ++{135, 92, 126}, ++{150, 85, 131}, ++{165, 79, 136}, ++{180, 72, 140}, ++{195, 66, 145}, ++{201, 64, 146}, ++{115, 104, 117}, ++{125, 99, 121}, ++{138, 93, 126}, ++{152, 86, 131}, ++{167, 80, 136}, ++{182, 73, 140}, ++{197, 67, 145}, ++{202, 64, 146}, ++{118, 105, 118}, ++{128, 100, 122}, ++{140, 94, 127}, ++{154, 87, 131}, ++{169, 80, 136}, ++{184, 74, 141}, ++{198, 67, 145}, ++{204, 65, 146}, ++{121, 107, 119}, ++{131, 101, 123}, ++{143, 95, 127}, ++{157, 88, 132}, ++{171, 81, 136}, ++{185, 75, 141}, ++{200, 68, 145}, ++{205, 66, 146}, ++{125, 108, 120}, ++{134, 102, 123}, ++{146, 96, 128}, ++{159, 89, 132}, ++{173, 82, 137}, ++{187, 75, 141}, ++{202, 69, 145}, ++{207, 67, 147}, ++{128, 108, 121}, ++{137, 103, 124}, ++{148, 97, 128}, ++{161, 90, 133}, ++{175, 83, 137}, ++{189, 76, 141}, ++{204, 70, 145}, ++{209, 67, 147}, ++{132, 109, 122}, ++{140, 104, 125}, ++{151, 98, 129}, ++{164, 91, 133}, ++{178, 84, 137}, ++{191, 77, 141}, ++{205, 70, 145}, ++{211, 68, 147}, ++{135, 110, 122}, ++{143, 105, 125}, ++{154, 99, 129}, ++{167, 92, 133}, ++{180, 85, 138}, ++{194, 78, 142}, ++{207, 71, 146}, ++{213, 69, 147}, ++{139, 111, 123}, ++{146, 106, 126}, ++{157, 100, 130}, ++{169, 93, 134}, ++{182, 85, 138}, ++{196, 79, 142}, ++{209, 72, 146}, ++{215, 70, 147}, ++{142, 112, 124}, ++{150, 107, 127}, ++{160, 100, 130}, ++{172, 93, 134}, ++{185, 86, 138}, ++{198, 79, 142}, ++{212, 73, 146}, ++{217, 70, 147}, ++{146, 113, 125}, ++{153, 108, 127}, ++{163, 101, 131}, ++{175, 94, 135}, ++{187, 87, 139}, ++{200, 80, 142}, ++{214, 74, 146}, ++{219, 71, 148}, ++{150, 113, 126}, ++{157, 108, 128}, ++{166, 102, 131}, ++{178, 95, 135}, ++{190, 88, 139}, ++{203, 81, 143}, ++{216, 74, 146}, ++{221, 72, 148}, ++{153, 114, 126}, ++{160, 109, 129}, ++{170, 103, 132}, ++{181, 96, 136}, ++{193, 89, 139}, ++{205, 82, 143}, ++{218, 75, 147}, ++{223, 73, 148}, ++{157, 115, 127}, ++{164, 110, 129}, ++{173, 104, 132}, ++{184, 97, 136}, ++{196, 90, 140}, ++{208, 83, 143}, ++{221, 76, 147}, ++{225, 74, 148}, ++{161, 115, 128}, ++{167, 111, 130}, ++{176, 104, 133}, ++{187, 98, 136}, ++{198, 91, 140}, ++{211, 84, 143}, ++{223, 77, 147}, ++{228, 74, 148}, ++{165, 116, 129}, ++{171, 111, 131}, ++{180, 105, 134}, ++{190, 98, 137}, ++{201, 91, 140}, ++{213, 84, 144}, ++{226, 78, 147}, ++{230, 75, 148}, ++{169, 116, 129}, ++{175, 112, 131}, ++{183, 106, 134}, ++{193, 99, 137}, ++{204, 92, 141}, ++{216, 85, 144}, ++{228, 78, 147}, ++{233, 76, 149}, ++{172, 117, 130}, ++{178, 112, 132}, ++{186, 106, 135}, ++{196, 100, 138}, ++{207, 93, 141}, ++{219, 86, 144}, ++{231, 79, 148}, ++{235, 77, 149}, ++{174, 117, 130}, ++{180, 113, 132}, ++{188, 107, 135}, ++{198, 100, 138}, ++{209, 93, 141}, ++{220, 86, 144}, ++{232, 80, 148}, ++{236, 77, 149}, ++{174, 117, 130}, ++{180, 113, 132}, ++{188, 107, 135}, ++{198, 100, 138}, ++{209, 93, 141}, ++{220, 86, 144}, ++{232, 80, 148}, ++{236, 77, 149}, ++{174, 117, 130}, ++{180, 113, 132}, ++{188, 107, 135}, ++{198, 100, 138}, ++{209, 93, 141}, ++{220, 86, 144}, ++{232, 80, 148}, ++{236, 77, 149}, ++{174, 117, 130}, ++{180, 113, 132}, ++{188, 107, 135}, ++{198, 100, 138}, ++{209, 93, 141}, ++{220, 86, 144}, ++{232, 80, 148}, ++{236, 77, 149}, ++{97, 92, 108}, ++{109, 89, 114}, ++{125, 84, 120}, ++{141, 79, 126}, ++{157, 73, 132}, ++{173, 68, 137}, ++{189, 62, 142}, ++{195, 60, 144}, ++{97, 92, 108}, ++{109, 89, 114}, ++{125, 85, 120}, ++{141, 79, 126}, ++{157, 73, 132}, ++{173, 68, 137}, ++{189, 62, 142}, ++{195, 60, 144}, ++{98, 93, 109}, ++{110, 90, 114}, ++{125, 85, 120}, ++{141, 79, 127}, ++{158, 74, 132}, ++{174, 68, 137}, ++{189, 62, 142}, ++{195, 60, 144}, ++{99, 93, 109}, ++{111, 90, 114}, ++{126, 85, 121}, ++{142, 80, 127}, ++{158, 74, 132}, ++{174, 68, 137}, ++{190, 62, 142}, ++{196, 60, 144}, ++{100, 94, 110}, ++{112, 91, 115}, ++{127, 86, 121}, ++{143, 80, 127}, ++{159, 74, 132}, ++{175, 68, 137}, ++{190, 63, 142}, ++{196, 60, 144}, ++{102, 95, 110}, ++{114, 92, 115}, ++{128, 86, 121}, ++{144, 81, 127}, ++{160, 75, 133}, ++{176, 69, 138}, ++{191, 63, 142}, ++{197, 61, 144}, ++{104, 96, 111}, ++{115, 92, 116}, ++{130, 87, 122}, ++{145, 81, 127}, ++{161, 75, 133}, ++{177, 69, 138}, ++{192, 63, 142}, ++{198, 61, 144}, ++{106, 98, 112}, ++{117, 93, 116}, ++{131, 88, 122}, ++{147, 82, 128}, ++{162, 76, 133}, ++{178, 70, 138}, ++{193, 64, 142}, ++{199, 62, 144}, ++{109, 99, 112}, ++{119, 94, 117}, ++{133, 89, 122}, ++{148, 83, 128}, ++{164, 77, 133}, ++{179, 70, 138}, ++{194, 64, 142}, ++{200, 62, 144}, ++{111, 100, 113}, ++{122, 96, 118}, ++{135, 90, 123}, ++{150, 84, 128}, ++{165, 77, 133}, ++{180, 71, 138}, ++{195, 65, 143}, ++{201, 63, 144}, ++{114, 101, 114}, ++{124, 97, 118}, ++{137, 91, 123}, ++{152, 84, 129}, ++{167, 78, 134}, ++{182, 72, 138}, ++{197, 66, 143}, ++{202, 63, 144}, ++{117, 102, 115}, ++{127, 98, 119}, ++{140, 92, 124}, ++{154, 85, 129}, ++{168, 79, 134}, ++{183, 72, 139}, ++{198, 66, 143}, ++{204, 64, 144}, ++{120, 104, 116}, ++{130, 99, 120}, ++{142, 93, 124}, ++{156, 86, 129}, ++{170, 80, 134}, ++{185, 73, 139}, ++{200, 67, 143}, ++{205, 65, 145}, ++{123, 105, 117}, ++{132, 100, 120}, ++{145, 94, 125}, ++{158, 87, 130}, ++{172, 80, 134}, ++{187, 74, 139}, ++{201, 68, 143}, ++{207, 65, 145}, ++{127, 106, 118}, ++{135, 101, 121}, ++{147, 95, 126}, ++{160, 88, 130}, ++{174, 81, 135}, ++{189, 75, 139}, ++{203, 68, 143}, ++{208, 66, 145}, ++{130, 107, 119}, ++{138, 102, 122}, ++{150, 96, 126}, ++{163, 89, 131}, ++{177, 82, 135}, ++{191, 75, 139}, ++{205, 69, 144}, ++{210, 67, 145}, ++{133, 108, 120}, ++{142, 103, 123}, ++{153, 96, 127}, ++{165, 90, 131}, ++{179, 83, 135}, ++{193, 76, 140}, ++{207, 70, 144}, ++{212, 67, 145}, ++{137, 109, 120}, ++{145, 104, 123}, ++{156, 97, 127}, ++{168, 91, 132}, ++{181, 84, 136}, ++{195, 77, 140}, ++{209, 71, 144}, ++{214, 68, 145}, ++{140, 109, 121}, ++{148, 105, 124}, ++{159, 98, 128}, ++{171, 92, 132}, ++{184, 85, 136}, ++{197, 78, 140}, ++{211, 71, 144}, ++{216, 69, 146}, ++{144, 110, 122}, ++{151, 106, 125}, ++{162, 99, 128}, ++{174, 92, 132}, ++{186, 86, 136}, ++{199, 79, 140}, ++{213, 72, 144}, ++{218, 70, 146}, ++{148, 111, 123}, ++{155, 106, 126}, ++{165, 100, 129}, ++{176, 93, 133}, ++{189, 86, 137}, ++{202, 80, 141}, ++{215, 73, 145}, ++{220, 71, 146}, ++{151, 112, 124}, ++{158, 107, 126}, ++{168, 101, 130}, ++{179, 94, 133}, ++{191, 87, 137}, ++{204, 80, 141}, ++{217, 74, 145}, ++{222, 71, 146}, ++{155, 113, 125}, ++{162, 108, 127}, ++{171, 102, 130}, ++{182, 95, 134}, ++{194, 88, 138}, ++{207, 81, 141}, ++{219, 75, 145}, ++{224, 72, 146}, ++{159, 113, 125}, ++{165, 109, 128}, ++{174, 103, 131}, ++{185, 96, 134}, ++{197, 89, 138}, ++{209, 82, 142}, ++{222, 75, 145}, ++{226, 73, 147}, ++{162, 114, 126}, ++{169, 109, 128}, ++{178, 103, 131}, ++{188, 97, 135}, ++{200, 90, 138}, ++{212, 83, 142}, ++{224, 76, 145}, ++{229, 74, 147}, ++{166, 114, 127}, ++{172, 110, 129}, ++{181, 104, 132}, ++{191, 97, 135}, ++{203, 91, 139}, ++{214, 84, 142}, ++{227, 77, 146}, ++{231, 75, 147}, ++{170, 115, 128}, ++{176, 111, 130}, ++{184, 105, 132}, ++{194, 98, 136}, ++{205, 91, 139}, ++{217, 85, 143}, ++{229, 78, 146}, ++{234, 75, 147}, ++{174, 116, 128}, ++{179, 111, 130}, ++{188, 106, 133}, ++{198, 99, 136}, ++{208, 92, 139}, ++{220, 85, 143}, ++{232, 79, 146}, ++{236, 76, 147}, ++{176, 116, 129}, ++{181, 112, 131}, ++{189, 106, 133}, ++{199, 99, 136}, ++{210, 93, 140}, ++{221, 86, 143}, ++{233, 79, 146}, ++{237, 77, 148}, ++{176, 116, 129}, ++{181, 112, 131}, ++{189, 106, 133}, ++{199, 99, 136}, ++{210, 93, 140}, ++{221, 86, 143}, ++{233, 79, 146}, ++{237, 77, 148}, ++{176, 116, 129}, ++{181, 112, 131}, ++{189, 106, 133}, ++{199, 99, 136}, ++{210, 93, 140}, ++{221, 86, 143}, ++{233, 79, 146}, ++{237, 77, 148}, ++{176, 116, 129}, ++{181, 112, 131}, ++{189, 106, 133}, ++{199, 99, 136}, ++{210, 93, 140}, ++{221, 86, 143}, ++{233, 79, 146}, ++{237, 77, 148}, ++{100, 90, 106}, ++{112, 87, 111}, ++{127, 83, 118}, ++{143, 78, 124}, ++{159, 72, 130}, ++{175, 67, 135}, ++{190, 61, 140}, ++{196, 59, 142}, ++{100, 90, 106}, ++{112, 87, 111}, ++{127, 83, 118}, ++{143, 78, 124}, ++{159, 72, 130}, ++{175, 67, 135}, ++{191, 61, 140}, ++{196, 59, 142}, ++{101, 90, 106}, ++{112, 88, 112}, ++{127, 83, 118}, ++{143, 78, 124}, ++{159, 73, 130}, ++{175, 67, 135}, ++{191, 61, 140}, ++{197, 59, 142}, ++{102, 91, 107}, ++{113, 88, 112}, ++{128, 84, 118}, ++{144, 78, 124}, ++{160, 73, 130}, ++{176, 67, 135}, ++{191, 62, 140}, ++{197, 60, 142}, ++{103, 92, 107}, ++{114, 89, 112}, ++{129, 84, 119}, ++{145, 79, 125}, ++{161, 73, 130}, ++{176, 68, 135}, ++{192, 62, 140}, ++{198, 60, 142}, ++{105, 93, 108}, ++{116, 90, 113}, ++{130, 85, 119}, ++{146, 79, 125}, ++{162, 74, 130}, ++{177, 68, 136}, ++{193, 62, 140}, ++{198, 60, 142}, ++{107, 94, 108}, ++{118, 91, 113}, ++{132, 86, 119}, ++{147, 80, 125}, ++{163, 74, 131}, ++{178, 68, 136}, ++{193, 63, 140}, ++{199, 61, 142}, ++{109, 95, 109}, ++{119, 92, 114}, ++{133, 86, 120}, ++{148, 81, 125}, ++{164, 75, 131}, ++{179, 69, 136}, ++{194, 63, 140}, ++{200, 61, 142}, ++{111, 97, 110}, ++{122, 93, 115}, ++{135, 87, 120}, ++{150, 82, 126}, ++{165, 76, 131}, ++{180, 70, 136}, ++{195, 64, 141}, ++{201, 61, 142}, ++{114, 98, 111}, ++{124, 94, 115}, ++{137, 88, 121}, ++{152, 82, 126}, ++{167, 76, 131}, ++{182, 70, 136}, ++{197, 64, 141}, ++{202, 62, 142}, ++{117, 99, 112}, ++{126, 95, 116}, ++{139, 89, 121}, ++{153, 83, 126}, ++{168, 77, 132}, ++{183, 71, 136}, ++{198, 65, 141}, ++{203, 63, 143}, ++{119, 100, 113}, ++{129, 96, 117}, ++{141, 90, 122}, ++{155, 84, 127}, ++{170, 78, 132}, ++{185, 72, 137}, ++{199, 65, 141}, ++{205, 63, 143}, ++{122, 102, 114}, ++{132, 97, 117}, ++{144, 91, 122}, ++{158, 85, 127}, ++{172, 79, 132}, ++{186, 72, 137}, ++{201, 66, 141}, ++{206, 64, 143}, ++{126, 103, 115}, ++{134, 98, 118}, ++{146, 92, 123}, ++{160, 86, 128}, ++{174, 79, 132}, ++{188, 73, 137}, ++{202, 67, 141}, ++{208, 65, 143}, ++{129, 104, 116}, ++{137, 99, 119}, ++{149, 93, 123}, ++{162, 87, 128}, ++{176, 80, 133}, ++{190, 74, 137}, ++{204, 68, 142}, ++{209, 65, 143}, ++{132, 105, 116}, ++{140, 100, 120}, ++{152, 94, 124}, ++{165, 88, 129}, ++{178, 81, 133}, ++{192, 75, 138}, ++{206, 68, 142}, ++{211, 66, 143}, ++{135, 106, 117}, ++{143, 101, 121}, ++{154, 95, 125}, ++{167, 89, 129}, ++{180, 82, 134}, ++{194, 75, 138}, ++{208, 69, 142}, ++{213, 67, 144}, ++{139, 107, 118}, ++{147, 102, 121}, ++{157, 96, 125}, ++{170, 90, 130}, ++{183, 83, 134}, ++{196, 76, 138}, ++{210, 70, 142}, ++{215, 68, 144}, ++{142, 108, 119}, ++{150, 103, 122}, ++{160, 97, 126}, ++{172, 90, 130}, ++{185, 84, 134}, ++{198, 77, 138}, ++{212, 71, 142}, ++{217, 68, 144}, ++{146, 109, 120}, ++{153, 104, 123}, ++{163, 98, 126}, ++{175, 91, 131}, ++{188, 85, 135}, ++{201, 78, 139}, ++{214, 71, 143}, ++{219, 69, 144}, ++{149, 110, 121}, ++{156, 105, 124}, ++{166, 99, 127}, ++{178, 92, 131}, ++{190, 86, 135}, ++{203, 79, 139}, ++{216, 72, 143}, ++{221, 70, 144}, ++{153, 110, 122}, ++{160, 106, 124}, ++{169, 100, 128}, ++{181, 93, 131}, ++{193, 86, 135}, ++{205, 80, 139}, ++{218, 73, 143}, ++{223, 71, 145}, ++{157, 111, 123}, ++{163, 107, 125}, ++{173, 101, 128}, ++{184, 94, 132}, ++{195, 87, 136}, ++{208, 81, 140}, ++{220, 74, 143}, ++{225, 72, 145}, ++{160, 112, 123}, ++{167, 107, 126}, ++{176, 101, 129}, ++{187, 95, 132}, ++{198, 88, 136}, ++{210, 81, 140}, ++{223, 75, 144}, ++{228, 72, 145}, ++{164, 112, 124}, ++{170, 108, 126}, ++{179, 102, 129}, ++{190, 96, 133}, ++{201, 89, 137}, ++{213, 82, 140}, ++{225, 76, 144}, ++{230, 73, 145}, ++{168, 113, 125}, ++{174, 109, 127}, ++{182, 103, 130}, ++{193, 97, 133}, ++{204, 90, 137}, ++{216, 83, 141}, ++{228, 76, 144}, ++{232, 74, 146}, ++{171, 114, 126}, ++{177, 109, 128}, ++{186, 104, 131}, ++{196, 97, 134}, ++{207, 91, 137}, ++{218, 84, 141}, ++{230, 77, 144}, ++{235, 75, 146}, ++{175, 114, 126}, ++{181, 110, 128}, ++{189, 104, 131}, ++{199, 98, 134}, ++{210, 91, 138}, ++{221, 85, 141}, ++{233, 78, 145}, ++{237, 76, 146}, ++{177, 115, 127}, ++{183, 110, 129}, ++{191, 105, 132}, ++{200, 98, 135}, ++{211, 92, 138}, ++{222, 85, 141}, ++{234, 78, 145}, ++{238, 76, 146}, ++{177, 115, 127}, ++{183, 110, 129}, ++{191, 105, 132}, ++{200, 98, 135}, ++{211, 92, 138}, ++{222, 85, 141}, ++{234, 78, 145}, ++{238, 76, 146}, ++{177, 115, 127}, ++{183, 110, 129}, ++{191, 105, 132}, ++{200, 98, 135}, ++{211, 92, 138}, ++{222, 85, 141}, ++{234, 78, 145}, ++{238, 76, 146}, ++{177, 115, 127}, ++{183, 110, 129}, ++{191, 105, 132}, ++{200, 98, 135}, ++{211, 92, 138}, ++{222, 85, 141}, ++{234, 78, 145}, ++{238, 76, 146}, ++{102, 87, 103}, ++{114, 85, 109}, ++{129, 81, 115}, ++{145, 77, 122}, ++{161, 71, 128}, ++{176, 66, 133}, ++{192, 60, 138}, ++{198, 58, 140}, ++{103, 87, 103}, ++{114, 85, 109}, ++{129, 81, 116}, ++{145, 77, 122}, ++{161, 71, 128}, ++{176, 66, 133}, ++{192, 61, 138}, ++{198, 58, 140}, ++{103, 88, 104}, ++{115, 85, 109}, ++{130, 82, 116}, ++{145, 77, 122}, ++{161, 72, 128}, ++{177, 66, 133}, ++{192, 61, 138}, ++{198, 59, 140}, ++{104, 88, 104}, ++{116, 86, 110}, ++{130, 82, 116}, ++{146, 77, 122}, ++{162, 72, 128}, ++{177, 66, 133}, ++{193, 61, 138}, ++{198, 59, 140}, ++{106, 89, 105}, ++{117, 87, 110}, ++{131, 83, 116}, ++{147, 78, 122}, ++{162, 72, 128}, ++{178, 67, 133}, ++{193, 61, 138}, ++{199, 59, 140}, ++{107, 90, 105}, ++{118, 88, 110}, ++{132, 83, 116}, ++{148, 78, 123}, ++{163, 73, 128}, ++{179, 67, 133}, ++{194, 62, 138}, ++{200, 59, 140}, ++{109, 92, 106}, ++{120, 89, 111}, ++{134, 84, 117}, ++{149, 79, 123}, ++{164, 73, 128}, ++{180, 68, 134}, ++{195, 62, 138}, ++{200, 60, 140}, ++{111, 93, 107}, ++{122, 90, 112}, ++{135, 85, 117}, ++{150, 79, 123}, ++{165, 74, 129}, ++{181, 68, 134}, ++{196, 62, 139}, ++{201, 60, 140}, ++{114, 94, 108}, ++{124, 91, 112}, ++{137, 86, 118}, ++{152, 80, 123}, ++{167, 74, 129}, ++{182, 69, 134}, ++{197, 63, 139}, ++{202, 61, 140}, ++{116, 96, 109}, ++{126, 92, 113}, ++{139, 87, 118}, ++{153, 81, 124}, ++{168, 75, 129}, ++{183, 69, 134}, ++{198, 63, 139}, ++{204, 61, 141}, ++{119, 97, 109}, ++{128, 93, 114}, ++{141, 88, 119}, ++{155, 82, 124}, ++{170, 76, 129}, ++{185, 70, 134}, ++{199, 64, 139}, ++{205, 62, 141}, ++{122, 98, 110}, ++{131, 94, 114}, ++{143, 89, 119}, ++{157, 83, 125}, ++{172, 77, 130}, ++{186, 71, 135}, ++{201, 65, 139}, ++{206, 63, 141}, ++{125, 99, 111}, ++{134, 95, 115}, ++{146, 90, 120}, ++{159, 84, 125}, ++{173, 78, 130}, ++{188, 71, 135}, ++{202, 65, 139}, ++{208, 63, 141}, ++{128, 101, 112}, ++{136, 96, 116}, ++{148, 91, 121}, ++{161, 85, 126}, ++{175, 78, 130}, ++{190, 72, 135}, ++{204, 66, 140}, ++{209, 64, 141}, ++{131, 102, 113}, ++{139, 97, 117}, ++{151, 92, 121}, ++{164, 86, 126}, ++{177, 79, 131}, ++{191, 73, 135}, ++{205, 67, 140}, ++{211, 65, 141}, ++{134, 103, 114}, ++{142, 99, 118}, ++{153, 93, 122}, ++{166, 87, 127}, ++{180, 80, 131}, ++{193, 74, 136}, ++{207, 68, 140}, ++{212, 65, 142}, ++{137, 104, 115}, ++{145, 100, 118}, ++{156, 94, 123}, ++{169, 87, 127}, ++{182, 81, 132}, ++{195, 75, 136}, ++{209, 68, 140}, ++{214, 66, 142}, ++{141, 105, 116}, ++{148, 101, 119}, ++{159, 95, 123}, ++{171, 88, 128}, ++{184, 82, 132}, ++{197, 75, 136}, ++{211, 69, 140}, ++{216, 67, 142}, ++{144, 106, 117}, ++{152, 102, 120}, ++{162, 96, 124}, ++{174, 89, 128}, ++{187, 83, 132}, ++{200, 76, 137}, ++{213, 70, 141}, ++{218, 68, 142}, ++{148, 107, 118}, ++{155, 103, 121}, ++{165, 97, 124}, ++{177, 90, 129}, ++{189, 84, 133}, ++{202, 77, 137}, ++{215, 71, 141}, ++{220, 68, 142}, ++{151, 108, 119}, ++{158, 103, 122}, ++{168, 98, 125}, ++{179, 91, 129}, ++{192, 85, 133}, ++{204, 78, 137}, ++{217, 72, 141}, ++{222, 69, 143}, ++{155, 109, 120}, ++{162, 104, 122}, ++{171, 99, 126}, ++{182, 92, 130}, ++{194, 85, 134}, ++{207, 79, 138}, ++{219, 72, 141}, ++{224, 70, 143}, ++{158, 110, 121}, ++{165, 105, 123}, ++{174, 99, 126}, ++{185, 93, 130}, ++{197, 86, 134}, ++{209, 80, 138}, ++{222, 73, 142}, ++{226, 71, 143}, ++{162, 110, 121}, ++{168, 106, 124}, ++{177, 100, 127}, ++{188, 94, 131}, ++{199, 87, 134}, ++{212, 81, 138}, ++{224, 74, 142}, ++{229, 72, 143}, ++{166, 111, 122}, ++{172, 107, 125}, ++{181, 101, 128}, ++{191, 95, 131}, ++{202, 88, 135}, ++{214, 81, 139}, ++{226, 75, 142}, ++{231, 73, 144}, ++{169, 112, 123}, ++{175, 108, 125}, ++{184, 102, 128}, ++{194, 96, 132}, ++{205, 89, 135}, ++{217, 82, 139}, ++{229, 76, 143}, ++{233, 73, 144}, ++{173, 112, 124}, ++{179, 108, 126}, ++{187, 103, 129}, ++{197, 96, 132}, ++{208, 90, 136}, ++{219, 83, 139}, ++{231, 77, 143}, ++{236, 74, 144}, ++{177, 113, 125}, ++{182, 109, 127}, ++{190, 103, 129}, ++{200, 97, 133}, ++{211, 91, 136}, ++{222, 84, 140}, ++{234, 77, 143}, ++{238, 75, 144}, ++{178, 113, 125}, ++{184, 109, 127}, ++{192, 104, 130}, ++{202, 97, 133}, ++{212, 91, 136}, ++{223, 84, 140}, ++{235, 78, 143}, ++{239, 75, 145}, ++{178, 113, 125}, ++{184, 109, 127}, ++{192, 104, 130}, ++{202, 97, 133}, ++{212, 91, 136}, ++{223, 84, 140}, ++{235, 78, 143}, ++{239, 75, 145}, ++{178, 113, 125}, ++{184, 109, 127}, ++{192, 104, 130}, ++{202, 97, 133}, ++{212, 91, 136}, ++{223, 84, 140}, ++{235, 78, 143}, ++{239, 75, 145}, ++{178, 113, 125}, ++{184, 109, 127}, ++{192, 104, 130}, ++{202, 97, 133}, ++{212, 91, 136}, ++{223, 84, 140}, ++{235, 78, 143}, ++{239, 75, 145}, ++{105, 85, 101}, ++{117, 83, 107}, ++{131, 80, 113}, ++{147, 75, 119}, ++{162, 70, 125}, ++{178, 65, 131}, ++{193, 60, 136}, ++{199, 58, 138}, ++{105, 85, 101}, ++{117, 83, 107}, ++{131, 80, 113}, ++{147, 75, 119}, ++{162, 70, 125}, ++{178, 65, 131}, ++{193, 60, 136}, ++{199, 58, 138}, ++{106, 85, 101}, ++{117, 83, 107}, ++{132, 80, 113}, ++{147, 75, 120}, ++{163, 70, 126}, ++{178, 65, 131}, ++{194, 60, 136}, ++{199, 58, 138}, ++{107, 86, 102}, ++{118, 84, 107}, ++{132, 80, 113}, ++{148, 76, 120}, ++{163, 71, 126}, ++{179, 65, 131}, ++{194, 60, 136}, ++{200, 58, 138}, ++{108, 87, 102}, ++{119, 85, 108}, ++{133, 81, 114}, ++{149, 76, 120}, ++{164, 71, 126}, ++{180, 66, 131}, ++{195, 60, 136}, ++{200, 58, 138}, ++{110, 88, 103}, ++{121, 86, 108}, ++{135, 82, 114}, ++{150, 77, 120}, ++{165, 72, 126}, ++{180, 66, 131}, ++{195, 61, 136}, ++{201, 59, 138}, ++{112, 89, 104}, ++{122, 86, 109}, ++{136, 82, 115}, ++{151, 77, 121}, ++{166, 72, 126}, ++{181, 67, 131}, ++{196, 61, 136}, ++{202, 59, 138}, ++{114, 91, 104}, ++{124, 88, 109}, ++{138, 83, 115}, ++{152, 78, 121}, ++{167, 73, 126}, ++{182, 67, 132}, ++{197, 62, 137}, ++{203, 60, 138}, ++{116, 92, 105}, ++{126, 89, 110}, ++{139, 84, 115}, ++{154, 79, 121}, ++{169, 73, 127}, ++{183, 68, 132}, ++{198, 62, 137}, ++{204, 60, 138}, ++{119, 93, 106}, ++{128, 90, 111}, ++{141, 85, 116}, ++{155, 80, 122}, ++{170, 74, 127}, ++{185, 68, 132}, ++{199, 63, 137}, ++{205, 61, 139}, ++{121, 95, 107}, ++{131, 91, 111}, ++{143, 86, 117}, ++{157, 81, 122}, ++{172, 75, 127}, ++{186, 69, 132}, ++{201, 63, 137}, ++{206, 61, 139}, ++{124, 96, 108}, ++{133, 92, 112}, ++{145, 87, 117}, ++{159, 81, 122}, ++{173, 76, 128}, ++{188, 70, 133}, ++{202, 64, 137}, ++{208, 62, 139}, ++{127, 97, 109}, ++{136, 93, 113}, ++{148, 88, 118}, ++{161, 82, 123}, ++{175, 76, 128}, ++{189, 70, 133}, ++{204, 65, 137}, ++{209, 62, 139}, ++{130, 99, 110}, ++{139, 95, 114}, ++{150, 89, 118}, ++{163, 83, 123}, ++{177, 77, 128}, ++{191, 71, 133}, ++{205, 65, 138}, ++{210, 63, 139}, ++{133, 100, 111}, ++{141, 96, 115}, ++{153, 90, 119}, ++{166, 84, 124}, ++{179, 78, 129}, ++{193, 72, 133}, ++{207, 66, 138}, ++{212, 64, 140}, ++{136, 101, 112}, ++{144, 97, 115}, ++{155, 91, 120}, ++{168, 85, 124}, ++{181, 79, 129}, ++{195, 73, 134}, ++{209, 67, 138}, ++{214, 65, 140}, ++{140, 102, 113}, ++{147, 98, 116}, ++{158, 92, 120}, ++{170, 86, 125}, ++{183, 80, 130}, ++{197, 74, 134}, ++{210, 68, 138}, ++{216, 65, 140}, ++{143, 103, 114}, ++{150, 99, 117}, ++{161, 93, 121}, ++{173, 87, 126}, ++{186, 81, 130}, ++{199, 75, 134}, ++{212, 68, 139}, ++{217, 66, 140}, ++{146, 104, 115}, ++{154, 100, 118}, ++{164, 94, 122}, ++{175, 88, 126}, ++{188, 82, 130}, ++{201, 75, 135}, ++{214, 69, 139}, ++{219, 67, 140}, ++{150, 105, 116}, ++{157, 101, 119}, ++{167, 95, 122}, ++{178, 89, 127}, ++{190, 83, 131}, ++{203, 76, 135}, ++{216, 70, 139}, ++{221, 68, 141}, ++{153, 106, 117}, ++{160, 102, 119}, ++{170, 96, 123}, ++{181, 90, 127}, ++{193, 84, 131}, ++{206, 77, 135}, ++{218, 71, 139}, ++{223, 68, 141}, ++{157, 107, 118}, ++{163, 103, 120}, ++{173, 97, 124}, ++{184, 91, 128}, ++{196, 84, 132}, ++{208, 78, 136}, ++{221, 72, 140}, ++{225, 69, 141}, ++{160, 108, 119}, ++{167, 104, 121}, ++{176, 98, 124}, ++{187, 92, 128}, ++{198, 85, 132}, ++{210, 79, 136}, ++{223, 72, 140}, ++{228, 70, 142}, ++{164, 109, 119}, ++{170, 105, 122}, ++{179, 99, 125}, ++{189, 93, 129}, ++{201, 86, 133}, ++{213, 80, 137}, ++{225, 73, 140}, ++{230, 71, 142}, ++{167, 109, 120}, ++{173, 105, 123}, ++{182, 100, 126}, ++{192, 94, 129}, ++{204, 87, 133}, ++{215, 81, 137}, ++{228, 74, 141}, ++{232, 72, 142}, ++{171, 110, 121}, ++{177, 106, 123}, ++{185, 101, 126}, ++{195, 94, 130}, ++{206, 88, 134}, ++{218, 81, 137}, ++{230, 75, 141}, ++{235, 73, 142}, ++{175, 111, 122}, ++{180, 107, 124}, ++{189, 101, 127}, ++{198, 95, 130}, ++{209, 89, 134}, ++{221, 82, 138}, ++{232, 76, 141}, ++{237, 73, 143}, ++{178, 112, 123}, ++{184, 108, 125}, ++{192, 102, 128}, ++{202, 96, 131}, ++{212, 90, 134}, ++{223, 83, 138}, ++{235, 77, 142}, ++{239, 74, 143}, ++{180, 112, 123}, ++{186, 108, 125}, ++{194, 103, 128}, ++{203, 96, 131}, ++{214, 90, 135}, ++{225, 84, 138}, ++{236, 77, 142}, ++{241, 75, 143}, ++{180, 112, 123}, ++{186, 108, 125}, ++{194, 103, 128}, ++{203, 96, 131}, ++{214, 90, 135}, ++{225, 84, 138}, ++{236, 77, 142}, ++{241, 75, 143}, ++{180, 112, 123}, ++{186, 108, 125}, ++{194, 103, 128}, ++{203, 96, 131}, ++{214, 90, 135}, ++{225, 84, 138}, ++{236, 77, 142}, ++{241, 75, 143}, ++{180, 112, 123}, ++{186, 108, 125}, ++{194, 103, 128}, ++{203, 96, 131}, ++{214, 90, 135}, ++{225, 84, 138}, ++{236, 77, 142}, ++{241, 75, 143}, ++{108, 82, 99}, ++{119, 81, 104}, ++{133, 78, 111}, ++{149, 74, 117}, ++{164, 69, 123}, ++{180, 64, 129}, ++{195, 59, 134}, ++{201, 57, 136}, ++{108, 82, 99}, ++{119, 81, 104}, ++{134, 78, 111}, ++{149, 74, 117}, ++{164, 69, 123}, ++{180, 64, 129}, ++{195, 59, 134}, ++{201, 57, 136}, ++{109, 83, 99}, ++{120, 81, 104}, ++{134, 78, 111}, ++{149, 74, 117}, ++{165, 69, 123}, ++{180, 64, 129}, ++{195, 59, 134}, ++{201, 57, 136}, ++{110, 83, 99}, ++{121, 82, 105}, ++{135, 79, 111}, ++{150, 74, 117}, ++{165, 70, 123}, ++{181, 64, 129}, ++{196, 59, 134}, ++{201, 57, 136}, ++{111, 84, 100}, ++{122, 82, 105}, ++{136, 79, 111}, ++{151, 75, 118}, ++{166, 70, 124}, ++{181, 65, 129}, ++{196, 60, 134}, ++{202, 58, 136}, ++{113, 85, 101}, ++{123, 83, 106}, ++{137, 80, 112}, ++{152, 75, 118}, ++{167, 70, 124}, ++{182, 65, 129}, ++{197, 60, 134}, ++{203, 58, 136}, ++{115, 87, 101}, ++{125, 84, 106}, ++{138, 81, 112}, ++{153, 76, 118}, ++{168, 71, 124}, ++{183, 66, 129}, ++{198, 60, 134}, ++{203, 58, 136}, ++{117, 88, 102}, ++{127, 85, 107}, ++{140, 81, 113}, ++{154, 77, 119}, ++{169, 72, 124}, ++{184, 66, 130}, ++{199, 61, 135}, ++{204, 59, 136}, ++{119, 89, 103}, ++{129, 87, 108}, ++{141, 82, 113}, ++{156, 77, 119}, ++{170, 72, 125}, ++{185, 67, 130}, ++{200, 61, 135}, ++{205, 59, 136}, ++{121, 91, 104}, ++{131, 88, 108}, ++{143, 83, 114}, ++{157, 78, 119}, ++{172, 73, 125}, ++{186, 67, 130}, ++{201, 62, 135}, ++{206, 60, 137}, ++{124, 92, 105}, ++{133, 89, 109}, ++{145, 84, 114}, ++{159, 79, 120}, ++{173, 74, 125}, ++{188, 68, 130}, ++{202, 62, 135}, ++{208, 60, 137}, ++{126, 94, 106}, ++{135, 90, 110}, ++{147, 85, 115}, ++{161, 80, 120}, ++{175, 74, 126}, ++{189, 69, 131}, ++{204, 63, 135}, ++{209, 61, 137}, ++{129, 95, 107}, ++{138, 91, 111}, ++{150, 87, 116}, ++{163, 81, 121}, ++{177, 75, 126}, ++{191, 70, 131}, ++{205, 64, 136}, ++{210, 62, 137}, ++{132, 96, 108}, ++{141, 93, 111}, ++{152, 88, 116}, ++{165, 82, 121}, ++{179, 76, 126}, ++{193, 70, 131}, ++{207, 64, 136}, ++{212, 62, 137}, ++{135, 98, 109}, ++{143, 94, 112}, ++{155, 89, 117}, ++{167, 83, 122}, ++{181, 77, 127}, ++{194, 71, 131}, ++{208, 65, 136}, ++{213, 63, 138}, ++{138, 99, 110}, ++{146, 95, 113}, ++{157, 90, 118}, ++{170, 84, 122}, ++{183, 78, 127}, ++{196, 72, 132}, ++{210, 66, 136}, ++{215, 64, 138}, ++{142, 100, 111}, ++{149, 96, 114}, ++{160, 91, 118}, ++{172, 85, 123}, ++{185, 79, 128}, ++{198, 73, 132}, ++{212, 67, 137}, ++{217, 65, 138}, ++{145, 101, 112}, ++{152, 97, 115}, ++{163, 92, 119}, ++{175, 86, 123}, ++{187, 80, 128}, ++{200, 74, 133}, ++{214, 68, 137}, ++{219, 65, 138}, ++{148, 102, 113}, ++{155, 98, 116}, ++{165, 93, 120}, ++{177, 87, 124}, ++{190, 81, 128}, ++{203, 74, 133}, ++{216, 68, 137}, ++{221, 66, 139}, ++{152, 103, 114}, ++{159, 99, 117}, ++{168, 94, 120}, ++{180, 88, 125}, ++{192, 82, 129}, ++{205, 75, 133}, ++{218, 69, 137}, ++{223, 67, 139}, ++{155, 104, 115}, ++{162, 100, 117}, ++{171, 95, 121}, ++{182, 89, 125}, ++{194, 83, 129}, ++{207, 76, 134}, ++{220, 70, 138}, ++{225, 68, 139}, ++{158, 105, 116}, ++{165, 101, 118}, ++{174, 96, 122}, ++{185, 90, 126}, ++{197, 83, 130}, ++{209, 77, 134}, ++{222, 71, 138}, ++{227, 69, 140}, ++{162, 106, 117}, ++{168, 102, 119}, ++{177, 97, 122}, ++{188, 91, 126}, ++{200, 84, 130}, ++{212, 78, 134}, ++{224, 72, 138}, ++{229, 69, 140}, ++{165, 107, 117}, ++{172, 103, 120}, ++{181, 98, 123}, ++{191, 92, 127}, ++{202, 85, 131}, ++{214, 79, 135}, ++{226, 73, 139}, ++{231, 70, 140}, ++{169, 108, 118}, ++{175, 104, 121}, ++{184, 99, 124}, ++{194, 92, 127}, ++{205, 86, 131}, ++{217, 80, 135}, ++{229, 73, 139}, ++{233, 71, 140}, ++{173, 109, 119}, ++{179, 105, 121}, ++{187, 99, 125}, ++{197, 93, 128}, ++{208, 87, 132}, ++{219, 81, 136}, ++{231, 74, 139}, ++{236, 72, 141}, ++{176, 109, 120}, ++{182, 106, 122}, ++{190, 100, 125}, ++{200, 94, 129}, ++{211, 88, 132}, ++{222, 81, 136}, ++{234, 75, 140}, ++{238, 73, 141}, ++{180, 110, 121}, ++{185, 106, 123}, ++{193, 101, 126}, ++{203, 95, 129}, ++{213, 89, 133}, ++{225, 82, 136}, ++{236, 76, 140}, ++{241, 74, 141}, ++{182, 110, 121}, ++{187, 107, 123}, ++{195, 101, 126}, ++{204, 95, 129}, ++{215, 89, 133}, ++{226, 83, 137}, ++{237, 76, 140}, ++{242, 74, 141}, ++{182, 110, 121}, ++{187, 107, 123}, ++{195, 101, 126}, ++{204, 95, 129}, ++{215, 89, 133}, ++{226, 83, 137}, ++{237, 76, 140}, ++{242, 74, 141}, ++{182, 110, 121}, ++{187, 107, 123}, ++{195, 101, 126}, ++{204, 95, 129}, ++{215, 89, 133}, ++{226, 83, 137}, ++{237, 76, 140}, ++{242, 74, 141}, ++{182, 110, 121}, ++{187, 107, 123}, ++{195, 101, 126}, ++{204, 95, 129}, ++{215, 89, 133}, ++{226, 83, 137}, ++{237, 76, 140}, ++{242, 74, 141}, ++{111, 79, 96}, ++{122, 78, 102}, ++{136, 76, 108}, ++{151, 72, 115}, ++{166, 68, 121}, ++{181, 63, 127}, ++{196, 58, 132}, ++{202, 56, 134}, ++{111, 80, 97}, ++{122, 79, 102}, ++{136, 76, 108}, ++{151, 72, 115}, ++{166, 68, 121}, ++{181, 63, 127}, ++{197, 58, 132}, ++{202, 56, 134}, ++{112, 80, 97}, ++{122, 79, 102}, ++{136, 76, 109}, ++{151, 72, 115}, ++{167, 68, 121}, ++{182, 63, 127}, ++{197, 58, 132}, ++{202, 56, 134}, ++{113, 81, 97}, ++{123, 80, 102}, ++{137, 77, 109}, ++{152, 73, 115}, ++{167, 68, 121}, ++{182, 63, 127}, ++{197, 58, 132}, ++{203, 56, 134}, ++{114, 82, 98}, ++{124, 80, 103}, ++{138, 77, 109}, ++{153, 73, 115}, ++{168, 69, 121}, ++{183, 64, 127}, ++{198, 59, 132}, ++{203, 57, 134}, ++{116, 83, 98}, ++{126, 81, 103}, ++{139, 78, 109}, ++{154, 74, 116}, ++{169, 69, 122}, ++{184, 64, 127}, ++{199, 59, 132}, ++{204, 57, 134}, ++{117, 84, 99}, ++{127, 82, 104}, ++{140, 79, 110}, ++{155, 74, 116}, ++{170, 70, 122}, ++{185, 65, 127}, ++{199, 59, 132}, ++{205, 57, 134}, ++{119, 86, 100}, ++{129, 83, 105}, ++{142, 80, 110}, ++{156, 75, 116}, ++{171, 70, 122}, ++{186, 65, 127}, ++{200, 60, 133}, ++{206, 58, 134}, ++{121, 87, 101}, ++{131, 84, 105}, ++{144, 81, 111}, ++{158, 76, 117}, ++{172, 71, 122}, ++{187, 66, 128}, ++{201, 60, 133}, ++{207, 58, 135}, ++{124, 88, 102}, ++{133, 86, 106}, ++{145, 82, 111}, ++{159, 77, 117}, ++{174, 72, 123}, ++{188, 66, 128}, ++{202, 61, 133}, ++{208, 59, 135}, ++{126, 90, 103}, ++{135, 87, 107}, ++{147, 83, 112}, ++{161, 78, 118}, ++{175, 72, 123}, ++{189, 67, 128}, ++{204, 62, 133}, ++{209, 59, 135}, ++{129, 91, 104}, ++{138, 88, 108}, ++{150, 84, 113}, ++{163, 79, 118}, ++{177, 73, 123}, ++{191, 68, 129}, ++{205, 62, 133}, ++{210, 60, 135}, ++{132, 93, 105}, ++{140, 89, 108}, ++{152, 85, 113}, ++{165, 80, 119}, ++{179, 74, 124}, ++{192, 68, 129}, ++{207, 63, 134}, ++{212, 61, 135}, ++{135, 94, 106}, ++{143, 91, 109}, ++{154, 86, 114}, ++{167, 81, 119}, ++{180, 75, 124}, ++{194, 69, 129}, ++{208, 64, 134}, ++{213, 61, 136}, ++{138, 96, 107}, ++{146, 92, 110}, ++{157, 87, 115}, ++{169, 82, 120}, ++{182, 76, 125}, ++{196, 70, 129}, ++{210, 64, 134}, ++{215, 62, 136}, ++{141, 97, 108}, ++{148, 93, 111}, ++{159, 88, 115}, ++{171, 83, 120}, ++{184, 77, 125}, ++{198, 71, 130}, ++{211, 65, 134}, ++{217, 63, 136}, ++{144, 98, 109}, ++{151, 94, 112}, ++{162, 89, 116}, ++{174, 84, 121}, ++{187, 78, 126}, ++{200, 72, 130}, ++{213, 66, 135}, ++{218, 64, 136}, ++{147, 99, 110}, ++{154, 95, 113}, ++{165, 90, 117}, ++{176, 85, 121}, ++{189, 79, 126}, ++{202, 73, 131}, ++{215, 67, 135}, ++{220, 64, 137}, ++{150, 100, 111}, ++{157, 97, 114}, ++{167, 91, 118}, ++{179, 86, 122}, ++{191, 80, 126}, ++{204, 73, 131}, ++{217, 67, 135}, ++{222, 65, 137}, ++{154, 101, 112}, ++{161, 98, 114}, ++{170, 92, 118}, ++{181, 87, 123}, ++{194, 80, 127}, ++{206, 74, 131}, ++{219, 68, 136}, ++{224, 66, 137}, ++{157, 103, 113}, ++{164, 99, 115}, ++{173, 93, 119}, ++{184, 88, 123}, ++{196, 81, 127}, ++{208, 75, 132}, ++{221, 69, 136}, ++{226, 67, 137}, ++{160, 104, 114}, ++{167, 100, 116}, ++{176, 94, 120}, ++{187, 88, 124}, ++{199, 82, 128}, ++{211, 76, 132}, ++{223, 70, 136}, ++{228, 68, 138}, ++{164, 104, 115}, ++{170, 101, 117}, ++{179, 95, 121}, ++{190, 89, 124}, ++{201, 83, 128}, ++{213, 77, 133}, ++{226, 71, 137}, ++{230, 69, 138}, ++{167, 105, 115}, ++{173, 102, 118}, ++{182, 96, 121}, ++{193, 90, 125}, ++{204, 84, 129}, ++{216, 78, 133}, ++{228, 72, 137}, ++{232, 69, 138}, ++{171, 106, 116}, ++{177, 102, 119}, ++{185, 97, 122}, ++{195, 91, 126}, ++{206, 85, 129}, ++{218, 79, 133}, ++{230, 73, 137}, ++{235, 70, 139}, ++{174, 107, 117}, ++{180, 103, 120}, ++{189, 98, 123}, ++{198, 92, 126}, ++{209, 86, 130}, ++{221, 80, 134}, ++{232, 73, 138}, ++{237, 71, 139}, ++{178, 108, 118}, ++{184, 104, 120}, ++{192, 99, 123}, ++{201, 93, 127}, ++{212, 87, 130}, ++{223, 81, 134}, ++{235, 74, 138}, ++{239, 72, 139}, ++{181, 109, 119}, ++{187, 105, 121}, ++{195, 100, 124}, ++{204, 94, 127}, ++{215, 88, 131}, ++{226, 81, 135}, ++{237, 75, 138}, ++{242, 73, 140}, ++{183, 109, 119}, ++{189, 105, 122}, ++{197, 100, 124}, ++{206, 94, 128}, ++{216, 88, 131}, ++{227, 82, 135}, ++{239, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{189, 105, 122}, ++{197, 100, 124}, ++{206, 94, 128}, ++{216, 88, 131}, ++{227, 82, 135}, ++{239, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{189, 105, 122}, ++{197, 100, 124}, ++{206, 94, 128}, ++{216, 88, 131}, ++{227, 82, 135}, ++{239, 76, 138}, ++{243, 73, 140}, ++{183, 109, 119}, ++{189, 105, 122}, ++{197, 100, 124}, ++{206, 94, 128}, ++{216, 88, 131}, ++{227, 82, 135}, ++{239, 76, 138}, ++{243, 73, 140}, ++{114, 77, 94}, ++{124, 76, 100}, ++{138, 74, 106}, ++{153, 71, 113}, ++{168, 66, 119}, ++{183, 62, 124}, ++{198, 57, 130}, ++{204, 55, 132}, ++{114, 77, 94}, ++{125, 76, 100}, ++{138, 74, 106}, ++{153, 71, 113}, ++{168, 66, 119}, ++{183, 62, 125}, ++{198, 57, 130}, ++{204, 55, 132}, ++{115, 78, 95}, ++{125, 77, 100}, ++{139, 74, 106}, ++{153, 71, 113}, ++{168, 67, 119}, ++{183, 62, 125}, ++{198, 57, 130}, ++{204, 55, 132}, ++{116, 78, 95}, ++{126, 77, 100}, ++{139, 75, 106}, ++{154, 71, 113}, ++{169, 67, 119}, ++{184, 62, 125}, ++{199, 57, 130}, ++{204, 55, 132}, ++{117, 79, 95}, ++{127, 78, 101}, ++{140, 75, 107}, ++{155, 72, 113}, ++{170, 67, 119}, ++{185, 63, 125}, ++{199, 58, 130}, ++{205, 56, 132}, ++{118, 80, 96}, ++{128, 79, 101}, ++{141, 76, 107}, ++{156, 72, 113}, ++{170, 68, 119}, ++{185, 63, 125}, ++{200, 58, 130}, ++{206, 56, 132}, ++{120, 82, 97}, ++{130, 80, 102}, ++{143, 77, 108}, ++{157, 73, 114}, ++{171, 68, 120}, ++{186, 63, 125}, ++{201, 58, 130}, ++{206, 57, 132}, ++{122, 83, 98}, ++{131, 81, 102}, ++{144, 78, 108}, ++{158, 74, 114}, ++{173, 69, 120}, ++{187, 64, 125}, ++{202, 59, 131}, ++{207, 57, 132}, ++{124, 85, 99}, ++{133, 82, 103}, ++{146, 79, 109}, ++{160, 74, 115}, ++{174, 70, 120}, ++{188, 65, 126}, ++{203, 59, 131}, ++{208, 57, 133}, ++{126, 86, 99}, ++{135, 84, 104}, ++{148, 80, 109}, ++{161, 75, 115}, ++{175, 70, 121}, ++{190, 65, 126}, ++{204, 60, 131}, ++{209, 58, 133}, ++{129, 88, 100}, ++{138, 85, 105}, ++{150, 81, 110}, ++{163, 76, 115}, ++{177, 71, 121}, ++{191, 66, 126}, ++{205, 61, 131}, ++{211, 59, 133}, ++{131, 89, 101}, ++{140, 86, 105}, ++{152, 82, 110}, ++{165, 77, 116}, ++{178, 72, 121}, ++{193, 67, 126}, ++{207, 61, 131}, ++{212, 59, 133}, ++{134, 90, 102}, ++{142, 87, 106}, ++{154, 83, 111}, ++{167, 78, 116}, ++{180, 73, 122}, ++{194, 67, 127}, ++{208, 62, 132}, ++{213, 60, 133}, ++{137, 92, 103}, ++{145, 89, 107}, ++{156, 84, 112}, ++{169, 79, 117}, ++{182, 74, 122}, ++{196, 68, 127}, ++{210, 63, 132}, ++{215, 61, 134}, ++{140, 93, 104}, ++{148, 90, 108}, ++{159, 85, 113}, ++{171, 80, 118}, ++{184, 75, 123}, ++{198, 69, 127}, ++{211, 63, 132}, ++{216, 61, 134}, ++{143, 95, 105}, ++{151, 91, 109}, ++{161, 86, 113}, ++{173, 81, 118}, ++{186, 76, 123}, ++{199, 70, 128}, ++{213, 64, 132}, ++{218, 62, 134}, ++{146, 96, 107}, ++{153, 92, 110}, ++{164, 88, 114}, ++{176, 82, 119}, ++{188, 76, 124}, ++{201, 71, 128}, ++{215, 65, 133}, ++{220, 63, 134}, ++{149, 97, 108}, ++{156, 94, 111}, ++{166, 89, 115}, ++{178, 83, 119}, ++{190, 77, 124}, ++{203, 72, 129}, ++{217, 66, 133}, ++{221, 64, 135}, ++{152, 98, 109}, ++{159, 95, 112}, ++{169, 90, 116}, ++{181, 84, 120}, ++{193, 78, 125}, ++{206, 72, 129}, ++{218, 67, 133}, ++{223, 64, 135}, ++{156, 100, 110}, ++{162, 96, 112}, ++{172, 91, 116}, ++{183, 85, 121}, ++{195, 79, 125}, ++{208, 73, 129}, ++{220, 67, 134}, ++{225, 65, 135}, ++{159, 101, 111}, ++{166, 97, 113}, ++{175, 92, 117}, ++{186, 86, 121}, ++{198, 80, 126}, ++{210, 74, 130}, ++{223, 68, 134}, ++{227, 66, 136}, ++{162, 102, 112}, ++{169, 98, 114}, ++{178, 93, 118}, ++{189, 87, 122}, ++{200, 81, 126}, ++{212, 75, 130}, ++{225, 69, 134}, ++{229, 67, 136}, ++{166, 103, 113}, ++{172, 99, 115}, ++{181, 94, 119}, ++{191, 88, 122}, ++{203, 82, 127}, ++{215, 76, 131}, ++{227, 70, 135}, ++{232, 68, 136}, ++{169, 104, 113}, ++{175, 100, 116}, ++{184, 95, 119}, ++{194, 89, 123}, ++{205, 83, 127}, ++{217, 77, 131}, ++{229, 71, 135}, ++{234, 69, 137}, ++{173, 105, 114}, ++{179, 101, 117}, ++{187, 96, 120}, ++{197, 90, 124}, ++{208, 84, 128}, ++{219, 78, 132}, ++{231, 72, 136}, ++{236, 69, 137}, ++{176, 105, 115}, ++{182, 102, 118}, ++{190, 97, 121}, ++{200, 91, 124}, ++{211, 85, 128}, ++{222, 79, 132}, ++{234, 73, 136}, ++{238, 70, 137}, ++{180, 106, 116}, ++{185, 103, 118}, ++{193, 98, 121}, ++{203, 92, 125}, ++{213, 86, 129}, ++{225, 80, 132}, ++{236, 73, 136}, ++{241, 71, 138}, ++{183, 107, 117}, ++{189, 103, 119}, ++{197, 98, 122}, ++{206, 93, 126}, ++{216, 87, 129}, ++{227, 80, 133}, ++{239, 74, 137}, ++{243, 72, 138}, ++{185, 107, 118}, ++{190, 104, 120}, ++{198, 99, 123}, ++{207, 93, 126}, ++{218, 87, 129}, ++{229, 81, 133}, ++{240, 75, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{190, 104, 120}, ++{198, 99, 123}, ++{207, 93, 126}, ++{218, 87, 129}, ++{229, 81, 133}, ++{240, 75, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{190, 104, 120}, ++{198, 99, 123}, ++{207, 93, 126}, ++{218, 87, 129}, ++{229, 81, 133}, ++{240, 75, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{190, 104, 120}, ++{198, 99, 123}, ++{207, 93, 126}, ++{218, 87, 129}, ++{229, 81, 133}, ++{240, 75, 137}, ++{244, 72, 138}, ++{117, 74, 92}, ++{127, 74, 97}, ++{140, 72, 104}, ++{155, 69, 110}, ++{170, 65, 117}, ++{185, 61, 122}, ++{200, 56, 128}, ++{205, 54, 130}, ++{117, 74, 92}, ++{127, 74, 97}, ++{141, 72, 104}, ++{155, 69, 110}, ++{170, 65, 117}, ++{185, 61, 122}, ++{200, 56, 128}, ++{205, 54, 130}, ++{117, 75, 92}, ++{128, 74, 98}, ++{141, 72, 104}, ++{155, 69, 110}, ++{170, 65, 117}, ++{185, 61, 122}, ++{200, 56, 128}, ++{206, 54, 130}, ++{118, 76, 93}, ++{128, 75, 98}, ++{142, 73, 104}, ++{156, 70, 111}, ++{171, 66, 117}, ++{186, 61, 123}, ++{200, 56, 128}, ++{206, 55, 130}, ++{120, 77, 93}, ++{130, 76, 98}, ++{143, 74, 105}, ++{157, 70, 111}, ++{172, 66, 117}, ++{186, 61, 123}, ++{201, 57, 128}, ++{206, 55, 130}, ++{121, 78, 94}, ++{131, 77, 99}, ++{144, 74, 105}, ++{158, 71, 111}, ++{172, 66, 117}, ++{187, 62, 123}, ++{202, 57, 128}, ++{207, 55, 130}, ++{123, 79, 95}, ++{132, 78, 99}, ++{145, 75, 105}, ++{159, 71, 111}, ++{173, 67, 117}, ++{188, 62, 123}, ++{202, 57, 128}, ++{208, 56, 130}, ++{125, 81, 95}, ++{134, 79, 100}, ++{146, 76, 106}, ++{160, 72, 112}, ++{174, 68, 118}, ++{189, 63, 123}, ++{203, 58, 128}, ++{209, 56, 130}, ++{127, 82, 96}, ++{136, 80, 101}, ++{148, 77, 106}, ++{162, 73, 112}, ++{176, 68, 118}, ++{190, 63, 124}, ++{204, 58, 129}, ++{210, 57, 131}, ++{129, 84, 97}, ++{138, 81, 102}, ++{150, 78, 107}, ++{163, 74, 113}, ++{177, 69, 118}, ++{191, 64, 124}, ++{206, 59, 129}, ++{211, 57, 131}, ++{131, 85, 98}, ++{140, 83, 102}, ++{152, 79, 108}, ++{165, 75, 113}, ++{179, 70, 119}, ++{193, 65, 124}, ++{207, 60, 129}, ++{212, 58, 131}, ++{134, 87, 99}, ++{142, 84, 103}, ++{154, 80, 108}, ++{167, 76, 114}, ++{180, 71, 119}, ++{194, 66, 124}, ++{208, 60, 129}, ++{213, 58, 131}, ++{137, 88, 100}, ++{145, 85, 104}, ++{156, 81, 109}, ++{169, 77, 114}, ++{182, 72, 120}, ++{196, 66, 125}, ++{210, 61, 130}, ++{215, 59, 131}, ++{139, 90, 101}, ++{147, 87, 105}, ++{158, 82, 110}, ++{171, 78, 115}, ++{184, 72, 120}, ++{197, 67, 125}, ++{211, 62, 130}, ++{216, 60, 132}, ++{142, 91, 102}, ++{150, 88, 106}, ++{161, 84, 110}, ++{173, 79, 115}, ++{186, 73, 121}, ++{199, 68, 125}, ++{213, 62, 130}, ++{218, 60, 132}, ++{145, 92, 103}, ++{153, 89, 107}, ++{163, 85, 111}, ++{175, 80, 116}, ++{188, 74, 121}, ++{201, 69, 126}, ++{214, 63, 131}, ++{219, 61, 132}, ++{148, 94, 104}, ++{156, 90, 108}, ++{166, 86, 112}, ++{177, 81, 117}, ++{190, 75, 122}, ++{203, 70, 126}, ++{216, 64, 131}, ++{221, 62, 133}, ++{151, 95, 105}, ++{158, 92, 109}, ++{168, 87, 113}, ++{180, 82, 117}, ++{192, 76, 122}, ++{205, 71, 127}, ++{218, 65, 131}, ++{223, 63, 133}, ++{154, 96, 106}, ++{161, 93, 109}, ++{171, 88, 113}, ++{182, 83, 118}, ++{194, 77, 123}, ++{207, 71, 127}, ++{220, 66, 132}, ++{225, 64, 133}, ++{158, 98, 107}, ++{164, 94, 110}, ++{174, 89, 114}, ++{185, 84, 119}, ++{197, 78, 123}, ++{209, 72, 128}, ++{222, 67, 132}, ++{227, 64, 134}, ++{161, 99, 108}, ++{168, 95, 111}, ++{177, 90, 115}, ++{188, 85, 119}, ++{199, 79, 124}, ++{211, 73, 128}, ++{224, 67, 132}, ++{229, 65, 134}, ++{164, 100, 110}, ++{171, 96, 112}, ++{180, 91, 116}, ++{190, 86, 120}, ++{202, 80, 124}, ++{214, 74, 128}, ++{226, 68, 133}, ++{231, 66, 134}, ++{168, 101, 110}, ++{174, 97, 113}, ++{183, 92, 117}, ++{193, 87, 120}, ++{204, 81, 125}, ++{216, 75, 129}, ++{228, 69, 133}, ++{233, 67, 135}, ++{171, 102, 111}, ++{177, 98, 114}, ++{186, 93, 117}, ++{196, 88, 121}, ++{207, 82, 125}, ++{218, 76, 129}, ++{230, 70, 133}, ++{235, 68, 135}, ++{174, 103, 112}, ++{180, 99, 115}, ++{189, 94, 118}, ++{199, 89, 122}, ++{209, 83, 126}, ++{221, 77, 130}, ++{233, 71, 134}, ++{237, 69, 135}, ++{178, 104, 113}, ++{184, 100, 116}, ++{192, 95, 119}, ++{201, 90, 122}, ++{212, 84, 126}, ++{223, 78, 130}, ++{235, 72, 134}, ++{240, 69, 136}, ++{181, 105, 114}, ++{187, 101, 117}, ++{195, 96, 120}, ++{204, 91, 123}, ++{215, 85, 127}, ++{226, 79, 131}, ++{238, 73, 135}, ++{242, 70, 136}, ++{185, 105, 115}, ++{190, 102, 117}, ++{198, 97, 120}, ++{207, 91, 124}, ++{218, 86, 127}, ++{229, 79, 131}, ++{240, 73, 135}, ++{244, 71, 136}, ++{187, 106, 116}, ++{192, 102, 118}, ++{200, 97, 121}, ++{209, 92, 124}, ++{219, 86, 128}, ++{230, 80, 131}, ++{241, 74, 135}, ++{245, 72, 137}, ++{187, 106, 116}, ++{192, 102, 118}, ++{200, 97, 121}, ++{209, 92, 124}, ++{219, 86, 128}, ++{230, 80, 131}, ++{241, 74, 135}, ++{245, 72, 137}, ++{187, 106, 116}, ++{192, 102, 118}, ++{200, 97, 121}, ++{209, 92, 124}, ++{219, 86, 128}, ++{230, 80, 131}, ++{241, 74, 135}, ++{245, 72, 137}, ++{187, 106, 116}, ++{192, 102, 118}, ++{200, 97, 121}, ++{209, 92, 124}, ++{219, 86, 128}, ++{230, 80, 131}, ++{241, 74, 135}, ++{245, 72, 137}, ++{120, 72, 90}, ++{130, 72, 95}, ++{143, 70, 102}, ++{157, 67, 108}, ++{172, 64, 114}, ++{187, 59, 120}, ++{201, 55, 126}, ++{207, 53, 128}, ++{120, 72, 90}, ++{130, 72, 95}, ++{143, 70, 102}, ++{157, 67, 108}, ++{172, 64, 114}, ++{187, 59, 120}, ++{201, 55, 126}, ++{207, 53, 128}, ++{120, 72, 90}, ++{130, 72, 95}, ++{143, 71, 102}, ++{158, 68, 108}, ++{172, 64, 114}, ++{187, 60, 120}, ++{202, 55, 126}, ++{207, 53, 128}, ++{121, 73, 91}, ++{131, 73, 96}, ++{144, 71, 102}, ++{158, 68, 108}, ++{173, 64, 115}, ++{187, 60, 120}, ++{202, 55, 126}, ++{208, 54, 128}, ++{122, 74, 91}, ++{132, 74, 96}, ++{145, 72, 102}, ++{159, 68, 109}, ++{173, 65, 115}, ++{188, 60, 121}, ++{203, 56, 126}, ++{208, 54, 128}, ++{124, 75, 92}, ++{133, 74, 97}, ++{146, 72, 103}, ++{160, 69, 109}, ++{174, 65, 115}, ++{189, 61, 121}, ++{203, 56, 126}, ++{209, 54, 128}, ++{125, 77, 93}, ++{135, 76, 97}, ++{147, 73, 103}, ++{161, 70, 109}, ++{175, 66, 115}, ++{190, 61, 121}, ++{204, 56, 126}, ++{209, 55, 128}, ++{127, 78, 93}, ++{136, 77, 98}, ++{149, 74, 104}, ++{162, 70, 110}, ++{176, 66, 116}, ++{191, 62, 121}, ++{205, 57, 126}, ++{210, 55, 128}, ++{129, 80, 94}, ++{138, 78, 99}, ++{150, 75, 104}, ++{164, 71, 110}, ++{178, 67, 116}, ++{192, 62, 121}, ++{206, 57, 127}, ++{211, 56, 129}, ++{131, 81, 95}, ++{140, 79, 99}, ++{152, 76, 105}, ++{165, 72, 111}, ++{179, 68, 116}, ++{193, 63, 122}, ++{207, 58, 127}, ++{212, 56, 129}, ++{134, 83, 96}, ++{142, 81, 100}, ++{154, 77, 105}, ++{167, 73, 111}, ++{180, 69, 117}, ++{194, 64, 122}, ++{208, 59, 127}, ++{214, 57, 129}, ++{136, 84, 97}, ++{145, 82, 101}, ++{156, 78, 106}, ++{169, 74, 112}, ++{182, 69, 117}, ++{196, 64, 122}, ++{210, 59, 127}, ++{215, 57, 129}, ++{139, 86, 98}, ++{147, 83, 102}, ++{158, 80, 107}, ++{171, 75, 112}, ++{184, 70, 118}, ++{197, 65, 123}, ++{211, 60, 128}, ++{216, 58, 129}, ++{142, 87, 99}, ++{150, 85, 103}, ++{160, 81, 108}, ++{173, 76, 113}, ++{186, 71, 118}, ++{199, 66, 123}, ++{213, 61, 128}, ++{218, 59, 130}, ++{144, 89, 100}, ++{152, 86, 104}, ++{163, 82, 108}, ++{175, 77, 113}, ++{188, 72, 118}, ++{201, 67, 123}, ++{214, 61, 128}, ++{219, 59, 130}, ++{147, 90, 101}, ++{155, 87, 105}, ++{165, 83, 109}, ++{177, 78, 114}, ++{190, 73, 119}, ++{203, 68, 124}, ++{216, 62, 129}, ++{221, 60, 130}, ++{150, 92, 102}, ++{158, 89, 106}, ++{168, 84, 110}, ++{179, 79, 115}, ++{192, 74, 119}, ++{205, 69, 124}, ++{218, 63, 129}, ++{223, 61, 131}, ++{153, 93, 103}, ++{160, 90, 106}, ++{170, 85, 111}, ++{182, 80, 115}, ++{194, 75, 120}, ++{207, 69, 125}, ++{219, 64, 129}, ++{224, 62, 131}, ++{157, 94, 104}, ++{163, 91, 107}, ++{173, 87, 111}, ++{184, 81, 116}, ++{196, 76, 121}, ++{209, 70, 125}, ++{221, 65, 130}, ++{226, 63, 131}, ++{160, 96, 105}, ++{166, 92, 108}, ++{176, 88, 112}, ++{187, 82, 117}, ++{198, 77, 121}, ++{211, 71, 126}, ++{223, 66, 130}, ++{228, 63, 132}, ++{163, 97, 106}, ++{169, 93, 109}, ++{179, 89, 113}, ++{189, 83, 117}, ++{201, 78, 122}, ++{213, 72, 126}, ++{225, 66, 130}, ++{230, 64, 132}, ++{166, 98, 107}, ++{173, 94, 110}, ++{181, 90, 114}, ++{192, 84, 118}, ++{203, 79, 122}, ++{215, 73, 127}, ++{228, 67, 131}, ++{232, 65, 132}, ++{170, 99, 108}, ++{176, 96, 111}, ++{184, 91, 115}, ++{195, 85, 119}, ++{206, 80, 123}, ++{218, 74, 127}, ++{230, 68, 131}, ++{234, 66, 133}, ++{173, 100, 109}, ++{179, 97, 112}, ++{187, 92, 115}, ++{197, 86, 119}, ++{208, 81, 123}, ++{220, 75, 127}, ++{232, 69, 132}, ++{236, 67, 133}, ++{176, 101, 110}, ++{182, 98, 113}, ++{190, 93, 116}, ++{200, 87, 120}, ++{211, 82, 124}, ++{222, 76, 128}, ++{234, 70, 132}, ++{239, 68, 133}, ++{180, 102, 111}, ++{185, 99, 114}, ++{193, 94, 117}, ++{203, 88, 121}, ++{214, 83, 124}, ++{225, 77, 128}, ++{236, 71, 132}, ++{241, 69, 134}, ++{183, 103, 112}, ++{189, 99, 115}, ++{197, 95, 118}, ++{206, 89, 121}, ++{216, 84, 125}, ++{227, 78, 129}, ++{239, 72, 133}, ++{243, 69, 134}, ++{187, 104, 113}, ++{192, 100, 115}, ++{200, 96, 118}, ++{209, 90, 122}, ++{219, 84, 126}, ++{230, 78, 129}, ++{241, 72, 133}, ++{246, 70, 135}, ++{188, 104, 114}, ++{194, 101, 116}, ++{201, 96, 119}, ++{210, 91, 122}, ++{221, 85, 126}, ++{231, 79, 130}, ++{242, 73, 133}, ++{247, 71, 135}, ++{188, 104, 114}, ++{194, 101, 116}, ++{201, 96, 119}, ++{210, 91, 122}, ++{221, 85, 126}, ++{231, 79, 130}, ++{242, 73, 133}, ++{247, 71, 135}, ++{188, 104, 114}, ++{194, 101, 116}, ++{201, 96, 119}, ++{210, 91, 122}, ++{221, 85, 126}, ++{231, 79, 130}, ++{242, 73, 133}, ++{247, 71, 135}, ++{188, 104, 114}, ++{194, 101, 116}, ++{201, 96, 119}, ++{210, 91, 122}, ++{221, 85, 126}, ++{231, 79, 130}, ++{242, 73, 133}, ++{247, 71, 135}, ++{122, 69, 88}, ++{132, 69, 93}, ++{145, 68, 99}, ++{159, 66, 106}, ++{174, 62, 112}, ++{188, 58, 118}, ++{203, 54, 124}, ++{208, 52, 126}, ++{123, 69, 88}, ++{132, 69, 93}, ++{145, 68, 99}, ++{159, 66, 106}, ++{174, 62, 112}, ++{189, 58, 118}, ++{203, 54, 124}, ++{209, 52, 126}, ++{123, 70, 88}, ++{133, 70, 93}, ++{146, 69, 100}, ++{160, 66, 106}, ++{174, 62, 112}, ++{189, 58, 118}, ++{203, 54, 124}, ++{209, 52, 126}, ++{124, 71, 89}, ++{134, 70, 94}, ++{146, 69, 100}, ++{160, 66, 106}, ++{175, 63, 112}, ++{189, 59, 118}, ++{204, 54, 124}, ++{209, 53, 126}, ++{125, 72, 89}, ++{135, 71, 94}, ++{147, 70, 100}, ++{161, 67, 106}, ++{175, 63, 113}, ++{190, 59, 118}, ++{204, 55, 124}, ++{210, 53, 126}, ++{127, 73, 90}, ++{136, 72, 95}, ++{148, 70, 101}, ++{162, 67, 107}, ++{176, 64, 113}, ++{191, 59, 119}, ++{205, 55, 124}, ++{210, 53, 126}, ++{128, 74, 90}, ++{137, 73, 95}, ++{149, 71, 101}, ++{163, 68, 107}, ++{177, 64, 113}, ++{191, 60, 119}, ++{206, 55, 124}, ++{211, 54, 126}, ++{130, 76, 91}, ++{139, 74, 96}, ++{151, 72, 102}, ++{164, 69, 108}, ++{178, 65, 113}, ++{192, 60, 119}, ++{207, 56, 124}, ++{212, 54, 126}, ++{132, 77, 92}, ++{141, 76, 96}, ++{152, 73, 102}, ++{166, 70, 108}, ++{180, 66, 114}, ++{194, 61, 119}, ++{208, 56, 125}, ++{213, 55, 127}, ++{134, 79, 93}, ++{143, 77, 97}, ++{154, 74, 103}, ++{167, 71, 108}, ++{181, 66, 114}, ++{195, 62, 120}, ++{209, 57, 125}, ++{214, 55, 127}, ++{136, 80, 94}, ++{145, 78, 98}, ++{156, 75, 103}, ++{169, 71, 109}, ++{182, 67, 115}, ++{196, 62, 120}, ++{210, 58, 125}, ++{215, 56, 127}, ++{139, 82, 95}, ++{147, 80, 99}, ++{158, 76, 104}, ++{171, 72, 110}, ++{184, 68, 115}, ++{198, 63, 120}, ++{211, 58, 125}, ++{216, 56, 127}, ++{141, 83, 96}, ++{149, 81, 100}, ++{160, 78, 105}, ++{173, 73, 110}, ++{186, 69, 115}, ++{199, 64, 121}, ++{213, 59, 126}, ++{218, 57, 128}, ++{144, 85, 97}, ++{152, 82, 101}, ++{162, 79, 105}, ++{175, 75, 111}, ++{187, 70, 116}, ++{201, 65, 121}, ++{214, 60, 126}, ++{219, 58, 128}, ++{147, 87, 98}, ++{154, 84, 102}, ++{165, 80, 106}, ++{177, 76, 111}, ++{189, 71, 116}, ++{202, 66, 121}, ++{216, 60, 126}, ++{221, 58, 128}, ++{150, 88, 99}, ++{157, 85, 102}, ++{167, 81, 107}, ++{179, 77, 112}, ++{191, 72, 117}, ++{204, 66, 122}, ++{217, 61, 127}, ++{222, 59, 128}, ++{153, 89, 100}, ++{160, 87, 103}, ++{170, 82, 108}, ++{181, 78, 113}, ++{193, 73, 117}, ++{206, 67, 122}, ++{219, 62, 127}, ++{224, 60, 129}, ++{156, 91, 101}, ++{163, 88, 104}, ++{172, 84, 109}, ++{183, 79, 113}, ++{196, 74, 118}, ++{208, 68, 123}, ++{221, 63, 127}, ++{226, 61, 129}, ++{159, 92, 102}, ++{165, 89, 105}, ++{175, 85, 109}, ++{186, 80, 114}, ++{198, 75, 119}, ++{210, 69, 123}, ++{223, 64, 128}, ++{228, 62, 129}, ++{162, 94, 103}, ++{168, 90, 106}, ++{178, 86, 110}, ++{188, 81, 115}, ++{200, 76, 119}, ++{212, 70, 124}, ++{225, 65, 128}, ++{230, 62, 130}, ++{165, 95, 104}, ++{171, 92, 107}, ++{180, 87, 111}, ++{191, 82, 115}, ++{202, 77, 120}, ++{215, 71, 124}, ++{227, 65, 129}, ++{232, 63, 130}, ++{168, 96, 105}, ++{174, 93, 108}, ++{183, 88, 112}, ++{194, 83, 116}, ++{205, 78, 120}, ++{217, 72, 125}, ++{229, 66, 129}, ++{234, 64, 131}, ++{172, 97, 106}, ++{178, 94, 109}, ++{186, 89, 113}, ++{196, 84, 117}, ++{207, 79, 121}, ++{219, 73, 125}, ++{231, 67, 129}, ++{236, 65, 131}, ++{175, 98, 108}, ++{181, 95, 110}, ++{189, 90, 113}, ++{199, 85, 117}, ++{210, 79, 121}, ++{221, 74, 126}, ++{233, 68, 130}, ++{238, 66, 131}, ++{178, 99, 109}, ++{184, 96, 111}, ++{192, 91, 114}, ++{202, 86, 118}, ++{213, 80, 122}, ++{224, 75, 126}, ++{236, 69, 130}, ++{240, 67, 132}, ++{182, 100, 109}, ++{187, 97, 112}, ++{195, 92, 115}, ++{205, 87, 119}, ++{215, 81, 123}, ++{226, 76, 127}, ++{238, 70, 131}, ++{242, 68, 132}, ++{185, 101, 110}, ++{190, 98, 113}, ++{198, 93, 116}, ++{208, 88, 119}, ++{218, 82, 123}, ++{229, 77, 127}, ++{240, 71, 131}, ++{245, 68, 132}, ++{188, 102, 111}, ++{194, 99, 114}, ++{201, 94, 117}, ++{211, 89, 120}, ++{221, 83, 124}, ++{231, 77, 128}, ++{243, 72, 131}, ++{247, 69, 133}, ++{190, 103, 112}, ++{195, 99, 114}, ++{203, 95, 117}, ++{212, 89, 120}, ++{222, 84, 124}, ++{233, 78, 128}, ++{244, 72, 132}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 99, 114}, ++{203, 95, 117}, ++{212, 89, 120}, ++{222, 84, 124}, ++{233, 78, 128}, ++{244, 72, 132}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 99, 114}, ++{203, 95, 117}, ++{212, 89, 120}, ++{222, 84, 124}, ++{233, 78, 128}, ++{244, 72, 132}, ++{248, 70, 133}, ++{190, 103, 112}, ++{195, 99, 114}, ++{203, 95, 117}, ++{212, 89, 120}, ++{222, 84, 124}, ++{233, 78, 128}, ++{244, 72, 132}, ++{248, 70, 133}, ++{125, 67, 86}, ++{135, 67, 91}, ++{147, 66, 97}, ++{161, 64, 104}, ++{176, 61, 110}, ++{190, 57, 116}, ++{205, 53, 122}, ++{210, 51, 124}, ++{125, 67, 86}, ++{135, 67, 91}, ++{148, 66, 97}, ++{161, 64, 104}, ++{176, 61, 110}, ++{190, 57, 116}, ++{205, 53, 122}, ++{210, 51, 124}, ++{126, 67, 86}, ++{135, 68, 91}, ++{148, 67, 97}, ++{162, 64, 104}, ++{176, 61, 110}, ++{191, 57, 116}, ++{205, 53, 122}, ++{210, 51, 124}, ++{127, 68, 87}, ++{136, 68, 91}, ++{149, 67, 98}, ++{162, 65, 104}, ++{177, 61, 110}, ++{191, 57, 116}, ++{205, 53, 122}, ++{211, 52, 124}, ++{128, 69, 87}, ++{137, 69, 92}, ++{150, 68, 98}, ++{163, 65, 104}, ++{177, 62, 110}, ++{192, 58, 116}, ++{206, 53, 122}, ++{211, 52, 124}, ++{129, 70, 88}, ++{138, 70, 92}, ++{151, 68, 98}, ++{164, 66, 105}, ++{178, 62, 111}, ++{192, 58, 117}, ++{207, 54, 122}, ++{212, 52, 124}, ++{131, 72, 88}, ++{140, 71, 93}, ++{152, 69, 99}, ++{165, 66, 105}, ++{179, 63, 111}, ++{193, 59, 117}, ++{207, 54, 122}, ++{213, 53, 124}, ++{133, 73, 89}, ++{141, 72, 94}, ++{153, 70, 99}, ++{166, 67, 105}, ++{180, 63, 111}, ++{194, 59, 117}, ++{208, 55, 122}, ++{214, 53, 124}, ++{135, 75, 90}, ++{143, 73, 94}, ++{155, 71, 100}, ++{168, 68, 106}, ++{181, 64, 112}, ++{195, 60, 117}, ++{209, 55, 123}, ++{215, 54, 125}, ++{137, 76, 91}, ++{145, 75, 95}, ++{156, 72, 101}, ++{169, 69, 106}, ++{183, 65, 112}, ++{197, 60, 118}, ++{210, 56, 123}, ++{216, 54, 125}, ++{139, 78, 92}, ++{147, 76, 96}, ++{158, 73, 101}, ++{171, 70, 107}, ++{184, 66, 112}, ++{198, 61, 118}, ++{212, 56, 123}, ++{217, 55, 125}, ++{141, 79, 93}, ++{149, 78, 97}, ++{160, 75, 102}, ++{173, 71, 107}, ++{186, 67, 113}, ++{199, 62, 118}, ++{213, 57, 123}, ++{218, 55, 125}, ++{144, 81, 94}, ++{152, 79, 98}, ++{162, 76, 103}, ++{175, 72, 108}, ++{187, 67, 113}, ++{201, 63, 119}, ++{214, 58, 124}, ++{219, 56, 126}, ++{146, 83, 95}, ++{154, 80, 99}, ++{165, 77, 103}, ++{176, 73, 109}, ++{189, 68, 114}, ++{202, 64, 119}, ++{216, 59, 124}, ++{221, 57, 126}, ++{149, 84, 96}, ++{157, 82, 99}, ++{167, 78, 104}, ++{179, 74, 109}, ++{191, 69, 114}, ++{204, 64, 119}, ++{217, 59, 124}, ++{222, 57, 126}, ++{152, 86, 97}, ++{159, 83, 100}, ++{169, 79, 105}, ++{181, 75, 110}, ++{193, 70, 115}, ++{206, 65, 120}, ++{219, 60, 125}, ++{224, 58, 127}, ++{155, 87, 98}, ++{162, 85, 101}, ++{172, 81, 106}, ++{183, 76, 111}, ++{195, 71, 115}, ++{208, 66, 120}, ++{221, 61, 125}, ++{226, 59, 127}, ++{158, 89, 99}, ++{165, 86, 102}, ++{174, 82, 107}, ++{185, 77, 111}, ++{197, 72, 116}, ++{210, 67, 121}, ++{223, 62, 126}, ++{227, 60, 127}, ++{161, 90, 100}, ++{168, 87, 103}, ++{177, 83, 107}, ++{188, 78, 112}, ++{200, 73, 117}, ++{212, 68, 121}, ++{224, 63, 126}, ++{229, 61, 128}, ++{164, 91, 101}, ++{170, 88, 104}, ++{180, 84, 108}, ++{190, 79, 113}, ++{202, 74, 117}, ++{214, 69, 122}, ++{226, 64, 126}, ++{231, 61, 128}, ++{167, 93, 102}, ++{173, 90, 105}, ++{182, 85, 109}, ++{193, 81, 113}, ++{204, 75, 118}, ++{216, 70, 122}, ++{228, 64, 127}, ++{233, 62, 128}, ++{170, 94, 103}, ++{176, 91, 106}, ++{185, 87, 110}, ++{195, 82, 114}, ++{207, 76, 118}, ++{218, 71, 123}, ++{230, 65, 127}, ++{235, 63, 129}, ++{174, 95, 105}, ++{180, 92, 107}, ++{188, 88, 111}, ++{198, 83, 115}, ++{209, 77, 119}, ++{221, 72, 123}, ++{233, 66, 128}, ++{237, 64, 129}, ++{177, 96, 106}, ++{183, 93, 108}, ++{191, 89, 111}, ++{201, 84, 115}, ++{212, 78, 120}, ++{223, 73, 124}, ++{235, 67, 128}, ++{239, 65, 130}, ++{180, 97, 107}, ++{186, 94, 109}, ++{194, 90, 112}, ++{204, 85, 116}, ++{214, 79, 120}, ++{225, 74, 124}, ++{237, 68, 128}, ++{241, 66, 130}, ++{183, 98, 108}, ++{189, 95, 110}, ++{197, 91, 113}, ++{206, 86, 117}, ++{217, 80, 121}, ++{228, 75, 125}, ++{239, 69, 129}, ++{244, 67, 130}, ++{187, 99, 109}, ++{192, 96, 111}, ++{200, 92, 114}, ++{209, 87, 117}, ++{219, 81, 121}, ++{230, 75, 125}, ++{242, 70, 129}, ++{246, 68, 131}, ++{190, 100, 110}, ++{195, 97, 112}, ++{203, 93, 115}, ++{212, 88, 118}, ++{222, 82, 122}, ++{233, 76, 126}, ++{244, 71, 130}, ++{248, 68, 131}, ++{192, 101, 110}, ++{197, 98, 112}, ++{205, 93, 115}, ++{214, 88, 119}, ++{224, 83, 122}, ++{234, 77, 126}, ++{245, 71, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{197, 98, 112}, ++{205, 93, 115}, ++{214, 88, 119}, ++{224, 83, 122}, ++{234, 77, 126}, ++{245, 71, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{197, 98, 112}, ++{205, 93, 115}, ++{214, 88, 119}, ++{224, 83, 122}, ++{234, 77, 126}, ++{245, 71, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{197, 98, 112}, ++{205, 93, 115}, ++{214, 88, 119}, ++{224, 83, 122}, ++{234, 77, 126}, ++{245, 71, 130}, ++{249, 69, 131}, ++{128, 64, 84}, ++{137, 65, 89}, ++{150, 64, 95}, ++{164, 62, 102}, ++{178, 59, 108}, ++{192, 56, 114}, ++{206, 52, 120}, ++{212, 50, 122}, ++{128, 64, 84}, ++{138, 65, 89}, ++{150, 64, 95}, ++{164, 62, 102}, ++{178, 59, 108}, ++{192, 56, 114}, ++{206, 52, 120}, ++{212, 50, 122}, ++{129, 65, 84}, ++{138, 65, 89}, ++{150, 65, 95}, ++{164, 62, 102}, ++{178, 59, 108}, ++{192, 56, 114}, ++{207, 52, 120}, ++{212, 50, 122}, ++{130, 66, 85}, ++{139, 66, 89}, ++{151, 65, 96}, ++{165, 63, 102}, ++{179, 60, 108}, ++{193, 56, 114}, ++{207, 52, 120}, ++{212, 50, 122}, ++{131, 67, 85}, ++{140, 67, 90}, ++{152, 66, 96}, ++{165, 63, 102}, ++{179, 60, 108}, ++{193, 56, 114}, ++{208, 52, 120}, ++{213, 51, 122}, ++{132, 68, 86}, ++{141, 68, 90}, ++{153, 66, 96}, ++{166, 64, 103}, ++{180, 61, 109}, ++{194, 57, 114}, ++{208, 53, 120}, ++{214, 51, 122}, ++{134, 69, 86}, ++{142, 69, 91}, ++{154, 67, 97}, ++{167, 65, 103}, ++{181, 61, 109}, ++{195, 57, 115}, ++{209, 53, 120}, ++{214, 51, 122}, ++{135, 71, 87}, ++{144, 70, 92}, ++{155, 68, 97}, ++{168, 65, 103}, ++{182, 62, 109}, ++{196, 58, 115}, ++{210, 54, 120}, ++{215, 52, 122}, ++{137, 72, 88}, ++{146, 71, 92}, ++{157, 69, 98}, ++{170, 66, 104}, ++{183, 63, 110}, ++{197, 59, 115}, ++{211, 54, 121}, ++{216, 52, 123}, ++{139, 74, 89}, ++{147, 73, 93}, ++{159, 70, 98}, ++{171, 67, 104}, ++{185, 63, 110}, ++{198, 59, 116}, ++{212, 55, 121}, ++{217, 53, 123}, ++{141, 75, 90}, ++{149, 74, 94}, ++{160, 71, 99}, ++{173, 68, 105}, ++{186, 64, 110}, ++{200, 60, 116}, ++{213, 55, 121}, ++{218, 54, 123}, ++{144, 77, 91}, ++{152, 75, 95}, ++{162, 73, 100}, ++{175, 69, 105}, ++{188, 65, 111}, ++{201, 61, 116}, ++{215, 56, 121}, ++{220, 54, 123}, ++{146, 79, 92}, ++{154, 77, 96}, ++{164, 74, 101}, ++{177, 70, 106}, ++{189, 66, 111}, ++{203, 61, 117}, ++{216, 57, 122}, ++{221, 55, 124}, ++{149, 80, 93}, ++{156, 78, 97}, ++{167, 75, 101}, ++{178, 71, 107}, ++{191, 67, 112}, ++{204, 62, 117}, ++{217, 57, 122}, ++{222, 56, 124}, ++{152, 82, 94}, ++{159, 80, 97}, ++{169, 76, 102}, ++{181, 72, 107}, ++{193, 68, 112}, ++{206, 63, 118}, ++{219, 58, 122}, ++{224, 56, 124}, ++{154, 84, 95}, ++{161, 81, 98}, ++{171, 78, 103}, ++{183, 73, 108}, ++{195, 69, 113}, ++{208, 64, 118}, ++{221, 59, 123}, ++{225, 57, 125}, ++{157, 85, 96}, ++{164, 83, 99}, ++{174, 79, 104}, ++{185, 75, 109}, ++{197, 70, 113}, ++{209, 65, 118}, ++{222, 60, 123}, ++{227, 58, 125}, ++{160, 87, 97}, ++{167, 84, 100}, ++{176, 80, 104}, ++{187, 76, 109}, ++{199, 71, 114}, ++{211, 66, 119}, ++{224, 61, 124}, ++{229, 59, 125}, ++{163, 88, 98}, ++{170, 85, 101}, ++{179, 81, 105}, ++{190, 77, 110}, ++{201, 72, 115}, ++{213, 67, 119}, ++{226, 62, 124}, ++{231, 60, 126}, ++{166, 89, 99}, ++{172, 87, 102}, ++{181, 83, 106}, ++{192, 78, 111}, ++{203, 73, 115}, ++{216, 68, 120}, ++{228, 62, 124}, ++{233, 60, 126}, ++{169, 91, 100}, ++{175, 88, 103}, ++{184, 84, 107}, ++{195, 79, 111}, ++{206, 74, 116}, ++{218, 69, 120}, ++{230, 63, 125}, ++{234, 61, 127}, ++{172, 92, 101}, ++{178, 89, 104}, ++{187, 85, 108}, ++{197, 80, 112}, ++{208, 75, 116}, ++{220, 70, 121}, ++{232, 64, 125}, ++{236, 62, 127}, ++{176, 93, 103}, ++{181, 90, 105}, ++{190, 86, 109}, ++{200, 81, 113}, ++{211, 76, 117}, ++{222, 71, 121}, ++{234, 65, 126}, ++{239, 63, 127}, ++{179, 94, 104}, ++{185, 91, 106}, ++{193, 87, 110}, ++{202, 82, 113}, ++{213, 77, 118}, ++{224, 72, 122}, ++{236, 66, 126}, ++{241, 64, 128}, ++{182, 96, 105}, ++{188, 92, 107}, ++{196, 88, 110}, ++{205, 83, 114}, ++{216, 78, 118}, ++{227, 72, 122}, ++{238, 67, 127}, ++{243, 65, 128}, ++{185, 97, 106}, ++{191, 94, 108}, ++{199, 89, 111}, ++{208, 84, 115}, ++{218, 79, 119}, ++{229, 73, 123}, ++{241, 68, 127}, ++{245, 66, 129}, ++{189, 98, 107}, ++{194, 95, 109}, ++{202, 90, 112}, ++{211, 85, 116}, ++{221, 80, 120}, ++{232, 74, 124}, ++{243, 69, 128}, ++{247, 67, 129}, ++{192, 99, 108}, ++{197, 96, 110}, ++{205, 91, 113}, ++{214, 86, 116}, ++{224, 81, 120}, ++{234, 75, 124}, ++{245, 70, 128}, ++{250, 67, 129}, ++{194, 99, 108}, ++{199, 96, 110}, ++{206, 92, 113}, ++{215, 87, 117}, ++{225, 81, 120}, ++{236, 76, 124}, ++{247, 70, 128}, ++{251, 68, 130}, ++{194, 99, 108}, ++{199, 96, 110}, ++{206, 92, 113}, ++{215, 87, 117}, ++{225, 81, 120}, ++{236, 76, 124}, ++{247, 70, 128}, ++{251, 68, 130}, ++{194, 99, 108}, ++{199, 96, 110}, ++{206, 92, 113}, ++{215, 87, 117}, ++{225, 81, 120}, ++{236, 76, 124}, ++{247, 70, 128}, ++{251, 68, 130}, ++{194, 99, 108}, ++{199, 96, 110}, ++{206, 92, 113}, ++{215, 87, 117}, ++{225, 81, 120}, ++{236, 76, 124}, ++{247, 70, 128}, ++{251, 68, 130}, ++{131, 62, 82}, ++{140, 62, 87}, ++{152, 62, 93}, ++{166, 60, 99}, ++{180, 58, 106}, ++{194, 54, 112}, ++{208, 50, 118}, ++{213, 49, 120}, ++{131, 62, 82}, ++{140, 63, 87}, ++{152, 62, 93}, ++{166, 60, 100}, ++{180, 58, 106}, ++{194, 54, 112}, ++{208, 50, 118}, ++{213, 49, 120}, ++{132, 62, 82}, ++{141, 63, 87}, ++{153, 63, 93}, ++{166, 61, 100}, ++{180, 58, 106}, ++{194, 55, 112}, ++{208, 51, 118}, ++{214, 49, 120}, ++{132, 63, 83}, ++{141, 64, 87}, ++{153, 63, 93}, ++{167, 61, 100}, ++{181, 58, 106}, ++{195, 55, 112}, ++{209, 51, 118}, ++{214, 49, 120}, ++{133, 64, 83}, ++{142, 64, 88}, ++{154, 64, 94}, ++{167, 62, 100}, ++{181, 59, 106}, ++{195, 55, 112}, ++{209, 51, 118}, ++{215, 50, 120}, ++{135, 65, 84}, ++{143, 65, 88}, ++{155, 64, 94}, ++{168, 62, 100}, ++{182, 59, 107}, ++{196, 56, 112}, ++{210, 52, 118}, ++{215, 50, 120}, ++{136, 67, 84}, ++{145, 67, 89}, ++{156, 65, 95}, ++{169, 63, 101}, ++{183, 60, 107}, ++{197, 56, 113}, ++{211, 52, 118}, ++{216, 50, 120}, ++{138, 68, 85}, ++{146, 68, 90}, ++{158, 66, 95}, ++{171, 64, 101}, ++{184, 60, 107}, ++{198, 57, 113}, ++{212, 52, 118}, ++{217, 51, 120}, ++{140, 70, 86}, ++{148, 69, 90}, ++{159, 67, 96}, ++{172, 65, 102}, ++{185, 61, 108}, ++{199, 57, 113}, ++{213, 53, 119}, ++{218, 51, 121}, ++{142, 71, 87}, ++{150, 70, 91}, ++{161, 68, 96}, ++{173, 65, 102}, ++{187, 62, 108}, ++{200, 58, 114}, ++{214, 54, 119}, ++{219, 52, 121}, ++{144, 73, 88}, ++{152, 72, 92}, ++{163, 70, 97}, ++{175, 66, 103}, ++{188, 63, 108}, ++{201, 59, 114}, ++{215, 54, 119}, ++{220, 53, 121}, ++{146, 75, 89}, ++{154, 73, 93}, ++{165, 71, 98}, ++{177, 67, 103}, ++{190, 64, 109}, ++{203, 59, 114}, ++{216, 55, 120}, ++{221, 53, 121}, ++{149, 76, 90}, ++{156, 75, 94}, ++{167, 72, 99}, ++{179, 69, 104}, ++{191, 65, 109}, ++{204, 60, 115}, ++{218, 56, 120}, ++{223, 54, 122}, ++{151, 78, 91}, ++{159, 76, 94}, ++{169, 73, 99}, ++{180, 70, 105}, ++{193, 65, 110}, ++{206, 61, 115}, ++{219, 56, 120}, ++{224, 55, 122}, ++{154, 80, 92}, ++{161, 78, 95}, ++{171, 75, 100}, ++{182, 71, 105}, ++{195, 66, 110}, ++{208, 62, 116}, ++{221, 57, 121}, ++{225, 55, 122}, ++{157, 81, 93}, ++{164, 79, 96}, ++{173, 76, 101}, ++{185, 72, 106}, ++{197, 67, 111}, ++{209, 63, 116}, ++{222, 58, 121}, ++{227, 56, 123}, ++{159, 83, 94}, ++{166, 80, 97}, ++{176, 77, 102}, ++{187, 73, 107}, ++{199, 68, 111}, ++{211, 64, 116}, ++{224, 59, 121}, ++{229, 57, 123}, ++{162, 84, 95}, ++{169, 82, 98}, ++{178, 78, 102}, ++{189, 74, 107}, ++{201, 69, 112}, ++{213, 65, 117}, ++{226, 60, 122}, ++{230, 58, 123}, ++{165, 86, 96}, ++{172, 83, 99}, ++{181, 80, 103}, ++{191, 75, 108}, ++{203, 71, 113}, ++{215, 66, 117}, ++{227, 60, 122}, ++{232, 59, 124}, ++{168, 87, 97}, ++{175, 85, 100}, ++{183, 81, 104}, ++{194, 76, 109}, ++{205, 72, 113}, ++{217, 66, 118}, ++{229, 61, 123}, ++{234, 59, 124}, ++{171, 89, 98}, ++{177, 86, 101}, ++{186, 82, 105}, ++{196, 77, 109}, ++{208, 73, 114}, ++{219, 67, 118}, ++{231, 62, 123}, ++{236, 60, 125}, ++{174, 90, 100}, ++{180, 87, 102}, ++{189, 83, 106}, ++{199, 79, 110}, ++{210, 74, 115}, ++{221, 68, 119}, ++{233, 63, 123}, ++{238, 61, 125}, ++{178, 91, 101}, ++{183, 88, 103}, ++{192, 84, 107}, ++{202, 80, 111}, ++{212, 75, 115}, ++{224, 69, 120}, ++{235, 64, 124}, ++{240, 62, 126}, ++{181, 92, 102}, ++{186, 90, 104}, ++{195, 85, 108}, ++{204, 81, 112}, ++{215, 76, 116}, ++{226, 70, 120}, ++{238, 65, 124}, ++{242, 63, 126}, ++{184, 94, 103}, ++{190, 91, 105}, ++{197, 87, 108}, ++{207, 82, 112}, ++{217, 77, 116}, ++{228, 71, 121}, ++{240, 66, 125}, ++{244, 64, 126}, ++{187, 95, 104}, ++{193, 92, 106}, ++{200, 88, 109}, ++{210, 83, 113}, ++{220, 78, 117}, ++{231, 72, 121}, ++{242, 67, 125}, ++{246, 65, 127}, ++{191, 96, 105}, ++{196, 93, 107}, ++{203, 89, 110}, ++{212, 84, 114}, ++{223, 79, 118}, ++{233, 73, 122}, ++{244, 68, 126}, ++{249, 66, 127}, ++{194, 97, 106}, ++{199, 94, 108}, ++{206, 90, 111}, ++{215, 85, 115}, ++{225, 80, 118}, ++{236, 74, 122}, ++{247, 69, 126}, ++{251, 66, 128}, ++{195, 97, 106}, ++{201, 94, 108}, ++{208, 90, 111}, ++{217, 85, 115}, ++{227, 80, 119}, ++{237, 75, 123}, ++{248, 69, 126}, ++{252, 67, 128}, ++{195, 97, 106}, ++{201, 94, 108}, ++{208, 90, 111}, ++{217, 85, 115}, ++{227, 80, 119}, ++{237, 75, 123}, ++{248, 69, 126}, ++{252, 67, 128}, ++{195, 97, 106}, ++{201, 94, 108}, ++{208, 90, 111}, ++{217, 85, 115}, ++{227, 80, 119}, ++{237, 75, 123}, ++{248, 69, 126}, ++{252, 67, 128}, ++{195, 97, 106}, ++{201, 94, 108}, ++{208, 90, 111}, ++{217, 85, 115}, ++{227, 80, 119}, ++{237, 75, 123}, ++{248, 69, 126}, ++{252, 67, 128}, ++{134, 59, 80}, ++{143, 60, 85}, ++{155, 60, 91}, ++{168, 59, 97}, ++{182, 56, 104}, ++{196, 53, 110}, ++{210, 49, 116}, ++{215, 48, 118}, ++{134, 60, 80}, ++{143, 60, 85}, ++{155, 60, 91}, ++{168, 59, 97}, ++{182, 56, 104}, ++{196, 53, 110}, ++{210, 49, 116}, ++{215, 48, 118}, ++{134, 60, 80}, ++{143, 61, 85}, ++{155, 60, 91}, ++{168, 59, 98}, ++{182, 56, 104}, ++{196, 53, 110}, ++{210, 49, 116}, ++{215, 48, 118}, ++{135, 61, 81}, ++{144, 61, 85}, ++{156, 61, 91}, ++{169, 59, 98}, ++{183, 57, 104}, ++{197, 53, 110}, ++{211, 50, 116}, ++{216, 48, 118}, ++{136, 62, 81}, ++{145, 62, 86}, ++{157, 62, 92}, ++{170, 60, 98}, ++{183, 57, 104}, ++{197, 54, 110}, ++{211, 50, 116}, ++{216, 48, 118}, ++{137, 63, 82}, ++{146, 63, 86}, ++{158, 62, 92}, ++{170, 60, 98}, ++{184, 58, 105}, ++{198, 54, 110}, ++{212, 50, 116}, ++{217, 49, 118}, ++{139, 64, 82}, ++{147, 64, 87}, ++{159, 63, 93}, ++{172, 61, 99}, ++{185, 58, 105}, ++{199, 55, 111}, ++{212, 51, 116}, ++{218, 49, 118}, ++{141, 66, 83}, ++{149, 65, 88}, ++{160, 64, 93}, ++{173, 62, 99}, ++{186, 59, 105}, ++{200, 55, 111}, ++{213, 51, 116}, ++{218, 50, 118}, ++{142, 67, 84}, ++{150, 67, 88}, ++{162, 65, 94}, ++{174, 63, 100}, ++{187, 60, 106}, ++{201, 56, 111}, ++{214, 52, 117}, ++{219, 50, 119}, ++{144, 69, 85}, ++{152, 68, 89}, ++{163, 66, 94}, ++{175, 64, 100}, ++{188, 60, 106}, ++{202, 57, 112}, ++{215, 52, 117}, ++{220, 51, 119}, ++{146, 71, 86}, ++{154, 70, 90}, ++{165, 68, 95}, ++{177, 65, 101}, ++{190, 61, 106}, ++{203, 57, 112}, ++{217, 53, 117}, ++{222, 51, 119}, ++{149, 72, 87}, ++{156, 71, 91}, ++{167, 69, 96}, ++{179, 66, 101}, ++{191, 62, 107}, ++{205, 58, 112}, ++{218, 54, 118}, ++{223, 52, 119}, ++{151, 74, 88}, ++{159, 73, 92}, ++{169, 70, 96}, ++{181, 67, 102}, ++{193, 63, 107}, ++{206, 59, 113}, ++{219, 54, 118}, ++{224, 53, 120}, ++{154, 76, 89}, ++{161, 74, 92}, ++{171, 71, 97}, ++{182, 68, 102}, ++{195, 64, 108}, ++{208, 60, 113}, ++{221, 55, 118}, ++{226, 53, 120}, ++{156, 77, 90}, ++{163, 75, 93}, ++{173, 73, 98}, ++{184, 69, 103}, ++{197, 65, 108}, ++{209, 61, 114}, ++{222, 56, 119}, ++{227, 54, 120}, ++{159, 79, 91}, ++{166, 77, 94}, ++{175, 74, 99}, ++{187, 70, 104}, ++{199, 66, 109}, ++{211, 61, 114}, ++{224, 57, 119}, ++{229, 55, 121}, ++{162, 81, 92}, ++{168, 78, 95}, ++{178, 75, 100}, ++{189, 71, 105}, ++{201, 67, 110}, ++{213, 62, 115}, ++{225, 58, 119}, ++{230, 56, 121}, ++{164, 82, 93}, ++{171, 80, 96}, ++{180, 76, 101}, ++{191, 72, 105}, ++{203, 68, 110}, ++{215, 63, 115}, ++{227, 58, 120}, ++{232, 57, 122}, ++{167, 84, 94}, ++{174, 81, 97}, ++{183, 78, 101}, ++{193, 74, 106}, ++{205, 69, 111}, ++{217, 64, 116}, ++{229, 59, 120}, ++{234, 57, 122}, ++{170, 85, 95}, ++{177, 83, 98}, ++{185, 79, 102}, ++{196, 75, 107}, ++{207, 70, 111}, ++{219, 65, 116}, ++{231, 60, 121}, ++{236, 58, 122}, ++{173, 87, 97}, ++{179, 84, 99}, ++{188, 80, 103}, ++{198, 76, 107}, ++{209, 71, 112}, ++{221, 66, 117}, ++{233, 61, 121}, ++{237, 59, 123}, ++{176, 88, 98}, ++{182, 85, 100}, ++{191, 81, 104}, ++{201, 77, 108}, ++{212, 72, 113}, ++{223, 67, 117}, ++{235, 62, 122}, ++{239, 60, 123}, ++{180, 89, 99}, ++{185, 87, 101}, ++{194, 83, 105}, ++{203, 78, 109}, ++{214, 73, 113}, ++{225, 68, 118}, ++{237, 63, 122}, ++{241, 61, 124}, ++{183, 91, 100}, ++{188, 88, 102}, ++{196, 84, 106}, ++{206, 79, 110}, ++{216, 74, 114}, ++{228, 69, 118}, ++{239, 64, 123}, ++{244, 62, 124}, ++{186, 92, 101}, ++{191, 89, 103}, ++{199, 85, 107}, ++{209, 80, 110}, ++{219, 75, 115}, ++{230, 70, 119}, ++{241, 65, 123}, ++{246, 63, 125}, ++{189, 93, 102}, ++{194, 90, 104}, ++{202, 86, 107}, ++{211, 81, 111}, ++{222, 76, 115}, ++{232, 71, 119}, ++{244, 66, 124}, ++{248, 64, 125}, ++{192, 94, 103}, ++{198, 91, 105}, ++{205, 87, 108}, ++{214, 82, 112}, ++{224, 77, 116}, ++{235, 72, 120}, ++{246, 67, 124}, ++{250, 65, 126}, ++{196, 95, 104}, ++{201, 92, 106}, ++{208, 88, 109}, ++{217, 83, 113}, ++{227, 78, 117}, ++{237, 73, 120}, ++{248, 68, 124}, ++{252, 65, 126}, ++{197, 96, 104}, ++{202, 93, 107}, ++{210, 89, 110}, ++{218, 84, 113}, ++{228, 79, 117}, ++{239, 73, 121}, ++{249, 68, 125}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 107}, ++{210, 89, 110}, ++{218, 84, 113}, ++{228, 79, 117}, ++{239, 73, 121}, ++{249, 68, 125}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 107}, ++{210, 89, 110}, ++{218, 84, 113}, ++{228, 79, 117}, ++{239, 73, 121}, ++{249, 68, 125}, ++{254, 66, 126}, ++{197, 96, 104}, ++{202, 93, 107}, ++{210, 89, 110}, ++{218, 84, 113}, ++{228, 79, 117}, ++{239, 73, 121}, ++{249, 68, 125}, ++{254, 66, 126}, ++{137, 57, 78}, ++{145, 58, 83}, ++{157, 58, 89}, ++{170, 57, 95}, ++{184, 55, 102}, ++{198, 52, 108}, ++{212, 48, 114}, ++{217, 47, 116}, ++{137, 57, 78}, ++{145, 58, 83}, ++{157, 58, 89}, ++{170, 57, 95}, ++{184, 55, 102}, ++{198, 52, 108}, ++{212, 48, 114}, ++{217, 47, 116}, ++{137, 58, 78}, ++{146, 59, 83}, ++{158, 58, 89}, ++{171, 57, 96}, ++{184, 55, 102}, ++{198, 52, 108}, ++{212, 48, 114}, ++{217, 47, 116}, ++{138, 58, 79}, ++{147, 59, 84}, ++{158, 59, 89}, ++{171, 58, 96}, ++{185, 55, 102}, ++{198, 52, 108}, ++{212, 48, 114}, ++{217, 47, 116}, ++{139, 59, 79}, ++{147, 60, 84}, ++{159, 60, 90}, ++{172, 58, 96}, ++{185, 56, 102}, ++{199, 52, 108}, ++{213, 49, 114}, ++{218, 47, 116}, ++{140, 61, 80}, ++{149, 61, 84}, ++{160, 60, 90}, ++{173, 59, 96}, ++{186, 56, 102}, ++{200, 53, 108}, ++{213, 49, 114}, ++{219, 48, 116}, ++{142, 62, 81}, ++{150, 62, 85}, ++{161, 61, 91}, ++{174, 59, 97}, ++{187, 57, 103}, ++{201, 53, 109}, ++{214, 50, 114}, ++{219, 48, 116}, ++{143, 63, 81}, ++{151, 63, 86}, ++{162, 62, 91}, ++{175, 60, 97}, ++{188, 57, 103}, ++{201, 54, 109}, ++{215, 50, 114}, ++{220, 49, 116}, ++{145, 65, 82}, ++{153, 65, 86}, ++{164, 63, 92}, ++{176, 61, 98}, ++{189, 58, 104}, ++{203, 55, 109}, ++{216, 51, 115}, ++{221, 49, 117}, ++{147, 67, 83}, ++{155, 66, 87}, ++{165, 64, 92}, ++{178, 62, 98}, ++{190, 59, 104}, ++{204, 55, 110}, ++{217, 51, 115}, ++{222, 50, 117}, ++{149, 68, 84}, ++{157, 67, 88}, ++{167, 66, 93}, ++{179, 63, 99}, ++{192, 60, 104}, ++{205, 56, 110}, ++{218, 52, 115}, ++{223, 50, 117}, ++{151, 70, 85}, ++{159, 69, 89}, ++{169, 67, 94}, ++{181, 64, 99}, ++{193, 61, 105}, ++{206, 57, 110}, ++{219, 53, 116}, ++{224, 51, 118}, ++{154, 72, 86}, ++{161, 70, 90}, ++{171, 68, 95}, ++{183, 65, 100}, ++{195, 62, 105}, ++{208, 58, 111}, ++{221, 53, 116}, ++{226, 52, 118}, ++{156, 73, 87}, ++{163, 72, 91}, ++{173, 69, 95}, ++{184, 66, 101}, ++{197, 62, 106}, ++{209, 58, 111}, ++{222, 54, 116}, ++{227, 52, 118}, ++{159, 75, 88}, ++{165, 73, 91}, ++{175, 71, 96}, ++{186, 67, 101}, ++{198, 63, 106}, ++{211, 59, 112}, ++{224, 55, 117}, ++{229, 53, 119}, ++{161, 77, 89}, ++{168, 75, 92}, ++{177, 72, 97}, ++{188, 69, 102}, ++{200, 65, 107}, ++{213, 60, 112}, ++{225, 56, 117}, ++{230, 54, 119}, ++{164, 78, 90}, ++{171, 76, 93}, ++{180, 73, 98}, ++{191, 70, 103}, ++{202, 66, 108}, ++{215, 61, 113}, ++{227, 56, 118}, ++{232, 55, 119}, ++{167, 80, 91}, ++{173, 78, 94}, ++{182, 75, 99}, ++{193, 71, 103}, ++{204, 67, 108}, ++{216, 62, 113}, ++{229, 57, 118}, ++{233, 56, 120}, ++{170, 82, 92}, ++{176, 79, 95}, ++{185, 76, 99}, ++{195, 72, 104}, ++{207, 68, 109}, ++{218, 63, 114}, ++{231, 58, 118}, ++{235, 56, 120}, ++{172, 83, 94}, ++{179, 81, 96}, ++{187, 77, 100}, ++{198, 73, 105}, ++{209, 69, 109}, ++{220, 64, 114}, ++{232, 59, 119}, ++{237, 57, 121}, ++{175, 84, 95}, ++{181, 82, 97}, ++{190, 78, 101}, ++{200, 74, 106}, ++{211, 70, 110}, ++{223, 65, 115}, ++{234, 60, 119}, ++{239, 58, 121}, ++{178, 86, 96}, ++{184, 83, 98}, ++{193, 80, 102}, ++{202, 75, 106}, ++{213, 71, 111}, ++{225, 66, 115}, ++{236, 61, 120}, ++{241, 59, 121}, ++{182, 87, 97}, ++{187, 85, 99}, ++{195, 81, 103}, ++{205, 77, 107}, ++{216, 72, 111}, ++{227, 67, 116}, ++{239, 62, 120}, ++{243, 60, 122}, ++{185, 89, 98}, ++{190, 86, 100}, ++{198, 82, 104}, ++{208, 78, 108}, ++{218, 73, 112}, ++{229, 68, 116}, ++{241, 63, 121}, ++{245, 61, 122}, ++{188, 90, 99}, ++{193, 87, 101}, ++{201, 83, 105}, ++{210, 79, 109}, ++{221, 74, 113}, ++{231, 69, 117}, ++{243, 64, 121}, ++{247, 62, 123}, ++{191, 91, 100}, ++{196, 88, 102}, ++{204, 84, 106}, ++{213, 80, 109}, ++{223, 75, 113}, ++{234, 70, 118}, ++{245, 65, 122}, ++{249, 63, 123}, ++{194, 92, 101}, ++{199, 89, 103}, ++{207, 86, 106}, ++{216, 81, 110}, ++{226, 76, 114}, ++{236, 71, 118}, ++{247, 66, 122}, ++{252, 64, 124}, ++{197, 93, 102}, ++{203, 91, 104}, ++{210, 87, 107}, ++{219, 82, 111}, ++{228, 77, 115}, ++{239, 72, 119}, ++{250, 66, 123}, ++{254, 64, 124}, ++{199, 94, 103}, ++{204, 91, 105}, ++{211, 87, 108}, ++{220, 83, 111}, ++{230, 77, 115}, ++{240, 72, 119}, ++{251, 67, 123}, ++{255, 65, 124}, ++{199, 94, 103}, ++{204, 91, 105}, ++{211, 87, 108}, ++{220, 83, 111}, ++{230, 77, 115}, ++{240, 72, 119}, ++{251, 67, 123}, ++{255, 65, 124}, ++{199, 94, 103}, ++{204, 91, 105}, ++{211, 87, 108}, ++{220, 83, 111}, ++{230, 77, 115}, ++{240, 72, 119}, ++{251, 67, 123}, ++{255, 65, 124}, ++{199, 94, 103}, ++{204, 91, 105}, ++{211, 87, 108}, ++{220, 83, 111}, ++{230, 77, 115}, ++{240, 72, 119}, ++{251, 67, 123}, ++{255, 65, 124}, ++{139, 55, 76}, ++{148, 56, 81}, ++{159, 56, 87}, ++{172, 55, 93}, ++{186, 53, 100}, ++{199, 50, 106}, ++{213, 47, 112}, ++{218, 45, 114}, ++{139, 55, 76}, ++{148, 56, 81}, ++{159, 56, 87}, ++{172, 55, 93}, ++{186, 53, 100}, ++{200, 50, 106}, ++{213, 47, 112}, ++{219, 45, 114}, ++{140, 55, 77}, ++{148, 56, 81}, ++{160, 56, 87}, ++{173, 55, 94}, ++{186, 53, 100}, ++{200, 50, 106}, ++{214, 47, 112}, ++{219, 46, 114}, ++{141, 56, 77}, ++{149, 57, 82}, ++{160, 57, 88}, ++{173, 56, 94}, ++{187, 54, 100}, ++{200, 51, 106}, ++{214, 47, 112}, ++{219, 46, 114}, ++{142, 57, 77}, ++{150, 58, 82}, ++{161, 58, 88}, ++{174, 56, 94}, ++{187, 54, 100}, ++{201, 51, 106}, ++{215, 48, 112}, ++{220, 46, 114}, ++{143, 58, 78}, ++{151, 59, 82}, ++{162, 58, 88}, ++{175, 57, 94}, ++{188, 54, 100}, ++{202, 51, 106}, ++{215, 48, 112}, ++{220, 46, 114}, ++{144, 60, 79}, ++{152, 60, 83}, ++{163, 59, 89}, ++{176, 58, 95}, ++{189, 55, 101}, ++{202, 52, 107}, ++{216, 48, 112}, ++{221, 47, 114}, ++{146, 61, 79}, ++{154, 61, 84}, ++{165, 60, 89}, ++{177, 58, 95}, ++{190, 56, 101}, ++{203, 53, 107}, ++{217, 49, 113}, ++{222, 47, 115}, ++{148, 63, 80}, ++{155, 62, 84}, ++{166, 61, 90}, ++{178, 59, 96}, ++{191, 56, 102}, ++{204, 53, 107}, ++{218, 49, 113}, ++{223, 48, 115}, ++{149, 64, 81}, ++{157, 64, 85}, ++{168, 62, 90}, ++{180, 60, 96}, ++{192, 57, 102}, ++{205, 54, 108}, ++{219, 50, 113}, ++{224, 48, 115}, ++{152, 66, 82}, ++{159, 65, 86}, ++{169, 64, 91}, ++{181, 61, 97}, ++{194, 58, 102}, ++{207, 55, 108}, ++{220, 51, 113}, ++{225, 49, 115}, ++{154, 68, 83}, ++{161, 67, 87}, ++{171, 65, 92}, ++{183, 62, 97}, ++{195, 59, 103}, ++{208, 55, 108}, ++{221, 51, 114}, ++{226, 50, 116}, ++{156, 69, 84}, ++{163, 68, 88}, ++{173, 66, 93}, ++{185, 63, 98}, ++{197, 60, 103}, ++{210, 56, 109}, ++{222, 52, 114}, ++{227, 50, 116}, ++{158, 71, 85}, ++{165, 70, 89}, ++{175, 67, 93}, ++{186, 65, 99}, ++{199, 61, 104}, ++{211, 57, 109}, ++{224, 53, 114}, ++{229, 51, 116}, ++{161, 73, 86}, ++{168, 71, 90}, ++{177, 69, 94}, ++{188, 66, 99}, ++{200, 62, 104}, ++{213, 58, 110}, ++{225, 54, 115}, ++{230, 52, 117}, ++{163, 74, 87}, ++{170, 73, 91}, ++{180, 70, 95}, ++{190, 67, 100}, ++{202, 63, 105}, ++{214, 59, 110}, ++{227, 54, 115}, ++{232, 53, 117}, ++{166, 76, 88}, ++{173, 74, 91}, ++{182, 71, 96}, ++{193, 68, 101}, ++{204, 64, 106}, ++{216, 60, 111}, ++{229, 55, 116}, ++{233, 54, 117}, ++{169, 78, 89}, ++{175, 76, 92}, ++{184, 73, 97}, ++{195, 69, 101}, ++{206, 65, 106}, ++{218, 61, 111}, ++{230, 56, 116}, ++{235, 54, 118}, ++{172, 79, 91}, ++{178, 77, 93}, ++{187, 74, 98}, ++{197, 70, 102}, ++{208, 66, 107}, ++{220, 62, 112}, ++{232, 57, 117}, ++{237, 55, 118}, ++{175, 81, 92}, ++{181, 79, 94}, ++{189, 75, 98}, ++{199, 72, 103}, ++{210, 67, 108}, ++{222, 63, 112}, ++{234, 58, 117}, ++{239, 56, 119}, ++{178, 82, 93}, ++{183, 80, 95}, ++{192, 77, 99}, ++{202, 73, 104}, ++{213, 68, 108}, ++{224, 64, 113}, ++{236, 59, 117}, ++{240, 57, 119}, ++{181, 84, 94}, ++{186, 81, 96}, ++{195, 78, 100}, ++{204, 74, 104}, ++{215, 69, 109}, ++{226, 65, 113}, ++{238, 60, 118}, ++{242, 58, 120}, ++{184, 85, 95}, ++{189, 83, 97}, ++{197, 79, 101}, ++{207, 75, 105}, ++{217, 70, 110}, ++{229, 66, 114}, ++{240, 61, 118}, ++{244, 59, 120}, ++{187, 87, 96}, ++{192, 84, 98}, ++{200, 80, 102}, ++{209, 76, 106}, ++{220, 72, 110}, ++{231, 67, 115}, ++{242, 62, 119}, ++{246, 60, 121}, ++{190, 88, 97}, ++{195, 85, 99}, ++{203, 82, 103}, ++{212, 77, 107}, ++{222, 73, 111}, ++{233, 68, 115}, ++{244, 63, 119}, ++{249, 61, 121}, ++{193, 89, 98}, ++{198, 86, 100}, ++{206, 83, 104}, ++{215, 78, 107}, ++{225, 74, 112}, ++{235, 69, 116}, ++{247, 64, 120}, ++{251, 62, 122}, ++{196, 90, 99}, ++{201, 88, 101}, ++{209, 84, 105}, ++{218, 79, 108}, ++{227, 75, 112}, ++{238, 70, 116}, ++{249, 64, 120}, ++{253, 62, 122}, ++{199, 91, 100}, ++{204, 89, 102}, ++{212, 85, 105}, ++{220, 81, 109}, ++{230, 76, 113}, ++{240, 71, 117}, ++{251, 65, 121}, ++{255, 63, 123}, ++{201, 92, 101}, ++{206, 89, 103}, ++{213, 86, 106}, ++{222, 81, 109}, ++{231, 76, 113}, ++{242, 71, 117}, ++{252, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{206, 89, 103}, ++{213, 86, 106}, ++{222, 81, 109}, ++{231, 76, 113}, ++{242, 71, 117}, ++{252, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{206, 89, 103}, ++{213, 86, 106}, ++{222, 81, 109}, ++{231, 76, 113}, ++{242, 71, 117}, ++{252, 66, 121}, ++{255, 64, 123}, ++{201, 92, 101}, ++{206, 89, 103}, ++{213, 86, 106}, ++{222, 81, 109}, ++{231, 76, 113}, ++{242, 71, 117}, ++{252, 66, 121}, ++{255, 64, 123}, ++{142, 52, 75}, ++{150, 54, 79}, ++{162, 54, 85}, ++{174, 53, 91}, ++{188, 51, 98}, ++{201, 49, 104}, ++{215, 46, 110}, ++{220, 44, 112}, ++{142, 52, 75}, ++{151, 54, 79}, ++{162, 54, 85}, ++{175, 53, 91}, ++{188, 51, 98}, ++{201, 49, 104}, ++{215, 46, 110}, ++{220, 44, 112}, ++{143, 53, 75}, ++{151, 54, 79}, ++{162, 54, 85}, ++{175, 54, 92}, ++{188, 52, 98}, ++{202, 49, 104}, ++{215, 46, 110}, ++{220, 44, 112}, ++{143, 54, 75}, ++{152, 55, 80}, ++{163, 55, 86}, ++{175, 54, 92}, ++{189, 52, 98}, ++{202, 49, 104}, ++{216, 46, 110}, ++{221, 45, 112}, ++{144, 55, 76}, ++{153, 56, 80}, ++{164, 56, 86}, ++{176, 54, 92}, ++{189, 52, 98}, ++{203, 50, 104}, ++{216, 46, 110}, ++{221, 45, 112}, ++{146, 56, 76}, ++{154, 56, 81}, ++{165, 56, 86}, ++{177, 55, 92}, ++{190, 53, 99}, ++{203, 50, 104}, ++{217, 47, 110}, ++{222, 45, 112}, ++{147, 57, 77}, ++{155, 58, 81}, ++{166, 57, 87}, ++{178, 56, 93}, ++{191, 53, 99}, ++{204, 51, 105}, ++{218, 47, 110}, ++{223, 46, 112}, ++{148, 59, 78}, ++{156, 59, 82}, ++{167, 58, 87}, ++{179, 57, 93}, ++{192, 54, 99}, ++{205, 51, 105}, ++{218, 48, 111}, ++{223, 46, 113}, ++{150, 60, 78}, ++{158, 60, 83}, ++{168, 59, 88}, ++{180, 57, 94}, ++{193, 55, 100}, ++{206, 52, 105}, ++{219, 48, 111}, ++{224, 47, 113}, ++{152, 62, 79}, ++{160, 62, 83}, ++{170, 60, 88}, ++{182, 58, 94}, ++{194, 56, 100}, ++{207, 52, 106}, ++{220, 49, 111}, ++{225, 47, 113}, ++{154, 64, 80}, ++{161, 63, 84}, ++{172, 62, 89}, ++{183, 59, 95}, ++{196, 57, 100}, ++{209, 53, 106}, ++{222, 49, 111}, ++{227, 48, 113}, ++{156, 65, 81}, ++{163, 64, 85}, ++{173, 63, 90}, ++{185, 61, 95}, ++{197, 57, 101}, ++{210, 54, 106}, ++{223, 50, 112}, ++{228, 49, 114}, ++{158, 67, 82}, ++{165, 66, 86}, ++{175, 64, 91}, ++{187, 62, 96}, ++{199, 58, 101}, ++{211, 55, 107}, ++{224, 51, 112}, ++{229, 49, 114}, ++{161, 69, 83}, ++{168, 68, 87}, ++{177, 66, 91}, ++{188, 63, 97}, ++{200, 59, 102}, ++{213, 56, 107}, ++{226, 52, 113}, ++{230, 50, 114}, ++{163, 70, 84}, ++{170, 69, 88}, ++{179, 67, 92}, ++{190, 64, 97}, ++{202, 60, 103}, ++{214, 57, 108}, ++{227, 52, 113}, ++{232, 51, 115}, ++{166, 72, 85}, ++{172, 71, 89}, ++{182, 68, 93}, ++{192, 65, 98}, ++{204, 61, 103}, ++{216, 57, 108}, ++{229, 53, 113}, ++{233, 52, 115}, ++{168, 74, 86}, ++{175, 72, 90}, ++{184, 70, 94}, ++{194, 66, 99}, ++{206, 63, 104}, ++{218, 58, 109}, ++{230, 54, 114}, ++{235, 52, 116}, ++{171, 76, 88}, ++{177, 74, 91}, ++{186, 71, 95}, ++{197, 68, 99}, ++{208, 64, 104}, ++{220, 59, 109}, ++{232, 55, 114}, ++{237, 53, 116}, ++{174, 77, 89}, ++{180, 75, 92}, ++{189, 72, 96}, ++{199, 69, 100}, ++{210, 65, 105}, ++{222, 60, 110}, ++{234, 56, 115}, ++{238, 54, 116}, ++{177, 79, 90}, ++{183, 77, 93}, ++{191, 74, 96}, ++{201, 70, 101}, ++{212, 66, 106}, ++{224, 61, 110}, ++{236, 57, 115}, ++{240, 55, 117}, ++{180, 80, 91}, ++{186, 78, 94}, ++{194, 75, 97}, ++{204, 71, 102}, ++{214, 67, 106}, ++{226, 62, 111}, ++{238, 58, 116}, ++{242, 56, 117}, ++{183, 82, 92}, ++{188, 79, 95}, ++{196, 76, 98}, ++{206, 72, 103}, ++{217, 68, 107}, ++{228, 63, 112}, ++{240, 59, 116}, ++{244, 57, 118}, ++{186, 83, 93}, ++{191, 81, 96}, ++{199, 77, 99}, ++{209, 73, 103}, ++{219, 69, 108}, ++{230, 64, 112}, ++{242, 60, 117}, ++{246, 58, 118}, ++{189, 85, 94}, ++{194, 82, 97}, ++{202, 79, 100}, ++{211, 75, 104}, ++{221, 70, 108}, ++{232, 65, 113}, ++{244, 60, 117}, ++{248, 59, 119}, ++{192, 86, 95}, ++{197, 83, 98}, ++{205, 80, 101}, ++{214, 76, 105}, ++{224, 71, 109}, ++{235, 66, 113}, ++{246, 61, 118}, ++{250, 60, 119}, ++{195, 87, 96}, ++{200, 85, 99}, ++{208, 81, 102}, ++{216, 77, 106}, ++{226, 72, 110}, ++{237, 67, 114}, ++{248, 62, 118}, ++{252, 60, 120}, ++{198, 88, 97}, ++{203, 86, 100}, ++{210, 82, 103}, ++{219, 78, 106}, ++{229, 73, 110}, ++{239, 68, 115}, ++{250, 63, 119}, ++{254, 61, 120}, ++{201, 90, 98}, ++{206, 87, 101}, ++{213, 83, 104}, ++{222, 79, 107}, ++{232, 74, 111}, ++{242, 69, 115}, ++{253, 64, 119}, ++{255, 62, 121}, ++{203, 90, 99}, ++{208, 88, 101}, ++{215, 84, 104}, ++{223, 80, 108}, ++{233, 75, 111}, ++{243, 70, 115}, ++{254, 65, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{208, 88, 101}, ++{215, 84, 104}, ++{223, 80, 108}, ++{233, 75, 111}, ++{243, 70, 115}, ++{254, 65, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{208, 88, 101}, ++{215, 84, 104}, ++{223, 80, 108}, ++{233, 75, 111}, ++{243, 70, 115}, ++{254, 65, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{208, 88, 101}, ++{215, 84, 104}, ++{223, 80, 108}, ++{233, 75, 111}, ++{243, 70, 115}, ++{254, 65, 120}, ++{255, 63, 121}, ++{145, 50, 73}, ++{153, 51, 77}, ++{164, 52, 83}, ++{177, 51, 89}, ++{190, 50, 96}, ++{203, 47, 102}, ++{217, 44, 108}, ++{222, 43, 110}, ++{145, 50, 73}, ++{153, 51, 77}, ++{164, 52, 83}, ++{177, 51, 90}, ++{190, 50, 96}, ++{203, 47, 102}, ++{217, 44, 108}, ++{222, 43, 110}, ++{145, 51, 73}, ++{154, 52, 78}, ++{165, 52, 83}, ++{177, 52, 90}, ++{190, 50, 96}, ++{204, 48, 102}, ++{217, 44, 108}, ++{222, 43, 110}, ++{146, 51, 73}, ++{154, 53, 78}, ++{165, 53, 84}, ++{178, 52, 90}, ++{191, 50, 96}, ++{204, 48, 102}, ++{218, 45, 108}, ++{223, 43, 110}, ++{147, 52, 74}, ++{155, 53, 78}, ++{166, 54, 84}, ++{178, 53, 90}, ++{191, 51, 96}, ++{205, 48, 102}, ++{218, 45, 108}, ++{223, 44, 110}, ++{148, 54, 74}, ++{156, 54, 79}, ++{167, 54, 84}, ++{179, 53, 90}, ++{192, 51, 97}, ++{205, 49, 103}, ++{219, 45, 108}, ++{224, 44, 110}, ++{150, 55, 75}, ++{157, 55, 79}, ++{168, 55, 85}, ++{180, 54, 91}, ++{193, 52, 97}, ++{206, 49, 103}, ++{219, 46, 108}, ++{224, 44, 111}, ++{151, 56, 76}, ++{159, 57, 80}, ++{169, 56, 85}, ++{181, 55, 91}, ++{194, 53, 97}, ++{207, 50, 103}, ++{220, 46, 109}, ++{225, 45, 111}, ++{153, 58, 77}, ++{160, 58, 81}, ++{171, 57, 86}, ++{182, 56, 92}, ++{195, 53, 98}, ++{208, 50, 103}, ++{221, 47, 109}, ++{226, 45, 111}, ++{155, 60, 78}, ++{162, 59, 81}, ++{172, 58, 87}, ++{184, 57, 92}, ++{196, 54, 98}, ++{209, 51, 104}, ++{222, 47, 109}, ++{227, 46, 111}, ++{157, 61, 78}, ++{164, 61, 82}, ++{174, 60, 87}, ++{185, 58, 93}, ++{198, 55, 99}, ++{210, 52, 104}, ++{223, 48, 110}, ++{228, 47, 112}, ++{159, 63, 79}, ++{166, 62, 83}, ++{176, 61, 88}, ++{187, 59, 93}, ++{199, 56, 99}, ++{212, 53, 105}, ++{225, 49, 110}, ++{229, 47, 112}, ++{161, 65, 80}, ++{168, 64, 84}, ++{177, 62, 89}, ++{189, 60, 94}, ++{201, 57, 100}, ++{213, 53, 105}, ++{226, 50, 110}, ++{231, 48, 112}, ++{163, 66, 81}, ++{170, 65, 85}, ++{179, 64, 90}, ++{190, 61, 95}, ++{202, 58, 100}, ++{215, 54, 105}, ++{227, 50, 111}, ++{232, 49, 113}, ++{166, 68, 82}, ++{172, 67, 86}, ++{182, 65, 90}, ++{192, 62, 95}, ++{204, 59, 101}, ++{216, 55, 106}, ++{229, 51, 111}, ++{233, 50, 113}, ++{168, 70, 84}, ++{175, 69, 87}, ++{184, 66, 91}, ++{194, 63, 96}, ++{206, 60, 101}, ++{218, 56, 106}, ++{230, 52, 112}, ++{235, 50, 113}, ++{171, 72, 85}, ++{177, 70, 88}, ++{186, 68, 92}, ++{196, 65, 97}, ++{208, 61, 102}, ++{220, 57, 107}, ++{232, 53, 112}, ++{237, 51, 114}, ++{173, 73, 86}, ++{180, 72, 89}, ++{188, 69, 93}, ++{199, 66, 98}, ++{210, 62, 103}, ++{222, 58, 107}, ++{234, 54, 112}, ++{238, 52, 114}, ++{176, 75, 87}, ++{182, 73, 90}, ++{191, 70, 94}, ++{201, 67, 98}, ++{212, 63, 103}, ++{223, 59, 108}, ++{235, 55, 113}, ++{240, 53, 115}, ++{179, 77, 88}, ++{185, 75, 91}, ++{193, 72, 95}, ++{203, 68, 99}, ++{214, 64, 104}, ++{225, 60, 109}, ++{237, 56, 113}, ++{242, 54, 115}, ++{182, 78, 89}, ++{188, 76, 92}, ++{196, 73, 96}, ++{206, 69, 100}, ++{216, 65, 104}, ++{227, 61, 109}, ++{239, 56, 114}, ++{244, 55, 116}, ++{185, 80, 90}, ++{190, 78, 93}, ++{198, 74, 96}, ++{208, 71, 101}, ++{218, 66, 105}, ++{230, 62, 110}, ++{241, 57, 114}, ++{245, 56, 116}, ++{188, 81, 91}, ++{193, 79, 94}, ++{201, 76, 97}, ++{210, 72, 101}, ++{221, 68, 106}, ++{232, 63, 110}, ++{243, 58, 115}, ++{247, 57, 117}, ++{191, 83, 92}, ++{196, 80, 95}, ++{204, 77, 98}, ++{213, 73, 102}, ++{223, 69, 107}, ++{234, 64, 111}, ++{245, 59, 115}, ++{249, 57, 117}, ++{194, 84, 93}, ++{199, 82, 96}, ++{207, 78, 99}, ++{216, 74, 103}, ++{226, 70, 107}, ++{236, 65, 112}, ++{247, 60, 116}, ++{252, 58, 118}, ++{197, 85, 94}, ++{202, 83, 97}, ++{209, 79, 100}, ++{218, 75, 104}, ++{228, 71, 108}, ++{239, 66, 112}, ++{250, 61, 116}, ++{254, 59, 118}, ++{200, 87, 96}, ++{205, 84, 98}, ++{212, 81, 101}, ++{221, 76, 105}, ++{231, 72, 109}, ++{241, 67, 113}, ++{252, 62, 117}, ++{255, 60, 119}, ++{203, 88, 97}, ++{208, 85, 99}, ++{215, 82, 102}, ++{224, 78, 105}, ++{233, 73, 109}, ++{243, 68, 113}, ++{254, 63, 118}, ++{255, 61, 119}, ++{205, 88, 97}, ++{210, 86, 99}, ++{217, 82, 102}, ++{225, 78, 106}, ++{234, 73, 110}, ++{245, 69, 114}, ++{255, 64, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 86, 99}, ++{217, 82, 102}, ++{225, 78, 106}, ++{234, 73, 110}, ++{245, 69, 114}, ++{255, 64, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 86, 99}, ++{217, 82, 102}, ++{225, 78, 106}, ++{234, 73, 110}, ++{245, 69, 114}, ++{255, 64, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 86, 99}, ++{217, 82, 102}, ++{225, 78, 106}, ++{234, 73, 110}, ++{245, 69, 114}, ++{255, 64, 118}, ++{255, 62, 119}, ++{147, 48, 71}, ++{156, 49, 76}, ++{166, 50, 81}, ++{179, 50, 88}, ++{192, 48, 94}, ++{205, 46, 100}, ++{219, 43, 106}, ++{224, 42, 108}, ++{148, 48, 71}, ++{156, 49, 76}, ++{167, 50, 81}, ++{179, 50, 88}, ++{192, 48, 94}, ++{205, 46, 100}, ++{219, 43, 106}, ++{224, 42, 108}, ++{148, 48, 71}, ++{156, 50, 76}, ++{167, 50, 82}, ++{179, 50, 88}, ++{192, 48, 94}, ++{205, 46, 100}, ++{219, 43, 106}, ++{224, 42, 108}, ++{149, 49, 72}, ++{157, 50, 76}, ++{167, 51, 82}, ++{180, 50, 88}, ++{193, 49, 94}, ++{206, 46, 100}, ++{219, 43, 106}, ++{224, 42, 108}, ++{150, 50, 72}, ++{158, 51, 76}, ++{168, 51, 82}, ++{180, 51, 88}, ++{193, 49, 94}, ++{206, 47, 100}, ++{220, 44, 106}, ++{225, 42, 108}, ++{151, 51, 73}, ++{159, 52, 77}, ++{169, 52, 83}, ++{181, 51, 89}, ++{194, 50, 95}, ++{207, 47, 101}, ++{220, 44, 106}, ++{225, 43, 108}, ++{152, 53, 73}, ++{160, 53, 78}, ++{170, 53, 83}, ++{182, 52, 89}, ++{195, 50, 95}, ++{208, 48, 101}, ++{221, 44, 107}, ++{226, 43, 109}, ++{154, 54, 74}, ++{161, 54, 78}, ++{171, 54, 84}, ++{183, 53, 89}, ++{196, 51, 95}, ++{209, 48, 101}, ++{222, 45, 107}, ++{227, 44, 109}, ++{155, 56, 75}, ++{163, 56, 79}, ++{173, 55, 84}, ++{185, 54, 90}, ++{197, 52, 96}, ++{210, 49, 101}, ++{223, 46, 107}, ++{228, 44, 109}, ++{157, 57, 76}, ++{164, 57, 80}, ++{174, 56, 85}, ++{186, 55, 90}, ++{198, 53, 96}, ++{211, 50, 102}, ++{224, 46, 107}, ++{229, 45, 109}, ++{159, 59, 77}, ++{166, 59, 80}, ++{176, 58, 85}, ++{187, 56, 91}, ++{200, 53, 97}, ++{212, 50, 102}, ++{225, 47, 108}, ++{230, 45, 110}, ++{161, 61, 78}, ++{168, 60, 81}, ++{178, 59, 86}, ++{189, 57, 92}, ++{201, 54, 97}, ++{213, 51, 103}, ++{226, 48, 108}, ++{231, 46, 110}, ++{163, 62, 79}, ++{170, 62, 82}, ++{180, 60, 87}, ++{191, 58, 92}, ++{203, 55, 98}, ++{215, 52, 103}, ++{228, 48, 108}, ++{232, 47, 110}, ++{166, 64, 80}, ++{172, 63, 83}, ++{182, 62, 88}, ++{192, 59, 93}, ++{204, 56, 98}, ++{216, 53, 104}, ++{229, 49, 109}, ++{234, 48, 111}, ++{168, 66, 81}, ++{174, 65, 84}, ++{184, 63, 88}, ++{194, 60, 94}, ++{206, 57, 99}, ++{218, 54, 104}, ++{230, 50, 109}, ++{235, 48, 111}, ++{170, 68, 82}, ++{177, 66, 85}, ++{186, 64, 89}, ++{196, 62, 94}, ++{208, 58, 99}, ++{220, 55, 105}, ++{232, 51, 110}, ++{237, 49, 112}, ++{173, 69, 83}, ++{179, 68, 86}, ++{188, 66, 90}, ++{198, 63, 95}, ++{210, 59, 100}, ++{221, 56, 105}, ++{234, 52, 110}, ++{238, 50, 112}, ++{176, 71, 84}, ++{182, 70, 87}, ++{190, 67, 91}, ++{201, 64, 96}, ++{212, 61, 101}, ++{223, 57, 106}, ++{235, 52, 111}, ++{240, 51, 112}, ++{178, 73, 85}, ++{184, 71, 88}, ++{193, 69, 92}, ++{203, 65, 96}, ++{214, 62, 101}, ++{225, 58, 106}, ++{237, 53, 111}, ++{241, 52, 113}, ++{181, 74, 86}, ++{187, 73, 89}, ++{195, 70, 93}, ++{205, 67, 97}, ++{216, 63, 102}, ++{227, 59, 107}, ++{239, 54, 112}, ++{243, 53, 113}, ++{184, 76, 87}, ++{190, 74, 90}, ++{198, 71, 94}, ++{207, 68, 98}, ++{218, 64, 103}, ++{229, 60, 107}, ++{241, 55, 112}, ++{245, 54, 114}, ++{187, 78, 88}, ++{192, 76, 91}, ++{200, 73, 95}, ++{210, 69, 99}, ++{220, 65, 103}, ++{231, 61, 108}, ++{243, 56, 113}, ++{247, 54, 114}, ++{190, 79, 89}, ++{195, 77, 92}, ++{203, 74, 95}, ++{212, 70, 100}, ++{222, 66, 104}, ++{233, 62, 109}, ++{245, 57, 113}, ++{249, 55, 115}, ++{193, 81, 90}, ++{198, 78, 93}, ++{206, 75, 96}, ++{215, 71, 100}, ++{225, 67, 105}, ++{236, 63, 109}, ++{247, 58, 114}, ++{251, 56, 115}, ++{196, 82, 92}, ++{201, 80, 94}, ++{208, 76, 97}, ++{217, 73, 101}, ++{227, 68, 105}, ++{238, 64, 110}, ++{249, 59, 114}, ++{253, 57, 116}, ++{199, 83, 93}, ++{204, 81, 95}, ++{211, 78, 98}, ++{220, 74, 102}, ++{230, 69, 106}, ++{240, 65, 110}, ++{251, 60, 115}, ++{255, 58, 116}, ++{202, 85, 94}, ++{207, 82, 96}, ++{214, 79, 99}, ++{223, 75, 103}, ++{232, 70, 107}, ++{243, 66, 111}, ++{253, 61, 115}, ++{255, 59, 117}, ++{205, 86, 95}, ++{210, 84, 97}, ++{217, 80, 100}, ++{225, 76, 104}, ++{235, 72, 108}, ++{245, 67, 112}, ++{255, 62, 116}, ++{255, 60, 117}, ++{207, 87, 95}, ++{211, 84, 97}, ++{218, 81, 101}, ++{227, 77, 104}, ++{236, 72, 108}, ++{246, 67, 112}, ++{255, 62, 116}, ++{255, 61, 118}, ++{207, 87, 95}, ++{211, 84, 97}, ++{218, 81, 101}, ++{227, 77, 104}, ++{236, 72, 108}, ++{246, 67, 112}, ++{255, 62, 116}, ++{255, 61, 118}, ++{207, 87, 95}, ++{211, 84, 97}, ++{218, 81, 101}, ++{227, 77, 104}, ++{236, 72, 108}, ++{246, 67, 112}, ++{255, 62, 116}, ++{255, 61, 118}, ++{207, 87, 95}, ++{211, 84, 97}, ++{218, 81, 101}, ++{227, 77, 104}, ++{236, 72, 108}, ++{246, 67, 112}, ++{255, 62, 116}, ++{255, 61, 118}, ++{150, 45, 69}, ++{158, 47, 74}, ++{169, 48, 80}, ++{181, 48, 86}, ++{194, 46, 92}, ++{207, 44, 98}, ++{220, 42, 104}, ++{225, 40, 106}, ++{150, 46, 69}, ++{158, 47, 74}, ++{169, 48, 80}, ++{181, 48, 86}, ++{194, 47, 92}, ++{207, 44, 98}, ++{220, 42, 104}, ++{225, 40, 106}, ++{151, 46, 70}, ++{159, 48, 74}, ++{169, 48, 80}, ++{181, 48, 86}, ++{194, 47, 92}, ++{207, 45, 98}, ++{221, 42, 104}, ++{226, 41, 106}, ++{151, 47, 70}, ++{159, 48, 74}, ++{170, 49, 80}, ++{182, 48, 86}, ++{195, 47, 92}, ++{208, 45, 98}, ++{221, 42, 104}, ++{226, 41, 106}, ++{152, 48, 70}, ++{160, 49, 75}, ++{171, 49, 80}, ++{183, 49, 86}, ++{195, 47, 92}, ++{208, 45, 98}, ++{222, 42, 104}, ++{226, 41, 106}, ++{153, 49, 71}, ++{161, 50, 75}, ++{171, 50, 81}, ++{183, 50, 87}, ++{196, 48, 93}, ++{209, 46, 99}, ++{222, 43, 104}, ++{227, 42, 107}, ++{155, 50, 72}, ++{162, 51, 76}, ++{173, 51, 81}, ++{184, 50, 87}, ++{197, 49, 93}, ++{210, 46, 99}, ++{223, 43, 105}, ++{228, 42, 107}, ++{156, 52, 72}, ++{164, 52, 76}, ++{174, 52, 82}, ++{185, 51, 87}, ++{198, 49, 93}, ++{211, 47, 99}, ++{224, 44, 105}, ++{229, 42, 107}, ++{158, 53, 73}, ++{165, 54, 77}, ++{175, 53, 82}, ++{187, 52, 88}, ++{199, 50, 94}, ++{212, 47, 100}, ++{225, 44, 105}, ++{229, 43, 107}, ++{160, 55, 74}, ++{167, 55, 78}, ++{177, 54, 83}, ++{188, 53, 89}, ++{200, 51, 94}, ++{213, 48, 100}, ++{226, 45, 106}, ++{230, 44, 108}, ++{161, 57, 75}, ++{168, 56, 79}, ++{178, 56, 84}, ++{189, 54, 89}, ++{201, 52, 95}, ++{214, 49, 100}, ++{227, 46, 106}, ++{232, 44, 108}, ++{163, 58, 76}, ++{170, 58, 79}, ++{180, 57, 84}, ++{191, 55, 90}, ++{203, 53, 95}, ++{215, 50, 101}, ++{228, 46, 106}, ++{233, 45, 108}, ++{166, 60, 77}, ++{172, 60, 80}, ++{182, 58, 85}, ++{193, 56, 90}, ++{204, 54, 96}, ++{217, 51, 101}, ++{229, 47, 107}, ++{234, 46, 109}, ++{168, 62, 78}, ++{174, 61, 81}, ++{184, 60, 86}, ++{194, 57, 91}, ++{206, 55, 96}, ++{218, 51, 102}, ++{231, 48, 107}, ++{235, 46, 109}, ++{170, 64, 79}, ++{177, 63, 82}, ++{186, 61, 87}, ++{196, 59, 92}, ++{208, 56, 97}, ++{220, 52, 102}, ++{232, 49, 107}, ++{237, 47, 109}, ++{173, 66, 80}, ++{179, 64, 83}, ++{188, 62, 87}, ++{198, 60, 92}, ++{210, 57, 98}, ++{221, 53, 103}, ++{234, 49, 108}, ++{238, 48, 110}, ++{175, 67, 81}, ++{181, 66, 84}, ++{190, 64, 88}, ++{200, 61, 93}, ++{211, 58, 98}, ++{223, 54, 103}, ++{235, 50, 108}, ++{240, 49, 110}, ++{178, 69, 82}, ++{184, 68, 85}, ++{192, 65, 89}, ++{202, 62, 94}, ++{213, 59, 99}, ++{225, 55, 104}, ++{237, 51, 109}, ++{241, 50, 111}, ++{180, 71, 83}, ++{186, 69, 86}, ++{195, 67, 90}, ++{205, 64, 95}, ++{215, 60, 99}, ++{227, 56, 104}, ++{239, 52, 109}, ++{243, 51, 111}, ++{183, 72, 84}, ++{189, 71, 87}, ++{197, 68, 91}, ++{207, 65, 95}, ++{218, 61, 100}, ++{229, 57, 105}, ++{240, 53, 110}, ++{245, 51, 112}, ++{186, 74, 85}, ++{192, 72, 88}, ++{200, 69, 92}, ++{209, 66, 96}, ++{220, 62, 101}, ++{231, 58, 106}, ++{242, 54, 110}, ++{247, 52, 112}, ++{189, 76, 86}, ++{194, 74, 89}, ++{202, 71, 93}, ++{212, 67, 97}, ++{222, 64, 102}, ++{233, 59, 106}, ++{244, 55, 111}, ++{249, 53, 113}, ++{192, 77, 88}, ++{197, 75, 90}, ++{205, 72, 94}, ++{214, 69, 98}, ++{224, 65, 102}, ++{235, 60, 107}, ++{246, 56, 111}, ++{251, 54, 113}, ++{195, 79, 89}, ++{200, 76, 91}, ++{208, 73, 95}, ++{217, 70, 99}, ++{227, 66, 103}, ++{237, 61, 107}, ++{248, 57, 112}, ++{253, 55, 114}, ++{198, 80, 90}, ++{203, 78, 92}, ++{210, 75, 96}, ++{219, 71, 99}, ++{229, 67, 104}, ++{239, 62, 108}, ++{250, 58, 112}, ++{255, 56, 114}, ++{201, 81, 91}, ++{206, 79, 93}, ++{213, 76, 96}, ++{222, 72, 100}, ++{231, 68, 104}, ++{242, 64, 109}, ++{253, 59, 113}, ++{255, 57, 115}, ++{204, 83, 92}, ++{209, 80, 94}, ++{216, 77, 97}, ++{224, 73, 101}, ++{234, 69, 105}, ++{244, 65, 109}, ++{255, 60, 114}, ++{255, 58, 115}, ++{207, 84, 93}, ++{212, 82, 95}, ++{219, 78, 98}, ++{227, 74, 102}, ++{236, 70, 106}, ++{246, 66, 110}, ++{255, 61, 114}, ++{255, 59, 116}, ++{208, 85, 94}, ++{213, 82, 96}, ++{220, 79, 99}, ++{228, 75, 102}, ++{238, 71, 106}, ++{248, 66, 110}, ++{255, 61, 114}, ++{255, 59, 116}, ++{208, 85, 94}, ++{213, 82, 96}, ++{220, 79, 99}, ++{228, 75, 102}, ++{238, 71, 106}, ++{248, 66, 110}, ++{255, 61, 114}, ++{255, 59, 116}, ++{208, 85, 94}, ++{213, 82, 96}, ++{220, 79, 99}, ++{228, 75, 102}, ++{238, 71, 106}, ++{248, 66, 110}, ++{255, 61, 114}, ++{255, 59, 116}, ++{208, 85, 94}, ++{213, 82, 96}, ++{220, 79, 99}, ++{228, 75, 102}, ++{238, 71, 106}, ++{248, 66, 110}, ++{255, 61, 114}, ++{255, 59, 116}, ++{153, 43, 68}, ++{161, 45, 72}, ++{171, 46, 78}, ++{183, 46, 84}, ++{196, 45, 90}, ++{209, 43, 96}, ++{222, 40, 102}, ++{227, 39, 104}, ++{153, 43, 68}, ++{161, 45, 72}, ++{171, 46, 78}, ++{183, 46, 84}, ++{196, 45, 90}, ++{209, 43, 96}, ++{222, 40, 102}, ++{227, 39, 104}, ++{153, 44, 68}, ++{161, 45, 72}, ++{172, 46, 78}, ++{184, 46, 84}, ++{196, 45, 90}, ++{209, 43, 96}, ++{222, 40, 102}, ++{227, 39, 104}, ++{154, 45, 68}, ++{162, 46, 73}, ++{172, 47, 78}, ++{184, 47, 84}, ++{197, 45, 90}, ++{210, 43, 96}, ++{223, 41, 102}, ++{228, 40, 104}, ++{155, 46, 69}, ++{163, 47, 73}, ++{173, 47, 78}, ++{185, 47, 85}, ++{197, 46, 91}, ++{210, 44, 97}, ++{223, 41, 102}, ++{228, 40, 105}, ++{156, 47, 69}, ++{164, 48, 73}, ++{174, 48, 79}, ++{185, 48, 85}, ++{198, 46, 91}, ++{211, 44, 97}, ++{224, 41, 103}, ++{229, 40, 105}, ++{157, 48, 70}, ++{165, 49, 74}, ++{175, 49, 79}, ++{186, 49, 85}, ++{199, 47, 91}, ++{212, 45, 97}, ++{225, 42, 103}, ++{229, 41, 105}, ++{159, 49, 71}, ++{166, 50, 75}, ++{176, 50, 80}, ++{188, 49, 86}, ++{200, 48, 92}, ++{213, 45, 97}, ++{225, 42, 103}, ++{230, 41, 105}, ++{160, 51, 71}, ++{167, 51, 75}, ++{177, 51, 80}, ++{189, 50, 86}, ++{201, 48, 92}, ++{213, 46, 98}, ++{226, 43, 103}, ++{231, 42, 105}, ++{162, 53, 72}, ++{169, 53, 76}, ++{179, 52, 81}, ++{190, 51, 87}, ++{202, 49, 92}, ++{215, 47, 98}, ++{227, 44, 104}, ++{232, 42, 106}, ++{164, 54, 73}, ++{171, 54, 77}, ++{180, 54, 82}, ++{191, 52, 87}, ++{203, 50, 93}, ++{216, 47, 99}, ++{228, 44, 104}, ++{233, 43, 106}, ++{166, 56, 74}, ++{173, 56, 78}, ++{182, 55, 82}, ++{193, 53, 88}, ++{205, 51, 93}, ++{217, 48, 99}, ++{230, 45, 104}, ++{234, 44, 106}, ++{168, 58, 75}, ++{175, 57, 78}, ++{184, 56, 83}, ++{195, 55, 88}, ++{206, 52, 94}, ++{218, 49, 99}, ++{231, 46, 105}, ++{236, 44, 107}, ++{170, 60, 76}, ++{177, 59, 79}, ++{186, 58, 84}, ++{196, 56, 89}, ++{208, 53, 94}, ++{220, 50, 100}, ++{232, 46, 105}, ++{237, 45, 107}, ++{173, 61, 77}, ++{179, 61, 80}, ++{188, 59, 85}, ++{198, 57, 90}, ++{210, 54, 95}, ++{222, 51, 100}, ++{234, 47, 106}, ++{238, 46, 107}, ++{175, 63, 78}, ++{181, 62, 81}, ++{190, 61, 86}, ++{200, 58, 91}, ++{211, 55, 96}, ++{223, 52, 101}, ++{235, 48, 106}, ++{240, 47, 108}, ++{177, 65, 79}, ++{184, 64, 82}, ++{192, 62, 86}, ++{202, 59, 91}, ++{213, 56, 96}, ++{225, 53, 101}, ++{237, 49, 106}, ++{241, 48, 108}, ++{180, 67, 80}, ++{186, 65, 83}, ++{194, 63, 87}, ++{204, 61, 92}, ++{215, 57, 97}, ++{227, 54, 102}, ++{239, 50, 107}, ++{243, 48, 109}, ++{183, 69, 81}, ++{188, 67, 84}, ++{197, 65, 88}, ++{207, 62, 93}, ++{217, 59, 98}, ++{229, 55, 103}, ++{240, 51, 107}, ++{245, 49, 109}, ++{185, 70, 82}, ++{191, 69, 85}, ++{199, 66, 89}, ++{209, 63, 94}, ++{219, 60, 98}, ++{230, 56, 103}, ++{242, 52, 108}, ++{246, 50, 110}, ++{188, 72, 84}, ++{194, 70, 86}, ++{202, 68, 90}, ++{211, 64, 94}, ++{221, 61, 99}, ++{232, 57, 104}, ++{244, 53, 108}, ++{248, 51, 110}, ++{191, 73, 85}, ++{196, 72, 87}, ++{204, 69, 91}, ++{213, 66, 95}, ++{224, 62, 100}, ++{235, 58, 104}, ++{246, 54, 109}, ++{250, 52, 111}, ++{194, 75, 86}, ++{199, 73, 88}, ++{207, 70, 92}, ++{216, 67, 96}, ++{226, 63, 100}, ++{237, 59, 105}, ++{248, 55, 110}, ++{252, 53, 111}, ++{197, 77, 87}, ++{202, 75, 89}, ++{209, 72, 93}, ++{218, 68, 97}, ++{228, 64, 101}, ++{239, 60, 106}, ++{250, 56, 110}, ++{254, 54, 112}, ++{200, 78, 88}, ++{205, 76, 90}, ++{212, 73, 94}, ++{221, 69, 98}, ++{231, 65, 102}, ++{241, 61, 106}, ++{252, 57, 111}, ++{255, 55, 112}, ++{203, 79, 89}, ++{208, 77, 91}, ++{215, 74, 95}, ++{223, 71, 98}, ++{233, 67, 103}, ++{243, 62, 107}, ++{254, 58, 111}, ++{255, 56, 113}, ++{206, 81, 90}, ++{211, 79, 92}, ++{218, 76, 96}, ++{226, 72, 99}, ++{236, 68, 103}, ++{246, 63, 108}, ++{255, 59, 112}, ++{255, 57, 113}, ++{209, 82, 91}, ++{213, 80, 93}, ++{220, 77, 97}, ++{229, 73, 100}, ++{238, 69, 104}, ++{248, 64, 108}, ++{255, 60, 112}, ++{255, 58, 114}, ++{210, 83, 92}, ++{215, 81, 94}, ++{222, 77, 97}, ++{230, 74, 101}, ++{239, 69, 104}, ++{249, 65, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{210, 83, 92}, ++{215, 81, 94}, ++{222, 77, 97}, ++{230, 74, 101}, ++{239, 69, 104}, ++{249, 65, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{210, 83, 92}, ++{215, 81, 94}, ++{222, 77, 97}, ++{230, 74, 101}, ++{239, 69, 104}, ++{249, 65, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{210, 83, 92}, ++{215, 81, 94}, ++{222, 77, 97}, ++{230, 74, 101}, ++{239, 69, 104}, ++{249, 65, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{155, 41, 66}, ++{163, 43, 70}, ++{173, 44, 76}, ++{185, 44, 82}, ++{198, 43, 88}, ++{211, 41, 94}, ++{224, 39, 100}, ++{229, 38, 102}, ++{156, 41, 66}, ++{163, 43, 70}, ++{174, 44, 76}, ++{185, 44, 82}, ++{198, 43, 88}, ++{211, 41, 94}, ++{224, 39, 100}, ++{229, 38, 102}, ++{156, 42, 66}, ++{164, 43, 71}, ++{174, 44, 76}, ++{186, 44, 82}, ++{198, 43, 88}, ++{211, 42, 94}, ++{224, 39, 100}, ++{229, 38, 102}, ++{157, 42, 67}, ++{164, 44, 71}, ++{174, 45, 76}, ++{186, 45, 82}, ++{199, 44, 89}, ++{212, 42, 95}, ++{225, 39, 100}, ++{229, 38, 103}, ++{158, 43, 67}, ++{165, 45, 71}, ++{175, 45, 77}, ++{187, 45, 83}, ++{199, 44, 89}, ++{212, 42, 95}, ++{225, 40, 101}, ++{230, 39, 103}, ++{159, 44, 68}, ++{166, 46, 72}, ++{176, 46, 77}, ++{188, 46, 83}, ++{200, 45, 89}, ++{213, 43, 95}, ++{226, 40, 101}, ++{230, 39, 103}, ++{160, 46, 68}, ++{167, 47, 72}, ++{177, 47, 78}, ++{189, 47, 83}, ++{201, 45, 89}, ++{213, 43, 95}, ++{226, 40, 101}, ++{231, 39, 103}, ++{161, 47, 69}, ++{168, 48, 73}, ++{178, 48, 78}, ++{190, 48, 84}, ++{202, 46, 90}, ++{214, 44, 96}, ++{227, 41, 101}, ++{232, 40, 103}, ++{163, 49, 70}, ++{170, 49, 74}, ++{180, 49, 79}, ++{191, 48, 84}, ++{203, 47, 90}, ++{215, 44, 96}, ++{228, 42, 102}, ++{233, 40, 104}, ++{165, 50, 71}, ++{171, 51, 74}, ++{181, 50, 79}, ++{192, 49, 85}, ++{204, 48, 91}, ++{216, 45, 96}, ++{229, 42, 102}, ++{234, 41, 104}, ++{166, 52, 71}, ++{173, 52, 75}, ++{183, 52, 80}, ++{194, 50, 85}, ++{205, 49, 91}, ++{218, 46, 97}, ++{230, 43, 102}, ++{235, 42, 104}, ++{168, 54, 72}, ++{175, 54, 76}, ++{184, 53, 81}, ++{195, 52, 86}, ++{207, 49, 92}, ++{219, 47, 97}, ++{231, 44, 103}, ++{236, 42, 105}, ++{170, 56, 73}, ++{177, 55, 77}, ++{186, 54, 81}, ++{197, 53, 87}, ++{208, 50, 92}, ++{220, 48, 98}, ++{233, 44, 103}, ++{237, 43, 105}, ++{173, 57, 74}, ++{179, 57, 78}, ++{188, 56, 82}, ++{198, 54, 87}, ++{210, 51, 93}, ++{222, 49, 98}, ++{234, 45, 103}, ++{239, 44, 105}, ++{175, 59, 75}, ++{181, 59, 79}, ++{190, 57, 83}, ++{200, 55, 88}, ++{212, 53, 93}, ++{223, 49, 99}, ++{235, 46, 104}, ++{240, 45, 106}, ++{177, 61, 76}, ++{183, 60, 80}, ++{192, 59, 84}, ++{202, 56, 89}, ++{213, 54, 94}, ++{225, 50, 99}, ++{237, 47, 104}, ++{241, 45, 106}, ++{180, 63, 77}, ++{186, 62, 80}, ++{194, 60, 85}, ++{204, 58, 89}, ++{215, 55, 95}, ++{227, 51, 100}, ++{238, 48, 105}, ++{243, 46, 107}, ++{182, 65, 79}, ++{188, 63, 81}, ++{196, 61, 86}, ++{206, 59, 90}, ++{217, 56, 95}, ++{228, 52, 100}, ++{240, 49, 105}, ++{245, 47, 107}, ++{185, 66, 80}, ++{191, 65, 82}, ++{199, 63, 86}, ++{208, 60, 91}, ++{219, 57, 96}, ++{230, 53, 101}, ++{242, 50, 106}, ++{246, 48, 107}, ++{187, 68, 81}, ++{193, 67, 83}, ++{201, 64, 87}, ++{211, 61, 92}, ++{221, 58, 97}, ++{232, 54, 101}, ++{244, 51, 106}, ++{248, 49, 108}, ++{190, 70, 82}, ++{196, 68, 85}, ++{204, 66, 88}, ++{213, 63, 93}, ++{223, 59, 97}, ++{234, 56, 102}, ++{246, 51, 107}, ++{250, 50, 108}, ++{193, 71, 83}, ++{198, 70, 86}, ++{206, 67, 89}, ++{215, 64, 93}, ++{225, 60, 98}, ++{236, 57, 103}, ++{247, 52, 107}, ++{252, 51, 109}, ++{196, 73, 84}, ++{201, 71, 87}, ++{209, 69, 90}, ++{218, 65, 94}, ++{228, 62, 99}, ++{238, 58, 103}, ++{249, 53, 108}, ++{254, 52, 110}, ++{199, 75, 85}, ++{204, 73, 88}, ++{211, 70, 91}, ++{220, 67, 95}, ++{230, 63, 99}, ++{240, 59, 104}, ++{251, 54, 108}, ++{255, 53, 110}, ++{202, 76, 86}, ++{207, 74, 89}, ++{214, 71, 92}, ++{223, 68, 96}, ++{232, 64, 100}, ++{243, 60, 105}, ++{253, 55, 109}, ++{255, 54, 111}, ++{205, 77, 87}, ++{210, 75, 90}, ++{217, 73, 93}, ++{225, 69, 97}, ++{235, 65, 101}, ++{245, 61, 105}, ++{255, 56, 110}, ++{255, 55, 111}, ++{208, 79, 88}, ++{212, 77, 91}, ++{219, 74, 94}, ++{228, 70, 98}, ++{237, 66, 102}, ++{247, 62, 106}, ++{255, 57, 110}, ++{255, 56, 112}, ++{211, 80, 90}, ++{215, 78, 92}, ++{222, 75, 95}, ++{230, 71, 98}, ++{240, 67, 102}, ++{250, 63, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{212, 81, 90}, ++{217, 79, 92}, ++{224, 76, 95}, ++{232, 72, 99}, ++{241, 68, 103}, ++{251, 63, 107}, ++{255, 59, 111}, ++{255, 57, 113}, ++{212, 81, 90}, ++{217, 79, 92}, ++{224, 76, 95}, ++{232, 72, 99}, ++{241, 68, 103}, ++{251, 63, 107}, ++{255, 59, 111}, ++{255, 57, 113}, ++{212, 81, 90}, ++{217, 79, 92}, ++{224, 76, 95}, ++{232, 72, 99}, ++{241, 68, 103}, ++{251, 63, 107}, ++{255, 59, 111}, ++{255, 57, 113}, ++{212, 81, 90}, ++{217, 79, 92}, ++{224, 76, 95}, ++{232, 72, 99}, ++{241, 68, 103}, ++{251, 63, 107}, ++{255, 59, 111}, ++{255, 57, 113}, ++{157, 40, 65}, ++{164, 42, 69}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 70}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 41, 66}, ++{165, 42, 70}, ++{175, 43, 75}, ++{187, 43, 81}, ++{199, 43, 87}, ++{212, 41, 94}, ++{225, 38, 99}, ++{230, 37, 102}, ++{158, 41, 66}, ++{165, 43, 70}, ++{176, 44, 76}, ++{187, 44, 82}, ++{200, 43, 88}, ++{212, 41, 94}, ++{225, 39, 99}, ++{230, 38, 102}, ++{159, 42, 66}, ++{166, 44, 70}, ++{176, 44, 76}, ++{188, 44, 82}, ++{200, 43, 88}, ++{213, 41, 94}, ++{226, 39, 100}, ++{231, 38, 102}, ++{160, 43, 67}, ++{167, 45, 71}, ++{177, 45, 76}, ++{189, 45, 82}, ++{201, 44, 88}, ++{214, 42, 94}, ++{227, 39, 100}, ++{231, 38, 102}, ++{161, 45, 67}, ++{168, 46, 71}, ++{178, 46, 77}, ++{190, 46, 82}, ++{202, 44, 88}, ++{214, 42, 94}, ++{227, 40, 100}, ++{232, 39, 102}, ++{163, 46, 68}, ++{170, 47, 72}, ++{179, 47, 77}, ++{191, 47, 83}, ++{203, 45, 89}, ++{215, 43, 95}, ++{228, 40, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{171, 48, 73}, ++{181, 48, 78}, ++{192, 48, 83}, ++{204, 46, 89}, ++{216, 44, 95}, ++{229, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{173, 50, 73}, ++{182, 49, 78}, ++{193, 49, 84}, ++{205, 47, 90}, ++{217, 44, 95}, ++{230, 42, 101}, ++{235, 40, 103}, ++{168, 51, 71}, ++{174, 51, 74}, ++{184, 51, 79}, ++{195, 50, 84}, ++{206, 48, 90}, ++{219, 45, 96}, ++{231, 42, 101}, ++{236, 41, 103}, ++{170, 53, 71}, ++{176, 53, 75}, ++{185, 52, 80}, ++{196, 51, 85}, ++{208, 49, 91}, ++{220, 46, 96}, ++{232, 43, 102}, ++{237, 42, 104}, ++{172, 55, 72}, ++{178, 54, 76}, ++{187, 53, 81}, ++{198, 52, 86}, ++{209, 50, 91}, ++{221, 47, 97}, ++{233, 44, 102}, ++{238, 42, 104}, ++{174, 56, 73}, ++{180, 56, 77}, ++{189, 55, 81}, ++{199, 53, 86}, ++{211, 51, 92}, ++{223, 48, 97}, ++{235, 44, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{182, 58, 78}, ++{191, 56, 82}, ++{201, 54, 87}, ++{212, 52, 92}, ++{224, 49, 98}, ++{236, 45, 103}, ++{241, 44, 105}, ++{178, 60, 76}, ++{184, 59, 79}, ++{193, 58, 83}, ++{203, 56, 88}, ++{214, 53, 93}, ++{226, 50, 98}, ++{238, 46, 103}, ++{242, 45, 105}, ++{181, 62, 77}, ++{187, 61, 80}, ++{195, 59, 84}, ++{205, 57, 89}, ++{216, 54, 94}, ++{228, 51, 99}, ++{239, 47, 104}, ++{244, 46, 106}, ++{183, 64, 78}, ++{189, 62, 81}, ++{197, 61, 85}, ++{207, 58, 89}, ++{218, 55, 94}, ++{229, 52, 99}, ++{241, 48, 104}, ++{245, 47, 106}, ++{186, 65, 79}, ++{192, 64, 82}, ++{200, 62, 86}, ++{209, 59, 90}, ++{220, 56, 95}, ++{231, 53, 100}, ++{243, 49, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{194, 66, 83}, ++{202, 63, 86}, ++{212, 61, 91}, ++{222, 57, 96}, ++{233, 54, 100}, ++{244, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{197, 67, 84}, ++{205, 65, 87}, ++{214, 62, 92}, ++{224, 59, 96}, ++{235, 55, 101}, ++{246, 51, 106}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 85}, ++{207, 66, 88}, ++{216, 63, 93}, ++{226, 60, 97}, ++{237, 56, 102}, ++{248, 52, 106}, ++{252, 50, 108}, ++{197, 72, 83}, ++{202, 70, 86}, ++{210, 68, 89}, ++{219, 64, 93}, ++{229, 61, 98}, ++{239, 57, 102}, ++{250, 53, 107}, ++{254, 51, 109}, ++{200, 74, 84}, ++{205, 72, 87}, ++{212, 69, 90}, ++{221, 66, 94}, ++{231, 62, 99}, ++{241, 58, 103}, ++{252, 54, 108}, ++{255, 52, 109}, ++{203, 75, 85}, ++{208, 73, 88}, ++{215, 70, 91}, ++{224, 67, 95}, ++{233, 63, 99}, ++{243, 59, 104}, ++{254, 55, 108}, ++{255, 53, 110}, ++{206, 76, 87}, ++{210, 75, 89}, ++{218, 72, 92}, ++{226, 68, 96}, ++{236, 64, 100}, ++{246, 60, 104}, ++{255, 56, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{213, 76, 90}, ++{220, 73, 93}, ++{229, 69, 97}, ++{238, 65, 101}, ++{248, 61, 105}, ++{255, 57, 109}, ++{255, 55, 111}, ++{212, 79, 89}, ++{216, 77, 91}, ++{223, 74, 94}, ++{231, 71, 98}, ++{241, 67, 102}, ++{250, 62, 106}, ++{255, 58, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{157, 40, 65}, ++{164, 42, 69}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 70}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 41, 66}, ++{165, 42, 70}, ++{175, 43, 75}, ++{187, 43, 81}, ++{199, 43, 87}, ++{212, 41, 94}, ++{225, 38, 99}, ++{230, 37, 102}, ++{158, 41, 66}, ++{165, 43, 70}, ++{176, 44, 76}, ++{187, 44, 82}, ++{200, 43, 88}, ++{212, 41, 94}, ++{225, 39, 99}, ++{230, 38, 102}, ++{159, 42, 66}, ++{166, 44, 70}, ++{176, 44, 76}, ++{188, 44, 82}, ++{200, 43, 88}, ++{213, 41, 94}, ++{226, 39, 100}, ++{231, 38, 102}, ++{160, 43, 67}, ++{167, 45, 71}, ++{177, 45, 76}, ++{189, 45, 82}, ++{201, 44, 88}, ++{214, 42, 94}, ++{227, 39, 100}, ++{231, 38, 102}, ++{161, 45, 67}, ++{168, 46, 71}, ++{178, 46, 77}, ++{190, 46, 82}, ++{202, 44, 88}, ++{214, 42, 94}, ++{227, 40, 100}, ++{232, 39, 102}, ++{163, 46, 68}, ++{170, 47, 72}, ++{179, 47, 77}, ++{191, 47, 83}, ++{203, 45, 89}, ++{215, 43, 95}, ++{228, 40, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{171, 48, 73}, ++{181, 48, 78}, ++{192, 48, 83}, ++{204, 46, 89}, ++{216, 44, 95}, ++{229, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{173, 50, 73}, ++{182, 49, 78}, ++{193, 49, 84}, ++{205, 47, 90}, ++{217, 44, 95}, ++{230, 42, 101}, ++{235, 40, 103}, ++{168, 51, 71}, ++{174, 51, 74}, ++{184, 51, 79}, ++{195, 50, 84}, ++{206, 48, 90}, ++{219, 45, 96}, ++{231, 42, 101}, ++{236, 41, 103}, ++{170, 53, 71}, ++{176, 53, 75}, ++{185, 52, 80}, ++{196, 51, 85}, ++{208, 49, 91}, ++{220, 46, 96}, ++{232, 43, 102}, ++{237, 42, 104}, ++{172, 55, 72}, ++{178, 54, 76}, ++{187, 53, 81}, ++{198, 52, 86}, ++{209, 50, 91}, ++{221, 47, 97}, ++{233, 44, 102}, ++{238, 42, 104}, ++{174, 56, 73}, ++{180, 56, 77}, ++{189, 55, 81}, ++{199, 53, 86}, ++{211, 51, 92}, ++{223, 48, 97}, ++{235, 44, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{182, 58, 78}, ++{191, 56, 82}, ++{201, 54, 87}, ++{212, 52, 92}, ++{224, 49, 98}, ++{236, 45, 103}, ++{241, 44, 105}, ++{178, 60, 76}, ++{184, 59, 79}, ++{193, 58, 83}, ++{203, 56, 88}, ++{214, 53, 93}, ++{226, 50, 98}, ++{238, 46, 103}, ++{242, 45, 105}, ++{181, 62, 77}, ++{187, 61, 80}, ++{195, 59, 84}, ++{205, 57, 89}, ++{216, 54, 94}, ++{228, 51, 99}, ++{239, 47, 104}, ++{244, 46, 106}, ++{183, 64, 78}, ++{189, 62, 81}, ++{197, 61, 85}, ++{207, 58, 89}, ++{218, 55, 94}, ++{229, 52, 99}, ++{241, 48, 104}, ++{245, 47, 106}, ++{186, 65, 79}, ++{192, 64, 82}, ++{200, 62, 86}, ++{209, 59, 90}, ++{220, 56, 95}, ++{231, 53, 100}, ++{243, 49, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{194, 66, 83}, ++{202, 63, 86}, ++{212, 61, 91}, ++{222, 57, 96}, ++{233, 54, 100}, ++{244, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{197, 67, 84}, ++{205, 65, 87}, ++{214, 62, 92}, ++{224, 59, 96}, ++{235, 55, 101}, ++{246, 51, 106}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 85}, ++{207, 66, 88}, ++{216, 63, 93}, ++{226, 60, 97}, ++{237, 56, 102}, ++{248, 52, 106}, ++{252, 50, 108}, ++{197, 72, 83}, ++{202, 70, 86}, ++{210, 68, 89}, ++{219, 64, 93}, ++{229, 61, 98}, ++{239, 57, 102}, ++{250, 53, 107}, ++{254, 51, 109}, ++{200, 74, 84}, ++{205, 72, 87}, ++{212, 69, 90}, ++{221, 66, 94}, ++{231, 62, 99}, ++{241, 58, 103}, ++{252, 54, 108}, ++{255, 52, 109}, ++{203, 75, 85}, ++{208, 73, 88}, ++{215, 70, 91}, ++{224, 67, 95}, ++{233, 63, 99}, ++{243, 59, 104}, ++{254, 55, 108}, ++{255, 53, 110}, ++{206, 76, 87}, ++{210, 75, 89}, ++{218, 72, 92}, ++{226, 68, 96}, ++{236, 64, 100}, ++{246, 60, 104}, ++{255, 56, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{213, 76, 90}, ++{220, 73, 93}, ++{229, 69, 97}, ++{238, 65, 101}, ++{248, 61, 105}, ++{255, 57, 109}, ++{255, 55, 111}, ++{212, 79, 89}, ++{216, 77, 91}, ++{223, 74, 94}, ++{231, 71, 98}, ++{241, 67, 102}, ++{250, 62, 106}, ++{255, 58, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{157, 40, 65}, ++{164, 42, 69}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 70}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 41, 66}, ++{165, 42, 70}, ++{175, 43, 75}, ++{187, 43, 81}, ++{199, 43, 87}, ++{212, 41, 94}, ++{225, 38, 99}, ++{230, 37, 102}, ++{158, 41, 66}, ++{165, 43, 70}, ++{176, 44, 76}, ++{187, 44, 82}, ++{200, 43, 88}, ++{212, 41, 94}, ++{225, 39, 99}, ++{230, 38, 102}, ++{159, 42, 66}, ++{166, 44, 70}, ++{176, 44, 76}, ++{188, 44, 82}, ++{200, 43, 88}, ++{213, 41, 94}, ++{226, 39, 100}, ++{231, 38, 102}, ++{160, 43, 67}, ++{167, 45, 71}, ++{177, 45, 76}, ++{189, 45, 82}, ++{201, 44, 88}, ++{214, 42, 94}, ++{227, 39, 100}, ++{231, 38, 102}, ++{161, 45, 67}, ++{168, 46, 71}, ++{178, 46, 77}, ++{190, 46, 82}, ++{202, 44, 88}, ++{214, 42, 94}, ++{227, 40, 100}, ++{232, 39, 102}, ++{163, 46, 68}, ++{170, 47, 72}, ++{179, 47, 77}, ++{191, 47, 83}, ++{203, 45, 89}, ++{215, 43, 95}, ++{228, 40, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{171, 48, 73}, ++{181, 48, 78}, ++{192, 48, 83}, ++{204, 46, 89}, ++{216, 44, 95}, ++{229, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{173, 50, 73}, ++{182, 49, 78}, ++{193, 49, 84}, ++{205, 47, 90}, ++{217, 44, 95}, ++{230, 42, 101}, ++{235, 40, 103}, ++{168, 51, 71}, ++{174, 51, 74}, ++{184, 51, 79}, ++{195, 50, 84}, ++{206, 48, 90}, ++{219, 45, 96}, ++{231, 42, 101}, ++{236, 41, 103}, ++{170, 53, 71}, ++{176, 53, 75}, ++{185, 52, 80}, ++{196, 51, 85}, ++{208, 49, 91}, ++{220, 46, 96}, ++{232, 43, 102}, ++{237, 42, 104}, ++{172, 55, 72}, ++{178, 54, 76}, ++{187, 53, 81}, ++{198, 52, 86}, ++{209, 50, 91}, ++{221, 47, 97}, ++{233, 44, 102}, ++{238, 42, 104}, ++{174, 56, 73}, ++{180, 56, 77}, ++{189, 55, 81}, ++{199, 53, 86}, ++{211, 51, 92}, ++{223, 48, 97}, ++{235, 44, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{182, 58, 78}, ++{191, 56, 82}, ++{201, 54, 87}, ++{212, 52, 92}, ++{224, 49, 98}, ++{236, 45, 103}, ++{241, 44, 105}, ++{178, 60, 76}, ++{184, 59, 79}, ++{193, 58, 83}, ++{203, 56, 88}, ++{214, 53, 93}, ++{226, 50, 98}, ++{238, 46, 103}, ++{242, 45, 105}, ++{181, 62, 77}, ++{187, 61, 80}, ++{195, 59, 84}, ++{205, 57, 89}, ++{216, 54, 94}, ++{228, 51, 99}, ++{239, 47, 104}, ++{244, 46, 106}, ++{183, 64, 78}, ++{189, 62, 81}, ++{197, 61, 85}, ++{207, 58, 89}, ++{218, 55, 94}, ++{229, 52, 99}, ++{241, 48, 104}, ++{245, 47, 106}, ++{186, 65, 79}, ++{192, 64, 82}, ++{200, 62, 86}, ++{209, 59, 90}, ++{220, 56, 95}, ++{231, 53, 100}, ++{243, 49, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{194, 66, 83}, ++{202, 63, 86}, ++{212, 61, 91}, ++{222, 57, 96}, ++{233, 54, 100}, ++{244, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{197, 67, 84}, ++{205, 65, 87}, ++{214, 62, 92}, ++{224, 59, 96}, ++{235, 55, 101}, ++{246, 51, 106}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 85}, ++{207, 66, 88}, ++{216, 63, 93}, ++{226, 60, 97}, ++{237, 56, 102}, ++{248, 52, 106}, ++{252, 50, 108}, ++{197, 72, 83}, ++{202, 70, 86}, ++{210, 68, 89}, ++{219, 64, 93}, ++{229, 61, 98}, ++{239, 57, 102}, ++{250, 53, 107}, ++{254, 51, 109}, ++{200, 74, 84}, ++{205, 72, 87}, ++{212, 69, 90}, ++{221, 66, 94}, ++{231, 62, 99}, ++{241, 58, 103}, ++{252, 54, 108}, ++{255, 52, 109}, ++{203, 75, 85}, ++{208, 73, 88}, ++{215, 70, 91}, ++{224, 67, 95}, ++{233, 63, 99}, ++{243, 59, 104}, ++{254, 55, 108}, ++{255, 53, 110}, ++{206, 76, 87}, ++{210, 75, 89}, ++{218, 72, 92}, ++{226, 68, 96}, ++{236, 64, 100}, ++{246, 60, 104}, ++{255, 56, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{213, 76, 90}, ++{220, 73, 93}, ++{229, 69, 97}, ++{238, 65, 101}, ++{248, 61, 105}, ++{255, 57, 109}, ++{255, 55, 111}, ++{212, 79, 89}, ++{216, 77, 91}, ++{223, 74, 94}, ++{231, 71, 98}, ++{241, 67, 102}, ++{250, 62, 106}, ++{255, 58, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{157, 40, 65}, ++{164, 42, 69}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 40, 65}, ++{164, 42, 70}, ++{175, 43, 75}, ++{186, 43, 81}, ++{199, 42, 87}, ++{212, 41, 93}, ++{225, 38, 99}, ++{230, 37, 101}, ++{157, 41, 66}, ++{165, 42, 70}, ++{175, 43, 75}, ++{187, 43, 81}, ++{199, 43, 87}, ++{212, 41, 94}, ++{225, 38, 99}, ++{230, 37, 102}, ++{158, 41, 66}, ++{165, 43, 70}, ++{176, 44, 76}, ++{187, 44, 82}, ++{200, 43, 88}, ++{212, 41, 94}, ++{225, 39, 99}, ++{230, 38, 102}, ++{159, 42, 66}, ++{166, 44, 70}, ++{176, 44, 76}, ++{188, 44, 82}, ++{200, 43, 88}, ++{213, 41, 94}, ++{226, 39, 100}, ++{231, 38, 102}, ++{160, 43, 67}, ++{167, 45, 71}, ++{177, 45, 76}, ++{189, 45, 82}, ++{201, 44, 88}, ++{214, 42, 94}, ++{227, 39, 100}, ++{231, 38, 102}, ++{161, 45, 67}, ++{168, 46, 71}, ++{178, 46, 77}, ++{190, 46, 82}, ++{202, 44, 88}, ++{214, 42, 94}, ++{227, 40, 100}, ++{232, 39, 102}, ++{163, 46, 68}, ++{170, 47, 72}, ++{179, 47, 77}, ++{191, 47, 83}, ++{203, 45, 89}, ++{215, 43, 95}, ++{228, 40, 100}, ++{233, 39, 102}, ++{164, 48, 69}, ++{171, 48, 73}, ++{181, 48, 78}, ++{192, 48, 83}, ++{204, 46, 89}, ++{216, 44, 95}, ++{229, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{173, 50, 73}, ++{182, 49, 78}, ++{193, 49, 84}, ++{205, 47, 90}, ++{217, 44, 95}, ++{230, 42, 101}, ++{235, 40, 103}, ++{168, 51, 71}, ++{174, 51, 74}, ++{184, 51, 79}, ++{195, 50, 84}, ++{206, 48, 90}, ++{219, 45, 96}, ++{231, 42, 101}, ++{236, 41, 103}, ++{170, 53, 71}, ++{176, 53, 75}, ++{185, 52, 80}, ++{196, 51, 85}, ++{208, 49, 91}, ++{220, 46, 96}, ++{232, 43, 102}, ++{237, 42, 104}, ++{172, 55, 72}, ++{178, 54, 76}, ++{187, 53, 81}, ++{198, 52, 86}, ++{209, 50, 91}, ++{221, 47, 97}, ++{233, 44, 102}, ++{238, 42, 104}, ++{174, 56, 73}, ++{180, 56, 77}, ++{189, 55, 81}, ++{199, 53, 86}, ++{211, 51, 92}, ++{223, 48, 97}, ++{235, 44, 102}, ++{239, 43, 104}, ++{176, 58, 74}, ++{182, 58, 78}, ++{191, 56, 82}, ++{201, 54, 87}, ++{212, 52, 92}, ++{224, 49, 98}, ++{236, 45, 103}, ++{241, 44, 105}, ++{178, 60, 76}, ++{184, 59, 79}, ++{193, 58, 83}, ++{203, 56, 88}, ++{214, 53, 93}, ++{226, 50, 98}, ++{238, 46, 103}, ++{242, 45, 105}, ++{181, 62, 77}, ++{187, 61, 80}, ++{195, 59, 84}, ++{205, 57, 89}, ++{216, 54, 94}, ++{228, 51, 99}, ++{239, 47, 104}, ++{244, 46, 106}, ++{183, 64, 78}, ++{189, 62, 81}, ++{197, 61, 85}, ++{207, 58, 89}, ++{218, 55, 94}, ++{229, 52, 99}, ++{241, 48, 104}, ++{245, 47, 106}, ++{186, 65, 79}, ++{192, 64, 82}, ++{200, 62, 86}, ++{209, 59, 90}, ++{220, 56, 95}, ++{231, 53, 100}, ++{243, 49, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{194, 66, 83}, ++{202, 63, 86}, ++{212, 61, 91}, ++{222, 57, 96}, ++{233, 54, 100}, ++{244, 50, 105}, ++{249, 48, 107}, ++{191, 69, 81}, ++{197, 67, 84}, ++{205, 65, 87}, ++{214, 62, 92}, ++{224, 59, 96}, ++{235, 55, 101}, ++{246, 51, 106}, ++{251, 49, 108}, ++{194, 70, 82}, ++{199, 69, 85}, ++{207, 66, 88}, ++{216, 63, 93}, ++{226, 60, 97}, ++{237, 56, 102}, ++{248, 52, 106}, ++{252, 50, 108}, ++{197, 72, 83}, ++{202, 70, 86}, ++{210, 68, 89}, ++{219, 64, 93}, ++{229, 61, 98}, ++{239, 57, 102}, ++{250, 53, 107}, ++{254, 51, 109}, ++{200, 74, 84}, ++{205, 72, 87}, ++{212, 69, 90}, ++{221, 66, 94}, ++{231, 62, 99}, ++{241, 58, 103}, ++{252, 54, 108}, ++{255, 52, 109}, ++{203, 75, 85}, ++{208, 73, 88}, ++{215, 70, 91}, ++{224, 67, 95}, ++{233, 63, 99}, ++{243, 59, 104}, ++{254, 55, 108}, ++{255, 53, 110}, ++{206, 76, 87}, ++{210, 75, 89}, ++{218, 72, 92}, ++{226, 68, 96}, ++{236, 64, 100}, ++{246, 60, 104}, ++{255, 56, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{213, 76, 90}, ++{220, 73, 93}, ++{229, 69, 97}, ++{238, 65, 101}, ++{248, 61, 105}, ++{255, 57, 109}, ++{255, 55, 111}, ++{212, 79, 89}, ++{216, 77, 91}, ++{223, 74, 94}, ++{231, 71, 98}, ++{241, 67, 102}, ++{250, 62, 106}, ++{255, 58, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 91}, ++{224, 75, 94}, ++{233, 71, 98}, ++{242, 67, 102}, ++{252, 63, 106}, ++{255, 58, 110}, ++{255, 57, 112}, ++{85, 102, 121}, ++{100, 97, 127}, ++{117, 90, 133}, ++{135, 83, 138}, ++{152, 76, 143}, ++{169, 70, 147}, ++{185, 64, 151}, ++{189, 62, 152}, ++{86, 103, 122}, ++{100, 97, 127}, ++{117, 90, 133}, ++{135, 83, 138}, ++{152, 77, 143}, ++{169, 70, 147}, ++{185, 64, 151}, ++{189, 62, 152}, ++{87, 103, 122}, ++{101, 97, 127}, ++{118, 90, 133}, ++{135, 83, 138}, ++{152, 77, 143}, ++{169, 70, 147}, ++{186, 64, 151}, ++{190, 63, 152}, ++{88, 104, 122}, ++{102, 98, 127}, ++{119, 91, 133}, ++{136, 84, 138}, ++{153, 77, 143}, ++{170, 70, 147}, ++{186, 64, 151}, ++{190, 63, 152}, ++{89, 104, 123}, ++{103, 98, 128}, ++{120, 91, 133}, ++{137, 84, 138}, ++{154, 77, 143}, ++{170, 71, 147}, ++{187, 65, 151}, ++{191, 63, 152}, ++{91, 105, 123}, ++{105, 99, 128}, ++{121, 92, 133}, ++{138, 85, 138}, ++{155, 78, 143}, ++{171, 71, 147}, ++{187, 65, 151}, ++{191, 63, 152}, ++{94, 106, 124}, ++{107, 100, 128}, ++{123, 92, 134}, ++{139, 85, 139}, ++{156, 78, 143}, ++{172, 72, 147}, ++{188, 65, 151}, ++{192, 64, 152}, ++{96, 107, 124}, ++{109, 100, 129}, ++{124, 93, 134}, ++{141, 86, 139}, ++{157, 79, 143}, ++{173, 72, 147}, ++{189, 66, 151}, ++{193, 64, 152}, ++{99, 108, 125}, ++{111, 101, 129}, ++{126, 94, 134}, ++{142, 87, 139}, ++{159, 79, 143}, ++{175, 73, 147}, ++{190, 66, 151}, ++{194, 65, 152}, ++{102, 109, 125}, ++{114, 102, 130}, ++{128, 95, 134}, ++{144, 87, 139}, ++{160, 80, 143}, ++{176, 73, 147}, ++{192, 67, 151}, ++{195, 65, 152}, ++{105, 110, 126}, ++{116, 103, 130}, ++{131, 96, 135}, ++{146, 88, 139}, ++{162, 81, 144}, ++{178, 74, 148}, ++{193, 67, 151}, ++{197, 66, 152}, ++{108, 111, 127}, ++{119, 104, 131}, ++{133, 96, 135}, ++{148, 89, 139}, ++{164, 82, 144}, ++{179, 75, 148}, ++{194, 68, 151}, ++{198, 66, 152}, ++{111, 111, 127}, ++{122, 105, 131}, ++{136, 97, 135}, ++{150, 90, 140}, ++{166, 82, 144}, ++{181, 75, 148}, ++{196, 69, 151}, ++{200, 67, 152}, ++{115, 112, 128}, ++{125, 106, 132}, ++{138, 98, 136}, ++{153, 91, 140}, ++{168, 83, 144}, ++{183, 76, 148}, ++{198, 69, 152}, ++{201, 68, 152}, ++{118, 113, 129}, ++{128, 107, 132}, ++{141, 99, 136}, ++{155, 91, 140}, ++{170, 84, 144}, ++{185, 77, 148}, ++{199, 70, 152}, ++{203, 68, 152}, ++{122, 114, 129}, ++{132, 107, 132}, ++{144, 100, 136}, ++{158, 92, 140}, ++{172, 85, 144}, ++{187, 78, 148}, ++{201, 71, 152}, ++{205, 69, 153}, ++{126, 114, 130}, ++{135, 108, 133}, ++{147, 101, 137}, ++{160, 93, 141}, ++{175, 86, 144}, ++{189, 78, 148}, ++{203, 72, 152}, ++{207, 70, 153}, ++{129, 115, 131}, ++{138, 109, 133}, ++{150, 102, 137}, ++{163, 94, 141}, ++{177, 86, 145}, ++{191, 79, 148}, ++{205, 72, 152}, ++{209, 71, 153}, ++{133, 116, 131}, ++{142, 110, 134}, ++{153, 102, 137}, ++{166, 95, 141}, ++{179, 87, 145}, ++{193, 80, 148}, ++{207, 73, 152}, ++{211, 71, 153}, ++{137, 116, 132}, ++{145, 110, 134}, ++{156, 103, 138}, ++{169, 96, 141}, ++{182, 88, 145}, ++{196, 81, 149}, ++{209, 74, 152}, ++{213, 72, 153}, ++{141, 117, 132}, ++{149, 111, 135}, ++{160, 104, 138}, ++{172, 96, 142}, ++{185, 89, 145}, ++{198, 82, 149}, ++{212, 75, 152}, ++{215, 73, 153}, ++{145, 117, 133}, ++{152, 112, 135}, ++{163, 105, 139}, ++{175, 97, 142}, ++{187, 90, 145}, ++{201, 83, 149}, ++{214, 76, 152}, ++{217, 74, 153}, ++{149, 118, 134}, ++{156, 112, 136}, ++{166, 106, 139}, ++{178, 98, 142}, ++{190, 91, 146}, ++{203, 83, 149}, ++{216, 76, 152}, ++{220, 75, 153}, ++{152, 118, 134}, ++{160, 113, 136}, ++{169, 106, 139}, ++{181, 99, 143}, ++{193, 91, 146}, ++{206, 84, 149}, ++{219, 77, 152}, ++{222, 75, 153}, ++{156, 119, 135}, ++{163, 114, 137}, ++{173, 107, 140}, ++{184, 100, 143}, ++{196, 92, 146}, ++{208, 85, 149}, ++{221, 78, 153}, ++{224, 76, 153}, ++{160, 119, 135}, ++{167, 114, 137}, ++{176, 108, 140}, ++{187, 100, 143}, ++{199, 93, 146}, ++{211, 86, 150}, ++{224, 79, 153}, ++{227, 77, 153}, ++{164, 120, 136}, ++{171, 115, 138}, ++{180, 108, 140}, ++{190, 101, 143}, ++{202, 94, 147}, ++{214, 87, 150}, ++{226, 80, 153}, ++{229, 78, 154}, ++{168, 120, 136}, ++{174, 115, 138}, ++{183, 109, 141}, ++{194, 102, 144}, ++{205, 95, 147}, ++{217, 87, 150}, ++{229, 80, 153}, ++{232, 79, 154}, ++{170, 120, 137}, ++{176, 115, 138}, ++{185, 109, 141}, ++{195, 102, 144}, ++{206, 95, 147}, ++{218, 88, 150}, ++{230, 81, 153}, ++{233, 79, 154}, ++{170, 120, 137}, ++{176, 115, 138}, ++{185, 109, 141}, ++{195, 102, 144}, ++{206, 95, 147}, ++{218, 88, 150}, ++{230, 81, 153}, ++{233, 79, 154}, ++{170, 120, 137}, ++{176, 115, 138}, ++{185, 109, 141}, ++{195, 102, 144}, ++{206, 95, 147}, ++{218, 88, 150}, ++{230, 81, 153}, ++{233, 79, 154}, ++{170, 120, 137}, ++{176, 115, 138}, ++{185, 109, 141}, ++{195, 102, 144}, ++{206, 95, 147}, ++{218, 88, 150}, ++{230, 81, 153}, ++{233, 79, 154}, ++{86, 102, 120}, ++{101, 96, 126}, ++{118, 89, 132}, ++{135, 83, 137}, ++{153, 76, 142}, ++{169, 70, 146}, ++{186, 64, 150}, ++{190, 62, 151}, ++{87, 102, 120}, ++{101, 96, 126}, ++{118, 90, 132}, ++{136, 83, 137}, ++{153, 76, 142}, ++{169, 70, 146}, ++{186, 64, 150}, ++{190, 62, 151}, ++{88, 102, 121}, ++{102, 96, 126}, ++{119, 90, 132}, ++{136, 83, 137}, ++{153, 76, 142}, ++{170, 70, 146}, ++{186, 64, 150}, ++{190, 62, 151}, ++{89, 103, 121}, ++{103, 97, 126}, ++{119, 90, 132}, ++{137, 83, 137}, ++{154, 77, 142}, ++{170, 70, 146}, ++{187, 64, 150}, ++{191, 63, 151}, ++{90, 103, 121}, ++{104, 98, 127}, ++{121, 91, 132}, ++{138, 84, 137}, ++{154, 77, 142}, ++{171, 71, 146}, ++{187, 64, 150}, ++{191, 63, 151}, ++{92, 104, 122}, ++{106, 98, 127}, ++{122, 91, 132}, ++{139, 84, 137}, ++{155, 77, 142}, ++{172, 71, 146}, ++{188, 65, 150}, ++{192, 63, 151}, ++{95, 105, 122}, ++{108, 99, 127}, ++{123, 92, 133}, ++{140, 85, 138}, ++{156, 78, 142}, ++{173, 71, 147}, ++{189, 65, 151}, ++{193, 64, 151}, ++{97, 106, 123}, ++{110, 100, 128}, ++{125, 93, 133}, ++{141, 86, 138}, ++{158, 79, 142}, ++{174, 72, 147}, ++{190, 66, 151}, ++{194, 64, 151}, ++{100, 107, 124}, ++{112, 101, 128}, ++{127, 93, 133}, ++{143, 86, 138}, ++{159, 79, 142}, ++{175, 72, 147}, ++{191, 66, 151}, ++{195, 64, 152}, ++{103, 108, 124}, ++{114, 102, 129}, ++{129, 94, 133}, ++{145, 87, 138}, ++{161, 80, 143}, ++{177, 73, 147}, ++{192, 67, 151}, ++{196, 65, 152}, ++{106, 109, 125}, ++{117, 103, 129}, ++{131, 95, 134}, ++{147, 88, 138}, ++{162, 81, 143}, ++{178, 74, 147}, ++{193, 67, 151}, ++{197, 66, 152}, ++{109, 110, 126}, ++{120, 103, 130}, ++{134, 96, 134}, ++{149, 89, 139}, ++{164, 81, 143}, ++{180, 74, 147}, ++{195, 68, 151}, ++{199, 66, 152}, ++{112, 111, 126}, ++{123, 104, 130}, ++{136, 97, 134}, ++{151, 89, 139}, ++{166, 82, 143}, ++{181, 75, 147}, ++{196, 68, 151}, ++{200, 67, 152}, ++{116, 112, 127}, ++{126, 105, 131}, ++{139, 98, 135}, ++{153, 90, 139}, ++{168, 83, 143}, ++{183, 76, 147}, ++{198, 69, 151}, ++{202, 68, 152}, ++{119, 112, 128}, ++{129, 106, 131}, ++{142, 99, 135}, ++{156, 91, 139}, ++{170, 84, 143}, ++{185, 77, 147}, ++{200, 70, 151}, ++{203, 68, 152}, ++{123, 113, 128}, ++{132, 107, 132}, ++{145, 100, 136}, ++{158, 92, 140}, ++{173, 85, 144}, ++{187, 77, 147}, ++{202, 71, 151}, ++{205, 69, 152}, ++{126, 114, 129}, ++{136, 108, 132}, ++{148, 100, 136}, ++{161, 93, 140}, ++{175, 85, 144}, ++{189, 78, 148}, ++{204, 71, 151}, ++{207, 70, 152}, ++{130, 115, 130}, ++{139, 109, 133}, ++{151, 101, 136}, ++{164, 94, 140}, ++{177, 86, 144}, ++{191, 79, 148}, ++{206, 72, 151}, ++{209, 70, 152}, ++{134, 115, 130}, ++{142, 109, 133}, ++{154, 102, 137}, ++{166, 95, 140}, ++{180, 87, 144}, ++{194, 80, 148}, ++{208, 73, 151}, ++{211, 71, 152}, ++{138, 116, 131}, ++{146, 110, 134}, ++{157, 103, 137}, ++{169, 95, 141}, ++{182, 88, 144}, ++{196, 81, 148}, ++{210, 74, 151}, ++{213, 72, 152}, ++{141, 116, 132}, ++{149, 111, 134}, ++{160, 104, 137}, ++{172, 96, 141}, ++{185, 89, 145}, ++{198, 81, 148}, ++{212, 75, 152}, ++{215, 73, 152}, ++{145, 117, 132}, ++{153, 111, 135}, ++{163, 104, 138}, ++{175, 97, 141}, ++{188, 90, 145}, ++{201, 82, 148}, ++{214, 75, 152}, ++{218, 74, 152}, ++{149, 118, 133}, ++{157, 112, 135}, ++{167, 105, 138}, ++{178, 98, 142}, ++{191, 90, 145}, ++{203, 83, 148}, ++{217, 76, 152}, ++{220, 74, 153}, ++{153, 118, 133}, ++{160, 113, 136}, ++{170, 106, 139}, ++{181, 99, 142}, ++{193, 91, 145}, ++{206, 84, 149}, ++{219, 77, 152}, ++{222, 75, 153}, ++{157, 119, 134}, ++{164, 113, 136}, ++{173, 107, 139}, ++{184, 99, 142}, ++{196, 92, 145}, ++{209, 85, 149}, ++{221, 78, 152}, ++{225, 76, 153}, ++{161, 119, 135}, ++{168, 114, 137}, ++{177, 107, 139}, ++{188, 100, 142}, ++{199, 93, 146}, ++{211, 86, 149}, ++{224, 79, 152}, ++{227, 77, 153}, ++{165, 119, 135}, ++{171, 114, 137}, ++{180, 108, 140}, ++{191, 101, 143}, ++{202, 94, 146}, ++{214, 86, 149}, ++{226, 79, 152}, ++{230, 78, 153}, ++{169, 120, 136}, ++{175, 115, 138}, ++{184, 109, 140}, ++{194, 101, 143}, ++{205, 94, 146}, ++{217, 87, 149}, ++{229, 80, 152}, ++{232, 78, 153}, ++{170, 120, 136}, ++{177, 115, 138}, ++{185, 109, 140}, ++{196, 102, 143}, ++{207, 95, 146}, ++{218, 88, 149}, ++{230, 81, 153}, ++{233, 79, 153}, ++{170, 120, 136}, ++{177, 115, 138}, ++{185, 109, 140}, ++{196, 102, 143}, ++{207, 95, 146}, ++{218, 88, 149}, ++{230, 81, 153}, ++{233, 79, 153}, ++{170, 120, 136}, ++{177, 115, 138}, ++{185, 109, 140}, ++{196, 102, 143}, ++{207, 95, 146}, ++{218, 88, 149}, ++{230, 81, 153}, ++{233, 79, 153}, ++{170, 120, 136}, ++{177, 115, 138}, ++{185, 109, 140}, ++{196, 102, 143}, ++{207, 95, 146}, ++{218, 88, 149}, ++{230, 81, 153}, ++{233, 79, 153}, ++{88, 100, 118}, ++{103, 95, 124}, ++{119, 89, 130}, ++{136, 82, 136}, ++{154, 76, 141}, ++{170, 69, 145}, ++{186, 63, 149}, ++{190, 62, 150}, ++{89, 100, 118}, ++{103, 95, 124}, ++{119, 89, 130}, ++{137, 82, 136}, ++{154, 76, 141}, ++{170, 69, 145}, ++{187, 63, 149}, ++{191, 62, 150}, ++{89, 101, 119}, ++{103, 95, 124}, ++{120, 89, 130}, ++{137, 82, 136}, ++{154, 76, 141}, ++{171, 70, 145}, ++{187, 64, 149}, ++{191, 62, 150}, ++{91, 101, 119}, ++{104, 96, 124}, ++{121, 89, 130}, ++{138, 83, 136}, ++{155, 76, 141}, ++{171, 70, 145}, ++{187, 64, 149}, ++{191, 62, 150}, ++{92, 102, 119}, ++{106, 96, 125}, ++{122, 90, 130}, ++{139, 83, 136}, ++{155, 77, 141}, ++{172, 70, 145}, ++{188, 64, 149}, ++{192, 63, 150}, ++{94, 103, 120}, ++{107, 97, 125}, ++{123, 91, 131}, ++{140, 84, 136}, ++{156, 77, 141}, ++{173, 71, 145}, ++{189, 64, 149}, ++{193, 63, 150}, ++{96, 104, 121}, ++{109, 98, 126}, ++{125, 91, 131}, ++{141, 84, 136}, ++{157, 78, 141}, ++{174, 71, 145}, ++{189, 65, 149}, ++{193, 63, 150}, ++{99, 105, 121}, ++{111, 99, 126}, ++{126, 92, 131}, ++{142, 85, 136}, ++{159, 78, 141}, ++{175, 72, 145}, ++{190, 65, 149}, ++{194, 64, 150}, ++{101, 106, 122}, ++{113, 100, 126}, ++{128, 93, 132}, ++{144, 86, 136}, ++{160, 79, 141}, ++{176, 72, 145}, ++{192, 66, 149}, ++{195, 64, 150}, ++{104, 107, 123}, ++{116, 101, 127}, ++{130, 94, 132}, ++{146, 86, 137}, ++{162, 79, 141}, ++{177, 73, 146}, ++{193, 66, 150}, ++{197, 65, 150}, ++{107, 108, 123}, ++{118, 102, 127}, ++{133, 94, 132}, ++{148, 87, 137}, ++{163, 80, 141}, ++{179, 73, 146}, ++{194, 67, 150}, ++{198, 65, 151}, ++{110, 109, 124}, ++{121, 103, 128}, ++{135, 95, 133}, ++{150, 88, 137}, ++{165, 81, 142}, ++{180, 74, 146}, ++{196, 67, 150}, ++{199, 66, 151}, ++{114, 110, 125}, ++{124, 103, 129}, ++{137, 96, 133}, ++{152, 89, 137}, ++{167, 82, 142}, ++{182, 75, 146}, ++{197, 68, 150}, ++{201, 67, 151}, ++{117, 111, 126}, ++{127, 104, 129}, ++{140, 97, 133}, ++{154, 90, 138}, ++{169, 82, 142}, ++{184, 75, 146}, ++{199, 69, 150}, ++{202, 67, 151}, ++{120, 111, 126}, ++{130, 105, 130}, ++{143, 98, 134}, ++{157, 91, 138}, ++{171, 83, 142}, ++{186, 76, 146}, ++{201, 70, 150}, ++{204, 68, 151}, ++{124, 112, 127}, ++{133, 106, 130}, ++{146, 99, 134}, ++{159, 91, 138}, ++{173, 84, 142}, ++{188, 77, 146}, ++{202, 70, 150}, ++{206, 69, 151}, ++{128, 113, 128}, ++{137, 107, 131}, ++{149, 100, 135}, ++{162, 92, 139}, ++{176, 85, 143}, ++{190, 78, 146}, ++{204, 71, 150}, ++{208, 69, 151}, ++{131, 114, 128}, ++{140, 108, 131}, ++{152, 101, 135}, ++{165, 93, 139}, ++{178, 86, 143}, ++{192, 79, 147}, ++{206, 72, 150}, ++{210, 70, 151}, ++{135, 114, 129}, ++{143, 109, 132}, ++{155, 101, 135}, ++{167, 94, 139}, ++{181, 87, 143}, ++{194, 79, 147}, ++{208, 73, 150}, ++{212, 71, 151}, ++{139, 115, 130}, ++{147, 109, 132}, ++{158, 102, 136}, ++{170, 95, 140}, ++{183, 87, 143}, ++{197, 80, 147}, ++{210, 73, 150}, ++{214, 72, 151}, ++{142, 116, 130}, ++{150, 110, 133}, ++{161, 103, 136}, ++{173, 96, 140}, ++{186, 88, 143}, ++{199, 81, 147}, ++{213, 74, 151}, ++{216, 73, 151}, ++{146, 116, 131}, ++{154, 111, 133}, ++{164, 104, 137}, ++{176, 96, 140}, ++{189, 89, 144}, ++{202, 82, 147}, ++{215, 75, 151}, ++{218, 73, 152}, ++{150, 117, 132}, ++{157, 111, 134}, ++{167, 105, 137}, ++{179, 97, 140}, ++{191, 90, 144}, ++{204, 83, 147}, ++{217, 76, 151}, ++{220, 74, 152}, ++{154, 117, 132}, ++{161, 112, 134}, ++{171, 105, 137}, ++{182, 98, 141}, ++{194, 91, 144}, ++{207, 84, 148}, ++{220, 77, 151}, ++{223, 75, 152}, ++{158, 118, 133}, ++{165, 113, 135}, ++{174, 106, 138}, ++{185, 99, 141}, ++{197, 92, 144}, ++{209, 84, 148}, ++{222, 77, 151}, ++{225, 76, 152}, ++{162, 118, 133}, ++{168, 113, 136}, ++{178, 107, 138}, ++{188, 100, 141}, ++{200, 92, 145}, ++{212, 85, 148}, ++{225, 78, 151}, ++{228, 77, 152}, ++{165, 119, 134}, ++{172, 114, 136}, ++{181, 107, 139}, ++{191, 100, 142}, ++{203, 93, 145}, ++{215, 86, 148}, ++{227, 79, 151}, ++{230, 77, 152}, ++{169, 119, 135}, ++{176, 114, 137}, ++{184, 108, 139}, ++{195, 101, 142}, ++{206, 94, 145}, ++{218, 87, 148}, ++{230, 80, 152}, ++{233, 78, 152}, ++{171, 119, 135}, ++{178, 115, 137}, ++{186, 108, 139}, ++{196, 101, 142}, ++{207, 94, 145}, ++{219, 87, 149}, ++{231, 80, 152}, ++{234, 79, 152}, ++{171, 119, 135}, ++{178, 115, 137}, ++{186, 108, 139}, ++{196, 101, 142}, ++{207, 94, 145}, ++{219, 87, 149}, ++{231, 80, 152}, ++{234, 79, 152}, ++{171, 119, 135}, ++{178, 115, 137}, ++{186, 108, 139}, ++{196, 101, 142}, ++{207, 94, 145}, ++{219, 87, 149}, ++{231, 80, 152}, ++{234, 79, 152}, ++{171, 119, 135}, ++{178, 115, 137}, ++{186, 108, 139}, ++{196, 101, 142}, ++{207, 94, 145}, ++{219, 87, 149}, ++{231, 80, 152}, ++{234, 79, 152}, ++{90, 98, 116}, ++{104, 94, 122}, ++{121, 88, 128}, ++{138, 81, 134}, ++{155, 75, 139}, ++{171, 69, 143}, ++{187, 63, 148}, ++{191, 61, 149}, ++{91, 98, 116}, ++{105, 94, 122}, ++{121, 88, 128}, ++{138, 81, 134}, ++{155, 75, 139}, ++{171, 69, 143}, ++{188, 63, 148}, ++{191, 61, 149}, ++{91, 99, 116}, ++{105, 94, 122}, ++{122, 88, 128}, ++{138, 82, 134}, ++{155, 75, 139}, ++{172, 69, 144}, ++{188, 63, 148}, ++{192, 62, 149}, ++{93, 100, 117}, ++{106, 95, 122}, ++{122, 88, 128}, ++{139, 82, 134}, ++{156, 76, 139}, ++{172, 69, 144}, ++{188, 63, 148}, ++{192, 62, 149}, ++{94, 100, 117}, ++{107, 95, 123}, ++{123, 89, 128}, ++{140, 82, 134}, ++{157, 76, 139}, ++{173, 70, 144}, ++{189, 64, 148}, ++{193, 62, 149}, ++{96, 101, 118}, ++{109, 96, 123}, ++{125, 90, 129}, ++{141, 83, 134}, ++{157, 76, 139}, ++{174, 70, 144}, ++{190, 64, 148}, ++{193, 62, 149}, ++{98, 102, 118}, ++{111, 97, 123}, ++{126, 90, 129}, ++{142, 84, 134}, ++{159, 77, 139}, ++{175, 71, 144}, ++{190, 64, 148}, ++{194, 63, 149}, ++{101, 103, 119}, ++{113, 98, 124}, ++{128, 91, 129}, ++{144, 84, 135}, ++{160, 77, 139}, ++{176, 71, 144}, ++{191, 65, 148}, ++{195, 63, 149}, ++{103, 104, 120}, ++{115, 99, 124}, ++{130, 92, 130}, ++{145, 85, 135}, ++{161, 78, 140}, ++{177, 72, 144}, ++{193, 65, 148}, ++{196, 64, 149}, ++{106, 105, 121}, ++{117, 99, 125}, ++{132, 93, 130}, ++{147, 86, 135}, ++{163, 79, 140}, ++{178, 72, 144}, ++{194, 66, 148}, ++{198, 64, 149}, ++{109, 106, 121}, ++{120, 100, 126}, ++{134, 93, 130}, ++{149, 86, 135}, ++{164, 80, 140}, ++{180, 73, 144}, ++{195, 66, 148}, ++{199, 65, 149}, ++{112, 107, 122}, ++{123, 101, 126}, ++{136, 94, 131}, ++{151, 87, 136}, ++{166, 80, 140}, ++{181, 74, 144}, ++{197, 67, 148}, ++{200, 65, 149}, ++{115, 108, 123}, ++{126, 102, 127}, ++{139, 95, 131}, ++{153, 88, 136}, ++{168, 81, 140}, ++{183, 74, 144}, ++{198, 68, 148}, ++{202, 66, 149}, ++{119, 109, 124}, ++{129, 103, 127}, ++{141, 96, 132}, ++{156, 89, 136}, ++{170, 82, 140}, ++{185, 75, 145}, ++{200, 68, 149}, ++{203, 67, 149}, ++{122, 110, 124}, ++{132, 104, 128}, ++{144, 97, 132}, ++{158, 90, 136}, ++{172, 83, 141}, ++{187, 76, 145}, ++{201, 69, 149}, ++{205, 68, 150}, ++{125, 111, 125}, ++{135, 105, 128}, ++{147, 98, 133}, ++{160, 91, 137}, ++{175, 83, 141}, ++{189, 77, 145}, ++{203, 70, 149}, ++{207, 68, 150}, ++{129, 112, 126}, ++{138, 106, 129}, ++{150, 99, 133}, ++{163, 92, 137}, ++{177, 84, 141}, ++{191, 77, 145}, ++{205, 71, 149}, ++{209, 69, 150}, ++{133, 113, 127}, ++{141, 107, 130}, ++{153, 100, 133}, ++{166, 92, 137}, ++{179, 85, 141}, ++{193, 78, 145}, ++{207, 71, 149}, ++{211, 70, 150}, ++{136, 113, 127}, ++{145, 108, 130}, ++{156, 101, 134}, ++{168, 93, 138}, ++{182, 86, 142}, ++{195, 79, 145}, ++{209, 72, 149}, ++{213, 71, 150}, ++{140, 114, 128}, ++{148, 108, 131}, ++{159, 101, 134}, ++{171, 94, 138}, ++{184, 87, 142}, ++{198, 80, 146}, ++{211, 73, 149}, ++{215, 71, 150}, ++{144, 115, 129}, ++{152, 109, 131}, ++{162, 102, 135}, ++{174, 95, 138}, ++{187, 88, 142}, ++{200, 81, 146}, ++{213, 74, 149}, ++{217, 72, 150}, ++{147, 115, 129}, ++{155, 110, 132}, ++{165, 103, 135}, ++{177, 96, 139}, ++{190, 89, 142}, ++{202, 81, 146}, ++{216, 75, 150}, ++{219, 73, 150}, ++{151, 116, 130}, ++{159, 111, 133}, ++{169, 104, 136}, ++{180, 97, 139}, ++{192, 89, 143}, ++{205, 82, 146}, ++{218, 75, 150}, ++{221, 74, 151}, ++{155, 116, 131}, ++{162, 111, 133}, ++{172, 105, 136}, ++{183, 97, 139}, ++{195, 90, 143}, ++{208, 83, 146}, ++{220, 76, 150}, ++{224, 75, 151}, ++{159, 117, 131}, ++{166, 112, 134}, ++{175, 105, 137}, ++{186, 98, 140}, ++{198, 91, 143}, ++{210, 84, 147}, ++{223, 77, 150}, ++{226, 75, 151}, ++{163, 117, 132}, ++{169, 112, 134}, ++{179, 106, 137}, ++{189, 99, 140}, ++{201, 92, 144}, ++{213, 85, 147}, ++{225, 78, 150}, ++{228, 76, 151}, ++{167, 118, 133}, ++{173, 113, 135}, ++{182, 107, 137}, ++{192, 100, 141}, ++{204, 93, 144}, ++{216, 86, 147}, ++{228, 79, 150}, ++{231, 77, 151}, ++{170, 118, 133}, ++{177, 114, 135}, ++{185, 107, 138}, ++{196, 100, 141}, ++{207, 93, 144}, ++{218, 86, 147}, ++{230, 79, 151}, ++{233, 78, 151}, ++{172, 119, 134}, ++{179, 114, 135}, ++{187, 108, 138}, ++{197, 101, 141}, ++{208, 94, 144}, ++{220, 87, 147}, ++{232, 80, 151}, ++{235, 78, 151}, ++{172, 119, 134}, ++{179, 114, 135}, ++{187, 108, 138}, ++{197, 101, 141}, ++{208, 94, 144}, ++{220, 87, 147}, ++{232, 80, 151}, ++{235, 78, 151}, ++{172, 119, 134}, ++{179, 114, 135}, ++{187, 108, 138}, ++{197, 101, 141}, ++{208, 94, 144}, ++{220, 87, 147}, ++{232, 80, 151}, ++{235, 78, 151}, ++{172, 119, 134}, ++{179, 114, 135}, ++{187, 108, 138}, ++{197, 101, 141}, ++{208, 94, 144}, ++{220, 87, 147}, ++{232, 80, 151}, ++{235, 78, 151}, ++{93, 96, 114}, ++{106, 92, 120}, ++{123, 87, 126}, ++{139, 81, 132}, ++{156, 74, 137}, ++{172, 68, 142}, ++{189, 62, 146}, ++{192, 61, 147}, ++{93, 96, 114}, ++{107, 92, 120}, ++{123, 87, 126}, ++{140, 81, 132}, ++{156, 74, 137}, ++{173, 68, 142}, ++{189, 62, 146}, ++{193, 61, 147}, ++{94, 97, 114}, ++{107, 93, 120}, ++{123, 87, 126}, ++{140, 81, 132}, ++{157, 75, 137}, ++{173, 69, 142}, ++{189, 63, 146}, ++{193, 61, 147}, ++{95, 98, 114}, ++{108, 93, 120}, ++{124, 87, 126}, ++{141, 81, 132}, ++{157, 75, 137}, ++{173, 69, 142}, ++{189, 63, 146}, ++{193, 61, 147}, ++{96, 98, 115}, ++{109, 94, 120}, ++{125, 88, 126}, ++{142, 82, 132}, ++{158, 75, 137}, ++{174, 69, 142}, ++{190, 63, 146}, ++{194, 62, 147}, ++{98, 99, 115}, ++{111, 94, 121}, ++{126, 88, 127}, ++{143, 82, 132}, ++{159, 76, 137}, ++{175, 69, 142}, ++{191, 63, 146}, ++{195, 62, 147}, ++{100, 100, 116}, ++{113, 95, 121}, ++{128, 89, 127}, ++{144, 83, 132}, ++{160, 76, 137}, ++{176, 70, 142}, ++{192, 64, 146}, ++{195, 62, 147}, ++{103, 101, 117}, ++{115, 96, 122}, ++{130, 90, 127}, ++{145, 83, 133}, ++{161, 77, 138}, ++{177, 70, 142}, ++{193, 64, 146}, ++{196, 63, 147}, ++{105, 102, 118}, ++{117, 97, 122}, ++{131, 91, 128}, ++{147, 84, 133}, ++{163, 77, 138}, ++{178, 71, 142}, ++{194, 65, 146}, ++{197, 63, 148}, ++{108, 104, 118}, ++{119, 98, 123}, ++{133, 92, 128}, ++{149, 85, 133}, ++{164, 78, 138}, ++{180, 72, 142}, ++{195, 65, 147}, ++{199, 64, 148}, ++{111, 105, 119}, ++{122, 99, 123}, ++{136, 92, 128}, ++{150, 86, 133}, ++{166, 79, 138}, ++{181, 72, 143}, ++{196, 66, 147}, ++{200, 64, 148}, ++{114, 106, 120}, ++{124, 100, 124}, ++{138, 93, 129}, ++{152, 86, 134}, ++{168, 80, 138}, ++{183, 73, 143}, ++{198, 67, 147}, ++{201, 65, 148}, ++{117, 107, 121}, ++{127, 101, 125}, ++{140, 94, 129}, ++{155, 87, 134}, ++{169, 80, 139}, ++{184, 74, 143}, ++{199, 67, 147}, ++{203, 66, 148}, ++{120, 108, 122}, ++{130, 102, 125}, ++{143, 95, 130}, ++{157, 88, 134}, ++{171, 81, 139}, ++{186, 74, 143}, ++{201, 68, 147}, ++{204, 66, 148}, ++{124, 109, 122}, ++{133, 103, 126}, ++{146, 96, 130}, ++{159, 89, 135}, ++{173, 82, 139}, ++{188, 75, 143}, ++{202, 69, 147}, ++{206, 67, 148}, ++{127, 110, 123}, ++{136, 104, 127}, ++{148, 97, 131}, ++{162, 90, 135}, ++{176, 83, 139}, ++{190, 76, 143}, ++{204, 69, 147}, ++{208, 68, 148}, ++{131, 110, 124}, ++{139, 105, 127}, ++{151, 98, 131}, ++{164, 91, 135}, ++{178, 84, 140}, ++{192, 77, 144}, ++{206, 70, 147}, ++{210, 69, 148}, ++{134, 111, 125}, ++{143, 106, 128}, ++{154, 99, 132}, ++{167, 92, 136}, ++{180, 85, 140}, ++{194, 78, 144}, ++{208, 71, 148}, ++{212, 69, 148}, ++{138, 112, 126}, ++{146, 106, 128}, ++{157, 100, 132}, ++{170, 93, 136}, ++{183, 85, 140}, ++{196, 78, 144}, ++{210, 72, 148}, ++{214, 70, 149}, ++{141, 113, 126}, ++{149, 107, 129}, ++{160, 101, 133}, ++{172, 93, 136}, ++{185, 86, 140}, ++{199, 79, 144}, ++{212, 72, 148}, ++{216, 71, 149}, ++{145, 113, 127}, ++{153, 108, 130}, ++{163, 101, 133}, ++{175, 94, 137}, ++{188, 87, 141}, ++{201, 80, 144}, ++{214, 73, 148}, ++{218, 72, 149}, ++{149, 114, 128}, ++{156, 109, 130}, ++{167, 102, 134}, ++{178, 95, 137}, ++{191, 88, 141}, ++{203, 81, 145}, ++{217, 74, 148}, ++{220, 72, 149}, ++{153, 115, 128}, ++{160, 110, 131}, ++{170, 103, 134}, ++{181, 96, 138}, ++{193, 89, 141}, ++{206, 82, 145}, ++{219, 75, 148}, ++{222, 73, 149}, ++{156, 115, 129}, ++{163, 110, 131}, ++{173, 104, 135}, ++{184, 97, 138}, ++{196, 90, 142}, ++{209, 83, 145}, ++{221, 76, 149}, ++{224, 74, 149}, ++{160, 116, 130}, ++{167, 111, 132}, ++{176, 104, 135}, ++{187, 97, 138}, ++{199, 90, 142}, ++{211, 83, 145}, ++{224, 77, 149}, ++{227, 75, 150}, ++{164, 116, 130}, ++{171, 111, 133}, ++{180, 105, 136}, ++{190, 98, 139}, ++{202, 91, 142}, ++{214, 84, 146}, ++{226, 77, 149}, ++{229, 76, 150}, ++{168, 117, 131}, ++{174, 112, 133}, ++{183, 106, 136}, ++{193, 99, 139}, ++{205, 92, 142}, ++{216, 85, 146}, ++{229, 78, 149}, ++{232, 77, 150}, ++{172, 117, 132}, ++{178, 113, 134}, ++{186, 107, 136}, ++{197, 100, 140}, ++{208, 93, 143}, ++{219, 86, 146}, ++{231, 79, 149}, ++{234, 77, 150}, ++{173, 118, 132}, ++{180, 113, 134}, ++{188, 107, 137}, ++{198, 100, 140}, ++{209, 93, 143}, ++{221, 86, 146}, ++{232, 79, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{180, 113, 134}, ++{188, 107, 137}, ++{198, 100, 140}, ++{209, 93, 143}, ++{221, 86, 146}, ++{232, 79, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{180, 113, 134}, ++{188, 107, 137}, ++{198, 100, 140}, ++{209, 93, 143}, ++{221, 86, 146}, ++{232, 79, 149}, ++{235, 78, 150}, ++{173, 118, 132}, ++{180, 113, 134}, ++{188, 107, 137}, ++{198, 100, 140}, ++{209, 93, 143}, ++{221, 86, 146}, ++{232, 79, 149}, ++{235, 78, 150}, ++{95, 94, 111}, ++{109, 90, 117}, ++{125, 85, 123}, ++{141, 79, 129}, ++{158, 74, 135}, ++{174, 68, 140}, ++{190, 62, 144}, ++{194, 60, 145}, ++{96, 94, 111}, ++{109, 91, 117}, ++{125, 85, 123}, ++{141, 80, 129}, ++{158, 74, 135}, ++{174, 68, 140}, ++{190, 62, 144}, ++{194, 60, 145}, ++{96, 95, 112}, ++{109, 91, 117}, ++{125, 86, 124}, ++{142, 80, 130}, ++{158, 74, 135}, ++{174, 68, 140}, ++{190, 62, 144}, ++{194, 61, 145}, ++{97, 95, 112}, ++{110, 91, 118}, ++{126, 86, 124}, ++{142, 80, 130}, ++{159, 74, 135}, ++{175, 68, 140}, ++{191, 62, 144}, ++{194, 61, 146}, ++{99, 96, 112}, ++{112, 92, 118}, ++{127, 87, 124}, ++{143, 81, 130}, ++{159, 74, 135}, ++{175, 68, 140}, ++{191, 63, 144}, ++{195, 61, 146}, ++{101, 97, 113}, ++{113, 93, 118}, ++{128, 87, 124}, ++{144, 81, 130}, ++{160, 75, 135}, ++{176, 69, 140}, ++{192, 63, 145}, ++{196, 61, 146}, ++{103, 98, 114}, ++{115, 94, 119}, ++{130, 88, 125}, ++{145, 82, 130}, ++{161, 75, 135}, ++{177, 69, 140}, ++{193, 63, 145}, ++{197, 62, 146}, ++{105, 99, 114}, ++{117, 95, 119}, ++{131, 89, 125}, ++{147, 82, 130}, ++{163, 76, 136}, ++{178, 70, 140}, ++{194, 64, 145}, ++{197, 62, 146}, ++{107, 100, 115}, ++{119, 96, 120}, ++{133, 89, 125}, ++{148, 83, 131}, ++{164, 77, 136}, ++{179, 70, 140}, ++{195, 64, 145}, ++{199, 63, 146}, ++{110, 102, 116}, ++{121, 97, 121}, ++{135, 90, 126}, ++{150, 84, 131}, ++{165, 77, 136}, ++{181, 71, 141}, ++{196, 65, 145}, ++{200, 63, 146}, ++{113, 103, 117}, ++{124, 98, 121}, ++{137, 91, 126}, ++{152, 85, 131}, ++{167, 78, 136}, ++{182, 72, 141}, ++{197, 65, 145}, ++{201, 64, 146}, ++{116, 104, 118}, ++{126, 99, 122}, ++{140, 92, 127}, ++{154, 85, 132}, ++{169, 79, 136}, ++{184, 72, 141}, ++{199, 66, 145}, ++{202, 64, 146}, ++{119, 105, 119}, ++{129, 100, 122}, ++{142, 93, 127}, ++{156, 86, 132}, ++{171, 80, 137}, ++{186, 73, 141}, ++{200, 67, 145}, ++{204, 65, 146}, ++{122, 106, 119}, ++{132, 101, 123}, ++{144, 94, 128}, ++{158, 87, 132}, ++{173, 80, 137}, ++{187, 74, 141}, ++{202, 67, 145}, ++{205, 66, 146}, ++{126, 107, 120}, ++{135, 102, 124}, ++{147, 95, 128}, ++{161, 88, 133}, ++{175, 81, 137}, ++{189, 75, 142}, ++{204, 68, 146}, ++{207, 67, 147}, ++{129, 108, 121}, ++{138, 103, 125}, ++{150, 96, 129}, ++{163, 89, 133}, ++{177, 82, 138}, ++{191, 75, 142}, ++{205, 69, 146}, ++{209, 67, 147}, ++{132, 109, 122}, ++{141, 103, 125}, ++{153, 97, 129}, ++{166, 90, 134}, ++{179, 83, 138}, ++{193, 76, 142}, ++{207, 70, 146}, ++{211, 68, 147}, ++{136, 110, 123}, ++{144, 104, 126}, ++{156, 98, 130}, ++{168, 91, 134}, ++{182, 84, 138}, ++{195, 77, 142}, ++{209, 70, 146}, ++{213, 69, 147}, ++{139, 111, 124}, ++{148, 105, 127}, ++{159, 99, 130}, ++{171, 92, 134}, ++{184, 85, 138}, ++{198, 78, 142}, ++{211, 71, 146}, ++{215, 70, 147}, ++{143, 111, 124}, ++{151, 106, 127}, ++{162, 100, 131}, ++{174, 93, 135}, ++{187, 85, 139}, ++{200, 79, 143}, ++{213, 72, 146}, ++{217, 70, 147}, ++{147, 112, 125}, ++{154, 107, 128}, ++{165, 100, 131}, ++{176, 93, 135}, ++{189, 86, 139}, ++{202, 79, 143}, ++{215, 73, 147}, ++{219, 71, 148}, ++{150, 113, 126}, ++{158, 108, 128}, ++{168, 101, 132}, ++{179, 94, 136}, ++{192, 87, 139}, ++{205, 80, 143}, ++{218, 74, 147}, ++{221, 72, 148}, ++{154, 113, 127}, ++{161, 108, 129}, ++{171, 102, 132}, ++{182, 95, 136}, ++{194, 88, 140}, ++{207, 81, 143}, ++{220, 74, 147}, ++{223, 73, 148}, ++{158, 114, 127}, ++{165, 109, 130}, ++{174, 103, 133}, ++{185, 96, 136}, ++{197, 89, 140}, ++{210, 82, 144}, ++{222, 75, 147}, ++{225, 74, 148}, ++{162, 115, 128}, ++{168, 110, 130}, ++{178, 104, 133}, ++{188, 97, 137}, ++{200, 90, 140}, ++{212, 83, 144}, ++{225, 76, 147}, ++{228, 74, 148}, ++{165, 115, 129}, ++{172, 110, 131}, ++{181, 104, 134}, ++{191, 97, 137}, ++{203, 91, 141}, ++{215, 84, 144}, ++{227, 77, 148}, ++{230, 75, 148}, ++{169, 116, 129}, ++{175, 111, 132}, ++{184, 105, 134}, ++{195, 98, 138}, ++{206, 91, 141}, ++{217, 84, 144}, ++{230, 78, 148}, ++{233, 76, 149}, ++{173, 116, 130}, ++{179, 112, 132}, ++{188, 106, 135}, ++{198, 99, 138}, ++{209, 92, 141}, ++{220, 85, 145}, ++{232, 78, 148}, ++{235, 77, 149}, ++{175, 117, 130}, ++{181, 112, 132}, ++{189, 106, 135}, ++{199, 99, 138}, ++{210, 93, 142}, ++{222, 86, 145}, ++{233, 79, 148}, ++{236, 77, 149}, ++{175, 117, 130}, ++{181, 112, 132}, ++{189, 106, 135}, ++{199, 99, 138}, ++{210, 93, 142}, ++{222, 86, 145}, ++{233, 79, 148}, ++{236, 77, 149}, ++{175, 117, 130}, ++{181, 112, 132}, ++{189, 106, 135}, ++{199, 99, 138}, ++{210, 93, 142}, ++{222, 86, 145}, ++{233, 79, 148}, ++{236, 77, 149}, ++{175, 117, 130}, ++{181, 112, 132}, ++{189, 106, 135}, ++{199, 99, 138}, ++{210, 93, 142}, ++{222, 86, 145}, ++{233, 79, 148}, ++{236, 77, 149}, ++{98, 92, 109}, ++{111, 89, 115}, ++{127, 84, 121}, ++{143, 78, 127}, ++{159, 73, 133}, ++{175, 67, 138}, ++{191, 61, 143}, ++{195, 60, 144}, ++{98, 92, 109}, ++{111, 89, 115}, ++{127, 84, 121}, ++{143, 78, 127}, ++{159, 73, 133}, ++{175, 67, 138}, ++{191, 61, 143}, ++{195, 60, 144}, ++{99, 92, 109}, ++{112, 89, 115}, ++{127, 84, 121}, ++{143, 79, 127}, ++{160, 73, 133}, ++{176, 67, 138}, ++{191, 61, 143}, ++{195, 60, 144}, ++{100, 93, 110}, ++{113, 90, 115}, ++{128, 85, 121}, ++{144, 79, 127}, ++{160, 73, 133}, ++{176, 67, 138}, ++{192, 62, 143}, ++{196, 60, 144}, ++{101, 94, 110}, ++{114, 90, 116}, ++{129, 85, 122}, ++{145, 79, 128}, ++{161, 74, 133}, ++{177, 68, 138}, ++{192, 62, 143}, ++{196, 60, 144}, ++{103, 95, 111}, ++{115, 91, 116}, ++{130, 86, 122}, ++{146, 80, 128}, ++{162, 74, 133}, ++{178, 68, 138}, ++{193, 62, 143}, ++{197, 61, 144}, ++{105, 96, 111}, ++{117, 92, 116}, ++{132, 86, 122}, ++{147, 81, 128}, ++{163, 75, 133}, ++{179, 69, 138}, ++{194, 63, 143}, ++{198, 61, 144}, ++{107, 97, 112}, ++{119, 93, 117}, ++{133, 87, 123}, ++{149, 81, 128}, ++{164, 75, 134}, ++{180, 69, 138}, ++{195, 63, 143}, ++{199, 62, 144}, ++{110, 98, 113}, ++{121, 94, 118}, ++{135, 88, 123}, ++{150, 82, 129}, ++{165, 76, 134}, ++{181, 70, 139}, ++{196, 64, 143}, ++{200, 62, 144}, ++{112, 100, 114}, ++{123, 95, 118}, ++{137, 89, 124}, ++{152, 83, 129}, ++{167, 76, 134}, ++{182, 70, 139}, ++{197, 64, 143}, ++{201, 63, 144}, ++{115, 101, 115}, ++{126, 96, 119}, ++{139, 90, 124}, ++{154, 84, 129}, ++{169, 77, 134}, ++{184, 71, 139}, ++{199, 65, 143}, ++{202, 63, 144}, ++{118, 102, 115}, ++{128, 97, 120}, ++{141, 91, 125}, ++{156, 84, 130}, ++{170, 78, 134}, ++{185, 72, 139}, ++{200, 65, 143}, ++{204, 64, 144}, ++{121, 103, 116}, ++{131, 98, 120}, ++{144, 92, 125}, ++{158, 85, 130}, ++{172, 79, 135}, ++{187, 72, 139}, ++{201, 66, 144}, ++{205, 65, 145}, ++{124, 104, 117}, ++{134, 99, 121}, ++{146, 93, 126}, ++{160, 86, 130}, ++{174, 80, 135}, ++{189, 73, 139}, ++{203, 67, 144}, ++{207, 65, 145}, ++{128, 105, 118}, ++{137, 100, 122}, ++{149, 94, 126}, ++{162, 87, 131}, ++{176, 80, 135}, ++{190, 74, 140}, ++{205, 67, 144}, ++{208, 66, 145}, ++{131, 106, 119}, ++{140, 101, 122}, ++{151, 95, 127}, ++{165, 88, 131}, ++{178, 81, 136}, ++{192, 75, 140}, ++{206, 68, 144}, ++{210, 67, 145}, ++{134, 107, 120}, ++{143, 102, 123}, ++{154, 96, 127}, ++{167, 89, 132}, ++{181, 82, 136}, ++{194, 75, 140}, ++{208, 69, 144}, ++{212, 67, 145}, ++{138, 108, 121}, ++{146, 103, 124}, ++{157, 97, 128}, ++{170, 90, 132}, ++{183, 83, 136}, ++{197, 76, 140}, ++{210, 70, 144}, ++{214, 68, 145}, ++{141, 109, 122}, ++{149, 104, 125}, ++{160, 98, 128}, ++{172, 91, 132}, ++{185, 84, 137}, ++{199, 77, 141}, ++{212, 71, 145}, ++{216, 69, 146}, ++{145, 110, 122}, ++{153, 105, 125}, ++{163, 98, 129}, ++{175, 92, 133}, ++{188, 85, 137}, ++{201, 78, 141}, ++{214, 71, 145}, ++{218, 70, 146}, ++{148, 111, 123}, ++{156, 106, 126}, ++{166, 99, 129}, ++{178, 92, 133}, ++{190, 86, 137}, ++{203, 79, 141}, ++{216, 72, 145}, ++{220, 71, 146}, ++{152, 111, 124}, ++{159, 106, 127}, ++{169, 100, 130}, ++{181, 93, 134}, ++{193, 86, 138}, ++{206, 80, 142}, ++{219, 73, 145}, ++{222, 71, 146}, ++{156, 112, 125}, ++{163, 107, 127}, ++{172, 101, 131}, ++{184, 94, 134}, ++{196, 87, 138}, ++{208, 80, 142}, ++{221, 74, 145}, ++{224, 72, 146}, ++{159, 113, 126}, ++{166, 108, 128}, ++{176, 102, 131}, ++{187, 95, 135}, ++{198, 88, 138}, ++{211, 81, 142}, ++{223, 75, 146}, ++{226, 73, 147}, ++{163, 113, 126}, ++{170, 109, 129}, ++{179, 103, 132}, ++{190, 96, 135}, ++{201, 89, 139}, ++{213, 82, 142}, ++{226, 75, 146}, ++{229, 74, 147}, ++{167, 114, 127}, ++{173, 109, 129}, ++{182, 103, 132}, ++{193, 97, 136}, ++{204, 90, 139}, ++{216, 83, 143}, ++{228, 76, 146}, ++{231, 75, 147}, ++{170, 115, 128}, ++{177, 110, 130}, ++{186, 104, 133}, ++{196, 97, 136}, ++{207, 91, 139}, ++{219, 84, 143}, ++{231, 77, 146}, ++{234, 75, 147}, ++{174, 115, 128}, ++{180, 111, 131}, ++{189, 105, 133}, ++{199, 98, 136}, ++{210, 91, 140}, ++{221, 85, 143}, ++{233, 78, 147}, ++{236, 76, 147}, ++{176, 115, 129}, ++{182, 111, 131}, ++{191, 105, 134}, ++{200, 99, 137}, ++{211, 92, 140}, ++{223, 85, 143}, ++{234, 78, 147}, ++{237, 77, 148}, ++{176, 115, 129}, ++{182, 111, 131}, ++{191, 105, 134}, ++{200, 99, 137}, ++{211, 92, 140}, ++{223, 85, 143}, ++{234, 78, 147}, ++{237, 77, 148}, ++{176, 115, 129}, ++{182, 111, 131}, ++{191, 105, 134}, ++{200, 99, 137}, ++{211, 92, 140}, ++{223, 85, 143}, ++{234, 78, 147}, ++{237, 77, 148}, ++{176, 115, 129}, ++{182, 111, 131}, ++{191, 105, 134}, ++{200, 99, 137}, ++{211, 92, 140}, ++{223, 85, 143}, ++{234, 78, 147}, ++{237, 77, 148}, ++{101, 89, 106}, ++{113, 87, 112}, ++{129, 82, 119}, ++{145, 77, 125}, ++{161, 72, 131}, ++{177, 66, 136}, ++{192, 61, 141}, ++{196, 59, 142}, ++{101, 90, 106}, ++{114, 87, 112}, ++{129, 82, 119}, ++{145, 77, 125}, ++{161, 72, 131}, ++{177, 66, 136}, ++{192, 61, 141}, ++{196, 59, 142}, ++{102, 90, 107}, ++{114, 87, 112}, ++{129, 83, 119}, ++{145, 77, 125}, ++{161, 72, 131}, ++{177, 66, 136}, ++{193, 61, 141}, ++{197, 59, 142}, ++{103, 91, 107}, ++{115, 88, 113}, ++{130, 83, 119}, ++{146, 78, 125}, ++{162, 72, 131}, ++{178, 67, 136}, ++{193, 61, 141}, ++{197, 60, 142}, ++{104, 92, 108}, ++{116, 88, 113}, ++{131, 84, 119}, ++{147, 78, 125}, ++{163, 73, 131}, ++{178, 67, 136}, ++{194, 61, 141}, ++{198, 60, 142}, ++{106, 93, 108}, ++{118, 89, 114}, ++{132, 84, 120}, ++{148, 79, 126}, ++{163, 73, 131}, ++{179, 67, 136}, ++{194, 62, 141}, ++{198, 60, 142}, ++{108, 94, 109}, ++{119, 90, 114}, ++{134, 85, 120}, ++{149, 79, 126}, ++{165, 74, 131}, ++{180, 68, 136}, ++{195, 62, 141}, ++{199, 61, 142}, ++{110, 95, 110}, ++{121, 91, 115}, ++{135, 86, 120}, ++{150, 80, 126}, ++{166, 74, 131}, ++{181, 68, 136}, ++{196, 62, 141}, ++{200, 61, 142}, ++{112, 96, 111}, ++{123, 92, 115}, ++{137, 87, 121}, ++{152, 81, 126}, ++{167, 75, 132}, ++{182, 69, 137}, ++{197, 63, 141}, ++{201, 61, 142}, ++{115, 97, 111}, ++{125, 93, 116}, ++{139, 88, 121}, ++{154, 82, 127}, ++{169, 75, 132}, ++{184, 69, 137}, ++{199, 63, 141}, ++{202, 62, 142}, ++{117, 99, 112}, ++{128, 94, 117}, ++{141, 88, 122}, ++{155, 82, 127}, ++{170, 76, 132}, ++{185, 70, 137}, ++{200, 64, 141}, ++{203, 63, 143}, ++{120, 100, 113}, ++{130, 95, 117}, ++{143, 89, 122}, ++{157, 83, 127}, ++{172, 77, 132}, ++{187, 71, 137}, ++{201, 65, 142}, ++{205, 63, 143}, ++{123, 101, 114}, ++{133, 96, 118}, ++{146, 90, 123}, ++{159, 84, 128}, ++{174, 78, 133}, ++{188, 71, 137}, ++{203, 65, 142}, ++{206, 64, 143}, ++{126, 102, 115}, ++{136, 97, 119}, ++{148, 91, 123}, ++{162, 85, 128}, ++{176, 79, 133}, ++{190, 72, 138}, ++{204, 66, 142}, ++{208, 65, 143}, ++{130, 103, 116}, ++{139, 99, 120}, ++{151, 92, 124}, ++{164, 86, 129}, ++{178, 79, 133}, ++{192, 73, 138}, ++{206, 67, 142}, ++{209, 65, 143}, ++{133, 104, 117}, ++{142, 100, 120}, ++{153, 93, 125}, ++{166, 87, 129}, ++{180, 80, 134}, ++{194, 74, 138}, ++{208, 68, 142}, ++{211, 66, 143}, ++{136, 105, 118}, ++{145, 101, 121}, ++{156, 94, 125}, ++{169, 88, 130}, ++{182, 81, 134}, ++{196, 75, 138}, ++{210, 68, 143}, ++{213, 67, 144}, ++{140, 106, 119}, ++{148, 102, 122}, ++{159, 95, 126}, ++{171, 89, 130}, ++{184, 82, 134}, ++{198, 75, 139}, ++{211, 69, 143}, ++{215, 68, 144}, ++{143, 107, 119}, ++{151, 102, 122}, ++{162, 96, 126}, ++{174, 90, 131}, ++{187, 83, 135}, ++{200, 76, 139}, ++{213, 70, 143}, ++{217, 68, 144}, ++{147, 108, 120}, ++{154, 103, 123}, ++{165, 97, 127}, ++{177, 91, 131}, ++{189, 84, 135}, ++{202, 77, 139}, ++{216, 71, 143}, ++{219, 69, 144}, ++{150, 109, 121}, ++{158, 104, 124}, ++{168, 98, 128}, ++{179, 91, 132}, ++{192, 85, 136}, ++{205, 78, 140}, ++{218, 71, 143}, ++{221, 70, 144}, ++{154, 110, 122}, ++{161, 105, 125}, ++{171, 99, 128}, ++{182, 92, 132}, ++{194, 86, 136}, ++{207, 79, 140}, ++{220, 72, 144}, ++{223, 71, 145}, ++{157, 111, 123}, ++{164, 106, 125}, ++{174, 100, 129}, ++{185, 93, 132}, ++{197, 86, 136}, ++{209, 80, 140}, ++{222, 73, 144}, ++{225, 72, 145}, ++{161, 111, 124}, ++{168, 107, 126}, ++{177, 101, 129}, ++{188, 94, 133}, ++{200, 87, 137}, ++{212, 81, 140}, ++{224, 74, 144}, ++{228, 72, 145}, ++{165, 112, 124}, ++{171, 107, 127}, ++{180, 101, 130}, ++{191, 95, 133}, ++{202, 88, 137}, ++{214, 81, 141}, ++{227, 75, 144}, ++{230, 73, 145}, ++{168, 113, 125}, ++{175, 108, 127}, ++{184, 102, 130}, ++{194, 96, 134}, ++{205, 89, 137}, ++{217, 82, 141}, ++{229, 76, 145}, ++{232, 74, 146}, ++{172, 113, 126}, ++{178, 109, 128}, ++{187, 103, 131}, ++{197, 96, 134}, ++{208, 90, 138}, ++{220, 83, 141}, ++{232, 76, 145}, ++{235, 75, 146}, ++{176, 114, 127}, ++{182, 109, 129}, ++{190, 104, 132}, ++{200, 97, 135}, ++{211, 91, 138}, ++{222, 84, 142}, ++{234, 77, 145}, ++{237, 76, 146}, ++{178, 114, 127}, ++{184, 110, 129}, ++{192, 104, 132}, ++{202, 98, 135}, ++{212, 91, 138}, ++{224, 84, 142}, ++{235, 78, 145}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 110, 129}, ++{192, 104, 132}, ++{202, 98, 135}, ++{212, 91, 138}, ++{224, 84, 142}, ++{235, 78, 145}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 110, 129}, ++{192, 104, 132}, ++{202, 98, 135}, ++{212, 91, 138}, ++{224, 84, 142}, ++{235, 78, 145}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 110, 129}, ++{192, 104, 132}, ++{202, 98, 135}, ++{212, 91, 138}, ++{224, 84, 142}, ++{235, 78, 145}, ++{238, 76, 146}, ++{103, 87, 104}, ++{116, 85, 110}, ++{131, 81, 116}, ++{147, 76, 123}, ++{163, 71, 128}, ++{178, 65, 134}, ++{194, 60, 139}, ++{198, 58, 140}, ++{104, 87, 104}, ++{116, 85, 110}, ++{131, 81, 116}, ++{147, 76, 123}, ++{163, 71, 128}, ++{178, 65, 134}, ++{194, 60, 139}, ++{198, 58, 140}, ++{104, 88, 104}, ++{117, 85, 110}, ++{131, 81, 116}, ++{147, 76, 123}, ++{163, 71, 128}, ++{179, 65, 134}, ++{194, 60, 139}, ++{198, 59, 140}, ++{105, 88, 105}, ++{117, 86, 110}, ++{132, 81, 117}, ++{148, 77, 123}, ++{164, 71, 129}, ++{179, 66, 134}, ++{195, 60, 139}, ++{198, 59, 140}, ++{107, 89, 105}, ++{119, 86, 111}, ++{133, 82, 117}, ++{149, 77, 123}, ++{164, 72, 129}, ++{180, 66, 134}, ++{195, 60, 139}, ++{199, 59, 140}, ++{108, 90, 106}, ++{120, 87, 111}, ++{134, 83, 117}, ++{150, 77, 123}, ++{165, 72, 129}, ++{181, 66, 134}, ++{196, 61, 139}, ++{200, 59, 140}, ++{110, 91, 107}, ++{122, 88, 112}, ++{136, 83, 118}, ++{151, 78, 124}, ++{166, 73, 129}, ++{182, 67, 134}, ++{197, 61, 139}, ++{200, 60, 140}, ++{112, 93, 107}, ++{123, 89, 112}, ++{137, 84, 118}, ++{152, 79, 124}, ++{167, 73, 129}, ++{183, 67, 134}, ++{198, 62, 139}, ++{201, 60, 140}, ++{115, 94, 108}, ++{125, 90, 113}, ++{139, 85, 119}, ++{154, 80, 124}, ++{169, 74, 130}, ++{184, 68, 135}, ++{199, 62, 139}, ++{202, 61, 140}, ++{117, 95, 109}, ++{128, 91, 114}, ++{141, 86, 119}, ++{155, 80, 125}, ++{170, 74, 130}, ++{185, 69, 135}, ++{200, 63, 139}, ++{204, 61, 141}, ++{120, 97, 110}, ++{130, 92, 114}, ++{143, 87, 120}, ++{157, 81, 125}, ++{172, 75, 130}, ++{186, 69, 135}, ++{201, 63, 140}, ++{205, 62, 141}, ++{123, 98, 111}, ++{132, 93, 115}, ++{145, 88, 120}, ++{159, 82, 125}, ++{173, 76, 130}, ++{188, 70, 135}, ++{203, 64, 140}, ++{206, 63, 141}, ++{126, 99, 112}, ++{135, 95, 116}, ++{147, 89, 121}, ++{161, 83, 126}, ++{175, 77, 131}, ++{190, 71, 135}, ++{204, 65, 140}, ++{208, 63, 141}, ++{129, 100, 113}, ++{138, 96, 117}, ++{150, 90, 121}, ++{163, 84, 126}, ++{177, 78, 131}, ++{191, 71, 136}, ++{206, 65, 140}, ++{209, 64, 141}, ++{132, 101, 114}, ++{141, 97, 117}, ++{152, 91, 122}, ++{165, 85, 127}, ++{179, 78, 131}, ++{193, 72, 136}, ++{207, 66, 140}, ++{211, 65, 141}, ++{135, 103, 115}, ++{144, 98, 118}, ++{155, 92, 122}, ++{168, 86, 127}, ++{181, 79, 132}, ++{195, 73, 136}, ++{209, 67, 141}, ++{212, 65, 142}, ++{138, 104, 116}, ++{147, 99, 119}, ++{158, 93, 123}, ++{170, 87, 128}, ++{184, 80, 132}, ++{197, 74, 137}, ++{211, 68, 141}, ++{214, 66, 142}, ++{142, 105, 116}, ++{150, 100, 120}, ++{161, 94, 124}, ++{173, 88, 128}, ++{186, 81, 133}, ++{199, 75, 137}, ++{213, 68, 141}, ++{216, 67, 142}, ++{145, 106, 117}, ++{153, 101, 120}, ++{163, 95, 124}, ++{175, 89, 129}, ++{188, 82, 133}, ++{201, 75, 137}, ++{215, 69, 141}, ++{218, 68, 142}, ++{148, 107, 118}, ++{156, 102, 121}, ++{166, 96, 125}, ++{178, 89, 129}, ++{191, 83, 133}, ++{204, 76, 137}, ++{217, 70, 141}, ++{220, 68, 142}, ++{152, 107, 119}, ++{159, 103, 122}, ++{169, 97, 126}, ++{181, 90, 130}, ++{193, 84, 134}, ++{206, 77, 138}, ++{219, 71, 142}, ++{222, 69, 143}, ++{155, 108, 120}, ++{163, 104, 123}, ++{172, 98, 126}, ++{184, 91, 130}, ++{196, 85, 134}, ++{208, 78, 138}, ++{221, 72, 142}, ++{224, 70, 143}, ++{159, 109, 121}, ++{166, 105, 123}, ++{175, 99, 127}, ++{186, 92, 131}, ++{198, 86, 135}, ++{211, 79, 138}, ++{223, 72, 142}, ++{226, 71, 143}, ++{163, 110, 122}, ++{169, 105, 124}, ++{179, 99, 127}, ++{189, 93, 131}, ++{201, 86, 135}, ++{213, 80, 139}, ++{226, 73, 143}, ++{229, 72, 143}, ++{166, 111, 122}, ++{173, 106, 125}, ++{182, 100, 128}, ++{192, 94, 132}, ++{204, 87, 135}, ++{216, 81, 139}, ++{228, 74, 143}, ++{231, 73, 144}, ++{170, 111, 123}, ++{176, 107, 126}, ++{185, 101, 129}, ++{195, 95, 132}, ++{206, 88, 136}, ++{218, 81, 139}, ++{230, 75, 143}, ++{233, 73, 144}, ++{173, 112, 124}, ++{180, 108, 126}, ++{188, 102, 129}, ++{198, 96, 133}, ++{209, 89, 136}, ++{221, 82, 140}, ++{233, 76, 143}, ++{236, 74, 144}, ++{177, 113, 125}, ++{183, 108, 127}, ++{192, 103, 130}, ++{201, 96, 133}, ++{212, 90, 137}, ++{224, 83, 140}, ++{235, 77, 144}, ++{238, 75, 144}, ++{179, 113, 125}, ++{185, 109, 127}, ++{193, 103, 130}, ++{203, 97, 133}, ++{214, 90, 137}, ++{225, 84, 140}, ++{237, 77, 144}, ++{239, 75, 145}, ++{179, 113, 125}, ++{185, 109, 127}, ++{193, 103, 130}, ++{203, 97, 133}, ++{214, 90, 137}, ++{225, 84, 140}, ++{237, 77, 144}, ++{239, 75, 145}, ++{179, 113, 125}, ++{185, 109, 127}, ++{193, 103, 130}, ++{203, 97, 133}, ++{214, 90, 137}, ++{225, 84, 140}, ++{237, 77, 144}, ++{239, 75, 145}, ++{179, 113, 125}, ++{185, 109, 127}, ++{193, 103, 130}, ++{203, 97, 133}, ++{214, 90, 137}, ++{225, 84, 140}, ++{237, 77, 144}, ++{239, 75, 145}, ++{106, 84, 102}, ++{118, 82, 107}, ++{133, 79, 114}, ++{149, 75, 120}, ++{164, 70, 126}, ++{180, 64, 132}, ++{195, 59, 137}, ++{199, 58, 138}, ++{107, 85, 102}, ++{119, 83, 107}, ++{133, 79, 114}, ++{149, 75, 120}, ++{164, 70, 126}, ++{180, 64, 132}, ++{195, 59, 137}, ++{199, 58, 138}, ++{107, 85, 102}, ++{119, 83, 108}, ++{134, 79, 114}, ++{149, 75, 120}, ++{165, 70, 126}, ++{180, 65, 132}, ++{196, 59, 137}, ++{199, 58, 138}, ++{108, 86, 102}, ++{120, 84, 108}, ++{134, 80, 114}, ++{150, 75, 121}, ++{165, 70, 126}, ++{181, 65, 132}, ++{196, 59, 137}, ++{200, 58, 138}, ++{109, 87, 103}, ++{121, 84, 108}, ++{135, 80, 115}, ++{151, 76, 121}, ++{166, 70, 126}, ++{181, 65, 132}, ++{197, 60, 137}, ++{200, 58, 138}, ++{111, 88, 103}, ++{122, 85, 109}, ++{136, 81, 115}, ++{152, 76, 121}, ++{167, 71, 127}, ++{182, 65, 132}, ++{197, 60, 137}, ++{201, 59, 138}, ++{113, 89, 104}, ++{124, 86, 109}, ++{138, 82, 115}, ++{153, 77, 121}, ++{168, 71, 127}, ++{183, 66, 132}, ++{198, 60, 137}, ++{202, 59, 138}, ++{115, 90, 105}, ++{126, 87, 110}, ++{139, 83, 116}, ++{154, 77, 122}, ++{169, 72, 127}, ++{184, 66, 132}, ++{199, 61, 137}, ++{203, 60, 138}, ++{117, 92, 106}, ++{128, 88, 111}, ++{141, 83, 116}, ++{156, 78, 122}, ++{170, 73, 127}, ++{185, 67, 133}, ++{200, 61, 137}, ++{204, 60, 138}, ++{120, 93, 107}, ++{130, 89, 111}, ++{143, 84, 117}, ++{157, 79, 122}, ++{172, 73, 128}, ++{187, 68, 133}, ++{201, 62, 137}, ++{205, 61, 139}, ++{122, 94, 108}, ++{132, 90, 112}, ++{145, 85, 117}, ++{159, 80, 123}, ++{173, 74, 128}, ++{188, 68, 133}, ++{203, 63, 138}, ++{206, 61, 139}, ++{125, 96, 109}, ++{135, 92, 113}, ++{147, 86, 118}, ++{161, 81, 123}, ++{175, 75, 128}, ++{190, 69, 133}, ++{204, 63, 138}, ++{208, 62, 139}, ++{128, 97, 109}, ++{137, 93, 113}, ++{149, 87, 118}, ++{163, 82, 124}, ++{177, 76, 129}, ++{191, 70, 133}, ++{205, 64, 138}, ++{209, 62, 139}, ++{131, 98, 110}, ++{140, 94, 114}, ++{152, 88, 119}, ++{165, 83, 124}, ++{179, 77, 129}, ++{193, 71, 134}, ++{207, 65, 138}, ++{210, 63, 139}, ++{134, 99, 111}, ++{143, 95, 115}, ++{154, 90, 120}, ++{167, 84, 125}, ++{181, 77, 129}, ++{195, 71, 134}, ++{209, 65, 138}, ++{212, 64, 140}, ++{137, 101, 112}, ++{146, 96, 116}, ++{157, 91, 120}, ++{169, 84, 125}, ++{183, 78, 130}, ++{197, 72, 134}, ++{210, 66, 139}, ++{214, 65, 140}, ++{140, 102, 113}, ++{149, 97, 117}, ++{160, 92, 121}, ++{172, 85, 126}, ++{185, 79, 130}, ++{199, 73, 135}, ++{212, 67, 139}, ++{216, 65, 140}, ++{144, 103, 114}, ++{152, 98, 117}, ++{162, 93, 122}, ++{174, 86, 126}, ++{187, 80, 131}, ++{201, 74, 135}, ++{214, 68, 139}, ++{217, 66, 140}, ++{147, 104, 115}, ++{155, 99, 118}, ++{165, 94, 122}, ++{177, 87, 127}, ++{190, 81, 131}, ++{203, 75, 135}, ++{216, 68, 139}, ++{219, 67, 140}, ++{150, 105, 116}, ++{158, 100, 119}, ++{168, 95, 123}, ++{180, 88, 127}, ++{192, 82, 131}, ++{205, 75, 136}, ++{218, 69, 140}, ++{221, 68, 141}, ++{154, 106, 117}, ++{161, 101, 120}, ++{171, 96, 124}, ++{182, 89, 128}, ++{195, 83, 132}, ++{207, 76, 136}, ++{220, 70, 140}, ++{223, 68, 141}, ++{157, 107, 118}, ++{164, 102, 121}, ++{174, 96, 124}, ++{185, 90, 128}, ++{197, 84, 132}, ++{210, 77, 136}, ++{222, 71, 140}, ++{225, 69, 141}, ++{161, 108, 119}, ++{168, 103, 121}, ++{177, 97, 125}, ++{188, 91, 129}, ++{200, 85, 133}, ++{212, 78, 137}, ++{224, 72, 141}, ++{228, 70, 142}, ++{164, 108, 120}, ++{171, 104, 122}, ++{180, 98, 126}, ++{191, 92, 129}, ++{202, 85, 133}, ++{214, 79, 137}, ++{227, 73, 141}, ++{230, 71, 142}, ++{168, 109, 121}, ++{174, 105, 123}, ++{183, 99, 126}, ++{194, 93, 130}, ++{205, 86, 134}, ++{217, 80, 137}, ++{229, 73, 141}, ++{232, 72, 142}, ++{171, 110, 121}, ++{178, 106, 124}, ++{187, 100, 127}, ++{197, 94, 130}, ++{208, 87, 134}, ++{219, 81, 138}, ++{231, 74, 141}, ++{235, 73, 142}, ++{175, 111, 122}, ++{181, 106, 124}, ++{190, 101, 127}, ++{200, 94, 131}, ++{211, 88, 134}, ++{222, 81, 138}, ++{234, 75, 142}, ++{237, 73, 143}, ++{179, 111, 123}, ++{185, 107, 125}, ++{193, 101, 128}, ++{203, 95, 131}, ++{213, 89, 135}, ++{225, 82, 138}, ++{236, 76, 142}, ++{239, 74, 143}, ++{181, 112, 123}, ++{186, 107, 126}, ++{195, 102, 128}, ++{204, 96, 132}, ++{215, 89, 135}, ++{226, 83, 139}, ++{238, 76, 142}, ++{241, 75, 143}, ++{181, 112, 123}, ++{186, 107, 126}, ++{195, 102, 128}, ++{204, 96, 132}, ++{215, 89, 135}, ++{226, 83, 139}, ++{238, 76, 142}, ++{241, 75, 143}, ++{181, 112, 123}, ++{186, 107, 126}, ++{195, 102, 128}, ++{204, 96, 132}, ++{215, 89, 135}, ++{226, 83, 139}, ++{238, 76, 142}, ++{241, 75, 143}, ++{181, 112, 123}, ++{186, 107, 126}, ++{195, 102, 128}, ++{204, 96, 132}, ++{215, 89, 135}, ++{226, 83, 139}, ++{238, 76, 142}, ++{241, 75, 143}, ++{109, 82, 99}, ++{121, 80, 105}, ++{135, 77, 112}, ++{151, 73, 118}, ++{166, 68, 124}, ++{182, 63, 129}, ++{197, 58, 135}, ++{201, 57, 136}, ++{109, 82, 99}, ++{121, 80, 105}, ++{135, 77, 112}, ++{151, 73, 118}, ++{166, 68, 124}, ++{182, 63, 129}, ++{197, 58, 135}, ++{201, 57, 136}, ++{110, 83, 100}, ++{122, 81, 105}, ++{136, 78, 112}, ++{151, 73, 118}, ++{167, 69, 124}, ++{182, 64, 130}, ++{197, 58, 135}, ++{201, 57, 136}, ++{111, 83, 100}, ++{122, 81, 106}, ++{137, 78, 112}, ++{152, 74, 118}, ++{167, 69, 124}, ++{182, 64, 130}, ++{198, 59, 135}, ++{201, 57, 136}, ++{112, 84, 101}, ++{123, 82, 106}, ++{138, 79, 112}, ++{153, 74, 118}, ++{168, 69, 124}, ++{183, 64, 130}, ++{198, 59, 135}, ++{202, 58, 136}, ++{114, 85, 101}, ++{125, 83, 106}, ++{139, 79, 113}, ++{154, 75, 119}, ++{169, 70, 124}, ++{184, 64, 130}, ++{199, 59, 135}, ++{203, 58, 136}, ++{116, 87, 102}, ++{126, 84, 107}, ++{140, 80, 113}, ++{155, 75, 119}, ++{170, 70, 125}, ++{185, 65, 130}, ++{200, 60, 135}, ++{203, 58, 136}, ++{118, 88, 103}, ++{128, 85, 108}, ++{141, 81, 113}, ++{156, 76, 119}, ++{171, 71, 125}, ++{186, 65, 130}, ++{201, 60, 135}, ++{204, 59, 136}, ++{120, 89, 103}, ++{130, 86, 108}, ++{143, 82, 114}, ++{157, 77, 120}, ++{172, 71, 125}, ++{187, 66, 130}, ++{202, 61, 135}, ++{205, 59, 136}, ++{122, 91, 104}, ++{132, 87, 109}, ++{145, 83, 114}, ++{159, 78, 120}, ++{174, 72, 126}, ++{188, 67, 131}, ++{203, 61, 135}, ++{206, 60, 137}, ++{125, 92, 105}, ++{134, 88, 110}, ++{147, 84, 115}, ++{161, 78, 121}, ++{175, 73, 126}, ++{190, 67, 131}, ++{204, 62, 136}, ++{208, 60, 137}, ++{127, 93, 106}, ++{137, 90, 110}, ++{149, 85, 116}, ++{163, 79, 121}, ++{177, 74, 126}, ++{191, 68, 131}, ++{205, 62, 136}, ++{209, 61, 137}, ++{130, 95, 107}, ++{139, 91, 111}, ++{151, 86, 116}, ++{165, 80, 121}, ++{179, 75, 127}, ++{193, 69, 131}, ++{207, 63, 136}, ++{210, 62, 137}, ++{133, 96, 108}, ++{142, 92, 112}, ++{154, 87, 117}, ++{167, 81, 122}, ++{180, 75, 127}, ++{194, 70, 132}, ++{208, 64, 136}, ++{212, 62, 137}, ++{136, 97, 109}, ++{145, 93, 113}, ++{156, 88, 118}, ++{169, 82, 122}, ++{182, 76, 127}, ++{196, 70, 132}, ++{210, 64, 137}, ++{213, 63, 138}, ++{139, 99, 110}, ++{148, 94, 114}, ++{159, 89, 118}, ++{171, 83, 123}, ++{184, 77, 128}, ++{198, 71, 132}, ++{212, 65, 137}, ++{215, 64, 138}, ++{142, 100, 111}, ++{151, 96, 115}, ++{161, 90, 119}, ++{174, 84, 123}, ++{187, 78, 128}, ++{200, 72, 133}, ++{214, 66, 137}, ++{217, 65, 138}, ++{146, 101, 112}, ++{154, 97, 115}, ++{164, 91, 120}, ++{176, 85, 124}, ++{189, 79, 129}, ++{202, 73, 133}, ++{215, 67, 137}, ++{219, 65, 138}, ++{149, 102, 113}, ++{157, 98, 116}, ++{167, 92, 120}, ++{179, 86, 125}, ++{191, 80, 129}, ++{204, 74, 133}, ++{217, 68, 138}, ++{221, 66, 139}, ++{152, 103, 114}, ++{160, 99, 117}, ++{170, 93, 121}, ++{181, 87, 125}, ++{194, 81, 129}, ++{206, 75, 134}, ++{219, 68, 138}, ++{223, 67, 139}, ++{156, 104, 115}, ++{163, 100, 118}, ++{173, 94, 122}, ++{184, 88, 126}, ++{196, 82, 130}, ++{209, 75, 134}, ++{221, 69, 138}, ++{225, 68, 139}, ++{159, 105, 116}, ++{166, 101, 119}, ++{176, 95, 122}, ++{187, 89, 126}, ++{199, 83, 130}, ++{211, 76, 134}, ++{224, 70, 139}, ++{227, 69, 140}, ++{163, 106, 117}, ++{169, 102, 119}, ++{179, 96, 123}, ++{189, 90, 127}, ++{201, 84, 131}, ++{213, 77, 135}, ++{226, 71, 139}, ++{229, 69, 140}, ++{166, 107, 118}, ++{173, 102, 120}, ++{182, 97, 124}, ++{192, 91, 127}, ++{204, 84, 131}, ++{216, 78, 135}, ++{228, 72, 139}, ++{231, 70, 140}, ++{170, 108, 119}, ++{176, 103, 121}, ++{185, 98, 124}, ++{195, 92, 128}, ++{206, 85, 132}, ++{218, 79, 136}, ++{230, 73, 139}, ++{233, 71, 140}, ++{173, 108, 119}, ++{179, 104, 122}, ++{188, 99, 125}, ++{198, 93, 129}, ++{209, 86, 132}, ++{221, 80, 136}, ++{233, 73, 140}, ++{236, 72, 141}, ++{177, 109, 120}, ++{183, 105, 123}, ++{191, 99, 126}, ++{201, 93, 129}, ++{212, 87, 133}, ++{223, 81, 136}, ++{235, 74, 140}, ++{238, 73, 141}, ++{180, 110, 121}, ++{186, 106, 123}, ++{195, 100, 126}, ++{204, 94, 130}, ++{215, 88, 133}, ++{226, 81, 137}, ++{238, 75, 140}, ++{241, 74, 141}, ++{182, 110, 122}, ++{188, 106, 124}, ++{196, 101, 127}, ++{206, 95, 130}, ++{216, 88, 133}, ++{227, 82, 137}, ++{239, 76, 141}, ++{242, 74, 141}, ++{182, 110, 122}, ++{188, 106, 124}, ++{196, 101, 127}, ++{206, 95, 130}, ++{216, 88, 133}, ++{227, 82, 137}, ++{239, 76, 141}, ++{242, 74, 141}, ++{182, 110, 122}, ++{188, 106, 124}, ++{196, 101, 127}, ++{206, 95, 130}, ++{216, 88, 133}, ++{227, 82, 137}, ++{239, 76, 141}, ++{242, 74, 141}, ++{182, 110, 122}, ++{188, 106, 124}, ++{196, 101, 127}, ++{206, 95, 130}, ++{216, 88, 133}, ++{227, 82, 137}, ++{239, 76, 141}, ++{242, 74, 141}, ++{112, 79, 97}, ++{123, 78, 103}, ++{138, 75, 109}, ++{153, 72, 116}, ++{168, 67, 122}, ++{183, 62, 127}, ++{198, 57, 133}, ++{202, 56, 134}, ++{112, 80, 97}, ++{124, 78, 103}, ++{138, 76, 109}, ++{153, 72, 116}, ++{168, 67, 122}, ++{183, 62, 127}, ++{198, 57, 133}, ++{202, 56, 134}, ++{113, 80, 97}, ++{124, 79, 103}, ++{138, 76, 109}, ++{153, 72, 116}, ++{168, 67, 122}, ++{184, 62, 127}, ++{199, 57, 133}, ++{202, 56, 134}, ++{114, 81, 98}, ++{125, 79, 103}, ++{139, 76, 110}, ++{154, 72, 116}, ++{169, 68, 122}, ++{184, 63, 127}, ++{199, 58, 133}, ++{203, 56, 134}, ++{115, 82, 98}, ++{126, 80, 104}, ++{140, 77, 110}, ++{155, 73, 116}, ++{170, 68, 122}, ++{185, 63, 128}, ++{200, 58, 133}, ++{203, 57, 134}, ++{116, 83, 99}, ++{127, 81, 104}, ++{141, 78, 110}, ++{155, 73, 116}, ++{170, 68, 122}, ++{185, 63, 128}, ++{200, 58, 133}, ++{204, 57, 134}, ++{118, 84, 100}, ++{129, 82, 105}, ++{142, 78, 111}, ++{157, 74, 117}, ++{171, 69, 123}, ++{186, 64, 128}, ++{201, 59, 133}, ++{205, 57, 134}, ++{120, 85, 100}, ++{131, 83, 105}, ++{144, 79, 111}, ++{158, 75, 117}, ++{173, 70, 123}, ++{187, 64, 128}, ++{202, 59, 133}, ++{206, 58, 134}, ++{122, 87, 101}, ++{132, 84, 106}, ++{145, 80, 112}, ++{159, 75, 117}, ++{174, 70, 123}, ++{189, 65, 128}, ++{203, 60, 133}, ++{207, 58, 135}, ++{125, 88, 102}, ++{134, 85, 107}, ++{147, 81, 112}, ++{161, 76, 118}, ++{175, 71, 123}, ++{190, 66, 129}, ++{204, 60, 134}, ++{208, 59, 135}, ++{127, 90, 103}, ++{137, 86, 107}, ++{149, 82, 113}, ++{163, 77, 118}, ++{177, 72, 124}, ++{191, 66, 129}, ++{205, 61, 134}, ++{209, 59, 135}, ++{130, 91, 104}, ++{139, 88, 108}, ++{151, 83, 113}, ++{165, 78, 119}, ++{178, 73, 124}, ++{193, 67, 129}, ++{207, 61, 134}, ++{210, 60, 135}, ++{133, 92, 105}, ++{142, 89, 109}, ++{153, 84, 114}, ++{166, 79, 119}, ++{180, 73, 124}, ++{194, 68, 129}, ++{208, 62, 134}, ++{212, 61, 135}, ++{135, 94, 106}, ++{144, 90, 110}, ++{156, 85, 115}, ++{169, 80, 120}, ++{182, 74, 125}, ++{196, 69, 130}, ++{210, 63, 134}, ++{213, 61, 136}, ++{138, 95, 107}, ++{147, 91, 111}, ++{158, 86, 115}, ++{171, 81, 120}, ++{184, 75, 125}, ++{198, 69, 130}, ++{211, 64, 135}, ++{215, 62, 136}, ++{141, 96, 108}, ++{150, 93, 112}, ++{161, 87, 116}, ++{173, 82, 121}, ++{186, 76, 126}, ++{200, 70, 130}, ++{213, 64, 135}, ++{217, 63, 136}, ++{144, 98, 109}, ++{153, 94, 112}, ++{163, 89, 117}, ++{175, 83, 121}, ++{188, 77, 126}, ++{201, 71, 131}, ++{215, 65, 135}, ++{218, 64, 136}, ++{148, 99, 110}, ++{155, 95, 113}, ++{166, 90, 117}, ++{178, 84, 122}, ++{190, 78, 127}, ++{204, 72, 131}, ++{217, 66, 136}, ++{220, 64, 137}, ++{151, 100, 111}, ++{159, 96, 114}, ++{169, 91, 118}, ++{180, 85, 123}, ++{193, 79, 127}, ++{206, 73, 132}, ++{219, 67, 136}, ++{222, 65, 137}, ++{154, 101, 112}, ++{162, 97, 115}, ++{172, 92, 119}, ++{183, 86, 123}, ++{195, 80, 128}, ++{208, 74, 132}, ++{221, 68, 136}, ++{224, 66, 137}, ++{158, 102, 113}, ++{165, 98, 116}, ++{174, 93, 120}, ++{186, 87, 124}, ++{198, 81, 128}, ++{210, 74, 132}, ++{223, 68, 136}, ++{226, 67, 137}, ++{161, 103, 114}, ++{168, 99, 117}, ++{177, 94, 120}, ++{188, 88, 124}, ++{200, 82, 128}, ++{212, 75, 133}, ++{225, 69, 137}, ++{228, 68, 138}, ++{164, 104, 115}, ++{171, 100, 117}, ++{180, 95, 121}, ++{191, 89, 125}, ++{203, 82, 129}, ++{215, 76, 133}, ++{227, 70, 137}, ++{230, 69, 138}, ++{168, 105, 116}, ++{174, 101, 118}, ++{183, 96, 122}, ++{194, 90, 125}, ++{205, 83, 129}, ++{217, 77, 133}, ++{229, 71, 137}, ++{232, 69, 138}, ++{171, 106, 117}, ++{178, 102, 119}, ++{187, 96, 122}, ++{197, 90, 126}, ++{208, 84, 130}, ++{220, 78, 134}, ++{232, 72, 138}, ++{235, 70, 139}, ++{175, 107, 118}, ++{181, 103, 120}, ++{190, 97, 123}, ++{200, 91, 127}, ++{211, 85, 130}, ++{222, 79, 134}, ++{234, 73, 138}, ++{237, 71, 139}, ++{178, 108, 118}, ++{184, 103, 121}, ++{193, 98, 124}, ++{203, 92, 127}, ++{213, 86, 131}, ++{225, 80, 135}, ++{236, 73, 138}, ++{239, 72, 139}, ++{182, 108, 119}, ++{188, 104, 121}, ++{196, 99, 124}, ++{206, 93, 128}, ++{216, 87, 131}, ++{227, 81, 135}, ++{239, 74, 139}, ++{242, 73, 140}, ++{184, 109, 120}, ++{190, 105, 122}, ++{198, 99, 125}, ++{207, 94, 128}, ++{218, 87, 132}, ++{229, 81, 135}, ++{240, 75, 139}, ++{243, 73, 140}, ++{184, 109, 120}, ++{190, 105, 122}, ++{198, 99, 125}, ++{207, 94, 128}, ++{218, 87, 132}, ++{229, 81, 135}, ++{240, 75, 139}, ++{243, 73, 140}, ++{184, 109, 120}, ++{190, 105, 122}, ++{198, 99, 125}, ++{207, 94, 128}, ++{218, 87, 132}, ++{229, 81, 135}, ++{240, 75, 139}, ++{243, 73, 140}, ++{184, 109, 120}, ++{190, 105, 122}, ++{198, 99, 125}, ++{207, 94, 128}, ++{218, 87, 132}, ++{229, 81, 135}, ++{240, 75, 139}, ++{243, 73, 140}, ++{115, 77, 95}, ++{126, 76, 100}, ++{140, 74, 107}, ++{155, 70, 113}, ++{170, 66, 119}, ++{185, 61, 125}, ++{200, 56, 130}, ++{204, 55, 132}, ++{115, 77, 95}, ++{126, 76, 100}, ++{140, 74, 107}, ++{155, 70, 113}, ++{170, 66, 119}, ++{185, 61, 125}, ++{200, 56, 130}, ++{204, 55, 132}, ++{116, 77, 95}, ++{127, 76, 101}, ++{140, 74, 107}, ++{155, 70, 113}, ++{170, 66, 120}, ++{185, 61, 125}, ++{200, 57, 131}, ++{204, 55, 132}, ++{117, 78, 95}, ++{127, 77, 101}, ++{141, 74, 107}, ++{156, 71, 114}, ++{171, 66, 120}, ++{186, 62, 125}, ++{201, 57, 131}, ++{204, 55, 132}, ++{118, 79, 96}, ++{128, 78, 101}, ++{142, 75, 108}, ++{157, 71, 114}, ++{171, 67, 120}, ++{186, 62, 125}, ++{201, 57, 131}, ++{205, 56, 132}, ++{119, 80, 97}, ++{130, 79, 102}, ++{143, 76, 108}, ++{158, 72, 114}, ++{172, 67, 120}, ++{187, 62, 126}, ++{202, 57, 131}, ++{206, 56, 132}, ++{121, 82, 97}, ++{131, 80, 102}, ++{144, 76, 108}, ++{159, 72, 114}, ++{173, 68, 120}, ++{188, 63, 126}, ++{203, 58, 131}, ++{206, 57, 132}, ++{123, 83, 98}, ++{133, 81, 103}, ++{146, 77, 109}, ++{160, 73, 115}, ++{174, 68, 121}, ++{189, 63, 126}, ++{204, 58, 131}, ++{207, 57, 132}, ++{125, 84, 99}, ++{135, 82, 104}, ++{147, 78, 109}, ++{161, 74, 115}, ++{176, 69, 121}, ++{190, 64, 126}, ++{205, 59, 131}, ++{208, 57, 133}, ++{127, 86, 100}, ++{137, 83, 104}, ++{149, 79, 110}, ++{163, 75, 116}, ++{177, 70, 121}, ++{191, 65, 127}, ++{206, 59, 132}, ++{209, 58, 133}, ++{130, 87, 101}, ++{139, 84, 105}, ++{151, 80, 111}, ++{165, 76, 116}, ++{179, 71, 122}, ++{193, 65, 127}, ++{207, 60, 132}, ++{211, 59, 133}, ++{132, 89, 102}, ++{141, 86, 106}, ++{153, 81, 111}, ++{166, 77, 117}, ++{180, 71, 122}, ++{194, 66, 127}, ++{208, 61, 132}, ++{212, 59, 133}, ++{135, 90, 103}, ++{144, 87, 107}, ++{155, 83, 112}, ++{168, 77, 117}, ++{182, 72, 122}, ++{196, 67, 127}, ++{210, 61, 132}, ++{213, 60, 133}, ++{138, 92, 104}, ++{146, 88, 108}, ++{158, 84, 112}, ++{170, 78, 118}, ++{184, 73, 123}, ++{198, 68, 128}, ++{211, 62, 132}, ++{215, 61, 134}, ++{141, 93, 105}, ++{149, 89, 108}, ++{160, 85, 113}, ++{173, 79, 118}, ++{186, 74, 123}, ++{199, 68, 128}, ++{213, 63, 133}, ++{216, 61, 134}, ++{144, 94, 106}, ++{152, 91, 109}, ++{163, 86, 114}, ++{175, 80, 119}, ++{188, 75, 124}, ++{201, 69, 128}, ++{215, 63, 133}, ++{218, 62, 134}, ++{147, 96, 107}, ++{155, 92, 110}, ++{165, 87, 115}, ++{177, 81, 119}, ++{190, 76, 124}, ++{203, 70, 129}, ++{216, 64, 133}, ++{220, 63, 134}, ++{150, 97, 108}, ++{157, 93, 111}, ++{168, 88, 115}, ++{180, 82, 120}, ++{192, 77, 125}, ++{205, 71, 129}, ++{218, 65, 134}, ++{221, 64, 135}, ++{153, 98, 109}, ++{160, 94, 112}, ++{171, 89, 116}, ++{182, 83, 121}, ++{194, 78, 125}, ++{207, 72, 130}, ++{220, 66, 134}, ++{223, 64, 135}, ++{156, 99, 110}, ++{164, 95, 113}, ++{173, 90, 117}, ++{185, 84, 121}, ++{197, 79, 126}, ++{209, 73, 130}, ++{222, 67, 134}, ++{225, 65, 135}, ++{160, 100, 111}, ++{167, 96, 114}, ++{176, 91, 118}, ++{187, 85, 122}, ++{199, 80, 126}, ++{211, 73, 130}, ++{224, 68, 135}, ++{227, 66, 136}, ++{163, 101, 112}, ++{170, 97, 115}, ++{179, 92, 118}, ++{190, 86, 122}, ++{202, 80, 127}, ++{214, 74, 131}, ++{226, 68, 135}, ++{229, 67, 136}, ++{166, 102, 113}, ++{173, 98, 115}, ++{182, 93, 119}, ++{193, 87, 123}, ++{204, 81, 127}, ++{216, 75, 131}, ++{228, 69, 135}, ++{232, 68, 136}, ++{170, 103, 114}, ++{176, 99, 116}, ++{185, 94, 120}, ++{195, 88, 124}, ++{207, 82, 128}, ++{219, 76, 132}, ++{231, 70, 136}, ++{234, 69, 137}, ++{173, 104, 115}, ++{180, 100, 117}, ++{188, 95, 120}, ++{198, 89, 124}, ++{209, 83, 128}, ++{221, 77, 132}, ++{233, 71, 136}, ++{236, 69, 137}, ++{177, 105, 116}, ++{183, 101, 118}, ++{191, 96, 121}, ++{201, 90, 125}, ++{212, 84, 129}, ++{223, 78, 132}, ++{235, 72, 136}, ++{238, 70, 137}, ++{180, 106, 116}, ++{186, 102, 119}, ++{194, 97, 122}, ++{204, 91, 125}, ++{215, 85, 129}, ++{226, 79, 133}, ++{238, 73, 137}, ++{241, 71, 138}, ++{184, 107, 117}, ++{190, 103, 120}, ++{198, 98, 123}, ++{207, 92, 126}, ++{218, 86, 130}, ++{229, 80, 133}, ++{240, 73, 137}, ++{243, 72, 138}, ++{185, 107, 118}, ++{191, 103, 120}, ++{199, 98, 123}, ++{209, 92, 126}, ++{219, 86, 130}, ++{230, 80, 134}, ++{241, 74, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{191, 103, 120}, ++{199, 98, 123}, ++{209, 92, 126}, ++{219, 86, 130}, ++{230, 80, 134}, ++{241, 74, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{191, 103, 120}, ++{199, 98, 123}, ++{209, 92, 126}, ++{219, 86, 130}, ++{230, 80, 134}, ++{241, 74, 137}, ++{244, 72, 138}, ++{185, 107, 118}, ++{191, 103, 120}, ++{199, 98, 123}, ++{209, 92, 126}, ++{219, 86, 130}, ++{230, 80, 134}, ++{241, 74, 137}, ++{244, 72, 138}, ++{118, 74, 93}, ++{129, 74, 98}, ++{142, 72, 105}, ++{157, 68, 111}, ++{172, 65, 117}, ++{187, 60, 123}, ++{202, 55, 128}, ++{205, 54, 130}, ++{118, 74, 93}, ++{129, 74, 98}, ++{142, 72, 105}, ++{157, 69, 111}, ++{172, 65, 117}, ++{187, 60, 123}, ++{202, 55, 128}, ++{205, 54, 130}, ++{118, 75, 93}, ++{129, 74, 98}, ++{143, 72, 105}, ++{157, 69, 111}, ++{172, 65, 117}, ++{187, 60, 123}, ++{202, 56, 128}, ++{206, 54, 130}, ++{119, 76, 93}, ++{130, 75, 99}, ++{143, 73, 105}, ++{158, 69, 111}, ++{173, 65, 118}, ++{188, 61, 123}, ++{202, 56, 129}, ++{206, 55, 130}, ++{121, 77, 94}, ++{131, 76, 99}, ++{144, 73, 105}, ++{159, 70, 112}, ++{173, 65, 118}, ++{188, 61, 123}, ++{203, 56, 129}, ++{206, 55, 130}, ++{122, 78, 94}, ++{132, 76, 100}, ++{145, 74, 106}, ++{160, 70, 112}, ++{174, 66, 118}, ++{189, 61, 124}, ++{204, 56, 129}, ++{207, 55, 130}, ++{124, 79, 95}, ++{134, 77, 100}, ++{147, 75, 106}, ++{161, 71, 112}, ++{175, 66, 118}, ++{190, 62, 124}, ++{204, 57, 129}, ++{208, 56, 130}, ++{125, 80, 96}, ++{135, 79, 101}, ++{148, 76, 107}, ++{162, 72, 113}, ++{176, 67, 118}, ++{191, 62, 124}, ++{205, 57, 129}, ++{209, 56, 130}, ++{128, 82, 97}, ++{137, 80, 101}, ++{150, 76, 107}, ++{163, 72, 113}, ++{178, 68, 119}, ++{192, 63, 124}, ++{206, 58, 129}, ++{210, 57, 131}, ++{130, 83, 98}, ++{139, 81, 102}, ++{151, 77, 108}, ++{165, 73, 113}, ++{179, 68, 119}, ++{193, 63, 124}, ++{207, 58, 130}, ++{211, 57, 131}, ++{132, 85, 99}, ++{141, 82, 103}, ++{153, 79, 108}, ++{167, 74, 114}, ++{180, 69, 119}, ++{194, 64, 125}, ++{209, 59, 130}, ++{212, 58, 131}, ++{135, 86, 100}, ++{144, 84, 104}, ++{155, 80, 109}, ++{168, 75, 114}, ++{182, 70, 120}, ++{196, 65, 125}, ++{210, 60, 130}, ++{213, 58, 131}, ++{137, 88, 101}, ++{146, 85, 105}, ++{157, 81, 110}, ++{170, 76, 115}, ++{184, 71, 120}, ++{197, 66, 125}, ++{211, 60, 130}, ++{215, 59, 131}, ++{140, 89, 102}, ++{149, 86, 105}, ++{160, 82, 110}, ++{172, 77, 116}, ++{186, 72, 121}, ++{199, 66, 126}, ++{213, 61, 131}, ++{216, 60, 132}, ++{143, 91, 103}, ++{151, 87, 106}, ++{162, 83, 111}, ++{174, 78, 116}, ++{187, 73, 121}, ++{201, 67, 126}, ++{214, 62, 131}, ++{218, 60, 132}, ++{146, 92, 104}, ++{154, 89, 107}, ++{165, 84, 112}, ++{177, 79, 117}, ++{189, 74, 122}, ++{203, 68, 126}, ++{216, 63, 131}, ++{219, 61, 132}, ++{149, 94, 105}, ++{157, 90, 108}, ++{167, 85, 113}, ++{179, 80, 117}, ++{192, 75, 122}, ++{205, 69, 127}, ++{218, 63, 131}, ++{221, 62, 133}, ++{152, 95, 106}, ++{160, 91, 109}, ++{170, 86, 113}, ++{181, 81, 118}, ++{194, 75, 123}, ++{207, 70, 127}, ++{220, 64, 132}, ++{223, 63, 133}, ++{155, 96, 107}, ++{162, 92, 110}, ++{172, 88, 114}, ++{184, 82, 118}, ++{196, 76, 123}, ++{209, 71, 128}, ++{222, 65, 132}, ++{225, 64, 133}, ++{158, 97, 108}, ++{165, 94, 111}, ++{175, 89, 115}, ++{186, 83, 119}, ++{198, 77, 124}, ++{211, 72, 128}, ++{224, 66, 132}, ++{227, 64, 134}, ++{162, 98, 109}, ++{169, 95, 112}, ++{178, 90, 116}, ++{189, 84, 120}, ++{201, 78, 124}, ++{213, 72, 128}, ++{226, 67, 133}, ++{229, 65, 134}, ++{165, 99, 110}, ++{172, 96, 113}, ++{181, 91, 116}, ++{192, 85, 120}, ++{203, 79, 125}, ++{215, 73, 129}, ++{228, 67, 133}, ++{231, 66, 134}, ++{168, 101, 111}, ++{175, 97, 113}, ++{184, 92, 117}, ++{194, 86, 121}, ++{206, 80, 125}, ++{218, 74, 129}, ++{230, 68, 133}, ++{233, 67, 135}, ++{172, 102, 112}, ++{178, 98, 114}, ++{187, 93, 118}, ++{197, 87, 122}, ++{208, 81, 126}, ++{220, 75, 130}, ++{232, 69, 134}, ++{235, 68, 135}, ++{175, 102, 113}, ++{181, 99, 115}, ++{190, 94, 119}, ++{200, 88, 122}, ++{211, 82, 126}, ++{222, 76, 130}, ++{234, 70, 134}, ++{237, 69, 135}, ++{178, 103, 114}, ++{185, 100, 116}, ++{193, 95, 119}, ++{203, 89, 123}, ++{214, 83, 127}, ++{225, 77, 131}, ++{237, 71, 135}, ++{240, 69, 136}, ++{182, 104, 115}, ++{188, 101, 117}, ++{196, 95, 120}, ++{206, 90, 124}, ++{216, 84, 127}, ++{227, 78, 131}, ++{239, 72, 135}, ++{242, 70, 136}, ++{185, 105, 115}, ++{191, 101, 118}, ++{199, 96, 121}, ++{209, 91, 124}, ++{219, 85, 128}, ++{230, 79, 132}, ++{241, 73, 135}, ++{244, 71, 136}, ++{187, 106, 116}, ++{193, 102, 118}, ++{201, 97, 121}, ++{210, 91, 124}, ++{220, 85, 128}, ++{231, 79, 132}, ++{243, 73, 136}, ++{245, 72, 137}, ++{187, 106, 116}, ++{193, 102, 118}, ++{201, 97, 121}, ++{210, 91, 124}, ++{220, 85, 128}, ++{231, 79, 132}, ++{243, 73, 136}, ++{245, 72, 137}, ++{187, 106, 116}, ++{193, 102, 118}, ++{201, 97, 121}, ++{210, 91, 124}, ++{220, 85, 128}, ++{231, 79, 132}, ++{243, 73, 136}, ++{245, 72, 137}, ++{187, 106, 116}, ++{193, 102, 118}, ++{201, 97, 121}, ++{210, 91, 124}, ++{220, 85, 128}, ++{231, 79, 132}, ++{243, 73, 136}, ++{245, 72, 137}, ++{121, 72, 90}, ++{131, 71, 96}, ++{144, 70, 102}, ++{159, 67, 109}, ++{174, 63, 115}, ++{188, 59, 121}, ++{203, 54, 126}, ++{207, 53, 128}, ++{121, 72, 91}, ++{131, 72, 96}, ++{145, 70, 102}, ++{159, 67, 109}, ++{174, 63, 115}, ++{189, 59, 121}, ++{203, 54, 126}, ++{207, 53, 128}, ++{121, 72, 91}, ++{132, 72, 96}, ++{145, 70, 103}, ++{159, 67, 109}, ++{174, 63, 115}, ++{189, 59, 121}, ++{204, 55, 126}, ++{207, 53, 128}, ++{122, 73, 91}, ++{133, 73, 96}, ++{146, 71, 103}, ++{160, 68, 109}, ++{175, 64, 115}, ++{189, 59, 121}, ++{204, 55, 127}, ++{208, 54, 128}, ++{123, 74, 92}, ++{134, 73, 97}, ++{147, 71, 103}, ++{161, 68, 109}, ++{175, 64, 116}, ++{190, 60, 121}, ++{204, 55, 127}, ++{208, 54, 128}, ++{125, 75, 92}, ++{135, 74, 97}, ++{148, 72, 103}, ++{162, 69, 110}, ++{176, 65, 116}, ++{191, 60, 121}, ++{205, 55, 127}, ++{209, 54, 128}, ++{126, 77, 93}, ++{136, 75, 98}, ++{149, 73, 104}, ++{163, 69, 110}, ++{177, 65, 116}, ++{191, 61, 122}, ++{206, 56, 127}, ++{209, 55, 128}, ++{128, 78, 94}, ++{138, 76, 99}, ++{150, 74, 104}, ++{164, 70, 110}, ++{178, 66, 116}, ++{192, 61, 122}, ++{207, 56, 127}, ++{210, 55, 128}, ++{130, 79, 95}, ++{140, 78, 99}, ++{152, 75, 105}, ++{165, 71, 111}, ++{179, 66, 117}, ++{194, 62, 122}, ++{208, 57, 127}, ++{211, 56, 129}, ++{132, 81, 96}, ++{142, 79, 100}, ++{154, 76, 106}, ++{167, 72, 111}, ++{181, 67, 117}, ++{195, 62, 122}, ++{209, 57, 128}, ++{212, 56, 129}, ++{135, 82, 96}, ++{144, 80, 101}, ++{155, 77, 106}, ++{169, 73, 112}, ++{182, 68, 117}, ++{196, 63, 123}, ++{210, 58, 128}, ++{214, 57, 129}, ++{137, 84, 97}, ++{146, 81, 102}, ++{157, 78, 107}, ++{170, 74, 112}, ++{184, 69, 118}, ++{198, 64, 123}, ++{211, 59, 128}, ++{215, 57, 129}, ++{140, 86, 98}, ++{148, 83, 102}, ++{160, 79, 107}, ++{172, 74, 113}, ++{186, 70, 118}, ++{199, 64, 123}, ++{213, 59, 128}, ++{216, 58, 129}, ++{142, 87, 99}, ++{151, 84, 103}, ++{162, 80, 108}, ++{174, 75, 113}, ++{187, 70, 119}, ++{201, 65, 124}, ++{214, 60, 129}, ++{218, 59, 130}, ++{145, 89, 100}, ++{153, 85, 104}, ++{164, 81, 109}, ++{176, 77, 114}, ++{189, 71, 119}, ++{202, 66, 124}, ++{216, 61, 129}, ++{219, 59, 130}, ++{148, 90, 102}, ++{156, 87, 105}, ++{167, 82, 110}, ++{178, 78, 115}, ++{191, 72, 120}, ++{204, 67, 124}, ++{218, 62, 129}, ++{221, 60, 130}, ++{151, 91, 103}, ++{159, 88, 106}, ++{169, 84, 110}, ++{181, 79, 115}, ++{193, 73, 120}, ++{206, 68, 125}, ++{219, 62, 130}, ++{223, 61, 131}, ++{154, 93, 104}, ++{162, 89, 107}, ++{172, 85, 111}, ++{183, 80, 116}, ++{195, 74, 121}, ++{208, 69, 125}, ++{221, 63, 130}, ++{224, 62, 131}, ++{157, 94, 105}, ++{164, 91, 108}, ++{174, 86, 112}, ++{186, 81, 116}, ++{198, 75, 121}, ++{210, 70, 126}, ++{223, 64, 130}, ++{226, 63, 131}, ++{160, 95, 106}, ++{167, 92, 109}, ++{177, 87, 113}, ++{188, 82, 117}, ++{200, 76, 122}, ++{212, 70, 126}, ++{225, 65, 131}, ++{228, 63, 132}, ++{164, 96, 107}, ++{170, 93, 110}, ++{180, 88, 113}, ++{191, 83, 118}, ++{202, 77, 122}, ++{214, 71, 127}, ++{227, 66, 131}, ++{230, 64, 132}, ++{167, 98, 108}, ++{174, 94, 111}, ++{183, 89, 114}, ++{193, 84, 118}, ++{205, 78, 123}, ++{217, 72, 127}, ++{229, 67, 131}, ++{232, 65, 132}, ++{170, 99, 109}, ++{177, 95, 111}, ++{186, 90, 115}, ++{196, 85, 119}, ++{207, 79, 123}, ++{219, 73, 128}, ++{231, 67, 132}, ++{234, 66, 133}, ++{173, 100, 110}, ++{180, 96, 112}, ++{189, 91, 116}, ++{199, 86, 120}, ++{210, 80, 124}, ++{221, 74, 128}, ++{233, 68, 132}, ++{236, 67, 133}, ++{177, 101, 111}, ++{183, 97, 113}, ++{192, 92, 117}, ++{202, 87, 120}, ++{212, 81, 124}, ++{224, 75, 128}, ++{236, 69, 132}, ++{239, 68, 133}, ++{180, 102, 112}, ++{186, 98, 114}, ++{195, 93, 117}, ++{204, 88, 121}, ++{215, 82, 125}, ++{226, 76, 129}, ++{238, 70, 133}, ++{241, 69, 134}, ++{184, 103, 113}, ++{190, 99, 115}, ++{198, 94, 118}, ++{207, 89, 122}, ++{218, 83, 125}, ++{229, 77, 129}, ++{240, 71, 133}, ++{243, 69, 134}, ++{187, 103, 114}, ++{193, 100, 116}, ++{201, 95, 119}, ++{210, 89, 122}, ++{220, 84, 126}, ++{231, 78, 130}, ++{243, 72, 134}, ++{246, 70, 135}, ++{189, 104, 114}, ++{195, 100, 116}, ++{202, 95, 119}, ++{212, 90, 123}, ++{222, 84, 126}, ++{233, 78, 130}, ++{244, 72, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 116}, ++{202, 95, 119}, ++{212, 90, 123}, ++{222, 84, 126}, ++{233, 78, 130}, ++{244, 72, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 116}, ++{202, 95, 119}, ++{212, 90, 123}, ++{222, 84, 126}, ++{233, 78, 130}, ++{244, 72, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 116}, ++{202, 95, 119}, ++{212, 90, 123}, ++{222, 84, 126}, ++{233, 78, 130}, ++{244, 72, 134}, ++{247, 71, 135}, ++{123, 69, 88}, ++{134, 69, 94}, ++{147, 68, 100}, ++{161, 65, 107}, ++{176, 62, 113}, ++{190, 58, 119}, ++{205, 53, 124}, ++{208, 52, 126}, ++{124, 69, 88}, ++{134, 69, 94}, ++{147, 68, 100}, ++{161, 65, 107}, ++{176, 62, 113}, ++{190, 58, 119}, ++{205, 53, 124}, ++{209, 52, 126}, ++{124, 70, 89}, ++{134, 70, 94}, ++{147, 68, 100}, ++{162, 66, 107}, ++{176, 62, 113}, ++{191, 58, 119}, ++{205, 53, 124}, ++{209, 52, 126}, ++{125, 71, 89}, ++{135, 70, 94}, ++{148, 69, 101}, ++{162, 66, 107}, ++{177, 62, 113}, ++{191, 58, 119}, ++{206, 54, 124}, ++{209, 53, 126}, ++{126, 72, 90}, ++{136, 71, 95}, ++{149, 69, 101}, ++{163, 66, 107}, ++{177, 63, 113}, ++{192, 58, 119}, ++{206, 54, 125}, ++{210, 53, 126}, ++{127, 73, 90}, ++{137, 72, 95}, ++{150, 70, 101}, ++{164, 67, 108}, ++{178, 63, 114}, ++{192, 59, 119}, ++{207, 54, 125}, ++{210, 53, 126}, ++{129, 74, 91}, ++{139, 73, 96}, ++{151, 71, 102}, ++{165, 68, 108}, ++{179, 64, 114}, ++{193, 59, 120}, ++{208, 55, 125}, ++{211, 54, 126}, ++{131, 76, 92}, ++{140, 74, 96}, ++{153, 72, 102}, ++{166, 68, 108}, ++{180, 64, 114}, ++{194, 60, 120}, ++{208, 55, 125}, ++{212, 54, 126}, ++{133, 77, 93}, ++{142, 75, 97}, ++{154, 73, 103}, ++{167, 69, 109}, ++{181, 65, 115}, ++{195, 60, 120}, ++{209, 56, 125}, ++{213, 55, 127}, ++{135, 79, 93}, ++{144, 77, 98}, ++{156, 74, 103}, ++{169, 70, 109}, ++{183, 66, 115}, ++{197, 61, 120}, ++{210, 56, 126}, ++{214, 55, 127}, ++{137, 80, 94}, ++{146, 78, 99}, ++{158, 75, 104}, ++{171, 71, 110}, ++{184, 67, 115}, ++{198, 62, 121}, ++{212, 57, 126}, ++{215, 56, 127}, ++{140, 82, 95}, ++{148, 79, 99}, ++{160, 76, 105}, ++{172, 72, 110}, ++{186, 67, 116}, ++{199, 63, 121}, ++{213, 58, 126}, ++{216, 56, 127}, ++{142, 83, 96}, ++{151, 81, 100}, ++{162, 77, 105}, ++{174, 73, 111}, ++{187, 68, 116}, ++{201, 63, 121}, ++{214, 58, 126}, ++{218, 57, 128}, ++{145, 85, 97}, ++{153, 82, 101}, ++{164, 78, 106}, ++{176, 74, 111}, ++{189, 69, 117}, ++{202, 64, 122}, ++{216, 59, 127}, ++{219, 58, 128}, ++{148, 86, 98}, ++{156, 83, 102}, ++{166, 80, 107}, ++{178, 75, 112}, ++{191, 70, 117}, ++{204, 65, 122}, ++{217, 60, 127}, ++{221, 58, 128}, ++{150, 88, 99}, ++{158, 85, 103}, ++{169, 81, 108}, ++{180, 76, 113}, ++{193, 71, 118}, ++{206, 66, 123}, ++{219, 61, 127}, ++{222, 59, 128}, ++{153, 89, 100}, ++{161, 86, 104}, ++{171, 82, 108}, ++{183, 77, 113}, ++{195, 72, 118}, ++{208, 67, 123}, ++{221, 61, 128}, ++{224, 60, 129}, ++{156, 91, 102}, ++{164, 87, 105}, ++{174, 83, 109}, ++{185, 78, 114}, ++{197, 73, 119}, ++{210, 68, 123}, ++{223, 62, 128}, ++{226, 61, 129}, ++{159, 92, 103}, ++{167, 89, 106}, ++{176, 84, 110}, ++{187, 79, 114}, ++{199, 74, 119}, ++{212, 68, 124}, ++{224, 63, 128}, ++{228, 62, 129}, ++{162, 93, 104}, ++{169, 90, 107}, ++{179, 85, 111}, ++{190, 80, 115}, ++{202, 75, 120}, ++{214, 69, 124}, ++{226, 64, 129}, ++{230, 62, 130}, ++{166, 94, 105}, ++{172, 91, 108}, ++{182, 86, 111}, ++{192, 81, 116}, ++{204, 76, 120}, ++{216, 70, 125}, ++{228, 65, 129}, ++{232, 63, 130}, ++{169, 96, 106}, ++{175, 92, 109}, ++{185, 88, 112}, ++{195, 82, 116}, ++{206, 77, 121}, ++{218, 71, 125}, ++{230, 66, 129}, ++{234, 64, 131}, ++{172, 97, 107}, ++{179, 93, 109}, ++{187, 89, 113}, ++{198, 83, 117}, ++{209, 78, 121}, ++{221, 72, 126}, ++{233, 66, 130}, ++{236, 65, 131}, ++{175, 98, 108}, ++{182, 94, 110}, ++{190, 90, 114}, ++{200, 84, 118}, ++{211, 79, 122}, ++{223, 73, 126}, ++{235, 67, 130}, ++{238, 66, 131}, ++{179, 99, 109}, ++{185, 95, 111}, ++{193, 91, 115}, ++{203, 85, 118}, ++{214, 80, 123}, ++{225, 74, 127}, ++{237, 68, 131}, ++{240, 67, 132}, ++{182, 100, 110}, ++{188, 96, 112}, ++{196, 92, 115}, ++{206, 86, 119}, ++{217, 81, 123}, ++{228, 75, 127}, ++{239, 69, 131}, ++{242, 68, 132}, ++{185, 101, 111}, ++{191, 97, 113}, ++{199, 93, 116}, ++{209, 87, 120}, ++{219, 82, 124}, ++{230, 76, 128}, ++{242, 70, 132}, ++{245, 68, 132}, ++{189, 102, 112}, ++{195, 98, 114}, ++{202, 94, 117}, ++{212, 88, 120}, ++{222, 83, 124}, ++{233, 77, 128}, ++{244, 71, 132}, ++{247, 69, 133}, ++{191, 102, 112}, ++{196, 99, 114}, ++{204, 94, 117}, ++{213, 89, 121}, ++{223, 83, 125}, ++{234, 77, 128}, ++{245, 71, 132}, ++{248, 70, 133}, ++{191, 102, 112}, ++{196, 99, 114}, ++{204, 94, 117}, ++{213, 89, 121}, ++{223, 83, 125}, ++{234, 77, 128}, ++{245, 71, 132}, ++{248, 70, 133}, ++{191, 102, 112}, ++{196, 99, 114}, ++{204, 94, 117}, ++{213, 89, 121}, ++{223, 83, 125}, ++{234, 77, 128}, ++{245, 71, 132}, ++{248, 70, 133}, ++{191, 102, 112}, ++{196, 99, 114}, ++{204, 94, 117}, ++{213, 89, 121}, ++{223, 83, 125}, ++{234, 77, 128}, ++{245, 71, 132}, ++{248, 70, 133}, ++{126, 67, 86}, ++{136, 67, 92}, ++{149, 66, 98}, ++{163, 64, 105}, ++{178, 60, 111}, ++{192, 56, 117}, ++{206, 52, 122}, ++{210, 51, 124}, ++{126, 67, 86}, ++{136, 67, 92}, ++{149, 66, 98}, ++{163, 64, 105}, ++{178, 60, 111}, ++{192, 56, 117}, ++{207, 52, 122}, ++{210, 51, 124}, ++{127, 67, 87}, ++{137, 68, 92}, ++{150, 66, 98}, ++{164, 64, 105}, ++{178, 61, 111}, ++{192, 57, 117}, ++{207, 52, 122}, ++{210, 51, 124}, ++{128, 68, 87}, ++{138, 68, 92}, ++{150, 67, 98}, ++{164, 64, 105}, ++{178, 61, 111}, ++{193, 57, 117}, ++{207, 53, 122}, ++{211, 52, 124}, ++{129, 69, 88}, ++{139, 69, 93}, ++{151, 67, 99}, ++{165, 65, 105}, ++{179, 61, 111}, ++{193, 57, 117}, ++{208, 53, 123}, ++{211, 52, 124}, ++{130, 70, 88}, ++{140, 70, 93}, ++{152, 68, 99}, ++{166, 65, 105}, ++{180, 62, 111}, ++{194, 58, 117}, ++{208, 53, 123}, ++{212, 52, 124}, ++{132, 72, 89}, ++{141, 71, 94}, ++{153, 69, 100}, ++{167, 66, 106}, ++{181, 62, 112}, ++{195, 58, 117}, ++{209, 54, 123}, ++{213, 53, 124}, ++{133, 73, 90}, ++{143, 72, 94}, ++{155, 70, 100}, ++{168, 67, 106}, ++{182, 63, 112}, ++{196, 59, 118}, ++{210, 54, 123}, ++{214, 53, 124}, ++{135, 75, 90}, ++{144, 73, 95}, ++{156, 71, 101}, ++{169, 68, 107}, ++{183, 64, 112}, ++{197, 59, 118}, ++{211, 55, 123}, ++{215, 54, 125}, ++{137, 76, 91}, ++{146, 75, 96}, ++{158, 72, 101}, ++{171, 68, 107}, ++{184, 64, 113}, ++{198, 60, 118}, ++{212, 55, 124}, ++{216, 54, 125}, ++{140, 78, 92}, ++{148, 76, 97}, ++{160, 73, 102}, ++{173, 69, 108}, ++{186, 65, 113}, ++{200, 61, 119}, ++{213, 56, 124}, ++{217, 55, 125}, ++{142, 79, 93}, ++{151, 77, 97}, ++{162, 74, 103}, ++{174, 70, 108}, ++{187, 66, 114}, ++{201, 61, 119}, ++{215, 57, 124}, ++{218, 55, 125}, ++{145, 81, 94}, ++{153, 79, 98}, ++{164, 75, 103}, ++{176, 71, 109}, ++{189, 67, 114}, ++{202, 62, 119}, ++{216, 57, 124}, ++{219, 56, 126}, ++{147, 82, 95}, ++{155, 80, 99}, ++{166, 77, 104}, ++{178, 72, 109}, ++{191, 68, 115}, ++{204, 63, 120}, ++{217, 58, 125}, ++{221, 57, 126}, ++{150, 84, 96}, ++{158, 81, 100}, ++{168, 78, 105}, ++{180, 73, 110}, ++{193, 69, 115}, ++{206, 64, 120}, ++{219, 59, 125}, ++{222, 57, 126}, ++{153, 86, 97}, ++{160, 83, 101}, ++{171, 79, 106}, ++{182, 74, 110}, ++{195, 70, 116}, ++{208, 65, 121}, ++{221, 60, 125}, ++{224, 58, 127}, ++{156, 87, 98}, ++{163, 84, 102}, ++{173, 80, 106}, ++{184, 76, 111}, ++{197, 71, 116}, ++{209, 66, 121}, ++{222, 60, 126}, ++{226, 59, 127}, ++{158, 88, 100}, ++{166, 85, 103}, ++{176, 81, 107}, ++{187, 77, 112}, ++{199, 72, 117}, ++{211, 66, 121}, ++{224, 61, 126}, ++{227, 60, 127}, ++{161, 90, 101}, ++{169, 87, 104}, ++{178, 83, 108}, ++{189, 78, 112}, ++{201, 73, 117}, ++{213, 67, 122}, ++{226, 62, 126}, ++{229, 61, 128}, ++{165, 91, 102}, ++{171, 88, 105}, ++{181, 84, 109}, ++{192, 79, 113}, ++{203, 74, 118}, ++{215, 68, 122}, ++{228, 63, 127}, ++{231, 61, 128}, ++{168, 92, 103}, ++{174, 89, 106}, ++{184, 85, 109}, ++{194, 80, 114}, ++{206, 75, 118}, ++{218, 69, 123}, ++{230, 64, 127}, ++{233, 62, 128}, ++{171, 94, 104}, ++{177, 90, 107}, ++{186, 86, 110}, ++{197, 81, 114}, ++{208, 76, 119}, ++{220, 70, 123}, ++{232, 65, 128}, ++{235, 63, 129}, ++{174, 95, 105}, ++{180, 92, 107}, ++{189, 87, 111}, ++{199, 82, 115}, ++{210, 77, 119}, ++{222, 71, 124}, ++{234, 65, 128}, ++{237, 64, 129}, ++{177, 96, 106}, ++{184, 93, 108}, ++{192, 88, 112}, ++{202, 83, 116}, ++{213, 78, 120}, ++{224, 72, 124}, ++{236, 66, 128}, ++{239, 65, 130}, ++{181, 97, 107}, ++{187, 94, 109}, ++{195, 89, 113}, ++{205, 84, 117}, ++{215, 79, 121}, ++{227, 73, 125}, ++{238, 67, 129}, ++{241, 66, 130}, ++{184, 98, 108}, ++{190, 95, 110}, ++{198, 90, 114}, ++{208, 85, 117}, ++{218, 79, 121}, ++{229, 74, 125}, ++{241, 68, 129}, ++{244, 67, 130}, ++{187, 99, 109}, ++{193, 96, 111}, ++{201, 91, 114}, ++{210, 86, 118}, ++{221, 80, 122}, ++{232, 75, 126}, ++{243, 69, 130}, ++{246, 68, 131}, ++{191, 100, 110}, ++{196, 97, 112}, ++{204, 92, 115}, ++{213, 87, 119}, ++{223, 81, 122}, ++{234, 76, 126}, ++{245, 70, 130}, ++{248, 68, 131}, ++{192, 101, 110}, ++{198, 97, 112}, ++{206, 93, 115}, ++{215, 87, 119}, ++{225, 82, 123}, ++{235, 76, 127}, ++{247, 70, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{198, 97, 112}, ++{206, 93, 115}, ++{215, 87, 119}, ++{225, 82, 123}, ++{235, 76, 127}, ++{247, 70, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{198, 97, 112}, ++{206, 93, 115}, ++{215, 87, 119}, ++{225, 82, 123}, ++{235, 76, 127}, ++{247, 70, 130}, ++{249, 69, 131}, ++{192, 101, 110}, ++{198, 97, 112}, ++{206, 93, 115}, ++{215, 87, 119}, ++{225, 82, 123}, ++{235, 76, 127}, ++{247, 70, 130}, ++{249, 69, 131}, ++{129, 64, 84}, ++{139, 65, 90}, ++{151, 64, 96}, ++{165, 62, 102}, ++{180, 59, 109}, ++{194, 55, 115}, ++{208, 51, 120}, ++{212, 50, 122}, ++{129, 64, 84}, ++{139, 65, 90}, ++{152, 64, 96}, ++{165, 62, 102}, ++{180, 59, 109}, ++{194, 55, 115}, ++{208, 51, 120}, ++{212, 50, 122}, ++{130, 65, 85}, ++{140, 65, 90}, ++{152, 64, 96}, ++{166, 62, 103}, ++{180, 59, 109}, ++{194, 55, 115}, ++{209, 51, 120}, ++{212, 50, 122}, ++{131, 66, 85}, ++{140, 66, 90}, ++{153, 65, 96}, ++{166, 63, 103}, ++{180, 59, 109}, ++{195, 56, 115}, ++{209, 51, 120}, ++{212, 50, 122}, ++{132, 67, 86}, ++{141, 67, 91}, ++{153, 65, 97}, ++{167, 63, 103}, ++{181, 60, 109}, ++{195, 56, 115}, ++{209, 52, 121}, ++{213, 51, 122}, ++{133, 68, 86}, ++{142, 68, 91}, ++{155, 66, 97}, ++{168, 64, 103}, ++{182, 60, 109}, ++{196, 56, 115}, ++{210, 52, 121}, ++{214, 51, 122}, ++{134, 69, 87}, ++{144, 69, 92}, ++{156, 67, 98}, ++{169, 64, 104}, ++{183, 61, 110}, ++{197, 57, 115}, ++{211, 53, 121}, ++{214, 51, 122}, ++{136, 71, 88}, ++{145, 70, 92}, ++{157, 68, 98}, ++{170, 65, 104}, ++{184, 61, 110}, ++{198, 57, 116}, ++{212, 53, 121}, ++{215, 52, 122}, ++{138, 72, 88}, ++{147, 71, 93}, ++{159, 69, 99}, ++{171, 66, 104}, ++{185, 62, 110}, ++{199, 58, 116}, ++{213, 54, 121}, ++{216, 52, 123}, ++{140, 74, 89}, ++{149, 72, 94}, ++{160, 70, 99}, ++{173, 67, 105}, ++{186, 63, 111}, ++{200, 59, 116}, ++{214, 54, 122}, ++{217, 53, 123}, ++{142, 75, 90}, ++{151, 74, 94}, ++{162, 71, 100}, ++{175, 68, 105}, ++{188, 64, 111}, ++{201, 59, 117}, ++{215, 55, 122}, ++{218, 54, 123}, ++{145, 77, 91}, ++{153, 75, 95}, ++{164, 72, 100}, ++{176, 69, 106}, ++{189, 65, 112}, ++{203, 60, 117}, ++{216, 55, 122}, ++{220, 54, 123}, ++{147, 79, 92}, ++{155, 77, 96}, ++{166, 73, 101}, ++{178, 70, 107}, ++{191, 65, 112}, ++{204, 61, 117}, ++{218, 56, 122}, ++{221, 55, 124}, ++{150, 80, 93}, ++{157, 78, 97}, ++{168, 75, 102}, ++{180, 71, 107}, ++{193, 66, 113}, ++{206, 62, 118}, ++{219, 57, 123}, ++{222, 56, 124}, ++{152, 82, 94}, ++{160, 79, 98}, ++{170, 76, 103}, ++{182, 72, 108}, ++{195, 67, 113}, ++{207, 63, 118}, ++{221, 58, 123}, ++{224, 56, 124}, ++{155, 83, 95}, ++{162, 81, 99}, ++{173, 77, 103}, ++{184, 73, 108}, ++{196, 68, 114}, ++{209, 63, 119}, ++{222, 58, 123}, ++{225, 57, 125}, ++{158, 85, 96}, ++{165, 82, 100}, ++{175, 78, 104}, ++{186, 74, 109}, ++{198, 69, 114}, ++{211, 64, 119}, ++{224, 59, 124}, ++{227, 58, 125}, ++{161, 86, 97}, ++{168, 83, 101}, ++{178, 80, 105}, ++{189, 75, 110}, ++{201, 70, 115}, ++{213, 65, 119}, ++{226, 60, 124}, ++{229, 59, 125}, ++{164, 88, 99}, ++{171, 85, 102}, ++{180, 81, 106}, ++{191, 76, 110}, ++{203, 71, 115}, ++{215, 66, 120}, ++{227, 61, 125}, ++{231, 60, 126}, ++{167, 89, 100}, ++{173, 86, 103}, ++{183, 82, 107}, ++{193, 77, 111}, ++{205, 72, 116}, ++{217, 67, 120}, ++{229, 62, 125}, ++{233, 60, 126}, ++{170, 90, 101}, ++{176, 87, 104}, ++{185, 83, 108}, ++{196, 78, 112}, ++{207, 73, 116}, ++{219, 68, 121}, ++{231, 63, 125}, ++{234, 61, 127}, ++{173, 92, 102}, ++{179, 89, 105}, ++{188, 84, 108}, ++{198, 79, 113}, ++{210, 74, 117}, ++{221, 69, 121}, ++{233, 64, 126}, ++{236, 62, 127}, ++{176, 93, 103}, ++{182, 90, 106}, ++{191, 85, 109}, ++{201, 81, 113}, ++{212, 75, 118}, ++{224, 70, 122}, ++{236, 64, 126}, ++{239, 63, 127}, ++{179, 94, 104}, ++{185, 91, 106}, ++{194, 87, 110}, ++{204, 82, 114}, ++{215, 76, 118}, ++{226, 71, 122}, ++{238, 65, 127}, ++{241, 64, 128}, ++{183, 95, 105}, ++{189, 92, 107}, ++{197, 88, 111}, ++{206, 83, 115}, ++{217, 77, 119}, ++{228, 72, 123}, ++{240, 66, 127}, ++{243, 65, 128}, ++{186, 96, 106}, ++{192, 93, 108}, ++{200, 89, 112}, ++{209, 84, 115}, ++{220, 78, 119}, ++{231, 73, 123}, ++{242, 67, 128}, ++{245, 66, 129}, ++{189, 97, 107}, ++{195, 94, 109}, ++{203, 90, 112}, ++{212, 85, 116}, ++{222, 79, 120}, ++{233, 74, 124}, ++{244, 68, 128}, ++{247, 67, 129}, ++{192, 98, 108}, ++{198, 95, 110}, ++{206, 91, 113}, ++{215, 86, 117}, ++{225, 80, 121}, ++{236, 75, 125}, ++{247, 69, 128}, ++{250, 67, 129}, ++{194, 99, 108}, ++{200, 96, 111}, ++{207, 91, 114}, ++{216, 86, 117}, ++{226, 81, 121}, ++{237, 75, 125}, ++{248, 69, 129}, ++{251, 68, 130}, ++{194, 99, 108}, ++{200, 96, 111}, ++{207, 91, 114}, ++{216, 86, 117}, ++{226, 81, 121}, ++{237, 75, 125}, ++{248, 69, 129}, ++{251, 68, 130}, ++{194, 99, 108}, ++{200, 96, 111}, ++{207, 91, 114}, ++{216, 86, 117}, ++{226, 81, 121}, ++{237, 75, 125}, ++{248, 69, 129}, ++{251, 68, 130}, ++{194, 99, 108}, ++{200, 96, 111}, ++{207, 91, 114}, ++{216, 86, 117}, ++{226, 81, 121}, ++{237, 75, 125}, ++{248, 69, 129}, ++{251, 68, 130}, ++{132, 62, 82}, ++{141, 63, 88}, ++{154, 62, 94}, ++{167, 60, 100}, ++{181, 57, 107}, ++{196, 54, 113}, ++{210, 50, 118}, ++{213, 49, 120}, ++{132, 62, 82}, ++{142, 63, 88}, ++{154, 62, 94}, ++{168, 60, 100}, ++{182, 57, 107}, ++{196, 54, 113}, ++{210, 50, 118}, ++{213, 49, 120}, ++{132, 63, 83}, ++{142, 63, 88}, ++{154, 62, 94}, ++{168, 60, 100}, ++{182, 58, 107}, ++{196, 54, 113}, ++{210, 50, 118}, ++{214, 49, 120}, ++{133, 63, 83}, ++{143, 64, 88}, ++{155, 63, 94}, ++{168, 61, 101}, ++{182, 58, 107}, ++{196, 54, 113}, ++{211, 50, 118}, ++{214, 49, 120}, ++{134, 64, 84}, ++{144, 64, 89}, ++{156, 63, 95}, ++{169, 61, 101}, ++{183, 58, 107}, ++{197, 55, 113}, ++{211, 51, 119}, ++{215, 50, 120}, ++{136, 65, 84}, ++{145, 65, 89}, ++{157, 64, 95}, ++{170, 62, 101}, ++{184, 59, 107}, ++{198, 55, 113}, ++{212, 51, 119}, ++{215, 50, 120}, ++{137, 67, 85}, ++{146, 66, 90}, ++{158, 65, 95}, ++{171, 63, 102}, ++{185, 59, 108}, ++{199, 56, 113}, ++{212, 51, 119}, ++{216, 50, 120}, ++{139, 68, 86}, ++{148, 68, 90}, ++{159, 66, 96}, ++{172, 63, 102}, ++{186, 60, 108}, ++{200, 56, 114}, ++{213, 52, 119}, ++{217, 51, 120}, ++{141, 70, 86}, ++{149, 69, 91}, ++{161, 67, 97}, ++{174, 64, 102}, ++{187, 61, 108}, ++{201, 57, 114}, ++{214, 52, 119}, ++{218, 51, 121}, ++{143, 71, 87}, ++{151, 70, 92}, ++{162, 68, 97}, ++{175, 65, 103}, ++{188, 61, 109}, ++{202, 57, 114}, ++{215, 53, 120}, ++{219, 52, 121}, ++{145, 73, 88}, ++{153, 72, 92}, ++{164, 69, 98}, ++{177, 66, 103}, ++{190, 62, 109}, ++{203, 58, 115}, ++{217, 54, 120}, ++{220, 53, 121}, ++{147, 75, 89}, ++{155, 73, 93}, ++{166, 70, 98}, ++{178, 67, 104}, ++{191, 63, 110}, ++{204, 59, 115}, ++{218, 54, 120}, ++{221, 53, 121}, ++{149, 76, 90}, ++{157, 74, 94}, ++{168, 72, 99}, ++{180, 68, 105}, ++{193, 64, 110}, ++{206, 60, 115}, ++{219, 55, 120}, ++{223, 54, 122}, ++{152, 78, 91}, ++{160, 76, 95}, ++{170, 73, 100}, ++{182, 69, 105}, ++{195, 65, 111}, ++{207, 60, 116}, ++{221, 56, 121}, ++{224, 55, 122}, ++{155, 79, 92}, ++{162, 77, 96}, ++{172, 74, 101}, ++{184, 70, 106}, ++{196, 66, 111}, ++{209, 61, 116}, ++{222, 57, 121}, ++{225, 55, 122}, ++{157, 81, 93}, ++{165, 79, 97}, ++{175, 75, 101}, ++{186, 71, 106}, ++{198, 67, 112}, ++{211, 62, 117}, ++{224, 57, 122}, ++{227, 56, 123}, ++{160, 83, 94}, ++{167, 80, 98}, ++{177, 77, 102}, ++{188, 72, 107}, ++{200, 68, 112}, ++{213, 63, 117}, ++{225, 58, 122}, ++{229, 57, 123}, ++{163, 84, 95}, ++{170, 81, 99}, ++{179, 78, 103}, ++{190, 74, 108}, ++{202, 69, 113}, ++{215, 64, 118}, ++{227, 59, 122}, ++{230, 58, 123}, ++{166, 86, 97}, ++{173, 83, 100}, ++{182, 79, 104}, ++{193, 75, 108}, ++{204, 70, 113}, ++{217, 65, 118}, ++{229, 60, 123}, ++{232, 59, 124}, ++{169, 87, 98}, ++{176, 84, 101}, ++{185, 80, 105}, ++{195, 76, 109}, ++{207, 71, 114}, ++{219, 66, 119}, ++{231, 61, 123}, ++{234, 59, 124}, ++{172, 88, 99}, ++{178, 85, 102}, ++{187, 81, 106}, ++{198, 77, 110}, ++{209, 72, 114}, ++{221, 67, 119}, ++{233, 62, 124}, ++{236, 60, 125}, ++{175, 90, 100}, ++{181, 87, 103}, ++{190, 83, 106}, ++{200, 78, 111}, ++{211, 73, 115}, ++{223, 68, 120}, ++{235, 62, 124}, ++{238, 61, 125}, ++{178, 91, 101}, ++{184, 88, 104}, ++{193, 84, 107}, ++{203, 79, 111}, ++{214, 74, 116}, ++{225, 69, 120}, ++{237, 63, 124}, ++{240, 62, 126}, ++{181, 92, 102}, ++{187, 89, 105}, ++{196, 85, 108}, ++{205, 80, 112}, ++{216, 75, 116}, ++{227, 70, 121}, ++{239, 64, 125}, ++{242, 63, 126}, ++{184, 93, 103}, ++{190, 90, 105}, ++{199, 86, 109}, ++{208, 81, 113}, ++{219, 76, 117}, ++{230, 71, 121}, ++{241, 65, 125}, ++{244, 64, 126}, ++{188, 94, 104}, ++{193, 91, 106}, ++{201, 87, 110}, ++{211, 82, 114}, ++{221, 77, 118}, ++{232, 72, 122}, ++{244, 66, 126}, ++{246, 65, 127}, ++{191, 96, 105}, ++{197, 92, 107}, ++{204, 88, 111}, ++{214, 83, 114}, ++{224, 78, 118}, ++{235, 72, 122}, ++{246, 67, 126}, ++{249, 66, 127}, ++{194, 97, 106}, ++{200, 93, 108}, ++{207, 89, 111}, ++{217, 84, 115}, ++{227, 79, 119}, ++{237, 73, 123}, ++{248, 68, 127}, ++{251, 66, 128}, ++{196, 97, 106}, ++{201, 94, 109}, ++{209, 90, 112}, ++{218, 85, 115}, ++{228, 79, 119}, ++{238, 74, 123}, ++{249, 68, 127}, ++{252, 67, 128}, ++{196, 97, 106}, ++{201, 94, 109}, ++{209, 90, 112}, ++{218, 85, 115}, ++{228, 79, 119}, ++{238, 74, 123}, ++{249, 68, 127}, ++{252, 67, 128}, ++{196, 97, 106}, ++{201, 94, 109}, ++{209, 90, 112}, ++{218, 85, 115}, ++{228, 79, 119}, ++{238, 74, 123}, ++{249, 68, 127}, ++{252, 67, 128}, ++{196, 97, 106}, ++{201, 94, 109}, ++{209, 90, 112}, ++{218, 85, 115}, ++{228, 79, 119}, ++{238, 74, 123}, ++{249, 68, 127}, ++{252, 67, 128}, ++{135, 59, 80}, ++{144, 60, 86}, ++{156, 60, 92}, ++{170, 58, 98}, ++{183, 56, 105}, ++{198, 52, 111}, ++{212, 49, 116}, ++{215, 48, 118}, ++{135, 60, 81}, ++{144, 60, 86}, ++{156, 60, 92}, ++{170, 58, 98}, ++{184, 56, 105}, ++{198, 53, 111}, ++{212, 49, 116}, ++{215, 48, 118}, ++{135, 60, 81}, ++{145, 61, 86}, ++{157, 60, 92}, ++{170, 59, 98}, ++{184, 56, 105}, ++{198, 53, 111}, ++{212, 49, 116}, ++{215, 48, 118}, ++{136, 61, 81}, ++{145, 61, 86}, ++{157, 61, 92}, ++{171, 59, 99}, ++{184, 56, 105}, ++{198, 53, 111}, ++{212, 49, 116}, ++{216, 48, 118}, ++{137, 62, 82}, ++{146, 62, 87}, ++{158, 61, 93}, ++{171, 60, 99}, ++{185, 57, 105}, ++{199, 53, 111}, ++{213, 49, 117}, ++{216, 48, 118}, ++{138, 63, 82}, ++{147, 63, 87}, ++{159, 62, 93}, ++{172, 60, 99}, ++{186, 57, 105}, ++{200, 54, 111}, ++{213, 50, 117}, ++{217, 49, 118}, ++{140, 64, 83}, ++{149, 64, 88}, ++{160, 63, 93}, ++{173, 61, 100}, ++{187, 58, 106}, ++{200, 54, 111}, ++{214, 50, 117}, ++{218, 49, 118}, ++{141, 66, 84}, ++{150, 65, 88}, ++{162, 64, 94}, ++{174, 62, 100}, ++{188, 58, 106}, ++{201, 55, 112}, ++{215, 51, 117}, ++{218, 50, 118}, ++{143, 67, 84}, ++{152, 67, 89}, ++{163, 65, 94}, ++{176, 62, 100}, ++{189, 59, 106}, ++{202, 55, 112}, ++{216, 51, 117}, ++{219, 50, 119}, ++{145, 69, 85}, ++{154, 68, 90}, ++{165, 66, 95}, ++{177, 63, 101}, ++{190, 60, 107}, ++{204, 56, 112}, ++{217, 52, 118}, ++{220, 51, 119}, ++{147, 71, 86}, ++{155, 69, 90}, ++{166, 67, 96}, ++{179, 64, 101}, ++{192, 61, 107}, ++{205, 57, 113}, ++{218, 52, 118}, ++{222, 51, 119}, ++{149, 72, 87}, ++{158, 71, 91}, ++{168, 68, 96}, ++{180, 65, 102}, ++{193, 62, 108}, ++{206, 58, 113}, ++{219, 53, 118}, ++{223, 52, 119}, ++{152, 74, 88}, ++{160, 72, 92}, ++{170, 70, 97}, ++{182, 66, 103}, ++{195, 63, 108}, ++{208, 58, 113}, ++{221, 54, 119}, ++{224, 53, 120}, ++{154, 76, 89}, ++{162, 74, 93}, ++{172, 71, 98}, ++{184, 67, 103}, ++{196, 63, 109}, ++{209, 59, 114}, ++{222, 55, 119}, ++{226, 53, 120}, ++{157, 77, 90}, ++{164, 75, 94}, ++{174, 72, 99}, ++{186, 69, 104}, ++{198, 64, 109}, ++{211, 60, 114}, ++{224, 55, 119}, ++{227, 54, 120}, ++{160, 79, 91}, ++{167, 77, 95}, ++{177, 73, 99}, ++{188, 70, 104}, ++{200, 65, 110}, ++{213, 61, 115}, ++{225, 56, 120}, ++{229, 55, 121}, ++{162, 80, 92}, ++{169, 78, 96}, ++{179, 75, 100}, ++{190, 71, 105}, ++{202, 66, 110}, ++{214, 62, 115}, ++{227, 57, 120}, ++{230, 56, 121}, ++{165, 82, 94}, ++{172, 79, 97}, ++{181, 76, 101}, ++{192, 72, 106}, ++{204, 67, 111}, ++{216, 63, 116}, ++{229, 58, 120}, ++{232, 57, 122}, ++{168, 83, 95}, ++{175, 81, 98}, ++{184, 77, 102}, ++{195, 73, 107}, ++{206, 68, 111}, ++{218, 64, 116}, ++{231, 59, 121}, ++{234, 57, 122}, ++{171, 85, 96}, ++{178, 82, 99}, ++{187, 79, 103}, ++{197, 74, 107}, ++{208, 70, 112}, ++{220, 65, 117}, ++{232, 60, 121}, ++{236, 58, 122}, ++{174, 86, 97}, ++{180, 84, 100}, ++{189, 80, 104}, ++{200, 75, 108}, ++{211, 71, 113}, ++{222, 66, 117}, ++{234, 61, 122}, ++{237, 59, 123}, ++{177, 88, 98}, ++{183, 85, 101}, ++{192, 81, 104}, ++{202, 76, 109}, ++{213, 72, 113}, ++{225, 67, 118}, ++{236, 61, 122}, ++{239, 60, 123}, ++{180, 89, 99}, ++{186, 86, 102}, ++{195, 82, 105}, ++{205, 78, 109}, ++{215, 73, 114}, ++{227, 68, 118}, ++{238, 62, 123}, ++{241, 61, 124}, ++{183, 90, 100}, ++{189, 87, 103}, ++{198, 83, 106}, ++{207, 79, 110}, ++{218, 74, 114}, ++{229, 68, 119}, ++{241, 63, 123}, ++{244, 62, 124}, ++{186, 91, 101}, ++{192, 88, 104}, ++{200, 84, 107}, ++{210, 80, 111}, ++{220, 75, 115}, ++{231, 69, 119}, ++{243, 64, 124}, ++{246, 63, 125}, ++{190, 93, 102}, ++{195, 90, 105}, ++{203, 85, 108}, ++{213, 81, 112}, ++{223, 76, 116}, ++{234, 70, 120}, ++{245, 65, 124}, ++{248, 64, 125}, ++{193, 94, 103}, ++{198, 91, 105}, ++{206, 87, 109}, ++{215, 82, 112}, ++{225, 77, 116}, ++{236, 71, 120}, ++{247, 66, 125}, ++{250, 65, 126}, ++{196, 95, 104}, ++{202, 92, 106}, ++{209, 88, 110}, ++{218, 83, 113}, ++{228, 78, 117}, ++{239, 72, 121}, ++{250, 67, 125}, ++{252, 65, 126}, ++{198, 95, 105}, ++{203, 92, 107}, ++{211, 88, 110}, ++{220, 83, 114}, ++{229, 78, 117}, ++{240, 73, 121}, ++{251, 67, 125}, ++{254, 66, 126}, ++{198, 95, 105}, ++{203, 92, 107}, ++{211, 88, 110}, ++{220, 83, 114}, ++{229, 78, 117}, ++{240, 73, 121}, ++{251, 67, 125}, ++{254, 66, 126}, ++{198, 95, 105}, ++{203, 92, 107}, ++{211, 88, 110}, ++{220, 83, 114}, ++{229, 78, 117}, ++{240, 73, 121}, ++{251, 67, 125}, ++{254, 66, 126}, ++{198, 95, 105}, ++{203, 92, 107}, ++{211, 88, 110}, ++{220, 83, 114}, ++{229, 78, 117}, ++{240, 73, 121}, ++{251, 67, 125}, ++{254, 66, 126}, ++{137, 57, 79}, ++{147, 58, 84}, ++{159, 58, 90}, ++{172, 57, 96}, ++{185, 54, 102}, ++{199, 51, 109}, ++{213, 48, 114}, ++{217, 47, 116}, ++{138, 57, 79}, ++{147, 58, 84}, ++{159, 58, 90}, ++{172, 57, 96}, ++{186, 54, 103}, ++{199, 51, 109}, ++{213, 48, 114}, ++{217, 47, 116}, ++{138, 58, 79}, ++{147, 59, 84}, ++{159, 58, 90}, ++{172, 57, 96}, ++{186, 54, 103}, ++{200, 51, 109}, ++{214, 48, 114}, ++{217, 47, 116}, ++{139, 59, 79}, ++{148, 59, 84}, ++{160, 59, 90}, ++{173, 57, 97}, ++{186, 55, 103}, ++{200, 52, 109}, ++{214, 48, 114}, ++{217, 47, 116}, ++{140, 59, 80}, ++{149, 60, 85}, ++{160, 59, 91}, ++{173, 58, 97}, ++{187, 55, 103}, ++{201, 52, 109}, ++{215, 48, 115}, ++{218, 47, 116}, ++{141, 61, 80}, ++{150, 61, 85}, ++{161, 60, 91}, ++{174, 58, 97}, ++{188, 56, 103}, ++{201, 52, 109}, ++{215, 49, 115}, ++{219, 48, 116}, ++{142, 62, 81}, ++{151, 62, 86}, ++{163, 61, 91}, ++{175, 59, 97}, ++{189, 56, 104}, ++{202, 53, 109}, ++{216, 49, 115}, ++{219, 48, 116}, ++{144, 63, 82}, ++{153, 63, 86}, ++{164, 62, 92}, ++{176, 60, 98}, ++{190, 57, 104}, ++{203, 53, 110}, ++{217, 50, 115}, ++{220, 49, 116}, ++{146, 65, 83}, ++{154, 64, 87}, ++{165, 63, 92}, ++{178, 61, 98}, ++{191, 58, 104}, ++{204, 54, 110}, ++{218, 50, 115}, ++{221, 49, 117}, ++{148, 67, 83}, ++{156, 66, 88}, ++{167, 64, 93}, ++{179, 62, 99}, ++{192, 58, 105}, ++{205, 55, 110}, ++{219, 51, 116}, ++{222, 50, 117}, ++{150, 68, 84}, ++{158, 67, 88}, ++{169, 65, 94}, ++{181, 63, 99}, ++{193, 59, 105}, ++{207, 55, 111}, ++{220, 51, 116}, ++{223, 50, 117}, ++{152, 70, 85}, ++{160, 69, 89}, ++{170, 67, 94}, ++{182, 64, 100}, ++{195, 60, 106}, ++{208, 56, 111}, ++{221, 52, 116}, ++{224, 51, 118}, ++{154, 72, 86}, ++{162, 70, 90}, ++{172, 68, 95}, ++{184, 65, 101}, ++{197, 61, 106}, ++{209, 57, 111}, ++{222, 53, 117}, ++{226, 52, 118}, ++{157, 73, 87}, ++{164, 72, 91}, ++{174, 69, 96}, ++{186, 66, 101}, ++{198, 62, 107}, ++{211, 58, 112}, ++{224, 53, 117}, ++{227, 52, 118}, ++{159, 75, 88}, ++{167, 73, 92}, ++{177, 70, 97}, ++{188, 67, 102}, ++{200, 63, 107}, ++{213, 59, 112}, ++{225, 54, 117}, ++{229, 53, 119}, ++{162, 77, 89}, ++{169, 75, 93}, ++{179, 72, 97}, ++{190, 68, 103}, ++{202, 64, 108}, ++{214, 60, 113}, ++{227, 55, 118}, ++{230, 54, 119}, ++{165, 78, 91}, ++{172, 76, 94}, ++{181, 73, 98}, ++{192, 69, 103}, ++{204, 65, 108}, ++{216, 61, 113}, ++{229, 56, 118}, ++{232, 55, 119}, ++{167, 80, 92}, ++{174, 77, 95}, ++{183, 74, 99}, ++{194, 70, 104}, ++{206, 66, 109}, ++{218, 61, 114}, ++{230, 57, 119}, ++{233, 56, 120}, ++{170, 81, 93}, ++{177, 79, 96}, ++{186, 75, 100}, ++{197, 71, 105}, ++{208, 67, 109}, ++{220, 62, 114}, ++{232, 58, 119}, ++{235, 56, 120}, ++{173, 83, 94}, ++{180, 80, 97}, ++{189, 77, 101}, ++{199, 73, 105}, ++{210, 68, 110}, ++{222, 63, 115}, ++{234, 58, 119}, ++{237, 57, 121}, ++{176, 84, 95}, ++{182, 82, 98}, ++{191, 78, 102}, ++{201, 74, 106}, ++{212, 69, 111}, ++{224, 64, 115}, ++{236, 59, 120}, ++{239, 58, 121}, ++{179, 86, 96}, ++{185, 83, 99}, ++{194, 79, 103}, ++{204, 75, 107}, ++{215, 70, 111}, ++{226, 65, 116}, ++{238, 60, 120}, ++{241, 59, 121}, ++{182, 87, 97}, ++{188, 84, 100}, ++{197, 80, 103}, ++{206, 76, 108}, ++{217, 71, 112}, ++{228, 66, 116}, ++{240, 61, 121}, ++{243, 60, 122}, ++{185, 88, 98}, ++{191, 85, 101}, ++{199, 82, 104}, ++{209, 77, 108}, ++{219, 72, 113}, ++{231, 67, 117}, ++{242, 62, 121}, ++{245, 61, 122}, ++{188, 90, 99}, ++{194, 87, 102}, ++{202, 83, 105}, ++{212, 78, 109}, ++{222, 73, 113}, ++{233, 68, 118}, ++{244, 63, 122}, ++{247, 62, 123}, ++{192, 91, 100}, ++{197, 88, 103}, ++{205, 84, 106}, ++{214, 79, 110}, ++{224, 74, 114}, ++{235, 69, 118}, ++{246, 64, 122}, ++{249, 63, 123}, ++{195, 92, 101}, ++{200, 89, 104}, ++{208, 85, 107}, ++{217, 80, 111}, ++{227, 75, 115}, ++{238, 70, 119}, ++{249, 65, 123}, ++{252, 64, 124}, ++{198, 93, 102}, ++{203, 90, 105}, ++{211, 86, 108}, ++{220, 81, 111}, ++{230, 76, 115}, ++{240, 71, 119}, ++{251, 66, 123}, ++{254, 64, 124}, ++{200, 94, 103}, ++{205, 91, 105}, ++{212, 87, 108}, ++{221, 82, 112}, ++{231, 77, 116}, ++{241, 72, 120}, ++{252, 66, 124}, ++{255, 65, 124}, ++{200, 94, 103}, ++{205, 91, 105}, ++{212, 87, 108}, ++{221, 82, 112}, ++{231, 77, 116}, ++{241, 72, 120}, ++{252, 66, 124}, ++{255, 65, 124}, ++{200, 94, 103}, ++{205, 91, 105}, ++{212, 87, 108}, ++{221, 82, 112}, ++{231, 77, 116}, ++{241, 72, 120}, ++{252, 66, 124}, ++{255, 65, 124}, ++{200, 94, 103}, ++{205, 91, 105}, ++{212, 87, 108}, ++{221, 82, 112}, ++{231, 77, 116}, ++{241, 72, 120}, ++{252, 66, 124}, ++{255, 65, 124}, ++{140, 55, 77}, ++{149, 56, 82}, ++{161, 56, 88}, ++{174, 55, 94}, ++{187, 53, 100}, ++{201, 50, 107}, ++{215, 46, 112}, ++{218, 45, 114}, ++{140, 55, 77}, ++{149, 56, 82}, ++{161, 56, 88}, ++{174, 55, 94}, ++{188, 53, 101}, ++{201, 50, 107}, ++{215, 46, 112}, ++{219, 45, 114}, ++{141, 55, 77}, ++{150, 56, 82}, ++{161, 56, 88}, ++{174, 55, 94}, ++{188, 53, 101}, ++{202, 50, 107}, ++{215, 47, 112}, ++{219, 46, 114}, ++{141, 56, 77}, ++{150, 57, 82}, ++{162, 57, 88}, ++{175, 56, 95}, ++{188, 53, 101}, ++{202, 50, 107}, ++{216, 47, 112}, ++{219, 46, 114}, ++{142, 57, 78}, ++{151, 58, 83}, ++{163, 57, 89}, ++{176, 56, 95}, ++{189, 54, 101}, ++{203, 51, 107}, ++{216, 47, 113}, ++{220, 46, 114}, ++{144, 58, 78}, ++{152, 59, 83}, ++{164, 58, 89}, ++{176, 57, 95}, ++{190, 54, 101}, ++{203, 51, 107}, ++{217, 47, 113}, ++{220, 46, 114}, ++{145, 60, 79}, ++{154, 60, 84}, ++{165, 59, 89}, ++{177, 57, 95}, ++{191, 55, 102}, ++{204, 52, 107}, ++{218, 48, 113}, ++{221, 47, 114}, ++{147, 61, 80}, ++{155, 61, 84}, ++{166, 60, 90}, ++{179, 58, 96}, ++{192, 55, 102}, ++{205, 52, 108}, ++{218, 48, 113}, ++{222, 47, 115}, ++{148, 63, 81}, ++{157, 62, 85}, ++{168, 61, 91}, ++{180, 59, 96}, ++{193, 56, 102}, ++{206, 53, 108}, ++{219, 49, 113}, ++{223, 48, 115}, ++{150, 64, 82}, ++{158, 64, 86}, ++{169, 62, 91}, ++{181, 60, 97}, ++{194, 57, 103}, ++{207, 53, 108}, ++{220, 49, 114}, ++{224, 48, 115}, ++{152, 66, 82}, ++{160, 65, 87}, ++{171, 63, 92}, ++{183, 61, 97}, ++{195, 58, 103}, ++{208, 54, 109}, ++{222, 50, 114}, ++{225, 49, 115}, ++{154, 68, 83}, ++{162, 66, 87}, ++{173, 65, 92}, ++{184, 62, 98}, ++{197, 59, 104}, ++{210, 55, 109}, ++{223, 51, 114}, ++{226, 50, 116}, ++{157, 69, 84}, ++{164, 68, 88}, ++{174, 66, 93}, ++{186, 63, 99}, ++{198, 60, 104}, ++{211, 56, 109}, ++{224, 52, 115}, ++{227, 50, 116}, ++{159, 71, 85}, ++{166, 69, 89}, ++{176, 67, 94}, ++{188, 64, 99}, ++{200, 60, 105}, ++{213, 57, 110}, ++{226, 52, 115}, ++{229, 51, 116}, ++{162, 73, 86}, ++{169, 71, 90}, ++{179, 68, 95}, ++{190, 65, 100}, ++{202, 61, 105}, ++{214, 57, 110}, ++{227, 53, 115}, ++{230, 52, 117}, ++{164, 74, 88}, ++{171, 72, 91}, ++{181, 70, 96}, ++{192, 66, 101}, ++{204, 62, 106}, ++{216, 58, 111}, ++{229, 54, 116}, ++{232, 53, 117}, ++{167, 76, 89}, ++{174, 74, 92}, ++{183, 71, 96}, ++{194, 68, 101}, ++{206, 64, 106}, ++{218, 59, 111}, ++{230, 55, 116}, ++{233, 54, 117}, ++{170, 78, 90}, ++{176, 75, 93}, ++{186, 72, 97}, ++{196, 69, 102}, ++{208, 65, 107}, ++{220, 60, 112}, ++{232, 56, 117}, ++{235, 54, 118}, ++{172, 79, 91}, ++{179, 77, 94}, ++{188, 74, 98}, ++{198, 70, 103}, ++{210, 66, 108}, ++{222, 61, 112}, ++{234, 56, 117}, ++{237, 55, 118}, ++{175, 81, 92}, ++{182, 78, 95}, ++{190, 75, 99}, ++{201, 71, 103}, ++{212, 67, 108}, ++{224, 62, 113}, ++{236, 57, 118}, ++{239, 56, 119}, ++{178, 82, 93}, ++{184, 80, 96}, ++{193, 76, 100}, ++{203, 72, 104}, ++{214, 68, 109}, ++{226, 63, 113}, ++{237, 58, 118}, ++{240, 57, 119}, ++{181, 84, 94}, ++{187, 81, 97}, ++{196, 77, 101}, ++{206, 73, 105}, ++{216, 69, 109}, ++{228, 64, 114}, ++{239, 59, 119}, ++{242, 58, 120}, ++{184, 85, 95}, ++{190, 82, 98}, ++{198, 79, 102}, ++{208, 74, 106}, ++{219, 70, 110}, ++{230, 65, 115}, ++{241, 60, 119}, ++{244, 59, 120}, ++{187, 86, 96}, ++{193, 84, 99}, ++{201, 80, 102}, ++{211, 76, 106}, ++{221, 71, 111}, ++{232, 66, 115}, ++{244, 61, 119}, ++{246, 60, 121}, ++{190, 88, 97}, ++{196, 85, 100}, ++{204, 81, 103}, ++{213, 77, 107}, ++{224, 72, 111}, ++{234, 67, 116}, ++{246, 62, 120}, ++{249, 61, 121}, ++{193, 89, 98}, ++{199, 86, 101}, ++{207, 82, 104}, ++{216, 78, 108}, ++{226, 73, 112}, ++{237, 68, 116}, ++{248, 63, 120}, ++{251, 62, 122}, ++{197, 90, 99}, ++{202, 87, 102}, ++{210, 83, 105}, ++{219, 79, 109}, ++{229, 74, 113}, ++{239, 69, 117}, ++{250, 64, 121}, ++{253, 62, 122}, ++{200, 91, 100}, ++{205, 88, 103}, ++{213, 84, 106}, ++{221, 80, 110}, ++{231, 75, 113}, ++{242, 70, 117}, ++{252, 65, 122}, ++{255, 63, 123}, ++{201, 92, 101}, ++{207, 89, 103}, ++{214, 85, 106}, ++{223, 80, 110}, ++{233, 76, 114}, ++{243, 70, 118}, ++{254, 65, 122}, ++{255, 64, 123}, ++{201, 92, 101}, ++{207, 89, 103}, ++{214, 85, 106}, ++{223, 80, 110}, ++{233, 76, 114}, ++{243, 70, 118}, ++{254, 65, 122}, ++{255, 64, 123}, ++{201, 92, 101}, ++{207, 89, 103}, ++{214, 85, 106}, ++{223, 80, 110}, ++{233, 76, 114}, ++{243, 70, 118}, ++{254, 65, 122}, ++{255, 64, 123}, ++{201, 92, 101}, ++{207, 89, 103}, ++{214, 85, 106}, ++{223, 80, 110}, ++{233, 76, 114}, ++{243, 70, 118}, ++{254, 65, 122}, ++{255, 64, 123}, ++{143, 52, 75}, ++{152, 54, 80}, ++{163, 54, 86}, ++{176, 53, 92}, ++{189, 51, 99}, ++{203, 48, 105}, ++{217, 45, 110}, ++{220, 44, 112}, ++{143, 53, 75}, ++{152, 54, 80}, ++{163, 54, 86}, ++{176, 53, 92}, ++{190, 51, 99}, ++{203, 48, 105}, ++{217, 45, 110}, ++{220, 44, 112}, ++{143, 53, 75}, ++{152, 54, 80}, ++{164, 54, 86}, ++{177, 53, 92}, ++{190, 51, 99}, ++{203, 49, 105}, ++{217, 45, 110}, ++{220, 44, 112}, ++{144, 54, 76}, ++{153, 55, 80}, ++{164, 55, 86}, ++{177, 54, 93}, ++{190, 52, 99}, ++{204, 49, 105}, ++{217, 46, 111}, ++{221, 45, 112}, ++{145, 55, 76}, ++{154, 56, 81}, ++{165, 55, 87}, ++{178, 54, 93}, ++{191, 52, 99}, ++{204, 49, 105}, ++{218, 46, 111}, ++{221, 45, 112}, ++{146, 56, 77}, ++{155, 57, 81}, ++{166, 56, 87}, ++{179, 55, 93}, ++{192, 53, 99}, ++{205, 50, 105}, ++{219, 46, 111}, ++{222, 45, 112}, ++{148, 57, 77}, ++{156, 58, 82}, ++{167, 57, 88}, ++{179, 56, 94}, ++{193, 53, 100}, ++{206, 50, 105}, ++{219, 47, 111}, ++{223, 46, 112}, ++{149, 59, 78}, ++{157, 59, 82}, ++{168, 58, 88}, ++{181, 56, 94}, ++{194, 54, 100}, ++{207, 51, 106}, ++{220, 47, 111}, ++{223, 46, 113}, ++{151, 60, 79}, ++{159, 60, 83}, ++{170, 59, 89}, ++{182, 57, 94}, ++{195, 55, 100}, ++{208, 51, 106}, ++{221, 48, 112}, ++{224, 47, 113}, ++{153, 62, 80}, ++{161, 61, 84}, ++{171, 60, 89}, ++{183, 58, 95}, ++{196, 55, 101}, ++{209, 52, 106}, ++{222, 48, 112}, ++{225, 47, 113}, ++{155, 64, 81}, ++{163, 63, 85}, ++{173, 61, 90}, ++{185, 59, 95}, ++{197, 56, 101}, ++{210, 53, 107}, ++{223, 49, 112}, ++{227, 48, 113}, ++{157, 65, 82}, ++{164, 64, 85}, ++{175, 63, 91}, ++{186, 60, 96}, ++{199, 57, 102}, ++{211, 53, 107}, ++{224, 50, 112}, ++{228, 49, 114}, ++{159, 67, 83}, ++{167, 66, 86}, ++{177, 64, 91}, ++{188, 61, 97}, ++{200, 58, 102}, ++{213, 54, 108}, ++{226, 50, 113}, ++{229, 49, 114}, ++{161, 69, 84}, ++{169, 67, 87}, ++{179, 65, 92}, ++{190, 62, 97}, ++{202, 59, 103}, ++{214, 55, 108}, ++{227, 51, 113}, ++{230, 50, 114}, ++{164, 70, 85}, ++{171, 69, 88}, ++{181, 67, 93}, ++{192, 64, 98}, ++{204, 60, 103}, ++{216, 56, 108}, ++{229, 52, 114}, ++{232, 51, 115}, ++{166, 72, 86}, ++{173, 70, 89}, ++{183, 68, 94}, ++{194, 65, 99}, ++{206, 61, 104}, ++{218, 57, 109}, ++{230, 53, 114}, ++{233, 52, 115}, ++{169, 74, 87}, ++{176, 72, 90}, ++{185, 69, 94}, ++{196, 66, 99}, ++{207, 62, 104}, ++{219, 58, 109}, ++{232, 54, 114}, ++{235, 52, 116}, ++{172, 75, 88}, ++{178, 73, 91}, ++{188, 71, 95}, ++{198, 67, 100}, ++{209, 63, 105}, ++{221, 59, 110}, ++{234, 54, 115}, ++{237, 53, 116}, ++{174, 77, 89}, ++{181, 75, 92}, ++{190, 72, 96}, ++{200, 68, 101}, ++{211, 64, 106}, ++{223, 60, 110}, ++{235, 55, 115}, ++{238, 54, 116}, ++{177, 79, 90}, ++{184, 76, 93}, ++{192, 73, 97}, ++{203, 69, 102}, ++{214, 65, 106}, ++{225, 61, 111}, ++{237, 56, 116}, ++{240, 55, 117}, ++{180, 80, 91}, ++{186, 78, 94}, ++{195, 74, 98}, ++{205, 71, 102}, ++{216, 66, 107}, ++{227, 62, 112}, ++{239, 57, 116}, ++{242, 56, 117}, ++{183, 82, 92}, ++{189, 79, 95}, ++{198, 76, 99}, ++{207, 72, 103}, ++{218, 67, 108}, ++{229, 63, 112}, ++{241, 58, 117}, ++{244, 57, 118}, ++{186, 83, 93}, ++{192, 80, 96}, ++{200, 77, 100}, ++{210, 73, 104}, ++{220, 68, 108}, ++{232, 64, 113}, ++{243, 59, 117}, ++{246, 58, 118}, ++{189, 84, 94}, ++{195, 82, 97}, ++{203, 78, 101}, ++{212, 74, 105}, ++{223, 70, 109}, ++{234, 65, 113}, ++{245, 60, 118}, ++{248, 59, 119}, ++{192, 86, 95}, ++{198, 83, 98}, ++{206, 79, 101}, ++{215, 75, 105}, ++{225, 71, 110}, ++{236, 66, 114}, ++{247, 61, 118}, ++{250, 60, 119}, ++{195, 87, 97}, ++{201, 84, 99}, ++{209, 81, 102}, ++{218, 76, 106}, ++{228, 72, 110}, ++{238, 67, 114}, ++{249, 62, 119}, ++{252, 60, 120}, ++{198, 88, 98}, ++{204, 85, 100}, ++{211, 82, 103}, ++{220, 77, 107}, ++{230, 73, 111}, ++{241, 68, 115}, ++{252, 63, 119}, ++{254, 61, 120}, ++{202, 89, 99}, ++{207, 87, 101}, ++{214, 83, 104}, ++{223, 78, 108}, ++{233, 74, 112}, ++{243, 69, 116}, ++{254, 64, 120}, ++{255, 62, 121}, ++{203, 90, 99}, ++{209, 87, 101}, ++{216, 83, 105}, ++{224, 79, 108}, ++{234, 74, 112}, ++{244, 69, 116}, ++{255, 64, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{209, 87, 101}, ++{216, 83, 105}, ++{224, 79, 108}, ++{234, 74, 112}, ++{244, 69, 116}, ++{255, 64, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{209, 87, 101}, ++{216, 83, 105}, ++{224, 79, 108}, ++{234, 74, 112}, ++{244, 69, 116}, ++{255, 64, 120}, ++{255, 63, 121}, ++{203, 90, 99}, ++{209, 87, 101}, ++{216, 83, 105}, ++{224, 79, 108}, ++{234, 74, 112}, ++{244, 69, 116}, ++{255, 64, 120}, ++{255, 63, 121}, ++{146, 50, 73}, ++{154, 51, 78}, ++{166, 52, 84}, ++{178, 51, 90}, ++{191, 49, 97}, ++{205, 47, 103}, ++{218, 44, 108}, ++{222, 43, 110}, ++{146, 50, 73}, ++{154, 52, 78}, ++{166, 52, 84}, ++{178, 51, 90}, ++{192, 50, 97}, ++{205, 47, 103}, ++{219, 44, 108}, ++{222, 43, 110}, ++{146, 51, 74}, ++{155, 52, 78}, ++{166, 52, 84}, ++{179, 52, 90}, ++{192, 50, 97}, ++{205, 47, 103}, ++{219, 44, 109}, ++{222, 43, 110}, ++{147, 52, 74}, ++{155, 53, 79}, ++{167, 53, 84}, ++{179, 52, 91}, ++{192, 50, 97}, ++{206, 47, 103}, ++{219, 44, 109}, ++{223, 43, 110}, ++{148, 52, 74}, ++{156, 53, 79}, ++{167, 53, 85}, ++{180, 52, 91}, ++{193, 50, 97}, ++{206, 48, 103}, ++{220, 45, 109}, ++{223, 44, 110}, ++{149, 54, 75}, ++{157, 54, 79}, ++{168, 54, 85}, ++{181, 53, 91}, ++{194, 51, 97}, ++{207, 48, 103}, ++{220, 45, 109}, ++{224, 44, 110}, ++{150, 55, 76}, ++{159, 55, 80}, ++{169, 55, 86}, ++{182, 54, 92}, ++{194, 52, 98}, ++{208, 49, 104}, ++{221, 45, 109}, ++{224, 44, 111}, ++{152, 56, 76}, ++{160, 57, 81}, ++{171, 56, 86}, ++{183, 55, 92}, ++{195, 52, 98}, ++{209, 49, 104}, ++{222, 46, 109}, ++{225, 45, 111}, ++{153, 58, 77}, ++{161, 58, 81}, ++{172, 57, 87}, ++{184, 55, 92}, ++{197, 53, 98}, ++{210, 50, 104}, ++{223, 46, 110}, ++{226, 45, 111}, ++{155, 60, 78}, ++{163, 59, 82}, ++{174, 58, 87}, ++{185, 56, 93}, ++{198, 54, 99}, ++{211, 51, 104}, ++{224, 47, 110}, ++{227, 46, 111}, ++{157, 61, 79}, ++{165, 61, 83}, ++{175, 59, 88}, ++{187, 57, 94}, ++{199, 55, 99}, ++{212, 51, 105}, ++{225, 48, 110}, ++{228, 47, 112}, ++{159, 63, 80}, ++{167, 62, 84}, ++{177, 61, 89}, ++{188, 58, 94}, ++{201, 56, 100}, ++{213, 52, 105}, ++{226, 48, 111}, ++{229, 47, 112}, ++{161, 65, 81}, ++{169, 64, 84}, ++{179, 62, 89}, ++{190, 60, 95}, ++{202, 56, 100}, ++{215, 53, 106}, ++{227, 49, 111}, ++{231, 48, 112}, ++{164, 66, 82}, ++{171, 65, 85}, ++{181, 63, 90}, ++{192, 61, 95}, ++{204, 57, 101}, ++{216, 54, 106}, ++{229, 50, 111}, ++{232, 49, 113}, ++{166, 68, 83}, ++{173, 67, 86}, ++{183, 65, 91}, ++{194, 62, 96}, ++{206, 58, 101}, ++{218, 55, 107}, ++{230, 51, 112}, ++{233, 50, 113}, ++{169, 70, 84}, ++{176, 68, 87}, ++{185, 66, 92}, ++{196, 63, 97}, ++{207, 59, 102}, ++{219, 56, 107}, ++{232, 51, 112}, ++{235, 50, 113}, ++{171, 72, 85}, ++{178, 70, 88}, ++{187, 67, 93}, ++{198, 64, 97}, ++{209, 61, 103}, ++{221, 57, 108}, ++{233, 52, 113}, ++{237, 51, 114}, ++{174, 73, 86}, ++{181, 71, 89}, ++{190, 69, 93}, ++{200, 65, 98}, ++{211, 62, 103}, ++{223, 57, 108}, ++{235, 53, 113}, ++{238, 52, 114}, ++{177, 75, 87}, ++{183, 73, 90}, ++{192, 70, 94}, ++{202, 67, 99}, ++{213, 63, 104}, ++{225, 58, 109}, ++{237, 54, 113}, ++{240, 53, 115}, ++{179, 76, 88}, ++{186, 74, 91}, ++{194, 71, 95}, ++{204, 68, 100}, ++{215, 64, 104}, ++{227, 59, 109}, ++{239, 55, 114}, ++{242, 54, 115}, ++{182, 78, 89}, ++{188, 76, 92}, ++{197, 73, 96}, ++{207, 69, 100}, ++{218, 65, 105}, ++{229, 60, 110}, ++{241, 56, 114}, ++{244, 55, 116}, ++{185, 79, 90}, ++{191, 77, 93}, ++{200, 74, 97}, ++{209, 70, 101}, ++{220, 66, 106}, ++{231, 61, 110}, ++{243, 57, 115}, ++{245, 56, 116}, ++{188, 81, 91}, ++{194, 79, 94}, ++{202, 75, 98}, ++{212, 71, 102}, ++{222, 67, 106}, ++{233, 62, 111}, ++{245, 58, 115}, ++{247, 57, 117}, ++{191, 82, 93}, ++{197, 80, 95}, ++{205, 77, 99}, ++{214, 73, 103}, ++{224, 68, 107}, ++{235, 63, 112}, ++{247, 59, 116}, ++{249, 57, 117}, ++{194, 84, 94}, ++{200, 81, 96}, ++{208, 78, 100}, ++{217, 74, 104}, ++{227, 69, 108}, ++{238, 64, 112}, ++{249, 60, 116}, ++{252, 58, 118}, ++{197, 85, 95}, ++{203, 82, 97}, ++{210, 79, 100}, ++{219, 75, 104}, ++{229, 70, 108}, ++{240, 65, 113}, ++{251, 61, 117}, ++{254, 59, 118}, ++{200, 86, 96}, ++{206, 84, 98}, ++{213, 80, 101}, ++{222, 76, 105}, ++{232, 71, 109}, ++{242, 66, 113}, ++{253, 62, 118}, ++{255, 60, 119}, ++{204, 88, 97}, ++{209, 85, 99}, ++{216, 81, 102}, ++{225, 77, 106}, ++{234, 72, 110}, ++{245, 67, 114}, ++{255, 62, 118}, ++{255, 61, 119}, ++{205, 88, 97}, ++{210, 85, 100}, ++{218, 82, 103}, ++{226, 78, 106}, ++{236, 73, 110}, ++{246, 68, 114}, ++{255, 63, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 85, 100}, ++{218, 82, 103}, ++{226, 78, 106}, ++{236, 73, 110}, ++{246, 68, 114}, ++{255, 63, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 85, 100}, ++{218, 82, 103}, ++{226, 78, 106}, ++{236, 73, 110}, ++{246, 68, 114}, ++{255, 63, 118}, ++{255, 62, 119}, ++{205, 88, 97}, ++{210, 85, 100}, ++{218, 82, 103}, ++{226, 78, 106}, ++{236, 73, 110}, ++{246, 68, 114}, ++{255, 63, 118}, ++{255, 62, 119}, ++{148, 48, 71}, ++{157, 49, 76}, ++{168, 50, 82}, ++{180, 49, 88}, ++{193, 48, 95}, ++{207, 45, 101}, ++{220, 43, 107}, ++{224, 42, 108}, ++{148, 48, 72}, ++{157, 49, 76}, ++{168, 50, 82}, ++{180, 50, 88}, ++{194, 48, 95}, ++{207, 46, 101}, ++{220, 43, 107}, ++{224, 42, 108}, ++{149, 48, 72}, ++{157, 50, 76}, ++{168, 50, 82}, ++{181, 50, 89}, ++{194, 48, 95}, ++{207, 46, 101}, ++{221, 43, 107}, ++{224, 42, 108}, ++{150, 49, 72}, ++{158, 50, 77}, ++{169, 51, 83}, ++{181, 50, 89}, ++{194, 48, 95}, ++{208, 46, 101}, ++{221, 43, 107}, ++{224, 42, 108}, ++{150, 50, 73}, ++{159, 51, 77}, ++{170, 51, 83}, ++{182, 51, 89}, ++{195, 49, 95}, ++{208, 46, 101}, ++{221, 43, 107}, ++{225, 42, 108}, ++{152, 51, 73}, ++{160, 52, 78}, ++{171, 52, 83}, ++{183, 51, 89}, ++{196, 49, 95}, ++{209, 47, 101}, ++{222, 44, 107}, ++{225, 43, 108}, ++{153, 53, 74}, ++{161, 53, 78}, ++{172, 53, 84}, ++{184, 52, 90}, ++{196, 50, 96}, ++{210, 47, 102}, ++{223, 44, 107}, ++{226, 43, 109}, ++{154, 54, 74}, ++{162, 54, 79}, ++{173, 54, 84}, ++{185, 53, 90}, ++{197, 51, 96}, ++{210, 48, 102}, ++{224, 45, 107}, ++{227, 44, 109}, ++{156, 56, 75}, ++{164, 56, 79}, ++{174, 55, 85}, ++{186, 54, 91}, ++{199, 51, 96}, ++{211, 48, 102}, ++{224, 45, 108}, ++{228, 44, 109}, ++{158, 57, 76}, ++{165, 57, 80}, ++{176, 56, 85}, ++{187, 55, 91}, ++{200, 52, 97}, ++{213, 49, 103}, ++{225, 46, 108}, ++{229, 45, 109}, ++{160, 59, 77}, ++{167, 59, 81}, ++{177, 57, 86}, ++{189, 56, 92}, ++{201, 53, 97}, ++{214, 50, 103}, ++{227, 46, 108}, ++{230, 45, 110}, ++{162, 61, 78}, ++{169, 60, 82}, ++{179, 59, 87}, ++{190, 57, 92}, ++{203, 54, 98}, ++{215, 51, 103}, ++{228, 47, 109}, ++{231, 46, 110}, ++{164, 62, 79}, ++{171, 62, 83}, ++{181, 60, 88}, ++{192, 58, 93}, ++{204, 55, 98}, ++{216, 52, 104}, ++{229, 48, 109}, ++{232, 47, 110}, ++{166, 64, 80}, ++{173, 63, 84}, ++{183, 61, 88}, ++{194, 59, 93}, ++{206, 56, 99}, ++{218, 52, 104}, ++{230, 49, 109}, ++{234, 48, 111}, ++{169, 66, 81}, ++{175, 65, 84}, ++{185, 63, 89}, ++{196, 60, 94}, ++{207, 57, 99}, ++{220, 53, 105}, ++{232, 49, 110}, ++{235, 48, 111}, ++{171, 68, 82}, ++{178, 66, 85}, ++{187, 64, 90}, ++{198, 61, 95}, ++{209, 58, 100}, ++{221, 54, 105}, ++{233, 50, 110}, ++{237, 49, 112}, ++{174, 69, 83}, ++{180, 68, 86}, ++{189, 65, 91}, ++{200, 62, 96}, ++{211, 59, 101}, ++{223, 55, 106}, ++{235, 51, 111}, ++{238, 50, 112}, ++{176, 71, 84}, ++{183, 69, 87}, ++{192, 67, 92}, ++{202, 64, 96}, ++{213, 60, 101}, ++{225, 56, 106}, ++{237, 52, 111}, ++{240, 51, 112}, ++{179, 73, 85}, ++{185, 71, 88}, ++{194, 68, 92}, ++{204, 65, 97}, ++{215, 61, 102}, ++{227, 57, 107}, ++{238, 53, 112}, ++{241, 52, 113}, ++{182, 74, 86}, ++{188, 72, 89}, ++{196, 70, 93}, ++{206, 66, 98}, ++{217, 62, 103}, ++{229, 58, 107}, ++{240, 54, 112}, ++{243, 53, 113}, ++{184, 76, 87}, ++{191, 74, 90}, ++{199, 71, 94}, ++{209, 67, 99}, ++{219, 63, 103}, ++{231, 59, 108}, ++{242, 55, 113}, ++{245, 54, 114}, ++{187, 77, 89}, ++{193, 75, 91}, ++{201, 72, 95}, ++{211, 69, 99}, ++{222, 64, 104}, ++{233, 60, 109}, ++{244, 56, 113}, ++{247, 54, 114}, ++{190, 79, 90}, ++{196, 77, 92}, ++{204, 73, 96}, ++{213, 70, 100}, ++{224, 66, 105}, ++{235, 61, 109}, ++{246, 57, 114}, ++{249, 55, 115}, ++{193, 80, 91}, ++{199, 78, 93}, ++{207, 75, 97}, ++{216, 71, 101}, ++{226, 67, 105}, ++{237, 62, 110}, ++{248, 58, 114}, ++{251, 56, 115}, ++{196, 82, 92}, ++{202, 79, 94}, ++{209, 76, 98}, ++{219, 72, 102}, ++{229, 68, 106}, ++{239, 63, 110}, ++{250, 58, 115}, ++{253, 57, 116}, ++{199, 83, 93}, ++{205, 81, 95}, ++{212, 77, 99}, ++{221, 73, 103}, ++{231, 69, 107}, ++{241, 64, 111}, ++{252, 59, 115}, ++{255, 58, 116}, ++{202, 84, 94}, ++{208, 82, 96}, ++{215, 78, 100}, ++{224, 74, 103}, ++{233, 70, 107}, ++{244, 65, 112}, ++{255, 60, 116}, ++{255, 59, 117}, ++{205, 86, 95}, ++{211, 83, 97}, ++{218, 80, 100}, ++{226, 75, 104}, ++{236, 71, 108}, ++{246, 66, 112}, ++{255, 61, 116}, ++{255, 60, 117}, ++{207, 86, 96}, ++{212, 84, 98}, ++{219, 80, 101}, ++{228, 76, 105}, ++{237, 72, 108}, ++{247, 67, 113}, ++{255, 62, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{212, 84, 98}, ++{219, 80, 101}, ++{228, 76, 105}, ++{237, 72, 108}, ++{247, 67, 113}, ++{255, 62, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{212, 84, 98}, ++{219, 80, 101}, ++{228, 76, 105}, ++{237, 72, 108}, ++{247, 67, 113}, ++{255, 62, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{212, 84, 98}, ++{219, 80, 101}, ++{228, 76, 105}, ++{237, 72, 108}, ++{247, 67, 113}, ++{255, 62, 117}, ++{255, 61, 118}, ++{151, 46, 70}, ++{159, 47, 74}, ++{170, 48, 80}, ++{183, 48, 86}, ++{195, 46, 93}, ++{209, 44, 99}, ++{222, 41, 105}, ++{225, 40, 106}, ++{151, 46, 70}, ++{159, 47, 74}, ++{170, 48, 80}, ++{183, 48, 87}, ++{196, 46, 93}, ++{209, 44, 99}, ++{222, 41, 105}, ++{225, 40, 106}, ++{152, 46, 70}, ++{160, 48, 75}, ++{171, 48, 80}, ++{183, 48, 87}, ++{196, 46, 93}, ++{209, 44, 99}, ++{222, 41, 105}, ++{226, 41, 106}, ++{152, 47, 70}, ++{160, 48, 75}, ++{171, 49, 81}, ++{183, 48, 87}, ++{196, 47, 93}, ++{209, 45, 99}, ++{223, 42, 105}, ++{226, 41, 106}, ++{153, 48, 71}, ++{161, 49, 75}, ++{172, 49, 81}, ++{184, 49, 87}, ++{197, 47, 93}, ++{210, 45, 99}, ++{223, 42, 105}, ++{226, 41, 106}, ++{154, 49, 71}, ++{162, 50, 76}, ++{173, 50, 81}, ++{185, 49, 87}, ++{198, 48, 94}, ++{211, 45, 99}, ++{224, 42, 105}, ++{227, 42, 107}, ++{155, 50, 72}, ++{163, 51, 76}, ++{174, 51, 82}, ++{186, 50, 88}, ++{198, 48, 94}, ++{211, 46, 100}, ++{224, 43, 105}, ++{228, 42, 107}, ++{157, 52, 73}, ++{165, 52, 77}, ++{175, 52, 82}, ++{187, 51, 88}, ++{199, 49, 94}, ++{212, 46, 100}, ++{225, 43, 106}, ++{229, 42, 107}, ++{158, 53, 73}, ++{166, 54, 78}, ++{176, 53, 83}, ++{188, 52, 89}, ++{201, 50, 95}, ++{213, 47, 100}, ++{226, 44, 106}, ++{229, 43, 107}, ++{160, 55, 74}, ++{168, 55, 78}, ++{178, 54, 84}, ++{189, 53, 89}, ++{202, 51, 95}, ++{214, 48, 101}, ++{227, 44, 106}, ++{230, 44, 108}, ++{162, 57, 75}, ++{170, 56, 79}, ++{180, 56, 84}, ++{191, 54, 90}, ++{203, 51, 95}, ++{216, 48, 101}, ++{228, 45, 107}, ++{232, 44, 108}, ++{164, 58, 76}, ++{171, 58, 80}, ++{181, 57, 85}, ++{192, 55, 90}, ++{204, 52, 96}, ++{217, 49, 101}, ++{230, 46, 107}, ++{233, 45, 108}, ++{166, 60, 77}, ++{173, 59, 81}, ++{183, 58, 86}, ++{194, 56, 91}, ++{206, 53, 96}, ++{218, 50, 102}, ++{231, 47, 107}, ++{234, 46, 109}, ++{169, 62, 78}, ++{176, 61, 82}, ++{185, 59, 86}, ++{196, 57, 92}, ++{208, 54, 97}, ++{220, 51, 102}, ++{232, 47, 108}, ++{235, 46, 109}, ++{171, 64, 79}, ++{178, 63, 83}, ++{187, 61, 87}, ++{198, 58, 92}, ++{209, 55, 98}, ++{221, 52, 103}, ++{234, 48, 108}, ++{237, 47, 109}, ++{173, 65, 80}, ++{180, 64, 84}, ++{189, 62, 88}, ++{200, 60, 93}, ++{211, 56, 98}, ++{223, 53, 103}, ++{235, 49, 108}, ++{238, 48, 110}, ++{176, 67, 81}, ++{182, 66, 85}, ++{191, 64, 89}, ++{202, 61, 94}, ++{213, 57, 99}, ++{225, 54, 104}, ++{237, 50, 109}, ++{240, 49, 110}, ++{178, 69, 82}, ++{185, 67, 86}, ++{194, 65, 90}, ++{204, 62, 94}, ++{215, 59, 99}, ++{226, 55, 104}, ++{238, 51, 109}, ++{241, 50, 111}, ++{181, 71, 83}, ++{187, 69, 86}, ++{196, 66, 91}, ++{206, 63, 95}, ++{217, 60, 100}, ++{228, 56, 105}, ++{240, 52, 110}, ++{243, 51, 111}, ++{184, 72, 85}, ++{190, 70, 87}, ++{198, 68, 91}, ++{208, 64, 96}, ++{219, 61, 101}, ++{230, 57, 106}, ++{242, 53, 110}, ++{245, 51, 112}, ++{187, 74, 86}, ++{193, 72, 88}, ++{201, 69, 92}, ++{210, 66, 97}, ++{221, 62, 101}, ++{232, 58, 106}, ++{244, 53, 111}, ++{247, 52, 112}, ++{189, 75, 87}, ++{195, 73, 90}, ++{203, 70, 93}, ++{213, 67, 98}, ++{223, 63, 102}, ++{234, 59, 107}, ++{246, 54, 111}, ++{249, 53, 113}, ++{192, 77, 88}, ++{198, 75, 91}, ++{206, 72, 94}, ++{215, 68, 98}, ++{226, 64, 103}, ++{236, 60, 107}, ++{248, 55, 112}, ++{251, 54, 113}, ++{195, 78, 89}, ++{201, 76, 92}, ++{209, 73, 95}, ++{218, 69, 99}, ++{228, 65, 103}, ++{239, 61, 108}, ++{250, 56, 112}, ++{253, 55, 114}, ++{198, 80, 90}, ++{204, 77, 93}, ++{211, 74, 96}, ++{220, 71, 100}, ++{230, 66, 104}, ++{241, 62, 109}, ++{252, 57, 113}, ++{255, 56, 114}, ++{201, 81, 91}, ++{207, 79, 94}, ++{214, 76, 97}, ++{223, 72, 101}, ++{233, 67, 105}, ++{243, 63, 109}, ++{254, 58, 114}, ++{255, 57, 115}, ++{204, 83, 92}, ++{209, 80, 95}, ++{217, 77, 98}, ++{225, 73, 102}, ++{235, 69, 106}, ++{245, 64, 110}, ++{255, 59, 114}, ++{255, 58, 115}, ++{207, 84, 93}, ++{212, 81, 96}, ++{220, 78, 99}, ++{228, 74, 102}, ++{238, 70, 106}, ++{248, 65, 110}, ++{255, 60, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{214, 82, 96}, ++{221, 79, 99}, ++{230, 75, 103}, ++{239, 70, 107}, ++{249, 65, 111}, ++{255, 61, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{214, 82, 96}, ++{221, 79, 99}, ++{230, 75, 103}, ++{239, 70, 107}, ++{249, 65, 111}, ++{255, 61, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{214, 82, 96}, ++{221, 79, 99}, ++{230, 75, 103}, ++{239, 70, 107}, ++{249, 65, 111}, ++{255, 61, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{214, 82, 96}, ++{221, 79, 99}, ++{230, 75, 103}, ++{239, 70, 107}, ++{249, 65, 111}, ++{255, 61, 115}, ++{255, 59, 116}, ++{154, 43, 68}, ++{162, 45, 73}, ++{173, 46, 78}, ++{185, 46, 85}, ++{197, 45, 91}, ++{211, 43, 97}, ++{224, 40, 103}, ++{227, 39, 104}, ++{154, 44, 68}, ++{162, 45, 73}, ++{173, 46, 79}, ++{185, 46, 85}, ++{198, 45, 91}, ++{211, 43, 97}, ++{224, 40, 103}, ++{227, 39, 104}, ++{154, 44, 68}, ++{162, 46, 73}, ++{173, 46, 79}, ++{185, 46, 85}, ++{198, 45, 91}, ++{211, 43, 97}, ++{224, 40, 103}, ++{227, 39, 104}, ++{155, 45, 69}, ++{163, 46, 73}, ++{174, 47, 79}, ++{186, 47, 85}, ++{198, 45, 91}, ++{211, 43, 97}, ++{224, 40, 103}, ++{228, 40, 104}, ++{156, 46, 69}, ++{164, 47, 74}, ++{174, 47, 79}, ++{186, 47, 85}, ++{199, 46, 91}, ++{212, 43, 97}, ++{225, 41, 103}, ++{228, 40, 105}, ++{157, 47, 70}, ++{165, 48, 74}, ++{175, 48, 80}, ++{187, 48, 86}, ++{200, 46, 92}, ++{212, 44, 98}, ++{226, 41, 103}, ++{229, 40, 105}, ++{158, 48, 70}, ++{166, 49, 75}, ++{176, 49, 80}, ++{188, 48, 86}, ++{200, 47, 92}, ++{213, 44, 98}, ++{226, 41, 104}, ++{229, 41, 105}, ++{159, 50, 71}, ++{167, 50, 75}, ++{177, 50, 81}, ++{189, 49, 86}, ++{201, 47, 92}, ++{214, 45, 98}, ++{227, 42, 104}, ++{230, 41, 105}, ++{161, 51, 72}, ++{169, 51, 76}, ++{179, 51, 81}, ++{190, 50, 87}, ++{202, 48, 93}, ++{215, 46, 98}, ++{228, 43, 104}, ++{231, 42, 105}, ++{163, 53, 73}, ++{170, 53, 77}, ++{180, 52, 82}, ++{192, 51, 87}, ++{204, 49, 93}, ++{216, 46, 99}, ++{229, 43, 104}, ++{232, 42, 106}, ++{165, 54, 73}, ++{172, 54, 77}, ++{182, 54, 82}, ++{193, 52, 88}, ++{205, 50, 94}, ++{217, 47, 99}, ++{230, 44, 105}, ++{233, 43, 106}, ++{167, 56, 74}, ++{174, 56, 78}, ++{183, 55, 83}, ++{194, 53, 89}, ++{206, 51, 94}, ++{219, 48, 100}, ++{231, 44, 105}, ++{234, 44, 106}, ++{169, 58, 75}, ++{176, 57, 79}, ++{185, 56, 84}, ++{196, 54, 89}, ++{208, 52, 95}, ++{220, 49, 100}, ++{232, 45, 105}, ++{236, 44, 107}, ++{171, 60, 76}, ++{178, 59, 80}, ++{187, 58, 85}, ++{198, 55, 90}, ++{209, 53, 95}, ++{221, 50, 101}, ++{234, 46, 106}, ++{237, 45, 107}, ++{173, 61, 77}, ++{180, 61, 81}, ++{189, 59, 85}, ++{200, 57, 90}, ++{211, 54, 96}, ++{223, 50, 101}, ++{235, 47, 106}, ++{238, 46, 107}, ++{176, 63, 78}, ++{182, 62, 82}, ++{191, 60, 86}, ++{202, 58, 91}, ++{213, 55, 96}, ++{225, 51, 102}, ++{237, 48, 107}, ++{240, 47, 108}, ++{178, 65, 79}, ++{185, 64, 83}, ++{193, 62, 87}, ++{204, 59, 92}, ++{215, 56, 97}, ++{226, 52, 102}, ++{238, 49, 107}, ++{241, 48, 108}, ++{181, 67, 81}, ++{187, 65, 84}, ++{196, 63, 88}, ++{206, 60, 93}, ++{217, 57, 98}, ++{228, 53, 103}, ++{240, 49, 108}, ++{243, 48, 109}, ++{183, 68, 82}, ++{189, 67, 85}, ++{198, 64, 89}, ++{208, 62, 93}, ++{219, 58, 98}, ++{230, 54, 103}, ++{242, 50, 108}, ++{245, 49, 109}, ++{186, 70, 83}, ++{192, 68, 86}, ++{200, 66, 90}, ++{210, 63, 94}, ++{221, 59, 99}, ++{232, 55, 104}, ++{243, 51, 109}, ++{246, 50, 110}, ++{189, 72, 84}, ++{195, 70, 87}, ++{203, 67, 91}, ++{212, 64, 95}, ++{223, 60, 100}, ++{234, 56, 104}, ++{245, 52, 109}, ++{248, 51, 110}, ++{191, 73, 85}, ++{197, 71, 88}, ++{205, 69, 91}, ++{215, 65, 96}, ++{225, 62, 100}, ++{236, 57, 105}, ++{247, 53, 110}, ++{250, 52, 111}, ++{194, 75, 86}, ++{200, 73, 89}, ++{208, 70, 92}, ++{217, 67, 97}, ++{227, 63, 101}, ++{238, 58, 106}, ++{249, 54, 110}, ++{252, 53, 111}, ++{197, 76, 87}, ++{203, 74, 90}, ++{210, 71, 93}, ++{220, 68, 97}, ++{230, 64, 102}, ++{240, 60, 106}, ++{251, 55, 111}, ++{254, 54, 112}, ++{200, 78, 88}, ++{206, 76, 91}, ++{213, 73, 94}, ++{222, 69, 98}, ++{232, 65, 102}, ++{242, 61, 107}, ++{253, 56, 111}, ++{255, 55, 112}, ++{203, 79, 89}, ++{208, 77, 92}, ++{216, 74, 95}, ++{225, 70, 99}, ++{234, 66, 103}, ++{245, 62, 107}, ++{255, 57, 112}, ++{255, 56, 113}, ++{206, 81, 90}, ++{211, 78, 93}, ++{219, 75, 96}, ++{227, 71, 100}, ++{237, 67, 104}, ++{247, 63, 108}, ++{255, 58, 112}, ++{255, 57, 113}, ++{209, 82, 91}, ++{214, 80, 94}, ++{221, 76, 97}, ++{230, 72, 101}, ++{239, 68, 105}, ++{249, 64, 109}, ++{255, 59, 113}, ++{255, 58, 114}, ++{211, 83, 92}, ++{216, 80, 94}, ++{223, 77, 97}, ++{231, 73, 101}, ++{241, 69, 105}, ++{251, 64, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{211, 83, 92}, ++{216, 80, 94}, ++{223, 77, 97}, ++{231, 73, 101}, ++{241, 69, 105}, ++{251, 64, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{211, 83, 92}, ++{216, 80, 94}, ++{223, 77, 97}, ++{231, 73, 101}, ++{241, 69, 105}, ++{251, 64, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{211, 83, 92}, ++{216, 80, 94}, ++{223, 77, 97}, ++{231, 73, 101}, ++{241, 69, 105}, ++{251, 64, 109}, ++{255, 60, 113}, ++{255, 58, 114}, ++{156, 41, 66}, ++{164, 43, 71}, ++{175, 44, 77}, ++{187, 44, 83}, ++{199, 43, 89}, ++{212, 41, 95}, ++{226, 39, 101}, ++{229, 38, 102}, ++{156, 41, 67}, ++{164, 43, 71}, ++{175, 44, 77}, ++{187, 44, 83}, ++{200, 43, 89}, ++{213, 41, 95}, ++{226, 39, 101}, ++{229, 38, 102}, ++{157, 42, 67}, ++{165, 43, 71}, ++{175, 44, 77}, ++{187, 44, 83}, ++{200, 43, 89}, ++{213, 41, 95}, ++{226, 39, 101}, ++{229, 38, 102}, ++{157, 43, 67}, ++{165, 44, 71}, ++{176, 45, 77}, ++{188, 45, 83}, ++{200, 44, 89}, ++{213, 42, 95}, ++{226, 39, 101}, ++{229, 38, 103}, ++{158, 43, 67}, ++{166, 45, 72}, ++{177, 46, 77}, ++{188, 45, 83}, ++{201, 44, 90}, ++{214, 42, 95}, ++{227, 39, 101}, ++{230, 39, 103}, ++{159, 45, 68}, ++{167, 46, 72}, ++{177, 46, 78}, ++{189, 46, 84}, ++{202, 44, 90}, ++{214, 42, 96}, ++{227, 40, 101}, ++{230, 39, 103}, ++{161, 46, 69}, ++{168, 47, 73}, ++{178, 47, 78}, ++{190, 47, 84}, ++{202, 45, 90}, ++{215, 43, 96}, ++{228, 40, 102}, ++{231, 39, 103}, ++{162, 47, 69}, ++{170, 48, 73}, ++{180, 48, 79}, ++{191, 47, 85}, ++{203, 46, 90}, ++{216, 43, 96}, ++{229, 41, 102}, ++{232, 40, 103}, ++{163, 49, 70}, ++{171, 49, 74}, ++{181, 49, 79}, ++{192, 48, 85}, ++{204, 47, 91}, ++{217, 44, 97}, ++{230, 41, 102}, ++{233, 40, 104}, ++{165, 50, 71}, ++{173, 51, 75}, ++{182, 50, 80}, ++{194, 49, 86}, ++{206, 47, 91}, ++{218, 45, 97}, ++{231, 42, 103}, ++{234, 41, 104}, ++{167, 52, 72}, ++{174, 52, 76}, ++{184, 52, 81}, ++{195, 50, 86}, ++{207, 48, 92}, ++{219, 46, 97}, ++{232, 42, 103}, ++{235, 42, 104}, ++{169, 54, 73}, ++{176, 54, 76}, ++{186, 53, 81}, ++{197, 51, 87}, ++{208, 49, 92}, ++{220, 46, 98}, ++{233, 43, 103}, ++{236, 42, 105}, ++{171, 56, 74}, ++{178, 55, 77}, ++{187, 54, 82}, ++{198, 52, 87}, ++{210, 50, 93}, ++{222, 47, 98}, ++{234, 44, 104}, ++{237, 43, 105}, ++{173, 57, 75}, ++{180, 57, 78}, ++{189, 56, 83}, ++{200, 54, 88}, ++{211, 51, 93}, ++{223, 48, 99}, ++{235, 45, 104}, ++{239, 44, 105}, ++{175, 59, 76}, ++{182, 58, 79}, ++{191, 57, 84}, ++{202, 55, 89}, ++{213, 52, 94}, ++{225, 49, 99}, ++{237, 46, 104}, ++{240, 45, 106}, ++{178, 61, 77}, ++{184, 60, 80}, ++{193, 58, 84}, ++{204, 56, 89}, ++{215, 53, 95}, ++{226, 50, 100}, ++{238, 46, 105}, ++{241, 45, 106}, ++{180, 63, 78}, ++{187, 62, 81}, ++{195, 60, 85}, ++{206, 57, 90}, ++{217, 54, 95}, ++{228, 51, 100}, ++{240, 47, 105}, ++{243, 46, 107}, ++{183, 65, 79}, ++{189, 63, 82}, ++{198, 61, 86}, ++{208, 59, 91}, ++{218, 55, 96}, ++{230, 52, 101}, ++{242, 48, 106}, ++{245, 47, 107}, ++{185, 66, 80}, ++{191, 65, 83}, ++{200, 63, 87}, ++{210, 60, 92}, ++{220, 57, 96}, ++{232, 53, 101}, ++{243, 49, 106}, ++{246, 48, 107}, ++{188, 68, 81}, ++{194, 66, 84}, ++{202, 64, 88}, ++{212, 61, 92}, ++{222, 58, 97}, ++{234, 54, 102}, ++{245, 50, 107}, ++{248, 49, 108}, ++{191, 70, 82}, ++{197, 68, 85}, ++{205, 65, 89}, ++{214, 62, 93}, ++{225, 59, 98}, ++{236, 55, 103}, ++{247, 51, 107}, ++{250, 50, 108}, ++{193, 71, 83}, ++{199, 69, 86}, ++{207, 67, 90}, ++{217, 64, 94}, ++{227, 60, 99}, ++{238, 56, 103}, ++{249, 52, 108}, ++{252, 51, 109}, ++{196, 73, 84}, ++{202, 71, 87}, ++{210, 68, 91}, ++{219, 65, 95}, ++{229, 61, 99}, ++{240, 57, 104}, ++{251, 53, 108}, ++{254, 52, 110}, ++{199, 74, 85}, ++{205, 72, 88}, ++{212, 70, 92}, ++{221, 66, 96}, ++{231, 62, 100}, ++{242, 58, 104}, ++{253, 54, 109}, ++{255, 53, 110}, ++{202, 76, 86}, ++{207, 74, 89}, ++{215, 71, 92}, ++{224, 67, 96}, ++{234, 63, 101}, ++{244, 59, 105}, ++{255, 55, 109}, ++{255, 54, 111}, ++{205, 77, 88}, ++{210, 75, 90}, ++{218, 72, 93}, ++{226, 69, 97}, ++{236, 65, 101}, ++{246, 60, 106}, ++{255, 56, 110}, ++{255, 55, 111}, ++{208, 79, 89}, ++{213, 76, 91}, ++{220, 73, 94}, ++{229, 70, 98}, ++{238, 66, 102}, ++{249, 61, 106}, ++{255, 57, 111}, ++{255, 56, 112}, ++{211, 80, 90}, ++{216, 78, 92}, ++{223, 75, 95}, ++{232, 71, 99}, ++{241, 67, 103}, ++{251, 62, 107}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 81, 90}, ++{218, 78, 93}, ++{225, 75, 96}, ++{233, 71, 99}, ++{242, 67, 103}, ++{252, 63, 107}, ++{255, 58, 111}, ++{255, 57, 113}, ++{213, 81, 90}, ++{218, 78, 93}, ++{225, 75, 96}, ++{233, 71, 99}, ++{242, 67, 103}, ++{252, 63, 107}, ++{255, 58, 111}, ++{255, 57, 113}, ++{213, 81, 90}, ++{218, 78, 93}, ++{225, 75, 96}, ++{233, 71, 99}, ++{242, 67, 103}, ++{252, 63, 107}, ++{255, 58, 111}, ++{255, 57, 113}, ++{213, 81, 90}, ++{218, 78, 93}, ++{225, 75, 96}, ++{233, 71, 99}, ++{242, 67, 103}, ++{252, 63, 107}, ++{255, 58, 111}, ++{255, 57, 113}, ++{158, 40, 66}, ++{165, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{200, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 40, 66}, ++{166, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 41, 66}, ++{166, 42, 70}, ++{177, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 37, 102}, ++{159, 41, 66}, ++{167, 43, 71}, ++{177, 44, 76}, ++{189, 44, 82}, ++{201, 43, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 38, 102}, ++{160, 42, 67}, ++{167, 44, 71}, ++{178, 45, 77}, ++{189, 44, 83}, ++{202, 43, 89}, ++{215, 41, 95}, ++{228, 39, 100}, ++{231, 38, 102}, ++{161, 43, 67}, ++{168, 45, 71}, ++{179, 45, 77}, ++{190, 45, 83}, ++{203, 44, 89}, ++{215, 42, 95}, ++{228, 39, 101}, ++{231, 38, 102}, ++{162, 45, 68}, ++{169, 46, 72}, ++{180, 46, 77}, ++{191, 46, 83}, ++{203, 44, 89}, ++{216, 42, 95}, ++{229, 39, 101}, ++{232, 39, 102}, ++{163, 46, 68}, ++{171, 47, 73}, ++{181, 47, 78}, ++{192, 46, 84}, ++{204, 45, 90}, ++{217, 43, 95}, ++{230, 40, 101}, ++{233, 39, 102}, ++{165, 48, 69}, ++{172, 48, 73}, ++{182, 48, 78}, ++{193, 47, 84}, ++{205, 46, 90}, ++{218, 43, 96}, ++{231, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{174, 50, 74}, ++{183, 49, 79}, ++{195, 48, 85}, ++{207, 47, 90}, ++{219, 44, 96}, ++{231, 41, 102}, ++{235, 40, 103}, ++{168, 51, 71}, ++{175, 51, 75}, ++{185, 51, 80}, ++{196, 49, 85}, ++{208, 47, 91}, ++{220, 45, 96}, ++{233, 42, 102}, ++{236, 41, 103}, ++{170, 53, 72}, ++{177, 53, 76}, ++{187, 52, 80}, ++{198, 50, 86}, ++{209, 48, 91}, ++{221, 46, 97}, ++{234, 43, 102}, ++{237, 42, 104}, ++{172, 55, 73}, ++{179, 54, 76}, ++{188, 53, 81}, ++{199, 52, 86}, ++{211, 49, 92}, ++{223, 46, 97}, ++{235, 43, 103}, ++{238, 42, 104}, ++{174, 56, 74}, ++{181, 56, 77}, ++{190, 55, 82}, ++{201, 53, 87}, ++{212, 50, 92}, ++{224, 47, 98}, ++{236, 44, 103}, ++{239, 43, 104}, ++{177, 58, 75}, ++{183, 57, 78}, ++{192, 56, 83}, ++{203, 54, 88}, ++{214, 51, 93}, ++{226, 48, 98}, ++{238, 45, 104}, ++{241, 44, 105}, ++{179, 60, 76}, ++{185, 59, 79}, ++{194, 57, 84}, ++{205, 55, 88}, ++{216, 52, 94}, ++{227, 49, 99}, ++{239, 46, 104}, ++{242, 45, 105}, ++{181, 62, 77}, ++{188, 61, 80}, ++{196, 59, 84}, ++{207, 56, 89}, ++{217, 54, 94}, ++{229, 50, 99}, ++{241, 47, 104}, ++{244, 46, 106}, ++{184, 63, 78}, ++{190, 62, 81}, ++{199, 60, 85}, ++{209, 58, 90}, ++{219, 55, 95}, ++{231, 51, 100}, ++{242, 48, 105}, ++{245, 47, 106}, ++{186, 65, 79}, ++{193, 64, 82}, ++{201, 62, 86}, ++{211, 59, 91}, ++{221, 56, 96}, ++{233, 52, 100}, ++{244, 48, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{195, 65, 83}, ++{203, 63, 87}, ++{213, 60, 91}, ++{223, 57, 96}, ++{234, 53, 101}, ++{246, 49, 106}, ++{249, 48, 107}, ++{192, 69, 81}, ++{198, 67, 84}, ++{206, 65, 88}, ++{215, 62, 92}, ++{225, 58, 97}, ++{236, 54, 102}, ++{248, 50, 106}, ++{251, 49, 108}, ++{195, 70, 82}, ++{200, 68, 85}, ++{208, 66, 89}, ++{217, 63, 93}, ++{228, 59, 98}, ++{238, 55, 102}, ++{250, 51, 107}, ++{252, 50, 108}, ++{197, 72, 83}, ++{203, 70, 86}, ++{211, 67, 90}, ++{220, 64, 94}, ++{230, 60, 98}, ++{241, 56, 103}, ++{252, 52, 108}, ++{254, 51, 109}, ++{200, 73, 85}, ++{206, 71, 87}, ++{213, 69, 91}, ++{222, 65, 95}, ++{232, 62, 99}, ++{243, 58, 104}, ++{254, 53, 108}, ++{255, 52, 109}, ++{203, 75, 86}, ++{208, 73, 88}, ++{216, 70, 92}, ++{225, 67, 96}, ++{234, 63, 100}, ++{245, 59, 104}, ++{255, 54, 109}, ++{255, 53, 110}, ++{206, 76, 87}, ++{211, 74, 89}, ++{219, 71, 93}, ++{227, 68, 96}, ++{237, 64, 101}, ++{247, 60, 105}, ++{255, 55, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{214, 76, 90}, ++{221, 73, 93}, ++{230, 69, 97}, ++{239, 65, 101}, ++{249, 61, 105}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{217, 77, 91}, ++{224, 74, 94}, ++{232, 70, 98}, ++{242, 66, 102}, ++{252, 62, 106}, ++{255, 57, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{165, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{200, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 40, 66}, ++{166, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 41, 66}, ++{166, 42, 70}, ++{177, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 37, 102}, ++{159, 41, 66}, ++{167, 43, 71}, ++{177, 44, 76}, ++{189, 44, 82}, ++{201, 43, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 38, 102}, ++{160, 42, 67}, ++{167, 44, 71}, ++{178, 45, 77}, ++{189, 44, 83}, ++{202, 43, 89}, ++{215, 41, 95}, ++{228, 39, 100}, ++{231, 38, 102}, ++{161, 43, 67}, ++{168, 45, 71}, ++{179, 45, 77}, ++{190, 45, 83}, ++{203, 44, 89}, ++{215, 42, 95}, ++{228, 39, 101}, ++{231, 38, 102}, ++{162, 45, 68}, ++{169, 46, 72}, ++{180, 46, 77}, ++{191, 46, 83}, ++{203, 44, 89}, ++{216, 42, 95}, ++{229, 39, 101}, ++{232, 39, 102}, ++{163, 46, 68}, ++{171, 47, 73}, ++{181, 47, 78}, ++{192, 46, 84}, ++{204, 45, 90}, ++{217, 43, 95}, ++{230, 40, 101}, ++{233, 39, 102}, ++{165, 48, 69}, ++{172, 48, 73}, ++{182, 48, 78}, ++{193, 47, 84}, ++{205, 46, 90}, ++{218, 43, 96}, ++{231, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{174, 50, 74}, ++{183, 49, 79}, ++{195, 48, 85}, ++{207, 47, 90}, ++{219, 44, 96}, ++{231, 41, 102}, ++{235, 40, 103}, ++{168, 51, 71}, ++{175, 51, 75}, ++{185, 51, 80}, ++{196, 49, 85}, ++{208, 47, 91}, ++{220, 45, 96}, ++{233, 42, 102}, ++{236, 41, 103}, ++{170, 53, 72}, ++{177, 53, 76}, ++{187, 52, 80}, ++{198, 50, 86}, ++{209, 48, 91}, ++{221, 46, 97}, ++{234, 43, 102}, ++{237, 42, 104}, ++{172, 55, 73}, ++{179, 54, 76}, ++{188, 53, 81}, ++{199, 52, 86}, ++{211, 49, 92}, ++{223, 46, 97}, ++{235, 43, 103}, ++{238, 42, 104}, ++{174, 56, 74}, ++{181, 56, 77}, ++{190, 55, 82}, ++{201, 53, 87}, ++{212, 50, 92}, ++{224, 47, 98}, ++{236, 44, 103}, ++{239, 43, 104}, ++{177, 58, 75}, ++{183, 57, 78}, ++{192, 56, 83}, ++{203, 54, 88}, ++{214, 51, 93}, ++{226, 48, 98}, ++{238, 45, 104}, ++{241, 44, 105}, ++{179, 60, 76}, ++{185, 59, 79}, ++{194, 57, 84}, ++{205, 55, 88}, ++{216, 52, 94}, ++{227, 49, 99}, ++{239, 46, 104}, ++{242, 45, 105}, ++{181, 62, 77}, ++{188, 61, 80}, ++{196, 59, 84}, ++{207, 56, 89}, ++{217, 54, 94}, ++{229, 50, 99}, ++{241, 47, 104}, ++{244, 46, 106}, ++{184, 63, 78}, ++{190, 62, 81}, ++{199, 60, 85}, ++{209, 58, 90}, ++{219, 55, 95}, ++{231, 51, 100}, ++{242, 48, 105}, ++{245, 47, 106}, ++{186, 65, 79}, ++{193, 64, 82}, ++{201, 62, 86}, ++{211, 59, 91}, ++{221, 56, 96}, ++{233, 52, 100}, ++{244, 48, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{195, 65, 83}, ++{203, 63, 87}, ++{213, 60, 91}, ++{223, 57, 96}, ++{234, 53, 101}, ++{246, 49, 106}, ++{249, 48, 107}, ++{192, 69, 81}, ++{198, 67, 84}, ++{206, 65, 88}, ++{215, 62, 92}, ++{225, 58, 97}, ++{236, 54, 102}, ++{248, 50, 106}, ++{251, 49, 108}, ++{195, 70, 82}, ++{200, 68, 85}, ++{208, 66, 89}, ++{217, 63, 93}, ++{228, 59, 98}, ++{238, 55, 102}, ++{250, 51, 107}, ++{252, 50, 108}, ++{197, 72, 83}, ++{203, 70, 86}, ++{211, 67, 90}, ++{220, 64, 94}, ++{230, 60, 98}, ++{241, 56, 103}, ++{252, 52, 108}, ++{254, 51, 109}, ++{200, 73, 85}, ++{206, 71, 87}, ++{213, 69, 91}, ++{222, 65, 95}, ++{232, 62, 99}, ++{243, 58, 104}, ++{254, 53, 108}, ++{255, 52, 109}, ++{203, 75, 86}, ++{208, 73, 88}, ++{216, 70, 92}, ++{225, 67, 96}, ++{234, 63, 100}, ++{245, 59, 104}, ++{255, 54, 109}, ++{255, 53, 110}, ++{206, 76, 87}, ++{211, 74, 89}, ++{219, 71, 93}, ++{227, 68, 96}, ++{237, 64, 101}, ++{247, 60, 105}, ++{255, 55, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{214, 76, 90}, ++{221, 73, 93}, ++{230, 69, 97}, ++{239, 65, 101}, ++{249, 61, 105}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{217, 77, 91}, ++{224, 74, 94}, ++{232, 70, 98}, ++{242, 66, 102}, ++{252, 62, 106}, ++{255, 57, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{165, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{200, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 40, 66}, ++{166, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 41, 66}, ++{166, 42, 70}, ++{177, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 37, 102}, ++{159, 41, 66}, ++{167, 43, 71}, ++{177, 44, 76}, ++{189, 44, 82}, ++{201, 43, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 38, 102}, ++{160, 42, 67}, ++{167, 44, 71}, ++{178, 45, 77}, ++{189, 44, 83}, ++{202, 43, 89}, ++{215, 41, 95}, ++{228, 39, 100}, ++{231, 38, 102}, ++{161, 43, 67}, ++{168, 45, 71}, ++{179, 45, 77}, ++{190, 45, 83}, ++{203, 44, 89}, ++{215, 42, 95}, ++{228, 39, 101}, ++{231, 38, 102}, ++{162, 45, 68}, ++{169, 46, 72}, ++{180, 46, 77}, ++{191, 46, 83}, ++{203, 44, 89}, ++{216, 42, 95}, ++{229, 39, 101}, ++{232, 39, 102}, ++{163, 46, 68}, ++{171, 47, 73}, ++{181, 47, 78}, ++{192, 46, 84}, ++{204, 45, 90}, ++{217, 43, 95}, ++{230, 40, 101}, ++{233, 39, 102}, ++{165, 48, 69}, ++{172, 48, 73}, ++{182, 48, 78}, ++{193, 47, 84}, ++{205, 46, 90}, ++{218, 43, 96}, ++{231, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{174, 50, 74}, ++{183, 49, 79}, ++{195, 48, 85}, ++{207, 47, 90}, ++{219, 44, 96}, ++{231, 41, 102}, ++{235, 40, 103}, ++{168, 51, 71}, ++{175, 51, 75}, ++{185, 51, 80}, ++{196, 49, 85}, ++{208, 47, 91}, ++{220, 45, 96}, ++{233, 42, 102}, ++{236, 41, 103}, ++{170, 53, 72}, ++{177, 53, 76}, ++{187, 52, 80}, ++{198, 50, 86}, ++{209, 48, 91}, ++{221, 46, 97}, ++{234, 43, 102}, ++{237, 42, 104}, ++{172, 55, 73}, ++{179, 54, 76}, ++{188, 53, 81}, ++{199, 52, 86}, ++{211, 49, 92}, ++{223, 46, 97}, ++{235, 43, 103}, ++{238, 42, 104}, ++{174, 56, 74}, ++{181, 56, 77}, ++{190, 55, 82}, ++{201, 53, 87}, ++{212, 50, 92}, ++{224, 47, 98}, ++{236, 44, 103}, ++{239, 43, 104}, ++{177, 58, 75}, ++{183, 57, 78}, ++{192, 56, 83}, ++{203, 54, 88}, ++{214, 51, 93}, ++{226, 48, 98}, ++{238, 45, 104}, ++{241, 44, 105}, ++{179, 60, 76}, ++{185, 59, 79}, ++{194, 57, 84}, ++{205, 55, 88}, ++{216, 52, 94}, ++{227, 49, 99}, ++{239, 46, 104}, ++{242, 45, 105}, ++{181, 62, 77}, ++{188, 61, 80}, ++{196, 59, 84}, ++{207, 56, 89}, ++{217, 54, 94}, ++{229, 50, 99}, ++{241, 47, 104}, ++{244, 46, 106}, ++{184, 63, 78}, ++{190, 62, 81}, ++{199, 60, 85}, ++{209, 58, 90}, ++{219, 55, 95}, ++{231, 51, 100}, ++{242, 48, 105}, ++{245, 47, 106}, ++{186, 65, 79}, ++{193, 64, 82}, ++{201, 62, 86}, ++{211, 59, 91}, ++{221, 56, 96}, ++{233, 52, 100}, ++{244, 48, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{195, 65, 83}, ++{203, 63, 87}, ++{213, 60, 91}, ++{223, 57, 96}, ++{234, 53, 101}, ++{246, 49, 106}, ++{249, 48, 107}, ++{192, 69, 81}, ++{198, 67, 84}, ++{206, 65, 88}, ++{215, 62, 92}, ++{225, 58, 97}, ++{236, 54, 102}, ++{248, 50, 106}, ++{251, 49, 108}, ++{195, 70, 82}, ++{200, 68, 85}, ++{208, 66, 89}, ++{217, 63, 93}, ++{228, 59, 98}, ++{238, 55, 102}, ++{250, 51, 107}, ++{252, 50, 108}, ++{197, 72, 83}, ++{203, 70, 86}, ++{211, 67, 90}, ++{220, 64, 94}, ++{230, 60, 98}, ++{241, 56, 103}, ++{252, 52, 108}, ++{254, 51, 109}, ++{200, 73, 85}, ++{206, 71, 87}, ++{213, 69, 91}, ++{222, 65, 95}, ++{232, 62, 99}, ++{243, 58, 104}, ++{254, 53, 108}, ++{255, 52, 109}, ++{203, 75, 86}, ++{208, 73, 88}, ++{216, 70, 92}, ++{225, 67, 96}, ++{234, 63, 100}, ++{245, 59, 104}, ++{255, 54, 109}, ++{255, 53, 110}, ++{206, 76, 87}, ++{211, 74, 89}, ++{219, 71, 93}, ++{227, 68, 96}, ++{237, 64, 101}, ++{247, 60, 105}, ++{255, 55, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{214, 76, 90}, ++{221, 73, 93}, ++{230, 69, 97}, ++{239, 65, 101}, ++{249, 61, 105}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{217, 77, 91}, ++{224, 74, 94}, ++{232, 70, 98}, ++{242, 66, 102}, ++{252, 62, 106}, ++{255, 57, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{165, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{200, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 40, 66}, ++{166, 42, 70}, ++{176, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{213, 40, 94}, ++{226, 38, 100}, ++{230, 37, 101}, ++{158, 41, 66}, ++{166, 42, 70}, ++{177, 43, 76}, ++{188, 43, 82}, ++{201, 42, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 37, 102}, ++{159, 41, 66}, ++{167, 43, 71}, ++{177, 44, 76}, ++{189, 44, 82}, ++{201, 43, 88}, ++{214, 41, 94}, ++{227, 38, 100}, ++{230, 38, 102}, ++{160, 42, 67}, ++{167, 44, 71}, ++{178, 45, 77}, ++{189, 44, 83}, ++{202, 43, 89}, ++{215, 41, 95}, ++{228, 39, 100}, ++{231, 38, 102}, ++{161, 43, 67}, ++{168, 45, 71}, ++{179, 45, 77}, ++{190, 45, 83}, ++{203, 44, 89}, ++{215, 42, 95}, ++{228, 39, 101}, ++{231, 38, 102}, ++{162, 45, 68}, ++{169, 46, 72}, ++{180, 46, 77}, ++{191, 46, 83}, ++{203, 44, 89}, ++{216, 42, 95}, ++{229, 39, 101}, ++{232, 39, 102}, ++{163, 46, 68}, ++{171, 47, 73}, ++{181, 47, 78}, ++{192, 46, 84}, ++{204, 45, 90}, ++{217, 43, 95}, ++{230, 40, 101}, ++{233, 39, 102}, ++{165, 48, 69}, ++{172, 48, 73}, ++{182, 48, 78}, ++{193, 47, 84}, ++{205, 46, 90}, ++{218, 43, 96}, ++{231, 41, 101}, ++{234, 40, 103}, ++{166, 49, 70}, ++{174, 50, 74}, ++{183, 49, 79}, ++{195, 48, 85}, ++{207, 47, 90}, ++{219, 44, 96}, ++{231, 41, 102}, ++{235, 40, 103}, ++{168, 51, 71}, ++{175, 51, 75}, ++{185, 51, 80}, ++{196, 49, 85}, ++{208, 47, 91}, ++{220, 45, 96}, ++{233, 42, 102}, ++{236, 41, 103}, ++{170, 53, 72}, ++{177, 53, 76}, ++{187, 52, 80}, ++{198, 50, 86}, ++{209, 48, 91}, ++{221, 46, 97}, ++{234, 43, 102}, ++{237, 42, 104}, ++{172, 55, 73}, ++{179, 54, 76}, ++{188, 53, 81}, ++{199, 52, 86}, ++{211, 49, 92}, ++{223, 46, 97}, ++{235, 43, 103}, ++{238, 42, 104}, ++{174, 56, 74}, ++{181, 56, 77}, ++{190, 55, 82}, ++{201, 53, 87}, ++{212, 50, 92}, ++{224, 47, 98}, ++{236, 44, 103}, ++{239, 43, 104}, ++{177, 58, 75}, ++{183, 57, 78}, ++{192, 56, 83}, ++{203, 54, 88}, ++{214, 51, 93}, ++{226, 48, 98}, ++{238, 45, 104}, ++{241, 44, 105}, ++{179, 60, 76}, ++{185, 59, 79}, ++{194, 57, 84}, ++{205, 55, 88}, ++{216, 52, 94}, ++{227, 49, 99}, ++{239, 46, 104}, ++{242, 45, 105}, ++{181, 62, 77}, ++{188, 61, 80}, ++{196, 59, 84}, ++{207, 56, 89}, ++{217, 54, 94}, ++{229, 50, 99}, ++{241, 47, 104}, ++{244, 46, 106}, ++{184, 63, 78}, ++{190, 62, 81}, ++{199, 60, 85}, ++{209, 58, 90}, ++{219, 55, 95}, ++{231, 51, 100}, ++{242, 48, 105}, ++{245, 47, 106}, ++{186, 65, 79}, ++{193, 64, 82}, ++{201, 62, 86}, ++{211, 59, 91}, ++{221, 56, 96}, ++{233, 52, 100}, ++{244, 48, 105}, ++{247, 47, 107}, ++{189, 67, 80}, ++{195, 65, 83}, ++{203, 63, 87}, ++{213, 60, 91}, ++{223, 57, 96}, ++{234, 53, 101}, ++{246, 49, 106}, ++{249, 48, 107}, ++{192, 69, 81}, ++{198, 67, 84}, ++{206, 65, 88}, ++{215, 62, 92}, ++{225, 58, 97}, ++{236, 54, 102}, ++{248, 50, 106}, ++{251, 49, 108}, ++{195, 70, 82}, ++{200, 68, 85}, ++{208, 66, 89}, ++{217, 63, 93}, ++{228, 59, 98}, ++{238, 55, 102}, ++{250, 51, 107}, ++{252, 50, 108}, ++{197, 72, 83}, ++{203, 70, 86}, ++{211, 67, 90}, ++{220, 64, 94}, ++{230, 60, 98}, ++{241, 56, 103}, ++{252, 52, 108}, ++{254, 51, 109}, ++{200, 73, 85}, ++{206, 71, 87}, ++{213, 69, 91}, ++{222, 65, 95}, ++{232, 62, 99}, ++{243, 58, 104}, ++{254, 53, 108}, ++{255, 52, 109}, ++{203, 75, 86}, ++{208, 73, 88}, ++{216, 70, 92}, ++{225, 67, 96}, ++{234, 63, 100}, ++{245, 59, 104}, ++{255, 54, 109}, ++{255, 53, 110}, ++{206, 76, 87}, ++{211, 74, 89}, ++{219, 71, 93}, ++{227, 68, 96}, ++{237, 64, 101}, ++{247, 60, 105}, ++{255, 55, 109}, ++{255, 54, 110}, ++{209, 78, 88}, ++{214, 76, 90}, ++{221, 73, 93}, ++{230, 69, 97}, ++{239, 65, 101}, ++{249, 61, 105}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{217, 77, 91}, ++{224, 74, 94}, ++{232, 70, 98}, ++{242, 66, 102}, ++{252, 62, 106}, ++{255, 57, 110}, ++{255, 56, 111}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{213, 80, 89}, ++{218, 78, 92}, ++{225, 74, 95}, ++{234, 71, 98}, ++{243, 67, 102}, ++{253, 62, 106}, ++{255, 58, 111}, ++{255, 57, 112}, ++{87, 102, 122}, ++{102, 96, 128}, ++{119, 89, 133}, ++{137, 82, 139}, ++{154, 76, 143}, ++{171, 69, 148}, ++{187, 63, 152}, ++{189, 62, 152}, ++{87, 102, 122}, ++{102, 96, 128}, ++{120, 89, 134}, ++{137, 82, 139}, ++{154, 76, 143}, ++{171, 69, 148}, ++{187, 63, 152}, ++{189, 62, 152}, ++{88, 102, 122}, ++{103, 96, 128}, ++{120, 89, 134}, ++{137, 83, 139}, ++{155, 76, 143}, ++{171, 69, 148}, ++{188, 63, 152}, ++{190, 63, 152}, ++{89, 103, 123}, ++{104, 97, 128}, ++{121, 90, 134}, ++{138, 83, 139}, ++{155, 76, 143}, ++{172, 70, 148}, ++{188, 63, 152}, ++{190, 63, 152}, ++{91, 104, 123}, ++{105, 97, 128}, ++{122, 90, 134}, ++{139, 83, 139}, ++{156, 77, 144}, ++{172, 70, 148}, ++{189, 64, 152}, ++{191, 63, 152}, ++{93, 104, 124}, ++{107, 98, 129}, ++{123, 91, 134}, ++{140, 84, 139}, ++{157, 77, 144}, ++{173, 70, 148}, ++{189, 64, 152}, ++{191, 63, 152}, ++{95, 105, 124}, ++{109, 99, 129}, ++{125, 91, 134}, ++{141, 84, 139}, ++{158, 77, 144}, ++{174, 71, 148}, ++{190, 65, 152}, ++{192, 64, 152}, ++{97, 106, 125}, ++{111, 100, 129}, ++{126, 92, 134}, ++{143, 85, 139}, ++{159, 78, 144}, ++{175, 71, 148}, ++{191, 65, 152}, ++{193, 64, 152}, ++{100, 107, 125}, ++{113, 100, 130}, ++{128, 93, 135}, ++{144, 86, 139}, ++{161, 79, 144}, ++{177, 72, 148}, ++{192, 65, 152}, ++{194, 65, 152}, ++{103, 108, 126}, ++{115, 101, 130}, ++{130, 94, 135}, ++{146, 86, 140}, ++{162, 79, 144}, ++{178, 72, 148}, ++{194, 66, 152}, ++{195, 65, 152}, ++{106, 109, 126}, ++{118, 102, 131}, ++{133, 95, 135}, ++{148, 87, 140}, ++{164, 80, 144}, ++{179, 73, 148}, ++{195, 67, 152}, ++{197, 66, 152}, ++{109, 110, 127}, ++{121, 103, 131}, ++{135, 95, 136}, ++{150, 88, 140}, ++{166, 81, 144}, ++{181, 74, 148}, ++{196, 67, 152}, ++{198, 66, 152}, ++{112, 111, 128}, ++{124, 104, 132}, ++{138, 96, 136}, ++{152, 89, 140}, ++{168, 81, 144}, ++{183, 75, 148}, ++{198, 68, 152}, ++{200, 67, 152}, ++{116, 112, 128}, ++{127, 105, 132}, ++{140, 97, 136}, ++{155, 90, 140}, ++{170, 82, 144}, ++{185, 75, 148}, ++{200, 69, 152}, ++{201, 68, 152}, ++{119, 112, 129}, ++{130, 106, 132}, ++{143, 98, 137}, ++{157, 90, 141}, ++{172, 83, 145}, ++{187, 76, 148}, ++{201, 69, 152}, ++{203, 68, 152}, ++{123, 113, 130}, ++{133, 107, 133}, ++{146, 99, 137}, ++{160, 91, 141}, ++{174, 84, 145}, ++{189, 77, 149}, ++{203, 70, 152}, ++{205, 69, 153}, ++{127, 114, 130}, ++{136, 107, 133}, ++{149, 100, 137}, ++{162, 92, 141}, ++{176, 85, 145}, ++{191, 78, 149}, ++{205, 71, 152}, ++{207, 70, 153}, ++{130, 115, 131}, ++{140, 108, 134}, ++{152, 101, 138}, ++{165, 93, 141}, ++{179, 86, 145}, ++{193, 78, 149}, ++{207, 72, 152}, ++{209, 71, 153}, ++{134, 115, 132}, ++{143, 109, 134}, ++{155, 101, 138}, ++{168, 94, 142}, ++{181, 86, 145}, ++{195, 79, 149}, ++{209, 72, 152}, ++{211, 71, 153}, ++{138, 116, 132}, ++{147, 110, 135}, ++{158, 102, 138}, ++{170, 95, 142}, ++{184, 87, 145}, ++{197, 80, 149}, ++{211, 73, 152}, ++{213, 72, 153}, ++{142, 116, 133}, ++{150, 110, 135}, ++{161, 103, 139}, ++{173, 96, 142}, ++{186, 88, 146}, ++{200, 81, 149}, ++{213, 74, 153}, ++{215, 73, 153}, ++{145, 117, 133}, ++{154, 111, 136}, ++{164, 104, 139}, ++{176, 96, 142}, ++{189, 89, 146}, ++{202, 82, 149}, ++{216, 75, 153}, ++{217, 74, 153}, ++{149, 117, 134}, ++{157, 112, 136}, ++{168, 105, 139}, ++{179, 97, 143}, ++{192, 90, 146}, ++{205, 82, 149}, ++{218, 75, 153}, ++{220, 75, 153}, ++{153, 118, 134}, ++{161, 112, 137}, ++{171, 105, 140}, ++{182, 98, 143}, ++{195, 91, 146}, ++{207, 83, 150}, ++{220, 76, 153}, ++{222, 75, 153}, ++{157, 118, 135}, ++{164, 113, 137}, ++{174, 106, 140}, ++{185, 99, 143}, ++{197, 91, 146}, ++{210, 84, 150}, ++{223, 77, 153}, ++{224, 76, 153}, ++{161, 119, 135}, ++{168, 113, 138}, ++{178, 107, 140}, ++{189, 99, 143}, ++{200, 92, 147}, ++{213, 85, 150}, ++{225, 78, 153}, ++{227, 77, 153}, ++{165, 119, 136}, ++{172, 114, 138}, ++{181, 107, 141}, ++{192, 100, 144}, ++{203, 93, 147}, ++{215, 86, 150}, ++{228, 79, 153}, ++{229, 78, 154}, ++{169, 120, 136}, ++{175, 115, 138}, ++{184, 108, 141}, ++{195, 101, 144}, ++{206, 94, 147}, ++{218, 86, 150}, ++{230, 80, 153}, ++{232, 79, 154}, ++{171, 120, 137}, ++{177, 115, 139}, ++{186, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{219, 87, 150}, ++{232, 80, 153}, ++{233, 79, 154}, ++{171, 120, 137}, ++{177, 115, 139}, ++{186, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{219, 87, 150}, ++{232, 80, 153}, ++{233, 79, 154}, ++{171, 120, 137}, ++{177, 115, 139}, ++{186, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{219, 87, 150}, ++{232, 80, 153}, ++{233, 79, 154}, ++{171, 120, 137}, ++{177, 115, 139}, ++{186, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{219, 87, 150}, ++{232, 80, 153}, ++{233, 79, 154}, ++{88, 101, 121}, ++{103, 95, 127}, ++{120, 89, 132}, ++{138, 82, 138}, ++{155, 75, 143}, ++{171, 69, 147}, ++{188, 63, 151}, ++{190, 62, 151}, ++{88, 101, 121}, ++{103, 95, 127}, ++{120, 89, 132}, ++{138, 82, 138}, ++{155, 75, 143}, ++{172, 69, 147}, ++{188, 63, 151}, ++{190, 62, 151}, ++{89, 102, 121}, ++{104, 96, 127}, ++{121, 89, 133}, ++{138, 82, 138}, ++{155, 76, 143}, ++{172, 69, 147}, ++{188, 63, 151}, ++{190, 62, 151}, ++{90, 102, 122}, ++{105, 96, 127}, ++{122, 89, 133}, ++{139, 83, 138}, ++{156, 76, 143}, ++{172, 69, 147}, ++{189, 63, 151}, ++{191, 63, 151}, ++{92, 103, 122}, ++{106, 97, 127}, ++{123, 90, 133}, ++{140, 83, 138}, ++{156, 76, 143}, ++{173, 70, 147}, ++{189, 64, 151}, ++{191, 63, 151}, ++{94, 104, 122}, ++{108, 97, 128}, ++{124, 90, 133}, ++{141, 83, 138}, ++{157, 77, 143}, ++{174, 70, 147}, ++{190, 64, 151}, ++{192, 63, 151}, ++{96, 105, 123}, ++{110, 98, 128}, ++{125, 91, 133}, ++{142, 84, 138}, ++{159, 77, 143}, ++{175, 71, 147}, ++{191, 64, 151}, ++{193, 64, 151}, ++{98, 105, 124}, ++{112, 99, 128}, ++{127, 92, 133}, ++{143, 85, 138}, ++{160, 78, 143}, ++{176, 71, 147}, ++{192, 65, 151}, ++{194, 64, 151}, ++{101, 106, 124}, ++{114, 100, 129}, ++{129, 93, 134}, ++{145, 85, 139}, ++{161, 78, 143}, ++{177, 72, 147}, ++{193, 65, 151}, ++{195, 64, 152}, ++{104, 107, 125}, ++{116, 101, 129}, ++{131, 93, 134}, ++{147, 86, 139}, ++{163, 79, 143}, ++{178, 72, 147}, ++{194, 66, 151}, ++{196, 65, 152}, ++{107, 108, 125}, ++{119, 102, 130}, ++{133, 94, 134}, ++{149, 87, 139}, ++{164, 80, 143}, ++{180, 73, 147}, ++{195, 66, 151}, ++{197, 66, 152}, ++{110, 109, 126}, ++{122, 103, 130}, ++{136, 95, 135}, ++{151, 88, 139}, ++{166, 80, 143}, ++{182, 74, 147}, ++{197, 67, 151}, ++{199, 66, 152}, ++{113, 110, 127}, ++{124, 103, 131}, ++{138, 96, 135}, ++{153, 88, 139}, ++{168, 81, 144}, ++{183, 74, 148}, ++{198, 68, 151}, ++{200, 67, 152}, ++{117, 111, 127}, ++{127, 104, 131}, ++{141, 97, 135}, ++{155, 89, 140}, ++{170, 82, 144}, ++{185, 75, 148}, ++{200, 68, 151}, ++{202, 68, 152}, ++{120, 112, 128}, ++{131, 105, 132}, ++{143, 98, 136}, ++{158, 90, 140}, ++{172, 83, 144}, ++{187, 76, 148}, ++{202, 69, 151}, ++{203, 68, 152}, ++{124, 113, 129}, ++{134, 106, 132}, ++{146, 99, 136}, ++{160, 91, 140}, ++{174, 84, 144}, ++{189, 77, 148}, ++{203, 70, 151}, ++{205, 69, 152}, ++{127, 113, 129}, ++{137, 107, 133}, ++{149, 99, 136}, ++{163, 92, 140}, ++{177, 84, 144}, ++{191, 77, 148}, ++{205, 71, 152}, ++{207, 70, 152}, ++{131, 114, 130}, ++{140, 108, 133}, ++{152, 100, 137}, ++{165, 93, 141}, ++{179, 85, 144}, ++{193, 78, 148}, ++{207, 71, 152}, ++{209, 70, 152}, ++{135, 115, 131}, ++{144, 108, 134}, ++{155, 101, 137}, ++{168, 94, 141}, ++{182, 86, 145}, ++{195, 79, 148}, ++{209, 72, 152}, ++{211, 71, 152}, ++{138, 115, 131}, ++{147, 109, 134}, ++{158, 102, 137}, ++{171, 94, 141}, ++{184, 87, 145}, ++{198, 80, 148}, ++{211, 73, 152}, ++{213, 72, 152}, ++{142, 116, 132}, ++{151, 110, 135}, ++{162, 103, 138}, ++{174, 95, 141}, ++{187, 88, 145}, ++{200, 81, 149}, ++{214, 74, 152}, ++{215, 73, 152}, ++{146, 116, 132}, ++{154, 111, 135}, ++{165, 103, 138}, ++{177, 96, 142}, ++{189, 89, 145}, ++{203, 81, 149}, ++{216, 74, 152}, ++{218, 74, 152}, ++{150, 117, 133}, ++{158, 111, 136}, ++{168, 104, 139}, ++{180, 97, 142}, ++{192, 89, 145}, ++{205, 82, 149}, ++{218, 75, 152}, ++{220, 74, 153}, ++{154, 118, 134}, ++{161, 112, 136}, ++{171, 105, 139}, ++{183, 98, 142}, ++{195, 90, 146}, ++{208, 83, 149}, ++{221, 76, 152}, ++{222, 75, 153}, ++{158, 118, 134}, ++{165, 112, 136}, ++{175, 106, 139}, ++{186, 98, 143}, ++{198, 91, 146}, ++{210, 84, 149}, ++{223, 77, 152}, ++{225, 76, 153}, ++{161, 118, 135}, ++{169, 113, 137}, ++{178, 106, 140}, ++{189, 99, 143}, ++{201, 92, 146}, ++{213, 85, 149}, ++{225, 78, 153}, ++{227, 77, 153}, ++{165, 119, 135}, ++{172, 114, 137}, ++{181, 107, 140}, ++{192, 100, 143}, ++{204, 93, 146}, ++{216, 85, 150}, ++{228, 79, 153}, ++{230, 78, 153}, ++{169, 119, 136}, ++{176, 114, 138}, ++{185, 108, 141}, ++{195, 101, 143}, ++{207, 93, 147}, ++{218, 86, 150}, ++{231, 79, 153}, ++{232, 78, 153}, ++{171, 120, 136}, ++{178, 114, 138}, ++{187, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{220, 87, 150}, ++{232, 80, 153}, ++{233, 79, 153}, ++{171, 120, 136}, ++{178, 114, 138}, ++{187, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{220, 87, 150}, ++{232, 80, 153}, ++{233, 79, 153}, ++{171, 120, 136}, ++{178, 114, 138}, ++{187, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{220, 87, 150}, ++{232, 80, 153}, ++{233, 79, 153}, ++{171, 120, 136}, ++{178, 114, 138}, ++{187, 108, 141}, ++{197, 101, 144}, ++{208, 94, 147}, ++{220, 87, 150}, ++{232, 80, 153}, ++{233, 79, 153}, ++{90, 100, 119}, ++{105, 94, 125}, ++{121, 88, 131}, ++{139, 81, 136}, ++{156, 75, 141}, ++{172, 69, 146}, ++{188, 63, 150}, ++{190, 62, 150}, ++{90, 100, 119}, ++{105, 94, 125}, ++{122, 88, 131}, ++{139, 81, 136}, ++{156, 75, 141}, ++{172, 69, 146}, ++{189, 63, 150}, ++{191, 62, 150}, ++{91, 100, 119}, ++{105, 95, 125}, ++{122, 88, 131}, ++{139, 82, 136}, ++{156, 75, 141}, ++{173, 69, 146}, ++{189, 63, 150}, ++{191, 62, 150}, ++{92, 101, 120}, ++{106, 95, 125}, ++{123, 89, 131}, ++{140, 82, 136}, ++{157, 75, 141}, ++{173, 69, 146}, ++{189, 63, 150}, ++{191, 62, 150}, ++{94, 101, 120}, ++{108, 96, 125}, ++{124, 89, 131}, ++{141, 82, 136}, ++{157, 76, 141}, ++{174, 69, 146}, ++{190, 63, 150}, ++{192, 63, 150}, ++{95, 102, 121}, ++{109, 96, 126}, ++{125, 90, 131}, ++{142, 83, 137}, ++{158, 76, 141}, ++{175, 70, 146}, ++{191, 64, 150}, ++{193, 63, 150}, ++{98, 103, 121}, ++{111, 97, 126}, ++{127, 90, 132}, ++{143, 83, 137}, ++{159, 77, 141}, ++{176, 70, 146}, ++{191, 64, 150}, ++{193, 63, 150}, ++{100, 104, 122}, ++{113, 98, 127}, ++{128, 91, 132}, ++{145, 84, 137}, ++{161, 77, 142}, ++{177, 71, 146}, ++{192, 64, 150}, ++{194, 64, 150}, ++{103, 105, 122}, ++{115, 99, 127}, ++{130, 92, 132}, ++{146, 85, 137}, ++{162, 78, 142}, ++{178, 71, 146}, ++{194, 65, 150}, ++{195, 64, 150}, ++{105, 106, 123}, ++{118, 100, 128}, ++{132, 93, 132}, ++{148, 85, 137}, ++{164, 79, 142}, ++{179, 72, 146}, ++{195, 65, 150}, ++{197, 65, 150}, ++{108, 107, 124}, ++{120, 101, 128}, ++{134, 93, 133}, ++{150, 86, 138}, ++{165, 79, 142}, ++{181, 73, 146}, ++{196, 66, 150}, ++{198, 65, 151}, ++{111, 108, 124}, ++{123, 102, 129}, ++{137, 94, 133}, ++{152, 87, 138}, ++{167, 80, 142}, ++{182, 73, 146}, ++{197, 67, 150}, ++{199, 66, 151}, ++{115, 109, 125}, ++{126, 103, 129}, ++{139, 95, 134}, ++{154, 88, 138}, ++{169, 81, 142}, ++{184, 74, 146}, ++{199, 67, 150}, ++{201, 67, 151}, ++{118, 110, 126}, ++{129, 104, 130}, ++{142, 96, 134}, ++{156, 89, 138}, ++{171, 82, 142}, ++{186, 75, 146}, ++{201, 68, 150}, ++{202, 67, 151}, ++{121, 111, 127}, ++{132, 104, 130}, ++{145, 97, 134}, ++{159, 90, 139}, ++{173, 82, 143}, ++{188, 75, 147}, ++{202, 69, 150}, ++{204, 68, 151}, ++{125, 112, 127}, ++{135, 105, 131}, ++{147, 98, 135}, ++{161, 90, 139}, ++{175, 83, 143}, ++{190, 76, 147}, ++{204, 69, 150}, ++{206, 69, 151}, ++{128, 112, 128}, ++{138, 106, 131}, ++{150, 99, 135}, ++{164, 91, 139}, ++{178, 84, 143}, ++{192, 77, 147}, ++{206, 70, 151}, ++{208, 69, 151}, ++{132, 113, 129}, ++{141, 107, 132}, ++{153, 100, 135}, ++{166, 92, 139}, ++{180, 85, 143}, ++{194, 78, 147}, ++{208, 71, 151}, ++{210, 70, 151}, ++{136, 114, 129}, ++{145, 108, 132}, ++{156, 101, 136}, ++{169, 93, 140}, ++{182, 86, 143}, ++{196, 79, 147}, ++{210, 72, 151}, ++{212, 71, 151}, ++{139, 114, 130}, ++{148, 108, 133}, ++{159, 101, 136}, ++{172, 94, 140}, ++{185, 87, 144}, ++{198, 79, 147}, ++{212, 73, 151}, ++{214, 72, 151}, ++{143, 115, 131}, ++{152, 109, 133}, ++{162, 102, 137}, ++{175, 95, 140}, ++{188, 87, 144}, ++{201, 80, 148}, ++{214, 73, 151}, ++{216, 73, 151}, ++{147, 116, 131}, ++{155, 110, 134}, ++{166, 103, 137}, ++{178, 96, 141}, ++{190, 88, 144}, ++{203, 81, 148}, ++{217, 74, 151}, ++{218, 73, 152}, ++{151, 116, 132}, ++{159, 111, 134}, ++{169, 104, 137}, ++{180, 96, 141}, ++{193, 89, 144}, ++{206, 82, 148}, ++{219, 75, 151}, ++{220, 74, 152}, ++{155, 117, 132}, ++{162, 111, 135}, ++{172, 104, 138}, ++{184, 97, 141}, ++{196, 90, 145}, ++{208, 83, 148}, ++{221, 76, 151}, ++{223, 75, 152}, ++{158, 117, 133}, ++{166, 112, 135}, ++{175, 105, 138}, ++{187, 98, 142}, ++{199, 91, 145}, ++{211, 84, 148}, ++{224, 77, 152}, ++{225, 76, 152}, ++{162, 118, 134}, ++{169, 112, 136}, ++{179, 106, 139}, ++{190, 99, 142}, ++{201, 91, 145}, ++{214, 84, 148}, ++{226, 77, 152}, ++{228, 77, 152}, ++{166, 118, 134}, ++{173, 113, 136}, ++{182, 106, 139}, ++{193, 99, 142}, ++{204, 92, 145}, ++{216, 85, 149}, ++{229, 78, 152}, ++{230, 77, 152}, ++{170, 119, 135}, ++{177, 114, 137}, ++{186, 107, 139}, ++{196, 100, 142}, ++{207, 93, 146}, ++{219, 86, 149}, ++{231, 79, 152}, ++{233, 78, 152}, ++{172, 119, 135}, ++{179, 114, 137}, ++{187, 107, 140}, ++{198, 100, 143}, ++{209, 93, 146}, ++{220, 86, 149}, ++{232, 79, 152}, ++{234, 79, 152}, ++{172, 119, 135}, ++{179, 114, 137}, ++{187, 107, 140}, ++{198, 100, 143}, ++{209, 93, 146}, ++{220, 86, 149}, ++{232, 79, 152}, ++{234, 79, 152}, ++{172, 119, 135}, ++{179, 114, 137}, ++{187, 107, 140}, ++{198, 100, 143}, ++{209, 93, 146}, ++{220, 86, 149}, ++{232, 79, 152}, ++{234, 79, 152}, ++{172, 119, 135}, ++{179, 114, 137}, ++{187, 107, 140}, ++{198, 100, 143}, ++{209, 93, 146}, ++{220, 86, 149}, ++{232, 79, 152}, ++{234, 79, 152}, ++{92, 98, 117}, ++{106, 93, 123}, ++{123, 87, 129}, ++{140, 81, 134}, ++{157, 74, 139}, ++{173, 68, 144}, ++{189, 62, 148}, ++{191, 61, 149}, ++{92, 98, 117}, ++{107, 93, 123}, ++{123, 87, 129}, ++{140, 81, 134}, ++{157, 74, 139}, ++{173, 68, 144}, ++{190, 62, 148}, ++{191, 61, 149}, ++{93, 98, 117}, ++{107, 93, 123}, ++{124, 87, 129}, ++{141, 81, 134}, ++{157, 75, 139}, ++{174, 68, 144}, ++{190, 62, 148}, ++{192, 62, 149}, ++{94, 99, 117}, ++{108, 94, 123}, ++{124, 88, 129}, ++{141, 81, 135}, ++{158, 75, 140}, ++{174, 69, 144}, ++{190, 63, 148}, ++{192, 62, 149}, ++{96, 100, 118}, ++{109, 94, 123}, ++{125, 88, 129}, ++{142, 82, 135}, ++{159, 75, 140}, ++{175, 69, 144}, ++{191, 63, 148}, ++{193, 62, 149}, ++{97, 101, 118}, ++{111, 95, 124}, ++{127, 89, 129}, ++{143, 82, 135}, ++{160, 76, 140}, ++{176, 69, 144}, ++{192, 63, 148}, ++{193, 62, 149}, ++{99, 102, 119}, ++{113, 96, 124}, ++{128, 89, 130}, ++{144, 83, 135}, ++{161, 76, 140}, ++{177, 70, 144}, ++{192, 64, 148}, ++{194, 63, 149}, ++{102, 103, 120}, ++{115, 97, 125}, ++{130, 90, 130}, ++{146, 83, 135}, ++{162, 77, 140}, ++{178, 70, 144}, ++{193, 64, 148}, ++{195, 63, 149}, ++{104, 104, 120}, ++{117, 98, 125}, ++{132, 91, 130}, ++{147, 84, 135}, ++{163, 77, 140}, ++{179, 71, 144}, ++{194, 65, 149}, ++{196, 64, 149}, ++{107, 105, 121}, ++{119, 99, 126}, ++{134, 92, 131}, ++{149, 85, 136}, ++{165, 78, 140}, ++{180, 71, 145}, ++{196, 65, 149}, ++{198, 64, 149}, ++{110, 106, 122}, ++{122, 100, 126}, ++{136, 93, 131}, ++{151, 86, 136}, ++{166, 79, 140}, ++{182, 72, 145}, ++{197, 66, 149}, ++{199, 65, 149}, ++{113, 107, 123}, ++{124, 101, 127}, ++{138, 93, 131}, ++{153, 86, 136}, ++{168, 79, 141}, ++{183, 73, 145}, ++{198, 66, 149}, ++{200, 65, 149}, ++{116, 108, 123}, ++{127, 102, 127}, ++{141, 94, 132}, ++{155, 87, 136}, ++{170, 80, 141}, ++{185, 73, 145}, ++{200, 67, 149}, ++{202, 66, 149}, ++{120, 109, 124}, ++{130, 102, 128}, ++{143, 95, 132}, ++{157, 88, 137}, ++{172, 81, 141}, ++{187, 74, 145}, ++{202, 68, 149}, ++{203, 67, 149}, ++{123, 110, 125}, ++{133, 103, 128}, ++{146, 96, 133}, ++{160, 89, 137}, ++{174, 82, 141}, ++{189, 75, 145}, ++{203, 68, 149}, ++{205, 68, 150}, ++{126, 110, 126}, ++{136, 104, 129}, ++{149, 97, 133}, ++{162, 90, 137}, ++{176, 83, 141}, ++{191, 76, 145}, ++{205, 69, 149}, ++{207, 68, 150}, ++{130, 111, 126}, ++{139, 105, 130}, ++{151, 98, 133}, ++{165, 91, 138}, ++{179, 83, 142}, ++{193, 76, 146}, ++{207, 70, 149}, ++{209, 69, 150}, ++{133, 112, 127}, ++{143, 106, 130}, ++{154, 99, 134}, ++{167, 92, 138}, ++{181, 84, 142}, ++{195, 77, 146}, ++{209, 71, 149}, ++{211, 70, 150}, ++{137, 113, 128}, ++{146, 107, 131}, ++{157, 100, 134}, ++{170, 92, 138}, ++{183, 85, 142}, ++{197, 78, 146}, ++{211, 71, 150}, ++{213, 71, 150}, ++{141, 113, 128}, ++{149, 108, 131}, ++{160, 101, 135}, ++{173, 93, 139}, ++{186, 86, 142}, ++{199, 79, 146}, ++{213, 72, 150}, ++{215, 71, 150}, ++{144, 114, 129}, ++{153, 108, 132}, ++{164, 101, 135}, ++{176, 94, 139}, ++{188, 87, 143}, ++{202, 80, 146}, ++{215, 73, 150}, ++{217, 72, 150}, ++{148, 115, 130}, ++{156, 109, 132}, ++{167, 102, 136}, ++{179, 95, 139}, ++{191, 88, 143}, ++{204, 81, 146}, ++{217, 74, 150}, ++{219, 73, 150}, ++{152, 115, 130}, ++{160, 110, 133}, ++{170, 103, 136}, ++{181, 96, 140}, ++{194, 88, 143}, ++{207, 81, 147}, ++{220, 75, 150}, ++{221, 74, 151}, ++{156, 116, 131}, ++{163, 110, 133}, ++{173, 104, 137}, ++{184, 97, 140}, ++{197, 89, 143}, ++{209, 82, 147}, ++{222, 75, 150}, ++{224, 75, 151}, ++{160, 116, 132}, ++{167, 111, 134}, ++{176, 104, 137}, ++{188, 97, 140}, ++{199, 90, 144}, ++{212, 83, 147}, ++{224, 76, 150}, ++{226, 75, 151}, ++{163, 117, 132}, ++{170, 112, 134}, ++{180, 105, 137}, ++{191, 98, 141}, ++{202, 91, 144}, ++{214, 84, 147}, ++{227, 77, 151}, ++{228, 76, 151}, ++{167, 117, 133}, ++{174, 112, 135}, ++{183, 106, 138}, ++{194, 99, 141}, ++{205, 92, 144}, ++{217, 85, 148}, ++{229, 78, 151}, ++{231, 77, 151}, ++{171, 118, 133}, ++{178, 113, 136}, ++{187, 106, 138}, ++{197, 100, 141}, ++{208, 92, 144}, ++{220, 85, 148}, ++{232, 79, 151}, ++{233, 78, 151}, ++{173, 118, 134}, ++{180, 113, 136}, ++{188, 107, 138}, ++{198, 100, 141}, ++{210, 93, 145}, ++{221, 86, 148}, ++{233, 79, 151}, ++{235, 78, 151}, ++{173, 118, 134}, ++{180, 113, 136}, ++{188, 107, 138}, ++{198, 100, 141}, ++{210, 93, 145}, ++{221, 86, 148}, ++{233, 79, 151}, ++{235, 78, 151}, ++{173, 118, 134}, ++{180, 113, 136}, ++{188, 107, 138}, ++{198, 100, 141}, ++{210, 93, 145}, ++{221, 86, 148}, ++{233, 79, 151}, ++{235, 78, 151}, ++{173, 118, 134}, ++{180, 113, 136}, ++{188, 107, 138}, ++{198, 100, 141}, ++{210, 93, 145}, ++{221, 86, 148}, ++{233, 79, 151}, ++{235, 78, 151}, ++{94, 96, 114}, ++{108, 91, 120}, ++{125, 86, 127}, ++{141, 80, 132}, ++{158, 74, 138}, ++{175, 68, 142}, ++{191, 62, 147}, ++{192, 61, 147}, ++{94, 96, 114}, ++{109, 92, 120}, ++{125, 86, 127}, ++{142, 80, 132}, ++{158, 74, 138}, ++{175, 68, 142}, ++{191, 62, 147}, ++{193, 61, 147}, ++{95, 96, 115}, ++{109, 92, 121}, ++{125, 86, 127}, ++{142, 80, 132}, ++{159, 74, 138}, ++{175, 68, 142}, ++{191, 62, 147}, ++{193, 61, 147}, ++{96, 97, 115}, ++{110, 92, 121}, ++{126, 87, 127}, ++{143, 80, 132}, ++{159, 74, 138}, ++{175, 68, 142}, ++{191, 62, 147}, ++{193, 61, 147}, ++{98, 98, 116}, ++{111, 93, 121}, ++{127, 87, 127}, ++{144, 81, 133}, ++{160, 74, 138}, ++{176, 68, 142}, ++{192, 62, 147}, ++{194, 62, 147}, ++{100, 99, 116}, ++{113, 94, 121}, ++{128, 88, 127}, ++{145, 81, 133}, ++{161, 75, 138}, ++{177, 69, 143}, ++{193, 63, 147}, ++{195, 62, 147}, ++{102, 100, 117}, ++{115, 95, 122}, ++{130, 88, 128}, ++{146, 82, 133}, ++{162, 75, 138}, ++{178, 69, 143}, ++{193, 63, 147}, ++{195, 62, 147}, ++{104, 101, 117}, ++{116, 95, 122}, ++{131, 89, 128}, ++{147, 82, 133}, ++{163, 76, 138}, ++{179, 70, 143}, ++{194, 64, 147}, ++{196, 63, 147}, ++{106, 102, 118}, ++{119, 96, 123}, ++{133, 90, 128}, ++{149, 83, 133}, ++{165, 77, 138}, ++{180, 70, 143}, ++{196, 64, 147}, ++{197, 63, 148}, ++{109, 103, 119}, ++{121, 97, 123}, ++{135, 91, 129}, ++{151, 84, 134}, ++{166, 77, 138}, ++{181, 71, 143}, ++{197, 65, 147}, ++{199, 64, 148}, ++{112, 104, 120}, ++{123, 98, 124}, ++{137, 92, 129}, ++{152, 85, 134}, ++{168, 78, 139}, ++{183, 71, 143}, ++{198, 65, 147}, ++{200, 64, 148}, ++{115, 105, 120}, ++{126, 99, 125}, ++{140, 92, 129}, ++{154, 86, 134}, ++{169, 79, 139}, ++{184, 72, 143}, ++{199, 66, 147}, ++{201, 65, 148}, ++{118, 106, 121}, ++{129, 100, 125}, ++{142, 93, 130}, ++{156, 86, 135}, ++{171, 79, 139}, ++{186, 73, 143}, ++{201, 66, 147}, ++{203, 66, 148}, ++{121, 107, 122}, ++{132, 101, 126}, ++{145, 94, 130}, ++{159, 87, 135}, ++{173, 80, 139}, ++{188, 74, 144}, ++{203, 67, 148}, ++{204, 66, 148}, ++{125, 108, 123}, ++{135, 102, 126}, ++{147, 95, 131}, ++{161, 88, 135}, ++{175, 81, 140}, ++{190, 74, 144}, ++{204, 68, 148}, ++{206, 67, 148}, ++{128, 109, 124}, ++{138, 103, 127}, ++{150, 96, 131}, ++{163, 89, 136}, ++{177, 82, 140}, ++{192, 75, 144}, ++{206, 69, 148}, ++{208, 68, 148}, ++{131, 110, 124}, ++{141, 104, 128}, ++{153, 97, 132}, ++{166, 90, 136}, ++{180, 83, 140}, ++{194, 76, 144}, ++{208, 69, 148}, ++{210, 69, 148}, ++{135, 111, 125}, ++{144, 105, 128}, ++{156, 98, 132}, ++{169, 91, 136}, ++{182, 84, 140}, ++{196, 77, 144}, ++{210, 70, 148}, ++{212, 69, 148}, ++{139, 111, 126}, ++{147, 106, 129}, ++{159, 99, 133}, ++{171, 92, 137}, ++{184, 84, 141}, ++{198, 78, 144}, ++{212, 71, 148}, ++{214, 70, 149}, ++{142, 112, 127}, ++{151, 107, 129}, ++{162, 100, 133}, ++{174, 92, 137}, ++{187, 85, 141}, ++{200, 78, 145}, ++{214, 72, 148}, ++{216, 71, 149}, ++{146, 113, 127}, ++{154, 107, 130}, ++{165, 100, 134}, ++{177, 93, 137}, ++{190, 86, 141}, ++{203, 79, 145}, ++{216, 72, 148}, ++{218, 72, 149}, ++{150, 114, 128}, ++{158, 108, 131}, ++{168, 101, 134}, ++{180, 94, 138}, ++{192, 87, 141}, ++{205, 80, 145}, ++{218, 73, 149}, ++{220, 72, 149}, ++{153, 114, 129}, ++{161, 109, 131}, ++{171, 102, 135}, ++{183, 95, 138}, ++{195, 88, 142}, ++{208, 81, 145}, ++{221, 74, 149}, ++{222, 73, 149}, ++{157, 115, 129}, ++{165, 109, 132}, ++{174, 103, 135}, ++{186, 96, 138}, ++{198, 89, 142}, ++{210, 82, 146}, ++{223, 75, 149}, ++{224, 74, 149}, ++{161, 115, 130}, ++{168, 110, 132}, ++{178, 104, 135}, ++{189, 97, 139}, ++{200, 90, 142}, ++{213, 83, 146}, ++{225, 76, 149}, ++{227, 75, 150}, ++{165, 116, 131}, ++{172, 111, 133}, ++{181, 104, 136}, ++{192, 97, 139}, ++{203, 90, 143}, ++{215, 83, 146}, ++{228, 77, 149}, ++{229, 76, 150}, ++{168, 116, 131}, ++{175, 111, 134}, ++{184, 105, 136}, ++{195, 98, 140}, ++{206, 91, 143}, ++{218, 84, 146}, ++{230, 77, 150}, ++{232, 77, 150}, ++{172, 117, 132}, ++{179, 112, 134}, ++{188, 106, 137}, ++{198, 99, 140}, ++{209, 92, 143}, ++{221, 85, 146}, ++{233, 78, 150}, ++{234, 77, 150}, ++{174, 117, 132}, ++{181, 112, 134}, ++{189, 106, 137}, ++{199, 99, 140}, ++{210, 92, 143}, ++{222, 85, 147}, ++{234, 79, 150}, ++{235, 78, 150}, ++{174, 117, 132}, ++{181, 112, 134}, ++{189, 106, 137}, ++{199, 99, 140}, ++{210, 92, 143}, ++{222, 85, 147}, ++{234, 79, 150}, ++{235, 78, 150}, ++{174, 117, 132}, ++{181, 112, 134}, ++{189, 106, 137}, ++{199, 99, 140}, ++{210, 92, 143}, ++{222, 85, 147}, ++{234, 79, 150}, ++{235, 78, 150}, ++{174, 117, 132}, ++{181, 112, 134}, ++{189, 106, 137}, ++{199, 99, 140}, ++{210, 92, 143}, ++{222, 85, 147}, ++{234, 79, 150}, ++{235, 78, 150}, ++{97, 94, 112}, ++{111, 90, 118}, ++{127, 85, 124}, ++{143, 79, 130}, ++{160, 73, 136}, ++{176, 67, 140}, ++{192, 61, 145}, ++{194, 60, 145}, ++{97, 94, 112}, ++{111, 90, 118}, ++{127, 85, 124}, ++{143, 79, 130}, ++{160, 73, 136}, ++{176, 67, 140}, ++{192, 61, 145}, ++{194, 60, 145}, ++{98, 94, 112}, ++{111, 90, 118}, ++{127, 85, 124}, ++{144, 79, 130}, ++{160, 73, 136}, ++{176, 67, 140}, ++{192, 61, 145}, ++{194, 61, 145}, ++{99, 95, 113}, ++{112, 91, 118}, ++{128, 85, 125}, ++{144, 79, 130}, ++{161, 73, 136}, ++{177, 67, 141}, ++{193, 62, 145}, ++{194, 61, 146}, ++{100, 96, 113}, ++{113, 91, 119}, ++{129, 86, 125}, ++{145, 80, 130}, ++{161, 74, 136}, ++{177, 68, 141}, ++{193, 62, 145}, ++{195, 61, 146}, ++{102, 97, 114}, ++{115, 92, 119}, ++{130, 86, 125}, ++{146, 80, 131}, ++{162, 74, 136}, ++{178, 68, 141}, ++{194, 62, 145}, ++{196, 61, 146}, ++{104, 98, 114}, ++{117, 93, 120}, ++{132, 87, 125}, ++{147, 81, 131}, ++{163, 75, 136}, ++{179, 69, 141}, ++{195, 63, 145}, ++{197, 62, 146}, ++{106, 99, 115}, ++{118, 94, 120}, ++{133, 88, 126}, ++{149, 82, 131}, ++{165, 75, 136}, ++{180, 69, 141}, ++{196, 63, 145}, ++{197, 62, 146}, ++{109, 100, 116}, ++{121, 95, 121}, ++{135, 89, 126}, ++{150, 82, 131}, ++{166, 76, 136}, ++{181, 70, 141}, ++{197, 63, 145}, ++{199, 63, 146}, ++{111, 101, 117}, ++{123, 96, 121}, ++{137, 89, 126}, ++{152, 83, 132}, ++{167, 76, 137}, ++{183, 70, 141}, ++{198, 64, 145}, ++{200, 63, 146}, ++{114, 102, 117}, ++{125, 97, 122}, ++{139, 90, 127}, ++{154, 84, 132}, ++{169, 77, 137}, ++{184, 71, 141}, ++{199, 65, 146}, ++{201, 64, 146}, ++{117, 103, 118}, ++{128, 98, 122}, ++{141, 91, 127}, ++{156, 85, 132}, ++{171, 78, 137}, ++{186, 71, 141}, ++{201, 65, 146}, ++{202, 64, 146}, ++{120, 104, 119}, ++{131, 99, 123}, ++{144, 92, 128}, ++{158, 85, 133}, ++{173, 79, 137}, ++{187, 72, 142}, ++{202, 66, 146}, ++{204, 65, 146}, ++{123, 105, 120}, ++{133, 100, 124}, ++{146, 93, 128}, ++{160, 86, 133}, ++{175, 80, 138}, ++{189, 73, 142}, ++{204, 67, 146}, ++{205, 66, 146}, ++{126, 106, 121}, ++{136, 101, 124}, ++{149, 94, 129}, ++{162, 87, 133}, ++{177, 80, 138}, ++{191, 74, 142}, ++{205, 67, 146}, ++{207, 67, 147}, ++{130, 107, 121}, ++{139, 102, 125}, ++{151, 95, 129}, ++{165, 88, 134}, ++{179, 81, 138}, ++{193, 74, 142}, ++{207, 68, 146}, ++{209, 67, 147}, ++{133, 108, 122}, ++{142, 103, 126}, ++{154, 96, 130}, ++{167, 89, 134}, ++{181, 82, 138}, ++{195, 75, 142}, ++{209, 69, 146}, ++{211, 68, 147}, ++{137, 109, 123}, ++{146, 104, 126}, ++{157, 97, 130}, ++{170, 90, 134}, ++{183, 83, 139}, ++{197, 76, 143}, ++{211, 70, 147}, ++{213, 69, 147}, ++{140, 110, 124}, ++{149, 104, 127}, ++{160, 98, 131}, ++{173, 91, 135}, ++{186, 84, 139}, ++{199, 77, 143}, ++{213, 70, 147}, ++{215, 70, 147}, ++{144, 111, 125}, ++{152, 105, 128}, ++{163, 99, 131}, ++{175, 92, 135}, ++{188, 85, 139}, ++{201, 78, 143}, ++{215, 71, 147}, ++{217, 70, 147}, ++{147, 112, 125}, ++{156, 106, 128}, ++{166, 100, 132}, ++{178, 92, 136}, ++{191, 85, 140}, ++{204, 79, 143}, ++{217, 72, 147}, ++{219, 71, 148}, ++{151, 112, 126}, ++{159, 107, 129}, ++{169, 100, 132}, ++{181, 93, 136}, ++{193, 86, 140}, ++{206, 79, 144}, ++{219, 73, 147}, ++{221, 72, 148}, ++{155, 113, 127}, ++{162, 108, 130}, ++{172, 101, 133}, ++{184, 94, 136}, ++{196, 87, 140}, ++{209, 80, 144}, ++{222, 74, 147}, ++{223, 73, 148}, ++{158, 114, 128}, ++{166, 108, 130}, ++{176, 102, 133}, ++{187, 95, 137}, ++{199, 88, 140}, ++{211, 81, 144}, ++{224, 74, 148}, ++{225, 74, 148}, ++{162, 114, 128}, ++{169, 109, 131}, ++{179, 103, 134}, ++{190, 96, 137}, ++{201, 89, 141}, ++{214, 82, 144}, ++{226, 75, 148}, ++{228, 74, 148}, ++{166, 115, 129}, ++{173, 110, 131}, ++{182, 103, 134}, ++{193, 97, 138}, ++{204, 90, 141}, ++{216, 83, 145}, ++{229, 76, 148}, ++{230, 75, 148}, ++{170, 115, 130}, ++{176, 110, 132}, ++{185, 104, 135}, ++{196, 97, 138}, ++{207, 90, 141}, ++{219, 84, 145}, ++{231, 77, 148}, ++{233, 76, 149}, ++{173, 116, 130}, ++{180, 111, 133}, ++{189, 105, 135}, ++{199, 98, 138}, ++{210, 91, 142}, ++{222, 84, 145}, ++{234, 78, 148}, ++{235, 77, 149}, ++{175, 116, 131}, ++{182, 111, 133}, ++{191, 105, 136}, ++{201, 99, 139}, ++{212, 92, 142}, ++{223, 85, 145}, ++{235, 78, 149}, ++{236, 77, 149}, ++{175, 116, 131}, ++{182, 111, 133}, ++{191, 105, 136}, ++{201, 99, 139}, ++{212, 92, 142}, ++{223, 85, 145}, ++{235, 78, 149}, ++{236, 77, 149}, ++{175, 116, 131}, ++{182, 111, 133}, ++{191, 105, 136}, ++{201, 99, 139}, ++{212, 92, 142}, ++{223, 85, 145}, ++{235, 78, 149}, ++{236, 77, 149}, ++{175, 116, 131}, ++{182, 111, 133}, ++{191, 105, 136}, ++{201, 99, 139}, ++{212, 92, 142}, ++{223, 85, 145}, ++{235, 78, 149}, ++{236, 77, 149}, ++{99, 91, 109}, ++{113, 88, 115}, ++{129, 83, 122}, ++{145, 78, 128}, ++{161, 72, 133}, ++{177, 66, 138}, ++{193, 61, 143}, ++{195, 60, 144}, ++{100, 92, 110}, ++{113, 88, 116}, ++{129, 83, 122}, ++{145, 78, 128}, ++{161, 72, 133}, ++{177, 66, 138}, ++{193, 61, 143}, ++{195, 60, 144}, ++{100, 92, 110}, ++{114, 88, 116}, ++{129, 84, 122}, ++{145, 78, 128}, ++{162, 72, 133}, ++{178, 66, 138}, ++{193, 61, 143}, ++{195, 60, 144}, ++{101, 93, 110}, ++{114, 89, 116}, ++{130, 84, 122}, ++{146, 78, 128}, ++{162, 72, 134}, ++{178, 67, 139}, ++{194, 61, 143}, ++{196, 60, 144}, ++{103, 94, 111}, ++{116, 90, 116}, ++{131, 84, 122}, ++{147, 79, 128}, ++{163, 73, 134}, ++{179, 67, 139}, ++{194, 61, 143}, ++{196, 60, 144}, ++{104, 95, 111}, ++{117, 90, 117}, ++{132, 85, 123}, ++{148, 79, 128}, ++{164, 73, 134}, ++{180, 67, 139}, ++{195, 62, 143}, ++{197, 61, 144}, ++{106, 96, 112}, ++{119, 91, 117}, ++{134, 86, 123}, ++{149, 80, 129}, ++{165, 74, 134}, ++{180, 68, 139}, ++{196, 62, 143}, ++{198, 61, 144}, ++{109, 97, 113}, ++{121, 92, 118}, ++{135, 86, 123}, ++{150, 80, 129}, ++{166, 74, 134}, ++{182, 68, 139}, ++{197, 62, 143}, ++{199, 62, 144}, ++{111, 98, 113}, ++{123, 93, 118}, ++{137, 87, 124}, ++{152, 81, 129}, ++{167, 75, 134}, ++{183, 69, 139}, ++{198, 63, 144}, ++{200, 62, 144}, ++{113, 99, 114}, ++{125, 94, 119}, ++{139, 88, 124}, ++{154, 82, 130}, ++{169, 76, 135}, ++{184, 69, 139}, ++{199, 63, 144}, ++{201, 63, 144}, ++{116, 100, 115}, ++{127, 95, 120}, ++{141, 89, 125}, ++{155, 83, 130}, ++{170, 76, 135}, ++{185, 70, 139}, ++{200, 64, 144}, ++{202, 63, 144}, ++{119, 101, 116}, ++{130, 96, 120}, ++{143, 90, 125}, ++{157, 84, 130}, ++{172, 77, 135}, ++{187, 71, 140}, ++{202, 65, 144}, ++{204, 64, 144}, ++{122, 103, 117}, ++{132, 97, 121}, ++{145, 91, 126}, ++{159, 84, 131}, ++{174, 78, 135}, ++{189, 71, 140}, ++{203, 65, 144}, ++{205, 65, 145}, ++{125, 104, 118}, ++{135, 98, 122}, ++{148, 92, 126}, ++{162, 85, 131}, ++{176, 79, 136}, ++{190, 72, 140}, ++{205, 66, 144}, ++{207, 65, 145}, ++{128, 105, 118}, ++{138, 99, 122}, ++{150, 93, 127}, ++{164, 86, 131}, ++{178, 80, 136}, ++{192, 73, 140}, ++{206, 67, 144}, ++{208, 66, 145}, ++{132, 106, 119}, ++{141, 100, 123}, ++{153, 94, 127}, ++{166, 87, 132}, ++{180, 80, 136}, ++{194, 74, 140}, ++{208, 67, 145}, ++{210, 67, 145}, ++{135, 107, 120}, ++{144, 101, 124}, ++{156, 95, 128}, ++{169, 88, 132}, ++{182, 81, 137}, ++{196, 75, 141}, ++{210, 68, 145}, ++{212, 67, 145}, ++{138, 108, 121}, ++{147, 102, 124}, ++{159, 96, 128}, ++{171, 89, 133}, ++{185, 82, 137}, ++{198, 75, 141}, ++{212, 69, 145}, ++{214, 68, 145}, ++{142, 108, 122}, ++{151, 103, 125}, ++{162, 97, 129}, ++{174, 90, 133}, ++{187, 83, 137}, ++{200, 76, 141}, ++{214, 70, 145}, ++{216, 69, 146}, ++{146, 109, 123}, ++{154, 104, 126}, ++{165, 98, 129}, ++{177, 91, 133}, ++{189, 84, 137}, ++{203, 77, 141}, ++{216, 71, 145}, ++{218, 70, 146}, ++{149, 110, 123}, ++{157, 105, 126}, ++{168, 98, 130}, ++{179, 92, 134}, ++{192, 85, 138}, ++{205, 78, 142}, ++{218, 71, 145}, ++{220, 71, 146}, ++{153, 111, 124}, ++{160, 106, 127}, ++{171, 99, 131}, ++{182, 92, 134}, ++{195, 86, 138}, ++{207, 79, 142}, ++{220, 72, 146}, ++{222, 71, 146}, ++{156, 112, 125}, ++{164, 106, 128}, ++{174, 100, 131}, ++{185, 93, 135}, ++{197, 86, 138}, ++{210, 80, 142}, ++{223, 73, 146}, ++{224, 72, 146}, ++{160, 112, 126}, ++{167, 107, 128}, ++{177, 101, 132}, ++{188, 94, 135}, ++{200, 87, 139}, ++{212, 80, 143}, ++{225, 74, 146}, ++{226, 73, 147}, ++{164, 113, 127}, ++{171, 108, 129}, ++{180, 102, 132}, ++{191, 95, 136}, ++{203, 88, 139}, ++{215, 81, 143}, ++{227, 75, 146}, ++{229, 74, 147}, ++{167, 114, 127}, ++{174, 109, 130}, ++{183, 102, 133}, ++{194, 96, 136}, ++{205, 89, 140}, ++{217, 82, 143}, ++{230, 75, 147}, ++{231, 75, 147}, ++{171, 114, 128}, ++{178, 109, 130}, ++{187, 103, 133}, ++{197, 97, 136}, ++{208, 90, 140}, ++{220, 83, 143}, ++{232, 76, 147}, ++{234, 75, 147}, ++{175, 115, 129}, ++{181, 110, 131}, ++{190, 104, 134}, ++{200, 97, 137}, ++{211, 91, 140}, ++{223, 84, 144}, ++{235, 77, 147}, ++{236, 76, 147}, ++{177, 115, 129}, ++{183, 110, 131}, ++{192, 104, 134}, ++{202, 98, 137}, ++{213, 91, 140}, ++{224, 84, 144}, ++{236, 77, 147}, ++{237, 77, 148}, ++{177, 115, 129}, ++{183, 110, 131}, ++{192, 104, 134}, ++{202, 98, 137}, ++{213, 91, 140}, ++{224, 84, 144}, ++{236, 77, 147}, ++{237, 77, 148}, ++{177, 115, 129}, ++{183, 110, 131}, ++{192, 104, 134}, ++{202, 98, 137}, ++{213, 91, 140}, ++{224, 84, 144}, ++{236, 77, 147}, ++{237, 77, 148}, ++{177, 115, 129}, ++{183, 110, 131}, ++{192, 104, 134}, ++{202, 98, 137}, ++{213, 91, 140}, ++{224, 84, 144}, ++{236, 77, 147}, ++{237, 77, 148}, ++{102, 89, 107}, ++{115, 86, 113}, ++{131, 82, 119}, ++{147, 77, 126}, ++{163, 71, 131}, ++{179, 65, 136}, ++{194, 60, 141}, ++{196, 59, 142}, ++{102, 89, 107}, ++{115, 86, 113}, ++{131, 82, 120}, ++{147, 77, 126}, ++{163, 71, 131}, ++{179, 65, 136}, ++{194, 60, 141}, ++{196, 59, 142}, ++{103, 90, 107}, ++{116, 87, 113}, ++{131, 82, 120}, ++{147, 77, 126}, ++{163, 71, 131}, ++{179, 66, 136}, ++{195, 60, 141}, ++{197, 59, 142}, ++{104, 90, 108}, ++{117, 87, 114}, ++{132, 82, 120}, ++{148, 77, 126}, ++{164, 72, 131}, ++{180, 66, 137}, ++{195, 60, 141}, ++{197, 60, 142}, ++{105, 91, 108}, ++{118, 88, 114}, ++{133, 83, 120}, ++{149, 78, 126}, ++{165, 72, 132}, ++{180, 66, 137}, ++{196, 61, 141}, ++{198, 60, 142}, ++{107, 92, 109}, ++{119, 89, 114}, ++{134, 84, 120}, ++{150, 78, 126}, ++{165, 72, 132}, ++{181, 67, 137}, ++{196, 61, 141}, ++{198, 60, 142}, ++{109, 93, 109}, ++{121, 89, 115}, ++{135, 84, 121}, ++{151, 79, 126}, ++{166, 73, 132}, ++{182, 67, 137}, ++{197, 61, 141}, ++{199, 61, 142}, ++{111, 95, 110}, ++{123, 90, 115}, ++{137, 85, 121}, ++{152, 79, 127}, ++{168, 73, 132}, ++{183, 68, 137}, ++{198, 62, 142}, ++{200, 61, 142}, ++{113, 96, 111}, ++{125, 91, 116}, ++{139, 86, 122}, ++{154, 80, 127}, ++{169, 74, 132}, ++{184, 68, 137}, ++{199, 62, 142}, ++{201, 61, 142}, ++{116, 97, 112}, ++{127, 92, 117}, ++{141, 87, 122}, ++{155, 81, 127}, ++{170, 75, 133}, ++{185, 69, 137}, ++{200, 63, 142}, ++{202, 62, 142}, ++{118, 98, 113}, ++{129, 94, 117}, ++{143, 88, 122}, ++{157, 82, 128}, ++{172, 75, 133}, ++{187, 69, 138}, ++{202, 63, 142}, ++{203, 63, 143}, ++{121, 99, 114}, ++{132, 95, 118}, ++{145, 89, 123}, ++{159, 82, 128}, ++{174, 76, 133}, ++{188, 70, 138}, ++{203, 64, 142}, ++{205, 63, 143}, ++{124, 101, 114}, ++{134, 96, 119}, ++{147, 90, 124}, ++{161, 83, 129}, ++{175, 77, 133}, ++{190, 71, 138}, ++{204, 65, 142}, ++{206, 64, 143}, ++{127, 102, 115}, ++{137, 97, 119}, ++{150, 91, 124}, ++{163, 84, 129}, ++{177, 78, 134}, ++{192, 71, 138}, ++{206, 65, 142}, ++{208, 65, 143}, ++{130, 103, 116}, ++{140, 98, 120}, ++{152, 92, 125}, ++{166, 85, 129}, ++{179, 79, 134}, ++{194, 72, 138}, ++{208, 66, 143}, ++{209, 65, 143}, ++{134, 104, 117}, ++{143, 99, 121}, ++{155, 93, 125}, ++{168, 86, 130}, ++{182, 79, 134}, ++{195, 73, 139}, ++{209, 67, 143}, ++{211, 66, 143}, ++{137, 105, 118}, ++{146, 100, 121}, ++{157, 94, 126}, ++{170, 87, 130}, ++{184, 80, 135}, ++{197, 74, 139}, ++{211, 68, 143}, ++{213, 67, 144}, ++{140, 106, 119}, ++{149, 101, 122}, ++{160, 95, 126}, ++{173, 88, 131}, ++{186, 81, 135}, ++{200, 75, 139}, ++{213, 68, 143}, ++{215, 68, 144}, ++{144, 107, 120}, ++{152, 102, 123}, ++{163, 95, 127}, ++{175, 89, 131}, ++{188, 82, 135}, ++{202, 75, 139}, ++{215, 69, 143}, ++{217, 68, 144}, ++{147, 108, 121}, ++{155, 103, 124}, ++{166, 96, 127}, ++{178, 90, 132}, ++{191, 83, 136}, ++{204, 76, 140}, ++{217, 70, 144}, ++{219, 69, 144}, ++{151, 109, 121}, ++{159, 104, 124}, ++{169, 97, 128}, ++{181, 91, 132}, ++{193, 84, 136}, ++{206, 77, 140}, ++{219, 71, 144}, ++{221, 70, 144}, ++{154, 109, 122}, ++{162, 104, 125}, ++{172, 98, 129}, ++{184, 91, 132}, ++{196, 85, 136}, ++{209, 78, 140}, ++{221, 72, 144}, ++{223, 71, 145}, ++{158, 110, 123}, ++{165, 105, 126}, ++{175, 99, 129}, ++{186, 92, 133}, ++{198, 86, 137}, ++{211, 79, 141}, ++{224, 72, 144}, ++{225, 72, 145}, ++{162, 111, 124}, ++{169, 106, 126}, ++{178, 100, 130}, ++{189, 93, 133}, ++{201, 86, 137}, ++{213, 80, 141}, ++{226, 73, 145}, ++{228, 72, 145}, ++{165, 112, 125}, ++{172, 107, 127}, ++{182, 101, 130}, ++{192, 94, 134}, ++{204, 87, 138}, ++{216, 81, 141}, ++{228, 74, 145}, ++{230, 73, 145}, ++{169, 112, 125}, ++{176, 107, 128}, ++{185, 101, 131}, ++{195, 95, 134}, ++{207, 88, 138}, ++{219, 81, 142}, ++{231, 75, 145}, ++{232, 74, 146}, ++{173, 113, 126}, ++{179, 108, 128}, ++{188, 102, 131}, ++{198, 96, 135}, ++{209, 89, 138}, ++{221, 82, 142}, ++{233, 76, 145}, ++{235, 75, 146}, ++{176, 113, 127}, ++{183, 109, 129}, ++{191, 103, 132}, ++{201, 96, 135}, ++{212, 90, 139}, ++{224, 83, 142}, ++{236, 76, 146}, ++{237, 76, 146}, ++{178, 114, 127}, ++{184, 109, 129}, ++{193, 103, 132}, ++{203, 97, 135}, ++{214, 90, 139}, ++{225, 83, 142}, ++{237, 77, 146}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 109, 129}, ++{193, 103, 132}, ++{203, 97, 135}, ++{214, 90, 139}, ++{225, 83, 142}, ++{237, 77, 146}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 109, 129}, ++{193, 103, 132}, ++{203, 97, 135}, ++{214, 90, 139}, ++{225, 83, 142}, ++{237, 77, 146}, ++{238, 76, 146}, ++{178, 114, 127}, ++{184, 109, 129}, ++{193, 103, 132}, ++{203, 97, 135}, ++{214, 90, 139}, ++{225, 83, 142}, ++{237, 77, 146}, ++{238, 76, 146}, ++{105, 87, 105}, ++{118, 84, 111}, ++{133, 80, 117}, ++{149, 75, 123}, ++{165, 70, 129}, ++{180, 65, 134}, ++{196, 59, 139}, ++{198, 58, 140}, ++{105, 87, 105}, ++{118, 84, 111}, ++{133, 80, 117}, ++{149, 75, 123}, ++{165, 70, 129}, ++{180, 65, 134}, ++{196, 59, 139}, ++{198, 58, 140}, ++{106, 87, 105}, ++{118, 85, 111}, ++{133, 80, 117}, ++{149, 76, 123}, ++{165, 70, 129}, ++{181, 65, 134}, ++{196, 59, 139}, ++{198, 59, 140}, ++{107, 88, 105}, ++{119, 85, 111}, ++{134, 81, 117}, ++{150, 76, 124}, ++{166, 71, 129}, ++{181, 65, 134}, ++{197, 60, 139}, ++{198, 59, 140}, ++{108, 89, 106}, ++{120, 86, 111}, ++{135, 81, 118}, ++{151, 76, 124}, ++{166, 71, 129}, ++{182, 65, 135}, ++{197, 60, 139}, ++{199, 59, 140}, ++{110, 90, 106}, ++{122, 87, 112}, ++{136, 82, 118}, ++{152, 77, 124}, ++{167, 71, 130}, ++{183, 66, 135}, ++{198, 60, 139}, ++{200, 59, 140}, ++{111, 91, 107}, ++{123, 88, 112}, ++{138, 83, 118}, ++{153, 77, 124}, ++{168, 72, 130}, ++{183, 66, 135}, ++{199, 61, 140}, ++{200, 60, 140}, ++{113, 92, 108}, ++{125, 88, 113}, ++{139, 84, 119}, ++{154, 78, 125}, ++{169, 72, 130}, ++{184, 67, 135}, ++{200, 61, 140}, ++{201, 60, 140}, ++{116, 94, 109}, ++{127, 90, 114}, ++{141, 84, 119}, ++{156, 79, 125}, ++{171, 73, 130}, ++{186, 67, 135}, ++{201, 61, 140}, ++{202, 61, 140}, ++{118, 95, 109}, ++{129, 91, 114}, ++{143, 85, 120}, ++{157, 80, 125}, ++{172, 74, 130}, ++{187, 68, 135}, ++{202, 62, 140}, ++{204, 61, 141}, ++{121, 96, 110}, ++{131, 92, 115}, ++{145, 86, 120}, ++{159, 80, 126}, ++{174, 74, 131}, ++{188, 68, 136}, ++{203, 63, 140}, ++{205, 62, 141}, ++{124, 97, 111}, ++{134, 93, 116}, ++{147, 87, 121}, ++{161, 81, 126}, ++{175, 75, 131}, ++{190, 69, 136}, ++{204, 63, 140}, ++{206, 63, 141}, ++{126, 99, 112}, ++{137, 94, 116}, ++{149, 88, 121}, ++{163, 82, 126}, ++{177, 76, 131}, ++{191, 70, 136}, ++{206, 64, 140}, ++{208, 63, 141}, ++{129, 100, 113}, ++{139, 95, 117}, ++{151, 89, 122}, ++{165, 83, 127}, ++{179, 77, 132}, ++{193, 71, 136}, ++{207, 65, 141}, ++{209, 64, 141}, ++{133, 101, 114}, ++{142, 96, 118}, ++{154, 90, 122}, ++{167, 84, 127}, ++{181, 78, 132}, ++{195, 71, 137}, ++{209, 65, 141}, ++{211, 65, 141}, ++{136, 102, 115}, ++{145, 97, 119}, ++{157, 91, 123}, ++{169, 85, 128}, ++{183, 79, 132}, ++{197, 72, 137}, ++{211, 66, 141}, ++{212, 65, 142}, ++{139, 103, 116}, ++{148, 98, 119}, ++{159, 92, 124}, ++{172, 86, 128}, ++{185, 79, 133}, ++{199, 73, 137}, ++{213, 67, 141}, ++{214, 66, 142}, ++{142, 104, 117}, ++{151, 99, 120}, ++{162, 93, 124}, ++{174, 87, 129}, ++{187, 80, 133}, ++{201, 74, 137}, ++{214, 68, 141}, ++{216, 67, 142}, ++{146, 105, 118}, ++{154, 100, 121}, ++{165, 94, 125}, ++{177, 88, 129}, ++{190, 81, 133}, ++{203, 75, 138}, ++{216, 68, 142}, ++{218, 68, 142}, ++{149, 106, 119}, ++{157, 101, 122}, ++{168, 95, 125}, ++{180, 89, 130}, ++{192, 82, 134}, ++{205, 76, 138}, ++{218, 69, 142}, ++{220, 68, 142}, ++{153, 107, 119}, ++{160, 102, 122}, ++{171, 96, 126}, ++{182, 90, 130}, ++{195, 83, 134}, ++{207, 76, 138}, ++{220, 70, 142}, ++{222, 69, 143}, ++{156, 108, 120}, ++{164, 103, 123}, ++{174, 97, 127}, ++{185, 90, 131}, ++{197, 84, 135}, ++{210, 77, 139}, ++{223, 71, 142}, ++{224, 70, 143}, ++{160, 109, 121}, ++{167, 104, 124}, ++{177, 98, 127}, ++{188, 91, 131}, ++{200, 85, 135}, ++{212, 78, 139}, ++{225, 72, 143}, ++{226, 71, 143}, ++{163, 109, 122}, ++{170, 105, 125}, ++{180, 99, 128}, ++{191, 92, 132}, ++{202, 86, 135}, ++{215, 79, 139}, ++{227, 72, 143}, ++{229, 72, 143}, ++{167, 110, 123}, ++{174, 105, 125}, ++{183, 100, 128}, ++{194, 93, 132}, ++{205, 86, 136}, ++{217, 80, 140}, ++{229, 73, 143}, ++{231, 73, 144}, ++{170, 111, 124}, ++{177, 106, 126}, ++{186, 100, 129}, ++{197, 94, 133}, ++{208, 87, 136}, ++{220, 81, 140}, ++{232, 74, 144}, ++{233, 73, 144}, ++{174, 112, 124}, ++{181, 107, 127}, ++{189, 101, 130}, ++{200, 95, 133}, ++{211, 88, 137}, ++{222, 81, 140}, ++{234, 75, 144}, ++{236, 74, 144}, ++{178, 112, 125}, ++{184, 108, 127}, ++{193, 102, 130}, ++{203, 95, 134}, ++{214, 89, 137}, ++{225, 82, 141}, ++{237, 76, 144}, ++{238, 75, 144}, ++{180, 112, 125}, ++{186, 108, 128}, ++{194, 102, 131}, ++{204, 96, 134}, ++{215, 89, 137}, ++{226, 83, 141}, ++{238, 76, 144}, ++{239, 75, 145}, ++{180, 112, 125}, ++{186, 108, 128}, ++{194, 102, 131}, ++{204, 96, 134}, ++{215, 89, 137}, ++{226, 83, 141}, ++{238, 76, 144}, ++{239, 75, 145}, ++{180, 112, 125}, ++{186, 108, 128}, ++{194, 102, 131}, ++{204, 96, 134}, ++{215, 89, 137}, ++{226, 83, 141}, ++{238, 76, 144}, ++{239, 75, 145}, ++{180, 112, 125}, ++{186, 108, 128}, ++{194, 102, 131}, ++{204, 96, 134}, ++{215, 89, 137}, ++{226, 83, 141}, ++{238, 76, 144}, ++{239, 75, 145}, ++{108, 84, 102}, ++{120, 82, 108}, ++{135, 78, 115}, ++{151, 74, 121}, ++{166, 69, 127}, ++{182, 64, 132}, ++{197, 58, 137}, ++{199, 58, 138}, ++{108, 84, 102}, ++{120, 82, 108}, ++{135, 79, 115}, ++{151, 74, 121}, ++{166, 69, 127}, ++{182, 64, 132}, ++{197, 58, 137}, ++{199, 58, 138}, ++{108, 85, 103}, ++{121, 83, 108}, ++{136, 79, 115}, ++{151, 74, 121}, ++{167, 69, 127}, ++{182, 64, 132}, ++{198, 59, 137}, ++{199, 58, 138}, ++{109, 86, 103}, ++{122, 83, 109}, ++{136, 79, 115}, ++{152, 75, 121}, ++{167, 69, 127}, ++{183, 64, 132}, ++{198, 59, 137}, ++{200, 58, 138}, ++{111, 87, 103}, ++{123, 84, 109}, ++{137, 80, 115}, ++{152, 75, 121}, ++{168, 70, 127}, ++{183, 64, 132}, ++{199, 59, 137}, ++{200, 58, 138}, ++{112, 88, 104}, ++{124, 85, 110}, ++{138, 80, 116}, ++{153, 76, 122}, ++{169, 70, 127}, ++{184, 65, 133}, ++{199, 59, 137}, ++{201, 59, 138}, ++{114, 89, 105}, ++{126, 86, 110}, ++{140, 81, 116}, ++{155, 76, 122}, ++{170, 71, 128}, ++{185, 65, 133}, ++{200, 60, 138}, ++{202, 59, 138}, ++{116, 90, 105}, ++{127, 87, 111}, ++{141, 82, 116}, ++{156, 77, 122}, ++{171, 71, 128}, ++{186, 66, 133}, ++{201, 60, 138}, ++{203, 60, 138}, ++{118, 91, 106}, ++{129, 88, 111}, ++{143, 83, 117}, ++{157, 78, 123}, ++{172, 72, 128}, ++{187, 66, 133}, ++{202, 61, 138}, ++{204, 60, 138}, ++{121, 93, 107}, ++{131, 89, 112}, ++{145, 84, 117}, ++{159, 78, 123}, ++{174, 73, 128}, ++{188, 67, 133}, ++{203, 61, 138}, ++{205, 61, 139}, ++{123, 94, 108}, ++{134, 90, 113}, ++{147, 85, 118}, ++{161, 79, 123}, ++{175, 73, 129}, ++{190, 68, 134}, ++{204, 62, 138}, ++{206, 61, 139}, ++{126, 95, 109}, ++{136, 91, 113}, ++{149, 86, 119}, ++{163, 80, 124}, ++{177, 74, 129}, ++{191, 68, 134}, ++{206, 62, 138}, ++{208, 62, 139}, ++{129, 96, 110}, ++{139, 92, 114}, ++{151, 87, 119}, ++{165, 81, 124}, ++{179, 75, 129}, ++{193, 69, 134}, ++{207, 63, 139}, ++{209, 62, 139}, ++{132, 98, 111}, ++{141, 93, 115}, ++{153, 88, 120}, ++{167, 82, 125}, ++{181, 76, 130}, ++{195, 70, 134}, ++{209, 64, 139}, ++{210, 63, 139}, ++{135, 99, 112}, ++{144, 94, 116}, ++{156, 89, 120}, ++{169, 83, 125}, ++{182, 77, 130}, ++{196, 71, 135}, ++{210, 65, 139}, ++{212, 64, 140}, ++{138, 100, 113}, ++{147, 96, 116}, ++{158, 90, 121}, ++{171, 84, 126}, ++{185, 77, 130}, ++{198, 71, 135}, ++{212, 65, 139}, ++{214, 65, 140}, ++{141, 101, 114}, ++{150, 97, 117}, ++{161, 91, 122}, ++{174, 85, 126}, ++{187, 78, 131}, ++{200, 72, 135}, ++{214, 66, 139}, ++{216, 65, 140}, ++{144, 102, 115}, ++{153, 98, 118}, ++{164, 92, 122}, ++{176, 86, 127}, ++{189, 79, 131}, ++{202, 73, 135}, ++{216, 67, 140}, ++{217, 66, 140}, ++{148, 103, 116}, ++{156, 99, 119}, ++{167, 93, 123}, ++{179, 87, 127}, ++{191, 80, 132}, ++{204, 74, 136}, ++{218, 68, 140}, ++{219, 67, 140}, ++{151, 104, 116}, ++{159, 100, 120}, ++{169, 94, 123}, ++{181, 87, 128}, ++{194, 81, 132}, ++{207, 75, 136}, ++{220, 68, 140}, ++{221, 68, 141}, ++{154, 105, 117}, ++{162, 101, 120}, ++{172, 95, 124}, ++{184, 88, 128}, ++{196, 82, 132}, ++{209, 76, 136}, ++{222, 69, 140}, ++{223, 68, 141}, ++{158, 106, 118}, ++{165, 102, 121}, ++{175, 96, 125}, ++{187, 89, 129}, ++{199, 83, 133}, ++{211, 76, 137}, ++{224, 70, 141}, ++{225, 69, 141}, ++{161, 107, 119}, ++{169, 102, 122}, ++{178, 97, 125}, ++{189, 90, 129}, ++{201, 84, 133}, ++{214, 77, 137}, ++{226, 71, 141}, ++{228, 70, 142}, ++{165, 108, 120}, ++{172, 103, 123}, ++{181, 97, 126}, ++{192, 91, 130}, ++{204, 85, 134}, ++{216, 78, 137}, ++{228, 72, 141}, ++{230, 71, 142}, ++{169, 109, 121}, ++{175, 104, 123}, ++{185, 98, 127}, ++{195, 92, 130}, ++{207, 85, 134}, ++{218, 79, 138}, ++{231, 73, 142}, ++{232, 72, 142}, ++{172, 109, 122}, ++{179, 105, 124}, ++{188, 99, 127}, ++{198, 93, 131}, ++{209, 86, 134}, ++{221, 80, 138}, ++{233, 73, 142}, ++{235, 73, 142}, ++{176, 110, 122}, ++{182, 106, 125}, ++{191, 100, 128}, ++{201, 94, 131}, ++{212, 87, 135}, ++{224, 81, 139}, ++{235, 74, 142}, ++{237, 73, 143}, ++{179, 111, 123}, ++{186, 106, 126}, ++{194, 101, 128}, ++{204, 94, 132}, ++{215, 88, 135}, ++{226, 82, 139}, ++{238, 75, 142}, ++{239, 74, 143}, ++{181, 111, 124}, ++{187, 107, 126}, ++{196, 101, 129}, ++{206, 95, 132}, ++{216, 88, 136}, ++{228, 82, 139}, ++{239, 75, 143}, ++{241, 75, 143}, ++{181, 111, 124}, ++{187, 107, 126}, ++{196, 101, 129}, ++{206, 95, 132}, ++{216, 88, 136}, ++{228, 82, 139}, ++{239, 75, 143}, ++{241, 75, 143}, ++{181, 111, 124}, ++{187, 107, 126}, ++{196, 101, 129}, ++{206, 95, 132}, ++{216, 88, 136}, ++{228, 82, 139}, ++{239, 75, 143}, ++{241, 75, 143}, ++{181, 111, 124}, ++{187, 107, 126}, ++{196, 101, 129}, ++{206, 95, 132}, ++{216, 88, 136}, ++{228, 82, 139}, ++{239, 75, 143}, ++{241, 75, 143}, ++{110, 82, 100}, ++{123, 80, 106}, ++{137, 77, 112}, ++{153, 73, 119}, ++{168, 68, 125}, ++{183, 63, 130}, ++{199, 58, 135}, ++{201, 57, 136}, ++{111, 82, 100}, ++{123, 80, 106}, ++{137, 77, 112}, ++{153, 73, 119}, ++{168, 68, 125}, ++{184, 63, 130}, ++{199, 58, 135}, ++{201, 57, 136}, ++{111, 82, 100}, ++{123, 81, 106}, ++{138, 77, 113}, ++{153, 73, 119}, ++{169, 68, 125}, ++{184, 63, 130}, ++{199, 58, 135}, ++{201, 57, 136}, ++{112, 83, 101}, ++{124, 81, 106}, ++{138, 78, 113}, ++{154, 73, 119}, ++{169, 68, 125}, ++{184, 63, 130}, ++{199, 58, 135}, ++{201, 57, 136}, ++{113, 84, 101}, ++{125, 82, 107}, ++{139, 78, 113}, ++{154, 74, 119}, ++{170, 69, 125}, ++{185, 63, 130}, ++{200, 58, 135}, ++{202, 58, 136}, ++{115, 85, 102}, ++{126, 83, 107}, ++{140, 79, 113}, ++{155, 74, 119}, ++{171, 69, 125}, ++{186, 64, 131}, ++{201, 59, 135}, ++{203, 58, 136}, ++{117, 86, 102}, ++{128, 84, 108}, ++{142, 80, 114}, ++{157, 75, 120}, ++{172, 70, 125}, ++{187, 64, 131}, ++{201, 59, 136}, ++{203, 58, 136}, ++{119, 88, 103}, ++{130, 85, 108}, ++{143, 80, 114}, ++{158, 75, 120}, ++{173, 70, 126}, ++{188, 65, 131}, ++{202, 59, 136}, ++{204, 59, 136}, ++{121, 89, 104}, ++{132, 86, 109}, ++{145, 81, 115}, ++{159, 76, 120}, ++{174, 71, 126}, ++{189, 65, 131}, ++{203, 60, 136}, ++{205, 59, 136}, ++{123, 90, 105}, ++{134, 87, 110}, ++{147, 82, 115}, ++{161, 77, 121}, ++{175, 72, 126}, ++{190, 66, 131}, ++{205, 60, 136}, ++{206, 60, 137}, ++{126, 92, 106}, ++{136, 88, 110}, ++{149, 83, 116}, ++{163, 78, 121}, ++{177, 72, 126}, ++{191, 67, 132}, ++{206, 61, 136}, ++{208, 60, 137}, ++{128, 93, 107}, ++{138, 89, 111}, ++{151, 84, 116}, ++{164, 79, 122}, ++{179, 73, 127}, ++{193, 67, 132}, ++{207, 62, 136}, ++{209, 61, 137}, ++{131, 94, 108}, ++{141, 90, 112}, ++{153, 85, 117}, ++{166, 80, 122}, ++{180, 74, 127}, ++{194, 68, 132}, ++{209, 62, 137}, ++{210, 62, 137}, ++{134, 96, 109}, ++{143, 91, 113}, ++{155, 86, 117}, ++{168, 81, 123}, ++{182, 75, 128}, ++{196, 69, 132}, ++{210, 63, 137}, ++{212, 62, 137}, ++{137, 97, 110}, ++{146, 93, 113}, ++{158, 87, 118}, ++{171, 81, 123}, ++{184, 76, 128}, ++{198, 70, 133}, ++{212, 64, 137}, ++{213, 63, 138}, ++{140, 98, 111}, ++{149, 94, 114}, ++{160, 88, 119}, ++{173, 82, 124}, ++{186, 76, 128}, ++{200, 70, 133}, ++{213, 64, 137}, ++{215, 64, 138}, ++{143, 99, 111}, ++{152, 95, 115}, ++{163, 89, 119}, ++{175, 83, 124}, ++{188, 77, 129}, ++{202, 71, 133}, ++{215, 65, 138}, ++{217, 65, 138}, ++{146, 100, 112}, ++{155, 96, 116}, ++{166, 90, 120}, ++{178, 84, 125}, ++{190, 78, 129}, ++{204, 72, 134}, ++{217, 66, 138}, ++{219, 65, 138}, ++{150, 102, 113}, ++{158, 97, 117}, ++{168, 91, 121}, ++{180, 85, 125}, ++{193, 79, 130}, ++{206, 73, 134}, ++{219, 67, 138}, ++{221, 66, 139}, ++{153, 103, 114}, ++{161, 98, 117}, ++{171, 92, 121}, ++{183, 86, 126}, ++{195, 80, 130}, ++{208, 74, 134}, ++{221, 68, 138}, ++{223, 67, 139}, ++{156, 104, 115}, ++{164, 99, 118}, ++{174, 93, 122}, ++{185, 87, 126}, ++{198, 81, 130}, ++{210, 75, 135}, ++{223, 68, 139}, ++{225, 68, 139}, ++{160, 105, 116}, ++{167, 100, 119}, ++{177, 94, 123}, ++{188, 88, 127}, ++{200, 82, 131}, ++{212, 76, 135}, ++{225, 69, 139}, ++{227, 69, 140}, ++{163, 105, 117}, ++{170, 101, 120}, ++{180, 95, 123}, ++{191, 89, 127}, ++{203, 83, 131}, ++{215, 76, 135}, ++{227, 70, 139}, ++{229, 69, 140}, ++{167, 106, 118}, ++{174, 102, 121}, ++{183, 96, 124}, ++{194, 90, 128}, ++{205, 84, 132}, ++{217, 77, 136}, ++{230, 71, 140}, ++{231, 70, 140}, ++{170, 107, 119}, ++{177, 103, 121}, ++{186, 97, 125}, ++{197, 91, 128}, ++{208, 85, 132}, ++{220, 78, 136}, ++{232, 72, 140}, ++{233, 71, 140}, ++{174, 108, 120}, ++{180, 103, 122}, ++{189, 98, 125}, ++{200, 92, 129}, ++{211, 85, 133}, ++{222, 79, 136}, ++{234, 73, 140}, ++{236, 72, 141}, ++{177, 109, 121}, ++{184, 104, 123}, ++{192, 99, 126}, ++{202, 93, 130}, ++{213, 86, 133}, ++{225, 80, 137}, ++{237, 73, 141}, ++{238, 73, 141}, ++{181, 109, 121}, ++{187, 105, 124}, ++{196, 100, 127}, ++{205, 93, 130}, ++{216, 87, 134}, ++{227, 81, 137}, ++{239, 74, 141}, ++{241, 74, 141}, ++{183, 110, 122}, ++{189, 105, 124}, ++{197, 100, 127}, ++{207, 94, 130}, ++{218, 87, 134}, ++{229, 81, 137}, ++{240, 75, 141}, ++{242, 74, 141}, ++{183, 110, 122}, ++{189, 105, 124}, ++{197, 100, 127}, ++{207, 94, 130}, ++{218, 87, 134}, ++{229, 81, 137}, ++{240, 75, 141}, ++{242, 74, 141}, ++{183, 110, 122}, ++{189, 105, 124}, ++{197, 100, 127}, ++{207, 94, 130}, ++{218, 87, 134}, ++{229, 81, 137}, ++{240, 75, 141}, ++{242, 74, 141}, ++{183, 110, 122}, ++{189, 105, 124}, ++{197, 100, 127}, ++{207, 94, 130}, ++{218, 87, 134}, ++{229, 81, 137}, ++{240, 75, 141}, ++{242, 74, 141}, ++{113, 79, 98}, ++{125, 78, 103}, ++{139, 75, 110}, ++{155, 71, 116}, ++{170, 67, 122}, ++{185, 62, 128}, ++{200, 57, 133}, ++{202, 56, 134}, ++{113, 79, 98}, ++{125, 78, 104}, ++{140, 75, 110}, ++{155, 71, 116}, ++{170, 67, 122}, ++{185, 62, 128}, ++{200, 57, 133}, ++{202, 56, 134}, ++{114, 80, 98}, ++{126, 78, 104}, ++{140, 75, 110}, ++{155, 71, 117}, ++{170, 67, 123}, ++{186, 62, 128}, ++{201, 57, 133}, ++{202, 56, 134}, ++{115, 81, 98}, ++{127, 79, 104}, ++{141, 76, 110}, ++{156, 72, 117}, ++{171, 67, 123}, ++{186, 62, 128}, ++{201, 57, 133}, ++{203, 56, 134}, ++{116, 82, 99}, ++{128, 80, 104}, ++{142, 76, 111}, ++{156, 72, 117}, ++{172, 67, 123}, ++{187, 62, 128}, ++{202, 57, 133}, ++{203, 57, 134}, ++{118, 83, 99}, ++{129, 80, 105}, ++{143, 77, 111}, ++{157, 73, 117}, ++{172, 68, 123}, ++{187, 63, 128}, ++{202, 58, 133}, ++{204, 57, 134}, ++{119, 84, 100}, ++{130, 81, 105}, ++{144, 78, 111}, ++{158, 73, 117}, ++{173, 68, 123}, ++{188, 63, 129}, ++{203, 58, 134}, ++{205, 57, 134}, ++{121, 85, 101}, ++{132, 82, 106}, ++{145, 79, 112}, ++{160, 74, 118}, ++{174, 69, 123}, ++{189, 64, 129}, ++{204, 59, 134}, ++{206, 58, 134}, ++{123, 87, 102}, ++{134, 84, 107}, ++{147, 80, 112}, ++{161, 75, 118}, ++{176, 70, 124}, ++{190, 64, 129}, ++{205, 59, 134}, ++{207, 58, 135}, ++{126, 88, 103}, ++{136, 85, 107}, ++{149, 80, 113}, ++{163, 76, 119}, ++{177, 70, 124}, ++{192, 65, 129}, ++{206, 60, 134}, ++{208, 59, 135}, ++{128, 89, 103}, ++{138, 86, 108}, ++{151, 81, 113}, ++{164, 76, 119}, ++{179, 71, 124}, ++{193, 66, 129}, ++{207, 60, 134}, ++{209, 59, 135}, ++{131, 91, 104}, ++{140, 87, 109}, ++{153, 83, 114}, ++{166, 77, 119}, ++{180, 72, 125}, ++{194, 66, 130}, ++{209, 61, 135}, ++{210, 60, 135}, ++{133, 92, 105}, ++{143, 88, 110}, ++{155, 84, 115}, ++{168, 78, 120}, ++{182, 73, 125}, ++{196, 67, 130}, ++{210, 61, 135}, ++{212, 61, 135}, ++{136, 93, 106}, ++{145, 90, 110}, ++{157, 85, 115}, ++{170, 79, 120}, ++{184, 74, 125}, ++{198, 68, 130}, ++{212, 62, 135}, ++{213, 61, 136}, ++{139, 95, 107}, ++{148, 91, 111}, ++{160, 86, 116}, ++{172, 80, 121}, ++{186, 74, 126}, ++{199, 69, 131}, ++{213, 63, 135}, ++{215, 62, 136}, ++{142, 96, 108}, ++{151, 92, 112}, ++{162, 87, 117}, ++{175, 81, 121}, ++{188, 75, 126}, ++{201, 69, 131}, ++{215, 64, 135}, ++{217, 63, 136}, ++{145, 97, 109}, ++{154, 93, 113}, ++{165, 88, 117}, ++{177, 82, 122}, ++{190, 76, 127}, ++{203, 70, 131}, ++{217, 64, 136}, ++{218, 64, 136}, ++{148, 98, 110}, ++{157, 94, 114}, ++{167, 89, 118}, ++{179, 83, 123}, ++{192, 77, 127}, ++{205, 71, 132}, ++{218, 65, 136}, ++{220, 64, 137}, ++{152, 100, 111}, ++{160, 95, 115}, ++{170, 90, 119}, ++{182, 84, 123}, ++{194, 78, 128}, ++{207, 72, 132}, ++{220, 66, 136}, ++{222, 65, 137}, ++{155, 101, 112}, ++{163, 96, 115}, ++{173, 91, 119}, ++{184, 85, 124}, ++{197, 79, 128}, ++{209, 73, 132}, ++{222, 67, 137}, ++{224, 66, 137}, ++{158, 102, 113}, ++{166, 97, 116}, ++{176, 92, 120}, ++{187, 86, 124}, ++{199, 80, 129}, ++{212, 74, 133}, ++{224, 68, 137}, ++{226, 67, 137}, ++{162, 103, 114}, ++{169, 98, 117}, ++{179, 93, 121}, ++{190, 87, 125}, ++{202, 81, 129}, ++{214, 75, 133}, ++{226, 68, 137}, ++{228, 68, 138}, ++{165, 104, 115}, ++{172, 99, 118}, ++{182, 94, 121}, ++{192, 88, 125}, ++{204, 82, 129}, ++{216, 75, 134}, ++{229, 69, 138}, ++{230, 69, 138}, ++{169, 105, 116}, ++{175, 100, 119}, ++{185, 95, 122}, ++{195, 89, 126}, ++{207, 83, 130}, ++{219, 76, 134}, ++{231, 70, 138}, ++{232, 69, 138}, ++{172, 105, 117}, ++{179, 101, 119}, ++{188, 96, 123}, ++{198, 90, 127}, ++{209, 83, 130}, ++{221, 77, 134}, ++{233, 71, 138}, ++{235, 70, 139}, ++{175, 106, 118}, ++{182, 102, 120}, ++{191, 97, 123}, ++{201, 91, 127}, ++{212, 84, 131}, ++{224, 78, 135}, ++{235, 72, 139}, ++{237, 71, 139}, ++{179, 107, 119}, ++{185, 103, 121}, ++{194, 97, 124}, ++{204, 91, 128}, ++{215, 85, 131}, ++{226, 79, 135}, ++{238, 73, 139}, ++{239, 72, 139}, ++{183, 108, 119}, ++{189, 104, 122}, ++{197, 98, 125}, ++{207, 92, 128}, ++{218, 86, 132}, ++{229, 80, 136}, ++{240, 74, 139}, ++{242, 73, 140}, ++{184, 108, 120}, ++{191, 104, 122}, ++{199, 99, 125}, ++{208, 93, 129}, ++{219, 87, 132}, ++{230, 80, 136}, ++{242, 74, 139}, ++{243, 73, 140}, ++{184, 108, 120}, ++{191, 104, 122}, ++{199, 99, 125}, ++{208, 93, 129}, ++{219, 87, 132}, ++{230, 80, 136}, ++{242, 74, 139}, ++{243, 73, 140}, ++{184, 108, 120}, ++{191, 104, 122}, ++{199, 99, 125}, ++{208, 93, 129}, ++{219, 87, 132}, ++{230, 80, 136}, ++{242, 74, 139}, ++{243, 73, 140}, ++{184, 108, 120}, ++{191, 104, 122}, ++{199, 99, 125}, ++{208, 93, 129}, ++{219, 87, 132}, ++{230, 80, 136}, ++{242, 74, 139}, ++{243, 73, 140}, ++{116, 77, 95}, ++{128, 76, 101}, ++{142, 73, 108}, ++{157, 70, 114}, ++{172, 65, 120}, ++{187, 61, 126}, ++{202, 56, 131}, ++{204, 55, 132}, ++{116, 77, 95}, ++{128, 76, 101}, ++{142, 73, 108}, ++{157, 70, 114}, ++{172, 65, 120}, ++{187, 61, 126}, ++{202, 56, 131}, ++{204, 55, 132}, ++{117, 77, 96}, ++{128, 76, 101}, ++{142, 74, 108}, ++{157, 70, 114}, ++{172, 66, 120}, ++{187, 61, 126}, ++{202, 56, 131}, ++{204, 55, 132}, ++{118, 78, 96}, ++{129, 77, 102}, ++{143, 74, 108}, ++{158, 70, 114}, ++{173, 66, 120}, ++{188, 61, 126}, ++{203, 56, 131}, ++{204, 55, 132}, ++{119, 79, 97}, ++{130, 78, 102}, ++{144, 75, 108}, ++{158, 71, 115}, ++{173, 66, 121}, ++{188, 61, 126}, ++{203, 56, 131}, ++{205, 56, 132}, ++{120, 80, 97}, ++{131, 78, 103}, ++{145, 75, 109}, ++{159, 71, 115}, ++{174, 67, 121}, ++{189, 62, 126}, ++{204, 57, 131}, ++{206, 56, 132}, ++{122, 81, 98}, ++{133, 79, 103}, ++{146, 76, 109}, ++{160, 72, 115}, ++{175, 67, 121}, ++{190, 62, 126}, ++{205, 57, 132}, ++{206, 57, 132}, ++{124, 83, 99}, ++{134, 80, 104}, ++{148, 77, 110}, ++{162, 73, 116}, ++{176, 68, 121}, ++{191, 63, 127}, ++{205, 58, 132}, ++{207, 57, 132}, ++{126, 84, 99}, ++{136, 82, 104}, ++{149, 78, 110}, ++{163, 73, 116}, ++{178, 68, 122}, ++{192, 63, 127}, ++{206, 58, 132}, ++{208, 57, 133}, ++{128, 86, 100}, ++{138, 83, 105}, ++{151, 79, 111}, ++{165, 74, 116}, ++{179, 69, 122}, ++{193, 64, 127}, ++{208, 59, 132}, ++{209, 58, 133}, ++{131, 87, 101}, ++{140, 84, 106}, ++{153, 80, 111}, ++{166, 75, 117}, ++{180, 70, 122}, ++{195, 65, 127}, ++{209, 59, 132}, ++{211, 59, 133}, ++{133, 88, 102}, ++{143, 85, 107}, ++{155, 81, 112}, ++{168, 76, 117}, ++{182, 71, 123}, ++{196, 65, 128}, ++{210, 60, 133}, ++{212, 59, 133}, ++{136, 90, 103}, ++{145, 86, 107}, ++{157, 82, 112}, ++{170, 77, 118}, ++{184, 71, 123}, ++{198, 66, 128}, ++{212, 61, 133}, ++{213, 60, 133}, ++{139, 91, 104}, ++{148, 88, 108}, ++{159, 83, 113}, ++{172, 78, 118}, ++{186, 72, 123}, ++{199, 67, 128}, ++{213, 61, 133}, ++{215, 61, 134}, ++{141, 93, 105}, ++{150, 89, 109}, ++{162, 84, 114}, ++{174, 79, 119}, ++{187, 73, 124}, ++{201, 68, 129}, ++{215, 62, 133}, ++{216, 61, 134}, ++{144, 94, 106}, ++{153, 90, 110}, ++{164, 85, 114}, ++{176, 80, 119}, ++{189, 74, 124}, ++{203, 68, 129}, ++{216, 63, 134}, ++{218, 62, 134}, ++{147, 95, 107}, ++{156, 91, 111}, ++{167, 86, 115}, ++{179, 81, 120}, ++{192, 75, 125}, ++{205, 69, 129}, ++{218, 64, 134}, ++{220, 63, 134}, ++{151, 96, 108}, ++{159, 92, 112}, ++{169, 87, 116}, ++{181, 82, 121}, ++{194, 76, 125}, ++{207, 70, 130}, ++{220, 64, 134}, ++{221, 64, 135}, ++{154, 98, 109}, ++{162, 94, 112}, ++{172, 88, 117}, ++{184, 83, 121}, ++{196, 77, 126}, ++{209, 71, 130}, ++{222, 65, 134}, ++{223, 64, 135}, ++{157, 99, 110}, ++{165, 95, 113}, ++{175, 89, 117}, ++{186, 84, 122}, ++{198, 78, 126}, ++{211, 72, 131}, ++{224, 66, 135}, ++{225, 65, 135}, ++{160, 100, 111}, ++{168, 96, 114}, ++{178, 91, 118}, ++{189, 85, 122}, ++{201, 79, 127}, ++{213, 73, 131}, ++{226, 67, 135}, ++{227, 66, 136}, ++{164, 101, 112}, ++{171, 97, 115}, ++{180, 92, 119}, ++{191, 86, 123}, ++{203, 80, 127}, ++{215, 74, 131}, ++{228, 68, 135}, ++{229, 67, 136}, ++{167, 102, 113}, ++{174, 98, 116}, ++{183, 92, 119}, ++{194, 87, 123}, ++{206, 81, 128}, ++{218, 75, 132}, ++{230, 68, 136}, ++{232, 68, 136}, ++{170, 103, 114}, ++{177, 99, 117}, ++{186, 93, 120}, ++{197, 88, 124}, ++{208, 82, 128}, ++{220, 75, 132}, ++{232, 69, 136}, ++{234, 69, 137}, ++{174, 104, 115}, ++{180, 100, 118}, ++{189, 94, 121}, ++{200, 89, 125}, ++{211, 82, 129}, ++{222, 76, 133}, ++{234, 70, 136}, ++{236, 69, 137}, ++{177, 105, 116}, ++{184, 101, 118}, ++{192, 95, 122}, ++{203, 89, 125}, ++{213, 83, 129}, ++{225, 77, 133}, ++{237, 71, 137}, ++{238, 70, 137}, ++{181, 106, 117}, ++{187, 101, 119}, ++{196, 96, 122}, ++{205, 90, 126}, ++{216, 84, 130}, ++{227, 78, 133}, ++{239, 72, 137}, ++{241, 71, 138}, ++{184, 106, 118}, ++{190, 102, 120}, ++{199, 97, 123}, ++{208, 91, 126}, ++{219, 85, 130}, ++{230, 79, 134}, ++{242, 73, 138}, ++{243, 72, 138}, ++{186, 107, 118}, ++{192, 103, 120}, ++{200, 97, 123}, ++{210, 92, 127}, ++{220, 86, 130}, ++{231, 79, 134}, ++{243, 73, 138}, ++{244, 72, 138}, ++{186, 107, 118}, ++{192, 103, 120}, ++{200, 97, 123}, ++{210, 92, 127}, ++{220, 86, 130}, ++{231, 79, 134}, ++{243, 73, 138}, ++{244, 72, 138}, ++{186, 107, 118}, ++{192, 103, 120}, ++{200, 97, 123}, ++{210, 92, 127}, ++{220, 86, 130}, ++{231, 79, 134}, ++{243, 73, 138}, ++{244, 72, 138}, ++{186, 107, 118}, ++{192, 103, 120}, ++{200, 97, 123}, ++{210, 92, 127}, ++{220, 86, 130}, ++{231, 79, 134}, ++{243, 73, 138}, ++{244, 72, 138}, ++{119, 74, 93}, ++{130, 74, 99}, ++{144, 71, 105}, ++{159, 68, 112}, ++{174, 64, 118}, ++{189, 59, 124}, ++{203, 55, 129}, ++{205, 54, 130}, ++{119, 74, 93}, ++{130, 74, 99}, ++{144, 71, 105}, ++{159, 68, 112}, ++{174, 64, 118}, ++{189, 60, 124}, ++{203, 55, 129}, ++{205, 54, 130}, ++{120, 75, 93}, ++{131, 74, 99}, ++{145, 72, 106}, ++{159, 68, 112}, ++{174, 64, 118}, ++{189, 60, 124}, ++{204, 55, 129}, ++{206, 54, 130}, ++{120, 76, 94}, ++{132, 75, 99}, ++{145, 72, 106}, ++{160, 69, 112}, ++{175, 65, 118}, ++{189, 60, 124}, ++{204, 55, 129}, ++{206, 55, 130}, ++{122, 77, 94}, ++{133, 75, 100}, ++{146, 73, 106}, ++{160, 69, 112}, ++{175, 65, 118}, ++{190, 60, 124}, ++{205, 55, 129}, ++{206, 55, 130}, ++{123, 78, 95}, ++{134, 76, 100}, ++{147, 73, 106}, ++{161, 70, 113}, ++{176, 65, 119}, ++{191, 61, 124}, ++{205, 56, 129}, ++{207, 55, 130}, ++{125, 79, 96}, ++{135, 77, 101}, ++{148, 74, 107}, ++{162, 70, 113}, ++{177, 66, 119}, ++{192, 61, 124}, ++{206, 56, 130}, ++{208, 56, 130}, ++{126, 80, 96}, ++{137, 78, 101}, ++{150, 75, 107}, ++{164, 71, 113}, ++{178, 66, 119}, ++{193, 62, 125}, ++{207, 57, 130}, ++{209, 56, 130}, ++{128, 82, 97}, ++{139, 79, 102}, ++{151, 76, 108}, ++{165, 72, 114}, ++{179, 67, 119}, ++{194, 62, 125}, ++{208, 57, 130}, ++{210, 57, 131}, ++{131, 83, 98}, ++{141, 81, 103}, ++{153, 77, 108}, ++{167, 73, 114}, ++{181, 68, 120}, ++{195, 63, 125}, ++{209, 58, 130}, ++{211, 57, 131}, ++{133, 85, 99}, ++{143, 82, 104}, ++{155, 78, 109}, ++{168, 74, 115}, ++{182, 69, 120}, ++{196, 64, 125}, ++{210, 58, 130}, ++{212, 58, 131}, ++{136, 86, 100}, ++{145, 83, 104}, ++{157, 79, 110}, ++{170, 74, 115}, ++{184, 69, 121}, ++{198, 64, 126}, ++{212, 59, 131}, ++{213, 58, 131}, ++{138, 88, 101}, ++{147, 84, 105}, ++{159, 80, 110}, ++{172, 75, 116}, ++{185, 70, 121}, ++{199, 65, 126}, ++{213, 60, 131}, ++{215, 59, 131}, ++{141, 89, 102}, ++{150, 86, 106}, ++{161, 81, 111}, ++{174, 76, 116}, ++{187, 71, 121}, ++{201, 66, 126}, ++{214, 60, 131}, ++{216, 60, 132}, ++{144, 90, 103}, ++{152, 87, 107}, ++{164, 82, 112}, ++{176, 77, 117}, ++{189, 72, 122}, ++{203, 67, 127}, ++{216, 61, 131}, ++{218, 60, 132}, ++{147, 92, 104}, ++{155, 88, 108}, ++{166, 84, 112}, ++{178, 78, 117}, ++{191, 73, 122}, ++{204, 67, 127}, ++{218, 62, 132}, ++{219, 61, 132}, ++{150, 93, 105}, ++{158, 89, 109}, ++{169, 85, 113}, ++{180, 79, 118}, ++{193, 74, 123}, ++{206, 68, 127}, ++{219, 63, 132}, ++{221, 62, 133}, ++{153, 94, 106}, ++{161, 91, 109}, ++{171, 86, 114}, ++{183, 80, 118}, ++{195, 75, 123}, ++{208, 69, 128}, ++{221, 63, 132}, ++{223, 63, 133}, ++{156, 96, 107}, ++{164, 92, 110}, ++{174, 87, 115}, ++{185, 81, 119}, ++{198, 76, 124}, ++{210, 70, 128}, ++{223, 64, 133}, ++{225, 64, 133}, ++{159, 97, 108}, ++{167, 93, 111}, ++{177, 88, 115}, ++{188, 82, 120}, ++{200, 77, 124}, ++{212, 71, 129}, ++{225, 65, 133}, ++{227, 64, 134}, ++{162, 98, 109}, ++{170, 94, 112}, ++{179, 89, 116}, ++{190, 83, 120}, ++{202, 78, 125}, ++{215, 72, 129}, ++{227, 66, 133}, ++{229, 65, 134}, ++{166, 99, 110}, ++{173, 95, 113}, ++{182, 90, 117}, ++{193, 84, 121}, ++{205, 79, 125}, ++{217, 73, 129}, ++{229, 67, 134}, ++{231, 66, 134}, ++{169, 100, 111}, ++{176, 96, 114}, ++{185, 91, 117}, ++{196, 85, 122}, ++{207, 79, 126}, ++{219, 74, 130}, ++{231, 68, 134}, ++{233, 67, 135}, ++{172, 101, 112}, ++{179, 97, 115}, ++{188, 92, 118}, ++{198, 86, 122}, ++{210, 80, 126}, ++{221, 74, 130}, ++{234, 68, 134}, ++{235, 68, 135}, ++{176, 102, 113}, ++{182, 98, 116}, ++{191, 93, 119}, ++{201, 87, 123}, ++{212, 81, 127}, ++{224, 75, 131}, ++{236, 69, 135}, ++{237, 69, 135}, ++{179, 103, 114}, ++{185, 99, 116}, ++{194, 94, 120}, ++{204, 88, 123}, ++{215, 82, 127}, ++{226, 76, 131}, ++{238, 70, 135}, ++{240, 69, 136}, ++{182, 104, 115}, ++{189, 100, 117}, ++{197, 95, 120}, ++{207, 89, 124}, ++{218, 83, 128}, ++{229, 77, 132}, ++{240, 71, 135}, ++{242, 70, 136}, ++{186, 105, 116}, ++{192, 101, 118}, ++{200, 96, 121}, ++{210, 90, 125}, ++{220, 84, 128}, ++{231, 78, 132}, ++{243, 72, 136}, ++{244, 71, 136}, ++{188, 105, 116}, ++{194, 101, 118}, ++{202, 96, 121}, ++{211, 90, 125}, ++{222, 84, 129}, ++{233, 78, 132}, ++{244, 72, 136}, ++{245, 72, 137}, ++{188, 105, 116}, ++{194, 101, 118}, ++{202, 96, 121}, ++{211, 90, 125}, ++{222, 84, 129}, ++{233, 78, 132}, ++{244, 72, 136}, ++{245, 72, 137}, ++{188, 105, 116}, ++{194, 101, 118}, ++{202, 96, 121}, ++{211, 90, 125}, ++{222, 84, 129}, ++{233, 78, 132}, ++{244, 72, 136}, ++{245, 72, 137}, ++{188, 105, 116}, ++{194, 101, 118}, ++{202, 96, 121}, ++{211, 90, 125}, ++{222, 84, 129}, ++{233, 78, 132}, ++{244, 72, 136}, ++{245, 72, 137}, ++{122, 72, 91}, ++{133, 71, 97}, ++{146, 69, 103}, ++{161, 66, 110}, ++{176, 63, 116}, ++{190, 58, 122}, ++{205, 54, 127}, ++{207, 53, 128}, ++{122, 72, 91}, ++{133, 72, 97}, ++{146, 70, 103}, ++{161, 67, 110}, ++{176, 63, 116}, ++{190, 58, 122}, ++{205, 54, 127}, ++{207, 53, 128}, ++{122, 72, 91}, ++{133, 72, 97}, ++{147, 70, 103}, ++{161, 67, 110}, ++{176, 63, 116}, ++{191, 59, 122}, ++{205, 54, 127}, ++{207, 53, 128}, ++{123, 73, 92}, ++{134, 72, 97}, ++{147, 70, 104}, ++{162, 67, 110}, ++{176, 63, 116}, ++{191, 59, 122}, ++{206, 54, 127}, ++{208, 54, 128}, ++{124, 74, 92}, ++{135, 73, 98}, ++{148, 71, 104}, ++{163, 68, 110}, ++{177, 64, 116}, ++{192, 59, 122}, ++{206, 54, 127}, ++{208, 54, 128}, ++{126, 75, 93}, ++{136, 74, 98}, ++{149, 72, 104}, ++{163, 68, 110}, ++{178, 64, 116}, ++{192, 60, 122}, ++{207, 55, 127}, ++{209, 54, 128}, ++{127, 77, 94}, ++{138, 75, 99}, ++{151, 72, 105}, ++{165, 69, 111}, ++{179, 65, 117}, ++{193, 60, 122}, ++{208, 55, 128}, ++{209, 55, 128}, ++{129, 78, 94}, ++{139, 76, 99}, ++{152, 73, 105}, ++{166, 69, 111}, ++{180, 65, 117}, ++{194, 60, 123}, ++{209, 56, 128}, ++{210, 55, 128}, ++{131, 79, 95}, ++{141, 77, 100}, ++{153, 74, 106}, ++{167, 70, 112}, ++{181, 66, 117}, ++{195, 61, 123}, ++{210, 56, 128}, ++{211, 56, 129}, ++{133, 81, 96}, ++{143, 79, 101}, ++{155, 75, 106}, ++{169, 71, 112}, ++{182, 67, 118}, ++{197, 62, 123}, ++{211, 57, 128}, ++{212, 56, 129}, ++{136, 82, 97}, ++{145, 80, 101}, ++{157, 76, 107}, ++{170, 72, 113}, ++{184, 67, 118}, ++{198, 62, 123}, ++{212, 57, 128}, ++{214, 57, 129}, ++{138, 84, 98}, ++{147, 81, 102}, ++{159, 77, 108}, ++{172, 73, 113}, ++{186, 68, 118}, ++{199, 63, 124}, ++{213, 58, 129}, ++{215, 57, 129}, ++{141, 85, 99}, ++{150, 82, 103}, ++{161, 78, 108}, ++{174, 74, 114}, ++{187, 69, 119}, ++{201, 64, 124}, ++{215, 59, 129}, ++{216, 58, 129}, ++{143, 87, 100}, ++{152, 84, 104}, ++{163, 80, 109}, ++{176, 75, 114}, ++{189, 70, 119}, ++{202, 65, 124}, ++{216, 59, 129}, ++{218, 59, 130}, ++{146, 88, 101}, ++{155, 85, 105}, ++{166, 81, 110}, ++{178, 76, 115}, ++{191, 71, 120}, ++{204, 65, 125}, ++{218, 60, 129}, ++{219, 59, 130}, ++{149, 90, 102}, ++{157, 86, 106}, ++{168, 82, 110}, ++{180, 77, 115}, ++{193, 72, 120}, ++{206, 66, 125}, ++{219, 61, 130}, ++{221, 60, 130}, ++{152, 91, 103}, ++{160, 88, 107}, ++{170, 83, 111}, ++{182, 78, 116}, ++{195, 73, 121}, ++{208, 67, 125}, ++{221, 62, 130}, ++{223, 61, 131}, ++{155, 92, 104}, ++{163, 89, 107}, ++{173, 84, 112}, ++{185, 79, 116}, ++{197, 74, 121}, ++{210, 68, 126}, ++{223, 62, 130}, ++{224, 62, 131}, ++{158, 94, 105}, ++{166, 90, 108}, ++{176, 85, 112}, ++{187, 80, 117}, ++{199, 74, 122}, ++{212, 69, 126}, ++{225, 63, 131}, ++{226, 63, 131}, ++{161, 95, 106}, ++{169, 91, 109}, ++{178, 86, 113}, ++{190, 81, 118}, ++{201, 75, 122}, ++{214, 70, 127}, ++{227, 64, 131}, ++{228, 63, 132}, ++{164, 96, 107}, ++{172, 92, 110}, ++{181, 87, 114}, ++{192, 82, 118}, ++{204, 76, 123}, ++{216, 71, 127}, ++{229, 65, 131}, ++{230, 64, 132}, ++{168, 97, 108}, ++{175, 93, 111}, ++{184, 89, 115}, ++{195, 83, 119}, ++{206, 77, 123}, ++{218, 72, 128}, ++{231, 66, 132}, ++{232, 65, 132}, ++{171, 98, 109}, ++{178, 94, 112}, ++{187, 90, 116}, ++{197, 84, 120}, ++{209, 78, 124}, ++{221, 72, 128}, ++{233, 67, 132}, ++{234, 66, 133}, ++{174, 99, 110}, ++{181, 96, 113}, ++{190, 91, 116}, ++{200, 85, 120}, ++{211, 79, 124}, ++{223, 73, 128}, ++{235, 68, 133}, ++{236, 67, 133}, ++{177, 100, 111}, ++{184, 97, 114}, ++{193, 92, 117}, ++{203, 86, 121}, ++{214, 80, 125}, ++{225, 74, 129}, ++{237, 68, 133}, ++{239, 68, 133}, ++{181, 101, 112}, ++{187, 97, 114}, ++{196, 92, 118}, ++{206, 87, 122}, ++{216, 81, 125}, ++{228, 75, 129}, ++{239, 69, 133}, ++{241, 69, 134}, ++{184, 102, 113}, ++{190, 98, 115}, ++{199, 93, 119}, ++{209, 88, 122}, ++{219, 82, 126}, ++{230, 76, 130}, ++{242, 70, 134}, ++{243, 69, 134}, ++{188, 103, 114}, ++{194, 99, 116}, ++{202, 94, 119}, ++{211, 89, 123}, ++{222, 83, 127}, ++{233, 77, 130}, ++{244, 71, 134}, ++{246, 70, 135}, ++{189, 104, 114}, ++{195, 100, 117}, ++{203, 95, 120}, ++{213, 89, 123}, ++{223, 83, 127}, ++{234, 77, 131}, ++{245, 71, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 117}, ++{203, 95, 120}, ++{213, 89, 123}, ++{223, 83, 127}, ++{234, 77, 131}, ++{245, 71, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 117}, ++{203, 95, 120}, ++{213, 89, 123}, ++{223, 83, 127}, ++{234, 77, 131}, ++{245, 71, 134}, ++{247, 71, 135}, ++{189, 104, 114}, ++{195, 100, 117}, ++{203, 95, 120}, ++{213, 89, 123}, ++{223, 83, 127}, ++{234, 77, 131}, ++{245, 71, 134}, ++{247, 71, 135}, ++{124, 69, 89}, ++{135, 69, 95}, ++{149, 68, 101}, ++{163, 65, 107}, ++{177, 61, 114}, ++{192, 57, 120}, ++{207, 53, 125}, ++{208, 52, 126}, ++{125, 69, 89}, ++{135, 69, 95}, ++{149, 68, 101}, ++{163, 65, 108}, ++{178, 61, 114}, ++{192, 57, 120}, ++{207, 53, 125}, ++{209, 52, 126}, ++{125, 70, 89}, ++{136, 70, 95}, ++{149, 68, 101}, ++{163, 65, 108}, ++{178, 61, 114}, ++{192, 57, 120}, ++{207, 53, 125}, ++{209, 52, 126}, ++{126, 71, 90}, ++{137, 70, 95}, ++{150, 68, 101}, ++{164, 65, 108}, ++{178, 62, 114}, ++{193, 58, 120}, ++{207, 53, 125}, ++{209, 53, 126}, ++{127, 72, 90}, ++{138, 71, 95}, ++{151, 69, 102}, ++{165, 66, 108}, ++{179, 62, 114}, ++{193, 58, 120}, ++{208, 53, 125}, ++{210, 53, 126}, ++{128, 73, 91}, ++{139, 72, 96}, ++{152, 70, 102}, ++{165, 67, 108}, ++{180, 63, 114}, ++{194, 58, 120}, ++{209, 54, 125}, ++{210, 53, 126}, ++{130, 74, 91}, ++{140, 73, 97}, ++{153, 70, 103}, ++{167, 67, 109}, ++{181, 63, 115}, ++{195, 59, 120}, ++{209, 54, 126}, ++{211, 54, 126}, ++{132, 75, 92}, ++{142, 74, 97}, ++{154, 71, 103}, ++{168, 68, 109}, ++{182, 64, 115}, ++{196, 59, 120}, ++{210, 55, 126}, ++{212, 54, 126}, ++{134, 77, 93}, ++{143, 75, 98}, ++{156, 72, 104}, ++{169, 69, 109}, ++{183, 64, 115}, ++{197, 60, 121}, ++{211, 55, 126}, ++{213, 55, 127}, ++{136, 78, 94}, ++{145, 76, 99}, ++{157, 73, 104}, ++{171, 70, 110}, ++{184, 65, 116}, ++{198, 61, 121}, ++{212, 56, 126}, ++{214, 55, 127}, ++{138, 80, 95}, ++{147, 78, 99}, ++{159, 74, 105}, ++{172, 70, 110}, ++{186, 66, 116}, ++{200, 61, 121}, ++{213, 56, 126}, ++{215, 56, 127}, ++{140, 81, 96}, ++{150, 79, 100}, ++{161, 76, 105}, ++{174, 71, 111}, ++{187, 67, 116}, ++{201, 62, 122}, ++{215, 57, 127}, ++{216, 56, 127}, ++{143, 83, 97}, ++{152, 80, 101}, ++{163, 77, 106}, ++{176, 72, 111}, ++{189, 68, 117}, ++{202, 63, 122}, ++{216, 58, 127}, ++{218, 57, 128}, ++{146, 85, 98}, ++{154, 82, 102}, ++{165, 78, 107}, ++{178, 73, 112}, ++{191, 69, 117}, ++{204, 63, 122}, ++{218, 58, 127}, ++{219, 58, 128}, ++{148, 86, 99}, ++{157, 83, 103}, ++{168, 79, 107}, ++{180, 74, 113}, ++{193, 69, 118}, ++{206, 64, 123}, ++{219, 59, 128}, ++{221, 58, 128}, ++{151, 87, 100}, ++{159, 84, 104}, ++{170, 80, 108}, ++{182, 75, 113}, ++{195, 70, 118}, ++{208, 65, 123}, ++{221, 60, 128}, ++{222, 59, 128}, ++{154, 89, 101}, ++{162, 86, 104}, ++{172, 81, 109}, ++{184, 76, 114}, ++{197, 71, 119}, ++{209, 66, 124}, ++{222, 61, 128}, ++{224, 60, 129}, ++{157, 90, 102}, ++{165, 87, 105}, ++{175, 82, 110}, ++{186, 78, 114}, ++{199, 72, 119}, ++{211, 67, 124}, ++{224, 61, 129}, ++{226, 61, 129}, ++{160, 92, 103}, ++{168, 88, 106}, ++{178, 84, 110}, ++{189, 79, 115}, ++{201, 73, 120}, ++{213, 68, 124}, ++{226, 62, 129}, ++{228, 62, 129}, ++{163, 93, 104}, ++{171, 89, 107}, ++{180, 85, 111}, ++{191, 80, 116}, ++{203, 74, 120}, ++{215, 69, 125}, ++{228, 63, 129}, ++{230, 62, 130}, ++{166, 94, 105}, ++{173, 91, 108}, ++{183, 86, 112}, ++{194, 81, 116}, ++{205, 75, 121}, ++{218, 70, 125}, ++{230, 64, 130}, ++{232, 63, 130}, ++{169, 95, 106}, ++{176, 92, 109}, ++{186, 87, 113}, ++{196, 82, 117}, ++{208, 76, 121}, ++{220, 71, 126}, ++{232, 65, 130}, ++{234, 64, 131}, ++{173, 96, 107}, ++{180, 93, 110}, ++{189, 88, 114}, ++{199, 83, 118}, ++{210, 77, 122}, ++{222, 71, 126}, ++{234, 66, 130}, ++{236, 65, 131}, ++{176, 98, 108}, ++{183, 94, 111}, ++{192, 89, 114}, ++{202, 84, 118}, ++{213, 78, 122}, ++{224, 72, 127}, ++{236, 67, 131}, ++{238, 66, 131}, ++{179, 99, 109}, ++{186, 95, 112}, ++{194, 90, 115}, ++{204, 85, 119}, ++{215, 79, 123}, ++{227, 73, 127}, ++{239, 67, 131}, ++{240, 67, 132}, ++{183, 100, 110}, ++{189, 96, 113}, ++{197, 91, 116}, ++{207, 86, 120}, ++{218, 80, 124}, ++{229, 74, 128}, ++{241, 68, 132}, ++{242, 68, 132}, ++{186, 101, 111}, ++{192, 97, 113}, ++{200, 92, 117}, ++{210, 87, 120}, ++{221, 81, 124}, ++{232, 75, 128}, ++{243, 69, 132}, ++{245, 68, 132}, ++{189, 101, 112}, ++{195, 98, 114}, ++{204, 93, 117}, ++{213, 88, 121}, ++{223, 82, 125}, ++{234, 76, 129}, ++{245, 70, 132}, ++{247, 69, 133}, ++{191, 102, 112}, ++{197, 98, 115}, ++{205, 93, 118}, ++{214, 88, 121}, ++{225, 82, 125}, ++{235, 76, 129}, ++{247, 71, 133}, ++{248, 70, 133}, ++{191, 102, 112}, ++{197, 98, 115}, ++{205, 93, 118}, ++{214, 88, 121}, ++{225, 82, 125}, ++{235, 76, 129}, ++{247, 71, 133}, ++{248, 70, 133}, ++{191, 102, 112}, ++{197, 98, 115}, ++{205, 93, 118}, ++{214, 88, 121}, ++{225, 82, 125}, ++{235, 76, 129}, ++{247, 71, 133}, ++{248, 70, 133}, ++{191, 102, 112}, ++{197, 98, 115}, ++{205, 93, 118}, ++{214, 88, 121}, ++{225, 82, 125}, ++{235, 76, 129}, ++{247, 71, 133}, ++{248, 70, 133}, ++{127, 67, 87}, ++{138, 67, 92}, ++{151, 66, 99}, ++{165, 63, 105}, ++{179, 60, 112}, ++{194, 56, 117}, ++{208, 52, 123}, ++{210, 51, 124}, ++{127, 67, 87}, ++{138, 67, 92}, ++{151, 66, 99}, ++{165, 63, 105}, ++{179, 60, 112}, ++{194, 56, 117}, ++{208, 52, 123}, ++{210, 51, 124}, ++{128, 68, 87}, ++{138, 67, 93}, ++{151, 66, 99}, ++{165, 63, 105}, ++{180, 60, 112}, ++{194, 56, 118}, ++{209, 52, 123}, ++{210, 51, 124}, ++{129, 68, 88}, ++{139, 68, 93}, ++{152, 67, 99}, ++{166, 64, 106}, ++{180, 60, 112}, ++{195, 56, 118}, ++{209, 52, 123}, ++{211, 52, 124}, ++{130, 69, 88}, ++{140, 69, 93}, ++{153, 67, 100}, ++{167, 64, 106}, ++{181, 61, 112}, ++{195, 57, 118}, ++{210, 52, 123}, ++{211, 52, 124}, ++{131, 70, 89}, ++{141, 70, 94}, ++{154, 68, 100}, ++{168, 65, 106}, ++{182, 61, 112}, ++{196, 57, 118}, ++{210, 53, 123}, ++{212, 52, 124}, ++{133, 72, 89}, ++{143, 71, 94}, ++{155, 69, 100}, ++{169, 66, 107}, ++{183, 62, 112}, ++{197, 58, 118}, ++{211, 53, 124}, ++{213, 53, 124}, ++{134, 73, 90}, ++{144, 72, 95}, ++{156, 69, 101}, ++{170, 66, 107}, ++{184, 62, 113}, ++{198, 58, 118}, ++{212, 54, 124}, ++{214, 53, 124}, ++{136, 74, 91}, ++{146, 73, 96}, ++{158, 70, 101}, ++{171, 67, 107}, ++{185, 63, 113}, ++{199, 59, 119}, ++{213, 54, 124}, ++{215, 54, 125}, ++{138, 76, 92}, ++{148, 74, 96}, ++{160, 72, 102}, ++{173, 68, 108}, ++{186, 64, 113}, ++{200, 59, 119}, ++{214, 55, 124}, ++{216, 54, 125}, ++{141, 78, 93}, ++{150, 76, 97}, ++{161, 73, 103}, ++{174, 69, 108}, ++{188, 65, 114}, ++{201, 60, 119}, ++{215, 55, 124}, ++{217, 55, 125}, ++{143, 79, 94}, ++{152, 77, 98}, ++{163, 74, 103}, ++{176, 70, 109}, ++{189, 65, 114}, ++{203, 61, 120}, ++{216, 56, 125}, ++{218, 55, 125}, ++{145, 81, 95}, ++{154, 78, 99}, ++{165, 75, 104}, ++{178, 71, 109}, ++{191, 66, 115}, ++{204, 62, 120}, ++{218, 57, 125}, ++{219, 56, 126}, ++{148, 82, 96}, ++{156, 80, 100}, ++{167, 76, 105}, ++{180, 72, 110}, ++{193, 67, 115}, ++{206, 62, 120}, ++{219, 57, 125}, ++{221, 57, 126}, ++{151, 84, 97}, ++{159, 81, 101}, ++{170, 77, 105}, ++{182, 73, 111}, ++{194, 68, 116}, ++{207, 63, 121}, ++{221, 58, 126}, ++{222, 57, 126}, ++{153, 85, 98}, ++{161, 82, 101}, ++{172, 78, 106}, ++{184, 74, 111}, ++{196, 69, 116}, ++{209, 64, 121}, ++{222, 59, 126}, ++{224, 58, 127}, ++{156, 87, 99}, ++{164, 84, 102}, ++{174, 80, 107}, ++{186, 75, 112}, ++{198, 70, 117}, ++{211, 65, 122}, ++{224, 60, 126}, ++{226, 59, 127}, ++{159, 88, 100}, ++{167, 85, 103}, ++{177, 81, 108}, ++{188, 76, 112}, ++{200, 71, 117}, ++{213, 66, 122}, ++{226, 60, 127}, ++{227, 60, 127}, ++{162, 90, 101}, ++{170, 86, 104}, ++{179, 82, 108}, ++{191, 77, 113}, ++{203, 72, 118}, ++{215, 67, 122}, ++{228, 61, 127}, ++{229, 61, 128}, ++{165, 91, 102}, ++{173, 87, 105}, ++{182, 83, 109}, ++{193, 78, 114}, ++{205, 73, 118}, ++{217, 68, 123}, ++{229, 62, 127}, ++{231, 61, 128}, ++{168, 92, 103}, ++{175, 89, 106}, ++{185, 84, 110}, ++{196, 79, 114}, ++{207, 74, 119}, ++{219, 68, 123}, ++{231, 63, 128}, ++{233, 62, 128}, ++{171, 93, 104}, ++{178, 90, 107}, ++{188, 85, 111}, ++{198, 80, 115}, ++{209, 75, 119}, ++{221, 69, 124}, ++{233, 64, 128}, ++{235, 63, 129}, ++{175, 95, 105}, ++{181, 91, 108}, ++{190, 86, 112}, ++{201, 81, 116}, ++{212, 76, 120}, ++{224, 70, 124}, ++{236, 65, 129}, ++{237, 64, 129}, ++{178, 96, 106}, ++{185, 92, 109}, ++{193, 88, 112}, ++{203, 82, 116}, ++{214, 77, 121}, ++{226, 71, 125}, ++{238, 66, 129}, ++{239, 65, 130}, ++{181, 97, 107}, ++{188, 93, 110}, ++{196, 89, 113}, ++{206, 83, 117}, ++{217, 78, 121}, ++{228, 72, 125}, ++{240, 67, 129}, ++{241, 66, 130}, ++{185, 98, 108}, ++{191, 94, 111}, ++{199, 90, 114}, ++{209, 84, 118}, ++{219, 79, 122}, ++{231, 73, 126}, ++{242, 67, 130}, ++{244, 67, 130}, ++{188, 99, 109}, ++{194, 95, 111}, ++{202, 91, 115}, ++{212, 85, 118}, ++{222, 80, 122}, ++{233, 74, 126}, ++{244, 68, 130}, ++{246, 68, 131}, ++{191, 100, 110}, ++{197, 96, 112}, ++{205, 92, 116}, ++{215, 86, 119}, ++{225, 81, 123}, ++{236, 75, 127}, ++{247, 69, 131}, ++{248, 68, 131}, ++{193, 100, 110}, ++{199, 97, 113}, ++{207, 92, 116}, ++{216, 87, 119}, ++{226, 81, 123}, ++{237, 75, 127}, ++{248, 70, 131}, ++{249, 69, 131}, ++{193, 100, 110}, ++{199, 97, 113}, ++{207, 92, 116}, ++{216, 87, 119}, ++{226, 81, 123}, ++{237, 75, 127}, ++{248, 70, 131}, ++{249, 69, 131}, ++{193, 100, 110}, ++{199, 97, 113}, ++{207, 92, 116}, ++{216, 87, 119}, ++{226, 81, 123}, ++{237, 75, 127}, ++{248, 70, 131}, ++{249, 69, 131}, ++{193, 100, 110}, ++{199, 97, 113}, ++{207, 92, 116}, ++{216, 87, 119}, ++{226, 81, 123}, ++{237, 75, 127}, ++{248, 70, 131}, ++{249, 69, 131}, ++{130, 64, 85}, ++{140, 65, 90}, ++{153, 64, 97}, ++{167, 61, 103}, ++{181, 58, 109}, ++{196, 55, 115}, ++{210, 51, 121}, ++{212, 50, 122}, ++{130, 65, 85}, ++{141, 65, 90}, ++{153, 64, 97}, ++{167, 62, 103}, ++{181, 58, 109}, ++{196, 55, 115}, ++{210, 51, 121}, ++{212, 50, 122}, ++{131, 65, 85}, ++{141, 65, 91}, ++{154, 64, 97}, ++{168, 62, 103}, ++{182, 59, 110}, ++{196, 55, 115}, ++{210, 51, 121}, ++{212, 50, 122}, ++{131, 66, 86}, ++{142, 66, 91}, ++{154, 65, 97}, ++{168, 62, 104}, ++{182, 59, 110}, ++{196, 55, 116}, ++{211, 51, 121}, ++{212, 50, 122}, ++{133, 67, 86}, ++{143, 67, 91}, ++{155, 65, 97}, ++{169, 63, 104}, ++{183, 59, 110}, ++{197, 55, 116}, ++{211, 51, 121}, ++{213, 51, 122}, ++{134, 68, 87}, ++{144, 67, 92}, ++{156, 66, 98}, ++{170, 63, 104}, ++{184, 60, 110}, ++{198, 56, 116}, ++{212, 52, 121}, ++{214, 51, 122}, ++{135, 69, 87}, ++{145, 68, 92}, ++{157, 67, 98}, ++{171, 64, 104}, ++{185, 60, 110}, ++{199, 56, 116}, ++{213, 52, 122}, ++{214, 51, 122}, ++{137, 71, 88}, ++{147, 70, 93}, ++{159, 68, 99}, ++{172, 65, 105}, ++{186, 61, 111}, ++{199, 57, 116}, ++{213, 52, 122}, ++{215, 52, 122}, ++{139, 72, 89}, ++{148, 71, 94}, ++{160, 69, 99}, ++{173, 65, 105}, ++{187, 62, 111}, ++{201, 57, 117}, ++{214, 53, 122}, ++{216, 52, 123}, ++{141, 74, 90}, ++{150, 72, 94}, ++{162, 70, 100}, ++{175, 66, 106}, ++{188, 62, 111}, ++{202, 58, 117}, ++{215, 54, 122}, ++{217, 53, 123}, ++{143, 75, 91}, ++{152, 73, 95}, ++{163, 71, 101}, ++{176, 67, 106}, ++{189, 63, 112}, ++{203, 59, 117}, ++{217, 54, 122}, ++{218, 54, 123}, ++{145, 77, 92}, ++{154, 75, 96}, ++{165, 72, 101}, ++{178, 68, 107}, ++{191, 64, 112}, ++{204, 60, 118}, ++{218, 55, 123}, ++{220, 54, 123}, ++{148, 78, 93}, ++{156, 76, 97}, ++{167, 73, 102}, ++{180, 69, 107}, ++{193, 65, 113}, ++{206, 60, 118}, ++{219, 56, 123}, ++{221, 55, 124}, ++{150, 80, 94}, ++{159, 78, 98}, ++{169, 74, 103}, ++{182, 70, 108}, ++{194, 66, 113}, ++{207, 61, 118}, ++{221, 56, 123}, ++{222, 56, 124}, ++{153, 82, 95}, ++{161, 79, 99}, ++{172, 75, 103}, ++{184, 71, 108}, ++{196, 67, 114}, ++{209, 62, 119}, ++{222, 57, 124}, ++{224, 56, 124}, ++{156, 83, 96}, ++{164, 80, 99}, ++{174, 77, 104}, ++{186, 72, 109}, ++{198, 68, 114}, ++{211, 63, 119}, ++{224, 58, 124}, ++{225, 57, 125}, ++{158, 85, 97}, ++{166, 82, 100}, ++{176, 78, 105}, ++{188, 73, 110}, ++{200, 69, 115}, ++{213, 64, 120}, ++{225, 59, 124}, ++{227, 58, 125}, ++{161, 86, 98}, ++{169, 83, 101}, ++{179, 79, 106}, ++{190, 75, 110}, ++{202, 70, 115}, ++{215, 65, 120}, ++{227, 59, 125}, ++{229, 59, 125}, ++{164, 87, 99}, ++{172, 84, 102}, ++{181, 80, 106}, ++{192, 76, 111}, ++{204, 71, 116}, ++{217, 65, 121}, ++{229, 60, 125}, ++{231, 60, 126}, ++{167, 89, 100}, ++{175, 86, 103}, ++{184, 81, 107}, ++{195, 77, 112}, ++{206, 72, 116}, ++{219, 66, 121}, ++{231, 61, 126}, ++{233, 60, 126}, ++{170, 90, 101}, ++{177, 87, 104}, ++{187, 83, 108}, ++{197, 78, 112}, ++{209, 73, 117}, ++{221, 67, 121}, ++{233, 62, 126}, ++{234, 61, 127}, ++{174, 91, 102}, ++{180, 88, 105}, ++{189, 84, 109}, ++{200, 79, 113}, ++{211, 74, 118}, ++{223, 68, 122}, ++{235, 63, 126}, ++{236, 62, 127}, ++{177, 93, 103}, ++{183, 89, 106}, ++{192, 85, 110}, ++{202, 80, 114}, ++{213, 75, 118}, ++{225, 69, 122}, ++{237, 64, 127}, ++{239, 63, 127}, ++{180, 94, 104}, ++{186, 90, 107}, ++{195, 86, 110}, ++{205, 81, 114}, ++{216, 76, 119}, ++{227, 70, 123}, ++{239, 65, 127}, ++{241, 64, 128}, ++{183, 95, 105}, ++{189, 91, 108}, ++{198, 87, 111}, ++{208, 82, 115}, ++{218, 77, 119}, ++{230, 71, 123}, ++{241, 66, 128}, ++{243, 65, 128}, ++{186, 96, 106}, ++{193, 93, 109}, ++{201, 88, 112}, ++{211, 83, 116}, ++{221, 78, 120}, ++{232, 72, 124}, ++{244, 66, 128}, ++{245, 66, 129}, ++{190, 97, 107}, ++{196, 94, 110}, ++{204, 89, 113}, ++{213, 84, 117}, ++{224, 78, 121}, ++{235, 73, 125}, ++{246, 67, 129}, ++{247, 67, 129}, ++{193, 98, 108}, ++{199, 95, 110}, ++{207, 90, 114}, ++{216, 85, 117}, ++{226, 79, 121}, ++{237, 74, 125}, ++{248, 68, 129}, ++{250, 67, 129}, ++{195, 99, 109}, ++{201, 95, 111}, ++{208, 91, 114}, ++{218, 85, 118}, ++{228, 80, 121}, ++{238, 74, 125}, ++{249, 69, 129}, ++{251, 68, 130}, ++{195, 99, 109}, ++{201, 95, 111}, ++{208, 91, 114}, ++{218, 85, 118}, ++{228, 80, 121}, ++{238, 74, 125}, ++{249, 69, 129}, ++{251, 68, 130}, ++{195, 99, 109}, ++{201, 95, 111}, ++{208, 91, 114}, ++{218, 85, 118}, ++{228, 80, 121}, ++{238, 74, 125}, ++{249, 69, 129}, ++{251, 68, 130}, ++{195, 99, 109}, ++{201, 95, 111}, ++{208, 91, 114}, ++{218, 85, 118}, ++{228, 80, 121}, ++{238, 74, 125}, ++{249, 69, 129}, ++{251, 68, 130}, ++{133, 62, 83}, ++{143, 63, 88}, ++{156, 62, 95}, ++{169, 60, 101}, ++{183, 57, 107}, ++{197, 53, 113}, ++{212, 49, 119}, ++{213, 49, 120}, ++{133, 62, 83}, ++{143, 63, 88}, ++{156, 62, 95}, ++{169, 60, 101}, ++{183, 57, 107}, ++{198, 53, 113}, ++{212, 49, 119}, ++{213, 49, 120}, ++{133, 63, 83}, ++{144, 63, 89}, ++{156, 62, 95}, ++{170, 60, 101}, ++{184, 57, 107}, ++{198, 54, 113}, ++{212, 50, 119}, ++{214, 49, 120}, ++{134, 63, 84}, ++{144, 64, 89}, ++{157, 63, 95}, ++{170, 60, 101}, ++{184, 57, 108}, ++{198, 54, 114}, ++{212, 50, 119}, ++{214, 49, 120}, ++{135, 64, 84}, ++{145, 64, 89}, ++{157, 63, 95}, ++{171, 61, 102}, ++{185, 58, 108}, ++{199, 54, 114}, ++{213, 50, 119}, ++{215, 50, 120}, ++{136, 65, 85}, ++{146, 65, 90}, ++{158, 64, 96}, ++{172, 62, 102}, ++{186, 58, 108}, ++{200, 55, 114}, ++{213, 50, 119}, ++{215, 50, 120}, ++{138, 67, 85}, ++{148, 66, 90}, ++{160, 65, 96}, ++{173, 62, 102}, ++{186, 59, 108}, ++{200, 55, 114}, ++{214, 51, 120}, ++{216, 50, 120}, ++{140, 68, 86}, ++{149, 67, 91}, ++{161, 66, 97}, ++{174, 63, 103}, ++{187, 60, 109}, ++{201, 56, 114}, ++{215, 51, 120}, ++{217, 51, 120}, ++{141, 70, 87}, ++{151, 69, 92}, ++{162, 67, 97}, ++{175, 64, 103}, ++{189, 60, 109}, ++{202, 56, 115}, ++{216, 52, 120}, ++{218, 51, 121}, ++{143, 71, 88}, ++{152, 70, 92}, ++{164, 68, 98}, ++{177, 65, 104}, ++{190, 61, 109}, ++{203, 57, 115}, ++{217, 52, 120}, ++{219, 52, 121}, ++{146, 73, 89}, ++{154, 71, 93}, ++{166, 69, 98}, ++{178, 66, 104}, ++{191, 62, 110}, ++{205, 58, 115}, ++{218, 53, 121}, ++{220, 53, 121}, ++{148, 74, 90}, ++{156, 73, 94}, ++{168, 70, 99}, ++{180, 67, 105}, ++{193, 63, 110}, ++{206, 58, 116}, ++{220, 54, 121}, ++{221, 53, 121}, ++{150, 76, 91}, ++{159, 74, 95}, ++{169, 71, 100}, ++{182, 68, 105}, ++{194, 63, 111}, ++{208, 59, 116}, ++{221, 54, 121}, ++{223, 54, 122}, ++{153, 78, 92}, ++{161, 75, 96}, ++{172, 72, 101}, ++{184, 69, 106}, ++{196, 64, 111}, ++{209, 60, 116}, ++{222, 55, 121}, ++{224, 55, 122}, ++{155, 79, 93}, ++{163, 77, 97}, ++{174, 74, 101}, ++{185, 70, 106}, ++{198, 65, 112}, ++{211, 61, 117}, ++{224, 56, 122}, ++{225, 55, 122}, ++{158, 81, 94}, ++{166, 78, 97}, ++{176, 75, 102}, ++{188, 71, 107}, ++{200, 66, 112}, ++{213, 62, 117}, ++{225, 57, 122}, ++{227, 56, 123}, ++{161, 82, 95}, ++{168, 80, 98}, ++{178, 76, 103}, ++{190, 72, 108}, ++{202, 67, 113}, ++{214, 62, 118}, ++{227, 58, 123}, ++{229, 57, 123}, ++{164, 84, 96}, ++{171, 81, 99}, ++{181, 77, 104}, ++{192, 73, 108}, ++{204, 68, 113}, ++{216, 63, 118}, ++{229, 58, 123}, ++{230, 58, 123}, ++{166, 85, 97}, ++{174, 82, 100}, ++{183, 79, 104}, ++{194, 74, 109}, ++{206, 69, 114}, ++{218, 64, 119}, ++{231, 59, 123}, ++{232, 59, 124}, ++{169, 87, 98}, ++{177, 84, 101}, ++{186, 80, 105}, ++{197, 75, 110}, ++{208, 70, 114}, ++{220, 65, 119}, ++{232, 60, 124}, ++{234, 59, 124}, ++{172, 88, 99}, ++{179, 85, 102}, ++{189, 81, 106}, ++{199, 76, 110}, ++{210, 71, 115}, ++{222, 66, 120}, ++{234, 61, 124}, ++{236, 60, 125}, ++{176, 89, 100}, ++{182, 86, 103}, ++{191, 82, 107}, ++{202, 77, 111}, ++{213, 72, 116}, ++{224, 67, 120}, ++{236, 62, 125}, ++{238, 61, 125}, ++{179, 91, 101}, ++{185, 87, 104}, ++{194, 83, 108}, ++{204, 78, 112}, ++{215, 73, 116}, ++{227, 68, 121}, ++{238, 63, 125}, ++{240, 62, 126}, ++{182, 92, 102}, ++{188, 89, 105}, ++{197, 84, 109}, ++{207, 79, 113}, ++{218, 74, 117}, ++{229, 69, 121}, ++{241, 64, 125}, ++{242, 63, 126}, ++{185, 93, 103}, ++{191, 90, 106}, ++{200, 85, 109}, ++{209, 81, 113}, ++{220, 75, 117}, ++{231, 70, 122}, ++{243, 65, 126}, ++{244, 64, 126}, ++{188, 94, 104}, ++{194, 91, 107}, ++{203, 86, 110}, ++{212, 82, 114}, ++{223, 76, 118}, ++{234, 71, 122}, ++{245, 65, 126}, ++{246, 65, 127}, ++{192, 95, 105}, ++{198, 92, 108}, ++{206, 88, 111}, ++{215, 83, 115}, ++{225, 77, 119}, ++{236, 72, 123}, ++{247, 66, 127}, ++{249, 66, 127}, ++{195, 96, 106}, ++{201, 93, 109}, ++{209, 89, 112}, ++{218, 84, 115}, ++{228, 78, 119}, ++{238, 73, 123}, ++{250, 67, 127}, ++{251, 66, 128}, ++{196, 97, 107}, ++{202, 93, 109}, ++{210, 89, 112}, ++{219, 84, 116}, ++{229, 79, 120}, ++{240, 73, 124}, ++{251, 68, 127}, ++{252, 67, 128}, ++{196, 97, 107}, ++{202, 93, 109}, ++{210, 89, 112}, ++{219, 84, 116}, ++{229, 79, 120}, ++{240, 73, 124}, ++{251, 68, 127}, ++{252, 67, 128}, ++{196, 97, 107}, ++{202, 93, 109}, ++{210, 89, 112}, ++{219, 84, 116}, ++{229, 79, 120}, ++{240, 73, 124}, ++{251, 68, 127}, ++{252, 67, 128}, ++{196, 97, 107}, ++{202, 93, 109}, ++{210, 89, 112}, ++{219, 84, 116}, ++{229, 79, 120}, ++{240, 73, 124}, ++{251, 68, 127}, ++{252, 67, 128}, ++{136, 60, 81}, ++{145, 60, 86}, ++{158, 60, 93}, ++{171, 58, 99}, ++{185, 55, 105}, ++{199, 52, 111}, ++{213, 48, 117}, ++{215, 48, 118}, ++{136, 60, 81}, ++{146, 60, 86}, ++{158, 60, 93}, ++{171, 58, 99}, ++{185, 55, 105}, ++{199, 52, 111}, ++{213, 48, 117}, ++{215, 48, 118}, ++{136, 60, 81}, ++{146, 61, 87}, ++{158, 60, 93}, ++{172, 58, 99}, ++{186, 56, 105}, ++{200, 52, 111}, ++{214, 48, 117}, ++{215, 48, 118}, ++{137, 61, 82}, ++{147, 61, 87}, ++{159, 61, 93}, ++{172, 59, 99}, ++{186, 56, 106}, ++{200, 53, 111}, ++{214, 49, 117}, ++{216, 48, 118}, ++{138, 62, 82}, ++{148, 62, 87}, ++{160, 61, 93}, ++{173, 59, 100}, ++{187, 56, 106}, ++{201, 53, 112}, ++{215, 49, 117}, ++{216, 48, 118}, ++{139, 63, 83}, ++{149, 63, 88}, ++{161, 62, 94}, ++{174, 60, 100}, ++{187, 57, 106}, ++{201, 53, 112}, ++{215, 49, 117}, ++{217, 49, 118}, ++{141, 64, 83}, ++{150, 64, 88}, ++{162, 63, 94}, ++{175, 60, 100}, ++{188, 57, 106}, ++{202, 54, 112}, ++{216, 50, 118}, ++{218, 49, 118}, ++{142, 66, 84}, ++{151, 65, 89}, ++{163, 64, 95}, ++{176, 61, 101}, ++{189, 58, 107}, ++{203, 54, 112}, ++{217, 50, 118}, ++{218, 50, 118}, ++{144, 67, 85}, ++{153, 66, 90}, ++{165, 65, 95}, ++{177, 62, 101}, ++{191, 59, 107}, ++{204, 55, 113}, ++{218, 51, 118}, ++{219, 50, 119}, ++{146, 69, 86}, ++{155, 68, 90}, ++{166, 66, 96}, ++{179, 63, 102}, ++{192, 59, 107}, ++{205, 56, 113}, ++{219, 51, 118}, ++{220, 51, 119}, ++{148, 70, 87}, ++{157, 69, 91}, ++{168, 67, 96}, ++{180, 64, 102}, ++{193, 60, 108}, ++{206, 56, 113}, ++{220, 52, 119}, ++{222, 51, 119}, ++{150, 72, 88}, ++{159, 71, 92}, ++{170, 68, 97}, ++{182, 65, 103}, ++{195, 61, 108}, ++{208, 57, 114}, ++{221, 53, 119}, ++{223, 52, 119}, ++{153, 74, 89}, ++{161, 72, 93}, ++{172, 69, 98}, ++{184, 66, 103}, ++{196, 62, 109}, ++{209, 58, 114}, ++{222, 53, 119}, ++{224, 53, 120}, ++{155, 75, 90}, ++{163, 73, 94}, ++{174, 71, 99}, ++{185, 67, 104}, ++{198, 63, 109}, ++{211, 59, 114}, ++{224, 54, 120}, ++{226, 53, 120}, ++{158, 77, 91}, ++{166, 75, 95}, ++{176, 72, 99}, ++{187, 68, 104}, ++{200, 64, 110}, ++{212, 59, 115}, ++{225, 55, 120}, ++{227, 54, 120}, ++{160, 79, 92}, ++{168, 76, 95}, ++{178, 73, 100}, ++{189, 69, 105}, ++{202, 65, 110}, ++{214, 60, 115}, ++{227, 56, 120}, ++{229, 55, 121}, ++{163, 80, 93}, ++{171, 78, 96}, ++{180, 74, 101}, ++{192, 70, 106}, ++{204, 66, 111}, ++{216, 61, 116}, ++{229, 56, 121}, ++{230, 56, 121}, ++{166, 82, 94}, ++{173, 79, 97}, ++{183, 76, 102}, ++{194, 71, 106}, ++{206, 67, 111}, ++{218, 62, 116}, ++{230, 57, 121}, ++{232, 57, 122}, ++{169, 83, 95}, ++{176, 80, 98}, ++{185, 77, 102}, ++{196, 73, 107}, ++{208, 68, 112}, ++{220, 63, 117}, ++{232, 58, 121}, ++{234, 57, 122}, ++{172, 85, 96}, ++{179, 82, 99}, ++{188, 78, 103}, ++{198, 74, 108}, ++{210, 69, 113}, ++{222, 64, 117}, ++{234, 59, 122}, ++{236, 58, 122}, ++{175, 86, 97}, ++{181, 83, 100}, ++{190, 79, 104}, ++{201, 75, 109}, ++{212, 70, 113}, ++{224, 65, 118}, ++{236, 60, 122}, ++{237, 59, 123}, ++{178, 87, 98}, ++{184, 84, 101}, ++{193, 80, 105}, ++{203, 76, 109}, ++{214, 71, 114}, ++{226, 66, 118}, ++{238, 61, 123}, ++{239, 60, 123}, ++{181, 89, 99}, ++{187, 86, 102}, ++{196, 82, 106}, ++{206, 77, 110}, ++{217, 72, 114}, ++{228, 67, 119}, ++{240, 62, 123}, ++{241, 61, 124}, ++{184, 90, 100}, ++{190, 87, 103}, ++{199, 83, 107}, ++{208, 78, 111}, ++{219, 73, 115}, ++{230, 68, 119}, ++{242, 63, 124}, ++{244, 62, 124}, ++{187, 91, 101}, ++{193, 88, 104}, ++{201, 84, 107}, ++{211, 79, 111}, ++{222, 74, 116}, ++{233, 69, 120}, ++{244, 63, 124}, ++{246, 63, 125}, ++{190, 92, 102}, ++{196, 89, 105}, ++{204, 85, 108}, ++{214, 80, 112}, ++{224, 75, 116}, ++{235, 70, 120}, ++{246, 64, 125}, ++{248, 64, 125}, ++{193, 93, 103}, ++{199, 90, 106}, ++{207, 86, 109}, ++{217, 81, 113}, ++{227, 76, 117}, ++{238, 71, 121}, ++{249, 65, 125}, ++{250, 65, 126}, ++{197, 95, 104}, ++{202, 91, 107}, ++{210, 87, 110}, ++{219, 82, 114}, ++{229, 77, 118}, ++{240, 72, 121}, ++{251, 66, 125}, ++{252, 65, 126}, ++{198, 95, 105}, ++{204, 92, 107}, ++{212, 88, 110}, ++{221, 83, 114}, ++{231, 77, 118}, ++{241, 72, 122}, ++{252, 67, 126}, ++{254, 66, 126}, ++{198, 95, 105}, ++{204, 92, 107}, ++{212, 88, 110}, ++{221, 83, 114}, ++{231, 77, 118}, ++{241, 72, 122}, ++{252, 67, 126}, ++{254, 66, 126}, ++{198, 95, 105}, ++{204, 92, 107}, ++{212, 88, 110}, ++{221, 83, 114}, ++{231, 77, 118}, ++{241, 72, 122}, ++{252, 67, 126}, ++{254, 66, 126}, ++{198, 95, 105}, ++{204, 92, 107}, ++{212, 88, 110}, ++{221, 83, 114}, ++{231, 77, 118}, ++{241, 72, 122}, ++{252, 67, 126}, ++{254, 66, 126}, ++{138, 57, 79}, ++{148, 58, 84}, ++{160, 58, 91}, ++{173, 56, 97}, ++{187, 54, 103}, ++{201, 51, 109}, ++{215, 47, 115}, ++{217, 47, 116}, ++{138, 57, 79}, ++{148, 58, 84}, ++{160, 58, 91}, ++{174, 56, 97}, ++{187, 54, 103}, ++{201, 51, 109}, ++{215, 47, 115}, ++{217, 47, 116}, ++{139, 58, 79}, ++{149, 59, 85}, ++{161, 58, 91}, ++{174, 57, 97}, ++{188, 54, 103}, ++{201, 51, 109}, ++{215, 47, 115}, ++{217, 47, 116}, ++{140, 59, 80}, ++{149, 59, 85}, ++{161, 59, 91}, ++{174, 57, 97}, ++{188, 54, 104}, ++{202, 51, 109}, ++{216, 47, 115}, ++{217, 47, 116}, ++{141, 60, 80}, ++{150, 60, 85}, ++{162, 59, 91}, ++{175, 58, 98}, ++{189, 55, 104}, ++{202, 52, 110}, ++{216, 48, 115}, ++{218, 47, 116}, ++{142, 61, 81}, ++{151, 61, 86}, ++{163, 60, 92}, ++{176, 58, 98}, ++{189, 55, 104}, ++{203, 52, 110}, ++{217, 48, 115}, ++{219, 48, 116}, ++{143, 62, 81}, ++{152, 62, 86}, ++{164, 61, 92}, ++{177, 59, 98}, ++{190, 56, 104}, ++{204, 52, 110}, ++{218, 49, 116}, ++{219, 48, 116}, ++{145, 63, 82}, ++{154, 63, 87}, ++{165, 62, 93}, ++{178, 60, 99}, ++{191, 57, 105}, ++{205, 53, 110}, ++{218, 49, 116}, ++{220, 49, 116}, ++{147, 65, 83}, ++{155, 64, 88}, ++{167, 63, 93}, ++{179, 60, 99}, ++{192, 57, 105}, ++{206, 54, 111}, ++{219, 50, 116}, ++{221, 49, 117}, ++{148, 66, 84}, ++{157, 66, 88}, ++{168, 64, 94}, ++{181, 61, 100}, ++{194, 58, 105}, ++{207, 54, 111}, ++{220, 50, 116}, ++{222, 50, 117}, ++{151, 68, 85}, ++{159, 67, 89}, ++{170, 65, 94}, ++{182, 62, 100}, ++{195, 59, 106}, ++{208, 55, 111}, ++{222, 51, 117}, ++{223, 50, 117}, ++{153, 70, 86}, ++{161, 68, 90}, ++{172, 66, 95}, ++{184, 63, 101}, ++{197, 60, 106}, ++{210, 56, 112}, ++{223, 51, 117}, ++{224, 51, 118}, ++{155, 71, 87}, ++{163, 70, 91}, ++{174, 67, 96}, ++{186, 64, 101}, ++{198, 61, 107}, ++{211, 56, 112}, ++{224, 52, 117}, ++{226, 52, 118}, ++{157, 73, 88}, ++{165, 71, 92}, ++{176, 69, 97}, ++{187, 65, 102}, ++{200, 61, 107}, ++{213, 57, 112}, ++{225, 53, 118}, ++{227, 52, 118}, ++{160, 75, 89}, ++{168, 73, 93}, ++{178, 70, 97}, ++{189, 66, 102}, ++{202, 62, 108}, ++{214, 58, 113}, ++{227, 54, 118}, ++{229, 53, 119}, ++{163, 76, 90}, ++{170, 74, 93}, ++{180, 71, 98}, ++{191, 68, 103}, ++{203, 63, 108}, ++{216, 59, 113}, ++{229, 54, 118}, ++{230, 54, 119}, ++{165, 78, 91}, ++{173, 76, 94}, ++{182, 72, 99}, ++{193, 69, 104}, ++{205, 64, 109}, ++{218, 60, 114}, ++{230, 55, 119}, ++{232, 55, 119}, ++{168, 80, 92}, ++{175, 77, 95}, ++{185, 74, 100}, ++{196, 70, 105}, ++{207, 65, 109}, ++{219, 61, 114}, ++{232, 56, 119}, ++{233, 56, 120}, ++{171, 81, 93}, ++{178, 78, 96}, ++{187, 75, 101}, ++{198, 71, 105}, ++{209, 67, 110}, ++{221, 62, 115}, ++{234, 57, 120}, ++{235, 56, 120}, ++{174, 83, 94}, ++{181, 80, 97}, ++{190, 76, 101}, ++{200, 72, 106}, ++{212, 68, 111}, ++{223, 63, 115}, ++{236, 58, 120}, ++{237, 57, 121}, ++{177, 84, 95}, ++{183, 81, 98}, ++{192, 77, 102}, ++{203, 73, 107}, ++{214, 69, 111}, ++{225, 64, 116}, ++{237, 59, 120}, ++{239, 58, 121}, ++{180, 85, 96}, ++{186, 83, 99}, ++{195, 79, 103}, ++{205, 74, 107}, ++{216, 70, 112}, ++{228, 65, 116}, ++{239, 60, 121}, ++{241, 59, 121}, ++{183, 87, 97}, ++{189, 84, 100}, ++{198, 80, 104}, ++{208, 75, 108}, ++{218, 71, 112}, ++{230, 66, 117}, ++{241, 61, 121}, ++{243, 60, 122}, ++{186, 88, 98}, ++{192, 85, 101}, ++{200, 81, 105}, ++{210, 77, 109}, ++{221, 72, 113}, ++{232, 67, 117}, ++{244, 61, 122}, ++{245, 61, 122}, ++{189, 89, 99}, ++{195, 86, 102}, ++{203, 82, 106}, ++{213, 78, 110}, ++{223, 73, 114}, ++{234, 68, 118}, ++{246, 62, 122}, ++{247, 62, 123}, ++{192, 90, 100}, ++{198, 87, 103}, ++{206, 83, 106}, ++{216, 79, 110}, ++{226, 74, 114}, ++{237, 69, 119}, ++{248, 63, 123}, ++{249, 63, 123}, ++{195, 92, 101}, ++{201, 89, 104}, ++{209, 84, 107}, ++{218, 80, 111}, ++{228, 75, 115}, ++{239, 70, 119}, ++{250, 64, 123}, ++{252, 64, 124}, ++{198, 93, 102}, ++{204, 90, 105}, ++{212, 85, 108}, ++{221, 81, 112}, ++{231, 76, 116}, ++{241, 70, 120}, ++{252, 65, 124}, ++{254, 64, 124}, ++{200, 93, 103}, ++{206, 90, 105}, ++{213, 86, 109}, ++{222, 81, 112}, ++{232, 76, 116}, ++{243, 71, 120}, ++{254, 66, 124}, ++{255, 65, 124}, ++{200, 93, 103}, ++{206, 90, 105}, ++{213, 86, 109}, ++{222, 81, 112}, ++{232, 76, 116}, ++{243, 71, 120}, ++{254, 66, 124}, ++{255, 65, 124}, ++{200, 93, 103}, ++{206, 90, 105}, ++{213, 86, 109}, ++{222, 81, 112}, ++{232, 76, 116}, ++{243, 71, 120}, ++{254, 66, 124}, ++{255, 65, 124}, ++{200, 93, 103}, ++{206, 90, 105}, ++{213, 86, 109}, ++{222, 81, 112}, ++{232, 76, 116}, ++{243, 71, 120}, ++{254, 66, 124}, ++{255, 65, 124}, ++{141, 55, 77}, ++{151, 56, 82}, ++{162, 56, 89}, ++{176, 55, 95}, ++{189, 52, 101}, ++{203, 49, 107}, ++{217, 46, 113}, ++{218, 45, 114}, ++{141, 55, 77}, ++{151, 56, 83}, ++{163, 56, 89}, ++{176, 55, 95}, ++{189, 52, 101}, ++{203, 49, 107}, ++{217, 46, 113}, ++{219, 45, 114}, ++{142, 56, 78}, ++{151, 56, 83}, ++{163, 56, 89}, ++{176, 55, 95}, ++{190, 53, 101}, ++{203, 50, 107}, ++{217, 46, 113}, ++{219, 46, 114}, ++{142, 56, 78}, ++{152, 57, 83}, ++{164, 57, 89}, ++{177, 55, 95}, ++{190, 53, 102}, ++{204, 50, 108}, ++{217, 46, 113}, ++{219, 46, 114}, ++{143, 57, 78}, ++{153, 58, 83}, ++{164, 57, 89}, ++{177, 56, 96}, ++{191, 53, 102}, ++{204, 50, 108}, ++{218, 47, 113}, ++{220, 46, 114}, ++{144, 58, 79}, ++{154, 59, 84}, ++{165, 58, 90}, ++{178, 56, 96}, ++{191, 54, 102}, ++{205, 51, 108}, ++{219, 47, 113}, ++{220, 46, 114}, ++{146, 60, 80}, ++{155, 60, 84}, ++{166, 59, 90}, ++{179, 57, 96}, ++{192, 54, 102}, ++{206, 51, 108}, ++{219, 47, 114}, ++{221, 47, 114}, ++{147, 61, 80}, ++{156, 61, 85}, ++{168, 60, 91}, ++{180, 58, 97}, ++{193, 55, 103}, ++{207, 52, 108}, ++{220, 48, 114}, ++{222, 47, 115}, ++{149, 63, 81}, ++{158, 62, 86}, ++{169, 61, 91}, ++{181, 59, 97}, ++{194, 56, 103}, ++{208, 52, 109}, ++{221, 48, 114}, ++{223, 48, 115}, ++{151, 64, 82}, ++{160, 63, 86}, ++{171, 62, 92}, ++{183, 60, 98}, ++{196, 56, 103}, ++{209, 53, 109}, ++{222, 49, 114}, ++{224, 48, 115}, ++{153, 66, 83}, ++{161, 65, 87}, ++{172, 63, 92}, ++{184, 61, 98}, ++{197, 57, 104}, ++{210, 54, 109}, ++{223, 50, 115}, ++{225, 49, 115}, ++{155, 67, 84}, ++{163, 66, 88}, ++{174, 64, 93}, ++{186, 62, 99}, ++{198, 58, 104}, ++{211, 54, 110}, ++{224, 50, 115}, ++{226, 50, 116}, ++{157, 69, 85}, ++{165, 68, 89}, ++{176, 66, 94}, ++{188, 63, 99}, ++{200, 59, 105}, ++{213, 55, 110}, ++{226, 51, 115}, ++{227, 50, 116}, ++{160, 71, 86}, ++{168, 69, 90}, ++{178, 67, 95}, ++{189, 64, 100}, ++{202, 60, 105}, ++{214, 56, 111}, ++{227, 52, 116}, ++{229, 51, 116}, ++{162, 72, 87}, ++{170, 71, 91}, ++{180, 68, 95}, ++{191, 65, 101}, ++{203, 61, 106}, ++{216, 57, 111}, ++{229, 53, 116}, ++{230, 52, 117}, ++{165, 74, 88}, ++{172, 72, 92}, ++{182, 69, 96}, ++{193, 66, 101}, ++{205, 62, 106}, ++{218, 58, 111}, ++{230, 53, 116}, ++{232, 53, 117}, ++{167, 76, 89}, ++{175, 74, 92}, ++{184, 71, 97}, ++{195, 67, 102}, ++{207, 63, 107}, ++{219, 59, 112}, ++{232, 54, 117}, ++{233, 54, 117}, ++{170, 77, 90}, ++{177, 75, 93}, ++{187, 72, 98}, ++{198, 68, 103}, ++{209, 64, 108}, ++{221, 60, 112}, ++{233, 55, 117}, ++{235, 54, 118}, ++{173, 79, 91}, ++{180, 77, 94}, ++{189, 73, 99}, ++{200, 69, 103}, ++{211, 65, 108}, ++{223, 61, 113}, ++{235, 56, 118}, ++{237, 55, 118}, ++{176, 80, 92}, ++{183, 78, 95}, ++{192, 75, 99}, ++{202, 71, 104}, ++{213, 66, 109}, ++{225, 62, 113}, ++{237, 57, 118}, ++{239, 56, 119}, ++{179, 82, 93}, ++{185, 79, 96}, ++{194, 76, 100}, ++{204, 72, 105}, ++{216, 67, 109}, ++{227, 62, 114}, ++{239, 58, 119}, ++{240, 57, 119}, ++{182, 83, 94}, ++{188, 81, 97}, ++{197, 77, 101}, ++{207, 73, 105}, ++{218, 68, 110}, ++{229, 63, 115}, ++{241, 59, 119}, ++{242, 58, 120}, ++{185, 85, 95}, ++{191, 82, 98}, ++{200, 78, 102}, ++{209, 74, 106}, ++{220, 69, 111}, ++{231, 64, 115}, ++{243, 59, 120}, ++{244, 59, 120}, ++{188, 86, 96}, ++{194, 83, 99}, ++{202, 79, 103}, ++{212, 75, 107}, ++{222, 70, 111}, ++{234, 65, 116}, ++{245, 60, 120}, ++{246, 60, 121}, ++{191, 87, 98}, ++{197, 84, 100}, ++{205, 81, 104}, ++{215, 76, 108}, ++{225, 71, 112}, ++{236, 66, 116}, ++{247, 61, 121}, ++{249, 61, 121}, ++{194, 89, 99}, ++{200, 86, 101}, ++{208, 82, 105}, ++{217, 77, 108}, ++{227, 72, 113}, ++{238, 67, 117}, ++{249, 62, 121}, ++{251, 62, 122}, ++{197, 90, 100}, ++{203, 87, 102}, ++{211, 83, 105}, ++{220, 78, 109}, ++{230, 73, 113}, ++{241, 68, 117}, ++{252, 63, 122}, ++{253, 62, 122}, ++{200, 91, 101}, ++{206, 88, 103}, ++{214, 84, 106}, ++{223, 79, 110}, ++{232, 74, 114}, ++{243, 69, 118}, ++{254, 64, 122}, ++{255, 63, 123}, ++{202, 92, 101}, ++{208, 88, 104}, ++{215, 84, 107}, ++{224, 80, 110}, ++{234, 75, 114}, ++{244, 70, 118}, ++{255, 65, 122}, ++{255, 64, 123}, ++{202, 92, 101}, ++{208, 88, 104}, ++{215, 84, 107}, ++{224, 80, 110}, ++{234, 75, 114}, ++{244, 70, 118}, ++{255, 65, 122}, ++{255, 64, 123}, ++{202, 92, 101}, ++{208, 88, 104}, ++{215, 84, 107}, ++{224, 80, 110}, ++{234, 75, 114}, ++{244, 70, 118}, ++{255, 65, 122}, ++{255, 64, 123}, ++{202, 92, 101}, ++{208, 88, 104}, ++{215, 84, 107}, ++{224, 80, 110}, ++{234, 75, 114}, ++{244, 70, 118}, ++{255, 65, 122}, ++{255, 64, 123}, ++{144, 53, 75}, ++{153, 54, 81}, ++{165, 54, 87}, ++{178, 53, 93}, ++{191, 51, 99}, ++{205, 48, 105}, ++{218, 45, 111}, ++{220, 44, 112}, ++{144, 53, 76}, ++{153, 54, 81}, ++{165, 54, 87}, ++{178, 53, 93}, ++{191, 51, 99}, ++{205, 48, 105}, ++{219, 45, 111}, ++{220, 44, 112}, ++{144, 53, 76}, ++{154, 54, 81}, ++{165, 54, 87}, ++{178, 53, 93}, ++{192, 51, 99}, ++{205, 48, 105}, ++{219, 45, 111}, ++{220, 44, 112}, ++{145, 54, 76}, ++{154, 55, 81}, ++{166, 55, 87}, ++{179, 54, 93}, ++{192, 51, 100}, ++{206, 48, 106}, ++{219, 45, 111}, ++{221, 45, 112}, ++{146, 55, 77}, ++{155, 56, 81}, ++{167, 55, 87}, ++{179, 54, 94}, ++{193, 52, 100}, ++{206, 49, 106}, ++{220, 45, 111}, ++{221, 45, 112}, ++{147, 56, 77}, ++{156, 57, 82}, ++{168, 56, 88}, ++{180, 55, 94}, ++{193, 52, 100}, ++{207, 49, 106}, ++{220, 46, 112}, ++{222, 45, 112}, ++{148, 57, 78}, ++{157, 58, 82}, ++{169, 57, 88}, ++{181, 55, 94}, ++{194, 53, 100}, ++{208, 50, 106}, ++{221, 46, 112}, ++{223, 46, 112}, ++{150, 59, 78}, ++{159, 59, 83}, ++{170, 58, 89}, ++{182, 56, 95}, ++{195, 53, 101}, ++{208, 50, 106}, ++{222, 47, 112}, ++{223, 46, 113}, ++{152, 60, 79}, ++{160, 60, 84}, ++{171, 59, 89}, ++{183, 57, 95}, ++{196, 54, 101}, ++{209, 51, 107}, ++{223, 47, 112}, ++{224, 47, 113}, ++{153, 62, 80}, ++{162, 61, 84}, ++{173, 60, 90}, ++{185, 58, 96}, ++{198, 55, 101}, ++{211, 52, 107}, ++{224, 48, 113}, ++{225, 47, 113}, ++{155, 63, 81}, ++{164, 63, 85}, ++{174, 61, 91}, ++{186, 59, 96}, ++{199, 56, 102}, ++{212, 52, 107}, ++{225, 48, 113}, ++{227, 48, 113}, ++{158, 65, 82}, ++{166, 64, 86}, ++{176, 62, 91}, ++{188, 60, 97}, ++{200, 57, 102}, ++{213, 53, 108}, ++{226, 49, 113}, ++{228, 49, 114}, ++{160, 67, 83}, ++{168, 66, 87}, ++{178, 64, 92}, ++{190, 61, 97}, ++{202, 58, 103}, ++{215, 54, 108}, ++{227, 50, 113}, ++{229, 49, 114}, ++{162, 69, 84}, ++{170, 67, 88}, ++{180, 65, 93}, ++{191, 62, 98}, ++{203, 59, 103}, ++{216, 55, 109}, ++{229, 51, 114}, ++{230, 50, 114}, ++{165, 70, 85}, ++{172, 69, 89}, ++{182, 66, 93}, ++{193, 63, 99}, ++{205, 59, 104}, ++{218, 56, 109}, ++{230, 51, 114}, ++{232, 51, 115}, ++{167, 72, 86}, ++{174, 70, 90}, ++{184, 68, 94}, ++{195, 64, 99}, ++{207, 61, 104}, ++{219, 56, 110}, ++{232, 52, 115}, ++{233, 52, 115}, ++{170, 74, 87}, ++{177, 72, 91}, ++{186, 69, 95}, ++{197, 65, 100}, ++{209, 62, 105}, ++{221, 57, 110}, ++{233, 53, 115}, ++{235, 52, 116}, ++{172, 75, 88}, ++{179, 73, 92}, ++{189, 70, 96}, ++{199, 67, 101}, ++{211, 63, 106}, ++{223, 58, 111}, ++{235, 54, 115}, ++{237, 53, 116}, ++{175, 77, 89}, ++{182, 75, 93}, ++{191, 71, 97}, ++{202, 68, 101}, ++{213, 64, 106}, ++{225, 59, 111}, ++{237, 55, 116}, ++{238, 54, 116}, ++{178, 78, 90}, ++{185, 76, 93}, ++{194, 73, 98}, ++{204, 69, 102}, ++{215, 65, 107}, ++{227, 60, 112}, ++{239, 56, 116}, ++{240, 55, 117}, ++{181, 80, 91}, ++{187, 77, 94}, ++{196, 74, 98}, ++{206, 70, 103}, ++{217, 66, 107}, ++{229, 61, 112}, ++{241, 56, 117}, ++{242, 56, 117}, ++{184, 81, 92}, ++{190, 79, 95}, ++{199, 75, 99}, ++{209, 71, 104}, ++{219, 67, 108}, ++{231, 62, 113}, ++{242, 57, 117}, ++{244, 57, 118}, ++{187, 83, 94}, ++{193, 80, 96}, ++{201, 77, 100}, ++{211, 72, 104}, ++{222, 68, 109}, ++{233, 63, 113}, ++{244, 58, 118}, ++{246, 58, 118}, ++{190, 84, 95}, ++{196, 81, 97}, ++{204, 78, 101}, ++{214, 74, 105}, ++{224, 69, 109}, ++{235, 64, 114}, ++{247, 59, 118}, ++{248, 59, 119}, ++{193, 85, 96}, ++{199, 83, 98}, ++{207, 79, 102}, ++{216, 75, 106}, ++{227, 70, 110}, ++{237, 65, 114}, ++{249, 60, 119}, ++{250, 60, 119}, ++{196, 87, 97}, ++{202, 84, 99}, ++{210, 80, 103}, ++{219, 76, 107}, ++{229, 71, 111}, ++{240, 66, 115}, ++{251, 61, 119}, ++{252, 60, 120}, ++{199, 88, 98}, ++{205, 85, 100}, ++{213, 81, 104}, ++{222, 77, 107}, ++{232, 72, 111}, ++{242, 67, 116}, ++{253, 62, 120}, ++{254, 61, 120}, ++{202, 89, 99}, ++{208, 86, 101}, ++{215, 82, 105}, ++{224, 78, 108}, ++{234, 73, 112}, ++{244, 68, 116}, ++{255, 63, 120}, ++{255, 62, 121}, ++{204, 90, 99}, ++{209, 87, 102}, ++{217, 83, 105}, ++{226, 78, 109}, ++{235, 74, 112}, ++{246, 69, 116}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 90, 99}, ++{209, 87, 102}, ++{217, 83, 105}, ++{226, 78, 109}, ++{235, 74, 112}, ++{246, 69, 116}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 90, 99}, ++{209, 87, 102}, ++{217, 83, 105}, ++{226, 78, 109}, ++{235, 74, 112}, ++{246, 69, 116}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 90, 99}, ++{209, 87, 102}, ++{217, 83, 105}, ++{226, 78, 109}, ++{235, 74, 112}, ++{246, 69, 116}, ++{255, 63, 121}, ++{255, 63, 121}, ++{146, 50, 74}, ++{156, 52, 79}, ++{167, 52, 85}, ++{180, 51, 91}, ++{193, 49, 97}, ++{207, 47, 103}, ++{220, 43, 109}, ++{222, 43, 110}, ++{147, 50, 74}, ++{156, 52, 79}, ++{167, 52, 85}, ++{180, 51, 91}, ++{193, 49, 97}, ++{207, 47, 103}, ++{220, 43, 109}, ++{222, 43, 110}, ++{147, 51, 74}, ++{156, 52, 79}, ++{168, 52, 85}, ++{180, 51, 91}, ++{194, 49, 97}, ++{207, 47, 103}, ++{221, 44, 109}, ++{222, 43, 110}, ++{148, 52, 74}, ++{157, 53, 79}, ++{168, 53, 85}, ++{181, 52, 91}, ++{194, 50, 98}, ++{207, 47, 104}, ++{221, 44, 109}, ++{223, 43, 110}, ++{149, 53, 75}, ++{158, 53, 80}, ++{169, 53, 86}, ++{181, 52, 92}, ++{195, 50, 98}, ++{208, 47, 104}, ++{221, 44, 109}, ++{223, 44, 110}, ++{150, 54, 75}, ++{159, 54, 80}, ++{170, 54, 86}, ++{182, 53, 92}, ++{195, 51, 98}, ++{209, 48, 104}, ++{222, 44, 110}, ++{224, 44, 110}, ++{151, 55, 76}, ++{160, 55, 81}, ++{171, 55, 86}, ++{183, 54, 92}, ++{196, 51, 98}, ++{209, 48, 104}, ++{223, 45, 110}, ++{224, 44, 111}, ++{153, 56, 77}, ++{161, 57, 81}, ++{172, 56, 87}, ++{184, 54, 93}, ++{197, 52, 99}, ++{210, 49, 104}, ++{223, 45, 110}, ++{225, 45, 111}, ++{154, 58, 77}, ++{163, 58, 82}, ++{173, 57, 87}, ++{186, 55, 93}, ++{198, 53, 99}, ++{211, 49, 105}, ++{224, 46, 110}, ++{226, 45, 111}, ++{156, 60, 78}, ++{164, 59, 83}, ++{175, 58, 88}, ++{187, 56, 94}, ++{199, 53, 99}, ++{212, 50, 105}, ++{225, 47, 111}, ++{227, 46, 111}, ++{158, 61, 79}, ++{166, 61, 83}, ++{177, 59, 89}, ++{188, 57, 94}, ++{201, 54, 100}, ++{214, 51, 106}, ++{227, 47, 111}, ++{228, 47, 112}, ++{160, 63, 80}, ++{168, 62, 84}, ++{178, 60, 89}, ++{190, 58, 95}, ++{202, 55, 100}, ++{215, 52, 106}, ++{228, 48, 111}, ++{229, 47, 112}, ++{162, 65, 81}, ++{170, 64, 85}, ++{180, 62, 90}, ++{192, 59, 95}, ++{204, 56, 101}, ++{216, 52, 106}, ++{229, 49, 112}, ++{231, 48, 112}, ++{164, 66, 82}, ++{172, 65, 86}, ++{182, 63, 91}, ++{193, 60, 96}, ++{205, 57, 101}, ++{218, 53, 107}, ++{230, 49, 112}, ++{232, 49, 113}, ++{167, 68, 83}, ++{174, 67, 87}, ++{184, 64, 92}, ++{195, 61, 97}, ++{207, 58, 102}, ++{219, 54, 107}, ++{232, 50, 112}, ++{233, 50, 113}, ++{169, 70, 84}, ++{177, 68, 88}, ++{186, 66, 92}, ++{197, 63, 97}, ++{209, 59, 103}, ++{221, 55, 108}, ++{233, 51, 113}, ++{235, 50, 113}, ++{172, 71, 85}, ++{179, 70, 89}, ++{188, 67, 93}, ++{199, 64, 98}, ++{211, 60, 103}, ++{223, 56, 108}, ++{235, 52, 113}, ++{237, 51, 114}, ++{175, 73, 86}, ++{182, 71, 90}, ++{191, 68, 94}, ++{201, 65, 99}, ++{213, 61, 104}, ++{225, 57, 109}, ++{237, 53, 114}, ++{238, 52, 114}, ++{177, 75, 87}, ++{184, 73, 91}, ++{193, 70, 95}, ++{204, 66, 100}, ++{215, 62, 104}, ++{226, 58, 109}, ++{238, 54, 114}, ++{240, 53, 115}, ++{180, 76, 88}, ++{187, 74, 92}, ++{196, 71, 96}, ++{206, 67, 100}, ++{217, 63, 105}, ++{228, 59, 110}, ++{240, 54, 115}, ++{242, 54, 115}, ++{183, 78, 90}, ++{189, 75, 93}, ++{198, 72, 97}, ++{208, 68, 101}, ++{219, 64, 106}, ++{230, 60, 110}, ++{242, 55, 115}, ++{244, 55, 116}, ++{186, 79, 91}, ++{192, 77, 94}, ++{201, 74, 97}, ++{210, 70, 102}, ++{221, 65, 106}, ++{232, 61, 111}, ++{244, 56, 115}, ++{245, 56, 116}, ++{189, 81, 92}, ++{195, 78, 95}, ++{203, 75, 98}, ++{213, 71, 103}, ++{223, 66, 107}, ++{235, 62, 111}, ++{246, 57, 116}, ++{247, 57, 117}, ++{192, 82, 93}, ++{198, 80, 96}, ++{206, 76, 99}, ++{215, 72, 103}, ++{226, 68, 108}, ++{237, 63, 112}, ++{248, 58, 116}, ++{249, 57, 117}, ++{195, 83, 94}, ++{201, 81, 97}, ++{209, 77, 100}, ++{218, 73, 104}, ++{228, 69, 108}, ++{239, 64, 113}, ++{250, 59, 117}, ++{252, 58, 118}, ++{198, 85, 95}, ++{204, 82, 98}, ++{211, 78, 101}, ++{221, 74, 105}, ++{231, 70, 109}, ++{241, 65, 113}, ++{252, 60, 118}, ++{254, 59, 118}, ++{201, 86, 96}, ++{207, 83, 99}, ++{214, 80, 102}, ++{223, 75, 106}, ++{233, 71, 110}, ++{244, 66, 114}, ++{254, 61, 118}, ++{255, 60, 119}, ++{204, 87, 97}, ++{210, 84, 99}, ++{217, 81, 103}, ++{226, 76, 106}, ++{236, 72, 110}, ++{246, 67, 114}, ++{255, 62, 119}, ++{255, 61, 119}, ++{206, 88, 98}, ++{211, 85, 100}, ++{219, 81, 103}, ++{227, 77, 107}, ++{237, 72, 111}, ++{247, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{211, 85, 100}, ++{219, 81, 103}, ++{227, 77, 107}, ++{237, 72, 111}, ++{247, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{211, 85, 100}, ++{219, 81, 103}, ++{227, 77, 107}, ++{237, 72, 111}, ++{247, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{211, 85, 100}, ++{219, 81, 103}, ++{227, 77, 107}, ++{237, 72, 111}, ++{247, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{149, 48, 72}, ++{158, 49, 77}, ++{169, 50, 83}, ++{182, 49, 89}, ++{195, 48, 95}, ++{208, 45, 101}, ++{222, 42, 107}, ++{224, 42, 108}, ++{149, 48, 72}, ++{158, 50, 77}, ++{170, 50, 83}, ++{182, 49, 89}, ++{195, 48, 95}, ++{209, 45, 101}, ++{222, 42, 107}, ++{224, 42, 108}, ++{150, 49, 72}, ++{159, 50, 77}, ++{170, 50, 83}, ++{182, 50, 89}, ++{195, 48, 96}, ++{209, 45, 102}, ++{222, 42, 107}, ++{224, 42, 108}, ++{150, 49, 73}, ++{159, 51, 77}, ++{170, 51, 83}, ++{183, 50, 90}, ++{196, 48, 96}, ++{209, 46, 102}, ++{223, 43, 107}, ++{224, 42, 108}, ++{151, 50, 73}, ++{160, 51, 78}, ++{171, 51, 84}, ++{184, 50, 90}, ++{197, 49, 96}, ++{210, 46, 102}, ++{223, 43, 108}, ++{225, 42, 108}, ++{152, 51, 74}, ++{161, 52, 78}, ++{172, 52, 84}, ++{184, 51, 90}, ++{197, 49, 96}, ++{210, 46, 102}, ++{224, 43, 108}, ++{225, 43, 108}, ++{154, 53, 74}, ++{162, 53, 79}, ++{173, 53, 84}, ++{185, 52, 90}, ++{198, 50, 96}, ++{211, 47, 102}, ++{224, 44, 108}, ++{226, 43, 109}, ++{155, 54, 75}, ++{164, 54, 79}, ++{174, 54, 85}, ++{186, 53, 91}, ++{199, 50, 97}, ++{212, 47, 103}, ++{225, 44, 108}, ++{227, 44, 109}, ++{157, 56, 76}, ++{165, 56, 80}, ++{176, 55, 86}, ++{188, 53, 91}, ++{200, 51, 97}, ++{213, 48, 103}, ++{226, 45, 108}, ++{228, 44, 109}, ++{158, 57, 76}, ++{167, 57, 81}, ++{177, 56, 86}, ++{189, 54, 92}, ++{201, 52, 98}, ++{214, 49, 103}, ++{227, 45, 109}, ++{229, 45, 109}, ++{160, 59, 77}, ++{168, 58, 82}, ++{179, 57, 87}, ++{190, 55, 92}, ++{203, 53, 98}, ++{215, 49, 104}, ++{228, 46, 109}, ++{230, 45, 110}, ++{162, 61, 78}, ++{170, 60, 82}, ++{180, 59, 87}, ++{192, 56, 93}, ++{204, 54, 99}, ++{217, 50, 104}, ++{229, 47, 109}, ++{231, 46, 110}, ++{165, 62, 79}, ++{172, 61, 83}, ++{182, 60, 88}, ++{194, 57, 94}, ++{206, 54, 99}, ++{218, 51, 104}, ++{231, 47, 110}, ++{232, 47, 110}, ++{167, 64, 80}, ++{174, 63, 84}, ++{184, 61, 89}, ++{195, 59, 94}, ++{207, 55, 100}, ++{220, 52, 105}, ++{232, 48, 110}, ++{234, 48, 111}, ++{169, 66, 81}, ++{177, 64, 85}, ++{186, 62, 90}, ++{197, 60, 95}, ++{209, 56, 100}, ++{221, 53, 105}, ++{233, 49, 111}, ++{235, 48, 111}, ++{172, 67, 82}, ++{179, 66, 86}, ++{188, 64, 90}, ++{199, 61, 96}, ++{211, 57, 101}, ++{223, 54, 106}, ++{235, 50, 111}, ++{237, 49, 112}, ++{174, 69, 83}, ++{181, 68, 87}, ++{190, 65, 91}, ++{201, 62, 96}, ++{213, 59, 101}, ++{224, 55, 106}, ++{237, 51, 111}, ++{238, 50, 112}, ++{177, 71, 84}, ++{184, 69, 88}, ++{193, 66, 92}, ++{203, 63, 97}, ++{214, 60, 102}, ++{226, 56, 107}, ++{238, 51, 112}, ++{240, 51, 112}, ++{179, 73, 86}, ++{186, 71, 89}, ++{195, 68, 93}, ++{205, 64, 98}, ++{216, 61, 103}, ++{228, 57, 107}, ++{240, 52, 112}, ++{241, 52, 113}, ++{182, 74, 87}, ++{189, 72, 90}, ++{198, 69, 94}, ++{208, 66, 98}, ++{219, 62, 103}, ++{230, 58, 108}, ++{242, 53, 113}, ++{243, 53, 113}, ++{185, 76, 88}, ++{191, 73, 91}, ++{200, 70, 95}, ++{210, 67, 99}, ++{221, 63, 104}, ++{232, 59, 109}, ++{244, 54, 113}, ++{245, 54, 114}, ++{188, 77, 89}, ++{194, 75, 92}, ++{203, 72, 96}, ++{212, 68, 100}, ++{223, 64, 104}, ++{234, 60, 109}, ++{246, 55, 114}, ++{247, 54, 114}, ++{191, 79, 90}, ++{197, 76, 93}, ++{205, 73, 96}, ++{215, 69, 101}, ++{225, 65, 105}, ++{236, 61, 110}, ++{248, 56, 114}, ++{249, 55, 115}, ++{194, 80, 91}, ++{200, 78, 94}, ++{208, 74, 97}, ++{217, 70, 101}, ++{227, 66, 106}, ++{238, 62, 110}, ++{250, 57, 115}, ++{251, 56, 115}, ++{197, 82, 92}, ++{203, 79, 95}, ++{211, 76, 98}, ++{220, 72, 102}, ++{230, 67, 107}, ++{241, 63, 111}, ++{252, 58, 115}, ++{253, 57, 116}, ++{200, 83, 93}, ++{205, 80, 96}, ++{213, 77, 99}, ++{222, 73, 103}, ++{232, 68, 107}, ++{243, 64, 111}, ++{254, 59, 116}, ++{255, 58, 116}, ++{203, 84, 94}, ++{208, 82, 97}, ++{216, 78, 100}, ++{225, 74, 104}, ++{235, 69, 108}, ++{245, 65, 112}, ++{255, 60, 116}, ++{255, 59, 117}, ++{206, 85, 95}, ++{211, 83, 98}, ++{219, 79, 101}, ++{228, 75, 105}, ++{237, 70, 109}, ++{248, 66, 113}, ++{255, 61, 117}, ++{255, 60, 117}, ++{207, 86, 96}, ++{213, 83, 98}, ++{220, 80, 101}, ++{229, 75, 105}, ++{239, 71, 109}, ++{249, 66, 113}, ++{255, 61, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{213, 83, 98}, ++{220, 80, 101}, ++{229, 75, 105}, ++{239, 71, 109}, ++{249, 66, 113}, ++{255, 61, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{213, 83, 98}, ++{220, 80, 101}, ++{229, 75, 105}, ++{239, 71, 109}, ++{249, 66, 113}, ++{255, 61, 117}, ++{255, 61, 118}, ++{207, 86, 96}, ++{213, 83, 98}, ++{220, 80, 101}, ++{229, 75, 105}, ++{239, 71, 109}, ++{249, 66, 113}, ++{255, 61, 117}, ++{255, 61, 118}, ++{152, 46, 70}, ++{161, 47, 75}, ++{172, 48, 81}, ++{184, 47, 87}, ++{197, 46, 93}, ++{210, 44, 100}, ++{224, 41, 105}, ++{225, 40, 106}, ++{152, 46, 70}, ++{161, 47, 75}, ++{172, 48, 81}, ++{184, 48, 87}, ++{197, 46, 94}, ++{210, 44, 100}, ++{224, 41, 105}, ++{225, 40, 106}, ++{152, 46, 71}, ++{161, 48, 75}, ++{172, 48, 81}, ++{185, 48, 87}, ++{197, 46, 94}, ++{211, 44, 100}, ++{224, 41, 105}, ++{226, 41, 106}, ++{153, 47, 71}, ++{162, 48, 76}, ++{173, 49, 81}, ++{185, 48, 88}, ++{198, 47, 94}, ++{211, 44, 100}, ++{224, 41, 106}, ++{226, 41, 106}, ++{154, 48, 71}, ++{162, 49, 76}, ++{173, 49, 82}, ++{186, 49, 88}, ++{198, 47, 94}, ++{212, 45, 100}, ++{225, 42, 106}, ++{226, 41, 106}, ++{155, 49, 72}, ++{163, 50, 76}, ++{174, 50, 82}, ++{186, 49, 88}, ++{199, 47, 94}, ++{212, 45, 100}, ++{225, 42, 106}, ++{227, 42, 107}, ++{156, 50, 72}, ++{165, 51, 77}, ++{175, 51, 83}, ++{187, 50, 89}, ++{200, 48, 95}, ++{213, 45, 100}, ++{226, 42, 106}, ++{228, 42, 107}, ++{158, 52, 73}, ++{166, 52, 78}, ++{177, 52, 83}, ++{188, 51, 89}, ++{201, 49, 95}, ++{214, 46, 101}, ++{227, 43, 106}, ++{229, 42, 107}, ++{159, 53, 74}, ++{167, 54, 78}, ++{178, 53, 84}, ++{190, 52, 89}, ++{202, 49, 95}, ++{215, 47, 101}, ++{228, 43, 107}, ++{229, 43, 107}, ++{161, 55, 75}, ++{169, 55, 79}, ++{179, 54, 84}, ++{191, 53, 90}, ++{203, 50, 96}, ++{216, 47, 101}, ++{229, 44, 107}, ++{230, 44, 108}, ++{163, 57, 76}, ++{171, 56, 80}, ++{181, 55, 85}, ++{192, 54, 90}, ++{205, 51, 96}, ++{217, 48, 102}, ++{230, 45, 107}, ++{232, 44, 108}, ++{165, 58, 77}, ++{173, 58, 81}, ++{183, 57, 86}, ++{194, 55, 91}, ++{206, 52, 97}, ++{218, 49, 102}, ++{231, 45, 108}, ++{233, 45, 108}, ++{167, 60, 77}, ++{175, 59, 81}, ++{184, 58, 86}, ++{196, 56, 92}, ++{207, 53, 97}, ++{220, 50, 103}, ++{232, 46, 108}, ++{234, 46, 109}, ++{169, 62, 78}, ++{177, 61, 82}, ++{186, 59, 87}, ++{197, 57, 92}, ++{209, 54, 98}, ++{221, 51, 103}, ++{234, 47, 108}, ++{235, 46, 109}, ++{172, 64, 79}, ++{179, 62, 83}, ++{188, 61, 88}, ++{199, 58, 93}, ++{211, 55, 98}, ++{223, 51, 104}, ++{235, 48, 109}, ++{237, 47, 109}, ++{174, 65, 81}, ++{181, 64, 84}, ++{190, 62, 89}, ++{201, 59, 94}, ++{213, 56, 99}, ++{224, 52, 104}, ++{237, 48, 109}, ++{238, 48, 110}, ++{176, 67, 82}, ++{183, 66, 85}, ++{193, 63, 89}, ++{203, 60, 94}, ++{214, 57, 99}, ++{226, 53, 105}, ++{238, 49, 110}, ++{240, 49, 110}, ++{179, 69, 83}, ++{186, 67, 86}, ++{195, 65, 90}, ++{205, 62, 95}, ++{216, 58, 100}, ++{228, 54, 105}, ++{240, 50, 110}, ++{241, 50, 111}, ++{182, 70, 84}, ++{188, 69, 87}, ++{197, 66, 91}, ++{207, 63, 96}, ++{218, 59, 101}, ++{230, 55, 106}, ++{242, 51, 110}, ++{243, 51, 111}, ++{184, 72, 85}, ++{191, 70, 88}, ++{199, 67, 92}, ++{209, 64, 97}, ++{220, 60, 101}, ++{232, 56, 106}, ++{243, 52, 111}, ++{245, 51, 112}, ++{187, 74, 86}, ++{193, 72, 89}, ++{202, 69, 93}, ++{212, 65, 97}, ++{222, 61, 102}, ++{234, 57, 107}, ++{245, 53, 111}, ++{247, 52, 112}, ++{190, 75, 87}, ++{196, 73, 90}, ++{204, 70, 94}, ++{214, 66, 98}, ++{225, 62, 103}, ++{236, 58, 107}, ++{247, 54, 112}, ++{249, 53, 113}, ++{193, 77, 88}, ++{199, 74, 91}, ++{207, 71, 95}, ++{217, 68, 99}, ++{227, 64, 103}, ++{238, 59, 108}, ++{249, 55, 112}, ++{251, 54, 113}, ++{196, 78, 89}, ++{202, 76, 92}, ++{210, 73, 96}, ++{219, 69, 100}, ++{229, 65, 104}, ++{240, 60, 109}, ++{251, 56, 113}, ++{253, 55, 114}, ++{199, 80, 90}, ++{204, 77, 93}, ++{212, 74, 96}, ++{221, 70, 100}, ++{232, 66, 105}, ++{242, 61, 109}, ++{253, 57, 114}, ++{255, 56, 114}, ++{202, 81, 91}, ++{207, 78, 94}, ++{215, 75, 97}, ++{224, 71, 101}, ++{234, 67, 105}, ++{244, 62, 110}, ++{255, 58, 114}, ++{255, 57, 115}, ++{205, 82, 92}, ++{210, 80, 95}, ++{218, 76, 98}, ++{227, 72, 102}, ++{236, 68, 106}, ++{247, 63, 110}, ++{255, 59, 115}, ++{255, 58, 115}, ++{208, 84, 93}, ++{213, 81, 96}, ++{221, 77, 99}, ++{229, 73, 103}, ++{239, 69, 107}, ++{249, 64, 111}, ++{255, 60, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{215, 82, 96}, ++{222, 78, 100}, ++{231, 74, 103}, ++{240, 70, 107}, ++{250, 65, 111}, ++{255, 60, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{215, 82, 96}, ++{222, 78, 100}, ++{231, 74, 103}, ++{240, 70, 107}, ++{250, 65, 111}, ++{255, 60, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{215, 82, 96}, ++{222, 78, 100}, ++{231, 74, 103}, ++{240, 70, 107}, ++{250, 65, 111}, ++{255, 60, 115}, ++{255, 59, 116}, ++{209, 84, 94}, ++{215, 82, 96}, ++{222, 78, 100}, ++{231, 74, 103}, ++{240, 70, 107}, ++{250, 65, 111}, ++{255, 60, 115}, ++{255, 59, 116}, ++{154, 44, 69}, ++{163, 45, 73}, ++{174, 46, 79}, ++{186, 46, 85}, ++{199, 44, 92}, ++{212, 42, 98}, ++{225, 40, 103}, ++{227, 39, 104}, ++{155, 44, 69}, ++{163, 45, 73}, ++{174, 46, 79}, ++{186, 46, 85}, ++{199, 44, 92}, ++{212, 42, 98}, ++{225, 40, 103}, ++{227, 39, 104}, ++{155, 44, 69}, ++{164, 46, 74}, ++{174, 46, 79}, ++{187, 46, 86}, ++{199, 45, 92}, ++{213, 42, 98}, ++{226, 40, 104}, ++{227, 39, 104}, ++{156, 45, 69}, ++{164, 46, 74}, ++{175, 47, 80}, ++{187, 46, 86}, ++{200, 45, 92}, ++{213, 43, 98}, ++{226, 40, 104}, ++{228, 40, 104}, ++{156, 46, 70}, ++{165, 47, 74}, ++{176, 47, 80}, ++{188, 47, 86}, ++{200, 45, 92}, ++{213, 43, 98}, ++{227, 40, 104}, ++{228, 40, 105}, ++{158, 47, 70}, ++{166, 48, 75}, ++{177, 48, 80}, ++{189, 48, 86}, ++{201, 46, 92}, ++{214, 44, 98}, ++{227, 41, 104}, ++{229, 40, 105}, ++{159, 48, 71}, ++{167, 49, 75}, ++{178, 49, 81}, ++{189, 48, 87}, ++{202, 46, 93}, ++{215, 44, 99}, ++{228, 41, 104}, ++{229, 41, 105}, ++{160, 50, 71}, ++{168, 50, 76}, ++{179, 50, 81}, ++{191, 49, 87}, ++{203, 47, 93}, ++{216, 45, 99}, ++{229, 42, 104}, ++{230, 41, 105}, ++{162, 51, 72}, ++{170, 51, 76}, ++{180, 51, 82}, ++{192, 50, 88}, ++{204, 48, 93}, ++{217, 45, 99}, ++{230, 42, 105}, ++{231, 42, 105}, ++{163, 53, 73}, ++{171, 53, 77}, ++{182, 52, 82}, ++{193, 51, 88}, ++{205, 49, 94}, ++{218, 46, 100}, ++{231, 43, 105}, ++{232, 42, 106}, ++{165, 54, 74}, ++{173, 54, 78}, ++{183, 53, 83}, ++{194, 52, 89}, ++{206, 50, 94}, ++{219, 47, 100}, ++{232, 43, 105}, ++{233, 43, 106}, ++{167, 56, 75}, ++{175, 56, 79}, ++{185, 55, 84}, ++{196, 53, 89}, ++{208, 50, 95}, ++{220, 47, 100}, ++{233, 44, 106}, ++{234, 44, 106}, ++{169, 58, 76}, ++{177, 57, 80}, ++{187, 56, 84}, ++{198, 54, 90}, ++{209, 51, 95}, ++{222, 48, 101}, ++{234, 45, 106}, ++{236, 44, 107}, ++{172, 60, 77}, ++{179, 59, 80}, ++{188, 57, 85}, ++{199, 55, 90}, ++{211, 52, 96}, ++{223, 49, 101}, ++{235, 46, 106}, ++{237, 45, 107}, ++{174, 61, 78}, ++{181, 60, 81}, ++{190, 59, 86}, ++{201, 56, 91}, ++{213, 53, 96}, ++{225, 50, 102}, ++{237, 46, 107}, ++{238, 46, 107}, ++{176, 63, 79}, ++{183, 62, 82}, ++{192, 60, 87}, ++{203, 57, 92}, ++{214, 54, 97}, ++{226, 51, 102}, ++{238, 47, 107}, ++{240, 47, 108}, ++{179, 65, 80}, ++{186, 63, 83}, ++{195, 61, 88}, ++{205, 59, 93}, ++{216, 55, 98}, ++{228, 52, 103}, ++{240, 48, 108}, ++{241, 48, 108}, ++{181, 67, 81}, ++{188, 65, 84}, ++{197, 63, 88}, ++{207, 60, 93}, ++{218, 57, 98}, ++{230, 53, 103}, ++{241, 49, 108}, ++{243, 48, 109}, ++{184, 68, 82}, ++{190, 67, 85}, ++{199, 64, 89}, ++{209, 61, 94}, ++{220, 58, 99}, ++{231, 54, 104}, ++{243, 50, 109}, ++{245, 49, 109}, ++{186, 70, 83}, ++{193, 68, 86}, ++{201, 66, 90}, ++{211, 62, 95}, ++{222, 59, 100}, ++{233, 55, 104}, ++{245, 51, 109}, ++{246, 50, 110}, ++{189, 72, 84}, ++{195, 70, 87}, ++{204, 67, 91}, ++{214, 64, 96}, ++{224, 60, 100}, ++{235, 56, 105}, ++{247, 52, 110}, ++{248, 51, 110}, ++{192, 73, 85}, ++{198, 71, 88}, ++{206, 68, 92}, ++{216, 65, 96}, ++{226, 61, 101}, ++{237, 57, 106}, ++{249, 53, 110}, ++{250, 52, 111}, ++{195, 75, 86}, ++{201, 73, 89}, ++{209, 70, 93}, ++{218, 66, 97}, ++{229, 62, 102}, ++{239, 58, 106}, ++{251, 54, 111}, ++{252, 53, 111}, ++{198, 76, 87}, ++{204, 74, 90}, ++{212, 71, 94}, ++{221, 67, 98}, ++{231, 63, 102}, ++{242, 59, 107}, ++{253, 55, 111}, ++{254, 54, 112}, ++{201, 78, 88}, ++{206, 75, 91}, ++{214, 72, 95}, ++{223, 68, 99}, ++{233, 64, 103}, ++{244, 60, 107}, ++{255, 56, 112}, ++{255, 55, 112}, ++{204, 79, 90}, ++{209, 77, 92}, ++{217, 73, 96}, ++{226, 70, 100}, ++{236, 65, 104}, ++{246, 61, 108}, ++{255, 56, 112}, ++{255, 56, 113}, ++{207, 80, 91}, ++{212, 78, 93}, ++{220, 75, 97}, ++{228, 71, 100}, ++{238, 67, 104}, ++{248, 62, 109}, ++{255, 57, 113}, ++{255, 57, 113}, ++{210, 82, 92}, ++{215, 79, 94}, ++{222, 76, 97}, ++{231, 72, 101}, ++{240, 68, 105}, ++{251, 63, 109}, ++{255, 58, 113}, ++{255, 58, 114}, ++{211, 82, 92}, ++{217, 80, 95}, ++{224, 76, 98}, ++{232, 72, 102}, ++{242, 68, 105}, ++{252, 64, 110}, ++{255, 59, 114}, ++{255, 58, 114}, ++{211, 82, 92}, ++{217, 80, 95}, ++{224, 76, 98}, ++{232, 72, 102}, ++{242, 68, 105}, ++{252, 64, 110}, ++{255, 59, 114}, ++{255, 58, 114}, ++{211, 82, 92}, ++{217, 80, 95}, ++{224, 76, 98}, ++{232, 72, 102}, ++{242, 68, 105}, ++{252, 64, 110}, ++{255, 59, 114}, ++{255, 58, 114}, ++{211, 82, 92}, ++{217, 80, 95}, ++{224, 76, 98}, ++{232, 72, 102}, ++{242, 68, 105}, ++{252, 64, 110}, ++{255, 59, 114}, ++{255, 58, 114}, ++{157, 41, 67}, ++{165, 43, 72}, ++{176, 44, 77}, ++{188, 44, 84}, ++{201, 43, 90}, ++{214, 41, 96}, ++{227, 38, 102}, ++{229, 38, 102}, ++{157, 42, 67}, ++{166, 43, 72}, ++{176, 44, 77}, ++{188, 44, 84}, ++{201, 43, 90}, ++{214, 41, 96}, ++{227, 38, 102}, ++{229, 38, 102}, ++{158, 42, 67}, ++{166, 44, 72}, ++{177, 44, 78}, ++{189, 44, 84}, ++{201, 43, 90}, ++{214, 41, 96}, ++{227, 38, 102}, ++{229, 38, 102}, ++{158, 43, 68}, ++{167, 44, 72}, ++{177, 45, 78}, ++{189, 45, 84}, ++{202, 43, 90}, ++{215, 41, 96}, ++{228, 39, 102}, ++{229, 38, 103}, ++{159, 44, 68}, ++{167, 45, 73}, ++{178, 46, 78}, ++{190, 45, 84}, ++{202, 44, 90}, ++{215, 42, 96}, ++{228, 39, 102}, ++{230, 39, 103}, ++{160, 45, 68}, ++{168, 46, 73}, ++{179, 46, 79}, ++{191, 46, 85}, ++{203, 44, 91}, ++{216, 42, 96}, ++{229, 39, 102}, ++{230, 39, 103}, ++{161, 46, 69}, ++{169, 47, 73}, ++{180, 47, 79}, ++{192, 46, 85}, ++{204, 45, 91}, ++{217, 43, 97}, ++{230, 40, 102}, ++{231, 39, 103}, ++{163, 47, 70}, ++{171, 48, 74}, ++{181, 48, 79}, ++{193, 47, 85}, ++{205, 46, 91}, ++{218, 43, 97}, ++{230, 40, 103}, ++{232, 40, 103}, ++{164, 49, 70}, ++{172, 49, 75}, ++{182, 49, 80}, ++{194, 48, 86}, ++{206, 46, 92}, ++{219, 44, 97}, ++{231, 41, 103}, ++{233, 40, 104}, ++{166, 50, 71}, ++{174, 51, 75}, ++{184, 50, 81}, ++{195, 49, 86}, ++{207, 47, 92}, ++{220, 44, 98}, ++{232, 41, 103}, ++{234, 41, 104}, ++{168, 52, 72}, ++{175, 52, 76}, ++{185, 51, 81}, ++{196, 50, 87}, ++{208, 48, 92}, ++{221, 45, 98}, ++{233, 42, 104}, ++{235, 42, 104}, ++{170, 54, 73}, ++{177, 54, 77}, ++{187, 53, 82}, ++{198, 51, 87}, ++{210, 49, 93}, ++{222, 46, 98}, ++{234, 43, 104}, ++{236, 42, 105}, ++{172, 56, 74}, ++{179, 55, 78}, ++{189, 54, 83}, ++{200, 52, 88}, ++{211, 50, 93}, ++{223, 47, 99}, ++{236, 43, 104}, ++{237, 43, 105}, ++{174, 57, 75}, ++{181, 57, 79}, ++{190, 55, 83}, ++{201, 53, 89}, ++{213, 51, 94}, ++{225, 48, 99}, ++{237, 44, 105}, ++{239, 44, 105}, ++{176, 59, 76}, ++{183, 58, 80}, ++{192, 57, 84}, ++{203, 55, 89}, ++{214, 52, 95}, ++{226, 49, 100}, ++{238, 45, 105}, ++{240, 45, 106}, ++{178, 61, 77}, ++{185, 60, 81}, ++{194, 58, 85}, ++{205, 56, 90}, ++{216, 53, 95}, ++{228, 50, 100}, ++{240, 46, 105}, ++{241, 45, 106}, ++{181, 63, 78}, ++{188, 61, 81}, ++{197, 60, 86}, ++{207, 57, 91}, ++{218, 54, 96}, ++{230, 51, 101}, ++{241, 47, 106}, ++{243, 46, 107}, ++{183, 64, 79}, ++{190, 63, 82}, ++{199, 61, 87}, ++{209, 58, 91}, ++{220, 55, 96}, ++{231, 51, 101}, ++{243, 48, 106}, ++{245, 47, 107}, ++{186, 66, 80}, ++{192, 65, 83}, ++{201, 62, 88}, ++{211, 59, 92}, ++{222, 56, 97}, ++{233, 52, 102}, ++{245, 49, 107}, ++{246, 48, 107}, ++{189, 68, 81}, ++{195, 66, 84}, ++{203, 64, 88}, ++{213, 61, 93}, ++{224, 57, 98}, ++{235, 54, 103}, ++{247, 50, 107}, ++{248, 49, 108}, ++{191, 69, 82}, ++{198, 68, 85}, ++{206, 65, 89}, ++{215, 62, 94}, ++{226, 58, 98}, ++{237, 55, 103}, ++{248, 50, 108}, ++{250, 50, 108}, ++{194, 71, 83}, ++{200, 69, 86}, ++{208, 66, 90}, ++{218, 63, 95}, ++{228, 60, 99}, ++{239, 56, 104}, ++{250, 51, 108}, ++{252, 51, 109}, ++{197, 73, 85}, ++{203, 71, 87}, ++{211, 68, 91}, ++{220, 64, 95}, ++{230, 61, 100}, ++{241, 57, 104}, ++{252, 52, 109}, ++{254, 52, 110}, ++{200, 74, 86}, ++{206, 72, 88}, ++{213, 69, 92}, ++{223, 66, 96}, ++{233, 62, 101}, ++{243, 58, 105}, ++{254, 53, 109}, ++{255, 53, 110}, ++{203, 76, 87}, ++{208, 73, 89}, ++{216, 70, 93}, ++{225, 67, 97}, ++{235, 63, 101}, ++{245, 59, 106}, ++{255, 54, 110}, ++{255, 54, 111}, ++{206, 77, 88}, ++{211, 75, 90}, ++{219, 72, 94}, ++{228, 68, 98}, ++{237, 64, 102}, ++{248, 60, 106}, ++{255, 55, 111}, ++{255, 55, 111}, ++{209, 78, 89}, ++{214, 76, 91}, ++{221, 73, 95}, ++{230, 69, 99}, ++{240, 65, 103}, ++{250, 61, 107}, ++{255, 56, 111}, ++{255, 56, 112}, ++{212, 80, 90}, ++{217, 77, 92}, ++{224, 74, 96}, ++{233, 70, 99}, ++{242, 66, 103}, ++{252, 62, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{213, 80, 91}, ++{218, 78, 93}, ++{226, 75, 96}, ++{234, 71, 100}, ++{243, 67, 104}, ++{253, 62, 108}, ++{255, 58, 112}, ++{255, 57, 113}, ++{213, 80, 91}, ++{218, 78, 93}, ++{226, 75, 96}, ++{234, 71, 100}, ++{243, 67, 104}, ++{253, 62, 108}, ++{255, 58, 112}, ++{255, 57, 113}, ++{213, 80, 91}, ++{218, 78, 93}, ++{226, 75, 96}, ++{234, 71, 100}, ++{243, 67, 104}, ++{253, 62, 108}, ++{255, 58, 112}, ++{255, 57, 113}, ++{213, 80, 91}, ++{218, 78, 93}, ++{226, 75, 96}, ++{234, 71, 100}, ++{243, 67, 104}, ++{253, 62, 108}, ++{255, 58, 112}, ++{255, 57, 113}, ++{158, 40, 66}, ++{167, 42, 71}, ++{177, 43, 77}, ++{189, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{158, 40, 66}, ++{167, 42, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{159, 41, 66}, ++{167, 43, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 102}, ++{160, 42, 67}, ++{168, 43, 71}, ++{178, 44, 77}, ++{190, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{230, 38, 102}, ++{160, 43, 67}, ++{169, 44, 72}, ++{179, 45, 77}, ++{191, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{231, 38, 102}, ++{161, 44, 68}, ++{170, 45, 72}, ++{180, 45, 78}, ++{192, 45, 84}, ++{204, 43, 90}, ++{217, 41, 96}, ++{230, 39, 101}, ++{231, 38, 102}, ++{163, 45, 68}, ++{171, 46, 73}, ++{181, 46, 78}, ++{193, 46, 84}, ++{205, 44, 90}, ++{218, 42, 96}, ++{230, 39, 101}, ++{232, 39, 102}, ++{164, 46, 69}, ++{172, 47, 73}, ++{182, 47, 79}, ++{194, 46, 84}, ++{206, 45, 90}, ++{218, 42, 96}, ++{231, 40, 102}, ++{233, 39, 102}, ++{165, 48, 70}, ++{173, 48, 74}, ++{183, 48, 79}, ++{195, 47, 85}, ++{207, 45, 91}, ++{219, 43, 96}, ++{232, 40, 102}, ++{234, 40, 103}, ++{167, 49, 70}, ++{175, 50, 75}, ++{185, 49, 80}, ++{196, 48, 85}, ++{208, 46, 91}, ++{220, 44, 97}, ++{233, 41, 102}, ++{235, 40, 103}, ++{169, 51, 71}, ++{176, 51, 75}, ++{186, 51, 80}, ++{197, 49, 86}, ++{209, 47, 92}, ++{222, 44, 97}, ++{234, 41, 103}, ++{236, 41, 103}, ++{171, 53, 72}, ++{178, 53, 76}, ++{188, 52, 81}, ++{199, 50, 86}, ++{211, 48, 92}, ++{223, 45, 98}, ++{235, 42, 103}, ++{237, 42, 104}, ++{173, 54, 73}, ++{180, 54, 77}, ++{190, 53, 82}, ++{201, 51, 87}, ++{212, 49, 93}, ++{224, 46, 98}, ++{237, 43, 103}, ++{238, 42, 104}, ++{175, 56, 74}, ++{182, 56, 78}, ++{192, 54, 83}, ++{202, 52, 88}, ++{214, 50, 93}, ++{226, 47, 98}, ++{238, 44, 104}, ++{239, 43, 104}, ++{177, 58, 75}, ++{184, 57, 79}, ++{193, 56, 83}, ++{204, 54, 88}, ++{215, 51, 94}, ++{227, 48, 99}, ++{239, 44, 104}, ++{241, 44, 105}, ++{180, 60, 76}, ++{186, 59, 80}, ++{196, 57, 84}, ++{206, 55, 89}, ++{217, 52, 94}, ++{229, 49, 99}, ++{241, 45, 105}, ++{242, 45, 105}, ++{182, 62, 77}, ++{189, 60, 81}, ++{198, 59, 85}, ++{208, 56, 90}, ++{219, 53, 95}, ++{230, 50, 100}, ++{242, 46, 105}, ++{244, 46, 106}, ++{184, 63, 78}, ++{191, 62, 82}, ++{200, 60, 86}, ++{210, 57, 91}, ++{221, 54, 96}, ++{232, 51, 101}, ++{244, 47, 106}, ++{245, 47, 106}, ++{187, 65, 79}, ++{193, 64, 83}, ++{202, 61, 87}, ++{212, 59, 91}, ++{223, 55, 96}, ++{234, 52, 101}, ++{246, 48, 106}, ++{247, 47, 107}, ++{190, 67, 80}, ++{196, 65, 83}, ++{204, 63, 88}, ++{214, 60, 92}, ++{225, 57, 97}, ++{236, 53, 102}, ++{247, 49, 107}, ++{249, 48, 107}, ++{192, 68, 81}, ++{199, 67, 84}, ++{207, 64, 88}, ++{216, 61, 93}, ++{227, 58, 98}, ++{238, 54, 102}, ++{249, 50, 107}, ++{251, 49, 108}, ++{195, 70, 83}, ++{201, 68, 86}, ++{209, 66, 89}, ++{219, 62, 94}, ++{229, 59, 98}, ++{240, 55, 103}, ++{251, 51, 108}, ++{252, 50, 108}, ++{198, 72, 84}, ++{204, 70, 87}, ++{212, 67, 90}, ++{221, 64, 94}, ++{231, 60, 99}, ++{242, 56, 103}, ++{253, 52, 108}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{214, 68, 91}, ++{223, 65, 95}, ++{233, 61, 100}, ++{244, 57, 104}, ++{255, 53, 109}, ++{255, 52, 109}, ++{204, 75, 86}, ++{209, 73, 89}, ++{217, 70, 92}, ++{226, 66, 96}, ++{236, 62, 100}, ++{246, 58, 105}, ++{255, 54, 109}, ++{255, 53, 110}, ++{207, 76, 87}, ++{212, 74, 90}, ++{220, 71, 93}, ++{228, 67, 97}, ++{238, 63, 101}, ++{248, 59, 105}, ++{255, 55, 110}, ++{255, 54, 110}, ++{209, 78, 88}, ++{215, 75, 91}, ++{222, 72, 94}, ++{231, 68, 98}, ++{240, 64, 102}, ++{251, 60, 106}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{218, 77, 92}, ++{225, 73, 95}, ++{234, 70, 99}, ++{243, 66, 103}, ++{253, 61, 107}, ++{255, 57, 111}, ++{255, 56, 111}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{167, 42, 71}, ++{177, 43, 77}, ++{189, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{158, 40, 66}, ++{167, 42, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{159, 41, 66}, ++{167, 43, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 102}, ++{160, 42, 67}, ++{168, 43, 71}, ++{178, 44, 77}, ++{190, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{230, 38, 102}, ++{160, 43, 67}, ++{169, 44, 72}, ++{179, 45, 77}, ++{191, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{231, 38, 102}, ++{161, 44, 68}, ++{170, 45, 72}, ++{180, 45, 78}, ++{192, 45, 84}, ++{204, 43, 90}, ++{217, 41, 96}, ++{230, 39, 101}, ++{231, 38, 102}, ++{163, 45, 68}, ++{171, 46, 73}, ++{181, 46, 78}, ++{193, 46, 84}, ++{205, 44, 90}, ++{218, 42, 96}, ++{230, 39, 101}, ++{232, 39, 102}, ++{164, 46, 69}, ++{172, 47, 73}, ++{182, 47, 79}, ++{194, 46, 84}, ++{206, 45, 90}, ++{218, 42, 96}, ++{231, 40, 102}, ++{233, 39, 102}, ++{165, 48, 70}, ++{173, 48, 74}, ++{183, 48, 79}, ++{195, 47, 85}, ++{207, 45, 91}, ++{219, 43, 96}, ++{232, 40, 102}, ++{234, 40, 103}, ++{167, 49, 70}, ++{175, 50, 75}, ++{185, 49, 80}, ++{196, 48, 85}, ++{208, 46, 91}, ++{220, 44, 97}, ++{233, 41, 102}, ++{235, 40, 103}, ++{169, 51, 71}, ++{176, 51, 75}, ++{186, 51, 80}, ++{197, 49, 86}, ++{209, 47, 92}, ++{222, 44, 97}, ++{234, 41, 103}, ++{236, 41, 103}, ++{171, 53, 72}, ++{178, 53, 76}, ++{188, 52, 81}, ++{199, 50, 86}, ++{211, 48, 92}, ++{223, 45, 98}, ++{235, 42, 103}, ++{237, 42, 104}, ++{173, 54, 73}, ++{180, 54, 77}, ++{190, 53, 82}, ++{201, 51, 87}, ++{212, 49, 93}, ++{224, 46, 98}, ++{237, 43, 103}, ++{238, 42, 104}, ++{175, 56, 74}, ++{182, 56, 78}, ++{192, 54, 83}, ++{202, 52, 88}, ++{214, 50, 93}, ++{226, 47, 98}, ++{238, 44, 104}, ++{239, 43, 104}, ++{177, 58, 75}, ++{184, 57, 79}, ++{193, 56, 83}, ++{204, 54, 88}, ++{215, 51, 94}, ++{227, 48, 99}, ++{239, 44, 104}, ++{241, 44, 105}, ++{180, 60, 76}, ++{186, 59, 80}, ++{196, 57, 84}, ++{206, 55, 89}, ++{217, 52, 94}, ++{229, 49, 99}, ++{241, 45, 105}, ++{242, 45, 105}, ++{182, 62, 77}, ++{189, 60, 81}, ++{198, 59, 85}, ++{208, 56, 90}, ++{219, 53, 95}, ++{230, 50, 100}, ++{242, 46, 105}, ++{244, 46, 106}, ++{184, 63, 78}, ++{191, 62, 82}, ++{200, 60, 86}, ++{210, 57, 91}, ++{221, 54, 96}, ++{232, 51, 101}, ++{244, 47, 106}, ++{245, 47, 106}, ++{187, 65, 79}, ++{193, 64, 83}, ++{202, 61, 87}, ++{212, 59, 91}, ++{223, 55, 96}, ++{234, 52, 101}, ++{246, 48, 106}, ++{247, 47, 107}, ++{190, 67, 80}, ++{196, 65, 83}, ++{204, 63, 88}, ++{214, 60, 92}, ++{225, 57, 97}, ++{236, 53, 102}, ++{247, 49, 107}, ++{249, 48, 107}, ++{192, 68, 81}, ++{199, 67, 84}, ++{207, 64, 88}, ++{216, 61, 93}, ++{227, 58, 98}, ++{238, 54, 102}, ++{249, 50, 107}, ++{251, 49, 108}, ++{195, 70, 83}, ++{201, 68, 86}, ++{209, 66, 89}, ++{219, 62, 94}, ++{229, 59, 98}, ++{240, 55, 103}, ++{251, 51, 108}, ++{252, 50, 108}, ++{198, 72, 84}, ++{204, 70, 87}, ++{212, 67, 90}, ++{221, 64, 94}, ++{231, 60, 99}, ++{242, 56, 103}, ++{253, 52, 108}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{214, 68, 91}, ++{223, 65, 95}, ++{233, 61, 100}, ++{244, 57, 104}, ++{255, 53, 109}, ++{255, 52, 109}, ++{204, 75, 86}, ++{209, 73, 89}, ++{217, 70, 92}, ++{226, 66, 96}, ++{236, 62, 100}, ++{246, 58, 105}, ++{255, 54, 109}, ++{255, 53, 110}, ++{207, 76, 87}, ++{212, 74, 90}, ++{220, 71, 93}, ++{228, 67, 97}, ++{238, 63, 101}, ++{248, 59, 105}, ++{255, 55, 110}, ++{255, 54, 110}, ++{209, 78, 88}, ++{215, 75, 91}, ++{222, 72, 94}, ++{231, 68, 98}, ++{240, 64, 102}, ++{251, 60, 106}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{218, 77, 92}, ++{225, 73, 95}, ++{234, 70, 99}, ++{243, 66, 103}, ++{253, 61, 107}, ++{255, 57, 111}, ++{255, 56, 111}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{167, 42, 71}, ++{177, 43, 77}, ++{189, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{158, 40, 66}, ++{167, 42, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{159, 41, 66}, ++{167, 43, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 102}, ++{160, 42, 67}, ++{168, 43, 71}, ++{178, 44, 77}, ++{190, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{230, 38, 102}, ++{160, 43, 67}, ++{169, 44, 72}, ++{179, 45, 77}, ++{191, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{231, 38, 102}, ++{161, 44, 68}, ++{170, 45, 72}, ++{180, 45, 78}, ++{192, 45, 84}, ++{204, 43, 90}, ++{217, 41, 96}, ++{230, 39, 101}, ++{231, 38, 102}, ++{163, 45, 68}, ++{171, 46, 73}, ++{181, 46, 78}, ++{193, 46, 84}, ++{205, 44, 90}, ++{218, 42, 96}, ++{230, 39, 101}, ++{232, 39, 102}, ++{164, 46, 69}, ++{172, 47, 73}, ++{182, 47, 79}, ++{194, 46, 84}, ++{206, 45, 90}, ++{218, 42, 96}, ++{231, 40, 102}, ++{233, 39, 102}, ++{165, 48, 70}, ++{173, 48, 74}, ++{183, 48, 79}, ++{195, 47, 85}, ++{207, 45, 91}, ++{219, 43, 96}, ++{232, 40, 102}, ++{234, 40, 103}, ++{167, 49, 70}, ++{175, 50, 75}, ++{185, 49, 80}, ++{196, 48, 85}, ++{208, 46, 91}, ++{220, 44, 97}, ++{233, 41, 102}, ++{235, 40, 103}, ++{169, 51, 71}, ++{176, 51, 75}, ++{186, 51, 80}, ++{197, 49, 86}, ++{209, 47, 92}, ++{222, 44, 97}, ++{234, 41, 103}, ++{236, 41, 103}, ++{171, 53, 72}, ++{178, 53, 76}, ++{188, 52, 81}, ++{199, 50, 86}, ++{211, 48, 92}, ++{223, 45, 98}, ++{235, 42, 103}, ++{237, 42, 104}, ++{173, 54, 73}, ++{180, 54, 77}, ++{190, 53, 82}, ++{201, 51, 87}, ++{212, 49, 93}, ++{224, 46, 98}, ++{237, 43, 103}, ++{238, 42, 104}, ++{175, 56, 74}, ++{182, 56, 78}, ++{192, 54, 83}, ++{202, 52, 88}, ++{214, 50, 93}, ++{226, 47, 98}, ++{238, 44, 104}, ++{239, 43, 104}, ++{177, 58, 75}, ++{184, 57, 79}, ++{193, 56, 83}, ++{204, 54, 88}, ++{215, 51, 94}, ++{227, 48, 99}, ++{239, 44, 104}, ++{241, 44, 105}, ++{180, 60, 76}, ++{186, 59, 80}, ++{196, 57, 84}, ++{206, 55, 89}, ++{217, 52, 94}, ++{229, 49, 99}, ++{241, 45, 105}, ++{242, 45, 105}, ++{182, 62, 77}, ++{189, 60, 81}, ++{198, 59, 85}, ++{208, 56, 90}, ++{219, 53, 95}, ++{230, 50, 100}, ++{242, 46, 105}, ++{244, 46, 106}, ++{184, 63, 78}, ++{191, 62, 82}, ++{200, 60, 86}, ++{210, 57, 91}, ++{221, 54, 96}, ++{232, 51, 101}, ++{244, 47, 106}, ++{245, 47, 106}, ++{187, 65, 79}, ++{193, 64, 83}, ++{202, 61, 87}, ++{212, 59, 91}, ++{223, 55, 96}, ++{234, 52, 101}, ++{246, 48, 106}, ++{247, 47, 107}, ++{190, 67, 80}, ++{196, 65, 83}, ++{204, 63, 88}, ++{214, 60, 92}, ++{225, 57, 97}, ++{236, 53, 102}, ++{247, 49, 107}, ++{249, 48, 107}, ++{192, 68, 81}, ++{199, 67, 84}, ++{207, 64, 88}, ++{216, 61, 93}, ++{227, 58, 98}, ++{238, 54, 102}, ++{249, 50, 107}, ++{251, 49, 108}, ++{195, 70, 83}, ++{201, 68, 86}, ++{209, 66, 89}, ++{219, 62, 94}, ++{229, 59, 98}, ++{240, 55, 103}, ++{251, 51, 108}, ++{252, 50, 108}, ++{198, 72, 84}, ++{204, 70, 87}, ++{212, 67, 90}, ++{221, 64, 94}, ++{231, 60, 99}, ++{242, 56, 103}, ++{253, 52, 108}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{214, 68, 91}, ++{223, 65, 95}, ++{233, 61, 100}, ++{244, 57, 104}, ++{255, 53, 109}, ++{255, 52, 109}, ++{204, 75, 86}, ++{209, 73, 89}, ++{217, 70, 92}, ++{226, 66, 96}, ++{236, 62, 100}, ++{246, 58, 105}, ++{255, 54, 109}, ++{255, 53, 110}, ++{207, 76, 87}, ++{212, 74, 90}, ++{220, 71, 93}, ++{228, 67, 97}, ++{238, 63, 101}, ++{248, 59, 105}, ++{255, 55, 110}, ++{255, 54, 110}, ++{209, 78, 88}, ++{215, 75, 91}, ++{222, 72, 94}, ++{231, 68, 98}, ++{240, 64, 102}, ++{251, 60, 106}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{218, 77, 92}, ++{225, 73, 95}, ++{234, 70, 99}, ++{243, 66, 103}, ++{253, 61, 107}, ++{255, 57, 111}, ++{255, 56, 111}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{158, 40, 66}, ++{167, 42, 71}, ++{177, 43, 77}, ++{189, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{158, 40, 66}, ++{167, 42, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 101}, ++{159, 41, 66}, ++{167, 43, 71}, ++{178, 43, 77}, ++{190, 43, 83}, ++{202, 42, 89}, ++{215, 40, 95}, ++{228, 38, 101}, ++{230, 37, 102}, ++{160, 42, 67}, ++{168, 43, 71}, ++{178, 44, 77}, ++{190, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{230, 38, 102}, ++{160, 43, 67}, ++{169, 44, 72}, ++{179, 45, 77}, ++{191, 44, 83}, ++{203, 43, 89}, ++{216, 41, 95}, ++{229, 38, 101}, ++{231, 38, 102}, ++{161, 44, 68}, ++{170, 45, 72}, ++{180, 45, 78}, ++{192, 45, 84}, ++{204, 43, 90}, ++{217, 41, 96}, ++{230, 39, 101}, ++{231, 38, 102}, ++{163, 45, 68}, ++{171, 46, 73}, ++{181, 46, 78}, ++{193, 46, 84}, ++{205, 44, 90}, ++{218, 42, 96}, ++{230, 39, 101}, ++{232, 39, 102}, ++{164, 46, 69}, ++{172, 47, 73}, ++{182, 47, 79}, ++{194, 46, 84}, ++{206, 45, 90}, ++{218, 42, 96}, ++{231, 40, 102}, ++{233, 39, 102}, ++{165, 48, 70}, ++{173, 48, 74}, ++{183, 48, 79}, ++{195, 47, 85}, ++{207, 45, 91}, ++{219, 43, 96}, ++{232, 40, 102}, ++{234, 40, 103}, ++{167, 49, 70}, ++{175, 50, 75}, ++{185, 49, 80}, ++{196, 48, 85}, ++{208, 46, 91}, ++{220, 44, 97}, ++{233, 41, 102}, ++{235, 40, 103}, ++{169, 51, 71}, ++{176, 51, 75}, ++{186, 51, 80}, ++{197, 49, 86}, ++{209, 47, 92}, ++{222, 44, 97}, ++{234, 41, 103}, ++{236, 41, 103}, ++{171, 53, 72}, ++{178, 53, 76}, ++{188, 52, 81}, ++{199, 50, 86}, ++{211, 48, 92}, ++{223, 45, 98}, ++{235, 42, 103}, ++{237, 42, 104}, ++{173, 54, 73}, ++{180, 54, 77}, ++{190, 53, 82}, ++{201, 51, 87}, ++{212, 49, 93}, ++{224, 46, 98}, ++{237, 43, 103}, ++{238, 42, 104}, ++{175, 56, 74}, ++{182, 56, 78}, ++{192, 54, 83}, ++{202, 52, 88}, ++{214, 50, 93}, ++{226, 47, 98}, ++{238, 44, 104}, ++{239, 43, 104}, ++{177, 58, 75}, ++{184, 57, 79}, ++{193, 56, 83}, ++{204, 54, 88}, ++{215, 51, 94}, ++{227, 48, 99}, ++{239, 44, 104}, ++{241, 44, 105}, ++{180, 60, 76}, ++{186, 59, 80}, ++{196, 57, 84}, ++{206, 55, 89}, ++{217, 52, 94}, ++{229, 49, 99}, ++{241, 45, 105}, ++{242, 45, 105}, ++{182, 62, 77}, ++{189, 60, 81}, ++{198, 59, 85}, ++{208, 56, 90}, ++{219, 53, 95}, ++{230, 50, 100}, ++{242, 46, 105}, ++{244, 46, 106}, ++{184, 63, 78}, ++{191, 62, 82}, ++{200, 60, 86}, ++{210, 57, 91}, ++{221, 54, 96}, ++{232, 51, 101}, ++{244, 47, 106}, ++{245, 47, 106}, ++{187, 65, 79}, ++{193, 64, 83}, ++{202, 61, 87}, ++{212, 59, 91}, ++{223, 55, 96}, ++{234, 52, 101}, ++{246, 48, 106}, ++{247, 47, 107}, ++{190, 67, 80}, ++{196, 65, 83}, ++{204, 63, 88}, ++{214, 60, 92}, ++{225, 57, 97}, ++{236, 53, 102}, ++{247, 49, 107}, ++{249, 48, 107}, ++{192, 68, 81}, ++{199, 67, 84}, ++{207, 64, 88}, ++{216, 61, 93}, ++{227, 58, 98}, ++{238, 54, 102}, ++{249, 50, 107}, ++{251, 49, 108}, ++{195, 70, 83}, ++{201, 68, 86}, ++{209, 66, 89}, ++{219, 62, 94}, ++{229, 59, 98}, ++{240, 55, 103}, ++{251, 51, 108}, ++{252, 50, 108}, ++{198, 72, 84}, ++{204, 70, 87}, ++{212, 67, 90}, ++{221, 64, 94}, ++{231, 60, 99}, ++{242, 56, 103}, ++{253, 52, 108}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{214, 68, 91}, ++{223, 65, 95}, ++{233, 61, 100}, ++{244, 57, 104}, ++{255, 53, 109}, ++{255, 52, 109}, ++{204, 75, 86}, ++{209, 73, 89}, ++{217, 70, 92}, ++{226, 66, 96}, ++{236, 62, 100}, ++{246, 58, 105}, ++{255, 54, 109}, ++{255, 53, 110}, ++{207, 76, 87}, ++{212, 74, 90}, ++{220, 71, 93}, ++{228, 67, 97}, ++{238, 63, 101}, ++{248, 59, 105}, ++{255, 55, 110}, ++{255, 54, 110}, ++{209, 78, 88}, ++{215, 75, 91}, ++{222, 72, 94}, ++{231, 68, 98}, ++{240, 64, 102}, ++{251, 60, 106}, ++{255, 56, 110}, ++{255, 55, 111}, ++{212, 79, 89}, ++{218, 77, 92}, ++{225, 73, 95}, ++{234, 70, 99}, ++{243, 66, 103}, ++{253, 61, 107}, ++{255, 57, 111}, ++{255, 56, 111}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{214, 80, 90}, ++{219, 77, 92}, ++{226, 74, 95}, ++{235, 70, 99}, ++{244, 66, 103}, ++{254, 62, 107}, ++{255, 57, 111}, ++{255, 57, 112}, ++{89, 101, 123}, ++{104, 95, 129}, ++{122, 88, 134}, ++{139, 81, 139}, ++{156, 75, 144}, ++{173, 68, 148}, ++{189, 62, 152}, ++{189, 62, 152}, ++{89, 101, 123}, ++{104, 95, 129}, ++{122, 88, 134}, ++{139, 82, 139}, ++{156, 75, 144}, ++{173, 69, 148}, ++{189, 62, 152}, ++{189, 62, 152}, ++{90, 102, 123}, ++{105, 95, 129}, ++{122, 89, 134}, ++{140, 82, 139}, ++{157, 75, 144}, ++{173, 69, 148}, ++{190, 63, 152}, ++{190, 63, 152}, ++{91, 102, 123}, ++{106, 96, 129}, ++{123, 89, 134}, ++{140, 82, 139}, ++{157, 75, 144}, ++{174, 69, 148}, ++{190, 63, 152}, ++{190, 63, 152}, ++{92, 103, 124}, ++{107, 96, 129}, ++{124, 89, 134}, ++{141, 82, 139}, ++{158, 76, 144}, ++{175, 69, 148}, ++{191, 63, 152}, ++{191, 63, 152}, ++{94, 104, 124}, ++{109, 97, 129}, ++{125, 90, 135}, ++{142, 83, 140}, ++{159, 76, 144}, ++{175, 70, 148}, ++{191, 63, 152}, ++{191, 63, 152}, ++{96, 105, 125}, ++{111, 98, 130}, ++{127, 91, 135}, ++{143, 83, 140}, ++{160, 77, 144}, ++{176, 70, 148}, ++{192, 64, 152}, ++{192, 64, 152}, ++{99, 105, 125}, ++{113, 99, 130}, ++{128, 91, 135}, ++{145, 84, 140}, ++{161, 77, 144}, ++{177, 71, 148}, ++{193, 64, 152}, ++{193, 64, 152}, ++{101, 106, 126}, ++{115, 99, 130}, ++{130, 92, 135}, ++{146, 85, 140}, ++{163, 78, 144}, ++{179, 71, 148}, ++{194, 65, 152}, ++{194, 65, 152}, ++{104, 107, 126}, ++{117, 100, 131}, ++{132, 93, 136}, ++{148, 85, 140}, ++{164, 78, 144}, ++{180, 72, 148}, ++{195, 65, 152}, ++{195, 65, 152}, ++{107, 108, 127}, ++{120, 101, 131}, ++{135, 94, 136}, ++{150, 86, 140}, ++{166, 79, 145}, ++{181, 72, 149}, ++{197, 66, 152}, ++{197, 66, 152}, ++{110, 109, 128}, ++{122, 102, 132}, ++{137, 95, 136}, ++{152, 87, 141}, ++{168, 80, 145}, ++{183, 73, 149}, ++{198, 66, 152}, ++{198, 66, 152}, ++{114, 110, 128}, ++{125, 103, 132}, ++{139, 95, 136}, ++{154, 88, 141}, ++{169, 81, 145}, ++{185, 74, 149}, ++{200, 67, 152}, ++{200, 67, 152}, ++{117, 111, 129}, ++{128, 104, 133}, ++{142, 96, 137}, ++{157, 89, 141}, ++{171, 81, 145}, ++{186, 74, 149}, ++{201, 68, 152}, ++{201, 68, 152}, ++{120, 112, 129}, ++{131, 105, 133}, ++{145, 97, 137}, ++{159, 90, 141}, ++{174, 82, 145}, ++{188, 75, 149}, ++{203, 68, 152}, ++{203, 68, 152}, ++{124, 112, 130}, ++{135, 106, 133}, ++{147, 98, 137}, ++{161, 90, 141}, ++{176, 83, 145}, ++{190, 76, 149}, ++{205, 69, 153}, ++{205, 69, 153}, ++{128, 113, 131}, ++{138, 106, 134}, ++{150, 99, 138}, ++{164, 91, 142}, ++{178, 84, 145}, ++{192, 77, 149}, ++{207, 70, 153}, ++{207, 70, 153}, ++{131, 114, 131}, ++{141, 107, 134}, ++{153, 100, 138}, ++{167, 92, 142}, ++{180, 85, 146}, ++{195, 77, 149}, ++{209, 71, 153}, ++{209, 71, 153}, ++{135, 115, 132}, ++{144, 108, 135}, ++{156, 101, 138}, ++{169, 93, 142}, ++{183, 85, 146}, ++{197, 78, 149}, ++{211, 71, 153}, ++{211, 71, 153}, ++{139, 115, 132}, ++{148, 109, 135}, ++{159, 101, 139}, ++{172, 94, 142}, ++{185, 86, 146}, ++{199, 79, 149}, ++{213, 72, 153}, ++{213, 72, 153}, ++{142, 116, 133}, ++{151, 109, 136}, ++{162, 102, 139}, ++{175, 95, 143}, ++{188, 87, 146}, ++{201, 80, 150}, ++{215, 73, 153}, ++{215, 73, 153}, ++{146, 116, 134}, ++{155, 110, 136}, ++{166, 103, 139}, ++{178, 95, 143}, ++{191, 88, 146}, ++{204, 81, 150}, ++{217, 74, 153}, ++{217, 74, 153}, ++{150, 117, 134}, ++{158, 111, 137}, ++{169, 104, 140}, ++{181, 96, 143}, ++{193, 89, 146}, ++{206, 82, 150}, ++{219, 75, 153}, ++{220, 75, 153}, ++{154, 117, 135}, ++{162, 111, 137}, ++{172, 104, 140}, ++{184, 97, 143}, ++{196, 90, 147}, ++{209, 82, 150}, ++{222, 75, 153}, ++{222, 75, 153}, ++{158, 118, 135}, ++{166, 112, 137}, ++{176, 105, 140}, ++{187, 98, 144}, ++{199, 90, 147}, ++{211, 83, 150}, ++{224, 76, 153}, ++{224, 76, 153}, ++{162, 118, 136}, ++{169, 113, 138}, ++{179, 106, 141}, ++{190, 99, 144}, ++{202, 91, 147}, ++{214, 84, 150}, ++{227, 77, 153}, ++{227, 77, 153}, ++{165, 119, 136}, ++{173, 113, 138}, ++{182, 106, 141}, ++{193, 99, 144}, ++{205, 92, 147}, ++{217, 85, 150}, ++{229, 78, 154}, ++{229, 78, 154}, ++{169, 119, 137}, ++{176, 114, 139}, ++{186, 107, 141}, ++{196, 100, 144}, ++{208, 93, 148}, ++{220, 86, 151}, ++{232, 79, 154}, ++{232, 79, 154}, ++{171, 119, 137}, ++{178, 114, 139}, ++{187, 107, 142}, ++{198, 100, 145}, ++{209, 93, 148}, ++{221, 86, 151}, ++{233, 79, 154}, ++{233, 79, 154}, ++{171, 119, 137}, ++{178, 114, 139}, ++{187, 107, 142}, ++{198, 100, 145}, ++{209, 93, 148}, ++{221, 86, 151}, ++{233, 79, 154}, ++{233, 79, 154}, ++{171, 119, 137}, ++{178, 114, 139}, ++{187, 107, 142}, ++{198, 100, 145}, ++{209, 93, 148}, ++{221, 86, 151}, ++{233, 79, 154}, ++{233, 79, 154}, ++{171, 119, 137}, ++{178, 114, 139}, ++{187, 107, 142}, ++{198, 100, 145}, ++{209, 93, 148}, ++{221, 86, 151}, ++{233, 79, 154}, ++{233, 79, 154}, ++{90, 100, 122}, ++{105, 94, 127}, ++{122, 88, 133}, ++{140, 81, 138}, ++{157, 75, 143}, ++{173, 68, 147}, ++{190, 62, 151}, ++{190, 62, 151}, ++{90, 101, 122}, ++{105, 95, 127}, ++{122, 88, 133}, ++{140, 81, 138}, ++{157, 75, 143}, ++{174, 68, 147}, ++{190, 62, 151}, ++{190, 62, 151}, ++{91, 101, 122}, ++{106, 95, 128}, ++{123, 88, 133}, ++{140, 81, 138}, ++{157, 75, 143}, ++{174, 68, 147}, ++{190, 62, 151}, ++{190, 62, 151}, ++{92, 101, 122}, ++{107, 95, 128}, ++{124, 88, 133}, ++{141, 82, 138}, ++{158, 75, 143}, ++{174, 69, 147}, ++{191, 63, 151}, ++{191, 63, 151}, ++{93, 102, 123}, ++{108, 96, 128}, ++{125, 89, 133}, ++{142, 82, 139}, ++{159, 75, 143}, ++{175, 69, 147}, ++{191, 63, 151}, ++{191, 63, 151}, ++{95, 103, 123}, ++{110, 97, 128}, ++{126, 90, 134}, ++{143, 83, 139}, ++{159, 76, 143}, ++{176, 69, 148}, ++{192, 63, 151}, ++{192, 63, 151}, ++{97, 104, 124}, ++{111, 97, 129}, ++{128, 90, 134}, ++{144, 83, 139}, ++{161, 76, 143}, ++{177, 70, 148}, ++{193, 64, 151}, ++{193, 64, 151}, ++{100, 105, 124}, ++{113, 98, 129}, ++{129, 91, 134}, ++{145, 84, 139}, ++{162, 77, 143}, ++{178, 70, 148}, ++{194, 64, 151}, ++{194, 64, 151}, ++{102, 106, 125}, ++{116, 99, 129}, ++{131, 92, 134}, ++{147, 84, 139}, ++{163, 77, 144}, ++{179, 71, 148}, ++{195, 64, 152}, ++{195, 64, 152}, ++{105, 107, 125}, ++{118, 100, 130}, ++{133, 92, 135}, ++{149, 85, 139}, ++{165, 78, 144}, ++{180, 71, 148}, ++{196, 65, 152}, ++{196, 65, 152}, ++{108, 108, 126}, ++{121, 101, 130}, ++{135, 93, 135}, ++{151, 86, 139}, ++{166, 79, 144}, ++{182, 72, 148}, ++{197, 66, 152}, ++{197, 66, 152}, ++{111, 109, 127}, ++{123, 102, 131}, ++{138, 94, 135}, ++{153, 87, 140}, ++{168, 80, 144}, ++{183, 73, 148}, ++{199, 66, 152}, ++{199, 66, 152}, ++{114, 109, 127}, ++{126, 103, 131}, ++{140, 95, 136}, ++{155, 88, 140}, ++{170, 80, 144}, ++{185, 73, 148}, ++{200, 67, 152}, ++{200, 67, 152}, ++{118, 110, 128}, ++{129, 103, 132}, ++{143, 96, 136}, ++{157, 88, 140}, ++{172, 81, 144}, ++{187, 74, 148}, ++{202, 68, 152}, ++{202, 68, 152}, ++{121, 111, 128}, ++{132, 104, 132}, ++{145, 97, 136}, ++{159, 89, 140}, ++{174, 82, 144}, ++{189, 75, 148}, ++{203, 68, 152}, ++{203, 68, 152}, ++{125, 112, 129}, ++{135, 105, 133}, ++{148, 98, 137}, ++{162, 90, 141}, ++{176, 83, 145}, ++{191, 76, 148}, ++{205, 69, 152}, ++{205, 69, 152}, ++{128, 113, 130}, ++{138, 106, 133}, ++{151, 98, 137}, ++{164, 91, 141}, ++{179, 84, 145}, ++{193, 76, 148}, ++{207, 70, 152}, ++{207, 70, 152}, ++{132, 113, 130}, ++{142, 107, 134}, ++{154, 99, 137}, ++{167, 92, 141}, ++{181, 84, 145}, ++{195, 77, 149}, ++{209, 70, 152}, ++{209, 70, 152}, ++{136, 114, 131}, ++{145, 108, 134}, ++{157, 100, 138}, ++{170, 93, 141}, ++{183, 85, 145}, ++{197, 78, 149}, ++{211, 71, 152}, ++{211, 71, 152}, ++{139, 115, 132}, ++{148, 108, 134}, ++{160, 101, 138}, ++{173, 93, 142}, ++{186, 86, 145}, ++{199, 79, 149}, ++{213, 72, 152}, ++{213, 72, 152}, ++{143, 115, 132}, ++{152, 109, 135}, ++{163, 102, 138}, ++{175, 94, 142}, ++{188, 87, 145}, ++{202, 80, 149}, ++{215, 73, 152}, ++{215, 73, 152}, ++{147, 116, 133}, ++{155, 110, 135}, ++{166, 103, 139}, ++{178, 95, 142}, ++{191, 88, 146}, ++{204, 81, 149}, ++{218, 74, 152}, ++{218, 74, 152}, ++{151, 116, 133}, ++{159, 110, 136}, ++{169, 103, 139}, ++{181, 96, 142}, ++{194, 89, 146}, ++{207, 81, 149}, ++{220, 74, 153}, ++{220, 74, 153}, ++{154, 117, 134}, ++{162, 111, 136}, ++{173, 104, 139}, ++{184, 97, 143}, ++{197, 89, 146}, ++{209, 82, 149}, ++{222, 75, 153}, ++{222, 75, 153}, ++{158, 117, 134}, ++{166, 112, 137}, ++{176, 105, 140}, ++{187, 97, 143}, ++{199, 90, 146}, ++{212, 83, 150}, ++{225, 76, 153}, ++{225, 76, 153}, ++{162, 118, 135}, ++{170, 112, 137}, ++{179, 105, 140}, ++{190, 98, 143}, ++{202, 91, 147}, ++{214, 84, 150}, ++{227, 77, 153}, ++{227, 77, 153}, ++{166, 118, 135}, ++{173, 113, 138}, ++{183, 106, 141}, ++{194, 99, 144}, ++{205, 92, 147}, ++{217, 85, 150}, ++{230, 78, 153}, ++{230, 78, 153}, ++{170, 119, 136}, ++{177, 113, 138}, ++{186, 107, 141}, ++{197, 100, 144}, ++{208, 93, 147}, ++{220, 85, 150}, ++{232, 78, 153}, ++{232, 78, 153}, ++{172, 119, 136}, ++{179, 114, 138}, ++{188, 107, 141}, ++{198, 100, 144}, ++{210, 93, 147}, ++{221, 86, 150}, ++{233, 79, 153}, ++{233, 79, 153}, ++{172, 119, 136}, ++{179, 114, 138}, ++{188, 107, 141}, ++{198, 100, 144}, ++{210, 93, 147}, ++{221, 86, 150}, ++{233, 79, 153}, ++{233, 79, 153}, ++{172, 119, 136}, ++{179, 114, 138}, ++{188, 107, 141}, ++{198, 100, 144}, ++{210, 93, 147}, ++{221, 86, 150}, ++{233, 79, 153}, ++{233, 79, 153}, ++{172, 119, 136}, ++{179, 114, 138}, ++{188, 107, 141}, ++{198, 100, 144}, ++{210, 93, 147}, ++{221, 86, 150}, ++{233, 79, 153}, ++{233, 79, 153}, ++{91, 99, 120}, ++{107, 93, 126}, ++{124, 87, 131}, ++{141, 81, 137}, ++{158, 74, 142}, ++{174, 68, 146}, ++{190, 62, 150}, ++{190, 62, 150}, ++{92, 99, 120}, ++{107, 94, 126}, ++{124, 87, 131}, ++{141, 81, 137}, ++{158, 74, 142}, ++{174, 68, 146}, ++{191, 62, 150}, ++{191, 62, 150}, ++{92, 100, 120}, ++{107, 94, 126}, ++{124, 87, 132}, ++{141, 81, 137}, ++{158, 74, 142}, ++{175, 68, 146}, ++{191, 62, 150}, ++{191, 62, 150}, ++{94, 100, 120}, ++{108, 94, 126}, ++{125, 88, 132}, ++{142, 81, 137}, ++{159, 75, 142}, ++{175, 68, 146}, ++{191, 62, 150}, ++{191, 62, 150}, ++{95, 101, 121}, ++{110, 95, 126}, ++{126, 88, 132}, ++{143, 82, 137}, ++{160, 75, 142}, ++{176, 69, 146}, ++{192, 63, 150}, ++{192, 63, 150}, ++{97, 102, 121}, ++{111, 96, 127}, ++{127, 89, 132}, ++{144, 82, 137}, ++{160, 75, 142}, ++{177, 69, 146}, ++{193, 63, 150}, ++{193, 63, 150}, ++{99, 103, 122}, ++{113, 96, 127}, ++{129, 89, 132}, ++{145, 83, 137}, ++{162, 76, 142}, ++{178, 69, 146}, ++{193, 63, 150}, ++{193, 63, 150}, ++{101, 104, 122}, ++{115, 97, 127}, ++{130, 90, 133}, ++{147, 83, 138}, ++{163, 76, 142}, ++{179, 70, 146}, ++{194, 64, 150}, ++{194, 64, 150}, ++{104, 104, 123}, ++{117, 98, 128}, ++{132, 91, 133}, ++{148, 84, 138}, ++{164, 77, 142}, ++{180, 70, 146}, ++{195, 64, 150}, ++{195, 64, 150}, ++{107, 105, 124}, ++{119, 99, 128}, ++{134, 92, 133}, ++{150, 85, 138}, ++{166, 78, 142}, ++{181, 71, 147}, ++{197, 65, 150}, ++{197, 65, 150}, ++{110, 106, 124}, ++{122, 100, 129}, ++{136, 93, 133}, ++{152, 85, 138}, ++{167, 78, 143}, ++{183, 72, 147}, ++{198, 65, 151}, ++{198, 65, 151}, ++{113, 107, 125}, ++{124, 101, 129}, ++{139, 93, 134}, ++{154, 86, 138}, ++{169, 79, 143}, ++{184, 72, 147}, ++{199, 66, 151}, ++{199, 66, 151}, ++{116, 108, 126}, ++{127, 102, 130}, ++{141, 94, 134}, ++{156, 87, 139}, ++{171, 80, 143}, ++{186, 73, 147}, ++{201, 67, 151}, ++{201, 67, 151}, ++{119, 109, 126}, ++{130, 103, 130}, ++{144, 95, 134}, ++{158, 88, 139}, ++{173, 81, 143}, ++{188, 74, 147}, ++{202, 67, 151}, ++{202, 67, 151}, ++{122, 110, 127}, ++{133, 104, 131}, ++{146, 96, 135}, ++{160, 89, 139}, ++{175, 81, 143}, ++{190, 75, 147}, ++{204, 68, 151}, ++{204, 68, 151}, ++{126, 111, 128}, ++{136, 104, 131}, ++{149, 97, 135}, ++{163, 90, 139}, ++{177, 82, 143}, ++{192, 75, 147}, ++{206, 69, 151}, ++{206, 69, 151}, ++{129, 112, 128}, ++{139, 105, 132}, ++{152, 98, 136}, ++{165, 90, 140}, ++{179, 83, 144}, ++{194, 76, 147}, ++{208, 69, 151}, ++{208, 69, 151}, ++{133, 112, 129}, ++{143, 106, 132}, ++{155, 99, 136}, ++{168, 91, 140}, ++{182, 84, 144}, ++{196, 77, 147}, ++{210, 70, 151}, ++{210, 70, 151}, ++{137, 113, 130}, ++{146, 107, 133}, ++{158, 100, 136}, ++{171, 92, 140}, ++{184, 85, 144}, ++{198, 78, 148}, ++{212, 71, 151}, ++{212, 71, 151}, ++{140, 114, 130}, ++{149, 108, 133}, ++{161, 100, 137}, ++{173, 93, 140}, ++{187, 86, 144}, ++{200, 79, 148}, ++{214, 72, 151}, ++{214, 72, 151}, ++{144, 114, 131}, ++{153, 108, 134}, ++{164, 101, 137}, ++{176, 94, 141}, ++{189, 86, 144}, ++{203, 79, 148}, ++{216, 73, 151}, ++{216, 73, 151}, ++{148, 115, 131}, ++{156, 109, 134}, ++{167, 102, 138}, ++{179, 95, 141}, ++{192, 87, 145}, ++{205, 80, 148}, ++{218, 73, 152}, ++{218, 73, 152}, ++{152, 116, 132}, ++{160, 110, 135}, ++{170, 103, 138}, ++{182, 95, 141}, ++{195, 88, 145}, ++{207, 81, 148}, ++{220, 74, 152}, ++{220, 74, 152}, ++{155, 116, 133}, ++{163, 110, 135}, ++{174, 104, 138}, ++{185, 96, 142}, ++{197, 89, 145}, ++{210, 82, 148}, ++{223, 75, 152}, ++{223, 75, 152}, ++{159, 117, 133}, ++{167, 111, 136}, ++{177, 104, 139}, ++{188, 97, 142}, ++{200, 90, 145}, ++{213, 83, 149}, ++{225, 76, 152}, ++{225, 76, 152}, ++{163, 117, 134}, ++{170, 112, 136}, ++{180, 105, 139}, ++{191, 98, 142}, ++{203, 91, 146}, ++{215, 83, 149}, ++{228, 77, 152}, ++{228, 77, 152}, ++{167, 118, 134}, ++{174, 112, 137}, ++{184, 106, 139}, ++{194, 99, 143}, ++{206, 91, 146}, ++{218, 84, 149}, ++{230, 77, 152}, ++{230, 77, 152}, ++{171, 118, 135}, ++{178, 113, 137}, ++{187, 106, 140}, ++{197, 99, 143}, ++{209, 92, 146}, ++{221, 85, 149}, ++{233, 78, 152}, ++{233, 78, 152}, ++{173, 118, 135}, ++{180, 113, 137}, ++{189, 107, 140}, ++{199, 100, 143}, ++{210, 92, 146}, ++{222, 85, 149}, ++{234, 79, 152}, ++{234, 79, 152}, ++{173, 118, 135}, ++{180, 113, 137}, ++{189, 107, 140}, ++{199, 100, 143}, ++{210, 92, 146}, ++{222, 85, 149}, ++{234, 79, 152}, ++{234, 79, 152}, ++{173, 118, 135}, ++{180, 113, 137}, ++{189, 107, 140}, ++{199, 100, 143}, ++{210, 92, 146}, ++{222, 85, 149}, ++{234, 79, 152}, ++{234, 79, 152}, ++{173, 118, 135}, ++{180, 113, 137}, ++{189, 107, 140}, ++{199, 100, 143}, ++{210, 92, 146}, ++{222, 85, 149}, ++{234, 79, 152}, ++{234, 79, 152}, ++{93, 97, 117}, ++{108, 92, 123}, ++{125, 86, 129}, ++{142, 80, 135}, ++{159, 74, 140}, ++{175, 67, 145}, ++{191, 61, 149}, ++{191, 61, 149}, ++{94, 97, 117}, ++{109, 92, 123}, ++{125, 86, 129}, ++{142, 80, 135}, ++{159, 74, 140}, ++{175, 67, 145}, ++{191, 61, 149}, ++{191, 61, 149}, ++{94, 98, 118}, ++{109, 93, 124}, ++{126, 86, 130}, ++{143, 80, 135}, ++{159, 74, 140}, ++{176, 68, 145}, ++{192, 62, 149}, ++{192, 62, 149}, ++{96, 98, 118}, ++{110, 93, 124}, ++{127, 87, 130}, ++{143, 80, 135}, ++{160, 74, 140}, ++{176, 68, 145}, ++{192, 62, 149}, ++{192, 62, 149}, ++{97, 99, 118}, ++{111, 94, 124}, ++{128, 87, 130}, ++{144, 81, 135}, ++{161, 74, 140}, ++{177, 68, 145}, ++{193, 62, 149}, ++{193, 62, 149}, ++{99, 100, 119}, ++{113, 94, 124}, ++{129, 88, 130}, ++{145, 81, 135}, ++{162, 75, 140}, ++{178, 69, 145}, ++{193, 62, 149}, ++{193, 62, 149}, ++{101, 101, 120}, ++{114, 95, 125}, ++{130, 89, 130}, ++{146, 82, 136}, ++{163, 75, 140}, ++{179, 69, 145}, ++{194, 63, 149}, ++{194, 63, 149}, ++{103, 102, 120}, ++{116, 96, 125}, ++{132, 89, 131}, ++{148, 82, 136}, ++{164, 76, 141}, ++{180, 69, 145}, ++{195, 63, 149}, ++{195, 63, 149}, ++{106, 103, 121}, ++{119, 97, 126}, ++{134, 90, 131}, ++{149, 83, 136}, ++{165, 76, 141}, ++{181, 70, 145}, ++{196, 64, 149}, ++{196, 64, 149}, ++{108, 104, 122}, ++{121, 98, 126}, ++{136, 91, 131}, ++{151, 84, 136}, ++{167, 77, 141}, ++{182, 71, 145}, ++{198, 64, 149}, ++{198, 64, 149}, ++{111, 105, 122}, ++{123, 99, 127}, ++{138, 92, 132}, ++{153, 85, 136}, ++{168, 78, 141}, ++{184, 71, 145}, ++{199, 65, 149}, ++{199, 65, 149}, ++{114, 106, 123}, ++{126, 100, 127}, ++{140, 93, 132}, ++{155, 85, 137}, ++{170, 79, 141}, ++{185, 72, 145}, ++{200, 65, 149}, ++{200, 65, 149}, ++{117, 107, 124}, ++{129, 101, 128}, ++{142, 93, 132}, ++{157, 86, 137}, ++{172, 79, 141}, ++{187, 73, 145}, ++{202, 66, 149}, ++{202, 66, 149}, ++{121, 108, 124}, ++{132, 102, 128}, ++{145, 94, 133}, ++{159, 87, 137}, ++{174, 80, 142}, ++{189, 73, 146}, ++{203, 67, 149}, ++{203, 67, 149}, ++{124, 109, 125}, ++{135, 102, 129}, ++{147, 95, 133}, ++{161, 88, 137}, ++{176, 81, 142}, ++{191, 74, 146}, ++{205, 68, 150}, ++{205, 68, 150}, ++{127, 110, 126}, ++{138, 103, 129}, ++{150, 96, 134}, ++{164, 89, 138}, ++{178, 82, 142}, ++{192, 75, 146}, ++{207, 68, 150}, ++{207, 68, 150}, ++{131, 111, 127}, ++{141, 104, 130}, ++{153, 97, 134}, ++{166, 90, 138}, ++{180, 83, 142}, ++{194, 76, 146}, ++{209, 69, 150}, ++{209, 69, 150}, ++{134, 111, 127}, ++{144, 105, 131}, ++{156, 98, 134}, ++{169, 91, 138}, ++{183, 83, 142}, ++{197, 76, 146}, ++{211, 70, 150}, ++{211, 70, 150}, ++{138, 112, 128}, ++{147, 106, 131}, ++{159, 99, 135}, ++{172, 91, 139}, ++{185, 84, 143}, ++{199, 77, 146}, ++{213, 71, 150}, ++{213, 71, 150}, ++{142, 113, 129}, ++{151, 107, 132}, ++{162, 100, 135}, ++{174, 92, 139}, ++{188, 85, 143}, ++{201, 78, 147}, ++{215, 71, 150}, ++{215, 71, 150}, ++{145, 113, 129}, ++{154, 107, 132}, ++{165, 100, 136}, ++{177, 93, 139}, ++{190, 86, 143}, ++{203, 79, 147}, ++{217, 72, 150}, ++{217, 72, 150}, ++{149, 114, 130}, ++{157, 108, 133}, ++{168, 101, 136}, ++{180, 94, 140}, ++{193, 87, 143}, ++{206, 80, 147}, ++{219, 73, 150}, ++{219, 73, 150}, ++{153, 115, 131}, ++{161, 109, 133}, ++{171, 102, 137}, ++{183, 95, 140}, ++{195, 88, 144}, ++{208, 81, 147}, ++{221, 74, 151}, ++{221, 74, 151}, ++{156, 115, 131}, ++{164, 110, 134}, ++{175, 103, 137}, ++{186, 96, 140}, ++{198, 88, 144}, ++{211, 81, 147}, ++{224, 75, 151}, ++{224, 75, 151}, ++{160, 116, 132}, ++{168, 110, 134}, ++{178, 104, 137}, ++{189, 96, 141}, ++{201, 89, 144}, ++{213, 82, 148}, ++{226, 75, 151}, ++{226, 75, 151}, ++{164, 116, 132}, ++{172, 111, 135}, ++{181, 104, 138}, ++{192, 97, 141}, ++{204, 90, 144}, ++{216, 83, 148}, ++{228, 76, 151}, ++{228, 76, 151}, ++{168, 117, 133}, ++{175, 111, 135}, ++{184, 105, 138}, ++{195, 98, 141}, ++{207, 91, 145}, ++{219, 84, 148}, ++{231, 77, 151}, ++{231, 77, 151}, ++{172, 117, 134}, ++{179, 112, 136}, ++{188, 106, 139}, ++{198, 99, 142}, ++{210, 92, 145}, ++{221, 85, 148}, ++{233, 78, 151}, ++{233, 78, 151}, ++{174, 118, 134}, ++{181, 112, 136}, ++{190, 106, 139}, ++{200, 99, 142}, ++{211, 92, 145}, ++{223, 85, 148}, ++{235, 78, 151}, ++{235, 78, 151}, ++{174, 118, 134}, ++{181, 112, 136}, ++{190, 106, 139}, ++{200, 99, 142}, ++{211, 92, 145}, ++{223, 85, 148}, ++{235, 78, 151}, ++{235, 78, 151}, ++{174, 118, 134}, ++{181, 112, 136}, ++{190, 106, 139}, ++{200, 99, 142}, ++{211, 92, 145}, ++{223, 85, 148}, ++{235, 78, 151}, ++{235, 78, 151}, ++{174, 118, 134}, ++{181, 112, 136}, ++{190, 106, 139}, ++{200, 99, 142}, ++{211, 92, 145}, ++{223, 85, 148}, ++{235, 78, 151}, ++{235, 78, 151}, ++{96, 95, 115}, ++{110, 91, 121}, ++{127, 85, 127}, ++{144, 79, 133}, ++{160, 73, 138}, ++{177, 67, 143}, ++{192, 61, 147}, ++{192, 61, 147}, ++{96, 96, 115}, ++{111, 91, 121}, ++{127, 85, 127}, ++{144, 79, 133}, ++{160, 73, 138}, ++{177, 67, 143}, ++{193, 61, 147}, ++{193, 61, 147}, ++{97, 96, 115}, ++{111, 91, 121}, ++{127, 85, 127}, ++{144, 79, 133}, ++{161, 73, 138}, ++{177, 67, 143}, ++{193, 61, 147}, ++{193, 61, 147}, ++{98, 97, 116}, ++{112, 92, 122}, ++{128, 86, 128}, ++{145, 80, 133}, ++{161, 73, 138}, ++{177, 67, 143}, ++{193, 61, 147}, ++{193, 61, 147}, ++{99, 97, 116}, ++{113, 92, 122}, ++{129, 86, 128}, ++{146, 80, 133}, ++{162, 74, 138}, ++{178, 68, 143}, ++{194, 62, 147}, ++{194, 62, 147}, ++{101, 98, 117}, ++{115, 93, 122}, ++{130, 87, 128}, ++{147, 80, 133}, ++{163, 74, 138}, ++{179, 68, 143}, ++{195, 62, 147}, ++{195, 62, 147}, ++{103, 99, 117}, ++{116, 94, 123}, ++{132, 87, 128}, ++{148, 81, 134}, ++{164, 75, 139}, ++{180, 68, 143}, ++{195, 62, 147}, ++{195, 62, 147}, ++{105, 100, 118}, ++{118, 95, 123}, ++{133, 88, 129}, ++{149, 82, 134}, ++{165, 75, 139}, ++{181, 69, 143}, ++{196, 63, 147}, ++{196, 63, 147}, ++{108, 101, 119}, ++{120, 96, 124}, ++{135, 89, 129}, ++{151, 82, 134}, ++{166, 76, 139}, ++{182, 69, 143}, ++{197, 63, 148}, ++{197, 63, 148}, ++{110, 102, 119}, ++{123, 96, 124}, ++{137, 90, 129}, ++{152, 83, 134}, ++{168, 76, 139}, ++{183, 70, 143}, ++{199, 64, 148}, ++{199, 64, 148}, ++{113, 103, 120}, ++{125, 97, 125}, ++{139, 91, 130}, ++{154, 84, 135}, ++{170, 77, 139}, ++{185, 71, 144}, ++{200, 64, 148}, ++{200, 64, 148}, ++{116, 104, 121}, ++{128, 98, 125}, ++{141, 92, 130}, ++{156, 85, 135}, ++{171, 78, 139}, ++{186, 71, 144}, ++{201, 65, 148}, ++{201, 65, 148}, ++{119, 106, 122}, ++{130, 99, 126}, ++{144, 92, 130}, ++{158, 85, 135}, ++{173, 79, 140}, ++{188, 72, 144}, ++{203, 66, 148}, ++{203, 66, 148}, ++{122, 106, 122}, ++{133, 100, 126}, ++{146, 93, 131}, ++{160, 86, 135}, ++{175, 79, 140}, ++{190, 73, 144}, ++{204, 66, 148}, ++{204, 66, 148}, ++{126, 107, 123}, ++{136, 101, 127}, ++{149, 94, 131}, ++{163, 87, 136}, ++{177, 80, 140}, ++{192, 74, 144}, ++{206, 67, 148}, ++{206, 67, 148}, ++{129, 108, 124}, ++{139, 102, 128}, ++{152, 95, 132}, ++{165, 88, 136}, ++{179, 81, 140}, ++{194, 74, 144}, ++{208, 68, 148}, ++{208, 68, 148}, ++{132, 109, 125}, ++{142, 103, 128}, ++{154, 96, 132}, ++{168, 89, 136}, ++{181, 82, 141}, ++{196, 75, 145}, ++{210, 69, 148}, ++{210, 69, 148}, ++{136, 110, 125}, ++{145, 104, 129}, ++{157, 97, 133}, ++{170, 90, 137}, ++{184, 83, 141}, ++{198, 76, 145}, ++{212, 69, 148}, ++{212, 69, 148}, ++{139, 111, 126}, ++{149, 105, 129}, ++{160, 98, 133}, ++{173, 91, 137}, ++{186, 84, 141}, ++{200, 77, 145}, ++{214, 70, 149}, ++{214, 70, 149}, ++{143, 112, 127}, ++{152, 106, 130}, ++{163, 99, 134}, ++{176, 92, 137}, ++{189, 84, 141}, ++{202, 78, 145}, ++{216, 71, 149}, ++{216, 71, 149}, ++{147, 112, 128}, ++{155, 106, 130}, ++{166, 100, 134}, ++{178, 92, 138}, ++{191, 85, 142}, ++{204, 78, 145}, ++{218, 72, 149}, ++{218, 72, 149}, ++{150, 113, 128}, ++{159, 107, 131}, ++{169, 100, 134}, ++{181, 93, 138}, ++{194, 86, 142}, ++{207, 79, 146}, ++{220, 72, 149}, ++{220, 72, 149}, ++{154, 114, 129}, ++{162, 108, 132}, ++{172, 101, 135}, ++{184, 94, 139}, ++{196, 87, 142}, ++{209, 80, 146}, ++{222, 73, 149}, ++{222, 73, 149}, ++{158, 114, 130}, ++{166, 109, 132}, ++{176, 102, 135}, ++{187, 95, 139}, ++{199, 88, 142}, ++{212, 81, 146}, ++{224, 74, 149}, ++{224, 74, 149}, ++{162, 115, 130}, ++{169, 109, 133}, ++{179, 103, 136}, ++{190, 96, 139}, ++{202, 89, 143}, ++{214, 82, 146}, ++{227, 75, 150}, ++{227, 75, 150}, ++{165, 115, 131}, ++{173, 110, 133}, ++{182, 103, 136}, ++{193, 97, 140}, ++{205, 89, 143}, ++{217, 82, 146}, ++{229, 76, 150}, ++{229, 76, 150}, ++{169, 116, 132}, ++{176, 111, 134}, ++{186, 104, 137}, ++{196, 97, 140}, ++{208, 90, 143}, ++{219, 83, 147}, ++{232, 77, 150}, ++{232, 77, 150}, ++{173, 116, 132}, ++{180, 111, 134}, ++{189, 105, 137}, ++{199, 98, 140}, ++{210, 91, 144}, ++{222, 84, 147}, ++{234, 77, 150}, ++{234, 77, 150}, ++{175, 117, 132}, ++{182, 112, 135}, ++{191, 105, 137}, ++{201, 98, 141}, ++{212, 91, 144}, ++{224, 84, 147}, ++{235, 78, 150}, ++{235, 78, 150}, ++{175, 117, 132}, ++{182, 112, 135}, ++{191, 105, 137}, ++{201, 98, 141}, ++{212, 91, 144}, ++{224, 84, 147}, ++{235, 78, 150}, ++{235, 78, 150}, ++{175, 117, 132}, ++{182, 112, 135}, ++{191, 105, 137}, ++{201, 98, 141}, ++{212, 91, 144}, ++{224, 84, 147}, ++{235, 78, 150}, ++{235, 78, 150}, ++{175, 117, 132}, ++{182, 112, 135}, ++{191, 105, 137}, ++{201, 98, 141}, ++{212, 91, 144}, ++{224, 84, 147}, ++{235, 78, 150}, ++{235, 78, 150}, ++{98, 93, 113}, ++{112, 89, 119}, ++{129, 84, 125}, ++{145, 78, 131}, ++{162, 72, 136}, ++{178, 66, 141}, ++{194, 60, 145}, ++{194, 60, 145}, ++{98, 94, 113}, ++{113, 89, 119}, ++{129, 84, 125}, ++{145, 78, 131}, ++{162, 72, 136}, ++{178, 66, 141}, ++{194, 60, 145}, ++{194, 60, 145}, ++{99, 94, 113}, ++{113, 90, 119}, ++{129, 84, 125}, ++{146, 78, 131}, ++{162, 72, 136}, ++{178, 66, 141}, ++{194, 61, 145}, ++{194, 61, 145}, ++{100, 95, 113}, ++{114, 90, 119}, ++{130, 85, 125}, ++{146, 79, 131}, ++{163, 73, 136}, ++{179, 67, 141}, ++{194, 61, 146}, ++{194, 61, 146}, ++{102, 95, 114}, ++{115, 91, 119}, ++{131, 85, 126}, ++{147, 79, 131}, ++{163, 73, 136}, ++{179, 67, 141}, ++{195, 61, 146}, ++{195, 61, 146}, ++{103, 96, 114}, ++{117, 91, 120}, ++{132, 86, 126}, ++{148, 80, 131}, ++{164, 73, 137}, ++{180, 67, 141}, ++{196, 61, 146}, ++{196, 61, 146}, ++{105, 97, 115}, ++{118, 92, 120}, ++{134, 86, 126}, ++{149, 80, 132}, ++{165, 74, 137}, ++{181, 68, 141}, ++{197, 62, 146}, ++{197, 62, 146}, ++{107, 98, 116}, ++{120, 93, 121}, ++{135, 87, 126}, ++{151, 81, 132}, ++{167, 74, 137}, ++{182, 68, 141}, ++{197, 62, 146}, ++{197, 62, 146}, ++{110, 99, 116}, ++{122, 94, 121}, ++{137, 88, 127}, ++{152, 81, 132}, ++{168, 75, 137}, ++{183, 69, 142}, ++{199, 63, 146}, ++{199, 63, 146}, ++{112, 101, 117}, ++{125, 95, 122}, ++{139, 89, 127}, ++{154, 82, 132}, ++{169, 76, 137}, ++{185, 69, 142}, ++{200, 63, 146}, ++{200, 63, 146}, ++{115, 102, 118}, ++{127, 96, 122}, ++{141, 90, 128}, ++{156, 83, 133}, ++{171, 76, 137}, ++{186, 70, 142}, ++{201, 64, 146}, ++{201, 64, 146}, ++{118, 103, 119}, ++{129, 97, 123}, ++{143, 90, 128}, ++{158, 84, 133}, ++{173, 77, 138}, ++{188, 71, 142}, ++{202, 64, 146}, ++{202, 64, 146}, ++{121, 104, 119}, ++{132, 98, 124}, ++{145, 91, 128}, ++{160, 85, 133}, ++{174, 78, 138}, ++{189, 71, 142}, ++{204, 65, 146}, ++{204, 65, 146}, ++{124, 105, 120}, ++{135, 99, 124}, ++{148, 92, 129}, ++{162, 85, 134}, ++{176, 79, 138}, ++{191, 72, 142}, ++{205, 66, 146}, ++{205, 66, 146}, ++{127, 106, 121}, ++{138, 100, 125}, ++{150, 93, 129}, ++{164, 86, 134}, ++{178, 80, 138}, ++{193, 73, 143}, ++{207, 67, 147}, ++{207, 67, 147}, ++{131, 107, 122}, ++{141, 101, 126}, ++{153, 94, 130}, ++{167, 87, 134}, ++{181, 80, 139}, ++{195, 74, 143}, ++{209, 67, 147}, ++{209, 67, 147}, ++{134, 108, 123}, ++{144, 102, 126}, ++{156, 95, 130}, ++{169, 88, 135}, ++{183, 81, 139}, ++{197, 74, 143}, ++{211, 68, 147}, ++{211, 68, 147}, ++{138, 109, 123}, ++{147, 103, 127}, ++{159, 96, 131}, ++{172, 89, 135}, ++{185, 82, 139}, ++{199, 75, 143}, ++{213, 69, 147}, ++{213, 69, 147}, ++{141, 109, 124}, ++{150, 104, 127}, ++{162, 97, 131}, ++{174, 90, 135}, ++{187, 83, 139}, ++{201, 76, 143}, ++{215, 70, 147}, ++{215, 70, 147}, ++{145, 110, 125}, ++{153, 105, 128}, ++{165, 98, 132}, ++{177, 91, 136}, ++{190, 84, 140}, ++{203, 77, 144}, ++{217, 70, 147}, ++{217, 70, 147}, ++{148, 111, 126}, ++{157, 105, 129}, ++{168, 99, 132}, ++{180, 92, 136}, ++{192, 85, 140}, ++{205, 78, 144}, ++{219, 71, 147}, ++{219, 71, 148}, ++{152, 112, 126}, ++{160, 106, 129}, ++{171, 99, 133}, ++{182, 92, 137}, ++{195, 85, 140}, ++{208, 79, 144}, ++{221, 72, 148}, ++{221, 72, 148}, ++{156, 112, 127}, ++{164, 107, 130}, ++{174, 100, 133}, ++{185, 93, 137}, ++{198, 86, 141}, ++{210, 79, 144}, ++{223, 73, 148}, ++{223, 73, 148}, ++{159, 113, 128}, ++{167, 108, 130}, ++{177, 101, 134}, ++{188, 94, 137}, ++{200, 87, 141}, ++{213, 80, 145}, ++{225, 74, 148}, ++{225, 74, 148}, ++{163, 114, 129}, ++{170, 108, 131}, ++{180, 102, 134}, ++{191, 95, 138}, ++{203, 88, 141}, ++{215, 81, 145}, ++{228, 74, 148}, ++{228, 74, 148}, ++{167, 114, 129}, ++{174, 109, 132}, ++{183, 103, 135}, ++{194, 96, 138}, ++{206, 89, 142}, ++{218, 82, 145}, ++{230, 75, 148}, ++{230, 75, 148}, ++{170, 115, 130}, ++{177, 110, 132}, ++{187, 103, 135}, ++{197, 97, 138}, ++{209, 90, 142}, ++{220, 83, 145}, ++{233, 76, 149}, ++{233, 76, 149}, ++{174, 115, 131}, ++{181, 110, 133}, ++{190, 104, 136}, ++{200, 97, 139}, ++{211, 90, 142}, ++{223, 84, 146}, ++{235, 77, 149}, ++{235, 77, 149}, ++{176, 116, 131}, ++{183, 111, 133}, ++{192, 104, 136}, ++{202, 98, 139}, ++{213, 91, 142}, ++{224, 84, 146}, ++{236, 77, 149}, ++{236, 77, 149}, ++{176, 116, 131}, ++{183, 111, 133}, ++{192, 104, 136}, ++{202, 98, 139}, ++{213, 91, 142}, ++{224, 84, 146}, ++{236, 77, 149}, ++{236, 77, 149}, ++{176, 116, 131}, ++{183, 111, 133}, ++{192, 104, 136}, ++{202, 98, 139}, ++{213, 91, 142}, ++{224, 84, 146}, ++{236, 77, 149}, ++{236, 77, 149}, ++{176, 116, 131}, ++{183, 111, 133}, ++{192, 104, 136}, ++{202, 98, 139}, ++{213, 91, 142}, ++{224, 84, 146}, ++{236, 77, 149}, ++{236, 77, 149}, ++{101, 91, 110}, ++{115, 87, 116}, ++{131, 82, 123}, ++{147, 77, 129}, ++{163, 71, 134}, ++{179, 65, 139}, ++{195, 60, 144}, ++{195, 60, 144}, ++{101, 91, 110}, ++{115, 88, 116}, ++{131, 83, 123}, ++{147, 77, 129}, ++{163, 71, 134}, ++{179, 66, 139}, ++{195, 60, 144}, ++{195, 60, 144}, ++{102, 92, 110}, ++{115, 88, 116}, ++{131, 83, 123}, ++{147, 77, 129}, ++{164, 71, 134}, ++{180, 66, 139}, ++{195, 60, 144}, ++{195, 60, 144}, ++{103, 92, 111}, ++{116, 88, 117}, ++{132, 83, 123}, ++{148, 78, 129}, ++{164, 72, 134}, ++{180, 66, 139}, ++{196, 60, 144}, ++{196, 60, 144}, ++{104, 93, 111}, ++{117, 89, 117}, ++{133, 84, 123}, ++{149, 78, 129}, ++{165, 72, 134}, ++{181, 66, 139}, ++{196, 60, 144}, ++{196, 60, 144}, ++{106, 94, 112}, ++{119, 90, 117}, ++{134, 84, 123}, ++{150, 78, 129}, ++{166, 73, 134}, ++{182, 67, 139}, ++{197, 61, 144}, ++{197, 61, 144}, ++{108, 95, 112}, ++{120, 91, 118}, ++{135, 85, 124}, ++{151, 79, 129}, ++{167, 73, 135}, ++{182, 67, 139}, ++{198, 61, 144}, ++{198, 61, 144}, ++{110, 96, 113}, ++{122, 91, 118}, ++{137, 86, 124}, ++{152, 80, 130}, ++{168, 74, 135}, ++{183, 68, 140}, ++{199, 62, 144}, ++{199, 62, 144}, ++{112, 97, 114}, ++{124, 92, 119}, ++{139, 87, 125}, ++{154, 80, 130}, ++{169, 74, 135}, ++{185, 68, 140}, ++{200, 62, 144}, ++{200, 62, 144}, ++{115, 99, 115}, ++{127, 93, 120}, ++{141, 87, 125}, ++{156, 81, 130}, ++{171, 75, 135}, ++{186, 69, 140}, ++{201, 63, 144}, ++{201, 63, 144}, ++{117, 100, 116}, ++{129, 94, 120}, ++{143, 88, 125}, ++{157, 82, 131}, ++{172, 76, 135}, ++{187, 69, 140}, ++{202, 63, 144}, ++{202, 63, 144}, ++{120, 101, 116}, ++{131, 96, 121}, ++{145, 89, 126}, ++{159, 83, 131}, ++{174, 76, 136}, ++{189, 70, 140}, ++{204, 64, 144}, ++{204, 64, 144}, ++{123, 102, 117}, ++{134, 97, 121}, ++{147, 90, 126}, ++{161, 84, 131}, ++{176, 77, 136}, ++{190, 71, 140}, ++{205, 65, 145}, ++{205, 65, 145}, ++{126, 103, 118}, ++{137, 98, 122}, ++{150, 91, 127}, ++{163, 84, 132}, ++{178, 78, 136}, ++{192, 71, 141}, ++{207, 65, 145}, ++{207, 65, 145}, ++{129, 104, 119}, ++{140, 99, 123}, ++{152, 92, 127}, ++{166, 85, 132}, ++{180, 79, 136}, ++{194, 72, 141}, ++{208, 66, 145}, ++{208, 66, 145}, ++{133, 105, 120}, ++{143, 100, 123}, ++{155, 93, 128}, ++{168, 86, 132}, ++{182, 80, 137}, ++{196, 73, 141}, ++{210, 67, 145}, ++{210, 67, 145}, ++{136, 106, 121}, ++{146, 101, 124}, ++{157, 94, 128}, ++{170, 87, 133}, ++{184, 80, 137}, ++{198, 74, 141}, ++{212, 67, 145}, ++{212, 67, 145}, ++{139, 107, 121}, ++{149, 101, 125}, ++{160, 95, 129}, ++{173, 88, 133}, ++{186, 81, 137}, ++{200, 75, 141}, ++{214, 68, 145}, ++{214, 68, 145}, ++{143, 108, 122}, ++{152, 102, 125}, ++{163, 96, 129}, ++{176, 89, 134}, ++{189, 82, 138}, ++{202, 75, 142}, ++{216, 69, 146}, ++{216, 69, 146}, ++{146, 109, 123}, ++{155, 103, 126}, ++{166, 97, 130}, ++{178, 90, 134}, ++{191, 83, 138}, ++{204, 76, 142}, ++{218, 70, 146}, ++{218, 70, 146}, ++{150, 110, 124}, ++{158, 104, 127}, ++{169, 98, 130}, ++{181, 91, 134}, ++{194, 84, 138}, ++{207, 77, 142}, ++{220, 71, 146}, ++{220, 71, 146}, ++{153, 110, 125}, ++{162, 105, 127}, ++{172, 98, 131}, ++{184, 92, 135}, ++{196, 85, 139}, ++{209, 78, 142}, ++{222, 71, 146}, ++{222, 71, 146}, ++{157, 111, 125}, ++{165, 106, 128}, ++{175, 99, 131}, ++{187, 92, 135}, ++{199, 86, 139}, ++{211, 79, 143}, ++{224, 72, 146}, ++{224, 72, 146}, ++{161, 112, 126}, ++{168, 106, 129}, ++{178, 100, 132}, ++{189, 93, 136}, ++{201, 86, 139}, ++{214, 80, 143}, ++{226, 73, 147}, ++{226, 73, 147}, ++{164, 112, 127}, ++{172, 107, 129}, ++{181, 101, 133}, ++{192, 94, 136}, ++{204, 87, 140}, ++{216, 80, 143}, ++{229, 74, 147}, ++{229, 74, 147}, ++{168, 113, 127}, ++{175, 108, 130}, ++{185, 102, 133}, ++{195, 95, 136}, ++{207, 88, 140}, ++{219, 81, 144}, ++{231, 75, 147}, ++{231, 75, 147}, ++{172, 114, 128}, ++{179, 109, 131}, ++{188, 102, 134}, ++{198, 96, 137}, ++{210, 89, 140}, ++{222, 82, 144}, ++{234, 75, 147}, ++{234, 75, 147}, ++{175, 114, 129}, ++{182, 109, 131}, ++{191, 103, 134}, ++{202, 96, 137}, ++{213, 90, 141}, ++{224, 83, 144}, ++{236, 76, 147}, ++{236, 76, 147}, ++{177, 114, 129}, ++{184, 110, 131}, ++{193, 103, 134}, ++{203, 97, 138}, ++{214, 90, 141}, ++{226, 83, 144}, ++{237, 77, 148}, ++{237, 77, 148}, ++{177, 114, 129}, ++{184, 110, 131}, ++{193, 103, 134}, ++{203, 97, 138}, ++{214, 90, 141}, ++{226, 83, 144}, ++{237, 77, 148}, ++{237, 77, 148}, ++{177, 114, 129}, ++{184, 110, 131}, ++{193, 103, 134}, ++{203, 97, 138}, ++{214, 90, 141}, ++{226, 83, 144}, ++{237, 77, 148}, ++{237, 77, 148}, ++{177, 114, 129}, ++{184, 110, 131}, ++{193, 103, 134}, ++{203, 97, 138}, ++{214, 90, 141}, ++{226, 83, 144}, ++{237, 77, 148}, ++{237, 77, 148}, ++{103, 89, 108}, ++{117, 86, 114}, ++{133, 81, 120}, ++{149, 76, 126}, ++{165, 70, 132}, ++{181, 65, 137}, ++{196, 59, 142}, ++{196, 59, 142}, ++{104, 89, 108}, ++{117, 86, 114}, ++{133, 81, 120}, ++{149, 76, 126}, ++{165, 70, 132}, ++{181, 65, 137}, ++{196, 59, 142}, ++{196, 59, 142}, ++{104, 89, 108}, ++{118, 86, 114}, ++{133, 81, 120}, ++{149, 76, 126}, ++{165, 71, 132}, ++{181, 65, 137}, ++{197, 59, 142}, ++{197, 59, 142}, ++{105, 90, 108}, ++{119, 87, 114}, ++{134, 82, 121}, ++{150, 76, 127}, ++{166, 71, 132}, ++{182, 65, 137}, ++{197, 60, 142}, ++{197, 60, 142}, ++{107, 91, 109}, ++{120, 87, 115}, ++{135, 82, 121}, ++{151, 77, 127}, ++{167, 71, 132}, ++{182, 65, 137}, ++{198, 60, 142}, ++{198, 60, 142}, ++{108, 92, 109}, ++{121, 88, 115}, ++{136, 83, 121}, ++{152, 77, 127}, ++{167, 72, 132}, ++{183, 66, 137}, ++{198, 60, 142}, ++{198, 60, 142}, ++{110, 93, 110}, ++{123, 89, 116}, ++{137, 84, 121}, ++{153, 78, 127}, ++{168, 72, 133}, ++{184, 66, 137}, ++{199, 61, 142}, ++{199, 61, 142}, ++{112, 94, 111}, ++{124, 90, 116}, ++{139, 84, 122}, ++{154, 79, 127}, ++{170, 73, 133}, ++{185, 67, 138}, ++{200, 61, 142}, ++{200, 61, 142}, ++{115, 95, 112}, ++{126, 91, 117}, ++{141, 85, 122}, ++{156, 79, 128}, ++{171, 73, 133}, ++{186, 67, 138}, ++{201, 61, 142}, ++{201, 61, 142}, ++{117, 97, 112}, ++{129, 92, 117}, ++{142, 86, 123}, ++{157, 80, 128}, ++{172, 74, 133}, ++{187, 68, 138}, ++{202, 62, 142}, ++{202, 62, 142}, ++{120, 98, 113}, ++{131, 93, 118}, ++{144, 87, 123}, ++{159, 81, 128}, ++{174, 75, 133}, ++{189, 69, 138}, ++{203, 63, 143}, ++{203, 63, 143}, ++{122, 99, 114}, ++{133, 94, 119}, ++{147, 88, 124}, ++{161, 82, 129}, ++{176, 75, 134}, ++{190, 69, 138}, ++{205, 63, 143}, ++{205, 63, 143}, ++{125, 100, 115}, ++{136, 95, 119}, ++{149, 89, 124}, ++{163, 83, 129}, ++{177, 76, 134}, ++{192, 70, 139}, ++{206, 64, 143}, ++{206, 64, 143}, ++{128, 101, 116}, ++{139, 96, 120}, ++{151, 90, 125}, ++{165, 83, 130}, ++{179, 77, 134}, ++{194, 71, 139}, ++{208, 65, 143}, ++{208, 65, 143}, ++{131, 102, 117}, ++{141, 97, 121}, ++{154, 91, 125}, ++{167, 84, 130}, ++{181, 78, 135}, ++{195, 71, 139}, ++{209, 65, 143}, ++{209, 65, 143}, ++{135, 103, 118}, ++{144, 98, 121}, ++{156, 92, 126}, ++{170, 85, 130}, ++{183, 79, 135}, ++{197, 72, 139}, ++{211, 66, 143}, ++{211, 66, 143}, ++{138, 104, 118}, ++{147, 99, 122}, ++{159, 93, 126}, ++{172, 86, 131}, ++{185, 80, 135}, ++{199, 73, 139}, ++{213, 67, 144}, ++{213, 67, 144}, ++{141, 105, 119}, ++{150, 100, 123}, ++{162, 94, 127}, ++{174, 87, 131}, ++{188, 80, 136}, ++{201, 74, 140}, ++{215, 68, 144}, ++{215, 68, 144}, ++{145, 106, 120}, ++{154, 101, 123}, ++{165, 95, 127}, ++{177, 88, 132}, ++{190, 81, 136}, ++{203, 75, 140}, ++{217, 68, 144}, ++{217, 68, 144}, ++{148, 107, 121}, ++{157, 102, 124}, ++{168, 96, 128}, ++{180, 89, 132}, ++{192, 82, 136}, ++{206, 76, 140}, ++{219, 69, 144}, ++{219, 69, 144}, ++{152, 108, 122}, ++{160, 103, 125}, ++{170, 96, 129}, ++{182, 90, 133}, ++{195, 83, 137}, ++{208, 76, 141}, ++{221, 70, 144}, ++{221, 70, 144}, ++{155, 109, 123}, ++{163, 104, 125}, ++{174, 97, 129}, ++{185, 91, 133}, ++{197, 84, 137}, ++{210, 77, 141}, ++{223, 71, 145}, ++{223, 71, 145}, ++{159, 110, 123}, ++{167, 104, 126}, ++{177, 98, 130}, ++{188, 91, 133}, ++{200, 85, 137}, ++{213, 78, 141}, ++{225, 72, 145}, ++{225, 72, 145}, ++{162, 110, 124}, ++{170, 105, 127}, ++{180, 99, 130}, ++{191, 92, 134}, ++{203, 86, 138}, ++{215, 79, 141}, ++{228, 72, 145}, ++{228, 72, 145}, ++{166, 111, 125}, ++{173, 106, 128}, ++{183, 100, 131}, ++{194, 93, 134}, ++{205, 86, 138}, ++{217, 80, 142}, ++{230, 73, 145}, ++{230, 73, 145}, ++{170, 112, 126}, ++{177, 107, 128}, ++{186, 101, 131}, ++{197, 94, 135}, ++{208, 87, 138}, ++{220, 81, 142}, ++{232, 74, 146}, ++{232, 74, 146}, ++{173, 112, 126}, ++{180, 107, 129}, ++{189, 101, 132}, ++{200, 95, 135}, ++{211, 88, 139}, ++{223, 81, 142}, ++{235, 75, 146}, ++{235, 75, 146}, ++{177, 113, 127}, ++{184, 108, 129}, ++{193, 102, 132}, ++{203, 96, 136}, ++{214, 89, 139}, ++{225, 82, 143}, ++{237, 76, 146}, ++{237, 76, 146}, ++{179, 113, 127}, ++{185, 108, 130}, ++{194, 102, 133}, ++{204, 96, 136}, ++{215, 89, 139}, ++{227, 83, 143}, ++{238, 76, 146}, ++{238, 76, 146}, ++{179, 113, 127}, ++{185, 108, 130}, ++{194, 102, 133}, ++{204, 96, 136}, ++{215, 89, 139}, ++{227, 83, 143}, ++{238, 76, 146}, ++{238, 76, 146}, ++{179, 113, 127}, ++{185, 108, 130}, ++{194, 102, 133}, ++{204, 96, 136}, ++{215, 89, 139}, ++{227, 83, 143}, ++{238, 76, 146}, ++{238, 76, 146}, ++{179, 113, 127}, ++{185, 108, 130}, ++{194, 102, 133}, ++{204, 96, 136}, ++{215, 89, 139}, ++{227, 83, 143}, ++{238, 76, 146}, ++{238, 76, 146}, ++{106, 87, 105}, ++{119, 84, 111}, ++{135, 80, 118}, ++{151, 75, 124}, ++{167, 69, 130}, ++{182, 64, 135}, ++{198, 58, 140}, ++{198, 58, 140}, ++{106, 87, 105}, ++{120, 84, 111}, ++{135, 80, 118}, ++{151, 75, 124}, ++{167, 69, 130}, ++{182, 64, 135}, ++{198, 58, 140}, ++{198, 58, 140}, ++{107, 87, 106}, ++{120, 84, 112}, ++{135, 80, 118}, ++{151, 75, 124}, ++{167, 70, 130}, ++{183, 64, 135}, ++{198, 59, 140}, ++{198, 59, 140}, ++{108, 88, 106}, ++{121, 85, 112}, ++{136, 80, 118}, ++{152, 75, 124}, ++{167, 70, 130}, ++{183, 64, 135}, ++{198, 59, 140}, ++{198, 59, 140}, ++{109, 89, 106}, ++{122, 85, 112}, ++{137, 81, 118}, ++{153, 76, 124}, ++{168, 70, 130}, ++{184, 65, 135}, ++{199, 59, 140}, ++{199, 59, 140}, ++{111, 90, 107}, ++{123, 86, 113}, ++{138, 81, 119}, ++{153, 76, 125}, ++{169, 71, 130}, ++{184, 65, 135}, ++{200, 59, 140}, ++{200, 59, 140}, ++{113, 91, 108}, ++{125, 87, 113}, ++{139, 82, 119}, ++{155, 77, 125}, ++{170, 71, 130}, ++{185, 65, 135}, ++{200, 60, 140}, ++{200, 60, 140}, ++{115, 92, 108}, ++{127, 88, 114}, ++{141, 83, 120}, ++{156, 77, 125}, ++{171, 72, 131}, ++{186, 66, 136}, ++{201, 60, 140}, ++{201, 60, 140}, ++{117, 93, 109}, ++{129, 89, 114}, ++{143, 84, 120}, ++{157, 78, 126}, ++{172, 72, 131}, ++{188, 66, 136}, ++{202, 61, 140}, ++{202, 61, 140}, ++{119, 94, 110}, ++{131, 90, 115}, ++{144, 85, 120}, ++{159, 79, 126}, ++{174, 73, 131}, ++{189, 67, 136}, ++{204, 61, 141}, ++{204, 61, 141}, ++{122, 96, 111}, ++{133, 91, 116}, ++{146, 86, 121}, ++{161, 80, 126}, ++{175, 74, 131}, ++{190, 68, 136}, ++{205, 62, 141}, ++{205, 62, 141}, ++{125, 97, 112}, ++{135, 92, 116}, ++{149, 87, 121}, ++{163, 81, 127}, ++{177, 74, 132}, ++{192, 68, 136}, ++{206, 63, 141}, ++{206, 63, 141}, ++{128, 98, 113}, ++{138, 93, 117}, ++{151, 87, 122}, ++{165, 81, 127}, ++{179, 75, 132}, ++{193, 69, 137}, ++{208, 63, 141}, ++{208, 63, 141}, ++{130, 99, 114}, ++{141, 94, 118}, ++{153, 88, 122}, ++{167, 82, 127}, ++{181, 76, 132}, ++{195, 70, 137}, ++{209, 64, 141}, ++{209, 64, 141}, ++{134, 100, 114}, ++{143, 95, 118}, ++{156, 89, 123}, ++{169, 83, 128}, ++{183, 77, 133}, ++{197, 71, 137}, ++{211, 65, 141}, ++{211, 65, 141}, ++{137, 102, 115}, ++{146, 96, 119}, ++{158, 90, 124}, ++{171, 84, 128}, ++{185, 78, 133}, ++{199, 71, 137}, ++{212, 65, 142}, ++{212, 65, 142}, ++{140, 103, 116}, ++{149, 98, 120}, ++{161, 91, 124}, ++{174, 85, 129}, ++{187, 79, 133}, ++{201, 72, 138}, ++{214, 66, 142}, ++{214, 66, 142}, ++{143, 104, 117}, ++{152, 99, 121}, ++{163, 92, 125}, ++{176, 86, 129}, ++{189, 79, 134}, ++{203, 73, 138}, ++{216, 67, 142}, ++{216, 67, 142}, ++{147, 105, 118}, ++{155, 100, 121}, ++{166, 93, 125}, ++{179, 87, 130}, ++{191, 80, 134}, ++{205, 74, 138}, ++{218, 68, 142}, ++{218, 68, 142}, ++{150, 106, 119}, ++{158, 100, 122}, ++{169, 94, 126}, ++{181, 88, 130}, ++{194, 81, 134}, ++{207, 75, 138}, ++{220, 68, 142}, ++{220, 68, 142}, ++{153, 106, 120}, ++{162, 101, 123}, ++{172, 95, 127}, ++{184, 89, 131}, ++{196, 82, 135}, ++{209, 76, 139}, ++{222, 69, 143}, ++{222, 69, 143}, ++{157, 107, 121}, ++{165, 102, 124}, ++{175, 96, 127}, ++{187, 90, 131}, ++{199, 83, 135}, ++{211, 76, 139}, ++{224, 70, 143}, ++{224, 70, 143}, ++{160, 108, 121}, ++{168, 103, 124}, ++{178, 97, 128}, ++{189, 90, 132}, ++{201, 84, 135}, ++{214, 77, 139}, ++{226, 71, 143}, ++{226, 71, 143}, ++{164, 109, 122}, ++{172, 104, 125}, ++{181, 98, 128}, ++{192, 91, 132}, ++{204, 85, 136}, ++{216, 78, 140}, ++{229, 72, 143}, ++{229, 72, 143}, ++{168, 110, 123}, ++{175, 105, 126}, ++{184, 99, 129}, ++{195, 92, 133}, ++{207, 86, 136}, ++{219, 79, 140}, ++{231, 73, 144}, ++{231, 73, 144}, ++{171, 110, 124}, ++{178, 106, 126}, ++{188, 100, 130}, ++{198, 93, 133}, ++{209, 86, 137}, ++{221, 80, 140}, ++{233, 73, 144}, ++{233, 73, 144}, ++{175, 111, 125}, ++{182, 106, 127}, ++{191, 100, 130}, ++{201, 94, 134}, ++{212, 87, 137}, ++{224, 81, 141}, ++{236, 74, 144}, ++{236, 74, 144}, ++{178, 112, 125}, ++{185, 107, 128}, ++{194, 101, 131}, ++{204, 95, 134}, ++{215, 88, 137}, ++{226, 81, 141}, ++{238, 75, 144}, ++{238, 75, 144}, ++{180, 112, 126}, ++{187, 107, 128}, ++{196, 101, 131}, ++{206, 95, 134}, ++{216, 88, 138}, ++{228, 82, 141}, ++{239, 75, 145}, ++{239, 75, 145}, ++{180, 112, 126}, ++{187, 107, 128}, ++{196, 101, 131}, ++{206, 95, 134}, ++{216, 88, 138}, ++{228, 82, 141}, ++{239, 75, 145}, ++{239, 75, 145}, ++{180, 112, 126}, ++{187, 107, 128}, ++{196, 101, 131}, ++{206, 95, 134}, ++{216, 88, 138}, ++{228, 82, 141}, ++{239, 75, 145}, ++{239, 75, 145}, ++{180, 112, 126}, ++{187, 107, 128}, ++{196, 101, 131}, ++{206, 95, 134}, ++{216, 88, 138}, ++{228, 82, 141}, ++{239, 75, 145}, ++{239, 75, 145}, ++{109, 84, 103}, ++{122, 82, 109}, ++{137, 78, 115}, ++{153, 73, 122}, ++{168, 68, 128}, ++{184, 63, 133}, ++{199, 58, 138}, ++{199, 58, 138}, ++{109, 84, 103}, ++{122, 82, 109}, ++{137, 78, 116}, ++{153, 73, 122}, ++{168, 68, 128}, ++{184, 63, 133}, ++{199, 58, 138}, ++{199, 58, 138}, ++{110, 85, 103}, ++{123, 82, 109}, ++{137, 78, 116}, ++{153, 74, 122}, ++{169, 68, 128}, ++{184, 63, 133}, ++{199, 58, 138}, ++{199, 58, 138}, ++{111, 85, 104}, ++{123, 83, 109}, ++{138, 79, 116}, ++{154, 74, 122}, ++{169, 69, 128}, ++{185, 63, 133}, ++{200, 58, 138}, ++{200, 58, 138}, ++{112, 86, 104}, ++{124, 83, 110}, ++{139, 79, 116}, ++{154, 74, 122}, ++{170, 69, 128}, ++{185, 64, 133}, ++{200, 58, 138}, ++{200, 58, 138}, ++{113, 87, 105}, ++{126, 84, 110}, ++{140, 80, 116}, ++{155, 75, 122}, ++{171, 70, 128}, ++{186, 64, 133}, ++{201, 59, 138}, ++{201, 59, 138}, ++{115, 88, 105}, ++{127, 85, 111}, ++{141, 81, 117}, ++{156, 75, 123}, ++{172, 70, 128}, ++{187, 65, 133}, ++{202, 59, 138}, ++{202, 59, 138}, ++{117, 90, 106}, ++{129, 86, 111}, ++{143, 81, 117}, ++{158, 76, 123}, ++{173, 71, 128}, ++{188, 65, 134}, ++{203, 60, 138}, ++{203, 60, 138}, ++{119, 91, 107}, ++{131, 87, 112}, ++{145, 82, 118}, ++{159, 77, 123}, ++{174, 71, 129}, ++{189, 66, 134}, ++{204, 60, 138}, ++{204, 60, 138}, ++{122, 92, 108}, ++{133, 88, 113}, ++{146, 83, 118}, ++{161, 78, 124}, ++{176, 72, 129}, ++{190, 66, 134}, ++{205, 61, 139}, ++{205, 61, 139}, ++{124, 93, 109}, ++{135, 89, 113}, ++{148, 84, 119}, ++{163, 78, 124}, ++{177, 73, 129}, ++{192, 67, 134}, ++{206, 61, 139}, ++{206, 61, 139}, ++{127, 95, 109}, ++{138, 90, 114}, ++{150, 85, 119}, ++{164, 79, 124}, ++{179, 73, 130}, ++{193, 68, 134}, ++{208, 62, 139}, ++{208, 62, 139}, ++{130, 96, 110}, ++{140, 92, 115}, ++{153, 86, 120}, ++{166, 80, 125}, ++{180, 74, 130}, ++{195, 68, 135}, ++{209, 62, 139}, ++{209, 62, 139}, ++{133, 97, 111}, ++{143, 93, 115}, ++{155, 87, 120}, ++{168, 81, 125}, ++{182, 75, 130}, ++{196, 69, 135}, ++{210, 63, 139}, ++{210, 63, 139}, ++{136, 98, 112}, ++{145, 94, 116}, ++{157, 88, 121}, ++{171, 82, 126}, ++{184, 76, 131}, ++{198, 70, 135}, ++{212, 64, 140}, ++{212, 64, 140}, ++{139, 100, 113}, ++{148, 95, 117}, ++{160, 89, 122}, ++{173, 83, 126}, ++{186, 77, 131}, ++{200, 71, 135}, ++{214, 65, 140}, ++{214, 65, 140}, ++{142, 101, 114}, ++{151, 96, 118}, ++{163, 90, 122}, ++{175, 84, 127}, ++{188, 78, 131}, ++{202, 71, 136}, ++{216, 65, 140}, ++{216, 65, 140}, ++{145, 102, 115}, ++{154, 97, 118}, ++{165, 91, 123}, ++{178, 85, 127}, ++{191, 78, 132}, ++{204, 72, 136}, ++{217, 66, 140}, ++{217, 66, 140}, ++{148, 103, 116}, ++{157, 98, 119}, ++{168, 92, 123}, ++{180, 86, 128}, ++{193, 79, 132}, ++{206, 73, 136}, ++{219, 67, 140}, ++{219, 67, 140}, ++{152, 104, 117}, ++{160, 99, 120}, ++{171, 93, 124}, ++{183, 87, 128}, ++{195, 80, 132}, ++{208, 74, 137}, ++{221, 68, 141}, ++{221, 68, 141}, ++{155, 105, 118}, ++{163, 100, 121}, ++{174, 94, 125}, ++{185, 88, 129}, ++{198, 81, 133}, ++{210, 75, 137}, ++{223, 68, 141}, ++{223, 68, 141}, ++{159, 106, 119}, ++{167, 101, 122}, ++{177, 95, 125}, ++{188, 89, 129}, ++{200, 82, 133}, ++{213, 76, 137}, ++{225, 69, 141}, ++{225, 69, 141}, ++{162, 107, 119}, ++{170, 102, 122}, ++{180, 96, 126}, ++{191, 89, 130}, ++{203, 83, 134}, ++{215, 76, 138}, ++{228, 70, 142}, ++{228, 70, 142}, ++{166, 107, 120}, ++{173, 103, 123}, ++{183, 97, 126}, ++{194, 90, 130}, ++{205, 84, 134}, ++{217, 77, 138}, ++{230, 71, 142}, ++{230, 71, 142}, ++{169, 108, 121}, ++{176, 103, 124}, ++{186, 98, 127}, ++{197, 91, 131}, ++{208, 85, 135}, ++{220, 78, 138}, ++{232, 72, 142}, ++{232, 72, 142}, ++{173, 109, 122}, ++{180, 104, 124}, ++{189, 98, 128}, ++{199, 92, 131}, ++{211, 86, 135}, ++{222, 79, 139}, ++{235, 73, 142}, ++{235, 73, 142}, ++{176, 110, 123}, ++{183, 105, 125}, ++{192, 99, 128}, ++{202, 93, 132}, ++{213, 86, 135}, ++{225, 80, 139}, ++{237, 73, 143}, ++{237, 73, 143}, ++{180, 110, 123}, ++{187, 106, 126}, ++{195, 100, 129}, ++{205, 94, 132}, ++{216, 87, 136}, ++{228, 81, 139}, ++{239, 74, 143}, ++{239, 74, 143}, ++{182, 111, 124}, ++{188, 106, 126}, ++{197, 100, 129}, ++{207, 94, 133}, ++{218, 88, 136}, ++{229, 81, 140}, ++{241, 75, 143}, ++{241, 75, 143}, ++{182, 111, 124}, ++{188, 106, 126}, ++{197, 100, 129}, ++{207, 94, 133}, ++{218, 88, 136}, ++{229, 81, 140}, ++{241, 75, 143}, ++{241, 75, 143}, ++{182, 111, 124}, ++{188, 106, 126}, ++{197, 100, 129}, ++{207, 94, 133}, ++{218, 88, 136}, ++{229, 81, 140}, ++{241, 75, 143}, ++{241, 75, 143}, ++{182, 111, 124}, ++{188, 106, 126}, ++{197, 100, 129}, ++{207, 94, 133}, ++{218, 88, 136}, ++{229, 81, 140}, ++{241, 75, 143}, ++{241, 75, 143}, ++{112, 82, 100}, ++{124, 80, 107}, ++{139, 76, 113}, ++{154, 72, 119}, ++{170, 67, 125}, ++{185, 62, 131}, ++{201, 57, 136}, ++{201, 57, 136}, ++{112, 82, 101}, ++{124, 80, 107}, ++{139, 76, 113}, ++{155, 72, 119}, ++{170, 67, 125}, ++{186, 62, 131}, ++{201, 57, 136}, ++{201, 57, 136}, ++{112, 82, 101}, ++{125, 80, 107}, ++{140, 77, 113}, ++{155, 72, 120}, ++{170, 67, 125}, ++{186, 62, 131}, ++{201, 57, 136}, ++{201, 57, 136}, ++{113, 83, 101}, ++{126, 81, 107}, ++{140, 77, 114}, ++{156, 73, 120}, ++{171, 68, 126}, ++{186, 62, 131}, ++{201, 57, 136}, ++{201, 57, 136}, ++{115, 84, 102}, ++{127, 81, 107}, ++{141, 78, 114}, ++{156, 73, 120}, ++{172, 68, 126}, ++{187, 63, 131}, ++{202, 58, 136}, ++{202, 58, 136}, ++{116, 85, 102}, ++{128, 82, 108}, ++{142, 78, 114}, ++{157, 74, 120}, ++{172, 68, 126}, ++{188, 63, 131}, ++{203, 58, 136}, ++{203, 58, 136}, ++{118, 86, 103}, ++{130, 83, 108}, ++{144, 79, 114}, ++{158, 74, 120}, ++{173, 69, 126}, ++{188, 64, 131}, ++{203, 58, 136}, ++{203, 58, 136}, ++{120, 87, 104}, ++{131, 84, 109}, ++{145, 80, 115}, ++{160, 75, 121}, ++{175, 70, 126}, ++{189, 64, 131}, ++{204, 59, 136}, ++{204, 59, 136}, ++{122, 89, 104}, ++{133, 85, 110}, ++{147, 81, 115}, ++{161, 76, 121}, ++{176, 70, 127}, ++{191, 65, 132}, ++{205, 59, 136}, ++{205, 59, 136}, ++{124, 90, 105}, ++{135, 86, 110}, ++{148, 82, 116}, ++{163, 76, 121}, ++{177, 71, 127}, ++{192, 65, 132}, ++{206, 60, 137}, ++{206, 60, 137}, ++{127, 91, 106}, ++{137, 87, 111}, ++{150, 82, 116}, ++{164, 77, 122}, ++{179, 72, 127}, ++{193, 66, 132}, ++{208, 60, 137}, ++{208, 60, 137}, ++{129, 93, 107}, ++{140, 89, 112}, ++{152, 83, 117}, ++{166, 78, 122}, ++{180, 72, 127}, ++{195, 67, 132}, ++{209, 61, 137}, ++{209, 61, 137}, ++{132, 94, 108}, ++{142, 90, 112}, ++{155, 85, 118}, ++{168, 79, 123}, ++{182, 73, 128}, ++{196, 67, 133}, ++{210, 62, 137}, ++{210, 62, 137}, ++{135, 95, 109}, ++{145, 91, 113}, ++{157, 86, 118}, ++{170, 80, 123}, ++{184, 74, 128}, ++{198, 68, 133}, ++{212, 62, 137}, ++{212, 62, 137}, ++{138, 96, 110}, ++{147, 92, 114}, ++{159, 87, 119}, ++{172, 81, 124}, ++{186, 75, 129}, ++{200, 69, 133}, ++{213, 63, 138}, ++{213, 63, 138}, ++{141, 98, 111}, ++{150, 93, 115}, ++{162, 88, 119}, ++{174, 82, 124}, ++{188, 76, 129}, ++{201, 70, 134}, ++{215, 64, 138}, ++{215, 64, 138}, ++{144, 99, 112}, ++{153, 94, 116}, ++{164, 89, 120}, ++{177, 83, 125}, ++{190, 77, 129}, ++{203, 70, 134}, ++{217, 65, 138}, ++{217, 65, 138}, ++{147, 100, 113}, ++{156, 95, 116}, ++{167, 90, 121}, ++{179, 84, 125}, ++{192, 77, 130}, ++{205, 71, 134}, ++{219, 65, 138}, ++{219, 65, 138}, ++{150, 101, 114}, ++{159, 96, 117}, ++{170, 91, 121}, ++{182, 85, 126}, ++{194, 78, 130}, ++{207, 72, 134}, ++{221, 66, 139}, ++{221, 66, 139}, ++{154, 102, 115}, ++{162, 97, 118}, ++{173, 92, 122}, ++{184, 86, 126}, ++{197, 79, 131}, ++{210, 73, 135}, ++{223, 67, 139}, ++{223, 67, 139}, ++{157, 103, 116}, ++{165, 98, 119}, ++{175, 93, 123}, ++{187, 86, 127}, ++{199, 80, 131}, ++{212, 74, 135}, ++{225, 68, 139}, ++{225, 68, 139}, ++{161, 104, 116}, ++{168, 99, 119}, ++{178, 94, 123}, ++{190, 87, 127}, ++{202, 81, 131}, ++{214, 75, 136}, ++{227, 69, 140}, ++{227, 69, 140}, ++{164, 105, 117}, ++{172, 100, 120}, ++{181, 95, 124}, ++{192, 88, 128}, ++{204, 82, 132}, ++{216, 76, 136}, ++{229, 69, 140}, ++{229, 69, 140}, ++{167, 106, 118}, ++{175, 101, 121}, ++{184, 95, 125}, ++{195, 89, 128}, ++{207, 83, 132}, ++{219, 76, 136}, ++{231, 70, 140}, ++{231, 70, 140}, ++{171, 107, 119}, ++{178, 102, 122}, ++{187, 96, 125}, ++{198, 90, 129}, ++{209, 84, 133}, ++{221, 77, 137}, ++{233, 71, 140}, ++{233, 71, 140}, ++{174, 107, 120}, ++{181, 103, 123}, ++{191, 97, 126}, ++{201, 91, 129}, ++{212, 85, 133}, ++{224, 78, 137}, ++{236, 72, 141}, ++{236, 72, 141}, ++{178, 108, 121}, ++{185, 104, 123}, ++{194, 98, 126}, ++{204, 92, 130}, ++{215, 85, 134}, ++{226, 79, 137}, ++{238, 73, 141}, ++{238, 73, 141}, ++{182, 109, 122}, ++{188, 104, 124}, ++{197, 99, 127}, ++{207, 93, 130}, ++{218, 86, 134}, ++{229, 80, 138}, ++{241, 74, 141}, ++{241, 74, 141}, ++{183, 109, 122}, ++{190, 105, 124}, ++{198, 99, 127}, ++{208, 93, 131}, ++{219, 87, 134}, ++{230, 80, 138}, ++{242, 74, 141}, ++{242, 74, 141}, ++{183, 109, 122}, ++{190, 105, 124}, ++{198, 99, 127}, ++{208, 93, 131}, ++{219, 87, 134}, ++{230, 80, 138}, ++{242, 74, 141}, ++{242, 74, 141}, ++{183, 109, 122}, ++{190, 105, 124}, ++{198, 99, 127}, ++{208, 93, 131}, ++{219, 87, 134}, ++{230, 80, 138}, ++{242, 74, 141}, ++{242, 74, 141}, ++{183, 109, 122}, ++{190, 105, 124}, ++{198, 99, 127}, ++{208, 93, 131}, ++{219, 87, 134}, ++{230, 80, 138}, ++{242, 74, 141}, ++{242, 74, 141}, ++{114, 79, 98}, ++{127, 78, 104}, ++{141, 75, 111}, ++{156, 71, 117}, ++{172, 66, 123}, ++{187, 61, 129}, ++{202, 56, 134}, ++{202, 56, 134}, ++{115, 79, 98}, ++{127, 78, 104}, ++{141, 75, 111}, ++{157, 71, 117}, ++{172, 66, 123}, ++{187, 61, 129}, ++{202, 56, 134}, ++{202, 56, 134}, ++{115, 80, 99}, ++{127, 78, 104}, ++{142, 75, 111}, ++{157, 71, 117}, ++{172, 66, 123}, ++{187, 61, 129}, ++{202, 56, 134}, ++{202, 56, 134}, ++{116, 81, 99}, ++{128, 79, 105}, ++{143, 75, 111}, ++{158, 71, 117}, ++{173, 66, 123}, ++{188, 61, 129}, ++{203, 56, 134}, ++{203, 56, 134}, ++{117, 81, 99}, ++{129, 79, 105}, ++{143, 76, 111}, ++{158, 72, 118}, ++{173, 67, 123}, ++{188, 62, 129}, ++{203, 57, 134}, ++{203, 57, 134}, ++{119, 82, 100}, ++{131, 80, 106}, ++{144, 77, 112}, ++{159, 72, 118}, ++{174, 67, 124}, ++{189, 62, 129}, ++{204, 57, 134}, ++{204, 57, 134}, ++{120, 84, 101}, ++{132, 81, 106}, ++{146, 77, 112}, ++{160, 73, 118}, ++{175, 68, 124}, ++{190, 63, 129}, ++{205, 57, 134}, ++{205, 57, 134}, ++{122, 85, 101}, ++{134, 82, 107}, ++{147, 78, 113}, ++{162, 73, 119}, ++{176, 68, 124}, ++{191, 63, 129}, ++{206, 58, 134}, ++{206, 58, 134}, ++{124, 86, 102}, ++{135, 83, 107}, ++{149, 79, 113}, ++{163, 74, 119}, ++{178, 69, 124}, ++{192, 64, 130}, ++{207, 58, 135}, ++{207, 58, 135}, ++{127, 88, 103}, ++{137, 84, 108}, ++{150, 80, 114}, ++{165, 75, 119}, ++{179, 70, 125}, ++{193, 64, 130}, ++{208, 59, 135}, ++{208, 59, 135}, ++{129, 89, 104}, ++{140, 85, 109}, ++{152, 81, 114}, ++{166, 76, 120}, ++{180, 70, 125}, ++{195, 65, 130}, ++{209, 59, 135}, ++{209, 59, 135}, ++{132, 90, 105}, ++{142, 87, 109}, ++{154, 82, 115}, ++{168, 77, 120}, ++{182, 71, 125}, ++{196, 66, 130}, ++{210, 60, 135}, ++{210, 60, 135}, ++{134, 92, 106}, ++{144, 88, 110}, ++{157, 83, 115}, ++{170, 78, 121}, ++{184, 72, 126}, ++{198, 66, 131}, ++{212, 61, 135}, ++{212, 61, 135}, ++{137, 93, 107}, ++{147, 89, 111}, ++{159, 84, 116}, ++{172, 78, 121}, ++{186, 73, 126}, ++{199, 67, 131}, ++{213, 61, 136}, ++{213, 61, 136}, ++{140, 94, 108}, ++{149, 90, 112}, ++{161, 85, 117}, ++{174, 79, 122}, ++{187, 74, 126}, ++{201, 68, 131}, ++{215, 62, 136}, ++{215, 62, 136}, ++{143, 96, 109}, ++{152, 91, 113}, ++{164, 86, 117}, ++{176, 80, 122}, ++{189, 75, 127}, ++{203, 69, 132}, ++{217, 63, 136}, ++{217, 63, 136}, ++{146, 97, 110}, ++{155, 92, 113}, ++{166, 87, 118}, ++{179, 81, 123}, ++{192, 75, 127}, ++{205, 70, 132}, ++{218, 64, 136}, ++{218, 64, 136}, ++{149, 98, 111}, ++{158, 94, 114}, ++{169, 88, 119}, ++{181, 82, 123}, ++{194, 76, 128}, ++{207, 70, 132}, ++{220, 64, 137}, ++{220, 64, 137}, ++{152, 99, 112}, ++{161, 95, 115}, ++{171, 89, 119}, ++{183, 83, 124}, ++{196, 77, 128}, ++{209, 71, 133}, ++{222, 65, 137}, ++{222, 65, 137}, ++{156, 100, 113}, ++{164, 96, 116}, ++{174, 90, 120}, ++{186, 84, 124}, ++{198, 78, 129}, ++{211, 72, 133}, ++{224, 66, 137}, ++{224, 66, 137}, ++{159, 101, 113}, ++{167, 97, 117}, ++{177, 91, 121}, ++{188, 85, 125}, ++{201, 79, 129}, ++{213, 73, 133}, ++{226, 67, 137}, ++{226, 67, 137}, ++{162, 102, 114}, ++{170, 98, 117}, ++{180, 92, 121}, ++{191, 86, 125}, ++{203, 80, 130}, ++{215, 74, 134}, ++{228, 68, 138}, ++{228, 68, 138}, ++{166, 103, 115}, ++{173, 99, 118}, ++{183, 93, 122}, ++{194, 87, 126}, ++{206, 81, 130}, ++{218, 75, 134}, ++{230, 69, 138}, ++{230, 69, 138}, ++{169, 104, 116}, ++{177, 100, 119}, ++{186, 94, 123}, ++{197, 88, 126}, ++{208, 82, 130}, ++{220, 76, 134}, ++{232, 69, 138}, ++{232, 69, 138}, ++{173, 105, 117}, ++{180, 101, 120}, ++{189, 95, 123}, ++{199, 89, 127}, ++{211, 83, 131}, ++{223, 76, 135}, ++{235, 70, 139}, ++{235, 70, 139}, ++{176, 106, 118}, ++{183, 101, 121}, ++{192, 96, 124}, ++{202, 90, 128}, ++{213, 84, 131}, ++{225, 77, 135}, ++{237, 71, 139}, ++{237, 71, 139}, ++{180, 107, 119}, ++{186, 102, 121}, ++{195, 97, 125}, ++{205, 91, 128}, ++{216, 84, 132}, ++{228, 78, 136}, ++{239, 72, 139}, ++{239, 72, 139}, ++{183, 107, 120}, ++{190, 103, 122}, ++{198, 98, 125}, ++{208, 92, 129}, ++{219, 85, 132}, ++{230, 79, 136}, ++{242, 73, 140}, ++{242, 73, 140}, ++{185, 108, 120}, ++{191, 103, 123}, ++{200, 98, 126}, ++{210, 92, 129}, ++{220, 86, 133}, ++{231, 79, 136}, ++{243, 73, 140}, ++{243, 73, 140}, ++{185, 108, 120}, ++{191, 103, 123}, ++{200, 98, 126}, ++{210, 92, 129}, ++{220, 86, 133}, ++{231, 79, 136}, ++{243, 73, 140}, ++{243, 73, 140}, ++{185, 108, 120}, ++{191, 103, 123}, ++{200, 98, 126}, ++{210, 92, 129}, ++{220, 86, 133}, ++{231, 79, 136}, ++{243, 73, 140}, ++{243, 73, 140}, ++{185, 108, 120}, ++{191, 103, 123}, ++{200, 98, 126}, ++{210, 92, 129}, ++{220, 86, 133}, ++{231, 79, 136}, ++{243, 73, 140}, ++{243, 73, 140}, ++{117, 77, 96}, ++{129, 76, 102}, ++{143, 73, 109}, ++{158, 69, 115}, ++{174, 65, 121}, ++{189, 60, 127}, ++{204, 55, 132}, ++{204, 55, 132}, ++{117, 77, 96}, ++{129, 76, 102}, ++{144, 73, 109}, ++{159, 69, 115}, ++{174, 65, 121}, ++{189, 60, 127}, ++{204, 55, 132}, ++{204, 55, 132}, ++{118, 77, 96}, ++{130, 76, 102}, ++{144, 73, 109}, ++{159, 69, 115}, ++{174, 65, 121}, ++{189, 60, 127}, ++{204, 55, 132}, ++{204, 55, 132}, ++{119, 78, 97}, ++{131, 77, 102}, ++{145, 74, 109}, ++{160, 70, 115}, ++{175, 65, 121}, ++{190, 60, 127}, ++{204, 55, 132}, ++{204, 55, 132}, ++{120, 79, 97}, ++{132, 77, 103}, ++{146, 74, 109}, ++{160, 70, 115}, ++{175, 66, 121}, ++{190, 61, 127}, ++{205, 56, 132}, ++{205, 56, 132}, ++{121, 80, 98}, ++{133, 78, 103}, ++{147, 75, 110}, ++{161, 71, 116}, ++{176, 66, 122}, ++{191, 61, 127}, ++{206, 56, 132}, ++{206, 56, 132}, ++{123, 81, 98}, ++{134, 79, 104}, ++{148, 76, 110}, ++{162, 71, 116}, ++{177, 67, 122}, ++{192, 62, 127}, ++{206, 57, 132}, ++{206, 57, 132}, ++{125, 83, 99}, ++{136, 80, 104}, ++{149, 76, 110}, ++{164, 72, 116}, ++{178, 67, 122}, ++{193, 62, 127}, ++{207, 57, 132}, ++{207, 57, 132}, ++{127, 84, 100}, ++{138, 81, 105}, ++{151, 77, 111}, ++{165, 73, 117}, ++{179, 68, 122}, ++{194, 63, 128}, ++{208, 57, 133}, ++{208, 57, 133}, ++{129, 85, 101}, ++{140, 82, 106}, ++{153, 78, 111}, ++{166, 74, 117}, ++{181, 68, 123}, ++{195, 63, 128}, ++{209, 58, 133}, ++{209, 58, 133}, ++{132, 87, 102}, ++{142, 83, 106}, ++{154, 79, 112}, ++{168, 74, 118}, ++{182, 69, 123}, ++{196, 64, 128}, ++{211, 59, 133}, ++{211, 59, 133}, ++{134, 88, 103}, ++{144, 85, 107}, ++{156, 80, 113}, ++{170, 75, 118}, ++{184, 70, 123}, ++{198, 65, 128}, ++{212, 59, 133}, ++{212, 59, 133}, ++{137, 90, 104}, ++{146, 86, 108}, ++{159, 81, 113}, ++{172, 76, 118}, ++{185, 71, 124}, ++{199, 65, 129}, ++{213, 60, 133}, ++{213, 60, 133}, ++{139, 91, 105}, ++{149, 87, 109}, ++{161, 82, 114}, ++{174, 77, 119}, ++{187, 72, 124}, ++{201, 66, 129}, ++{215, 61, 134}, ++{215, 61, 134}, ++{142, 92, 106}, ++{152, 88, 110}, ++{163, 83, 114}, ++{176, 78, 119}, ++{189, 73, 124}, ++{203, 67, 129}, ++{216, 61, 134}, ++{216, 61, 134}, ++{145, 94, 107}, ++{154, 90, 110}, ++{166, 85, 115}, ++{178, 79, 120}, ++{191, 73, 125}, ++{204, 68, 130}, ++{218, 62, 134}, ++{218, 62, 134}, ++{148, 95, 108}, ++{157, 91, 111}, ++{168, 86, 116}, ++{180, 80, 121}, ++{193, 74, 125}, ++{206, 69, 130}, ++{220, 63, 134}, ++{220, 63, 134}, ++{151, 96, 109}, ++{160, 92, 112}, ++{171, 87, 116}, ++{183, 81, 121}, ++{195, 75, 126}, ++{208, 69, 130}, ++{221, 64, 135}, ++{221, 64, 135}, ++{155, 97, 109}, ++{163, 93, 113}, ++{173, 88, 117}, ++{185, 82, 122}, ++{198, 76, 126}, ++{210, 70, 131}, ++{223, 64, 135}, ++{223, 64, 135}, ++{158, 98, 110}, ++{166, 94, 114}, ++{176, 89, 118}, ++{188, 83, 122}, ++{200, 77, 127}, ++{212, 71, 131}, ++{225, 65, 135}, ++{225, 65, 135}, ++{161, 99, 111}, ++{169, 95, 115}, ++{179, 90, 119}, ++{190, 84, 123}, ++{202, 78, 127}, ++{215, 72, 131}, ++{227, 66, 136}, ++{227, 66, 136}, ++{164, 101, 112}, ++{172, 96, 115}, ++{182, 91, 119}, ++{193, 85, 123}, ++{205, 79, 128}, ++{217, 73, 132}, ++{229, 67, 136}, ++{229, 67, 136}, ++{168, 102, 113}, ++{175, 97, 116}, ++{185, 92, 120}, ++{195, 86, 124}, ++{207, 80, 128}, ++{219, 74, 132}, ++{232, 68, 136}, ++{232, 68, 136}, ++{171, 102, 114}, ++{178, 98, 117}, ++{188, 93, 121}, ++{198, 87, 125}, ++{210, 81, 129}, ++{222, 75, 133}, ++{234, 69, 137}, ++{234, 69, 137}, ++{174, 103, 115}, ++{181, 99, 118}, ++{191, 94, 121}, ++{201, 88, 125}, ++{212, 82, 129}, ++{224, 76, 133}, ++{236, 69, 137}, ++{236, 69, 137}, ++{178, 104, 116}, ++{185, 100, 119}, ++{194, 95, 122}, ++{204, 89, 126}, ++{215, 83, 130}, ++{226, 76, 133}, ++{238, 70, 137}, ++{238, 70, 137}, ++{181, 105, 117}, ++{188, 101, 119}, ++{197, 95, 123}, ++{207, 90, 126}, ++{218, 83, 130}, ++{229, 77, 134}, ++{241, 71, 138}, ++{241, 71, 138}, ++{185, 106, 118}, ++{191, 102, 120}, ++{200, 96, 123}, ++{210, 90, 127}, ++{220, 84, 131}, ++{231, 78, 134}, ++{243, 72, 138}, ++{243, 72, 138}, ++{187, 106, 118}, ++{193, 102, 121}, ++{201, 97, 124}, ++{211, 91, 127}, ++{222, 85, 131}, ++{233, 79, 134}, ++{244, 72, 138}, ++{244, 72, 138}, ++{187, 106, 118}, ++{193, 102, 121}, ++{201, 97, 124}, ++{211, 91, 127}, ++{222, 85, 131}, ++{233, 79, 134}, ++{244, 72, 138}, ++{244, 72, 138}, ++{187, 106, 118}, ++{193, 102, 121}, ++{201, 97, 124}, ++{211, 91, 127}, ++{222, 85, 131}, ++{233, 79, 134}, ++{244, 72, 138}, ++{244, 72, 138}, ++{187, 106, 118}, ++{193, 102, 121}, ++{201, 97, 124}, ++{211, 91, 127}, ++{222, 85, 131}, ++{233, 79, 134}, ++{244, 72, 138}, ++{244, 72, 138}, ++{120, 74, 94}, ++{132, 73, 100}, ++{146, 71, 106}, ++{161, 68, 113}, ++{175, 63, 119}, ++{190, 59, 124}, ++{205, 54, 130}, ++{205, 54, 130}, ++{120, 74, 94}, ++{132, 74, 100}, ++{146, 71, 106}, ++{161, 68, 113}, ++{176, 63, 119}, ++{191, 59, 124}, ++{205, 54, 130}, ++{205, 54, 130}, ++{121, 75, 94}, ++{132, 74, 100}, ++{146, 71, 106}, ++{161, 68, 113}, ++{176, 64, 119}, ++{191, 59, 125}, ++{206, 54, 130}, ++{206, 54, 130}, ++{122, 76, 94}, ++{133, 74, 100}, ++{147, 72, 107}, ++{162, 68, 113}, ++{176, 64, 119}, ++{191, 59, 125}, ++{206, 55, 130}, ++{206, 55, 130}, ++{123, 77, 95}, ++{134, 75, 101}, ++{148, 72, 107}, ++{162, 69, 113}, ++{177, 64, 119}, ++{192, 60, 125}, ++{206, 55, 130}, ++{206, 55, 130}, ++{124, 78, 96}, ++{135, 76, 101}, ++{149, 73, 107}, ++{163, 69, 113}, ++{178, 65, 119}, ++{193, 60, 125}, ++{207, 55, 130}, ++{207, 55, 130}, ++{126, 79, 96}, ++{137, 77, 102}, ++{150, 74, 108}, ++{164, 70, 114}, ++{179, 65, 120}, ++{193, 61, 125}, ++{208, 56, 130}, ++{208, 56, 130}, ++{128, 80, 97}, ++{138, 78, 102}, ++{151, 75, 108}, ++{165, 70, 114}, ++{180, 66, 120}, ++{194, 61, 125}, ++{209, 56, 130}, ++{209, 56, 130}, ++{130, 82, 98}, ++{140, 79, 103}, ++{153, 76, 109}, ++{167, 71, 114}, ++{181, 67, 120}, ++{195, 62, 125}, ++{210, 57, 131}, ++{210, 57, 131}, ++{132, 83, 99}, ++{142, 80, 104}, ++{155, 76, 109}, ++{168, 72, 115}, ++{182, 67, 120}, ++{197, 62, 126}, ++{211, 57, 131}, ++{211, 57, 131}, ++{134, 84, 100}, ++{144, 81, 104}, ++{157, 77, 110}, ++{170, 73, 115}, ++{184, 68, 121}, ++{198, 63, 126}, ++{212, 58, 131}, ++{212, 58, 131}, ++{136, 86, 100}, ++{146, 83, 105}, ++{158, 79, 110}, ++{172, 74, 116}, ++{185, 69, 121}, ++{199, 64, 126}, ++{213, 58, 131}, ++{213, 58, 131}, ++{139, 87, 101}, ++{149, 84, 106}, ++{161, 80, 111}, ++{174, 75, 116}, ++{187, 70, 122}, ++{201, 64, 127}, ++{215, 59, 131}, ++{215, 59, 131}, ++{142, 89, 102}, ++{151, 85, 107}, ++{163, 81, 112}, ++{176, 76, 117}, ++{189, 70, 122}, ++{203, 65, 127}, ++{216, 60, 132}, ++{216, 60, 132}, ++{145, 90, 103}, ++{154, 86, 107}, ++{165, 82, 112}, ++{178, 77, 117}, ++{191, 71, 122}, ++{204, 66, 127}, ++{218, 60, 132}, ++{218, 60, 132}, ++{147, 91, 104}, ++{156, 88, 108}, ++{167, 83, 113}, ++{180, 78, 118}, ++{193, 72, 123}, ++{206, 67, 128}, ++{219, 61, 132}, ++{219, 61, 132}, ++{150, 93, 105}, ++{159, 89, 109}, ++{170, 84, 114}, ++{182, 79, 118}, ++{195, 73, 123}, ++{208, 68, 128}, ++{221, 62, 133}, ++{221, 62, 133}, ++{153, 94, 106}, ++{162, 90, 110}, ++{173, 85, 114}, ++{184, 80, 119}, ++{197, 74, 124}, ++{210, 68, 128}, ++{223, 63, 133}, ++{223, 63, 133}, ++{157, 95, 107}, ++{165, 91, 111}, ++{175, 86, 115}, ++{187, 81, 120}, ++{199, 75, 124}, ++{212, 69, 129}, ++{225, 64, 133}, ++{225, 64, 133}, ++{160, 96, 108}, ++{168, 92, 112}, ++{178, 87, 116}, ++{189, 82, 120}, ++{201, 76, 125}, ++{214, 70, 129}, ++{227, 64, 134}, ++{227, 64, 134}, ++{163, 98, 109}, ++{171, 93, 113}, ++{181, 88, 117}, ++{192, 83, 121}, ++{204, 77, 125}, ++{216, 71, 130}, ++{229, 65, 134}, ++{229, 65, 134}, ++{166, 99, 110}, ++{174, 95, 113}, ++{183, 89, 117}, ++{194, 84, 121}, ++{206, 78, 126}, ++{218, 72, 130}, ++{231, 66, 134}, ++{231, 66, 134}, ++{170, 100, 111}, ++{177, 96, 114}, ++{186, 90, 118}, ++{197, 85, 122}, ++{209, 79, 126}, ++{221, 73, 130}, ++{233, 67, 135}, ++{233, 67, 135}, ++{173, 101, 112}, ++{180, 97, 115}, ++{189, 91, 119}, ++{200, 86, 123}, ++{211, 80, 127}, ++{223, 74, 131}, ++{235, 68, 135}, ++{235, 68, 135}, ++{176, 102, 113}, ++{183, 98, 116}, ++{192, 92, 119}, ++{203, 87, 123}, ++{214, 81, 127}, ++{225, 75, 131}, ++{237, 69, 135}, ++{237, 69, 135}, ++{180, 103, 114}, ++{186, 98, 117}, ++{195, 93, 120}, ++{205, 87, 124}, ++{216, 81, 128}, ++{228, 75, 132}, ++{240, 69, 136}, ++{240, 69, 136}, ++{183, 104, 115}, ++{190, 99, 118}, ++{198, 94, 121}, ++{208, 88, 124}, ++{219, 82, 128}, ++{230, 76, 132}, ++{242, 70, 136}, ++{242, 70, 136}, ++{187, 104, 116}, ++{193, 100, 118}, ++{201, 95, 122}, ++{211, 89, 125}, ++{222, 83, 129}, ++{233, 77, 133}, ++{244, 71, 136}, ++{244, 71, 136}, ++{188, 105, 116}, ++{195, 101, 119}, ++{203, 95, 122}, ++{213, 90, 125}, ++{223, 84, 129}, ++{234, 78, 133}, ++{245, 72, 137}, ++{245, 72, 137}, ++{188, 105, 116}, ++{195, 101, 119}, ++{203, 95, 122}, ++{213, 90, 125}, ++{223, 84, 129}, ++{234, 78, 133}, ++{245, 72, 137}, ++{245, 72, 137}, ++{188, 105, 116}, ++{195, 101, 119}, ++{203, 95, 122}, ++{213, 90, 125}, ++{223, 84, 129}, ++{234, 78, 133}, ++{245, 72, 137}, ++{245, 72, 137}, ++{188, 105, 116}, ++{195, 101, 119}, ++{203, 95, 122}, ++{213, 90, 125}, ++{223, 84, 129}, ++{234, 78, 133}, ++{245, 72, 137}, ++{245, 72, 137}, ++{123, 72, 92}, ++{134, 71, 97}, ++{148, 69, 104}, ++{163, 66, 110}, ++{177, 62, 117}, ++{192, 58, 122}, ++{207, 53, 128}, ++{207, 53, 128}, ++{123, 72, 92}, ++{134, 71, 98}, ++{148, 69, 104}, ++{163, 66, 110}, ++{177, 62, 117}, ++{192, 58, 122}, ++{207, 53, 128}, ++{207, 53, 128}, ++{124, 72, 92}, ++{135, 72, 98}, ++{149, 70, 104}, ++{163, 66, 111}, ++{178, 62, 117}, ++{193, 58, 122}, ++{207, 53, 128}, ++{207, 53, 128}, ++{124, 73, 92}, ++{136, 72, 98}, ++{149, 70, 104}, ++{164, 67, 111}, ++{178, 63, 117}, ++{193, 58, 122}, ++{208, 54, 128}, ++{208, 54, 128}, ++{125, 74, 93}, ++{137, 73, 98}, ++{150, 71, 105}, ++{164, 67, 111}, ++{179, 63, 117}, ++{194, 59, 123}, ++{208, 54, 128}, ++{208, 54, 128}, ++{127, 75, 93}, ++{138, 74, 99}, ++{151, 71, 105}, ++{165, 68, 111}, ++{180, 63, 117}, ++{194, 59, 123}, ++{209, 54, 128}, ++{209, 54, 128}, ++{128, 76, 94}, ++{139, 75, 99}, ++{152, 72, 105}, ++{166, 68, 112}, ++{181, 64, 117}, ++{195, 59, 123}, ++{209, 55, 128}, ++{209, 55, 128}, ++{130, 78, 95}, ++{141, 76, 100}, ++{154, 73, 106}, ++{167, 69, 112}, ++{182, 65, 118}, ++{196, 60, 123}, ++{210, 55, 128}, ++{210, 55, 128}, ++{132, 79, 96}, ++{142, 77, 101}, ++{155, 74, 106}, ++{169, 70, 112}, ++{183, 65, 118}, ++{197, 60, 123}, ++{211, 56, 129}, ++{211, 56, 129}, ++{134, 81, 96}, ++{144, 78, 101}, ++{157, 75, 107}, ++{170, 71, 113}, ++{184, 66, 118}, ++{198, 61, 124}, ++{212, 56, 129}, ++{212, 56, 129}, ++{137, 82, 97}, ++{146, 79, 102}, ++{159, 76, 108}, ++{172, 71, 113}, ++{186, 67, 119}, ++{200, 62, 124}, ++{214, 57, 129}, ++{214, 57, 129}, ++{139, 84, 98}, ++{149, 81, 103}, ++{161, 77, 108}, ++{174, 72, 114}, ++{187, 67, 119}, ++{201, 62, 124}, ++{215, 57, 129}, ++{215, 57, 129}, ++{141, 85, 99}, ++{151, 82, 104}, ++{163, 78, 109}, ++{175, 73, 114}, ++{189, 68, 120}, ++{203, 63, 125}, ++{216, 58, 129}, ++{216, 58, 129}, ++{144, 86, 100}, ++{153, 83, 104}, ++{165, 79, 109}, ++{177, 74, 115}, ++{191, 69, 120}, ++{204, 64, 125}, ++{218, 59, 130}, ++{218, 59, 130}, ++{147, 88, 101}, ++{156, 85, 105}, ++{167, 80, 110}, ++{179, 75, 115}, ++{193, 70, 120}, ++{206, 65, 125}, ++{219, 59, 130}, ++{219, 59, 130}, ++{150, 89, 102}, ++{158, 86, 106}, ++{169, 81, 111}, ++{182, 76, 116}, ++{194, 71, 121}, ++{208, 66, 126}, ++{221, 60, 130}, ++{221, 60, 130}, ++{153, 91, 103}, ++{161, 87, 107}, ++{172, 82, 112}, ++{184, 77, 116}, ++{196, 72, 121}, ++{209, 66, 126}, ++{223, 61, 131}, ++{223, 61, 131}, ++{156, 92, 104}, ++{164, 88, 108}, ++{174, 84, 112}, ++{186, 78, 117}, ++{199, 73, 122}, ++{211, 67, 126}, ++{224, 62, 131}, ++{224, 62, 131}, ++{159, 93, 105}, ++{167, 89, 109}, ++{177, 85, 113}, ++{189, 79, 118}, ++{201, 74, 122}, ++{213, 68, 127}, ++{226, 63, 131}, ++{226, 63, 131}, ++{162, 95, 106}, ++{170, 91, 110}, ++{180, 86, 114}, ++{191, 80, 118}, ++{203, 75, 123}, ++{215, 69, 127}, ++{228, 63, 132}, ++{228, 63, 132}, ++{165, 96, 107}, ++{173, 92, 111}, ++{182, 87, 115}, ++{193, 81, 119}, ++{205, 76, 123}, ++{218, 70, 128}, ++{230, 64, 132}, ++{230, 64, 132}, ++{168, 97, 108}, ++{176, 93, 111}, ++{185, 88, 115}, ++{196, 82, 119}, ++{208, 77, 124}, ++{220, 71, 128}, ++{232, 65, 132}, ++{232, 65, 132}, ++{171, 98, 109}, ++{179, 94, 112}, ++{188, 89, 116}, ++{199, 83, 120}, ++{210, 78, 124}, ++{222, 72, 129}, ++{234, 66, 133}, ++{234, 66, 133}, ++{175, 99, 110}, ++{182, 95, 113}, ++{191, 90, 117}, ++{201, 84, 121}, ++{213, 79, 125}, ++{224, 73, 129}, ++{236, 67, 133}, ++{236, 67, 133}, ++{178, 100, 111}, ++{185, 96, 114}, ++{194, 91, 117}, ++{204, 85, 121}, ++{215, 79, 125}, ++{227, 74, 129}, ++{239, 68, 133}, ++{239, 68, 133}, ++{181, 101, 112}, ++{188, 97, 115}, ++{197, 92, 118}, ++{207, 86, 122}, ++{218, 80, 126}, ++{229, 74, 130}, ++{241, 69, 134}, ++{241, 69, 134}, ++{185, 102, 113}, ++{191, 98, 116}, ++{200, 93, 119}, ++{210, 87, 123}, ++{220, 81, 126}, ++{232, 75, 130}, ++{243, 69, 134}, ++{243, 69, 134}, ++{188, 103, 114}, ++{195, 99, 116}, ++{203, 94, 120}, ++{213, 88, 123}, ++{223, 82, 127}, ++{234, 76, 131}, ++{246, 70, 135}, ++{246, 70, 135}, ++{190, 103, 114}, ++{196, 99, 117}, ++{205, 94, 120}, ++{214, 89, 124}, ++{225, 83, 127}, ++{235, 77, 131}, ++{247, 71, 135}, ++{247, 71, 135}, ++{190, 103, 114}, ++{196, 99, 117}, ++{205, 94, 120}, ++{214, 89, 124}, ++{225, 83, 127}, ++{235, 77, 131}, ++{247, 71, 135}, ++{247, 71, 135}, ++{190, 103, 114}, ++{196, 99, 117}, ++{205, 94, 120}, ++{214, 89, 124}, ++{225, 83, 127}, ++{235, 77, 131}, ++{247, 71, 135}, ++{247, 71, 135}, ++{190, 103, 114}, ++{196, 99, 117}, ++{205, 94, 120}, ++{214, 89, 124}, ++{225, 83, 127}, ++{235, 77, 131}, ++{247, 71, 135}, ++{247, 71, 135}, ++{126, 69, 90}, ++{137, 69, 95}, ++{150, 67, 102}, ++{165, 64, 108}, ++{179, 61, 114}, ++{194, 57, 120}, ++{208, 52, 126}, ++{208, 52, 126}, ++{126, 70, 90}, ++{137, 69, 95}, ++{150, 67, 102}, ++{165, 65, 108}, ++{179, 61, 114}, ++{194, 57, 120}, ++{209, 52, 126}, ++{209, 52, 126}, ++{126, 70, 90}, ++{137, 70, 96}, ++{151, 68, 102}, ++{165, 65, 108}, ++{180, 61, 115}, ++{194, 57, 120}, ++{209, 52, 126}, ++{209, 52, 126}, ++{127, 71, 90}, ++{138, 70, 96}, ++{151, 68, 102}, ++{166, 65, 109}, ++{180, 61, 115}, ++{195, 57, 120}, ++{209, 53, 126}, ++{209, 53, 126}, ++{128, 72, 91}, ++{139, 71, 96}, ++{152, 69, 103}, ++{166, 66, 109}, ++{181, 62, 115}, ++{195, 57, 121}, ++{210, 53, 126}, ++{210, 53, 126}, ++{129, 73, 91}, ++{140, 72, 97}, ++{153, 69, 103}, ++{167, 66, 109}, ++{182, 62, 115}, ++{196, 58, 121}, ++{210, 53, 126}, ++{210, 53, 126}, ++{131, 74, 92}, ++{142, 73, 97}, ++{154, 70, 103}, ++{168, 67, 109}, ++{183, 63, 115}, ++{197, 58, 121}, ++{211, 54, 126}, ++{211, 54, 126}, ++{133, 75, 93}, ++{143, 74, 98}, ++{156, 71, 104}, ++{169, 67, 110}, ++{184, 63, 116}, ++{198, 59, 121}, ++{212, 54, 126}, ++{212, 54, 126}, ++{135, 77, 93}, ++{145, 75, 98}, ++{157, 72, 104}, ++{171, 68, 110}, ++{185, 64, 116}, ++{199, 59, 121}, ++{213, 55, 127}, ++{213, 55, 127}, ++{137, 78, 94}, ++{147, 76, 99}, ++{159, 73, 105}, ++{172, 69, 111}, ++{186, 65, 116}, ++{200, 60, 122}, ++{214, 55, 127}, ++{214, 55, 127}, ++{139, 80, 95}, ++{149, 77, 100}, ++{161, 74, 105}, ++{174, 70, 111}, ++{187, 65, 117}, ++{201, 61, 122}, ++{215, 56, 127}, ++{215, 56, 127}, ++{141, 81, 96}, ++{151, 79, 101}, ++{163, 75, 106}, ++{176, 71, 112}, ++{189, 66, 117}, ++{203, 61, 122}, ++{216, 56, 127}, ++{216, 56, 127}, ++{144, 83, 97}, ++{153, 80, 102}, ++{165, 76, 107}, ++{177, 72, 112}, ++{191, 67, 117}, ++{204, 62, 123}, ++{218, 57, 128}, ++{218, 57, 128}, ++{146, 84, 98}, ++{156, 81, 102}, ++{167, 77, 107}, ++{179, 73, 113}, ++{192, 68, 118}, ++{206, 63, 123}, ++{219, 58, 128}, ++{219, 58, 128}, ++{149, 86, 99}, ++{158, 83, 103}, ++{169, 78, 108}, ++{181, 74, 113}, ++{194, 69, 118}, ++{207, 64, 123}, ++{221, 58, 128}, ++{221, 58, 128}, ++{152, 87, 100}, ++{161, 84, 104}, ++{171, 80, 109}, ++{183, 75, 114}, ++{196, 70, 119}, ++{209, 64, 124}, ++{222, 59, 128}, ++{222, 59, 128}, ++{155, 89, 101}, ++{163, 85, 105}, ++{174, 81, 110}, ++{186, 76, 114}, ++{198, 71, 119}, ++{211, 65, 124}, ++{224, 60, 129}, ++{224, 60, 129}, ++{158, 90, 102}, ++{166, 86, 106}, ++{176, 82, 110}, ++{188, 77, 115}, ++{200, 72, 120}, ++{213, 66, 125}, ++{226, 61, 129}, ++{226, 61, 129}, ++{161, 91, 103}, ++{169, 88, 107}, ++{179, 83, 111}, ++{190, 78, 116}, ++{202, 73, 120}, ++{215, 67, 125}, ++{228, 62, 129}, ++{228, 62, 129}, ++{164, 93, 104}, ++{172, 89, 108}, ++{182, 84, 112}, ++{193, 79, 116}, ++{205, 74, 121}, ++{217, 68, 125}, ++{230, 62, 130}, ++{230, 62, 130}, ++{167, 94, 105}, ++{175, 90, 109}, ++{184, 85, 113}, ++{195, 80, 117}, ++{207, 74, 121}, ++{219, 69, 126}, ++{232, 63, 130}, ++{232, 63, 130}, ++{170, 95, 106}, ++{178, 91, 109}, ++{187, 86, 113}, ++{198, 81, 118}, ++{209, 75, 122}, ++{221, 70, 126}, ++{234, 64, 131}, ++{234, 64, 131}, ++{173, 96, 107}, ++{181, 92, 110}, ++{190, 87, 114}, ++{200, 82, 118}, ++{212, 76, 122}, ++{224, 71, 127}, ++{236, 65, 131}, ++{236, 65, 131}, ++{177, 97, 108}, ++{184, 93, 111}, ++{193, 88, 115}, ++{203, 83, 119}, ++{214, 77, 123}, ++{226, 72, 127}, ++{238, 66, 131}, ++{238, 66, 131}, ++{180, 98, 109}, ++{187, 94, 112}, ++{196, 89, 116}, ++{206, 84, 119}, ++{217, 78, 124}, ++{228, 73, 128}, ++{240, 67, 132}, ++{240, 67, 132}, ++{183, 99, 110}, ++{190, 95, 113}, ++{199, 90, 116}, ++{209, 85, 120}, ++{219, 79, 124}, ++{231, 73, 128}, ++{242, 68, 132}, ++{242, 68, 132}, ++{187, 100, 111}, ++{193, 96, 114}, ++{202, 91, 117}, ++{211, 86, 121}, ++{222, 80, 125}, ++{233, 74, 129}, ++{245, 68, 132}, ++{245, 68, 132}, ++{190, 101, 112}, ++{196, 97, 115}, ++{205, 92, 118}, ++{214, 87, 121}, ++{225, 81, 125}, ++{236, 75, 129}, ++{247, 69, 133}, ++{247, 69, 133}, ++{192, 102, 113}, ++{198, 98, 115}, ++{206, 93, 118}, ++{216, 87, 122}, ++{226, 82, 125}, ++{237, 76, 129}, ++{248, 70, 133}, ++{248, 70, 133}, ++{192, 102, 113}, ++{198, 98, 115}, ++{206, 93, 118}, ++{216, 87, 122}, ++{226, 82, 125}, ++{237, 76, 129}, ++{248, 70, 133}, ++{248, 70, 133}, ++{192, 102, 113}, ++{198, 98, 115}, ++{206, 93, 118}, ++{216, 87, 122}, ++{226, 82, 125}, ++{237, 76, 129}, ++{248, 70, 133}, ++{248, 70, 133}, ++{192, 102, 113}, ++{198, 98, 115}, ++{206, 93, 118}, ++{216, 87, 122}, ++{226, 82, 125}, ++{237, 76, 129}, ++{248, 70, 133}, ++{248, 70, 133}, ++{128, 67, 87}, ++{139, 67, 93}, ++{153, 65, 100}, ++{167, 63, 106}, ++{181, 59, 112}, ++{196, 55, 118}, ++{210, 51, 124}, ++{210, 51, 124}, ++{128, 67, 88}, ++{140, 67, 93}, ++{153, 66, 100}, ++{167, 63, 106}, ++{181, 59, 112}, ++{196, 55, 118}, ++{210, 51, 124}, ++{210, 51, 124}, ++{129, 68, 88}, ++{140, 67, 93}, ++{153, 66, 100}, ++{167, 63, 106}, ++{182, 60, 112}, ++{196, 56, 118}, ++{210, 51, 124}, ++{210, 51, 124}, ++{130, 68, 88}, ++{141, 68, 94}, ++{154, 66, 100}, ++{168, 63, 106}, ++{182, 60, 113}, ++{196, 56, 118}, ++{211, 52, 124}, ++{211, 52, 124}, ++{131, 69, 89}, ++{142, 69, 94}, ++{155, 67, 100}, ++{168, 64, 107}, ++{183, 60, 113}, ++{197, 56, 118}, ++{211, 52, 124}, ++{211, 52, 124}, ++{132, 70, 89}, ++{143, 70, 95}, ++{156, 67, 101}, ++{169, 64, 107}, ++{183, 61, 113}, ++{198, 57, 119}, ++{212, 52, 124}, ++{212, 52, 124}, ++{134, 72, 90}, ++{144, 70, 95}, ++{157, 68, 101}, ++{170, 65, 107}, ++{184, 61, 113}, ++{199, 57, 119}, ++{213, 53, 124}, ++{213, 53, 124}, ++{135, 73, 91}, ++{146, 72, 96}, ++{158, 69, 102}, ++{172, 66, 108}, ++{185, 62, 114}, ++{200, 58, 119}, ++{214, 53, 124}, ++{214, 53, 124}, ++{137, 74, 91}, ++{147, 73, 96}, ++{160, 70, 102}, ++{173, 67, 108}, ++{187, 63, 114}, ++{201, 58, 119}, ++{215, 54, 125}, ++{215, 54, 125}, ++{139, 76, 92}, ++{149, 74, 97}, ++{161, 71, 103}, ++{174, 67, 109}, ++{188, 63, 114}, ++{202, 59, 120}, ++{216, 54, 125}, ++{216, 54, 125}, ++{141, 77, 93}, ++{151, 75, 98}, ++{163, 72, 103}, ++{176, 68, 109}, ++{189, 64, 115}, ++{203, 59, 120}, ++{217, 55, 125}, ++{217, 55, 125}, ++{144, 79, 94}, ++{153, 77, 99}, ++{165, 73, 104}, ++{178, 69, 109}, ++{191, 65, 115}, ++{204, 60, 120}, ++{218, 55, 125}, ++{218, 55, 125}, ++{146, 80, 95}, ++{155, 78, 99}, ++{167, 74, 105}, ++{179, 70, 110}, ++{192, 66, 115}, ++{206, 61, 121}, ++{219, 56, 126}, ++{219, 56, 126}, ++{149, 82, 96}, ++{158, 79, 100}, ++{169, 76, 105}, ++{181, 71, 111}, ++{194, 67, 116}, ++{207, 62, 121}, ++{221, 57, 126}, ++{221, 57, 126}, ++{151, 83, 97}, ++{160, 81, 101}, ++{171, 77, 106}, ++{183, 72, 111}, ++{196, 67, 116}, ++{209, 63, 121}, ++{222, 57, 126}, ++{222, 57, 126}, ++{154, 85, 98}, ++{163, 82, 102}, ++{173, 78, 107}, ++{185, 73, 112}, ++{198, 68, 117}, ++{211, 63, 122}, ++{224, 58, 127}, ++{224, 58, 127}, ++{157, 86, 99}, ++{165, 83, 103}, ++{176, 79, 107}, ++{187, 74, 112}, ++{200, 69, 117}, ++{213, 64, 122}, ++{226, 59, 127}, ++{226, 59, 127}, ++{160, 88, 100}, ++{168, 84, 104}, ++{178, 80, 108}, ++{190, 75, 113}, ++{202, 70, 118}, ++{215, 65, 123}, ++{227, 60, 127}, ++{227, 60, 127}, ++{163, 89, 101}, ++{171, 86, 105}, ++{181, 81, 109}, ++{192, 76, 114}, ++{204, 71, 118}, ++{217, 66, 123}, ++{229, 61, 128}, ++{229, 61, 128}, ++{166, 91, 102}, ++{174, 87, 106}, ++{183, 83, 110}, ++{194, 78, 114}, ++{206, 72, 119}, ++{219, 67, 123}, ++{231, 61, 128}, ++{231, 61, 128}, ++{169, 92, 103}, ++{177, 88, 107}, ++{186, 84, 111}, ++{197, 79, 115}, ++{209, 73, 119}, ++{221, 68, 124}, ++{233, 62, 128}, ++{233, 62, 128}, ++{172, 93, 104}, ++{179, 89, 107}, ++{189, 85, 111}, ++{199, 80, 116}, ++{211, 74, 120}, ++{223, 69, 124}, ++{235, 63, 129}, ++{235, 63, 129}, ++{175, 94, 105}, ++{182, 90, 108}, ++{192, 86, 112}, ++{202, 81, 116}, ++{213, 75, 121}, ++{225, 70, 125}, ++{237, 64, 129}, ++{237, 64, 129}, ++{179, 95, 106}, ++{186, 92, 109}, ++{194, 87, 113}, ++{205, 82, 117}, ++{216, 76, 121}, ++{227, 71, 125}, ++{239, 65, 130}, ++{239, 65, 130}, ++{182, 96, 107}, ++{189, 93, 110}, ++{197, 88, 114}, ++{207, 83, 118}, ++{218, 77, 122}, ++{230, 71, 126}, ++{241, 66, 130}, ++{241, 66, 130}, ++{185, 97, 108}, ++{192, 94, 111}, ++{200, 89, 114}, ++{210, 84, 118}, ++{221, 78, 122}, ++{232, 72, 126}, ++{244, 67, 130}, ++{244, 67, 130}, ++{188, 98, 109}, ++{195, 95, 112}, ++{203, 90, 115}, ++{213, 85, 119}, ++{223, 79, 123}, ++{234, 73, 127}, ++{246, 68, 131}, ++{246, 68, 131}, ++{192, 99, 110}, ++{198, 96, 113}, ++{206, 91, 116}, ++{216, 86, 120}, ++{226, 80, 123}, ++{237, 74, 127}, ++{248, 68, 131}, ++{248, 68, 131}, ++{194, 100, 111}, ++{200, 96, 113}, ++{208, 91, 116}, ++{217, 86, 120}, ++{227, 80, 124}, ++{238, 75, 128}, ++{249, 69, 131}, ++{249, 69, 131}, ++{194, 100, 111}, ++{200, 96, 113}, ++{208, 91, 116}, ++{217, 86, 120}, ++{227, 80, 124}, ++{238, 75, 128}, ++{249, 69, 131}, ++{249, 69, 131}, ++{194, 100, 111}, ++{200, 96, 113}, ++{208, 91, 116}, ++{217, 86, 120}, ++{227, 80, 124}, ++{238, 75, 128}, ++{249, 69, 131}, ++{249, 69, 131}, ++{194, 100, 111}, ++{200, 96, 113}, ++{208, 91, 116}, ++{217, 86, 120}, ++{227, 80, 124}, ++{238, 75, 128}, ++{249, 69, 131}, ++{249, 69, 131}, ++{131, 64, 85}, ++{142, 65, 91}, ++{155, 64, 98}, ++{169, 61, 104}, ++{183, 58, 110}, ++{197, 54, 116}, ++{212, 50, 122}, ++{212, 50, 122}, ++{131, 65, 86}, ++{142, 65, 91}, ++{155, 64, 98}, ++{169, 61, 104}, ++{183, 58, 110}, ++{198, 54, 116}, ++{212, 50, 122}, ++{212, 50, 122}, ++{132, 65, 86}, ++{142, 65, 91}, ++{155, 64, 98}, ++{169, 61, 104}, ++{184, 58, 110}, ++{198, 54, 116}, ++{212, 50, 122}, ++{212, 50, 122}, ++{133, 66, 86}, ++{143, 66, 92}, ++{156, 64, 98}, ++{170, 62, 104}, ++{184, 58, 110}, ++{198, 55, 116}, ++{212, 50, 122}, ++{212, 50, 122}, ++{134, 67, 87}, ++{144, 66, 92}, ++{157, 65, 98}, ++{171, 62, 105}, ++{185, 59, 111}, ++{199, 55, 116}, ++{213, 51, 122}, ++{213, 51, 122}, ++{135, 68, 87}, ++{145, 67, 93}, ++{158, 66, 99}, ++{171, 63, 105}, ++{185, 59, 111}, ++{199, 55, 117}, ++{214, 51, 122}, ++{214, 51, 122}, ++{136, 69, 88}, ++{146, 68, 93}, ++{159, 66, 99}, ++{172, 63, 105}, ++{186, 60, 111}, ++{200, 56, 117}, ++{214, 51, 122}, ++{214, 51, 122}, ++{138, 71, 89}, ++{148, 69, 94}, ++{160, 67, 100}, ++{174, 64, 106}, ++{187, 60, 111}, ++{201, 56, 117}, ++{215, 52, 122}, ++{215, 52, 122}, ++{140, 72, 89}, ++{150, 71, 94}, ++{162, 68, 100}, ++{175, 65, 106}, ++{188, 61, 112}, ++{202, 57, 117}, ++{216, 52, 123}, ++{216, 52, 123}, ++{142, 73, 90}, ++{151, 72, 95}, ++{163, 69, 101}, ++{176, 66, 106}, ++{190, 62, 112}, ++{203, 58, 118}, ++{217, 53, 123}, ++{217, 53, 123}, ++{144, 75, 91}, ++{153, 73, 96}, ++{165, 70, 101}, ++{178, 67, 107}, ++{191, 63, 113}, ++{205, 58, 118}, ++{218, 54, 123}, ++{218, 54, 123}, ++{146, 77, 92}, ++{155, 74, 97}, ++{167, 71, 102}, ++{179, 68, 107}, ++{193, 63, 113}, ++{206, 59, 118}, ++{220, 54, 123}, ++{220, 54, 123}, ++{149, 78, 93}, ++{158, 76, 97}, ++{169, 73, 103}, ++{181, 69, 108}, ++{194, 64, 113}, ++{208, 60, 119}, ++{221, 55, 124}, ++{221, 55, 124}, ++{151, 80, 94}, ++{160, 77, 98}, ++{171, 74, 103}, ++{183, 70, 109}, ++{196, 65, 114}, ++{209, 61, 119}, ++{222, 56, 124}, ++{222, 56, 124}, ++{154, 81, 95}, ++{162, 79, 99}, ++{173, 75, 104}, ++{185, 71, 109}, ++{198, 66, 114}, ++{211, 61, 119}, ++{224, 56, 124}, ++{224, 56, 124}, ++{156, 83, 96}, ++{165, 80, 100}, ++{175, 76, 105}, ++{187, 72, 110}, ++{200, 67, 115}, ++{212, 62, 120}, ++{225, 57, 125}, ++{225, 57, 125}, ++{159, 84, 97}, ++{167, 81, 101}, ++{178, 77, 105}, ++{189, 73, 110}, ++{202, 68, 115}, ++{214, 63, 120}, ++{227, 58, 125}, ++{227, 58, 125}, ++{162, 86, 98}, ++{170, 83, 102}, ++{180, 79, 106}, ++{192, 74, 111}, ++{204, 69, 116}, ++{216, 64, 121}, ++{229, 59, 125}, ++{229, 59, 125}, ++{165, 87, 99}, ++{173, 84, 103}, ++{183, 80, 107}, ++{194, 75, 112}, ++{206, 70, 116}, ++{218, 65, 121}, ++{231, 60, 126}, ++{231, 60, 126}, ++{168, 88, 100}, ++{176, 85, 104}, ++{185, 81, 108}, ++{196, 76, 112}, ++{208, 71, 117}, ++{220, 66, 122}, ++{233, 60, 126}, ++{233, 60, 126}, ++{171, 90, 101}, ++{178, 86, 105}, ++{188, 82, 109}, ++{199, 77, 113}, ++{210, 72, 118}, ++{222, 67, 122}, ++{234, 61, 127}, ++{234, 61, 127}, ++{174, 91, 102}, ++{181, 88, 105}, ++{191, 83, 109}, ++{201, 78, 114}, ++{213, 73, 118}, ++{224, 68, 123}, ++{236, 62, 127}, ++{236, 62, 127}, ++{177, 92, 103}, ++{184, 89, 106}, ++{193, 84, 110}, ++{204, 79, 114}, ++{215, 74, 119}, ++{227, 69, 123}, ++{239, 63, 127}, ++{239, 63, 127}, ++{181, 93, 104}, ++{187, 90, 107}, ++{196, 85, 111}, ++{206, 80, 115}, ++{217, 75, 119}, ++{229, 69, 124}, ++{241, 64, 128}, ++{241, 64, 128}, ++{184, 95, 105}, ++{190, 91, 108}, ++{199, 86, 112}, ++{209, 81, 116}, ++{220, 76, 120}, ++{231, 70, 124}, ++{243, 65, 128}, ++{243, 65, 128}, ++{187, 96, 106}, ++{194, 92, 109}, ++{202, 87, 113}, ++{212, 82, 116}, ++{222, 77, 120}, ++{234, 71, 125}, ++{245, 66, 129}, ++{245, 66, 129}, ++{190, 97, 107}, ++{197, 93, 110}, ++{205, 88, 113}, ++{215, 83, 117}, ++{225, 78, 121}, ++{236, 72, 125}, ++{247, 67, 129}, ++{247, 67, 129}, ++{194, 98, 108}, ++{200, 94, 111}, ++{208, 89, 114}, ++{217, 84, 118}, ++{228, 79, 122}, ++{238, 73, 126}, ++{250, 67, 129}, ++{250, 67, 129}, ++{195, 98, 109}, ++{201, 95, 111}, ++{209, 90, 114}, ++{219, 85, 118}, ++{229, 79, 122}, ++{240, 74, 126}, ++{251, 68, 130}, ++{251, 68, 130}, ++{195, 98, 109}, ++{201, 95, 111}, ++{209, 90, 114}, ++{219, 85, 118}, ++{229, 79, 122}, ++{240, 74, 126}, ++{251, 68, 130}, ++{251, 68, 130}, ++{195, 98, 109}, ++{201, 95, 111}, ++{209, 90, 114}, ++{219, 85, 118}, ++{229, 79, 122}, ++{240, 74, 126}, ++{251, 68, 130}, ++{251, 68, 130}, ++{195, 98, 109}, ++{201, 95, 111}, ++{209, 90, 114}, ++{219, 85, 118}, ++{229, 79, 122}, ++{240, 74, 126}, ++{251, 68, 130}, ++{251, 68, 130}, ++{134, 62, 83}, ++{144, 62, 89}, ++{157, 62, 95}, ++{171, 59, 102}, ++{185, 56, 108}, ++{199, 53, 114}, ++{213, 49, 120}, ++{213, 49, 120}, ++{134, 62, 84}, ++{145, 63, 89}, ++{157, 62, 96}, ++{171, 60, 102}, ++{185, 57, 108}, ++{199, 53, 114}, ++{213, 49, 120}, ++{213, 49, 120}, ++{134, 63, 84}, ++{145, 63, 89}, ++{158, 62, 96}, ++{171, 60, 102}, ++{185, 57, 108}, ++{200, 53, 114}, ++{214, 49, 120}, ++{214, 49, 120}, ++{135, 63, 84}, ++{146, 64, 90}, ++{158, 62, 96}, ++{172, 60, 102}, ++{186, 57, 108}, ++{200, 53, 114}, ++{214, 49, 120}, ++{214, 49, 120}, ++{136, 64, 85}, ++{147, 64, 90}, ++{159, 63, 96}, ++{173, 61, 102}, ++{187, 57, 109}, ++{201, 54, 114}, ++{215, 50, 120}, ++{215, 50, 120}, ++{137, 66, 85}, ++{148, 65, 90}, ++{160, 64, 97}, ++{173, 61, 103}, ++{187, 58, 109}, ++{201, 54, 115}, ++{215, 50, 120}, ++{215, 50, 120}, ++{139, 67, 86}, ++{149, 66, 91}, ++{161, 64, 97}, ++{174, 62, 103}, ++{188, 58, 109}, ++{202, 55, 115}, ++{216, 50, 120}, ++{216, 50, 120}, ++{141, 68, 87}, ++{150, 67, 92}, ++{162, 65, 97}, ++{176, 63, 103}, ++{189, 59, 109}, ++{203, 55, 115}, ++{217, 51, 120}, ++{217, 51, 120}, ++{142, 70, 87}, ++{152, 68, 92}, ++{164, 66, 98}, ++{177, 63, 104}, ++{190, 60, 110}, ++{204, 56, 115}, ++{218, 51, 121}, ++{218, 51, 121}, ++{144, 71, 88}, ++{154, 70, 93}, ++{165, 67, 99}, ++{178, 64, 104}, ++{192, 60, 110}, ++{205, 56, 116}, ++{219, 52, 121}, ++{219, 52, 121}, ++{146, 73, 89}, ++{156, 71, 94}, ++{167, 68, 99}, ++{180, 65, 105}, ++{193, 61, 110}, ++{206, 57, 116}, ++{220, 53, 121}, ++{220, 53, 121}, ++{149, 74, 90}, ++{158, 72, 95}, ++{169, 70, 100}, ++{181, 66, 105}, ++{194, 62, 111}, ++{208, 58, 116}, ++{221, 53, 121}, ++{221, 53, 121}, ++{151, 76, 91}, ++{160, 74, 95}, ++{171, 71, 100}, ++{183, 67, 106}, ++{196, 63, 111}, ++{209, 58, 117}, ++{223, 54, 122}, ++{223, 54, 122}, ++{154, 77, 92}, ++{162, 75, 96}, ++{173, 72, 101}, ++{185, 68, 107}, ++{198, 64, 112}, ++{211, 59, 117}, ++{224, 55, 122}, ++{224, 55, 122}, ++{156, 79, 93}, ++{165, 77, 97}, ++{175, 73, 102}, ++{187, 69, 107}, ++{200, 65, 112}, ++{212, 60, 117}, ++{225, 55, 122}, ++{225, 55, 122}, ++{159, 81, 94}, ++{167, 78, 98}, ++{177, 74, 103}, ++{189, 70, 108}, ++{201, 66, 113}, ++{214, 61, 118}, ++{227, 56, 123}, ++{227, 56, 123}, ++{161, 82, 95}, ++{170, 79, 99}, ++{180, 76, 103}, ++{191, 71, 108}, ++{203, 67, 113}, ++{216, 62, 118}, ++{229, 57, 123}, ++{229, 57, 123}, ++{164, 84, 96}, ++{172, 81, 100}, ++{182, 77, 104}, ++{193, 72, 109}, ++{205, 68, 114}, ++{218, 63, 119}, ++{230, 58, 123}, ++{230, 58, 123}, ++{167, 85, 97}, ++{175, 82, 101}, ++{185, 78, 105}, ++{196, 73, 110}, ++{207, 69, 114}, ++{220, 64, 119}, ++{232, 59, 124}, ++{232, 59, 124}, ++{170, 86, 98}, ++{178, 83, 102}, ++{187, 79, 106}, ++{198, 75, 110}, ++{210, 70, 115}, ++{222, 65, 120}, ++{234, 59, 124}, ++{234, 59, 124}, ++{173, 88, 99}, ++{180, 85, 103}, ++{190, 80, 107}, ++{200, 76, 111}, ++{212, 71, 116}, ++{224, 66, 120}, ++{236, 60, 125}, ++{236, 60, 125}, ++{176, 89, 100}, ++{183, 86, 103}, ++{192, 82, 107}, ++{203, 77, 112}, ++{214, 72, 116}, ++{226, 66, 121}, ++{238, 61, 125}, ++{238, 61, 125}, ++{179, 90, 101}, ++{186, 87, 104}, ++{195, 83, 108}, ++{205, 78, 112}, ++{217, 73, 117}, ++{228, 67, 121}, ++{240, 62, 126}, ++{240, 62, 126}, ++{182, 92, 102}, ++{189, 88, 105}, ++{198, 84, 109}, ++{208, 79, 113}, ++{219, 74, 117}, ++{230, 68, 122}, ++{242, 63, 126}, ++{242, 63, 126}, ++{186, 93, 103}, ++{192, 89, 106}, ++{201, 85, 110}, ++{211, 80, 114}, ++{221, 75, 118}, ++{233, 69, 122}, ++{244, 64, 126}, ++{244, 64, 126}, ++{189, 94, 104}, ++{195, 90, 107}, ++{204, 86, 111}, ++{213, 81, 115}, ++{224, 76, 119}, ++{235, 70, 123}, ++{246, 65, 127}, ++{246, 65, 127}, ++{192, 95, 105}, ++{198, 91, 108}, ++{207, 87, 111}, ++{216, 82, 115}, ++{227, 77, 119}, ++{237, 71, 123}, ++{249, 66, 127}, ++{249, 66, 127}, ++{195, 96, 106}, ++{202, 92, 109}, ++{210, 88, 112}, ++{219, 83, 116}, ++{229, 78, 120}, ++{240, 72, 124}, ++{251, 66, 128}, ++{251, 66, 128}, ++{197, 96, 107}, ++{203, 93, 109}, ++{211, 88, 113}, ++{220, 83, 116}, ++{230, 78, 120}, ++{241, 73, 124}, ++{252, 67, 128}, ++{252, 67, 128}, ++{197, 96, 107}, ++{203, 93, 109}, ++{211, 88, 113}, ++{220, 83, 116}, ++{230, 78, 120}, ++{241, 73, 124}, ++{252, 67, 128}, ++{252, 67, 128}, ++{197, 96, 107}, ++{203, 93, 109}, ++{211, 88, 113}, ++{220, 83, 116}, ++{230, 78, 120}, ++{241, 73, 124}, ++{252, 67, 128}, ++{252, 67, 128}, ++{197, 96, 107}, ++{203, 93, 109}, ++{211, 88, 113}, ++{220, 83, 116}, ++{230, 78, 120}, ++{241, 73, 124}, ++{252, 67, 128}, ++{252, 67, 128}, ++{137, 60, 82}, ++{147, 60, 87}, ++{159, 60, 93}, ++{173, 58, 100}, ++{187, 55, 106}, ++{201, 52, 112}, ++{215, 48, 118}, ++{215, 48, 118}, ++{137, 60, 82}, ++{147, 60, 87}, ++{160, 60, 93}, ++{173, 58, 100}, ++{187, 55, 106}, ++{201, 52, 112}, ++{215, 48, 118}, ++{215, 48, 118}, ++{137, 60, 82}, ++{147, 61, 87}, ++{160, 60, 94}, ++{173, 58, 100}, ++{187, 55, 106}, ++{201, 52, 112}, ++{215, 48, 118}, ++{215, 48, 118}, ++{138, 61, 82}, ++{148, 61, 88}, ++{161, 60, 94}, ++{174, 58, 100}, ++{188, 56, 106}, ++{202, 52, 112}, ++{216, 48, 118}, ++{216, 48, 118}, ++{139, 62, 83}, ++{149, 62, 88}, ++{161, 61, 94}, ++{175, 59, 100}, ++{188, 56, 107}, ++{202, 52, 112}, ++{216, 48, 118}, ++{216, 48, 118}, ++{140, 63, 83}, ++{150, 63, 88}, ++{162, 62, 94}, ++{176, 59, 101}, ++{189, 56, 107}, ++{203, 53, 113}, ++{217, 49, 118}, ++{217, 49, 118}, ++{142, 64, 84}, ++{151, 64, 89}, ++{163, 63, 95}, ++{176, 60, 101}, ++{190, 57, 107}, ++{204, 53, 113}, ++{218, 49, 118}, ++{218, 49, 118}, ++{143, 66, 85}, ++{153, 65, 90}, ++{165, 63, 95}, ++{178, 61, 101}, ++{191, 58, 107}, ++{205, 54, 113}, ++{218, 50, 118}, ++{218, 50, 118}, ++{145, 67, 85}, ++{154, 66, 90}, ++{166, 64, 96}, ++{179, 62, 102}, ++{192, 58, 108}, ++{206, 54, 113}, ++{219, 50, 119}, ++{219, 50, 119}, ++{147, 69, 86}, ++{156, 68, 91}, ++{168, 65, 97}, ++{180, 63, 102}, ++{193, 59, 108}, ++{207, 55, 114}, ++{220, 51, 119}, ++{220, 51, 119}, ++{149, 70, 87}, ++{158, 69, 92}, ++{169, 67, 97}, ++{182, 63, 103}, ++{195, 60, 108}, ++{208, 56, 114}, ++{222, 51, 119}, ++{222, 51, 119}, ++{151, 72, 88}, ++{160, 70, 93}, ++{171, 68, 98}, ++{183, 64, 103}, ++{196, 61, 109}, ++{210, 56, 114}, ++{223, 52, 119}, ++{223, 52, 119}, ++{153, 74, 89}, ++{162, 72, 93}, ++{173, 69, 98}, ++{185, 65, 104}, ++{198, 62, 109}, ++{211, 57, 115}, ++{224, 53, 120}, ++{224, 53, 120}, ++{156, 75, 90}, ++{164, 73, 94}, ++{175, 70, 99}, ++{187, 67, 105}, ++{200, 62, 110}, ++{212, 58, 115}, ++{226, 53, 120}, ++{226, 53, 120}, ++{158, 77, 91}, ++{167, 75, 95}, ++{177, 71, 100}, ++{189, 68, 105}, ++{201, 63, 110}, ++{214, 59, 116}, ++{227, 54, 120}, ++{227, 54, 120}, ++{161, 78, 92}, ++{169, 76, 96}, ++{179, 73, 101}, ++{191, 69, 106}, ++{203, 64, 111}, ++{216, 60, 116}, ++{229, 55, 121}, ++{229, 55, 121}, ++{164, 80, 93}, ++{172, 77, 97}, ++{182, 74, 101}, ++{193, 70, 106}, ++{205, 65, 111}, ++{218, 61, 116}, ++{230, 56, 121}, ++{230, 56, 121}, ++{167, 81, 94}, ++{174, 79, 98}, ++{184, 75, 102}, ++{195, 71, 107}, ++{207, 66, 112}, ++{219, 62, 117}, ++{232, 57, 122}, ++{232, 57, 122}, ++{169, 83, 95}, ++{177, 80, 99}, ++{187, 76, 103}, ++{197, 72, 108}, ++{209, 67, 113}, ++{221, 62, 117}, ++{234, 57, 122}, ++{234, 57, 122}, ++{172, 84, 96}, ++{180, 81, 100}, ++{189, 77, 104}, ++{200, 73, 108}, ++{211, 68, 113}, ++{223, 63, 118}, ++{236, 58, 122}, ++{236, 58, 122}, ++{175, 86, 97}, ++{182, 83, 101}, ++{192, 79, 105}, ++{202, 74, 109}, ++{214, 69, 114}, ++{225, 64, 118}, ++{237, 59, 123}, ++{237, 59, 123}, ++{178, 87, 98}, ++{185, 84, 102}, ++{194, 80, 105}, ++{205, 75, 110}, ++{216, 70, 114}, ++{227, 65, 119}, ++{239, 60, 123}, ++{239, 60, 123}, ++{181, 88, 99}, ++{188, 85, 103}, ++{197, 81, 106}, ++{207, 76, 111}, ++{218, 71, 115}, ++{230, 66, 119}, ++{241, 61, 124}, ++{241, 61, 124}, ++{184, 90, 101}, ++{191, 86, 103}, ++{200, 82, 107}, ++{210, 77, 111}, ++{221, 72, 116}, ++{232, 67, 120}, ++{244, 62, 124}, ++{244, 62, 124}, ++{188, 91, 102}, ++{194, 88, 104}, ++{203, 83, 108}, ++{212, 78, 112}, ++{223, 73, 116}, ++{234, 68, 120}, ++{246, 63, 125}, ++{246, 63, 125}, ++{191, 92, 103}, ++{197, 89, 105}, ++{205, 84, 109}, ++{215, 80, 113}, ++{226, 74, 117}, ++{237, 69, 121}, ++{248, 64, 125}, ++{248, 64, 125}, ++{194, 93, 104}, ++{200, 90, 106}, ++{208, 85, 110}, ++{218, 81, 113}, ++{228, 75, 117}, ++{239, 70, 121}, ++{250, 65, 126}, ++{250, 65, 126}, ++{197, 94, 105}, ++{203, 91, 107}, ++{211, 86, 110}, ++{221, 82, 114}, ++{231, 76, 118}, ++{241, 71, 122}, ++{252, 65, 126}, ++{252, 65, 126}, ++{199, 95, 105}, ++{205, 91, 108}, ++{213, 87, 111}, ++{222, 82, 114}, ++{232, 77, 118}, ++{243, 71, 122}, ++{254, 66, 126}, ++{254, 66, 126}, ++{199, 95, 105}, ++{205, 91, 108}, ++{213, 87, 111}, ++{222, 82, 114}, ++{232, 77, 118}, ++{243, 71, 122}, ++{254, 66, 126}, ++{254, 66, 126}, ++{199, 95, 105}, ++{205, 91, 108}, ++{213, 87, 111}, ++{222, 82, 114}, ++{232, 77, 118}, ++{243, 71, 122}, ++{254, 66, 126}, ++{254, 66, 126}, ++{199, 95, 105}, ++{205, 91, 108}, ++{213, 87, 111}, ++{222, 82, 114}, ++{232, 77, 118}, ++{243, 71, 122}, ++{254, 66, 126}, ++{254, 66, 126}, ++{139, 57, 80}, ++{149, 58, 85}, ++{162, 58, 91}, ++{175, 56, 98}, ++{189, 53, 104}, ++{203, 50, 110}, ++{217, 47, 116}, ++{217, 47, 116}, ++{139, 58, 80}, ++{150, 58, 85}, ++{162, 58, 91}, ++{175, 56, 98}, ++{189, 54, 104}, ++{203, 50, 110}, ++{217, 47, 116}, ++{217, 47, 116}, ++{140, 58, 80}, ++{150, 59, 85}, ++{162, 58, 92}, ++{176, 56, 98}, ++{189, 54, 104}, ++{203, 50, 110}, ++{217, 47, 116}, ++{217, 47, 116}, ++{141, 59, 80}, ++{151, 59, 86}, ++{163, 59, 92}, ++{176, 57, 98}, ++{190, 54, 104}, ++{204, 51, 110}, ++{217, 47, 116}, ++{217, 47, 116}, ++{142, 60, 81}, ++{152, 60, 86}, ++{164, 59, 92}, ++{177, 57, 98}, ++{190, 54, 105}, ++{204, 51, 110}, ++{218, 47, 116}, ++{218, 47, 116}, ++{143, 61, 81}, ++{153, 61, 86}, ++{165, 60, 92}, ++{178, 58, 99}, ++{191, 55, 105}, ++{205, 51, 111}, ++{219, 48, 116}, ++{219, 48, 116}, ++{144, 62, 82}, ++{154, 62, 87}, ++{166, 61, 93}, ++{179, 58, 99}, ++{192, 55, 105}, ++{206, 52, 111}, ++{219, 48, 116}, ++{219, 48, 116}, ++{146, 63, 83}, ++{155, 63, 88}, ++{167, 62, 93}, ++{180, 59, 99}, ++{193, 56, 105}, ++{207, 52, 111}, ++{220, 49, 116}, ++{220, 49, 116}, ++{147, 65, 83}, ++{157, 64, 88}, ++{168, 63, 94}, ++{181, 60, 100}, ++{194, 57, 106}, ++{208, 53, 111}, ++{221, 49, 117}, ++{221, 49, 117}, ++{149, 66, 84}, ++{158, 65, 89}, ++{170, 64, 95}, ++{182, 61, 100}, ++{195, 58, 106}, ++{209, 54, 112}, ++{222, 50, 117}, ++{222, 50, 117}, ++{151, 68, 85}, ++{160, 67, 90}, ++{171, 65, 95}, ++{184, 62, 101}, ++{197, 58, 106}, ++{210, 54, 112}, ++{223, 50, 117}, ++{223, 50, 117}, ++{154, 70, 86}, ++{162, 68, 91}, ++{173, 66, 96}, ++{185, 63, 101}, ++{198, 59, 107}, ++{211, 55, 112}, ++{224, 51, 118}, ++{224, 51, 118}, ++{156, 71, 87}, ++{164, 70, 91}, ++{175, 67, 96}, ++{187, 64, 102}, ++{200, 60, 107}, ++{213, 56, 113}, ++{226, 52, 118}, ++{226, 52, 118}, ++{158, 73, 88}, ++{167, 71, 92}, ++{177, 68, 97}, ++{189, 65, 103}, ++{201, 61, 108}, ++{214, 57, 113}, ++{227, 52, 118}, ++{227, 52, 118}, ++{161, 75, 89}, ++{169, 72, 93}, ++{179, 70, 98}, ++{191, 66, 103}, ++{203, 62, 108}, ++{216, 58, 114}, ++{229, 53, 119}, ++{229, 53, 119}, ++{163, 76, 90}, ++{171, 74, 94}, ++{181, 71, 99}, ++{193, 67, 104}, ++{205, 63, 109}, ++{217, 58, 114}, ++{230, 54, 119}, ++{230, 54, 119}, ++{166, 78, 91}, ++{174, 75, 95}, ++{184, 72, 100}, ++{195, 68, 104}, ++{207, 64, 109}, ++{219, 59, 114}, ++{232, 55, 119}, ++{232, 55, 119}, ++{169, 79, 92}, ++{176, 77, 96}, ++{186, 73, 100}, ++{197, 69, 105}, ++{209, 65, 110}, ++{221, 60, 115}, ++{233, 56, 120}, ++{233, 56, 120}, ++{172, 81, 93}, ++{179, 78, 97}, ++{189, 75, 101}, ++{199, 70, 106}, ++{211, 66, 111}, ++{223, 61, 115}, ++{235, 56, 120}, ++{235, 56, 120}, ++{174, 82, 94}, ++{182, 79, 98}, ++{191, 76, 102}, ++{202, 72, 106}, ++{213, 67, 111}, ++{225, 62, 116}, ++{237, 57, 121}, ++{237, 57, 121}, ++{177, 84, 95}, ++{184, 81, 99}, ++{194, 77, 103}, ++{204, 73, 107}, ++{215, 68, 112}, ++{227, 63, 116}, ++{239, 58, 121}, ++{239, 58, 121}, ++{180, 85, 97}, ++{187, 82, 100}, ++{196, 78, 104}, ++{206, 74, 108}, ++{218, 69, 112}, ++{229, 64, 117}, ++{241, 59, 121}, ++{241, 59, 121}, ++{183, 86, 98}, ++{190, 83, 101}, ++{199, 79, 104}, ++{209, 75, 109}, ++{220, 70, 113}, ++{231, 65, 117}, ++{243, 60, 122}, ++{243, 60, 122}, ++{186, 88, 99}, ++{193, 85, 102}, ++{202, 81, 105}, ++{211, 76, 109}, ++{222, 71, 114}, ++{233, 66, 118}, ++{245, 61, 122}, ++{245, 61, 122}, ++{190, 89, 100}, ++{196, 86, 102}, ++{204, 82, 106}, ++{214, 77, 110}, ++{225, 72, 114}, ++{236, 67, 119}, ++{247, 62, 123}, ++{247, 62, 123}, ++{193, 90, 101}, ++{199, 87, 103}, ++{207, 83, 107}, ++{217, 78, 111}, ++{227, 73, 115}, ++{238, 68, 119}, ++{249, 63, 123}, ++{249, 63, 123}, ++{196, 91, 102}, ++{202, 88, 104}, ++{210, 84, 108}, ++{219, 79, 112}, ++{230, 74, 116}, ++{240, 69, 120}, ++{252, 64, 124}, ++{252, 64, 124}, ++{199, 92, 103}, ++{205, 89, 105}, ++{213, 85, 109}, ++{222, 80, 112}, ++{232, 75, 116}, ++{243, 70, 120}, ++{254, 64, 124}, ++{254, 64, 124}, ++{201, 93, 103}, ++{207, 90, 106}, ++{214, 85, 109}, ++{224, 81, 113}, ++{234, 76, 117}, ++{244, 70, 121}, ++{255, 65, 124}, ++{255, 65, 124}, ++{201, 93, 103}, ++{207, 90, 106}, ++{214, 85, 109}, ++{224, 81, 113}, ++{234, 76, 117}, ++{244, 70, 121}, ++{255, 65, 124}, ++{255, 65, 124}, ++{201, 93, 103}, ++{207, 90, 106}, ++{214, 85, 109}, ++{224, 81, 113}, ++{234, 76, 117}, ++{244, 70, 121}, ++{255, 65, 124}, ++{255, 65, 124}, ++{201, 93, 103}, ++{207, 90, 106}, ++{214, 85, 109}, ++{224, 81, 113}, ++{234, 76, 117}, ++{244, 70, 121}, ++{255, 65, 124}, ++{255, 65, 124}, ++{142, 55, 78}, ++{152, 56, 83}, ++{164, 56, 89}, ++{177, 54, 96}, ++{191, 52, 102}, ++{205, 49, 108}, ++{218, 45, 114}, ++{218, 45, 114}, ++{142, 55, 78}, ++{152, 56, 83}, ++{164, 56, 89}, ++{177, 54, 96}, ++{191, 52, 102}, ++{205, 49, 108}, ++{219, 45, 114}, ++{219, 45, 114}, ++{143, 56, 78}, ++{152, 56, 83}, ++{165, 56, 90}, ++{178, 55, 96}, ++{191, 52, 102}, ++{205, 49, 108}, ++{219, 46, 114}, ++{219, 46, 114}, ++{143, 56, 78}, ++{153, 57, 84}, ++{165, 57, 90}, ++{178, 55, 96}, ++{192, 53, 102}, ++{205, 49, 108}, ++{219, 46, 114}, ++{219, 46, 114}, ++{144, 57, 79}, ++{154, 58, 84}, ++{166, 57, 90}, ++{179, 56, 96}, ++{192, 53, 103}, ++{206, 50, 108}, ++{220, 46, 114}, ++{220, 46, 114}, ++{145, 58, 79}, ++{155, 59, 85}, ++{167, 58, 91}, ++{180, 56, 97}, ++{193, 53, 103}, ++{207, 50, 109}, ++{220, 46, 114}, ++{220, 46, 114}, ++{147, 60, 80}, ++{156, 60, 85}, ++{168, 59, 91}, ++{181, 57, 97}, ++{194, 54, 103}, ++{207, 51, 109}, ++{221, 47, 114}, ++{221, 47, 114}, ++{148, 61, 81}, ++{158, 61, 86}, ++{169, 60, 91}, ++{182, 57, 97}, ++{195, 55, 103}, ++{208, 51, 109}, ++{222, 47, 115}, ++{222, 47, 115}, ++{150, 63, 82}, ++{159, 62, 86}, ++{170, 61, 92}, ++{183, 58, 98}, ++{196, 55, 104}, ++{209, 52, 109}, ++{223, 48, 115}, ++{223, 48, 115}, ++{152, 64, 82}, ++{161, 63, 87}, ++{172, 62, 93}, ++{184, 59, 98}, ++{197, 56, 104}, ++{210, 52, 110}, ++{224, 48, 115}, ++{224, 48, 115}, ++{154, 66, 83}, ++{163, 65, 88}, ++{174, 63, 93}, ++{186, 60, 99}, ++{199, 57, 105}, ++{212, 53, 110}, ++{225, 49, 115}, ++{225, 49, 115}, ++{156, 67, 84}, ++{165, 66, 89}, ++{175, 64, 94}, ++{187, 61, 99}, ++{200, 58, 105}, ++{213, 54, 110}, ++{226, 50, 116}, ++{226, 50, 116}, ++{158, 69, 85}, ++{167, 68, 89}, ++{177, 65, 95}, ++{189, 62, 100}, ++{202, 59, 105}, ++{214, 55, 111}, ++{227, 50, 116}, ++{227, 50, 116}, ++{161, 71, 86}, ++{169, 69, 90}, ++{179, 66, 95}, ++{191, 63, 101}, ++{203, 60, 106}, ++{216, 55, 111}, ++{229, 51, 116}, ++{229, 51, 116}, ++{163, 72, 87}, ++{171, 70, 91}, ++{181, 68, 96}, ++{193, 64, 101}, ++{205, 60, 106}, ++{217, 56, 112}, ++{230, 52, 117}, ++{230, 52, 117}, ++{166, 74, 88}, ++{173, 72, 92}, ++{183, 69, 97}, ++{195, 65, 102}, ++{207, 61, 107}, ++{219, 57, 112}, ++{232, 53, 117}, ++{232, 53, 117}, ++{168, 76, 89}, ++{176, 73, 93}, ++{186, 70, 98}, ++{197, 67, 103}, ++{209, 62, 108}, ++{221, 58, 113}, ++{233, 54, 117}, ++{233, 54, 117}, ++{171, 77, 90}, ++{178, 75, 94}, ++{188, 72, 98}, ++{199, 68, 103}, ++{211, 63, 108}, ++{223, 59, 113}, ++{235, 54, 118}, ++{235, 54, 118}, ++{174, 79, 91}, ++{181, 76, 95}, ++{190, 73, 99}, ++{201, 69, 104}, ++{213, 65, 109}, ++{225, 60, 114}, ++{237, 55, 118}, ++{237, 55, 118}, ++{176, 80, 92}, ++{184, 78, 96}, ++{193, 74, 100}, ++{203, 70, 105}, ++{215, 66, 109}, ++{227, 61, 114}, ++{239, 56, 119}, ++{239, 56, 119}, ++{179, 82, 94}, ++{186, 79, 97}, ++{195, 75, 101}, ++{206, 71, 105}, ++{217, 67, 110}, ++{229, 62, 115}, ++{240, 57, 119}, ++{240, 57, 119}, ++{182, 83, 95}, ++{189, 80, 98}, ++{198, 76, 102}, ++{208, 72, 106}, ++{219, 68, 111}, ++{231, 63, 115}, ++{242, 58, 120}, ++{242, 58, 120}, ++{185, 84, 96}, ++{192, 82, 99}, ++{201, 78, 103}, ++{211, 73, 107}, ++{221, 69, 111}, ++{233, 64, 116}, ++{244, 59, 120}, ++{244, 59, 120}, ++{188, 86, 97}, ++{195, 83, 100}, ++{203, 79, 103}, ++{213, 74, 108}, ++{224, 70, 112}, ++{235, 65, 116}, ++{246, 60, 121}, ++{246, 60, 121}, ++{191, 87, 98}, ++{198, 84, 101}, ++{206, 80, 104}, ++{216, 76, 108}, ++{226, 71, 112}, ++{237, 66, 117}, ++{249, 61, 121}, ++{249, 61, 121}, ++{195, 88, 99}, ++{201, 85, 102}, ++{209, 81, 105}, ++{218, 77, 109}, ++{229, 72, 113}, ++{240, 67, 117}, ++{251, 62, 122}, ++{251, 62, 122}, ++{198, 89, 100}, ++{204, 86, 103}, ++{212, 82, 106}, ++{221, 78, 110}, ++{231, 73, 114}, ++{242, 68, 118}, ++{253, 62, 122}, ++{253, 62, 122}, ++{201, 91, 101}, ++{207, 87, 103}, ++{215, 83, 107}, ++{224, 79, 110}, ++{234, 74, 114}, ++{244, 69, 118}, ++{255, 63, 123}, ++{255, 63, 123}, ++{202, 91, 101}, ++{208, 88, 104}, ++{216, 84, 107}, ++{225, 79, 111}, ++{235, 74, 115}, ++{246, 69, 119}, ++{255, 64, 123}, ++{255, 64, 123}, ++{202, 91, 101}, ++{208, 88, 104}, ++{216, 84, 107}, ++{225, 79, 111}, ++{235, 74, 115}, ++{246, 69, 119}, ++{255, 64, 123}, ++{255, 64, 123}, ++{202, 91, 101}, ++{208, 88, 104}, ++{216, 84, 107}, ++{225, 79, 111}, ++{235, 74, 115}, ++{246, 69, 119}, ++{255, 64, 123}, ++{255, 64, 123}, ++{202, 91, 101}, ++{208, 88, 104}, ++{216, 84, 107}, ++{225, 79, 111}, ++{235, 74, 115}, ++{246, 69, 119}, ++{255, 64, 123}, ++{255, 64, 123}, ++{145, 53, 76}, ++{154, 54, 81}, ++{166, 54, 87}, ++{179, 53, 94}, ++{193, 50, 100}, ++{206, 48, 106}, ++{220, 44, 112}, ++{220, 44, 112}, ++{145, 53, 76}, ++{155, 54, 81}, ++{166, 54, 88}, ++{179, 53, 94}, ++{193, 51, 100}, ++{207, 48, 106}, ++{220, 44, 112}, ++{220, 44, 112}, ++{145, 53, 76}, ++{155, 54, 82}, ++{167, 54, 88}, ++{180, 53, 94}, ++{193, 51, 100}, ++{207, 48, 106}, ++{220, 44, 112}, ++{220, 44, 112}, ++{146, 54, 77}, ++{156, 55, 82}, ++{167, 55, 88}, ++{180, 53, 94}, ++{194, 51, 100}, ++{207, 48, 106}, ++{221, 45, 112}, ++{221, 45, 112}, ++{147, 55, 77}, ++{156, 56, 82}, ++{168, 55, 88}, ++{181, 54, 94}, ++{194, 51, 101}, ++{208, 48, 106}, ++{221, 45, 112}, ++{221, 45, 112}, ++{148, 56, 78}, ++{157, 57, 83}, ++{169, 56, 89}, ++{182, 54, 95}, ++{195, 52, 101}, ++{208, 49, 107}, ++{222, 45, 112}, ++{222, 45, 112}, ++{149, 57, 78}, ++{159, 58, 83}, ++{170, 57, 89}, ++{183, 55, 95}, ++{196, 52, 101}, ++{209, 49, 107}, ++{223, 46, 112}, ++{223, 46, 112}, ++{151, 59, 79}, ++{160, 59, 84}, ++{171, 58, 89}, ++{184, 56, 95}, ++{197, 53, 101}, ++{210, 50, 107}, ++{223, 46, 113}, ++{223, 46, 113}, ++{153, 60, 80}, ++{162, 60, 84}, ++{173, 59, 90}, ++{185, 57, 96}, ++{198, 54, 102}, ++{211, 50, 107}, ++{224, 47, 113}, ++{224, 47, 113}, ++{154, 62, 81}, ++{163, 61, 85}, ++{174, 60, 91}, ++{186, 57, 96}, ++{199, 55, 102}, ++{212, 51, 108}, ++{225, 47, 113}, ++{225, 47, 113}, ++{156, 63, 81}, ++{165, 63, 86}, ++{176, 61, 91}, ++{188, 58, 97}, ++{200, 55, 103}, ++{213, 52, 108}, ++{226, 48, 113}, ++{227, 48, 113}, ++{158, 65, 82}, ++{167, 64, 87}, ++{178, 62, 92}, ++{189, 59, 97}, ++{202, 56, 103}, ++{215, 53, 108}, ++{228, 49, 114}, ++{228, 49, 114}, ++{161, 67, 83}, ++{169, 65, 88}, ++{179, 63, 93}, ++{191, 60, 98}, ++{203, 57, 104}, ++{216, 53, 109}, ++{229, 49, 114}, ++{229, 49, 114}, ++{163, 68, 84}, ++{171, 67, 88}, ++{181, 65, 93}, ++{193, 62, 99}, ++{205, 58, 104}, ++{218, 54, 109}, ++{230, 50, 114}, ++{230, 50, 114}, ++{165, 70, 85}, ++{173, 68, 89}, ++{183, 66, 94}, ++{195, 63, 99}, ++{207, 59, 105}, ++{219, 55, 110}, ++{232, 51, 115}, ++{232, 51, 115}, ++{168, 72, 86}, ++{176, 70, 90}, ++{186, 67, 95}, ++{197, 64, 100}, ++{209, 60, 105}, ++{221, 56, 110}, ++{233, 52, 115}, ++{233, 52, 115}, ++{170, 73, 87}, ++{178, 71, 91}, ++{188, 68, 96}, ++{199, 65, 101}, ++{210, 61, 106}, ++{223, 57, 111}, ++{235, 52, 116}, ++{235, 52, 116}, ++{173, 75, 88}, ++{181, 73, 92}, ++{190, 70, 96}, ++{201, 66, 101}, ++{212, 62, 106}, ++{224, 58, 111}, ++{237, 53, 116}, ++{237, 53, 116}, ++{176, 77, 90}, ++{183, 74, 93}, ++{192, 71, 97}, ++{203, 67, 102}, ++{214, 63, 107}, ++{226, 59, 112}, ++{238, 54, 116}, ++{238, 54, 116}, ++{179, 78, 91}, ++{186, 76, 94}, ++{195, 72, 98}, ++{205, 68, 103}, ++{216, 64, 107}, ++{228, 60, 112}, ++{240, 55, 117}, ++{240, 55, 117}, ++{181, 80, 92}, ++{188, 77, 95}, ++{197, 74, 99}, ++{208, 70, 103}, ++{219, 65, 108}, ++{230, 61, 113}, ++{242, 56, 117}, ++{242, 56, 117}, ++{184, 81, 93}, ++{191, 78, 96}, ++{200, 75, 100}, ++{210, 71, 104}, ++{221, 66, 109}, ++{232, 62, 113}, ++{244, 57, 118}, ++{244, 57, 118}, ++{187, 82, 94}, ++{194, 80, 97}, ++{203, 76, 101}, ++{212, 72, 105}, ++{223, 67, 109}, ++{234, 63, 114}, ++{246, 58, 118}, ++{246, 58, 118}, ++{190, 84, 95}, ++{197, 81, 98}, ++{205, 77, 102}, ++{215, 73, 106}, ++{225, 68, 110}, ++{237, 64, 114}, ++{248, 59, 119}, ++{248, 59, 119}, ++{193, 85, 96}, ++{200, 82, 99}, ++{208, 78, 102}, ++{218, 74, 106}, ++{228, 69, 111}, ++{239, 65, 115}, ++{250, 60, 119}, ++{250, 60, 119}, ++{196, 86, 97}, ++{203, 83, 100}, ++{211, 80, 103}, ++{220, 75, 107}, ++{230, 70, 111}, ++{241, 66, 116}, ++{252, 60, 120}, ++{252, 60, 120}, ++{200, 88, 98}, ++{206, 85, 101}, ++{214, 81, 104}, ++{223, 76, 108}, ++{233, 71, 112}, ++{243, 66, 116}, ++{254, 61, 120}, ++{254, 61, 120}, ++{203, 89, 99}, ++{209, 86, 102}, ++{216, 82, 105}, ++{225, 77, 109}, ++{235, 72, 113}, ++{246, 67, 117}, ++{255, 62, 121}, ++{255, 62, 121}, ++{204, 89, 100}, ++{210, 86, 102}, ++{218, 82, 105}, ++{227, 78, 109}, ++{237, 73, 113}, ++{247, 68, 117}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 89, 100}, ++{210, 86, 102}, ++{218, 82, 105}, ++{227, 78, 109}, ++{237, 73, 113}, ++{247, 68, 117}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 89, 100}, ++{210, 86, 102}, ++{218, 82, 105}, ++{227, 78, 109}, ++{237, 73, 113}, ++{247, 68, 117}, ++{255, 63, 121}, ++{255, 63, 121}, ++{204, 89, 100}, ++{210, 86, 102}, ++{218, 82, 105}, ++{227, 78, 109}, ++{237, 73, 113}, ++{247, 68, 117}, ++{255, 63, 121}, ++{255, 63, 121}, ++{147, 50, 74}, ++{157, 52, 79}, ++{169, 52, 86}, ++{181, 51, 92}, ++{195, 49, 98}, ++{208, 46, 104}, ++{222, 43, 110}, ++{222, 43, 110}, ++{148, 51, 74}, ++{157, 52, 80}, ++{169, 52, 86}, ++{182, 51, 92}, ++{195, 49, 98}, ++{208, 46, 104}, ++{222, 43, 110}, ++{222, 43, 110}, ++{148, 51, 75}, ++{157, 52, 80}, ++{169, 52, 86}, ++{182, 51, 92}, ++{195, 49, 98}, ++{209, 46, 104}, ++{222, 43, 110}, ++{222, 43, 110}, ++{149, 52, 75}, ++{158, 53, 80}, ++{170, 53, 86}, ++{182, 52, 92}, ++{196, 49, 98}, ++{209, 47, 104}, ++{223, 43, 110}, ++{223, 43, 110}, ++{150, 53, 75}, ++{159, 54, 80}, ++{170, 53, 86}, ++{183, 52, 92}, ++{196, 50, 99}, ++{210, 47, 104}, ++{223, 44, 110}, ++{223, 44, 110}, ++{151, 54, 76}, ++{160, 54, 81}, ++{171, 54, 87}, ++{184, 53, 93}, ++{197, 50, 99}, ++{210, 47, 105}, ++{224, 44, 110}, ++{224, 44, 110}, ++{152, 55, 76}, ++{161, 55, 81}, ++{172, 55, 87}, ++{185, 53, 93}, ++{198, 51, 99}, ++{211, 48, 105}, ++{224, 44, 111}, ++{224, 44, 111}, ++{153, 56, 77}, ++{162, 57, 82}, ++{174, 56, 88}, ++{186, 54, 94}, ++{199, 52, 99}, ++{212, 48, 105}, ++{225, 45, 111}, ++{225, 45, 111}, ++{155, 58, 78}, ++{164, 58, 83}, ++{175, 57, 88}, ++{187, 55, 94}, ++{200, 52, 100}, ++{213, 49, 106}, ++{226, 45, 111}, ++{226, 45, 111}, ++{157, 60, 79}, ++{166, 59, 83}, ++{176, 58, 89}, ++{188, 56, 94}, ++{201, 53, 100}, ++{214, 50, 106}, ++{227, 46, 111}, ++{227, 46, 111}, ++{159, 61, 80}, ++{167, 60, 84}, ++{178, 59, 89}, ++{190, 57, 95}, ++{202, 54, 101}, ++{215, 50, 106}, ++{228, 47, 112}, ++{228, 47, 112}, ++{161, 63, 81}, ++{169, 62, 85}, ++{180, 60, 90}, ++{191, 58, 96}, ++{204, 55, 101}, ++{216, 51, 107}, ++{229, 47, 112}, ++{229, 47, 112}, ++{163, 64, 81}, ++{171, 63, 86}, ++{181, 61, 91}, ++{193, 59, 96}, ++{205, 56, 102}, ++{218, 52, 107}, ++{231, 48, 112}, ++{231, 48, 112}, ++{165, 66, 82}, ++{173, 65, 86}, ++{183, 63, 91}, ++{195, 60, 97}, ++{207, 57, 102}, ++{219, 53, 107}, ++{232, 49, 113}, ++{232, 49, 113}, ++{168, 68, 83}, ++{175, 66, 87}, ++{185, 64, 92}, ++{197, 61, 97}, ++{209, 58, 103}, ++{221, 54, 108}, ++{233, 50, 113}, ++{233, 50, 113}, ++{170, 70, 85}, ++{178, 68, 88}, ++{188, 65, 93}, ++{199, 62, 98}, ++{210, 59, 103}, ++{223, 55, 108}, ++{235, 50, 113}, ++{235, 50, 113}, ++{173, 71, 86}, ++{180, 69, 89}, ++{190, 67, 94}, ++{201, 63, 99}, ++{212, 60, 104}, ++{224, 55, 109}, ++{237, 51, 114}, ++{237, 51, 114}, ++{175, 73, 87}, ++{183, 71, 90}, ++{192, 68, 95}, ++{203, 64, 99}, ++{214, 61, 104}, ++{226, 56, 109}, ++{238, 52, 114}, ++{238, 52, 114}, ++{178, 74, 88}, ++{185, 72, 91}, ++{194, 69, 95}, ++{205, 66, 100}, ++{216, 62, 105}, ++{228, 57, 110}, ++{240, 53, 115}, ++{240, 53, 115}, ++{181, 76, 89}, ++{188, 74, 92}, ++{197, 71, 96}, ++{207, 67, 101}, ++{218, 63, 106}, ++{230, 58, 110}, ++{242, 54, 115}, ++{242, 54, 115}, ++{184, 78, 90}, ++{190, 75, 93}, ++{199, 72, 97}, ++{209, 68, 102}, ++{220, 64, 106}, ++{232, 59, 111}, ++{244, 55, 116}, ++{244, 55, 116}, ++{186, 79, 91}, ++{193, 76, 94}, ++{202, 73, 98}, ++{212, 69, 102}, ++{223, 65, 107}, ++{234, 60, 111}, ++{245, 56, 116}, ++{245, 56, 116}, ++{189, 80, 92}, ++{196, 78, 95}, ++{204, 74, 99}, ++{214, 70, 103}, ++{225, 66, 108}, ++{236, 61, 112}, ++{247, 57, 117}, ++{247, 57, 117}, ++{192, 82, 93}, ++{199, 79, 96}, ++{207, 76, 100}, ++{217, 71, 104}, ++{227, 67, 108}, ++{238, 62, 113}, ++{249, 57, 117}, ++{249, 57, 117}, ++{195, 83, 94}, ++{202, 80, 97}, ++{210, 77, 101}, ++{219, 73, 105}, ++{230, 68, 109}, ++{240, 63, 113}, ++{252, 58, 118}, ++{252, 58, 118}, ++{198, 85, 95}, ++{205, 82, 98}, ++{213, 78, 101}, ++{222, 74, 105}, ++{232, 69, 110}, ++{243, 64, 114}, ++{254, 59, 118}, ++{254, 59, 118}, ++{201, 86, 96}, ++{207, 83, 99}, ++{215, 79, 102}, ++{224, 75, 106}, ++{234, 70, 110}, ++{245, 65, 114}, ++{255, 60, 119}, ++{255, 60, 119}, ++{205, 87, 97}, ++{210, 84, 100}, ++{218, 80, 103}, ++{227, 76, 107}, ++{237, 71, 111}, ++{247, 66, 115}, ++{255, 61, 119}, ++{255, 61, 119}, ++{206, 88, 98}, ++{212, 85, 100}, ++{220, 81, 104}, ++{228, 76, 107}, ++{238, 72, 111}, ++{249, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{212, 85, 100}, ++{220, 81, 104}, ++{228, 76, 107}, ++{238, 72, 111}, ++{249, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{212, 85, 100}, ++{220, 81, 104}, ++{228, 76, 107}, ++{238, 72, 111}, ++{249, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{206, 88, 98}, ++{212, 85, 100}, ++{220, 81, 104}, ++{228, 76, 107}, ++{238, 72, 111}, ++{249, 67, 115}, ++{255, 62, 119}, ++{255, 62, 119}, ++{150, 48, 72}, ++{159, 50, 78}, ++{171, 50, 84}, ++{184, 49, 90}, ++{197, 47, 96}, ++{210, 45, 102}, ++{224, 42, 108}, ++{224, 42, 108}, ++{150, 48, 73}, ++{160, 50, 78}, ++{171, 50, 84}, ++{184, 49, 90}, ++{197, 47, 96}, ++{210, 45, 102}, ++{224, 42, 108}, ++{224, 42, 108}, ++{151, 49, 73}, ++{160, 50, 78}, ++{171, 50, 84}, ++{184, 49, 90}, ++{197, 48, 96}, ++{211, 45, 102}, ++{224, 42, 108}, ++{224, 42, 108}, ++{151, 50, 73}, ++{161, 51, 78}, ++{172, 51, 84}, ++{185, 50, 90}, ++{198, 48, 96}, ++{211, 45, 102}, ++{224, 42, 108}, ++{224, 42, 108}, ++{152, 50, 74}, ++{161, 51, 79}, ++{173, 51, 84}, ++{185, 50, 91}, ++{198, 48, 97}, ++{211, 46, 103}, ++{225, 42, 108}, ++{225, 42, 108}, ++{153, 52, 74}, ++{162, 52, 79}, ++{174, 52, 85}, ++{186, 51, 91}, ++{199, 49, 97}, ++{212, 46, 103}, ++{225, 43, 108}, ++{225, 43, 108}, ++{155, 53, 75}, ++{163, 53, 79}, ++{175, 53, 85}, ++{187, 52, 91}, ++{200, 49, 97}, ++{213, 47, 103}, ++{226, 43, 109}, ++{226, 43, 109}, ++{156, 54, 75}, ++{165, 54, 80}, ++{176, 54, 86}, ++{188, 52, 92}, ++{201, 50, 98}, ++{214, 47, 103}, ++{227, 44, 109}, ++{227, 44, 109}, ++{158, 56, 76}, ++{166, 56, 81}, ++{177, 55, 86}, ++{189, 53, 92}, ++{202, 51, 98}, ++{215, 48, 104}, ++{228, 44, 109}, ++{228, 44, 109}, ++{159, 57, 77}, ++{168, 57, 81}, ++{179, 56, 87}, ++{190, 54, 93}, ++{203, 51, 98}, ++{216, 48, 104}, ++{229, 45, 109}, ++{229, 45, 109}, ++{161, 59, 78}, ++{170, 58, 82}, ++{180, 57, 87}, ++{192, 55, 93}, ++{204, 52, 99}, ++{217, 49, 104}, ++{230, 45, 110}, ++{230, 45, 110}, ++{163, 61, 79}, ++{171, 60, 83}, ++{182, 58, 88}, ++{193, 56, 94}, ++{206, 53, 99}, ++{218, 50, 105}, ++{231, 46, 110}, ++{231, 46, 110}, ++{165, 62, 80}, ++{173, 61, 84}, ++{184, 60, 89}, ++{195, 57, 94}, ++{207, 54, 100}, ++{220, 51, 105}, ++{232, 47, 110}, ++{232, 47, 110}, ++{168, 64, 81}, ++{175, 63, 85}, ++{186, 61, 90}, ++{197, 58, 95}, ++{209, 55, 100}, ++{221, 51, 106}, ++{234, 48, 111}, ++{234, 48, 111}, ++{170, 66, 82}, ++{178, 64, 86}, ++{188, 62, 90}, ++{199, 59, 95}, ++{210, 56, 101}, ++{223, 52, 106}, ++{235, 48, 111}, ++{235, 48, 111}, ++{172, 67, 83}, ++{180, 66, 86}, ++{190, 63, 91}, ++{201, 60, 96}, ++{212, 57, 101}, ++{224, 53, 106}, ++{237, 49, 112}, ++{237, 49, 112}, ++{175, 69, 84}, ++{182, 67, 87}, ++{192, 65, 92}, ++{203, 62, 97}, ++{214, 58, 102}, ++{226, 54, 107}, ++{238, 50, 112}, ++{238, 50, 112}, ++{177, 71, 85}, ++{185, 69, 88}, ++{194, 66, 93}, ++{205, 63, 98}, ++{216, 59, 103}, ++{228, 55, 108}, ++{240, 51, 112}, ++{240, 51, 112}, ++{180, 72, 86}, ++{187, 70, 89}, ++{196, 67, 94}, ++{207, 64, 98}, ++{218, 60, 103}, ++{230, 56, 108}, ++{241, 52, 113}, ++{241, 52, 113}, ++{183, 74, 87}, ++{190, 72, 90}, ++{199, 69, 94}, ++{209, 65, 99}, ++{220, 61, 104}, ++{231, 57, 109}, ++{243, 53, 113}, ++{243, 53, 113}, ++{186, 75, 88}, ++{192, 73, 91}, ++{201, 70, 95}, ++{211, 66, 100}, ++{222, 62, 104}, ++{233, 58, 109}, ++{245, 54, 114}, ++{245, 54, 114}, ++{188, 77, 89}, ++{195, 75, 92}, ++{204, 71, 96}, ++{214, 68, 100}, ++{224, 63, 105}, ++{235, 59, 110}, ++{247, 54, 114}, ++{247, 54, 114}, ++{191, 78, 90}, ++{198, 76, 93}, ++{206, 73, 97}, ++{216, 69, 101}, ++{227, 65, 106}, ++{238, 60, 110}, ++{249, 55, 115}, ++{249, 55, 115}, ++{194, 80, 91}, ++{201, 77, 94}, ++{209, 74, 98}, ++{218, 70, 102}, ++{229, 66, 106}, ++{240, 61, 111}, ++{251, 56, 115}, ++{251, 56, 115}, ++{197, 81, 92}, ++{203, 79, 95}, ++{212, 75, 99}, ++{221, 71, 103}, ++{231, 67, 107}, ++{242, 62, 111}, ++{253, 57, 116}, ++{253, 57, 116}, ++{200, 83, 93}, ++{206, 80, 96}, ++{214, 76, 100}, ++{224, 72, 104}, ++{234, 68, 108}, ++{244, 63, 112}, ++{255, 58, 116}, ++{255, 58, 116}, ++{203, 84, 94}, ++{209, 81, 97}, ++{217, 77, 100}, ++{226, 73, 104}, ++{236, 69, 108}, ++{246, 64, 113}, ++{255, 59, 117}, ++{255, 59, 117}, ++{206, 85, 95}, ++{212, 82, 98}, ++{220, 79, 101}, ++{229, 74, 105}, ++{239, 70, 109}, ++{249, 65, 113}, ++{255, 60, 117}, ++{255, 60, 117}, ++{208, 86, 96}, ++{214, 83, 99}, ++{221, 79, 102}, ++{230, 75, 106}, ++{240, 70, 109}, ++{250, 66, 114}, ++{255, 61, 118}, ++{255, 61, 118}, ++{208, 86, 96}, ++{214, 83, 99}, ++{221, 79, 102}, ++{230, 75, 106}, ++{240, 70, 109}, ++{250, 66, 114}, ++{255, 61, 118}, ++{255, 61, 118}, ++{208, 86, 96}, ++{214, 83, 99}, ++{221, 79, 102}, ++{230, 75, 106}, ++{240, 70, 109}, ++{250, 66, 114}, ++{255, 61, 118}, ++{255, 61, 118}, ++{208, 86, 96}, ++{214, 83, 99}, ++{221, 79, 102}, ++{230, 75, 106}, ++{240, 70, 109}, ++{250, 66, 114}, ++{255, 61, 118}, ++{255, 61, 118}, ++{153, 46, 71}, ++{162, 47, 76}, ++{173, 48, 82}, ++{186, 47, 88}, ++{199, 46, 94}, ++{212, 43, 100}, ++{225, 40, 106}, ++{225, 40, 106}, ++{153, 46, 71}, ++{162, 48, 76}, ++{173, 48, 82}, ++{186, 47, 88}, ++{199, 46, 94}, ++{212, 43, 100}, ++{225, 40, 106}, ++{225, 40, 106}, ++{153, 47, 71}, ++{162, 48, 76}, ++{174, 48, 82}, ++{186, 48, 88}, ++{199, 46, 94}, ++{212, 44, 100}, ++{226, 41, 106}, ++{226, 41, 106}, ++{154, 47, 71}, ++{163, 49, 76}, ++{174, 49, 82}, ++{187, 48, 88}, ++{200, 46, 95}, ++{213, 44, 101}, ++{226, 41, 106}, ++{226, 41, 106}, ++{155, 48, 72}, ++{164, 49, 77}, ++{175, 49, 83}, ++{187, 49, 89}, ++{200, 47, 95}, ++{213, 44, 101}, ++{226, 41, 106}, ++{226, 41, 106}, ++{156, 49, 72}, ++{165, 50, 77}, ++{176, 50, 83}, ++{188, 49, 89}, ++{201, 47, 95}, ++{214, 45, 101}, ++{227, 42, 107}, ++{227, 42, 107}, ++{157, 51, 73}, ++{166, 51, 78}, ++{177, 51, 83}, ++{189, 50, 89}, ++{202, 48, 95}, ++{215, 45, 101}, ++{228, 42, 107}, ++{228, 42, 107}, ++{158, 52, 74}, ++{167, 52, 78}, ++{178, 52, 84}, ++{190, 51, 90}, ++{203, 48, 96}, ++{216, 46, 101}, ++{229, 42, 107}, ++{229, 42, 107}, ++{160, 53, 74}, ++{169, 54, 79}, ++{179, 53, 84}, ++{191, 51, 90}, ++{204, 49, 96}, ++{216, 46, 102}, ++{229, 43, 107}, ++{229, 43, 107}, ++{162, 55, 75}, ++{170, 55, 80}, ++{181, 54, 85}, ++{192, 52, 91}, ++{205, 50, 96}, ++{218, 47, 102}, ++{230, 44, 108}, ++{230, 44, 108}, ++{164, 57, 76}, ++{172, 56, 80}, ++{182, 55, 86}, ++{194, 53, 91}, ++{206, 51, 97}, ++{219, 48, 102}, ++{232, 44, 108}, ++{232, 44, 108}, ++{166, 58, 77}, ++{174, 58, 81}, ++{184, 56, 86}, ++{195, 54, 92}, ++{208, 52, 97}, ++{220, 48, 103}, ++{233, 45, 108}, ++{233, 45, 108}, ++{168, 60, 78}, ++{176, 59, 82}, ++{186, 58, 87}, ++{197, 55, 92}, ++{209, 53, 98}, ++{221, 49, 103}, ++{234, 46, 109}, ++{234, 46, 109}, ++{170, 62, 79}, ++{178, 61, 83}, ++{188, 59, 88}, ++{199, 57, 93}, ++{211, 54, 98}, ++{223, 50, 104}, ++{235, 46, 109}, ++{235, 46, 109}, ++{172, 63, 80}, ++{180, 62, 84}, ++{190, 60, 88}, ++{201, 58, 94}, ++{212, 55, 99}, ++{224, 51, 104}, ++{237, 47, 109}, ++{237, 47, 109}, ++{175, 65, 81}, ++{182, 64, 85}, ++{192, 62, 89}, ++{202, 59, 94}, ++{214, 56, 99}, ++{226, 52, 105}, ++{238, 48, 110}, ++{238, 48, 110}, ++{177, 67, 82}, ++{184, 65, 86}, ++{194, 63, 90}, ++{204, 60, 95}, ++{216, 57, 100}, ++{228, 53, 105}, ++{240, 49, 110}, ++{240, 49, 110}, ++{180, 69, 83}, ++{187, 67, 86}, ++{196, 64, 91}, ++{206, 61, 96}, ++{218, 58, 101}, ++{229, 54, 106}, ++{241, 50, 111}, ++{241, 50, 111}, ++{182, 70, 84}, ++{189, 68, 87}, ++{198, 66, 92}, ++{209, 62, 96}, ++{220, 59, 101}, ++{231, 55, 106}, ++{243, 51, 111}, ++{243, 51, 111}, ++{185, 72, 85}, ++{192, 70, 88}, ++{201, 67, 93}, ++{211, 64, 97}, ++{222, 60, 102}, ++{233, 56, 107}, ++{245, 51, 112}, ++{245, 51, 112}, ++{188, 73, 86}, ++{194, 71, 89}, ++{203, 68, 93}, ++{213, 65, 98}, ++{224, 61, 103}, ++{235, 57, 107}, ++{247, 52, 112}, ++{247, 52, 112}, ++{191, 75, 87}, ++{197, 73, 90}, ++{206, 70, 94}, ++{215, 66, 99}, ++{226, 62, 103}, ++{237, 58, 108}, ++{249, 53, 113}, ++{249, 53, 113}, ++{193, 76, 88}, ++{200, 74, 91}, ++{208, 71, 95}, ++{218, 67, 99}, ++{228, 63, 104}, ++{239, 59, 108}, ++{251, 54, 113}, ++{251, 54, 113}, ++{196, 78, 89}, ++{203, 75, 92}, ++{211, 72, 96}, ++{220, 68, 100}, ++{230, 64, 105}, ++{241, 60, 109}, ++{253, 55, 114}, ++{253, 55, 114}, ++{199, 79, 91}, ++{205, 77, 93}, ++{213, 73, 97}, ++{223, 70, 101}, ++{233, 65, 105}, ++{244, 61, 110}, ++{255, 56, 114}, ++{255, 56, 114}, ++{202, 81, 92}, ++{208, 78, 94}, ++{216, 75, 98}, ++{225, 71, 102}, ++{235, 66, 106}, ++{246, 62, 110}, ++{255, 57, 115}, ++{255, 57, 115}, ++{205, 82, 93}, ++{211, 79, 95}, ++{219, 76, 99}, ++{228, 72, 103}, ++{238, 67, 107}, ++{248, 63, 111}, ++{255, 58, 115}, ++{255, 58, 115}, ++{208, 83, 94}, ++{214, 81, 96}, ++{222, 77, 100}, ++{230, 73, 103}, ++{240, 68, 107}, ++{250, 64, 111}, ++{255, 59, 116}, ++{255, 59, 116}, ++{210, 84, 94}, ++{216, 81, 97}, ++{223, 78, 100}, ++{232, 73, 104}, ++{241, 69, 108}, ++{252, 64, 112}, ++{255, 59, 116}, ++{255, 59, 116}, ++{210, 84, 94}, ++{216, 81, 97}, ++{223, 78, 100}, ++{232, 73, 104}, ++{241, 69, 108}, ++{252, 64, 112}, ++{255, 59, 116}, ++{255, 59, 116}, ++{210, 84, 94}, ++{216, 81, 97}, ++{223, 78, 100}, ++{232, 73, 104}, ++{241, 69, 108}, ++{252, 64, 112}, ++{255, 59, 116}, ++{255, 59, 116}, ++{210, 84, 94}, ++{216, 81, 97}, ++{223, 78, 100}, ++{232, 73, 104}, ++{241, 69, 108}, ++{252, 64, 112}, ++{255, 59, 116}, ++{255, 59, 116}, ++{155, 44, 69}, ++{164, 45, 74}, ++{175, 46, 80}, ++{188, 46, 86}, ++{201, 44, 92}, ++{214, 42, 98}, ++{227, 39, 104}, ++{227, 39, 104}, ++{155, 44, 69}, ++{164, 45, 74}, ++{176, 46, 80}, ++{188, 46, 86}, ++{201, 44, 92}, ++{214, 42, 98}, ++{227, 39, 104}, ++{227, 39, 104}, ++{156, 44, 69}, ++{165, 46, 74}, ++{176, 46, 80}, ++{188, 46, 86}, ++{201, 44, 93}, ++{214, 42, 99}, ++{227, 39, 104}, ++{227, 39, 104}, ++{156, 45, 70}, ++{165, 46, 75}, ++{176, 47, 80}, ++{189, 46, 87}, ++{202, 45, 93}, ++{215, 42, 99}, ++{228, 40, 104}, ++{228, 40, 104}, ++{157, 46, 70}, ++{166, 47, 75}, ++{177, 47, 81}, ++{189, 47, 87}, ++{202, 45, 93}, ++{215, 43, 99}, ++{228, 40, 105}, ++{228, 40, 105}, ++{158, 47, 71}, ++{167, 48, 75}, ++{178, 48, 81}, ++{190, 47, 87}, ++{203, 46, 93}, ++{216, 43, 99}, ++{229, 40, 105}, ++{229, 40, 105}, ++{160, 48, 71}, ++{168, 49, 76}, ++{179, 49, 82}, ++{191, 48, 87}, ++{204, 46, 93}, ++{216, 44, 99}, ++{229, 41, 105}, ++{229, 41, 105}, ++{161, 50, 72}, ++{170, 50, 76}, ++{180, 50, 82}, ++{192, 49, 88}, ++{205, 47, 94}, ++{217, 44, 100}, ++{230, 41, 105}, ++{230, 41, 105}, ++{163, 51, 73}, ++{171, 51, 77}, ++{181, 51, 83}, ++{193, 50, 88}, ++{206, 48, 94}, ++{218, 45, 100}, ++{231, 42, 105}, ++{231, 42, 105}, ++{164, 53, 73}, ++{172, 53, 78}, ++{183, 52, 83}, ++{194, 51, 89}, ++{207, 48, 95}, ++{219, 46, 100}, ++{232, 42, 106}, ++{232, 42, 106}, ++{166, 54, 74}, ++{174, 54, 79}, ++{184, 53, 84}, ++{196, 52, 89}, ++{208, 49, 95}, ++{221, 46, 101}, ++{233, 43, 106}, ++{233, 43, 106}, ++{168, 56, 75}, ++{176, 56, 79}, ++{186, 54, 84}, ++{197, 53, 90}, ++{209, 50, 95}, ++{222, 47, 101}, ++{234, 44, 106}, ++{234, 44, 106}, ++{170, 58, 76}, ++{178, 57, 80}, ++{188, 56, 85}, ++{199, 54, 90}, ++{211, 51, 96}, ++{223, 48, 101}, ++{236, 44, 107}, ++{236, 44, 107}, ++{172, 60, 77}, ++{180, 59, 81}, ++{190, 57, 86}, ++{201, 55, 91}, ++{212, 52, 97}, ++{225, 49, 102}, ++{237, 45, 107}, ++{237, 45, 107}, ++{175, 61, 78}, ++{182, 60, 82}, ++{192, 58, 87}, ++{202, 56, 92}, ++{214, 53, 97}, ++{226, 50, 102}, ++{238, 46, 107}, ++{238, 46, 107}, ++{177, 63, 79}, ++{184, 62, 83}, ++{194, 60, 87}, ++{204, 57, 92}, ++{216, 54, 98}, ++{228, 51, 103}, ++{240, 47, 108}, ++{240, 47, 108}, ++{179, 65, 80}, ++{187, 63, 84}, ++{196, 61, 88}, ++{206, 58, 93}, ++{218, 55, 98}, ++{229, 51, 103}, ++{241, 48, 108}, ++{241, 48, 108}, ++{182, 66, 81}, ++{189, 65, 85}, ++{198, 62, 89}, ++{208, 60, 94}, ++{219, 56, 99}, ++{231, 52, 104}, ++{243, 48, 109}, ++{243, 48, 109}, ++{184, 68, 82}, ++{191, 66, 86}, ++{200, 64, 90}, ++{210, 61, 95}, ++{221, 57, 99}, ++{233, 53, 104}, ++{245, 49, 109}, ++{245, 49, 109}, ++{187, 70, 83}, ++{194, 68, 87}, ++{203, 65, 91}, ++{213, 62, 95}, ++{223, 58, 100}, ++{235, 54, 105}, ++{246, 50, 110}, ++{246, 50, 110}, ++{190, 71, 84}, ++{196, 69, 88}, ++{205, 66, 92}, ++{215, 63, 96}, ++{226, 59, 101}, ++{237, 55, 106}, ++{248, 51, 110}, ++{248, 51, 110}, ++{193, 73, 86}, ++{199, 71, 89}, ++{208, 68, 93}, ++{217, 64, 97}, ++{228, 61, 101}, ++{239, 56, 106}, ++{250, 52, 111}, ++{250, 52, 111}, ++{195, 74, 87}, ++{202, 72, 90}, ++{210, 69, 93}, ++{220, 66, 98}, ++{230, 62, 102}, ++{241, 57, 107}, ++{252, 53, 111}, ++{252, 53, 111}, ++{198, 76, 88}, ++{204, 74, 91}, ++{213, 70, 94}, ++{222, 67, 98}, ++{232, 63, 103}, ++{243, 58, 107}, ++{254, 54, 112}, ++{254, 54, 112}, ++{201, 77, 89}, ++{207, 75, 92}, ++{215, 72, 95}, ++{224, 68, 99}, ++{234, 64, 104}, ++{245, 59, 108}, ++{255, 55, 112}, ++{255, 55, 112}, ++{204, 79, 90}, ++{210, 76, 93}, ++{218, 73, 96}, ++{227, 69, 100}, ++{237, 65, 104}, ++{247, 60, 109}, ++{255, 56, 113}, ++{255, 56, 113}, ++{207, 80, 91}, ++{213, 78, 94}, ++{221, 74, 97}, ++{230, 70, 101}, ++{239, 66, 105}, ++{250, 62, 109}, ++{255, 57, 113}, ++{255, 57, 113}, ++{210, 81, 92}, ++{216, 79, 95}, ++{223, 75, 98}, ++{232, 71, 102}, ++{242, 67, 106}, ++{252, 63, 110}, ++{255, 58, 114}, ++{255, 58, 114}, ++{212, 82, 92}, ++{217, 79, 95}, ++{225, 76, 98}, ++{233, 72, 102}, ++{243, 68, 106}, ++{253, 63, 110}, ++{255, 58, 114}, ++{255, 58, 114}, ++{212, 82, 92}, ++{217, 79, 95}, ++{225, 76, 98}, ++{233, 72, 102}, ++{243, 68, 106}, ++{253, 63, 110}, ++{255, 58, 114}, ++{255, 58, 114}, ++{212, 82, 92}, ++{217, 79, 95}, ++{225, 76, 98}, ++{233, 72, 102}, ++{243, 68, 106}, ++{253, 63, 110}, ++{255, 58, 114}, ++{255, 58, 114}, ++{212, 82, 92}, ++{217, 79, 95}, ++{225, 76, 98}, ++{233, 72, 102}, ++{243, 68, 106}, ++{253, 63, 110}, ++{255, 58, 114}, ++{255, 58, 114}, ++{158, 42, 67}, ++{167, 43, 72}, ++{178, 44, 78}, ++{190, 44, 84}, ++{203, 43, 91}, ++{216, 40, 97}, ++{229, 38, 102}, ++{229, 38, 102}, ++{158, 42, 67}, ++{167, 43, 72}, ++{178, 44, 78}, ++{190, 44, 84}, ++{203, 43, 91}, ++{216, 41, 97}, ++{229, 38, 102}, ++{229, 38, 102}, ++{158, 42, 68}, ++{167, 44, 73}, ++{178, 44, 78}, ++{190, 44, 85}, ++{203, 43, 91}, ++{216, 41, 97}, ++{229, 38, 102}, ++{229, 38, 102}, ++{159, 43, 68}, ++{168, 44, 73}, ++{179, 45, 79}, ++{191, 44, 85}, ++{203, 43, 91}, ++{216, 41, 97}, ++{229, 38, 103}, ++{229, 38, 103}, ++{160, 44, 68}, ++{169, 45, 73}, ++{179, 46, 79}, ++{191, 45, 85}, ++{204, 44, 91}, ++{217, 41, 97}, ++{230, 39, 103}, ++{230, 39, 103}, ++{161, 45, 69}, ++{170, 46, 74}, ++{180, 46, 79}, ++{192, 46, 85}, ++{205, 44, 91}, ++{218, 42, 97}, ++{230, 39, 103}, ++{230, 39, 103}, ++{162, 46, 70}, ++{171, 47, 74}, ++{181, 47, 80}, ++{193, 46, 86}, ++{206, 45, 92}, ++{218, 42, 97}, ++{231, 39, 103}, ++{231, 39, 103}, ++{164, 47, 70}, ++{172, 48, 75}, ++{182, 48, 80}, ++{194, 47, 86}, ++{206, 45, 92}, ++{219, 43, 98}, ++{232, 40, 103}, ++{232, 40, 103}, ++{165, 49, 71}, ++{173, 49, 75}, ++{184, 49, 81}, ++{195, 48, 86}, ++{208, 46, 92}, ++{220, 43, 98}, ++{233, 40, 104}, ++{233, 40, 104}, ++{167, 51, 72}, ++{175, 51, 76}, ++{185, 50, 81}, ++{197, 49, 87}, ++{209, 47, 93}, ++{221, 44, 98}, ++{234, 41, 104}, ++{234, 41, 104}, ++{168, 52, 73}, ++{176, 52, 77}, ++{187, 51, 82}, ++{198, 50, 88}, ++{210, 48, 93}, ++{222, 45, 99}, ++{235, 42, 104}, ++{235, 42, 104}, ++{170, 54, 73}, ++{178, 54, 78}, ++{188, 53, 83}, ++{199, 51, 88}, ++{211, 48, 94}, ++{224, 46, 99}, ++{236, 42, 105}, ++{236, 42, 105}, ++{172, 56, 74}, ++{180, 55, 78}, ++{190, 54, 83}, ++{201, 52, 89}, ++{213, 49, 94}, ++{225, 46, 100}, ++{237, 43, 105}, ++{237, 43, 105}, ++{175, 57, 75}, ++{182, 57, 79}, ++{192, 55, 84}, ++{203, 53, 89}, ++{214, 50, 95}, ++{226, 47, 100}, ++{239, 44, 105}, ++{239, 44, 105}, ++{177, 59, 76}, ++{184, 58, 80}, ++{194, 56, 85}, ++{204, 54, 90}, ++{216, 51, 95}, ++{228, 48, 101}, ++{240, 45, 106}, ++{240, 45, 106}, ++{179, 61, 77}, ++{186, 60, 81}, ++{196, 58, 86}, ++{206, 55, 91}, ++{218, 52, 96}, ++{229, 49, 101}, ++{241, 45, 106}, ++{241, 45, 106}, ++{182, 63, 78}, ++{189, 61, 82}, ++{198, 59, 86}, ++{208, 57, 91}, ++{219, 54, 96}, ++{231, 50, 102}, ++{243, 46, 107}, ++{243, 46, 107}, ++{184, 64, 79}, ++{191, 63, 83}, ++{200, 61, 87}, ++{210, 58, 92}, ++{221, 55, 97}, ++{233, 51, 102}, ++{245, 47, 107}, ++{245, 47, 107}, ++{187, 66, 81}, ++{193, 64, 84}, ++{202, 62, 88}, ++{212, 59, 93}, ++{223, 56, 98}, ++{235, 52, 103}, ++{246, 48, 107}, ++{246, 48, 107}, ++{189, 68, 82}, ++{196, 66, 85}, ++{205, 63, 89}, ++{214, 60, 94}, ++{225, 57, 98}, ++{236, 53, 103}, ++{248, 49, 108}, ++{248, 49, 108}, ++{192, 69, 83}, ++{198, 67, 86}, ++{207, 65, 90}, ++{217, 62, 94}, ++{227, 58, 99}, ++{238, 54, 104}, ++{250, 50, 108}, ++{250, 50, 108}, ++{195, 71, 84}, ++{201, 69, 87}, ++{209, 66, 91}, ++{219, 63, 95}, ++{229, 59, 100}, ++{240, 55, 104}, ++{252, 51, 109}, ++{252, 51, 109}, ++{197, 72, 85}, ++{204, 70, 88}, ++{212, 67, 92}, ++{221, 64, 96}, ++{232, 60, 100}, ++{242, 56, 105}, ++{254, 52, 110}, ++{254, 52, 110}, ++{200, 74, 86}, ++{206, 72, 89}, ++{214, 69, 93}, ++{224, 65, 97}, ++{234, 61, 101}, ++{245, 57, 106}, ++{255, 53, 110}, ++{255, 53, 110}, ++{203, 75, 87}, ++{209, 73, 90}, ++{217, 70, 93}, ++{226, 66, 97}, ++{236, 62, 102}, ++{247, 58, 106}, ++{255, 54, 111}, ++{255, 54, 111}, ++{206, 77, 88}, ++{212, 74, 91}, ++{220, 71, 94}, ++{229, 68, 98}, ++{239, 64, 102}, ++{249, 59, 107}, ++{255, 55, 111}, ++{255, 55, 111}, ++{209, 78, 89}, ++{215, 76, 92}, ++{222, 73, 95}, ++{231, 69, 99}, ++{241, 65, 103}, ++{251, 60, 107}, ++{255, 56, 112}, ++{255, 56, 112}, ++{212, 80, 90}, ++{218, 77, 93}, ++{225, 74, 96}, ++{234, 70, 100}, ++{243, 66, 104}, ++{253, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 80, 91}, ++{219, 78, 93}, ++{227, 74, 97}, ++{235, 70, 100}, ++{245, 66, 104}, ++{255, 62, 108}, ++{255, 57, 113}, ++{255, 57, 113}, ++{214, 80, 91}, ++{219, 78, 93}, ++{227, 74, 97}, ++{235, 70, 100}, ++{245, 66, 104}, ++{255, 62, 108}, ++{255, 57, 113}, ++{255, 57, 113}, ++{214, 80, 91}, ++{219, 78, 93}, ++{227, 74, 97}, ++{235, 70, 100}, ++{245, 66, 104}, ++{255, 62, 108}, ++{255, 57, 113}, ++{255, 57, 113}, ++{214, 80, 91}, ++{219, 78, 93}, ++{227, 74, 97}, ++{235, 70, 100}, ++{245, 66, 104}, ++{255, 62, 108}, ++{255, 57, 113}, ++{255, 57, 113}, ++{159, 41, 67}, ++{168, 42, 71}, ++{179, 43, 77}, ++{191, 43, 83}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{159, 41, 67}, ++{168, 42, 72}, ++{179, 43, 77}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{160, 41, 67}, ++{168, 43, 72}, ++{179, 44, 78}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 102}, ++{230, 37, 102}, ++{160, 42, 67}, ++{169, 43, 72}, ++{180, 44, 78}, ++{192, 44, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 38, 102}, ++{230, 38, 102}, ++{161, 43, 68}, ++{170, 44, 72}, ++{181, 45, 78}, ++{192, 44, 84}, ++{205, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{162, 44, 68}, ++{171, 45, 73}, ++{181, 45, 78}, ++{193, 45, 84}, ++{206, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{163, 45, 69}, ++{172, 46, 73}, ++{182, 46, 79}, ++{194, 45, 85}, ++{207, 44, 91}, ++{219, 42, 97}, ++{232, 39, 102}, ++{232, 39, 102}, ++{165, 46, 69}, ++{173, 47, 74}, ++{184, 47, 79}, ++{195, 46, 85}, ++{207, 44, 91}, ++{220, 42, 97}, ++{233, 39, 102}, ++{233, 39, 102}, ++{166, 48, 70}, ++{174, 48, 74}, ++{185, 48, 80}, ++{196, 47, 86}, ++{208, 45, 91}, ++{221, 43, 97}, ++{234, 40, 103}, ++{234, 40, 103}, ++{168, 49, 71}, ++{176, 50, 75}, ++{186, 49, 80}, ++{198, 48, 86}, ++{210, 46, 92}, ++{222, 43, 97}, ++{235, 40, 103}, ++{235, 40, 103}, ++{170, 51, 72}, ++{178, 51, 76}, ++{188, 50, 81}, ++{199, 49, 87}, ++{211, 47, 92}, ++{223, 44, 98}, ++{236, 41, 103}, ++{236, 41, 103}, ++{172, 53, 73}, ++{179, 53, 77}, ++{189, 52, 82}, ++{200, 50, 87}, ++{212, 48, 93}, ++{224, 45, 98}, ++{237, 42, 104}, ++{237, 42, 104}, ++{174, 54, 74}, ++{181, 54, 77}, ++{191, 53, 82}, ++{202, 51, 88}, ++{214, 49, 93}, ++{226, 46, 99}, ++{238, 42, 104}, ++{238, 42, 104}, ++{176, 56, 74}, ++{183, 56, 78}, ++{193, 54, 83}, ++{204, 52, 88}, ++{215, 50, 94}, ++{227, 47, 99}, ++{239, 43, 104}, ++{239, 43, 104}, ++{178, 58, 75}, ++{185, 57, 79}, ++{195, 56, 84}, ++{205, 53, 89}, ++{217, 51, 94}, ++{229, 47, 100}, ++{241, 44, 105}, ++{241, 44, 105}, ++{180, 60, 76}, ++{187, 59, 80}, ++{197, 57, 85}, ++{207, 55, 90}, ++{219, 52, 95}, ++{230, 48, 100}, ++{242, 45, 105}, ++{242, 45, 105}, ++{183, 61, 78}, ++{190, 60, 81}, ++{199, 58, 86}, ++{209, 56, 90}, ++{220, 53, 96}, ++{232, 49, 101}, ++{244, 46, 106}, ++{244, 46, 106}, ++{185, 63, 79}, ++{192, 62, 82}, ++{201, 60, 86}, ++{211, 57, 91}, ++{222, 54, 96}, ++{234, 50, 101}, ++{245, 47, 106}, ++{245, 47, 106}, ++{188, 65, 80}, ++{194, 63, 83}, ++{203, 61, 87}, ++{213, 58, 92}, ++{224, 55, 97}, ++{235, 51, 102}, ++{247, 47, 107}, ++{247, 47, 107}, ++{190, 67, 81}, ++{197, 65, 84}, ++{206, 62, 88}, ++{215, 59, 93}, ++{226, 56, 97}, ++{237, 52, 102}, ++{249, 48, 107}, ++{249, 48, 107}, ++{193, 68, 82}, ++{199, 66, 85}, ++{208, 64, 89}, ++{218, 61, 93}, ++{228, 57, 98}, ++{239, 53, 103}, ++{251, 49, 108}, ++{251, 49, 108}, ++{196, 70, 83}, ++{202, 68, 86}, ++{210, 65, 90}, ++{220, 62, 94}, ++{230, 58, 99}, ++{241, 54, 103}, ++{252, 50, 108}, ++{252, 50, 108}, ++{198, 71, 84}, ++{205, 69, 87}, ++{213, 67, 91}, ++{222, 63, 95}, ++{232, 59, 99}, ++{243, 55, 104}, ++{254, 51, 109}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{215, 68, 92}, ++{225, 64, 96}, ++{235, 61, 100}, ++{245, 56, 105}, ++{255, 52, 109}, ++{255, 52, 109}, ++{204, 74, 86}, ++{210, 72, 89}, ++{218, 69, 93}, ++{227, 66, 97}, ++{237, 62, 101}, ++{247, 58, 105}, ++{255, 53, 110}, ++{255, 53, 110}, ++{207, 76, 87}, ++{213, 74, 90}, ++{221, 70, 93}, ++{230, 67, 97}, ++{239, 63, 102}, ++{250, 59, 106}, ++{255, 54, 110}, ++{255, 54, 110}, ++{210, 77, 88}, ++{216, 75, 91}, ++{223, 72, 94}, ++{232, 68, 98}, ++{242, 64, 102}, ++{252, 60, 107}, ++{255, 55, 111}, ++{255, 55, 111}, ++{213, 79, 89}, ++{219, 76, 92}, ++{226, 73, 95}, ++{235, 69, 99}, ++{244, 65, 103}, ++{254, 61, 107}, ++{255, 56, 111}, ++{255, 56, 111}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{159, 41, 67}, ++{168, 42, 71}, ++{179, 43, 77}, ++{191, 43, 83}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{159, 41, 67}, ++{168, 42, 72}, ++{179, 43, 77}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{160, 41, 67}, ++{168, 43, 72}, ++{179, 44, 78}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 102}, ++{230, 37, 102}, ++{160, 42, 67}, ++{169, 43, 72}, ++{180, 44, 78}, ++{192, 44, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 38, 102}, ++{230, 38, 102}, ++{161, 43, 68}, ++{170, 44, 72}, ++{181, 45, 78}, ++{192, 44, 84}, ++{205, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{162, 44, 68}, ++{171, 45, 73}, ++{181, 45, 78}, ++{193, 45, 84}, ++{206, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{163, 45, 69}, ++{172, 46, 73}, ++{182, 46, 79}, ++{194, 45, 85}, ++{207, 44, 91}, ++{219, 42, 97}, ++{232, 39, 102}, ++{232, 39, 102}, ++{165, 46, 69}, ++{173, 47, 74}, ++{184, 47, 79}, ++{195, 46, 85}, ++{207, 44, 91}, ++{220, 42, 97}, ++{233, 39, 102}, ++{233, 39, 102}, ++{166, 48, 70}, ++{174, 48, 74}, ++{185, 48, 80}, ++{196, 47, 86}, ++{208, 45, 91}, ++{221, 43, 97}, ++{234, 40, 103}, ++{234, 40, 103}, ++{168, 49, 71}, ++{176, 50, 75}, ++{186, 49, 80}, ++{198, 48, 86}, ++{210, 46, 92}, ++{222, 43, 97}, ++{235, 40, 103}, ++{235, 40, 103}, ++{170, 51, 72}, ++{178, 51, 76}, ++{188, 50, 81}, ++{199, 49, 87}, ++{211, 47, 92}, ++{223, 44, 98}, ++{236, 41, 103}, ++{236, 41, 103}, ++{172, 53, 73}, ++{179, 53, 77}, ++{189, 52, 82}, ++{200, 50, 87}, ++{212, 48, 93}, ++{224, 45, 98}, ++{237, 42, 104}, ++{237, 42, 104}, ++{174, 54, 74}, ++{181, 54, 77}, ++{191, 53, 82}, ++{202, 51, 88}, ++{214, 49, 93}, ++{226, 46, 99}, ++{238, 42, 104}, ++{238, 42, 104}, ++{176, 56, 74}, ++{183, 56, 78}, ++{193, 54, 83}, ++{204, 52, 88}, ++{215, 50, 94}, ++{227, 47, 99}, ++{239, 43, 104}, ++{239, 43, 104}, ++{178, 58, 75}, ++{185, 57, 79}, ++{195, 56, 84}, ++{205, 53, 89}, ++{217, 51, 94}, ++{229, 47, 100}, ++{241, 44, 105}, ++{241, 44, 105}, ++{180, 60, 76}, ++{187, 59, 80}, ++{197, 57, 85}, ++{207, 55, 90}, ++{219, 52, 95}, ++{230, 48, 100}, ++{242, 45, 105}, ++{242, 45, 105}, ++{183, 61, 78}, ++{190, 60, 81}, ++{199, 58, 86}, ++{209, 56, 90}, ++{220, 53, 96}, ++{232, 49, 101}, ++{244, 46, 106}, ++{244, 46, 106}, ++{185, 63, 79}, ++{192, 62, 82}, ++{201, 60, 86}, ++{211, 57, 91}, ++{222, 54, 96}, ++{234, 50, 101}, ++{245, 47, 106}, ++{245, 47, 106}, ++{188, 65, 80}, ++{194, 63, 83}, ++{203, 61, 87}, ++{213, 58, 92}, ++{224, 55, 97}, ++{235, 51, 102}, ++{247, 47, 107}, ++{247, 47, 107}, ++{190, 67, 81}, ++{197, 65, 84}, ++{206, 62, 88}, ++{215, 59, 93}, ++{226, 56, 97}, ++{237, 52, 102}, ++{249, 48, 107}, ++{249, 48, 107}, ++{193, 68, 82}, ++{199, 66, 85}, ++{208, 64, 89}, ++{218, 61, 93}, ++{228, 57, 98}, ++{239, 53, 103}, ++{251, 49, 108}, ++{251, 49, 108}, ++{196, 70, 83}, ++{202, 68, 86}, ++{210, 65, 90}, ++{220, 62, 94}, ++{230, 58, 99}, ++{241, 54, 103}, ++{252, 50, 108}, ++{252, 50, 108}, ++{198, 71, 84}, ++{205, 69, 87}, ++{213, 67, 91}, ++{222, 63, 95}, ++{232, 59, 99}, ++{243, 55, 104}, ++{254, 51, 109}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{215, 68, 92}, ++{225, 64, 96}, ++{235, 61, 100}, ++{245, 56, 105}, ++{255, 52, 109}, ++{255, 52, 109}, ++{204, 74, 86}, ++{210, 72, 89}, ++{218, 69, 93}, ++{227, 66, 97}, ++{237, 62, 101}, ++{247, 58, 105}, ++{255, 53, 110}, ++{255, 53, 110}, ++{207, 76, 87}, ++{213, 74, 90}, ++{221, 70, 93}, ++{230, 67, 97}, ++{239, 63, 102}, ++{250, 59, 106}, ++{255, 54, 110}, ++{255, 54, 110}, ++{210, 77, 88}, ++{216, 75, 91}, ++{223, 72, 94}, ++{232, 68, 98}, ++{242, 64, 102}, ++{252, 60, 107}, ++{255, 55, 111}, ++{255, 55, 111}, ++{213, 79, 89}, ++{219, 76, 92}, ++{226, 73, 95}, ++{235, 69, 99}, ++{244, 65, 103}, ++{254, 61, 107}, ++{255, 56, 111}, ++{255, 56, 111}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{159, 41, 67}, ++{168, 42, 71}, ++{179, 43, 77}, ++{191, 43, 83}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{159, 41, 67}, ++{168, 42, 72}, ++{179, 43, 77}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{160, 41, 67}, ++{168, 43, 72}, ++{179, 44, 78}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 102}, ++{230, 37, 102}, ++{160, 42, 67}, ++{169, 43, 72}, ++{180, 44, 78}, ++{192, 44, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 38, 102}, ++{230, 38, 102}, ++{161, 43, 68}, ++{170, 44, 72}, ++{181, 45, 78}, ++{192, 44, 84}, ++{205, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{162, 44, 68}, ++{171, 45, 73}, ++{181, 45, 78}, ++{193, 45, 84}, ++{206, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{163, 45, 69}, ++{172, 46, 73}, ++{182, 46, 79}, ++{194, 45, 85}, ++{207, 44, 91}, ++{219, 42, 97}, ++{232, 39, 102}, ++{232, 39, 102}, ++{165, 46, 69}, ++{173, 47, 74}, ++{184, 47, 79}, ++{195, 46, 85}, ++{207, 44, 91}, ++{220, 42, 97}, ++{233, 39, 102}, ++{233, 39, 102}, ++{166, 48, 70}, ++{174, 48, 74}, ++{185, 48, 80}, ++{196, 47, 86}, ++{208, 45, 91}, ++{221, 43, 97}, ++{234, 40, 103}, ++{234, 40, 103}, ++{168, 49, 71}, ++{176, 50, 75}, ++{186, 49, 80}, ++{198, 48, 86}, ++{210, 46, 92}, ++{222, 43, 97}, ++{235, 40, 103}, ++{235, 40, 103}, ++{170, 51, 72}, ++{178, 51, 76}, ++{188, 50, 81}, ++{199, 49, 87}, ++{211, 47, 92}, ++{223, 44, 98}, ++{236, 41, 103}, ++{236, 41, 103}, ++{172, 53, 73}, ++{179, 53, 77}, ++{189, 52, 82}, ++{200, 50, 87}, ++{212, 48, 93}, ++{224, 45, 98}, ++{237, 42, 104}, ++{237, 42, 104}, ++{174, 54, 74}, ++{181, 54, 77}, ++{191, 53, 82}, ++{202, 51, 88}, ++{214, 49, 93}, ++{226, 46, 99}, ++{238, 42, 104}, ++{238, 42, 104}, ++{176, 56, 74}, ++{183, 56, 78}, ++{193, 54, 83}, ++{204, 52, 88}, ++{215, 50, 94}, ++{227, 47, 99}, ++{239, 43, 104}, ++{239, 43, 104}, ++{178, 58, 75}, ++{185, 57, 79}, ++{195, 56, 84}, ++{205, 53, 89}, ++{217, 51, 94}, ++{229, 47, 100}, ++{241, 44, 105}, ++{241, 44, 105}, ++{180, 60, 76}, ++{187, 59, 80}, ++{197, 57, 85}, ++{207, 55, 90}, ++{219, 52, 95}, ++{230, 48, 100}, ++{242, 45, 105}, ++{242, 45, 105}, ++{183, 61, 78}, ++{190, 60, 81}, ++{199, 58, 86}, ++{209, 56, 90}, ++{220, 53, 96}, ++{232, 49, 101}, ++{244, 46, 106}, ++{244, 46, 106}, ++{185, 63, 79}, ++{192, 62, 82}, ++{201, 60, 86}, ++{211, 57, 91}, ++{222, 54, 96}, ++{234, 50, 101}, ++{245, 47, 106}, ++{245, 47, 106}, ++{188, 65, 80}, ++{194, 63, 83}, ++{203, 61, 87}, ++{213, 58, 92}, ++{224, 55, 97}, ++{235, 51, 102}, ++{247, 47, 107}, ++{247, 47, 107}, ++{190, 67, 81}, ++{197, 65, 84}, ++{206, 62, 88}, ++{215, 59, 93}, ++{226, 56, 97}, ++{237, 52, 102}, ++{249, 48, 107}, ++{249, 48, 107}, ++{193, 68, 82}, ++{199, 66, 85}, ++{208, 64, 89}, ++{218, 61, 93}, ++{228, 57, 98}, ++{239, 53, 103}, ++{251, 49, 108}, ++{251, 49, 108}, ++{196, 70, 83}, ++{202, 68, 86}, ++{210, 65, 90}, ++{220, 62, 94}, ++{230, 58, 99}, ++{241, 54, 103}, ++{252, 50, 108}, ++{252, 50, 108}, ++{198, 71, 84}, ++{205, 69, 87}, ++{213, 67, 91}, ++{222, 63, 95}, ++{232, 59, 99}, ++{243, 55, 104}, ++{254, 51, 109}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{215, 68, 92}, ++{225, 64, 96}, ++{235, 61, 100}, ++{245, 56, 105}, ++{255, 52, 109}, ++{255, 52, 109}, ++{204, 74, 86}, ++{210, 72, 89}, ++{218, 69, 93}, ++{227, 66, 97}, ++{237, 62, 101}, ++{247, 58, 105}, ++{255, 53, 110}, ++{255, 53, 110}, ++{207, 76, 87}, ++{213, 74, 90}, ++{221, 70, 93}, ++{230, 67, 97}, ++{239, 63, 102}, ++{250, 59, 106}, ++{255, 54, 110}, ++{255, 54, 110}, ++{210, 77, 88}, ++{216, 75, 91}, ++{223, 72, 94}, ++{232, 68, 98}, ++{242, 64, 102}, ++{252, 60, 107}, ++{255, 55, 111}, ++{255, 55, 111}, ++{213, 79, 89}, ++{219, 76, 92}, ++{226, 73, 95}, ++{235, 69, 99}, ++{244, 65, 103}, ++{254, 61, 107}, ++{255, 56, 111}, ++{255, 56, 111}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{159, 41, 67}, ++{168, 42, 71}, ++{179, 43, 77}, ++{191, 43, 83}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{159, 41, 67}, ++{168, 42, 72}, ++{179, 43, 77}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 101}, ++{230, 37, 101}, ++{160, 41, 67}, ++{168, 43, 72}, ++{179, 44, 78}, ++{191, 43, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 37, 102}, ++{230, 37, 102}, ++{160, 42, 67}, ++{169, 43, 72}, ++{180, 44, 78}, ++{192, 44, 84}, ++{204, 42, 90}, ++{217, 40, 96}, ++{230, 38, 102}, ++{230, 38, 102}, ++{161, 43, 68}, ++{170, 44, 72}, ++{181, 45, 78}, ++{192, 44, 84}, ++{205, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{162, 44, 68}, ++{171, 45, 73}, ++{181, 45, 78}, ++{193, 45, 84}, ++{206, 43, 90}, ++{218, 41, 96}, ++{231, 38, 102}, ++{231, 38, 102}, ++{163, 45, 69}, ++{172, 46, 73}, ++{182, 46, 79}, ++{194, 45, 85}, ++{207, 44, 91}, ++{219, 42, 97}, ++{232, 39, 102}, ++{232, 39, 102}, ++{165, 46, 69}, ++{173, 47, 74}, ++{184, 47, 79}, ++{195, 46, 85}, ++{207, 44, 91}, ++{220, 42, 97}, ++{233, 39, 102}, ++{233, 39, 102}, ++{166, 48, 70}, ++{174, 48, 74}, ++{185, 48, 80}, ++{196, 47, 86}, ++{208, 45, 91}, ++{221, 43, 97}, ++{234, 40, 103}, ++{234, 40, 103}, ++{168, 49, 71}, ++{176, 50, 75}, ++{186, 49, 80}, ++{198, 48, 86}, ++{210, 46, 92}, ++{222, 43, 97}, ++{235, 40, 103}, ++{235, 40, 103}, ++{170, 51, 72}, ++{178, 51, 76}, ++{188, 50, 81}, ++{199, 49, 87}, ++{211, 47, 92}, ++{223, 44, 98}, ++{236, 41, 103}, ++{236, 41, 103}, ++{172, 53, 73}, ++{179, 53, 77}, ++{189, 52, 82}, ++{200, 50, 87}, ++{212, 48, 93}, ++{224, 45, 98}, ++{237, 42, 104}, ++{237, 42, 104}, ++{174, 54, 74}, ++{181, 54, 77}, ++{191, 53, 82}, ++{202, 51, 88}, ++{214, 49, 93}, ++{226, 46, 99}, ++{238, 42, 104}, ++{238, 42, 104}, ++{176, 56, 74}, ++{183, 56, 78}, ++{193, 54, 83}, ++{204, 52, 88}, ++{215, 50, 94}, ++{227, 47, 99}, ++{239, 43, 104}, ++{239, 43, 104}, ++{178, 58, 75}, ++{185, 57, 79}, ++{195, 56, 84}, ++{205, 53, 89}, ++{217, 51, 94}, ++{229, 47, 100}, ++{241, 44, 105}, ++{241, 44, 105}, ++{180, 60, 76}, ++{187, 59, 80}, ++{197, 57, 85}, ++{207, 55, 90}, ++{219, 52, 95}, ++{230, 48, 100}, ++{242, 45, 105}, ++{242, 45, 105}, ++{183, 61, 78}, ++{190, 60, 81}, ++{199, 58, 86}, ++{209, 56, 90}, ++{220, 53, 96}, ++{232, 49, 101}, ++{244, 46, 106}, ++{244, 46, 106}, ++{185, 63, 79}, ++{192, 62, 82}, ++{201, 60, 86}, ++{211, 57, 91}, ++{222, 54, 96}, ++{234, 50, 101}, ++{245, 47, 106}, ++{245, 47, 106}, ++{188, 65, 80}, ++{194, 63, 83}, ++{203, 61, 87}, ++{213, 58, 92}, ++{224, 55, 97}, ++{235, 51, 102}, ++{247, 47, 107}, ++{247, 47, 107}, ++{190, 67, 81}, ++{197, 65, 84}, ++{206, 62, 88}, ++{215, 59, 93}, ++{226, 56, 97}, ++{237, 52, 102}, ++{249, 48, 107}, ++{249, 48, 107}, ++{193, 68, 82}, ++{199, 66, 85}, ++{208, 64, 89}, ++{218, 61, 93}, ++{228, 57, 98}, ++{239, 53, 103}, ++{251, 49, 108}, ++{251, 49, 108}, ++{196, 70, 83}, ++{202, 68, 86}, ++{210, 65, 90}, ++{220, 62, 94}, ++{230, 58, 99}, ++{241, 54, 103}, ++{252, 50, 108}, ++{252, 50, 108}, ++{198, 71, 84}, ++{205, 69, 87}, ++{213, 67, 91}, ++{222, 63, 95}, ++{232, 59, 99}, ++{243, 55, 104}, ++{254, 51, 109}, ++{254, 51, 109}, ++{201, 73, 85}, ++{207, 71, 88}, ++{215, 68, 92}, ++{225, 64, 96}, ++{235, 61, 100}, ++{245, 56, 105}, ++{255, 52, 109}, ++{255, 52, 109}, ++{204, 74, 86}, ++{210, 72, 89}, ++{218, 69, 93}, ++{227, 66, 97}, ++{237, 62, 101}, ++{247, 58, 105}, ++{255, 53, 110}, ++{255, 53, 110}, ++{207, 76, 87}, ++{213, 74, 90}, ++{221, 70, 93}, ++{230, 67, 97}, ++{239, 63, 102}, ++{250, 59, 106}, ++{255, 54, 110}, ++{255, 54, 110}, ++{210, 77, 88}, ++{216, 75, 91}, ++{223, 72, 94}, ++{232, 68, 98}, ++{242, 64, 102}, ++{252, 60, 107}, ++{255, 55, 111}, ++{255, 55, 111}, ++{213, 79, 89}, ++{219, 76, 92}, ++{226, 73, 95}, ++{235, 69, 99}, ++{244, 65, 103}, ++{254, 61, 107}, ++{255, 56, 111}, ++{255, 56, 111}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++{214, 79, 90}, ++{220, 77, 92}, ++{227, 74, 96}, ++{236, 70, 99}, ++{245, 66, 103}, ++{255, 61, 108}, ++{255, 57, 112}, ++{255, 57, 112}, ++}; ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/tve_reg_def.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/tve_reg_def.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/tve_reg_def.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/tve_reg_def.h 2010-01-26 17:33:14.112964374 +0000 +@@ -0,0 +1,334 @@ ++/*************************************************************************** ++* ++* TVE_REG_DEF.H ++* ++* registers defination for TVE. ++* ++*************************************************************************** ++* ++* Author(s) : Ray Sun-B17777 ++* Create Date : 2009-01-16 ++* Description : TV Display Test Case For Elvis TO2 3stack Board. ++* ++***************************************************************************/ ++ ++#ifndef _TVE_REG_DEF_ ++#define _TVE_REG_DEF_ ++ ++#include ++ ++#define CCM_CDCDR (CCM_BASE_ADDR + CCM_CDCDR_OFFSET) ++#define CCM_CDCDR_TVE_CLK_PRED 0x70000000 //the relevant mask for the tve_clk_pred[2:0] field ++ ++//#define TVE_BASE_ADDR 0x83FF000 ++#define TVE_REG_TVE_EN (TVE_BASE_ADDR + 0x1000),0x00000001 ++#define TVE_REG_TVDAC_SAMP_RATE (TVE_BASE_ADDR + 0x1000),0x00000006 ++#define TVE_REG_IPU_CLK_EN (TVE_BASE_ADDR + 0x1000),0x00000008 ++#define TVE_REG_DATA_SOURCE_SEL (TVE_BASE_ADDR + 0x1000),0x00000030 ++#define TVE_REG_INP_VIDEO_FORM (TVE_BASE_ADDR + 0x1000),0x00000040 ++#define TVE_REG_P2I_CONV_EN (TVE_BASE_ADDR + 0x1000),0x00000080 ++#define TVE_REG_TV_STAND (TVE_BASE_ADDR + 0x1000),0x00000f00 ++#define TVE_REG_TV_OUT_MODE (TVE_BASE_ADDR + 0x1000),0x00007000 ++#define TVE_REG_SD_PED_AMP_CONT (TVE_BASE_ADDR + 0x1000),0x00030000 ++#define TVE_REG_SYNC_CH_0_EN (TVE_BASE_ADDR + 0x1000),0x00100000 ++#define TVE_REG_SYNC_CH_1_EN (TVE_BASE_ADDR + 0x1000),0x00200000 ++#define TVE_REG_SYNC_CH_2_EN (TVE_BASE_ADDR + 0x1000),0x00400000 ++#define TVE_REG_ACT_LINE_OFFSET (TVE_BASE_ADDR + 0x1000),0x07000000 ++#define TVE_REG_COM_CONF_REG (TVE_BASE_ADDR + 0x1000),0x07737fff ++#define TVE_REG_DEFLICK_EN (TVE_BASE_ADDR + 0x1004),0x00000001 ++#define TVE_REG_DEFLICK_MEAS_WIN (TVE_BASE_ADDR + 0x1004),0x00000002 ++#define TVE_REG_DEFLICK_COEF (TVE_BASE_ADDR + 0x1004),0x00000070 ++#define TVE_REG_DEFLICK_LOW_THRESH (TVE_BASE_ADDR + 0x1004),0x0000ff00 ++#define TVE_REG_DEFLICK_MID_THRESH (TVE_BASE_ADDR + 0x1004),0x00ff0000 ++#define TVE_REG_DEFLICK_HIGH_THRESH (TVE_BASE_ADDR + 0x1004),0xff000000 ++#define TVE_REG_LUMA_FILT_CONT_REG_0 (TVE_BASE_ADDR + 0x1004),0xffffff73 ++#define TVE_REG_V_SHARP_EN (TVE_BASE_ADDR + 0x1008),0x00000001 ++#define TVE_REG_V_SHARP_COEF (TVE_BASE_ADDR + 0x1008),0x00000070 ++#define TVE_REG_V_SHARP_LOW_THRESH (TVE_BASE_ADDR + 0x1008),0x0000ff00 ++#define TVE_REG_V_SHARP_HIGH_THRESH (TVE_BASE_ADDR + 0x1008),0xff000000 ++#define TVE_REG_LUMA_FILT_CONT_REG_1 (TVE_BASE_ADDR + 0x1008),0xff00ff71 ++#define TVE_REG_H_SHARP_EN (TVE_BASE_ADDR + 0x100c),0x00000001 ++#define TVE_REG_H_SHARP_COEF (TVE_BASE_ADDR + 0x100c),0x00000070 ++#define TVE_REG_H_SHARP_LOW_THRESH (TVE_BASE_ADDR + 0x100c),0x0000ff00 ++#define TVE_REG_H_SHARP_HIGH_THRESH (TVE_BASE_ADDR + 0x100c),0xff000000 ++#define TVE_REG_LUMA_FILT_CONT_REG_2 (TVE_BASE_ADDR + 0x100c),0xff00ff71 ++#define TVE_REG_DERING_EN (TVE_BASE_ADDR + 0x1010),0x00000001 ++#define TVE_REG_SUPP_FILTER_TYPE (TVE_BASE_ADDR + 0x1010),0x00000006 ++#define TVE_REG_DERING_COEF (TVE_BASE_ADDR + 0x1010),0x00000070 ++#define TVE_REG_DERING_LOW_THRESH (TVE_BASE_ADDR + 0x1010),0x0000ff00 ++#define TVE_REG_DERING_MID_THRESH (TVE_BASE_ADDR + 0x1010),0x00ff0000 ++#define TVE_REG_DERING_HIGH_THRESH (TVE_BASE_ADDR + 0x1010),0xff000000 ++#define TVE_REG_LUMA_FILT_CONT_REG_3 (TVE_BASE_ADDR + 0x1010),0xffffff77 ++#define TVE_REG_LUMA_SA_EN (TVE_BASE_ADDR + 0x1014),0x00000001 ++#define TVE_REG_SA_H_POINTS_NUM (TVE_BASE_ADDR + 0x1014),0x00000030 ++#define TVE_REG_SA_V_POINTS_NUM (TVE_BASE_ADDR + 0x1014),0x00000300 ++#define TVE_REG_LUMA_SA_CONT_REG_0 (TVE_BASE_ADDR + 0x1014),0x00000331 ++#define TVE_REG_SA_WIN_WIDTH (TVE_BASE_ADDR + 0x1018),0x000000ff ++#define TVE_REG_SA_WIN_HEIGHT (TVE_BASE_ADDR + 0x1018),0x0000ff00 ++#define TVE_REG_SA_WIN_H_OFFSET (TVE_BASE_ADDR + 0x1018),0x00ff0000 ++#define TVE_REG_SA_WIN_V_OFFSET (TVE_BASE_ADDR + 0x1018),0xff000000 ++#define TVE_REG_LUMA_SA_CONT_REG_1 (TVE_BASE_ADDR + 0x1018),0xffffffff ++#define TVE_REG_LPU_DEFLICK_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x000000ff ++#define TVE_REG_LPU_V_SHARP_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x0000ff00 ++#define TVE_REG_LPU_H_SHARP_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x00ff0000 ++#define TVE_REG_LPU_DERING_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0xff000000 ++#define TVE_REG_LUMA_SA_STAT_REG_0 (TVE_BASE_ADDR + 0x101c),0xffffffff ++#define TVE_REG_LPU_LUMA_MEAN (TVE_BASE_ADDR + 0x1020),0x000000ff ++#define TVE_REG_LUMA_SA_STAT_REG_1 (TVE_BASE_ADDR + 0x1020),0x000000ff ++#define TVE_REG_CHROMA_V_FILT_EN (TVE_BASE_ADDR + 0x1024),0x00000001 ++#define TVE_REG_CHROMA_BW (TVE_BASE_ADDR + 0x1024),0x00000070 ++#define TVE_REG_SCH_PHASE (TVE_BASE_ADDR + 0x1024),0x0000ff00 ++#define TVE_REG_CHROMA_CONT_REG (TVE_BASE_ADDR + 0x1024),0x0000ff71 ++#define TVE_REG_TVDAC_0_GAIN (TVE_BASE_ADDR + 0x1028),0x0000003f ++#define TVE_REG_TVDAC_0_OFFSET (TVE_BASE_ADDR + 0x1028),0x0000ff00 ++#define TVE_REG_BG_RDY_TIME (TVE_BASE_ADDR + 0x1028),0x00ff0000 ++#define TVE_REG_TVDAC_0_CONT_REG (TVE_BASE_ADDR + 0x1028),0x00ffff3f ++#define TVE_REG_TVDAC_1_GAIN (TVE_BASE_ADDR + 0x102c),0x0000003f ++#define TVE_REG_TVDAC_1_OFFSET (TVE_BASE_ADDR + 0x102c),0x0000ff00 ++#define TVE_REG_TVDAC_1_CONT_REG (TVE_BASE_ADDR + 0x102c),0x0000ff3f ++#define TVE_REG_TVDAC_2_GAIN (TVE_BASE_ADDR + 0x1030),0x0000003f ++#define TVE_REG_TVDAC_2_OFFSET (TVE_BASE_ADDR + 0x1030),0x0000ff00 ++#define TVE_REG_TVDAC_2_CONT_REG (TVE_BASE_ADDR + 0x1030),0x0000ff3f ++#define TVE_REG_CD_EN (TVE_BASE_ADDR + 0x1034),0x00000001 ++#define TVE_REG_CD_TRIG_MODE (TVE_BASE_ADDR + 0x1034),0x00000002 ++#define TVE_REG_CD_STBY_MON_PER (TVE_BASE_ADDR + 0x1034),0x000000f0 ++#define TVE_REG_CD_CH_0_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000100 ++#define TVE_REG_CD_CH_1_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000200 ++#define TVE_REG_CD_CH_2_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000400 ++#define TVE_REG_CD_REF_MODE (TVE_BASE_ADDR + 0x1034),0x00000800 ++#define TVE_REG_CD_CH_0_LM_EN (TVE_BASE_ADDR + 0x1034),0x00010000 ++#define TVE_REG_CD_CH_1_LM_EN (TVE_BASE_ADDR + 0x1034),0x00020000 ++#define TVE_REG_CD_CH_2_LM_EN (TVE_BASE_ADDR + 0x1034),0x00040000 ++#define TVE_REG_CD_CH_0_SM_EN (TVE_BASE_ADDR + 0x1034),0x00100000 ++#define TVE_REG_CD_CH_1_SM_EN (TVE_BASE_ADDR + 0x1034),0x00200000 ++#define TVE_REG_CD_CH_2_SM_EN (TVE_BASE_ADDR + 0x1034),0x00400000 ++#define TVE_REG_CD_CONT_REG (TVE_BASE_ADDR + 0x1034),0x00770ff3 ++#define TVE_REG_CC_SD_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000001 ++#define TVE_REG_CC_SD_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000002 ++#define TVE_REG_CC_SD_BOOST_EN (TVE_BASE_ADDR + 0x1038),0x00000004 ++#define TVE_REG_CGMS_SD_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000010 ++#define TVE_REG_CGMS_SD_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000020 ++#define TVE_REG_CGMS_SD_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00000040 ++#define TVE_REG_WSS_SD_EN (TVE_BASE_ADDR + 0x1038),0x00000080 ++#define TVE_REG_CGMS_HD_A_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000100 ++#define TVE_REG_CGMS_HD_A_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000200 ++#define TVE_REG_CGMS_HD_A_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00000400 ++#define TVE_REG_CGMS_HD_B_F1_EN (TVE_BASE_ADDR + 0x1038),0x00001000 ++#define TVE_REG_CGMS_HD_B_F2_EN (TVE_BASE_ADDR + 0x1038),0x00002000 ++#define TVE_REG_CGMS_HD_B_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00004000 ++#define TVE_REG_CGMS_HD_B_F1_HEADER (TVE_BASE_ADDR + 0x1038),0x003f0000 ++#define TVE_REG_CGMS_HD_B_F2_HEADER (TVE_BASE_ADDR + 0x1038),0x3f000000 ++#define TVE_REG_VBI_DATA_CONT_REG (TVE_BASE_ADDR + 0x1038),0x3f3f77f7 ++#define TVE_REG_CGMS_SD_HD_A_F1_DATA (TVE_BASE_ADDR + 0x103c),0x000fffff ++#define TVE_REG_VBI_DATA_REG_0 (TVE_BASE_ADDR + 0x103c),0x000fffff ++#define TVE_REG_CGMS_SD_HD_A_F2_DATA (TVE_BASE_ADDR + 0x1040),0x000fffff ++#define TVE_REG_VBI_DATA_REG_1 (TVE_BASE_ADDR + 0x1040),0x000fffff ++#define TVE_REG_CC_SD_CGMS_HD_B_F1_DATA_0 (TVE_BASE_ADDR + 0x1044),0xffffffff ++#define TVE_REG_VBI_DATA_REG_2 (TVE_BASE_ADDR + 0x1044),0xffffffff ++#define TVE_REG_WSS_SD_CGMS_HD_B_F1_DATA_1 (TVE_BASE_ADDR + 0x1048),0xffffffff ++#define TVE_REG_VBI_DATA_REG_3 (TVE_BASE_ADDR + 0x1048),0xffffffff ++#define TVE_REG_CGMS_HD_B_F1_DATA_2 (TVE_BASE_ADDR + 0x104c),0xffffffff ++#define TVE_REG_VBI_DATA_REG_4 (TVE_BASE_ADDR + 0x104c),0xffffffff ++#define TVE_REG_CGMS_HD_B_F1_DATA_3 (TVE_BASE_ADDR + 0x1050),0xffffffff ++#define TVE_REG_VBI_DATA_REG_5 (TVE_BASE_ADDR + 0x1050),0xffffffff ++#define TVE_REG_CC_SD_CGMS_HD_B_F2_DATA_0 (TVE_BASE_ADDR + 0x1054),0xffffffff ++#define TVE_REG_VBI_DATA_REG_6 (TVE_BASE_ADDR + 0x1054),0xffffffff ++#define TVE_REG_CGMS_HD_B_F2_DATA_1 (TVE_BASE_ADDR + 0x1058),0xffffffff ++#define TVE_REG_VBI_DATA_REG_7 (TVE_BASE_ADDR + 0x1058),0xffffffff ++#define TVE_REG_CGMS_HD_B_F2_DATA_2 (TVE_BASE_ADDR + 0x105c),0xffffffff ++#define TVE_REG_VBI_DATA_REG_8 (TVE_BASE_ADDR + 0x105c),0xffffffff ++#define TVE_REG_CGMS_HD_B_F2_DATA_3 (TVE_BASE_ADDR + 0x1060),0xffffffff ++#define TVE_REG_VBI_DATA_REG_9 (TVE_BASE_ADDR + 0x1060),0xffffffff ++#define TVE_REG_CD_LM_IEN (TVE_BASE_ADDR + 0x1064),0x00000001 ++#define TVE_REG_CD_SM_IEN (TVE_BASE_ADDR + 0x1064),0x00000002 ++#define TVE_REG_CD_MON_END_IEN (TVE_BASE_ADDR + 0x1064),0x00000004 ++#define TVE_REG_CC_SD_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000008 ++#define TVE_REG_CC_SD_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000010 ++#define TVE_REG_CGMS_SD_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000020 ++#define TVE_REG_CGMS_SD_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000040 ++#define TVE_REG_WSS_SD_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000080 ++#define TVE_REG_CGMS_HD_A_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000100 ++#define TVE_REG_CGMS_HD_A_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000200 ++#define TVE_REG_CGMS_HD_B_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000400 ++#define TVE_REG_CGMS_HD_B_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000800 ++#define TVE_REG_TVE_FIELD_END_IEN (TVE_BASE_ADDR + 0x1064),0x00001000 ++#define TVE_REG_TVE_FRAME_END_IEN (TVE_BASE_ADDR + 0x1064),0x00002000 ++#define TVE_REG_SA_MEAS_END_IEN (TVE_BASE_ADDR + 0x1064),0x00004000 ++#define TVE_REG_INT_CONT_REG (TVE_BASE_ADDR + 0x1064),0x00007fff ++#define TVE_REG_CDCU_CD_LM_INT (TVE_BASE_ADDR + 0x1068),0x00000001 ++#define TVE_REG_CDCU_CD_SM_INT (TVE_BASE_ADDR + 0x1068),0x00000002 ++#define TVE_REG_CDCU_CD_MON_END_INT (TVE_BASE_ADDR + 0x1068),0x00000004 ++#define TVE_REG_VDG_CC_SD_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000008 ++#define TVE_REG_VDG_CC_SD_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000010 ++#define TVE_REG_VDG_CGMS_SD_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000020 ++#define TVE_REG_VDG_CGMS_SD_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000040 ++#define TVE_REG_VDG_WSS_SD_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000080 ++#define TVE_REG_VDG_CGMS_HD_A_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000100 ++#define TVE_REG_VDG_CGMS_HD_A_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000200 ++#define TVE_REG_VDG_CGMS_HD_B_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000400 ++#define TVE_REG_VDG_CGMS_HD_B_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000800 ++#define TVE_REG_TSC_TVE_FIELD_END_INT (TVE_BASE_ADDR + 0x1068),0x00001000 ++#define TVE_REG_TSC_TVE_FRAME_END_INT (TVE_BASE_ADDR + 0x1068),0x00002000 ++#define TVE_REG_LPU_SA_MEAS_END_INT (TVE_BASE_ADDR + 0x1068),0x00004000 ++#define TVE_REG_CD_CH_0_LM_ST (TVE_BASE_ADDR + 0x1068),0x00010000 ++#define TVE_REG_CD_CH_1_LM_ST (TVE_BASE_ADDR + 0x1068),0x00020000 ++#define TVE_REG_CD_CH_2_LM_ST (TVE_BASE_ADDR + 0x1068),0x00040000 ++#define TVE_REG_CD_CH_0_SM_ST (TVE_BASE_ADDR + 0x1068),0x00100000 ++#define TVE_REG_CD_CH_1_SM_ST (TVE_BASE_ADDR + 0x1068),0x00200000 ++#define TVE_REG_CD_CH_2_SM_ST (TVE_BASE_ADDR + 0x1068),0x00400000 ++#define TVE_REG_CD_MAN_TRIG (TVE_BASE_ADDR + 0x1068),0x01000000 ++#define TVE_REG_BG_READY (TVE_BASE_ADDR + 0x1068),0x02000000 ++#define TVE_REG_STAT_REG (TVE_BASE_ADDR + 0x1068),0x03777fff ++#define TVE_REG_TVDAC_TEST_MODE (TVE_BASE_ADDR + 0x106c),0x00000007 ++#define TVE_REG_TVDAC_0_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000010 ++#define TVE_REG_TVDAC_1_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000020 ++#define TVE_REG_TVDAC_2_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000040 ++#define TVE_REG_TVDAC_TEST_SINE_FREQ (TVE_BASE_ADDR + 0x106c),0x00000700 ++#define TVE_REG_TVDAC_TEST_SINE_LEVEL (TVE_BASE_ADDR + 0x106c),0x00003000 ++#define TVE_REG_COLORBAR_TYPE (TVE_BASE_ADDR + 0x106c),0x00010000 ++#define TVE_REG_TST_MODE_REG (TVE_BASE_ADDR + 0x106c),0x00013777 ++#define TVE_REG_H_TIMING_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000001 ++#define TVE_REG_LUMA_FILT_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000002 ++#define TVE_REG_SC_FREQ_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000004 ++#define TVE_REG_CSCM_COEF_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000008 ++#define TVE_REG_BLANK_LEVEL_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000010 ++#define TVE_REG_VBI_DATA_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000020 ++#define TVE_REG_TVDAC_DROP_COMP_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000040 ++#define TVE_REG_USER_MODE_CONT_REG (TVE_BASE_ADDR + 0x1070),0x0000007f ++#define TVE_REG_SD_VBI_T0_USR (TVE_BASE_ADDR + 0x1074),0x0000003f ++#define TVE_REG_SD_VBI_T1_USR (TVE_BASE_ADDR + 0x1074),0x0003ff00 ++#define TVE_REG_SD_VBI_T2_USR (TVE_BASE_ADDR + 0x1074),0x3ff00000 ++#define TVE_REG_SD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1074),0x3ff3ff3f ++#define TVE_REG_SD_ACT_T0_USR (TVE_BASE_ADDR + 0x1078),0x0000007f ++#define TVE_REG_SD_ACT_T1_USR (TVE_BASE_ADDR + 0x1078),0x00001f00 ++#define TVE_REG_SD_ACT_T2_USR (TVE_BASE_ADDR + 0x1078),0x007f0000 ++#define TVE_REG_SD_ACT_T3_USR (TVE_BASE_ADDR + 0x1078),0x7f000000 ++#define TVE_REG_SD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1078),0x7f7f1f7f ++#define TVE_REG_SD_ACT_T4_USR (TVE_BASE_ADDR + 0x107c),0x000007ff ++#define TVE_REG_SD_ACT_T5_USR (TVE_BASE_ADDR + 0x107c),0x003ff000 ++#define TVE_REG_SD_ACT_T6_USR (TVE_BASE_ADDR + 0x107c),0x3f000000 ++#define TVE_REG_SD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x107c),0x3f3ff7ff ++#define TVE_REG_HD_VBI_ACT_T0_USR (TVE_BASE_ADDR + 0x1080),0x0000007f ++#define TVE_REG_HD_VBI_T1_USR (TVE_BASE_ADDR + 0x1080),0x0001ff00 ++#define TVE_REG_HD_VBI_T2_USR (TVE_BASE_ADDR + 0x1080),0x7ff00000 ++#define TVE_REG_HD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1080),0x7ff1ff7f ++#define TVE_REG_HD_VBI_T3_USR (TVE_BASE_ADDR + 0x1084),0x00001fff ++#define TVE_REG_HD_ACT_T1_USR (TVE_BASE_ADDR + 0x1084),0x01ff0000 ++#define TVE_REG_HD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1084),0x01ff1fff ++#define TVE_REG_HD_ACT_T2_USR (TVE_BASE_ADDR + 0x1088),0x00000fff ++#define TVE_REG_HD_ACT_T3_USR (TVE_BASE_ADDR + 0x1088),0x1fff0000 ++#define TVE_REG_HD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1088),0x1fff0fff ++#define TVE_REG_DEFLICK_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x108c),0x00ffffff ++#define TVE_REG_LUMA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x108c),0x00ffffff ++#define TVE_REG_V_SHARP_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1090),0x00ffffff ++#define TVE_REG_LUMA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1090),0x00ffffff ++#define TVE_REG_H_SHARP_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1094),0x00ffffff ++#define TVE_REG_LUMA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1094),0x00ffffff ++#define TVE_REG_DERING_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1098),0x00ffffff ++#define TVE_REG_LUMA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x1098),0x00ffffff ++#define TVE_REG_DATA_CLIP_USR (TVE_BASE_ADDR + 0x109c),0x00000001 ++#define TVE_REG_BRIGHT_CORR_USR (TVE_BASE_ADDR + 0x109c),0x00003f00 ++#define TVE_REG_CSCM_A_COEF_USR (TVE_BASE_ADDR + 0x109c),0x07ff0000 ++#define TVE_REG_CSC_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x109c),0x07ff3f01 ++#define TVE_REG_CSCM_B_COEF_USR (TVE_BASE_ADDR + 0x10a0),0x00000fff ++#define TVE_REG_CSCM_C_COEF_USR (TVE_BASE_ADDR + 0x10a0),0x07ff0000 ++#define TVE_REG_CSC_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10a0),0x07ff0fff ++#define TVE_REG_CSCM_D_COEF_USR (TVE_BASE_ADDR + 0x10a4),0x00000fff ++#define TVE_REG_CSCM_E_COEF_USR (TVE_BASE_ADDR + 0x10a4),0x1fff0000 ++#define TVE_REG_CSC_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10a4),0x1fff0fff ++#define TVE_REG_BLANKING_CH_0_USR (TVE_BASE_ADDR + 0x10a8),0x000003ff ++#define TVE_REG_BLANKING_CH_1_USR (TVE_BASE_ADDR + 0x10a8),0x000ffc00 ++#define TVE_REG_BLANKING_CH_2_USR (TVE_BASE_ADDR + 0x10a8),0x3ff00000 ++#define TVE_REG_BLANK_USR_CONT_REG (TVE_BASE_ADDR + 0x10a8),0x3fffffff ++#define TVE_REG_SC_FREQ_USR (TVE_BASE_ADDR + 0x10ac),0x3fffffff ++#define TVE_REG_SD_MOD_USR_CONT_REG (TVE_BASE_ADDR + 0x10ac),0x3fffffff ++#define TVE_REG_VBI_DATA_START_TIME_USR (TVE_BASE_ADDR + 0x10b0),0x00000fff ++#define TVE_REG_VBI_DATA_STOP_TIME_USR (TVE_BASE_ADDR + 0x10b0),0x0fff0000 ++#define TVE_REG_VBI_DATA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x10b0),0x0fff0fff ++#define TVE_REG_VBI_PACKET_START_TIME_USR (TVE_BASE_ADDR + 0x10b4),0x00000fff ++#define TVE_REG_VBI_DATA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10b4),0x00000fff ++#define TVE_REG_CC_SD_RUNIN_START_TIME_USR (TVE_BASE_ADDR + 0x10b8),0x00000fff ++#define TVE_REG_CC_SD_RUNIN_DIV_NUM_USR (TVE_BASE_ADDR + 0x10b8),0x07ff0000 ++#define TVE_REG_VBI_DATA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10b8),0x07ff0fff ++#define TVE_REG_CC_SD_CGMS_HD_B_DIV_NUM_USR (TVE_BASE_ADDR + 0x10bc),0x0000007f ++#define TVE_REG_CC_SD_CGMS_HD_B_DIV_DENOM_USR (TVE_BASE_ADDR + 0x10bc),0x1fff0000 ++#define TVE_REG_VBI_DATA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x10bc),0x1fff007f ++#define TVE_REG_WSS_CGMS_SD_CGMS_HD_A_DIV_NUM_USR (TVE_BASE_ADDR + 0x10c0),0x0000007f ++#define TVE_REG_WSS_CGMS_SD_CGMS_HD_A_DIV_DENOM_USR (TVE_BASE_ADDR + 0x10c0),0x1fff0000 ++#define TVE_REG_VBI_DATA_USR_CONT_REG_4 (TVE_BASE_ADDR + 0x10c0),0x1fff007f ++#define TVE_REG_TVDAC_0_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x0000000f ++#define TVE_REG_TVDAC_1_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x000000f0 ++#define TVE_REG_TVDAC_2_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x00000f00 ++#define TVE_REG_DROP_COMP_USR_CONT_REG (TVE_BASE_ADDR + 0x10c4),0x00000fff ++#define TVE_REG_MV_WORD_0 (TVE_BASE_ADDR + 0x10c8),0xffffffff ++#define TVE_REG_MAC_WORD_REG_0 (TVE_BASE_ADDR + 0x10c8),0xffffffff ++#define TVE_REG_MV_WORD_1 (TVE_BASE_ADDR + 0x10cc),0xffffffff ++#define TVE_REG_MAC_WORD_REG_1 (TVE_BASE_ADDR + 0x10cc),0xffffffff ++#define TVE_REG_MV_WORD_2 (TVE_BASE_ADDR + 0x10d0),0xffffffff ++#define TVE_REG_MAC_WORD_REG_2 (TVE_BASE_ADDR + 0x10d0),0xffffffff ++#define TVE_REG_MV_WORD_3 (TVE_BASE_ADDR + 0x10d4),0xffffffff ++#define TVE_REG_MAC_WORD_REG_3 (TVE_BASE_ADDR + 0x10d4),0xffffffff ++#define TVE_REG_MV_WORD_4 (TVE_BASE_ADDR + 0x10d8),0xffffffff ++#define TVE_REG_MAC_WORD_REG_4 (TVE_BASE_ADDR + 0x10d8),0xffffffff ++#define TVE_REG_MV_DATA_READY (TVE_BASE_ADDR + 0x10dc),0x00000001 ++#define TVE_REG_MAC_CONT_REG (TVE_BASE_ADDR + 0x10dc),0x00000001 ++ ++//TVEV2 - registers defines without masking : ++#define TVEV2_REG_COM_CONF_REG (TVE_BASE_ADDR + 0x1000) ++#define TVEV2_REG_LUMA_FILT_CONT_REG_0 (TVE_BASE_ADDR + 0x1004) ++#define TVEV2_REG_LUMA_FILT_CONT_REG_1 (TVE_BASE_ADDR + 0x1008) ++#define TVEV2_REG_LUMA_FILT_CONT_REG_2 (TVE_BASE_ADDR + 0x100c) ++#define TVEV2_REG_LUMA_FILT_CONT_REG_3 (TVE_BASE_ADDR + 0x1010) ++#define TVEV2_REG_LUMA_SA_CONT_REG_0 (TVE_BASE_ADDR + 0x1014) ++#define TVEV2_REG_LUMA_SA_CONT_REG_1 (TVE_BASE_ADDR + 0x1018) ++#define TVEV2_REG_LUMA_SA_STAT_REG_0 (TVE_BASE_ADDR + 0x101c) ++#define TVEV2_REG_LUMA_SA_STAT_REG_1 (TVE_BASE_ADDR + 0x1020) ++#define TVEV2_REG_CHROMA_CONT_REG (TVE_BASE_ADDR + 0x1024) ++#define TVEV2_REG_TVDAC_0_CONT_REG (TVE_BASE_ADDR + 0x1028) ++#define TVEV2_REG_TVDAC_1_CONT_REG (TVE_BASE_ADDR + 0x102c) ++#define TVEV2_REG_TVDAC_2_CONT_REG (TVE_BASE_ADDR + 0x1030) ++#define TVEV2_REG_CD_CONT_REG (TVE_BASE_ADDR + 0x1034) ++#define TVEV2_REG_VBI_DATA_CONT_REG (TVE_BASE_ADDR + 0x1038) ++#define TVEV2_REG_VBI_DATA_REG_0 (TVE_BASE_ADDR + 0x103c) ++#define TVEV2_REG_VBI_DATA_REG_1 (TVE_BASE_ADDR + 0x1040) ++#define TVEV2_REG_VBI_DATA_REG_2 (TVE_BASE_ADDR + 0x1044) ++#define TVEV2_REG_VBI_DATA_REG_3 (TVE_BASE_ADDR + 0x1048) ++#define TVEV2_REG_VBI_DATA_REG_4 (TVE_BASE_ADDR + 0x104c) ++#define TVEV2_REG_VBI_DATA_REG_5 (TVE_BASE_ADDR + 0x1050) ++#define TVEV2_REG_VBI_DATA_REG_6 (TVE_BASE_ADDR + 0x1054) ++#define TVEV2_REG_VBI_DATA_REG_7 (TVE_BASE_ADDR + 0x1058) ++#define TVEV2_REG_VBI_DATA_REG_8 (TVE_BASE_ADDR + 0x105c) ++#define TVEV2_REG_VBI_DATA_REG_9 (TVE_BASE_ADDR + 0x1060) ++#define TVEV2_REG_INT_CONT_REG (TVE_BASE_ADDR + 0x1064) ++#define TVEV2_REG_STAT_REG (TVE_BASE_ADDR + 0x1068) ++#define TVEV2_REG_TST_MODE_REG (TVE_BASE_ADDR + 0x106c) ++#define TVEV2_REG_USER_MODE_CONT_REG (TVE_BASE_ADDR + 0x1070) ++#define TVEV2_REG_SD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1074) ++#define TVEV2_REG_SD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1078) ++#define TVEV2_REG_SD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x107c) ++#define TVEV2_REG_HD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1080) ++#define TVEV2_REG_HD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1084) ++#define TVEV2_REG_HD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1088) ++#define TVEV2_REG_LUMA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x108c) ++#define TVEV2_REG_LUMA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1090) ++#define TVEV2_REG_LUMA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1094) ++#define TVEV2_REG_LUMA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x1098) ++#define TVEV2_REG_CSC_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x109c) ++#define TVEV2_REG_CSC_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10a0) ++#define TVEV2_REG_CSC_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10a4) ++#define TVEV2_REG_BLANK_USR_CONT_REG (TVE_BASE_ADDR + 0x10a8) ++#define TVEV2_REG_SD_MOD_USR_CONT_REG (TVE_BASE_ADDR + 0x10ac) ++#define TVEV2_REG_VBI_DATA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x10b0) ++#define TVEV2_REG_VBI_DATA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10b4) ++#define TVEV2_REG_VBI_DATA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10b8) ++#define TVEV2_REG_VBI_DATA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x10bc) ++#define TVEV2_REG_VBI_DATA_USR_CONT_REG_4 (TVE_BASE_ADDR + 0x10c0) ++#define TVEV2_REG_DROP_COMP_USR_CONT_REG (TVE_BASE_ADDR + 0x10c4) ++#define TVEV2_REG_MAC_WORD_REG_0 (TVE_BASE_ADDR + 0x10c8) ++#define TVEV2_REG_MAC_WORD_REG_1 (TVE_BASE_ADDR + 0x10cc) ++#define TVEV2_REG_MAC_WORD_REG_2 (TVE_BASE_ADDR + 0x10d0) ++#define TVEV2_REG_MAC_WORD_REG_3 (TVE_BASE_ADDR + 0x10d4) ++#define TVEV2_REG_MAC_WORD_REG_4 (TVE_BASE_ADDR + 0x10d8) ++#define TVEV2_REG_MAC_CONT_REG (TVE_BASE_ADDR + 0x10dc) ++ ++#endif +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/xec_dls.h redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/xec_dls.h +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/include/xec_dls.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/include/xec_dls.h 2010-01-26 17:33:14.112964374 +0000 +@@ -0,0 +1,101 @@ ++/* ++ * Copyright 2008 Freescale Semiconductor, Inc. ++ * ++ * All modifications are confidential and proprietary information ++ * of Freescale Semiconductor, Inc. ALL RIGHTS RESERVED. ++ * ++ */ ++/*! ++ * @file xec_dls.h ++ * ++ * @brief This file contains the XEC_LCD dls part declarations. ++ * ++ */ ++#ifndef __XEC_DLS_H__ ++#define __XEC_DLS_H__ ++ ++#define SSIM_XSTEP 4 ++#define SSIM_YSTEP 4 ++ ++/* default configures for xec dls algorithm */ ++#define XECDLS_frameStep 6 ++#define XECDLS_xStep 4 ++#define XECDLS_yStep 4 ++#define XECDLS_yMaxPrime 235 ++#define XECDLS_disTh 500 /*xxxx = xx.xx */ ++#define XECDLS_blDeltaMax 30 ++#define XECDLS_alphaMax 138 /* 149 */ ++#define XECDLS_yRangeMax 255 ++#define XECDLS_yRangeMin 0 ++#define XECDLS_FFilter_Step 3 ++#define XECDLS_ALPHA_Step 109 /* gamma=2. or 108 if gamma=2.20 */ ++#define XECDLS_BLDelay 20 ++#define XECDLS_BLStep 3 ++ ++enum XECDLS_FRAME_FORMAT { ++ XECDLS_YV12 = 0, ++ XECDLS_RGB888, ++ XECDLS_YUYV, ++}; ++ ++struct xecDlsFrameInfo { ++ unsigned char *framePointer; ++ int width; ++ int height; ++ int rectTop; ++ int rectBottom; ++ int rectLeft; ++ int rectRight; ++ int ambientBacklight; ++ enum XECDLS_FRAME_FORMAT frameFormat; ++ int bytesPerPixel; ++ int index; ++}; ++ ++struct xecDlsConfig { ++ int yMaxPrime; ++ int yRangeMin; ++ int yRangeMax; ++ int xStep; ++ int yStep; ++ int disThreshold; ++ int alphaMax; ++ int blDeltaMax; ++ int frameStep; ++ int blStep; ++ int blDelay; ++}; ++ ++struct xecDlsOutput { ++ unsigned short pendingAlpha; ++ int pendingBLChange; ++ int pending; ++}; ++struct xec_dls_params{ ++ int prevCurrent; ++ int curCurrent; ++ int diffCurrent; ++ int prevAlpha; ++ int curAlpha; ++ int diffAlpha; ++ int stepSize; ++ int stepNum; ++ int stepCounter; ++ int lastStep; ++}; ++ ++typedef struct image_block{ ++ unsigned int startAddr; ++ int blockXSize; ++ int blockYSize; ++ int xStride; ++ int yStride; ++}image_block_t; ++ ++void xec_dls_core_init(void); ++void xec_dls_core(struct xecDlsFrameInfo g_xecDlsCoreFrameInfo); ++void xec_dls_stream_init(void); ++int xec_dls_perform(unsigned char *frame, int xSize, int ySize, ++ int pixelformat, int index); ++#endif ++ +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_common.c redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_common.c +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_common.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_common.c 2010-01-26 17:33:14.112964374 +0000 +@@ -0,0 +1,241 @@ ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//===========================================================================*/ ++/*************************************************************************** ++* ++* IPU_COMMON.C ++* ++* Copyright 2005-2006 by Freescale Semiconductor, Inc. ++* All modifications are confidential and proprietary information ++* of Freescale Semiconductor, Inc. ALL RIGHTS RESERVED. ++* ++*************************************************************************** ++* ++* Author(s) : Ray Sun-B17777 ++* Create Date : 2008-11-10 ++* Description : common functions definition for IPU API. ++* ++***************************************************************************/ ++#include ++#ifdef CYGPKG_REDBOOT ++#include ++#endif ++#include ++#ifdef CYGSEM_REDBOOT_FLASH_CONFIG ++#include ++#endif ++#ifdef CYGOPT_REDBOOT_FIS ++#include ++#endif ++#include ++ ++/* ++* write bit fields of special IPU regs ++*/ ++void ipu_write_field(unsigned int id_addr, unsigned int id_mask, unsigned int data) ++{ ++ unsigned int rdata; ++ id_addr += IPU_CTRL_BASE_ADDR; ++ rdata = readl(id_addr); ++ rdata &= ~id_mask; ++ rdata |= (data * (id_mask & -id_mask)) & id_mask; ++ writel(rdata, id_addr); ++} ++ ++/* ++* enable ipu display ++*/ ++void ipu_enable_display(void) ++{ ++ //enable DI0 (display interface 1) ++ ipu_write_field(IPU_IPU_CONF__DP_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DC_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DI0_EN, 1); ++ ipu_write_field(IPU_IPU_CONF__DI1_EN, 1); ++#ifdef CYGPKG_HAL_ARM_MX51_3STACK ++ ipu_write_field(IPU_IPU_CONF__CSI1_EN, 1); ++#endif ++} ++ ++/* ++* disable ipu display ++*/ ++void ipu_disable_display(void) ++{ ++ ipu_write_field(IPU_IPU_CONF__DI0_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DI1_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DP_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DC_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__IC_EN, 0); ++#ifdef CYGPKG_HAL_ARM_MX51_3STACK ++ ipu_write_field(IPU_IPU_CONF__CSI0_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__CSI1_EN, 0); ++ ipu_write_field(IPU_IPU_CONF__SMFC_EN, 0); ++#endif ++ ipu_write_field(IPU_IC_CONF__PP_EN, 0); ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, 0); ++ ipu_write_field(IPU_IC_CONF__PRPENC_EN, 0); ++} ++ ++/*! ++* this function is used to reset ipu by SRC(system reset controller) ++* the return value should be negative if resetting timeout ++*/ ++static int ipu_sw_reset(int timeout) ++{ ++ int tmpVal; ++ int ipuOffset = 0x3; ++ tmpVal = readl(SRC_BASE_ADDR); ++ writel(tmpVal | (0x1 << ipuOffset), SRC_BASE_ADDR); ++ while (timeout > 0) { ++ tmpVal = readl(SRC_BASE_ADDR) & (0x1 << ipuOffset); ++ timeout--; ++ if (tmpVal == 0) ++ return 0; ++ } ++ diag_printf("Error: ipu software reset time out!!\n"); ++ return -1; ++} ++ ++display_buffer_info_t display_buffer = {0}; ++ ++/*! ++* load the logo from nand flash to memory. ++*/ ++static void do_logo_load(void) ++{ ++ unsigned int fis_addr; ++ int ret = 0xFF; ++ void *err_addr; ++ unsigned int logo_size; ++ struct fis_image_desc *img; ++ ++ /* Read the logo from storage media */ ++ if ((img = fis_lookup("logo", NULL)) == (struct fis_image_desc *)0) { ++ diag_printf("No logo partition found in the fis table, logo not loaded\n"); ++ return; ++ } ++ ++ fis_addr = img->flash_base; ++ logo_size = img->size; ++ ret = FLASH_READ((void *)fis_addr, (void *)DISPLAY_BUFFER_ADDR, logo_size, (void **)&err_addr); ++ if(ret != 0) { ++ diag_printf("Load logo from FLASH to MEMORY failed! error code : 0x%0x",ret); ++ } ++} ++ ++extern int display_ready; ++static void redboot_init_display(void) ++{ ++ bool fastlogo_feature_enable; ++ int ok; ++ ++ display_buffer.startAddr = DISPLAY_BUFFER_ADDR; ++ display_buffer.height = LCD_HEIGHT; ++ display_buffer.width = LCD_WIDTH; ++ display_buffer.dataFormat = RGB565; ++ display_buffer.bpp = 16; // bit per pixel ++ ++ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, ++ "fastlogo_enable", &fastlogo_feature_enable, CONFIG_BOOL); ++ ++ if(ok && fastlogo_feature_enable) { ++ do_logo_load(); ++ } ++ ++ ipu_sw_reset(0x10000); // go to SRC module and reset the IPU ++ ++ /* ++ * do_logo_load() do: ++ -- 1) load image from flash to display buffer ++ -- 2) setup the global variable like below ++ display_buffer.startAddr = DISPLAY_BUFFER_ADDR; ++ display_buffer.height = LCD_HEIGHT; ++ display_buffer.width = LCD_WIDTH; ++ display_buffer.dataFormat = RGB565; ++ display_buffer.bpp = 16; // bit per pixel ++ */ ++ mxc_ipu_iomux_config(); ++ ++ //turn on backlight through PMIC calls. TODO: Remove those pmic functions and use existing ones!!!! ++ lcd_backlit_on(); ++ ++ // setup lcd panel through MIPI_HSC_BASE_ADDR and also IPU registers. ++ // calls epson_lcd_spi_simulate() to setup microcode and then write to IPU ++ // also calls epson_lcd_rst() ++ lcd_config(); ++ ++ // Setup IPU IDMAC - Image DMA Controller ++ // Controls the memory port; transfers data to/from system memory ++ fastlogo_dma(); ++ ++ // Setup IPU DMFC - Display Multi FIFO Controller ++ // Controls FIFO’s for IDMAC channels related to the display system ++ fastlogo_dmfc(); ++ ++ // Setup IPU DC - DC - Display Controller ++ // Controls the display ports. It calls: ++ // -- 1) ipu_dc_microcode_config() ++ // -- 2) ipu_dc_microcode_event() ++ // -- 3) ipu_dc_write_channel_config ++ // -- 4) ipu_dc_display_config(2, 2 /*paralell */ , 0, display_buffer.width); ++ // -- 5) ipu_dc_map(1, RGB666); ++ fastlogo_dc(); ++ ++ // Setup IPU DI - Display Interface ++ // Provides interface to displays, display controllers and related devices. ++ // IPUv3 includes 2 such blocks ++ fastlogo_di(); ++ ++ // Simple write to some IPU registes ++ ipu_enable_display(); ++ ++ // do some IDMA IPU calls ++ ipu_idmac_channel_buf_ready(DISPLAY_CHANNEL, 0); ++ ++ display_ready = 1; ++} ++ ++#ifdef CYGPKG_REDBOOT ++RedBoot_init(redboot_init_display, RedBoot_INIT_SECOND); ++#endif ++ ++RedBoot_config_option("Enable fast logo display at boot", ++ fastlogo_enable, ++ ALWAYS_ENABLED, true, ++ CONFIG_BOOL, ++ false ++ ); +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_display.c redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_display.c +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_display.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_display.c 2010-01-26 17:33:14.122962874 +0000 +@@ -0,0 +1,144 @@ ++//========================================================================== ++// ++// IPU_DI.c ++// ++// common functions definitions for IPU modules operation ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include // Hardware definitions ++ ++/* ++* this function is used to config the waveform generator in the DI ++*/ ++void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_waveform_gen) ++{ ++ ipu_write_field(DI_SWGEN0_RUN_VALUE_M1(di, pointer), sync_waveform_gen.runValue); ++ ipu_write_field(DI_SWGEN0_RUN_RESOL(di, pointer), sync_waveform_gen.runResolution); ++ ipu_write_field(DI_SWGEN0_OFFSET_VALUE(di, pointer), sync_waveform_gen.offsetValue); ++ ipu_write_field(DI_SWGEN0_OFFSET_RESOL(di, pointer), sync_waveform_gen.offsetResolution); ++ ipu_write_field(DI_SWGEN1_CNT_POL_GEN_EN(di, pointer), sync_waveform_gen.cntPolarityGenEn); ++ ipu_write_field(DI_SWGEN1_CNT_AUTOLOAD(di, pointer), sync_waveform_gen.cntAutoReload); ++ ipu_write_field(DI_SWGEN1_CNT_CLR_SEL(di, pointer), sync_waveform_gen.cntClrSel); ++ ipu_write_field(DI_SWGEN1_CNT_DOW(di, pointer), sync_waveform_gen.cntDown); ++ ipu_write_field(DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer), sync_waveform_gen.cntPolarityTrigSel); ++ ipu_write_field(DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer), sync_waveform_gen.cntPolarityClrSel); ++ ipu_write_field(DI_SWGEN1_CNT_CNT_UP(di, pointer), sync_waveform_gen.cntUp); ++ ipu_write_field(DI_STEP_RPT(di, pointer), sync_waveform_gen.stepRepeat); ++ ++ return; ++} ++ ++void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst, int pt0, ++ int pt1, int pt2, int pt3, int pt4, int pt5, int pt6) ++{ ++ unsigned int regVal = 0; ++ regVal = ++ (access << 24) | (component << 16) | (cst << 14) | (pt6 << 12) | (pt5 << 10) | (pt4 << 8) | ++ (pt3 << 6) | (pt2 << 4) | (pt1 << 2) | pt0; ++ ++ if (di == 0) { ++ writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI0_DW_GEN_0__ADDR + pointer * 4); ++ } else { ++ writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI1_DW_GEN_0__ADDR + pointer * 4); ++ } ++ return; ++} ++ ++void ipu_di_waveform_config(int di, int pointer, int set, int up, int down) ++{ ++ ipu_write_field(DI_WAVESET_UP(di, pointer, set), up); ++ ipu_write_field(DI_WAVESET_DOWN(di, pointer, set), down); ++ ++ return; ++} ++ ++int ipu_di_bsclk_gen(int di, int division, int up, int down) ++{ ++ switch (di) { ++ case 0: ++ ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET, 0); ++ ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD, division); ++ ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN, down); ++ ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP, up); ++ break; ++ ++ case 1: ++ ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET, 0); ++ ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD, division); ++ ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN, down); ++ ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP, up); ++ break; ++ ++ default: ++ ERRDP("Wrong di pointer!!\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++int ipu_di_screen_set(int di, int screen_height) ++{ ++ switch (di) { ++ case 0: ++ ipu_write_field(IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT, screen_height); ++ break; ++ ++ case 1: ++ ipu_write_field(IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT, screen_height); ++ break; ++ ++ default: ++ ERRDP("Wrong di pointer!!\n"); ++ return -1; ++ } ++ return 0; ++} ++int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel) ++{ ++ switch (di) { ++ case 0: ++ ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START, line_prediction); ++ ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL, vsync_sel); ++ ipu_write_field(IPU_DI0_GENERAL__DI0_CLK_EXT, clk_sel); ++ ++ ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK, 1); ++ ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_3, 0); //HSYNC polarity, active low ++ ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_2, 0); //VSYNC polarity, active low ++ ipu_write_field(IPU_DI0_POL__DI0_DRDY_POLARITY_15, 1); //VIDEO_DATA_EN polarity, active hign ++ ++ /*release ipu DI0 counter */ ++ ipu_write_field(IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE, 1); ++ break; ++ ++ case 1: ++ ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START, line_prediction); ++ ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL, vsync_sel); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_DISP_Y_SEL, hsync_sel); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_CLK_EXT, clk_sel); ++ ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK, 0); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_8, 1); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_5, 1); ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_3, 1); //HSYNC POLARITY ++ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_2, 1); //VSYNC POLARITY ++ ipu_write_field(IPU_DI1_POL__DI1_DRDY_POLARITY_15, 1); ++ /*release ipu DI1 counter */ ++ ipu_write_field(IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE, 1); ++ break; ++ ++ default: ++ ERRDP("Wrong di pointer!!\n"); ++ return -1; ++ } ++ return 0; ++} +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_dma.c redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_dma.c +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_dma.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_dma.c 2010-01-26 17:33:14.122962874 +0000 +@@ -0,0 +1,223 @@ ++//========================================================================== ++// ++// IPU_COMMON.c ++// ++// common functions definitions for IPU modules operation ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++ ++void ipu_idmac_params_init(ipu_channel_parameter_t * ipu_channel_params_ptr) ++{ ++ memset((void *)ipu_channel_params_ptr, 0, sizeof(ipu_channel_parameter_t)); ++} ++ ++/* ++* config the dma channel to be interleaved mode ++*/ ++void ipu_idmac_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params) ++{ ++ int w0_d0 = 0, w0_d1 = 0, w0_d2 = 0, w0_d3 = 0, w0_d4 = 0, w1_d0 = 0, w1_d1 = 0, w1_d2 = ++ 0, w1_d3 = 0, w1_d4 = 0; ++ ++ w0_d0 = ipu_channel_params.xb << 19 | ipu_channel_params.yv << 10 | ipu_channel_params.xv; ++ w0_d1 = ++ ipu_channel_params.sy << 26 | ipu_channel_params.sx << 14 | ipu_channel_params. ++ cf << 13 | ipu_channel_params.nsb_b << 12 | ipu_channel_params.yb; ++ w0_d2 = ++ ipu_channel_params.sm << 22 | ipu_channel_params.sdx << 15 | ipu_channel_params. ++ ns << 5 | ipu_channel_params.sy >> 6; ++ w0_d3 = ++ ipu_channel_params.fw << 29 | ipu_channel_params.cae << 28 | ipu_channel_params. ++ cap << 27 | ipu_channel_params.the << 26 | ipu_channel_params.vf << 25 | ipu_channel_params. ++ hf << 24 | ipu_channel_params.rot << 23 | ipu_channel_params.bm << 21 | ipu_channel_params. ++ bndm << 18 | ipu_channel_params.so << 17 | ipu_channel_params. ++ dim << 16 | ipu_channel_params.dec_sel << 14 | ipu_channel_params. ++ bpp << 11 | ipu_channel_params.sdry << 10 | ipu_channel_params. ++ sdrx << 9 | ipu_channel_params.sdy << 2 | ipu_channel_params.sce << 1 | ipu_channel_params. ++ scc; ++ w0_d4 = ipu_channel_params.fh << 10 | ipu_channel_params.fw >> 3; ++ ++ w1_d0 = ipu_channel_params.eba1 << 29 | ipu_channel_params.eba0; ++ w1_d1 = ipu_channel_params.ilo << 26 | ipu_channel_params.eba1 >> 3; ++ w1_d2 = ++ ipu_channel_params.th << 31 | ipu_channel_params.id << 29 | ipu_channel_params. ++ albm << 26 | ipu_channel_params.alu << 25 | ipu_channel_params. ++ pfs << 21 | ipu_channel_params.npb << 14 | ipu_channel_params.ilo >> 6; ++ w1_d3 = ++ ipu_channel_params.wid3 << 29 | ipu_channel_params.wid2 << 26 | ipu_channel_params. ++ wid1 << 23 | ipu_channel_params.wid0 << 20 | ipu_channel_params. ++ sl << 6 | ipu_channel_params.th >> 1; ++ w1_d4 = ++ ipu_channel_params.ofs3 << 15 | ipu_channel_params.ofs2 << 10 | ipu_channel_params. ++ ofs1 << 5 | ipu_channel_params.ofs0; ++ ++ /* config the cpmem */ ++ writel(w0_d0, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA0_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w0_d1, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA1_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w0_d2, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA2_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w0_d3, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA3_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w0_d4, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA4_INT__ADDR + (ipu_channel_params.channel << 6)); ++ ++ writel(w1_d0, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA0_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w1_d1, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA1_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w1_d2, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA2_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w1_d3, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA3_INT__ADDR + (ipu_channel_params.channel << 6)); ++ writel(w1_d4, ++ IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA4_INT__ADDR + (ipu_channel_params.channel << 6)); ++ ++} ++ ++void ipu_idmac_channel_buf_ready(int channel, int buf) ++{ ++ int idx = channel / 32; ++ int offset = channel % 32; ++ if (idx) { ++ if (buf) { ++ ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR, 0); ++ ipu_write_field(IPU_IPU_CH_BUF1_RDY1__ADDR, 1 << offset, 1); ++ } else { ++ ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR, 0); ++ ipu_write_field(IPU_IPU_CH_BUF0_RDY1__ADDR, 1 << offset, 1); ++ } ++ } else { ++ if (buf) { ++ ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR, 0); ++ ipu_write_field(IPU_IPU_CH_BUF1_RDY0__ADDR, 1 << offset, 1); ++ } else { ++ ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR, 0); ++ ipu_write_field(IPU_IPU_CH_BUF0_RDY0__ADDR, 1 << offset, 1); ++ } ++ } ++} ++ ++void ipu_idmac_channel_mode_sel(int channel, int double_buf_en) ++{ ++ int idx = channel / 32; ++ int offset = channel % 32; ++ ipu_write_field(IPU_IPU_CH_DB_MODE_SEL_0__ADDR + idx * 4, 1 << offset, double_buf_en); ++} ++ ++void ipu_idmac_channel_enable(int channel, int enable) ++{ ++ int idx = channel / 32; ++ int offset = channel % 32; ++ ipu_write_field(IPU_IDMAC_CH_EN_1__ADDR + idx * 4, 1 << offset, enable); ++} ++ ++int ipu_idmac_channel_busy(int channel) ++{ ++ int idx, offset; ++ idx = channel / 32; ++ offset = channel % 32; ++ return ((readl(IPU_CTRL_BASE_ADDR + IPU_IDMAC_CH_BUSY_1__ADDR + 4 * idx) & (1 << offset)) >> ++ offset); ++} ++int ipu_idmac_chan_cur_buff(int channel) ++{ ++ int idx, offset; ++ idx = channel / 32; ++ offset = channel % 32; ++ return ((readl(IPU_CTRL_BASE_ADDR + IPU_IPU_CUR_BUF_0__ADDR + 4 * idx) & (1 << offset)) >> ++ offset); ++} ++ ++int ipu_idamc_chan_eof_int(int channel) ++{ ++ int idx, offset; ++ idx = channel / 32; ++ offset = channel % 32; ++ return ((readl(IPU_CTRL_BASE_ADDR + IPU_IPU_INT_STAT_1__ADDR + 4 * idx) & (1 << offset)) >> ++ offset); ++} ++ ++int ipu_idmac_chan_till_idle(int channel, int timeout) ++{ ++ int i = 0; ++ unsigned int chanBusy; ++ ++ while (i < timeout) { ++ chanBusy = ipu_idmac_channel_busy(channel); ++ if (!chanBusy) { ++// diag_printf("\ncount cycles:%d\n",i); ++ __asm("nop"); ++ return 0; ++ } ++ i++; ++ } ++ ERRDP("can not get channel %d idle state\n", channel); ++ return -1; ++} ++ ++/* ++* allocate dmfc fifo for ipu display channel ++*/ ++int ipu_dmfc_fifo_allocate(int channel, int fifo_size, int burst_size, int offset_addr) ++{ ++ ++ if (fifo_size > 7 || fifo_size < 0) { ++ ERRDP("FIFO size is wrong! range from 0 to 7.\n"); ++ return -1; ++ } ++ if (burst_size > 3 || burst_size < 0) { ++ ERRDP("Burst size is wrong! range from 0 to 3.\n"); ++ return -1; ++ } ++ if (offset_addr < 0 || offset_addr > 7) { ++ ERRDP("Start addr of FIFO is wrong! range from 0 to 7.\n"); ++ return -1; ++ } ++ switch (channel) { ++ case 28: ++ ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1, fifo_size); ++ ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1, burst_size); ++ ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1, offset_addr); ++ ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1, 0); ++ ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1, 0); ++ ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1, 0); ++ ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_1, 0); ++ break; ++ ++ case 23: ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B, fifo_size); ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B, burst_size); ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B, offset_addr); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B, 0); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B, 0); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B, 0); ++ ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_5B, 0); ++ break; ++ ++ case 27: ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F, fifo_size); ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F, burst_size); ++ ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F, offset_addr); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F, 0); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F, 0); ++ ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F, 0); ++ ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_5F, 0); ++ break; ++ default: ++ ERRDP("Channel selection error!!\n"); ++ return -1; ++ } ++ return 0; ++} +diff -urNad redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_proc.c redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_proc.c +--- redboot-imx-200952~/packages/devs/ipu/arm/imx/current/src/ipu_proc.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/ipu/arm/imx/current/src/ipu_proc.c 2010-01-26 17:33:14.122962874 +0000 +@@ -0,0 +1,776 @@ ++//========================================================================== ++// ++// IPU_COMMON.c ++// ++// common functions definitions for IPU modules operation ++// ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Ray Sun ++// Create Date: 2008-07-31 ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++ ++extern struct xec_dls_params xecDlsParams; ++ ++void ipu_ic_enable(int ic_enable, int irt_enable) ++{ ++ ipu_write_field(IPU_IPU_CONF__IC_EN, ic_enable); ++ ipu_write_field(IPU_IPU_CONF__IRT_EN, irt_enable); ++} ++ ++/* ++* this function is used to config the rotation/resizing task perform by the Image Converter ++*/ ++void ipu_ic_task_config(ipu_task_params_t task_params) ++{ ++ int resCoff = 0, downsCoff = 0; ++ switch (task_params.taskType) { ++ case PrP_ENC_TASK: ++ ipu_write_field(IPU_IC_CONF__PRPENC_EN, 0); ++ ipu_write_field(IPU_IC_CONF__RWS_EN, 1); ++ ipu_write_field(IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID, 1); ++ ipu_write_field(IPU_IC_IDMAC_1__CB0_BURST_16, 1); // set to 16bps ++ ipu_write_field(IPU_IC_IDMAC_1__CB6_BURST_16, 1); ++ ipu_write_field(IPU_IC_CONF__PRPENC_EN, 1); ++ ipu_write_field(IPU_IC_CONF__PRPENC_ROT_EN, task_params.rotEnable); ++ /* set rotation task */ ++ if (task_params.rotEnable) { ++ ipu_write_field(IPU_IC_IDMAC_1__T1_FLIP_LR, task_params.rotInfo.HorizFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T1_FLIP_UD, task_params.rotInfo.VertFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T1_ROT, task_params.rotInfo.rotation); ++ } ++ /* set resizing task */ ++ if (task_params.resEnable) { ++ ipu_write_field(IPU_IC_IDMAC_2__T1_FR_HEIGHT, task_params.resInfo.outHeight - 1); ++ ipu_write_field(IPU_IC_IDMAC_3__T1_FR_WIDTH, task_params.resInfo.outWidth - 1); ++ ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth, ++ &resCoff, &downsCoff); ++ ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H, downsCoff); ++ ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H, resCoff); ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight, ++ &resCoff, &downsCoff); ++ ++ ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V, downsCoff); ++ ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V, resCoff); ++ } ++ ipu_write_field(IPU_IC_CONF__PRPENC_EN, 1); ++ break; ++ ++ case PrP_VF_TASK: ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, 0); ++ ipu_write_field(IPU_IC_CONF__RWS_EN, 1); ++ ipu_write_field(IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID, 1); ++ ipu_write_field(IPU_IC_IDMAC_1__CB1_BURST_16, 1); // set to 16bps ++ ipu_write_field(IPU_IC_IDMAC_1__CB6_BURST_16, 1); ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1); ++ ipu_write_field(IPU_IC_CONF__PRPVF_ROT_EN, task_params.rotEnable); ++ // set rotation ++ if (task_params.rotEnable) { ++ ipu_write_field(IPU_IC_IDMAC_1__T2_FLIP_LR, task_params.rotInfo.HorizFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T2_FLIP_UD, task_params.rotInfo.VertFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T2_ROT, task_params.rotInfo.rotation); ++ } ++ // set resizing ++ if (task_params.resEnable) { ++ ipu_write_field(IPU_IC_IDMAC_2__T2_FR_HEIGHT, task_params.resInfo.outHeight - 1); ++ ipu_write_field(IPU_IC_IDMAC_3__T2_FR_WIDTH, task_params.resInfo.outWidth - 1); ++ ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth, ++ &resCoff, &downsCoff); ++ ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H, downsCoff); ++ ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H, resCoff); ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight, ++ &resCoff, &downsCoff); ++ ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V, downsCoff); ++ ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V, resCoff); ++ } ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1); ++ break; ++ ++ case PP_TASK: ++ ipu_write_field(IPU_IC_CONF__PP_EN, 0); ++ ipu_write_field(IPU_IC_IDMAC_1__CB2_BURST_16, 1); // set to 16bps ++ ipu_write_field(IPU_IC_IDMAC_1__CB5_BURST_16, 1); ++ ipu_write_field(IPU_IC_CONF__PP_EN, 1); ++ ipu_write_field(IPU_IC_CONF__PP_ROT_EN, task_params.rotEnable); ++ // set rotation ++ if (task_params.rotEnable) { ++ ipu_write_field(IPU_IC_IDMAC_1__T3_FLIP_LR, task_params.rotInfo.HorizFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T3_FLIP_UD, task_params.rotInfo.VertFlip); ++ ipu_write_field(IPU_IC_IDMAC_1__T3_ROT, task_params.rotInfo.rotation); ++ } ++ // set resizing ++ if (task_params.resEnable) { ++ ipu_write_field(IPU_IC_IDMAC_2__T3_FR_HEIGHT, task_params.resInfo.outHeight - 1); ++ ipu_write_field(IPU_IC_IDMAC_3__T3_FR_WIDTH, task_params.resInfo.outWidth - 1); ++ ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth, ++ &resCoff, &downsCoff); ++ ++ ipu_write_field(IPU_IC_PP_RSC__PP_DS_R_H, downsCoff); ++ ipu_write_field(IPU_IC_PP_RSC__PP_RS_R_H, resCoff); ++ ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight, ++ &resCoff, &downsCoff); ++ ++ ipu_write_field(IPU_IC_PP_RSC__PP_DS_R_V, downsCoff); ++ ipu_write_field(IPU_IC_PP_RSC__PP_RS_R_V, resCoff); // FROM (1536/2 -1)->479 *8192 = 13117 ++ } ++ ipu_write_field(IPU_IC_CONF__PP_EN, 1); ++ break; ++ default: ++ ERRDP("Task type is wrong, IC task configuration failed\n"); ++ } ++ ++} ++ ++/* ++* this function is used to calculate the params for resizing ++*/ ++void ipu_ic_calc_resize_coeffs(unsigned int in_size, unsigned int out_size, ++ unsigned int *resize_coeff, unsigned int *downsize_coeff) ++{ ++ unsigned int tempSize; ++ unsigned int tempDownsize; ++ ++ /* Cannot downsize more than 8:1 */ ++ if ((out_size << 3) < in_size) ++ return false; ++ ++ /* compute downsizing coefficient */ ++ tempDownsize = 0; ++ tempSize = in_size; ++ while ((tempSize >= out_size * 2) && (tempDownsize < 2)) { ++ tempSize >>= 1; ++ tempDownsize++; ++ } ++ *downsize_coeff = tempDownsize; ++ ++ /* compute resizing coefficient using the following equation: ++ resizeCoeff = M*(SI -1)/(SO - 1) ++ where M = 2^13, SI - input size, SO - output size */ ++ *resize_coeff = (8192L * (tempSize - 1)) / (out_size - 1); ++ if (*resize_coeff >= 16384L) { ++ ERRDP("Overflow on resize coeff.\n"); ++ *resize_coeff = 0x3FFF; ++ } ++} ++ ++/* ++* this function is used to set the resizing parameters ++*/ ++int ipu_ic_config_resize_rate(char *task_type, unsigned int res_vert, unsigned int down_vert, ++ unsigned int res_horiz, unsigned int down_horiz) ++{ ++ unsigned int val; ++ val = (down_vert << 30) | (res_vert << 16) | (down_horiz << 14) | (res_horiz); ++ ++ if (!strcmp(task_type, "PPTASK")) { ++ DP("Post Processing Task!\n"); ++ writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PP_RSC__ADDR); ++ } else if (!strcmp(task_type, "VFTASK")) { ++ DP("View Finder Task!\n"); ++ writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PRP_VF_RSC__ADDR); ++ } else if (!strcmp(task_type, "PrPTASK")) { ++ DP("Pre Processing Task!\n"); ++ writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PRP_ENC_RSC__ADDR); ++ } else { ++ ERRDP("Task type is not defined!\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/* ++* this function is used to calculate the output size for IC resizing task ++*/ ++void ipu_ic_calc_vout_size(ipu_res_info_t * info, display_device_t disp_device, int rotation, ++ int full_screen_enable) ++{ ++ float coffHeight, coffWidth; ++ float coff; ++ unsigned int dispFW, dispFH; ++ ++ /*if rotation is enabled, swap the width and height */ ++ if (rotation) { ++ coffWidth = (float)(disp_device.height) / info->inWidth; ++ coffHeight = (float)(disp_device.width) / info->inHeight; ++ } else { ++ coffWidth = (float)(disp_device.width) / info->inWidth; ++ coffHeight = (float)(disp_device.height) / info->inHeight; ++ } ++ /* the resizing ratio should be the same in both width and height */ ++ if (coffWidth >= coffHeight) { ++ info->outWidth = info->inWidth * coffHeight; ++ info->outHeight = info->inHeight * coffHeight; ++ } else { ++ info->outWidth = info->inWidth * coffWidth; ++ info->outHeight = info->inHeight * coffWidth; ++ } ++ ++ if (full_screen_enable) { ++ if(rotation) { ++ info->outWidth = disp_device.height; ++ info->outHeight = disp_device.width; ++ } ++ else { ++ info->outWidth = disp_device.width; ++ info->outHeight = disp_device.height; ++ } ++ } ++ ++ /* the output of IPU resizing is up to 1024*1024 */ ++ info->xSplitParts = info->outWidth / 1024 + 1; ++ info->ySplitParts = info->outHeight / 1024 + 1; ++ ++ /* the image in block mode, which is 8*8 size */ ++ info->outHeight -= info->outHeight % 8; ++ info->outWidth -= info->outWidth % 8; ++ ++} ++ ++/* ++* this function is used to config the combination task in the IC ++* local alpha with per-pixel or from separate buffer can be used ++* global alpha can be used also. ++*/ ++int ipu_ic_combine_config(ic_comb_params_t comb_params) ++{ ++ switch (comb_params.taskType) { ++ case PrP_VF_TASK: ++ ipu_write_field(IPU_IC_IDMAC_1__CB3_BURST_16, 1); // set to 16bps ++ if (comb_params.alpha < 0) { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0); // local alpha with per-pixel ++ } else if (comb_params.alpha < 0x100) { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 1); // global alpha enabled ++ ipu_write_field(IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V, comb_params.alpha); // global alpha value ++ } else { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0); // local alpha from separate buffer ++ } ++ ipu_write_field(IPU_IC_CONF__PRPVF_CMB, ++ (comb_params.alpha == 0) ? 0 : 1); ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1); ++ break; ++ case PP_TASK: ++ ipu_write_field(IPU_IC_IDMAC_1__CB4_BURST_16, 1); // set to 16bps ++ if (comb_params.alpha < 0) { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0); // local alpha with per-pixel ++ } else if (comb_params.alpha < 0x100) { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 1); // global alpha enabled ++ ipu_write_field(IPU_IC_CMBP_1__IC_PP_ALPHA_V, comb_params.alpha); // global alpha ++ } else { ++ ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0); // local alpha in sepatate buffer ++ } ++ ipu_write_field(IPU_IC_CONF__PP_CMB, ++ (comb_params.alpha == 0) ? 0 : 1); ++ ipu_write_field(IPU_IC_CONF__PP_EN, 1); ++ break; ++ default: ++ ERRDP("Task Type is wrong!!\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/* ++* this function is used to config the color space conversion task in the IC ++*/ ++extern int xecDlsEnable; ++int ipu_ic_csc_config(int csc_set_index, ic_csc_params_t csc_params) ++{ ++ unsigned int param; ++ unsigned int tpmBaseAddr = IPU_CTRL_BASE_ADDR + 0x1F060000; ++ unsigned int *base = NULL; ++ if (csc_set_index != 1 && csc_set_index != 2) { ++ ERRDP("Wrong index input for IC CSC!!\n"); ++ return -1; ++ } ++ /*Y = R * .299 + G * .587 + B * .114; ++ U = R * -.169 + G * -.332 + B * .500 + 128.; ++ V = R * .500 + G * -.419 + B * -.0813 + 128.; */ ++ unsigned int rgb2ycbcr_coeff[4][3] = { ++ {0x004D, 0x0096, 0x001D}, ++ {0x01D5, 0x01AB, 0x0080}, ++ {0x0080, 0x0195, 0x01EB}, ++ {0x0000, 0x0200, 0x0200}, /* A0, A1, A2 */ ++ }; ++ ++ /* transparent RGB->RGB matrix for combining ++ */ ++ unsigned int rgb2rgb_coeff[4][3] = { ++ {0x0080, 0x0000, 0x0000}, ++ {0x0000, 0x0080, 0x0000}, ++ {0x0000, 0x0000, 0x0080}, ++ {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ ++ }; ++ ++ /* ++ R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); ++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); ++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); ++ */ ++ unsigned int ycbcr2rgb_coeff[4][3] = { ++ {0x95, 0x0, 0xCC}, ++ {0x95, 0x1CE, 0x198}, ++ {0x95, 0xFF, 0x0}, ++ {0x1E42, 0x10A, 0x1DD6}, // A0, A1, A2 ++ }; ++ ++ /* ++ R = (1.164 * alpha * (Y - 16)) + (1.596 * (Cr - 128)); ++ G = (1.164 * alpha * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); ++ B = (1.164 * alpha * (Y - 16)) + (2.017 * (Cb - 128); ++ */ ++ if(xecDlsEnable) { ++ /*compensation of y_coeff*/ ++ ycbcr2rgb_coeff[0][0] = ycbcr2rgb_coeff[0][0] * xecDlsParams.curAlpha/100; ++ ycbcr2rgb_coeff[1][0] = ycbcr2rgb_coeff[1][0] * xecDlsParams.curAlpha/100; ++ ycbcr2rgb_coeff[2][0] = ycbcr2rgb_coeff[2][0] * xecDlsParams.curAlpha/100; ++ /*compensation of costant coeff*/ ++/* ycbcr2rgb_coeff[3][0] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100); ++ ycbcr2rgb_coeff[3][1] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100); ++ ycbcr2rgb_coeff[3][2] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100); ++*/ DP("alpha %d \n", xecDlsParams.curAlpha); ++ } ++ ++ if (csc_set_index == 1) { ++ if (csc_params.taskType == PrP_ENC_TASK) { ++ base = tpmBaseAddr + 0x2008; ++ } else if (csc_params.taskType == PrP_VF_TASK) { ++ base = tpmBaseAddr + 0x4028; ++ } else if (csc_params.taskType == PP_TASK) { ++ base = tpmBaseAddr + 0x6060; ++ } else { ++ ERRDP("Wrong task type for IC CSC1 input!!\n"); ++ return -1; ++ } ++ } else { ++ if (csc_params.taskType == PrP_VF_TASK) { ++ base = tpmBaseAddr + 0x4040; ++ } else if (csc_params.taskType == PP_TASK) { ++ base = tpmBaseAddr + 0x6078; ++ } else { ++ ERRDP("Wrong task type for IC CSC2 input!!\n"); ++ return -1; ++ } ++ } ++ ++ if ((csc_params.inFormat == YCbCr) && (csc_params.outFormat == RGB)) { ++ /* Init CSC (YCbCr->RGB) */ ++ param = (ycbcr2rgb_coeff[3][0] << 27) | ++ (ycbcr2rgb_coeff[0][0] << 18) | (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2]; ++ writel(param, base++); ++ /* scale = 2, sat = 0 */ ++ param = (ycbcr2rgb_coeff[3][0] >> 5) | (2 << (40 - 32)); ++ writel(param, base++); ++ ++ param = (ycbcr2rgb_coeff[3][1] << 27) | ++ (ycbcr2rgb_coeff[0][1] << 18) | (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0]; ++ writel(param, base++); ++ param = (ycbcr2rgb_coeff[3][1] >> 5); ++ writel(param, base++); ++ ++ param = (ycbcr2rgb_coeff[3][2] << 27) | ++ (ycbcr2rgb_coeff[0][2] << 18) | (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1]; ++ writel(param, base++); ++ param = (ycbcr2rgb_coeff[3][2] >> 5); ++ writel(param, base++); ++ } else if ((csc_params.inFormat == RGB) && (csc_params.outFormat == YCbCr)) { ++ /* Init CSC1 (RGB->YCbCr) */ ++ param = (rgb2ycbcr_coeff[3][0] << 27) | ++ (rgb2ycbcr_coeff[0][0] << 18) | (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2]; ++ writel(param, base++); ++ /* scale = 1, sat = 0 */ ++ param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8); ++ writel(param, base++); ++ ++ param = (rgb2ycbcr_coeff[3][1] << 27) | ++ (rgb2ycbcr_coeff[0][1] << 18) | (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0]; ++ writel(param, base++); ++ param = (rgb2ycbcr_coeff[3][1] >> 5); ++ writel(param, base++); ++ ++ param = (rgb2ycbcr_coeff[3][2] << 27) | ++ (rgb2ycbcr_coeff[0][2] << 18) | (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1]; ++ writel(param, base++); ++ param = (rgb2ycbcr_coeff[3][2] >> 5); ++ writel(param, base++); ++ } else if ((csc_params.inFormat == RGB) && (csc_params.outFormat == RGB)) { ++ /* Init CSC1 */ ++ param = ++ (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) | ++ (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2]; ++ writel(param, base++); ++ /* scale = 2, sat = 0 */ ++ param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8); ++ writel(param, base++); ++ ++ param = ++ (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) | ++ (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0]; ++ writel(param, base++); ++ param = (rgb2rgb_coeff[3][1] >> 5); ++ writel(param, base++); ++ ++ param = ++ (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) | ++ (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1]; ++ writel(param, base++); ++ param = (rgb2rgb_coeff[3][2] >> 5); ++ writel(param, base++); ++ } else { ++ ERRDP("Unkown color space conversion!!\n"); ++ return -1; ++ } ++ if (csc_set_index == 1) { ++ if (csc_params.taskType == PrP_ENC_TASK) { ++ ipu_write_field(IPU_IC_CONF__PRPENC_CSC1, 1); ++ } else if (csc_params.taskType == PrP_VF_TASK) { ++ ipu_write_field(IPU_IC_CONF__PRPVF_CSC1, 1); ++ } else if (csc_params.taskType == PP_TASK) { ++ ipu_write_field(IPU_IC_CONF__PP_CSC1, 1); ++ } else { ++ ERRDP("Wrong Task input!!\n"); ++ return -1; ++ } ++ } else { ++ if (csc_params.taskType == PrP_VF_TASK) { ++ ipu_write_field(IPU_IC_CONF__PRPVF_CSC2, 1); ++ } else if (csc_params.taskType == PP_TASK) { ++ ipu_write_field(IPU_IC_CONF__PP_CSC2, 1); ++ } else { ++ ERRDP("Wrong Task input!!\n"); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++* enable ipu tasks, such as preprocessing/post-processing task ++*/ ++int ipu_ic_task_enable(int task_type, int task, int enable) ++{ ++ switch (task_type) { ++ case PrP_ENC_TASK: ++ if (task == IC_CSC1) ++ ipu_write_field(IPU_IC_CONF__PRPENC_CSC1, enable); ++ else if (IC_PRPENC) ++ ipu_write_field(IPU_IC_CONF__PRPENC_EN, enable); ++ else ++ ERRDP("Task Type is wrong!!\n"); ++ break; ++ case PrP_VF_TASK: ++ if (task == IC_CMB) ++ ipu_write_field(IPU_IC_CONF__PRPVF_CMB, enable); ++ else if (task == IC_CSC1) ++ ipu_write_field(IPU_IC_CONF__PRPVF_CSC1, enable); ++ else if (task == IC_CSC2) ++ ipu_write_field(IPU_IC_CONF__PRPVF_CSC2, enable); ++ else if (task == IC_PRPVF) ++ ipu_write_field(IPU_IC_CONF__PRPVF_EN, enable); ++ else ++ ERRDP("Task Type is wrong!!\n"); ++ break; ++ case PP_TASK: ++ if (task == IC_CMB) ++ ipu_write_field(IPU_IC_CONF__PP_CMB, enable); ++ else if (task == IC_CSC1) ++ ipu_write_field(IPU_IC_CONF__PP_CSC1, enable); ++ else if (task == IC_CSC2) ++ ipu_write_field(IPU_IC_CONF__PP_CSC2, enable); ++ else if (task == IC_PP) ++ ipu_write_field(IPU_IC_CONF__PP_EN, enable); ++ else ++ ERRDP("Task Type is wrong!!\n"); ++ break; ++ default: ++ ERRDP("Task Type is wrong!!\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/* ++* this function is used to config the color space conversion task in the DP ++*/ ++void ipu_dp_csc_config(int dp, dp_csc_param_t dp_csc_params, bool srm_mode_update) ++{ ++ unsigned int regVal; ++ int (*coeff)[3]; ++ ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC, 0); //SAT mode is zero ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC, 0); //GAMUT en (RGB...) ++ ++ if (dp_csc_params.mode >= 0) { ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC, dp_csc_params.mode); //disable CSC ++ } ++ ++ coeff = dp_csc_params.coeff; ++ ++ if (coeff) { ++ writel(GET_LSB(10, coeff[0][0]) | (GET_LSB(10, coeff[0][1]) << 16), ++ IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_0__ADDR + dp * 4); ++ writel(GET_LSB(10, coeff[0][2]) | (GET_LSB(10, coeff[1][0]) << 16), ++ IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_1__ADDR + dp * 4); ++ writel(GET_LSB(10, coeff[1][1]) | (GET_LSB(10, coeff[1][2]) << 16), ++ IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_2__ADDR + dp * 4); ++ writel(GET_LSB(10, coeff[2][0]) | (GET_LSB(10, coeff[2][1]) << 16), ++ IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_3__ADDR + dp * 4); ++ writel(GET_LSB(10, coeff[2][2]) | (GET_LSB(14, coeff[3][0]) << 16) | ++ (coeff[4][0] << 30), IPU_CTRL_BASE_ADDR + SRM_DP_CSC_SYNC_0__ADDR + dp * 4); ++ writel(GET_LSB(14, coeff[3][1]) | (coeff[4][1] << 14) | ++ (GET_LSB(14, coeff[3][2]) << 16) | (coeff[4][2] << 30), ++ IPU_CTRL_BASE_ADDR + SRM_DP_CSC_SYNC_1__ADDR + dp * 4); ++ } ++ if (srm_mode_update) { ++ ipu_write_field(IPU_IPU_SRM_PRI2__DP_S_SRM_MODE, 3); ++ ipu_write_field(IPU_IPU_SRM_PRI2__DP_SRM_PRI, 0x0); ++ } ++} ++ ++/* ++* this function is used to config the foreground plane for combination in the DP ++*/ ++void ipu_dp_fg_config(dp_fg_param_t foreground_params) ++{ ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC, 0); ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC, 0); ++ ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_COC_SYNC, foreground_params.cursorEnable); ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC, foreground_params.colorKeyEnable); //color key ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC, foreground_params.alphaMode); //1=global alpha,0=local alpha ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC, foreground_params.graphicSelect); //1=graphic is FG,0=graphic is BG ++ ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC, foreground_params.fgEnable); //1=FG channel enabled,0=FG channel disabled ++ ipu_write_field(SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC, foreground_params.offsetHoriz); ++ ipu_write_field(SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC, foreground_params.offsetVert); ++ ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC, foreground_params.opaque); // set the FG opaque ++ ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC, 0xFF); ++ ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC, 0xFF); ++ ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC, 0xFF); ++} ++ ++/* ++* microcode configuration, refer to ipuv3 spec ++*/ ++void ipu_dc_microcode_config(dc_microcode_t microcode) ++{ ++ unsigned int LowWord = 0; ++ unsigned int HighWord = 0; ++ unsigned int opcode_fixed; ++ ++ if (!strcmp(microcode.opcode, "WROD")) { ++ LowWord = LowWord | microcode.sync; ++ LowWord = LowWord | (microcode.gluelogic << 4); ++ LowWord = LowWord | (microcode.waveform << 11); ++ LowWord = LowWord | (microcode.mapping << 15); ++ LowWord = LowWord | (microcode.operand << 20); ++ ++ HighWord = HighWord | (microcode.operand >> 12); ++ opcode_fixed = 0x18 | (microcode.lf << 1); ++ HighWord = HighWord | (opcode_fixed << 4); ++ HighWord = HighWord | (microcode.stop << 9); ++ } else { ++ ERRDP("Microcode type not supported yet!!\n"); ++ } ++ writel(LowWord, IPU_CTRL_BASE_ADDR + IPU_MEM_DC_MICROCODE_BASE_ADDR + microcode.addr * 8); ++ writel(HighWord, IPU_CTRL_BASE_ADDR + IPU_MEM_DC_MICROCODE_BASE_ADDR + microcode.addr * 8 + 4); ++} ++ ++/* ++* microcode event configuration, to handle different event ++*/ ++void ipu_dc_microcode_event(int channel, char event[8], int priority, int address) ++{ ++ int channel_offset = (channel >= 5) ? (0x5C + (channel - 5) * 0x1C) : channel * 0x1C; ++ if (!strcmp(event, "NL")) { ++ ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0, priority); ++ } //New Line ++ else if (!strcmp(event, "NF")) { ++ ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0, priority); ++ } //New Frame ++ else if (!strcmp(event, "NFIELD")) { ++ ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0, priority); ++ } //New Field ++ else if (!strcmp(event, "EOF")) { ++ ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0, priority); ++ } //End of Frame ++ else if (!strcmp(event, "EOFIELD")) { ++ ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0, priority); ++ } //End of Field ++ else if (!strcmp(event, "EOL")) { ++ ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0, priority); ++ } //End of Line ++ else if (!strcmp(event, "NEW_CHAN")) { ++ ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0, priority); ++ } //New Channel ++ else if (!strcmp(event, "NEW_ADDR")) { ++ ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0, priority); ++ } //New Address ++ else if (!strcmp(event, "NEW_DATA")) { ++ ipu_write_field(channel_offset + IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0, address); ++ ipu_write_field(channel_offset + IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0, priority); ++ } //New Data ++ else { ++ ERRDP("Wrong DC microcode\n"); ++ } ++ ++} ++ ++/* ++* this function is ued to perform pack/unpacking for yuv/rgb data ++*/ ++int ipu_dc_map(int map, int format) ++{ ++ int offset[3], mask[3]; ++ if (format == RGB565) { ++ offset[0] = 15; ++ mask[0] = 0xF8; ++ offset[1] = 10; ++ mask[1] = 0xFC; ++ offset[2] = 4; ++ mask[2] = 0xF8; ++ } else if (format == RGB666) { ++ offset[0] = 17; ++ mask[0] = 0xFC; ++ offset[1] = 11; ++ mask[1] = 0xFC; ++ offset[2] = 5; ++ mask[2] = 0xFC; ++ } else if (format == RGB888 || format == YUV888) { ++ offset[0] = 23; ++ mask[0] = 0xFF; ++ offset[1] = 15; ++ mask[1] = 0xFF; ++ offset[2] = 7; ++ mask[2] = 0xFF; ++ } ++ switch (map) { ++ case 0: ++ //DC_MAP, should be RGB666 mode ++ ipu_write_field(IPU_DC_MAP_CONF_16__MD_OFFSET_2, offset[0]); ++ ipu_write_field(IPU_DC_MAP_CONF_16__MD_MASK_2, mask[0]); ++ ipu_write_field(IPU_DC_MAP_CONF_15__MD_OFFSET_1, offset[1]); ++ ipu_write_field(IPU_DC_MAP_CONF_15__MD_MASK_1, mask[1]); ++ ipu_write_field(IPU_DC_MAP_CONF_15__MD_OFFSET_0, offset[2]); ++ ipu_write_field(IPU_DC_MAP_CONF_15__MD_MASK_0, mask[2]); ++ ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0, 0); ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0, 2); ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0, 1); ++ break; ++ ++ case 1: ++ //DC_MAP ++ ipu_write_field(IPU_DC_MAP_CONF_18__MD_OFFSET_6, offset[0]); ++ ipu_write_field(IPU_DC_MAP_CONF_18__MD_MASK_6, mask[0]); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_5, offset[1]); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_5, mask[1]); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_4, offset[2]); ++ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_4, mask[2]); ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1, 6); ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1, 5); ++ ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1, 4); ++ break; ++ ++ default: ++ ERRDP("Map pointer not support yet!\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/* ++* config the display port in the DC ++*/ ++int ipu_dc_display_config(int display_port, int type, int increment, int strideline) ++{ ++ switch (display_port) { ++ case 0: ++ ipu_write_field(IPU_DC_DISP_CONF1_0__DISP_TYP_0, type); //paralel display without byte enable ++ ipu_write_field(IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0, increment); //automatical address increase by 1 ++ ipu_write_field(IPU_DC_DISP_CONF2_0__SL_0, strideline); //stride line ++ break; ++ case 1: ++ ipu_write_field(IPU_DC_DISP_CONF1_1__DISP_TYP_1, type); //paralel display without byte enable ++ ipu_write_field(IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1, increment); //automatical address increase by 1 ++ ipu_write_field(IPU_DC_DISP_CONF2_1__SL_1, strideline); //stride line ++ break; ++ case 2: ++ ipu_write_field(IPU_DC_DISP_CONF1_2__DISP_TYP_2, type); //paralel display without byte enable ++ ipu_write_field(IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2, increment); //automatical address increase by 1 ++ ipu_write_field(IPU_DC_DISP_CONF2_2__SL_2, strideline); //stride line ++ break; ++ case 3: ++ ipu_write_field(IPU_DC_DISP_CONF1_3__DISP_TYP_3, type); //paralel display without byte enable ++ ipu_write_field(IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3, increment); //automatical address increase by 1 ++ ipu_write_field(IPU_DC_DISP_CONF2_3__SL_3, strideline); //stride line ++ break; ++ default: ++ ERRDP("Display port wrong!\n"); ++ return -1; ++ } ++} ++ ++/* ++* config the write channel for display. ++* different channels linked to different display port ++*/ ++int ipu_dc_write_channel_config(int dma_channel, int disp_port, int link_di_index, ++ int field_mode_enable) ++{ ++ switch (dma_channel) { ++ case 23: ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5, 0); ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5, 0); ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5, 4); //Normal mode without anti-tearing ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5, disp_port); ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5, link_di_index); ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__W_SIZE_5, 2); //Component size access to DC set to 24bit ++ ipu_write_field(IPU_DC_WR_CH_ADDR_5__ST_ADDR_5, 0); ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__FIELD_MODE_5, field_mode_enable); ++ ++ ipu_write_field(IPU_DC_GEN__SYNC_PRIORITY_5, 1); //sets the priority of channel #5 to high. ++ ipu_write_field(IPU_DC_GEN__MASK4CHAN_5, 0); // mask channel is associated to the sync flow via DC (without DP) ++ ipu_write_field(IPU_DC_GEN__MASK_EN, 0); // mask channel is disabled ++ ipu_write_field(IPU_DC_GEN__DC_CH5_TYPE, 0); // alternate sync or asyn flow ++ break; ++ case 28: ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1, 0); ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1, 0); ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1, 4); //Normal mode without anti-tearing ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1, disp_port); ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1, link_di_index); ++ /* if CH28 is connected to DI0, CH23 must connect to DI1 even if it is not used. */ ++ if (link_di_index == 0) ++ ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5, 1); ++ ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__W_SIZE_1, 2); //Component size access to DC set to 24bit ++ ipu_write_field(IPU_DC_WR_CH_ADDR_1__ST_ADDR_1, 0); //START ADDRESS OF CHANNEL ++ ipu_write_field(IPU_DC_WR_CH_CONF_1__FIELD_MODE_1, field_mode_enable); ++ ++ ipu_write_field(IPU_DC_GEN__SYNC_PRIORITY_1, 1); //sets the priority of channel #5 to high. ++ ipu_write_field(IPU_DC_GEN__SYNC_1_6, 2); //Channel 1 of the DC handless sync flow ++ break; ++ default: ++ ERRDP("Display channel wrong!\n"); ++ return -1; ++ } ++ return 0; ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/cdl/mc34704.cdl redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/cdl/mc34704.cdl +--- redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/cdl/mc34704.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/cdl/mc34704.cdl 2010-01-26 17:33:14.182957126 +0000 +@@ -0,0 +1,85 @@ ++# ==================================================================== ++# ++# mc34704.cdl ++# ++# A PMIC package for i.MX25 3stack. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. ++## Copyright (C) 2004 eCosCentric, Ltd ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Quinn Jensen ++# Contributors: ++# Date: 2008-05-08 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK { ++ display "PMIC driver for i.MX25 3stack platforms" ++ ++ compile -library=libextras.a mc34704.c ++ ++ include_dir cyg/io ++ ++ define_proc { ++ puts $::cdl_header "#include "; ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C { ++ display "Support I2C interface to PMIC" ++ default_value 0 ++ active_if CYGPKG_DEVS_MXC_I2C ++ description " ++ When this option is enabled, it enables i2c interface ++ to access pmic device on the i.MX25 3stack platform" ++ define_proc { ++ puts $::cdl_system_header "#define MXC_PMIC_I2C_ENABLED" ++ } ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C_PORT { ++ display "I2C interface number to PMIC" ++ flavor data ++ default_value 0 ++ active_if CYGHWR_DEVS_PMIC_I2C ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR { ++ display "I2C addess of PMIC" ++ flavor data ++ default_value 0 ++ active_if CYGHWR_DEVS_PMIC_I2C ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/include/mc34704.h redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/include/mc34704.h +--- redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/include/mc34704.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/include/mc34704.h 2010-01-26 17:33:14.182957126 +0000 +@@ -0,0 +1,47 @@ ++//========================================================================== ++// ++// mc34704.h ++// ++// PMIC support on i.mx25 3stack platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#ifndef __MC34704_H__ ++#define __MC34704_H__ ++ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write); ++ ++#endif /* __MC34704_H__ */ +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/src/mc34704.c redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/src/mc34704.c +--- redboot-imx-200952~/packages/devs/pmic/arm/mx25_3stack/current/src/mc34704.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx25_3stack/current/src/mc34704.c 2010-01-26 17:33:14.182957126 +0000 +@@ -0,0 +1,137 @@ ++//========================================================================== ++// ++// mc34704.c ++// ++// PMIC support on i.MX25 3stack platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MC34704_REG_MAX 0x59 ++ ++static void mxc_pmic_init(void) ++{ ++ if (CYGHWR_DEVS_PMIC_I2C_PORT >= i2c_num) ++ return; ++ ++ i2c_init(i2c_base_addr[CYGHWR_DEVS_PMIC_I2C_PORT], 40000); ++ ++ diag_printf("Turning on PMIC regulators: 1,2,3,4,5\n"); ++ ++ pmic_reg(0x02, 0x09, 1); ++} ++ ++RedBoot_init(mxc_pmic_init, RedBoot_INIT_PRIO(100)); ++ ++static void do_pmic(int argc, char *argv[]); ++RedBoot_cmd("pmic", ++ "Read/Write internal PMIC register", ++ " [value to be written]", ++ do_pmic); ++ ++static void do_pmic(int argc,char *argv[]) ++{ ++ unsigned int reg, temp, val = 0, write = 0; ++ ++ if (argc == 1) { ++ diag_printf("\tRead: pmic \n"); ++ diag_printf("\tWrite: pmic \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)®, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ if (argc == 3) { ++ if (!parse_num(*(&argv[2]), (unsigned long *)&val, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ write = 1; ++ } ++ ++ temp = pmic_reg(reg, val, write); ++ ++ diag_printf("\tval: 0x%08x\n\n", temp); ++} ++ ++static unsigned int pmic_reg_i2c(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ struct mxc_i2c_request rq; ++ rq.dev_addr = CYGHWR_DEVS_PMIC_I2C_ADDR; ++ rq.reg_addr = reg; ++ rq.reg_addr_sz = 1; ++ rq.buffer = (unsigned char *)&val; ++ rq.buffer_sz = 1; ++ write = write ? I2C_WRITE : I2C_READ; ++ if (i2c_xfer(CYGHWR_DEVS_PMIC_I2C_PORT, &rq, write) != 0) { ++ diag_printf("Error in I2C transaction\n\n"); ++ return 0; ++ } ++ return val; ++} ++ ++/*! ++ * To read/write to a PMIC register. For write, it does another read for the ++ * actual register value. ++ * ++ * @param reg register number inside the PMIC ++ * @param val data to be written to the register; don't care for read ++ * @param write 0 for read; 1 for write ++ * ++ * @return the actual data in the PMIC register ++ */ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ if (reg > MC34704_REG_MAX) { ++ diag_printf(" = %d is invalid. Should be less than %d\n", ++ reg, MC34704_REG_MAX); ++ return 0; ++ } ++ return pmic_reg_i2c(reg, val, write); ++} +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/cdl/mc9s08dz.cdl redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/cdl/mc9s08dz.cdl +--- redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/cdl/mc9s08dz.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/cdl/mc9s08dz.cdl 2010-01-26 17:33:14.182957126 +0000 +@@ -0,0 +1,105 @@ ++# ==================================================================== ++# ++# mc9s08dz.cdl ++# ++# A PMIC package for i.MX35 3stack. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. ++## Copyright (C) 2004 eCosCentric, Ltd ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Fred Fan ++# Contributors: ++# Date: 2008-05-08 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_PMIC_ARM_IMX35_3STACK { ++ display "PMIC driver for i.MX35 3stack platforms" ++ ++ compile -library=libextras.a mc9s08dz.c ++ ++ include_dir cyg/io ++ ++ define_proc { ++ puts $::cdl_header "#include "; ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_SPI { ++ display "Support SPI interface to PMIC" ++ default_value 0 ++ active_if CYGPKG_DEVS_MXC_SPI ++ ++ description " ++ When this option is enabled, it enables spi interface ++ to access pmic device on the i.MX35 3stack platform" ++ define_proc { ++ puts $::cdl_system_header "#define MXC_PMIC_SPI_ENABLED" ++ } ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_SPI_PORT { ++ display "SPI interface number to PMIC" ++ flavor data ++ default_value 0 ++ active_if CYGHWR_DEVS_PMIC_SPI ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C { ++ display "Support I2C interface to PMIC" ++ default_value 0 ++ active_if CYGPKG_DEVS_MXC_I2C ++ description " ++ When this option is enabled, it enables i2c interface ++ to access pmic device on the i.MX35 3stack platform" ++ define_proc { ++ puts $::cdl_system_header "#define MXC_PMIC_I2C_ENABLED" ++ } ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C_PORT { ++ display "I2C interface number to PMIC" ++ flavor data ++ default_value 0 ++ active_if CYGHWR_DEVS_PMIC_I2C ++ } ++ ++ cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR { ++ display "I2C addess of PMIC" ++ flavor data ++ default_value 0 ++ active_if CYGHWR_DEVS_PMIC_I2C ++ } ++} +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/include/mc9s08dz.h redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/include/mc9s08dz.h +--- redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/include/mc9s08dz.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/include/mc9s08dz.h 2010-01-26 17:33:14.182957126 +0000 +@@ -0,0 +1,49 @@ ++//========================================================================== ++// ++// mc9s08dz.h ++// ++// PMIC support on i.mx35 3stack platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#ifndef __MC9S08DZ_H__ ++#define __MC9S08DZ_H__ ++ ++#define MC9S08DZ_MAX_REGS 0x28 ++ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write); ++ ++#endif /* __MC9S08DZ_H__ */ +diff -urNad redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/src/mc9s08dz.c redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/src/mc9s08dz.c +--- redboot-imx-200952~/packages/devs/pmic/arm/mx35_3stack/current/src/mc9s08dz.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/pmic/arm/mx35_3stack/current/src/mc9s08dz.c 2010-01-26 17:33:14.192960877 +0000 +@@ -0,0 +1,212 @@ ++//========================================================================== ++// ++// mc9s08dz.c ++// ++// PMIC support on i.MX35 3stack platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef MXC_PMIC_I2C_ENABLED ++#include ++#endif // MXC_PMIC_I2C_ENABLED ++#include ++ ++extern unsigned int system_rev; ++ ++static void mxc_pmic_init(void) ++{ ++ volatile unsigned int rev_id; ++ ++#ifdef MXC_PMIC_I2C_ENABLED ++ if (CYGHWR_DEVS_PMIC_I2C_PORT >= i2c_num) ++ return; ++// 40kHz data rate ++ i2c_init(i2c_base_addr[CYGHWR_DEVS_PMIC_I2C_PORT], 40000); ++#else ++#error "Please select a valid interface" ++#endif // MXC_PMIC_I2C_ENABLED ++ ++ rev_id = pmic_reg(0, 0, 0); ++ diag_printf("PMIC ID: 0x%08x [Rev: ", rev_id); ++ switch (rev_id & 0x1F) { ++ case 0x10: ++ diag_printf("1.0"); ++ break; ++ default: ++ diag_printf("unknown"); ++ break; ++ } ++ diag_printf("]\n"); ++} ++ ++RedBoot_init(mxc_pmic_init, RedBoot_INIT_PRIO(100)); ++ ++static void do_pmic(int argc, char *argv[]); ++RedBoot_cmd("pmic", ++ "Read/Write internal PMIC register", ++ " [value to be written]", do_pmic); ++ ++static void do_pmic(int argc, char *argv[]) ++{ ++ unsigned int reg, temp, val = 0, write = 0; ++ ++ if (argc == 1) { ++ diag_printf("\tRead: pmic \n"); ++ diag_printf("\tWrite: pmic \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)®, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ if (argc == 3) { ++ if (!parse_num(*(&argv[2]), (unsigned long *)&val, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ write = 1; ++ } ++ ++ temp = pmic_reg(reg, val, write); ++ ++ diag_printf("\tval: 0x%08x\n\n", temp); ++} ++ ++#ifdef MXC_PMIC_I2C_ENABLED ++static unsigned int pmic_reg_i2c(unsigned int reg, unsigned int val, ++ unsigned int write) ++{ ++ struct mxc_i2c_request rq; ++ rq.dev_addr = CYGHWR_DEVS_PMIC_I2C_ADDR; ++ rq.reg_addr = reg; ++ rq.reg_addr_sz = 1; ++ rq.buffer = (unsigned char *)&val; ++ rq.buffer_sz = 1; ++ write = write ? I2C_WRITE : I2C_READ; ++ if (i2c_xfer(CYGHWR_DEVS_PMIC_I2C_PORT, &rq, write) != 0) { ++ diag_printf("Error I2C transfer\n\n"); ++ return 0; ++ } ++ return val; ++} ++#endif //MXC_PMIC_I2C_ENABLED ++/*! ++ * To read/write to a PMIC register. For write, it does another read for the ++ * actual register value. ++ * ++ * @param reg register number inside the PMIC ++ * @param val data to be written to the register; don't care for read ++ * @param write 0 for read; 1 for write ++ * ++ * @return the actual data in the PMIC register ++ */ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ if (reg > MC9S08DZ_MAX_REGS) { ++ diag_printf(" = %d is invalide. Should be less then 0x28\n", ++ reg); ++ return 0; ++ } ++#ifdef MXC_PMIC_I2C_ENABLED ++ return pmic_reg_i2c(reg, val, write); ++#else ++ return 0; ++#endif //MXC_PMIC_I2C_ENABLED ++} ++ ++static void mxc_pmic_detect(void) ++{ ++ struct mxc_i2c_request rq; ++ unsigned char buf[4] = { 0 }; ++ ++ rq.dev_addr = 0x34; ++ rq.reg_addr = 0x10; ++ rq.reg_addr_sz = 1; ++ rq.buffer = buf; ++ rq.buffer_sz = 1; ++ ++ if (i2c_xfer(0, &rq, I2C_WRITE) != 0) { ++ /* v2.0 board which does not have max8660 */ ++ system_rev |= 0x1 << 8; ++ /* workaround for WDOG reset pin */ ++ writel(0x11, IOMUXC_BASE_ADDR + 0xC); ++ diag_printf("Board version V2.0\n"); ++ } else { ++ diag_printf("Board version V1.0\n"); ++ } ++ ++#ifdef CYGPKG_DEVS_ETH_FEC ++ /** ++ * if we have v2.0 board, need to enable ++ * APLite VGEN1 regulator ++ */ ++ if (system_rev & 0xF00) { ++ /* set VGEN voltage to 3.3v */ ++ rq.dev_addr = 0x08; ++ rq.reg_addr = 0x1E; /* VGEN REG0 setting */ ++ rq.reg_addr_sz = 1; ++ rq.buffer = buf; ++ rq.buffer_sz = 3; ++ i2c_xfer(0, &rq, I2C_READ); ++ rq.buffer_sz = 3; ++ buf[2] |= 0x3; ++ i2c_xfer(0, &rq, I2C_WRITE); ++ /* enable FEC 3v3 */ ++ rq.dev_addr = 0x08; ++ rq.reg_addr = 0x20; /* VGEN REG0 */ ++ rq.reg_addr_sz = 1; ++ rq.buffer = buf; ++ rq.buffer_sz = 3; ++ i2c_xfer(0, &rq, I2C_READ); ++ rq.buffer_sz = 3; ++ buf[2] |= 0x1; ++ i2c_xfer(0, &rq, I2C_WRITE); ++ } ++#endif ++ ++} ++ ++RedBoot_init(mxc_pmic_detect, RedBoot_INIT_PRIO(101)); +diff -urNad redboot-imx-200952~/packages/devs/serial/arm/imx/current/ChangeLog redboot-imx-200952/packages/devs/serial/arm/imx/current/ChangeLog +--- redboot-imx-200952~/packages/devs/serial/arm/imx/current/ChangeLog 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/arm/imx/current/ChangeLog 2010-01-26 17:33:14.262959632 +0000 +@@ -0,0 +1,76 @@ ++2003-02-24 Jonathan Larmour ++ ++ * cdl/ser_arm_sa11x0.cdl: Remove irrelevant doc link. ++ ++2001-10-09 Hugo Tyson ++ ++ * src/sa11x0_serial.c (sa11x0_serial_DSR): Acknowledge the ++ interrupts for start or end of a line break, otherwise messing ++ with the wiring can cause an interrupt loop and hang the target. ++ ++2001-09-10 Jonathan Larmour ++ ++ * cdl/ser_arm_sa11x0.cdl: ++ Fix 234000->230400 typo. ++ ++2000-10-12 Jesper Skov ++ ++ * cdl/ser_arm_sa11x0.cdl: Testing parameters moved here. ++ ++2000-08-01 Jonathan Larmour ++ ++ * src/sa11x0_serial.c (sa11x0_serial_set_config): Now use keys to make ++ more flexible. ++ ++2000-06-29 Jesper Skov ++ ++ * src/sa11x0_serial.h: ++ * src/sa11x0_serial.c: ++ Registers renamed. ++ ++2000-06-22 Hugo Tyson ++ ++ * cdl/.cdl: Remove the comment on the empty ++ include_files directive; the tools now support this correctly. ++ This keeps internal include files internal. ++ ++2000-05-10 Gary Thomas ++ ++ * cdl/ser_arm_sa11x0.cdl: ++ * src/sa11x0_serial.h: ++ * src/sa11x0_serial.c: New file(s). ++ ++//=========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== +diff -urNad redboot-imx-200952~/packages/devs/serial/arm/imx/current/cdl/ser_arm_imx.cdl redboot-imx-200952/packages/devs/serial/arm/imx/current/cdl/ser_arm_imx.cdl +--- redboot-imx-200952~/packages/devs/serial/arm/imx/current/cdl/ser_arm_imx.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/arm/imx/current/cdl/ser_arm_imx.cdl 2010-01-26 17:33:14.262959632 +0000 +@@ -0,0 +1,131 @@ ++# ==================================================================== ++# ++# ser_arm_imx.cdl ++# ++# eCos serial Freescale MXC (ARM) configuration data ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Alex XIE ++# Contributors: Freescale ++# Date: 2008-10-10 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++ ++cdl_package CYGPKG_IO_SERIAL_ARM_IMX { ++ display "ARM i.MX serial device drivers" ++ ++ parent CYGPKG_IO_SERIAL_DEVICES ++ active_if CYGPKG_IO_SERIAL ++ ++ requires CYGPKG_ERROR ++ include_dir cyg/io ++ include_files ; # none _exported_ whatsoever ++ description " ++ This option enables the serial device drivers for the ++ i.MX platform." ++ ++ implements CYGINT_IO_SERIAL_BLOCK_TRANSFER ++ ++ compile -library=libextras.a imx_serial.c ++ ++ define_proc { ++ puts $::cdl_system_header "/***** serial driver proc output start *****/" ++ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER " ++ puts $::cdl_system_header "/***** serial driver proc output end *****/" ++ } ++ ++cdl_component CYGPKG_IO_SERIAL_ARM_IMX_SERIAL0 { ++ display "Freescale i.MX serial port 0 driver" ++ flavor bool ++ default_value 1 ++ description " ++ This option includes the serial device driver for the Freescale i.MX ++ port 0 ." ++ ++ cdl_option CYGDAT_IO_SERIAL_ARM_IMX_SERIAL0_NAME { ++ display "Device name for Freescale i.MX serial port 0 driver" ++ flavor data ++ default_value {"\"/dev/ser0\""} ++ description " ++ This option specifies the name of the serial device for the ++ Freescale i.MX port 0." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_ARM_IMX_SERIAL0_BAUD { ++ display "Baud rate for the Freescale i.MX serial port 0 driver" ++ flavor data ++ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 ++ 4800 7200 9600 14400 19200 38400 57600 115200 230400 ++ } ++ default_value 115200 ++ description " ++ This option specifies the default baud rate (speed) for the ++ Freescale i.MX port 0." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_ARM_IMX_SERIAL0_BUFSIZE { ++ display "Buffer size for the Freescale i.MX serial port 0 driver" ++ flavor data ++ legal_values 0 to 8192 ++ default_value 128 ++ description " ++ This option specifies the size of the internal buffers used ++ for the Freescale i.MX port 0." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_ARM_IMX_SERIAL0_RCV_CHUNK_SIZE { ++ display "Receive data chunk size" ++ flavor data ++ legal_values 1 to 65519 ++ default_value 1 ++ description " ++ This parameter can be used to reduce the number of interrupts ++ that must be processed by the driver. An interrupt will only ++ be generated if either this many data bytes have been received ++ or the receiver has been idle for some time. This reduces ++ overall system load at the expense of making the driver less ++ responsive and using slightly more memory for buffering data. ++ Setting this parameter to 1 will give standard behavior." ++ } ++} ++ ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/serial/arm/imx/current/src/imx_serial.c redboot-imx-200952/packages/devs/serial/arm/imx/current/src/imx_serial.c +--- redboot-imx-200952~/packages/devs/serial/arm/imx/current/src/imx_serial.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/arm/imx/current/src/imx_serial.c 2010-01-26 17:33:14.272962382 +0000 +@@ -0,0 +1,269 @@ ++//========================================================================== ++// ++// devs/serial/arm/mxc/imx_serial.c ++// ++// Freescale i.MX Serial I/O Interface Module ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Alex XIE ++// Contributors: Alex XIE ++// Date: 2008-10-10 ++// Purpose: Freescale imx Serial I/O module (interrupt driven version) ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CYGPKG_IO_SERIAL_ARM_IMX ++ ++#include "imx_serial.h" ++ ++#define RCVBUF_SIZE 16 ++ ++#ifdef CYGPKG_HAL_ARM_MX23_ARMADILLO ++struct mxc_serial { //0x80070000 ++ volatile cyg_uint32 HW_UARTDBGDR; //0x0 ++ volatile cyg_uint32 HW_UARTDBGRSR; //0x4 ++ volatile cyg_uint32 reserved1[4]; ++ volatile cyg_uint32 HW_UARTDBGFR; //0x18 ++ volatile cyg_uint32 reserved2; //0x1c ++ volatile cyg_uint32 HW_UARTDBGILPR; //0x20 ++ volatile cyg_uint32 HW_UARTDBGIBRD;//0x24 ++ volatile cyg_uint32 HW_UARTDBGFBRD;//0x28 ++ volatile cyg_uint32 HW_UARTDBGLCR; //0x2c ++ volatile cyg_uint32 HW_UARTDBGCR; //0x30 ++ volatile cyg_uint32 HW_UARTDBGIFLS;//0x34 ++ volatile cyg_uint32 HW_UARTDBGIMSC;//0x38 ++ volatile cyg_uint32 HW_UARTDBGRIS; //0x3c ++ volatile cyg_uint32 HW_UARTDBGMIS; //0x40 ++ volatile cyg_uint32 HW_UARTDBGICR; //0x44 ++ volatile cyg_uint32 HW_UARTDBGMACR; //0x48 ++ ++}; ++#else ++struct mxc_serial { ++ volatile cyg_uint32 urxd[16]; ++ volatile cyg_uint32 utxd[16]; ++ volatile cyg_uint32 ucr1; ++ volatile cyg_uint32 ucr2; ++ volatile cyg_uint32 ucr3; ++ volatile cyg_uint32 ucr4; ++ volatile cyg_uint32 ufcr; ++ volatile cyg_uint32 usr1; ++ volatile cyg_uint32 usr2; ++ volatile cyg_uint32 uesc; ++ volatile cyg_uint32 utim; ++ volatile cyg_uint32 ubir; ++ volatile cyg_uint32 ubmr; ++ volatile cyg_uint32 ubrc; ++ volatile cyg_uint32 onems; ++ volatile cyg_uint32 uts; ++}; ++#endif ++typedef struct { ++ volatile struct mxc_serial* base; ++ cyg_int32 msec_timeout; ++ int isr_vector; ++ int baud_rate; ++ cyg_interrupt serial_interrupt; ++ cyg_handle_t serial_interrupt_handle; ++ unsigned char receive_buf[RCVBUF_SIZE]; ++ unsigned int receive_point; ++// cyg_mutex_t mxc_serial_mutex; ++ cyg_sem_t mxc_serial_sem; ++} mxc_serial_info; ++ ++static bool mxc_serial_init(struct cyg_devtab_entry *tab); ++ ++ ++static unsigned char mxc_serial_getc_interrupt(serial_channel *chan); ++ ++static cyg_uint32 mxc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); ++static void mxc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); ++ ++static SERIAL_FUNS(mxc_serial_funs_interrupt, ++ 0, ++ mxc_serial_getc_interrupt, ++ 0, ++ 0, ++ 0 ++ ); ++ ++ ++static mxc_serial_info mxc_serial_info0 = { ++ (volatile struct mxc_serial*)UART1_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_IO_SERIAL_ARM_MXC_SERIAL0_BAUD, ++}; ++ ++static SERIAL_CHANNEL_USING_INTERRUPTS(mxc_serial_channel0, ++ mxc_serial_funs_interrupt, ++ mxc_serial_info0, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_MXC_SERIAL0_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT, ++ 0, 0, ++ 0, 0 ++ ); ++ ++ ++DEVTAB_ENTRY(mxc_serial_io0, ++ CYGDAT_IO_SERIAL_ARM_MXC_SERIAL0_NAME, ++ 0, // Does not depend on a lower level interface ++ &cyg_io_serial_devio, ++ mxc_serial_init, ++ 0, // Serial driver may need initializing ++ &mxc_serial_channel0 ++ ); ++ ++static void mxc_serial_isr_en(mxc_serial_info* mxc_chan) ++{ ++ ++ volatile struct mxc_serial* base=mxc_chan->base; ++#ifdef CYGPKG_HAL_ARM_MX23_ARMADILLO ++ base->HW_UARTDBGICR =0xffffffff; ++ base->HW_UARTDBGLCR &=~0x10; ++ base->HW_UARTDBGIFLS =0; ++ base->HW_UARTDBGIMSC =0;//|=0xffffffff; ++ base->HW_UARTDBGIMSC |=(1<<4); //&=~(1<<4); ++#else ++ base->ucr1 |= EUartUCR1_RRDYEN; ++#endif ++} ++ ++externC void* memset(void *, int, size_t); ++// Function to initialize the device. Called at bootstrap time. ++ ++static bool mxc_serial_init(struct cyg_devtab_entry *tab) ++{ ++ serial_channel * const chan = (serial_channel *) tab->priv; ++ mxc_serial_info * const mxc_chan = (mxc_serial_info *) chan->dev_priv; ++ int res=ENOERR; ++ ++ mxc_chan->receive_point=0; ++ memset(mxc_chan->receive_buf,0,RCVBUF_SIZE); ++ /* if you want to use serial_channel.in_cbuf.lock to block serial_read(), ++ you should call in the following function. ++ Now, we don't use it, we create the mutex in mx37_serial_info. ++ This help us to simplize the code. */ ++ /*(chan->callbacks->serial_init)(chan); */ /* Really only required for interrupt driven devices*/ ++ cyg_drv_interrupt_create(mxc_chan->isr_vector, ++ 2, // Priority ++ (cyg_addrword_t)chan, // Data item passed to interrupt handler ++ mxc_serial_ISR, ++ mxc_serial_DSR, ++ &mxc_chan->serial_interrupt_handle, ++ &mxc_chan->serial_interrupt); ++ cyg_drv_interrupt_attach(mxc_chan->serial_interrupt_handle); ++ cyg_semaphore_init(&mxc_chan->mxc_serial_sem,0); ++ mxc_serial_isr_en(mxc_chan); ++ cyg_drv_interrupt_unmask(mxc_chan->isr_vector); ++ return res; ++} ++ ++/* Fetch a character from the device input buffer, waiting if necessary*/ ++static unsigned char mxc_serial_getc_interrupt(serial_channel *chan) ++{ ++ mxc_serial_info * mxc_chan = (mxc_serial_info *) chan->dev_priv; ++ cyg_semaphore_wait(&mxc_chan->mxc_serial_sem); ++ if(mxc_chan->receive_point==0) ++ return mxc_chan->receive_buf[RCVBUF_SIZE-1]; ++ else ++ return mxc_chan->receive_buf[mxc_chan->receive_point-1]; ++} ++ ++// Serial I/O - low level interrupt handler (ISR) ++static cyg_uint32 ++mxc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ serial_channel * const chan = (serial_channel *) data; ++ mxc_serial_info * const mxc_chan = (mxc_serial_info *) chan->dev_priv; ++ volatile struct mxc_serial* base=mxc_chan->base; ++ ++#ifdef CYGPKG_HAL_ARM_MX23_ARMADILLO ++ ++ //base->HW_UARTDBGICR = base->HW_UARTDBGRIS; /*clear interrupt*/ ++ //interrupt_acknowledge(); ++ //if (!(base->HW_UARTDBGFR & (1<<4))) { // receive fifo not empty ++ mxc_chan->receive_buf[mxc_chan->receive_point]= (char)(base->HW_UARTDBGDR & 0xff); ++ mxc_chan->receive_point++; ++ if(mxc_chan->receive_point>=RCVBUF_SIZE) ++ mxc_chan->receive_point=0; ++ //} ++ base->HW_UARTDBGICR = base->HW_UARTDBGRIS; /*clear interrupt*/ ++ interrupt_acknowledge(); ++#else ++ if(base->usr1& EUartUSR1_RRDY){ ++ mxc_chan->receive_buf[mxc_chan->receive_point] = (char)base->urxd[0]; ++ mxc_chan->receive_point++; ++ if(mxc_chan->receive_point>=RCVBUF_SIZE) ++ mxc_chan->receive_point=0; ++ } ++#endif ++ return CYG_ISR_CALL_DSR; ++} ++ ++/* Serial I/O - high level interrupt handler (DSR)*/ ++static void ++mxc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ serial_channel * const chan = (serial_channel *) data; ++ mxc_serial_info * const mxc_chan = (mxc_serial_info *) chan->dev_priv; ++// cyg_mutex_unlock(&mxc_chan->mxc_serial_mutex);/*wake the blocking task*/ ++ cyg_semaphore_post(&mxc_chan->mxc_serial_sem); ++} ++#endif +diff -urNad redboot-imx-200952~/packages/devs/serial/arm/imx/current/src/imx_serial.h redboot-imx-200952/packages/devs/serial/arm/imx/current/src/imx_serial.h +--- redboot-imx-200952~/packages/devs/serial/arm/imx/current/src/imx_serial.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/arm/imx/current/src/imx_serial.h 2010-01-26 17:33:14.272962382 +0000 +@@ -0,0 +1,149 @@ ++#ifndef CYGONCE_ARM_MX51_SERIAL_H ++#define CYGONCE_ARM_MX51_SERIAL_H ++ ++/* ==================================================================== ++ ++ imx_serial.h ++ ++ Device I/O - Description of Freescale i.MX serial hardware ++ ++ ==================================================================== ++####ECOSGPLCOPYRIGHTBEGIN#### ++ ------------------------------------------- ++ This file is part of eCos, the Embedded Configurable Operating System. ++ Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++ ++ eCos is free software; you can redistribute it and/or modify it under ++ the terms of the GNU General Public License as published by the Free ++ Software Foundation; either version 2 or (at your option) any later version. ++ ++ eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++ WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ for more details. ++ ++ You should have received a copy of the GNU General Public License along ++ with eCos; if not, write to the Free Software Foundation, Inc., ++ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++ ++ As a special exception, if other files instantiate templates or use macros ++ or inline functions from this file, or you compile this file and link it ++ with other works to produce a work based on this file, this file does not ++ by itself cause the resulting work to be covered by the GNU General Public ++ License. However the source code for this file must still be made available ++ in accordance with section (3) of the GNU General Public License. ++ ++ This exception does not invalidate any other reasons why a work based on ++ this file might be covered by the GNU General Public License. ++ ++ Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++ at http://sources.redhat.com/ecos/ecos-license/ ++ ------------------------------------------- ++####ECOSGPLCOPYRIGHTEND#### ++ ==================================================================== ++#####DESCRIPTIONBEGIN#### ++ ++ Author(s): Alex XIE ++ Contributors: Freesacle ++ Date: 2008-10-10 ++ Purpose: Internal interfaces for serial I/O drivers ++ Description: ++ ++####DESCRIPTIONEND#### ++ ++ ==================================================================== ++ ++ Description of serial ports on Freescale i.MX ++*/ ++#include // Register definitions ++ ++/* ++ * UART Control Register 0 Bit Fields. ++ */ ++#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt ++#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate ++#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable ++#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt ++#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable ++#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable ++#define EUartUCR1_IREN (1 << 7) // Infrared interface enable ++#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable ++#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable ++#define EUartUCR1_SNDBRK (1 << 4) // Send break ++#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable ++#define EUartUCR1_DOZE (1 << 1) // Doze ++#define EUartUCR1_UARTEN (1 << 0) // UART enabled ++#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable ++#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin ++#define EUartUCR2_CTSC (1 << 13) // CTS pin control ++#define EUartUCR2_CTS (1 << 12) // Clear to send ++#define EUartUCR2_ESCEN (1 << 11) // Escape enable ++#define EUartUCR2_PREN (1 << 8) // Parity enable ++#define EUartUCR2_PROE (1 << 7) // Parity odd/even ++#define EUartUCR2_STPB (1 << 6) // Stop ++#define EUartUCR2_WS (1 << 5) // Word size ++#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable ++#define EUartUCR2_ATEN (1 << 3) // Aging timer enable ++#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled ++#define EUartUCR2_RXEN (1 << 1) // Receiver enabled ++#define EUartUCR2_SRST_ (1 << 0) // SW reset ++#define EUartUCR3_PARERREN (1 << 12) // Parity enable ++#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable ++#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved ++#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable ++#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable ++#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable ++#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected ++#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission ++#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable ++#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) ++#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception ++#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable ++#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable ++#define EUartUCR4_IRSC (1 << 5) // IR special case ++#define EUartUCR4_LPBYP (1 << 4) // Low power bypass ++#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable ++#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable ++#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable ++#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable ++#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift ++#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1) ++#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2) ++#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) ++#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) ++#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) ++#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) ++#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) ++#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift ++#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag ++#define EUartUSR1_RTSS (1 << 14) // RTS pin status ++#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag ++#define EUartUSR1_RTSD (1 << 12) // RTS delta ++#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag ++#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag ++#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag ++#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status ++#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag ++#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag ++#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag ++#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete ++#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty ++#define EUartUSR2_IDLE (1 << 12) // Idle condition ++#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped ++#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag ++#define EUartUSR2_WAKE (1 << 7) // Wake ++#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag ++#define EUartUSR2_TXDC (1 << 3) // Transmitter complete ++#define EUartUSR2_BRCD (1 << 2) // Break condition ++#define EUartUSR2_ORE (1 << 1) // Overrun error ++#define EUartUSR2_RDR (1 << 0) // Recv data ready ++#define EUartUTS_FRCPERR (1 << 13) // Force parity error ++#define EUartUTS_LOOP (1 << 12) // Loop tx and rx ++#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty ++#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty ++#define EUartUTS_TXFULL (1 << 4) // TxFIFO full ++#define EUartUTS_RXFULL (1 << 3) // RxFIFO full ++#define EUartUTS_SOFTRST (1 << 0) // Software reset ++ ++ ++#endif // CYGONCE_ARM_MX51_SERIAL_H +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/ChangeLog redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/ChangeLog +--- redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/ChangeLog 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/ChangeLog 2010-01-26 17:33:14.492957135 +0000 +@@ -0,0 +1,47 @@ ++2003-02-24 Jonathan Larmour ++ ++ * cdl/ser_powerpc_cme555.cdl: Remove irrelevant doc link. ++ ++2002-11-11 Bob Koninckx ++ ++ * src/cme555_serial_with_ints.c: ++ interrupt arbiter slightly modified to make GDB CTRL-C work ++ ++2002-04-24 Bob Koninckx ++ ++ * New package. ++ ++//=========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/cdl/ser_powerpc_cme555.cdl redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/cdl/ser_powerpc_cme555.cdl +--- redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/cdl/ser_powerpc_cme555.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/cdl/ser_powerpc_cme555.cdl 2010-01-26 17:33:14.492957135 +0000 +@@ -0,0 +1,184 @@ ++# ==================================================================== ++# ++# ser_powerpc_cme555.cdl ++# ++# eCos serial PowerPC/cme555 configuration data ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Bob Koninckx ++# Original data: ++# Contributors: ++# Date: 1999-07-14 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_IO_SERIAL_POWERPC_CME555 { ++ display "cme555 PowerPC serial device drivers" ++ ++ parent CYGPKG_IO_SERIAL_DEVICES ++ active_if CYGPKG_IO_SERIAL ++ active_if CYGPKG_HAL_POWERPC_CME555 ++ ++ requires CYGPKG_ERROR ++ include_dir cyg/io ++ include_files ; # none _exported_ whatsoever ++ description " ++ This option enables the serial device drivers for the ++ cme555 mpc555 development board." ++ ++ compile -library=libextras.a cme555_serial_with_ints.c ++ ++ define_proc { ++ puts $::cdl_system_header "/***** serial driver proc output start *****/" ++ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER " ++ puts $::cdl_system_header "/***** serial driver proc output end *****/" ++ } ++ ++cdl_component CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A { ++ display "cme555 PowerPC serial port A driver" ++ flavor bool ++ default_value 0 ++ description " ++ This option includes the serial device driver for the cme555 ++ PowerPC port A." ++ ++ cdl_option CYGDAT_IO_SERIAL_POWERPC_CME555_SERIAL_A_NAME { ++ display "Device name for cme555 PowerPC serial port A" ++ flavor data ++ default_value {"\"/dev/ser1\""} ++ description " ++ This option specifies the device name for the cme555 PowerPC ++ port A." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BAUD { ++ display "Baud rate for the cme555 PowerPC serial port A driver" ++ flavor data ++ legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } ++ default_value 38400 ++ description " ++ This option specifies the default baud rate (speed) for the ++ cme555 PowerPC port A." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BUFSIZE { ++ display "Buffer size for the cme555 PowerPC serial port A driver" ++ flavor data ++ legal_values 0 to 8192 ++ default_value 128 ++ description " ++ This option specifies the size of the internal buffers used for ++ the cme555 PowerPC port A." ++ } ++} ++ ++cdl_component CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B { ++ display "cme555 PowerPC serial port B driver" ++ flavor bool ++ default_value 1 ++ description " ++ This option includes the serial device driver for the cme555 ++ PowerPC port B." ++ ++ cdl_option CYGDAT_IO_SERIAL_POWERPC_CME555_SERIAL_B_NAME { ++ display "Device name for cme555 PowerPC serial port B" ++ flavor data ++ default_value {"\"/dev/ser2\""} ++ description " ++ This option specifies the device name for the cme555 PowerPC ++ port B." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BAUD { ++ display "Baud rate for the cme555 PowerPC serial port B driver" ++ flavor data ++ legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } ++ default_value 38400 ++ description " ++ This option specifies the default baud rate (speed) for the ++ cme555 PowerPC port B." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BUFSIZE { ++ display "Buffer size for the cme555 PowerPC serial port B driver" ++ flavor data ++ legal_values 0 to 8192 ++ default_value 128 ++ description " ++ This option specifies the size of the internal buffers used ++ for the cme555 PowerPC port B." ++ } ++} ++ ++ cdl_component CYGPKG_IO_SERIAL_POWERPC_CME555_OPTIONS { ++ display "Serial device driver build options" ++ flavor none ++ description " ++ Package specific build options including control over ++ compiler flags used only in building this package, ++ and details of which tests are built." ++ ++ ++ cdl_option CYGPKG_IO_SERIAL_POWERPC_CME555_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building these serial device drivers. These flags are used in addition ++ to the set of global flags." ++ } ++ ++ cdl_option CYGPKG_IO_SERIAL_POWERPC_CME555_CFLAGS_REMOVE { ++ display "Suppressed compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building these serial device drivers. These flags are removed from ++ the set of global flags if present." ++ } ++ } ++ ++} ++ ++# EOF ser_powerpc_cme555.cdl +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/src/cme555_serial.h redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/src/cme555_serial.h +--- redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/src/cme555_serial.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/src/cme555_serial.h 2010-01-26 17:33:14.492957135 +0000 +@@ -0,0 +1,157 @@ ++#ifndef CYGONCE_DEVS_SERIAL_POWERPC_CME555_SERIAL_H ++#define CYGONCE_DEVS_SERIAL_POWERPC_CME555_SERIAL_H ++//========================================================================== ++// ++// cme555_serial.h ++// ++// PowerPC 5xx CME555 Serial I/O definitions. ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Bob Koninckx ++// Contributors: ++// Date: 2002-04-25 ++// Purpose: CME555 Serial I/O definitions. ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//========================================================================== ++ ++//---------------------------------- ++// Includes and forward declarations ++//---------------------------------- ++ ++//---------------------- ++// Constants definitions ++//---------------------- ++// Base addresses for the two serial ports ++#define MPC555_SERIAL_BASE_A 0x305008 ++#define MPC555_SERIAL_BASE_B 0x305020 ++ ++// The offset from the base for all serial registers ++#define MPC555_SERIAL_SCCxR0 0 ++#define MPC555_SERIAL_SCCxR1 2 ++#define MPC555_SERIAL_SCxSR 4 ++#define MPC555_SERIAL_SCxDR 6 ++ ++// The bits in the serial registers ++#define MPC555_SERIAL_SCCxR0_OTHR 0x8000 ++#define MPC555_SERIAL_SCCxR0_LINKBD 0x4000 ++#define MPC555_SERIAL_SCCxR0_SCxBR 0x1fff ++ ++#define MPC555_SERIAL_SCCxR1_LOOPS 0x4000 ++#define MPC555_SERIAL_SCCxR1_WOMS 0x2000 ++#define MPC555_SERIAL_SCCxR1_ILT 0x1000 ++#define MPC555_SERIAL_SCCxR1_PT 0x0800 ++#define MPC555_SERIAL_SCCxR1_PE 0x0400 ++#define MPC555_SERIAL_SCCxR1_M 0x0200 ++#define MPC555_SERIAL_SCCxR1_WAKE 0x0100 ++#define MPC555_SERIAL_SCCxR1_TIE 0x0080 ++#define MPC555_SERIAL_SCCxR1_TCIE 0x0040 ++#define MPC555_SERIAL_SCCxR1_RIE 0x0020 ++#define MPC555_SERIAL_SCCxR1_ILIE 0x0010 ++#define MPC555_SERIAL_SCCxR1_TE 0x0008 ++#define MPC555_SERIAL_SCCxR1_RE 0x0004 ++#define MPC555_SERIAL_SCCxR1_RWU 0x0002 ++#define MPC555_SERIAL_SCCxR1_SBK 0x0001 ++ ++#define MPC555_SERIAL_SCxSR_TDRE 0x0100 ++#define MPC555_SERIAL_SCxSR_TC 0x0080 ++#define MPC555_SERIAL_SCxSR_RDRF 0x0040 ++#define MPC555_SERIAL_SCxSR_RAF 0x0020 ++#define MPC555_SERIAL_SCxSR_IDLE 0x0010 ++#define MPC555_SERIAL_SCxSR_OR 0x0008 ++#define MPC555_SERIAL_SCxSR_NF 0x0004 ++#define MPC555_SERIAL_SCxSR_FE 0x0002 ++#define MPC555_SERIAL_SCxSR_PF 0x0001 ++ ++// The available baud rates ++// These are calculated for a busclock of 40 MHz ++// It is not necessary to let the compiler calculate these ++// values, we did not provide clockfrequency as a configuarion ++// option anyway. ++static unsigned short select_baud[] = { ++ 0, // Unused ++ 0, // 50 bps unsupported ++ 0, // 75 bps unsupported ++ 0, // 110 bps unsupported ++ 0, // 134_5 bps unsupported ++ 0, // 150 bps unsupported ++ 0, // 200 bps unsupported ++ 4167, // 300 bps ++ 2083, // 600 bps ++ 1042, // 1200 bps ++ 0, // 1800 bps unsupported ++ 521, // 2400 bps ++ 0, // 3600 bps unsupported ++ 260, // 4800 bps ++ 0, // 7200 bps unsupported ++ 130, // 9600 bps ++ 87, // 14400 bps ++ 65, // 19200 bps ++ 33, // 38400 bps ++ 22, // 57600 bps ++ 11, // 115200 bps ++ 0 // 230400 bps unsupported ++}; ++ ++static unsigned char select_word_length[] = { ++ 0, // 5 bits / word (char) not supported ++ 0, // 6 bits / word (char) not supported ++ 7, // 7 bits / word (char) ->> 7 bits per frame ++ 8 // 8 bits / word (char) ->> 8 bits per frame ++}; ++ ++static unsigned char select_stop_bits[] = { ++ 0, ++ 1, // 1 stop bit ->> 1 bit per frame ++ 0, // 1.5 stop bit not supported ++ 2 // 2 stop bits ->> 2 bits per frame ++}; ++ ++static unsigned char select_parity[] = { ++ 0, // No parity ->> 0 bits per frame ++ 1, // Even parity ->> 1 bit per frame ++ 1, // Odd parityv ->> 1 bit per frame ++ 0, // Mark parity not supported ++ 0, // Space parity not supported ++}; ++ ++#endif // CYGONCE_DEVS_SERIAL_POWERPC_CME555_SERIAL_H ++ ++// EOF cme555_serial.h +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c +--- redboot-imx-200952~/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 2010-01-26 17:33:14.502961760 +0000 +@@ -0,0 +1,634 @@ ++//========================================================================== ++// ++// cme555_serial_with_ints.c ++// ++// PowerPC 5xx CME555 Serial I/O Interface Module (interrupt driven) ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Bob Koninckx ++// Contributors: ++// Date: 2002-04-25 ++// Purpose: CME555 Serial I/O module (interrupt driven version) ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//========================================================================== ++//---------------------------------- ++// Includes and forward declarations ++//---------------------------------- ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Only build this driver for the MPC555 based CME555 board ++#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555 ++ ++#include "cme555_serial.h" ++ ++//----------------- ++// Type definitions ++//----------------- ++typedef struct mpc555_serial_info { ++ CYG_ADDRWORD base; // The base address of the serial port ++ CYG_WORD tx_interrupt_num; // trivial ++ CYG_WORD rx_interrupt_num; // trivial ++ cyg_priority_t tx_interrupt_priority; // trivial ++ cyg_priority_t rx_interrupt_priority; // trivial ++ bool tx_interrupt_enable; // tells if the transmit interrupt may be re-enabled ++ cyg_interrupt tx_interrupt; // the tx interrupt object ++ cyg_handle_t tx_interrupt_handle; // the tx interrupt handle ++ cyg_interrupt rx_interrupt; // the rx interrupt object ++ cyg_handle_t rx_interrupt_handle; // the rx interrupt handle ++} mpc555_serial_info; ++ ++//-------------------- ++// Function prototypes ++//-------------------- ++static bool mpc555_serial_init(struct cyg_devtab_entry * tab); ++static bool mpc555_serial_putc(serial_channel * chan, unsigned char c); ++static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, ++ struct cyg_devtab_entry * sub_tab, ++ const char * name); ++static unsigned char mpc555_serial_getc(serial_channel *chan); ++static Cyg_ErrNo mpc555_serial_set_config(serial_channel *chan, cyg_uint32 key, ++ const void *xbuf, cyg_uint32 *len); ++static void mpc555_serial_start_xmit(serial_channel *chan); ++static void mpc555_serial_stop_xmit(serial_channel *chan); ++ ++// The interrupt servers ++static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); ++static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); ++static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); ++static void mpc555_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); ++ ++//------------------------------------------- ++// Register the device driver with the kernel ++//------------------------------------------- ++static SERIAL_FUNS(mpc555_serial_funs, ++ mpc555_serial_putc, ++ mpc555_serial_getc, ++ mpc555_serial_set_config, ++ mpc555_serial_start_xmit, ++ mpc555_serial_stop_xmit); ++ ++//------------------- ++// Device driver data ++//------------------- ++#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A ++static mpc555_serial_info mpc555_serial_info0 = {MPC555_SERIAL_BASE_A, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX_PRIORITY, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX_PRIORITY, ++ false}; ++#if CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BUFSIZE > 0 ++static unsigned char mpc555_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BUFSIZE]; ++static unsigned char mpc555_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BUFSIZE]; ++ ++static SERIAL_CHANNEL_USING_INTERRUPTS(mpc555_serial_channel0, ++ mpc555_serial_funs, ++ mpc555_serial_info0, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT, ++ &mpc555_serial_out_buf0[0], ++ sizeof(mpc555_serial_out_buf0), ++ &mpc555_serial_in_buf0[0], ++ sizeof(mpc555_serial_in_buf0)); ++#else ++static SERIAL_CHANNEL(mpc555_serial_channel0, ++ mpc555_serial_funs, ++ mpc555_serial_info0, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_A_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT); ++#endif ++DEVTAB_ENTRY(mpc555_serial_io0, ++ CYGDAT_IO_SERIAL_POWERPC_CME555_SERIAL_A_NAME, ++ 0, // does not depend on a lower level device driver ++ &cyg_io_serial_devio, ++ mpc555_serial_init, ++ mpc555_serial_lookup, ++ &mpc555_serial_channel0); ++#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A ++ ++#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B ++static mpc555_serial_info mpc555_serial_info1 = {MPC555_SERIAL_BASE_B, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, ++ false}; ++#if CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BUFSIZE > 0 ++static unsigned char mpc555_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BUFSIZE]; ++static unsigned char mpc555_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BUFSIZE]; ++ ++static SERIAL_CHANNEL_USING_INTERRUPTS(mpc555_serial_channel1, ++ mpc555_serial_funs, ++ mpc555_serial_info1, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT, ++ &mpc555_serial_out_buf1[0], ++ sizeof(mpc555_serial_out_buf1), ++ &mpc555_serial_in_buf1[0], ++ sizeof(mpc555_serial_in_buf1)); ++#else ++static SERIAL_CHANNEL(mpc555_serial_channel1, ++ mpc555_serial_funs, ++ mpc555_serial_info1, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_CME555_SERIAL_B_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT); ++#endif ++DEVTAB_ENTRY(mpc555_serial_io1, ++ CYGDAT_IO_SERIAL_POWERPC_CME555_SERIAL_B_NAME, ++ 0, // does not depend on a lower level device driver ++ &cyg_io_serial_devio, ++ mpc555_serial_init, ++ mpc555_serial_lookup, ++ &mpc555_serial_channel1); ++#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B ++ ++//----------------------------- ++// Device driver implementation ++//----------------------------- ++ ++// The arbitration isr. ++// I think this is the best place to implement it. The device driver is the only place ++// in the code where the knowledge is present about how the hardware is used ++// ++// Always check receive interrupts. Some rom monitor might be waiting for CTRL-C ++static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data) ++{ ++ cyg_uint16 status; ++ cyg_uint16 control; ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control); ++ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); ++#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A // Do not waist time on unused hardware ++ if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE); ++#endif ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control); ++ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); ++#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B // Do not waist time on unused hardware ++ if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); ++ ++#if 0 ++ // The driver doesn't use the queue operation of the hardware (It would need different code for serial 1 and 2 ++ // since oly one port supports queue mode). So the following is not needed. ++ // Leave it there. It is easyer for later implementations to remove the comments than finding ++ // out how the hardware works again. ++ HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, control); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QTHF) && (control & CYGARC_REG_IMM_QSCI1CR_QTHFI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QBHF) && (control & CYGARC_REG_IMM_QSCI1CR_QBHFI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QTHE) && (control & CYGARC_REG_IMM_QSCI1CR_QTHEI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QBHE) && (control & CYGARC_REG_IMM_QSCI1CR_QBHEI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE); ++ ++ cyg_uint16 status; ++ cyg_uint16 control; ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, control); ++ if((status & CYGARC_REG_IMM_SPSR_SPIF) && (control & CYGARC_REG_IMM_SPCR2_SPIFIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI); ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, control); ++ if((status & CYGARC_REG_IMM_SPSR_MODF) && (control & CYGARC_REG_IMM_SPCR3_HMIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF); ++ ++ if((status & CYGARC_REG_IMM_SPSR_HALTA) && (control & CYGARC_REG_IMM_SPCR3_HMIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA); ++#endif ++ ++#endif ++ ++ return 0; ++} ++ ++//-------------------------------------------------------------------------------- ++// Internal function to actually configure the hardware to desired baud rate, etc. ++//-------------------------------------------------------------------------------- ++static bool mpc555_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config, bool init) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)(chan->dev_priv); ++ ++ cyg_addrword_t port = mpc555_chan->base; ++ cyg_uint16 baud_rate = select_baud[new_config->baud]; ++ unsigned char frame_length = 1; // The start bit ++ ++ cyg_uint16 old_isrstate; ++ cyg_uint16 sccxr; ++ ++ if(!baud_rate) ++ return false; // Invalid baud rate selected ++ ++ if((new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_7) && ++ (new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_8)) ++ return false; // Invalid word length selected ++ ++ if((new_config->parity != CYGNUM_SERIAL_PARITY_NONE) && ++ (new_config->parity != CYGNUM_SERIAL_PARITY_EVEN) && ++ (new_config->parity != CYGNUM_SERIAL_PARITY_ODD)) ++ return false; // Invalid parity selected ++ ++ if((new_config->stop != CYGNUM_SERIAL_STOP_1) && ++ (new_config->stop != CYGNUM_SERIAL_STOP_2)) ++ return false; // Invalid stop bits selected ++ ++ frame_length += select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; ++ frame_length += select_stop_bits[new_config->stop]; ++ frame_length += select_parity[new_config->parity]; ++ ++ if((frame_length != 10) && (frame_length != 11)) ++ return false; // Invalid frame format selected ++ ++ // Disable port interrupts while changing hardware ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ old_isrstate = sccxr; ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_LOOPS); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WOMS); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILT); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WAKE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RWU); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_SBK); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TCIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILIE); ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ // Set databits, stopbits and parity. ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ if(frame_length == 11) ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_M; ++ else ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); ++ ++ switch(new_config->parity) ++ { ++ case CYGNUM_SERIAL_PARITY_NONE: ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); ++ break; ++ case CYGNUM_SERIAL_PARITY_EVEN: ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); ++ break; ++ case CYGNUM_SERIAL_PARITY_ODD: ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PT; ++ break; ++ default: ++ break; ++ } ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ // Set baud rate. ++ baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_OTHR); ++ baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_LINKBD); ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); ++ sccxr &= ~(MPC555_SERIAL_SCCxR0_SCxBR); ++ sccxr |= baud_rate; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); ++ ++ // Enable the device ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= MPC555_SERIAL_SCCxR1_TE; ++ sccxr |= MPC555_SERIAL_SCCxR1_RE; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ if(init) ++ { // enable the receiver interrupt ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= MPC555_SERIAL_SCCxR1_RIE; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ } ++ else // Restore the old interrupt state ++ { ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= old_isrstate; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ } ++ ++ if(new_config != &chan->config) ++ chan->config = *new_config; ++ ++ return true; ++} ++ ++//-------------------------------------------------------------- ++// Function to initialize the device. Called at bootstrap time. ++//-------------------------------------------------------------- ++static hal_mpc5xx_arbitration_data arbiter; ++ ++static bool mpc555_serial_init(struct cyg_devtab_entry * tab) ++{ ++ serial_channel * chan = (serial_channel *)tab->priv; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ if(!mpc555_serial_config_port(chan, &chan->config, true)) ++ return false; ++ ++ (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices ++ if(chan->out_cbuf.len != 0) ++ { ++ arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI; ++ arbiter.data = 0; ++ arbiter.arbiter = hal_arbitration_isr_qsci; ++ ++ // Install the arbitration isr, Make sure that is is not installed twice ++ hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); ++ hal_mpc5xx_install_arbitration_isr(&arbiter); ++ ++ // Create the Tx interrupt, do not enable it yet ++ cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_num, ++ mpc555_chan->tx_interrupt_priority, ++ (cyg_addrword_t)chan, // Data item passed to interrupt handler ++ mpc555_serial_tx_ISR, ++ mpc555_serial_tx_DSR, ++ &mpc555_chan->tx_interrupt_handle, ++ &mpc555_chan->tx_interrupt); ++ cyg_drv_interrupt_attach(mpc555_chan->tx_interrupt_handle); ++ ++ // Create the Rx interrupt, this can be safely unmasked now ++ cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_num, ++ mpc555_chan->rx_interrupt_priority, ++ (cyg_addrword_t)chan, ++ mpc555_serial_rx_ISR, ++ mpc555_serial_rx_DSR, ++ &mpc555_chan->rx_interrupt_handle, ++ &mpc555_chan->rx_interrupt); ++ cyg_drv_interrupt_attach(mpc555_chan->rx_interrupt_handle); ++ cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); ++ } ++ ++ return true; ++} ++ ++//---------------------------------------------------------------------- ++// This routine is called when the device is "looked" up (i.e. attached) ++//---------------------------------------------------------------------- ++static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, ++ struct cyg_devtab_entry * sub_tab, ++ const char * name) ++{ ++ serial_channel * chan = (serial_channel *)(*tab)->priv; ++ (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices ++ ++ return ENOERR; ++} ++ ++//---------------------------------------------- ++// Send a character to the device output buffer. ++// Return 'true' if character is sent to device ++//---------------------------------------------- ++static bool mpc555_serial_putc(serial_channel * chan, unsigned char c) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ ++ cyg_uint16 scsr; ++ cyg_uint16 scdr; ++ ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ if(scsr & MPC555_SERIAL_SCxSR_TDRE) ++ { // Ok, we have space, write the character and return success ++ scdr = (cyg_uint16)c; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ return true; ++ } ++ else ++ // We cannot write to the transmitter, return failure ++ return false; ++} ++ ++//--------------------------------------------------------------------- ++// Fetch a character from the device input buffer, waiting if necessary ++//--------------------------------------------------------------------- ++static unsigned char mpc555_serial_getc(serial_channel * chan) ++{ ++ unsigned char c; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ ++ cyg_uint16 scsr; ++ cyg_uint16 scdr; ++ ++ do { ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ } while(!(scsr & MPC555_SERIAL_SCxSR_RDRF)); ++ ++ // Ok, data is received, read it out and return ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ c = (unsigned char)scdr; ++ ++ return c; ++} ++ ++//--------------------------------------------------- ++// Set up the device characteristics; baud rate, etc. ++//--------------------------------------------------- ++static bool mpc555_serial_set_config(serial_channel * chan, cyg_uint32 key, ++ const void *xbuf, cyg_uint32 * len) ++{ ++ switch(key) { ++ case CYG_IO_SET_CONFIG_SERIAL_INFO: ++ { ++ cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; ++ if(*len < sizeof(cyg_serial_info_t)) { ++ return -EINVAL; ++ } ++ *len = sizeof(cyg_serial_info_t); ++ if(true != mpc555_serial_config_port(chan, config, false)) ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ return ENOERR; ++} ++ ++//------------------------------------- ++// Enable the transmitter on the device ++//------------------------------------- ++static void mpc555_serial_start_xmit(serial_channel * chan) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ mpc555_chan->tx_interrupt_enable = true; ++ cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); ++ ++ // No need to call xmt_char, this will generate an interrupt immediately. ++} ++ ++//-------------------------------------- ++// Disable the transmitter on the device ++//-------------------------------------- ++static void mpc555_serial_stop_xmit(serial_channel * chan) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_dsr_lock(); ++ mpc555_chan->tx_interrupt_enable = false; ++ cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); ++ cyg_drv_dsr_unlock(); ++} ++ ++//----------------------------------------- ++// The low level transmit interrupt handler ++//----------------------------------------- ++static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); ++ cyg_drv_interrupt_acknowledge(mpc555_chan->tx_interrupt_num); ++ ++ return CYG_ISR_CALL_DSR; // cause the DSR to run ++} ++ ++//---------------------------------------- ++// The low level receive interrupt handler ++//---------------------------------------- ++static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_num); ++ cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_num); ++ ++ return CYG_ISR_CALL_DSR; // cause the DSR to run ++} ++ ++//------------------------------------------ ++// The high level transmit interrupt handler ++//------------------------------------------ ++static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ (chan->callbacks->xmt_char)(chan); ++ if(mpc555_chan->tx_interrupt_enable) ++ cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); ++} ++ ++//----------------------------------------- ++// The high level receive interrupt handler ++//----------------------------------------- ++#define MPC555_SERIAL_SCxSR_ERRORS (MPC555_SERIAL_SCxSR_OR | \ ++ MPC555_SERIAL_SCxSR_NF | \ ++ MPC555_SERIAL_SCxSR_FE | \ ++ MPC555_SERIAL_SCxSR_PF) ++ ++static void mpc555_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ cyg_uint16 scdr; ++ cyg_uint16 scsr; ++ ++ // Allways read out the received character, in order to clear receiver flags ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ if(scsr & (cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS) ++ { ++ scsr &= ~((cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS); ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ } ++ else ++ { ++ (chan->callbacks->rcv_char)(chan, (cyg_uint8)scdr); ++ } ++ ++ cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); ++} ++ ++#endif // CYGPKG_IO_SERIAL_POWERPC_CME555 ++ ++// EOF cmd555_serial_with_ints.c +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/ChangeLog redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/ChangeLog +--- redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/ChangeLog 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/ChangeLog 2010-01-26 17:33:14.522959634 +0000 +@@ -0,0 +1,47 @@ ++2003-02-24 Jonathan Larmour ++ ++ * cdl/ser_powerpc_ec555.cdl: Remove irrelevant doc link. ++ ++2002-11-11 Bob Koninckx ++ ++ * src/ec555_serial_with_ints: ++ arbiter slightly modified to make GDB-CTRLC work. ++ ++2002-04-24 Bob Koninckx ++ ++ * New package. ++ ++//=========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//=========================================================================== +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/cdl/ser_powerpc_ec555.cdl redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/cdl/ser_powerpc_ec555.cdl +--- redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/cdl/ser_powerpc_ec555.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/cdl/ser_powerpc_ec555.cdl 2010-01-26 17:33:14.512959760 +0000 +@@ -0,0 +1,184 @@ ++# ==================================================================== ++# ++# ser_powerpc_ec555.cdl ++# ++# eCos serial PowerPC/ec555 configuration data ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Bob Koninckx ++# Original data: ++# Contributors: ++# Date: 1999-07-14 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_IO_SERIAL_POWERPC_EC555 { ++ display "ec555 PowerPC serial device drivers" ++ ++ parent CYGPKG_IO_SERIAL_DEVICES ++ active_if CYGPKG_IO_SERIAL ++ active_if CYGPKG_HAL_POWERPC_EC555 ++ ++ requires CYGPKG_ERROR ++ include_dir cyg/io ++ include_files ; # none _exported_ whatsoever ++ description " ++ This option enables the serial device drivers for the ++ ec555 mpc555 development board." ++ ++ compile -library=libextras.a ec555_serial_with_ints.c ++ ++ define_proc { ++ puts $::cdl_system_header "/***** serial driver proc output start *****/" ++ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER " ++ puts $::cdl_system_header "/***** serial driver proc output end *****/" ++ } ++ ++cdl_component CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A { ++ display "ec555 PowerPC serial port A driver" ++ flavor bool ++ default_value 0 ++ description " ++ This option includes the serial device driver for the ec555 ++ PowerPC port A." ++ ++ cdl_option CYGDAT_IO_SERIAL_POWERPC_EC555_SERIAL_A_NAME { ++ display "Device name for ec555 PowerPC serial port A" ++ flavor data ++ default_value {"\"/dev/ser1\""} ++ description " ++ This option specifies the device name for the ec555 PowerPC ++ port A." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BAUD { ++ display "Baud rate for the ec555 PowerPC serial port A driver" ++ flavor data ++ legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } ++ default_value 38400 ++ description " ++ This option specifies the default baud rate (speed) for the ++ ec555 PowerPC port A." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BUFSIZE { ++ display "Buffer size for the ec555 PowerPC serial port A driver" ++ flavor data ++ legal_values 0 to 8192 ++ default_value 128 ++ description " ++ This option specifies the size of the internal buffers used for ++ the ec555 PowerPC port A." ++ } ++} ++ ++cdl_component CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B { ++ display "ec555 PowerPC serial port B driver" ++ flavor bool ++ default_value 1 ++ description " ++ This option includes the serial device driver for the ec555 ++ PowerPC port B." ++ ++ cdl_option CYGDAT_IO_SERIAL_POWERPC_EC555_SERIAL_B_NAME { ++ display "Device name for ec555 PowerPC serial port B" ++ flavor data ++ default_value {"\"/dev/ser2\""} ++ description " ++ This option specifies the device name for the ec555 PowerPC ++ port B." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BAUD { ++ display "Baud rate for the ec555 PowerPC serial port B driver" ++ flavor data ++ legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 57600 115200 } ++ default_value 38400 ++ description " ++ This option specifies the default baud rate (speed) for the ++ ec555 PowerPC port B." ++ } ++ ++ cdl_option CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BUFSIZE { ++ display "Buffer size for the ec555 PowerPC serial port B driver" ++ flavor data ++ legal_values 0 to 8192 ++ default_value 128 ++ description " ++ This option specifies the size of the internal buffers used ++ for the ec555 PowerPC port B." ++ } ++} ++ ++ cdl_component CYGPKG_IO_SERIAL_POWERPC_EC555_OPTIONS { ++ display "Serial device driver build options" ++ flavor none ++ description " ++ Package specific build options including control over ++ compiler flags used only in building this package, ++ and details of which tests are built." ++ ++ ++ cdl_option CYGPKG_IO_SERIAL_POWERPC_EC555_CFLAGS_ADD { ++ display "Additional compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building these serial device drivers. These flags are used in addition ++ to the set of global flags." ++ } ++ ++ cdl_option CYGPKG_IO_SERIAL_POWERPC_EC555_CFLAGS_REMOVE { ++ display "Suppressed compiler flags" ++ flavor data ++ no_define ++ default_value { "" } ++ description " ++ This option modifies the set of compiler flags for ++ building these serial device drivers. These flags are removed from ++ the set of global flags if present." ++ } ++ } ++ ++} ++ ++# EOF ser_powerpc_ec555.cdl +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/src/ec555_serial.h redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/src/ec555_serial.h +--- redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/src/ec555_serial.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/src/ec555_serial.h 2010-01-26 17:33:14.522959634 +0000 +@@ -0,0 +1,157 @@ ++#ifndef CYGONCE_DEVS_SERIAL_POWERPC_EC555_SERIAL_H ++#define CYGONCE_DEVS_SERIAL_POWERPC_EC555_SERIAL_H ++//========================================================================== ++// ++// ec555_serial.h ++// ++// PowerPC 5xx EC555 Serial I/O definitions. ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Bob Koninckx ++// Contributors: ++// Date: 2002-04-25 ++// Purpose: EC555 Serial I/O definitions. ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//========================================================================== ++ ++//---------------------------------- ++// Includes and forward declarations ++//---------------------------------- ++ ++//---------------------- ++// Constants definitions ++//---------------------- ++// Base addresses for the two serial ports ++#define MPC555_SERIAL_BASE_A 0x305008 ++#define MPC555_SERIAL_BASE_B 0x305020 ++ ++// The offset from the base for all serial registers ++#define MPC555_SERIAL_SCCxR0 0 ++#define MPC555_SERIAL_SCCxR1 2 ++#define MPC555_SERIAL_SCxSR 4 ++#define MPC555_SERIAL_SCxDR 6 ++ ++// The bits in the serial registers ++#define MPC555_SERIAL_SCCxR0_OTHR 0x8000 ++#define MPC555_SERIAL_SCCxR0_LINKBD 0x4000 ++#define MPC555_SERIAL_SCCxR0_SCxBR 0x1fff ++ ++#define MPC555_SERIAL_SCCxR1_LOOPS 0x4000 ++#define MPC555_SERIAL_SCCxR1_WOMS 0x2000 ++#define MPC555_SERIAL_SCCxR1_ILT 0x1000 ++#define MPC555_SERIAL_SCCxR1_PT 0x0800 ++#define MPC555_SERIAL_SCCxR1_PE 0x0400 ++#define MPC555_SERIAL_SCCxR1_M 0x0200 ++#define MPC555_SERIAL_SCCxR1_WAKE 0x0100 ++#define MPC555_SERIAL_SCCxR1_TIE 0x0080 ++#define MPC555_SERIAL_SCCxR1_TCIE 0x0040 ++#define MPC555_SERIAL_SCCxR1_RIE 0x0020 ++#define MPC555_SERIAL_SCCxR1_ILIE 0x0010 ++#define MPC555_SERIAL_SCCxR1_TE 0x0008 ++#define MPC555_SERIAL_SCCxR1_RE 0x0004 ++#define MPC555_SERIAL_SCCxR1_RWU 0x0002 ++#define MPC555_SERIAL_SCCxR1_SBK 0x0001 ++ ++#define MPC555_SERIAL_SCxSR_TDRE 0x0100 ++#define MPC555_SERIAL_SCxSR_TC 0x0080 ++#define MPC555_SERIAL_SCxSR_RDRF 0x0040 ++#define MPC555_SERIAL_SCxSR_RAF 0x0020 ++#define MPC555_SERIAL_SCxSR_IDLE 0x0010 ++#define MPC555_SERIAL_SCxSR_OR 0x0008 ++#define MPC555_SERIAL_SCxSR_NF 0x0004 ++#define MPC555_SERIAL_SCxSR_FE 0x0002 ++#define MPC555_SERIAL_SCxSR_PF 0x0001 ++ ++// The available baud rates ++// These are calculated for a busclock of 40 MHz ++// It is not necessary to let the compiler calculate these ++// values, we did not provide clockfrequency as a configuarion ++// option anyway. ++static unsigned short select_baud[] = { ++ 0, // Unused ++ 0, // 50 bps unsupported ++ 0, // 75 bps unsupported ++ 0, // 110 bps unsupported ++ 0, // 134_5 bps unsupported ++ 0, // 150 bps unsupported ++ 0, // 200 bps unsupported ++ 4167, // 300 bps ++ 2083, // 600 bps ++ 1042, // 1200 bps ++ 0, // 1800 bps unsupported ++ 521, // 2400 bps ++ 0, // 3600 bps unsupported ++ 260, // 4800 bps ++ 0, // 7200 bps unsupported ++ 130, // 9600 bps ++ 87, // 14400 bps ++ 65, // 19200 bps ++ 33, // 38400 bps ++ 22, // 57600 bps ++ 11, // 115200 bps ++ 0 // 230400 bps unsupported ++}; ++ ++static unsigned char select_word_length[] = { ++ 0, // 5 bits / word (char) not supported ++ 0, // 6 bits / word (char) not supported ++ 7, // 7 bits / word (char) ->> 7 bits per frame ++ 8 // 8 bits / word (char) ->> 8 bits per frame ++}; ++ ++static unsigned char select_stop_bits[] = { ++ 0, ++ 1, // 1 stop bit ->> 1 bit per frame ++ 0, // 1.5 stop bit not supported ++ 2 // 2 stop bits ->> 2 bits per frame ++}; ++ ++static unsigned char select_parity[] = { ++ 0, // No parity ->> 0 bits per frame ++ 1, // Even parity ->> 1 bit per frame ++ 1, // Odd parityv ->> 1 bit per frame ++ 0, // Mark parity not supported ++ 0, // Space parity not supported ++}; ++ ++#endif // CYGONCE_DEVS_SERIAL_POWERPC_EC555_SERIAL_H ++ ++// EOF ec555_serial.h +diff -urNad redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c +--- redboot-imx-200952~/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 2010-01-26 17:33:14.532960509 +0000 +@@ -0,0 +1,636 @@ ++//========================================================================== ++// ++// ec555_serial_with_ints.c ++// ++// PowerPC 5xx EC555 Serial I/O Interface Module (interrupt driven) ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Bob Koninckx ++// Contributors: ++// Date: 2002-04-25 ++// Purpose: EC555 Serial I/O module (interrupt driven version) ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++//========================================================================== ++//---------------------------------- ++// Includes and forward declarations ++//---------------------------------- ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Only build this driver for the MPC555 based EC555 board ++#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555 ++ ++#include "ec555_serial.h" ++ ++//----------------- ++// Type definitions ++//----------------- ++typedef struct mpc555_serial_info { ++ CYG_ADDRWORD base; // The base address of the serial port ++ CYG_WORD tx_interrupt_num; // trivial ++ CYG_WORD rx_interrupt_num; // trivial ++ cyg_priority_t tx_interrupt_priority; // trivial ++ cyg_priority_t rx_interrupt_priority; // trivial ++ bool tx_interrupt_enable; // tells if the transmit interrupt may be re-enabled ++ cyg_interrupt tx_interrupt; // the tx interrupt object ++ cyg_handle_t tx_interrupt_handle; // the tx interrupt handle ++ cyg_interrupt rx_interrupt; // the rx interrupt object ++ cyg_handle_t rx_interrupt_handle; // the rx interrupt handle ++} mpc555_serial_info; ++ ++//-------------------- ++// Function prototypes ++//-------------------- ++static bool mpc555_serial_init(struct cyg_devtab_entry * tab); ++static bool mpc555_serial_putc(serial_channel * chan, unsigned char c); ++static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, ++ struct cyg_devtab_entry * sub_tab, ++ const char * name); ++static unsigned char mpc555_serial_getc(serial_channel *chan); ++static Cyg_ErrNo mpc555_serial_set_config(serial_channel *chan, cyg_uint32 key, ++ const void *xbuf, cyg_uint32 *len); ++static void mpc555_serial_start_xmit(serial_channel *chan); ++static void mpc555_serial_stop_xmit(serial_channel *chan); ++ ++// The interrupt servers ++static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); ++static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); ++static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); ++static void mpc555_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); ++ ++//------------------------------------------- ++// Register the device driver with the kernel ++//------------------------------------------- ++static SERIAL_FUNS(mpc555_serial_funs, ++ mpc555_serial_putc, ++ mpc555_serial_getc, ++ mpc555_serial_set_config, ++ mpc555_serial_start_xmit, ++ mpc555_serial_stop_xmit); ++ ++//------------------- ++// Device driver data ++//------------------- ++#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A ++static mpc555_serial_info mpc555_serial_info0 = {MPC555_SERIAL_BASE_A, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX_PRIORITY, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX_PRIORITY, ++ false}; ++#if CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BUFSIZE > 0 ++static unsigned char mpc555_serial_out_buf0[CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BUFSIZE]; ++static unsigned char mpc555_serial_in_buf0[CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BUFSIZE]; ++ ++static SERIAL_CHANNEL_USING_INTERRUPTS(mpc555_serial_channel0, ++ mpc555_serial_funs, ++ mpc555_serial_info0, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT, ++ &mpc555_serial_out_buf0[0], ++ sizeof(mpc555_serial_out_buf0), ++ &mpc555_serial_in_buf0[0], ++ sizeof(mpc555_serial_in_buf0)); ++#else ++static SERIAL_CHANNEL(mpc555_serial_channel0, ++ mpc555_serial_funs, ++ mpc555_serial_info0, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_A_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT); ++#endif ++DEVTAB_ENTRY(mpc555_serial_io0, ++ CYGDAT_IO_SERIAL_POWERPC_EC555_SERIAL_A_NAME, ++ 0, // does not depend on a lower level device driver ++ &cyg_io_serial_devio, ++ mpc555_serial_init, ++ mpc555_serial_lookup, ++ &mpc555_serial_channel0); ++#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A ++ ++#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B ++static mpc555_serial_info mpc555_serial_info1 = {MPC555_SERIAL_BASE_B, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY, ++ CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY, ++ false}; ++#if CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BUFSIZE > 0 ++static unsigned char mpc555_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BUFSIZE]; ++static unsigned char mpc555_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BUFSIZE]; ++ ++static SERIAL_CHANNEL_USING_INTERRUPTS(mpc555_serial_channel1, ++ mpc555_serial_funs, ++ mpc555_serial_info1, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT, ++ &mpc555_serial_out_buf1[0], ++ sizeof(mpc555_serial_out_buf1), ++ &mpc555_serial_in_buf1[0], ++ sizeof(mpc555_serial_in_buf1)); ++#else ++static SERIAL_CHANNEL(mpc555_serial_channel1, ++ mpc555_serial_funs, ++ mpc555_serial_info1, ++ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_EC555_SERIAL_B_BAUD), ++ CYG_SERIAL_STOP_DEFAULT, ++ CYG_SERIAL_PARITY_DEFAULT, ++ CYG_SERIAL_WORD_LENGTH_DEFAULT, ++ CYG_SERIAL_FLAGS_DEFAULT); ++#endif ++DEVTAB_ENTRY(mpc555_serial_io1, ++ CYGDAT_IO_SERIAL_POWERPC_EC555_SERIAL_B_NAME, ++ 0, // does not depend on a lower level device driver ++ &cyg_io_serial_devio, ++ mpc555_serial_init, ++ mpc555_serial_lookup, ++ &mpc555_serial_channel1); ++#endif // ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B ++ ++//----------------------------- ++// Device driver implementation ++//----------------------------- ++ ++// The arbitration isr. ++// I think this is the best place to implement it. The device driver is the only place ++// in the code where the knowledge is present about how the hardware is used ++// ++// Always check receiver interrupts. Some rom monitor might be listening to CTRL-C ++static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data) ++{ ++ cyg_uint16 status; ++ cyg_uint16 control; ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control); ++ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); ++ ++#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A // Do not waist time on unused hardware ++ if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE); ++#endif ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control); ++ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); ++ ++#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B // Do not waist time on unused hardware ++ if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC); ++// Don't waist time on unused interrupts ++// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) ++// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); ++ ++#if 0 ++ // The driver doesn't use the queue operation of the hardware (It would need different code for serial 1 and 2 ++ // since oly one port supports queue mode). So the following is not needed. ++ // Leave it there. It is easyer for later implementations to remove the comments than finding ++ // out how the hardware works again. ++ HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, control); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QTHF) && (control & CYGARC_REG_IMM_QSCI1CR_QTHFI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QBHF) && (control & CYGARC_REG_IMM_QSCI1CR_QBHFI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QTHE) && (control & CYGARC_REG_IMM_QSCI1CR_QTHEI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE); ++ if((status & CYGARC_REG_IMM_QSCI1SR_QBHE) && (control & CYGARC_REG_IMM_QSCI1CR_QBHEI)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE); ++ ++ cyg_uint16 status; ++ cyg_uint16 control; ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, status); ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, control); ++ if((status & CYGARC_REG_IMM_SPSR_SPIF) && (control & CYGARC_REG_IMM_SPCR2_SPIFIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI); ++ ++ HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, control); ++ if((status & CYGARC_REG_IMM_SPSR_MODF) && (control & CYGARC_REG_IMM_SPCR3_HMIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF); ++ ++ if((status & CYGARC_REG_IMM_SPSR_HALTA) && (control & CYGARC_REG_IMM_SPCR3_HMIE)) ++ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA); ++#endif ++ ++#endif ++ ++ return 0; ++} ++ ++//-------------------------------------------------------------------------------- ++// Internal function to actually configure the hardware to desired baud rate, etc. ++//-------------------------------------------------------------------------------- ++static bool mpc555_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config, bool init) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)(chan->dev_priv); ++ ++ cyg_addrword_t port = mpc555_chan->base; ++ cyg_uint16 baud_rate = select_baud[new_config->baud]; ++ unsigned char frame_length = 1; // The start bit ++ ++ cyg_uint16 old_isrstate; ++ cyg_uint16 sccxr; ++ ++ if(!baud_rate) ++ return false; // Invalid baud rate selected ++ ++ if((new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_7) && ++ (new_config->word_length != CYGNUM_SERIAL_WORD_LENGTH_8)) ++ return false; // Invalid word length selected ++ ++ if((new_config->parity != CYGNUM_SERIAL_PARITY_NONE) && ++ (new_config->parity != CYGNUM_SERIAL_PARITY_EVEN) && ++ (new_config->parity != CYGNUM_SERIAL_PARITY_ODD)) ++ return false; // Invalid parity selected ++ ++ if((new_config->stop != CYGNUM_SERIAL_STOP_1) && ++ (new_config->stop != CYGNUM_SERIAL_STOP_2)) ++ return false; // Invalid stop bits selected ++ ++ frame_length += select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; ++ frame_length += select_stop_bits[new_config->stop]; ++ frame_length += select_parity[new_config->parity]; ++ ++ if((frame_length != 10) && (frame_length != 11)) ++ return false; // Invalid frame format selected ++ ++ // Disable port interrupts while changing hardware ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ old_isrstate = sccxr; ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_LOOPS); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WOMS); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILT); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_WAKE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RE); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RWU); ++ old_isrstate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_SBK); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_TCIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_RIE); ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_ILIE); ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ // Set databits, stopbits and parity. ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ if(frame_length == 11) ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_M; ++ else ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_M); ++ ++ switch(new_config->parity) ++ { ++ case CYGNUM_SERIAL_PARITY_NONE: ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PE); ++ break; ++ case CYGNUM_SERIAL_PARITY_EVEN: ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; ++ sccxr &= ~((cyg_uint16)MPC555_SERIAL_SCCxR1_PT); ++ break; ++ case CYGNUM_SERIAL_PARITY_ODD: ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PE; ++ sccxr |= (cyg_uint16)MPC555_SERIAL_SCCxR1_PT; ++ break; ++ default: ++ break; ++ } ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ // Set baud rate. ++ baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_OTHR); ++ baud_rate &= ~((cyg_uint16)MPC555_SERIAL_SCCxR0_LINKBD); ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); ++ sccxr &= ~(MPC555_SERIAL_SCCxR0_SCxBR); ++ sccxr |= baud_rate; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR0, sccxr); ++ ++ // Enable the device ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= MPC555_SERIAL_SCCxR1_TE; ++ sccxr |= MPC555_SERIAL_SCCxR1_RE; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ ++ if(init) ++ { // enable the receiver interrupt ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= MPC555_SERIAL_SCCxR1_RIE; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ } ++ else // Restore the old interrupt state ++ { ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ sccxr |= old_isrstate; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCCxR1, sccxr); ++ } ++ ++ if(new_config != &chan->config) ++ chan->config = *new_config; ++ ++ return true; ++} ++ ++//-------------------------------------------------------------- ++// Function to initialize the device. Called at bootstrap time. ++//-------------------------------------------------------------- ++static hal_mpc5xx_arbitration_data arbiter; ++ ++static bool mpc555_serial_init(struct cyg_devtab_entry * tab) ++{ ++ serial_channel * chan = (serial_channel *)tab->priv; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ if(!mpc555_serial_config_port(chan, &chan->config, true)) ++ return false; ++ ++ (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices ++ if(chan->out_cbuf.len != 0) ++ { ++ arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI; ++ arbiter.data = 0; ++ arbiter.arbiter = hal_arbitration_isr_qsci; ++ ++ // Install the arbitration isr, Make sure that is is not installed twice ++ hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); ++ hal_mpc5xx_install_arbitration_isr(&arbiter); ++ ++ // Create the Tx interrupt, do not enable it yet ++ cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_num, ++ mpc555_chan->tx_interrupt_priority, ++ (cyg_addrword_t)chan, // Data item passed to interrupt handler ++ mpc555_serial_tx_ISR, ++ mpc555_serial_tx_DSR, ++ &mpc555_chan->tx_interrupt_handle, ++ &mpc555_chan->tx_interrupt); ++ cyg_drv_interrupt_attach(mpc555_chan->tx_interrupt_handle); ++ ++ // Create the Rx interrupt, this can be safely unmasked now ++ cyg_drv_interrupt_create(mpc555_chan->rx_interrupt_num, ++ mpc555_chan->rx_interrupt_priority, ++ (cyg_addrword_t)chan, ++ mpc555_serial_rx_ISR, ++ mpc555_serial_rx_DSR, ++ &mpc555_chan->rx_interrupt_handle, ++ &mpc555_chan->rx_interrupt); ++ cyg_drv_interrupt_attach(mpc555_chan->rx_interrupt_handle); ++ cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); ++ } ++ ++ return true; ++} ++ ++//---------------------------------------------------------------------- ++// This routine is called when the device is "looked" up (i.e. attached) ++//---------------------------------------------------------------------- ++static Cyg_ErrNo mpc555_serial_lookup(struct cyg_devtab_entry ** tab, ++ struct cyg_devtab_entry * sub_tab, ++ const char * name) ++{ ++ serial_channel * chan = (serial_channel *)(*tab)->priv; ++ (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices ++ ++ return ENOERR; ++} ++ ++//---------------------------------------------- ++// Send a character to the device output buffer. ++// Return 'true' if character is sent to device ++//---------------------------------------------- ++static bool mpc555_serial_putc(serial_channel * chan, unsigned char c) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ ++ cyg_uint16 scsr; ++ cyg_uint16 scdr; ++ ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ if(scsr & MPC555_SERIAL_SCxSR_TDRE) ++ { // Ok, we have space, write the character and return success ++ scdr = (cyg_uint16)c; ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ return true; ++ } ++ else ++ // We cannot write to the transmitter, return failure ++ return false; ++} ++ ++//--------------------------------------------------------------------- ++// Fetch a character from the device input buffer, waiting if necessary ++//--------------------------------------------------------------------- ++static unsigned char mpc555_serial_getc(serial_channel * chan) ++{ ++ unsigned char c; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ ++ cyg_uint16 scsr; ++ cyg_uint16 scdr; ++ ++ do { ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ } while(!(scsr & MPC555_SERIAL_SCxSR_RDRF)); ++ ++ // Ok, data is received, read it out and return ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ c = (unsigned char)scdr; ++ ++ return c; ++} ++ ++//--------------------------------------------------- ++// Set up the device characteristics; baud rate, etc. ++//--------------------------------------------------- ++static bool mpc555_serial_set_config(serial_channel * chan, cyg_uint32 key, ++ const void *xbuf, cyg_uint32 * len) ++{ ++ switch(key) { ++ case CYG_IO_SET_CONFIG_SERIAL_INFO: ++ { ++ cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; ++ if(*len < sizeof(cyg_serial_info_t)) { ++ return -EINVAL; ++ } ++ *len = sizeof(cyg_serial_info_t); ++ if(true != mpc555_serial_config_port(chan, config, false)) ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ return ENOERR; ++} ++ ++//------------------------------------- ++// Enable the transmitter on the device ++//------------------------------------- ++static void mpc555_serial_start_xmit(serial_channel * chan) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ mpc555_chan->tx_interrupt_enable = true; ++ cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); ++ ++ // No need to call xmt_char, this will generate an interrupt immediately. ++} ++ ++//-------------------------------------- ++// Disable the transmitter on the device ++//-------------------------------------- ++static void mpc555_serial_stop_xmit(serial_channel * chan) ++{ ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_dsr_lock(); ++ mpc555_chan->tx_interrupt_enable = false; ++ cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); ++ cyg_drv_dsr_unlock(); ++} ++ ++//----------------------------------------- ++// The low level transmit interrupt handler ++//----------------------------------------- ++static cyg_uint32 mpc555_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); ++ cyg_drv_interrupt_acknowledge(mpc555_chan->tx_interrupt_num); ++ ++ return CYG_ISR_CALL_DSR; // cause the DSR to run ++} ++ ++//---------------------------------------- ++// The low level receive interrupt handler ++//---------------------------------------- ++static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_num); ++ cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_num); ++ ++ return CYG_ISR_CALL_DSR; // cause the DSR to run ++} ++ ++//------------------------------------------ ++// The high level transmit interrupt handler ++//------------------------------------------ ++static void mpc555_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ ++ (chan->callbacks->xmt_char)(chan); ++ if(mpc555_chan->tx_interrupt_enable) ++ cyg_drv_interrupt_unmask(mpc555_chan->tx_interrupt_num); ++} ++ ++//----------------------------------------- ++// The high level receive interrupt handler ++//----------------------------------------- ++#define MPC555_SERIAL_SCxSR_ERRORS (MPC555_SERIAL_SCxSR_OR | \ ++ MPC555_SERIAL_SCxSR_NF | \ ++ MPC555_SERIAL_SCxSR_FE | \ ++ MPC555_SERIAL_SCxSR_PF) ++ ++static void mpc555_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ serial_channel * chan = (serial_channel *)data; ++ mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; ++ cyg_addrword_t port = mpc555_chan->base; ++ cyg_uint16 scdr; ++ cyg_uint16 scsr; ++ ++ // Allways read out the received character, in order to clear receiver flags ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxDR, scdr); ++ ++ HAL_READ_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ if(scsr & (cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS) ++ { ++ scsr &= ~((cyg_uint16)MPC555_SERIAL_SCxSR_ERRORS); ++ HAL_WRITE_UINT16(port + MPC555_SERIAL_SCxSR, scsr); ++ } ++ else ++ { ++ (chan->callbacks->rcv_char)(chan, (cyg_uint8)scdr); ++ } ++ ++ cyg_drv_interrupt_unmask(mpc555_chan->rx_interrupt_num); ++} ++ ++#endif // CYGPKG_IO_SERIAL_POWERPC_EC555 ++ ++// EOF ec555_serial_with_ints.c +diff -urNad redboot-imx-200952~/packages/devs/spi/arm/imx/current/cdl/spi.cdl redboot-imx-200952/packages/devs/spi/arm/imx/current/cdl/spi.cdl +--- redboot-imx-200952~/packages/devs/spi/arm/imx/current/cdl/spi.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/spi/arm/imx/current/cdl/spi.cdl 2010-01-26 17:33:14.682957001 +0000 +@@ -0,0 +1,101 @@ ++# ==================================================================== ++# ++# spi.cdl ++# ++# A Freescale i.MX SPI package. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. ++## Copyright (C) 2004 eCosCentric, Ltd ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Kevin Zhang ++# Contributors: ++# Date: 2008-11-14 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++ ++cdl_package CYGPKG_DEVS_IMX_SPI { ++ display "SPI driver for FSL i.MX based platforms" ++ ++ include_dir cyg/io ++ ++ cdl_option CYGHWR_DEVS_IMX_ECSPI { ++ display "ECSPI support for i.MX platforms" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates ECSPI is ++ supported on the i.MX platforms" ++ compile -library=libextras.a imx_ecspi.c ++ } ++ ++ cdl_option CYGHWR_DEVS_IMX_CSPI { ++ display "CSPI support for i.MX platforms" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates CSPI is ++ supported on the i.MX platforms" ++ compile -library=libextras.a imx_cspi.c ++ } ++ ++ cdl_option CYGHWR_DEVS_IMX_CSPI_VER_XX { ++ display "CSPI for MX21/MX27 support" ++ default_value 0 ++ description " " ++ define_proc { ++ puts $::cdl_system_header "#define IMX_CSPI_VER_XX" ++ } ++ } ++ cdl_option CYGHWR_DEVS_IMX_CSPI_VER_0_4 { ++ display "CSPI version 0.4 support for MX31" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates the SPI version ++ is 0.4" ++ define_proc { ++ puts $::cdl_system_header "#define IMX_CSPI_VER_0_4" ++ } ++ } ++ cdl_option CYGHWR_DEVS_IMX_CSPI_VER_0_7 { ++ display "CSPI version 0.7 support" ++ default_value 0 ++ description " ++ When this option is enabled, it indicates the SPI version ++ is 0.7" ++ define_proc { ++ puts $::cdl_system_header "#define IMX_CSPI_VER_0_7" ++ } ++ } ++} ++ +diff -urNad redboot-imx-200952~/packages/devs/spi/arm/imx/current/include/imx_spi.h redboot-imx-200952/packages/devs/spi/arm/imx/current/include/imx_spi.h +--- redboot-imx-200952~/packages/devs/spi/arm/imx/current/include/imx_spi.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/spi/arm/imx/current/include/imx_spi.h 2010-01-26 17:33:14.682957001 +0000 +@@ -0,0 +1,139 @@ ++#ifndef __IMX_SPI_H__ ++#define __IMX_SPI_H__ ++ ++#undef IMX_SPI_DEBUG ++//#define IMX_SPI_DEBUG ++ ++#ifdef IMX_SPI_DEBUG ++#define diag_printf1 diag_printf ++#else ++#define diag_printf1(fmt,args...) ++#endif ++ ++#define IMX_SPI_ACTIVE_HIGH 1 ++#define IMX_SPI_ACTIVE_LOW 0 ++#define SPI_RETRY_TIMES 100 ++ ++// Only for SPI master support ++struct imx_spi_dev { ++ unsigned int base; // base address of SPI module the device is connected to ++ unsigned int freq; // desired clock freq in Hz for this device ++ unsigned int ss_pol; // ss polarity: 1=active high; 0=active low ++ unsigned int ss; // slave select ++ unsigned int in_sctl; // inactive sclk ctl: 1=stay low; 0=stay high ++ unsigned int in_dctl; // inactive data ctl: 1=stay low; 0=stay high ++ unsigned int ssctl; // single burst mode vs multiple: 0=single; 1=multi ++ unsigned int sclkpol; // sclk polarity: active high=0; active low=1 ++ unsigned int sclkpha; // sclk phase: 0=phase 0; 1=phase1 ++ unsigned int fifo_sz; // fifo size in bytes for either tx or rx. Don't add them up! ++ unsigned int us_delay; // us delay in each xfer ++ void *reg; // pointer to a set of SPI registers ++}; ++ ++struct spi_v2_3_reg { ++ unsigned int ctrl_reg; ++ unsigned int cfg_reg; ++}; ++ ++int imx_ecspi_init(struct imx_spi_dev *dev); ++ ++// transfer up to fifo bytes data via spi. The data transferred is the sum of both the tx and rx ++int imx_ecspi_xfer( ++ struct imx_spi_dev *dev, // spi device pointer ++ unsigned char *tx_buf, // tx buffer (has to be 4-byte aligned) ++ unsigned char *rx_buf, // rx buffer (has to be 4-byte aligned) ++ int burst_bytes // total number of bytes in one burst or xfer ++ ); ++ ++// ++int imx_cspi_init (struct imx_spi_dev *dev); ++ ++// transfer up to fifo bytes data via spi. The data transferred is the sum of both the tx and rx ++int imx_cspi_xfer ( ++ struct imx_spi_dev *dev, // spi device pointer ++ unsigned char *tx_buf, // tx buffer (has to be 4-byte aligned) ++ unsigned char *rx_buf, // rx buffer (has to be 4-byte aligned) ++ int burst_bytes // total number of bytes in one burst or xfer ++ ); ++ ++typedef int imx_spi_init_func_t(struct imx_spi_dev *); ++typedef int imx_spi_xfer_func_t(struct imx_spi_dev *, unsigned char *, unsigned char *, int); ++ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write); ++ ++void io_cfg_spi(struct imx_spi_dev *dev); ++ ++#if defined(IMX_CSPI_VER_0_4) ++#define SPI_CTRL_EN (1 << 0) ++#define SPI_CTRL_MODE (1 << 1) ++#define SPI_CTRL_REG_XCH_BIT (1 << 2) ++#define SPI_CTRL_SSPOL (1 << 7) ++#define SPI_CTRL_SSPOL_OFF (7) ++#define SPI_CTRL_SSCTL (1 << 6) ++#define SPI_CTRL_SSCTL_OFF (6) ++#define SPI_CTRL_SCLK_POL (1 << 4) ++#define SPI_CTRL_SCLK_POL_OFF (4) ++#define SPI_CTRL_SCLK_PHA (1 << 5) ++#define SPI_CTRL_SCLK_PHA_OFF (5) ++#define SPI_CTRL_SS_OFF (24) ++#define SPI_CTRL_SS_MASK (3 << 24) ++#define SPI_CTRL_DATA_OFF (16) ++#define SPI_CTRL_DATA_MASK (7 << 16) ++#define SPI_CTRL_BURST_OFF (8) ++#define SPI_CTRL_BURST_MASK (0x1F << 8) ++ ++#define SPI_INT_STAT_REG_OFF 0x14 ++#define SPI_INT_STAT_TC (1 << 8) ++ ++#elif defined(IMX_CSPI_VER_0_7) ++#define SPI_CTRL_EN (1 << 0) ++#define SPI_CTRL_MODE (1 << 1) ++#define SPI_CTRL_REG_XCH_BIT (1 << 2) ++#define SPI_CTRL_SSPOL (1 << 7) ++#define SPI_CTRL_SSPOL_OFF (7) ++#define SPI_CTRL_SSCTL (1 << 6) ++#define SPI_CTRL_SSCTL_OFF (6) ++#define SPI_CTRL_SCLK_POL (1 << 4) ++#define SPI_CTRL_SCLK_POL_OFF (4) ++#define SPI_CTRL_SCLK_PHA (1 << 5) ++#define SPI_CTRL_SCLK_PHA_OFF (5) ++#define SPI_CTRL_SS_OFF (12) ++#define SPI_CTRL_SS_MASK (3 << 12) ++#define SPI_CTRL_DATA_OFF (16) ++#define SPI_CTRL_DATA_MASK (7 << 16) ++#define SPI_CTRL_BURST_OFF (20) ++#define SPI_CTRL_BURST_MASK (0xFFF << 20) ++ ++#define SPI_INT_STAT_REG_OFF 0x14 ++#define SPI_INT_STAT_TC (1 << 7) ++ ++#elif defined(IMX_CSPI_VER_XX) ++#define SPI_CTRL_EN (1 << 10) ++#define SPI_CTRL_MODE (1 << 11) ++#define SPI_CTRL_REG_XCH_BIT (1 << 9) ++#define SPI_CTRL_SSPOL (1 << 8) ++#define SPI_CTRL_SSPOL_OFF (8) ++#define SPI_CTRL_SSCTL (1 << 7) ++#define SPI_CTRL_SSCTL_OFF (7) ++#define SPI_CTRL_SCLK_POL (1 << 5) ++#define SPI_CTRL_SCLK_POL_OFF (5) ++#define SPI_CTRL_SCLK_PHA (1 << 6) ++#define SPI_CTRL_SCLK_PHA_OFF (6) ++#define SPI_CTRL_SS_OFF (19) ++#define SPI_CTRL_SS_MASK (3 << 19) ++#define SPI_CTRL_DATA_OFF (14) ++#define SPI_CTRL_DATA_MASK (0x1F << 14) ++#define SPI_CTRL_BURST_OFF (0) ++#define SPI_CTRL_BURST_MASK (0x1F << 0) ++ ++#define SPI_INT_STAT_REG_OFF 0xC ++#define SPI_INT_STAT_TC (1 << 3) ++ ++#endif ++ ++#define REV_ATLAS_LITE_1_0 0x8 ++#define REV_ATLAS_LITE_1_1 0x9 ++#define REV_ATLAS_LITE_2_0 0x10 ++#define REV_ATLAS_LITE_2_1 0x11 ++ ++#endif // __IMX_SPI_H__ +diff -urNad redboot-imx-200952~/packages/devs/spi/arm/imx/current/src/imx_cspi.c redboot-imx-200952/packages/devs/spi/arm/imx/current/src/imx_cspi.c +--- redboot-imx-200952~/packages/devs/spi/arm/imx/current/src/imx_cspi.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/spi/arm/imx/current/src/imx_cspi.c 2010-01-26 17:33:14.682957001 +0000 +@@ -0,0 +1,303 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/*! ++ * Initialization function for a spi slave device. It must be called BEFORE ++ * any spi operations. The SPI module will be -disabled- after this call. ++ */ ++int imx_cspi_init(struct imx_spi_dev *dev) ++{ ++ unsigned int clk_src = get_peri_clock(dev->base); ++ unsigned int div = 0, i, reg_ctrl; ++ struct spi_v2_3_reg *reg = (struct spi_v2_3_reg *)dev->reg; ++ int lim = 0; ++#if defined(IMX_CSPI_VER_0_7) || defined(IMX_CSPI_VER_0_4) ++ unsigned int baud_rate_div[] = {4, 8, 16, 32, 64, 128, 256, 512}; ++#elif defined(IMX_CSPI_VER_XX) ++ unsigned int baud_rate_div[] = { ++ 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 256, 384, 512, ++ }; ++#else ++#error No SPI version defined ++#endif ++ ++ lim = sizeof(baud_rate_div) / sizeof(unsigned int); ++ if (dev->freq == 0) { ++ diag_printf("Error: desired clock is 0\n"); ++ return -1; ++ } ++ // iomux config ++ io_cfg_spi(dev); ++ ++ reg_ctrl = readl(dev->base + 0x8); ++ // reset the spi ++ writel(0, dev->base + 0x8); ++ writel(reg_ctrl | SPI_CTRL_EN, dev->base + 0x8); ++ ++ // control register setup ++ if (clk_src > dev->freq) { ++ div = clk_src / dev->freq; ++ ++ for (i = 0; i < lim; i++) { ++ if (div <= baud_rate_div[i]) { ++ break; ++ } ++ } ++ } ++ ++ diag_printf1("div = %d\n", baud_rate_div[i]); ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_SS_MASK) | (dev->ss << SPI_CTRL_SS_OFF); ++#if defined(IMX_CSPI_VER_XX) ++ i += 1; ++#endif ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_DATA_MASK) | (i << SPI_CTRL_DATA_OFF); ++ reg_ctrl |= SPI_CTRL_MODE; // always set to master mode !!!! ++ reg_ctrl &= ~SPI_CTRL_EN; // disable spi ++ ++ // configuration register setup ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_SSPOL) | (dev->ss_pol << SPI_CTRL_SSPOL_OFF); ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_SSCTL) | (dev->ssctl << SPI_CTRL_SSCTL_OFF); ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_SCLK_POL) | (dev->sclkpol << SPI_CTRL_SCLK_POL_OFF); ++ reg_ctrl = (reg_ctrl & ~SPI_CTRL_SCLK_PHA) | (dev->sclkpha << SPI_CTRL_SCLK_PHA_OFF); ++ ++ diag_printf1("reg_ctrl = 0x%x\n", reg_ctrl); ++ writel(reg_ctrl, dev->base + 0x8); ++ ++ // save control register ++ reg->ctrl_reg = reg_ctrl; ++ ++ // clear interrupt reg ++ writel(0, dev->base + 0xC); ++ writel(SPI_INT_STAT_TC, dev->base + SPI_INT_STAT_REG_OFF); ++ return 0; ++} ++ ++/*! ++ * This function should only be called after the imx_spi_init_xxx(). ++ * It sets up the spi module according to the initialized value and then ++ * enables the SPI module. This function is called by the xfer function. ++ * ++ * Note: If one wants to change the SPI parameters such as clock, the ++ * imx_spi_init_xxx() needs to be called again. ++ */ ++static void imx_cspi_start(struct imx_spi_dev *dev, ++ struct spi_v2_3_reg *reg, int len) ++{ ++ if (reg->ctrl_reg == 0) { ++ diag_printf("Error: spi(base=0x%x) has not been initialized yet\n", ++ dev->base); ++ return; ++ } ++ // iomux config ++ io_cfg_spi(dev); ++ reg->ctrl_reg = (reg->ctrl_reg & ~SPI_CTRL_BURST_MASK) | ((len - 1) << SPI_CTRL_BURST_OFF); ++ writel(reg->ctrl_reg | SPI_CTRL_EN, dev->base + 0x8); ++ diag_printf1("ctrl_reg=0x%x, cfg_reg=0x%x\n", ++ readl(dev->base + 0x8), readl(dev->base + 0xC)); ++} ++ ++/*! ++ * Stop the SPI module that the slave device is connected to. ++ */ ++static void imx_cspi_stop(struct imx_spi_dev *dev) ++{ ++ writel(0, dev->base + 0x8); ++} ++ ++/*! ++ * Transfer up to burst_bytes bytes data via spi. The amount of data ++ * is the sum of both the tx and rx. ++ * After this call, the SPI module that the slave is connected to will ++ * be -disabled- again. ++ */ ++int imx_cspi_xfer ( ++ struct imx_spi_dev *dev, // spi device pointer ++ unsigned char *tx_buf, // tx buffer (has to be 4-byte aligned) ++ unsigned char *rx_buf, // rx buffer (has to be 4-byte aligned) ++ int burst_bits // total number of bits in one burst (or xfer) ++ ) ++{ ++ int val = SPI_RETRY_TIMES; ++ unsigned int *p_buf; ++ unsigned int reg; ++ int len, ret_val = 0; ++ int burst_bytes = burst_bits / 8; ++ ++ /* Account for rounding of non-byte aligned burst sizes */ ++ if ((burst_bits % 8) != 0) ++ burst_bytes++; ++ if (burst_bytes > dev->fifo_sz) { ++ diag_printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", ++ dev->fifo_sz, burst_bytes); ++ return -1; ++ } ++ ++ imx_cspi_start(dev, dev->reg, burst_bits); ++ ++ // move data to the tx fifo ++ for (p_buf = (unsigned int *)tx_buf, len = burst_bytes; len > 0; ++ p_buf++, len -= 4) { ++ writel(*p_buf, dev->base + 0x4); ++ } ++ reg = readl(dev->base + 0x8); ++ reg |= SPI_CTRL_REG_XCH_BIT; // set xch bit ++ diag_printf1("control reg = 0x%08x\n", reg); ++ writel(reg, dev->base + 0x8); ++ ++ // poll on the TC bit (transfer complete) ++ while ((val-- > 0) && (((reg = readl(dev->base + SPI_INT_STAT_REG_OFF)) & SPI_INT_STAT_TC) == 0)) { ++ if (dev->us_delay != 0) { ++ hal_delay_us(dev->us_delay); ++ } ++ } ++ ++ // clear the TC bit ++ writel(reg | SPI_INT_STAT_TC, dev->base + SPI_INT_STAT_REG_OFF); ++ if (val == 0) { ++ diag_printf("Error: re-tried %d times without response. Give up\n", SPI_RETRY_TIMES); ++ ret_val = -1; ++ goto error; ++ } ++ ++ // move data in the rx buf ++ for (p_buf = (unsigned int *)rx_buf, len = burst_bytes; len > 0; ++ p_buf++, len -= 4) { ++ *p_buf = readl(dev->base + 0x0); ++ } ++error: ++ imx_cspi_stop(dev); ++ return ret_val; ++} ++ ++#ifdef PMIC_SPI_BASE ++extern imx_spi_init_func_t *spi_pmic_init; ++extern imx_spi_xfer_func_t *spi_pmic_xfer; ++extern struct imx_spi_dev imx_spi_pmic; ++ ++static void mxc_pmic_init(void) ++{ ++ volatile unsigned int rev_id; ++ unsigned int ctrl; ++ ++ spi_pmic_init(&imx_spi_pmic); ++ rev_id = pmic_reg(7, 0, 0); ++ diag_printf("PMIC ID: 0x%08x [Rev: ", rev_id); ++ switch (rev_id & 0x1F) { ++ case 0x1: ++ diag_printf("1.0"); ++ break; ++ case 0x9: ++ diag_printf("1.1"); ++ break; ++ case 0xA: ++ diag_printf("1.2"); ++ break; ++ case 0x10: ++ diag_printf("2.0"); ++ break; ++ case 0x11: ++ diag_printf("2.1"); ++ break; ++ case 0x18: ++ diag_printf("3.0"); ++ break; ++ case 0x19: ++ diag_printf("3.1"); ++ break; ++ case 0x1A: ++ diag_printf("3.2"); ++ break; ++ case 0x2: ++ diag_printf("3.2A"); ++ break; ++ case 0x1B: ++ diag_printf("3.3"); ++ break; ++ case 0x1D: ++ diag_printf("3.5"); ++ break; ++ default: ++ diag_printf("unknown"); ++ break; ++ } ++ diag_printf("]\n"); ++} ++ ++RedBoot_init(mxc_pmic_init, RedBoot_INIT_PRIO(100)); ++ ++static void do_pmic(int argc, char *argv[]); ++RedBoot_cmd("pmic", ++ "Read/Write internal PMIC register", ++ " [value to be written]", ++ do_pmic ++ ); ++ ++static void do_pmic(int argc,char *argv[]) ++{ ++ unsigned int reg, temp, val = 0, write = 0; ++ ++ if (argc == 1) { ++ diag_printf("\tRead: pmic \n"); ++ diag_printf("\tWrite: pmic \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)®, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ if (argc == 3) { ++ if (!parse_num(*(&argv[2]), (unsigned long *)&val, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ write = 1; ++ } ++ ++ temp = pmic_reg(reg, val, write); ++ ++ diag_printf("\tval: 0x%08x\n\n", temp); ++} ++ ++static unsigned int pmic_tx, pmic_rx; ++/*! ++ * To read/write to a PMIC register. For write, it does another read for the ++ * actual register value. ++ * ++ * @param reg register number inside the PMIC ++ * @param val data to be written to the register; don't care for read ++ * @param write 0 for read; 1 for write ++ * ++ * @return the actual data in the PMIC register ++ */ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ unsigned int temp; ++ ++ if (reg > 63 || write > 1 ) { ++ diag_printf(" = %d is invalide. Should be less then 63\n", reg); ++ return 0; ++ } ++ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); ++ diag_printf1("reg=0x%x, val=0x%08x\n", reg, val); ++ ++ spi_pmic_xfer(&imx_spi_pmic, (unsigned char *)&pmic_tx, ++ (unsigned char *)&pmic_rx, (4 * 8)); ++ ++ if (write) { ++ pmic_tx &= ~(1 << 31); ++ spi_pmic_xfer(&imx_spi_pmic, (unsigned char *)&pmic_tx, ++ (unsigned char *)&pmic_rx, (4 * 8)); ++ } ++ ++ return pmic_rx; ++} ++#endif // PMIC_SPI_BASE +diff -urNad redboot-imx-200952~/packages/devs/spi/arm/imx/current/src/imx_ecspi.c redboot-imx-200952/packages/devs/spi/arm/imx/current/src/imx_ecspi.c +--- redboot-imx-200952~/packages/devs/spi/arm/imx/current/src/imx_ecspi.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/spi/arm/imx/current/src/imx_ecspi.c 2010-01-26 17:33:14.692963002 +0000 +@@ -0,0 +1,315 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/*! ++ * Initialization function for a spi slave device. It must be called BEFORE ++ * any spi operations. The SPI module will be -disabled- after this call. ++ */ ++int imx_ecspi_init(struct imx_spi_dev *dev) ++{ ++ unsigned int clk_src = get_peri_clock(dev->base); ++ unsigned int pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; ++ struct spi_v2_3_reg *reg = (struct spi_v2_3_reg *)dev->reg; ++ ++ if (dev->freq == 0) { ++ diag_printf("Error: desired clock is 0\n"); ++ return -1; ++ } ++ // iomux config ++ io_cfg_spi(dev); ++ ++ reg_ctrl = readl(dev->base + 0x8); ++ // reset the spi ++ writel(0, dev->base + 0x8); ++ writel(reg_ctrl | 0x1, dev->base + 0x8); ++ ++ // control register setup ++ if (clk_src > dev->freq) { ++ pre_div = clk_src / dev->freq; ++ if (pre_div > 16) { ++ post_div = pre_div / 16; ++ pre_div = 15; ++ } ++ if (post_div != 0) { ++ for (i = 0; i < 16; i++) { ++ if ((1 << i) >= post_div) ++ break; ++ } ++ if (i == 16) { ++ diag_printf("Error: no divider can meet the freq: %d\n", ++ dev->freq); ++ return -1; ++ } ++ post_div = i; ++ } ++ } ++ diag_printf1("pre_div = %d, post_div=%d\n", pre_div, post_div); ++ reg_ctrl = (reg_ctrl & ~(3 << 18)) | dev->ss << 18; ++ reg_ctrl = (reg_ctrl & ~(0xF << 12)) | pre_div << 12; ++ reg_ctrl = (reg_ctrl & ~(0xF << 8)) | post_div << 8; ++ reg_ctrl |= 1 << (dev->ss + 4); // always set to master mode !!!! ++ reg_ctrl &= ~0x1; // disable spi ++ ++ reg_config = readl(dev->base + 0xC); ++ // configuration register setup ++ reg_config = (reg_config & ~(1 << ((dev->ss + 12)))) | ++ (dev->ss_pol << (dev->ss + 12)); ++ reg_config = (reg_config & ~(1 << ((dev->ss + 20)))) | ++ (dev->in_sctl << (dev->ss + 20)); ++ reg_config = (reg_config & ~(1 << ((dev->ss + 16)))) | ++ (dev->in_dctl << (dev->ss + 16)); ++ reg_config = (reg_config & ~(1 << ((dev->ss + 8)))) | ++ (dev->ssctl << (dev->ss + 8)); ++ reg_config = (reg_config & ~(1 << ((dev->ss + 4)))) | ++ (dev->sclkpol << (dev->ss + 4)); ++ reg_config = (reg_config & ~(1 << ((dev->ss + 0)))) | ++ (dev->sclkpha << (dev->ss + 0)); ++ ++ diag_printf1("reg_ctrl = 0x%x\n", reg_ctrl); ++ writel(reg_ctrl, dev->base + 0x8); ++ diag_printf1("reg_config = 0x%x\n", reg_config); ++ writel(reg_config, dev->base + 0xC); ++ // save config register and control register ++ reg->cfg_reg = reg_config; ++ reg->ctrl_reg = reg_ctrl; ++ ++ // clear interrupt reg ++ writel(0, dev->base + 0x10); ++ writel(3 << 6, dev->base + 0x18); ++ ++ return 0; ++} ++ ++/*! ++ * This function should only be called after the imx_spi_init_xxx(). ++ * It sets up the spi module according to the initialized value and then ++ * enables the SPI module. This function is called by the xfer function. ++ * ++ * Note: If one wants to change the SPI parameters such as clock, the ++ * imx_spi_init_xxx() needs to be called again. ++ */ ++static void imx_ecspi_start(struct imx_spi_dev *dev, ++ struct spi_v2_3_reg *reg, int len) ++{ ++ if (reg->ctrl_reg == 0) { ++ diag_printf("Error: spi(base=0x%x) has not been initialized yet\n", ++ dev->base); ++ return; ++ } ++ // iomux config ++ io_cfg_spi(dev); ++ reg->ctrl_reg = (reg->ctrl_reg & ~0xFFF00000) | ((len - 1) << 20); ++ writel(reg->ctrl_reg | 0x1, dev->base + 0x8); ++ writel(reg->cfg_reg, dev->base + 0xC); ++ diag_printf1("ctrl_reg=0x%x, cfg_reg=0x%x\n", ++ readl(dev->base + 0x8), readl(dev->base + 0xC)); ++} ++ ++/*! ++ * Stop the SPI module that the slave device is connected to. ++ */ ++static void imx_ecspi_stop(struct imx_spi_dev *dev) ++{ ++ writel(0, dev->base + 0x8); ++} ++ ++/*! ++ * Transfer up to burst_bytes bytes data via spi. The amount of data ++ * is the sum of both the tx and rx. ++ * After this call, the SPI module that the slave is connected to will ++ * be -disabled- again. ++ */ ++int imx_ecspi_xfer( ++ struct imx_spi_dev *dev, // spi device pointer ++ unsigned char *tx_buf, // tx buffer (has to be 4-byte aligned) ++ unsigned char *rx_buf, // rx buffer (has to be 4-byte aligned) ++ int burst_bits // total number of bits in one burst (or xfer) ++ ) ++{ ++ int val = SPI_RETRY_TIMES; ++ unsigned int *p_buf; ++ unsigned int reg; ++ int len, ret_val = 0; ++ int burst_bytes = burst_bits / 8; ++ ++ /* Account for rounding of non-byte aligned burst sizes */ ++ if ((burst_bits % 8) != 0) ++ burst_bytes++; ++ if (burst_bytes > dev->fifo_sz) { ++ diag_printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", ++ dev->fifo_sz, burst_bytes); ++ return -1; ++ } ++ ++ imx_ecspi_start(dev, dev->reg, burst_bits); ++ ++ // move data to the tx fifo ++ for (p_buf = (unsigned int *)tx_buf, len = burst_bytes; len > 0; ++ p_buf++, len -= 4) { ++ writel(*p_buf, dev->base + 0x4); ++ } ++ reg = readl(dev->base + 0x8); ++ reg |= (1 << 2); // set xch bit ++ diag_printf1("control reg = 0x%08x\n", reg); ++ writel(reg, dev->base + 0x8); ++ ++ // poll on the TC bit (transfer complete) ++ while ((val-- > 0) && (readl(dev->base + 0x18) & (1 << 7)) == 0) { ++ if (dev->us_delay != 0) { ++ hal_delay_us(dev->us_delay); ++ } ++ } ++ ++ // clear the TC bit ++ writel(3 << 6, dev->base + 0x18); ++ if (val == 0) { ++ diag_printf("Error: re-tried %d times without response. Give up\n", SPI_RETRY_TIMES); ++ ret_val = -1; ++ goto error; ++ } ++ ++ // move data in the rx buf ++ for (p_buf = (unsigned int *)rx_buf, len = burst_bytes; len > 0; ++ p_buf++, len -= 4) { ++ *p_buf = readl(dev->base + 0x0); ++ } ++error: ++ imx_ecspi_stop(dev); ++ return ret_val; ++} ++ ++#ifdef PMIC_SPI_BASE ++extern imx_spi_init_func_t *spi_pmic_init; ++extern imx_spi_xfer_func_t *spi_pmic_xfer; ++extern struct imx_spi_dev imx_spi_pmic; ++ ++static void show_pmic_info(void) ++{ ++ volatile unsigned int rev_id; ++ ++ spi_pmic_init(&imx_spi_pmic); ++ rev_id = pmic_reg(7, 0, 0); ++ diag_printf("PMIC ID: 0x%08x [Rev: ", rev_id); ++ switch (rev_id & 0x1F) { ++ case 0x1: ++ diag_printf("1.0"); ++ break; ++ case 0x9: ++ diag_printf("1.1"); ++ break; ++ case 0xA: ++ diag_printf("1.2"); ++ break; ++ case 0x10: ++ if (((rev_id >> 9) & 0x3) == 0) { ++ diag_printf("2.0"); ++ } else { ++ diag_printf("2.0a"); ++ } ++ break; ++ case 0x11: ++ diag_printf("2.1"); ++ break; ++ case 0x18: ++ diag_printf("3.0"); ++ break; ++ case 0x19: ++ diag_printf("3.1"); ++ break; ++ case 0x1A: ++ diag_printf("3.2"); ++ break; ++ case 0x2: ++ diag_printf("3.2A"); ++ break; ++ case 0x1B: ++ diag_printf("3.3"); ++ break; ++ case 0x1D: ++ diag_printf("3.5"); ++ break; ++ default: ++ diag_printf("unknown"); ++ break; ++ } ++ diag_printf("]\n"); ++} ++ ++RedBoot_init(show_pmic_info, RedBoot_INIT_PRIO(100)); ++ ++static void do_pmic(int argc, char *argv[]); ++RedBoot_cmd("pmic", ++ "Read/Write internal PMIC register", ++ " [value to be written]", ++ do_pmic ++ ); ++ ++static void do_pmic(int argc, char *argv[]) ++{ ++ unsigned int reg, temp, val = 0, write = 0; ++ ++ if (argc == 1) { ++ diag_printf("\tRead: pmic \n"); ++ diag_printf("\tWrite: pmic \n"); ++ return; ++ } ++ ++ if (!parse_num(*(&argv[1]), (unsigned long *)®, &argv[1], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ ++ if (argc == 3) { ++ if (!parse_num(*(&argv[2]), (unsigned long *)&val, &argv[2], ":")) { ++ diag_printf("Error: Invalid parameter\n"); ++ return; ++ } ++ write = 1; ++ } ++ ++ spi_pmic_init(&imx_spi_pmic); ++ temp = pmic_reg(reg, val, write); ++ ++ diag_printf("\tval: 0x%08x\n\n", temp); ++} ++ ++static unsigned int pmic_tx, pmic_rx; ++/*! ++ * To read/write to a PMIC register. For write, it does another read for the ++ * actual register value. ++ * ++ * @param reg register number inside the PMIC ++ * @param val data to be written to the register; don't care for read ++ * @param write 0 for read; 1 for write ++ * ++ * @return the actual data in the PMIC register ++ */ ++unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ if (reg > 63 || write > 1 ) { ++ diag_printf(" = %d is invalide. Should be less then 63\n", reg); ++ return 0; ++ } ++ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); ++ diag_printf1("reg=0x%x, val=0x%08x\n", reg, pmic_tx); ++ ++ spi_pmic_xfer(&imx_spi_pmic, (unsigned char *)&pmic_tx, ++ (unsigned char *)&pmic_rx, (4 * 8)); ++ ++ if (write) { ++ pmic_tx &= ~(1 << 31); ++ spi_pmic_xfer(&imx_spi_pmic, (unsigned char *)&pmic_tx, ++ (unsigned char *)&pmic_rx, (4 * 8)); ++ } ++ ++ return pmic_rx; ++} ++#endif // PMIC_SPI_BASE ++ +diff -urNad redboot-imx-200952~/packages/devs/usb/imx/current/cdl/usbs_imx.cdl redboot-imx-200952/packages/devs/usb/imx/current/cdl/usbs_imx.cdl +--- redboot-imx-200952~/packages/devs/usb/imx/current/cdl/usbs_imx.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/usb/imx/current/cdl/usbs_imx.cdl 2010-01-26 17:33:14.742959005 +0000 +@@ -0,0 +1,107 @@ ++# ==================================================================== ++# ++# usbs_mx37.cdl ++# ++# MX37 USB OTG Device Mode support. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++# This file is a part of Diagnosis Package based on eCos for Freescale i.MX ++# Family microprocessor. ++## Copyright (C) 2008 Freescale Semiconductor, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): fisherz ++# Original data: fisherz ++# Contributors: ++# Date: 2008-10-16 ++# Comment: Porting to MX51 ++# ++#####DESCRIPTIONEND#### ++# ==================================================================== ++cdl_package CYGPKG_DEVS_USB_IMX_OTG { ++ display "Freescale i.MX51 or i.MX37 USB OTG Device Driver" ++ include_dir "cyg/io/usb" ++ parent CYGPKG_USB ++ implements CYGHWR_IO_USB_SLAVE ++ ++ # Make sure that we are running on the right hardware. ++ requires CYGPKG_HAL_ARM ++# requires CYGPKG_HAL_ARM_MX51 ++# requires CYGPKG_HAL_ARM_MX51_3STACK ++ requires CYGPKG_IO_USB ++ requires CYGPKG_IO_USB_SLAVE ++ compile usbs_imx.c ++ ++ description " ++ The on-chip USB OTG core on the MX51 or MX37 works as a USB ++ device controller, facilitating the use of this processor ++ in USB peripherals. This package provides a suitable eCos ++ device driver." ++ ++ cdl_option CYGHWR_USB_DEVS_MX51_OTG { ++ display "i.MX51 USB OTG" ++ flavor bool ++ default_value 0 ++ description " ++ i.MX51 is the default OTG device for this package" ++ } ++ ++ cdl_option CYGHWR_USB_DEVS_MX37_OTG { ++ display "i.MX37 USB OTG" ++ flavor bool ++ default_value 0 ++ description " ++ i.MX37 is not the default OTG device for this package" ++ } ++ ++ cdl_option CYGHWR_MXC_USB_BUFFER_USE_IRAM { ++ display "Determine where the USB buffer is" ++ flavor bool ++ default_value 1 ++ description " ++ USB buffer is defaultly in the internal RAM for better performance" ++ } ++ ++ cdl_option CYGHWR_IMX_USB_DOWNLOAD_SUPPORT { ++ display "USB Download for redboot is supported, i.MX OTG works in poll mode" ++ flavor bool ++ default_value 0 ++ description " ++ USB Download function is an add-value function for redboot, and USB OTG will work ++ under poll mode" ++ } ++ ++} ++ ++ +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/devs/usb/imx/current/include/usbs_imx.h redboot-imx-200952/packages/devs/usb/imx/current/include/usbs_imx.h +--- redboot-imx-200952~/packages/devs/usb/imx/current/include/usbs_imx.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/usb/imx/current/include/usbs_imx.h 2010-01-26 17:33:14.752962131 +0000 +@@ -0,0 +1,837 @@ ++//========================================================================== ++// ++// include/usbs_imx.h ++// ++// The interface exported by the i.MX37 or i.MX51 USB OTG device driver ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is a part of Diagnosis Package based on eCos for Freescale i.MX ++// Family microprocessor. ++// Copyright (C) 2008 Freescale Semiconductor, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): fisherz ++// Contributors: fisherz ++// Date: 2008-07-22 ++// Purpose: ++// ++//####DESCRIPTIONEND#### ++//========================================================================== ++#ifndef CYGONCE_USBS_IMX_H ++#define CYGONCE_USBS_IMX_H ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++//#define USBS_DEBUG 0 ++ ++/* ++ * This function is an exported API for application to initialize ++ * MX37 or MX51 USB OTG in device mode from hardware to driver. ++ */ ++void usbs_imx_otg_device_init(void); ++void usbs_imx_otg_device_deinit(void); ++#if defined(CYGBLD_IMX_USB_DOWNLOAD_SUPPORT) ++void usbs_imx_otg_download(unsigned char * buffer, unsigned int length); ++#endif ++/* ++ * The i.MX37 and 51 family comes with on-chip USB OTG support. This ++ * provides three endpoints. Endpoint 0 can only be used for control ++ * messages. Endpoints 1 and 2 can only be used for bulk transfers, ++ * host->slave for endpoint 1 and slave->host for endpoint 2. ++ */ ++extern usbs_control_endpoint usbs_imx_otg_ep0; ++extern usbs_rx_endpoint usbs_imx_otg_ep1; ++extern usbs_tx_endpoint usbs_imx_otg_ep2; ++ ++ ++/************************************************************************/ ++#define BUFFER_SIZE 0x800 ++ ++#if defined(CYGHWR_USB_DEVS_MX37_OTG) ++#define USB_BASE_ADDRESS 0xC3FD4000 ++#define MX37_IRQ_USB_SERVICE_REQUEST 18 //i.MX37 USB OTG Interrupt ++#define MX37_IRQ_USB_PRIORITY 99 //i.MX37 USB Interrupt Priority ++#define IMX_IRQ_USB_DEV_SERVICE_REQUEST MX37_IRQ_USB_SERVICE_REQUEST ++#define IMX_IRQ_USB_DEV_PRIORITY MX37_IRQ_USB_PRIORITY ++ ++#define CCM_BASE_ADDR 0xE3F8C000 ++#define CCM_CSCMR1_OFFSET 0x34 ++#define CCM_CSCMR1 (CCM_BASE_ADDR + CCM_CSCMR1_OFFSET) ++#define REGVAL_CCM_CSCMR1 (*((volatile cyg_uint32*)CCM_CSCMR1)) ++#define USB_MX37_SET_PHY_CLK_24MHZ() (REGVAL_CCM_CSCMR1&=(~((0x1) <<26))) ++ ++#define USB_IMX_SET_TD_OFFSET(offset,num) offset=num ++#endif ++ ++ ++#if defined(CYGHWR_USB_DEVS_MX51_OTG) ++#define USB_BASE_ADDRESS 0x73F80000 ++#define MX51_IRQ_USB_SERVICE_REQUEST 18 //i.MX51 USB OTG Interrupt ++#define MX51_IRQ_USB_PRIORITY 99 //i.MX51 USB Interrupt Priority ++#define IMX_IRQ_USB_DEV_SERVICE_REQUEST MX51_IRQ_USB_SERVICE_REQUEST ++#define IMX_IRQ_USB_DEV_PRIORITY MX51_IRQ_USB_PRIORITY ++ ++#define USB_OTG_BASE_ADDR ((cyg_uint32)USB_BASE_ADDRESS + 0x000) ++#define USB_H1_BASE_ADDR ((cyg_uint32)USB_BASE_ADDRESS + 0x200) ++#define USB_H2_BASE_ADDR ((cyg_uint32)USB_BASE_ADDRESS + 0x400) ++#define USB_H3_BASE_ADDR ((cyg_uint32)USB_BASE_ADDRESS + 0x400) ++#define USB_CONTROL_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x800) ++#define USB_OTG_MIRROR_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x804) ++#define USB_PHY_CTRL_0_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x808) ++#define USB_PHY_CTRL_1_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x80c) ++#define USB_CTRL_1_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x810) ++ ++#define CCM_BASE_ADDR 0x73FD4000 ++#define CCM_CSCMR1_OFFSET 0x1C ++#define CCM_CSCDR1_OFFSET 0x24 ++#define CCM_CSCMR1 (CCM_BASE_ADDR + CCM_CSCMR1_OFFSET) ++#define CCM_CSCDR1 (CCM_BASE_ADDR + CCM_CSCDR1_OFFSET) ++#define CCM_CSCMR1_REGVAL (*(cyg_uint32 *)(CCM_BASE_ADDR + CCM_CSCMR1_OFFSET)) ++#define CCM_CSCDR1_REGVAL (*(cyg_uint32 *)(CCM_BASE_ADDR + CCM_CSCDR1_OFFSET)) ++/* CSCMR1 register */ ++#define CSCMR1_USBOH3_PHY_CLK_SEL_MASK 0x04000000 ++#define CSCMR1_USBOH3_PHY_CLK_SEL_VALUE 0x04000000 ++#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 ++#define CSCMR1_USBOH3_CLK_SEL_VALUE 0x00400000 ++/*CSCDR1 register config*/ ++#define CSCDR1_USBOH3_CLK_PRED_SEL_MASK 0x00000700 ++#define CSCDR1_USBOH3_CLK_PRED_SEL_VALUE 0x00000400 /* divide by 5 */ ++#define CSCDR1_USBOH3_CLK_PODF_SEL_MASK 0x000000C0 ++#define CSCDR1_USBOH3_CLK_PODF_SEL_VALUE 0x00000040 /* divide by 2 */ ++/* CDCDR register */ ++#define CDCDR_USB_CLK_PREDF_MASK 0x00000070 ++#define CDCDR_USB_CLK_PREDF_VALUE 0x00000010 /* divide by 2 */ ++#define CDCDR_USB_CLK_PODF_MASK 0x0000000E ++#define CDCDR_USB_CLK_PODF_VALUE 0x00000002 /* divide by 2 */ ++ ++/*Hash Defines for PHY_CTRL_REG_1*/ ++#define USB_PHY_CTRL_PLLDIVVALUE_MASK 0x00000003 ++#define USB_PHY_CTRL_PLLDIVVALUE_19_2_MHZ 0x00000000 ++#define USB_PHY_CTRL_PLLDIVVALUE_24_MHZ 0x00000001 ++#define USB_PHY_CTRL_PLLDIVVALUE_26_MHZ 0x00000002 ++#define USB_PHY_CTRL_PLLDIVVALUE_27_MHZ 0x00000003 ++ ++ ++#define USB_IMX_SET_TD_OFFSET(offset,num) offset=num//do{}while(0) ++#endif ++/************************************************************************/ ++#define IMX_USB_INTR_DEV_SLE (1<<8) //DCSuspend - Sleep Enable ++#define IMX_USB_INTR_DEV_SRE (1<<7) //SOF Received Enable ++#define IMX_USB_INTR_DEV_RESET (1<<6) //USB Reset Enable ++#define IMX_USB_INTR_DEV_SEE (1<<4) //System Error Enable ++#define IMX_USB_INTR_DEV_PCE (1<<2) //Port Change Detect Enable ++#define IMX_USB_INTR_DEV_USBINT (1<<0) //USBINT Enable, IOS@dQH, IOC@dTD will be available ++ ++#define IMX_USB_STS_DCSPD (1<<8) //DCSuspend Interrupt ++#define IMX_USB_STS_SOFRSV (1<<7) //SOF Received Interrupt ++#define IMX_USB_STS_RESET (1<<6) //USB Reset Received Interrupt ++#define IMX_USB_STS_SYSERR (1<<4) //System Error Interrupt, not implemented in Marley, always '0' ++#define IMX_USB_STS_PTCHANGE (1<<2) //Port Change Detect Interrupt ++#define IMX_USB_STS_USBINT (1<<0) //USB Interrupt ++/************************************************************************/ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++/* Device Queue Head and Device Transfer Descriptor Related Defination */ ++#define SIZE_OF_QHD 0x40 ++#define SIZE_OF_DTD0 0x20 ++#define SIZE_OF_DTD1 0x20 ++#define dTD_SIZE_EPIN (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 ++#define dTD_SIZE_EPOUT (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 ++ ++#define BUFFER_USED_PER_EP ((SIZE_OF_QHD + dTD_SIZE_EPIN) +(SIZE_OF_QHD + dTD_SIZE_EPOUT)) //0x100 ++ ++#define ZLT_ENABLE 0 ++#define ZLT_DISABLE 1 ++ ++#define IOS_NOTSET 0 ++#define IOS_SET 1 ++ ++#define IOC_NOTSET 0 ++#define IOC_SET 1 ++ ++#define TERMINATE 1 ++#define NOT_TERMINATE 0 ++ ++#define NO_STATUS 0 ++#define ACTIVE BIT7 ++ ++#define EPOUT_COMPLETE BIT0 ++#define EPIN_COMPLETE BIT16 ++ ++#define EPOUT_PRIME BIT0 ++#define EPIN_PRIME BIT16 ++ ++#define EPOUT_ENABLE BIT7 ++#define EPIN_ENABLE BIT23 ++ ++#define STALL_RX 0x00000001 ++#define STALL_TX 0x00010000 ++ ++/* Buffer size of the buffer used for bulk data transfer */ ++ ++#define CONTROL_BUFFER_SIZE 0x40 ++#define BULK_BUFFER_SIZE 0x200 ++#define NUM_OF_BULK_BUFFER 0x2 ++#define TOTAL_DATA_BUFFER_SIZE ((BULK_BUFFER_SIZE * NUM_OF_BULK_BUFFER) + CONTROL_BUFFER_SIZE)//512*2+64=1088 ++ ++#define BULK_TD_BUFFER_TOTAL_SIZE 0x4000 ++#define BULK_TD_BUFFER_PAGE_SIZE 0x1000 ++/************************************************************************/ ++#define USB_OTG_TRANS_MASK 0xC0000000 ++#define USB_OTG_TRANS_SERIAL 0xC0000000 ++#define USB_OTG_TRANS_ULPI 0x80000000 ++#define USB_OTG_TRANS_PHILIP 0x40000000 ++#define USB_OTG_TRANS_UTMI 0x00000000 ++#define USB_OTG_FS_ONLY 0x01000000 ++#define USB_OTG_TRANS_WIDTH 0x10000000 ++ ++/***********************USB OTG Register Map*****************************/ ++// ---------------------------------------------------------------------------- ++// This device driver for i.MX37 has three endpoints. ++// ++// Endpoint 0 can only be used for bi-directional control messages. ++// ++// Endpoint 1 can only be used for host->slave bulk OUT transfers. ++// ++// Endpoint 2 can only be used for slave-host bulk IN transfers. ++// ++// Start with definitions of the hardware. The use of a structure and ++// a const base pointer should allow the compiler to do base/offset ++// addressing and keep the hardware base address in a register. This ++// is better than defining each hardware register via a separate ++// address. Although the registers are only a byte wide, the peripheral ++// bus only supports word accesses. ++// ++// The USB_OTG_ID etc. macros allow for an alternative way of ++// accessing the hardware if a better approach is presented, without ++// having to rewrite all the code. Macros that correspond to registers ++// are actually addresses, making it easier in the code to distinguish ++// them from bit values: the & and * operators will just cancel out. ++typedef struct usbs_imx_otg_hardware{ ++ volatile cyg_uint32 id; //0x000, Identification Register ++ volatile cyg_uint32 hwgeneral; //0x004, General HW Parameters ++ volatile cyg_uint32 hwhost; //0x008, Host HW Parameters ++ volatile cyg_uint32 hwdevice; //0x00c, Device HW Parameters ++ volatile cyg_uint32 hwtxbuf; //0x010, TX Buffer HW Parameters ++ volatile cyg_uint32 hwrxbuf; //0x014, RX Buffer HW Parameters ++ int rsv1[26]; ++ volatile cyg_uint32 gptimer0ld; //0x080, GP Timer0 Load Register ++ volatile cyg_uint32 gptimer0ctrl; //0x084, GP Timer0 Control Register ++ volatile cyg_uint32 gptimer1ld; //0x088, GP Timer1 Load Register ++ volatile cyg_uint32 gptimer1ctrl; //0x08c, GP Timer1 control register ++ volatile cyg_uint32 sbuscfg; //0x090, System Bus Interface Control ++ int rsv2[27]; ++ volatile unsigned char caplength; //0x100, Capability Length Register ++ char rsv3; ++ volatile cyg_uint16 hciversion; //0x102, Host Interface Version Number ++ volatile cyg_uint32 hcsparams; //0x104, Host Control Structural Parameters ++ volatile cyg_uint32 hccparams; //0x108, Host Control Capability Parameters ++ int rsv4[5]; ++ volatile cyg_uint16 dciversion; //0x120, Device Interface Version Number ++ short rsv5; ++ volatile cyg_uint32 dccparams; //0x124, Device Control Capability Parameters ++ int rsv6[6]; ++ volatile cyg_uint32 usbcmd; //0x140, USB Command ++ volatile cyg_uint32 usbsts; //0x144, USB Status ++ volatile cyg_uint32 usbintr; //0x148, USB Interrupt Enable ++ volatile cyg_uint32 frindex; //0x14c, USB Frame Index ++ int rsv7; ++ volatile cyg_uint32 devaddr; //0x154, USB Device Address ++ volatile cyg_uint32 endptlistaddr; //0x158, Address of Endpoint list in memory ++ volatile cyg_uint32 ttctrl; //0x15c, TT status and control ++ volatile cyg_uint32 burstsize; //0x160, Programmable Burst Size ++ volatile cyg_uint32 txfilltuning; //0x164, Host Transmit Pre-Buffer Packet Tuning ++ volatile cyg_uint32 txttfilltuning; //0x168,Host TT Transmit Pre-Buffer packet Tuning ++ int rsv8; ++ volatile cyg_uint32 ulpiviewpoint; //0x170, ULPI Viewport ++ int rsv9; ++ volatile cyg_uint32 endptnak; //0x178, Endpoint NAK ++ volatile cyg_uint32 endptnaken; //0x17c, Endpoint NAK Enable ++ volatile cyg_uint32 configflag; //0x180, Configured Flag Register ++ volatile cyg_uint32 portsc1; //0x184~0x1a0, Port Status/Control 1~8 ++ volatile cyg_uint32 portsc2; ++ volatile cyg_uint32 portsc3; ++ volatile cyg_uint32 portsc4; ++ volatile cyg_uint32 portsc5; ++ volatile cyg_uint32 portsc6; ++ volatile cyg_uint32 portsc7; ++ volatile cyg_uint32 portsc8; ++ volatile cyg_uint32 otgsc; //0x1a4, OTG Status and Control ++ volatile cyg_uint32 usbmode; //0x1a8, USB Device Mode ++ volatile cyg_uint32 endptsetupstat; //0x1ac,Endpoint Setup Status ++ volatile cyg_uint32 endptprime; //0x1b0, Endpoint Initialization ++ volatile cyg_uint32 endptflush; //0x1b4, Endpoint De-Initialization ++ volatile cyg_uint32 endptstatus; //0x1b8, Endpoint Status ++ volatile cyg_uint32 endptcomplete; //0x1bc, Endpoint Complete ++ volatile cyg_uint32 endptctrl[16]; //0x1c0~0x1fc, Endpoint Control 0~15 ++}usbs_imx_otg_hardware; ++/*************************usb structures typedefs*************************/ ++//----------------------------------------------- ++//USB buffer data structure ++typedef struct { ++ cyg_uint32 buffer_address; ++ cyg_uint32 buffer_size; ++}usb_plat_config_data_t; ++ ++//setup data for Queue Header ++typedef struct dqh_setup_t{ ++ cyg_uint32 dqh_word0; ++ cyg_uint32 dqh_word1; ++ cyg_uint32 dqh_word2; ++ cyg_uint32 dqh_word3; ++ cyg_uint32 dqh_word4; ++ cyg_uint32 dqh_word5; ++ cyg_uint32 dqh_word6; ++ cyg_uint32 dqh_word7; ++ cyg_uint32 dqh_word8; ++ cyg_uint32 dqh_word9; ++ cyg_uint32 dqh_word10; ++ cyg_uint32 dqh_word11; ++} dqh_setup_t; ++//setup data for Transfer Descriptor ++typedef struct dtd_setup_t { ++ cyg_uint32 dtd_word0; ++ cyg_uint32 dtd_word1; ++ cyg_uint32 dtd_word2; ++ cyg_uint32 dtd_word3; ++ cyg_uint32 dtd_word4; ++ cyg_uint32 dtd_word5; ++ cyg_uint32 dtd_word6; ++ cyg_uint32 dtd_word7; ++} dtd_setup_t; ++ ++//structure for Queue Header ++typedef struct dqh_t { ++ cyg_uint32 dqh_base; ++ cyg_uint32 next_link_ptr; ++ cyg_uint32 buffer_ptr0; ++ cyg_uint32 buffer_ptr1; ++ cyg_uint32 buffer_ptr2; ++ cyg_uint32 buffer_ptr3; ++ cyg_uint32 buffer_ptr4; ++ cyg_uint16 total_bytes; ++ cyg_uint16 mps; ++ cyg_uint16 current_offset; ++ cyg_uint8 zlt; ++ cyg_uint8 ios; ++ cyg_uint8 terminate; ++ cyg_uint8 ioc; ++ cyg_uint8 status; ++}dqh_t; ++ ++//structure for Transfer Descriptor ++typedef struct dtd_t { ++ cyg_uint32 dtd_base; ++ cyg_uint32 next_link_ptr; ++ cyg_uint32 buffer_ptr0; ++ cyg_uint32 buffer_ptr1; ++ cyg_uint32 buffer_ptr2; ++ cyg_uint32 buffer_ptr3; ++ cyg_uint32 buffer_ptr4; ++ cyg_uint16 total_bytes; ++ cyg_uint16 current_offset; ++ cyg_uint8 terminate; ++ cyg_uint8 ioc; ++ cyg_uint8 status; ++}dtd_t; ++ ++//structure for Transfer Descriptor layout ++typedef volatile struct TransferDescriptor { ++ unsigned terminal :1 ; ++ unsigned rsv1 :4 ; ++ unsigned nxt_pt :27 ; ++ ++ unsigned status :8 ; ++ unsigned rsv2 :2 ; ++ unsigned multo :2 ; ++ unsigned rsv3 :3 ; ++ unsigned ioc :1 ; ++ unsigned totalbytes :15 ; ++ unsigned rsv4 :1 ; ++ ++ unsigned offset :12 ; ++ unsigned bufferptr0 :20 ; ++ ++ unsigned frame_num :11 ; ++ unsigned rsv5 :1 ; ++ unsigned bufferptr1 :20 ; ++ ++ unsigned rsv6 :12 ; ++ unsigned bufferptr2 :20 ; ++ ++ unsigned rsv7 :12 ; ++ unsigned bufferptr3 :20 ; ++ ++ unsigned rsv8 :12 ; ++ unsigned bufferptr4 :20 ; ++}__attribute__((packed)) TransferDescriptor; ++ ++//structure for Queue Header layout ++typedef volatile struct QueueHeader { ++ unsigned rsv1 :15 ; ++ unsigned ios :1 ; ++ unsigned mps :11 ; ++ unsigned rsv2 :2 ; ++ unsigned zlt :1 ; ++ unsigned mult :2 ; ++ ++ unsigned rsv3 :5 ; ++ unsigned current_dtd :27 ; ++ ++ struct TransferDescriptor dtd ; ++ ++ unsigned rsv4 :32 ; ++ ++ unsigned setupbuf0 :8 ; ++ unsigned setupbuf1 :8 ; ++ unsigned setupbuf2 :8 ; ++ unsigned setupbuf3 :8 ; ++ ++ unsigned setupbuf4 :8 ; ++ unsigned setupbuf5 :8 ; ++ unsigned setupbuf6 :8 ; ++ unsigned setupbuf7 :8 ; ++}__attribute__((packed)) QueueHeader; ++ ++//bulk buffer status ++enum { ++ BUFFER_FREED, ++ BUFFER_RELEASED, ++ BUFFER_ALLOCATED ++}; ++ ++//structure of bulk buffer ++typedef struct { ++ unsigned char * buffer; ++ cyg_uint32 stat; ++}bulk_buffer_t; ++ ++//bulk buffer status ++enum { ++ MASS_STORAGE_CBW_TYPE = 1, ++ MASS_STORAGE_DATA_TYPE ++}; ++ ++//structure of USB buffer map ++typedef struct { ++ cyg_uint32 ep_dqh_base_addrs; /* Base Address of Queue Header */ ++ cyg_uint32 ep_dtd_base_addrs; /* Base Address of Transfer Descriptor */ ++ cyg_uint32 ep0_buffer_addrs; /* Buffer Addres for EP0 IN */ ++ cyg_uint32 buffer1_address; /* Buffer1 address for bulk transfer */ ++ cyg_uint32 buffer1_status; /* Status of Buffer1 */ ++ cyg_uint32 buffer2_address; /* Buffer2 address for bulk transfer */ ++ cyg_uint32 buffer2_status; /* Status of Buffer2 */ ++}buffer_map_t; ++ ++//Data Structure used for configuring the Endpoints. ++typedef struct { ++ cyg_uint8 end_pt_no; /* Endpoint number */ ++ cyg_uint8 direction; /* Direction of endpoint */ ++ cyg_uint8 transfer_type; /* type of transfer supporting on the endpoint */ ++ cyg_uint16 max_pkt_size; /* maximum packet size in bytes */ ++}usb_end_pt_info_t; ++ ++//Buffer descriptor used for data transfer on USB ++typedef struct { ++ void * buffer ; /* Address of the buffer to/from data is to be transmitted */ ++ cyg_uint32 size ; /* size of the buffer to be transmitted/recieved */ ++ cyg_uint32 bytes_transfered; /* actual number of bytes transfered */ ++}usb_buffer_descriptor_t; ++ ++/*************************important constant in usb transaction*************************/ ++/* Maximum packet size defination */ ++#define MPS_8 8 ++#define MPS_64 64 ++ ++#define SETUP_DATA_LENGTH 0x8 ++#define ENDPT_NUMBER_MASK 0x0F ++#define ENDPT_DIR_MASK 0x80 ++#define ENDPT_DIR_SHIFT 0x7 ++#define ENDPT_TRNS_TYPE_MASK 0x03 ++ ++#define USB_MAX_DEVICE_ADDR 127 ++#define USB_DEV_VALUE_OF_UNCONFIG 0x0 ++ ++#define USB_DEV_CONFIG_DESC_CONFIG_VALUE 0x01 ++/* Default device address */ ++#define USB_DEFAULT_ADDR 0x00 ++ ++/* DESCRIPTOR Type */ ++#define DEVICE_DESC 0x1 ++#define CONF_DESC 0x2 ++#define STRING_DESC 0x3 ++#define INTERFACE_DESC 0x4 ++#define ENDPOINT_DESC 0x5 ++#define DEVICE_QUALIFIER 0x6 ++#define OTHER_SPEED_CONF_DESC 0x7 ++ ++/* String SUB DESCRIPTOR type */ ++#define STR_DES0 0x0 ++#define STR_DES1 0x1 ++#define STR_DES2 0x2 ++#define STR_DES3 0x3 ++#define STR_DES4 0x4 ++#define STR_DES5 0x5 ++ ++/* Descriptor Index */ ++#define FILL_DEVICE_DESC 0x1 ++#define FILL_DEVICE_QF_DESC 0x2 ++#define FILL_CONF_DESC 0x3 ++#define FILL_OT_CONF_DESC 0x4 ++#define FILL_STR_DES0 0x5 ++#define FILL_STR_DES1 0x6 ++#define FILL_STR_DES2 0x7 ++#define FILL_STR_DES3 0x8 ++#define FILL_SN_DESC 0x9 //mandatory descriptor for mass storage device ++ ++#define LEN_OF_CONFIG_VALUE 0x1 ++ ++#define NUM_OF_ENDPT_OFFSET 0x4 ++#define CONFIG_NUMBER_OFFSET 0x5 ++#define STRING_DESC_LEN_OFFSET 0x0 ++#define DEVICE_DESC_LEN_OFFSET 0x0 ++#define CONF_DESC_LEN_OFFSET 0x0 ++#define INF_DESC_LEN_OFFSET 0x0 ++#define EP_DESC_LEN_OFFSET 0x0 ++ ++/*************************usb enums typedefs*************************/ ++typedef enum { ++ USB_DEFAULT_STATE, ++ USB_ADDRESSED_STATE, ++ USB_CONFIGURED_STATE, ++ USB_SUSPENDED_STATE ++} USB_DEVICE_STATE_T; ++ ++/* USB Device State which are handled by DCD */ ++typedef enum ++{ ++ USB_DEV_DUMMY_STATE, ++ USB_DEV_DEFAULT_STATE, ++ USB_DEV_ADDRESSED_STATE, ++ USB_DEV_CONFIGURED_STATE ++}usb_state_t; ++ ++/* Status of all transaction on USB */ ++typedef enum ++{ ++ USB_SUCCESS, ++ USB_FAILURE, ++ USB_INVALID = -1 /* Always Keep this entry in last */ ++}usb_status_t; ++ ++/* enum for endpoint numbers */ ++enum ++{ ++ EP0, ++ EP1, ++ EP2, ++ EP3, ++ EP4, ++ EP5 ++}; ++ ++enum ++{ ++ OUT, ++ IN ++}; ++/* enum for data transfer type on endpoints */ ++enum ++{ ++ CONTROL, ++ ISOCHRONOUS, ++ BULK, ++ INTERRUPT ++}; ++ ++/* Constants defined to represent the elements within the setup packet. */ ++enum ++{ ++ BMREQUESTTYPE, ++ BREQUEST, ++ WVALUE_LOWBYTE, ++ WVALUE_HIGHBYTE, ++ WINDEX_LOWBYTE, ++ WINDEX_HIGHBYTE, ++ WLENGTH_LOWBYTE, ++ WLENGTH_HIGHBYTE ++}; ++ ++/* Enum constants for function to identify the USB Standard Request defined ++ * in USB Specification. ++ */ ++enum ++{ ++ USB_GET_STATUS, ++ USB_CLEAR_FEATURE, ++ USB_RESERVED_REQ_ONE, ++ USB_SET_FEATURE, ++ USB_RESERVED_REQ_TWO, ++ USB_SET_ADDRESS, ++ USB_GET_DESCRIPTOR, ++ USB_SET_DESCRIPTOR, ++ USB_GET_CONFIGURATION, ++ USB_SET_CONFIGURATION, ++ USB_GET_INTERFACE, ++ USB_SET_INTERFACE, ++ USB_SYNCH_FRAME ++}; ++ ++/* Mass Storage Class-specific request ++ */ ++enum{ ++ USB_MSC_GET_MAX_LUN=0xFE, ++ USB_MSC_BOT_RESET ++}; ++#define USB_REQTYPE_RESET 0x21 ++#define USB_REQTYE_GETMAXLUN 0xA1 ++ ++/* Status of the buffer used for bulk transfer */ ++enum { ++ BUFFER_FREE, ++ BUFFER_IN_USE ++}; ++ ++/***********************usb_descriptor_definitions*************************/ ++#define VID 0x15A2 ++#define PID 0x002C ++ ++/* Constants defined to represent device descriptor elements. */ ++#define USB_DEV_DESC_LEN 0x12 ++#define USB_DEV_DESC_TYPE 0x01 ++#define USB_DEV_DESC_SPEC_LB 0x00 ++#define USB_DEV_DESC_SPEC_HB 0x02 ++#define USB_DEV_DESC_DEV_CLASS 0x00 /*ROM Code definition*///0x02 /* Fisher: CDC bDeviceClass */ ++#define USB_DEV_DESC_DEV_SUBCLASS 0x00 //0x02 /* Fisher: Abstract Control Model*/ ++#define USB_DEV_DESC_DEV_PROTOCOL 0x00 ++#define USB_DEV_DESC_EP0_MAXPACKETSIZE 0x40 ++#define USB_DEV_DESC_VENDORID_LB (VID & 0x00FF) ++#define USB_DEV_DESC_VENDORID_HB ((VID & 0xFF00) >> 0x8) ++#define USB_DEV_DESC_PRODUCTID_LB (PID & 0x00FF) ++#define USB_DEV_DESC_PRODUCTID_HB ((PID & 0xFF00) >> 0x8) ++#define USB_DEV_DESC_DEV_RELEASE_NUM_LB 0x01 ++#define USB_DEV_DESC_DEV_RELEASE_NUM_HB 0x00 ++#define USB_DEV_DESC_DEV_STRING_IND_MANUFACTURE 0x01 ++#define USB_DEV_DESC_DEV_STRING_IND_PRODUCT 0x02 ++#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++#define USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM 0x00 ++#else ++#define USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM 0x05 /*for mass storage device, it must >0*/ ++#endif ++#define USB_DEV_DESC_DEV_NUM_CONFIGURATIONS 0x01 ++ ++ ++ ++/* Constants defindes to represent elements of configuration descriptor. */ ++ ++#define USB_DEV_CONFIG_DESC_LEN 0x09 /* Length of configuration descriptor. */ ++#define USB_DEV_CONFIG_DESC_TYPE 0x02 /* Descriptor type. */ ++#define USB_DEV_CONFIG_DESC_TTL_LEN_LB 0x20 /* Total length of configuration information. */ ++#define USB_DEV_CONFIG_DESC_TTL_LEN_HB 0x00 /* Total length of configuration information. */ ++#define USB_DEV_CONFIG_DESC_NUM_0F_INF 0x01 /* Number of interfaces in this configuration. */ ++#define USB_DEV_CONFIG_DESC_CONFIG_VALUE 0x01 /* Configuration value. */ ++#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++#define USB_DEV_CONFIG_DESC_STRING_INDEX 0x04 /* String index for this configuration. */ ++#else ++#define USB_DEV_CONFIG_DESC_STRING_INDEX 0x00 /* String index for this configuration. */ ++#endif ++#define USB_DEV_CONFIG_DESC_ATTRIBUTES 0xC0/* Self powered and supported remote wakeup. */ ++ /* 0x80 Self powered and supported remote wakeup. */ ++ ++#define USB_DEV_CONFIG_DESC_MAX_POWER 0x32 /* 100ma,Max power consumed by phone. */ ++ ++#define USB_DEV_INF_DESC_LEN 0x09 /* Interface descriptor length. */ ++#define USB_DEV_INF_DESC_TYPE 0x04 /* The descriptor type, 4 interface descriptor. */ ++#define USB_DEV_INF_DESC_INF_INDEX 0x00 /* Interface index. */ ++#define USB_DEV_INF_DESC_ALT_SETTING 0x00 /* The alternate setting is 0. */ ++#define USB_DEV_INF_DESC_NUM_OF_EP 0x02 /* Control endpoint and data endpoint 1 and 2. */ ++#define USB_DEV_INF_DESC_INF_CLASS_VENDOR 0xFF /* Interface class: Vendor Specific. */ ++#define USB_DEV_INF_DESC_INF_CLASS_MSC 0x08 /* Interface class: Mass Storage. */ ++#define USB_DEV_INF_DESC_INF_SUBCLASS_S_BLANK 0x40 /* (Subclass) Motorola Flash Download. */ ++#define USB_DEV_INF_DESC_INF_SUBCLASS_NS_BLANK 0x42 ++#define USB_DEV_INF_DESC_INF_SUBCLASS_MSC_SCSI 0x06 /* SCSI transparent command set for mass storage*/ ++#define USB_DEV_INF_DESC_INF_PROTOCOL 0x01 /* (Interface protocol) Vendor Specific, ROM bootloader interface. */ ++#define USB_DEV_INF_DESC_INF_PROTOCOL_MSC_BOT 0x50 /* Mass Storage Bulk Only Transport*/ ++#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++#define USB_DEV_INF_DESC_STRING_INDEX 0x05 /* Index of interface string descriptor. */ ++#else ++#define USB_DEV_INF_DESC_STRING_INDEX 0x04 /* Index of interface string descriptor. */ ++#endif ++ ++/* Constants defined to represent the endpoint descriptor elements. */ ++#define USB_MAX_PACKET_SIZE 0x0200 ++#define USB_MAX_PACKET_SIZE_LO (USB_MAX_PACKET_SIZE&0xFF) ++#define USB_MAX_PACKET_SIZE_HI ((USB_MAX_PACKET_SIZE>>8)&0xFF) ++ ++/* Endpoint 1 descriptor. */ ++#define USB_EP1_DESC_SIZE 0x07 /* Size of descriptor in bytes. */ ++#define USB_EP1_DESC_TYPE 0x05 /* Descriptor type. */ ++#define USB_EP1_DESC_EP_ADDR 0x01 /* (Endpoint address) Endpoint 1, OUT. */ ++#define USB_EP1_DESC_ATTRIBUTES 0x02 /* (Attributes) Bulk Endpoint. */ ++#define USB_EP1_DESC_MAX_PACKET_SIZE_FS_LB 0x40 /* Max Packet Size. */ ++#define USB_EP1_DESC_MAX_PACKET_SIZE_FS_HB 0x00 /* Max Packet Size. */ ++#define USB_EP1_DESC_MAX_PACKET_SIZE_HS_LB USB_MAX_PACKET_SIZE_LO /* Max Packet Size. */ ++#define USB_EP1_DESC_MAX_PACKET_SIZE_HS_HB USB_MAX_PACKET_SIZE_HI /* Max Packet Size. */ ++#define USB_EP1_DESC_INTERVAL 0x00 /* Interval, ignored. */ ++#define USB_EP1_DESC_INTERVAL_HS 0x01 /* at most 1NAK. */ ++/* Endpoint 2 descriptor. */ ++#define USB_EP2_DESC_SIZE 0x07 /* Size of descriptor in bytes. */ ++#define USB_EP2_DESC_TYPE 0x05 /* Descriptor type. */ ++#define USB_EP2_DESC_EP_ADDR 0x82 /* (Endpoint address) Endpoint 2, IN. */ ++#define USB_EP2_DESC_ATTRIBUTES 0x02 /* (Attributes) Bulk Endpoint. */ ++#define USB_EP2_DESC_MAX_PACKET_SIZE_FS_LB 0x40 /* Max Packet Size. */ ++#define USB_EP2_DESC_MAX_PACKET_SIZE_FS_HB 0x00 /* Max Packet Size. */ ++#define USB_EP2_DESC_MAX_PACKET_SIZE_HS_LB USB_MAX_PACKET_SIZE_LO/* Max Packet Size. */ ++#define USB_EP2_DESC_MAX_PACKET_SIZE_HS_HB USB_MAX_PACKET_SIZE_HI /* Max Packet Size. */ ++ ++#define USB_EP2_DESC_INTERVAL 0x00 /* Interval, ignored. */ ++#define USB_EP2_DESC_INTERVAL_HS 0x01 /* at most 1NAK. */ ++/* String Descriptor 0 */ ++#define USB_STR0_DESC_SIZE 0x04 /* Size of descriptor in bytes. */ ++#define USB_STR0_DESC_TYPE 0x03 /* Descriptor type. */ ++#define USB_LANGUAGE_ID_LB 0x09 /* Language id of english */ ++#define USB_LANGUAGE_ID_HB 0x04 /* Language id of english */ ++ ++/* String Descriptor 1 */ ++#define USB_STR1_DESC_SIZE 0x3A /* Size of descriptor in bytes. */ ++#define USB_STR1_DESC_TYPE 0x03 /* Descriptor type. */ ++ ++/* String Descriptor 2 */ ++#define USB_STR2_DESC_SIZE_NS 0x20 /* Size of descriptor in bytes for Non Secure Download*/ ++#define USB_STR2_DESC_SIZE_SE 0x20 /* Size of descriptor in bytes for Secure Engg. download*/ ++#define USB_STR2_DESC_SIZE_S 0x20 /* Size of descriptor in bytes for Secure production download*/ ++#define USB_STR2_DESC_TYPE 0x03 /* Descriptor type. */ ++ ++/* String Descriptor 3 */ ++#define USB_STR3_DESC_SIZE 0x20 /* Size of descriptor in bytes. */ ++#define USB_STR3_DESC_TYPE 0x03 /* Descriptor type. */ ++ ++/* Serial number string descriptor */ ++#define USB_SN_DESC_LEN 0x1A /* Size of descriptor length*/ ++#define USB_SN_DESC_TYPE 0x03 /* type of descriptor*/ ++/*************************usb descriptor typedefs********************/ ++typedef struct { ++ usb_configuration_descriptor usb_config_desc; ++ usb_interface_descriptor usb_interface_desc; ++ usb_endpoint_descriptor usb_endpoint_desc[USB_DEV_INF_DESC_NUM_OF_EP]; ++}__attribute__((packed)) usb_conf_desc; ++/* USB device serial number for mass storage requiremen*/ ++typedef struct { ++ cyg_uint8 length; ++ cyg_uint8 descriptor_type; ++ cyg_uint8 string[24]; ++}__attribute__((packed)) usb_str4_desc; ++/* USB string Descriptor structure 0 according to USB2.0 Specification */ ++typedef struct { ++ cyg_uint8 length; ++ cyg_uint8 descriptor_type; ++ cyg_uint8 language_id0_l; ++ cyg_uint8 language_id0_h; ++}__attribute__((packed)) usb_str0_desc; ++ ++/* USB string Descriptor structure 1 according to USB2.0 Specification */ ++typedef struct { ++ cyg_uint8 length; ++ cyg_uint8 descriptor_type; ++ cyg_uint8 string[56]; ++}__attribute__((packed)) usb_str1_desc; ++ ++/* USB string Descriptor structure 2 according to USB2.0 Specification */ ++typedef struct { ++ cyg_uint8 length; ++ cyg_uint8 descriptor_type; ++ cyg_uint8 string[34]; ++}__attribute__((packed)) usb_str2_desc; ++ ++/* USB string Descriptor structure 3 according to USB2.0 Specification */ ++typedef struct { ++ cyg_uint8 length; ++ cyg_uint8 descriptor_type; ++ cyg_uint8 string[30]; ++}__attribute__((packed)) usb_str3_desc; ++ ++#define usb_dev_desc usb_device_descriptor //rename the structure ++ ++/* ALL USB Descriptors for both FS and HS */ ++typedef struct { ++ usb_dev_desc* device_desc; ++ usb_conf_desc* config_desc; ++ usb_str4_desc* sn_desc; ++ usb_str0_desc* str_desc0; ++ usb_str1_desc* str_desc1; ++ usb_str2_desc* str_desc2; ++ usb_str3_desc* str_desc3; ++ ++}usb_descriptor; ++ ++#ifdef __cplusplus ++} /* extern "C" { */ ++#endif ++ ++ ++#endif /* CYGONCE_USBS_IMX_H */ +diff -urNad redboot-imx-200952~/packages/devs/usb/imx/current/src/usbs_imx.c redboot-imx-200952/packages/devs/usb/imx/current/src/usbs_imx.c +--- redboot-imx-200952~/packages/devs/usb/imx/current/src/usbs_imx.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/devs/usb/imx/current/src/usbs_imx.c 2010-01-26 17:33:14.782960383 +0000 +@@ -0,0 +1,3440 @@ ++//========================================================================== ++// ++// usbs_imx.c ++// ++// Device driver for the i.MX51 or i.MX37 USB OTG port. ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is a part of Diagnosis Package based on eCos for Freescale i.MX ++// Family microprocessor. ++// Copyright (C) 2008 Freescale Semiconductor, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): fisherz ++// Contributors: fisherz ++// Date: 2008-10-16 ++// ++// This code implements support for the on-chip USB OTG port on the Freescale i.MX ++// family of processors. The code has been developed on the i.MX and ++// may or may not work on other members of the i.MX family. There ++// have problems with the USB support on certain revisions of the silicon, ++// so the errata sheet appropriate to the specific processor being used ++// should be consulted. There also appear to be problems which do not ++// appear on any errata, which this code attempts to work around. ++// ++// [Note] DMA is not enabled for USB transfer ++//####DESCRIPTIONEND#### ++// ++//####REVISION HISTORY#### ++// Date Author Comments ++// 22Jul08 Fisher ZHU(b18985) Created for i.MX37 eCos USB device driver ++// 16Oct08 Fisher ZHU(b18985) Ported to i.MX51 USB OTG core ++//========================================================================== ++#include //use memset() of C run-time library ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++#include ++#endif ++#include ++#include ++#include ++ ++#pragma O0 //this pragma is useful when Realview tool chain is used ++#define VOLATILE volatile ++ ++#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++//this error code is defined in error/include/codes.h ++//but when the usb driver is used in redboot, the codes.h won't ++//be included, so that this definition will solve the problem ++#define EPIPE 304 ++ ++/* Constants */ ++#define SDP_CMD_MAX_LEN 0x10 /* 16 bytes */ ++#define SDP_CMD_ACK_LEN 0x4 /* 4 bytes */ ++/* Command Packet Format: Header(2)+Address(4)+Format(1)+ByteCount(4)+Data(4) */ ++#define READ_HEADER 0x0101 //Read the flag in an assigned address on the target board ++#define WRITE_HEADER 0x0202 ++#define WRITE_FILE 0x0404 //Write a file in host PC to target board ++#define READ_FILE 0x0A0A //Read a block of RAM to host PC and save in a file ++#define ERROR_STATUS_HEADER 0x0505 ++ ++/* SDP Responses */ ++#define WRITE_COMPLETE 0x128A8A12 ++ ++/* SDP States */ ++#define CONTINUE 0 ++#define DONE 1 ++#define COMPLETE 0x88 ++ ++#define USB_DOWNLOAD_TIMEOUT_LIMIT 0x1D000000 ++cyg_uint32 usb_download_address; ++cyg_uint32 usb_download_length; ++static cyg_uint8 sdp_payload_data[SDP_CMD_MAX_LEN]; /* Used to send or receive Command/ACK */ ++static cyg_uint8 sdp_command[SDP_CMD_MAX_LEN]; /* Used to store Command */ ++static cyg_uint8 g_error_status; ++static cyg_uint8 g_usb_download_state = CONTINUE; ++static cyg_uint32 g_timeout_value = 0; ++static cyg_uint32 g_load_cycle; ++static cyg_bool pl_get_command(void); ++static cyg_uint8 pl_command_start(void); ++static cyg_uint8 pl_handle_command(cyg_uint8 g_error_status); ++static void pl_command_ack(cyg_uint32 ack); ++static void pl_handle_write_file(cyg_uint32 address, cyg_uint32 total_bytes); ++static cyg_uint32 usb_rx_processing(cyg_uint8* read_ptr, usb_status_t* status, cyg_uint32 data_length); ++static usb_status_t usb_tx_processing(cyg_uint8* write_ptr, cyg_uint32 data_len); ++#endif ++ ++/* Bit3 - Mass Storage Information ++ Bit2 - Enumeration Information ++ Bit1 - Transaction Information ++ Bit0 - Basic Information ++*/ ++//#define DEBUG_TRANS 0x8 //also defined in usbs_msc.c ++#define DEBUG_ENUM 0x4 ++#define DEBUG_TRANS 0x2 ++#define DEBUG_BASIC 0x1 ++ ++//#define USBDBGMSG(str) if(g_debug_switch&0x1) diag_printf(str) ++#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++extern cyg_uint32 g_debug_switch; //the lowest 4-bit is used for USB debug ++#if 1 ++#define USBDBGMSG(opt,fmt,args...) if(g_debug_switch&opt) diag_printf(fmt, ## args) ++#else ++#define USBDBGMSG(opt,fmt,args...) ++#endif ++ ++#else ++#define USBDBGMSG(opt,fmt,args...) //diag_printf(fmt, ## args) ++#define D(fmt,args...) diag_printf(fmt, ## args) ++#endif ++ ++// ---------------------------------------------------------------------------- ++//volatile cyg_uint8 g_bulkbuffer[BULK_TD_BUFFER_TOTAL_SIZE*NUM_OF_BULK_BUFFER] __attribute__((aligned(0x1000))); ++bulk_buffer_t g_bulkbuffer_a; ++bulk_buffer_t g_bulkbuffer_b; ++ ++//This variable is used to workaround the 31-byte packet issue in i.MX37 ++//It is initialized as "0x1", ++//When data read/write, it must initialize as '0x0' ++cyg_uint32 g_td_buffer_offset = 0; ++ ++//The below two flags is used to distinguish the received data is data or command ++cyg_uint32 g_received_data_type; ++ ++/* This is used to pause the EP2 In wait for complete, just a workaround for this issue ++ It is not sure to be a bug of IC or software, need to check later. ++*/ ++//cyg_uint8 g_tx_done=1; //to keep EP1 issue sempahore to scsi after the previous CBW processed ++cyg_uint8 g_ep2_complete_bit_set = 0; ++ ++#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++extern cyg_sem_t usbs_msc_sem; //semaphore to schedule mass storage command handling thread ++#endif ++ ++// ---------------------------------------------------------------------------- ++// Static pointers for USB buffer layout ++/*============================================================================= ++ STATIC VARIABLES ++//============================================================================*/ ++ ++// Allocate 2k-byte buffer as USB QueueHeaderList region. ++// Don't use #pragma arm section in GCC ++// !!!!USB buffer should not be cached and buffered. ++//#pragma arm section rwdata="usb_buffer_no_init", zidata="usb_buffer_no_init" ++//2k aligned, this buffer must be uncacheable and unbufferable. ++ ++#if defined(CYGHWR_IMX_USB_BUFFER_USE_IRAM) ++static volatile cyg_uint8 usb_buffer[BUFFER_SIZE] __attribute__((aligned(0x800))); ++static volatile cyg_uint8 bulk_buffer[BULK_TD_BUFFER_TOTAL_SIZE*NUM_OF_BULK_BUFFER] __attribute__((aligned(0x1000))); ++//#pragma arm section ++#else ++/* iRAM is configured as uncacheable and unbufferable in MMU initialization ++ Reserve 0x800 bytes as USB buffer ++ Don't use 0x10001000~0x10001800 for other program. */ ++#if defined(CYGHWR_USB_DEVS_MX37_OTG) ++static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x10001000); ++static volatile cyg_uint8 * bulk_buffer = (cyg_uint8 *)(0x10002000); ++#endif ++ ++#if defined(CYGHWR_USB_DEVS_MX51_OTG) ++static volatile cyg_uint8 * usb_buffer=(cyg_uint8 *)(0x1FFE9000); ++static volatile cyg_uint8 * bulk_buffer = (cyg_uint8 *)(0x1FFEA000); ++#endif ++// ++#endif //defined(CYGHWR_IMX_USB_BUFFER_USE_IRAM) ++ ++VOLATILE usbs_imx_otg_hardware* usbs_imx_otg_base = (VOLATILE usbs_imx_otg_hardware* const) USB_BASE_ADDRESS; ++ ++static void usbs_imx_otg_config_utmi_clock(void); ++ ++ ++/* Base address of the buffer allocated to IP Layer */ ++static VOLATILE cyg_uint32 g_bulkbuffer_address_base; ++/* length of the buffer */ ++static VOLATILE cyg_uint32 g_bulkbuffer_length; ++/* Buffer information used for data transfer */ ++static VOLATILE buffer_map_t g_bulkbuffer_map; ++/* Number of Endpoints configured in system */ ++static VOLATILE cyg_uint8 g_max_ep_supported; ++/* State os USB Device */ ++static VOLATILE usb_state_t g_usb_dev_state = USB_DEV_DUMMY_STATE; ++/* Length of setup data received */ ++static VOLATILE cyg_uint8 * g_usb_setup_data; ++/* Array to keep information about the endpoints used */ ++static VOLATILE usb_end_pt_info_t g_end_pt_info[USB_DEV_INF_DESC_NUM_OF_EP]; ++/* Number of endpoints */ ++static VOLATILE cyg_uint8 g_number_of_endpoints; ++/* USB Descriptors */ ++static VOLATILE usb_descriptor g_usb_desc; ++/* Number of Endpoint configured as IN */ ++static VOLATILE cyg_uint8 g_in_endpoint; ++/* Number of Endpoint configured as OUT*/ ++static VOLATILE cyg_uint8 g_out_endpoint; ++ ++/* Support for the interrupt handling code.*/ ++static cyg_interrupt g_usbs_dev_intr_data; ++static cyg_handle_t g_usbs_dev_intr_handle; ++static volatile int g_isr_status_bits = 0; ++ ++// ---------------------------------------------------------------------------- ++// get the base address of queue header for an endpointer ++#define USBS_EP_GET_dQH(endptno,dir) (g_bulkbuffer_map.ep_dqh_base_addrs + (SIZE_OF_QHD * (endptno * 2 + dir))) ++#define USBS_EP_GET_dTD(endptno,dir) (g_bulkbuffer_map.ep_dtd_base_addrs + (SIZE_OF_DTD0 + SIZE_OF_DTD1) * ( endptno * 2 + dir)) ++// ---------------------------------------------------------------------------- ++// USB interrupt enable/disable macros ++#define USBS_IMX_OTG_INTR_MASK() (usbs_imx_otg_base->usbintrclr = 0xFFFFFFFF)//0|IMX_USB_INTR_DEV_RESET|IMX_USB_INTR_DEV_USBINT) ++#define USBS_IMX_OTG_INTR_UNMASK(intr) (usbs_imx_otg_base->usbintr = 0|(intr)) ++ ++// ---------------------------------------------------------------------------- ++// Check if the IOS bit of QueueHeader or the IOC bit of Transfer Descriptor are set ++#define USBS_dQH_IOS_CHECK(ep_num,dir) (((*(cyg_uint32*)USBS_EP_GET_dQH(ep_num,dir))&0x8000)?1:0) ++#define USBS_dTD_IOC_CHECK(ep_num,dir) (((*(cyg_uint32*)USBS_EP_GET_dTD(ep_num,dir))&0x8000)?1:0) ++ ++// ---------------------------------------------------------------------------- ++// Set USB device address ++#define USBS_DEVICE_SET_ADDRESS(addr) (usbs_imx_otg_base->devaddr = ((cyg_uint32)addr & 0x7F) << 25) ++/* ++#************* ++# OTG ++#************* ++*/ ++#define USB_OTG_ID (&(usbs_imx_otg_base->id)) /* Identification Register */ ++#define USB_OTG_HWGENERAL (&(usbs_imx_otg_base->hwgeneral)) /* General Hardware Parameters */ ++#define USB_OTG_HWHOST (&(usbs_imx_otg_base->hwhost)) /* Host Hardware Parameters */ ++#define USB_OTG_HWDEVICE (&(usbs_imx_otg_base->hwdevice)) /* Device Hardware Parameters */ ++#define USB_OTG_HWTXBUF (&(usbs_imx_otg_base->hwtxbuf)) /* TX Buffer Hardware Parameters */ ++#define USB_OTG_HWRXBUF (&(usbs_imx_otg_base->hwrxbuf)) /* RX Buffer Hardware Parameters */ ++ ++#define USB_OTG_CAPLENGTH (&(usbs_imx_otg_base->caplength)) /* Capability Register Length */ ++#define USB_OTG_HCIVERSION (&(usbs_imx_otg_base->hciversion)) /* Host Interface Version Number */ ++#define USB_OTG_HCSPARAMS (&(usbs_imx_otg_base->hcsparams)) /* Host Ctrl. Structural Parameters */ ++#define USB_OTG_HCCPARAMS (&(usbs_imx_otg_base->hccparams)) /* Host Ctrl. Capability Parameters */ ++#define USB_OTG_DCIVERSION (&(usbs_imx_otg_base->dciversion)) /* Dev. Interface Version Number */ ++#define USB_OTG_DCCPARAMS (&(usbs_imx_otg_base->dccparams)) /* Dev. Ctrl. Capability Parameters */ ++ ++#define USB_OTG_USBCMD (&(usbs_imx_otg_base->usbcmd)) /* USB Command */ ++#define USB_OTG_USBSTS (&(usbs_imx_otg_base->usbsts)) /* USB Status */ ++#define USB_OTG_USBINTR (&(usbs_imx_otg_base->usbintr)) /* USB Interrupt Enable */ ++#define USB_OTG_FRINDEX (&(usbs_imx_otg_base->frindex)) /* USB Frame Index */ ++ ++#define USB_OTG_DEVICEADDR (&(usbs_imx_otg_base->devaddr)) /* USB Device Address */ ++#define USB_OTG_PERIODICLISTBASE USB_OTG_DEVICEADDR /* Frame List Base Address */ ++#define USB_OTG_ENDPOINTLISTADDR (&(usbs_imx_otg_base->endptlistaddr)) /*Address of Endpt list in memory*/ ++#define USB_OTG_ASYNCLISTADDR USB_OTG_ENDPOINTLISTADDR /* Next Asynchronous List Address */ ++ ++#define USB_OTG_BURSTSIZE (&(usbs_imx_otg_base->burstsize)) /* Programmable Burst Size */ ++#define USB_OTG_TXFILLTUNING (&(usbs_imx_otg_base->txfilltuning)) /* Host TX Pre-Buffer Packet Tuning */ ++#define USB_OTG_VIEWPORT (&(usbs_imx_otg_base->ulpiviewport)) /* ULPI Register */ ++#define USB_OTG_ENDPTNAK (&(usbs_imx_otg_base->endptnak)) /*Endpoint NAK */ ++#define USB_OTG_ENDPTNAKEN (&(usbs_imx_otg_base->endptnaken)) /*Endpoint NAK Enable */ ++#define USB_OTG_CONFIGFLAG (&(usbs_imx_otg_base->configflg)) /* Configured Flag Register */ ++#define USB_OTG_PORTSC1 (&(usbs_imx_otg_base->portsc1)) /* Port 0 Status/Control */ ++#define USB_OTG_OTGSC (&(usbs_imx_otg_base->otgsc)) /* OTG Status and Control */ ++#define USB_OTG_USBMODE (&(usbs_imx_otg_base->usbmode)) /* USB Device Mode */ ++#define USB_OTG_ENDPTSETUPSTAT (&(usbs_imx_otg_base->endptsetupstat)) /* Endpoint Setup Status */ ++#define USB_OTG_ENDPTPRIME (&(usbs_imx_otg_base->endptprime)) /* Endpoint Initialization */ ++#define USB_OTG_ENDPTFLUSH (&(usbs_imx_otg_base->endptflush)) /* Endpoint De-Initialize */ ++#define USB_OTG_ENDPTSTATUS (&(usbs_imx_otg_base->endptstatus))/* Endpoint Status */ ++#define USB_OTG_ENDPTCOMPLETE (&(usbs_imx_otg_base->endptcomplete)) /* Endpoint Complete */ ++#define USB_OTG_ENDPTCTRL0 (&(usbs_imx_otg_base->endptctrl[0])) /* Endpoint Control 0 */ ++#define USB_OTG_ENDPTCTRL1 (&(usbs_imx_otg_base->endptctrl[1])) /* Endpoint Control 1 */ ++#define USB_OTG_ENDPTCTRL2 (&(usbs_imx_otg_base->endptctrl[2])) /* Endpoint Control 2 */ ++#define USB_OTG_ENDPTCTRL3 (&(usbs_imx_otg_base->endptctrl[3])) /* Endpoint Control 3 */ ++#define USB_OTG_ENDPTCTRL4 (&(usbs_imx_otg_base->endptctrl[4])) /* Endpoint Control 4 */ ++#define USB_OTG_ENDPTCTRL5 (&(usbs_imx_otg_base->endptctrl[5])) /* Endpoint Control 5 */ ++#define USB_OTG_ENDPTCTRL6 (&(usbs_imx_otg_base->endptctrl[6])) /* Endpoint Control 6 */ ++#define USB_OTG_ENDPTCTRL7 (&(usbs_imx_otg_base->endptctrl[7])) /* Endpoint Control 7 */ ++// **************************************************************************** ++// -----------------------USB Device Descriptors------------------------------- ++// **************************************************************************** ++/* USB Device Descriptor according to USB2.0 Specification */ ++static VOLATILE usb_device_descriptor g_usb_device_desc ={ ++ USB_DEV_DESC_LEN, ++ USB_DEV_DESC_TYPE, ++ USB_DEV_DESC_SPEC_LB, ++ USB_DEV_DESC_SPEC_HB, ++ USB_DEV_DESC_DEV_CLASS, ++ USB_DEV_DESC_DEV_SUBCLASS, ++ USB_DEV_DESC_DEV_PROTOCOL, ++ USB_DEV_DESC_EP0_MAXPACKETSIZE, ++ USB_DEV_DESC_VENDORID_LB, ++ USB_DEV_DESC_VENDORID_HB, ++ USB_DEV_DESC_PRODUCTID_LB, ++ USB_DEV_DESC_PRODUCTID_HB, ++ USB_DEV_DESC_DEV_RELEASE_NUM_LB, ++ USB_DEV_DESC_DEV_RELEASE_NUM_HB, ++ USB_DEV_DESC_DEV_STRING_IND_MANUFACTURE, ++ USB_DEV_DESC_DEV_STRING_IND_PRODUCT, ++ USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM, ++ USB_DEV_DESC_DEV_NUM_CONFIGURATIONS ++}; ++ ++ ++/* USB Config Descriptor according to USB2.0 Specification */ ++static VOLATILE usb_conf_desc g_usb_config_desc = { ++ { ++ USB_DEV_CONFIG_DESC_LEN, ++ USB_DEV_CONFIG_DESC_TYPE, ++ USB_DEV_CONFIG_DESC_TTL_LEN_LB , ++ USB_DEV_CONFIG_DESC_TTL_LEN_HB , ++ USB_DEV_CONFIG_DESC_NUM_0F_INF, ++ USB_DEV_CONFIG_DESC_CONFIG_VALUE , ++ USB_DEV_CONFIG_DESC_STRING_INDEX, ++ USB_DEV_CONFIG_DESC_ATTRIBUTES, ++ USB_DEV_CONFIG_DESC_MAX_POWER ++ }, ++ /* USB Interface Descriptor according to USB2.0 Specification */ ++ {//09 ++ USB_DEV_INF_DESC_LEN, ++ USB_DEV_INF_DESC_TYPE, ++ USB_DEV_INF_DESC_INF_INDEX, ++ USB_DEV_INF_DESC_ALT_SETTING, ++ USB_DEV_INF_DESC_NUM_OF_EP, /* NOTE : This should not be more than 2 */ ++ #if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ USB_DEV_INF_DESC_INF_CLASS_VENDOR, ++ USB_DEV_INF_DESC_INF_SUBCLASS_NS_BLANK, ++ USB_DEV_INF_DESC_INF_PROTOCOL, ++ #else ++ USB_DEV_INF_DESC_INF_CLASS_MSC, ++ USB_DEV_INF_DESC_INF_SUBCLASS_MSC_SCSI, ++ USB_DEV_INF_DESC_INF_PROTOCOL_MSC_BOT, ++ #endif ++ USB_DEV_INF_DESC_STRING_INDEX ++ }, ++ /* USB Endpoint 1 Descriptors according to USB2.0 Specification, OUT */ ++ { ++ {//18 ++ USB_EP1_DESC_SIZE, ++ USB_EP1_DESC_TYPE, ++ USB_EP1_DESC_EP_ADDR, ++ USB_EP1_DESC_ATTRIBUTES, ++ USB_EP1_DESC_MAX_PACKET_SIZE_HS_LB, ++ USB_EP1_DESC_MAX_PACKET_SIZE_HS_HB, ++ USB_EP1_DESC_INTERVAL ++ }, ++ /* USB Endpoint 2 Descriptors according to USB2.0 Specification, IN */ ++ {//25 ++ USB_EP2_DESC_SIZE, ++ USB_EP2_DESC_TYPE, ++ USB_EP2_DESC_EP_ADDR, ++ USB_EP2_DESC_ATTRIBUTES, ++ USB_EP2_DESC_MAX_PACKET_SIZE_HS_LB, ++ USB_EP2_DESC_MAX_PACKET_SIZE_HS_HB, ++ USB_EP2_DESC_INTERVAL ++ } ++ } ++}; ++ ++/* USB String Descriptors 0, according to USB2.0 Specification */ ++static VOLATILE usb_str0_desc g_usb_otg_str0_desc ={ ++ USB_STR0_DESC_SIZE, ++ USB_STR0_DESC_TYPE, ++ USB_LANGUAGE_ID_LB, ++ USB_LANGUAGE_ID_HB ++}; ++ ++/* ++ STRING DESCRIPTOR ++ See table 9-15 in USB2.0 spec (www.usb.org) ++ iManufacturer ++*/ ++static VOLATILE usb_str1_desc g_usb_otg_string_desc1 ={ ++ USB_STR1_DESC_SIZE, /* bLength */ ++ USB_STR1_DESC_TYPE, /* bDescriptorType */ ++ { ++ 'F', 0x00, /* bString */ ++ 'r', 0x00, ++ 'e', 0x00, ++ 'e', 0x00, ++ 's', 0x00, ++ 'c', 0x00, ++ 'a', 0x00, ++ 'l', 0x00, ++ 'e', 0x00, ++ ' ', 0x00, ++ 'S', 0x00, ++ 'e', 0x00, ++ 'm', 0x00, ++ 'i', 0x00, ++ 'C', 0x00, ++ 'o', 0x00, ++ 'n', 0x00, ++ 'd', 0x00, ++ 'u', 0x00, ++ 'c', 0x00, ++ 't', 0x00, ++ 'o', 0x00, ++ 'r', 0x00, ++ ' ', 0x00, ++ 'I', 0x00, ++ 'n', 0x00, ++ 'c', 0x00, ++ '.', 0x00 ++ } ++}; ++#if defined(CYGHWR_USB_DEVS_MX37_OTG) ++/*iProduct*/ ++static VOLATILE usb_str2_desc g_usb_otg_string_desc2 = { ++ USB_STR2_DESC_SIZE_NS, /* bLength */ ++ USB_STR2_DESC_TYPE, /* bDescriptorType */ ++ { ++ 'M', 0x00, /* bString */ ++ 'A', 0x00, ++ 'R', 0x00, ++ 'L', 0x00, ++ 'E', 0x00, ++ 'Y', 0x00, ++ ' ', 0x00, ++ 'U', 0x00, ++ 'S', 0x00, ++ 'B', 0x00, ++ ' ', 0x00, ++ 'O', 0x00, ++ 'T', 0x00, ++ 'G', 0x00, ++ ' ', 0x00 ++ } ++}; ++//#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++/* USB Serial Number Descriptor which is mandatory to Mass Storage Device */ ++static VOLATILE usb_str4_desc g_usb_serialnumber_desc = { ++ USB_SN_DESC_LEN, ++ USB_SN_DESC_TYPE, ++ { ++ '2',0x00, ++ '0',0x00, ++ '0',0x00, ++ '8',0x00, ++ '1',0x00, ++ '8',0x00, ++ '9',0x00, ++ '8',0x00, ++ '5',0x00, ++ '0',0x00, ++ '3',0x00, ++ '7',0x00 ++ } ++}; ++//#endif ++#endif ++ ++#if defined(CYGHWR_USB_DEVS_MX51_OTG) ++static VOLATILE usb_str2_desc g_usb_otg_string_desc2 = { ++ USB_STR2_DESC_SIZE_NS, /* bLength */ ++ USB_STR2_DESC_TYPE, /* bDescriptorType */ ++ { ++ 'E', 0x00, /* bString */ ++ 'l', 0x00, ++ 'v', 0x00, ++ 'i', 0x00, ++ 's', 0x00, ++ ' ', 0x00, ++ 'U', 0x00, ++ 'S', 0x00, ++ 'B', 0x00, ++ ' ', 0x00, ++ 'O', 0x00, ++ 'T', 0x00, ++ 'T', 0x00, ++ ' ', 0x00, ++ ' ', 0x00 ++ } ++}; ++//#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++/* USB Serial Number Descriptor which is mandatory to Mass Storage Device */ ++static VOLATILE usb_str4_desc g_usb_serialnumber_desc = { ++ USB_SN_DESC_LEN, ++ USB_SN_DESC_TYPE, ++ { ++ '2',0x00, ++ '0',0x00, ++ '0',0x00, ++ '8',0x00, ++ '1',0x00, ++ '8',0x00, ++ '9',0x00, ++ '8',0x00, ++ '5',0x00, ++ '0',0x00, ++ '5',0x00, ++ '1',0x00 ++ } ++}; ++//#endif ++#endif ++ ++/* STRING DESCRIPTOR ++ See table 9-15 in USB2.0 spec (www.usb.org) ++ iSerialNumber */ ++static VOLATILE usb_str3_desc g_usb_otg_string_desc3 = { ++ USB_STR3_DESC_SIZE, /* bLength */ ++ USB_STR3_DESC_TYPE, /* bDescriptorType */ ++ { ++ 'F', 0x00, /* bString */ ++ 'r', 0x00, ++ 'e', 0x00, ++ 'e', 0x00, ++ 's', 0x00, ++ 'c', 0x00, ++ 'a', 0x00, ++ 'l', 0x00, ++ 'e', 0x00, ++ ' ', 0x00, ++ 'F', 0x00, ++ 'l', 0x00, ++ 'a', 0x00, ++ 's', 0x00, ++ 'h', 0x00 ++ } ++}; ++ ++ ++// **************************************************************************** ++// ---------------------------------------------------------------------------- ++// **************************************************************************** ++// ---------------------------------------------------------------------------- ++// Static data. There is a data structure for each endpoint. The ++// implementation is essentially a private class that inherits from ++// common classes for control and data endpoints, but device drivers ++// are supposed to be written in C so some ugliness is required. ++ ++// ---------------------------------------------------------------------------- ++// Endpoint 0 is always present, this module would not get compiled ++// otherwise. ++static void usbs_imx_otg_dev_ep0_start(usbs_control_endpoint*); ++static void usbs_imx_otg_dev_poll(usbs_control_endpoint*); ++ ++typedef enum ep0_state { ++ EP0_STATE_IDLE = 0, ++ EP0_STATE_IN = 1, ++ EP0_STATE_OUT = 2 ++} ep0_state; ++ ++typedef struct ep0_impl { ++ usbs_control_endpoint common; //struct usbs_control_endpoint defined in usbs.h ++ ep0_state ep_state; ++ int length; ++ int transmitted; ++} ep0_impl; ++ ++static ep0_impl ep0 = { ++ common: ++ { ++ state: USBS_STATE_POWERED, // The hardware does not distinguish between detached, attached and powered. ++ enumeration_data: (usbs_enumeration_data*) 0, ++ start_fn: &usbs_imx_otg_dev_ep0_start, ++ poll_fn: &usbs_imx_otg_dev_poll, ++ interrupt_vector: IMX_IRQ_USB_DEV_SERVICE_REQUEST, ++ control_buffer: { 0, 0, 0, 0, 0, 0, 0, 0 }, ++ state_change_fn: (void (*)(usbs_control_endpoint*, void*, usbs_state_change, int)) 0, ++ state_change_data: (void*) 0, ++ standard_control_fn: (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0, ++ standard_control_data: (void*) 0, ++ class_control_fn: (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0, ++ class_control_data: (void*) 0, ++ vendor_control_fn: (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0, ++ vendor_control_data: (void*) 0, ++ reserved_control_fn: (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0, ++ reserved_control_data: (void*) 0, ++ buffer: (unsigned char*) 0, ++ buffer_size: 0, ++ fill_buffer_fn: (void (*)(usbs_control_endpoint*)) 0, ++ fill_data: (void*) 0, ++ fill_index: 0, ++ complete_fn: (usbs_control_return (*)(usbs_control_endpoint*, int)) 0 ++ }, ++ ep_state: EP0_STATE_IDLE, ++ length: 0, ++ transmitted: 0 ++}; ++ ++extern usbs_control_endpoint usbs_imx_otg_ep0 __attribute__((alias ("ep0"))); ++ ++// Endpoint 1 is optional. If the application only involves control ++// messages or only slave->host transfers then the endpoint 1 ++// support can be disabled. ++//#ifdef CYGPKG_DEVS_USB_MX37_EP1 ++ ++typedef struct ep1_impl { ++ usbs_rx_endpoint common; //struct usbs_rx_endpoint defined in usbs.h ++ int fetched; ++ cyg_bool using_buf_a; ++} ep1_impl; ++ ++static void ep1_start_rx(usbs_rx_endpoint*); ++static void ep1_set_halted(usbs_rx_endpoint*, cyg_bool); ++ ++static ep1_impl ep1 = { ++ common: { ++ start_rx_fn: &ep1_start_rx, ++ set_halted_fn: &ep1_set_halted, ++ complete_fn: (void (*)(void*, int)) 0, ++ complete_data: (void*) 0, ++ buffer: (unsigned char*) 0, ++ buffer_size: 0, ++ halted: 0, ++ }, ++ fetched: 0, ++ using_buf_a: 0 ++}; ++ ++extern usbs_rx_endpoint usbs_imx_otg_ep1 __attribute__((alias ("ep1"))); ++//#endif ++ ++// Endpoint 2 is optional. If the application only involves control ++// messages or only host->slave transfers then the endpoint 2 support ++// can be disabled. ++//#ifdef CYGPKG_DEVS_USB_MX37_EP2 ++ ++typedef struct ep2_impl { ++ usbs_tx_endpoint common; //struct usbs_tx_endpoint defined in usbs.h ++ int transmitted; ++ int pkt_size; ++} ep2_impl; ++ ++static void ep2_start_tx(usbs_tx_endpoint*); ++static void ep2_set_halted(usbs_tx_endpoint*, cyg_bool); ++ ++static ep2_impl ep2 = { ++ common: { ++ start_tx_fn: &ep2_start_tx, ++ set_halted_fn: &ep2_set_halted, ++ complete_fn: (void (*)(void*, int)) 0, ++ complete_data: (void*) 0, ++ buffer: (const unsigned char*) 0, ++ buffer_size: 0, ++ halted: 0, ++ }, ++ transmitted: 0, ++ pkt_size: 0 ++}; ++ ++extern usbs_tx_endpoint usbs_imx_otg_ep2 __attribute__ ((alias ("ep2"))); ++//#endif ++ ++// **************************************************************************** ++// -----------------------Static Functions Initialization---------------------- ++// **************************************************************************** ++static void usbs_handle_get_descriptor(void); ++static void usbs_handle_set_configuration(void); ++static void usbs_handle_get_device_desc(void); ++static void usbs_handle_get_config_desc(void); ++static void usbs_handle_get_string_desc(void); ++static void usbs_handle_get_configuration(void); ++static void usbs_handle_set_address(void); ++ ++static void usbs_ep0in_fill_buffer(cyg_uint8 type, cyg_uint32 buffer_addrs); ++static usb_status_t usbs_ep0_send_data(usb_buffer_descriptor_t* bd,cyg_uint8 zlt); ++static usb_status_t usbs_ep0_receive_data(usb_buffer_descriptor_t* bd); ++ ++static void usbs_setup_queuehead(struct dqh_t* qhead); ++static void usbs_setup_transdesc(struct dtd_t* td); ++static void usbs_endpoint_stall(cyg_uint8 endpoint , cyg_uint8 direction); ++static void usbs_status_phase(cyg_uint8 trans_type, cyg_uint8 direction); ++ ++static void usbs_imx_otg_dev_set_configuration(usb_end_pt_info_t* config_data); ++static void usbs_imx_otg_dev_handle_bus_reset(void); ++static void usbs_imx_otg_dev_handle_port_change(void); ++static void usbs_imx_otg_hardware_init(void); ++ ++cyg_uint32 util_alloc_buffer(void); ++void util_free_buffer(cyg_uint32 address); ++void util_set_status_bulk_buffer(cyg_uint32 buffer_addr,int buffer_status); ++// **************************************************************************** ++// -----------------------Static Functions ------------------------------------ ++// **************************************************************************** ++/*============================================================================= ++FUNCTION: usbs_setup_queuehead ++DESCRIPTION: This function is used to setup the dQH ++ ------------------------ ++ | EP0 IN (64 bytes) | ++ | | ++ ------------------------ dQH1 ++ | EP0 OUT (64 bytes) | ++ | | ++ ------------------------ dQH0 ++ARGUMENTS PASSED: ++ cyg_uint32 dqh_base - Base Address of the dQH ++ cyg_uint8 zlt - zero lengh packet termination (enable - ZLT_ENABLE; disable - ZLT_DISABLE) ++ cyg_uint16 mps - Max packet length ++ cyg_uint8 ios - interrupt on Setup ++ cyg_uint32 next_link_ptr - Next Link Pointer, ++ cyg_uint8 terminate - terminate - TERMINATE; not terminate - NOT_TERMINATE ++ cyg_uint16 total_bytes - Total Bytes to be transfered in this dQH ++ cyg_uint8 ioc - interrupt on complete, set - IOC_SET, not set - IOC_NOTSET ++ cyg_uint8 status - status ++ cyg_uint32 buffer_ptr0 - Buffer Pointer page 0 ++ cyg_uint16 current_offset - current offset ++ cyg_uint32 buffer_ptr1 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr2 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr3 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr4 - Buffer Pointer page 1 ++ ++RETURN VALUE: None ++IMPORTANT NOTES:None ++=============================================================================*/ ++static void ++usbs_setup_queuehead(struct dqh_t* qhead) ++{ ++ volatile struct dqh_setup_t* dqh_word = (volatile struct dqh_setup_t*) qhead->dqh_base; ++ ++ /*Bit31:30 Mult; Bit29 zlt; Bit26:16 mps; Bit15 ios */ ++ dqh_word->dqh_word0 = (((cyg_uint32)(qhead->zlt) << 29)|((cyg_uint32)(qhead->mps) <<16) | ((cyg_uint32)(qhead->ios) <<15)); ++ ++ /*Current dTD Pointer => for hw use, not modified by DCD software */ ++ dqh_word->dqh_word1 = 0x0; ++ ++ /*Next dTD Pointer */ ++ dqh_word->dqh_word2 = (((qhead->next_link_ptr) & 0xFFFFFFE0) | qhead->terminate); ++ ++ /*Bit30:16 total_bytes; Bit15 ioc; Bit11:10 MultO; Bit7:0 status */ ++ dqh_word->dqh_word3 = ((((cyg_uint32)(qhead->total_bytes) & 0x7FFF) << 16) | ((cyg_uint32)(qhead->ioc) <<15) | (qhead->status)); ++ ++ /*Bit31:12 Buffer Pointer (Page 0) */ ++ dqh_word->dqh_word4 = ((qhead->buffer_ptr0 & 0xFFFFF000) | (qhead->current_offset & 0xFFF)); ++ ++ /*Bit31:12 Buffer Pointer (Page 1) */ ++ dqh_word->dqh_word5 = (qhead->buffer_ptr1 & 0xFFFFF000); ++ ++ /*Bit31:12 Buffer Pointer (Page 2) */ ++ dqh_word->dqh_word6 = (qhead->buffer_ptr2 & 0xFFFFF000); ++ ++ /*Bit31:12 Buffer Pointer (Page 3) */ ++ dqh_word->dqh_word7 = (qhead->buffer_ptr3 & 0xFFFFF000); ++ ++ /*Bit31:12 Buffer Pointer (Page 4) */ ++ dqh_word->dqh_word8 = (qhead->buffer_ptr4 & 0xFFFFF000); ++ ++ /*Reserved */ ++ dqh_word->dqh_word9 = 0; ++ ++ /*Setup Buffer 0 */ ++ dqh_word->dqh_word10 = 0; ++ ++ /*Setup Buffer 1 */ ++ dqh_word->dqh_word11 = 0; ++} ++/*============================================================================= ++FUNCTION: usbs_setup_transdesc ++DESCRIPTION: This function is used to setup the dTD ++ARGUMENTS PASSED: ++ cyg_uint32 dtd_base - Base Address of the dTD ++ cyg_uint32 next_link_ptr - Next Link Pointer, ++ cyg_uint8 terminate - terminate - TERMINATE; not terminate - NOT_TERMINATE ++ cyg_uint16 total_bytes - Total Bytes to be transfered in this dQH ++ cyg_uint8 ioc - interrupt on complete, set - IOC_SET, not set - IOC_NOTSET ++ cyg_uint8 Status - Status ++ cyg_uint32 buffer_ptr0 - Buffer Pointer page 0 ++ cyg_uint16 current_offset - current offset ++ cyg_uint32 buffer_ptr1 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr2 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr3 - Buffer Pointer page 1 ++ cyg_uint32 buffer_ptr4 - Buffer Pointer page 1 ++RETURN VALUE: None ++IMPORTANT NOTES:None ++==============================================================================*/ ++static void ++usbs_setup_transdesc(struct dtd_t* td) ++{ ++ volatile struct dtd_setup_t* dtd_word = (volatile struct dtd_setup_t *) td->dtd_base; ++ ++ /* Bit31:5 Next Link Pointer ; Bit0 terminate */ ++ dtd_word->dtd_word0 = ((td->next_link_ptr & 0xFFFFFFE0) | td->terminate); ++ ++ /* Bit30:16 total_bytes, Bit15 ioc, Bit7:0 status */ ++ dtd_word->dtd_word1 = ((((cyg_uint32)td->total_bytes & 0x7FFF) << 16)| ((cyg_uint32)td->ioc <<15) | (td->status)); ++ ++ /* Bit31:12 Buffer Pointer Page 0 ; Bit11:0 Current Offset */ ++ dtd_word->dtd_word2 = ((td->buffer_ptr0 & 0xFFFFF000) | (td->current_offset & 0xFFF)); ++ ++ /* Bit31:12 Buffer Pointer Page 1 ; Bit10:0 Frame Number */ ++ dtd_word->dtd_word3 = (td->buffer_ptr1 & 0xFFFFF000); ++ ++ /* Bit31:12 Buffer Pointer Page 2 ; */ ++ dtd_word->dtd_word4 = (td->buffer_ptr2 & 0xFFFFF000); ++ ++ /* Bit31:12 Buffer Pointer Page 3 ; */ ++ dtd_word->dtd_word5 = (td->buffer_ptr3 & 0xFFFFF000); ++ ++ /* Bit31:12 Buffer Pointer Page 4 ; */ ++ dtd_word->dtd_word6 = (td->buffer_ptr4 & 0xFFFFF000); ++ ++} ++ ++/*================================================================================================== ++FUNCTION: util_alloc_buffer ++DESCRIPTION: This utility function allocate the free buffer available ++ARGUMENTS PASSED: None ++RETURN VALUE: cyg_uint32 address : address of the allocated buffer ++IMPORTANT NOTES: If Buffer1 is FREE then return Buffer1 and mark this as Busy else check for buffer2 . If ++ none of the buffer is free then return NULL. ++==================================================================================================*/ ++cyg_uint32 util_alloc_buffer(void) ++{ ++ cyg_uint32 buffer_addr = (cyg_uint32)NULL; //force type conversion for multiple NULL definitions ++ ++ /* Check if buffer1 is free then mark it busy and return address */ ++ if (g_bulkbuffer_map.buffer1_status == BUFFER_FREE ) ++ { ++ buffer_addr = g_bulkbuffer_map.buffer1_address; ++ g_bulkbuffer_map.buffer1_status = BUFFER_IN_USE; ++ } ++ /* Check if buffer2 is free then mark it busy and return address */ ++ else if(g_bulkbuffer_map.buffer2_status == BUFFER_FREE) ++ { ++ buffer_addr = g_bulkbuffer_map.buffer2_address; ++ g_bulkbuffer_map.buffer2_status = BUFFER_IN_USE; ++ } ++ ++ return buffer_addr ; ++} ++/*================================================================================================== ++FUNCTION: util_free_buffer ++DESCRIPTION: This function put the buffer in free state. ++ARGUMENTS PASSED: cyg_uint32 address : address of the buffer . ++RETURN VALUE: None ++IMPORTANT NOTES: None ++ ++==================================================================================================*/ ++void util_free_buffer(cyg_uint32 address) ++{ ++ if( address == g_bulkbuffer_map.buffer1_address ) ++ { ++ g_bulkbuffer_map.buffer1_status = BUFFER_FREE; ++ } ++ else if ( address == g_bulkbuffer_map.buffer2_address ) ++ { ++ g_bulkbuffer_map.buffer2_status = BUFFER_FREE; ++ } ++} ++/*================================================================================================== ++FUNCTION: util_set_bulk_buffer_stat ++DESCRIPTION: This function change the bulk buffer status ++ARGUMENTS PASSED: cyg_uint32 buffer_addr: buffer base address ++ int buffer_status: new buffer_status ++enum { ++ BUFFER_FREED, ++ BUFFER_RELEASED, ++ BUFFER_ALLOCATED ++}; ++RETURN VALUE: None ++IMPORTANT NOTES: None ++ ++==================================================================================================*/ ++void util_set_status_bulk_buffer(cyg_uint32 buffer_addr,int buffer_status) ++{ ++ if( buffer_addr == (cyg_uint32)g_bulkbuffer_a.buffer) ++ { ++ g_bulkbuffer_a.stat = buffer_status; ++ } ++ else if ( buffer_addr == (cyg_uint32)g_bulkbuffer_b.buffer ) ++ { ++ g_bulkbuffer_b.stat = buffer_status; ++ } ++ else ++ return; ++} ++/*============================================================================= ++FUNCTION: usbs_endpoint_stall ++DESCRIPTION: This function Send/Receive the STALL HANDSHAKE to USB Host ++ARGUMENTS PASSED: ++ cyg_uint8 endpoint - Endpoint Number . ++ cyg_uint8 direction - IN/OUT : direction of EndPoint. ++RETURN VALUE: None ++IMPORTANT NOTES:None ++==============================================================================*/ ++static void ++usbs_endpoint_stall(cyg_uint8 endpoint , cyg_uint8 direction) ++{ ++ if( direction == OUT ) ++ { ++ usbs_imx_otg_base->endptctrl[endpoint]|= STALL_RX; ++ } ++ else ++ { ++ usbs_imx_otg_base->endptctrl[endpoint] |= STALL_TX; ++ } ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - EP%d - %d stalled\n",endpoint,direction); ++} ++ ++static void ++usbs_endpoint_unstall(cyg_uint8 endpoint , cyg_uint8 direction) ++{ ++ if( direction == OUT ) ++ { ++ usbs_imx_otg_base->endptctrl[endpoint]&= ~STALL_RX; ++ } ++ else ++ { ++ usbs_imx_otg_base->endptctrl[endpoint]&= ~STALL_TX; ++ } ++} ++ ++/*============================================================================= ++FUNCTION: usbs_status_phase ++DESCRIPTION: This function Send/Receive the Status to/from Host. ++ARGUMENTS PASSED: cyg_uint8 direction OUT Receive Status Command From Host ++ IN Send Status Command to Host ++RETURN VALUE: None ++IMPORTANT NOTES: ++===============================================================================*/ ++static void ++usbs_status_phase(cyg_uint8 trans_type, cyg_uint8 direction) ++{ ++ usb_buffer_descriptor_t bd ; ++ ++ /* Buffer pointer is not used for EP0 */ ++ bd.buffer = (cyg_uint32 *) 0xFFFFFFFF; ++ bd.size = 0x0; ++ ++ if(trans_type==CONTROL) ++ { ++ switch ( direction ) ++ { ++ case OUT : ++ /* Receive ZERO length Length Data */ ++ usbs_ep0_receive_data(&bd); ++ break; ++ case IN : ++ /* Send ZERO length Length Data */ ++ usbs_ep0_send_data(&bd,0); ++ break; ++ } ++ } ++ else if(trans_type==BULK)/*TODO*/ ++ { ++ switch ( direction ) ++ { ++ case OUT : ++ /* Send ZERO length Length Data */ ++ //usbs_ep2_send_data(EP2,&bd,FALSE); ++ break; ++ case IN : ++ /* Receive ZERO length Length Data */ ++ //usbs_ep1_receive_data(EP1,&bd); ++ break; ++ } ++ } ++ ++} ++// --------------------------------------------------------------------------- ++// The following static functions are for USB device enumeration processing ++/*============================================================================ ++FUNCTION: usbs_handle_get_descriptor ++DESCRIPTION: This function Handle the GET DESCRIPTOR request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++============================================================================*/ ++static void ++usbs_handle_get_descriptor() ++{ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get descriptor handler\n"); ++ switch (g_usb_setup_data[WVALUE_HIGHBYTE]) ++ { ++ case DEVICE_DESC: /* device descriptor*/ ++ usbs_handle_get_device_desc(); //Device will send the MPS to host ++ break; ++ case CONF_DESC: /* configuration descriptor*/ ++ usbs_handle_get_config_desc(); //Device will send the whole device descriptor to host ++ break; ++ case STRING_DESC: /* string descriptor*/ ++ usbs_handle_get_string_desc(); ++ break; ++ case INTERFACE_DESC: ++ case ENDPOINT_DESC: ++ case DEVICE_QUALIFIER: ++ case OTHER_SPEED_CONF_DESC: ++ default: /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ break; ++ } ++ ++ ++} ++/*============================================================================= ++FUNCTION: usbs_handle_get_device_desc ++DESCRIPTION: This function Handle the GET DEVICE DESCRIPTOR request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++==============================================================================*/ ++static void ++usbs_handle_get_device_desc(void) ++{ ++ usb_buffer_descriptor_t bd ; ++ cyg_uint32 buffer_addrs; ++ cyg_uint16 desc_length = 0x0; ++ cyg_uint8 zlt = 0;//0 means false ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get device descriptor\n"); ++ ++ /* get the buffer address for data transfer over EP0 */ ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; //256bytes before the two Bulk buffers ++ ++ /* Fill the buffer with the descriptor data */ ++ usbs_ep0in_fill_buffer(FILL_DEVICE_DESC,buffer_addrs); ++ ++ /* Get the length of descriptor requested */ ++ desc_length = g_usb_setup_data[WLENGTH_LOWBYTE]; ++ desc_length |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8); ++ ++ /* If requested length of descriptor is lesser than actual length of descriptor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if( g_usb_dev_state == USB_DEV_DEFAULT_STATE ) ++ { ++ bd.size = MPS_8; ++ } ++ else ++ { ++ bd.size = USB_DEV_DESC_LEN; ++ } ++ ++ /* Send descriptor - Data Phase*/ ++ usbs_ep0_send_data(&bd,zlt); //zlt is false=>not zero length packet ++ //send dev descriptor to host. ++ ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); //Get Zero-length data packet from Host, Device sends status: ACK(success), NAK(busy), or STALL(failed) ++ ++ ++} ++/*============================================================================= ++FUNCTION: usbs_handle_get_config_desc ++DESCRIPTION: This function Handle the GET CONFIGURATION DESCRIPTOR request ++ARGUMENTS PASSED: ++RETURN VALUE: None ++IMPORTANT NOTES:None ++=============================================================================*/ ++static void ++usbs_handle_get_config_desc(void) ++{ ++ usb_buffer_descriptor_t bd; ++ cyg_uint32 buffer_addrs; ++ cyg_uint16 desc_length_req = 0x0; ++ cyg_uint16 desc_length = 0x0; ++ int zlt = 0; ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get config descriptor\n"); ++ /* get the buffer address for data transfer over EP0 */ ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; ++ ++ /* Fill the buffer with the descriptor data */ ++ usbs_ep0in_fill_buffer(FILL_CONF_DESC, buffer_addrs); ++ ++ /* total length of descriptor */ ++ desc_length = ((g_usb_desc.config_desc->usb_config_desc.total_length_lo) \ ++ | ( g_usb_desc.config_desc->usb_config_desc.total_length_hi << 0x8 )); ++ /* Get the length of descriptor requested */ ++ desc_length_req = g_usb_setup_data[WLENGTH_LOWBYTE]; ++ desc_length_req |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8); ++ ++ ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= desc_length) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = desc_length; ++ ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ usbs_ep0_send_data(&bd,zlt); ++ ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ ++} ++/*============================================================================= ++FUNCTION: usbs_handle_get_string_desc ++DESCRIPTION: This function Handle the GET STRING DESCRIPTOR request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++==============================================================================*/ ++static void ++usbs_handle_get_string_desc(void) ++{ ++ usb_buffer_descriptor_t bd; ++ cyg_uint32 buffer_addrs; ++ cyg_uint16 desc_length_req = 0x0; ++ cyg_uint16 length_of_desc = 0x0; ++ int zlt = 0; ++ ++ ++ /* Get Buufer to fill the data to be received/transmitted. */ ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; ++ ++ /* Get the length of descriptor requested */ ++ desc_length_req = g_usb_setup_data[WLENGTH_LOWBYTE]; ++ desc_length_req |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8); ++ ++ switch (g_usb_setup_data[WVALUE_LOWBYTE]) ++ { ++ case STR_DES0: ++ usbs_ep0in_fill_buffer(FILL_STR_DES0,buffer_addrs); ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= g_usb_desc.str_desc0->length ) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = g_usb_desc.str_desc0->length; ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ /* Data Phase -- IN */ ++ usbs_ep0_send_data(&bd,zlt); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 0\n"); ++ break; ++ ++ case STR_DES1: /*iManufacturer */ ++ usbs_ep0in_fill_buffer(FILL_STR_DES1,buffer_addrs); ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= g_usb_desc.str_desc1->length ) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = g_usb_desc.str_desc1->length; ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ /* Data Phase -- IN */ ++ usbs_ep0_send_data(&bd,zlt); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 1\n"); ++ break; ++ ++ case STR_DES2: /*iProduct */ ++ usbs_ep0in_fill_buffer(FILL_STR_DES2,buffer_addrs ); ++ length_of_desc = g_usb_desc.str_desc2->length; ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= length_of_desc ) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = length_of_desc; ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ /* Data Phase -- IN */ ++ usbs_ep0_send_data(&bd,zlt); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 2\n"); ++ break; ++ ++ case STR_DES3: ++ /* send zero length data */ ++ usbs_status_phase(CONTROL,IN); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ break; ++ ++ case STR_DES5: /*iSerialNumber */ ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ usbs_ep0in_fill_buffer(FILL_SN_DESC,buffer_addrs ); ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= g_usb_desc.sn_desc->length ) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = g_usb_desc.sn_desc->length; ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ /* Data Phase -- IN */ ++ usbs_ep0_send_data(&bd,zlt); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor - SN\n"); ++ break; ++ #endif ++ case STR_DES4: /*iSerialNumber */ ++ usbs_ep0in_fill_buffer(FILL_STR_DES3,buffer_addrs ); ++ /* If requested length of descriptor is lesser than actual length of descriotor then send ++ * requested length of descroptor only else send the actual length of descriptor*/ ++ if(desc_length_req <= g_usb_desc.str_desc3->length ) ++ { ++ bd.size = desc_length_req; ++ } ++ else ++ { ++ bd.size = g_usb_desc.str_desc3->length; ++ if ( bd.size > MPS_64) ++ { ++ zlt = 1; ++ } ++ } ++ /* Data Phase -- IN */ ++ usbs_ep0_send_data(&bd,zlt); ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get string descriptor 3\n"); ++ break; ++ default: ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ //USBDBGMSG("+USBDBGMSG:EP0 IN stalled at get string desc\n"); ++ break; ++ } ++ ++ ++} ++ ++/*============================================================================= ++FUNCTION: usbs_handle_set_address ++DESCRIPTION: This function Handle the SET ADDRESS Request from USB Host ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: ++==============================================================================*/ ++static void ++usbs_handle_set_address(void) ++{ ++ cyg_uint16 device_addrs; ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set address handler\n"); ++ /* Get the Device Address to be SET from the Setup Data */ ++ device_addrs = g_usb_setup_data[WVALUE_LOWBYTE] + (g_usb_setup_data[WVALUE_HIGHBYTE]<<8); ++ ++ if ((g_usb_setup_data[WINDEX_LOWBYTE] == 0) && ++ (g_usb_setup_data[WINDEX_HIGHBYTE] == 0) && ++ (g_usb_setup_data[WLENGTH_LOWBYTE] == 0) && ++ (g_usb_setup_data[WLENGTH_HIGHBYTE] == 0) && ++ (device_addrs <= USB_MAX_DEVICE_ADDR)) ++ { ++ switch(g_usb_dev_state) ++ { ++ case USB_DEV_DEFAULT_STATE : ++ /* Send Ack to Host */ ++ usbs_status_phase(CONTROL,IN); ++ if (device_addrs != USB_DEFAULT_ADDR) ++ { ++ /* Set the Device Address */ ++ USBS_DEVICE_SET_ADDRESS(device_addrs); ++ /* Change state to ADDRESSED STATE */ ++ g_usb_dev_state = USB_DEV_ADDRESSED_STATE; ++ } ++ break; ++ ++ case USB_DEV_ADDRESSED_STATE : ++ /* Send Ack to Host */ ++ usbs_status_phase(CONTROL,IN); ++ if ( device_addrs == USB_DEFAULT_ADDR ) ++ { ++ /* Set the Device Address */ ++ USBS_DEVICE_SET_ADDRESS(USB_DEFAULT_ADDR); ++ /* Change state to ADDRESSED STATE */ ++ g_usb_dev_state = USB_DEV_DEFAULT_STATE; ++ } ++ else ++ { ++ /* Set the Device Address */ ++ USBS_DEVICE_SET_ADDRESS(device_addrs); ++ } ++ break; ++ ++ case USB_DEV_CONFIGURED_STATE : ++ if ( device_addrs == USB_DEFAULT_ADDR) ++ { ++ /* Send Ack to Host */ ++ usbs_status_phase(CONTROL,IN); ++ /* Set the Device Address */ ++ USBS_DEVICE_SET_ADDRESS(device_addrs); ++ /* Change state to ADDRESSED STATE */ ++ g_usb_dev_state = USB_DEV_DEFAULT_STATE; ++ } ++ else ++ { ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ } ++ default : ++ break; ++ } ++ } ++ else ++ { ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ } ++ ++ ++} ++/*============================================================================= ++FUNCTION: usbs_handle_get_configuration ++DESCRIPTION: This function Handle the GET CONFIGURATION request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++=============================================================================*/ ++static void ++usbs_handle_get_configuration(void) ++{ ++ usb_buffer_descriptor_t bd; ++ cyg_uint32 buffer_addrs; ++ cyg_uint32* buffer_ptr; ++ ++ if((g_usb_setup_data[WINDEX_LOWBYTE] == 0) && ++ (g_usb_setup_data[WINDEX_HIGHBYTE] == 0) && ++ (g_usb_setup_data[WVALUE_LOWBYTE] == 0) && ++ (g_usb_setup_data[WVALUE_HIGHBYTE] == 0) && ++ (g_usb_setup_data[WLENGTH_LOWBYTE] == LEN_OF_CONFIG_VALUE) && ++ (g_usb_setup_data[WLENGTH_HIGHBYTE] == 0)) ++ { ++ switch(g_usb_dev_state) ++ { ++ case USB_DEV_DEFAULT_STATE : ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ break; ++ case USB_DEV_ADDRESSED_STATE: ++ /* If the Device is in Address state then return 0x0 : See USB2.0 Spec */ ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; ++ buffer_ptr = (cyg_uint32 *)buffer_addrs; ++ *buffer_ptr = 0x0; ++ ++ bd.buffer = buffer_ptr; ++ bd.size=LEN_OF_CONFIG_VALUE; ++ ++ usbs_ep0_send_data(&bd,0); ++ ++ /* Receive Ack from Host*/ ++ usbs_status_phase(CONTROL,OUT); ++ break; ++ ++ case USB_DEV_CONFIGURED_STATE: ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; ++ buffer_ptr = (cyg_uint32 *)buffer_addrs; ++ ++ *buffer_ptr = (cyg_uint32 )g_usb_desc.config_desc->usb_config_desc.configuration_id; ++ ++ bd.buffer = buffer_ptr; ++ bd.size=LEN_OF_CONFIG_VALUE; ++ ++ usbs_ep0_send_data(&bd,0); ++ ++ /* Receive Ack from Host*/ ++ usbs_status_phase(CONTROL,OUT); ++ break; ++ ++ default: ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ } ++ ++ } ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - get config handler\n"); ++} ++/*============================================================================= ++FUNCTION: usbs_handle_set_configuration ++DESCRIPTION: This function Handle the SET CONFIGURATION request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++=============================================================================*/ ++static void ++usbs_handle_set_configuration(void) ++{ ++ usb_end_pt_info_t config_data ; ++ cyg_uint8 i; ++ ++ switch (g_usb_dev_state) ++ { ++ case USB_DEV_ADDRESSED_STATE : ++ if (g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_VALUE_OF_UNCONFIG) ++ { ++ /* Send Ack to Host*/ ++ usbs_status_phase(CONTROL,IN); ++ } ++ /* Check if the configuration value received request is same as in Config descriptor */ ++ else if(g_usb_setup_data[WVALUE_LOWBYTE] == g_usb_desc.config_desc->usb_config_desc.configuration_id) ++ { ++ /* Configure endpoints */ ++ for ( i = 0 ; i< g_number_of_endpoints ; i++) ++ { ++ config_data.end_pt_no = g_end_pt_info[i].end_pt_no; ++ config_data.direction = g_end_pt_info[i].direction; ++ config_data.transfer_type = g_end_pt_info[i].transfer_type; ++ config_data.max_pkt_size = g_end_pt_info[i].max_pkt_size; ++ ++ usbs_imx_otg_dev_set_configuration(&config_data); ++ } ++ ++ /* Send Ack to Host*/ ++ usbs_status_phase(CONTROL,IN); ++ ++ g_usb_dev_state = USB_DEV_CONFIGURED_STATE ; ++ } ++ else ++ { ++ /* Invalid configuration value. Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ //USBDBGMSG("+USBDBGMSG:EP0 IN stalled at set conf in addr state\n"); ++ } ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set conf@ADDRESSED_STATE\n"); ++ break; ++ case USB_DEV_CONFIGURED_STATE : ++ if(g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_CONFIG_DESC_CONFIG_VALUE) ++ { ++ /* Send Ack to Host*/ ++ usbs_status_phase(CONTROL,IN); ++ } ++ else if (g_usb_setup_data[WVALUE_LOWBYTE] == USB_DEV_VALUE_OF_UNCONFIG) ++ { ++ /* Send Ack to Host*/ ++ usbs_status_phase(CONTROL,IN); ++ ++ /* Change USB State to Addressed State */ ++ g_usb_dev_state = USB_DEV_ADDRESSED_STATE; ++ } ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set conf@CONFIGURED_STATE\n"); ++ break; ++ default : ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set conf@incorrect state\n"); ++ break; ++ } ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: enum - set config handler\n"); ++} ++/*============================================================================= ++FUNCTION: usbs_handle_msc_get_maxlun ++DESCRIPTION: This function Handle the GET MAX LUN Mass Storage class ++ specific request ++ARGUMENTS PASSED: None ++RETURN VALUE: None ++IMPORTANT NOTES: None ++=============================================================================*/ ++static void ++usbs_handle_msc_get_maxlun(void) ++{ ++ usb_buffer_descriptor_t bd ; ++ cyg_uint32 buffer_addrs; ++ cyg_uint16 desc_length = 0x0; ++ cyg_uint8 zlt = 0;//0 means false ++ cyg_uint8 Max_Lun=0; ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: MASS - Get MAX LUN\n"); ++ ++ /* get the buffer address for data transfer over EP0 */ ++ buffer_addrs = g_bulkbuffer_map.ep0_buffer_addrs; //256bytes before the two Bulk buffers ++ ++ /* Get the length of descriptor requested */ ++ desc_length = g_usb_setup_data[WLENGTH_LOWBYTE]; ++ desc_length |= ( g_usb_setup_data[WLENGTH_HIGHBYTE] <<0x8); ++ ++ /* If requested length of descriptor is zero*/ ++ if(desc_length==0) ++ { ++ /* Fill the buffer with the descriptor data */ ++ *(cyg_uint8 *)buffer_addrs = 0;//Max_Lun; ++ bd.size = 0; ++ } ++ else ++ { ++ /* Fill the buffer with the descriptor data */ ++ *(cyg_uint8 *)buffer_addrs = Max_Lun; ++ bd.size = desc_length; ++ } ++ ++ /* Send descriptor - Data Phase*/ ++ usbs_ep0_send_data(&bd,zlt); //zlt is false=>not zero length packet ++ //send dev descriptor to host. ++ ++ /* Status Phase -- OUT */ ++ usbs_status_phase(CONTROL,OUT); //Get Zero-length data packet from Host, Device sends status: ACK(success), NAK(busy), or STALL(failed) ++ ++ ++} ++/*============================================================================= ++FUNCTION: usbs_ep0in_fill_buffer ++DESCRIPTION: This function is used to fill the corresponding ++ response for the data phase of SETUP Transfer ++ARGUMENTS PASSED: ++ cyg_uint8 type: type of descriptor ++ cyg_uint32 buffer_addrs - buffer pointer to be filled ++RETURN VALUE: None ++IMPORTANT NOTES:None ++=============================================================================*/ ++static void ++usbs_ep0in_fill_buffer(cyg_uint8 type, cyg_uint32 buffer_addrs) ++{ ++ const cyg_uint8 *data=0; ++ cyg_uint32 *buffer_page = (cyg_uint32*)buffer_addrs; ++ int k = 0; ++ //USBDBGMSG("+USBDBGMSG: enum - copy descriptor to buffer\n"); ++ switch (type) ++ { ++ case FILL_DEVICE_DESC: /*5*32 bit */ ++ data = (cyg_uint8 *)g_usb_desc.device_desc; ++ break; ++ case FILL_CONF_DESC: /*8*32 bit */ ++ data = (cyg_uint8 *)g_usb_desc.config_desc; ++ break; ++ case FILL_STR_DES0: /*1*32 bit */ ++ data = (cyg_uint8 *)g_usb_desc.str_desc0; ++ break; ++ case FILL_STR_DES1: /*7*32 bit */ ++ data =(cyg_uint8 *)g_usb_desc.str_desc1; ++ break; ++ case FILL_STR_DES2: /*7*32 bit */ ++ data = (cyg_uint8 *)g_usb_desc.str_desc2; ++ break; ++ case FILL_STR_DES3: /*6*32 bit */ ++ data = (cyg_uint8 *)g_usb_desc.str_desc3; ++ break; ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ case FILL_SN_DESC: ++ data = (cyg_uint8 *)g_usb_desc.sn_desc; ++ break; ++ #endif ++ } ++ ++ for (k=0; k<(MPS_64/sizeof(cyg_uint32)); k++) ++ { ++ *buffer_page = data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24); ++ //USBDBGMSG("+USBDBGMSG: desc[k] = 0x%x\n",(*buffer_page)); ++ buffer_page++; ++ data += 4; ++ ++ } ++ ++ ++} ++ ++/*============================================================================= ++FUNCTION: usbs_ep0_init_dqh ++DESCRIPTION: This function is used to initialize the queue header of EP0 ++ARGUMENTS PASSED: NONE ++RETURN VALUE: NONE ++IMPORTANT NOTES: called by usbs_imx_otg_dev_ep0_init(),usbs_imx_otg_dev_handle_bus_reset() ++=============================================================================*/ ++static void ++usbs_ep0_init_dqh(void) ++{ ++ struct dqh_t qhead; ++ cyg_uint32 total_bytes; ++ volatile cyg_uint32 * ep_q_hdr_base; ++ cyg_int8 i; ++ ++ //clear queue header ++ ep_q_hdr_base = ((volatile cyg_uint32 *)g_bulkbuffer_map.ep_dqh_base_addrs); ++ /* Clear the dQH Memory */ ++ for ( i = 0; i < (SIZE_OF_QHD*g_max_ep_supported*2)/sizeof(cyg_uint32) ; i++) ++ { ++ *ep_q_hdr_base++ = 0; ++ } ++ ++ /****************************************************************************** ++ / ================= ++ / dQH0 for EP0OUT ++ / ================= ++ / Initialize device queue heads in system memory ++ / 8 bytes for the 1st setup packet */ ++ ++ total_bytes = 0x8; ++ qhead.dqh_base = USBS_EP_GET_dQH(EP0,OUT); ++ qhead.zlt = ZLT_DISABLE; ++ qhead.mps = MPS_64; ++ qhead.ios = IOS_SET; ++ qhead.next_link_ptr = USBS_EP_GET_dTD(EP0,OUT); ++ qhead.terminate = NOT_TERMINATE; ++ qhead.total_bytes = total_bytes; ++ qhead.ioc = IOC_SET; ++ qhead.status = NO_STATUS; ++ qhead.buffer_ptr0 = 0; ++ qhead.current_offset= 0; ++ qhead.buffer_ptr1 = 0; ++ qhead.buffer_ptr2 = 0; ++ qhead.buffer_ptr3 = 0; ++ qhead.buffer_ptr4 = 0; ++ /* Set Device Queue Head */ ++ usbs_setup_queuehead(&qhead); ++ ++ /* ================== ++ END of dQH0 setup ++ ====================*/ ++ /*================= ++ dQH1 for EP0IN ++ ================= */ ++ ++ total_bytes = 0x8; ++ qhead.dqh_base = USBS_EP_GET_dQH(EP0,IN); ++ qhead.zlt = ZLT_DISABLE; ++ qhead.mps = MPS_64; ++ qhead.ios = IOS_SET; ++ qhead.next_link_ptr = USBS_EP_GET_dTD(EP0,IN); ++ qhead.terminate = TERMINATE; ++ qhead.total_bytes = total_bytes; ++ qhead.ioc = IOC_SET; ++ qhead.status = NO_STATUS; ++ qhead.buffer_ptr0 = g_bulkbuffer_map.ep0_buffer_addrs; ++ qhead.current_offset= (g_bulkbuffer_map.ep0_buffer_addrs & 0xFFF); ++ qhead.buffer_ptr1 = 0; ++ qhead.buffer_ptr2 = 0; ++ qhead.buffer_ptr3 = 0; ++ qhead.buffer_ptr4 = 0; ++ ++ /* Set Device Queue Head */ ++ usbs_setup_queuehead(&qhead); ++ ++ /* ================== ++ / END of dQH1 setup ++ / ================*/ ++} ++/*============================================================================= ++FUNCTION: usbs_ep0_send_data ++DESCRIPTION: This function Send Data to host through EP0-IN Pipe. ++ARGUMENTS PASSED: ++ usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor. ++ cyg_uint8 zlt : Flag to decide if Zero Length Packet to be sent ++RETURN VALUE: ++ USB_SUCCESS - The buffer was successfully processed by the USB device and ++ data sent to the Host. ++ USB_FAILURE - Some failure occurred in transmitting the data. ++IMPORTANT NOTES: None ++=============================================================================*/ ++static usb_status_t ++usbs_ep0_send_data(usb_buffer_descriptor_t* bd,cyg_uint8 zlt) ++{ ++ struct dtd_t td; ++ cyg_uint32 total_bytes ; ++ cyg_uint32 dtd_address,dqh_address; ++ ++ usb_status_t status = USB_FAILURE; ++ ++ /* Get Device Transfer Descriptor of the requested endpoint */ ++ dtd_address = USBS_EP_GET_dTD(EP0,IN); ++ ++ /* Get Device Queue head of the requested endpoint */ ++ dqh_address = USBS_EP_GET_dQH(EP0,IN); ++ ++ /* Get Total Bytes to Be recieved */ ++ total_bytes = bd->size; ++ ++ /* Setup Transfer Descriptor for EP0 IN*/ ++ td.dtd_base = dtd_address; ++ td.next_link_ptr = 0; ++ td.terminate = TERMINATE; ++ td.total_bytes = total_bytes; ++ td.ioc = IOC_SET; ++ td.status = ACTIVE; ++ td.buffer_ptr0 = g_bulkbuffer_map.ep0_buffer_addrs; ++ td.current_offset = (g_bulkbuffer_map.ep0_buffer_addrs & 0xFFF); ++ td.buffer_ptr1 = 0; ++ td.buffer_ptr2 = 0; ++ td.buffer_ptr3 = 0; ++ td.buffer_ptr4 = 0; ++ ++ /* Set the transfer descriptor */ ++ usbs_setup_transdesc(&td); ++ ++ /* Enable ZLT when data size is in multiple of Maximum Packet Size */ ++ if(zlt) ++ { ++ /* set ZLT enable */ ++ (*(volatile cyg_uint32*)(dqh_address)) &= ~0x20000000; ++ } ++ ++ /* 1. write dQH next ptr and dQH terminate bit to 0 */ ++ *(volatile cyg_uint32*)(dqh_address+0x8)= (dtd_address); ++ ++ /* 2. clear active & halt bit in dQH */ ++ *(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME */ ++ usbs_imx_otg_base->endptprime |= BIT16; ++ ++ /* wait for complete set and clear */ ++ while (!(usbs_imx_otg_base->endptcomplete & EPIN_COMPLETE)); ++ ++ usbs_imx_otg_base->endptcomplete = EPIN_COMPLETE; ++ ++ status = USB_SUCCESS; ++ ++ return status; ++} ++/*============================================================================= ++FUNCTION: usbs_ep0_recevie_data ++DESCRIPTION: This function Handle the Status Token (IN/OUT) from USB Host ++ARGUMENTS PASSED: ++ usb_buffer_descriptor_t *bd : This is the pointer to the buffer descriptor. ++RETURN VALUE: ++ USB_SUCCESS - : The buffer was successfully processed by the USB device and ++ data is received from the host. ++ USB_FAILURE - : Some failure occurred in receiving the data. ++ USB_INVALID - : If the endpoint is invalid. ++IMPORTANT NOTES:None ++=============================================================================*/ ++static usb_status_t usbs_ep0_receive_data(usb_buffer_descriptor_t* bd) ++{ ++ struct dtd_t td; ++ usb_status_t status = USB_FAILURE; ++ cyg_uint32 total_bytes; ++ cyg_uint32 dtd_address; ++ cyg_uint32 dqh_address; ++ ++ /* Get Device Device Queue Head of the requested endpoint */ ++ dqh_address = USBS_EP_GET_dQH(EP0, OUT); ++ ++ /* Get Device Transfer Descriptor of the requested endpoint */ ++ dtd_address = USBS_EP_GET_dTD(EP0, OUT); ++ ++ /* Get the total bytes to be received */ ++ total_bytes = bd->size; ++ ++ td.dtd_base = dtd_address; ++ td.next_link_ptr = dtd_address + 0x20; ++ td.terminate = TERMINATE; ++ td.total_bytes = total_bytes; ++ td.ioc = IOC_SET; ++ td.status = ACTIVE; ++ td.buffer_ptr0 = g_bulkbuffer_map.ep0_buffer_addrs; ++ td.current_offset = (g_bulkbuffer_map.ep0_buffer_addrs & 0xFFF); ++ td.buffer_ptr1 = 0; ++ td.buffer_ptr2 = 0; ++ td.buffer_ptr3 = 0; ++ td.buffer_ptr4 = 0; ++ ++ /* Set the Transfer Descriptor */ ++ usbs_setup_transdesc(&td); ++ ++ /* 1. write dQH next ptr and dQH terminate bit to 0 */ ++ *(volatile cyg_uint32*)(dqh_address+0x8)= dtd_address; ++ ++ /* 2. clear active & halt bit in dQH */ ++ *(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME */ ++ usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << EP0 ); ++ ++ /* 4. Wait for the Complete Status */ ++ while (!((usbs_imx_otg_base->endptprime) & ( EPOUT_COMPLETE << EP0))); ++ ++ /*clear the complete status */ ++ usbs_imx_otg_base->endptprime = (EPOUT_COMPLETE << EP0); ++ ++ status = USB_SUCCESS; ++ ++ return status; ++} ++// **************************************************************************** ++// -----------------------Endpoint 0 Functions--------------------------------- ++// **************************************************************************** ++/*============================================================================= ++// This is where all the hard work happens. It is a very large routine ++// for a DSR, but in practice nearly all of it is nested if's and very ++// little code actually gets executed. Note that there may be ++// invocations of callback functions and the driver has no control ++// over how much time those will take, but those callbacks should be ++// simple. ++// so far, ep0 DSR works only during enumeration here. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_ep0_dsr(void) ++{ ++ usb_buffer_descriptor_t bd ; ++ usb_status_t status = USB_FAILURE; ++ volatile struct dqh_setup_t * dqh_word ; ++ cyg_uint32 dqh_address; ++ cyg_uint32 temp; ++ ++ //USBDBGMSG("+USBDBGMSG: enter ep0 dsr.\n"); ++ /* 1. Receive Setup Data*/ ++ bd.buffer = (cyg_uint32 *)g_usb_setup_data; ++ bd.size = 0; ++ ++ /* Get the Device Queue Head Address for EP0 OUT */ ++ dqh_address = USBS_EP_GET_dQH(EP0,OUT); ++ dqh_word = (volatile struct dqh_setup_t*)dqh_address; ++ ++ /* write '1' to clear corresponding bit in ENDPTSETUPSTAT */ ++ temp = usbs_imx_otg_base->endptsetupstat; ++ usbs_imx_otg_base->endptsetupstat = temp; ++ ++// if(usbs_imx_otg_base->endptsetupstat & BIT0) ++// usbs_imx_otg_base->endptsetupstat = BIT0; ++ ++ do{ ++ /* write '1' to Setup Tripwire (SUTW) in USBCMD register */ ++ usbs_imx_otg_base->usbcmd |= BIT13; ++ ++ /* Copy the SetupBuffer into local software byte array */ ++ temp = (dqh_word->dqh_word10); ++ ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )(temp & 0x000000FF); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0x0000FF00)>>8); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0x00FF0000)>>16); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0xFF000000)>>24); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ ++ temp = (dqh_word->dqh_word11); ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )(temp & 0x000000FF); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0x0000FF00)>>8); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0x00FF0000)>>16); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ *((cyg_uint8 *)(bd.buffer)) = (cyg_uint8 )((temp & 0xFF000000)>>24); ++ (bd.buffer) =(cyg_uint8 *)(bd.buffer) + 1; ++ }while (!(usbs_imx_otg_base->usbcmd & BIT13)); ++ ++ /* Write '0' to clear SUTW in USBCMD register */ ++ usbs_imx_otg_base->usbcmd &= ~BIT13; ++ status = USB_SUCCESS; ++ ++ #if 0 ++ USBDBGMSG("+USBDBGMSG: setup packet:(LSB)"); ++ for(temp=0;temp<8;temp++) ++ { ++ USBDBGMSG("%02X",g_usb_setup_data[temp]); ++ } ++ USBDBGMSG("(MSB)\n"); ++ #endif ++ ++ /* 2. Process Setup Data*/ ++ /* switch construct to handle different request*/ ++ /* Parser the Setup Request Type */ ++ switch (g_usb_setup_data[BREQUEST]) ++ { ++ case USB_GET_DESCRIPTOR: ++ /* Handle the GET DESCRIPTOR Request */ ++ usbs_handle_get_descriptor(); ++ break; ++ ++ case USB_SET_ADDRESS: ++ /* Handle the SET ADDRESS Request */ ++ usbs_handle_set_address(); ++ break; ++ ++ case USB_SET_CONFIGURATION: ++ /* Handle the SET CONFIGURATION Request */ ++ if ((g_usb_setup_data[WINDEX_LOWBYTE] == 0) && ++ (g_usb_setup_data[WINDEX_HIGHBYTE] == 0)&& ++ (g_usb_setup_data[WLENGTH_LOWBYTE] == 0)&& ++ (g_usb_setup_data[WLENGTH_HIGHBYTE] == 0)&& ++ (g_usb_setup_data[WVALUE_HIGHBYTE] == 0)) ++ { ++ usbs_handle_set_configuration(); ++ } ++ else ++ { ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ //USBDBGMSG("+USBDBGMSG:EP0 IN stalled at set conf in ep0 dsr\n"); ++ } ++ break; ++ ++ case USB_GET_CONFIGURATION: ++ /* GET CONFIGURATION request handler */ ++ usbs_handle_get_configuration(); ++ break; ++ case USB_MSC_GET_MAX_LUN: ++ usbs_handle_msc_get_maxlun(); ++ break; ++ case USB_MSC_BOT_RESET: ++ ++ default: ++ /* Send STALL Handshake */ ++ usbs_endpoint_stall(EP0,IN); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG:EP0 IN stalled in ep0 dsr\n"); ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG:Setup Request Type 0x%02x,0x%02X\n",g_usb_setup_data[BMREQUESTTYPE],g_usb_setup_data[BREQUEST]); ++ break; ++ } ++ ++ USBDBGMSG(DEBUG_ENUM,"+USBDBGMSG: ep0 dsr\n"); ++} ++/*============================================================================= ++// Endpoint 0 initialization. ++// Control Endpoint, bi-direction ++// This may get called during system start-up or following a reset ++// from the host. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_ep0_init(void) ++{ ++ /*initialize Endpoint 0 Queue Header*/ ++ usbs_ep0_init_dqh(); ++ ++ { ++ /*fill the structure for ep0*/ ++ if ((EP0_STATE_IDLE != ep0.ep_state) && ++ ((usbs_control_return (*)(usbs_control_endpoint*, int)) 0 != ep0.common.complete_fn)) ++ { ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ (*ep0.common.complete_fn)(&ep0.common, -EPIPE); ++ #endif ++ } ++ ep0.common.state = USBS_STATE_POWERED; ++ memset(ep0.common.control_buffer, 0, 8); ++ ep0.common.buffer = (unsigned char*) 0; ++ ep0.common.buffer_size = 0; ++ ep0.common.fill_buffer_fn = (void (*)(usbs_control_endpoint*)) 0; ++ ep0.common.fill_data = (void*) 0; ++ ep0.common.fill_index = 0; ++ ep0.common.complete_fn = (usbs_control_return (*)(usbs_control_endpoint*, int)) 0; ++ ep0.ep_state = EP0_STATE_IDLE; ++ ep0.length = 0; ++ ep0.transmitted = 0; ++ } ++} ++// ---------------------------------------------------------------------------- ++/*============================================================================= ++// The start function is called by higher-level code when things have ++// been set up, i.e. the enumeration data is available, appropriate ++// handlers have been installed for the different types of control ++// messages, and communication with the host is allowed to start. The ++// next event that should happen is a reset operation from the host, ++// so all other interrupts should be blocked. However it is likely ++// that the hardware will detect a suspend state before the reset ++// arrives, and hence the reset will act as a resume as well as a ++// reset. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_ep0_start(usbs_control_endpoint* endpoint) ++{ ++ cyg_uint32 temp; ++ ++ CYG_ASSERT( endpoint == &ep0.common, "USB startup involves the wrong endpoint"); ++ ++ /*clear all interrupt status bits*/ ++ temp = usbs_imx_otg_base->usbsts; ++ usbs_imx_otg_base->usbsts = temp; //clear all the previous interrupts ++ ++ /*enable all the sub-interrupt sources for USB device*/ ++ USBS_IMX_OTG_INTR_UNMASK(IMX_USB_INTR_DEV_PCE|IMX_USB_INTR_DEV_RESET|IMX_USB_INTR_DEV_USBINT); ++ ++ /*set Run/Stop bit to Run Mode*/ ++ usbs_imx_otg_base->usbcmd |= BIT0; ++ ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: mx37 ep0 start.\n"); ++} ++// **************************************************************************** ++// -----------------------Endpoint 1 Functions--------------------------------- ++// **************************************************************************** ++/*============================================================================= ++// Complete a transfer. This takes care of invoking the completion ++// callback and resetting the buffer. ++=============================================================================*/ ++static void ++ep1_rx_complete(int result) ++{ ++ //cyg_uint32 total_bytes; ++ cyg_uint32 dtd_address; ++ cyg_uint32 dqh_address; ++ cyg_uint32 received_buffer_addrs = 0x0; ++ cyg_uint32 received_data_length = 0x0; ++ cyg_uint32* temp = 0x0; ++ ++ int i; ++ ++ if(g_usb_dev_state != USB_DEV_CONFIGURED_STATE) ++ return; //EP1 only receives data when the USB device has been configured ++ ++ if(ep1.common.buffer == NULL) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: NULL buffer \n"); ++ return; //there is not a buffer used to store the data from host ++ } ++ ++ /* Get Device Device Queue Head of the out endpoint */ ++ dqh_address = USBS_EP_GET_dQH(EP1,OUT); ++ ++ /* Get Device Transfer Descriptor of the out endpoint */ ++ dtd_address = USBS_EP_GET_dTD(EP1,OUT); ++ ++ /*clear the complete status */ ++ usbs_imx_otg_base->endptcomplete |= (EPOUT_COMPLETE << EP1); ++ ++ //received_buffer_addrs = (*((unsigned int *)dtd_address + 2)) & 0xFFFFF000; ++ received_buffer_addrs = (cyg_uint32)ep1.common.buffer; ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: received_buffer_addrs 0x%08X \n",received_buffer_addrs); ++ if( received_buffer_addrs == 0) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: NULL rx buffer \n"); ++ return; ++ } ++ ++ /* calculate the received data length using number of bytes left in TD */ ++ temp = (cyg_uint32 *)dtd_address; ++ temp++; //pointer to total bytes in dtd, second work in dTD ++ received_data_length = (ep1.common.buffer_size - (((*temp) >> 16 )&0x7FFF)); //recevied data length <= BULK_TD_BUFFER_TOTAL_SIZE ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: received length %d \n",received_data_length); ++ #if 0 ++ /* Check if the received packet is SCSI WRITE, if yes, assign the TD buffer offset ++ is zero, otherwise, one. This is a bug in MX37 USB OTG */ ++ if((received_data_length==31)&&(*(destination_ptr+0xF)==0x2A))//WRITE10 received ++ { ++ g_bulk_out_transdesc_buffer_offset = 0; ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_start_rx - set offset to zero \n"); ++ } ++ ++ else if((g_bulk_out_sector_number_is_one == 1)&&(received_data_length!=31)) //last bulk out data sector ++ g_bulk_out_transdesc_buffer_offset = 1; ++ #endif ++ ++ /* tell ep1 how many bytes data is received*/ ++ ep1.fetched = received_data_length; ++ ++ if(ep1.fetched) ++ { ++ if(ep1.fetched == 31) ++ g_received_data_type = MASS_STORAGE_CBW_TYPE; ++ else ++ g_received_data_type = MASS_STORAGE_DATA_TYPE; ++ ep1.common.complete_data = (void*)(ep1.common.buffer); ++ ++ #if 0 ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete: \n"); ++ USBDBGMSG(DEBUG_TRANS,"----Dump Bulk-Out Recevied Data----\n"); ++ for(i=0;i<32;i++) ++ { ++ USBDBGMSG(DEBUG_TRANS,"%02X ", *((cyg_uint8 *)(ep1.common.complete_data)+i)); ++ } ++ USBDBGMSG(DEBUG_TRANS,"\n"); ++ #endif ++ //USB_IMX_SET_TD_OFFSET(g_td_buffer_offset, 0); ++ ep1.common.buffer = (unsigned char*) 0; ++ ep1.common.buffer_size = 0; ++ ep1_start_rx((usbs_rx_endpoint *)(&(ep1.common))); //prevent to receive more CBW before processing done ++ } ++ ++ #if 0 ++ if(ep1.fetched == 31) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_rx_complete - recevied data: \n"); ++ for(i=0;i<32;i++) ++ { ++ USBDBGMSG(DEBUG_TRANS,"%02X ", *((cyg_uint8 *)(ep1.common.complete_data)+i)); ++ } ++ USBDBGMSG(DEBUG_TRANS,"\n"); ++ ++ for(i=0;i<32;i++) ++ { ++ USBDBGMSG(DEBUG_TRANS,"%02X ", *((cyg_uint8 *)received_buffer_addrs+i)); ++ } ++ USBDBGMSG(DEBUG_TRANS,"\n"); ++ } ++ #endif ++ ++ ++} ++/*============================================================================= ++// Start to receive data from host. This functionality is overloaded to cope with ++// waiting for stalls to complete. ++// The transfer descriptor is prepared ++=============================================================================*/ ++static void ++ep1_start_rx(usbs_rx_endpoint* endpoint) ++{ ++ struct dtd_t td; ++ cyg_uint32 total_bytes; ++ cyg_uint32 dtd_address; ++ cyg_uint32 dqh_address; ++ cyg_uint32 buffer_addrs_page0; ++ ++ if(g_usb_dev_state != USB_DEV_CONFIGURED_STATE) ++ return; //EP1 only receives data when the USB device has been configured ++ #if 0 //don't check to prevent EP1 from receiving data before processing the previous. ++ if(endpoint->buffer == NULL) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1_start_rx: NULL buffer \n"); ++ return; //there is not a buffer used to store the data from host ++ } ++ #endif ++ /* Get Device Device Queue Head of the out endpoint */ ++ dqh_address = USBS_EP_GET_dQH(EP1,OUT); ++ ++ /* Get Device Transfer Descriptor of the out endpoint */ ++ dtd_address = USBS_EP_GET_dTD(EP1,OUT); ++ ++ /* ==Prepare TD for next bulk out transfer== */ ++ /* get the dTD buffer pointer */ ++ buffer_addrs_page0 = (cyg_uint32)(endpoint->buffer); ++ ++ /* Get the total bytes to be received */ ++ total_bytes = endpoint->buffer_size; ++ ++ /* OUT setup dTD */ ++ td.dtd_base = dtd_address; ++ td.next_link_ptr = dtd_address + 0x20; ++ td.terminate = TERMINATE; ++ td.total_bytes = total_bytes; ++ td.ioc = IOC_SET; ++ td.status = ACTIVE; ++ td.buffer_ptr0 = buffer_addrs_page0 ; ++ td.current_offset = ( buffer_addrs_page0 & 0xFFF ) + g_td_buffer_offset; ++ td.buffer_ptr1 = 0; ++ td.buffer_ptr2 = 0; ++ td.buffer_ptr3 = 0; ++ td.buffer_ptr4 = 0; ++ ++ /* re-define the buffer page pointers based on the total_bytes*/ ++ if(total_bytes > BULK_TD_BUFFER_PAGE_SIZE) ++ td.buffer_ptr1 = (td.buffer_ptr0 + BULK_TD_BUFFER_PAGE_SIZE); ++ if(total_bytes > BULK_TD_BUFFER_PAGE_SIZE*2) ++ td.buffer_ptr2 = (td.buffer_ptr1 + BULK_TD_BUFFER_PAGE_SIZE); ++ if(total_bytes > BULK_TD_BUFFER_PAGE_SIZE*3) ++ td.buffer_ptr3 = (td.buffer_ptr2 + BULK_TD_BUFFER_PAGE_SIZE); ++ ++ /* Set the Transfer Descriptor */ ++ usbs_setup_transdesc(&td); ++ ++ /* 1. write dQH next ptr and dQH terminate bit to 0 */ ++ *(volatile cyg_uint32 *)(dqh_address+0x8)= dtd_address; ++ ++ /* 2. clear active & halt bit in dQH */ ++ *(volatile cyg_uint32 *)(dqh_address+0xC) &= ~0xFF; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME ++ prime bulk out endpoint after sending the CSW of last command ++ */ ++ //usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << EP1 ); ++ ++} ++/*============================================================================= ++// The exported interface to halt the EP1 ++=============================================================================*/ ++static void ++ep1_set_halted(usbs_rx_endpoint* endpoint, cyg_bool new_value) ++{ ++ if (ep1.common.halted == new_value) { ++ return; ++ } ++ if (new_value) { ++ // The endpoint should be stalled. There is a potential race ++ // condition here with the current transfer and DSR invocation. ++ // Updating the stalled flag means that the DSR will do nothing. ++ usbs_endpoint_stall(EP1,OUT); ++ ep1.common.halted = 1; ++ } ++ else { ++ // Take care of the hardware so that a new transfer is allowed. ++ usbs_endpoint_unstall(EP1,OUT); ++ ep1.common.halted = 0; ++ } ++ ++} ++/*============================================================================= ++// The DSR is invoked following an interrupt. According to the docs an ++// endpoint 1 interrupt can only happen if the receive-packet-complete ++// bit is set. ++// [Note] EP1 DSR is only used to receive the command block wrapper from host ++// to USB mass storage device ++=============================================================================*/ ++ ++static void ++usbs_imx_otg_dev_ep1_dsr(void) ++{ ++ int result = 0; //contains the actual recevied data length from bulk-out endpoint ++ g_received_data_type = 0;//MASS_STORAGE_CBW_TYPE ++ ++ if(ep1.common.buffer)//buffer of TD is not null, then receive ++ { ++ ep1_rx_complete(result); ++ } ++ //USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - result = %d\n",result); ++ //recevie mass storage device CBW ++ ++ if((ep1.fetched == 31)&&(g_received_data_type == MASS_STORAGE_CBW_TYPE)) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - CBW received\n"); ++ //post the semaphore of MSC command handler thread ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ cyg_semaphore_post(&usbs_msc_sem); ++ #endif ++ ep1.fetched = 0; ++ } ++ else ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep1 dsr - received %d byte\n",ep1.fetched); ++ ++} ++ ++/*============================================================================= ++// Endpoint 1 initialization. ++// Bulk-OUT Endpoint ++// This may get called during system start-up or following a reset ++// from the host. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_ep1_init(void) ++{ ++ //at present, ep1.common.buffer is NULL. The buffer should be initialized ++ //by upper layer caller. ++ /*buffer is assigned in MSC initialization*/ ++ ++ // Endpoints should never be halted during a start-up. ++ ep1.common.halted = 0; //false =0, true =1 ++ ep1.common.complete_fn = ep1_rx_complete; ++ // If there has been a reset and there was a receive in progress, ++ // abort it. This also takes care of sorting out the endpoint ++ // fields ready for the next rx. ++ ep1_rx_complete(-EPIPE); ++} ++ ++// **************************************************************************** ++// -----------------------Endpoint 2 Functions--------------------------------- ++// **************************************************************************** ++/*============================================================================= ++// A utility routine for completing a transfer. This takes care of the ++// callback as well as resetting the buffer. ++=============================================================================*/ ++static void ++ep2_tx_complete(int result) ++{ ++ void (*complete_fn)(void*, int) = ep2.common.complete_fn; ++ void* complete_data = ep2.common.complete_data; ++ ++ ep2.common.buffer = (unsigned char*) 0; ++ ep2.common.buffer_size = 0; ++ ep2.common.complete_fn = (void (*)(void*, int)) 0; ++ ep2.common.complete_data = (void*) 0; ++ ++ if ((void (*)(void*, int))0 != complete_fn) { ++ (*complete_fn)(complete_data, result); ++ } ++} ++ ++/*============================================================================= ++// The exported interface to start to transmit data to Host ++=============================================================================*/ ++static void ++ep2_start_tx(usbs_tx_endpoint* endpoint) ++{ ++ int timeout = 400; ++ struct dtd_t td; ++ cyg_uint32 total_bytes ; ++ cyg_uint32 dtd_address,dqh_address; ++ cyg_uint32 buffer_addrs_page0; ++ cyg_uint32 size = 0x0; ++ ++ /* Get Device Transfer Descriptor of the requested endpoint */ ++ dtd_address = USBS_EP_GET_dTD(EP2,IN); ++ ++ /* Get Device Queue head of the requested endpoint */ ++ dqh_address = USBS_EP_GET_dQH(EP2,IN); ++ ++ /* allocate memory for data transfer */ ++ buffer_addrs_page0 = endpoint->buffer; ++ ++ if(buffer_addrs_page0 == 0) ++ { ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep2_start_tx: NULL tx buffer \n"); ++ return; ++ } ++ ++ total_bytes = (cyg_uint32)(endpoint->buffer_size); ++ size = (total_bytes < BULK_TD_BUFFER_TOTAL_SIZE )?total_bytes:(BULK_TD_BUFFER_TOTAL_SIZE); ++ ++ td.dtd_base = dtd_address; ++ td.next_link_ptr = dtd_address + 0x20 ; ++ td.terminate = TERMINATE; ++ td.total_bytes = size; ++ td.ioc = IOC_SET; ++ td.status = ACTIVE; ++ td.buffer_ptr0 = buffer_addrs_page0 ; ++ td.current_offset = (buffer_addrs_page0 & 0xFFF)+ g_td_buffer_offset; ++ td.buffer_ptr1 = 0; ++ td.buffer_ptr2 = 0; ++ td.buffer_ptr3 = 0; ++ td.buffer_ptr4 = 0; ++ ++ /* re-define the buffer page pointers based on the total_bytes*/ ++ if(size > BULK_TD_BUFFER_PAGE_SIZE) ++ td.buffer_ptr1 = (td.buffer_ptr0 + BULK_TD_BUFFER_PAGE_SIZE); ++ if(size > BULK_TD_BUFFER_PAGE_SIZE*2) ++ td.buffer_ptr2 = (td.buffer_ptr1 + BULK_TD_BUFFER_PAGE_SIZE); ++ if(size > BULK_TD_BUFFER_PAGE_SIZE*3) ++ td.buffer_ptr3 = (td.buffer_ptr2 + BULK_TD_BUFFER_PAGE_SIZE); ++ ++ /* Set the Transfer Descriptor */ ++ usbs_setup_transdesc(&td); ++ ++ /* 1. write dQH next ptr and dQH terminate bit to 0 */ ++ *(volatile cyg_uint32 *)(dqh_address+0x8)= (dtd_address); ++ ++ /* 2. clear active & halt bit in dQH */ ++ *(volatile cyg_uint32 *)(dqh_address+0xC) &= ~0xFF; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME */ ++ usbs_imx_otg_base->endptprime = ( EPIN_PRIME << EP2 ); ++ ++ /* wait for complete set and clear */ ++ while (!((usbs_imx_otg_base->endptcomplete) & (EPIN_COMPLETE<endptcomplete |= (EPIN_COMPLETE << EP2); ++ ++ ep2.transmitted = size; ++ ++ ep2_tx_complete(-EPIPE); ++ ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep2 tx done\n");// ep2.transmitted); ++ ++} ++/*============================================================================= ++// The exported interface to halt the EP2 ++=============================================================================*/ ++static void ++ep2_set_halted(usbs_tx_endpoint* endpoint, cyg_bool new_value) ++{ ++ if (ep2.common.halted == new_value) { ++ return; ++ } ++ if (new_value) { ++ // The endpoint should be stalled. There is a potential race ++ // condition here with the current transfer and DSR invocation. ++ // Updating the stalled flag means that the DSR will do nothing. ++ usbs_endpoint_stall(EP2,IN); ++ ep2.common.halted = 1; ++ } ++ else { ++ // Take care of the hardware so that a new transfer is allowed. ++ usbs_endpoint_unstall(EP2,IN); ++ ep2.common.halted = 0; ++ } ++} ++/*============================================================================= ++// The dsr will be invoked when the transmit-packet-complete bit is ++// set. Typically this happens when a packet has been completed ++=============================================================================*/ ++ ++static void ++usbs_imx_otg_dev_ep2_dsr(void) ++{ ++ USBDBGMSG(DEBUG_TRANS,"+USBDBGMSG: ep2 dsr\n"); ++ /* EP2 DSR will be called as soon as a transfer complete to clear status*/ ++ usbs_imx_otg_base->endptcomplete |= (EPIN_COMPLETE << EP2); ++ ++ ++ if(ep2.common.buffer_size==0) ++ { ++ ep2_tx_complete(-EPIPE); ++ ep2.transmitted = 0; //clear the field to wait for the next transmit ++ } ++ ++} ++ ++/*============================================================================= ++// Endpoint 2 initialization. ++// Bulk-IN Endpoint ++// This may be called during system start-up or following a reset ++// from the host. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_ep2_init(void) ++{ ++ //at initialization, ep2.common.buffer is NULL. The buffer should be initialized ++ //by upper layer caller. ++ ++ // Endpoints should never be halted after a reset ++ ep2.common.halted = false; ++ ++ // If there has been a reset and there was a receive in progress, ++ // abort it. This also takes care of clearing the endpoint ++ // structure fields. ++ ep2_tx_complete(-EPIPE); ++} ++ ++// **************************************************************************** ++// -----------------------MX37 USB Device Driver API Functions----------------- ++// **************************************************************************** ++ ++/*============================================================================= ++// The DSR. This can be invoked directly by poll(), or via the usual ++// interrupt subsystem. It acts as per the current value of ++// g_isr_status_bits. If another interrupt goes off while this ++// DSR is running, there will be another invocation of the DSR and ++// the status bits will be updated. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ int status = 0; ++ cyg_uint32 temp; ++ CYG_ASSERT(MX51_IRQ_USB_SERVICE_REQUEST == vector, "USB DSR should only be invoked for USB interrupts" ); ++ CYG_ASSERT(0 == data, "The i.MX37 USB DSR needs no global data pointer"); ++ //USBDBGMSG("+USBDBGMSG: enter mx37 dsr\n"); ++ // There is no atomic swap support, so interrupts have to be ++ // blocked. It might be possible to do this via the USBS_CONTROL ++ // register, but at the risk of messing up the status register ++ // if another interrupt comes in. Blocking interrupts at the ++ // processor level is less intrusive on the USB code. ++ //cyg_drv_isr_lock(); ++ status = g_isr_status_bits; ++ g_isr_status_bits = 0; ++ //cyg_drv_isr_unlock(); ++ ++ // Reset is special, since it invalidates everything else. ++ // If the reset is still ongoing then do not attempt any ++ // further processing, there will just be another interrupt. ++ // Otherwise handle_reset() does the hard work. Unmasking ++ // the interrupt means that another interrupt will occur ++ // immediately if reset is still asserted, i.e. no threads ++ // will run, but there is no easy way of triggering action ++ // at the end of reset. ++ if (status & IMX_USB_STS_RESET) ++ { ++ int new_status = usbs_imx_otg_base->usbsts; ++ if (0 == (new_status & IMX_USB_STS_RESET)) ++ { ++ usbs_imx_otg_dev_handle_bus_reset(); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: !!USB BUS RESET\n"); ++ } ++ ++ // This unmask is likely to cause another interrupt immediately ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST); ++ #endif ++ } ++ else if(status & IMX_USB_STS_USBINT) ++ { ++ ++ if(usbs_imx_otg_base->endptsetupstat & BIT0) ++ {// if Setup Packet arrived ++ usbs_imx_otg_dev_ep0_dsr(); ++ } ++ ++ else if((usbs_imx_otg_base->endptcomplete) & ( EPIN_COMPLETE << EP2)) ++ {// EP2 Queue Header buffer completes sending data ++ //complete bit is cleared in ep2_start_tx ++ } ++ ++ ++ else if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP1)) ++ {// EP1 Queue Header buffer get data ++ usbs_imx_otg_dev_ep1_dsr(); ++ ++ } ++ ++ else if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP0)) ++ { ++ //usbs_imx_otg_dev_ep0_dsr(); ++ usbs_imx_otg_base->endptcomplete = ( EPOUT_COMPLETE << EP0); ++ } ++ else ++ {//do nothing, only for constructure integrity ++ temp = usbs_imx_otg_base->endptcomplete; ++ usbs_imx_otg_base->endptcomplete = temp; ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: usbsts int - unknown.\n"); ++ } ++ ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ // This unmask is likely to cause another interrupt immediately ++ cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST); ++ #endif ++ } ++ else ++ { ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ // This unmask is likely to cause another interrupt immediately ++ cyg_interrupt_unmask(MX51_IRQ_USB_SERVICE_REQUEST); ++ #endif ++ } ++ ++ ++} ++/*============================================================================= ++// The DSR thread ++=============================================================================*/ ++#if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++#define CYGNUM_DEVS_USB_OTG_DEV_THREAD_STACK_SIZE 1024 ++#define CYGNUM_DEVS_USB_OTG_DEV_THREAD_PRIORITY 29 ++static unsigned char usbs_imx_otg_dev_thread_stack[CYGNUM_DEVS_USB_OTG_DEV_THREAD_STACK_SIZE]; ++static cyg_thread usbs_imx_otg_dev_thread; ++static cyg_handle_t usbs_imx_otg_dev_thread_handle; ++static cyg_sem_t usbs_imx_otg_dev_sem; ++ ++ ++static void ++usbs_imx_otg_dev_thread_fn(cyg_addrword_t param) ++{ ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: usb driver thread\n"); ++ for (;;) { ++ cyg_semaphore_wait(&usbs_imx_otg_dev_sem); ++ usbs_imx_otg_dev_dsr(IMX_IRQ_USB_DEV_SERVICE_REQUEST, 0, 0); ++ } ++ CYG_UNUSED_PARAM(cyg_addrword_t, param); ++} ++ ++static void ++usbs_imx_otg_dev_thread_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) ++{ ++ CYG_ASSERT( 0 != isr_status_bits, "DSR's should only be scheduled when there is work to do"); ++ cyg_semaphore_post(&usbs_imx_otg_dev_sem); ++ ++ ++ CYG_UNUSED_PARAM(cyg_vector_t, vector); ++ CYG_UNUSED_PARAM(cyg_ucount32, count); ++ CYG_UNUSED_PARAM(cyg_addrword_t, data); ++} ++#endif ++/*============================================================================= ++// The interrupt handler. This does as little as possible. ++=============================================================================*/ ++static cyg_uint32 ++usbs_imx_otg_dev_isr(cyg_vector_t vector, cyg_addrword_t data) ++{ ++ cyg_uint32 old_status_bits = g_isr_status_bits; ++ cyg_uint32 status_bits; ++ ++ CYG_ASSERT(IMX_IRQ_USB_DEV_SERVICE_REQUEST == vector, "USB ISR should only be invoked for USB interrupts" ); ++ CYG_ASSERT(0 == data, "The MX51 USB ISR needs no global data pointer" ); ++ ++ //USBDBGMSG("+USBDBGMSG: enter mx51 isr\n"); ++ // Read the current status. Reset is special, it means that the ++ // whole chip has been reset apart from the one bit in the status ++ // register. Nothing should be done about this until the DSR sets ++ // the endpoints back to a consistent state and re-enables ++ // interrupts in the control register. ++ status_bits = usbs_imx_otg_base->usbsts; ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: usb intr 0x%08X\n",status_bits); ++ if (status_bits & IMX_USB_STS_RESET) ++ { ++ ++ g_isr_status_bits |= IMX_USB_STS_RESET; ++ usbs_imx_otg_base->usbsts |= IMX_USB_STS_RESET; ++ cyg_interrupt_mask(IMX_IRQ_USB_DEV_SERVICE_REQUEST); ++ } ++ else if(status_bits & IMX_USB_STS_USBINT) ++ { ++ g_isr_status_bits |= IMX_USB_STS_USBINT; ++ usbs_imx_otg_base->usbsts |= IMX_USB_STS_USBINT; ++ cyg_interrupt_mask(IMX_IRQ_USB_DEV_SERVICE_REQUEST); ++ } ++ else ++ { ++ usbs_imx_otg_base->usbsts = status_bits; //clear the status bit of USBSTS ++ g_isr_status_bits &= ~status_bits; ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: unknown usb intr\n"); ++ } ++ ++ // Now keep the rest of the system happy. ++ cyg_interrupt_acknowledge(vector); //reenable the USB interrupt ++ return (old_status_bits != g_isr_status_bits) ? CYG_ISR_CALL_DSR : CYG_ISR_HANDLED; ++} ++/*============================================================================= ++// Polling support. This acts mostly like the interrupt handler: it ++// sets the isr status bits and causes the dsr to run. Reset has to be ++// handled specially: polling does nothing as long as reset is asserted. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_poll(usbs_control_endpoint* endpoint) ++{ ++ CYG_ASSERT( endpoint == &ep0.common, "USB poll involves the wrong endpoint"); ++ ++ if (g_isr_status_bits & IMX_USB_STS_RESET) ++ { ++ // Reset was detected the last time poll() was invoked. If ++ // reset is still active, do nothing. Once the reset has ++ // completed things can continue. ++ if (0 == (IMX_USB_STS_RESET & usbs_imx_otg_base->usbsts)) ++ { ++ g_isr_status_bits = 0; ++ usbs_imx_otg_dev_handle_bus_reset(); ++ } ++ } ++ else ++ { ++ g_isr_status_bits = usbs_imx_otg_base->usbsts; ++ if (IMX_USB_STS_PTCHANGE & g_isr_status_bits) ++ { ++ //process Port Change Detect ++ usbs_imx_otg_dev_handle_port_change(); ++ } ++ else if (IMX_USB_STS_USBINT & g_isr_status_bits) ++ { ++ usbs_imx_otg_dev_dsr(IMX_IRQ_USB_DEV_SERVICE_REQUEST, 0, (cyg_addrword_t) 0); ++ } ++ else ++ { ++ usbs_imx_otg_base->usbsts = g_isr_status_bits; //clear the don't-care status ++ } ++ } ++} ++/*============================================================================= ++// Perform reset operations on all endpoints that have been ++// configured in. It is convenient to keep this in a separate ++// routine to allow for polling, where manipulating the ++// interrupt controller mask is a bad idea. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_handle_bus_reset(void) ++{ ++ cyg_uint32 temp; ++ ++ usbs_imx_otg_base->usbcmd &= ~BIT0; //detach device from bus temprorarily ++ usbs_imx_otg_base->usbsts |= BIT6; //clear reset bit in USBSTS ++ ++ //temp = usbs_imx_otg_base->usbsts; ++ //usbs_imx_otg_base->usbsts = temp; ++ ++ /*1. Reading and writing back the ENDPTSETUPSTAT register ++ clears the setup token semaphores */ ++ temp = usbs_imx_otg_base->endptsetupstat; ++ usbs_imx_otg_base->endptsetupstat = temp; ++ ++ /*2. Reading and writing back the ENDPTCOMPLETE register ++ clears the endpoint complete status bits */ ++ temp = usbs_imx_otg_base->endptcomplete; ++ usbs_imx_otg_base->endptcomplete = temp; ++ ++ /*3. Cancel all primed status by waiting until all bits in ENDPTPRIME are 0 ++ and then write 0xFFFFFFFF to ENDPTFLUSH */ ++ while(usbs_imx_otg_base->endptprime); ++ usbs_imx_otg_base->endptflush = 0xFFFFFFFF; ++ ++ ++ /*4. Initialize EP0 Queue Head again*/ ++ usbs_ep0_init_dqh(); ++ ++ usbs_imx_otg_base->endptlistaddr = g_bulkbuffer_map.ep_dqh_base_addrs; ++ ++ usbs_imx_otg_base->usbcmd |= BIT0; //re-attach device to the bus ++ ++ g_usb_dev_state = USB_DEV_DEFAULT_STATE; ++ ++ ++} ++/*============================================================================= ++// Perform port change operations on all endpoints that have been ++// configured in. It is convenient to keep this in a separate ++// routine to allow for polling, where manipulating the ++// interrupt controller mask is a bad idea. ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_handle_port_change(void) ++{ ++ /*Port Change happens when USB device enters/exits FS or HS mode ++ When exiting from FS or HS due to Bus reset or DCSuspend, the notification ++ mechanisms are Reset Received and DCSuspend. ++ This function only processes the port change on entering FS or HS ++ Don't enable Port Change Detect interrupt, it's no sense for operation.*/ ++ usbs_imx_otg_base->usbsts |= IMX_USB_STS_PTCHANGE; //clear Port change status ++ ++} ++ ++// **************************************************************************** ++// ---------------------------------------------------------------------------- ++// **************************************************************************** ++/*============================================================================= ++FUNCTION: usbs_imx_otg_dev_set_configuration ++DESCRIPTION: This function Handle the SET CONFIGRATION Request. ++ARGUMENTS PASSED: usb_end_pt_info_t* config_data; ++RETURN VALUE: None ++IMPORTANT NOTES: None ++=============================================================================*/ ++static void ++usbs_imx_otg_dev_set_configuration(usb_end_pt_info_t* config_data) ++{ ++ struct dtd_t td; ++ cyg_uint32 total_bytes = 0x0; ++ cyg_uint32 buffer_addrs_page0 = 0; ++ cyg_uint32 dqh_address = 0; ++ cyg_uint32 dtd_address = 0; ++ cyg_uint8 endpt_num,direction; ++ ++ struct dqh_t qhead; ++ ++ ++ /* get endpoint number to be configured and its direction */ ++ endpt_num= config_data->end_pt_no; ++ direction= config_data->direction; ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: set config - ep%d\n",endpt_num); ++ /* Check if the endpoint number and direction is withing the permitted range or not */ ++ if (( endpt_num != EP0 ) && (endpt_num <= ( g_max_ep_supported - 1)) && ++ ( direction == OUT || direction == IN)) ++ { ++ /* get the device q head and deice TD */ ++ dqh_address = USBS_EP_GET_dQH(endpt_num,direction); ++ dtd_address = USBS_EP_GET_dTD(endpt_num,direction); ++ ++ if ( direction == OUT ) ++ { ++ total_bytes = BULK_BUFFER_SIZE ; ++ ++ qhead.dqh_base = dqh_address; ++ qhead.zlt = ZLT_DISABLE; ++ qhead.mps = config_data->max_pkt_size; ++ qhead.ios = IOS_SET; ++ qhead.next_link_ptr = dtd_address ; ++ qhead.terminate = TERMINATE; ++ qhead.total_bytes = total_bytes; ++ qhead.ioc = IOC_SET; ++ qhead.status = NO_STATUS; ++ qhead.buffer_ptr0 = 0; ++ qhead.current_offset= 0; ++ qhead.buffer_ptr1 = 0; ++ qhead.buffer_ptr2 = 0; ++ qhead.buffer_ptr3 = 0; ++ qhead.buffer_ptr4 = 0; ++ ++ usbs_setup_queuehead(&qhead); ++ ++ /* Endpoint 1 : MPS = 64, OUT (Rx endpoint) */ ++ usbs_imx_otg_base->endptctrl[endpt_num] = 0x00080048; ++ /* Enable EP1 OUT */ ++ usbs_imx_otg_base->endptctrl[endpt_num] |= EPOUT_ENABLE; ++ ++ /* allocate buffer for receiving data */ ++ /* free the usb buffer after re-enumeration*/ ++ //g_bulkbuffer_map.buffer1_status = BUFFER_FREE; ++ //g_bulkbuffer_map.buffer2_status = BUFFER_FREE; ++ g_bulkbuffer_a.stat = BUFFER_FREED; ++ g_bulkbuffer_b.stat = BUFFER_FREED; ++ ++ //buffer_addrs_page0 = util_alloc_buffer(); ++ ep1.common.buffer = g_bulkbuffer_a.buffer; ++ ep1.common.buffer_size = total_bytes; ++ g_bulkbuffer_a.stat = BUFFER_ALLOCATED; ++ buffer_addrs_page0 = (cyg_uint32)(ep1.common.buffer); ++ ++ ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: set config - ep1 dtd buffer 0x%08X\n",buffer_addrs_page0); ++ ++ /* OUT setup dTD */ ++ td.dtd_base = dtd_address; ++ td.next_link_ptr = dtd_address + 0x20; ++ td.terminate = TERMINATE; ++ td.total_bytes = total_bytes; ++ td.ioc = IOC_SET; ++ td.status = ACTIVE; ++ td.buffer_ptr0 = buffer_addrs_page0; ++ td.current_offset = (buffer_addrs_page0 & 0xFFF) + g_td_buffer_offset; ++ td.buffer_ptr1 = 0x0; ++ td.buffer_ptr2 = 0x0; ++ td.buffer_ptr3 = 0x0; ++ td.buffer_ptr4 = 0x0; ++ ++ /* Set the Transfer Descriptor */ ++ usbs_setup_transdesc(&td); ++ ++ /* 1. write dQH next ptr and dQH terminate bit to 0 */ ++ *(volatile cyg_uint32*)(dqh_address+0x8)= dtd_address; ++ ++ /* 2. clear active & halt bit in dQH */ ++ *(volatile cyg_uint32*)(dqh_address+0xC) &= ~0xFF; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME */ ++ usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << endpt_num ); ++ /* Endpoint Configured for output */ ++ g_out_endpoint= endpt_num; ++ ++ ++ } ++ ++ else ++ { ++ total_bytes = 0x4 ; ++ ++ qhead.dqh_base = USBS_EP_GET_dQH(endpt_num,direction); ++ qhead.zlt = ZLT_DISABLE; ++ qhead.mps = config_data->max_pkt_size; ++ qhead.ios = IOS_SET; ++ qhead.next_link_ptr = USBS_EP_GET_dQH(endpt_num,direction); ++ qhead.terminate = TERMINATE; ++ qhead.total_bytes = total_bytes; ++ qhead.ioc = IOC_SET; ++ qhead.status = NO_STATUS; ++ qhead.buffer_ptr0 = 0; ++ qhead.current_offset= 0; ++ qhead.buffer_ptr1 = 0; ++ qhead.buffer_ptr2 = 0; ++ qhead.buffer_ptr3 = 0; ++ qhead.buffer_ptr4 = 0; ++ ++ usbs_setup_queuehead(&qhead); ++ ++ /* Endpoint Configured for Input */ ++ g_in_endpoint= endpt_num; ++ ++ /* Endpoint 2: MPS = 64, IN (Tx endpoint) */ ++ usbs_imx_otg_base->endptctrl[endpt_num] = 0x00480008; ++ ++ /* Enable EP2 IN */ ++ usbs_imx_otg_base->endptctrl[endpt_num] |= EPIN_ENABLE; ++ ++ /* 3. prime endpoint by writing '1' in ENDPTPRIME */ ++ usbs_imx_otg_base->endptprime |= (EPIN_PRIME << g_in_endpoint); ++ ++ } ++ } ++ else ++ { ++ /* TODO: error handling TBD */ ++ } ++ ++} ++ ++static void usbs_imx_otg_config_utmi_clock(void) ++{ ++ #if defined(CYGHWR_USB_DEVS_MX37_OTG) ++ USB_MX37_SET_PHY_CLK_24MHZ(); ++ #endif ++ ++ #if defined(CYGHWR_USB_DEVS_MX51_OTG) ++ cyg_uint32 temp; ++ /*Configure USB_PHYCLOCK_ROOT source as 24MHz OSC*/ ++ CCM_CSCMR1_REGVAL = CCM_CSCMR1_REGVAL & (~CSCMR1_USBOH3_PHY_CLK_SEL_VALUE); //configure USB CRM ++ /*Configure plldivvalue of USB_PHY_CTRL_1_REG for 24 Mhz*/ ++ temp = *(volatile cyg_uint32 *)USB_PHY_CTRL_1_REG; ++ temp &= ~USB_PHY_CTRL_PLLDIVVALUE_MASK; ++ temp |= USB_PHY_CTRL_PLLDIVVALUE_24_MHZ; ++ *(volatile cyg_uint32 *)USB_PHY_CTRL_1_REG = temp; ++ #endif ++} ++ ++/*============================================================================= ++// The USB OTG hardware relevant initialization. ++=============================================================================*/ ++static void ++usbs_imx_otg_hardware_init(void) ++{ ++ cyg_uint32 temp; ++ cyg_uint32 timeout = 0x1D0000; ++ usb_plat_config_data_t config_data_ptr; ++ cyg_uint8 i; ++ ++ /*Enable USB Internal PHY Clock as 24MHz on-board Ocsillator*/ ++ usbs_imx_otg_config_utmi_clock(); ++ ++ {/*Setup USB Buffer Map*/ ++ config_data_ptr.buffer_address = (cyg_uint32)usb_buffer; ++ config_data_ptr.buffer_size = BUFFER_SIZE; ++ ++ /* Base address of the buffer allocated to IP Layer */ ++ g_bulkbuffer_address_base = config_data_ptr.buffer_address; ++ ++ /* length of the buffer */ ++ g_bulkbuffer_length = config_data_ptr.buffer_size; ++ ++ /* Maximum Number of EPs to be confiured */ ++ g_max_ep_supported = (( g_bulkbuffer_length - TOTAL_DATA_BUFFER_SIZE)/(BUFFER_USED_PER_EP)); //=(2048-1088)/256~=3.75->3 ++ ++ /* Base of queue Head Pointer */ ++ g_bulkbuffer_map.ep_dqh_base_addrs = g_bulkbuffer_address_base; ++ ++ /* Total size of qhead */ ++ temp = (SIZE_OF_QHD * (g_max_ep_supported * 2)); //total size of QH is 384byte ++ ++ /* Base Address of dTDs */ ++ g_bulkbuffer_map.ep_dtd_base_addrs = (g_bulkbuffer_map.ep_dqh_base_addrs + temp); ++ ++ /* Total size of transfer descriptor */ ++ temp = ((dTD_SIZE_EPIN * g_max_ep_supported) + (dTD_SIZE_EPOUT * g_max_ep_supported )); //total size of TD is 384 byte ++ ++ /* Base Address of EP0 Buffer */ ++ g_bulkbuffer_map.ep0_buffer_addrs = (g_bulkbuffer_map.ep_dtd_base_addrs + temp ); //256byte ++ ++ /*Bulk Buffer Areas, 512byte per buffer*/ ++ /*Actually, the dual 512 byte bulk buffers are not used, because two larger 16kB bulk buffers are used*/ ++ /* transfer buffer 1 */ ++ g_bulkbuffer_map.buffer1_address=(g_bulkbuffer_address_base + g_bulkbuffer_length -(BULK_BUFFER_SIZE*NUM_OF_BULK_BUFFER)); ++ g_bulkbuffer_map.buffer1_status = BUFFER_FREE; ++ ++ /* transfer buffer 2 */ ++ g_bulkbuffer_map.buffer2_address = g_bulkbuffer_map.buffer1_address + BULK_BUFFER_SIZE; ++ g_bulkbuffer_map.buffer2_status = BUFFER_FREE; ++ } ++ ++ {/*Set USB OTG at device only mode*/ ++ usbs_imx_otg_base->usbmode = 0x2; //set OTG as a device controller ++ temp = 0xA5A55A5A; ++ while (!(usbs_imx_otg_base->usbmode == 0x2)) ++ { ++ if(temp != (usbs_imx_otg_base->usbmode)) ++ { ++ temp = (usbs_imx_otg_base->usbmode); ++ USBDBGMSG(DEBUG_BASIC,"usbmode is 0x%08X\n",temp); ++ } ++ timeout--; ++ if(timeout==0) break; ++ } //check that device controller was configured to device mode only ++ } ++ ++ { ++ usbs_imx_otg_base->endptlistaddr = g_bulkbuffer_map.ep_dqh_base_addrs; // Configure ENDPOINTLISTADDR Pointer ++ usbs_imx_otg_base->otgsc |= BIT3; // Set OTG termination, controls the pulldown on DM ++ usbs_imx_otg_base->endptnak = 0x00010001; // Enable Endpoint NAK ++ usbs_imx_otg_base->usbmode |= BIT3; // Disable Setup Lockout by writing '1' to SLOM in USBMODE ++ //usbs_imx_otg_base->usbcmd |= BIT0; // Set Run/Stop bit to Run Mode, make USB run in usbs_imx_otg_dev_ep0_start() ++ } ++ ++ { ++ /* set it to be utmi interface */ ++ temp = usbs_imx_otg_base->portsc1; ++ temp &= ~USB_OTG_TRANS_MASK; ++ temp |= USB_OTG_TRANS_UTMI; ++ temp &= ~USB_OTG_FS_ONLY; //enable high speed ++ temp |= USB_OTG_TRANS_WIDTH; ++ ++ usbs_imx_otg_base->portsc1 = temp; ++ } ++ ++ {// The USB OTG transaction relevant initialization. ++ /* Select the common descriptors , these descriptor are independent of speed and security mode */ ++ g_usb_desc.device_desc = &g_usb_device_desc ; ++ g_usb_desc.config_desc = &g_usb_config_desc; ++ g_usb_desc.sn_desc = &g_usb_serialnumber_desc; ++ g_usb_desc.str_desc0 = &g_usb_otg_str0_desc; //language desc ++ g_usb_desc.str_desc1 = &g_usb_otg_string_desc1; //Manufacturer desc ++ g_usb_desc.str_desc2 = &g_usb_otg_string_desc2; //USB Name Desc ++ g_usb_desc.str_desc3 = &g_usb_otg_string_desc3; //Device Name Desc ++ ++ /* Get Number of Endpoints supported from Configuration Descriptor*/ ++ g_number_of_endpoints = g_usb_desc.config_desc->usb_interface_desc.number_endpoints; ++ ++ /* Store the Endpoint specific information in local variable structure to this Layer */ ++ for ( i = 0 ; i< g_number_of_endpoints ; i++) ++ { ++ g_end_pt_info[i].end_pt_no = ((g_usb_desc.config_desc->usb_endpoint_desc[i].endpoint) & ENDPT_NUMBER_MASK); ++ g_end_pt_info[i].direction = (((g_usb_desc.config_desc->usb_endpoint_desc[i].endpoint) & ENDPT_DIR_MASK )>>ENDPT_DIR_SHIFT); ++ g_end_pt_info[i].transfer_type = (g_usb_desc.config_desc->usb_endpoint_desc[i].attributes & ENDPT_TRNS_TYPE_MASK); ++ g_end_pt_info[i].max_pkt_size = ((g_usb_desc.config_desc->usb_endpoint_desc[i].max_packet_lo) \ ++ | (( g_usb_desc.config_desc->usb_endpoint_desc[i].max_packet_hi ) << 8 )); ++ } ++ ++ g_usb_dev_state = USB_DEV_DEFAULT_STATE; ++ } ++} ++// **************************************************************************** ++// ---------------------------------------------------------------------------- ++// **************************************************************************** ++/*============================================================================= ++// Initialization i.MX37(Marley) USB OTG Hardware ++// This function is the only extern function of this device driver, and it ++// registers the driver ISR and DSRs to the kernel. ++=============================================================================*/ ++void ++usbs_imx_otg_device_init(void) //works like usb port open when ++{ ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: USB Device Driver Start Initializing...\n"); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: USB OTG REG BASE@0x%08X\n",USB_BASE_ADDRESS); ++ g_usb_setup_data = ep0.common.control_buffer; ++ ++ g_td_buffer_offset = 0; ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ USB_IMX_SET_TD_OFFSET(g_td_buffer_offset,1); ++ #endif ++ ++ /*ping-pang buffer A*/ ++ g_bulkbuffer_a.buffer = bulk_buffer; ++ g_bulkbuffer_a.stat = BUFFER_FREED; ++ ++ /*ping-pang buffer B*/ ++ g_bulkbuffer_b.buffer = bulk_buffer + BULK_TD_BUFFER_TOTAL_SIZE; ++ g_bulkbuffer_b.stat = BUFFER_FREED; ++ ++ usbs_imx_otg_hardware_init(); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Hardware Initialize Complete.\n"); ++ usbs_imx_otg_dev_ep0_init(); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep0 Initialize Complete.\n"); ++ usbs_imx_otg_dev_ep1_init(); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep1 Initialize Complete.\n"); ++ usbs_imx_otg_dev_ep2_init(); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: Usb Ep2 Initialize Complete.\n"); ++ ++ #if !defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ cyg_semaphore_init(&usbs_imx_otg_dev_sem, 0); ++ cyg_thread_create(CYGNUM_DEVS_USB_OTG_DEV_THREAD_PRIORITY, ++ &usbs_imx_otg_dev_thread_fn, ++ 0, ++ "i.MX37/51 USB Device", ++ usbs_imx_otg_dev_thread_stack, ++ CYGNUM_DEVS_USB_OTG_DEV_THREAD_STACK_SIZE, ++ &usbs_imx_otg_dev_thread_handle, ++ &usbs_imx_otg_dev_thread ++ ); ++ cyg_thread_resume(usbs_imx_otg_dev_thread_handle); ++ // It is also possible and desirable to install the interrupt ++ // handler here, even though there will be no interrupts for a ++ // while yet. ++ cyg_interrupt_create(IMX_IRQ_USB_DEV_SERVICE_REQUEST, ++ IMX_IRQ_USB_DEV_PRIORITY, // priority ++ 0, // data ++ &usbs_imx_otg_dev_isr, ++ &usbs_imx_otg_dev_thread_dsr, ++ &g_usbs_dev_intr_handle, ++ &g_usbs_dev_intr_data); ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_create@vector %d.\n",IMX_IRQ_USB_DEV_SERVICE_REQUEST); ++ cyg_interrupt_attach(g_usbs_dev_intr_handle); //fill interrupt handler table for USB ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_attach.\n"); ++ cyg_interrupt_unmask(IMX_IRQ_USB_DEV_SERVICE_REQUEST); //enable USB interrrupt ++ USBDBGMSG(DEBUG_BASIC,"+USBDBGMSG: cyg_interrupt_unmask.\n"); ++ #endif ++ ep0.common.start_fn(&(ep0.common)); ++ ++} ++ ++void ++usbs_imx_otg_device_deinit(void) //works like usb port close ++{ ++ usbs_imx_otg_base->usbcmd &= (~BIT0); // Set Run/Stop bit to Stop Mode ++ g_usb_dev_state = USB_DEV_DUMMY_STATE; ++} ++ ++#if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT) ++ ++static cyg_uint32 get_free_bulk_buffer(void) ++{ ++ cyg_uint32 buff_addr = 0; ++ int i = 0; ++ while(buff_addr == 0) ++ { ++ if(g_bulkbuffer_a.stat == BUFFER_FREED) ++ { ++ buff_addr = (cyg_uint32)(g_bulkbuffer_a.buffer); ++ break; ++ } ++ else if(g_bulkbuffer_b.stat == BUFFER_FREED) ++ { ++ buff_addr = (cyg_uint32)(g_bulkbuffer_b.buffer); ++ break; ++ } ++ /* ++ else ++ { ++ i++; ++ if(i==0xD0000) ++ { ++ diag_printf("no bulk buffer free\n"); ++ break; ++ } ++ ++ } ++ */ ++ } ++ return buff_addr; ++} ++ ++cyg_bool set_status_bulk_buffer(cyg_uint32 buff_addr, int buff_stat) ++{ ++ cyg_bool ret = true; ++ if(buff_addr == (cyg_uint32)(g_bulkbuffer_a.buffer)) ++ g_bulkbuffer_a.stat = buff_stat; ++ else if (buff_addr == (cyg_uint32)(g_bulkbuffer_b.buffer)) ++ g_bulkbuffer_b.stat = buff_stat; ++ else ++ ret = false; ++ ++ return ret; ++} ++static usb_status_t usb_bulk_receive_data(usb_buffer_descriptor_t * bd) ++{ ++ usb_status_t status; ++ int res; ++ ++ /* Check if Bus Reset Received */ ++ if((usbs_imx_otg_base->usbsts) & IMX_USB_STS_RESET) ++ { ++ /* Handle Bus Reset */ ++ usbs_imx_otg_dev_handle_bus_reset(); ++ } ++ /* Check if Reset is already received and Setup Token Received */ ++ if((usbs_imx_otg_base->endptsetupstat) & BIT0) ++ { ++ /* Handle Setup Token */ ++ usbs_imx_otg_dev_ep0_dsr(); ++ } ++ ++ if((usbs_imx_otg_base->endptcomplete) & ( EPOUT_COMPLETE << EP1)) ++ { ++ ep1_rx_complete(res); ++ if(ep1.common.complete_data) ++ { ++ bd->bytes_transfered = ep1.fetched; ++ memcpy(bd->buffer,ep1.common.complete_data,ep1.fetched); ++ ep1.fetched = 0; ++ //D("+USBDBGMSG:bd->bytes_transfered %d\n",bd->bytes_transfered); ++ set_status_bulk_buffer((cyg_uint32)(ep1.common.complete_data), BUFFER_FREED); ++ ep1.common.buffer = (unsigned char *)get_free_bulk_buffer(); ++ ep1.common.buffer_size = BULK_TD_BUFFER_TOTAL_SIZE; ++ ep1_start_rx(&(ep1.common)); ++ usbs_imx_otg_base->endptprime |= ( EPOUT_PRIME << EP1 );//prime ep1 td ++ status = USB_SUCCESS; ++ } ++ ++ else ++ status = USB_FAILURE; ++ } ++ return status; ++} ++ ++static usb_status_t usb_bulk_transmit_data(usb_buffer_descriptor_t * bd) ++{ ++ //usb_state_t status; ++ ++ while(bd->size) ++ { ++ ep2.common.buffer = (unsigned char *)get_free_bulk_buffer(); ++ set_status_bulk_buffer((cyg_uint32)(ep2.common.buffer), BUFFER_ALLOCATED); ++ ep2.common.buffer_size = (BULK_TD_BUFFER_TOTAL_SIZE<(bd->size))?BULK_TD_BUFFER_TOTAL_SIZE:(bd->size); ++ memcpy((ep2.common.buffer),(bd->buffer),(ep2.common.buffer_size)); ++ ep2_start_tx(&(ep2.common)); ++ ++ bd->size -= (ep2.common.buffer_size); ++ } ++ ++ return USB_SUCCESS; ++} ++static cyg_uint32 usb_rx_processing(cyg_uint8* read_ptr, usb_status_t* status, cyg_uint32 data_length) ++{ ++ cyg_uint32 bytes_received = 0; ++ if ( (status != NULL) && (read_ptr != NULL) ) ++ { ++ usb_status_t trans_status = USB_FAILURE; ++ ++ usb_buffer_descriptor_t buf_desc; ++ ++ /* Prepare the buffer descriptor for USB transfer */ ++ //(cyg_uint8*)(buf_desc.buffer) = read_ptr; ++ buf_desc.buffer = (void *)read_ptr; ++ while(data_length != 0) ++ { ++ buf_desc.size = data_length; ++ buf_desc.bytes_transfered = 0; ++ ++ /* Receive data from USB */ ++ trans_status = (usb_status_t )usb_bulk_receive_data(&buf_desc); ++ if(trans_status == USB_SUCCESS) ++ { ++ data_length -= buf_desc.bytes_transfered; ++ bytes_received += buf_desc.bytes_transfered; ++ //(cyg_uint8*) ++ (buf_desc.buffer) += buf_desc.bytes_transfered; ++ } ++ else ++ { ++ *status = USB_FAILURE; ++ } ++ ++ g_timeout_value++; ++ if(g_timeout_value%0x1000000==0) D("C"); ++ if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) return 0; ++ } ++ } ++ ++ return ( bytes_received ); ++} ++static usb_status_t usb_tx_processing(cyg_uint8* write_ptr, cyg_uint32 data_len) ++{ ++ usb_status_t trans_status = USB_FAILURE; ++ ++ /* Prepare the buffer descriptor for USB transfer */ ++ usb_buffer_descriptor_t buf_desc; ++ ++ /* Prepare transfer buffer descriptor*/ ++ buf_desc.buffer = (void *)write_ptr; ++ buf_desc.size = data_len; ++ buf_desc.bytes_transfered = 0; ++ ++ /* Send data over USB */ ++ trans_status = usb_bulk_transmit_data(&buf_desc); ++ ++ return trans_status; ++} ++static cyg_bool pl_get_command(void) ++{ ++ cyg_uint8 i = 0; ++ usb_status_t status; ++ cyg_uint32 bytes_recvd = 0; ++ cyg_uint8 start_command = 0xFF; ++ ++ while(start_command == 0xFF) ++ { ++ //g_timeout_value++; ++ //if(g_timeout_value%1000==0) D("C"); ++ //D("%d\n",g_timeout_value); ++ bytes_recvd = usb_rx_processing(sdp_payload_data, &status, SDP_CMD_MAX_LEN); ++ start_command = pl_command_start(); ++ if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) return false; ++ } ++ //D("+USBDBGMSG: start_command = 0x%02X\n",start_command); ++ if(start_command == 0xF0) ++ { ++ //copy rest of the bytes ++ for(i=1; i < SDP_CMD_MAX_LEN; i++) ++ { ++ sdp_command[i] = sdp_payload_data[i-1]; ++ } ++ } ++ else ++ { ++ //copy starting bytes ++ for(i=0; i < (SDP_CMD_MAX_LEN - start_command) ; i++) ++ { ++ sdp_command[i] = sdp_payload_data[i + start_command]; ++ } ++ ++ if(start_command != 0) ++ { ++ //receive rest of the bytes ++ bytes_recvd = usb_rx_processing(sdp_payload_data, &status, start_command); ++ ++ if(bytes_recvd == start_command) ++ { ++ for(i=0; i usbsts) & IMX_USB_STS_RESET) ++ { ++ /* Handle Bus Reset */ ++ usbs_imx_otg_dev_handle_bus_reset(); ++ } ++ /* Check if Reset is already received and Setup Token Received */ ++ if((g_usb_dev_state != USB_DEV_DUMMY_STATE) && (usbs_imx_otg_base->endptsetupstat & BIT0)) ++ { ++ /* Handle Setup Token */ ++ usbs_imx_otg_dev_ep0_dsr(); ++ } ++ } ++ ++ if(g_usb_dev_state==USB_DEV_CONFIGURED_STATE) ++ { ++ //D("+USBDBGMSG: enumeration done\n"); ++ /*file download*/ ++ D("USB file download start\n"); ++ g_timeout_value = 0; ++ usb_download_length = 0; ++ //usb_download_address = 0; ++ //g_load_cycle = 0; ++ while(1) ++ { ++ ++ bytes_recvd = pl_get_command(); ++ if(bytes_recvd == true) ++ { ++ g_usb_download_state = pl_handle_command(g_error_status); ++ } ++ ++ if((g_usb_download_state==COMPLETE)||(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT)) ++ break; ++ ++ } ++ diag_printf("\n"); ++ if(g_timeout_value == USB_DOWNLOAD_TIMEOUT_LIMIT) //timeout value ++ D("USB download timeout to wait none file to download\n"); ++ else ++ { ++ D("USB file download complete\n"); ++ //D("+usbdownload: image base 0x%08X, length %d\n",usb_download_address,usb_download_length); ++ } ++ ++ } ++} ++#endif ++ ++//EOF +diff -urNad redboot-imx-200952~/packages/ecos.db redboot-imx-200952/packages/ecos.db +--- redboot-imx-200952~/packages/ecos.db 2008-07-12 14:33:02.000000000 +0000 ++++ redboot-imx-200952/packages/ecos.db 2010-01-26 17:33:15.032966759 +0000 +@@ -217,6 +217,68 @@ + flash memory devices." + } + ++package CYGPKG_DEVS_FLASH_ONMXC { ++ alias { "Support FLASH memory on Freescale MXC platforms" flash_mxc_flash } ++ directory devs/flash/arm/mxc ++ script mxc_flash_select.cdl ++ hardware ++ description " ++ This package contains hardware support for NOR/NAND selections on ++ Freescale MXC-based platforms." ++} ++ ++package CYGPKG_DEVS_FLASH_ONSTMP { ++ alias { "Support FLASH memory on Freescale stmp platforms" flash_stmp_flash } ++ directory devs/flash/arm/stmp ++ script stmp_flash_select.cdl ++ hardware ++ description " ++ This package contains hardware support for NOR/NAND selections on ++ Freescale STMP-based platforms." ++} ++ ++ ++ ++package CYGPKG_DEVS_MXC_I2C { ++ alias { "Support I2C on Freescale MXC platforms" fsl_mxc_i2c } ++ directory devs/i2c/arm/mxc ++ script mxc_i2c.cdl ++ hardware ++ description " ++ This package contains hardware support for I2C selections on ++ Freescale MXC-based platforms." ++} ++ ++package CYGPKG_DEVS_PMIC_ARM_IMX35_3STACK { ++ alias { "Support PMIC on Freescale i.MX35 3stack platforms" fsl_imx35_pmic } ++ directory devs/pmic/arm/mx35_3stack ++ script mc9s08dz.cdl ++ hardware ++ description " ++ This package contains hardware support for PMIC selections on ++ Freescale i.MX35 3stack platforms." ++} ++ ++package CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK { ++ alias { "Support PMIC on Freescale i.MX25 3stack platforms" fsl_imx25_pmic } ++ directory devs/pmic/arm/mx25_3stack ++ script mc34704.cdl ++ hardware ++ description " ++ This package contains hardware support for PMIC selections on ++ Freescale i.MX25 3stack platforms." ++} ++ ++package CYGPKG_DEVS_IMX_SPI { ++ alias { "Support SPI on Freescale i.MX platforms" fsl_imx_spi } ++ directory devs/spi/arm/imx ++ script spi.cdl ++ hardware ++ description " ++ This package contains hardware support for SPI selections on ++ Freescale i.MX based platforms." ++} ++ + package CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX { + alias { "Support for Atmel AT29Cxxxx flash memory" flash_atmel_at29cxxxx } + directory devs/flash/atmel/at29cxxxx +@@ -698,6 +760,96 @@ + on the Motorola PowerPC/860 MBX platform." + } + ++package CYGPKG_DEVS_FLASH_MX1ADS { ++ alias { "FLASH memory support for Freescale MX1 ADS board" flash_mx1ads } ++ directory devs/flash/arm/mx1ads ++ script flash_mx1ads.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the Freescale MX1 ads platform." ++} ++ ++package CYGPKG_DEVS_FLASH_ARM_AMD_AM29 { ++ alias { "FLASH memory support for AMD AM29" flash_am29 } ++ directory devs/flash/arm/am29 ++ script flash_am29.cdl ++ hardware ++ description " ++ This package contains hardware support for AMD Am29 FLASH memory ++ " ++} ++ ++package CYGPKG_DEVS_FLASH_MX31ADS_STRATA { ++ alias { "FLASH memory support for MX31ADS" flash_mx31ads } ++ directory devs/flash/arm/mx31ads ++ script flash_board_strata.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the MX31ADS platform." ++} ++ ++package CYGPKG_DEVS_FLASH_MX31ADS_SPANSION { ++ alias { "FLASH memory support for MX31ADS" flash_mx31ads } ++ directory devs/flash/arm/mx31ads ++ script flash_board_spansion.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the MX31ADS platform." ++} ++ ++package CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION { ++ alias { "FLASH memory support for IMX 3-Stack board" flash_imx_3stack } ++ directory devs/flash/arm/imx_3stack ++ script flash_board_spansion.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the i.MX 3-Stack platform." ++} ++ ++package CYGPKG_DEVS_FLASH_MX35EVB_SPANSION { ++ alias { "FLASH memory support for MX35EVB" flash_mx35evb } ++ directory devs/flash/arm/mx35evb ++ script flash_board_spansion.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the MX35EVB platform." ++} ++ ++package CYGPKG_DEVS_FLASH_MX27ADS_SPANSION { ++ alias { "FLASH memory support for MX27ADS" flash_mx27ads } ++ directory devs/flash/arm/mx27ads ++ script flash_board_spansion.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the MX27ADS platform." ++} ++ ++package CYGPKG_DEVS_FLASH_MXC30030EVB_SPANSION { ++ alias { "FLASH memory support for MXC300-30" flash_mxc30030evb } ++ directory devs/flash/arm/mxc30030evb ++ script flash_board_spansion.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the MXC300-30 EVB platform." ++} ++ ++ package CYGPKG_DEVS_FLASH_I30030ADS { ++ alias { "FLASH memory support for i.300-30 ADS" flash_i30030ads} ++ directory devs/flash/arm/i30030ads ++ script flash_board_strata.cdl ++ hardware ++ description " ++ This package contains hardware support for FLASH memory ++ on the i.300-30 ADS platform." ++} ++ + package CYGPKG_DEVS_FLASH_TS6 { + alias { "FLASH memory support for Delphi Communication Systems, Inc. TigerSHARC6 Board" flash_ts6 } + directory devs/flash/powerpc/ts6 +@@ -912,6 +1064,15 @@ + description "Intel StrongARM/SA11x0 serial device drivers" + } + ++package CYGPKG_IO_SERIAL_ARM_IMX { ++ alias { "Freescale i.MX serial driver" ++ devs_serial_arm_imx imx_serial_driver } ++ hardware ++ directory devs/serial/arm/imx ++ script ser_arm_imx.cdl ++ description "Freescale i.MX serial device drivers" ++} ++ + package CYGPKG_IO_SERIAL_ARM_PID { + alias { "ARM PID serial device drivers" + devs_serial_arm_pid pid_serial_driver } +@@ -1434,6 +1595,14 @@ + description "A device driver for the SA11X0 on-chip USB slave port" + } + ++package CYGPKG_DEVS_USB_IMX_OTG { ++ alias { "USB Device Driver for the i.MX37 or MX51 on-chip USB support" usb_otg_imx } ++ hardware ++ directory devs/usb/imx ++ script usbs_imx.cdl ++ description "A device driver for the i.MX37 or i.MX51 on-chip USB OTG device mode" ++} ++ + package CYGPKG_DEVS_USB_UPD985XX { + alias { usb_upd985xx } + hardware +@@ -1580,6 +1749,52 @@ + description "Ethernet driver for Agilent AAED2000 + development boards." + } ++ ++package CYGPKG_DEVS_ETH_ARM_MX1ADS { ++ alias { "Ethernet driver for Freescale MX1 ADS board" mx1ads_eth_driver } ++ hardware ++ directory devs/eth/arm/mx1ads ++ script mx1ads_eth_drivers.cdl ++ description "Ethernet driver for Freescale MX1 ADS ++ development boards." ++} ++ ++package CYGPKG_DEVS_ETH_ARM_MX21ADS { ++ alias { "Ethernet driver for Freescale MX21 ADS board" mx21ads_eth_driver } ++ hardware ++ directory devs/eth/arm/mx21ads ++ script board_eth_drivers.cdl ++ description "Ethernet driver for Freescale MX21 ADS ++ development boards." ++} ++ ++package CYGPKG_DEVS_ETH_ARM_MX27ADS { ++ alias { "Ethernet driver for Freescale MX27 ADS board" mx27ads_eth_driver } ++ hardware ++ directory devs/eth/arm/mx27ads ++ script board_eth_drivers.cdl ++ description "Ethernet driver for Freescale MX27 ADS ++ development boards." ++} ++ ++package CYGPKG_DEVS_ETH_ARM_IMX_3STACK { ++ alias { "Ethernet driver for Freescale 3-Stack board" imx_3stack_eth_driver } ++ hardware ++ directory devs/eth/arm/imx_3stack ++ script board_eth_drivers.cdl ++ description "Ethernet driver for Freescale 3-Stack ++ development boards." ++} ++ ++package CYGPKG_DEVS_ETH_ARM_MX31ADS { ++ alias { "Ethernet driver for Freescale MX31 ADS board" mx31ads_eth_driver } ++ hardware ++ directory devs/eth/arm/mx31ads ++ script board_eth_drivers.cdl ++ description "Ethernet driver for Freescale MX31 ADS ++ development boards." ++} ++ + package CYGPKG_DEVS_ETH_AMD_PCNET { + alias { "AMD PCNET ethernet driver" pcnet_eth_driver } + hardware +@@ -1921,6 +2136,14 @@ + description "Ethernet driver for Cirrus Logic CS8900A controller." + } + ++package CYGPKG_DEVS_ETH_FEC { ++ alias { "MXC FEC ethernet driver" mxc_fec_eth_driver } ++ hardware ++ directory devs/eth/fec ++ script fec_eth_drivers.cdl ++ description "Ethernet driver for FEC controller." ++} ++ + package CYGPKG_DEVS_ETH_MIPS_UPD985XX { + alias { "NEC uPD985xx ethernet driver" uPD985xx_eth_driver } + hardware +@@ -2366,6 +2589,20 @@ + description "ezXML, Simple XML Parser" + } + ++package CYGPKG_DIAGNOSIS { ++ alias { "Diagnosis" DIAGNOSIS diagnosis } ++ directory services/diagnosis ++ script diagnosis.cdl ++ description "Diagnosis" ++} ++ ++package CYGPKG_IMX_COMMON { ++ alias { "IMX Common files" IMX_COMMON imx_common } ++ directory hal/arm/imx ++ script imx_redboot_common.cdl ++ description "Common drivers for all iMX platforms" ++} ++ + package CYGPKG_UITRON { + alias { "uITRON compatibility" uitron } + directory compat/uitron +@@ -2958,6 +3195,13 @@ + description "Ethernet driver for SMSC LAN91CXX (LAN9000) controller." + } + ++package CYGPKG_DEVS_ETH_SMSC_LAN92XX { ++ alias { "SMSC LAN92XX ethernet driver" lan92xx_eth_driver lan9217_eth_driver } ++ hardware ++ directory devs/eth/smsc/lan92xx ++ script smsc_lan92xx_eth_drivers.cdl ++ description "Ethernet driver for SMSC LAN92XX (LAN9217) controller." ++} + + package CYGPKG_HAL_ARM_SA11X0_NANO { + alias { "Intel SA1110 nanoEngine eval board" hal_arm_sa11x0_nano } +@@ -3169,6 +3413,226 @@ + eCos on a MPC 5.0." + } + ++package CYGPKG_HAL_ARM_MDBMX1 { ++ alias { "Freescale MC9328MX1 Chipset" hal_arm_mdbmx1 } ++ directory hal/arm/mdbmx1/var ++ script hal_arm_mdbmx1.cdl ++ hardware ++ description " ++ The MDBMX1 HAL package provides the support needed to run ++ eCos on Freescale MC9328MX1 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MDBMX1_ADS { ++ alias { "Freescale MC9328MX1 ADS board" hal_arm_mdbmx1_ads } ++ directory hal/arm/mdbmx1/ads ++ script hal_arm_mdbmx1_ads.cdl ++ hardware ++ description " ++ The ADS HAL package provides the support needed to run ++ eCos on a Freescale MC9328MX1 ADS board." ++} ++ ++package CYGPKG_HAL_ARM_MX21 { ++ alias { "Freescale i.MX21 Chipset" hal_arm_mx21 } ++ directory hal/arm/mx21/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX21 HAL package provides the support needed to run ++ eCos on Freescale i.MX21 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX21ADS { ++ alias { "Freescale i.MX21 ADS board" hal_arm_mx21ads } ++ directory hal/arm/mx21/ads ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The ADS HAL package provides the support needed to run ++ eCos on a Freescale i.MX21 ADS board." ++} ++ ++package CYGPKG_HAL_ARM_MX25 { ++ alias { "Freescale i.MX25 Chipset" hal_arm_mx25 } ++ directory hal/arm/mx25/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX25 HAL package provides the support needed to run ++ eCos on Freescale i.MX25 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX27 { ++ alias { "Freescale i.MX27 Chipset" hal_arm_mx27 } ++ directory hal/arm/mx27/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX21 HAL package provides the support needed to run ++ eCos on Freescale i.MX27 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX27ADS { ++ alias { "Freescale i.MX27 ADS board" hal_arm_mx27ads } ++ directory hal/arm/mx27/ads ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The ADS HAL package provides the support needed to run ++ eCos on a Freescale i.MX27 ADS board." ++} ++ ++package CYGPKG_HAL_ARM_MX27_3STACK { ++ alias { "Freescale i.MX27 3-Stack board" hal_arm_mx27_3stack } ++ directory hal/arm/mx27/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX27 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX31 { ++ alias { "Freescale i.MX31 Chipset" hal_arm_mx31 } ++ directory hal/arm/mx31/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX31 HAL package provides the support needed to run ++ eCos on Freescale i.MX31 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX35 { ++ alias { "Freescale i.MX35 Chipset" hal_arm_mx35 } ++ directory hal/arm/mx35/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX35 HAL package provides the support needed to run ++ eCos on Freescale i.MX35 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX35EVB { ++ alias { "Freescale i.MX35 EVB board" hal_arm_mx35evb } ++ directory hal/arm/mx35/evb ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The ADS HAL package provides the support needed to run ++ eCos on a Freescale i.MX35 EVB board." ++} ++ ++package CYGPKG_HAL_ARM_MX37 { ++ alias { "Freescale i.MX37 Chipset" hal_arm_mx37 } ++ directory hal/arm/mx37/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX37 HAL package provides the support needed to run ++ eCos on Freescale i.MX37 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX51 { ++ alias { "Freescale i.MX51 Chipset" hal_arm_mx51 } ++ directory hal/arm/mx51/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX51 HAL package provides the support needed to run ++ eCos on Freescale i.MX51 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX23 { ++ alias { "Freescale i.MX23 Chipset" hal_arm_mx23 } ++ directory hal/arm/mx23/var ++ script hal_arm_soc.cdl ++ hardware ++ description " ++ The MX23 HAL package provides the support needed to run ++ eCos on Freescale i.MX23 based systems." ++} ++ ++package CYGPKG_HAL_ARM_MX31ADS { ++ alias { "Freescale i.MX31 ADS board" hal_arm_mx31ads } ++ directory hal/arm/mx31/ads ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The ADS HAL package provides the support needed to run ++ eCos on a Freescale i.MX31 ADS board." ++} ++ ++package CYGPKG_HAL_ARM_MX25_3STACK { ++ alias { "Freescale i.MX25 3-Stack board" hal_arm_mx25_3stack } ++ directory hal/arm/mx25/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX25 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX31_3STACK { ++ alias { "Freescale i.MX31 3-Stack board" hal_arm_mx31_3stack } ++ directory hal/arm/mx31/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX31 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX35_3STACK { ++ alias { "Freescale i.MX35 3-Stack board" hal_arm_mx35_3stack } ++ directory hal/arm/mx35/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX35 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX37_3STACK { ++ alias { "Freescale i.MX37 3-Stack board" hal_arm_mx37_3stack } ++ directory hal/arm/mx37/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX37 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX51_3STACK { ++ alias { "Freescale i.MX51 3-Stack board" hal_arm_mx51_3stack } ++ directory hal/arm/mx51/3stack ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The 3-Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX51 3-Stack board." ++} ++ ++package CYGPKG_HAL_ARM_MX51_BABBAGE { ++ alias { "Freescale i.MX51 Babbage board" hal_arm_mx51_babbage } ++ directory hal/arm/mx51/babbage ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The babbage HAL package provides the support needed to run ++ eCos on a Freescale i.MX51 Babbage board." ++} ++ ++package CYGPKG_HAL_ARM_MX23_ARMADILLO { ++ alias { "Freescale i.MX23 Armadillo board" hal_arm_mx23_armadillo } ++ directory hal/arm/mx23/armadillo ++ script hal_arm_board.cdl ++ hardware ++ description " ++ The Stack HAL package provides the support needed to run ++ eCos on a Freescale i.MX23 Armadillo board." ++} ++ + # -------------------------------------------------------------------------- + # SH packages + package CYGPKG_HAL_SH { +@@ -5208,6 +5672,156 @@ + MICROPLEX Printer Controller 5.0" + } + ++target mx1ads { ++ alias { "Freescale MC9328MX1 ADS board" mx1 mx1ads } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MDBMX1 ++ CYGPKG_HAL_ARM_MDBMX1_ADS ++ CYGPKG_IO_ETH_DRIVERS ++ CYGPKG_DEVS_ETH_ARM_MX1ADS ++ CYGPKG_DEVS_ETH_CL_CS8900A ++ CYGPKG_COMPRESS_ZLIB ++ CYGPKG_IO_FLASH ++ CYGPKG_DEVS_FLASH_ARM_AMD_AM29 ++ } ++ description " ++ The mx1ads target provides the packages needed to run ++ eCos on a Freescale MC9328MX1 ADS board." ++} ++ ++target mx21ads { ++ alias { "Freescale i.MX21 ADS board" mx21 mx21ads } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX21 ++ CYGPKG_HAL_ARM_MX21ADS ++ } ++ description " ++ The mx21ads target provides the packages needed to run ++ eCos on a Freescale i.MX21 ADS board." ++} ++ ++target mx25_3stack { ++ alias { "Freescale i.MX25 3-Stack board" mx25 mx25_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX25 ++ CYGPKG_HAL_ARM_MX25_3STACK ++ } ++ description " ++ The mx25_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX25 3-Stack board." ++} ++ ++target mx27ads { ++ alias { "Freescale i.MX27 ADS board" mx27 mx27ads } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX27 ++ CYGPKG_HAL_ARM_MX27ADS ++ } ++ description " ++ The mx27ads target provides the packages needed to run ++ eCos on a Freescale i.MX27 ADS board." ++} ++ ++target mx27_3stack { ++ alias { "Freescale i.MX27 3-Stack board" mx27_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX27 ++ CYGPKG_HAL_ARM_MX27_3STACK ++ } ++ description " ++ The mx27_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX27 3-Stack board." ++} ++ ++target mx31ads { ++ alias { "Freescale i.MX31 ADS board" mx31 mx31ads } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX31 ++ CYGPKG_HAL_ARM_MX31ADS ++ } ++ description " ++ The mx31ads target provides the packages needed to run ++ eCos on a Freescale i.MX31 ADS board." ++} ++ ++target mx31_3stack { ++ alias { "Freescale i.MX31 3-Stack board" mx31 mx31_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX31 ++ CYGPKG_HAL_ARM_MX31_3STACK ++ } ++ description " ++ The mx31_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX31 3-Stack board." ++} ++ ++target mx35_3stack { ++ alias { "Freescale i.MX35 3-Stack board" mx35 mx35_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX35 ++ CYGPKG_HAL_ARM_MX35_3STACK ++ } ++ description " ++ The mx35_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX35 3-Stack board." ++} ++ ++target mx35evb { ++ alias { "Freescale i.MX35 EVB board" mx35evb } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX35 ++ CYGPKG_HAL_ARM_MX35EVB ++ } ++ description " ++ The mx35evb target provides the packages needed to run ++ eCos on a Freescale i.MX35 EVB board." ++} ++ ++ ++target mx37_3stack { ++ alias { "Freescale i.MX37 3-Stack board" mx37 mx37_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX37 ++ CYGPKG_HAL_ARM_MX37_3STACK ++ } ++ description " ++ The mx37_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX37 3-Stack board." ++} ++ ++target mx51_3stack { ++ alias { "Freescale i.MX51 3-Stack board" mx51 mx51_3stack } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX51 ++ CYGPKG_HAL_ARM_MX51_3STACK ++ } ++ description " ++ The mx51_3stack target provides the packages needed to run ++ eCos on a Freescale i.MX51 3-Stack board." ++} ++ ++target mx51_babbage { ++ alias { "Freescale i.MX51 Babbage board" mx51 mx51_babbage } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX51 ++ CYGPKG_HAL_ARM_MX51_BABBAGE ++ } ++ description " ++ The mx51_babbage target provides the packages needed to run ++ eCos on a Freescale i.MX51 Babbage board." ++} ++ ++target mx23_armadillo { ++ alias { "Freescale i.MX23 Armadillo board" mx23 mx23_armadillo } ++ packages { CYGPKG_HAL_ARM ++ CYGPKG_HAL_ARM_MX23 ++ CYGPKG_HAL_ARM_MX23_ARMADILLO ++ } ++ description " ++ The mx23_armadillo target provides the packages needed to run ++ eCos on a Freescale i.MX23 Armadillo board." ++} ++ + # -------------------------------------------------------------------------- + # SH targets + +@@ -6574,4 +7188,11 @@ + description "Another Tiny HTTP server." + } + ++package CYGPKG_DEVS_IMX_IPU { ++ alias { "Support IPU on Freescale i.MX platforms" } ++ directory devs/ipu/arm/imx ++ script imx_ipu.cdl ++ description " ++ This package contains an IPU driver for i.MX chips" ++} + +diff -urNad redboot-imx-200952~/packages/hal/arm/arch/current/src/arm.ld redboot-imx-200952/packages/hal/arm/arch/current/src/arm.ld +--- redboot-imx-200952~/packages/hal/arm/arch/current/src/arm.ld 2002-08-28 03:02:49.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/arch/current/src/arm.ld 2010-01-26 17:33:15.142957624 +0000 +@@ -108,7 +108,7 @@ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + PROVIDE (__stext = ABSOLUTE(.)); \ +- *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \ ++ *(.text*) *(i.*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \ + *(.glue_7) *(.glue_7t) \ + } > _region_ \ + _etext = .; PROVIDE (__etext = .); +@@ -131,6 +131,14 @@ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ ++#define SECTION_extab(_region_, _vma_, _lma_) \ ++ .extab _vma_ : _lma_ \ ++ { FORCE_OUTPUT; *(.ARM.extab*) } \ ++ > _region_ ++#define SECTION_exidx(_region_, _vma_, _lma_) \ ++ .exidx _vma_ : _lma_ \ ++ { FORCE_OUTPUT; *(.ARM.exidx*) } \ ++ > _region_ + #endif // CYGPRI_PID_BE_WORKAROUND + + #define SECTION_fixup(_region_, _vma_, _lma_) \ +@@ -191,10 +199,10 @@ + } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .rela.got : { *(.rela.got) } > _region_ \ +- .rel.ctors : { *(.rel.ctors) } > _region_ \ +- .rela.ctors : { *(.rela.ctors) } > _region_ \ +- .rel.dtors : { *(.rel.dtors) } > _region_ \ +- .rela.dtors : { *(.rela.dtors) } > _region_ \ ++ .rel.init_array : { *(.rel.init_array) } > _region_ \ ++ .rela.init_array : { *(.rela.init_array } > _region_ \ ++ .rel.fini_array : { *(.rel.fini_array) } > _region_ \ ++ .rela.fini_array : { *(.rela.fini_array) } > _region_ \ + .rel.init : { *(.rel.init) } > _region_ \ + .rela.init : { *(.rela.init) } > _region_ \ + .rel.fini : { *(.rel.fini) } > _region_ \ +@@ -226,12 +234,12 @@ + #define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); \ +- *(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \ ++ *(.data*) *(.data1) *(.constdata*) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \ + . = ALIGN (4); \ + KEEP(*( SORT (.ecos.table.*))) ; \ + . = ALIGN (4); \ +- __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \ +- __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \ ++ __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.init_array.*))) KEEP(*(SORT(.init_array))) __CTOR_END__ = ABSOLUTE (.); \ ++ __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.fini_array*))) __DTOR_END__ = ABSOLUTE (.); \ + *(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \ + . = ALIGN (4); *(.2ram.*) } \ + > _region_ \ +diff -urNad redboot-imx-200952~/packages/hal/arm/arch/current/src/redboot_linux_exec.c redboot-imx-200952/packages/hal/arm/arch/current/src/redboot_linux_exec.c +--- redboot-imx-200952~/packages/hal/arm/arch/current/src/redboot_linux_exec.c 2005-04-21 18:17:55.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/arch/current/src/redboot_linux_exec.c 2010-01-26 17:33:15.142957624 +0000 +@@ -139,6 +139,9 @@ + + #endif // CYGARC_HAL_MMU_OFF + ++#ifndef CYGARC_HAL_EXEC_FIXUP ++#define CYGARC_HAL_EXEC_FIXUP() "" ++#endif + // + // Parameter info for Linux kernel + // ** C A U T I O N ** This setup must match "asm-arm/setup.h" +@@ -327,8 +330,7 @@ + + // Check to see if a valid image has been loaded + if (entry_address == (unsigned long)NO_MEMORY) { +- diag_printf("Can't execute Linux - invalid entry address\n"); +- return; ++ diag_printf("Warning: invalid entry address but still continue ...\n"); + } + // Default physical entry point for Linux is kernel base. + entry = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS; +@@ -364,6 +366,7 @@ + { + return; + } ++ diag_printf("entry=0x%x, target=0x%x\n", (unsigned int)entry, (unsigned int)target); + + // Set up parameters to pass to kernel + +@@ -495,6 +498,8 @@ + __tramp_start__, + __tramp_end__ - __tramp_start__); + ++ extern unsigned int system_rev; ++ + asm volatile ( + CYGARC_HAL_MMU_OFF(%5) + "__tramp_start__:\n" +@@ -508,6 +513,7 @@ + " subs %2,%2,#4;\n" + " bne 1b;\n" + "2:\n" ++ CYGARC_HAL_EXEC_FIXUP() + " mov r0,#0;\n" // Set board type + " mov r1,%3;\n" // Machine type + " mov r2,%6;\n" // Kernel parameters +@@ -520,7 +526,8 @@ + "r"(CYGHWR_REDBOOT_ARM_MACHINE_TYPE), + "r"(target), + "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS)), +- "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS)) ++ "r"(CYGARC_PHYSICAL_ADDRESS(CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS)), ++ "r"(system_rev) + : "r0", "r1" + ); + } +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/cdl/imx_redboot_common.cdl redboot-imx-200952/packages/hal/arm/imx/current/cdl/imx_redboot_common.cdl +--- redboot-imx-200952~/packages/hal/arm/imx/current/cdl/imx_redboot_common.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/cdl/imx_redboot_common.cdl 2010-01-26 17:33:15.432957762 +0000 +@@ -0,0 +1,130 @@ ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++ ++cdl_package CYGPKG_IMX_COMMON { ++ display "Common for all Freescale i.MX platforms" ++ include_dir cyg/hal ++ ++ cdl_option CYGHWR_IMX_GPIO { ++ display "IMX GPIO driver" ++ default_value 1 ++ description " ++ When this option is enabled, it indicates GPIO is ++ supported on the i.MX platforms" ++ define_proc { ++ puts $::cdl_system_header "#define IMX_GPIO" ++ } ++ compile -library=libextras.a imx_gpio.c ++ } ++ ++ cdl_option CYGHWR_IMX_COMMON_COMMANDS { ++ display "IMX common Redboot commands" ++ default_value 1 ++ description " ++ When this option is enabled, it indicates support for ++ new Redboot commands added for i.MX that are common ++ across platforms" ++ compile -library=libextras.a imx_redboot_commands.c ++ } ++ ++ cdl_option CYGHWR_IMX_IDE { ++ display "Support IDE disks." ++ default_value 0 ++ implements CYGINT_HAL_PLF_IF_IDE ++ description " ++ When this option is enabled, RedBoot will support IDE disks." ++ compile -library=libextras.a imx_ata.c ++ } ++ ++ cdl_component CYGHWR_IMX_DISPLAY { ++ display "Display Redboot prompt on LCD or VGA/DVI monitors for Freescale MXC platformsr" ++ active_if CYGPKG_DEVS_IMX_IPU ++ default_value 0 ++ compile -library=libextras.a display_prompt.c ++ } ++ ++ cdl_option CYGHWR_IMX_UART { ++ display "IMX UART driver" ++ default_value 1 ++ description " ++ When this option is enabled, it indicates support for ++ new UART on i.MX platforms" ++ compile -library=libextras.a imx_uart.c ++ } ++ ++ cdl_interface CYGHWR_IMX_UART1 { ++ display "UART1 available as diagnostic/debug channel" ++ active_if {CYGHWR_IMX_UART} ++ description " ++ The chip has multiple serial channels which may be ++ used for different things on different platforms. This ++ interface allows a platform to indicate that the specified ++ serial port can be used as a diagnostic and/or debug channel." ++ } ++ cdl_interface CYGHWR_IMX_UART2 { ++ display "UART2 available as diagnostic/debug channel" ++ active_if {CYGHWR_IMX_UART} ++ description " ++ The chip has multiple serial channels which may be ++ used for different things on different platforms. This ++ interface allows a platform to indicate that the specified ++ serial port can be used as a diagnostic and/or debug channel." ++ } ++ cdl_interface CYGHWR_IMX_UART3 { ++ display "UART3 available as diagnostic/debug channel" ++ active_if {CYGHWR_IMX_UART} ++ description " ++ The chip has multiple serial channels which may be ++ used for different things on different platforms. This ++ interface allows a platform to indicate that the specified ++ serial port can be used as a diagnostic and/or debug channel." ++ } ++ cdl_interface CYGHWR_IMX_UART4 { ++ display "UART4 available as diagnostic/debug channel" ++ active_if {CYGHWR_IMX_UART} ++ description " ++ The chip has multiple serial channels which may be ++ used for different things on different platforms. This ++ interface allows a platform to indicate that the specified ++ serial port can be used as a diagnostic and/or debug channel." ++ } ++ cdl_interface CYGHWR_IMX_UART5 { ++ display "UART5 available as diagnostic/debug channel" ++ active_if {CYGHWR_IMX_UART} ++ description " ++ The chip has multiple serial channels which may be ++ used for different things on different platforms. This ++ interface allows a platform to indicate that the specified ++ serial port can be used as a diagnostic and/or debug channel." ++ } ++} +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_ata.h redboot-imx-200952/packages/hal/arm/imx/current/include/imx_ata.h +--- redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_ata.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/include/imx_ata.h 2010-01-26 17:33:15.432957762 +0000 +@@ -0,0 +1,130 @@ ++#ifndef _IMX_ATA_H_ ++#define _IMX_ATA_H_ ++//========================================================================== ++// ++// imx_ata.h ++// ++// Support ATA on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Mahesh Mahadevan ++// Contributors: Mahesh Mahadevan ++// Date: 2008-11-18 ++// ++//========================================================================== ++#define FSL_ATA_TIMING_REGS 0x00 ++#define FSL_ATA_FIFO_FILL 0x20 ++#define FSL_ATA_CONTROL 0x24 ++#define FSL_ATA_INT_PEND 0x28 ++#define FSL_ATA_INT_EN 0x2C ++#define FSL_ATA_INT_CLEAR 0x30 ++#define FSL_ATA_FIFO_ALARM 0x34 ++#define FSL_ATA_ADMA_ERROR_STATUS 0x38 ++#define FSL_ATA_SYS_DMA_BADDR 0x3C ++#define FSL_ATA_ADMA_SYS_ADDR 0x40 ++#define FSL_ATA_BLOCK_COUNT 0x48 ++#define FSL_ATA_BURST_LENGTH 0x4C ++#define FSL_ATA_SECTOR_SIZE 0x50 ++#define FSL_ATA_DRIVE_DATA 0xA0 ++#define FSL_ATA_DFTR 0xA4 ++#define FSL_ATA_DSCR 0xA8 ++#define FSL_ATA_DSNR 0xAC ++#define FSL_ATA_DCLR 0xB0 ++#define FSL_ATA_DCHR 0xB4 ++#define FSL_ATA_DDHR 0xB8 ++#define FSL_ATA_DCDR 0xBC ++#define FSL_ATA_DRIVE_CONTROL 0xD8 ++ ++/* bits within FSL_ATA_CONTROL */ ++#define FSL_ATA_CTRL_DMA_SRST 0x1000 ++#define FSL_ATA_CTRL_DMA_64ADMA 0x800 ++#define FSL_ATA_CTRL_DMA_32ADMA 0x400 ++#define FSL_ATA_CTRL_DMA_STAT_STOP 0x200 ++#define FSL_ATA_CTRL_DMA_ENABLE 0x100 ++#define FSL_ATA_CTRL_FIFO_RST_B 0x80 ++#define FSL_ATA_CTRL_ATA_RST_B 0x40 ++#define FSL_ATA_CTRL_FIFO_TX_EN 0x20 ++#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10 ++#define FSL_ATA_CTRL_DMA_PENDING 0x08 ++#define FSL_ATA_CTRL_DMA_ULTRA 0x04 ++#define FSL_ATA_CTRL_DMA_WRITE 0x02 ++#define FSL_ATA_CTRL_IORDY_EN 0x01 ++ ++/* bits within the interrupt control registers */ ++#define FSL_ATA_INTR_ATA_INTRQ1 0x80 ++#define FSL_ATA_INTR_FIFO_UNDERFLOW 0x40 ++#define FSL_ATA_INTR_FIFO_OVERFLOW 0x20 ++#define FSL_ATA_INTR_CTRL_IDLE 0x10 ++#define FSL_ATA_INTR_ATA_INTRQ2 0x08 ++#define FSL_ATA_INTR_DMA_ERR 0x04 ++#define FSL_ATA_INTR_DMA_TRANS_OVER 0x02 ++ ++/* ADMA Addr Descriptor Attribute Filed */ ++#define FSL_ADMA_DES_ATTR_VALID 0x01 ++#define FSL_ADMA_DES_ATTR_END 0x02 ++#define FSL_ADMA_DES_ATTR_INT 0x04 ++#define FSL_ADMA_DES_ATTR_SET 0x10 ++#define FSL_ADMA_DES_ATTR_TRAN 0x20 ++#define FSL_ADMA_DES_ATTR_LINK 0x30 ++ ++#define PIO_XFER_MODE_0 0 ++#define PIO_XFER_MODE_1 1 ++#define PIO_XFER_MODE_2 2 ++#define PIO_XFER_MODE_3 3 ++#define PIO_XFER_MODE_4 4 ++ ++#define ATA_ID_PROD 27 ++#define ATA_ID_PROD_LEN 40 ++ ++#define ATA_BUSY (1 << 7) ++#define ATA_DRQ (1 << 3) ++#define ATA_ERR (1) ++ ++#define ATA_IEN (1 << 1) ++#define ATA_SRST (1 << 2) ++ ++#define ATA_CMD_READ 0x20 ++#define ATA_CMD_WRITE 0x30 ++#define ATA_CMD_READ_MULTI 0xC4 ++#define ATA_CMD_WRITE_MULTI 0xC5 ++#define ATA_CMD_ID_ATA 0xEC ++#define ATA_CMD_SET_FEATURES 0xEF ++ ++#define ATA_SECTOR_SIZE 512 ++#define MAX_NUMBER_OF_SECTORS 256 ++#endif // _IMX_ATA_H_ +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_common.h redboot-imx-200952/packages/hal/arm/imx/current/include/imx_common.h +--- redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_common.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/include/imx_common.h 2010-01-26 17:33:15.442961512 +0000 +@@ -0,0 +1,48 @@ ++#ifndef IMX_COMMON_H ++#define IMX_COMMON_H ++ ++/*============================================================================= ++// ++// imx_common.h ++// ++// i.MX common header file ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//===========================================================================*/ ++ ++typedef void display_putc_func_t(char c); ++void mxc_ipu_iomux_config(void); ++ ++#endif +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_gpio.h redboot-imx-200952/packages/hal/arm/imx/current/include/imx_gpio.h +--- redboot-imx-200952~/packages/hal/arm/imx/current/include/imx_gpio.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/include/imx_gpio.h 2010-01-26 17:33:15.442961512 +0000 +@@ -0,0 +1,100 @@ ++/*************************************************************************** ++* ++* MX51_GPIO.H ++* ++* Macros definations for MX51 GPIO. ++* ++*************************************************************************** ++* ++* Author(s) : Ray Sun-B17777 ++* Create Date : 2008-11-10 ++* Description : GPIO definitions for i.MX ++* ++***************************************************************************/ ++ ++ ++#ifndef _IMX_GPIO_H_ ++#define _IMX_GPIO_H_ ++ ++#include ++ ++/* Defines added as number of GPIO modules vary between different i.MX platforms */ ++#ifndef GPIO1_BASE_ADDR ++#define GPIO1_BASE_ADDR 0 ++#endif ++ ++#ifndef GPIO2_BASE_ADDR ++#define GPIO2_BASE_ADDR 0 ++#endif ++ ++#ifndef GPIO3_BASE_ADDR ++#define GPIO3_BASE_ADDR 0 ++#endif ++ ++#ifndef GPIO4_BASE_ADDR ++#define GPIO4_BASE_ADDR 0 ++#endif ++ ++#ifndef GPIO5_BASE_ADDR ++#define GPIO5_BASE_ADDR 0 ++#endif ++ ++#ifndef GPIO6_BASE_ADDR ++#define GPIO6_BASE_ADDR 0 ++#endif ++ ++#define GPIO_DR_OFFSET 0x0000 ++#define GPIO_GDIR_OFFSET 0x0004 ++#define GPIO_PSR_OFFSET 0x0008 ++#define GPIO_ICR1_OFFSET 0x000C ++#define GPIO_ICR2_OFFSET 0x0010 ++#define GPIO_IMR_OFFSET 0x0014 ++#define GPIO_ISR_OFFSET 0x0018 ++#define GPIO_EDGE_SEL_OFFSET 0x001C ++ ++typedef enum ++{ ++ GPIO_PORT1 = GPIO1_BASE_ADDR, ++ GPIO_PORT2 = GPIO2_BASE_ADDR, ++ GPIO_PORT3 = GPIO3_BASE_ADDR, ++ GPIO_PORT4 = GPIO4_BASE_ADDR, ++ GPIO_PORT5 = GPIO5_BASE_ADDR, ++ GPIO_PORT6 = GPIO6_BASE_ADDR, ++} GPIO_PORT; ++ ++typedef struct ++{ ++ unsigned int DR; ++ unsigned int GDIR; ++ unsigned int PSR; ++ unsigned int ICR1; ++ unsigned int ICR2; ++ unsigned int IMR; ++ unsigned int ISR; ++ unsigned int EDGE_SEL; ++} CSP_GPIO_REGS, *PCSP_GPIO_REGS; ++ ++ ++#define GPIO_GDIR_INPUT 0 // GPIO pin is input ++#define GPIO_GDIR_OUTPUT 1 // GPIO pin is output ++ ++#define GPIO_ICR_LOW_LEVEL 0 // Interrupt is low-level ++#define GPIO_ICR_HIGH_LEVEL 1 // Interrupt is high-level ++#define GPIO_ICR_RISE_EDGE 2 // Interrupt is rising edge ++#define GPIO_ICR_FALL_EDGE 3 // Interrupt is falling edge ++ ++#define GPIO_IMR_MASKED 0 // Interrupt is masked ++#define GPIO_IMR_UNMASKED 1 // Interrupt is unmasked ++ ++#define GPIO_EDGE_SEL_DISABLE 0 // Edge select is disabled ++#define GPIO_EDGE_SEL_ENABLE 1 // Edge select is enabled ++ ++#define GPIO_PIN_MASK(pin) (1U << (pin)) ++#define GPIO_PIN_VAL(val, pin) ((val) << (pin)) ++#define GPIO_ICR_MASK(pin) (0x3U << ((pin) << 1)) ++#define GPIO_ICR_VAL(val, pin) ((val) << ((pin) << 1)) ++ ++int gpio_dir_config(int port, int pin, int dir); ++int gpio_write_data(int port, int pin, unsigned int attr); ++ ++#endif +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/display_prompt.c redboot-imx-200952/packages/hal/arm/imx/current/src/display_prompt.c +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/display_prompt.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/display_prompt.c 2010-01-26 17:33:15.442961512 +0000 +@@ -0,0 +1,263 @@ ++//========================================================================== ++// ++// display_prompt.c ++// ++// i.mx - display support (based on sa11x0 platforms) ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++#include // IO macros ++#include // Virtual vector support ++#include // Register state info ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "font.h" ++ ++// Virtual screen info ++static int curX = 0; // Last used position ++static int curY = 0; ++ ++struct display_frame { ++ unsigned short pixels[LCD_HEIGHT][LCD_WIDTH]; ++}; ++static volatile struct display_frame *fp = (struct display_frame *)DISPLAY_BUFFER_ADDR; ++ ++static int fg = 0xFFFFFFFF; ++static int bg = 0; ++ ++static bool cursor_enable = false; // TODO ++ ++#define VISUAL_FONT_HEIGHT (FONT_STRETCH_Y * FONT_HEIGHT) ++#define VISUAL_FONT_WIDTH (FONT_STRETCH_X * FONT_WIDTH) ++ ++#ifdef ROTATE_NONE ++void set_pixel(int row, int col, int val) ++{ ++ int r, c; ++ // draw x ++ for (r = 0; r < FONT_STRETCH_X; r++) { ++ fp->pixels[row * FONT_STRETCH_Y][LCD_WIDTH - (col * FONT_STRETCH_X + r)] = val; ++ } ++ // draw y ++ for (c = 0; c < FONT_STRETCH_Y; c++) { ++ fp->pixels[row * FONT_STRETCH_Y + c][LCD_WIDTH - (col * FONT_STRETCH_X)] = val; ++ } ++} ++/* ++ * To restore the pixel value into val. ++ * This function is used along with set_pixel() for display scroll. ++ * Need to take care of the stretching effect. ++ */ ++void get_pixel(int row, int col, int *val) ++{ ++ *val = fp->pixels[row * FONT_STRETCH_Y][LCD_WIDTH - col * FONT_STRETCH_X]; ++} ++#define VISUAL_SCREEN_WIDTH (LCD_WIDTH / VISUAL_FONT_WIDTH) ++#define VISUAL_SCREEN_HEIGHT (LCD_HEIGHT / VISUAL_FONT_HEIGHT) ++#endif ++ ++#ifdef ROTATE_90 ++void set_pixel(int row, int col, int val) ++{ ++ int r, c; ++ // draw x ++ for (r = 0; r < FONT_STRETCH_X; r++) { ++ fp->pixels[col * FONT_STRETCH_X + r][row * FONT_STRETCH_Y] = val; ++ } ++ // draw y ++ for (c = 0; c < FONT_STRETCH_Y; c++) { ++ fp->pixels[col * FONT_STRETCH_X][row * FONT_STRETCH_Y + c] = val; ++ } ++} ++/* ++ * To restore the pixel value into val. ++ * This function is used along with set_pixel() for display scroll. ++ * Need to take care of the stretching effect. ++ */ ++void get_pixel(int row, int col, int *val) ++{ ++ *val = fp->pixels[col * FONT_STRETCH_X][row * FONT_STRETCH_Y]; ++} ++#define VISUAL_SCREEN_WIDTH (LCD_HEIGHT / VISUAL_FONT_WIDTH) ++#define VISUAL_SCREEN_HEIGHT (LCD_WIDTH / VISUAL_FONT_HEIGHT) ++#endif ++ ++/*! ++ * Render a character at position (X,Y) with current background/foreground. ++ * The x and y passed in is for the character 'c' position in the virtual screen. ++ */ ++static void display_drawc(cyg_int8 c, int x, int y) ++{ ++ cyg_uint8 bits; ++ int l, p; ++ ++ if ((x < 0) || (x >= VISUAL_SCREEN_WIDTH) || ++ (y < 0) || (y >= VISUAL_SCREEN_HEIGHT)) ++ return; ++ for (l = 0; l < FONT_HEIGHT; l++) { ++ bits = font_table[c-FIRST_CHAR][l]; ++ for (p = 0; p < FONT_WIDTH; p++) { ++ if (bits & 0x1) { ++ set_pixel(y * FONT_HEIGHT + l, (x * FONT_WIDTH + p), fg); ++ } else { ++ set_pixel(y * FONT_HEIGHT + l, (x * FONT_WIDTH + p), bg); ++ } ++ bits >>= 1; ++ } ++ } ++} ++ ++static void display_scroll(void) ++{ ++ int row, col, val; ++ ++ // move up screen by 1 (virtual) row ++ for (row = FONT_HEIGHT; row < VISUAL_SCREEN_HEIGHT * FONT_HEIGHT; row++) { ++ for (col = 0; col < VISUAL_SCREEN_WIDTH * FONT_WIDTH; col++) { ++ get_pixel(row, col, &val); ++ set_pixel(row - FONT_HEIGHT, col, val); ++ //fill in the last row ++ if (row >= VISUAL_SCREEN_HEIGHT * FONT_HEIGHT - FONT_HEIGHT) { ++ set_pixel(row, col, bg); ++ } ++ } ++ } ++ ++ HAL_CACHE_FLUSH_ALL(); ++ if (cursor_enable) { ++ display_drawc(CURSOR_ON, curX, curY); ++ } ++} ++ ++// Draw one character at the current position ++void imx_display_putc(char c) ++{ ++ if (cursor_enable) { ++// display_drawc(screen[curY][curX], curX, curY); ++ } ++ switch (c) { ++ case '\r': ++ curX = 0; ++ break; ++ case '\n': ++ curY++; ++ break; ++ case '\b': ++ curX--; ++ if (curX < 0) { ++ curY--; ++ if (curY < 0) ++ curY = 0; ++ curX = VISUAL_SCREEN_WIDTH - 1; ++ } ++ break; ++ case '\t': ++ curX = (curX + 8) & (~0x7); ++ if (curX >= VISUAL_SCREEN_WIDTH) { ++ curY++; ++ curX -= VISUAL_SCREEN_WIDTH; ++ } ++ break; ++ default: ++ if (((cyg_uint8)c < FIRST_CHAR) || ((cyg_uint8)c > LAST_CHAR)) ++ c = '.'; ++ display_drawc(c, curX, curY); ++ curX++; ++ if (curX == VISUAL_SCREEN_WIDTH) { ++ curY++; ++ curX = 0; ++ } ++ } ++ if (curY >= VISUAL_SCREEN_HEIGHT) { ++ display_scroll(); ++ curY = VISUAL_SCREEN_HEIGHT - 1; ++ } ++ if (cursor_enable) { ++ display_drawc(CURSOR_ON, curX, curY); ++ } ++} ++extern display_putc_func_t *display_putc; ++ ++static void redboot_init_display_putc(void) ++{ ++ int i, j; ++ ++ display_putc = imx_display_putc; ++ ++ // clear up the display ++ for (i = 0; i < VISUAL_SCREEN_HEIGHT * FONT_HEIGHT; i++) { ++ for (j = 0; j < VISUAL_SCREEN_WIDTH * FONT_WIDTH; j++) { ++ set_pixel(i, j, bg); ++ } ++ } ++ HAL_CACHE_FLUSH_ALL(); ++} ++ ++static void clear_display(int argc,char *argv[]) ++{ ++ int i, j; ++ ++ display_putc = imx_display_putc; ++ ++ // clear up the display ++ for (i = 0; i < VISUAL_SCREEN_HEIGHT * FONT_HEIGHT; i++) { ++ for (j = 0; j < VISUAL_SCREEN_WIDTH * FONT_WIDTH; j++) { ++ set_pixel(i, j, bg); ++ } ++ } ++ // reset position ++ curX = 0; ++ curY = 0; ++} ++ ++#ifdef CYGPKG_REDBOOT ++RedBoot_cmd("clear", ++ "Clear the LCD/monitor display screen", ++ "", ++ clear_display ++ ); ++ ++RedBoot_init(redboot_init_display_putc, RedBoot_INIT_SECOND); ++#endif ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/font.h redboot-imx-200952/packages/hal/arm/imx/current/src/font.h +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/font.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/font.h 2010-01-26 17:33:15.442961512 +0000 +@@ -0,0 +1,153 @@ ++//========================================================================== ++// ++// font.h ++// ++// i.mx - display support (based on sa11x0 platforms) ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#ifndef _LCD_FONT_H_ ++#define _LCD_FONT_H_ ++ ++// 8x8 Font - from Helios ++ ++#define FIRST_CHAR 0x20 ++#define LAST_CHAR 0x7F ++#define FONT_HEIGHT 8 ++#define FONT_WIDTH 8 ++#define CURSOR_ON 0x7F ++#define CURSOR_OFF 0x20 ++static char font_table[LAST_CHAR-FIRST_CHAR+1][8] = ++{ ++ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* */ ++ { 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x00 }, /* ! */ ++ { 0x36, 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* " */ ++ { 0x6C, 0x6C, 0xFE, 0x6C, 0xFE, 0x6C, 0x6C, 0x00 }, /* # */ ++ { 0x30, 0xFC, 0x16, 0x7C, 0xD0, 0x7E, 0x18, 0x00 }, /* $ */ ++ { 0x06, 0x66, 0x30, 0x18, 0x0C, 0x66, 0x60, 0x00 }, /* % */ ++ { 0x1C, 0x36, 0x36, 0x1C, 0xB6, 0x66, 0xDC, 0x00 }, /* & */ ++ { 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ' */ ++ { 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00 }, /* ( */ ++ { 0x0C, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0C, 0x00 }, /* ) */ ++ { 0x00, 0x18, 0x7E, 0x3C, 0x7E, 0x18, 0x00, 0x00 }, /* * */ ++ { 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00 }, /* + */ ++ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x0C }, /* , */ ++ { 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00 }, /* - */ ++ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00 }, /* . */ ++ { 0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00, 0x00 }, /* / */ ++ { 0x3C, 0x66, 0x76, 0x7E, 0x6E, 0x66, 0x3C, 0x00 }, /* 0 */ ++ { 0x18, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00 }, /* 1 */ ++ { 0x3C, 0x66, 0x60, 0x30, 0x18, 0x0C, 0x7E, 0x00 }, /* 2 */ ++ { 0x3C, 0x66, 0x60, 0x38, 0x60, 0x66, 0x3C, 0x00 }, /* 3 */ ++ { 0x30, 0x38, 0x3C, 0x36, 0x7E, 0x30, 0x30, 0x00 }, /* 4 */ ++ { 0x7E, 0x06, 0x3E, 0x60, 0x60, 0x66, 0x3C, 0x00 }, /* 5 */ ++ { 0x38, 0x0C, 0x06, 0x3E, 0x66, 0x66, 0x3C, 0x00 }, /* 6 */ ++ { 0x7E, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00 }, /* 7 */ ++ { 0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00 }, /* 8 */ ++ { 0x3C, 0x66, 0x66, 0x7C, 0x60, 0x30, 0x1C, 0x00 }, /* 9 */ ++ { 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00 }, /* : */ ++ { 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x0C }, /* ; */ ++ { 0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00 }, /* < */ ++ { 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00 }, /* = */ ++ { 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00 }, /* > */ ++ { 0x3C, 0x66, 0x30, 0x18, 0x18, 0x00, 0x18, 0x00 }, /* ? */ ++ { 0x3C, 0x66, 0x76, 0x56, 0x76, 0x06, 0x3C, 0x00 }, /* @ */ ++ { 0x3C, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00 }, /* A */ ++ { 0x3E, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3E, 0x00 }, /* B */ ++ { 0x3C, 0x66, 0x06, 0x06, 0x06, 0x66, 0x3C, 0x00 }, /* C */ ++ { 0x1E, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1E, 0x00 }, /* D */ ++ { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x7E, 0x00 }, /* E */ ++ { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x06, 0x00 }, /* F */ ++ { 0x3C, 0x66, 0x06, 0x76, 0x66, 0x66, 0x3C, 0x00 }, /* G */ ++ { 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00 }, /* H */ ++ { 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00 }, /* I */ ++ { 0x7C, 0x30, 0x30, 0x30, 0x30, 0x36, 0x1C, 0x00 }, /* J */ ++ { 0x66, 0x36, 0x1E, 0x0E, 0x1E, 0x36, 0x66, 0x00 }, /* K */ ++ { 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x7E, 0x00 }, /* L */ ++ { 0xC6, 0xEE, 0xFE, 0xD6, 0xD6, 0xC6, 0xC6, 0x00 }, /* M */ ++ { 0x66, 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x66, 0x00 }, /* N */ ++ { 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* O */ ++ { 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x06, 0x00 }, /* P */ ++ { 0x3C, 0x66, 0x66, 0x66, 0x56, 0x36, 0x6C, 0x00 }, /* Q */ ++ { 0x3E, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x66, 0x00 }, /* R */ ++ { 0x3C, 0x66, 0x06, 0x3C, 0x60, 0x66, 0x3C, 0x00 }, /* S */ ++ { 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00 }, /* T */ ++ { 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* U */ ++ { 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00 }, /* V */ ++ { 0xC6, 0xC6, 0xD6, 0xD6, 0xFE, 0xEE, 0xC6, 0x00 }, /* W */ ++ { 0x66, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00 }, /* X */ ++ { 0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00 }, /* Y */ ++ { 0x7E, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x7E, 0x00 }, /* Z */ ++ { 0x3E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x3E, 0x00 }, /* [ */ ++ { 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00, 0x00 }, /* \ */ ++ { 0x7C, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7C, 0x00 }, /* ] */ ++ { 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ^ */ ++ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF }, /* _ */ ++ { 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ` */ ++ { 0x00, 0x00, 0x3C, 0x60, 0x7C, 0x66, 0x7C, 0x00 }, /* a */ ++ { 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x00 }, /* b */ ++ { 0x00, 0x00, 0x3C, 0x66, 0x06, 0x66, 0x3C, 0x00 }, /* c */ ++ { 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x00 }, /* d */ ++ { 0x00, 0x00, 0x3C, 0x66, 0x7E, 0x06, 0x3C, 0x00 }, /* e */ ++ { 0x38, 0x0C, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x00 }, /* f */ ++ { 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x3C }, /* g */ ++ { 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x66, 0x00 }, /* h */ ++ { 0x18, 0x00, 0x1C, 0x18, 0x18, 0x18, 0x3C, 0x00 }, /* i */ ++ { 0x18, 0x00, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x0E }, /* j */ ++ { 0x06, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x00 }, /* k */ ++ { 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00 }, /* l */ ++ { 0x00, 0x00, 0x6C, 0xFE, 0xD6, 0xD6, 0xC6, 0x00 }, /* m */ ++ { 0x00, 0x00, 0x3E, 0x66, 0x66, 0x66, 0x66, 0x00 }, /* n */ ++ { 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* o */ ++ { 0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06 }, /* p */ ++ { 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0xE0 }, /* q */ ++ { 0x00, 0x00, 0x36, 0x6E, 0x06, 0x06, 0x06, 0x00 }, /* r */ ++ { 0x00, 0x00, 0x7C, 0x06, 0x3C, 0x60, 0x3E, 0x00 }, /* s */ ++ { 0x0C, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x38, 0x00 }, /* t */ ++ { 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x00 }, /* u */ ++ { 0x00, 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00 }, /* v */ ++ { 0x00, 0x00, 0xC6, 0xD6, 0xD6, 0xFE, 0x6C, 0x00 }, /* w */ ++ { 0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x00 }, /* x */ ++ { 0x00, 0x00, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x3C }, /* y */ ++ { 0x00, 0x00, 0x7E, 0x30, 0x18, 0x0C, 0x7E, 0x00 }, /* z */ ++ { 0x30, 0x18, 0x18, 0x0E, 0x18, 0x18, 0x30, 0x00 }, /* { */ ++ { 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00 }, /* | */ ++ { 0x0C, 0x18, 0x18, 0x70, 0x18, 0x18, 0x0C, 0x00 }, /* } */ ++ { 0x8C, 0xD6, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ~ */ ++ { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } /* Block cursor */ ++}; ++ ++#endif // _LCD_FONT_H_ +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_ata.c redboot-imx-200952/packages/hal/arm/imx/current/src/imx_ata.c +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_ata.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/imx_ata.c 2010-01-26 17:33:15.452960637 +0000 +@@ -0,0 +1,413 @@ ++//========================================================================== ++// ++// mxc_ata.c ++// ++// Flash programming to support ATA flash on Freescale MXC platforms ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Mahesh Mahadevan ++// Contributors: Mahesh Mahadevan ++// Date: 2008-11-18 Initial version ++// ++//========================================================================== ++// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++static struct fsl_ata_time_regs { ++ unsigned char time_off, time_on, time_1, time_2w; ++ unsigned char time_2r, time_ax, time_pio_rdx, time_4; ++ unsigned char time_9, time_m, time_jn, time_d; ++ unsigned char time_k, time_ack, time_env, time_rpx; ++ unsigned char time_zah, time_mlix, time_dvh, time_dzfs; ++ unsigned char time_dvs, time_cvh, time_ss, time_cyc; ++}; ++extern void mxc_ata_iomux_setup(void); ++ ++/* ++ * This structure contains the timing parameters for ++ * ATA bus timing in the 5 PIO modes. The timings ++ * are in nanoseconds, and are converted to clock ++ * cycles before being stored in the ATA controller ++ * timing registers. ++ */ ++static struct { ++ short t0, t1, t2_8, t2_16, t2i, t4, t9, tA; ++} pio_specs[] = { ++ [0] = { ++ .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 40, .t4 = ++ 30, .t9 = 20, .tA = 50,}, ++ [1] = { ++ .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, .t4 = ++ 20, .t9 = 15, .tA = 50,}, ++ [2] = { ++ .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, .t4 = ++ 15, .t9 = 10, .tA = 50,}, ++ [3] = { ++ .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, .t4 = ++ 10, .t9 = 10, .tA = 50,}, ++ [4] = { ++ .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, .t4 = ++ 10, .t9 = 10, .tA = 50,}, ++ }; ++ ++#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0]) ++ ++static void update_timing_config(struct fsl_ata_time_regs *tp) ++{ ++ unsigned int *lp = (unsigned int *) tp; ++ unsigned int *ctlp = (unsigned int *) ATA_BASE_ADDR; ++ int i; ++ ++ for (i = 0; i < 5; i++) { ++ writel(*lp, ctlp); ++ lp++; ++ ctlp++; ++ } ++} ++ ++static void set_ata_bus_timing(unsigned char xfer_mode) ++{ ++ int speed = xfer_mode; ++ struct fsl_ata_time_regs tr = { 0 }; ++ int T = 1 * 1000 * 1000 * 1000 / get_main_clock(IPG_CLK); ++ ++ if (speed >= NR_PIO_SPECS) ++ return; ++ tr.time_off = 3; ++ tr.time_on = 3; ++ ++ tr.time_1 = (pio_specs[speed].t1 + T) / T; ++ tr.time_2w = (pio_specs[speed].t2_8 + T) / T; ++ ++ tr.time_2r = (pio_specs[speed].t2_8 + T) / T; ++ tr.time_ax = (pio_specs[speed].tA + T) / T + 2; ++ tr.time_pio_rdx = 1; ++ tr.time_4 = (pio_specs[speed].t4 + T) / T; ++ ++ tr.time_9 = (pio_specs[speed].t9 + T) / T; ++ ++ update_timing_config(&tr); ++} ++ ++static unsigned char ata_sff_busy_wait(unsigned int bits, unsigned int max, unsigned int delay) ++{ ++ unsigned char status; ++ unsigned int iterations = 1; ++ ++ if (max != 0) ++ iterations = max; ++ ++ do { ++ hal_delay_us(delay); ++ status = readb(ATA_BASE_ADDR + FSL_ATA_DCDR); ++ if (max != 0) ++ iterations--; ++ } while (status != 0xff && (status & bits) && (iterations > 0)); ++ ++ if (iterations == 0) { ++ diag_printf("ata_sff_busy_wait timeout status = %x\n", status); ++ return 0xff; ++ } ++ ++ return status; ++} ++ ++static void ata_sff_exec_command(unsigned short cmd) ++{ ++ writeb(cmd, ATA_BASE_ADDR + FSL_ATA_DCDR); ++ readb(ATA_BASE_ADDR + FSL_ATA_DRIVE_CONTROL); ++ hal_delay_us(4); ++} ++ ++static void write_sector_pio(unsigned int *addr, int num_of_sectors) ++{ ++ int i, j; ++ ++ for (i = 0; i < num_of_sectors; i++) { ++ for (j= 0; j < ATA_SECTOR_SIZE; j = j + 4) { ++ /* Write 4 bytes in each iteration */ ++ writew((*addr & 0xFFFF), ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA) ; ++ writew(((*addr >> 16 ) & 0xFFFF), ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA) ; ++ addr++; ++ } ++ ata_sff_busy_wait(ATA_BUSY, 5000, 50); ++ } ++ readb(ATA_BASE_ADDR + FSL_ATA_DRIVE_CONTROL); ++} ++ ++static void read_sector_pio(unsigned int *addr, int num_of_sectors) ++{ ++ int i, j; ++ unsigned int data[2]; ++ ++ for (i = 0; i < num_of_sectors; i++) { ++ for (j = 0; j < ATA_SECTOR_SIZE; j = j + 4) { ++ /* Read 4 bytes in each iteration */ ++ data[0] = readw(ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA); ++ data[1] = readw(ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA); ++ *addr = ((data[1] << 16) & 0xFFFF0000) | (data[0] & 0xFFFF); ++ addr++; ++ } ++ ata_sff_busy_wait(ATA_BUSY, 5000, 10); ++ } ++ readb(ATA_BASE_ADDR + FSL_ATA_DRIVE_CONTROL); ++} ++ ++cyg_uint8 imx_ide_read_uint8(int ctlr, cyg_uint32 reg) ++{ ++ return readb(ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA + (reg * 4)); ++} ++ ++void imx_ide_write_uint8(int ctlr, cyg_uint32 reg, cyg_uint8 val) ++{ ++ if (reg == IDE_REG_COMMAND) { ++ ata_sff_exec_command(val); ++ } else { ++ writeb(val, ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA + (reg * 4)); ++ } ++} ++ ++cyg_uint16 imx_ide_read_uint16(int ctlr, cyg_uint32 reg) ++{ ++ return readw(ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA + (reg * 4)); ++} ++ ++void imx_ide_write_uint16(int ctlr, cyg_uint32 reg, cyg_uint16 val) ++{ ++ writew(val, ATA_BASE_ADDR + FSL_ATA_DRIVE_DATA + (reg * 4)); ++} ++ ++void imx_ide_write_control(int ctlr, cyg_uint8 val) ++{ ++ writeb(val, ATA_BASE_ADDR + FSL_ATA_DRIVE_CONTROL); ++} ++ ++int imx_ide_hwr_init(void) ++{ ++ mxc_ata_iomux_setup(); ++ ++ /* Deassert the reset bit to enable the interface */ ++ writel(FSL_ATA_CTRL_ATA_RST_B, ATA_BASE_ADDR + FSL_ATA_CONTROL); ++ writel(FSL_ATA_CTRL_ATA_RST_B | FSL_ATA_CTRL_FIFO_RST_B, ATA_BASE_ADDR + FSL_ATA_CONTROL); ++ /* Set initial timing and mode */ ++ set_ata_bus_timing(PIO_XFER_MODE_4); ++ writeb(20, ATA_BASE_ADDR+ FSL_ATA_FIFO_ALARM) ; /* set fifo alarm to 20 halfwords, midway */ ++ ++ if (ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, 6000, 1000) == 0xff) { ++ diag_printf("Failed to initialize the ATA drive\n"); ++ return 0; ++ } ++ return HAL_IDE_NUM_CONTROLLERS; ++} ++ ++static void ata_read_buf(int argc, char *argv[]); ++RedBoot_cmd("ata_read", ++ "Read Ata", ++ "-f -b -l ", ++ ata_read_buf ++ ); ++ ++static void ata_program_buf(int argc, char *argv[]); ++RedBoot_cmd("ata_write", ++ "Write Ata", ++ "-f -b -l ", ++ ata_program_buf ++ ); ++ ++static void ata_read_buf(int argc, char *argv[]) ++{ ++ unsigned int total_sectors, num_of_sectors; ++ unsigned char lba_addr[4]; ++ CYG_ADDRESS addr, data; ++ unsigned long sect_addr; ++ unsigned long len; ++ unsigned char status; ++ bool mem_addr_set = false; ++ bool flash_addr_set = false; ++ bool length_set = false; ++ struct option_info opts[3]; ++ ++ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&data, (bool *)&mem_addr_set, "memory base address"); ++ init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void *)&addr, (bool *)&flash_addr_set, "FLASH memory base address"); ++ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void *)&len, (bool *)&length_set, "image length [in FLASH]"); ++ ++ if (!scan_opts(argc, argv, 1, opts, 3, 0, 0, 0)) { ++ diag_printf("invalid arguments"); ++ return; ++ } ++ ++ if (!mem_addr_set || !flash_addr_set || !length_set) { ++ diag_printf("required parameter missing\n"); ++ return; ++ } ++ ++ if ((addr % ATA_SECTOR_SIZE) != 0) { ++ diag_printf("Need a sector-aligned (512 byte) address in ATA\n\n"); ++ return; ++ } ++ ++ total_sectors = (len / ATA_SECTOR_SIZE); ++ sect_addr = addr / ATA_SECTOR_SIZE; ++ ++ do { ++ lba_addr[0] = sect_addr & 0xFF; ++ lba_addr[1] = (sect_addr >> 8) & 0xFF; ++ lba_addr[2] = (sect_addr >> 16) & 0xFF; ++ /* Enable the LBA bit */ ++ lba_addr[3] = (1 << 6) | ((sect_addr >> 24) & 0xF); ++ ++ if (total_sectors >= MAX_NUMBER_OF_SECTORS) ++ num_of_sectors = 0; ++ else ++ num_of_sectors = total_sectors; ++ ++ ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, 5000, 50); ++ writeb(num_of_sectors, ATA_BASE_ADDR + FSL_ATA_DSCR); ++ writeb(lba_addr[0], ATA_BASE_ADDR + FSL_ATA_DSNR); ++ writeb(lba_addr[1], ATA_BASE_ADDR + FSL_ATA_DCLR); ++ writeb(lba_addr[2], ATA_BASE_ADDR + FSL_ATA_DCHR); ++ writeb(lba_addr[3], ATA_BASE_ADDR + FSL_ATA_DDHR); ++ ++ //Issue Read command ++ ata_sff_exec_command(ATA_CMD_READ); ++ status = ata_sff_busy_wait(ATA_BUSY, 5000, 50); ++ if (status & ATA_ERR) { ++ diag_printf("Error while issuing ATA Read command\n"); ++ return; ++ } ++ if (num_of_sectors == 0) { ++ read_sector_pio((unsigned int *)data, MAX_NUMBER_OF_SECTORS); ++ total_sectors -= MAX_NUMBER_OF_SECTORS; ++ sect_addr += MAX_NUMBER_OF_SECTORS; ++ data += (MAX_NUMBER_OF_SECTORS * ATA_SECTOR_SIZE); ++ } else { ++ read_sector_pio((unsigned int *)data, num_of_sectors); ++ total_sectors -= num_of_sectors; ++ sect_addr += num_of_sectors; ++ data += (num_of_sectors * ATA_SECTOR_SIZE); ++ } ++ } while (total_sectors > 0); ++} ++ ++static void ata_program_buf(int argc, char *argv[]) ++{ ++ int total_sectors, num_of_sectors, lba_addr[4]; ++ CYG_ADDRESS addr, data; ++ unsigned long len; ++ unsigned long sect_addr; ++ unsigned char status; ++ bool mem_addr_set = false; ++ bool flash_addr_set = false; ++ bool length_set = false; ++ struct option_info opts[3]; ++ ++ init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&data, (bool *)&mem_addr_set, "memory base address"); ++ init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM, ++ (void *)&addr, (bool *)&flash_addr_set, "FLASH memory base address"); ++ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void *)&len, (bool *)&length_set, "image length [in FLASH]"); ++ ++ if (!scan_opts(argc, argv, 1, opts, 3, 0, 0, 0)) { ++ diag_printf("invalid arguments"); ++ return; ++ } ++ ++ if (!mem_addr_set || !flash_addr_set || !length_set) { ++ diag_printf("required parameter missing\n"); ++ return; ++ } ++ ++ if ((addr % ATA_SECTOR_SIZE) != 0) { ++ diag_printf("Need a sector-aligned (512 byte) address in ATA\n\n"); ++ return; ++ } ++ ++ total_sectors = (len / ATA_SECTOR_SIZE); ++ sect_addr = addr / ATA_SECTOR_SIZE; ++ ++ do { ++ lba_addr[0] = sect_addr & 0xFF; ++ lba_addr[1] = (sect_addr >> 8) & 0xFF; ++ lba_addr[2] = (sect_addr >> 16) & 0xFF; ++ /* Enable the LBA bit */ ++ lba_addr[3] = (1 << 6) | ((sect_addr >> 24) & 0xF); ++ ++ if (total_sectors >= MAX_NUMBER_OF_SECTORS) ++ num_of_sectors = 0; ++ else ++ num_of_sectors = total_sectors; ++ ++ ata_sff_busy_wait(ATA_BUSY | ATA_DRQ, 5000, 50); ++ writeb(num_of_sectors, ATA_BASE_ADDR + FSL_ATA_DSCR); ++ writeb(lba_addr[0], ATA_BASE_ADDR + FSL_ATA_DSNR); ++ writeb(lba_addr[1], ATA_BASE_ADDR + FSL_ATA_DCLR); ++ writeb(lba_addr[2], ATA_BASE_ADDR + FSL_ATA_DCHR); ++ writeb(lba_addr[3], ATA_BASE_ADDR + FSL_ATA_DDHR); ++ ++ //Issue Write command ++ ata_sff_exec_command(ATA_CMD_WRITE); ++ ata_sff_busy_wait(ATA_BUSY, 5000, 50); ++ if (status & ATA_ERR) { ++ diag_printf("Error while issuing ATA Write command\n"); ++ return; ++ } ++ if (num_of_sectors == 0) { ++ write_sector_pio((unsigned int *)data, MAX_NUMBER_OF_SECTORS); ++ total_sectors -= MAX_NUMBER_OF_SECTORS; ++ sect_addr += MAX_NUMBER_OF_SECTORS; ++ data += (MAX_NUMBER_OF_SECTORS * ATA_SECTOR_SIZE); ++ } else { ++ write_sector_pio((unsigned int *)data, num_of_sectors); ++ total_sectors -= num_of_sectors; ++ sect_addr += num_of_sectors; ++ data += (num_of_sectors * ATA_SECTOR_SIZE); ++ } ++ } while (total_sectors > 0); ++} ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_gpio.c redboot-imx-200952/packages/hal/arm/imx/current/src/imx_gpio.c +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_gpio.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/imx_gpio.c 2010-01-26 17:33:15.452960637 +0000 +@@ -0,0 +1,86 @@ ++//========================================================================== ++// ++// imx_gpio.c ++// ++// iMX GPIO implementation ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++ ++int gpio_dir_config(int port, int pin, int dir) ++{ ++ unsigned int oldVal = 0, newVal = 0; ++ ++ if ((pin > 31) || (pin < 0)) { ++ diag_printf("Wrong GPIO Pin[%d] Input! [1~32] Is Allowed!\n", pin); ++ return -1; ++ } ++ oldVal = readl(port + GPIO_GDIR_OFFSET); ++ if (dir == GPIO_GDIR_INPUT) ++ newVal = oldVal & (~(1 << pin)); ++ else ++ newVal = oldVal | (1 << pin); ++ writel(newVal, port + GPIO_GDIR_OFFSET); ++ return 0; ++} ++ ++int gpio_write_data(int port, int pin, unsigned int attr) ++{ ++ int dir; ++ unsigned int oldVal = 0, newVal = 0; ++ ++ if ((pin > 31) || (pin < 0)) { ++ diag_printf("Wrong GPIO Pin[%d] Input! [1~32] Is Allowed!\n", pin); ++ return -1; ++ } ++ dir = (readl(port + GPIO_GDIR_OFFSET) & (1 << pin)) >> pin; ++ if (dir != 1) { ++ diag_printf("GPIO%d_%d is not configured to be output!\n", port + 1, pin); ++ return -1; ++ } ++ ++ oldVal = readl(port + GPIO_DR_OFFSET); ++ if (attr == 0) ++ newVal = oldVal & (~(1 << pin)); ++ else if (attr == 1) ++ newVal = oldVal | (1 << pin); ++ writel(newVal, port + GPIO_DR_OFFSET); ++ ++ return 0; ++} ++ +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_redboot_commands.c redboot-imx-200952/packages/hal/arm/imx/current/src/imx_redboot_commands.c +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_redboot_commands.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/imx_redboot_commands.c 2010-01-26 17:33:15.452960637 +0000 +@@ -0,0 +1,101 @@ ++//========================================================================== ++// ++// imx_redboot_cmds.c ++// ++// iMX specific RedBoot commands ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++ ++#include ++#include ++#include ++#include ++ ++static void runImg(int argc, char *argv[]); ++ ++RedBoot_cmd("run", ++ "Run an image at a location with MMU off", ++ "[]", ++ runImg ++ ); ++ ++void __attribute__((__noinline__)) launchRunImg(unsigned long addr) ++{ ++ asm volatile ("mov r12, r0;"); ++ ++ HAL_DCACHE_INVALIDATE_ALL(); ++ HAL_DCACHE_DISABLE(); ++ HAL_ICACHE_INVALIDATE_ALL(); ++ HAL_MMU_OFF(); ++ ++ asm volatile ( ++ "mov r0, #0;" ++ "mov r1, r12;" ++ "mov r11, #0;" ++ "mov r12, #0;" ++ "mrs r10, cpsr;" ++ "bic r10, r10, #0xF0000000;" ++ "msr cpsr_f, r10;" ++ "mov pc, r1" ++ ); ++} ++ ++extern unsigned long entry_address; ++ ++static void runImg(int argc,char *argv[]) ++{ ++ unsigned int virt_addr, phys_addr; ++ ++ // Default physical entry point for Symbian ++ if (entry_address == NO_MEMORY) ++ virt_addr = 0x800000; ++ else ++ virt_addr = entry_address; ++ ++ if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr, ++ OPTION_ARG_TYPE_NUM, "virtual address")) ++ return; ++ ++ if (entry_address != NO_MEMORY) ++ diag_printf("load entry_address=0x%lx\n", entry_address); ++ ++ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr); ++ ++ diag_printf("virt_addr=0x%x\n",virt_addr); ++ diag_printf("phys_addr=0x%x\n",phys_addr); ++ ++ launchRunImg(phys_addr); ++} +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_uart.c redboot-imx-200952/packages/hal/arm/imx/current/src/imx_uart.c +--- redboot-imx-200952~/packages/hal/arm/imx/current/src/imx_uart.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/hal/arm/imx/current/src/imx_uart.c 2010-01-26 17:33:15.452960637 +0000 +@@ -0,0 +1,769 @@ ++/*============================================================================= ++// ++// hal_diag.c ++// ++// HAL diagnostic output code ++// ++//============================================================================= ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//===========================================================================*/ ++ ++#include ++#include ++#include CYGBLD_HAL_PLATFORM_H ++ ++#include // base types ++#include // tracing macros ++#include // assertion macros ++ ++#include // basic machine info ++#include // interrupt macros ++#include // IO macros ++#include // Calling interface definitions ++#include ++#include // cyg_drv_interrupt_acknowledge ++#include // Helper functions ++#include // Hardware definitions ++#include ++ ++extern void cyg_hal_plf_duart_init(void); ++/* ++ * UART Control Register 0 Bit Fields. ++ */ ++#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt ++#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate ++#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable ++#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt ++#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable ++#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable ++#define EUartUCR1_IREN (1 << 7) // Infrared interface enable ++#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable ++#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable ++#define EUartUCR1_SNDBRK (1 << 4) // Send break ++#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable ++#define EUartUCR1_DOZE (1 << 1) // Doze ++#define EUartUCR1_UARTEN (1 << 0) // UART enabled ++#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable ++#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin ++#define EUartUCR2_CTSC (1 << 13) // CTS pin control ++#define EUartUCR2_CTS (1 << 12) // Clear to send ++#define EUartUCR2_ESCEN (1 << 11) // Escape enable ++#define EUartUCR2_PREN (1 << 8) // Parity enable ++#define EUartUCR2_PROE (1 << 7) // Parity odd/even ++#define EUartUCR2_STPB (1 << 6) // Stop ++#define EUartUCR2_WS (1 << 5) // Word size ++#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable ++#define EUartUCR2_ATEN (1 << 3) // Aging timer enable ++#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled ++#define EUartUCR2_RXEN (1 << 1) // Receiver enabled ++#define EUartUCR2_SRST_ (1 << 0) // SW reset ++#define EUartUCR3_PARERREN (1 << 12) // Parity enable ++#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable ++#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved ++#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable ++#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable ++#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable ++#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected ++#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission ++#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable ++#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) ++#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception ++#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable ++#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable ++#define EUartUCR4_IRSC (1 << 5) // IR special case ++#define EUartUCR4_LPBYP (1 << 4) // Low power bypass ++#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable ++#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable ++#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable ++#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable ++#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift ++#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1) ++#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2) ++#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) ++#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) ++#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) ++#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) ++#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) ++#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift ++#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag ++#define EUartUSR1_RTSS (1 << 14) // RTS pin status ++#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag ++#define EUartUSR1_RTSD (1 << 12) // RTS delta ++#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag ++#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag ++#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag ++#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status ++#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag ++#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag ++#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag ++#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete ++#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty ++#define EUartUSR2_IDLE (1 << 12) // Idle condition ++#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped ++#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag ++#define EUartUSR2_WAKE (1 << 7) // Wake ++#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag ++#define EUartUSR2_TXDC (1 << 3) // Transmitter complete ++#define EUartUSR2_BRCD (1 << 2) // Break condition ++#define EUartUSR2_ORE (1 << 1) // Overrun error ++#define EUartUSR2_RDR (1 << 0) // Recv data ready ++#define EUartUTS_FRCPERR (1 << 13) // Force parity error ++#define EUartUTS_LOOP (1 << 12) // Loop tx and rx ++#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty ++#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty ++#define EUartUTS_TXFULL (1 << 4) // TxFIFO full ++#define EUartUTS_RXFULL (1 << 3) // RxFIFO full ++#define EUartUTS_SOFTRST (1 << 0) // Software reset ++ ++#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2 ++//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4 ++//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_7 ++ ++#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2) ++#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2) ++#endif ++ ++#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4) ++#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4) ++#endif ++ ++#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_7) ++#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 7) ++#endif ++ ++void ++cyg_hal_plf_comms_init(void) ++{ ++ static int initialized = 0; ++ ++ if (initialized) ++ return; ++ ++ initialized = 1; ++#ifdef CYGHWR_HAL_ARM_DUART_UARTA ++ cyg_hal_plf_duart_init(); ++#endif ++ cyg_hal_plf_serial_init(); ++} ++ ++//============================================================================= ++// MXC Serial Port (UARTx) for Debug ++//============================================================================= ++#ifdef UART_WIDTH_32 ++struct mxc_serial { ++ volatile cyg_uint32 urxd[16]; ++ volatile cyg_uint32 utxd[16]; ++ volatile cyg_uint32 ucr1; ++ volatile cyg_uint32 ucr2; ++ volatile cyg_uint32 ucr3; ++ volatile cyg_uint32 ucr4; ++ volatile cyg_uint32 ufcr; ++ volatile cyg_uint32 usr1; ++ volatile cyg_uint32 usr2; ++ volatile cyg_uint32 uesc; ++ volatile cyg_uint32 utim; ++ volatile cyg_uint32 ubir; ++ volatile cyg_uint32 ubmr; ++ volatile cyg_uint32 ubrc; ++ volatile cyg_uint32 onems; ++ volatile cyg_uint32 uts; ++}; ++#else ++struct mxc_serial { ++ volatile cyg_uint16 urxd[1]; ++ volatile cyg_uint16 resv0[31]; ++ ++ volatile cyg_uint16 utxd[1]; ++ volatile cyg_uint16 resv1[31]; ++ volatile cyg_uint16 ucr1; ++ volatile cyg_uint16 resv2; ++ volatile cyg_uint16 ucr2; ++ volatile cyg_uint16 resv3; ++ volatile cyg_uint16 ucr3; ++ volatile cyg_uint16 resv4; ++ volatile cyg_uint16 ucr4; ++ volatile cyg_uint16 resv5; ++ volatile cyg_uint16 ufcr; ++ volatile cyg_uint16 resv6; ++ volatile cyg_uint16 usr1; ++ volatile cyg_uint16 resv7; ++ volatile cyg_uint16 usr2; ++ volatile cyg_uint16 resv8; ++ volatile cyg_uint16 uesc; ++ volatile cyg_uint16 resv9; ++ volatile cyg_uint16 utim; ++ volatile cyg_uint16 resv10; ++ volatile cyg_uint16 ubir; ++ volatile cyg_uint16 resv11; ++ volatile cyg_uint16 ubmr; ++ volatile cyg_uint16 resv12; ++ volatile cyg_uint16 ubrc; ++ volatile cyg_uint16 resv13; ++ volatile cyg_uint16 onems; ++ volatile cyg_uint16 resv14; ++ volatile cyg_uint16 uts; ++ volatile cyg_uint16 resv15; ++}; ++#endif ++ ++typedef struct { ++ volatile struct mxc_serial* base; ++ cyg_int32 msec_timeout; ++ int isr_vector; ++ int baud_rate; ++} channel_data_t; ++ ++static channel_data_t channels[] = { ++#if CYGHWR_IMX_UART1 != 0 ++ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, ++#endif ++#if CYGHWR_IMX_UART2 != 0 ++ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, ++#endif ++#if CYGHWR_IMX_UART3 != 0 ++ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, ++#endif ++#if CYGHWR_IMX_UART4 != 0 ++ {(volatile struct mxc_serial*)UART4_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART4, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, ++#endif ++#if CYGHWR_IMX_UART5 != 0 ++ {(volatile struct mxc_serial*)UART5_BASE_ADDR, 1000, ++ CYGNUM_HAL_INTERRUPT_UART5, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, ++#endif ++}; ++ ++/*---------------------------------------------------------------------------*/ ++ ++static void init_serial_channel(channel_data_t* __ch_data) ++{ ++ volatile struct mxc_serial* base = __ch_data->base; ++ ++ /* Wait for UART to finish transmitting */ ++ while (!(base->uts & EUartUTS_TXEMPTY)); ++ ++ /* Disable UART */ ++ base->ucr1 &= ~EUartUCR1_UARTEN; ++ ++ /* Set to default POR state */ ++ base->ucr1 = 0x00000000; ++ base->ucr2 = 0x00000000; ++ ++ while (!(base->ucr2 & EUartUCR2_SRST_)); ++ ++ base->ucr3 = 0x00000704; ++ base->ucr4 = 0x00008000; ++ base->ufcr = 0x00000801; ++ base->uesc = 0x0000002B; ++ base->utim = 0x00000000; ++ base->ubir = 0x00000000; ++ base->ubmr = 0x00000000; ++ base->onems = 0x00000000; ++ base->uts = 0x00000000; ++ ++ /* Configure FIFOs */ ++ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV ++ | (2 << EUartUFCR_TXTL_SHF); ++ ++ /* Setup One MS timer */ ++ base->onems = (MXC_UART_REFFREQ / 1000); ++ ++ /* Set to 8N1 */ ++ base->ucr2 &= ~EUartUCR2_PREN; ++ base->ucr2 |= EUartUCR2_WS; ++ base->ucr2 &= ~EUartUCR2_STPB; ++ ++ /* Ignore RTS */ ++ base->ucr2 |= EUartUCR2_IRTS; ++ ++ /* Enable UART */ ++ base->ucr1 |= EUartUCR1_UARTEN; ++ ++ /* Enable FIFOs */ ++ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN; ++ ++ /* Clear status flags */ ++ base->usr2 |= EUartUSR2_ADET | ++ EUartUSR2_IDLE | ++ EUartUSR2_IRINT | ++ EUartUSR2_WAKE | ++ EUartUSR2_RTSF | ++ EUartUSR2_BRCD | ++ EUartUSR2_ORE | ++ EUartUSR2_RDR; ++ ++ /* Clear status flags */ ++ base->usr1 |= EUartUSR1_PARITYERR | ++ EUartUSR1_RTSD | ++ EUartUSR1_ESCF | ++ EUartUSR1_FRAMERR | ++ EUartUSR1_AIRINT | ++ EUartUSR1_AWAKE; ++ ++ /* Set the numerator value minus one of the BRM ratio */ ++ base->ubir = (__ch_data->baud_rate / 100) - 1; ++ ++ /* Set the denominator value minus one of the BRM ratio */ ++ base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1); ++ ++} ++ ++static void stop_serial_channel(channel_data_t* __ch_data) ++{ ++ volatile struct mxc_serial* base = __ch_data->base; ++ ++ /* Wait for UART to finish transmitting */ ++ while (!(base->uts & EUartUTS_TXEMPTY)); ++ ++ /* Disable UART */ ++ base->ucr1 &= ~EUartUCR1_UARTEN; ++} ++ ++#define DIAG_BUFSIZE 2048 ++static char __log_buf[DIAG_BUFSIZE]; ++static int diag_bp = 0; ++ ++// This flag is needed to show the missing uart output due to display coming up late ++static int display_makeup = 1; ++ ++int display_ready = 0; ++ ++display_putc_func_t *display_putc = NULL; ++ ++void cyg_hal_plf_serial_putc(void *__ch_data, char c) ++{ ++ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base; ++ int i; ++ ++ if (diag_bp == DIAG_BUFSIZE) { ++ diag_bp = 0; // avoid overflow ++ } ++ __log_buf[diag_bp++] = c; ++ ++ CYGARC_HAL_SAVE_GP(); ++ ++ // Wait for Tx FIFO not full ++ while (base->uts & EUartUTS_TXFULL) ++ ; ++ base->utxd[0] = c; ++ if (display_ready && display_putc) { ++ if (display_makeup) { ++ display_makeup = 0; ++ for (i = 0; i < diag_bp; i++) { ++ display_putc(__log_buf[i]); ++ } ++ } ++ display_putc(c); ++ } ++ CYGARC_HAL_RESTORE_GP(); ++} ++ ++static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, ++ cyg_uint8* ch) ++{ ++ volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base; ++ ++ // If receive fifo is empty, return false ++ if (base->uts & EUartUTS_RXEMPTY) ++ return false; ++ ++ *ch = (char)base->urxd[0]; ++ ++ return true; ++} ++ ++cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) ++{ ++ cyg_uint8 ch; ++ CYGARC_HAL_SAVE_GP(); ++ ++ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); ++ ++ CYGARC_HAL_RESTORE_GP(); ++ return ch; ++} ++ ++static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, ++ cyg_uint32 __len) ++{ ++ CYGARC_HAL_SAVE_GP(); ++ ++ while(__len-- > 0) ++ cyg_hal_plf_serial_putc(__ch_data, *__buf++); ++ ++ CYGARC_HAL_RESTORE_GP(); ++} ++ ++static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, ++ cyg_uint32 __len) ++{ ++ CYGARC_HAL_SAVE_GP(); ++ ++ while (__len-- > 0) ++ *__buf++ = cyg_hal_plf_serial_getc(__ch_data); ++ ++ CYGARC_HAL_RESTORE_GP(); ++} ++ ++cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data, ++ cyg_uint8* ch) ++{ ++ int delay_count; ++ channel_data_t* chan = (channel_data_t*)__ch_data; ++ cyg_bool res; ++ CYGARC_HAL_SAVE_GP(); ++ ++ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps ++ ++ for(;;) { ++ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); ++ if (res || 0 == delay_count--) ++ break; ++ ++ CYGACC_CALL_IF_DELAY_US(100); ++ } ++ ++ CYGARC_HAL_RESTORE_GP(); ++ return res; ++} ++ ++static int cyg_hal_plf_serial_control(void *__ch_data, ++ __comm_control_cmd_t __func, ...) ++{ ++ static int irq_state = 0; ++ channel_data_t* chan = (channel_data_t*)__ch_data; ++ int ret = -1; ++ va_list ap; ++ ++ CYGARC_HAL_SAVE_GP(); ++ va_start(ap, __func); ++ ++ switch (__func) { ++ case __COMMCTL_GETBAUD: ++ ret = chan->baud_rate; ++ break; ++ case __COMMCTL_SETBAUD: ++ chan->baud_rate = va_arg(ap, cyg_int32); ++ // Should we verify this value here? ++ init_serial_channel(chan); ++ ret = 0; ++ break; ++ case __COMMCTL_IRQ_ENABLE: ++ irq_state = 1; ++ ++ chan->base->ucr1 |= EUartUCR1_RRDYEN; ++ ++ HAL_INTERRUPT_UNMASK(chan->isr_vector); ++ break; ++ case __COMMCTL_IRQ_DISABLE: ++ ret = irq_state; ++ irq_state = 0; ++ ++ chan->base->ucr1 &= ~EUartUCR1_RRDYEN; ++ ++ HAL_INTERRUPT_MASK(chan->isr_vector); ++ break; ++ case __COMMCTL_DBG_ISR_VECTOR: ++ ret = chan->isr_vector; ++ break; ++ case __COMMCTL_SET_TIMEOUT: ++ ret = chan->msec_timeout; ++ chan->msec_timeout = va_arg(ap, cyg_uint32); ++ break; ++ default: ++ break; ++ } ++ va_end(ap); ++ CYGARC_HAL_RESTORE_GP(); ++ return ret; ++} ++ ++static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, ++ CYG_ADDRWORD __vector, CYG_ADDRWORD __data) ++{ ++ int res = 0; ++ channel_data_t* chan = (channel_data_t*)__ch_data; ++ char c; ++ ++ CYGARC_HAL_SAVE_GP(); ++ ++ cyg_drv_interrupt_acknowledge(chan->isr_vector); ++ ++ *__ctrlc = 0; ++ if (!(chan->base->uts & EUartUTS_RXEMPTY)) { ++ c = (char)chan->base->urxd[0]; ++ ++ if (cyg_hal_is_break( &c , 1 )) ++ *__ctrlc = 1; ++ ++ res = CYG_ISR_HANDLED; ++ } ++ ++ CYGARC_HAL_RESTORE_GP(); ++ return res; ++} ++ ++void cyg_hal_plf_serial_init(void) ++{ ++ hal_virtual_comm_table_t* comm; ++ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); ++ int i; ++ static int jjj = 0; ++ ++ // Init channels ++#define NUMOF(x) (sizeof(x)/sizeof(x[0])) ++ for (i = 0; i < NUMOF(channels); i++) { ++ init_serial_channel(&channels[i]); ++ CYGACC_CALL_IF_SET_CONSOLE_COMM(i); ++ comm = CYGACC_CALL_IF_CONSOLE_PROCS(); ++ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]); ++ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); ++ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); ++ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); ++ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); ++ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); ++ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); ++ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); ++ if (jjj == 0) { ++ cyg_hal_plf_serial_putc(&channels[i], '+'); ++ jjj++; ++ } ++ cyg_hal_plf_serial_putc(&channels[i], '+'); ++ } ++ ++ // Restore original console ++ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); ++} ++ ++void cyg_hal_plf_serial_stop(void) ++{ ++ int i; ++ ++ // Init channels ++#define NUMOF(x) (sizeof(x)/sizeof(x[0])) ++ for (i = 0; i < NUMOF(channels); i++) { ++ stop_serial_channel(&channels[i]); ++ } ++} ++ ++//============================================================================= ++// Compatibility with older stubs ++//============================================================================= ++ ++#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG ++ ++#include // cyg_hal_gdb_interrupt ++ ++#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0) ++#define __BASE ((void*)UART1_BASE_ADDR) ++#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1 ++#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1) ++#define __BASE ((void*)UART2_BASE_ADDR) ++#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2 ++#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4) ++#define __BASE ((void*)UART3_BASE_ADDR) ++#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3 ++#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5) ++#define __BASE ((void*)UART4_BASE_ADDR) ++#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4 ++#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6) ++#define __BASE ((void*)UART5_BASE_ADDR) ++#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5 ++#endif ++ ++#ifdef __BASE ++ ++#ifdef CYGSEM_HAL_ROM_MONITOR ++#define CYG_HAL_STARTUP_ROM ++#define CYG_HAL_STARTUP_ROMRAM ++#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++#endif ++ ++#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) ++#define HAL_DIAG_USES_HARDWARE ++#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN) ++#define HAL_DIAG_USES_HARDWARE ++#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL ++#define HAL_DIAG_USES_HARDWARE ++#endif ++ ++static channel_data_t channel = { ++ (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR ++}; ++ ++#ifdef HAL_DIAG_USES_HARDWARE ++ ++void hal_diag_init(void) ++{ ++ static int init = 0; ++ char *msg = "\n\rARM eCos\n\r"; ++ cyg_uint8 lcr; ++ ++ if (init++) return; ++ ++ init_serial_channel(&channel); ++ ++ while (*msg) hal_diag_write_char(*msg++); ++} ++ ++#ifdef DEBUG_DIAG ++#ifndef CYG_HAL_STARTUP_ROM ++#define DIAG_BUFSIZE 2048 ++static char diag_buffer[DIAG_BUFSIZE]; ++static int diag_bp = 0; ++#endif ++#endif ++ ++void hal_diag_write_char(char c) ++{ ++#ifdef DEBUG_DIAG ++#ifndef CYG_HAL_STARTUP_ROM ++ diag_buffer[diag_bp++] = c; ++ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0; ++#endif ++#endif ++ cyg_hal_plf_serial_putc(&channel, c); ++} ++ ++void hal_diag_read_char(char *c) ++{ ++ *c = cyg_hal_plf_serial_getc(&channel); ++} ++ ++#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol ++ ++void hal_diag_read_char(char *c) ++{ ++ *c = cyg_hal_plf_serial_getc(&channel); ++} ++ ++void hal_diag_write_char(char c) ++{ ++ static char line[100]; ++ static int pos = 0; ++ ++ // FIXME: Some LED blinking might be nice right here. ++ ++ // No need to send CRs ++ if( c == '\r' ) return; ++ ++ line[pos++] = c; ++ ++ if (c == '\n' || pos == sizeof(line)) { ++ CYG_INTERRUPT_STATE old; ++ ++ // Disable interrupts. This prevents GDB trying to interrupt us ++ // while we are in the middle of sending a packet. The serial ++ // receive interrupt will be seen when we re-enable interrupts ++ // later. ++ ++#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); ++#else ++ HAL_DISABLE_INTERRUPTS(old); ++#endif ++ ++ while (1) { ++ static char hex[] = "0123456789ABCDEF"; ++ cyg_uint8 csum = 0; ++ int i; ++#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++ char c1; ++#endif ++ cyg_hal_plf_serial_putc(&channel, '$'); ++ cyg_hal_plf_serial_putc(&channel, 'O'); ++ csum += 'O'; ++ for(i = 0; i < pos; i++) { ++ char ch = line[i]; ++ char h = hex[(ch>>4)&0xF]; ++ char l = hex[ch&0xF]; ++ cyg_hal_plf_serial_putc(&channel, h); ++ cyg_hal_plf_serial_putc(&channel, l); ++ csum += h; ++ csum += l; ++ } ++ cyg_hal_plf_serial_putc(&channel, '#'); ++ cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]); ++ cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]); ++ ++#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++ ++ break; // regardless ++ ++#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually... ++ ++ // Wait for the ACK character '+' from GDB here and handle ++ // receiving a ^C instead. This is the reason for this clause ++ // being a loop. ++ c1 = cyg_hal_plf_serial_getc(&channel); ++ ++ if( c1 == '+' ) ++ break; // a good acknowledge ++ ++#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT ++ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR); ++ if( c1 == 3 ) { ++ // Ctrl-C: breakpoint. ++ cyg_hal_gdb_interrupt( ++ (target_register_t)__builtin_return_address(0) ); ++ break; ++ } ++#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT ++ ++#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++ // otherwise, loop round again ++ } ++ ++ pos = 0; ++ ++ // And re-enable interrupts ++#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); ++#else ++ HAL_RESTORE_INTERRUPTS(old); ++#endif ++ ++ } ++} ++#endif ++ ++#endif // __BASE ++ ++#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG ++ ++/*---------------------------------------------------------------------------*/ ++/* End of hal_diag.c */ +diff -urNad redboot-imx-200952~/packages/io/flash/current/src/flash.c redboot-imx-200952/packages/io/flash/current/src/flash.c +--- redboot-imx-200952~/packages/io/flash/current/src/flash.c 2006-02-25 14:07:43.000000000 +0000 ++++ redboot-imx-200952/packages/io/flash/current/src/flash.c 2010-01-26 17:33:17.232960255 +0000 +@@ -191,7 +191,13 @@ + (*flash_info.pf)("... Erase from %p-%p: ", (void*)block, (void*)end_addr); + #endif + ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn off caches */ ++ if (flash_info.start !=0) ++ HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#else + HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#endif + FLASH_Enable(block, end_addr); + while (block < end_addr) { + // Supply the blocksize for a gross check for erase success +@@ -213,7 +219,20 @@ + #endif + + if (!erased) { ++ ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to pass in block by block */ ++ if (flash_info.start !=0) { ++ stat = (*_flash_erase_block)(block, flash_info.block_size); ++ } else { ++ stat = (*_flash_erase_block)(block, len); ++ if (stat) ++ *err_addr = (void *)block; ++ break; ++ } ++#else + stat = (*_flash_erase_block)(block, flash_info.block_size); ++#endif + stat = flash_hwr_map_error(stat); + } + if (stat) { +@@ -235,7 +254,13 @@ + #endif + } + FLASH_Disable(block, end_addr); ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn on caches */ ++ if (flash_info.start !=0) ++ HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#else + HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#endif + #ifdef CYGSEM_IO_FLASH_CHATTER + (*flash_info.pf)("\n"); + #endif +@@ -270,10 +295,20 @@ + (void*)(((CYG_ADDRESS)data)+len), (void*)addr); + #endif + ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn off caches */ ++ if (flash_info.start !=0) ++ HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#else + HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#endif + FLASH_Enable((unsigned short*)addr, (unsigned short *)(addr+len)); + while (len > 0) { + size = len; ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to pass in block by block */ ++ if (flash_info.start !=0) ++#endif + if (size > flash_info.block_size) size = flash_info.block_size; + + tmp = (CYG_ADDRESS)addr & ~flash_info.block_mask; +@@ -307,7 +342,14 @@ + data += size/sizeof(*data); + } + FLASH_Disable((unsigned short*)addr, (unsigned short *)(addr+len)); ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn on caches */ ++ if (flash_info.start !=0) ++ HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#else + HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#endif ++ + #ifdef CYGSEM_IO_FLASH_CHATTER + (*flash_info.pf)("\n"); + #endif +@@ -338,10 +380,20 @@ + (void*)(((CYG_ADDRESS)data)+len), (void*)addr); + #endif + ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn off caches */ ++ if (flash_info.start !=0) ++ HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#else + HAL_FLASH_CACHES_OFF(d_cache, i_cache); ++#endif + FLASH_Enable((unsigned short*)addr, (unsigned short *)(addr+len)); + while (len > 0) { + size = len; ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to pass in block by block */ ++ if (flash_info.start !=0) ++#endif + if (size > flash_info.block_size) size = flash_info.block_size; + + tmp = (CYG_ADDRESS)addr & ~flash_info.block_mask; +@@ -375,7 +427,13 @@ + data += size/sizeof(*data); + } + FLASH_Disable((unsigned short*)addr, (unsigned short *)(addr+len)); ++#if defined(MXCFLASH_SELECT_NAND) || defined(MXCFLASH_SELECT_MMC) ++ /* For NOR we want to turn on caches */ ++ if (flash_info.start !=0) + HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#else ++ HAL_FLASH_CACHES_ON(d_cache, i_cache); ++#endif + #ifdef CYGSEM_IO_FLASH_CHATTER + (*flash_info.pf)("\n"); + #endif +diff -urNad redboot-imx-200952~/packages/net/.cvsignore redboot-imx-200952/packages/net/.cvsignore +--- redboot-imx-200952~/packages/net/.cvsignore 2003-11-22 13:05:01.000000000 +0000 ++++ redboot-imx-200952/packages/net/.cvsignore 1970-01-01 00:00:00.000000000 +0000 +@@ -1 +0,0 @@ +-openssl +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/net/athttpd/current/include/jim.h redboot-imx-200952/packages/net/athttpd/current/include/jim.h +--- redboot-imx-200952~/packages/net/athttpd/current/include/jim.h 2006-11-27 15:41:56.000000000 +0000 ++++ redboot-imx-200952/packages/net/athttpd/current/include/jim.h 2010-01-26 17:33:17.592956252 +0000 +@@ -2,7 +2,7 @@ + * Copyright 2005 Salvatore Sanfilippo + * Copyright 2005 Clemens Hintze + * +- * $Id: jim.h,v 1.76 2006/11/06 20:29:15 antirez Exp $ ++ * $Id: jim.h,v 1.1.1.1 2008/07/31 20:44:21 mmahesh Exp $ + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. +diff -urNad redboot-imx-200952~/packages/net/athttpd/current/src/jim-aio.c redboot-imx-200952/packages/net/athttpd/current/src/jim-aio.c +--- redboot-imx-200952~/packages/net/athttpd/current/src/jim-aio.c 2008-06-18 18:23:25.000000000 +0000 ++++ redboot-imx-200952/packages/net/athttpd/current/src/jim-aio.c 2010-01-26 17:33:17.602964750 +0000 +@@ -1,7 +1,7 @@ + /* Jim - ANSI I/O extension + * Copyright 2005 Salvatore Sanfilippo + * +- * $Id: jim-aio.c,v 1.10 2006/11/06 16:54:48 antirez Exp $ ++ * $Id: jim-aio.c,v 1.1.1.1 2008/07/31 20:44:21 mmahesh Exp $ + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. +diff -urNad redboot-imx-200952~/packages/net/athttpd/current/src/jim.c redboot-imx-200952/packages/net/athttpd/current/src/jim.c +--- redboot-imx-200952~/packages/net/athttpd/current/src/jim.c 2006-11-27 15:41:56.000000000 +0000 ++++ redboot-imx-200952/packages/net/athttpd/current/src/jim.c 2010-01-26 17:33:17.622966124 +0000 +@@ -2,7 +2,7 @@ + * Copyright 2005 Salvatore Sanfilippo + * Copyright 2005 Clemens Hintze + * +- * $Id: jim.c,v 1.170 2006/11/06 21:48:57 antirez Exp $ ++ * $Id: jim.c,v 1.1.1.1 2008/07/31 20:44:21 mmahesh Exp $ + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. +@@ -11750,7 +11750,7 @@ + "Copyright (c) 2005 Salvatore Sanfilippo" JIM_NL, + JIM_VERSION / 100, JIM_VERSION % 100); + fprintf(interp->stdout, +- "CVS ID: $Id: jim.c,v 1.170 2006/11/06 21:48:57 antirez Exp $" ++ "CVS ID: $Id: jim.c,v 1.1.1.1 2008/07/31 20:44:21 mmahesh Exp $" + JIM_NL); + Jim_SetVariableStrWithStr(interp, "jim_interactive", "1"); + while (1) { +diff -urNad redboot-imx-200952~/packages/net/bsd_tcpip/current/include/sys/time.h redboot-imx-200952/packages/net/bsd_tcpip/current/include/sys/time.h +--- redboot-imx-200952~/packages/net/bsd_tcpip/current/include/sys/time.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/net/bsd_tcpip/current/include/sys/time.h 2010-01-26 17:33:17.662958125 +0000 +@@ -0,0 +1,263 @@ ++//========================================================================== ++// ++// include/sys/time.h ++// ++//========================================================================== ++//####BSDCOPYRIGHTBEGIN#### ++// ++// ------------------------------------------- ++// ++// Portions of this software may have been derived from OpenBSD, ++// FreeBSD or other sources, and are covered by the appropriate ++// copyright disclaimers included herein. ++// ++// Portions created by Red Hat are ++// Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. ++// ++// ------------------------------------------- ++// ++//####BSDCOPYRIGHTEND#### ++//========================================================================== ++ ++//========================================================================== ++// ++// include/sys/time.h ++// ++// ++// ++//========================================================================== ++//####BSDCOPYRIGHTBEGIN#### ++// ++// ------------------------------------------- ++// ++// Portions of this software may have been derived from OpenBSD or other sources, ++// and are covered by the appropriate copyright disclaimers included herein. ++// ++// ------------------------------------------- ++// ++//####BSDCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): gthomas ++// Contributors: gthomas ++// Date: 2000-01-10 ++// Purpose: ++// Description: ++// ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++ ++/* $OpenBSD: time.h,v 1.9 1999/12/06 19:36:42 aaron Exp $ */ ++/* $NetBSD: time.h,v 1.18 1996/04/23 10:29:33 mycroft Exp $ */ ++ ++/* ++ * Copyright (c) 1982, 1986, 1993 ++ * The Regents of the University of California. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by the University of ++ * California, Berkeley and its contributors. ++ * 4. Neither the name of the University nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * @(#)time.h 8.2 (Berkeley) 7/10/94 ++ */ ++ ++#ifndef _SYS_TIME_H_ ++#define _SYS_TIME_H_ ++ ++#include ++#include ++ ++#if 0 //ndef __time_t_defined ++typedef int time_t; ++# define __time_t_defined ++#endif ++ ++#if 0 ++ ++/* ++ * Structure returned by gettimeofday(2) system call, ++ * and used in other calls. ++ */ ++struct timeval { ++ long tv_sec; /* seconds */ ++ long tv_usec; /* and microseconds */ ++}; ++ ++#endif ++ ++#if 0 ++/* ++ * Structure defined by POSIX.1b to be like a timeval. ++ */ ++struct timespec { ++ time_t tv_sec; /* seconds */ ++ long tv_nsec; /* and nanoseconds */ ++}; ++#endif ++ ++#define TIMEVAL_TO_TIMESPEC(tv, ts) { \ ++ (ts)->tv_sec = (tv)->tv_sec; \ ++ (ts)->tv_nsec = (tv)->tv_usec * 1000; \ ++} ++#define TIMESPEC_TO_TIMEVAL(tv, ts) { \ ++ (tv)->tv_sec = (ts)->tv_sec; \ ++ (tv)->tv_usec = (ts)->tv_nsec / 1000; \ ++} ++ ++struct timezone { ++ int tz_minuteswest; /* minutes west of Greenwich */ ++ int tz_dsttime; /* type of dst correction */ ++}; ++#define DST_NONE 0 /* not on dst */ ++#define DST_USA 1 /* USA style dst */ ++#define DST_AUST 2 /* Australian style dst */ ++#define DST_WET 3 /* Western European dst */ ++#define DST_MET 4 /* Middle European dst */ ++#define DST_EET 5 /* Eastern European dst */ ++#define DST_CAN 6 /* Canada */ ++ ++/* Operations on timevals. */ ++#define timerclear(tvp) (tvp)->tv_sec = (tvp)->tv_usec = 0 ++#define timerisset(tvp) ((tvp)->tv_sec || (tvp)->tv_usec) ++#define timercmp(tvp, uvp, cmp) \ ++ (((tvp)->tv_sec == (uvp)->tv_sec) ? \ ++ ((tvp)->tv_usec cmp (uvp)->tv_usec) : \ ++ ((tvp)->tv_sec cmp (uvp)->tv_sec)) ++#define timeradd(tvp, uvp, vvp) \ ++ do { \ ++ (vvp)->tv_sec = (tvp)->tv_sec + (uvp)->tv_sec; \ ++ (vvp)->tv_usec = (tvp)->tv_usec + (uvp)->tv_usec; \ ++ if ((vvp)->tv_usec >= 1000000) { \ ++ (vvp)->tv_sec++; \ ++ (vvp)->tv_usec -= 1000000; \ ++ } \ ++ } while (0) ++#define timersub(tvp, uvp, vvp) \ ++ do { \ ++ (vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec; \ ++ (vvp)->tv_usec = (tvp)->tv_usec - (uvp)->tv_usec; \ ++ if ((vvp)->tv_usec < 0) { \ ++ (vvp)->tv_sec--; \ ++ (vvp)->tv_usec += 1000000; \ ++ } \ ++ } while (0) ++ ++/* Operations on timespecs. */ ++#define timespecclear(tsp) (tsp)->tv_sec = (tsp)->tv_nsec = 0 ++#define timespecisset(tsp) ((tsp)->tv_sec || (tsp)->tv_nsec) ++#define timespeccmp(tsp, usp, cmp) \ ++ (((tsp)->tv_sec == (usp)->tv_sec) ? \ ++ ((tsp)->tv_nsec cmp (usp)->tv_nsec) : \ ++ ((tsp)->tv_sec cmp (usp)->tv_sec)) ++#define timespecadd(tsp, usp, vsp) \ ++ do { \ ++ (vsp)->tv_sec = (tsp)->tv_sec + (usp)->tv_sec; \ ++ (vsp)->tv_nsec = (tsp)->tv_nsec + (usp)->tv_nsec; \ ++ if ((vsp)->tv_nsec >= 1000000000L) { \ ++ (vsp)->tv_sec++; \ ++ (vsp)->tv_nsec -= 1000000000L; \ ++ } \ ++ } while (0) ++#define timespecsub(tsp, usp, vsp) \ ++ do { \ ++ (vsp)->tv_sec = (tsp)->tv_sec - (usp)->tv_sec; \ ++ (vsp)->tv_nsec = (tsp)->tv_nsec - (usp)->tv_nsec; \ ++ if ((vsp)->tv_nsec < 0) { \ ++ (vsp)->tv_sec--; \ ++ (vsp)->tv_nsec += 1000000000L; \ ++ } \ ++ } while (0) ++ ++/* ++ * Names of the interval timers, and structure ++ * defining a timer setting. ++ */ ++#define ITIMER_REAL 0 ++#define ITIMER_VIRTUAL 1 ++#define ITIMER_PROF 2 ++ ++struct itimerval { ++ struct timeval it_interval; /* timer interval */ ++ struct timeval it_value; /* current value */ ++}; ++ ++/* ++ * Getkerninfo clock information structure ++ */ ++struct clockinfo { ++ int hz; /* clock frequency */ ++ int tick; /* micro-seconds per hz tick */ ++ int tickadj; /* clock skew rate for adjtime() */ ++ int stathz; /* statistics clock frequency */ ++ int profhz; /* profiling clock frequency */ ++}; ++ ++#define CLOCK_REALTIME 0 ++#define CLOCK_VIRTUAL 1 ++#define CLOCK_PROF 2 ++ ++#define TIMER_RELTIME 0x0 /* relative timer */ ++#ifndef TIMER_ABSTIME ++#define TIMER_ABSTIME 0x1 /* absolute timer */ ++#endif ++ ++#if defined(_KERNEL) || defined(_STANDALONE) ++int itimerfix __P((struct timeval *tv)); ++int itimerdecr __P((struct itimerval *itp, int usec)); ++void microtime __P((struct timeval *tv)); ++void settime __P((struct timeval *tv)); ++#else /* !_KERNEL */ ++ ++#ifndef __ECOS ++#include ++#endif ++ ++#if 0 //ndef _POSIX_SOURCE ++#include ++ ++__BEGIN_DECLS ++int adjtime __P((const struct timeval *, struct timeval *)); ++int clock_getres __P((clockid_t, struct timespec *)); ++int clock_gettime __P((clockid_t, struct timespec *)); ++int clock_settime __P((clockid_t, const struct timespec *)); ++int futimes __P((int, const struct timeval *)); ++int getitimer __P((int, struct itimerval *)); ++int gettimeofday __P((struct timeval *, struct timezone *)); ++int nanosleep __P((const struct timespec *, struct timespec *)); ++int setitimer __P((int, const struct itimerval *, struct itimerval *)); ++int settimeofday __P((const struct timeval *, const struct timezone *)); ++int utimes __P((const char *, const struct timeval *)); ++__END_DECLS ++#endif /* !POSIX */ ++ ++#endif /* !_KERNEL */ ++ ++#endif /* !_SYS_TIME_H_ */ +diff -urNad redboot-imx-200952~/packages/net/common/current/doc/manpages/sys/socketpair.2 redboot-imx-200952/packages/net/common/current/doc/manpages/sys/socketpair.2 +--- redboot-imx-200952~/packages/net/common/current/doc/manpages/sys/socketpair.2 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/net/common/current/doc/manpages/sys/socketpair.2 2010-01-26 17:33:17.692955502 +0000 +@@ -0,0 +1,109 @@ ++.\" $OpenBSD: socketpair.2,v 1.10 1999/07/06 18:21:04 deraadt Exp $ ++.\" $NetBSD: socketpair.2,v 1.5 1995/02/27 12:38:00 cgd Exp $ ++.\" ++.\" Copyright (c) 1983, 1991, 1993 ++.\" The Regents of the University of California. All rights reserved. ++.\" ++.\" Redistribution and use in source and binary forms, with or without ++.\" modification, are permitted provided that the following conditions ++.\" are met: ++.\" 1. Redistributions of source code must retain the above copyright ++.\" notice, this list of conditions and the following disclaimer. ++.\" 2. Redistributions in binary form must reproduce the above copyright ++.\" notice, this list of conditions and the following disclaimer in the ++.\" documentation and/or other materials provided with the distribution. ++.\" 3. All advertising materials mentioning features or use of this software ++.\" must display the following acknowledgement: ++.\" This product includes software developed by the University of ++.\" California, Berkeley and its contributors. ++.\" 4. Neither the name of the University nor the names of its contributors ++.\" may be used to endorse or promote products derived from this software ++.\" without specific prior written permission. ++.\" ++.\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++.\" SUCH DAMAGE. ++.\" ++.\" @(#)socketpair.2 8.1 (Berkeley) 6/4/93 ++.\" ++.Dd June 4, 1993 ++.Dt SOCKETPAIR 2 ++.Os ++.Sh NAME ++.Nm socketpair ++.Nd create a pair of connected sockets ++.Sh SYNOPSIS ++.Fd #include ++.Fd #include ++.Ft int ++.Fn socketpair "int d" "int type" "int protocol" "int *sv" ++.Sh DESCRIPTION ++The ++.Fn socketpair ++call creates an unnamed pair of connected sockets in ++the specified domain ++.Fa d , ++of the specified ++.Fa type , ++and using the optionally specified ++.Fa protocol . ++The descriptors used in referencing the new sockets ++are returned in ++.Fa sv Ns [0] ++and ++.Fa sv Ns [1] . ++The two sockets are indistinguishable. ++.Sh RETURN VALUES ++A 0 is returned if the call succeeds, \-1 if it fails. ++.Sh ERRORS ++The call succeeds unless: ++.Bl -tag -width Er ++.It Bq Er EMFILE ++Too many descriptors are in use by this process. ++.It Bq Er EAFNOSUPPORT ++The specified address family is not supported on this machine. ++.It Bq Er EPROTONOSUPPORT ++The specified protocol is not supported on this machine. ++.It Bq Er EOPNOTSUPP ++The specified protocol does not support creation of socket pairs. ++.It Bq Er EFAULT ++The address ++.Fa sv ++does not specify a valid part of the ++process address space. ++.It Bq Er ENFILE ++The system file table is full. ++.El ++.Sh SEE ALSO ++.Xr pipe 2 , ++.Xr read 2 , ++.Xr write 2 ++.Sh BUGS ++This call is currently implemented only for the ++.Tn LOCAL ++domain. ++Many operating systems only accept a ++.Ar protocol ++of ++.Ev PF_UNSPEC , ++so that should be used instead of ++.Ev PF_LOCAL ++for maximal portability. ++.Sh STANDARDS ++The ++.Fn socketpair ++function conforms to ++.St -xpg4.2 . ++.Sh HISTORY ++The ++.Fn socketpair ++function call appeared in ++.Bx 4.2 . +diff -urNad redboot-imx-200952~/packages/net/ipsec/.cvsignore redboot-imx-200952/packages/net/ipsec/.cvsignore +--- redboot-imx-200952~/packages/net/ipsec/.cvsignore 2003-11-22 13:00:08.000000000 +0000 ++++ redboot-imx-200952/packages/net/ipsec/.cvsignore 1970-01-01 00:00:00.000000000 +0000 +@@ -1 +0,0 @@ +-bsd_crypto +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/dhcp.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/dhcp.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/dhcp.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/dhcp.c 2010-01-26 17:33:17.792963633 +0000 +@@ -67,9 +67,6 @@ + * to remove the DHCP client. + * + */ +- +-#include +- + #include "lwip/stats.h" + #include "lwip/mem.h" + #include "lwip/udp.h" +@@ -85,8 +82,7 @@ + #if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */ + + /** global transaction identifier, must be +- * unique for each DHCP request. We simply increment, starting +- * with this value (easy to match with a packet analyzer) */ ++ * unique for each DHCP request. */ + static u32_t xid = 0xABCD0000; + + /** DHCP client state machine functions */ +@@ -100,7 +96,8 @@ + static void dhcp_bind(struct netif *netif); + static err_t dhcp_decline(struct netif *netif); + static err_t dhcp_rebind(struct netif *netif); +-static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); ++static err_t dhcp_release(struct netif *netif); ++static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state); + + /** receive, unfold, parse and free incoming messages */ + static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); +@@ -144,10 +141,10 @@ + static void dhcp_handle_nak(struct netif *netif) { + struct dhcp *dhcp = netif->dhcp; + u16_t msecs = 10 * 1000; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", +- (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%u\n", netif, ++ netif->name[0], netif->name[1], (unsigned int)netif->num)); + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %u msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); + } + +@@ -163,8 +160,8 @@ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], +- (s16_t)netif->name[1])); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (unsigned int)netif->name[0], ++ (unsigned int)netif->name[1])); + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); +@@ -174,7 +171,7 @@ + dhcp->tries++; + msecs = 500; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %u msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_CHECKING); + } + +@@ -188,15 +185,15 @@ + struct dhcp *dhcp = netif->dhcp; + /* obtain the server address */ + u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", +- (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%u\n", netif, ++ netif->name[0], netif->name[1], netif->num)); + if (option_ptr != NULL) + { + dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08lx\n", dhcp->server_ip_addr.addr)); + /* remember offered address */ + ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08lx\n", dhcp->offered_ip_addr.addr)); + + dhcp_select(netif); + } +@@ -215,7 +212,7 @@ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u32_t msecs; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num)); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); +@@ -234,11 +231,10 @@ + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); + +- dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); ++ dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 3); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); +- dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + /* shrink the pbuf to the actual content length */ +@@ -261,7 +257,7 @@ + dhcp->tries++; + msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %u msecs\n", msecs)); + return result; + } + +@@ -297,20 +293,18 @@ + /** + * DHCP transaction timeout handling + * +- * A DHCP server is expected to respond within a short period of time. +- * This timer checks whether an outstanding DHCP request is timed out. +- * ++ * A DHCP server is expected to respond within a ++ * short period of time. + */ + void dhcp_fine_tmr() + { + struct netif *netif = netif_list; +- /* loop through netif's */ ++ /* loop through clients */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { +- /* timer is active (non zero), and is about to trigger now */ ++ /* timer is active (non zero), and triggers (zeroes) now */ + if (netif->dhcp->request_timeout-- == 1) { +- /* { netif->dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this clients' request timeout triggered */ + dhcp_timeout(netif); +@@ -389,8 +383,8 @@ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { +- /* just retry to renew - note that the rebind timer (t2) will +- * eventually time-out if renew tries fail. */ ++ /* just retry to renew */ ++ /* note that the rebind timer will eventually time-out if renew does not work */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); + dhcp_renew(netif); + } +@@ -485,19 +479,6 @@ + if (option_ptr != NULL) { + dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } +- +- /* DNS servers */ +- option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); +- if (option_ptr != NULL) { +- u8_t n; +- dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]); +- /* limit to at most DHCP_MAX_DNS DNS servers */ +- if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS; +- for (n = 0; n < dhcp->dns_count; n++) +- { +- dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)])); +- } +- } + } + + /** +@@ -519,44 +500,40 @@ + err_t result = ERR_OK; + + LWIP_ASSERT("netif != NULL", netif != NULL); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); +- netif->flags &= ~NETIF_FLAG_DHCP; ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num)); + +- /* no DHCP client attached yet? */ + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); + dhcp = mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); ++ netif->flags &= ~NETIF_FLAG_DHCP; ++ return ERR_MEM; ++ } ++ /* clear data structure */ ++ memset(dhcp, 0, sizeof(struct dhcp)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); ++ dhcp->pcb = udp_new(); ++ if (dhcp->pcb == NULL) { ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); ++ mem_free((void *)dhcp); ++ dhcp = NULL; ++ netif->flags &= ~NETIF_FLAG_DHCP; + return ERR_MEM; + } + /* store this dhcp client in the netif */ + netif->dhcp = dhcp; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); +- /* already has DHCP client attached */ ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): created new udp pcb\n")); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n")); + } +- +- /* clear data structure */ +- memset(dhcp, 0, sizeof(struct dhcp)); +- /* allocate UDP PCB */ +- dhcp->pcb = udp_new(); +- if (dhcp->pcb == NULL) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); +- mem_free((void *)dhcp); +- netif->dhcp = dhcp = NULL; +- return ERR_MEM; +- } +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + if (result != ERR_OK) { + /* free resources allocated above */ + dhcp_stop(netif); +- return ERR_MEM; + } +- netif->flags |= NETIF_FLAG_DHCP; + return result; + } + +@@ -633,11 +610,10 @@ + */ + void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) + { +- LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n")); +- /* is a DHCP client doing an ARP check? */ ++ /* is this DHCP client doing an ARP check? */ + if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08lx\n", addr->addr)); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { +@@ -680,10 +656,8 @@ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); +- /* @todo: should we really connect here? we are performing sendto() */ +- udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); +- /* per section 4.4.4, broadcast DECLINE messages */ +- udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); ++ udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); ++ udp_send(dhcp->pcb, dhcp->p_out); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { +@@ -692,7 +666,7 @@ + dhcp->tries++; + msecs = 10*1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %u msecs\n", msecs)); + return result; + } + #endif +@@ -720,11 +694,10 @@ + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + +- dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); ++ dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 3); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); +- dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + +@@ -747,7 +720,7 @@ + dhcp->tries++; + msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %u msecs\n", msecs)); + return result; + } + +@@ -763,22 +736,22 @@ + struct ip_addr sn_mask, gw_addr; + LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num)); + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %lu secs\n", dhcp->offered_t1_renew)); + dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t1_renew*1000)); + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %lu secs\n", dhcp->offered_t2_rebind)); + dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t2_rebind*1000)); + } + /* copy offered network mask */ + ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); +@@ -802,14 +775,12 @@ + gw_addr.addr |= htonl(0x00000001); + } + +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08lx\n", dhcp->offered_ip_addr.addr)); + netif_set_ipaddr(netif, &dhcp->offered_ip_addr); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08lx\n", sn_mask.addr)); + netif_set_netmask(netif, &sn_mask); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08lx\n", gw_addr.addr)); + netif_set_gw(netif, &gw_addr); +- /* bring the interface up */ +- netif_set_up(netif); + /* netif is now bound to DHCP leased address */ + dhcp_set_state(dhcp, DHCP_BOUND); + } +@@ -865,7 +836,7 @@ + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %u msecs\n", msecs)); + return result; + } + +@@ -918,7 +889,7 @@ + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %u msecs\n", msecs)); + return result; + } + +@@ -927,7 +898,7 @@ + * + * @param netif network interface which must release its lease + */ +-err_t dhcp_release(struct netif *netif) ++static err_t dhcp_release(struct netif *netif) + { + struct dhcp *dhcp = netif->dhcp; + err_t result; +@@ -936,13 +907,8 @@ + + /* idle DHCP client */ + dhcp_set_state(dhcp, DHCP_OFF); +- /* clean old DHCP offer */ +- dhcp->server_ip_addr.addr = 0; +- dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; +- dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; +- dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; +- dhcp->dns_count = 0; +- ++ ++ + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { +@@ -964,14 +930,11 @@ + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); +- /* bring the interface down */ +- netif_set_down(netif); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %u msecs\n", msecs)); + /* remove IP address from interface */ + netif_set_ipaddr(netif, IP_ADDR_ANY); + netif_set_gw(netif, IP_ADDR_ANY); + netif_set_netmask(netif, IP_ADDR_ANY); +- + /* TODO: netif_down(netif); */ + return result; + } +@@ -1013,7 +976,7 @@ + * + * TODO: we might also want to reset the timeout here? + */ +-static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state) ++static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state) + { + if (new_state != dhcp->state) + { +@@ -1109,7 +1072,7 @@ + j = 0; + } + } +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes into dhcp->msg_in[]\n", i)); + if (dhcp->options_in != NULL) { + ptr = (u8_t *)dhcp->options_in; + /* proceed through options */ +@@ -1122,7 +1085,7 @@ + j = 0; + } + } +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes to dhcp->options_in[]\n", i)); + } + return ERR_OK; + } +@@ -1158,17 +1121,17 @@ + u8_t *options_ptr; + u8_t msg_type; + u8_t i; +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, +- (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), +- (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %u.%u.%u.%u port %u\n", p, ++ (unsigned int)(ntohl(addr->addr) >> 24 & 0xff), (unsigned int)(ntohl(addr->addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(addr->addr) >> 8 & 0xff), (unsigned int)(ntohl(addr->addr) & 0xff), port)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %u\n", p->len)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %u\n", p->tot_len)); + /* prevent warnings about unused arguments */ + (void)pcb; (void)addr; (void)port; + dhcp->p = p; + /* TODO: check packet length before reading them */ + if (reply_msg->op != DHCP_BOOTREPLY) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %u\n", reply_msg->op)); + pbuf_free(p); + dhcp->p = NULL; + return; +@@ -1176,8 +1139,8 @@ + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len; i++) { + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", +- (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%u]==%02x != reply_msg->chaddr[%u]==%02x\n", ++ i, netif->hwaddr[i], i, reply_msg->chaddr[i])); + pbuf_free(p); + dhcp->p = NULL; + return; +@@ -1317,7 +1280,7 @@ + dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; + /* packet is too small, or not 4 byte aligned? */ + while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { +- /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ ++ /* LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_option_trailer: dhcp->options_out_len=%u, DHCP_OPTIONS_LEN=%u", dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + /* add a fill/padding byte */ + dhcp->msg_out->options[dhcp->options_out_len++] = 0; +@@ -1344,7 +1307,7 @@ + u16_t offset = 0; + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { +- /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ ++ /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%u, q->len=%u", msg_offset, q->len)); */ + /* are the sname and/or file field overloaded with options? */ + if (options[offset] == DHCP_OPTION_OVERLOAD) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n")); +@@ -1354,11 +1317,11 @@ + } + /* requested option found */ + else if (options[offset] == option_type) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %u in options\n", offset)); + return &options[offset]; + /* skip option */ + } else { +- LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); ++ LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %u in options\n", options[offset])); + /* skip option type */ + offset++; + /* skip option length, and then length bytes */ +@@ -1387,11 +1350,11 @@ + /* at least 1 byte to read and no end marker */ + while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { + if (options[offset] == option_type) { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%u\n", offset)); + return &options[offset]; + /* skip option */ + } else { +- LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); ++ LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %u\n", options[offset])); + /* skip option type */ + offset++; + offset += 1 + options[offset]; +@@ -1412,7 +1375,7 @@ + */ + static u8_t dhcp_get_option_byte(u8_t *ptr) + { +- LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); ++ LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%u\n", *ptr)); + return *ptr; + } + +@@ -1429,7 +1392,7 @@ + u16_t value; + value = *ptr++ << 8; + value |= *ptr; +- LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); ++ LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%u\n", value)); + return value; + } + +@@ -1448,7 +1411,7 @@ + value |= (u32_t)(*ptr++) << 16; + value |= (u32_t)(*ptr++) << 8; + value |= (u32_t)(*ptr++); +- LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); ++ LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%lu\n", value)); + return value; + } + +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/inet.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/inet.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/inet.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/inet.c 2010-01-26 17:33:17.792963633 +0000 +@@ -46,194 +46,35 @@ + #include "lwip/def.h" + #include "lwip/inet.h" + +-#include "lwip/sys.h" + +-/* This is a reference implementation of the checksum algorithm, with the +- * aim of being simple, correct and fully portable. Checksumming is the +- * first thing you would want to optimize for your platform. You will +- * need to port it to your architecture and in your sys_arch.h: +- * +- * #define LWIP_CHKSUM +-*/ +-#ifndef LWIP_CHKSUM +-#define LWIP_CHKSUM lwip_standard_chksum + +-/** +- * lwip checksum +- * +- * @param dataptr points to start of data to be summed at any boundary +- * @param len length of data to be summed +- * @return host order (!) lwip checksum (non-inverted Internet sum) +- * +- * @note accumulator size limits summable lenght to 64k +- * @note host endianess is irrelevant (p3 RFC1071) +- */ + static u16_t +-lwip_standard_chksum(void *dataptr, u16_t len) ++lwip_chksum(void *dataptr, int len) + { + u32_t acc; +- u16_t src; +- u8_t *octetptr; +- +- acc = 0; +- /* dataptr may be at odd or even addresses */ +- octetptr = (u8_t*)dataptr; +- while (len > 1) +- { +- /* declare first octet as most significant +- thus assume network order, ignoring host order */ +- src = (*octetptr) << 8; +- octetptr++; +- /* declare second octet as least significant */ +- src |= (*octetptr); +- octetptr++; +- acc += src; +- len -= 2; +- } +- if (len > 0) +- { +- /* accumulate remaining octet */ +- src = (*octetptr) << 8; +- acc += src; +- } +- /* add deferred carry bits */ +- acc = (acc >> 16) + (acc & 0x0000ffffUL); +- if ((acc & 0xffff0000) != 0) { +- acc = (acc >> 16) + (acc & 0x0000ffffUL); +- } +- /* This maybe a little confusing: reorder sum using htons() +- instead of ntohs() since it has a little less call overhead. +- The caller must invert bits for Internet sum ! */ +- return htons((u16_t)acc); +-} +- +-#endif +- +-#if 0 +-/* +- * Curt McDowell +- * Broadcom Corp. +- * csm@broadcom.com +- * +- * IP checksum two bytes at a time with support for +- * unaligned buffer. +- * Works for len up to and including 0x20000. +- * by Curt McDowell, Broadcom Corp. 12/08/2005 +- */ +- +-static u16_t +-lwip_standard_chksum2(void *dataptr, int len) +-{ +- u8_t *pb = dataptr; +- u16_t *ps, t = 0; +- u32_t sum = 0; +- int odd = ((u32_t)pb & 1); +- +- /* Get aligned to u16_t */ +- if (odd && len > 0) { +- ((u8_t *)&t)[1] = *pb++; +- len--; +- } +- +- /* Add the bulk of the data */ +- ps = (u16_t *)pb; +- while (len > 1) { +- sum += *ps++; +- len -= 2; +- } +- +- /* Consume left-over byte, if any */ +- if (len > 0) +- ((u8_t *)&t)[0] = *(u8_t *)ps;; +- +- /* Add end bytes */ +- sum += t; +- +- /* Fold 32-bit sum to 16 bits */ +- while (sum >> 16) +- sum = (sum & 0xffff) + (sum >> 16); +- +- /* Swap if alignment was odd */ +- if (odd) +- sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); +- +- return sum; +-} +- +-/** +- * An optimized checksum routine. Basically, it uses loop-unrolling on +- * the checksum loop, treating the head and tail bytes specially, whereas +- * the inner loop acts on 8 bytes at a time. +- * +- * @arg start of buffer to be checksummed. May be an odd byte address. +- * @len number of bytes in the buffer to be checksummed. +- * +- * @todo First argument type conflicts with generic checksum routine. +- * +- * by Curt McDowell, Broadcom Corp. December 8th, 2005 +- */ + +-static u16_t +-lwip_standard_chksum4(u8_t *pb, int len) +-{ +- u16_t *ps, t = 0; +- u32_t *pl; +- u32_t sum = 0, tmp; +- /* starts at odd byte address? */ +- int odd = ((u32_t)pb & 1); +- +- if (odd && len > 0) { +- ((u8_t *)&t)[1] = *pb++; +- len--; +- } +- +- ps = (u16_t *)pb; +- +- if (((u32_t)ps & 3) && len > 1) { +- sum += *ps++; +- len -= 2; ++ LWIP_DEBUGF(INET_DEBUG, ("lwip_chksum(%p, %d)\n", (void *)dataptr, len)); ++ for(acc = 0; len > 1; len -= 2) { ++ /* acc = acc + *((u16_t *)dataptr)++;*/ ++ acc += *(u16_t *)dataptr; ++ dataptr = (void *)((u16_t *)dataptr + 1); + } + +- pl = (u32_t *)ps; +- +- while (len > 7) { +- tmp = sum + *pl++; /* ping */ +- if (tmp < sum) +- tmp++; /* add back carry */ +- +- sum = tmp + *pl++; /* pong */ +- if (sum < tmp) +- sum++; /* add back carry */ +- +- len -= 8; ++ /* add up any odd byte */ ++ if (len == 1) { ++ acc += htons((u16_t)((*(u8_t *)dataptr) & 0xff) << 8); ++ LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: odd byte %d\n", (unsigned int)(*(u8_t *)dataptr))); ++ } else { ++ LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: no odd byte\n")); + } ++ acc = (acc >> 16) + (acc & 0xffffUL); + +- /* make room in upper bits */ +- sum = (sum >> 16) + (sum & 0xffff); +- +- ps = (u16_t *)pl; +- +- /* 16-bit aligned word remaining? */ +- while (len > 1) { +- sum += *ps++; +- len -= 2; ++ if ((acc & 0xffff0000) != 0) { ++ acc = (acc >> 16) + (acc & 0xffffUL); + } + +- /* dangling tail byte remaining? */ +- if (len > 0) /* include odd byte */ +- ((u8_t *)&t)[0] = *(u8_t *)ps; +- +- sum += t; /* add end bytes */ +- +- while (sum >> 16) /* combine halves */ +- sum = (sum >> 16) + (sum & 0xffff); +- +- if (odd) +- sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); +- +- return sum; ++ return (u16_t)acc; + } +-#endif + + /* inet_chksum_pseudo: + * +@@ -255,8 +96,8 @@ + for(q = p; q != NULL; q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); +- acc += LWIP_CHKSUM(q->payload, q->len); +- /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ ++ acc += lwip_chksum(q->payload, q->len); ++ /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%lx \n", acc));*/ + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } +@@ -264,7 +105,7 @@ + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); + } +- /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ ++ /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%lx \n", acc));*/ + } + + if (swapped) { +@@ -280,8 +121,8 @@ + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } +- LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); +- return (u16_t)~(acc & 0xffffUL); ++ LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%lx\n", acc)); ++ return ~(acc & 0xffffUL); + } + + /* inet_chksum: +@@ -295,11 +136,11 @@ + { + u32_t acc; + +- acc = LWIP_CHKSUM(dataptr, len); ++ acc = lwip_chksum(dataptr, len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } +- return (u16_t)~(acc & 0xffff); ++ return ~(acc & 0xffff); + } + + u16_t +@@ -312,7 +153,7 @@ + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { +- acc += LWIP_CHKSUM(q->payload, q->len); ++ acc += lwip_chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } +@@ -325,7 +166,7 @@ + if (swapped) { + acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8); + } +- return (u16_t)~(acc & 0xffffUL); ++ return ~(acc & 0xffffUL); + } + + /* Here for now until needed in other places in lwIP */ +@@ -365,11 +206,10 @@ + */ + /* */ + /* inet_aton */ +- s8_t +- inet_aton(const char *cp, struct in_addr *addr) ++ int inet_aton(const char *cp, struct in_addr *addr) + { + u32_t val; +- s32_t base, n; ++ int base, n; + char c; + u32_t parts[4]; + u32_t* pp = parts; +@@ -392,12 +232,12 @@ + base = 8; + } + for (;;) { +- if (isdigit(c)) { +- val = (val * base) + (s16_t)(c - '0'); ++ if (isascii(c) && isdigit(c)) { ++ val = (val * base) + (c - '0'); + c = *++cp; +- } else if (base == 16 && isxdigit(c)) { ++ } else if (base == 16 && isascii(c) && isxdigit(c)) { + val = (val << 4) | +- (s16_t)(c + 10 - (islower(c) ? 'a' : 'A')); ++ (c + 10 - (islower(c) ? 'a' : 'A')); + c = *++cp; + } else + break; +@@ -462,17 +302,17 @@ + */ + char *inet_ntoa(struct in_addr addr) + { +- static char str[16]; ++ static u8_t str[16]; + u32_t s_addr = addr.s_addr; +- char inv[3]; +- char *rp; ++ u8_t inv[3]; ++ u8_t *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + + rp = str; +- ap = (u8_t *)&s_addr; ++ ap = (char *)&s_addr; + for(n = 0; n < 4; n++) { + i = 0; + do { +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/icmp.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/icmp.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/icmp.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/icmp.c 2010-01-26 17:33:17.802964134 +0000 +@@ -33,21 +33,22 @@ + /* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +-#include +- + #include "lwip/opt.h" ++ + #include "lwip/icmp.h" + #include "lwip/inet.h" + #include "lwip/ip.h" + #include "lwip/def.h" ++ + #include "lwip/stats.h" ++ + #include "lwip/snmp.h" + + void + icmp_input(struct pbuf *p, struct netif *inp) + { +- u8_t type; +- u8_t code; ++ unsigned char type; ++ unsigned char code; + struct icmp_echo_hdr *iecho; + struct ip_hdr *iphdr; + struct ip_addr tmpaddr; +@@ -60,7 +61,7 @@ + iphdr = p->payload; + hlen = IPH_HL(iphdr) * 4; + if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) { +- LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); ++ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%u bytes) received\n", p->tot_len)); + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); +@@ -73,7 +74,7 @@ + case ICMP_ECHO: + /* broadcast or multicast destination address? */ + if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) { +- LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); ++ LWIP_DEBUGF(ICMP_DEBUG, ("Smurf.\n")); + ICMP_STATS_INC(icmp.err); + pbuf_free(p); + return; +@@ -116,7 +117,7 @@ + IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp); + break; + default: +- LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); ++ LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d code %d not supported.\n", (int)type, (int)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } +@@ -139,7 +140,7 @@ + ICMPH_TYPE_SET(idur, ICMP_DUR); + ICMPH_CODE_SET(idur, t); + +- memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); ++ memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8); + + /* calculate checksum */ + idur->chksum = 0; +@@ -177,7 +178,7 @@ + ICMPH_CODE_SET(tehdr, t); + + /* copy fields from original packet */ +- memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); ++ memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8); + + /* calculate checksum */ + tehdr->chksum = 0; +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip.c 2010-01-26 17:33:17.802964134 +0000 +@@ -1,10 +1,3 @@ +-/* @file +- * +- * This is the IP layer implementation for incoming and outgoing IP traffic. +- * +- * @see ip_frag.c +- * +- */ + /* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. +@@ -37,8 +30,18 @@ + * + */ + ++ ++ ++/* ip.c ++ * ++ * This is the code for the IP layer. ++ * ++ */ ++ ++ + #include "lwip/opt.h" + ++ + #include "lwip/def.h" + #include "lwip/mem.h" + #include "lwip/ip.h" +@@ -60,17 +63,18 @@ + #endif /* LWIP_DHCP */ + + +-/** ++/* ip_init: ++ * + * Initializes the IP layer. + */ + + void + ip_init(void) + { +- /* no initializations as of yet */ + } + +-/** ++/* ip_route: ++ * + * Finds the appropriate network interface for a given IP address. It + * searches the list of network interfaces linearly. A match is found + * if the masked IP address of the network interface equals the masked +@@ -85,7 +89,7 @@ + /* iterate through netifs */ + for(netif = netif_list; netif != NULL; netif = netif->next) { + /* network mask matches? */ +- if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { ++ if (ip_addr_maskcmp(dest, &(netif->ip_addr), &(netif->netmask))) { + /* return netif on which to forward IP packet */ + return netif; + } +@@ -95,13 +99,14 @@ + } + #if IP_FORWARD + +-/** ++/* ip_forward: ++ * + * Forwards an IP packet. It finds an appropriate route for the + * packet, decrements the TTL value of the packet, adjusts the + * checksum and outputs the packet on the appropriate interface. + */ + +-static struct netif * ++static void + ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) + { + struct netif *netif; +@@ -110,17 +115,17 @@ + /* Find network interface where to forward this IP packet to. */ + netif = ip_route((struct ip_addr *)&(iphdr->dest)); + if (netif == NULL) { +- LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", ++ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%lx found\n", + iphdr->dest.addr)); + snmp_inc_ipnoroutes(); +- return (struct netif *)NULL; ++ return; + } + /* Do not forward packets onto the same network interface on which +- * they arrived. */ ++ they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); + snmp_inc_ipnoroutes(); +- return (struct netif *)NULL; ++ return; + } + + /* decrement TTL */ +@@ -132,7 +137,7 @@ + icmp_time_exceeded(p, ICMP_TE_TTL); + snmp_inc_icmpouttimeexcds(); + } +- return (struct netif *)NULL; ++ return; + } + + /* Incrementally update the IP checksum. */ +@@ -142,7 +147,7 @@ + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); + } + +- LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", ++ LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%lx\n", + iphdr->dest.addr)); + + IP_STATS_INC(ip.fw); +@@ -152,11 +157,11 @@ + PERF_STOP("ip_forward"); + /* transmit pbuf on chosen interface */ + netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); +- return netif; + } + #endif /* IP_FORWARD */ + +-/** ++/* ip_input: ++ * + * This function is called by the network interface device driver when + * an IP packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header +@@ -164,16 +169,13 @@ + * forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. +- * +- * +- * + */ + + err_t + ip_input(struct pbuf *p, struct netif *inp) { +- struct ip_hdr *iphdr; +- struct netif *netif; +- u16_t iphdrlen; ++ static struct ip_hdr *iphdr; ++ static struct netif *netif; ++ static u16_t iphdrlen; + + IP_STATS_INC(ip.recv); + snmp_inc_ipinreceives(); +@@ -181,7 +183,7 @@ + /* identify the IP header */ + iphdr = p->payload; + if (IPH_V(iphdr) != 4) { +- LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); ++ LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %u\n", IPH_V(iphdr))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.err); +@@ -196,7 +198,7 @@ + + /* header length exceeds first pbuf length? */ + if (iphdrlen > p->len) { +- LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n", ++ LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %u) does not fit in first pbuf (len %u), IP packet droppped.\n", + iphdrlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); +@@ -210,7 +212,7 @@ + #if CHECKSUM_CHECK_IP + if (inet_chksum(iphdr, iphdrlen) != 0) { + +- LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); ++ LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%x) failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.chkerr); +@@ -221,41 +223,43 @@ + #endif + + /* Trim pbuf. This should have been done at the netif layer, +- * but we'll do it anyway just to be sure that its done. */ ++ but we'll do it anyway just to be sure that its done. */ + pbuf_realloc(p, ntohs(IPH_LEN(iphdr))); + +- /* match packet against an interface, i.e. is this packet for us? */ +- for (netif = netif_list; netif != NULL; netif = netif->next) { ++ /* is this packet for us? */ ++ for(netif = netif_list; netif != NULL; netif = netif->next) { + +- LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", +- iphdr->dest.addr, netif->ip_addr.addr, +- iphdr->dest.addr & netif->netmask.addr, +- netif->ip_addr.addr & netif->netmask.addr, +- iphdr->dest.addr & ~(netif->netmask.addr))); ++ LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%lx netif->ip_addr 0x%lx (0x%lx, 0x%lx, 0x%lx)\n", ++ iphdr->dest.addr, netif->ip_addr.addr, ++ iphdr->dest.addr & netif->netmask.addr, ++ netif->ip_addr.addr & netif->netmask.addr, ++ iphdr->dest.addr & ~(netif->netmask.addr))); + +- /* interface is up and configured? */ +- if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) ++ /* interface configured? */ ++ if (!ip_addr_isany(&(netif->ip_addr))) + { + /* unicast to this interface address? */ + if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || +- /* or broadcast on this interface network address? */ +- ip_addr_isbroadcast(&(iphdr->dest), netif)) { +- LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", +- netif->name[0], netif->name[1])); +- /* break out of for loop */ +- break; ++ /* or broadcast matching this interface network address? */ ++ (ip_addr_isbroadcast(&(iphdr->dest), netif) && ++ ip_addr_maskcmp(&(iphdr->dest), &(netif->ip_addr), &(netif->netmask))) || ++ /* or restricted broadcast? */ ++ ip_addr_cmp(&(iphdr->dest), IP_ADDR_BROADCAST)) { ++ LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", ++ netif->name[0], netif->name[1])); ++ /* break out of for loop */ ++ break; + } + } + } + #if LWIP_DHCP + /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed +- * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. +- * According to RFC 1542 section 3.1.1, referred by RFC 2131). +- */ ++ using link layer addressing (such as Ethernet MAC) so we must not filter on IP. ++ According to RFC 1542 section 3.1.1, referred by RFC 2131). */ + if (netif == NULL) { + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { +- LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", ++ LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %u\n", + ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest))); + if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) { + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n")); +@@ -264,7 +268,7 @@ + } + } + #endif /* LWIP_DHCP */ +- /* packet not for us? */ ++ /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n")); +@@ -282,30 +286,30 @@ + pbuf_free(p); + return ERR_OK; + } +- /* packet consists of multiple fragments? */ ++ ++#if IP_REASSEMBLY + if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { +-#if IP_REASSEMBLY /* packet fragment reassembly code present? */ +- LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", ++ LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04x tot_len=%u len=%u MF=%u offset=%u), calling ip_reass()\n", + ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); +- /* reassemble the packet*/ + p = ip_reass(p); +- /* packet not fully reassembled yet? */ + if (p == NULL) { + return ERR_OK; + } + iphdr = p->payload; +-#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ ++ } ++#else /* IP_REASSEMBLY */ ++ if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { + pbuf_free(p); +- LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", +- ntohs(IPH_OFFSET(iphdr)))); ++ LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%x) (while IP_REASSEMBLY == 0).\n", ++ ntohs(IPH_OFFSET(iphdr)))); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + snmp_inc_ipunknownprotos(); + return ERR_OK; +-#endif /* IP_REASSEMBLY */ + } ++#endif /* IP_REASSEMBLY */ + +-#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */ ++#if IP_OPTIONS == 0 + if (iphdrlen > IP_HLEN) { + LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n")); + pbuf_free(p); +@@ -319,11 +323,10 @@ + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); + ip_debug_print(p); +- LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); ++ LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %d p->tot_len %d\n", p->len, p->tot_len)); + + #if LWIP_RAW +- /* raw input did not eat the packet? */ +- if (raw_input(p, inp) == 0) { ++ if (!raw_input(p, inp)) { + #endif /* LWIP_RAW */ + + switch (IPH_PROTO(iphdr)) { +@@ -353,11 +356,12 @@ + } + pbuf_free(p); + +- LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); ++ LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %d\n", IPH_PROTO(iphdr))); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + snmp_inc_ipunknownprotos(); ++ + } + #if LWIP_RAW + } /* LWIP_RAW */ +@@ -365,7 +369,9 @@ + return ERR_OK; + } + +-/** ++ ++/* ip_output_if: ++ * + * Sends an IP packet on a network interface. This function constructs + * the IP header and calculates the IP header checksum. If the source + * IP address is NULL, the IP address of the outgoing network +@@ -377,8 +383,8 @@ + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) + { +- struct ip_hdr *iphdr; +- u16_t ip_id = 0; ++ static struct ip_hdr *iphdr; ++ static u16_t ip_id = 0; + + snmp_inc_ipoutrequests(); + +@@ -427,7 +433,7 @@ + + IP_STATS_INC(ip.xmit); + +- LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); ++ LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%u\n", netif->name[0], netif->name[1], netif->num)); + ip_debug_print(p); + + LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); +@@ -435,7 +441,8 @@ + return netif->output(netif, p, dest); + } + +-/** ++/* ip_output: ++ * + * Simple interface to ip_output_if. It finds the outgoing network + * interface and calls upon ip_output_if to do the actual work. + */ +@@ -447,7 +454,7 @@ + struct netif *netif; + + if ((netif = ip_route(dest)) == NULL) { +- LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); ++ LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%lx\n", dest->addr)); + + IP_STATS_INC(ip.rterr); + snmp_inc_ipoutdiscards(); +@@ -468,35 +475,35 @@ + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", ++ LWIP_DEBUGF(IP_DEBUG, ("|%2d |%2d | 0x%02x | %5u | (v, hl, tos, len)\n", + IPH_V(iphdr), + IPH_HL(iphdr), + IPH_TOS(iphdr), + ntohs(IPH_LEN(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", ++ LWIP_DEBUGF(IP_DEBUG, ("| %5u |%u%u%u| %4u | (id, flags, offset)\n", + ntohs(IPH_ID(iphdr)), + ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, + ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", ++ LWIP_DEBUGF(IP_DEBUG, ("| %3u | %3u | 0x%04x | (ttl, proto, chksum)\n", + IPH_TTL(iphdr), + IPH_PROTO(iphdr), + ntohs(IPH_CHKSUM(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", +- ip4_addr1(&iphdr->src), +- ip4_addr2(&iphdr->src), +- ip4_addr3(&iphdr->src), +- ip4_addr4(&iphdr->src))); ++ LWIP_DEBUGF(IP_DEBUG, ("| %3ld | %3ld | %3ld | %3ld | (src)\n", ++ ntohl(iphdr->src.addr) >> 24 & 0xff, ++ ntohl(iphdr->src.addr) >> 16 & 0xff, ++ ntohl(iphdr->src.addr) >> 8 & 0xff, ++ ntohl(iphdr->src.addr) & 0xff)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", +- ip4_addr1(&iphdr->dest), +- ip4_addr2(&iphdr->dest), +- ip4_addr3(&iphdr->dest), +- ip4_addr4(&iphdr->dest))); ++ LWIP_DEBUGF(IP_DEBUG, ("| %3ld | %3ld | %3ld | %3ld | (dest)\n", ++ ntohl(iphdr->dest.addr) >> 24 & 0xff, ++ ntohl(iphdr->dest.addr) >> 16 & 0xff, ++ ntohl(iphdr->dest.addr) >> 8 & 0xff, ++ ntohl(iphdr->dest.addr) & 0xff)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + } + #endif /* IP_DEBUG */ +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip_addr.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip_addr.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip_addr.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip_addr.c 2010-01-26 17:33:17.802964134 +0000 +@@ -60,12 +60,9 @@ + /* address matches network interface address exactly? => no broadcast */ + else if (addr->addr == netif->ip_addr.addr) + return 0; +- /* on the same (sub) network... */ +- else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) +- /* ...and host identifier bits are all ones? =>... */ +- && ((addr->addr & ~netif->netmask.addr) == +- (ip_addr_broadcast.addr & ~netif->netmask.addr))) +- /* => network broadcast address */ ++ /* host identifier bits are all ones? => network broadcast address */ ++ else if ((addr->addr & ~netif->netmask.addr) == ++ (ip_addr_broadcast.addr & ~netif->netmask.addr)) + return 1; + else + return 0; +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip_frag.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip_frag.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/ipv4/ip_frag.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/ipv4/ip_frag.c 2010-01-26 17:33:17.812965010 +0000 +@@ -1,9 +1,3 @@ +-/* @file +- * +- * This is the IP packet segmentation and reassembly implementation. +- * +- */ +- + /* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. +@@ -37,13 +31,20 @@ + * + */ + +-#include ++ ++/* ip_frag.c ++ * ++ * This is the code for IP segmentation and reassembly ++ * ++ */ ++ + + #include "lwip/opt.h" +-/* #include "lwip/sys.h" */ ++#include "lwip/sys.h" + #include "lwip/ip.h" + #include "lwip/ip_frag.h" + #include "lwip/netif.h" ++ + #include "lwip/stats.h" + + +@@ -78,7 +79,7 @@ + #define IP_REASS_TMO 1000 + + static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE]; +-static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1]; ++static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8)]; + static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01 + }; +@@ -88,26 +89,18 @@ + + static u8_t ip_reasstmr; + +-/** +- * Reassembly timer base function +- * for both NO_SYS == 0 and 1 (!). +- * +- * Should be called every 1000 msec. +- */ +-void +-ip_reass_tmr(void) ++/* Reassembly timer */ ++static void ++ip_reass_timer(void *arg) + { +- if (ip_reasstmr > 0) { ++ (void)arg; ++ if (ip_reasstmr > 1) { + ip_reasstmr--; +- } ++ sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL); ++ } else if (ip_reasstmr == 1) ++ ip_reasstmr = 0; + } + +-/** +- * Reassembles incoming IP fragments into an IP datagram. +- * +- * @param p points to a pbuf chain of the fragment +- * @return NULL if reassembly is incomplete, ? otherwise +- */ + struct pbuf * + ip_reass(struct pbuf *p) + { +@@ -127,6 +120,7 @@ + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n")); + memcpy(iphdr, fraghdr, IP_HLEN); + ip_reasstmr = IP_REASS_MAXAGE; ++ sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL); + ip_reassflags = 0; + /* Clear the bitmap. */ + memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); +@@ -138,8 +132,7 @@ + if (ip_addr_cmp(&iphdr->src, &fraghdr->src) && + ip_addr_cmp(&iphdr->dest, &fraghdr->dest) && + IPH_ID(iphdr) == IPH_ID(fraghdr)) { +- LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", +- ntohs(IPH_ID(fraghdr)))); ++ LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching old packet\n")); + IPFRAG_STATS_INC(ip_frag.cachehit); + /* Find out the offset in the reassembly buffer where we should + copy the fragment. */ +@@ -150,8 +143,9 @@ + reassembly buffer, we discard the entire packet. */ + if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) { + LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset, ++ ("ip_reass: fragment outside of buffer (%d:%d/%d).\n", offset, + offset + len, IP_REASS_BUFSIZE)); ++ sys_untimeout(ip_reass_timer, NULL); + ip_reasstmr = 0; + goto nullreturn; + } +@@ -159,7 +153,7 @@ + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset, ++ ("ip_reass: copying with offset %d into %d:%d\n", offset, + IP_HLEN + offset, IP_HLEN + offset + len)); + i = IPH_HL(fraghdr) * 4; + copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len); +@@ -168,29 +162,24 @@ + if (offset / (8 * 8) == (offset + len) / (8 * 8)) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: updating single byte in bitmap.\n")); +- /* If the two endpoints are in the same byte, we only update that byte. */ +- LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", +- offset / (8 * 8) < sizeof(ip_reassbitmap)); ++ /* If the two endpoints are in the same byte, we only update ++ that byte. */ + ip_reassbitmap[offset / (8 * 8)] |= +- bitmap_bits[(offset / 8) & 7] & +- ~bitmap_bits[((offset + len) / 8) & 7]; ++ bitmap_bits[(offset / 8) & 7] & ++ ~bitmap_bits[((offset + len) / 8) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ +- LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", +- offset / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7]; + LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n", ++ ("ip_reass: updating many bytes in bitmap (%d:%d).\n", + 1 + offset / (8 * 8), (offset + len) / (8 * 8))); + for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { +- ip_reassbitmap[i] = 0xff; ++ ip_reassbitmap[i] = 0xff; + } +- LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)", +- (offset + len) / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[(offset + len) / (8 * 8)] |= +- ~bitmap_bits[((offset + len) / 8) & 7]; ++ ~bitmap_bits[((offset + len) / 8) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we +@@ -203,7 +192,7 @@ + ip_reassflags |= IP_REASS_FLAG_LASTFRAG; + ip_reasslen = offset + len; + LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: last fragment seen, total len %"S16_F"\n", ++ ("ip_reass: last fragment seen, total len %d\n", + ip_reasslen)); + } + +@@ -213,27 +202,23 @@ + if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ +- LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)", +- ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)); + for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) { +- if (ip_reassbitmap[i] != 0xff) { +- LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n", +- i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); +- goto nullreturn; +- } ++ if (ip_reassbitmap[i] != 0xff) { ++ LWIP_DEBUGF(IP_REASS_DEBUG, ++ ("ip_reass: last fragment seen, bitmap %d/%d failed (%x)\n", ++ i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); ++ goto nullreturn; ++ } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ +- LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)", +- ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)); + if (ip_reassbitmap[ip_reasslen / (8 * 8)] != +- (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { +- LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n", +- ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], +- ip_reassbitmap[ip_reasslen / (8 * 8)])); +- goto nullreturn; ++ (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { ++ LWIP_DEBUGF(IP_REASS_DEBUG, ++ ("ip_reass: last fragment seen, bitmap %d didn't contain %x (%x)\n", ++ ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], ++ ip_reassbitmap[ip_reasslen / (8 * 8)])); ++ goto nullreturn; + } + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet +@@ -248,25 +233,27 @@ + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ ++ sys_untimeout(ip_reass_timer, NULL); + ip_reasstmr = 0; + pbuf_free(p); + p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL); + if (p != NULL) { +- i = 0; +- for (q = p; q != NULL; q = q->next) { +- /* Copy enough bytes to fill this pbuf in the chain. The +- available data in the pbuf is given by the q->len variable. */ +- LWIP_DEBUGF(IP_REASS_DEBUG, +- ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n", +- (void *)&ip_reassbuf[i], i, q->payload, +- q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); +- memcpy(q->payload, &ip_reassbuf[i], +- q->len > ip_reasslen - i ? ip_reasslen - i : q->len); +- i += q->len; +- } +- IPFRAG_STATS_INC(ip_frag.fw); ++ i = 0; ++ for (q = p; q != NULL; q = q->next) { ++ /* Copy enough bytes to fill this pbuf in the chain. The ++ available data in the pbuf is given by the q->len ++ variable. */ ++ LWIP_DEBUGF(IP_REASS_DEBUG, ++ ("ip_reass: memcpy from %p (%d) to %p, %d bytes\n", ++ &ip_reassbuf[i], i, q->payload, ++ q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); ++ memcpy(q->payload, &ip_reassbuf[i], ++ q->len > ip_reasslen - i ? ip_reasslen - i : q->len); ++ i += q->len; ++ } ++ IPFRAG_STATS_INC(ip_frag.fw); + } else { +- IPFRAG_STATS_INC(ip_frag.memerr); ++ IPFRAG_STATS_INC(ip_frag.memerr); + } + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p)); + return p; +@@ -283,9 +270,9 @@ + static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)]; + + /** +- * Fragment an IP datagram if too large for the netif. ++ * Fragment an IP packet if too large + * +- * Chop the datagram in MTU sized chunks and send them in order ++ * Chop the packet in mtu sized chunks and send them in order + * by using a fixed size static memory buffer (PBUF_ROM) + */ + err_t +@@ -304,12 +291,10 @@ + + /* Get a RAM based MTU sized pbuf */ + rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); +- if (rambuf == NULL) { +- return ERR_MEM; +- } + rambuf->tot_len = rambuf->len = mtu; + rambuf->payload = MEM_ALIGN((void *)buf); + ++ + /* Copy the IP header in it */ + iphdr = rambuf->payload; + memcpy(iphdr, p->payload, IP_HLEN); +@@ -350,15 +335,11 @@ + * worked would make things simpler. + */ + header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); +- if (header != NULL) { +- pbuf_chain(header, rambuf); +- netif->output(netif, header, dest); +- IPFRAG_STATS_INC(ip_frag.xmit); +- pbuf_free(header); +- } else { +- pbuf_free(rambuf); +- return ERR_MEM; +- } ++ pbuf_chain(header, rambuf); ++ netif->output(netif, header, dest); ++ IPFRAG_STATS_INC(ip_frag.xmit); ++ pbuf_free(header); ++ + left -= cop; + } + pbuf_free(rambuf); +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/mem.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/mem.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/mem.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/mem.c 2010-01-26 17:33:17.812965010 +0000 +@@ -36,7 +36,6 @@ + * + */ + +-#include + + #include "lwip/arch.h" + #include "lwip/opt.h" +@@ -301,7 +300,7 @@ + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } +- LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); ++ LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %d bytes\n", (int)size)); + #if MEM_STATS + ++lwip_stats.mem.err; + #endif /* MEM_STATS */ +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/memp.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/memp.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/memp.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/memp.c 2010-01-26 17:33:17.812965010 +0000 +@@ -124,7 +124,7 @@ + static int + memp_sanity(void) + { +- s16_t i, c; ++ int i, c; + struct memp *m, *n; + + for(i = 0; i < MEMP_MAX; i++) { +@@ -222,7 +222,7 @@ + mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp)); + return mem; + } else { +- LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type)); ++ LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %d\n", type)); + #if MEMP_STATS + ++lwip_stats.memp[type].err; + #endif /* MEMP_STATS */ +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/netif.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/netif.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/netif.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/netif.c 2010-01-26 17:33:17.822965135 +0000 +@@ -67,7 +67,8 @@ + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)) + { +- static s16_t netifnum = 0; ++ static int netifnum = 0; ++ + + #if LWIP_DHCP + /* netif not under DHCP control by default */ +@@ -197,44 +198,36 @@ + } + #endif + ip_addr_set(&(netif->ip_addr), ipaddr); +-#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */ +- /** For Ethernet network interfaces, we would like to send a +- * "gratuitous ARP"; this is an ARP packet sent by a node in order +- * to spontaneously cause other nodes to update an entry in their +- * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6. +- */ +- etharp_query(netif, ipaddr, NULL); +-#endif +- LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", ++ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %u.%u.%u.%u\n", + netif->name[0], netif->name[1], +- ip4_addr1(&netif->ip_addr), +- ip4_addr2(&netif->ip_addr), +- ip4_addr3(&netif->ip_addr), +- ip4_addr4(&netif->ip_addr))); ++ (unsigned int)(ntohl(netif->ip_addr.addr) >> 24 & 0xff), ++ (unsigned int)(ntohl(netif->ip_addr.addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(netif->ip_addr.addr) >> 8 & 0xff), ++ (unsigned int)(ntohl(netif->ip_addr.addr) & 0xff))); + } + + void + netif_set_gw(struct netif *netif, struct ip_addr *gw) + { + ip_addr_set(&(netif->gw), gw); +- LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", +- netif->name[0], netif->name[1], +- ip4_addr1(&netif->gw), +- ip4_addr2(&netif->gw), +- ip4_addr3(&netif->gw), +- ip4_addr4(&netif->gw))); ++ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %u.%u.%u.%u\n", ++ netif->name[0], netif->name[1], ++ (unsigned int)(ntohl(netif->gw.addr) >> 24 & 0xff), ++ (unsigned int)(ntohl(netif->gw.addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(netif->gw.addr) >> 8 & 0xff), ++ (unsigned int)(ntohl(netif->gw.addr) & 0xff))); + } + + void + netif_set_netmask(struct netif *netif, struct ip_addr *netmask) + { + ip_addr_set(&(netif->netmask), netmask); +- LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", +- netif->name[0], netif->name[1], +- ip4_addr1(&netif->netmask), +- ip4_addr2(&netif->netmask), +- ip4_addr3(&netif->netmask), +- ip4_addr4(&netif->netmask))); ++ LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %u.%u.%u.%u\n", ++ netif->name[0], netif->name[1], ++ (unsigned int)(ntohl(netif->netmask.addr) >> 24 & 0xff), ++ (unsigned int)(ntohl(netif->netmask.addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(netif->netmask.addr) >> 8 & 0xff), ++ (unsigned int)(ntohl(netif->netmask.addr) & 0xff))); + } + + void +@@ -245,41 +238,6 @@ + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); + } + +-/** +- * Bring an interface up, available for processing +- * traffic. +- * +- * @note: Enabling DHCP on a down interface will make it come +- * up once configured. +- * +- * @see dhcp_start() +- */ +-void netif_set_up(struct netif *netif) +-{ +- netif->flags |= NETIF_FLAG_UP; +-} +- +-/** +- * Ask if an interface is up +- */ +-u8_t netif_is_up(struct netif *netif) +-{ +- return (netif->flags & NETIF_FLAG_UP)?1:0; +-} +- +-/** +- * Bring an interface down, disabling any traffic processing. +- * +- * @note: Enabling DHCP on a down interface will make it come +- * up once configured. +- * +- * @see dhcp_start() +- */ +-void netif_set_down(struct netif *netif) +-{ +- netif->flags &= ~NETIF_FLAG_UP; +-} +- + void + netif_init(void) + { +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/pbuf.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/pbuf.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/pbuf.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/pbuf.c 2010-01-26 17:33:17.822965135 +0000 +@@ -62,18 +62,20 @@ + * + */ + +-#include +- + #include "lwip/opt.h" ++ + #include "lwip/stats.h" ++ + #include "lwip/def.h" + #include "lwip/mem.h" + #include "lwip/memp.h" + #include "lwip/pbuf.h" ++ + #include "lwip/sys.h" ++ + #include "arch/perf.h" + +-static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))]; ++static u8_t pbuf_pool_memory[(PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf)))]; + + #if !SYS_LIGHTWEIGHT_PROT + static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock; +@@ -100,7 +102,8 @@ + struct pbuf *p, *q = NULL; + u16_t i; + +- pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory); ++ pbuf_pool = (struct pbuf *)&pbuf_pool_memory[0]; ++ LWIP_ASSERT("pbuf_init: pool aligned", (mem_ptr_t)pbuf_pool % MEM_ALIGNMENT == 0); + + #if PBUF_STATS + lwip_stats.pbuf.avail = PBUF_POOL_SIZE; +@@ -180,7 +183,7 @@ + + + /** +- * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). ++ * Allocates a pbuf. + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size +@@ -214,7 +217,7 @@ + struct pbuf *p, *q, *r; + u16_t offset; + s32_t rem_len; /* remaining length */ +- LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length)); ++ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u)\n", length)); + + /* determine header offset */ + offset = 0; +@@ -303,7 +306,7 @@ + break; + case PBUF_RAM: + /* If pbuf is to be allocated in RAM, allocate memory for it. */ +- p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length)); ++ p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + length + offset)); + if (p == NULL) { + return NULL; + } +@@ -316,7 +319,7 @@ + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; +- /* pbuf references existing (non-volatile static constant) ROM payload? */ ++ /* pbuf references existing (static constant) ROM payload? */ + case PBUF_ROM: + /* pbuf references existing (externally allocated) RAM payload? */ + case PBUF_REF: +@@ -338,7 +341,7 @@ + } + /* set reference count */ + p->ref = 1; +- LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); ++ LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u) == %p\n", length, (void *)p)); + return p; + } + +@@ -450,60 +453,55 @@ + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * +- * @param hdr_size_inc Number of bytes to increment header size which ++ * @param hdr_size Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) +- * If hdr_size_inc is 0, this function does nothing and returns succesful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. +- * @return non-zero on failure, zero on success. ++ * @return 1 on failure, 0 on success. + * ++ * @note May not be called on a packet queue. + */ + u8_t +-pbuf_header(struct pbuf *p, s16_t header_size_increment) ++pbuf_header(struct pbuf *p, s16_t header_size) + { + void *payload; + +- LWIP_ASSERT("p != NULL", p != NULL); +- if ((header_size_increment == 0) || (p == NULL)) return 0; +- + /* remember current payload pointer */ + payload = p->payload; + + /* pbuf types containing payloads? */ + if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) { + /* set new payload pointer */ +- p->payload = (u8_t *)p->payload - header_size_increment; ++ p->payload = (u8_t *)p->payload - header_size; + /* boundary check fails? */ + if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) { +- LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", +- (void *)p->payload, +- (void *)(p + 1)));\ ++ LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p\n", ++ (u8_t *)p->payload, ++ (u8_t *)p + sizeof(struct pbuf)) );\ + /* restore old payload pointer */ + p->payload = payload; + /* bail out unsuccesfully */ + return 1; + } +- /* pbuf types refering to external payloads? */ ++ /* pbuf types refering to payloads? */ + } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) { + /* hide a header in the payload? */ +- if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) { ++ if ((header_size < 0) && (header_size - p->len <= 0)) { + /* increase payload pointer */ +- p->payload = (u8_t *)p->payload - header_size_increment; ++ p->payload = (u8_t *)p->payload - header_size; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccesfully */ + return 1; + } + } ++ LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%d)\n", (void *)payload, (void *)p->payload, header_size) ); + /* modify pbuf length fields */ +- p->len += header_size_increment; +- p->tot_len += header_size_increment; +- +- LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n", +- (void *)payload, (void *)p->payload, header_size_increment)); ++ p->len += header_size; ++ p->tot_len += header_size; + + return 0; + } +@@ -512,20 +510,19 @@ + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * +- * Decrements the pbuf reference count. If it reaches zero, the pbuf is +- * deallocated. ++ * Decrements the pbuf reference count. If it reaches ++ * zero, the pbuf is deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after +- * decrementing. So, when all reference counts are one, the whole +- * chain is free'd. ++ * decrementing. (This might de-allocate the whole chain.) + * + * @param pbuf The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * +- * @note MUST NOT be called on a packet queue (Not verified to work yet). ++ * @note MUST NOT be called on a packet queue. + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * +@@ -584,7 +581,7 @@ + p->len = p->tot_len = PBUF_POOL_BUFSIZE; + p->payload = (void *)((u8_t *)p + sizeof(struct pbuf)); + PBUF_POOL_FREE(p); +- /* is this a ROM or RAM referencing pbuf? */ ++ /* a ROM or RAM referencing pbuf */ + } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) { + memp_free(MEMP_PBUF, p); + /* p->flags == PBUF_FLAG_RAM */ +@@ -597,8 +594,8 @@ + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { +- LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref)); +- /* stop walking through the chain */ ++ LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %u, ending here.\n", (void *)p, (unsigned int)p->ref)); ++ /* stop walking through chain */ + p = NULL; + } + } +@@ -661,8 +658,8 @@ + { + struct pbuf *p; + +- LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL); +- LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL); ++ LWIP_ASSERT("h != NULL", h != NULL); ++ LWIP_ASSERT("t != NULL", t != NULL); + if ((h == NULL) || (t == NULL)) return; + + /* proceed to last pbuf of chain */ +@@ -672,14 +669,10 @@ + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); +- LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len += t->tot_len; + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; +- /* p->next now references t, but the caller will drop its reference to t, +- * so netto there is no change to the reference count of t. +- */ + } + + /** +@@ -707,8 +700,8 @@ + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); + } + +-/* For packet queueing. Note that queued packets MUST be dequeued first +- * using pbuf_dequeue() before calling other pbuf_() functions. */ ++/* For packet queueing. Note that queued packets must be dequeued first ++ * before calling any pbuf functions. */ + #if ARP_QUEUEING + /** + * Add a packet to the end of a queue. +@@ -716,22 +709,13 @@ + * @param q pointer to first packet on the queue + * @param n packet to be queued + * +- * Both packets MUST be given, and must be different. + */ + void + pbuf_queue(struct pbuf *p, struct pbuf *n) + { +-#if PBUF_DEBUG /* remember head of queue */ +- struct pbuf *q = p; +-#endif +- /* programmer stupidity checks */ +- LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL); +- LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL); +- LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n); +- if ((p == NULL) || (n == NULL) || (p == n)){ +- LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n")); +- return; +- } ++ LWIP_ASSERT("p != NULL", p != NULL); ++ LWIP_ASSERT("n != NULL", n != NULL); ++ if ((p == NULL) || (n == NULL)) return; + + /* iterate through all packets on queue */ + while (p->next != NULL) { +@@ -744,33 +728,26 @@ + /* make sure each packet is complete */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + p = p->next; +- /* { p->tot_len == p->len => p is last pbuf of a packet } */ ++ /* { p->tot_len == p->len } => p is last pbuf of a packet */ + } +- /* { p is last pbuf of a packet } */ +- /* proceed to next packet on queue */ + #endif +- /* proceed to next pbuf */ ++ /* { p->tot_len == p->len } => p is last pbuf of a packet */ ++ /* proceed to next packet on queue */ + if (p->next != NULL) p = p->next; + } + /* { p->tot_len == p->len and p->next == NULL } ==> + * { p is last pbuf of last packet on queue } */ + /* chain last pbuf of queue with n */ + p->next = n; +- /* n is now referenced to by the (packet p in the) queue */ ++ /* n is now referenced to one more time */ + pbuf_ref(n); +-#if PBUF_DEBUG +- LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, +- ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n", +- (void *)n, (void *)p, (void *)q)); +-#endif ++ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_queue: referencing queued packet %p\n", (void *)n)); + } + + /** + * Remove a packet from the head of a queue. + * +- * The caller MUST reference the remainder of the queue (as returned). The +- * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference +- * from p. ++ * The caller MUST reference the remainder of the queue (as returned). + * + * @param p pointer to first packet on the queue which will be dequeued. + * @return first packet on the remaining queue (NULL if no further packets). +@@ -782,7 +759,7 @@ + struct pbuf *q; + LWIP_ASSERT("p != NULL", p != NULL); + +- /* iterate through all pbufs in packet p */ ++ /* iterate through all pbufs in packet */ + while (p->tot_len != p->len) { + /* make sure invariant condition holds */ + LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); +@@ -791,16 +768,15 @@ + p = p->next; + } + /* { p->tot_len == p->len } => p is the last pbuf of the first packet */ +- /* remember next packet on queue in q */ ++ /* remember next packet on queue */ + q = p->next; +- /* dequeue packet p from queue */ ++ /* dequeue p from queue */ + p->next = NULL; + /* any next packet on queue? */ + if (q != NULL) { + /* although q is no longer referenced by p, it MUST be referenced by +- * the caller, who is maintaining this packet queue. So, we do not call +- * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */ +- LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q)); ++ * the caller, who is maintaining this packet queue */ ++ LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: at least one packet on queue, first %p\n", (void *)q)); + } else { + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n")); + } +@@ -821,7 +797,7 @@ + * + * @note You MUST explicitly use p = pbuf_take(p); + * The pbuf you give as argument, may have been replaced +- * by a (differently located) copy through pbuf_take()! ++ * by pbuf_take()! + * + * @note Any replaced pbufs will be freed through pbuf_free(). + * This may deallocate them if they become no longer referenced. +@@ -849,9 +825,7 @@ + /* PBUF_POOL buffers are faster if we can use them */ + if (p->len <= PBUF_POOL_BUFSIZE) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL); +- if (q == NULL) { +- LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); +- } ++ if (q == NULL) LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); + } else { + /* no replacement pbuf yet */ + q = NULL; +@@ -860,9 +834,7 @@ + /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */ + if (q == NULL) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM); +- if (q == NULL) { +- LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); +- } ++ if (q == NULL) LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); + } + /* replacement pbuf could be allocated? */ + if (q != NULL) +@@ -945,10 +917,8 @@ + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); +- if (tail_gone > 0) { +- LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, +- ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); +- } ++ if (tail_gone > 0) LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ++ ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/raw.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/raw.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/raw.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/raw.c 2010-01-26 17:33:17.832964510 +0000 +@@ -1,9 +1,6 @@ + /** + * @file +- * +- * Implementation of raw protocol PCBs for low-level handling of +- * different types of protocols besides (or overriding) those +- * already available in lwIP. ++ * Raw Access module + * + */ + /* +@@ -38,7 +35,12 @@ + * + */ + +-#include ++ ++/* raw.c ++ * ++ * The code for the Raw Access to the IP ++ * ++ */ + + #include "lwip/opt.h" + +@@ -55,10 +57,11 @@ + #include "lwip/snmp.h" + + #if LWIP_RAW ++/* The list of RAW PCBs */ + +-/** The list of RAW PCBs */ + static struct raw_pcb *raw_pcbs = NULL; + ++ + void + raw_init(void) + { +@@ -66,54 +69,42 @@ + } + + /** +- * Determine if in incoming IP packet is covered by a RAW PCB +- * and if so, pass it to a user-provided receive callback function. ++ * Determine if in incoming IP packet is covered by a RAW pcb and ++ * and process it if possible + * + * Given an incoming IP datagram (as a chain of pbufs) this function +- * finds a corresponding RAW PCB and calls the corresponding receive +- * callback function. ++ * finds a corresponding RAW PCB and + * + * @param pbuf pbuf to be demultiplexed to a RAW PCB. + * @param netif network interface on which the datagram was received. +- * @Return - 1 if the packet has been eaten by a RAW PCB receive +- * callback function. The caller MAY NOT not reference the +- * packet any longer, and MAY NOT call pbuf_free(). +- * @return - 0 if packet is not eaten (pbuf is still referenced by the +- * caller). ++ * @return 0 if packet is not eated (pbuf needs to be freed then) ++ * or 1 if the packet has been eaten (pbuf needs not to be freed ++ * then) + * + */ +-u8_t ++int + raw_input(struct pbuf *p, struct netif *inp) + { + struct raw_pcb *pcb; + struct ip_hdr *iphdr; +- s16_t proto; +- u8_t eaten = 0; ++ int proto; ++ int rc = 0; + + iphdr = p->payload; + proto = IPH_PROTO(iphdr); + +- pcb = raw_pcbs; +- /* loop through all raw pcbs until the packet is eaten by one */ +- /* this allows multiple pcbs to match against the packet by design */ +- while ((eaten == 0) && (pcb != NULL)) { ++ for(pcb = raw_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->protocol == proto) { +- /* receive callback function available? */ +- if (pcb->recv != NULL) { +- /* the receive callback function did not eat the packet? */ +- if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) +- { +- /* receive function ate the packet */ +- p = NULL; +- eaten = 1; +- } ++ if (pcb->recv) { ++ if (!pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src))) ++ return 0; + } +- /* no receive callback function was set for this raw PCB */ +- /* drop the packet */ ++ pbuf_free(p); ++ rc = 1; ++ break; + } +- pcb = pcb->next; + } +- return eaten; ++ return rc; + } + + /** +@@ -125,7 +116,7 @@ + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. +- * - ERR_USE. The specified IP address is already bound to by ++ * - ERR_USE. The specified ipaddr is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() +@@ -139,7 +130,7 @@ + + /** + * Connect an RAW PCB. This function is required by upper layers +- * of lwip. Using the raw api you could use raw_sendto() instead ++ * of lwip. Using the raw api you could use raw_send_to() instead + * + * This will associate the RAW PCB with the remote address. + * +@@ -148,7 +139,7 @@ + * + * @return lwIP error code + * +- * @see raw_disconnect() and raw_sendto() ++ * @see raw_disconnect() and raw_send_to() + */ + err_t + raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) +@@ -159,21 +150,14 @@ + + + /** +- * Set the callback function for received packets that match the +- * raw PCB's protocol and binding. +- * +- * The callback function MUST either +- * - eat the packet by calling pbuf_free() and returning non-zero. The +- * packet will not be passed to other raw PCBs or other protocol layers. +- * - not free the packet, and return zero. The packet will be matched +- * against further PCBs and/or forwarded to another protocol layers. +- * +- * @return non-zero if the packet was free()d, zero if the packet remains +- * available for others. ++ * Set the callback function if a RAW packet with the pcb's protocol ++ * is received. If the callback function returns a value unequal 0 ++ * the raw packet is "eaten" and not forwarded to any other raw pcb ++ * including lwip itself + */ + void + raw_recv(struct raw_pcb *pcb, +- u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, ++ int (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, + struct ip_addr *addr), + void *recv_arg) + { +@@ -184,25 +168,25 @@ + + /** + * Send the raw IP packet to the given address. Note that actually you cannot +- * modify the IP headers (this is inconsistent with the receive callback where +- * you actually get the IP headers), you can only specify the IP payload here. +- * It requires some more changes in lwIP. (there will be a raw_send() function +- * then.) ++ * modify the IP headers (this is inconsitent with the receive callback where ++ * you actually get the IP headers), you can only specifiy the ip payload here. ++ * It requires some more changes in LWIP. (there will be a raw_send() function ++ * then) + * + * @param pcb the raw pcb which to send +- * @param p the IP payload to send +- * @param ipaddr the destination address of the IP packet ++ * @param p the ip payload to send ++ * @param ipaddr the destination address of the whole IP packet + * + */ + err_t +-raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) ++raw_send_to(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) + { + err_t err; + struct netif *netif; + struct ip_addr *src_ip; + struct pbuf *q; /* q will be sent down the stack */ + +- LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n")); ++ LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_send_to\n")); + + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_header(p, IP_HLEN)) { +@@ -210,13 +194,13 @@ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { +- LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n")); ++ LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_send_to: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* { first pbuf q points to header pbuf } */ +- LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); ++ LWIP_DEBUGF(RAW_DEBUG, ("raw_send_to: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; +@@ -224,11 +208,10 @@ + } + + if ((netif = ip_route(ipaddr)) == NULL) { +- LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); ++ LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_send_to: No route to 0x%lx\n", ipaddr->addr)); + #if RAW_STATS + /* ++lwip_stats.raw.rterr;*/ + #endif /* RAW_STATS */ +- /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } +@@ -257,14 +240,14 @@ + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send +- * @param p the IP payload to send +- * @param ipaddr the destination address of the IP packet ++ * @param p the ip payload to send ++ * @param ipaddr the destination address of the whole IP packet + * + */ + err_t + raw_send(struct raw_pcb *pcb, struct pbuf *p) + { +- return raw_sendto(pcb, p, &pcb->remote_ip); ++ return raw_send_to(pcb,p,&pcb->remote_ip); + } + + /** +@@ -283,7 +266,7 @@ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; +- /* pcb not 1st in list */ ++ /* pcb not 1st in list */ + } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { +@@ -320,6 +303,7 @@ + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } ++ + return pcb; + } + +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/stats.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/stats.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/stats.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/stats.c 2010-01-26 17:33:17.832964510 +0000 +@@ -30,7 +30,6 @@ + * + */ + +-#include + + #include "lwip/opt.h" + +@@ -53,48 +52,48 @@ + stats_display_proto(struct stats_proto *proto, char *name) + { + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); +- LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); +- LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); +- LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); +- LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); +- LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); +- LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); +- LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); +- LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); +- LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); +- LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); +- LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); +- LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); +- LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); ++ LWIP_PLATFORM_DIAG(("xmit: %d\n\t", proto->xmit)); ++ LWIP_PLATFORM_DIAG(("rexmit: %d\n\t", proto->rexmit)); ++ LWIP_PLATFORM_DIAG(("recv: %d\n\t", proto->recv)); ++ LWIP_PLATFORM_DIAG(("fw: %d\n\t", proto->fw)); ++ LWIP_PLATFORM_DIAG(("drop: %d\n\t", proto->drop)); ++ LWIP_PLATFORM_DIAG(("chkerr: %d\n\t", proto->chkerr)); ++ LWIP_PLATFORM_DIAG(("lenerr: %d\n\t", proto->lenerr)); ++ LWIP_PLATFORM_DIAG(("memerr: %d\n\t", proto->memerr)); ++ LWIP_PLATFORM_DIAG(("rterr: %d\n\t", proto->rterr)); ++ LWIP_PLATFORM_DIAG(("proterr: %d\n\t", proto->proterr)); ++ LWIP_PLATFORM_DIAG(("opterr: %d\n\t", proto->opterr)); ++ LWIP_PLATFORM_DIAG(("err: %d\n\t", proto->err)); ++ LWIP_PLATFORM_DIAG(("cachehit: %d\n", proto->cachehit)); + } + + void + stats_display_pbuf(struct stats_pbuf *pbuf) + { + LWIP_PLATFORM_DIAG(("\nPBUF\n\t")); +- LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); +- LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); +- LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); +- LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); +- LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); +- LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); ++ LWIP_PLATFORM_DIAG(("avail: %d\n\t", pbuf->avail)); ++ LWIP_PLATFORM_DIAG(("used: %d\n\t", pbuf->used)); ++ LWIP_PLATFORM_DIAG(("max: %d\n\t", pbuf->max)); ++ LWIP_PLATFORM_DIAG(("err: %d\n\t", pbuf->err)); ++ LWIP_PLATFORM_DIAG(("alloc_locked: %d\n\t", pbuf->alloc_locked)); ++ LWIP_PLATFORM_DIAG(("refresh_locked: %d\n", pbuf->refresh_locked)); + } + + void + stats_display_mem(struct stats_mem *mem, char *name) + { + LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name)); +- LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", mem->avail)); +- LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", mem->used)); +- LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", mem->max)); +- LWIP_PLATFORM_DIAG(("err: %"S16_F"\n", mem->err)); ++ LWIP_PLATFORM_DIAG(("avail: %d\n\t", mem->avail)); ++ LWIP_PLATFORM_DIAG(("used: %d\n\t", mem->used)); ++ LWIP_PLATFORM_DIAG(("max: %d\n\t", mem->max)); ++ LWIP_PLATFORM_DIAG(("err: %d\n", mem->err)); + + } + + void + stats_display(void) + { +- s16_t i; ++ int i; + char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN", + "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"}; + stats_display_proto(&lwip_stats.link, "LINK"); +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/sys.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/sys.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/sys.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/sys.c 2010-01-26 17:33:17.832964510 +0000 +@@ -39,7 +39,7 @@ + + struct sswt_cb + { +- s16_t timeflag; ++ int timeflag; + sys_sem_t *psem; + }; + +@@ -170,7 +170,7 @@ + + timeouts = sys_arch_timeouts(); + +- LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", ++ LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%lu h=%p arg=%p\n", + (void *)timeout, msecs, (void *)h, (void *)arg)); + + LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp.c 2010-01-26 17:33:17.842963135 +0000 +@@ -41,8 +41,6 @@ + * + */ + +-#include +- + #include "lwip/opt.h" + #include "lwip/def.h" + #include "lwip/mem.h" +@@ -122,18 +120,6 @@ + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + #endif /* TCP_DEBUG */ + switch (pcb->state) { +- case CLOSED: +- /* Closing a pcb in the CLOSED state might seem erroneous, +- * however, it is in this state once allocated and as yet unused +- * and the user needs some way to free it should the need arise. +- * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) +- * or for a pcb that has been used and then entered the CLOSED state +- * is erroneous, but this should never happen as the pcb has in those cases +- * been freed, and so any remaining handles are bogus. */ +- err = ERR_OK; +- memp_free(MEMP_TCP_PCB, pcb); +- pcb = NULL; +- break; + case LISTEN: + err = ERR_OK; + tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); +@@ -237,10 +223,14 @@ + tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) + { + struct tcp_pcb *cpcb; ++#if SO_REUSE ++ int reuse_port_all_set = 1; ++#endif /* SO_REUSE */ + + if (port == 0) { + port = tcp_new_port(); + } ++#if SO_REUSE == 0 + /* Check if the address already is in use. */ + for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; + cpcb != NULL; cpcb = cpcb->next) { +@@ -262,12 +252,107 @@ + } + } + } ++#else /* SO_REUSE */ ++ /* Search through list of PCB's in LISTEN state. ++ ++ If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP ++ or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to ++ the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid. ++ But no two PCB's bound to same local port and same local address is valid. ++ ++ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then ++ all PCB's must have the SOF_REUSEPORT option set. ++ ++ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that ++ address is already in use. */ ++ for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; cpcb != NULL; cpcb = cpcb->next) { ++ if(cpcb->local_port == port) { ++ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { ++ if(pcb->so_options & SOF_REUSEPORT) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT set and same address.\n")); ++ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT)); ++ } ++ else { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT not set and same address.\n")); ++ return ERR_USE; ++ } ++ } ++ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) || ++ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) { ++ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n")); ++ return ERR_USE; ++ } ++ else { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n")); ++ } ++ } ++ } ++ } ++ ++ /* Search through list of PCB's in a state in which they can accept or send data. Same decription as for ++ PCB's in state LISTEN applies to this PCB's regarding the options SOF_REUSEADDR and SOF_REUSEPORT. */ ++ for(cpcb = tcp_active_pcbs; cpcb != NULL; cpcb = cpcb->next) { ++ if(cpcb->local_port == port) { ++ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { ++ if(pcb->so_options & SOF_REUSEPORT) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT set and same address.\n")); ++ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT)); ++ } ++ else { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT not set and same address.\n")); ++ return ERR_USE; ++ } ++ } ++ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) || ++ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) { ++ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n")); ++ return ERR_USE; ++ } ++ else { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n")); ++ } ++ } ++ } ++ } ++ ++ /* Search through list of PCB's in TIME_WAIT state. If SO_REUSEADDR is set a bound combination [IP, port} ++ can be rebound. The same applies when SOF_REUSEPORT is set. ++ ++ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then ++ all PCB's must have the SOF_REUSEPORT option set. ++ ++ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that ++ address is already in use. */ ++ for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) { ++ if(cpcb->local_port == port) { ++ if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { ++ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT or SO_REUSEADDR not set and same address.\n")); ++ return ERR_USE; ++ } ++ else if(pcb->so_options & SOF_REUSEPORT) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT set and same address.\n")); ++ reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT)); ++ } ++ } ++ } ++ } ++ ++ /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then ++ {IP, port} can't be reused. */ ++ if(!reuse_port_all_set) { ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: not all sockets have SO_REUSEPORT set.\n")); ++ return ERR_USE; ++ } ++#endif /* SO_REUSE */ + + if (!ip_addr_isany(ipaddr)) { + pcb->local_ip = *ipaddr; + } + pcb->local_port = port; +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %u\n", port)); + return ERR_OK; + } + #if LWIP_CALLBACK_API +@@ -345,19 +430,9 @@ + * continue to transmit. + */ + tcp_ack(pcb); +- } +- else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) { +- /* If we can send a window update such that there is a full +- * segment available in the window, do so now. This is sort of +- * nagle-like in its goals, and tries to hit a compromise between +- * sending acks each time the window is updated, and only sending +- * window updates when a timer expires. The "threshold" used +- * above (currently TCP_WND/2) can be tuned to be more or less +- * aggressive */ +- tcp_ack_now(pcb); + } + +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %u bytes, wnd %u (%u).\n", + len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); + } + +@@ -411,7 +486,7 @@ + err_t ret; + u32_t iss; + +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %u\n", port)); + if (ipaddr != NULL) { + pcb->remote_ip = *ipaddr; + } else { +@@ -470,9 +545,7 @@ + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; +- if (pcb == NULL) { +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); +- } ++ if (pcb == NULL) LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); +@@ -493,7 +566,7 @@ + if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { + + /* Time for a retransmission. */ +- LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n", ++ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %u pcb->rto %u\n", + pcb->rtime, pcb->rto)); + + /* Double retransmission time-out unless we are trying to +@@ -501,6 +574,7 @@ + if (pcb->state != SYN_SENT) { + pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; + } ++ tcp_rexmit(pcb); + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; +@@ -508,12 +582,9 @@ + pcb->ssthresh = pcb->mss * 2; + } + pcb->cwnd = pcb->mss; +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n", ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %u ssthresh %u\n", + pcb->cwnd, pcb->ssthresh)); +- +- /* The following needs to be called AFTER cwnd is set to one mss - STJ */ +- tcp_rexmit_rto(pcb); +- } ++ } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { +@@ -527,7 +598,7 @@ + /* Check if KEEPALIVE should be sent */ + if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) { +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %u.%u.%u.%u.\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + +@@ -555,19 +626,12 @@ + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > +- TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { ++ TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + +- /* Check if this PCB has stayed too long in LAST-ACK */ +- if (pcb->state == LAST_ACK) { +- if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { +- ++pcb_remove; +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); +- } +- } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { +@@ -722,7 +786,7 @@ + if (cseg == NULL) { + return NULL; + } +- memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); ++ memcpy((char *)cseg, (const char *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; + } +@@ -766,7 +830,7 @@ + } + } + if (inactive != NULL) { +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB 0x%p (%ld)\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +@@ -788,7 +852,7 @@ + } + } + if (inactive != NULL) { +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB 0x%p (%ld)\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +@@ -1020,16 +1084,16 @@ + { + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("| %5u | %5u | (src port, dest port)\n", + ntohs(tcphdr->src), ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("| %010lu | (seq no)\n", + ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("| %010lu | (ack no)\n", + ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", ++ LWIP_DEBUGF(TCP_DEBUG, ("| %2u | |%u%u%u%u%u%u| %5u | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + TCPH_FLAGS(tcphdr) >> 5 & 1, + TCPH_FLAGS(tcphdr) >> 4 & 1, +@@ -1041,7 +1105,7 @@ + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04x | %5u | (chksum, urgp)\n", + ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + } +@@ -1122,28 +1186,28 @@ + struct tcp_pcb *pcb; + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { +- LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", ++ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { +- LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", ++ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { +- LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", ++ LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + } + +-s16_t ++int + tcp_pcbs_sane(void) + { + struct tcp_pcb *pcb; +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp_in.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp_in.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp_in.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp_in.c 2010-01-26 17:33:17.852963885 +0000 +@@ -97,6 +97,12 @@ + u8_t hdrlen; + err_t err; + ++#if SO_REUSE ++ struct tcp_pcb *pcb_temp; ++ int reuse = 0; ++ int reuse_port = 0; ++#endif /* SO_REUSE */ ++ + PERF_START; + + TCP_STATS_INC(tcp.recv); +@@ -111,7 +117,7 @@ + /* remove header from payload */ + if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { + /* drop short packets */ +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%u bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + pbuf_free(p); +@@ -130,7 +136,7 @@ + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len) != 0) { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04x\n", + inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len))); + #if TCP_DEBUG +@@ -163,8 +169,16 @@ + for an active connection. */ + prev = NULL; + ++#if SO_REUSE ++ pcb_temp = tcp_active_pcbs; + ++ again_1: ++ ++ /* Iterate through the TCP pcb list for a fully matching pcb */ ++ for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) { ++#else /* SO_REUSE */ + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { ++#endif /* SO_REUSE */ + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); +@@ -173,6 +187,32 @@ + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + ++#if SO_REUSE ++ if(pcb->so_options & SOF_REUSEPORT) { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(TCP_INPUT_DEBUG,("tcp_input: second or later PCB and SOF_REUSEPORT set.\n")); ++ } else { ++ /* First PCB with this address */ ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: first PCB and SOF_REUSEPORT set.\n")); ++ reuse = 1; ++ } ++ ++ reuse_port = 1; ++ p->ref++; ++ ++ /* We want to search on next socket after receiving */ ++ pcb_temp = pcb->next; ++ ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: reference counter on PBUF set to %i\n", p->ref)); ++ } else { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: second or later PCB but SOF_REUSEPORT not set !\n")); ++ } ++ } ++#endif /* SO_REUSE */ ++ + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ +@@ -311,15 +351,31 @@ + increase the reference counter in the pbuf. If so, the buffer + isn't actually deallocated by the call to pbuf_free(), only the + reference count is decreased. */ +- if (inseg.p != NULL) pbuf_free(inseg.p); ++ pbuf_free(inseg.p); + #if TCP_INPUT_DEBUG + #if TCP_DEBUG + tcp_debug_print_state(pcb->state); + #endif /* TCP_DEBUG */ + #endif /* TCP_INPUT_DEBUG */ ++#if SO_REUSE ++ /* First socket should receive now */ ++ if(reuse_port) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: searching next PCB.\n")); ++ reuse_port = 0; + +- } else { ++ /* We are searching connected sockets */ ++ goto again_1; ++ } ++#endif /* SO_REUSE */ + ++ } else { ++#if SO_REUSE ++ if(reuse) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: freeing PBUF with reference counter set to %i\n", p->ref)); ++ pbuf_free(p); ++ goto end; ++ } ++#endif /* SO_REUSE */ + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); +@@ -332,7 +388,9 @@ + } + pbuf_free(p); + } +- ++#if SO_REUSE ++ end: ++#endif /* SO_REUSE */ + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); + } +@@ -359,7 +417,7 @@ + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { +- LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); ++ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %u -> %u.\n", tcphdr->src, tcphdr->dest)); + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the +@@ -445,14 +503,12 @@ + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + if (ackno == pcb->snd_nxt) { +- acceptable = 1; ++ acceptable = 1; + } + } else { +- /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && +- TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { +- */ +- if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { +- acceptable = 1; ++ if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && ++ TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { ++ acceptable = 1; + } + } + +@@ -463,9 +519,9 @@ + pcb->flags &= ~TF_ACK_DELAY; + return ERR_RST; + } else { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n", + seqno, pcb->rcv_nxt)); +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } +@@ -478,12 +534,10 @@ + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %lu pcb->snd_nxt %lu unacked %lu\n", ackno, + pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); +- /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { +- pcb->snd_buf++; + pcb->rcv_nxt = seqno + 1; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; +@@ -491,7 +545,7 @@ + pcb->state = ESTABLISHED; + pcb->cwnd = pcb->mss; + --pcb->snd_queuelen; +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %u\n", (unsigned int)pcb->snd_queuelen)); + rseg = pcb->unacked; + pcb->unacked = rseg->next; + tcp_seg_free(rseg); +@@ -504,20 +558,14 @@ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + tcp_ack(pcb); + } +- /* received ACK? possibly a half-open connection */ +- else if (flags & TCP_ACK) { +- /* send a RST to bring the other side in a non-synchronized state. */ +- tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), +- tcphdr->dest, tcphdr->src); +- } + break; + case SYN_RCVD: + if (flags & TCP_ACK && + !(flags & TCP_RST)) { +- /* expected ACK number? */ +- if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { ++ if (TCP_SEQ_LT(pcb->lastack, ackno) && ++ TCP_SEQ_LEQ(ackno, pcb->snd_nxt)) { + pcb->state = ESTABLISHED; +- LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); ++ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + #if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); + #endif +@@ -534,12 +582,6 @@ + tcp_receive(pcb); + pcb->cwnd = pcb->mss; + } +- /* incorrect ACK number */ +- else { +- /* send RST */ +- tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), +- tcphdr->dest, tcphdr->src); +- } + } + break; + case CLOSE_WAIT: +@@ -556,15 +598,15 @@ + if (flags & TCP_FIN) { + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, +- ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +- tcp_ack_now(pcb); +- tcp_pcb_purge(pcb); +- TCP_RMV(&tcp_active_pcbs, pcb); +- pcb->state = TIME_WAIT; +- TCP_REG(&tcp_tw_pcbs, pcb); ++ ("TCP connection closed %d -> %d.\n", inseg.tcphdr->src, inseg.tcphdr->dest)); ++ tcp_ack_now(pcb); ++ tcp_pcb_purge(pcb); ++ TCP_RMV(&tcp_active_pcbs, pcb); ++ pcb->state = TIME_WAIT; ++ TCP_REG(&tcp_tw_pcbs, pcb); + } else { +- tcp_ack_now(pcb); +- pcb->state = CLOSING; ++ tcp_ack_now(pcb); ++ pcb->state = CLOSING; + } + } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + pcb->state = FIN_WAIT_2; +@@ -573,7 +615,7 @@ + case FIN_WAIT_2: + tcp_receive(pcb); + if (flags & TCP_FIN) { +- LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); ++ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); +@@ -584,7 +626,7 @@ + case CLOSING: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { +- LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); ++ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); +@@ -595,7 +637,7 @@ + case LAST_ACK: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { +- LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); ++ LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + pcb->state = CLOSED; + recv_flags = TF_CLOSED; + } +@@ -603,6 +645,7 @@ + default: + break; + } ++ + return ERR_OK; + } + +@@ -627,9 +670,8 @@ + #endif + struct pbuf *p; + s32_t off; +- s16_t m; ++ int m; + u32_t right_wnd_edge; +- u16_t new_tot_len; + + + if (flags & TCP_ACK) { +@@ -642,11 +684,11 @@ + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; +- LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd)); ++ LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %lu\n", pcb->snd_wnd)); + #if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != tcphdr->wnd) { +- LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", ++ LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %lu snd_max %lu ackno %lu wl1 %lu seqno %lu wl2 %lu\n", + pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } + #endif /* TCP_WND_DEBUG */ +@@ -657,50 +699,43 @@ + pcb->acked = 0; + + if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){ +- ++pcb->dupacks; +- if (pcb->dupacks >= 3 && pcb->unacked != NULL) { +- if (!(pcb->flags & TF_INFR)) { +- /* This is fast retransmit. Retransmit the first unacked segment. */ +- LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n", +- (u16_t)pcb->dupacks, pcb->lastack, +- ntohl(pcb->unacked->tcphdr->seqno))); +- tcp_rexmit(pcb); +- /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ +- /*pcb->ssthresh = LWIP_MAX((pcb->snd_max - +- pcb->lastack) / 2, +- 2 * pcb->mss);*/ +- /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */ +- if(pcb->cwnd > pcb->snd_wnd) +- pcb->ssthresh = pcb->snd_wnd / 2; +- else +- pcb->ssthresh = pcb->cwnd / 2; ++ ++pcb->dupacks; ++ if (pcb->dupacks >= 3 && pcb->unacked != NULL) { ++ if (!(pcb->flags & TF_INFR)) { ++ /* This is fast retransmit. Retransmit the first unacked segment. */ ++ LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %u (%lu), fast retransmit %lu\n", ++ (unsigned int)pcb->dupacks, pcb->lastack, ++ ntohl(pcb->unacked->tcphdr->seqno))); ++ tcp_rexmit(pcb); ++ /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ ++ pcb->ssthresh = LWIP_MAX((pcb->snd_max - ++ pcb->lastack) / 2, ++ 2 * pcb->mss); + +- pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; +- pcb->flags |= TF_INFR; +- } else { +- /* Inflate the congestion window, but not if it means that +- the value overflows. */ +- if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { +- pcb->cwnd += pcb->mss; +- } +- } +- } ++ pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; ++ pcb->flags |= TF_INFR; ++ } else { ++ /* Inflate the congestion window, but not if it means that ++ the value overflows. */ ++ if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { ++ pcb->cwnd += pcb->mss; ++ } ++ } ++ } + } else { +- LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n", +- pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); ++ LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %lu %lu\n", ++ pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); + } +- } else +- /*if (TCP_SEQ_LT(pcb->lastack, ackno) && +- TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */ +- if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){ ++ } else if (TCP_SEQ_LT(pcb->lastack, ackno) && ++ TCP_SEQ_LEQ(ackno, pcb->snd_max)) { + /* We come here when the ACK acknowledges new data. */ +- ++ + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { +- pcb->flags &= ~TF_INFR; +- pcb->cwnd = pcb->ssthresh; ++ pcb->flags &= ~TF_INFR; ++ pcb->cwnd = pcb->ssthresh; + } + + /* Reset the number of retransmissions. */ +@@ -711,7 +746,6 @@ + + /* Update the send buffer space. */ + pcb->acked = ackno - pcb->lastack; +- + pcb->snd_buf += pcb->acked; + + /* Reset the fast retransmit variables. */ +@@ -722,85 +756,86 @@ + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { +- if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { +- pcb->cwnd += pcb->mss; +- } +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); ++ if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { ++ pcb->cwnd += pcb->mss; ++ } ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %u\n", pcb->cwnd)); + } else { +- u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); +- if (new_cwnd > pcb->cwnd) { +- pcb->cwnd = new_cwnd; +- } +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); ++ u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); ++ if (new_cwnd > pcb->cwnd) { ++ pcb->cwnd = new_cwnd; ++ } ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %u\n", pcb->cwnd)); + } + } +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", +- ackno, +- pcb->unacked != NULL? +- ntohl(pcb->unacked->tcphdr->seqno): 0, +- pcb->unacked != NULL? +- ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %lu, unacked->seqno %lu:%lu\n", ++ ackno, ++ pcb->unacked != NULL? ++ ntohl(pcb->unacked->tcphdr->seqno): 0, ++ pcb->unacked != NULL? ++ ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); + + /* Remove segment from the unacknowledged list if the incoming +- ACK acknowlegdes them. */ ++ ACK acknowlegdes them. */ + while (pcb->unacked != NULL && +- TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + +- TCP_TCPLEN(pcb->unacked), ackno)) { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", +- ntohl(pcb->unacked->tcphdr->seqno), +- ntohl(pcb->unacked->tcphdr->seqno) + +- TCP_TCPLEN(pcb->unacked))); ++ TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + ++ TCP_TCPLEN(pcb->unacked), ackno)) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unacked\n", ++ ntohl(pcb->unacked->tcphdr->seqno), ++ ntohl(pcb->unacked->tcphdr->seqno) + ++ TCP_TCPLEN(pcb->unacked))); + +- next = pcb->unacked; +- pcb->unacked = pcb->unacked->next; ++ next = pcb->unacked; ++ pcb->unacked = pcb->unacked->next; + +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); +- pcb->snd_queuelen -= pbuf_clen(next->p); +- tcp_seg_free(next); ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen)); ++ pcb->snd_queuelen -= pbuf_clen(next->p); ++ tcp_seg_free(next); + +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); +- if (pcb->snd_queuelen != 0) { +- LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || +- pcb->unsent != NULL); +- } ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unacked)\n", (unsigned int)pcb->snd_queuelen)); ++ if (pcb->snd_queuelen != 0) { ++ LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || ++ pcb->unsent != NULL); ++ } + } + pcb->polltmr = 0; + } + +- /* We go through the ->unsent list to see if any of the segments +- on the list are acknowledged by the ACK. This may seem +- strange since an "unsent" segment shouldn't be acked. The +- rationale is that lwIP puts all outstanding segments on the +- ->unsent list after a retransmission, so these segments may +- in fact have been sent once. */ +- while (pcb->unsent != NULL && +- /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) && +- TCP_SEQ_LEQ(ackno, pcb->snd_max)*/ +- TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max) +- ) { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", +- ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + +- TCP_TCPLEN(pcb->unsent))); ++ /* We go through the ->unsent list to see if any of the segments ++ on the list are acknowledged by the ACK. This may seem ++ strange since an "unsent" segment shouldn't be acked. The ++ rationale is that lwIP puts all outstanding segments on the ++ ->unsent list after a retransmission, so these segments may ++ in fact have been sent once. */ ++ while (pcb->unsent != NULL && ++ TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ++ ackno) && ++ TCP_SEQ_LEQ(ackno, pcb->snd_max)) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unsent\n", ++ ntohl(pcb->unsent->tcphdr->seqno), ++ ntohl(pcb->unsent->tcphdr->seqno) + ++ TCP_TCPLEN(pcb->unsent))); + +- next = pcb->unsent; +- pcb->unsent = pcb->unsent->next; +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); +- pcb->snd_queuelen -= pbuf_clen(next->p); +- tcp_seg_free(next); +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); +- if (pcb->snd_queuelen != 0) { +- LWIP_ASSERT("tcp_receive: valid queue length", +- pcb->unacked != NULL || pcb->unsent != NULL); +- } ++ next = pcb->unsent; ++ pcb->unsent = pcb->unsent->next; ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen)); ++ pcb->snd_queuelen -= pbuf_clen(next->p); ++ tcp_seg_free(next); ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unsent)\n", (unsigned int)pcb->snd_queuelen)); ++ if (pcb->snd_queuelen != 0) { ++ LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || ++ pcb->unsent != NULL); ++ } + +- if (pcb->unsent != NULL) { +- pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); ++ if (pcb->unsent != NULL) { ++ pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); ++ } + } +- } ++ + /* End of ACK for new data processing. */ + +- LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", +- pcb->rttest, pcb->rtseq, ackno)); ++ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %u rtseq %lu ackno %lu\n", ++ pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a +@@ -808,21 +843,21 @@ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + m = tcp_ticks - pcb->rttest; + +- LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", +- m, m * TCP_SLOW_INTERVAL)); ++ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %u ticks (%u msec).\n", ++ m, m * TCP_SLOW_INTERVAL)); + + /* This is taken directly from VJs original code in his paper */ + m = m - (pcb->sa >> 3); + pcb->sa += m; + if (m < 0) { +- m = -m; ++ m = -m; + } + m = m - (pcb->sv >> 2); + pcb->sv += m; + pcb->rto = (pcb->sa >> 3) + pcb->sv; + +- LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n", +- pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); ++ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %u (%u miliseconds)\n", ++ pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); + + pcb->rttest = 0; + } +@@ -833,314 +868,290 @@ + if (tcplen > 0) { + /* This code basically does three things: + +- +) If the incoming segment contains data that is the next +- in-sequence data, this data is passed to the application. This +- might involve trimming the first edge of the data. The rcv_nxt +- variable and the advertised window are adjusted. ++ +) If the incoming segment contains data that is the next ++ in-sequence data, this data is passed to the application. This ++ might involve trimming the first edge of the data. The rcv_nxt ++ variable and the advertised window are adjusted. + +- +) If the incoming segment has data that is above the next +- sequence number expected (->rcv_nxt), the segment is placed on +- the ->ooseq queue. This is done by finding the appropriate +- place in the ->ooseq queue (which is ordered by sequence +- number) and trim the segment in both ends if needed. An +- immediate ACK is sent to indicate that we received an +- out-of-sequence segment. ++ +) If the incoming segment has data that is above the next ++ sequence number expected (->rcv_nxt), the segment is placed on ++ the ->ooseq queue. This is done by finding the appropriate ++ place in the ->ooseq queue (which is ordered by sequence ++ number) and trim the segment in both ends if needed. An ++ immediate ACK is sent to indicate that we received an ++ out-of-sequence segment. + +- +) Finally, we check if the first segment on the ->ooseq queue +- now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If +- rcv_nxt > ooseq->seqno, we must trim the first edge of the +- segment on ->ooseq before we adjust rcv_nxt. The data in the +- segments that are now on sequence are chained onto the +- incoming segment so that we only need to call the application +- once. ++ +) Finally, we check if the first segment on the ->ooseq queue ++ now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If ++ rcv_nxt > ooseq->seqno, we must trim the first edge of the ++ segment on ->ooseq before we adjust rcv_nxt. The data in the ++ segments that are now on sequence are chained onto the ++ incoming segment so that we only need to call the application ++ once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ +- /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ +- if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ +- if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){ +- /* Trimming the first edge is done by pushing the payload +- pointer in the pbuf downwards. This is somewhat tricky since +- we do not want to discard the full contents of the pbuf up to +- the new starting point of the data since we have to keep the +- TCP header which is present in the first pbuf in the chain. +- +- What is done is really quite a nasty hack: the first pbuf in +- the pbuf chain is pointed to by inseg.p. Since we need to be +- able to deallocate the whole pbuf, we cannot change this +- inseg.p pointer to point to any of the later pbufs in the +- chain. Instead, we point the ->payload pointer in the first +- pbuf to data in one of the later pbufs. We also set the +- inseg.data pointer to point to the right place. This way, the +- ->p pointer will still point to the first pbuf, but the +- ->p->payload pointer will point to data in another pbuf. +- +- After we are done with adjusting the pbuf pointers we must +- adjust the ->data pointer in the seg and the segment +- length.*/ +- +- off = pcb->rcv_nxt - seqno; +- p = inseg.p; +- if (inseg.p->len < off) { +- new_tot_len = inseg.p->tot_len - off; +- while (p->len < off) { +- off -= p->len; +- /* KJM following line changed (with addition of new_tot_len var) +- to fix bug #9076 +- inseg.p->tot_len -= p->len; */ +- p->tot_len = new_tot_len; +- p->len = 0; +- p = p->next; +- } +- pbuf_header(p, -off); +- } else { +- pbuf_header(inseg.p, -off); +- } +- /* KJM following line changed to use p->payload rather than inseg->p->payload +- to fix bug #9076 */ +- inseg.dataptr = p->payload; +- inseg.len -= pcb->rcv_nxt - seqno; +- inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; ++ if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ ++ if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) { ++ /* Trimming the first edge is done by pushing the payload ++ pointer in the pbuf downwards. This is somewhat tricky since ++ we do not want to discard the full contents of the pbuf up to ++ the new starting point of the data since we have to keep the ++ TCP header which is present in the first pbuf in the chain. ++ ++ What is done is really quite a nasty hack: the first pbuf in ++ the pbuf chain is pointed to by inseg.p. Since we need to be ++ able to deallocate the whole pbuf, we cannot change this ++ inseg.p pointer to point to any of the later pbufs in the ++ chain. Instead, we point the ->payload pointer in the first ++ pbuf to data in one of the later pbufs. We also set the ++ inseg.data pointer to point to the right place. This way, the ++ ->p pointer will still point to the first pbuf, but the ++ ->p->payload pointer will point to data in another pbuf. ++ ++ After we are done with adjusting the pbuf pointers we must ++ adjust the ->data pointer in the seg and the segment ++ length.*/ ++ off = pcb->rcv_nxt - seqno; ++ if (inseg.p->len < off) { ++ p = inseg.p; ++ while (p->len < off) { ++ off -= p->len; ++ inseg.p->tot_len -= p->len; ++ p->len = 0; ++ p = p->next; + } +- else{ +- if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ +- /* the whole segment is < rcv_nxt */ +- /* must be a duplicate of a packet that has already been correctly handled */ +- +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); +- tcp_ack_now(pcb); ++ pbuf_header(p, -off); ++ } else { ++ pbuf_header(inseg.p, -off); ++ } ++ inseg.dataptr = inseg.p->payload; ++ inseg.len -= pcb->rcv_nxt - seqno; ++ inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; ++ } ++ else{ ++ /* the whole segment is < rcv_nxt */ ++ /* must be a duplicate of a packet that has already been correctly handled */ ++ ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %lu\n", seqno)); ++ tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ +- /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && +- TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ +- if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){ ++ if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && ++ TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { + if (pcb->rcv_nxt == seqno) { +- /* The incoming segment is the next in sequence. We check if ++ /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + #if TCP_QUEUE_OOSEQ +- if (pcb->ooseq != NULL && +- TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { +- /* We have to trim the second edge of the incoming ++ if (pcb->ooseq != NULL && ++ TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { ++ /* We have to trim the second edge of the incoming + segment. */ +- inseg.len = pcb->ooseq->tcphdr->seqno - seqno; +- pbuf_realloc(inseg.p, inseg.len); +- } ++ inseg.len = pcb->ooseq->tcphdr->seqno - seqno; ++ pbuf_realloc(inseg.p, inseg.len); ++ } + #endif /* TCP_QUEUE_OOSEQ */ + +- tcplen = TCP_TCPLEN(&inseg); ++ tcplen = TCP_TCPLEN(&inseg); + +- /* First received FIN will be ACKed +1, on any successive (duplicate) +- * FINs we are already in CLOSE_WAIT and have already done +1. +- */ +- if (pcb->state != CLOSE_WAIT) { +- pcb->rcv_nxt += tcplen; +- } ++ pcb->rcv_nxt += tcplen; + +- /* Update the receiver's (our) window. */ +- if (pcb->rcv_wnd < tcplen) { +- pcb->rcv_wnd = 0; +- } else { +- pcb->rcv_wnd -= tcplen; +- } ++ /* Update the receiver's (our) window. */ ++ if (pcb->rcv_wnd < tcplen) { ++ pcb->rcv_wnd = 0; ++ } else { ++ pcb->rcv_wnd -= tcplen; ++ } + +- /* If there is data in the segment, we make preparations to +- pass this up to the application. The ->recv_data variable +- is used for holding the pbuf that goes to the +- application. The code for reassembling out-of-sequence data +- chains its data on this pbuf as well. ++ /* If there is data in the segment, we make preparations to ++ pass this up to the application. The ->recv_data variable ++ is used for holding the pbuf that goes to the ++ application. The code for reassembling out-of-sequence data ++ chains its data on this pbuf as well. + +- If the segment was a FIN, we set the TF_GOT_FIN flag that will +- be used to indicate to the application that the remote side has +- closed its end of the connection. */ +- if (inseg.p->tot_len > 0) { +- recv_data = inseg.p; +- /* Since this pbuf now is the responsibility of the +- application, we delete our reference to it so that we won't +- (mistakingly) deallocate it. */ +- inseg.p = NULL; +- } +- if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); +- recv_flags = TF_GOT_FIN; +- } ++ If the segment was a FIN, we set the TF_GOT_FIN flag that will ++ be used to indicate to the application that the remote side has ++ closed its end of the connection. */ ++ if (inseg.p->tot_len > 0) { ++ recv_data = inseg.p; ++ /* Since this pbuf now is the responsibility of the ++ application, we delete our reference to it so that we won't ++ (mistakingly) deallocate it. */ ++ inseg.p = NULL; ++ } ++ if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); ++ recv_flags = TF_GOT_FIN; ++ } + + #if TCP_QUEUE_OOSEQ +- /* We now check if we have segments on the ->ooseq queue that ++ /* We now check if we have segments on the ->ooseq queue that + is now in sequence. */ +- while (pcb->ooseq != NULL && +- pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { ++ while (pcb->ooseq != NULL && ++ pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + +- cseg = pcb->ooseq; +- seqno = pcb->ooseq->tcphdr->seqno; ++ cseg = pcb->ooseq; ++ seqno = pcb->ooseq->tcphdr->seqno; + +- pcb->rcv_nxt += TCP_TCPLEN(cseg); +- if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { +- pcb->rcv_wnd = 0; +- } else { +- pcb->rcv_wnd -= TCP_TCPLEN(cseg); +- } +- if (cseg->p->tot_len > 0) { +- /* Chain this pbuf onto the pbuf that we will pass to +- the application. */ +- if (recv_data) { ++ pcb->rcv_nxt += TCP_TCPLEN(cseg); ++ if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { ++ pcb->rcv_wnd = 0; ++ } else { ++ pcb->rcv_wnd -= TCP_TCPLEN(cseg); ++ } ++ if (cseg->p->tot_len > 0) { ++ /* Chain this pbuf onto the pbuf that we will pass to ++ the application. */ ++ if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { +- recv_data = cseg->p; +- } +- cseg->p = NULL; +- } +- if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { +- LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); +- recv_flags = TF_GOT_FIN; +- } ++ recv_data = cseg->p; ++ } ++ cseg->p = NULL; ++ } ++ if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { ++ LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); ++ recv_flags = TF_GOT_FIN; ++ } + + +- pcb->ooseq = cseg->next; +- tcp_seg_free(cseg); +- } ++ pcb->ooseq = cseg->next; ++ tcp_seg_free(cseg); ++ } + #endif /* TCP_QUEUE_OOSEQ */ + + +- /* Acknowledge the segment(s). */ +- tcp_ack(pcb); ++ /* Acknowledge the segment(s). */ ++ tcp_ack(pcb); + + } else { +- /* We get here if the incoming segment is out-of-sequence. */ +- tcp_ack_now(pcb); ++ /* We get here if the incoming segment is out-of-sequence. */ ++ tcp_ack_now(pcb); + #if TCP_QUEUE_OOSEQ +- /* We queue the segment on the ->ooseq queue. */ +- if (pcb->ooseq == NULL) { +- pcb->ooseq = tcp_seg_copy(&inseg); +- } else { +- /* If the queue is not empty, we walk through the queue and +- try to find a place where the sequence number of the +- incoming segment is between the sequence numbers of the +- previous and the next segment on the ->ooseq queue. That is +- the place where we put the incoming segment. If needed, we +- trim the second edges of the previous and the incoming +- segment so that it will fit into the sequence. ++ /* We queue the segment on the ->ooseq queue. */ ++ if (pcb->ooseq == NULL) { ++ pcb->ooseq = tcp_seg_copy(&inseg); ++ } else { ++ /* If the queue is not empty, we walk through the queue and ++ try to find a place where the sequence number of the ++ incoming segment is between the sequence numbers of the ++ previous and the next segment on the ->ooseq queue. That is ++ the place where we put the incoming segment. If needed, we ++ trim the second edges of the previous and the incoming ++ segment so that it will fit into the sequence. + +- If the incoming segment has the same sequence number as a +- segment on the ->ooseq queue, we discard the segment that +- contains less data. */ ++ If the incoming segment has the same sequence number as a ++ segment on the ->ooseq queue, we discard the segment that ++ contains less data. */ + +- prev = NULL; +- for(next = pcb->ooseq; next != NULL; next = next->next) { +- if (seqno == next->tcphdr->seqno) { +- /* The sequence number of the incoming segment is the ++ prev = NULL; ++ for(next = pcb->ooseq; next != NULL; next = next->next) { ++ if (seqno == next->tcphdr->seqno) { ++ /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ +- if (inseg.len > next->len) { +- /* The incoming segment is larger than the old ++ if (inseg.len > next->len) { ++ /* The incoming segment is larger than the old + segment. We replace the old segment with the new + one. */ +- cseg = tcp_seg_copy(&inseg); +- if (cseg != NULL) { +- cseg->next = next->next; +- if (prev != NULL) { +- prev->next = cseg; +- } else { +- pcb->ooseq = cseg; +- } +- } +- break; +- } else { +- /* Either the lenghts are the same or the incoming ++ cseg = tcp_seg_copy(&inseg); ++ if (cseg != NULL) { ++ cseg->next = next->next; ++ if (prev != NULL) { ++ prev->next = cseg; ++ } else { ++ pcb->ooseq = cseg; ++ } ++ } ++ break; ++ } else { ++ /* Either the lenghts are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ +- break; +- } +- } else { +- if (prev == NULL) { +- if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { +- /* The sequence number of the incoming segment is lower +- than the sequence number of the first segment on the +- queue. We put the incoming segment first on the +- queue. */ ++ break; ++ } ++ } else { ++ if (prev == NULL) { ++ if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { ++ /* The sequence number of the incoming segment is lower ++ than the sequence number of the first segment on the ++ queue. We put the incoming segment first on the ++ queue. */ + +- if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { +- /* We need to trim the incoming segment. */ +- inseg.len = next->tcphdr->seqno - seqno; +- pbuf_realloc(inseg.p, inseg.len); +- } +- cseg = tcp_seg_copy(&inseg); +- if (cseg != NULL) { +- cseg->next = next; +- pcb->ooseq = cseg; +- } +- break; +- } +- } else +- /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && +- TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ +- if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){ +- /* The sequence number of the incoming segment is in ++ if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { ++ /* We need to trim the incoming segment. */ ++ inseg.len = next->tcphdr->seqno - seqno; ++ pbuf_realloc(inseg.p, inseg.len); ++ } ++ cseg = tcp_seg_copy(&inseg); ++ if (cseg != NULL) { ++ cseg->next = next; ++ pcb->ooseq = cseg; ++ } ++ break; ++ } ++ } else if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && ++ TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { ++ /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim and insert the + incoming segment and trim the previous segment, if + needed. */ +- if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { +- /* We need to trim the incoming segment. */ +- inseg.len = next->tcphdr->seqno - seqno; +- pbuf_realloc(inseg.p, inseg.len); +- } ++ if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { ++ /* We need to trim the incoming segment. */ ++ inseg.len = next->tcphdr->seqno - seqno; ++ pbuf_realloc(inseg.p, inseg.len); ++ } + +- cseg = tcp_seg_copy(&inseg); +- if (cseg != NULL) { +- cseg->next = next; +- prev->next = cseg; +- if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { +- /* We need to trim the prev segment. */ +- prev->len = seqno - prev->tcphdr->seqno; +- pbuf_realloc(prev->p, prev->len); +- } +- } +- break; +- } +- /* If the "next" segment is the last segment on the ++ cseg = tcp_seg_copy(&inseg); ++ if (cseg != NULL) { ++ cseg->next = next; ++ prev->next = cseg; ++ if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { ++ /* We need to trim the prev segment. */ ++ prev->len = seqno - prev->tcphdr->seqno; ++ pbuf_realloc(prev->p, prev->len); ++ } ++ } ++ break; ++ } ++ /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ +- if (next->next == NULL && +- TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { +- next->next = tcp_seg_copy(&inseg); +- if (next->next != NULL) { +- if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { +- /* We need to trim the last segment. */ +- next->len = seqno - next->tcphdr->seqno; +- pbuf_realloc(next->p, next->len); +- } +- } +- break; +- } +- } +- prev = next; +- } ++ if (next->next == NULL && ++ TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { ++ next->next = tcp_seg_copy(&inseg); ++ if (next->next != NULL) { ++ if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { ++ /* We need to trim the last segment. */ ++ next->len = seqno - next->tcphdr->seqno; ++ pbuf_realloc(next->p, next->len); ++ } ++ } ++ break; + } ++ } ++ prev = next; ++ } ++ } + #endif /* TCP_QUEUE_OOSEQ */ + + } +- } else { +- /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || +- TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ +- if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ +- tcp_ack_now(pcb); +- } + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ +- /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || +- TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ +- if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ ++ if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || ++ TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { + tcp_ack_now(pcb); + } + } +@@ -1174,7 +1185,7 @@ + ++c; + /* NOP option. */ + } else if (opt == 0x02 && +- opts[c + 1] == 0x04) { ++ opts[c + 1] == 0x04) { + /* An MSS option with the right option length. */ + mss = (opts[c + 2] << 8) | opts[c + 3]; + pcb->mss = mss > TCP_MSS? TCP_MSS: mss; +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp_out.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp_out.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/tcp_out.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/tcp_out.c 2010-01-26 17:33:17.862963761 +0000 +@@ -39,17 +39,19 @@ + * + */ + +-#include +- + #include "lwip/def.h" + #include "lwip/opt.h" ++ + #include "lwip/mem.h" + #include "lwip/memp.h" + #include "lwip/sys.h" ++ + #include "lwip/ip_addr.h" + #include "lwip/netif.h" ++ + #include "lwip/inet.h" + #include "lwip/tcp.h" ++ + #include "lwip/stats.h" + + #if LWIP_TCP +@@ -60,33 +62,27 @@ + err_t + tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) + { +- /* no data, no length, flags, copy=1, no optdata, no optdatalen */ + return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0); ++ + } + +-/** +- * Write data for sending (but does not send it immediately). +- * +- * It waits in the expectation of more data being sent soon (as +- * it can send them more efficiently by combining them together). +- * To prompt the system to send data now, call tcp_output() after +- * calling tcp_write(). +- * +- * @arg pcb Protocol control block of the TCP connection to enqueue data for. +- * +- * @see tcp_write() ++/* ++ * NB. tcp_write() enqueues data for sending, but does not send it ++ * straight away. It waits in the expectation of more data being sent ++ * soon (as it can send them more efficiently by combining them ++ * together). To prompt the system to send data now, call ++ * tcp_output() after calling tcp_write(). + */ + + err_t + tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy) + { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb, +- arg, len, (u16_t)copy)); +- /* connection is in valid state for data transmission? */ +- if (pcb->state == ESTABLISHED || +- pcb->state == CLOSE_WAIT || +- pcb->state == SYN_SENT || +- pcb->state == SYN_RCVD) { ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%u, copy=%d)\n", (void *)pcb, ++ arg, len, (unsigned int)copy)); ++ if (pcb->state == SYN_SENT || ++ pcb->state == SYN_RCVD || ++ pcb->state == ESTABLISHED || ++ pcb->state == CLOSE_WAIT) { + if (len > 0) { + return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0); + } +@@ -97,24 +93,10 @@ + } + } + +-/** +- * Enqueue either data or TCP options (but not both) for tranmission +- * +- * +- * +- * @arg pcb Protocol control block for the TCP connection to enqueue data for. +- * @arg arg Pointer to the data to be enqueued for sending. +- * @arg len Data length in bytes +- * @arg flags +- * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be +- * referenced. +- * @arg optdata +- * @arg optlen +- */ + err_t + tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, +- u8_t flags, u8_t copy, +- u8_t *optdata, u8_t optlen) ++ u8_t flags, u8_t copy, ++ u8_t *optdata, u8_t optlen) + { + struct pbuf *p; + struct tcp_seg *seg, *useg, *queue; +@@ -123,46 +105,41 @@ + void *ptr; + u8_t queuelen; + +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n", +- (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy)); +- LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)", +- len == 0 || optlen == 0); +- LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)", +- arg == NULL || optdata == NULL); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%u, flags=%x, copy=%u)\n", ++ (void *)pcb, arg, len, (unsigned int)flags, (unsigned int)copy)); ++ left = len; ++ ptr = arg; + /* fail on too much data */ + if (len > pcb->snd_buf) { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%u > snd_buf=%u)\n", len, pcb->snd_buf)); + return ERR_MEM; + } +- left = len; +- ptr = arg; + + /* seqno will be the sequence number of the first segment enqueued + * by the call to this function. */ + seqno = pcb->snd_lbb; + +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); ++ queue = NULL; ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %u\n", (unsigned int)pcb->snd_queuelen)); + +- /* If total number of pbufs on the unsent/unacked queues exceeds the +- * configured maximum, return an error */ ++ /* Check if the queue length exceeds the configured maximum queue ++ * length. If so, we return an error. */ + queuelen = pcb->snd_queuelen; + if (queuelen >= TCP_SND_QUEUELEN) { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); +- TCP_STATS_INC(tcp.memerr); +- return ERR_MEM; ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %u (max %u)\n", queuelen, TCP_SND_QUEUELEN)); ++ goto memerr; + } +- if (queuelen != 0) { +- LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", +- pcb->unacked != NULL || pcb->unsent != NULL); +- } else { +- LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", +- pcb->unacked == NULL && pcb->unsent == NULL); ++ ++ if (pcb->snd_queuelen != 0) { ++ LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || ++ pcb->unsent != NULL); + } + ++ seg = useg = NULL; ++ seglen = 0; ++ + /* First, break up the data into segments and tuck them together in + * the local "queue" variable. */ +- useg = queue = seg = NULL; +- seglen = 0; + while (queue == NULL || left > 0) { + + /* The segment length should be the MSS if the data to be enqueued +@@ -178,25 +155,20 @@ + seg->next = NULL; + seg->p = NULL; + +- /* first segment of to-be-queued data? */ + if (queue == NULL) { +- queue = seg; ++ useg = queue = seg; + } +- /* subsequent segments of to-be-queued data */ + else { +- /* Attach the segment to the end of the queued segments */ ++ /* Attach the segment to the end of the queued segments. */ + LWIP_ASSERT("useg != NULL", useg != NULL); + useg->next = seg; ++ useg = seg; + } +- /* remember last segment of to-be-queued data for next iteration */ +- useg = seg; + + /* If copy is set, memory should be allocated + * and data copied into pbuf, otherwise data comes from + * ROM or other static memory, and need not be copied. If + * optdata is != NULL, we have options instead of data. */ +- +- /* options? */ + if (optdata != NULL) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + goto memerr; +@@ -204,10 +176,9 @@ + ++queuelen; + seg->dataptr = seg->p->payload; + } +- /* copy from volatile memory? */ + else if (copy) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %u\n", seglen)); + goto memerr; + } + ++queuelen; +@@ -218,7 +189,8 @@ + } + /* do not copy data */ + else { +- /* First, allocate a pbuf for holding the data. ++ ++ /* first, allocate a pbuf for holding the data. + * since the referenced data is available at least until it is sent out on the + * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM + * instead of PBUF_REF here. +@@ -228,7 +200,6 @@ + goto memerr; + } + ++queuelen; +- /* reference the non-volatile payload data */ + p->payload = ptr; + seg->dataptr = ptr; + +@@ -243,22 +214,28 @@ + ++queuelen; + + /* Concatenate the headers and data pbufs together. */ +- pbuf_cat(seg->p/*header*/, p/*data*/); ++ pbuf_cat(seg->p, p); + p = NULL; + } + + /* Now that there are more segments queued, we check again if the + length of the queue exceeds the configured maximum. */ + if (queuelen > TCP_SND_QUEUELEN) { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %u (%u)\n", queuelen, TCP_SND_QUEUELEN)); + goto memerr; + } + + seg->len = seglen; +- +- /* build TCP header */ ++#if 0 /* Was commented out. TODO: can someone say why this is here? */ ++ if ((flags & TCP_SYN) || (flags & TCP_FIN)) { ++ ++seg->len; ++ } ++#endif ++ /* Build TCP header. */ + if (pbuf_header(seg->p, TCP_HLEN)) { ++ + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n")); ++ + TCP_STATS_INC(tcp.err); + goto memerr; + } +@@ -281,16 +258,17 @@ + segments such as SYN|ACK. */ + memcpy(seg->dataptr, optdata, optlen); + } +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %lu:%lu (0x%x)\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), +- (u16_t)flags)); ++ flags)); + + left -= seglen; + seqno += seglen; +- ptr = (void *)((u8_t *)ptr + seglen); ++ ptr = (void *)((char *)ptr + seglen); + } + ++ + /* Now that the data to be enqueued has been broken up into TCP + segments in the queue variable, we add them to the end of the + pcb->unsent queue. */ +@@ -300,7 +278,6 @@ + else { + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + } +- /* { useg is last segment on the unsent queue, NULL if list is empty } */ + + /* If there is room in the last pbuf on the unsent queue, + chain the first pbuf on the queue together with that. */ +@@ -308,27 +285,24 @@ + TCP_TCPLEN(useg) != 0 && + !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && + !(flags & (TCP_SYN | TCP_FIN)) && +- /* fit within max seg size */ + useg->len + queue->len <= pcb->mss) { +- /* Remove TCP header from first segment of our to-be-queued list */ ++ /* Remove TCP header from first segment. */ + pbuf_header(queue->p, -TCP_HLEN); + pbuf_cat(useg->p, queue->p); + useg->len += queue->len; + useg->next = queue->next; + +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining, new len %u\n", useg->len)); + if (seg == queue) { + seg = NULL; + } + memp_free(MEMP_TCP_SEG, queue); + } + else { +- /* empty list */ + if (useg == NULL) { +- /* initialize list with this segment */ + pcb->unsent = queue; ++ + } +- /* enqueue segment */ + else { + useg->next = queue; + } +@@ -337,15 +311,13 @@ + ++len; + } + pcb->snd_lbb += len; +- + pcb->snd_buf -= len; +- +- /* update number of segments on the queues */ + pcb->snd_queuelen = queuelen; +- LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); ++ LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %d (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { +- LWIP_ASSERT("tcp_enqueue: valid queue length", +- pcb->unacked != NULL || pcb->unsent != NULL); ++ LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || ++ pcb->unsent != NULL); ++ + } + + /* Set the PSH flag in the last segment that we enqueued, but only +@@ -355,7 +327,7 @@ + } + + return ERR_OK; +-memerr: ++ memerr: + TCP_STATS_INC(tcp.memerr); + + if (queue != NULL) { +@@ -364,8 +336,9 @@ + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); ++ + } +- LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); ++ LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %d (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; + } + +@@ -378,7 +351,7 @@ + struct tcp_seg *seg, *useg; + u32_t wnd; + #if TCP_CWND_DEBUG +- s16_t i = 0; ++ int i = 0; + #endif /* TCP_CWND_DEBUG */ + + /* First, check if we are invoked by the TCP input processing +@@ -391,6 +364,7 @@ + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + ++ + seg = pcb->unsent; + + /* useg should point to last segment on unacked queue */ +@@ -398,24 +372,24 @@ + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } ++ + +- /* If the TF_ACK_NOW flag is set and no data will be sent (either +- * because the ->unsent queue is empty or because the window does +- * not allow it), construct an empty ACK segment and send it. +- * +- * If data is to be sent, we will just piggyback the ACK (see below). +- */ ++ /* If the TF_ACK_NOW flag is set, we check if there is data that is ++ to be sent. If data is to be sent out, we'll just piggyback our ++ acknowledgement with the outgoing segment. If no data will be ++ sent (either because the ->unsent queue is empty or because the ++ window doesn't allow it) we'll have to construct an empty ACK ++ segment and send it. */ + if (pcb->flags & TF_ACK_NOW && + (seg == NULL || + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { ++ pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); +- /* remove ACK flags from the PCB, as we send an empty ACK now */ +- pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %lu\n", pcb->rcv_nxt)); + + tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); +@@ -432,6 +406,7 @@ + tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), + IP_PROTO_TCP, p->tot_len); + #endif ++ + ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); + pbuf_free(p); +@@ -441,26 +416,26 @@ + + #if TCP_OUTPUT_DEBUG + if (seg == NULL) { +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent)); ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", pcb->unsent)); + } + #endif /* TCP_OUTPUT_DEBUG */ + #if TCP_CWND_DEBUG + if (seg == NULL) { +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n", ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, seg == NULL, ack %lu\n", + pcb->snd_wnd, pcb->cwnd, wnd, + pcb->lastack)); + } else { +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + ntohl(seg->tcphdr->seqno), pcb->lastack)); + } + #endif /* TCP_CWND_DEBUG */ +- /* data available and window allows it to be sent? */ ++ + while (seg != NULL && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + #if TCP_CWND_DEBUG +- LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", ++ LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu, i%d\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, +@@ -483,26 +458,13 @@ + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; +- /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; +- /* unacked list is not empty? */ + } else { +- /* In the case of fast retransmit, the packet should not go to the tail +- * of the unacked queue, but rather at the head. We need to check for +- * this case. -STJ Jul 27, 2004 */ +- if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ +- /* add segment to head of unacked list */ +- seg->next = pcb->unacked; +- pcb->unacked = seg; +- } else { +- /* add segment to tail of unacked list */ +- useg->next = seg; +- useg = useg->next; +- } ++ useg->next = seg; ++ useg = useg->next; + } +- /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } +@@ -511,9 +473,6 @@ + return ERR_OK; + } + +-/** +- * Actually send a TCP segment over IP +- */ + static void + tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) + { +@@ -548,9 +507,9 @@ + pcb->rttest = tcp_ticks; + pcb->rtseq = ntohl(seg->tcphdr->seqno); + +- LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); ++ LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %lu\n", pcb->rtseq)); + } +- LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", ++ LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %lu:%lu\n", + htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + + seg->len)); + +@@ -606,12 +565,11 @@ + /* Send output with hardcoded TTL since we have no access to the pcb */ + ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); + pbuf_free(p); +- LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); ++ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %lu ackno %lu.\n", seqno, ackno)); + } + +-/* requeue all unacked segments for retransmission */ + void +-tcp_rexmit_rto(struct tcp_pcb *pcb) ++tcp_rexmit(struct tcp_pcb *pcb) + { + struct tcp_seg *seg; + +@@ -619,40 +577,14 @@ + return; + } + +- /* Move all unacked segments to the head of the unsent queue */ ++ /* Move all unacked segments to the unsent queue. */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); +- /* concatenate unsent queue after unacked queue */ ++ + seg->next = pcb->unsent; +- /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; +- /* unacked queue is now empty */ +- pcb->unacked = NULL; + +- pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); +- /* increment number of retransmissions */ +- ++pcb->nrtx; +- +- /* Don't take any RTT measurements after retransmitting. */ +- pcb->rttest = 0; +- +- /* Do the actual retransmission */ +- tcp_output(pcb); +-} +- +-void +-tcp_rexmit(struct tcp_pcb *pcb) +-{ +- struct tcp_seg *seg; +- +- if (pcb->unacked == NULL) { +- return; +- } ++ pcb->unacked = NULL; + +- /* Move the first unacked segment to the unsent queue */ +- seg = pcb->unacked->next; +- pcb->unacked->next = pcb->unsent; +- pcb->unsent = pcb->unacked; +- pcb->unacked = seg; + + pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); + +@@ -666,18 +598,17 @@ + + } + +- + void + tcp_keepalive(struct tcp_pcb *pcb) + { + struct pbuf *p; + struct tcp_hdr *tcphdr; + +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %u.%u.%u.%u\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + +- LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); ++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %ld pcb->tmr %ld pcb->keep_cnt %ld\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); + + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + +@@ -706,7 +637,7 @@ + + pbuf_free(p); + +- LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); ++ LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %lu ackno %lu.\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); + } + + #endif /* LWIP_TCP */ +diff -urNad redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/udp.c redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/udp.c +--- redboot-imx-200952~/packages/net/lwip_tcpip/current/src/core/udp.c 2006-03-29 10:33:28.000000000 +0000 ++++ redboot-imx-200952/packages/net/lwip_tcpip/current/src/core/udp.c 2010-01-26 17:33:17.872964761 +0000 +@@ -42,8 +42,6 @@ + * + */ + +-#include +- + #include "lwip/opt.h" + + #include "lwip/def.h" +@@ -66,6 +64,7 @@ + + static struct udp_pcb *pcb_cache = NULL; + ++ + void + udp_init(void) + { +@@ -87,11 +86,16 @@ + { + struct udp_hdr *udphdr; + struct udp_pcb *pcb; +- struct udp_pcb *uncon_pcb; + struct ip_hdr *iphdr; + u16_t src, dest; +- u8_t local_match; + ++#if SO_REUSE ++ struct udp_pcb *pcb_temp; ++ int reuse = 0; ++ int reuse_port_1 = 0; ++ int reuse_port_2 = 0; ++#endif /* SO_REUSE */ ++ + PERF_START; + + UDP_STATS_INC(udp.recv); +@@ -100,7 +104,7 @@ + + if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) { + /* drop short packets */ +- LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); +@@ -110,7 +114,7 @@ + + udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN); + +- LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %u\n", p->tot_len)); + + src = ntohs(udphdr->src); + dest = ntohs(udphdr->dest); +@@ -118,46 +122,117 @@ + udp_debug_print(udphdr); + + /* print the UDP source and destination */ +- LWIP_DEBUGF(UDP_DEBUG, ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", ++ LWIP_DEBUGF(UDP_DEBUG, ("udp (%u.%u.%u.%u, %u) <-- (%u.%u.%u.%u, %u)\n", + ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), + ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); + +- local_match = 0; +- uncon_pcb = NULL; +- /* Iterate through the UDP pcb list for a matching pcb */ +- for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { ++#if SO_REUSE ++ pcb_temp = udp_pcbs; ++ ++ again_1: ++ ++ /* Iterate through the UDP pcb list for a fully matching pcb */ ++ for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) { ++#else /* SO_REUSE */ ++ /* Iterate through the UDP pcb list for a fully matching pcb */ ++ for(pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { ++#endif /* SO_REUSE */ + /* print the PCB local and remote address */ +- LWIP_DEBUGF(UDP_DEBUG, ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", ++ LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n", + ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), + ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); + +- /* compare PCB local addr+port to UDP destination addr+port */ +- if ((pcb->local_port == dest) && ++ /* PCB remote port matches UDP source port? */ ++ if ((pcb->remote_port == src) && ++ /* PCB local port matches UDP destination port? */ ++ (pcb->local_port == dest) && ++ /* accepting from any remote (source) IP address? or... */ ++ (ip_addr_isany(&pcb->remote_ip) || ++ /* PCB remote IP address matches UDP source IP address? */ ++ ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src))) && ++ /* accepting on any local (netif) IP address? or... */ + (ip_addr_isany(&pcb->local_ip) || ++ /* PCB local IP address matches UDP destination IP address? */ + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) { +- local_match = 1; +- if ((uncon_pcb == NULL) && +- ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { +- /* the first unconnected matching PCB */ +- uncon_pcb = pcb; +- } +- } +- /* compare PCB remote addr+port to UDP source addr+port */ +- if ((local_match != 0) && +- (pcb->remote_port == src) && +- (ip_addr_isany(&pcb->remote_ip) || +- ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { +- /* the first fully matching PCB */ ++#if SO_REUSE ++ if(pcb->so_options & SOF_REUSEPORT) { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n")); ++ } else { ++ /* First PCB with this address */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n")); ++ reuse = 1; ++ } ++ ++ reuse_port_1 = 1; ++ p->ref++; ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref)); ++ } else { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n")); ++ } ++ } ++#endif /* SO_REUSE */ + break; + } + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { +- pcb = uncon_pcb; ++ /* Iterate through the UDP PCB list for a pcb that matches ++ the local address. */ ++ ++#if SO_REUSE ++ pcb_temp = udp_pcbs; ++ ++ again_2: ++ ++ for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) { ++#else /* SO_REUSE */ ++ for(pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { ++#endif /* SO_REUSE */ ++ LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n", ++ ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), ++ ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, ++ ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), ++ ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); ++ /* unconnected? */ ++ if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) && ++ /* destination port matches? */ ++ (pcb->local_port == dest) && ++ /* not bound to a specific (local) interface address? or... */ ++ (ip_addr_isany(&pcb->local_ip) || ++ /* ...matching interface address? */ ++ ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) { ++#if SO_REUSE ++ if(pcb->so_options & SOF_REUSEPORT) { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n")); ++ } else { ++ /* First PCB with this address */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n")); ++ reuse = 1; ++ } ++ ++ reuse_port_2 = 1; ++ p->ref++; ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref)); ++ } else { ++ if(reuse) { ++ /* We processed one PCB already */ ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n")); ++ } ++ } ++#endif /* SO_REUSE */ ++ break; ++ } ++ } + } + + /* Check checksum if this is a match or if it was directed at us. */ +@@ -203,12 +278,34 @@ + pbuf_header(p, -UDP_HLEN); + if (pcb != NULL) { + snmp_inc_udpindatagrams(); +- /* callback */ +- if (pcb->recv != NULL) +- { +- pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); +- } ++ pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); ++#if SO_REUSE ++ /* First socket should receive now */ ++ if(reuse_port_1 || reuse_port_2) { ++ /* We want to search on next socket after receiving */ ++ pcb_temp = pcb->next; ++ ++ if(reuse_port_1) { ++ /* We are searching connected sockets */ ++ reuse_port_1 = 0; ++ reuse_port_2 = 0; ++ goto again_1; + } else { ++ /* We are searching unconnected sockets */ ++ reuse_port_1 = 0; ++ reuse_port_2 = 0; ++ goto again_2; ++ } ++ } ++#endif /* SO_REUSE */ ++ } else { ++#if SO_REUSE ++ if(reuse) { ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_input: freeing PBUF with reference counter set to %i\n", p->ref)); ++ pbuf_free(p); ++ goto end; ++ } ++#endif /* SO_REUSE */ + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n")); + + /* No match was found, send ICMP destination port unreachable unless +@@ -257,10 +354,9 @@ + struct ip_addr *dst_ip, u16_t dst_port) + { + err_t err; +- /* temporary space for current PCB remote address */ + struct ip_addr pcb_remote_ip; + u16_t pcb_remote_port; +- /* remember current remote peer address of PCB */ ++ /* remember remote peer address of PCB */ + pcb_remote_ip.addr = pcb->remote_ip.addr; + pcb_remote_port = pcb->remote_port; + /* copy packet destination address to PCB remote peer address */ +@@ -268,7 +364,7 @@ + pcb->remote_port = dst_port; + /* send to the packet destination address */ + err = udp_send(pcb, p); +- /* restore PCB remote peer address */ ++ /* reset PCB remote peer address */ + pcb->remote_ip.addr = pcb_remote_ip.addr; + pcb->remote_port = pcb_remote_port; + return err; +@@ -307,14 +403,6 @@ + return err; + } + } +- /* find the outgoing network interface for this packet */ +- netif = ip_route(&(pcb->remote_ip)); +- /* no outgoing network interface could be found? */ +- if (netif == NULL) { +- LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr)); +- UDP_STATS_INC(udp.rterr); +- return ERR_RTE; +- } + + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_header(p, UDP_HLEN)) { +@@ -342,6 +430,12 @@ + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + ++ /* find the outgoing network interface for this packet */ ++ if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { ++ LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%lx\n", pcb->remote_ip.addr)); ++ UDP_STATS_INC(udp.rterr); ++ return ERR_RTE; ++ } + /* PCB local address is IP_ANY_ADDR? */ + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ +@@ -351,11 +445,11 @@ + src_ip = &(pcb->local_ip); + } + +- LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %u\n", q->tot_len)); + + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { +- LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %u\n", q->tot_len)); + /* set UDP message length in UDP header */ + udphdr->len = htons(pcb->chksum_len); + /* calculate checksum */ +@@ -372,7 +466,7 @@ + err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); + /* UDP */ + } else { +- LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %u\n", q->tot_len)); + udphdr->len = htons(q->tot_len); + /* calculate checksum */ + #if CHECKSUM_GEN_UDP +@@ -384,7 +478,7 @@ + #else + udphdr->chksum = 0x0000; + #endif +- LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04x\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); + /* output to IP */ + err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); +@@ -423,10 +517,12 @@ + { + struct udp_pcb *ipcb; + u8_t rebind; +- ++#if SO_REUSE ++ int reuse_port_all_set = 1; ++#endif /* SO_REUSE */ + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG, ipaddr); +- LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port)); ++ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %u)\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ +@@ -439,6 +535,7 @@ + rebind = 1; + } + ++#if SO_REUSE == 0 + /* this code does not allow upper layer to share a UDP port for + listening to broadcast or multicast traffic (See SO_REUSE_ADDR and + SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR +@@ -451,13 +548,56 @@ + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { + /* other PCB already binds to this local IP and port */ +- LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %u already bound by another pcb\n", port)); + return ERR_USE; + } + #endif + ++#else /* SO_REUSE */ ++ /* Search through list of PCB's. ++ ++ If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP ++ or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to ++ the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid. ++ But no two PCB's bound to same local port and same local address is valid. ++ ++ If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then ++ all PCB's must have the SOF_REUSEPORT option set. ++ ++ When the two options aren't set and specified port is already bound, ERR_USE is returned saying that ++ address is already in use. */ ++ else if (ipcb->local_port == port) { ++ if(ip_addr_cmp(&(ipcb->local_ip), ipaddr)) { ++ if(pcb->so_options & SOF_REUSEPORT) { ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT set and same address.\n")); ++ reuse_port_all_set = (reuse_port_all_set && (ipcb->so_options & SOF_REUSEPORT)); ++ } ++ else { ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT not set and same address.\n")); ++ return ERR_USE; ++ } ++ } ++ else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(ipcb->local_ip))) || ++ (!ip_addr_isany(ipaddr) && ip_addr_isany(&(ipcb->local_ip)))) { ++ if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) { ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n")); ++ return ERR_USE; ++ } ++ } ++ } ++#endif /* SO_REUSE */ ++ + } + ++#if SO_REUSE ++ /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then ++ {IP, port} can't be reused. */ ++ if(!reuse_port_all_set) { ++ LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: not all sockets have SO_REUSEPORT set.\n")); ++ return ERR_USE; ++ } ++#endif /* SO_REUSE */ ++ + ip_addr_set(&pcb->local_ip, ipaddr); + /* no port specified? */ + if (port == 0) { +@@ -487,11 +627,11 @@ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } +- LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", +- (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), +- (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), +- (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), +- (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); ++ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %u.%u.%u.%u, port %u\n", ++ (unsigned int)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), ++ (unsigned int)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), ++ (unsigned int)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); + return ERR_OK; + } + /** +@@ -540,11 +680,11 @@ + pcb->local_ip.addr = 0; + } + #endif +- LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", +- (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), +- (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), +- (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), +- (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); ++ LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %u.%u.%u.%u, port %u\n", ++ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), ++ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), ++ (unsigned int)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), ++ (unsigned int)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { +@@ -629,17 +769,18 @@ + } + + #if UDP_DEBUG +-void ++int + udp_debug_print(struct udp_hdr *udphdr) + { + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", ++ LWIP_DEBUGF(UDP_DEBUG, ("| %5u | %5u | (src port, dest port)\n", + ntohs(udphdr->src), ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +- LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", ++ LWIP_DEBUGF(UDP_DEBUG, ("| %5u | 0x%04x | (len, chksum)\n", + ntohs(udphdr->len), ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); ++ return 0; + } + #endif /* UDP_DEBUG */ + +diff -urNad redboot-imx-200952~/packages/redboot/current/cdl/redboot.cdl redboot-imx-200952/packages/redboot/current/cdl/redboot.cdl +--- redboot-imx-200952~/packages/redboot/current/cdl/redboot.cdl 2007-06-04 20:30:59.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/cdl/redboot.cdl 2010-01-26 17:33:18.012958885 +0000 +@@ -208,10 +208,11 @@ + than five bytes are available initially so this is the + minimum." + } ++ + cdl_option CYGPRI_REDBOOT_ZLIB_FLASH { + display "Support compression of Flash images" + active_if CYGPKG_REDBOOT_FLASH +- active_if !CYGSEM_IO_FLASH_READ_INDIRECT ++ active_if { (!CYGSEM_IO_FLASH_READ_INDIRECT) || CYGPRI_REDBOOT_ZLIB_FLASH_FORCE } + calculated 1 + description " + This CDL indicates whether flash images can +@@ -226,6 +227,13 @@ + to uncompress GZIP compressed data." + compile -library=libextras.a gunzip.c + } ++ ++ cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { ++ display "Turn on CYGPRI_REDBOOT_ZLIB_FLASH" ++ default_value 0 ++ description " ++ Force CYGPRI_REDBOOT_ZLIB_FLASH to be chosen" ++ } + } + + cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM { +@@ -248,6 +256,21 @@ + We assume anything which is invalid RAM is flash, hence + the requires statement" + } ++ ++ cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB { ++ display "Include support for MXC USB downloads" ++ no_define ++ default_value 0 ++ compile -library=libextras.a mxc_usb.c ++ } ++ ++ cdl_option CYGBLD_BUILD_REDBOOT_WITH_IMXOTG { ++ display "Include support for i.MX USB OTG downloads" ++ no_define ++ default_value 0 ++ compile -library=libextras.a imx_usb.c ++ } ++ + cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM { + display "Include POSIX checksum command" + doc ref/cksum-command.html +@@ -314,7 +337,7 @@ + cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { + display "Granularity of timer/ticks" + flavor data +- legal_values { 50 100 250 500 1000 } ++ legal_values { 10 25 50 100 250 500 1000 } + default_value 250 + description " + This option controls the granularity of the timers. +diff -urNad redboot-imx-200952~/packages/redboot/current/include/net/net.h redboot-imx-200952/packages/redboot/current/include/net/net.h +--- redboot-imx-200952~/packages/redboot/current/include/net/net.h 2007-06-04 20:31:00.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/include/net/net.h 2010-01-26 17:33:18.022963009 +0000 +@@ -162,7 +162,7 @@ + #define ETH_TYPE_IP 0x800 + #define ETH_TYPE_ARP 0x806 + #define ETH_TYPE_RARP 0x8053 +-} eth_header_t; ++} __attribute__((aligned(4),packed)) eth_header_t; + + + /* +@@ -298,7 +298,7 @@ + word pkt_bytes; /* number of data bytes in buf */ + word bufsize; /* size of buf */ + word *buf; +-} pktbuf_t; ++} __attribute__((aligned(4),packed)) pktbuf_t; + + + /* protocol handler */ +diff -urNad redboot-imx-200952~/packages/redboot/current/src/fconfig.c redboot-imx-200952/packages/redboot/current/src/fconfig.c +--- redboot-imx-200952~/packages/redboot/current/src/fconfig.c 2006-05-09 15:52:03.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/fconfig.c 2010-01-26 17:33:18.032964259 +0000 +@@ -1140,6 +1140,12 @@ + if (do_flash_init()<0) return; + #ifdef CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG + cfg_size = _rup(sizeof(struct _config), sizeof(struct fis_image_desc)); ++#if defined(MXCFLASH_SELECT_NAND) ++extern int mxc_nand_get_page_size(void); ++ if (IS_FIS_FROM_NAND()) { ++ cfg_size = _rup(sizeof(struct _config), mxc_nand_get_page_size()); ++ } ++#endif + if ((fisdir_size-cfg_size) < (CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT * + CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE)) { + // Too bad this can't be checked at compile/build time +diff -urNad redboot-imx-200952~/packages/redboot/current/src/flash.c redboot-imx-200952/packages/redboot/current/src/flash.c +--- redboot-imx-200952~/packages/redboot/current/src/flash.c 2007-08-28 10:59:52.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/flash.c 2010-01-26 17:33:18.032964259 +0000 +@@ -1610,7 +1610,26 @@ + fis_addr = (void *)((CYG_ADDRESS)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*flash_block_size)); + } ++#if defined(MXCFLASH_SELECT_NAND) ++extern int mxc_nand_fis_start(void); ++ if (IS_FIS_FROM_NAND()) { ++ fis_addr = (void *)((CYG_ADDRESS)flash_start + mxc_nand_fis_start()); ++ } ++#endif + ++#if defined(IMXFLASH_SELECT_SPI_NOR) ++extern int mxc_spi_nor_fis_start(void); ++ if (IS_FIS_FROM_SPI_NOR()) { ++ fis_addr = (void *)((CYG_ADDRESS)flash_start + mxc_spi_nor_fis_start()); ++ } ++#endif ++ ++#if defined(MXCFLASH_SELECT_MMC) ++ if (IS_FIS_FROM_MMC()) { ++ fis_addr = (void *)REDBOOT_IMAGE_SIZE; ++ } ++#endif ++ + if (((CYG_ADDRESS)fis_addr + fisdir_size - 1) > (CYG_ADDRESS)flash_end) { + diag_printf("FIS directory doesn't fit\n"); + return -1; +@@ -1702,4 +1721,4 @@ + fis_usage("unrecognized command"); + } + +-// EOF flash.c ++// EOF flash.c +\ No newline at end of file +diff -urNad redboot-imx-200952~/packages/redboot/current/src/imx_usb.c redboot-imx-200952/packages/redboot/current/src/imx_usb.c +--- redboot-imx-200952~/packages/redboot/current/src/imx_usb.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/imx_usb.c 2010-01-26 17:33:18.042965008 +0000 +@@ -0,0 +1,167 @@ ++//========================================================================== ++// ++// imx_usb.c ++// ++// usb download support for RedBoot ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// Copyright (C) 2002, 2003 Gary Thomas ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Fisher ZHU ++// Contributors: Fisher ZHU ++// Date: 2008-10-27 ++// Purpose: ++// Description: this code architecture is based on mxc_usb.c ++// ++// This code is part of RedBoot (tm). ++// ++// Revision History: ++// Date Author Comments ++// 2008-10-27 Fisher ZHU Initial Creation, support for i.mx37 ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++#include ++static struct { ++ bool open; ++ int total_timeouts, packets_received; ++ unsigned long last_good_block; ++ int avail, actual_len; ++// char data[SEGSIZE+sizeof(struct imxotghdr)]; ++// char *bufp; ++} imxotg_stream; ++ ++EXTERN unsigned long entry_address; ++EXTERN unsigned long load_address; ++EXTERN unsigned long load_address_end; ++ ++extern cyg_uint32 usb_download_address; ++extern cyg_uint32 usb_download_length; ++ ++extern void usbs_imx_otg_device_init(void); ++extern void usbs_imx_otg_device_deinit(void); ++#if defined(CYGBLD_IMX_USB_DOWNLOAD_SUPPORT) ++extern void usbs_imx_otg_download(unsigned char * buffer, unsigned int length); ++#endif ++ ++int ++imxotg_stream_open(connection_info_t *info, ++ int *err) ++{ ++ //diag_printf("%s()\n", __FUNCTION__); ++ usbs_imx_otg_device_init(); ++ return 0; ++} ++ ++void ++imxotg_stream_close(int *err) ++{ ++ //diag_printf("%s()\n", __FUNCTION__); ++ usbs_imx_otg_device_deinit(); ++} ++ ++void ++imxotg_stream_terminate(bool abort, ++ int (*getc)(void)) ++{ ++ int err; ++ //diag_printf("%s()\n", __FUNCTION__); ++ load_address_end = load_address + usb_download_length; ++ entry_address = load_address; ++} ++ ++int ++imxotg_stream_read(char *buf, ++ int len, ++ int *err) ++{ ++ ++ //diag_printf("%s(transfer length=%d,buffer address=0x%08x)\n", __FUNCTION__, len, buf); ++ ++ /*buf and len are not used by usb download. ++ buf is a buffer pointer created by redboot, but USB download will download the binary file directly to ++ the memory pointed by load_address. ++ len is the buffer length, while USB download will download all the binary file once. ++ The two variables are actually dummy.*/ ++ usb_download_address = load_address; ++ usbs_imx_otg_download(buf,len); ++ return 0; ++} ++ ++char * ++imxotg_error(int err) ++{ ++ char *errmsg = "Unknown error"; ++ ++ //diag_printf("%s()\n", __FUNCTION__); ++#if 0 ++ switch (err) { ++ case MXCUSB_ENOTFOUND: ++ return "file not found"; ++ case MXCUSB_EACCESS: ++ return "access violation"; ++ case MXCUSB_ENOSPACE: ++ return "disk full or allocation exceeded"; ++ case MXCUSB_EBADOP: ++ return "illegal MXCUSB operation"; ++ case MXCUSB_EBADID: ++ return "unknown transfer ID"; ++ case MXCUSB_EEXISTS: ++ return "file already exists"; ++ case MXCUSB_ENOUSER: ++ return "no such user"; ++ case MXCUSB_TIMEOUT: ++ return "operation timed out"; ++ case MXCUSB_INVALID: ++ return "invalid parameter"; ++ case MXCUSB_TOOLARGE: ++ return "file is larger than buffer"; ++ } ++#endif ++ return errmsg; ++} ++ ++// ++// RedBoot interface ++// ++GETC_IO_FUNCS(imxotg_io, imxotg_stream_open, imxotg_stream_close, ++ imxotg_stream_terminate, imxotg_stream_read, imxotg_error); ++RedBoot_load(usb, imxotg_io, true, false, 0); ++ ++ +diff -urNad redboot-imx-200952~/packages/redboot/current/src/load.c redboot-imx-200952/packages/redboot/current/src/load.c +--- redboot-imx-200952~/packages/redboot/current/src/load.c 2007-01-24 10:23:35.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/load.c 2010-01-26 17:33:18.042965008 +0000 +@@ -79,7 +79,7 @@ + #include "flash_load.h" + #endif + +-static char usage[] = "[-r] [-v] " ++static char usage[] = "[-r] [-v] [-z to swap endianness on 16 bit] " + #ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB + "[-d] " + #endif +@@ -116,8 +116,8 @@ + struct { + getc_io_funcs_t *io; + int (*fun)(char *, int len, int *err); +- unsigned char buf[BUF_SIZE]; +- unsigned char *bufp; ++ char buf[BUF_SIZE]; ++ char *bufp; + int avail, len, err; + int verbose, decompress, tick; + #ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB +@@ -165,7 +165,7 @@ + } + } + getc_info.avail--; +- return *getc_info.bufp++; ++ return ((int)*getc_info.bufp++) & 0x00FF; + } + + #ifdef CYGBLD_BUILD_REDBOOT_WITH_ZLIB +@@ -297,8 +297,14 @@ + // + // Load an ELF [binary] image + // ++// ++// Note that in case of multicore and the core we wanna load the ++// image for is not in the same endianness that the core we run ++// redboot from, have to invert bytes on 16-bit boundary ++// (16-bit memory) ++// + static unsigned long +-load_elf_image(getc_t getc, unsigned long base) ++load_elf_image(getc_t getc, unsigned long base, bool swap16bit) + { + #ifdef CYGSEM_REDBOOT_ELF + Elf32_Ehdr ehdr; +@@ -306,11 +312,11 @@ + Elf32_Phdr phdr[MAX_PHDR]; + unsigned long offset = 0; + int phx, len, ch; +- unsigned char *addr; ++ unsigned char *addr, *addr_swap; + unsigned long addr_offset = 0; + unsigned long highest_address = 0; + unsigned long lowest_address = 0xFFFFFFFF; +- unsigned char *SHORT_DATA = "Short data reading ELF file\n"; ++ const char SHORT_DATA[] = "Short data reading ELF file\n"; + + // Read the header + if (_read(getc, (unsigned char *)&ehdr, sizeof(ehdr)) != sizeof(ehdr)) { +@@ -422,17 +428,35 @@ + redboot_getc_terminate(true); + return 0; + } ++ ++ /* In case of multicore and the core we wanna load the image for is not in the same endianness ++ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/ ++ if(swap16bit){ ++ // addr is even, have to write char data to the last address ++ if(((unsigned long)addr)%2){ ++ addr_swap=addr-1; ++ *addr_swap = ch; ++ } ++ // addr is odd, have to write char data to the next address ++ else{ ++ addr_swap=addr+1; ++ *addr_swap = ch; ++ } ++ addr++; ++ } ++ else { + #ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS +- if (valid_address(addr)) ++ if (valid_address(addr)) + #endif +- *addr++ = ch; ++ *addr++ = ch; + + #ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH +- else { +- flash_load_write(addr, ch); +- addr++; +- } ++ else { ++ flash_load_write(addr, ch); ++ addr++; ++ } + #endif ++ } + offset++; + if ((unsigned long)(addr-addr_offset) > highest_address) { + highest_address = (unsigned long)(addr - addr_offset); +@@ -503,12 +527,17 @@ + // Because of this, "base" probably only makes sense for a set of + // data which has only one section, e.g. a ROM image. + // ++// Note that in case of multicore and the core we wanna load the ++// image for is not in the same endianness that the core we run ++// redboot from, have to invert bytes on 16-bit boundary ++// (16-bit memory) ++// + static unsigned long +-load_srec_image(getc_t getc, unsigned long base) ++load_srec_image(getc_t getc, unsigned long base, bool swap16bit) + { + int c; + long offset = 0, count, sum, val, cksum; +- unsigned char *addr, *base_addr; ++ unsigned char *addr, *base_addr, *addr_swap; + char type; + bool first_addr = true; + unsigned long addr_offset = 0; +@@ -569,17 +598,33 @@ + offset += count; + while (count-- > 0) { + val = _hex2(getc, 1, &sum); ++ /* In case of multicore and the core we wanna load the image for is not in the same endianness ++ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/ ++ if(swap16bit){ ++ // addr is even, have to write char data to the last address ++ if(((unsigned long)addr)%2){ ++ addr_swap=addr-1; ++ *addr_swap = val; ++ } ++ // addr is odd, have to write char data to the next address ++ else { ++ addr_swap=addr+1; ++ *addr_swap = val; ++ } ++ addr++; ++ } else { + #ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS +- if (valid_address(addr)) ++ if (valid_address(addr)) + #endif +- *addr++ = val; ++ *addr++ = val; + + #ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH +- else { +- flash_load_write(addr, val); +- addr++; +- } ++ else { ++ flash_load_write(addr, val); ++ addr++; ++ } + #endif ++ } + } + cksum = _hex2(getc, 1, 0); + offset += 1; +@@ -644,7 +689,7 @@ + { + int res, num_options; + int i, err; +- bool verbose, raw; ++ bool verbose, raw, swap16bit; + bool base_addr_set, mode_str_set; + char *mode_str; + #ifdef CYGPKG_REDBOOT_NETWORKING +@@ -690,7 +735,9 @@ + (void *)&base, (bool *)&base_addr_set, "load address"); + init_opts(&opts[3], 'm', true, OPTION_ARG_TYPE_STR, + (void *)&mode_str, (bool *)&mode_str_set, "download mode (TFTP, xyzMODEM, or disk)"); +- num_options = 4; ++ init_opts(&opts[4], 'z', false, OPTION_ARG_TYPE_FLG, ++ (void *)&swap16bit, 0, "swap endianness on 16 bit"); ++ num_options = 5; + #if CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS > 1 + init_opts(&opts[num_options], 'c', true, OPTION_ARG_TYPE_NUM, + (void *)&chan, (bool *)&chan_set, "I/O channel"); +@@ -839,6 +886,7 @@ + // Stream open, process the data + if (raw) { + unsigned char *mp = (unsigned char *)base; ++ unsigned char *addr_swap; + err = 0; + while ((res = redboot_getc()) >= 0) { + #ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS +@@ -863,14 +911,32 @@ + break; + } + #endif ++ ++ /* In case of multicore and the core we wanna load the image for is not in the same endianness ++ that the core we run redboot from, have to invert bytes on 16-bit boundary (16-bit memory)*/ ++ if(swap16bit){ ++ // addr is even, have to write char data to the last address ++ if(((unsigned long)mp)%2){ ++ addr_swap=mp-1; ++ *addr_swap = res; ++ } ++ // addr is odd, have to write char data to the next address ++ else{ ++ addr_swap=mp+1; ++ *addr_swap = res; ++ } ++ mp++; ++ } ++ else { + #ifdef CYGBLD_REDBOOT_LOAD_INTO_FLASH +- if (flash_addr_set) { +- flash_load_write(mp, res); +- mp++; +- res++; +- } else ++ if (flash_addr_set) { ++ flash_load_write(mp, res); ++ mp++; ++ res++; ++ } else + #endif +- *mp++ = res; ++ *mp++ = res; ++ } + } + end = (unsigned long) mp; + +@@ -896,10 +962,20 @@ + redboot_getc_rewind(); // Restore header to stream + // Treat data as some sort of executable image + if (strncmp(&type[1], "ELF", 3) == 0) { +- end = load_elf_image(redboot_getc, base); ++ if(swap16bit) { ++ end = load_elf_image(redboot_getc, base, true); ++ } ++ else { ++ end = load_elf_image(redboot_getc, base, false); ++ } + } else if ((type[0] == 'S') && + ((type[1] >= '0') && (type[1] <= '9'))) { +- end = load_srec_image(redboot_getc, base); ++ if(swap16bit) { ++ end = load_srec_image(redboot_getc, base, true); ++ } ++ else { ++ end = load_srec_image(redboot_getc, base, false); ++ } + } else { + redboot_getc_terminate(true); + err_printf("Unrecognized image type: 0x%lx\n", *(unsigned long *)type); +diff -urNad redboot-imx-200952~/packages/redboot/current/src/main.c redboot-imx-200952/packages/redboot/current/src/main.c +--- redboot-imx-200952~/packages/redboot/current/src/main.c 2006-07-20 20:27:47.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/main.c 2010-01-26 17:33:18.042965008 +0000 +@@ -352,6 +352,7 @@ + } + if (res != _GETS_TIMEOUT) break; + script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT; ++ hal_delay_us(CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT*1000); + } + if (res == _GETS_CTRLC) { + script = (unsigned char *)0; // Disable script +@@ -394,7 +395,7 @@ + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + + // set up a temporary context that will take us to the trampoline +- HAL_THREAD_INIT_CONTEXT((CYG_ADDRWORD)workspace_end, ++ HAL_THREAD_INIT_CONTEXT(workspace_end, + breakpoint, trampoline,0); + + // switch context to trampoline (get GDB stubs started) +@@ -600,7 +601,7 @@ + HAL_ICACHE_INVALIDATE_ALL(); + HAL_DCACHE_INVALIDATE_ALL(); + // set up a temporary context that will take us to the trampoline +- HAL_THREAD_INIT_CONTEXT((CYG_ADDRWORD)workspace_end, ++ HAL_THREAD_INIT_CONTEXT(workspace_end, + entry, trampoline, 0); + + // switch context to trampoline +diff -urNad redboot-imx-200952~/packages/redboot/current/src/mxc_usb.c redboot-imx-200952/packages/redboot/current/src/mxc_usb.c +--- redboot-imx-200952~/packages/redboot/current/src/mxc_usb.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/mxc_usb.c 2010-01-26 17:33:18.052964757 +0000 +@@ -0,0 +1,147 @@ ++//========================================================================== ++// ++// mxc_usb.c ++// ++// usb download support for RedBoot ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System. ++// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. ++// Copyright (C) 2002, 2003 Gary Thomas ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++// at http://sources.redhat.com/ecos/ecos-license/ ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Kevin Zhang ++// Contributors: Kevin Zhang ++// Date: 2006-09-06 ++// Purpose: ++// Description: this code is based on tftp_client.c ++// ++// This code is part of RedBoot (tm). ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++#include ++ ++static struct { ++ bool open; ++ int total_timeouts, packets_received; ++ unsigned long last_good_block; ++ int avail, actual_len; ++// char data[SEGSIZE+sizeof(struct mxcusbhdr)]; ++// char *bufp; ++} mxcusb_stream; ++ ++extern void mxc_pcd_open(void); ++extern void mxc_pcd_exit(void); ++extern int mxc_pcd_int_hndlr(long buffer, long length); ++ ++int ++mxcusb_stream_open(connection_info_t *info, ++ int *err) ++{ ++// diag_printf("%s()\n", __FUNCTION__); ++ ++ mxc_pcd_open(); ++ return 0; ++} ++ ++void ++mxcusb_stream_close(int *err) ++{ ++// diag_printf("%s()\n", __FUNCTION__); ++ ++ mxc_pcd_exit(); ++} ++ ++void ++mxcusb_stream_terminate(bool abort, ++ int (*getc)(void)) ++{ ++ int err; ++ ++// diag_printf("%s()\n", __FUNCTION__); ++} ++ ++int ++mxcusb_stream_read(char *buf, ++ int len, ++ int *err) ++{ ++// diag_printf("%s(len=%d buf=%x)\n", __FUNCTION__, len, buf); ++ ++ return mxc_pcd_int_hndlr(buf, len); ++} ++ ++char * ++mxcusb_error(int err) ++{ ++ char *errmsg = "Unknown error"; ++ ++ diag_printf("%s()\n", __FUNCTION__); ++#if 0 ++ switch (err) { ++ case MXCUSB_ENOTFOUND: ++ return "file not found"; ++ case MXCUSB_EACCESS: ++ return "access violation"; ++ case MXCUSB_ENOSPACE: ++ return "disk full or allocation exceeded"; ++ case MXCUSB_EBADOP: ++ return "illegal MXCUSB operation"; ++ case MXCUSB_EBADID: ++ return "unknown transfer ID"; ++ case MXCUSB_EEXISTS: ++ return "file already exists"; ++ case MXCUSB_ENOUSER: ++ return "no such user"; ++ case MXCUSB_TIMEOUT: ++ return "operation timed out"; ++ case MXCUSB_INVALID: ++ return "invalid parameter"; ++ case MXCUSB_TOOLARGE: ++ return "file is larger than buffer"; ++ } ++#endif ++ return errmsg; ++} ++ ++// ++// RedBoot interface ++// ++GETC_IO_FUNCS(mxcusb_io, mxcusb_stream_open, mxcusb_stream_close, ++ mxcusb_stream_terminate, mxcusb_stream_read, mxcusb_error); ++RedBoot_load(usb, mxcusb_io, true, false, 0); ++ +diff -urNad redboot-imx-200952~/packages/redboot/current/src/net/bootp.c redboot-imx-200952/packages/redboot/current/src/net/bootp.c +--- redboot-imx-200952~/packages/redboot/current/src/net/bootp.c 2007-06-04 20:31:00.000000000 +0000 ++++ redboot-imx-200952/packages/redboot/current/src/net/bootp.c 2010-01-26 17:33:18.052964757 +0000 +@@ -44,9 +44,9 @@ + // Author(s): gthomas + // Contributors: gthomas + // Date: 2000-07-14 +-// Purpose: +-// Description: +-// ++// Purpose: ++// Description: ++// + // This code is part of RedBoot (tm). + // + //####DESCRIPTIONEND#### +@@ -60,11 +60,11 @@ + #define SHOULD_BE_RANDOM 0x12345555 + + /* How many milliseconds to wait before retrying the request */ +-#define RETRY_TIME 2000 +-#define MAX_RETRIES 8 ++#define RETRY_TIME 20 ++#define MAX_RETRIES 50 + + static bootp_header_t *bp_info; +- ++ + #ifdef CYGSEM_REDBOOT_NETWORKING_DHCP + static const unsigned char dhcpCookie[] = {99,130,83,99}; + static const unsigned char dhcpEnd[] = {255}; +@@ -101,11 +101,11 @@ + // Only accept pure REPLY responses + if (b->bp_op != BOOTREPLY) + return; +- ++ + // Must be sent to me, as well! + if (memcmp(b->bp_chaddr, __local_enet_addr, 6)) + return; +- ++ + #ifdef CYGSEM_REDBOOT_NETWORKING_DHCP + p = b->bp_vend; + if (memcmp(p, dhcpCookie, sizeof(dhcpCookie))) +@@ -206,7 +206,7 @@ + // setup a socket listener for bootp replies + __udp_install_listener(&udp_skt, IPPORT_BOOTPC, bootp_handler); + +- retry = MAX_RETRIES; ++ retry = MAX_RETRIES; + do { + start = MS_TICKS(); + +@@ -218,7 +218,7 @@ + b.bp_xid = xid++; + memcpy(b.bp_chaddr, __local_enet_addr, 6); + memset(__local_ip_addr, 0, sizeof(__local_ip_addr)); +- ++ + #ifdef CYGSEM_REDBOOT_NETWORKING_DHCP + p = b.bp_vend; + switch (dhcpState) { +@@ -250,7 +250,7 @@ + // Ignore these states (they won't happen) + break; + } +- ++ + // Some servers insist on a minimum amount of "vendor" data + if (p < &b.bp_vend[BP_MIN_VEND_SIZE]) p = &b.bp_vend[BP_MIN_VEND_SIZE]; + txSize = p - (unsigned char*)&b; +@@ -291,10 +291,10 @@ + switch (tag) { + #ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY + case TAG_SUBNET_MASK: // subnet mask +- memcpy(__local_ip_mask,p,4); ++ memcpy(__local_ip_mask,p,4); + break; + case TAG_GATEWAY: // router +- memcpy(__local_ip_gate,p,4); ++ memcpy(__local_ip_gate,p,4); + break; + #endif + #ifdef CYGPKG_REDBOOT_NETWORKING_DNS +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/cdl/diagnosis.cdl redboot-imx-200952/packages/services/diagnosis/current/cdl/diagnosis.cdl +--- redboot-imx-200952~/packages/services/diagnosis/current/cdl/diagnosis.cdl 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/cdl/diagnosis.cdl 2010-01-26 17:33:18.102958875 +0000 +@@ -0,0 +1,112 @@ ++# ==================================================================== ++# ++# diagnosis.cdl ++# ++# diagnosis configuration data. ++# ++# ==================================================================== ++#####ECOSGPLCOPYRIGHTBEGIN#### ++## ------------------------------------------- ++## This file is part of eCos, the Embedded Configurable Operating System. ++## Copyright (C) 2008 Freescale ++## ++## eCos is free software; you can redistribute it and/or modify it under ++## the terms of the GNU General Public License as published by the Free ++## Software Foundation; either version 2 or (at your option) any later version. ++## ++## eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++## WARRANTY; without even the implied warranty of MERCHANTABILITY or ++## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++## for more details. ++## ++## You should have received a copy of the GNU General Public License along ++## with eCos; if not, write to the Free Software Foundation, Inc., ++## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++## ++## As a special exception, if other files instantiate templates or use macros ++## or inline functions from this file, or you compile this file and link it ++## with other works to produce a work based on this file, this file does not ++## by itself cause the resulting work to be covered by the GNU General Public ++## License. However the source code for this file must still be made available ++## in accordance with section (3) of the GNU General Public License. ++## ++## This exception does not invalidate any other reasons why a work based on ++## this file might be covered by the GNU General Public License. ++## ++## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. ++## at http://sources.redhat.com/ecos/ecos-license/ ++## ------------------------------------------- ++#####ECOSGPLCOPYRIGHTEND#### ++# ==================================================================== ++######DESCRIPTIONBEGIN#### ++# ++# Author(s): Fred.Fan ++# Original data: Fred.Fan ++# Contributors: ++# Date: 2008-03-15 ++# ++#####DESCRIPTIONEND#### ++# ++# ==================================================================== ++ ++cdl_package CYGPKG_DIAGNOSIS { ++ display "Diagnostic tools" ++ include_dir cyg/diagnosis ++# doc ref/services-diagnosis.html ++ ++ description " ++ This package provides support for hardware diagnosis." ++ ++ compile -library=libextras.a core.c ++ ++ cdl_component CYGPKG_MEMORY_DIAGNOSIS { ++ display "memory diagnosis" ++ flavor bool ++ ++ description "This option includes memory test cases." ++ ++ compile -library=libextras.a memory/routine.S ++ cdl_option CYGSEM_RAM_RW_DIAGNOSIS { ++ display "perform ram read/write diagnosis" ++ flavor bool ++ default_value 1 ++ ++ description " ++ This option is overriden by the configuration in hal." ++ ++ compile -library=libextras.a memory/ram_rw.c ++ } ++ ++ cdl_option CYGSEM_RAM_PM_DIAGNOSIS { ++ display "perform ram performance diagnosis" ++ flavor bool ++ default_value 1 ++ ++ description " ++ This option is overriden by the configuration in hal." ++ ++ compile -library=libextras.a memory/ram_pm.c ++ } ++ } ++ ++ cdl_component CYGPKG_WDT_DIAGNOSIS { ++ display "watchdog diagnosis" ++ flavor bool ++ ++ description "This option includes watchdog test cases." ++ ++ compile -library=libextras.a ++ cdl_option CYGSEM_WDT_DIAGNOSIS { ++ display "perform watchdog diagnosis" ++ flavor bool ++ default_value 1 ++ ++ description " ++ This option is overriden by the configuration in hal." ++ ++ compile wdt/wdt.c ++ } ++ } ++} ++ ++ +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/include/diagnosis.h redboot-imx-200952/packages/services/diagnosis/current/include/diagnosis.h +--- redboot-imx-200952~/packages/services/diagnosis/current/include/diagnosis.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/include/diagnosis.h 2010-01-26 17:33:18.102958875 +0000 +@@ -0,0 +1,19 @@ ++#ifndef _DIAGNOSIS_H_ ++#define _DIAGNOSIS_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CYGPKG_MEMORY_DIAGNOSIS ++#include ++#endif ++ ++extern struct cmd __DIAGNOSIS_cmds_TAB__[], __DIAGNOSIS_cmds_TAB_END__; ++extern void diagnosis_usage(char *why); ++ ++#endif /* _DIAGNOSIS_H_ */ +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/include/memory.h redboot-imx-200952/packages/services/diagnosis/current/include/memory.h +--- redboot-imx-200952~/packages/services/diagnosis/current/include/memory.h 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/include/memory.h 2010-01-26 17:33:18.102958875 +0000 +@@ -0,0 +1,15 @@ ++#ifndef __DIAGNOSIS_MEMORY_H_ ++#define __DIAGNOSIS_MEMORY_H_ ++ ++extern void diagnosis_mem_read_block(unsigned long start, int size); ++extern void diagnosis_mem_write_block(unsigned long start, int size); ++extern int diagnosis_mem_copy_block(unsigned long start, unsigned long dest, int size); ++ ++#ifdef CYGSEM_RAM_RW_DIAGNOSIS ++ ++enum { ++DIAGNOSIS_MEM_RAM_RD = 0, ++}; ++#endif ++ ++#endif /* __DIAGNOSIS_MEMORY_H_ */ +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/src/core.c redboot-imx-200952/packages/services/diagnosis/current/src/core.c +--- redboot-imx-200952~/packages/services/diagnosis/current/src/core.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/src/core.c 2010-01-26 17:33:18.102958875 +0000 +@@ -0,0 +1,40 @@ ++#include ++#include ++#include ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++// Define table boundaries ++CYG_HAL_TABLE_BEGIN( __DIAGNOSIS_cmds_TAB__, DIAGNOSIS_cmds); ++CYG_HAL_TABLE_END( __DIAGNOSIS_cmds_TAB_END__, DIAGNOSIS_cmds); ++ ++// CLI function ++static cmd_fun do_diagnosis_cmds; ++RedBoot_nested_cmd("diag", ++ "Tools for system diagnostics", ++ "{cmds}", ++ do_diagnosis_cmds, ++ __DIAGNOSIS_cmds_TAB__, &__DIAGNOSIS_cmds_TAB_END__ ++ ); ++ ++void diagnosis_usage(char *why) ++{ ++ diag_printf("*** invalid 'diag' command: %s\n", why); ++ cmd_usage(__DIAGNOSIS_cmds_TAB__, &__DIAGNOSIS_cmds_TAB_END__, "diag "); ++} ++ ++static void do_diagnosis_cmds(int argc, char *argv[]) ++{ ++ struct cmd * cmd; ++ if (argc < 2) { ++ diagnosis_usage("too few arguments"); ++ return; ++ } ++ if ((cmd = cmd_search(__DIAGNOSIS_cmds_TAB__, ++ &__DIAGNOSIS_cmds_TAB_END__, ++ argv[1])) != (struct cmd *)0) { ++ (cmd->fun)(argc, argv); ++ return; ++ } ++ diagnosis_usage("unrecognized command"); ++} +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/src/memory/ram_pm.c redboot-imx-200952/packages/services/diagnosis/current/src/memory/ram_pm.c +--- redboot-imx-200952~/packages/services/diagnosis/current/src/memory/ram_pm.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/src/memory/ram_pm.c 2010-01-26 17:33:18.112958624 +0000 +@@ -0,0 +1,183 @@ ++#include ++#include ++#include ++#include ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++#define DEFAULT_TEST_TIME 2 ++#define MIN_TEST_TIME 1 ++#define MAX_TEST_TIME 20 ++ ++#define DEFAULT_BLOCK_SIZE 4096 ++#define MAX_BLOCK_SIZE 32768 ++#define MIN_BLOCK_SIZE 1024 ++ ++local_cmd_entry("ram_pm", ++ "ram performance test", ++ "-t time -b size [-m mode]\n" ++ " -t time: set test time\n" ++ " -b size: set block size < 8192\n" ++ " -m mode: set 0:read, 1:write, 2:copy\n", ++ ram_pm_test, ++ DIAGNOSIS_cmds ++); ++ ++enum { ++ RAM_PM_READ = 0, ++ RAM_PM_WRITE, ++ RAM_PM_COPY, ++ RAM_PM_MAX, ++}; ++ ++static char * mode_str[RAM_PM_MAX] = ++{ ++ "read", ++ "write", ++ "copy" ++}; ++ ++static inline void start_timer(int second) ++{ ++ unsigned int reg; ++ reg = readl(CCM_BASE_ADDR + CLKCTL_CGR1); ++ writel(reg | 0x30, CCM_BASE_ADDR + CLKCTL_CGR1); ++ ++ reg = readl(GPT_BASE_ADDR + GPTCR) | 0x8002; ++ writel(reg&(~1), GPT_BASE_ADDR + GPTCR); ++ while(readl(GPT_BASE_ADDR + GPTCR) & 0x8000); ++ ++ reg = second * 1000; ++ writel(reg, GPT_BASE_ADDR + GPTOCR1); ++ writel(0, GPT_BASE_ADDR + GPTIR); ++ writel(0, GPT_BASE_ADDR + GPTCNT); ++ writel(31, GPT_BASE_ADDR + GPTPR); ++ writel(0x3F, GPT_BASE_ADDR + GPTSR); ++ ++ reg = readl(GPT_BASE_ADDR + GPTCR) | 0x303; ++ writel(reg, GPT_BASE_ADDR + GPTCR); ++} ++ ++static inline int get_time(int * cycles) ++{ ++ *cycles = readl(GPT_BASE_ADDR + GPTCNT); ++ if (readl(GPT_BASE_ADDR + GPTSR)& 1) ++ *cycles -= readl(GPT_BASE_ADDR + GPTOCR1); ++ return readl(GPT_BASE_ADDR + GPTSR) & 1; ++} ++ ++static inline void stop_timer(void) ++{ ++ unsigned int reg; ++ reg = readl(GPT_BASE_ADDR + GPTCR) | 0x8000; ++ writel(reg&(~1), GPT_BASE_ADDR + GPTCR); ++} ++ ++static int performance_read_write(int time, int bsize, int read) ++{ ++ unsigned long start = CYGMEM_REGION_ram + 1*1024*1024; ++ int size = CYGMEM_REGION_ram_SIZE / 2; ++ int cycles; ++ long long i; ++ ++ if ( (bsize % 32) || (size % bsize) || size < (1*1024*1024)) { ++ diag_printf("size is illegal(size=%d)\n", size); ++ } ++ ++ size = (size / bsize) * bsize; ++ diag_printf("%s:size=%d, bsize=%d\n", read?"READ":"WRITE", size, bsize); ++ start_timer(time); ++ for (i=0; !get_time(&cycles); i += bsize) { ++ if (read) ++ diagnosis_mem_read_block(start + (i % size), bsize); ++ else ++ diagnosis_mem_write_block(start + (i % size), bsize); ++ } ++ stop_timer(); ++ diag_printf("Finished size=%ld ", i); ++ diag_printf("time=%d", time); ++ diag_printf(" %d(ms)\n", cycles); ++ i = (i * 1000) / ((time * 1000) + cycles); ++ return i / 1024; ++} ++ ++static int performance_copy(int time, int bsize) ++{ ++ unsigned long start = CYGMEM_REGION_ram + 1 * 1024 * 1024; ++ unsigned long dest = start + 1 * 1024 * 1024; ++ int size = CYGMEM_REGION_ram_SIZE / 4; ++ int cycles; ++ long long i; ++ ++ dest += size; ++ ++ if ( (bsize % 32) || (size % bsize) || size < (1 * 1024 * 1024)) { ++ diag_printf("size is illegal(size=%d)\n", size); ++ } ++ ++ start_timer(time); ++ ++ size = (size / bsize) * bsize; ++ for (i = 0; !get_time(&cycles); i += bsize) { ++ if (diagnosis_mem_copy_block(start + (i % size), ++ dest + (i % size), bsize) ++ < 0) { ++ diag_printf("verify data fail\n"); ++ break; ++ } ++ } ++ stop_timer(); ++ i = (i * 1000) / ((time * 1000) + cycles); ++ return i / 1024; ++} ++ ++static void ram_pm_test(int argc, char * argv[]) ++{ ++ int opts_map[3]; ++ struct option_info opts[3]; ++ int time, mode, result, bsize; ++ ++ memset(opts_map, 0, sizeof(int)*2); ++ init_opts(&opts[0], 't', true, OPTION_ARG_TYPE_NUM, ++ (void *)&time, (bool *)&opts_map[0], "test time"); ++ init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&bsize, (bool *)&opts_map[1], "block size"); ++ init_opts(&opts[2], 'm', true, OPTION_ARG_TYPE_NUM, ++ (void *)&mode, (bool *)&opts_map[2], "operate mode"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 3, 0, 0, 0)) { ++ diagnosis_usage("invalid arguments"); ++ return; ++ } ++ ++ if (!opts_map[0] || time < MIN_TEST_TIME || time > MAX_TEST_TIME) ++ time = DEFAULT_TEST_TIME; ++ ++ if(!opts_map[1] || bsize < MIN_BLOCK_SIZE || bsize > MAX_BLOCK_SIZE) ++ bsize = DEFAULT_BLOCK_SIZE; ++ ++ if (!opts_map[2] || mode >= RAM_PM_MAX) ++ mode = RAM_PM_READ; ++ ++ diag_printf("Start memory performance test (%s)...\n", ++ mode_str[mode]); ++ switch(mode) { ++ case RAM_PM_READ: ++ result = performance_read_write(time, bsize, 1); ++ break; ++ case RAM_PM_WRITE: ++ result = performance_read_write(time, bsize, 0); ++ break; ++ case RAM_PM_COPY: ++ result = performance_copy(time, bsize); ++ break; ++ default: ++ result = -1; ++ } ++ if (result < 0) { ++ diag_printf("memory performance test fails\n"); ++ } else { ++ diag_printf("memory performance test success:%d.%d(MB/s)\n", ++ result / 1024, (result % 1024)); ++ } ++} +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/src/memory/ram_rw.c redboot-imx-200952/packages/services/diagnosis/current/src/memory/ram_rw.c +--- redboot-imx-200952~/packages/services/diagnosis/current/src/memory/ram_rw.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/src/memory/ram_rw.c 2010-01-26 17:33:18.112958624 +0000 +@@ -0,0 +1,262 @@ ++#include ++#include ++#include ++#include ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++static int loops1; ++static unsigned int pattern1, pattern2; ++static unsigned int start; ++static int length; ++static int burst = 0; ++ ++local_cmd_entry("ram_rw", ++ "ram read/write accessing", ++ "-c iterators -b -l "\ ++ "-p pattern -m case [-s]\n", ++ ram_rw_test, ++ DIAGNOSIS_cmds ++); ++ ++local_cmd_entry("memcpybm", ++ "ram memory copy benchmarking", ++ "-c -s -e -a -b \n", ++ memcpybm, ++ DIAGNOSIS_cmds ++); ++ ++static void raw_rw_case1(void) ++{ ++ unsigned int * current_write; ++ unsigned int * current_read; ++ int round = 0; ++ diag_printf("RAM diagnostical pattern from David.Young of freescale\n"); ++ diag_printf("burst is %s\n", burst?"enabled":"disabled"); ++ while( (round++) < loops1) { ++ if (_rb_break(0)) ++ return; ++ if(burst) { ++ current_write =(unsigned int *)start; ++ memset(current_write, (pattern1&0xFF000000)>>24, length); ++ } else { ++ for(current_write=(unsigned int *)start; current_write<(unsigned int *)(start + length); current_write += 2) { ++ *current_write = ((unsigned int)current_write & 0x0000FFFF)|(0xFFFF0000 & pattern1); ++ } ++ for(current_write=(unsigned int *)start + 1; current_write<(unsigned int *)(start + length); current_write += 2) { ++ *current_write = ((unsigned int)current_write & 0x0000FFFF)|(0xFFFF0000 & pattern2); ++ } ++ } ++ for(current_read=(unsigned int *)start; current_read<(unsigned int *)(start + length); current_read ++) { ++ if(burst) { ++ if((*current_read) != pattern2) { ++ diag_printf("\tround %d::[0x%08x]=0x%08x:0x%08x\n", round, current_read, pattern2, *current_read); ++ goto fail; ++ } ++ } else { ++ if((current_read - (unsigned int *)start) & 1) { ++ if(((*current_read)&0xFFFF0000) != (pattern2&0xFFFF0000)) { ++ diag_printf("\tround %d::[0x%08x]=0x%08x:0x%08x\n", round, current_read, (pattern2&0xFFFF0000)|((unsigned int)current_read)&0xFFFF, *current_read); ++ goto fail; ++ } ++ } else { ++ if(((*current_read)&0xFFFF0000) != (pattern1&0xFFFF0000)) { ++ diag_printf("\tround %d::[0x%08x]=0x%08x:0x%08x\n", round, current_read, (pattern1&0xFFFF0000)|((unsigned int)current_read)&0xFFFF, *current_read); ++ goto fail; ++ } ++ } ++ } ++ } ++ } ++ diag_printf("Diagnosis is successful!\n"); ++ return; ++fail: ++ diag_printf("Diagnosis is failure !\n"); ++} ++ ++static void ram_rw_test(int argc, char * argv[]) ++{ ++ int opts_map[6]; ++ struct option_info opts[6]; ++ int mode; ++ ++ memset(opts_map, 0, sizeof(int)*6); ++ ++ init_opts(&opts[0], 'c', true, OPTION_ARG_TYPE_NUM, ++ (void *)&loops1, (bool *)&opts_map[0], "the rounds of test"); ++ init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&start, (bool *)&opts_map[1], "accessing start address"); ++ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, ++ (void *)&length, (bool *)&opts_map[2], "accessing size(bytes)"); ++ init_opts(&opts[3], 'p', true, OPTION_ARG_TYPE_NUM, ++ (void *)&pattern1, (bool *)&opts_map[3], "High 16bit is valid"); ++ init_opts(&opts[4], 'm', true, OPTION_ARG_TYPE_NUM, ++ (void *)&mode, (bool *)&opts_map[4], "Test case number"); ++ init_opts(&opts[5], 's', false, OPTION_ARG_TYPE_FLG, ++ (void *)&burst, (bool *)0, "enable bust mode(based on memset)"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 6, 0, 0, 0)) { ++ diagnosis_usage("invalid arguments"); ++ return; ++ } ++ ++ if(!opts_map[0]) { ++ loops1 = 32; ++ } ++ ++ if(!opts_map[1]) { ++ start = 0x80000; ++ } ++ ++ if(!opts_map[2]) { ++ length = 8192; ++ } ++ ++ if(!opts_map[3]) { ++ pattern1 = 0x55550000; ++ } ++ ++ if(!opts_map[4]) { ++ mode = DIAGNOSIS_MEM_RAM_RD; ++ } ++ ++ if(burst) { ++ pattern2 = (pattern1&0xFF000000); ++ pattern2 |= pattern2>>8; ++ pattern2 |= pattern2>>16; ++ } else { ++ pattern2 = (~pattern1)&0xFFFF0000; ++ } ++ ++ if(!valid_address((unsigned char *)start)) { ++ if (!verify_action("Specified address (%p) is not believed to be in RAM", (void*)start)) ++ return; ++ } ++ ++ switch(mode) { ++ case DIAGNOSIS_MEM_RAM_RD: ++ raw_rw_case1(); ++ break; ++ default: ++ diag_printf("Invalid memory diagnosis case!\n"); ++ } ++} ++ ++/* Defines */ ++#define SIZE_1K 1024 ++#define SIZE_4K (4*SIZE_1K) ++#define SIZE_1M (1024*1024) ++#define START_SIZE (2*SIZE_1K) ++#define END_SIZE SIZE_1M ++#define ALIGN SIZE_4K ++#define START_LOOPS 200000 ++ ++#define OPT_SIZE 5 ++#define printf diag_printf ++#define CLOCKS_PER_SEC 32768 ++extern unsigned int hal_timer_count(void); ++#define clock() hal_timer_count() ++ ++//#define memcpy diagnosis_mem_copy_block ++static void memcpybm(int argc, char * argv[]) ++{ ++ int opts_map[OPT_SIZE]; ++ struct option_info opts[OPT_SIZE]; ++ int mode; ++ int size = START_SIZE / SIZE_1K; ++ int end_size = END_SIZE / SIZE_1K; ++ int salign = ALIGN; ++ int dalign = ALIGN; ++ int loops = START_LOOPS / 1000; ++ int src, dst, asrc, adst; ++ ++ ++ memset(opts_map, 0, sizeof(int)*OPT_SIZE); ++ ++ init_opts(&opts[0], 'c', true, OPTION_ARG_TYPE_NUM, ++ (void *)&loops, (bool *)&opts_map[0], "the rounds of test in thousands"); ++ init_opts(&opts[1], 's', true, OPTION_ARG_TYPE_NUM, ++ (void *)&size, (bool *)&opts_map[1], "start size in KB"); ++ init_opts(&opts[2], 'e', true, OPTION_ARG_TYPE_NUM, ++ (void *)&end_size, (bool *)&opts_map[2], "end size in KB"); ++ init_opts(&opts[3], 'a', true, OPTION_ARG_TYPE_NUM, ++ (void *)&salign, (bool *)&opts_map[3], "source align in byte"); ++ init_opts(&opts[4], 'b', true, OPTION_ARG_TYPE_NUM, ++ (void *)&dalign, (bool *)&opts_map[4], "destination align in byte"); ++ ++ if (!scan_opts(argc, argv, 2, opts, OPT_SIZE, 0, 0, 0)) { ++ diagnosis_usage("invalid arguments"); ++ return; ++ } ++ ++ loops *= 1000; ++ size *= SIZE_1K; ++ end_size *= SIZE_1K; ++ /* Allocate buffers */ ++ if ((src = (int) malloc(end_size + salign + SIZE_4K)) == 0) { ++ printf("%s: insufficient memory\n", argv[0]); ++ return; ++ } ++ memset((void*)src, 0xaa, end_size + salign + SIZE_4K); ++ if ((dst = (int) malloc(end_size + dalign + SIZE_4K)) == 0) { ++ free((void*)src); ++ printf("%s: insuficient memory\n", argv[0]); ++ return; ++ } ++ memset((void*)dst, 0x55, end_size + dalign + SIZE_4K); ++ ++ /* Align buffers */ ++ if (src % SIZE_4K == 0) ++ asrc = src + salign; ++ else ++ asrc = src + SIZE_4K - (src % SIZE_4K) + salign; ++ if (dst % SIZE_4K == 0) ++ adst = dst + dalign; ++ else ++ adst = dst + SIZE_4K - (dst % SIZE_4K) + dalign; ++ ++ /* Print Banner */ ++ printf("\nMEMCPY Benchmark\n\n"); ++ printf("Src Buffer 0x%08x\n", asrc); ++ printf("Dst Buffer 0x%08x\n\n", adst); ++ printf("%10s %10s\n", "Cached", "Bandwidth"); ++ printf("%10s %10s\n", "(KBytes)", "(MB/sec)"); ++ ++ /* Loop over copy sizes */ ++ while (size <= end_size) ++ { ++ unsigned int start_time; ++ unsigned int elapsed_time; ++ int loop; ++ unsigned long long sz; ++ ++ printf("%10d", size / SIZE_1K); ++ ++ /* Do data copies */ ++ start_time = clock(); ++ for (loop = 0; loop < loops; loop++) ++ memcpy((void*)adst, (void*)asrc, size); ++ elapsed_time = (clock() - start_time); ++ ++ sz = size *loops * 2; ++ printf(" %d", sz*CLOCKS_PER_SEC/elapsed_time/SIZE_1M); ++ printf("\t elapsed=%d", elapsed_time); ++ printf("\tsize=%d, loops=%d, sz=%d", size, loops, sz); ++ printf("\n"); ++ ++/* ++ printf(" %10.0f\n", ((float)size*loops*2)/elapsed_time/SIZE_1M); ++ printf(" %d.%d.%d\n", elapsed_time / CLOCKS_PER_SEC, ++ (elapsed_time % CLOCKS_PER_SEC) * 1000 / CLOCKS_PER_SEC, ++ (((elapsed_time % CLOCKS_PER_SEC) * 1000) % CLOCKS_PER_SEC) * 1000 / CLOCKS_PER_SEC); ++*/ ++ /* Adjust for next test */ ++ size *= 2; ++ loops /= 2; ++ } ++ ++ /* Free buffers */ ++ free((void*)src); ++ free((void*)dst); ++} ++ +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/src/memory/routine.S redboot-imx-200952/packages/services/diagnosis/current/src/memory/routine.S +--- redboot-imx-200952~/packages/services/diagnosis/current/src/memory/routine.S 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/src/memory/routine.S 2010-01-26 17:33:18.112958624 +0000 +@@ -0,0 +1,48 @@ ++ .text ++/* ++ * void diagnosis_mem_read_block(unsigned long start, int size) ++ */ ++ .global diagnosis_mem_read_block ++diagnosis_mem_read_block: ++ stmdb sp!, {r2 - r9} ++ add r1, r1, r0 ++1: cmp r0, r1 ++ ldmloia r0!, {r2-r9} ++ blo 1b ++ ldmia sp!, {r2 - r9} ++ mov pc, lr ++/* ++ * void diagnosis_mem_write_block(unsigned long start, int size) ++ */ ++ .global diagnosis_mem_write_block ++diagnosis_mem_write_block: ++ stmdb sp!, {r2 - r9} ++ add r1, r1, r0 ++1: cmp r0, r1 ++ stmloia r0!, {r2 - r9} ++ blo 1b ++ ldmia sp!, {r2 - r9} ++ mov pc, lr ++/* ++ * int diagnosis_mem_copy_block(unsigned long start, unsigned long dest, int size) ++ */ ++ .global diagnosis_mem_copy_block ++diagnosis_mem_copy_block: ++ stmdb sp!, {r3 - r11} ++ stmdb sp!, {r0, r1} ++ add r11, r1, r2 ++1: cmp r1, r11 ++ ldmloia r0!, {r3-r10} ++ stmloia r1!, {r3-r10} ++ blo 1b ++ ldmia sp!, {r0, r1} ++1: cmp r1, r11 ++ movhs r0, #0 ++ bhs 2f ++ ldrlo r3, [r0], #4 ++ ldrlo r4, [r1], #4 ++ cmp r3, r4 ++ beq 1b ++ mov r0, #-1 ++2: ldmia sp!, {r3 - r11} ++ mov pc, lr +diff -urNad redboot-imx-200952~/packages/services/diagnosis/current/src/wdt/wdt.c redboot-imx-200952/packages/services/diagnosis/current/src/wdt/wdt.c +--- redboot-imx-200952~/packages/services/diagnosis/current/src/wdt/wdt.c 1970-01-01 00:00:00.000000000 +0000 ++++ redboot-imx-200952/packages/services/diagnosis/current/src/wdt/wdt.c 2010-01-26 17:33:18.112958624 +0000 +@@ -0,0 +1,141 @@ ++#include ++#include ++#include ++#include ++ ++#include CYGHWR_MEMORY_LAYOUT_H ++ ++#define WDT_WCR 0x00 ++#define WDT_WSR 0x02 ++ ++#define WDT_CNT_MASK 0xFF00 ++#define WDT_WCR_MASK 0xFF ++#define WDT_CNT_OFF 8 ++ ++#define WDT_WCR_WDW (1 << 7) ++#define WDT_WCR_WOE (1 << 6) ++#define WDT_WCR_WDA (1 << 5) ++#define WDT_WCR_SRS (1 << 4) ++#define WDT_WCR_WDT (1 << 3) ++#define WDT_WCR_WDE (1 << 2) ++#define WDT_WCR_WDBG (1 << 1) ++#define WDT_WCR_WDZST (1) ++ ++#define WDT_MAGIC_1 (0x5555) ++#define WDT_MAGIC_2 (0xAAAA) ++ ++local_cmd_entry("wdt", ++ "watchdog test:Warning after run test, please reboot", ++ "-s sleep_time -t timeout [-c ctrl_bits] -b\n" ++ "-b:Insert memory access during ping operation\n", ++ wdt_test, ++ DIAGNOSIS_cmds ++); ++ ++static unsigned char wdt_wcr; ++ ++static unsigned int wdt_ping_mode; ++ ++static inline void wdt_setup(unsigned int timeout) ++{ ++ unsigned short int reg; ++ reg = readw(WDOG_BASE_ADDR + WDT_WCR) & WDT_WCR_MASK; ++ reg |= (timeout * 2 << WDT_CNT_OFF) & WDT_CNT_MASK; ++ ++ if (wdt_wcr) ++ reg |= wdt_wcr & WDT_WCR_MASK; ++ else ++ reg |= WDT_WCR_WOE | WDT_WCR_WDA | WDT_WCR_SRS| ++ WDT_WCR_WDBG | WDT_WCR_WDZST; ++ ++ diag_printf("WCR=%x\n", reg | WDT_WCR_WDE); ++ writew(reg | WDT_WCR_WDE, WDOG_BASE_ADDR + WDT_WCR); ++} ++ ++static inline void wdt_stop(void) ++{ ++ unsigned short int reg; ++ reg = readw(WDOG_BASE_ADDR + WDT_WCR) & (~WDT_WCR_WDE); ++ reg |= WDT_CNT_MASK; ++ writew(reg, WDOG_BASE_ADDR + WDT_WCR); ++} ++ ++static inline void wdt_keepalive(void) ++{ ++ int j; ++ volatile unsigned int i; ++ ++ if (wdt_ping_mode) { ++ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + WDT_WSR); ++ for (i = 0, j &= 0x7; i <= j; i++) ++ asm("nop"); ++ } else { ++ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + WDT_WSR); ++ } ++ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + WDT_WSR); ++} ++ ++static void wdt_sleep(int second) ++{ ++ int i; ++ unsigned int delayCount = 32000; ++ ++ for ( i = 0; i < second; i++) { ++ writel(0x01, EPIT_BASE_ADDR + EPITSR); ++ writel(delayCount, EPIT_BASE_ADDR + EPITLR); ++ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); ++ } ++} ++ ++static void wdt_test(int argc, char * argv[]) ++{ ++ int opts_map[4]; ++ struct option_info opts[4]; ++ unsigned int sleep_timeout; ++ unsigned int wdt_timeout; ++ ++ memset(opts_map, 0, sizeof(int)*4); ++ ++ init_opts(&opts[0], 's', true, OPTION_ARG_TYPE_NUM, ++ (void *)&sleep_timeout, (bool *)&opts_map[0], "sleep time"); ++ init_opts(&opts[1], 't', true, OPTION_ARG_TYPE_NUM, ++ (void *)&wdt_timeout, (bool *)&opts_map[1], "watchdog timeout"); ++ init_opts(&opts[2], 'c', true, OPTION_ARG_TYPE_NUM, ++ (void *)&wdt_wcr, (bool *)&opts_map[2], "watchdog control bits"); ++ init_opts(&opts[3], 'b', false, OPTION_ARG_TYPE_FLG, ++ (void *)&wdt_ping_mode, (bool *)0, "Add nop between ping operation"); ++ ++ if (!scan_opts(argc, argv, 2, opts, 4, 0, 0, 0)) { ++ diagnosis_usage("invalid arguments"); ++ return; ++ } ++ ++ if(!opts_map[0]) { ++ sleep_timeout = 1; ++ } ++ ++ if(!opts_map[1]) { ++ wdt_timeout = 2; ++ } ++ ++ if(!opts_map[2]) { ++ wdt_wcr = 0; ++ } ++ ++ diag_printf("Watchdog sleeptime=%d timeout=%d %s in ping", ++ sleep_timeout, wdt_timeout, ++ wdt_ping_mode?"Add memory access":"No memory access"); ++ wdt_setup(wdt_timeout); ++ ++ while(1) { ++ if(_rb_break(0)) { ++ diag_printf("break Watchdog test\n"); ++ wdt_sleep(wdt_timeout*2); ++ break; ++ } ++ wdt_keepalive(); ++ wdt_sleep(sleep_timeout); ++ } ++ wdt_stop(); ++ diag_printf("Exit Watchdog test\n"); ++} +diff -urNad redboot-imx-200952~/packages/services/memalloc/common/current/include/dlmalloc.hxx redboot-imx-200952/packages/services/memalloc/common/current/include/dlmalloc.hxx +--- redboot-imx-200952~/packages/services/memalloc/common/current/include/dlmalloc.hxx 2002-05-23 23:08:43.000000000 +0000 ++++ redboot-imx-200952/packages/services/memalloc/common/current/include/dlmalloc.hxx 2010-01-26 17:33:18.232957005 +0000 +@@ -111,7 +111,7 @@ + : mypool( base, size, argthru ) {} + + // Destructor +- ~Cyg_Mempool_dlmalloc() {} ++ //~Cyg_Mempool_dlmalloc() {} + + // get some memory; wait if none available + // if we aren't configured to be thread-aware this is irrelevant +diff -urNad redboot-imx-200952~/packages/services/memalloc/common/current/include/dlmallocimpl.hxx redboot-imx-200952/packages/services/memalloc/common/current/include/dlmallocimpl.hxx +--- redboot-imx-200952~/packages/services/memalloc/common/current/include/dlmallocimpl.hxx 2002-05-23 23:08:43.000000000 +0000 ++++ redboot-imx-200952/packages/services/memalloc/common/current/include/dlmallocimpl.hxx 2010-01-26 17:33:18.232957005 +0000 +@@ -146,7 +146,7 @@ + CYG_ADDRWORD /* argthru */ ); + + // Destructor +- ~Cyg_Mempool_dlmalloc_Implementation() {} ++ //~Cyg_Mempool_dlmalloc_Implementation() {} + + // get some memory, return NULL if none available + cyg_uint8 * +diff -urNad redboot-imx-200952~/packages/services/memalloc/common/current/src/heapgen.tcl redboot-imx-200952/packages/services/memalloc/common/current/src/heapgen.tcl +--- redboot-imx-200952~/packages/services/memalloc/common/current/src/heapgen.tcl 2007-10-24 13:25:46.000000000 +0000 ++++ redboot-imx-200952/packages/services/memalloc/common/current/src/heapgen.tcl 2010-01-26 17:33:18.232957005 +0000 +@@ -198,4 +198,4 @@ + close $cfile + + # ---------------------------------------------------------------------------- +-# EOF heapgen.tcl ++# EOF heapgen.tcl +\ No newline at end of file