pax_global_header00006660000000000000000000000064125652467450014532gustar00rootroot0000000000000052 comment=0288a4b87b65ba54f37fbeeea3cb32238deee92e xserver-xorg-video-ati-7.5.0+git20150819/000077500000000000000000000000001256524674500175065ustar00rootroot00000000000000xserver-xorg-video-ati-7.5.0+git20150819/.dir-locals.el000066400000000000000000000004071256524674500221400ustar00rootroot00000000000000((nil (indent-tabs-mode . t) (tab-width . 8) (c-basic-offset . 4) (c-file-style . "stroustrup") (fill-column . 78) (eval . (progn (c-set-offset 'innamespace '0) (c-set-offset 'inline-open '0))) ) (makefile-mode (indent-tabs-mode . t)) ) xserver-xorg-video-ati-7.5.0+git20150819/.gitignore000066400000000000000000000017571256524674500215100ustar00rootroot00000000000000# # X.Org module default exclusion patterns # The next section if for module specific patterns # # Do not edit the following section # GNU Build System (Autotools) aclocal.m4 autom4te.cache/ autoscan.log ChangeLog compile config.guess config.h config.h.in config.log config-ml.in config.py config.status config.status.lineno config.sub configure configure.scan depcomp .deps/ INSTALL install-sh .libs/ libtool libtool.m4 ltmain.sh lt~obsolete.m4 ltoptions.m4 ltsugar.m4 ltversion.m4 Makefile Makefile.in mdate-sh missing mkinstalldirs *.pc py-compile stamp-h? symlink-tree texinfo.tex ylwrap # Do not edit the following section # Edit Compile Debug Document Distribute *~ *.[0-9] *.[0-9]x *.bak *.bin core *.dll *.exe *-ISO*.bdf *-JIS*.bdf *-KOI8*.bdf *.kld *.ko *.ko.cmd *.lai *.l[oa] *.[oa] *.obj *.patch *.so *.pcf.gz *.pdb *.tar.bz2 *.tar.gz # # Add & Override patterns for xf86-video-ati # # Edit the following section as needed # For example, !report.pc overrides *.pc. See 'man gitignore' # xserver-xorg-video-ati-7.5.0+git20150819/COPYING000066400000000000000000000153271256524674500205510ustar00rootroot00000000000000Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation, and that the name of Marc Aurele La France not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. Marc Aurele La France makes no representations about the suitability of this software for any purpose. It is provided "as-is" without express or implied warranty. MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net Copyright (c) 1995-2003 by The XFree86 Project, Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Except as contained in this notice, the name of the copyright holder(s) and author(s) shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the copyright holder(s) and author(s). Copyright 2006-2007 Advanced Micro Devices, Inc. Copyright 2007 Egbert Eich Copyright 2007 Matthias Hopf Copyright (C) 1999-2001 Brian Paul All Rights Reserved. Copyright 2007 Luc Verhaegen Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Copyright 2007 Advanced Micro Devices, Inc. Copyright (C) 2008-2009 Advanced Micro Devices, Inc. Copyright 2004 Eric Anholt Copyright 2005 Eric Anholt Copyright 2000 ATI Technologies Inc., Markham, Ontario, and Copyright 2004 ATI Technologies Inc., Markham, Ontario Copyright (C) 2008-2009 Alexander Deucher Copyright 2008 Jérôme Glisse Copyright 2005 Benjamin Herrenschmidt Copyright 2008 Kristian Høgsberg Copyright (C) 2008-2009 Matthias Hopf Copyright (c) 2006 Itronix Inc. Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. Copyright © 2007 Red Hat, Inc. Copyright © 2009 Red Hat, Inc. Copyright 2007 George Sapountzis Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. Copyright 2006 Tungsten Graphics, Inc. Copyright 2000 VA Linux Systems, Inc., Fremont, California. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Copyright © 2006 Keith Packard Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation, and that the name of the copyright holders not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. The copyright holders make no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. xserver-xorg-video-ati-7.5.0+git20150819/Makefile.am000066400000000000000000000024201256524674500215400ustar00rootroot00000000000000# Copyright 2005 Adam Jackson. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # on the rights to use, copy, modify, merge, publish, distribute, sub # license, and/or sell copies of the Software, and to permit persons to whom # the Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL # ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. SUBDIRS = src man MAINTAINERCLEANFILES = ChangeLog INSTALL .PHONY: ChangeLog INSTALL INSTALL: $(INSTALL_CMD) ChangeLog: $(CHANGELOG_CMD) EXTRA_DIST = ChangeLog INSTALL xserver-xorg-video-ati-7.5.0+git20150819/README000066400000000000000000000013121256524674500203630ustar00rootroot00000000000000xf86-video-ati - ATI Radeon video driver for the Xorg X server All questions regarding this software should be directed at the Xorg mailing list: http://lists.freedesktop.org/mailman/listinfo/xorg Please submit bug reports to the Xorg bugzilla: https://bugs.freedesktop.org/enter_bug.cgi?product=xorg The master development code repository can be found at: git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati http://cgit.freedesktop.org/xorg/driver/xf86-video-ati For patch submission instructions, see: http://www.x.org/wiki/Development/Documentation/SubmittingPatches For more information on the git code manager, see: http://wiki.x.org/wiki/GitPage xserver-xorg-video-ati-7.5.0+git20150819/autogen.sh000077500000000000000000000003521256524674500215070ustar00rootroot00000000000000#! /bin/sh srcdir=`dirname $0` test -z "$srcdir" && srcdir=. ORIGDIR=`pwd` cd $srcdir autoreconf -v --install || exit 1 cd $ORIGDIR || exit $? if test -z "$NOCONFIGURE"; then $srcdir/configure --enable-maintainer-mode "$@" fi xserver-xorg-video-ati-7.5.0+git20150819/configure.ac000066400000000000000000000207031256524674500217760ustar00rootroot00000000000000# Copyright 2005 Adam Jackson. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # on the rights to use, copy, modify, merge, publish, distribute, sub # license, and/or sell copies of the Software, and to permit persons to whom # the Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL # ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Process this file with autoconf to produce a configure script # Initialize Autoconf AC_PREREQ([2.60]) AC_INIT([xf86-video-ati], [7.5.99], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], [xf86-video-ati]) AC_CONFIG_SRCDIR([Makefile.am]) AC_CONFIG_HEADERS([config.h]) AC_CONFIG_AUX_DIR(.) # Initialize Automake AM_INIT_AUTOMAKE([foreign dist-bzip2]) AC_SYS_LARGEFILE AM_MAINTAINER_MODE # Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS m4_ifndef([XORG_MACROS_VERSION], [m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])]) XORG_MACROS_VERSION(1.8) XORG_DEFAULT_OPTIONS # Initialize libtool AC_DISABLE_STATIC AC_PROG_LIBTOOL # Checks for programs. AM_PROG_CC_C_O if test "x$GCC" = "xyes"; then CPPFLAGS="$CPPFLAGS -Wall" fi AH_TOP([#include "xorg-server.h"]) # Define a configure option for an alternate module directory AC_ARG_WITH(xorg-module-dir, AS_HELP_STRING([--with-xorg-module-dir=DIR], [Default xorg module directory [[default=$libdir/xorg/modules]]]), [moduledir="$withval"], [moduledir="$libdir/xorg/modules"]) # Store the list of server defined optional extensions in REQUIRED_MODULES XORG_DRIVER_CHECK_EXT(RANDR, randrproto) XORG_DRIVER_CHECK_EXT(RENDER, renderproto) XORG_DRIVER_CHECK_EXT(XV, videoproto) XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) # Checks for libraries. PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.58]) PKG_CHECK_MODULES(LIBDRM_RADEON, [libdrm_radeon]) # Obtain compiler/linker options for the driver dependencies PKG_CHECK_MODULES(XORG, [xorg-server >= 1.8 xproto fontsproto xf86driproto $REQUIRED_MODULES]) PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1], HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, [xextproto 7.1 available]), HAVE_XEXTPROTO_71="no") AM_CONDITIONAL(HAVE_XEXTPROTO_71, [ test "$HAVE_XEXTPROTO_71" = "yes" ]) AC_ARG_ENABLE([udev], AS_HELP_STRING([--disable-udev], [Disable libudev support [default=auto]]), [enable_udev="$enableval"], [enable_udev=auto]) if test "x$enable_udev" != "xno"; then PKG_CHECK_MODULES(LIBUDEV, [libudev], [LIBUDEV=yes], [LIBUDEV=no]) if test "x$LIBUDEV" = xyes; then AC_DEFINE(HAVE_LIBUDEV, 1,[libudev support]) elif test "x$enable_udev" != "xauto"; then AC_MSG_ERROR([Building with udev requested but libudev not found]) fi fi AM_CONDITIONAL(LIBUDEV, test x$LIBUDEV = xyes) SAVE_CPPFLAGS="$CPPFLAGS" CPPFLAGS="$CPPFLAGS $XORG_CFLAGS" AC_MSG_CHECKING([whether to include GLAMOR support]) AC_ARG_ENABLE(glamor, AS_HELP_STRING([--disable-glamor], [Disable glamor, a new GL-based acceleration [default=enabled]]), [GLAMOR="$enableval"], [GLAMOR=yes]) if test "x$GLAMOR" != "xno"; then AC_CHECK_HEADERS([glamor.h], [GLAMOR_H="yes"], [GLAMOR_H="no"], [#include "xorg-server.h"]) if test "x$GLAMOR_H" = xyes; then AC_CHECK_DECL(GLAMOR_NO_DRI3, [GLAMOR_XSERVER="yes"], [GLAMOR_XSERVER="no"], [#include "xorg-server.h" #include "glamor.h"]) AC_CHECK_DECL(glamor_glyphs_init, [AC_DEFINE(HAVE_GLAMOR_GLYPHS_INIT, 1, [Have glamor_glyphs_init API])], [], [#include "xorg-server.h" #include "glamor.h"]) fi if test "x$GLAMOR_XSERVER" != xyes; then PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0]) PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl]) fi AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration]) else AC_MSG_RESULT([$GLAMOR]) fi AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno) AC_CHECK_DECL(fbGlyphs, [AC_DEFINE(HAVE_FBGLYPHS, 1, [Have fbGlyphs API])], [], [#include #include #include #include #include #include #include ]) AC_CHECK_DECL(xorg_list_init, [AC_DEFINE(HAVE_XORG_LIST, 1, [Have xorg_list API])], [], [#include #include "xorg-server.h" #include "list.h"]) AC_CHECK_HEADERS([misyncshm.h], [], [], [#include #include #include #include ]) AC_CHECK_HEADERS([present.h], [], [], [#include #include #include #include "xorg-server.h"]) AC_CHECK_HEADERS([dri3.h], [], [], [#include #include ]) CPPFLAGS="$SAVE_CPPFLAGS" PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0]) XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS" # Checks for headers/macros for byte swapping # Known variants: # bswap_16, bswap_32, bswap_64 (glibc) # __swap16, __swap32, __swap64 (OpenBSD) # bswap16, bswap32, bswap64 (other BSD's) # and a fallback to local macros if none of the above are found # if is found, assume it's the correct version AC_CHECK_HEADERS([byteswap.h]) # if is found, have to check which version AC_CHECK_HEADER([sys/endian.h], [HAVE_SYS_ENDIAN_H="yes"], [HAVE_SYS_ENDIAN_H="no"]) if test "x$HAVE_SYS_ENDIAN_H" = "xyes" ; then AC_MSG_CHECKING([for __swap16 variant of byteswapping macros]) AC_LINK_IFELSE([AC_LANG_PROGRAM([ #include #include ], [ int a = 1, b; b = __swap16(a); ]) ], [SYS_ENDIAN__SWAP='yes'], [SYS_ENDIAN__SWAP='no']) AC_MSG_RESULT([$SYS_ENDIAN__SWAP]) AC_MSG_CHECKING([for bswap16 variant of byteswapping macros]) AC_LINK_IFELSE([AC_LANG_PROGRAM([ #include #include ], [ int a = 1, b; b = bswap16(a); ]) ], [SYS_ENDIAN_BSWAP='yes'], [SYS_ENDIAN_BSWAP='no']) AC_MSG_RESULT([$SYS_ENDIAN_BSWAP]) if test "$SYS_ENDIAN_BSWAP" = "yes" ; then USE_SYS_ENDIAN_H=yes BSWAP=bswap else if test "$SYS_ENDIAN__SWAP" = "yes" ; then USE_SYS_ENDIAN_H=yes BSWAP=__swap else USE_SYS_ENDIAN_H=no fi fi if test "$USE_SYS_ENDIAN_H" = "yes" ; then AC_DEFINE([USE_SYS_ENDIAN_H], 1, [Define to use byteswap macros from ]) AC_DEFINE_UNQUOTED([bswap_16], ${BSWAP}16, [Define to 16-bit byteswap macro]) AC_DEFINE_UNQUOTED([bswap_32], ${BSWAP}32, [Define to 32-bit byteswap macro]) AC_DEFINE_UNQUOTED([bswap_64], ${BSWAP}64, [Define to 64-bit byteswap macro]) fi fi AC_SUBST([moduledir]) DRIVER_NAME=ati AC_SUBST([DRIVER_NAME]) AC_MSG_NOTICE( [The atimisc sub-driver has been split out to xf86-video-mach64:] [ git://anongit.freedesktop.org/git/xorg/driver/xf86-video-mach64] [Please install that driver as well for mach64-based cards.] ) AC_MSG_NOTICE( [The r128 sub-driver has been split out to xf86-video-r128:] [ git://anongit.freedesktop.org/git/xorg/driver/xf86-video-r128] [Please install that driver as well for rage128-based cards.] ) AC_CONFIG_FILES([ Makefile src/Makefile man/Makefile ]) AC_OUTPUT dnl dnl Output some configuration info for the user dnl echo "" echo " prefix: $prefix" echo " exec_prefix: $exec_prefix" echo " libdir: $libdir" echo " includedir: $includedir" echo "" echo " CFLAGS: $CFLAGS" echo " CXXFLAGS: $CXXFLAGS" echo " Macros: $DEFINES" echo "" echo " Run '${MAKE-make}' to build xf86-video-ati" echo "" xserver-xorg-video-ati-7.5.0+git20150819/man/000077500000000000000000000000001256524674500202615ustar00rootroot00000000000000xserver-xorg-video-ati-7.5.0+git20150819/man/Makefile.am000066400000000000000000000030341256524674500223150ustar00rootroot00000000000000# # Copyright 2005 Sun Microsystems, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER # DEALINGS IN THE SOFTWARE. # drivermandir = $(DRIVER_MAN_DIR) driverman_PRE = @DRIVER_NAME@.man radeon.man driverman_DATA = $(driverman_PRE:man=@DRIVER_MAN_SUFFIX@) EXTRA_DIST = @DRIVER_NAME@.man radeon.man CLEANFILES = $(driverman_DATA) # String replacements in MAN_SUBSTS now come from xorg-macros.m4 via configure SUFFIXES = .$(DRIVER_MAN_SUFFIX) .man .man.$(DRIVER_MAN_SUFFIX): $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@ xserver-xorg-video-ati-7.5.0+git20150819/man/ati.man000066400000000000000000000022071256524674500215340ustar00rootroot00000000000000.\" shorthand for double quote that works everywhere. .ds q \N'34' .TH ATI __drivermansuffix__ __vendorversion__ .SH NAME ati \- ATI video driver .SH SYNOPSIS .nf .B "Section \*qDevice\*q" .BI " Identifier \*q" devname \*q .B " Driver \*qati\*q" \ \ ... .B EndSection .fi .SH DESCRIPTION .B ati is an __xservername__ wrapper driver for ATI video cards. It autodetects whether your hardware has a Radeon, Rage 128, or Mach64 or earlier class of chipset, and loads the radeon(__drivermansuffix__), r128(__drivermansuffix__), or mach64 driver as appropriate. .SH SUPPORTED HARDWARE The .B ati driver supports Radeon, Rage 128, and Mach64 and earlier chipsets by loading those drivers. See those manpages for specific cards supported. .SH CONFIGURATION DETAILS Please refer to __xconfigfile__(__filemansuffix__) for general configuration details, and the specific card driver for driver configuration details. .SH "SEE ALSO" __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__), r128(__drivermansuffix__), radeon(__drivermansuffix__) .SH AUTHORS See the individual driver pages for authors. xserver-xorg-video-ati-7.5.0+git20150819/man/radeon.man000066400000000000000000000253461256524674500222400ustar00rootroot00000000000000.ds q \N'34' .TH RADEON __drivermansuffix__ __vendorversion__ .SH NAME radeon \- ATI/AMD RADEON video driver .SH SYNOPSIS .nf .B "Section \*qDevice\*q" .BI " Identifier \*q" devname \*q .B " Driver \*qradeon\*q" \ \ ... .B EndSection .fi .SH DESCRIPTION .B radeon is an __xservername__ driver for ATI/AMD RADEON-based video cards with the following features: .PP .PD 0 .TP 2 \(bu Full support for 8-, 15-, 16- and 24-bit pixel depths; .TP \(bu RandR 1.2 and RandR 1.3 support; .TP \(bu Full EXA 2D acceleration; .TP \(bu Textured XVideo acceleration including anti-tearing support (Bicubic filtering only available on R/RV3xx, R/RV/RS4xx, R/RV5xx, and RS6xx/RS740); .TP \(bu 3D acceleration; .PD .SH SUPPORTED HARDWARE The .B radeon driver supports PCI, AGP, and PCIe video cards based on the following ATI/AMD chips (note: list is non-exhaustive): .PP .PD 0 .TP 12 .B R100 Radeon 7200 .TP 12 .B RV100 Radeon 7000(VE), M6, RN50/ES1000 .TP 12 .B RS100 Radeon IGP320(M) .TP 12 .B RV200 Radeon 7500, M7, FireGL 7800 .TP 12 .B RS200 Radeon IGP330(M)/IGP340(M) .TP 12 .B RS250 Radeon Mobility 7000 IGP .TP 12 .B R200 Radeon 8500, 9100, FireGL 8800/8700 .TP 12 .B RV250 Radeon 9000PRO/9000, M9 .TP 12 .B RV280 Radeon 9200PRO/9200/9200SE/9250, M9+ .TP 12 .B RS300 Radeon 9100 IGP .TP 12 .B RS350 Radeon 9200 IGP .TP 12 .B RS400/RS480 Radeon XPRESS 200(M)/1100 IGP .TP 12 .B R300 Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1 .TP 12 .B R350 Radeon 9800PRO/9800SE/9800, FireGL X2 .TP 12 .B R360 Radeon 9800XT .TP 12 .B RV350 Radeon 9600PRO/9600SE/9600/9550, M10/M11, FireGL T2 .TP 12 .B RV360 Radeon 9600XT .TP 12 .B RV370 Radeon X300, M22 .TP 12 .B RV380 Radeon X600, M24 .TP 12 .B RV410 Radeon X700, M26 PCIe .TP 12 .B R420 Radeon X800 AGP .TP 12 .B R423/R430 Radeon X800, M28 PCIe .TP 12 .B R480/R481 Radeon X850 PCIe/AGP .TP 12 .B RV505/RV515/RV516/RV550 Radeon X1300/X1400/X1500/X1550/X2300 .TP 12 .B R520 Radeon X1800 .TP 12 .B RV530/RV560 Radeon X1600/X1650/X1700 .TP 12 .B RV570/R580 Radeon X1900/X1950 .TP 12 .B RS600/RS690/RS740 Radeon X1200/X1250/X2100 .TP 12 .B R600 Radeon HD 2900 .TP 12 .B RV610/RV630 Radeon HD 2400/2600/2700/4200/4225/4250 .TP 12 .B RV620/RV635 Radeon HD 3410/3430/3450/3470/3650/3670 .TP 12 .B RV670 Radeon HD 3690/3850/3870 .TP 12 .B RS780/RS880 Radeon HD 3100/3200/3300/4100/4200/4250/4290 .TP 12 .B RV710/RV730 Radeon HD 4330/4350/4550/4650/4670/5145/5165/530v/545v/560v/565v .TP 12 .B RV740/RV770/RV790 Radeon HD 4770/4730/4830/4850/4860/4870/4890 .TP 12 .B CEDAR Radeon HD 5430/5450/6330/6350/6370 .TP 12 .B REDWOOD Radeon HD 5550/5570/5650/5670/5730/5750/5770/6530/6550/6570 .TP 12 .B JUNIPER Radeon HD 5750/5770/5830/5850/5870/6750/6770/6830/6850/6870 .TP 12 .B CYPRESS Radeon HD 5830/5850/5870 .TP 12 .B HEMLOCK Radeon HD 5970 .TP 12 .B PALM Radeon HD 6310/6250 .TP 12 .B SUMO/SUMO2 Radeon HD 6370/6380/6410/6480/6520/6530/6550/6620 .TP 12 .B BARTS Radeon HD 6790/6850/6870/6950/6970/6990 .TP 12 .B TURKS Radeon HD 6570/6630/6650/6670/6730/6750/6770 .TP 12 .B CAICOS Radeon HD 6430/6450/6470/6490 .TP 12 .B CAYMAN Radeon HD 6950/6970/6990 .TP 12 .B ARUBA Radeon HD 7000 series .TP 12 .B TAHITI Radeon HD 7900 series .TP 12 .B PITCAIRN Radeon HD 7800 series .TP 12 .B VERDE Radeon HD 7700 series .TP 12 .B OLAND Radeon HD 8000 series .TP 12 .B HAINAN Radeon HD 8000 series .TP 12 .B BONAIRE Radeon HD 7790 series .TP 12 .B KAVERI KAVERI APUs .TP 12 .B KABINI KABINI APUs .TP 12 .B HAWAII Radeon R9 series .TP 12 .B MULLINS MULLINS APUs .PD .SH CONFIGURATION DETAILS Please refer to __xconfigfile__(__filemansuffix__) for general configuration details. This section only covers configuration details specific to this driver. .PP The following driver .B Options are supported: .TP .BI "Option \*qSWcursor\*q \*q" boolean \*q Selects software cursor. The default is .B off. .TP .BI "Option \*qAccel\*q \*q" boolean \*q Enables or disables all hardware acceleration. .br The default is .B on. .TP .BI "Option \*qZaphodHeads\*q \*q" string \*q Specify the RandR output(s) to use with zaphod mode for a particular driver instance. If you use this option you must use this option for all instances of the driver. .br For example: .B Option \*qZaphodHeads\*q \*qLVDS,VGA-0\*q will assign xrandr outputs LVDS and VGA-0 to this instance of the driver. .TP .BI "Option \*qColorTiling\*q \*q" "boolean" \*q The framebuffer can be addressed either in linear or tiled mode. Tiled mode can provide significant performance benefits with 3D applications. Tiling will be disabled if the drm module is too old or if the current display configuration does not support it. On R600+ this enables 1D tiling mode. .br The default value is .B on for R/RV3XX, R/RV4XX, R/RV5XX, RS6XX, RS740, R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, ARUBA, Southern Islands, and Sea Islands and .B off for R/RV/RS1XX, R/RV/RS2XX, RS3XX, and RS690/RS780/RS880 when fast fb feature is enabled. .TP .BI "Option \*qColorTiling2D\*q \*q" "boolean" \*q The framebuffer can be addressed either in linear, 1D, or 2D tiled modes. 2D tiled mode can provide significant performance benefits over 1D tiling with 3D applications. Tiling will be disabled if the drm module is too old or if the current display configuration does not support it. KMS ColorTiling2D is only supported on R600 and newer chips and requires Mesa 9.0 or newer for R6xx-ARUBA, Mesa 9.2 or newer for Southern Islands, and Mesa 10.1 or newer for Sea Islands. .br The default value is .B on for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, ARUBA, Southern Islands, and Sea Islands. .TP .BI "Option \*qDRI\*q \*q" integer \*q Define the maximum level of DRI to enable. Valid values are 2 for DRI2 or 3 for DRI3. The default is .B 2 for DRI2. .TP .BI "Option \*qEnablePageFlip\*q \*q" boolean \*q Enable DRI2 page flipping. The default is .B on. Pageflipping is supported on all radeon hardware. .TP .BI "Option \*qTearFree\*q \*q" boolean \*q Enable tearing prevention using the hardware page flipping mechanism. This option currently doesn't have any effect for rotated CRTCs. It requires allocating two separate scanout buffers for each non-rotated CRTC. Enabling this option currently disables Option \*qEnablePageFlip\*q. The default is .B off. .TP .BI "Option \*qAccelMethod\*q \*q" "string" \*q Chooses between available acceleration architectures. Valid values are .B EXA (for pre-TAHITI GPUs) and .B glamor (for R300 or higher). The default is .B glamor as of TAHITI, otherwise .B EXA. .PP The following driver .B Options are supported for .B glamor : .TP .BI "Option \*qShadowPrimary\*q \*q" boolean \*q This option enables a so-called "shadow primary" buffer for fast CPU access to pixel data, and separate scanout buffers for each display controller (CRTC). This may improve performance for some 2D workloads, potentially at the expense of other (e.g. 3D, video) workloads. Note in particular that enabling this option currently disables page flipping. The default is .B off. .PP The following driver .B Options are supported for .B EXA : .TP .BI "Option \*qEXAVSync\*q \*q" boolean \*q This option attempts to avoid tearing by stalling the engine until the display controller has passed the destination region. It reduces tearing at the cost of performance and has been known to cause instability on some chips. The default is .B off. .TP .BI "Option \*qEXAPixmaps\*q \*q" boolean \*q Under KMS, to avoid thrashing pixmaps in/out of VRAM on low memory cards, we use a heuristic based on VRAM amount to determine whether to allow EXA to use VRAM for non-essential pixmaps. This option allows us to override the heuristic. The default is .B on with > 32MB VRAM, off with < 32MB or when fast fb feature is enabled for RS690/RS780/RS880. .TP .BI "Option \*qSwapbuffersWait\*q \*q" boolean \*q This option controls the behavior of glXSwapBuffers and glXCopySubBufferMESA calls by GL applications. If enabled, the calls will avoid tearing by making sure the display scanline is outside of the area to be copied before the copy occurs. If disabled, no scanline synchronization is performed, meaning tearing will likely occur. Note that when enabled, this option can adversely affect the framerate of applications that render frames at less than refresh rate. .IP The default value is .B on. .SH TEXTURED VIDEO ATTRIBUTES The driver supports the following X11 Xv attributes for Textured Video. You can use the "xvattr" tool to query/set those attributes at runtime. .TP .BI "XV_VSYNC" XV_VSYNC is used to control whether textured adapter synchronizes the screen update to the monitor vertical refresh to eliminate tearing. It has two values: 'off'(0) and 'on'(1). The default is .B 'on'(1). .TP .BI "XV_CRTC" XV_CRTC is used to control which display controller (crtc) the textured adapter synchronizes the screen update with when XV_VSYNC is enabled. The default, 'auto'(-1), will sync to the display controller that more of the video is on; when this is ambiguous, the display controller associated with the RandR primary output is preferred. This attribute is useful for things like clone mode where the user can best decide which display should be synced. The default is .B 'auto'(-1). .TP .BI "XV_BICUBIC" XV_BICUBIC is used to control whether textured adapter should apply a bicubic filter to smooth the output. It has three values: 'off'(0), 'on'(1) and 'auto'(2). 'off' means never apply the filter, 'on' means always apply the filter and 'auto' means apply the filter only if the X and Y sizes are scaled to more than double to avoid blurred output. Bicubic filtering is not currently compatible with other Xv attributes like hue, contrast, and brightness, and must be disabled to use those attributes. The default is .B 'off'(0). .SH SEE ALSO __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) .IP " 1." 4 Wiki page: .RS 4 http://www.x.org/wiki/radeon .RE .IP " 2." 4 Overview about radeon development code: .RS 4 http://cgit.freedesktop.org/xorg/driver/xf86-video-ati/ .RE .IP " 3." 4 Mailing list: .RS 4 http://lists.x.org/mailman/listinfo/xorg-driver-ati .RE .IP " 4." 4 IRC channel: .RS 4 #radeon on irc.freenode.net .RE .IP " 5." 4 Query the bugtracker for radeon bugs: .RS 4 https://bugs.freedesktop.org/query.cgi?product=xorg&component=Driver/Radeon .RE .IP " 6." 4 Submit bugs & patches: .RS 4 https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/Radeon .RE .SH AUTHORS .nf Authors include: Rickard E. (Rik) Faith \fIfaith@precisioninsight.com\fP Kevin E. Martin \fIkem@freedesktop.org\fP Alan Hourihane \fIalanh@fairlite.demon.co.uk\fP Marc Aurele La France \fItsi@xfree86.org\fP Benjamin Herrenschmidt \fIbenh@kernel.crashing.org\fP Michel D\(:anzer \fImichel@daenzer.net\fP Alex Deucher \fIalexdeucher@gmail.com\fP Bogdan D. \fIbogdand@users.sourceforge.net\fP Eric Anholt \fIeric@anholt.net\fP xserver-xorg-video-ati-7.5.0+git20150819/src/000077500000000000000000000000001256524674500202755ustar00rootroot00000000000000xserver-xorg-video-ati-7.5.0+git20150819/src/.gitignore000066400000000000000000000001121256524674500222570ustar00rootroot00000000000000# Add & Override for this directory and it's subdirectories modes parser xserver-xorg-video-ati-7.5.0+git20150819/src/Makefile.am000066400000000000000000000070531256524674500223360ustar00rootroot00000000000000# Copyright 2005 Adam Jackson. # Copyright 2005 Red Hat, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # on the rights to use, copy, modify, merge, publish, distribute, sub # license, and/or sell copies of the Software, and to permit persons to whom # the Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL # ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # this is obnoxious: # -module lets us name the module exactly how we want # -avoid-version prevents gratuitous .0.0.0 version numbers on the end # _ladir passes a dummy rpath to libtool so the thing will actually link # TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc. ati_drv_la_LIBADD = $(PCIACCESS_LIBS) radeon_drv_la_LIBADD = $(LIBDRM_RADEON_LIBS) RADEON_KMS_SRCS=radeon_dri2.c radeon_dri3.c radeon_drm_queue.c radeon_kms.c \ radeon_present.c radeon_sync.c radeon_vbo.c radeon_bo_helper.c \ drmmode_display.c RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c \ evergreen_exa.c evergreen_accel.c evergreen_shader.c evergreen_textured_videofuncs.c cayman_accel.c cayman_shader.c AM_CFLAGS = \ @LIBDRM_RADEON_CFLAGS@ \ @XORG_CFLAGS@ \ @LIBUDEV_CFLAGS@ if LIBUDEV radeon_drv_la_LIBADD += $(LIBUDEV_LIBS) endif ati_drv_la_LTLIBRARIES = ati_drv.la ati_drv_la_LDFLAGS = -module -avoid-version ati_drv_ladir = @moduledir@/drivers ati_drv_la_SOURCES = \ ati.c atimodule.c radeon_drv_la_LTLIBRARIES = radeon_drv.la radeon_drv_la_LDFLAGS = -module -avoid-version radeon_drv_ladir = @moduledir@/drivers radeon_drv_la_SOURCES = \ radeon_accel.c radeon_video.c \ radeon_misc.c radeon_probe.c \ radeon_textured_video.c radeon_xvmc.c \ $(RADEON_EXA_SOURCES) \ $(RADEON_KMS_SRCS) if GLAMOR AM_CFLAGS += @LIBGLAMOR_CFLAGS@ radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ radeon_drv_la_SOURCES += \ radeon_glamor_wrappers.c \ radeon_glamor.c endif EXTRA_DIST = \ radeon_textured_videofuncs.c \ r600_reg.h \ r600_reg_auto_r6xx.h \ r600_reg_r6xx.h \ r600_reg_r7xx.h \ r600_shader.h \ r600_state.h \ evergreen_reg.h \ evergreen_reg_auto.h \ evergreen_shader.h \ evergreen_state.h \ cayman_reg.h \ cayman_reg_auto.h \ cayman_shader.h \ compat-api.h \ ati.h \ ativersion.h \ bicubic_table.h \ bicubic_table.py \ radeon_bo_helper.h \ radeon_drm_queue.h \ radeon_exa_render.c \ radeon_exa_funcs.c \ radeon_exa_shared.h \ radeon_glamor.h \ radeon.h \ radeon_list.h \ radeon_probe.h \ radeon_reg.h \ radeon_version.h \ radeon_vbo.h \ radeon_video.h \ simple_list.h \ atipciids.h \ atipcirename.h \ ati_pciids_gen.h \ radeon_chipinfo_gen.h \ radeon_chipset_gen.h \ radeon_pci_chipset_gen.h \ radeon_pci_device_match_gen.h \ pcidb/ati_pciids.csv \ pcidb/parse_pci_ids.pl \ radeon_dri2.h \ drmmode_display.h xserver-xorg-video-ati-7.5.0+git20150819/src/ati.c000066400000000000000000000240031256524674500212150ustar00rootroot00000000000000/* * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ /*************************************************************************/ /* * Author: Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * This is the ATI driver for XFree86. * * John Donne once said "No man is an island", and I am most certainly not an * exception. Contributions, intentional or not, to this and previous versions * of this driver by the following are hereby acknowledged: * * Thomas Roell, Per Lindqvist, Doug Evans, Rik Faith, Arthur Tateishi, * Alain Hebert, Ton van Rosmalen, David Chambers, William Shubert, * ATI Technologies Incorporated, Robert Wolff, David Dawes, Mark Weaver, * Hans Nasten, Kevin Martin, Frederic Rienthaler, Marc Bolduc, Reuben Sumner, * Benjamin T. Yang, James Fast Kane, Randall Hopper, W. Marcus Miller, * Henrik Harmsen, Christian Lupien, Precision Insight Incorporated, * Mark Vojkovich, Huw D M Davies, Andrew C Aitchison, Ani Joshi, * Kostas Gewrgiou, Jakub Jelinek, David S. Miller, A E Lawrence, * Linus Torvalds, William Blew, Ignacio Garcia Etxebarria, Patrick Chase, * Vladimir Dergachev, Egbert Eich, Mike A. Harris * * ... and, many, many others from around the world. * * In addition, this work would not have been possible without the active * support, both moral and otherwise, of the staff and management of Computing * and Network Services at the University of Alberta, in Edmonton, Alberta, * Canada. * * The driver is intended to support all ATI adapters since their VGA Wonder * V3, including OEM counterparts. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include "atipcirename.h" #include "ati.h" #include "atipciids.h" #include "ativersion.h" /* names duplicated from version headers */ #define MACH64_DRIVER_NAME "mach64" #define R128_DRIVER_NAME "r128" #define RADEON_DRIVER_NAME "radeon" enum { ATI_CHIP_FAMILY_NONE = 0, ATI_CHIP_FAMILY_Mach64, ATI_CHIP_FAMILY_Rage128, ATI_CHIP_FAMILY_Radeon }; static int ATIChipID(const uint16_t); /* domain defines (stolen from xserver) */ #if (defined(__alpha__) || defined(__ia64__)) && defined (linux) # define PCI_DOM_MASK 0x01fful #else # define PCI_DOM_MASK 0x0ffu #endif #define PCI_DOM_FROM_BUS(bus) (((bus) >> 8) & (PCI_DOM_MASK)) #define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu) static struct pci_device* ati_device_get_from_busid(int bus, int dev, int func) { return pci_device_find_by_slot(PCI_DOM_FROM_BUS(bus), PCI_BUS_NO_DOMAIN(bus), dev, func); } #ifndef XSERVER_PLATFORM_BUS static struct pci_device* ati_device_get_primary(void) { struct pci_device *device = NULL; struct pci_device_iterator *device_iter; device_iter = pci_slot_match_iterator_create(NULL); while ((device = pci_device_next(device_iter)) != NULL) { if (xf86IsPrimaryPci(device)) break; } pci_iterator_destroy(device_iter); return device; } #else static struct pci_device * ati_device_get_indexed(int index) { struct pci_device *device = NULL; struct pci_device_iterator *device_iter; int count = 0; device_iter = pci_slot_match_iterator_create(NULL); while ((device = pci_device_next(device_iter)) != NULL) { if (device->vendor_id == PCI_VENDOR_ATI) { if (count == index) return device; count++; } } return NULL; } #endif void ati_gdev_subdriver(pointer options) { int nATIGDev, nMach64GDev, nR128GDev, nRadeonGDev; GDevPtr *ATIGDevs; Bool load_mach64 = FALSE, load_r128 = FALSE, load_radeon = FALSE; int i; /* let the subdrivers configure for themselves */ if (xf86ServerIsOnlyDetecting()) return; /* get Device sections with Driver "ati" */ nATIGDev = xf86MatchDevice(ATI_DRIVER_NAME, &ATIGDevs); nMach64GDev = xf86MatchDevice(MACH64_DRIVER_NAME, NULL); nR128GDev = xf86MatchDevice(R128_DRIVER_NAME, NULL); nRadeonGDev = xf86MatchDevice(RADEON_DRIVER_NAME, NULL); for (i = 0; i < nATIGDev; i++) { GDevPtr ati_gdev = ATIGDevs[i]; pciVideoPtr device = NULL; int chip_family; /* get pci device for the Device section */ if (ati_gdev->busID) { int bus, dev, func; if (!xf86ParsePciBusString(ati_gdev->busID, &bus, &dev, &func)) continue; device = ati_device_get_from_busid(bus, dev, func); } #ifdef XSERVER_PLATFORM_BUS else device = ati_device_get_indexed(i); #else else { device = ati_device_get_primary(); } #endif if (!device) continue; /* check for non-ati devices and prehistoric mach32 */ if ((PCI_DEV_VENDOR_ID(device) != PCI_VENDOR_ATI) || (PCI_DEV_DEVICE_ID(device) == PCI_CHIP_MACH32)) continue; /* replace Driver line in the Device section */ chip_family = ATIChipID(PCI_DEV_DEVICE_ID(device)); if (chip_family == ATI_CHIP_FAMILY_Mach64) { ati_gdev->driver = MACH64_DRIVER_NAME; load_mach64 = TRUE; } if (chip_family == ATI_CHIP_FAMILY_Rage128) { ati_gdev->driver = R128_DRIVER_NAME; load_r128 = TRUE; } if (chip_family == ATI_CHIP_FAMILY_Radeon) { ati_gdev->driver = RADEON_DRIVER_NAME; load_radeon = TRUE; } } free(ATIGDevs); /* load subdrivers as primary modules and only if they do not get loaded * from other device sections */ if (load_mach64 && (nMach64GDev == 0)) xf86LoadOneModule(MACH64_DRIVER_NAME, options); if (load_r128 && (nR128GDev == 0)) xf86LoadOneModule(R128_DRIVER_NAME, options); if (load_radeon && (nRadeonGDev == 0)) xf86LoadOneModule(RADEON_DRIVER_NAME, options); } /* * ATIChipID -- * * This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID. */ static int ATIChipID(const uint16_t ChipID) { switch (ChipID) { case PCI_CHIP_MACH64GX: case PCI_CHIP_MACH64CX: case PCI_CHIP_MACH64CT: case PCI_CHIP_MACH64ET: case PCI_CHIP_MACH64VT: case PCI_CHIP_MACH64GT: case PCI_CHIP_MACH64VU: case PCI_CHIP_MACH64GU: case PCI_CHIP_MACH64LG: case PCI_CHIP_MACH64VV: case PCI_CHIP_MACH64GV: case PCI_CHIP_MACH64GW: case PCI_CHIP_MACH64GY: case PCI_CHIP_MACH64GZ: case PCI_CHIP_MACH64GB: case PCI_CHIP_MACH64GD: case PCI_CHIP_MACH64GI: case PCI_CHIP_MACH64GP: case PCI_CHIP_MACH64GQ: case PCI_CHIP_MACH64LB: case PCI_CHIP_MACH64LD: case PCI_CHIP_MACH64LI: case PCI_CHIP_MACH64LP: case PCI_CHIP_MACH64LQ: case PCI_CHIP_MACH64GL: case PCI_CHIP_MACH64GM: case PCI_CHIP_MACH64GN: case PCI_CHIP_MACH64GO: case PCI_CHIP_MACH64GR: case PCI_CHIP_MACH64GS: case PCI_CHIP_MACH64LM: case PCI_CHIP_MACH64LN: case PCI_CHIP_MACH64LR: case PCI_CHIP_MACH64LS: return ATI_CHIP_FAMILY_Mach64; case PCI_CHIP_RAGE128RE: case PCI_CHIP_RAGE128RF: case PCI_CHIP_RAGE128RG: case PCI_CHIP_RAGE128SK: case PCI_CHIP_RAGE128SL: case PCI_CHIP_RAGE128SM: case PCI_CHIP_RAGE128SN: case PCI_CHIP_RAGE128RK: case PCI_CHIP_RAGE128RL: case PCI_CHIP_RAGE128SE: case PCI_CHIP_RAGE128SF: case PCI_CHIP_RAGE128SG: case PCI_CHIP_RAGE128SH: case PCI_CHIP_RAGE128PA: case PCI_CHIP_RAGE128PB: case PCI_CHIP_RAGE128PC: case PCI_CHIP_RAGE128PD: case PCI_CHIP_RAGE128PE: case PCI_CHIP_RAGE128PF: case PCI_CHIP_RAGE128PG: case PCI_CHIP_RAGE128PH: case PCI_CHIP_RAGE128PI: case PCI_CHIP_RAGE128PJ: case PCI_CHIP_RAGE128PK: case PCI_CHIP_RAGE128PL: case PCI_CHIP_RAGE128PM: case PCI_CHIP_RAGE128PN: case PCI_CHIP_RAGE128PO: case PCI_CHIP_RAGE128PP: case PCI_CHIP_RAGE128PQ: case PCI_CHIP_RAGE128PR: case PCI_CHIP_RAGE128PS: case PCI_CHIP_RAGE128PT: case PCI_CHIP_RAGE128PU: case PCI_CHIP_RAGE128PV: case PCI_CHIP_RAGE128PW: case PCI_CHIP_RAGE128PX: case PCI_CHIP_RAGE128TF: case PCI_CHIP_RAGE128TL: case PCI_CHIP_RAGE128TR: case PCI_CHIP_RAGE128TS: case PCI_CHIP_RAGE128TT: case PCI_CHIP_RAGE128TU: case PCI_CHIP_RAGE128LE: case PCI_CHIP_RAGE128LF: #if 0 case PCI_CHIP_RAGE128LK: case PCI_CHIP_RAGE128LL: #endif case PCI_CHIP_RAGE128MF: case PCI_CHIP_RAGE128ML: return ATI_CHIP_FAMILY_Rage128; default: return ATI_CHIP_FAMILY_Radeon; } } xserver-xorg-video-ati-7.5.0+git20150819/src/ati.h000066400000000000000000000026751256524674500212350ustar00rootroot00000000000000/* * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef ___ATI_H___ #define ___ATI_H___ 1 #include #include #include "xf86Pci.h" #include "xf86.h" #include "xf86_OSproc.h" extern void ati_gdev_subdriver(pointer options); #endif /* ___ATI_H___ */ xserver-xorg-video-ati-7.5.0+git20150819/src/ati_pciids_gen.h000066400000000000000000000652051256524674500234170ustar00rootroot00000000000000#define PCI_CHIP_RV380_3150 0x3150 #define PCI_CHIP_RV380_3151 0x3151 #define PCI_CHIP_RV380_3152 0x3152 #define PCI_CHIP_RV380_3154 0x3154 #define PCI_CHIP_RV380_3155 0x3155 #define PCI_CHIP_RV380_3E50 0x3E50 #define PCI_CHIP_RV380_3E54 0x3E54 #define PCI_CHIP_RS100_4136 0x4136 #define PCI_CHIP_RS200_4137 0x4137 #define PCI_CHIP_R300_AD 0x4144 #define PCI_CHIP_R300_AE 0x4145 #define PCI_CHIP_R300_AF 0x4146 #define PCI_CHIP_R300_AG 0x4147 #define PCI_CHIP_R350_AH 0x4148 #define PCI_CHIP_R350_AI 0x4149 #define PCI_CHIP_R350_AJ 0x414A #define PCI_CHIP_R350_AK 0x414B #define PCI_CHIP_RV350_AP 0x4150 #define PCI_CHIP_RV350_AQ 0x4151 #define PCI_CHIP_RV360_AR 0x4152 #define PCI_CHIP_RV350_AS 0x4153 #define PCI_CHIP_RV350_AT 0x4154 #define PCI_CHIP_RV350_4155 0x4155 #define PCI_CHIP_RV350_AV 0x4156 #define PCI_CHIP_MACH32 0x4158 #define PCI_CHIP_RS250_4237 0x4237 #define PCI_CHIP_R200_BB 0x4242 #define PCI_CHIP_RS100_4336 0x4336 #define PCI_CHIP_RS200_4337 0x4337 #define PCI_CHIP_MACH64CT 0x4354 #define PCI_CHIP_MACH64CX 0x4358 #define PCI_CHIP_RS250_4437 0x4437 #define PCI_CHIP_MACH64ET 0x4554 #define PCI_CHIP_MACH64GB 0x4742 #define PCI_CHIP_MACH64GD 0x4744 #define PCI_CHIP_MACH64GI 0x4749 #define PCI_CHIP_MACH64GL 0x474C #define PCI_CHIP_MACH64GM 0x474D #define PCI_CHIP_MACH64GN 0x474E #define PCI_CHIP_MACH64GO 0x474F #define PCI_CHIP_MACH64GP 0x4750 #define PCI_CHIP_MACH64GQ 0x4751 #define PCI_CHIP_MACH64GR 0x4752 #define PCI_CHIP_MACH64GS 0x4753 #define PCI_CHIP_MACH64GT 0x4754 #define PCI_CHIP_MACH64GU 0x4755 #define PCI_CHIP_MACH64GV 0x4756 #define PCI_CHIP_MACH64GW 0x4757 #define PCI_CHIP_MACH64GX 0x4758 #define PCI_CHIP_MACH64GY 0x4759 #define PCI_CHIP_MACH64GZ 0x475A #define PCI_CHIP_RV250_If 0x4966 #define PCI_CHIP_RV250_Ig 0x4967 #define PCI_CHIP_R420_JH 0x4A48 #define PCI_CHIP_R420_JI 0x4A49 #define PCI_CHIP_R420_JJ 0x4A4A #define PCI_CHIP_R420_JK 0x4A4B #define PCI_CHIP_R420_JL 0x4A4C #define PCI_CHIP_R420_JM 0x4A4D #define PCI_CHIP_R420_JN 0x4A4E #define PCI_CHIP_R420_4A4F 0x4A4F #define PCI_CHIP_R420_JP 0x4A50 #define PCI_CHIP_R420_JT 0x4A54 #define PCI_CHIP_R481_4B48 0x4B48 #define PCI_CHIP_R481_4B49 0x4B49 #define PCI_CHIP_R481_4B4A 0x4B4A #define PCI_CHIP_R481_4B4B 0x4B4B #define PCI_CHIP_R481_4B4C 0x4B4C #define PCI_CHIP_MACH64LB 0x4C42 #define PCI_CHIP_MACH64LD 0x4C44 #define PCI_CHIP_RAGE128LE 0x4C45 #define PCI_CHIP_RAGE128LF 0x4C46 #define PCI_CHIP_MACH64LG 0x4C47 #define PCI_CHIP_MACH64LI 0x4C49 #define PCI_CHIP_MACH64LM 0x4C4D #define PCI_CHIP_MACH64LN 0x4C4E #define PCI_CHIP_MACH64LP 0x4C50 #define PCI_CHIP_MACH64LQ 0x4C51 #define PCI_CHIP_MACH64LR 0x4C52 #define PCI_CHIP_MACH64LS 0x4C53 #define PCI_CHIP_RADEON_LW 0x4C57 #define PCI_CHIP_RADEON_LX 0x4C58 #define PCI_CHIP_RADEON_LY 0x4C59 #define PCI_CHIP_RADEON_LZ 0x4C5A #define PCI_CHIP_RV250_Ld 0x4C64 #define PCI_CHIP_RV250_Lf 0x4C66 #define PCI_CHIP_RV250_Lg 0x4C67 #define PCI_CHIP_RV280_4C6E 0x4C6E #define PCI_CHIP_RAGE128MF 0x4D46 #define PCI_CHIP_RAGE128ML 0x4D4C #define PCI_CHIP_R300_ND 0x4E44 #define PCI_CHIP_R300_NE 0x4E45 #define PCI_CHIP_R300_NF 0x4E46 #define PCI_CHIP_R300_NG 0x4E47 #define PCI_CHIP_R350_NH 0x4E48 #define PCI_CHIP_R350_NI 0x4E49 #define PCI_CHIP_R360_NJ 0x4E4A #define PCI_CHIP_R350_NK 0x4E4B #define PCI_CHIP_RV350_NP 0x4E50 #define PCI_CHIP_RV350_NQ 0x4E51 #define PCI_CHIP_RV350_NR 0x4E52 #define PCI_CHIP_RV350_NS 0x4E53 #define PCI_CHIP_RV350_NT 0x4E54 #define PCI_CHIP_RV350_NV 0x4E56 #define PCI_CHIP_RAGE128PA 0x5041 #define PCI_CHIP_RAGE128PB 0x5042 #define PCI_CHIP_RAGE128PC 0x5043 #define PCI_CHIP_RAGE128PD 0x5044 #define PCI_CHIP_RAGE128PE 0x5045 #define PCI_CHIP_RAGE128PF 0x5046 #define PCI_CHIP_RAGE128PG 0x5047 #define PCI_CHIP_RAGE128PH 0x5048 #define PCI_CHIP_RAGE128PI 0x5049 #define PCI_CHIP_RAGE128PJ 0x504A #define PCI_CHIP_RAGE128PK 0x504B #define PCI_CHIP_RAGE128PL 0x504C #define PCI_CHIP_RAGE128PM 0x504D #define PCI_CHIP_RAGE128PN 0x504E #define PCI_CHIP_RAGE128PO 0x504F #define PCI_CHIP_RAGE128PP 0x5050 #define PCI_CHIP_RAGE128PQ 0x5051 #define PCI_CHIP_RAGE128PR 0x5052 #define PCI_CHIP_RAGE128PS 0x5053 #define PCI_CHIP_RAGE128PT 0x5054 #define PCI_CHIP_RAGE128PU 0x5055 #define PCI_CHIP_RAGE128PV 0x5056 #define PCI_CHIP_RAGE128PW 0x5057 #define PCI_CHIP_RAGE128PX 0x5058 #define PCI_CHIP_RADEON_QD 0x5144 #define PCI_CHIP_RADEON_QE 0x5145 #define PCI_CHIP_RADEON_QF 0x5146 #define PCI_CHIP_RADEON_QG 0x5147 #define PCI_CHIP_R200_QH 0x5148 #define PCI_CHIP_R200_QL 0x514C #define PCI_CHIP_R200_QM 0x514D #define PCI_CHIP_RV200_QW 0x5157 #define PCI_CHIP_RV200_QX 0x5158 #define PCI_CHIP_RV100_QY 0x5159 #define PCI_CHIP_RV100_QZ 0x515A #define PCI_CHIP_RN50_515E 0x515E #define PCI_CHIP_RAGE128RE 0x5245 #define PCI_CHIP_RAGE128RF 0x5246 #define PCI_CHIP_RAGE128RG 0x5247 #define PCI_CHIP_RAGE128RK 0x524B #define PCI_CHIP_RAGE128RL 0x524C #define PCI_CHIP_RAGE128SE 0x5345 #define PCI_CHIP_RAGE128SF 0x5346 #define PCI_CHIP_RAGE128SG 0x5347 #define PCI_CHIP_RAGE128SH 0x5348 #define PCI_CHIP_RAGE128SK 0x534B #define PCI_CHIP_RAGE128SL 0x534C #define PCI_CHIP_RAGE128SM 0x534D #define PCI_CHIP_RAGE128SN 0x534E #define PCI_CHIP_RAGE128TF 0x5446 #define PCI_CHIP_RAGE128TL 0x544C #define PCI_CHIP_RAGE128TR 0x5452 #define PCI_CHIP_RAGE128TS 0x5453 #define PCI_CHIP_RAGE128TT 0x5454 #define PCI_CHIP_RAGE128TU 0x5455 #define PCI_CHIP_RV370_5460 0x5460 #define PCI_CHIP_RV370_5462 0x5462 #define PCI_CHIP_RV370_5464 0x5464 #define PCI_CHIP_R423_UH 0x5548 #define PCI_CHIP_R423_UI 0x5549 #define PCI_CHIP_R423_UJ 0x554A #define PCI_CHIP_R423_UK 0x554B #define PCI_CHIP_R430_554C 0x554C #define PCI_CHIP_R430_554D 0x554D #define PCI_CHIP_R430_554E 0x554E #define PCI_CHIP_R430_554F 0x554F #define PCI_CHIP_R423_5550 0x5550 #define PCI_CHIP_R423_UQ 0x5551 #define PCI_CHIP_R423_UR 0x5552 #define PCI_CHIP_R423_UT 0x5554 #define PCI_CHIP_RV410_564A 0x564A #define PCI_CHIP_RV410_564B 0x564B #define PCI_CHIP_RV410_564F 0x564F #define PCI_CHIP_RV410_5652 0x5652 #define PCI_CHIP_RV410_5653 0x5653 #define PCI_CHIP_RV410_5657 0x5657 #define PCI_CHIP_MACH64VT 0x5654 #define PCI_CHIP_MACH64VU 0x5655 #define PCI_CHIP_MACH64VV 0x5656 #define PCI_CHIP_RS300_5834 0x5834 #define PCI_CHIP_RS300_5835 0x5835 #define PCI_CHIP_RS480_5954 0x5954 #define PCI_CHIP_RS480_5955 0x5955 #define PCI_CHIP_RV280_5960 0x5960 #define PCI_CHIP_RV280_5961 0x5961 #define PCI_CHIP_RV280_5962 0x5962 #define PCI_CHIP_RV280_5964 0x5964 #define PCI_CHIP_RV280_5965 0x5965 #define PCI_CHIP_RN50_5969 0x5969 #define PCI_CHIP_RS482_5974 0x5974 #define PCI_CHIP_RS485_5975 0x5975 #define PCI_CHIP_RS400_5A41 0x5A41 #define PCI_CHIP_RS400_5A42 0x5A42 #define PCI_CHIP_RC410_5A61 0x5A61 #define PCI_CHIP_RC410_5A62 0x5A62 #define PCI_CHIP_RV370_5B60 0x5B60 #define PCI_CHIP_RV370_5B62 0x5B62 #define PCI_CHIP_RV370_5B63 0x5B63 #define PCI_CHIP_RV370_5B64 0x5B64 #define PCI_CHIP_RV370_5B65 0x5B65 #define PCI_CHIP_RV280_5C61 0x5C61 #define PCI_CHIP_RV280_5C63 0x5C63 #define PCI_CHIP_R430_5D48 0x5D48 #define PCI_CHIP_R430_5D49 0x5D49 #define PCI_CHIP_R430_5D4A 0x5D4A #define PCI_CHIP_R480_5D4C 0x5D4C #define PCI_CHIP_R480_5D4D 0x5D4D #define PCI_CHIP_R480_5D4E 0x5D4E #define PCI_CHIP_R480_5D4F 0x5D4F #define PCI_CHIP_R480_5D50 0x5D50 #define PCI_CHIP_R480_5D52 0x5D52 #define PCI_CHIP_R423_5D57 0x5D57 #define PCI_CHIP_RV410_5E48 0x5E48 #define PCI_CHIP_RV410_5E4A 0x5E4A #define PCI_CHIP_RV410_5E4B 0x5E4B #define PCI_CHIP_RV410_5E4C 0x5E4C #define PCI_CHIP_RV410_5E4D 0x5E4D #define PCI_CHIP_RV410_5E4F 0x5E4F #define PCI_CHIP_R520_7100 0x7100 #define PCI_CHIP_R520_7101 0x7101 #define PCI_CHIP_R520_7102 0x7102 #define PCI_CHIP_R520_7103 0x7103 #define PCI_CHIP_R520_7104 0x7104 #define PCI_CHIP_R520_7105 0x7105 #define PCI_CHIP_R520_7106 0x7106 #define PCI_CHIP_R520_7108 0x7108 #define PCI_CHIP_R520_7109 0x7109 #define PCI_CHIP_R520_710A 0x710A #define PCI_CHIP_R520_710B 0x710B #define PCI_CHIP_R520_710C 0x710C #define PCI_CHIP_R520_710E 0x710E #define PCI_CHIP_R520_710F 0x710F #define PCI_CHIP_RV515_7140 0x7140 #define PCI_CHIP_RV515_7141 0x7141 #define PCI_CHIP_RV515_7142 0x7142 #define PCI_CHIP_RV515_7143 0x7143 #define PCI_CHIP_RV515_7144 0x7144 #define PCI_CHIP_RV515_7145 0x7145 #define PCI_CHIP_RV515_7146 0x7146 #define PCI_CHIP_RV515_7147 0x7147 #define PCI_CHIP_RV515_7149 0x7149 #define PCI_CHIP_RV515_714A 0x714A #define PCI_CHIP_RV515_714B 0x714B #define PCI_CHIP_RV515_714C 0x714C #define PCI_CHIP_RV515_714D 0x714D #define PCI_CHIP_RV515_714E 0x714E #define PCI_CHIP_RV515_714F 0x714F #define PCI_CHIP_RV515_7151 0x7151 #define PCI_CHIP_RV515_7152 0x7152 #define PCI_CHIP_RV515_7153 0x7153 #define PCI_CHIP_RV515_715E 0x715E #define PCI_CHIP_RV515_715F 0x715F #define PCI_CHIP_RV515_7180 0x7180 #define PCI_CHIP_RV515_7181 0x7181 #define PCI_CHIP_RV515_7183 0x7183 #define PCI_CHIP_RV515_7186 0x7186 #define PCI_CHIP_RV515_7187 0x7187 #define PCI_CHIP_RV515_7188 0x7188 #define PCI_CHIP_RV515_718A 0x718A #define PCI_CHIP_RV515_718B 0x718B #define PCI_CHIP_RV515_718C 0x718C #define PCI_CHIP_RV515_718D 0x718D #define PCI_CHIP_RV515_718F 0x718F #define PCI_CHIP_RV515_7193 0x7193 #define PCI_CHIP_RV515_7196 0x7196 #define PCI_CHIP_RV515_719B 0x719B #define PCI_CHIP_RV515_719F 0x719F #define PCI_CHIP_RV530_71C0 0x71C0 #define PCI_CHIP_RV530_71C1 0x71C1 #define PCI_CHIP_RV530_71C2 0x71C2 #define PCI_CHIP_RV530_71C3 0x71C3 #define PCI_CHIP_RV530_71C4 0x71C4 #define PCI_CHIP_RV530_71C5 0x71C5 #define PCI_CHIP_RV530_71C6 0x71C6 #define PCI_CHIP_RV530_71C7 0x71C7 #define PCI_CHIP_RV530_71CD 0x71CD #define PCI_CHIP_RV530_71CE 0x71CE #define PCI_CHIP_RV530_71D2 0x71D2 #define PCI_CHIP_RV530_71D4 0x71D4 #define PCI_CHIP_RV530_71D5 0x71D5 #define PCI_CHIP_RV530_71D6 0x71D6 #define PCI_CHIP_RV530_71DA 0x71DA #define PCI_CHIP_RV530_71DE 0x71DE #define PCI_CHIP_RV515_7200 0x7200 #define PCI_CHIP_RV515_7210 0x7210 #define PCI_CHIP_RV515_7211 0x7211 #define PCI_CHIP_R580_7240 0x7240 #define PCI_CHIP_R580_7243 0x7243 #define PCI_CHIP_R580_7244 0x7244 #define PCI_CHIP_R580_7245 0x7245 #define PCI_CHIP_R580_7246 0x7246 #define PCI_CHIP_R580_7247 0x7247 #define PCI_CHIP_R580_7248 0x7248 #define PCI_CHIP_R580_7249 0x7249 #define PCI_CHIP_R580_724A 0x724A #define PCI_CHIP_R580_724B 0x724B #define PCI_CHIP_R580_724C 0x724C #define PCI_CHIP_R580_724D 0x724D #define PCI_CHIP_R580_724E 0x724E #define PCI_CHIP_R580_724F 0x724F #define PCI_CHIP_RV570_7280 0x7280 #define PCI_CHIP_RV560_7281 0x7281 #define PCI_CHIP_RV560_7283 0x7283 #define PCI_CHIP_R580_7284 0x7284 #define PCI_CHIP_RV560_7287 0x7287 #define PCI_CHIP_RV570_7288 0x7288 #define PCI_CHIP_RV570_7289 0x7289 #define PCI_CHIP_RV570_728B 0x728B #define PCI_CHIP_RV570_728C 0x728C #define PCI_CHIP_RV560_7290 0x7290 #define PCI_CHIP_RV560_7291 0x7291 #define PCI_CHIP_RV560_7293 0x7293 #define PCI_CHIP_RV560_7297 0x7297 #define PCI_CHIP_RS350_7834 0x7834 #define PCI_CHIP_RS350_7835 0x7835 #define PCI_CHIP_RS690_791E 0x791E #define PCI_CHIP_RS690_791F 0x791F #define PCI_CHIP_RS600_793F 0x793F #define PCI_CHIP_RS600_7941 0x7941 #define PCI_CHIP_RS600_7942 0x7942 #define PCI_CHIP_RS740_796C 0x796C #define PCI_CHIP_RS740_796D 0x796D #define PCI_CHIP_RS740_796E 0x796E #define PCI_CHIP_RS740_796F 0x796F #define PCI_CHIP_R600_9400 0x9400 #define PCI_CHIP_R600_9401 0x9401 #define PCI_CHIP_R600_9402 0x9402 #define PCI_CHIP_R600_9403 0x9403 #define PCI_CHIP_R600_9405 0x9405 #define PCI_CHIP_R600_940A 0x940A #define PCI_CHIP_R600_940B 0x940B #define PCI_CHIP_R600_940F 0x940F #define PCI_CHIP_RV770_9440 0x9440 #define PCI_CHIP_RV770_9441 0x9441 #define PCI_CHIP_RV770_9442 0x9442 #define PCI_CHIP_RV770_9443 0x9443 #define PCI_CHIP_RV770_9444 0x9444 #define PCI_CHIP_RV770_9446 0x9446 #define PCI_CHIP_RV770_944A 0x944A #define PCI_CHIP_RV770_944B 0x944B #define PCI_CHIP_RV770_944C 0x944C #define PCI_CHIP_RV770_944E 0x944E #define PCI_CHIP_RV770_9450 0x9450 #define PCI_CHIP_RV770_9452 0x9452 #define PCI_CHIP_RV770_9456 0x9456 #define PCI_CHIP_RV770_945A 0x945A #define PCI_CHIP_RV770_945B 0x945B #define PCI_CHIP_RV770_945E 0x945E #define PCI_CHIP_RV790_9460 0x9460 #define PCI_CHIP_RV790_9462 0x9462 #define PCI_CHIP_RV770_946A 0x946A #define PCI_CHIP_RV770_946B 0x946B #define PCI_CHIP_RV770_947A 0x947A #define PCI_CHIP_RV770_947B 0x947B #define PCI_CHIP_RV730_9480 0x9480 #define PCI_CHIP_RV730_9487 0x9487 #define PCI_CHIP_RV730_9488 0x9488 #define PCI_CHIP_RV730_9489 0x9489 #define PCI_CHIP_RV730_948A 0x948A #define PCI_CHIP_RV730_948F 0x948F #define PCI_CHIP_RV730_9490 0x9490 #define PCI_CHIP_RV730_9491 0x9491 #define PCI_CHIP_RV730_9495 0x9495 #define PCI_CHIP_RV730_9498 0x9498 #define PCI_CHIP_RV730_949C 0x949C #define PCI_CHIP_RV730_949E 0x949E #define PCI_CHIP_RV730_949F 0x949F #define PCI_CHIP_RV740_94A0 0x94A0 #define PCI_CHIP_RV740_94A1 0x94A1 #define PCI_CHIP_RV740_94A3 0x94A3 #define PCI_CHIP_RV740_94B1 0x94B1 #define PCI_CHIP_RV740_94B3 0x94B3 #define PCI_CHIP_RV740_94B4 0x94B4 #define PCI_CHIP_RV740_94B5 0x94B5 #define PCI_CHIP_RV740_94B9 0x94B9 #define PCI_CHIP_RV610_94C0 0x94C0 #define PCI_CHIP_RV610_94C1 0x94C1 #define PCI_CHIP_RV610_94C3 0x94C3 #define PCI_CHIP_RV610_94C4 0x94C4 #define PCI_CHIP_RV610_94C5 0x94C5 #define PCI_CHIP_RV610_94C6 0x94C6 #define PCI_CHIP_RV610_94C7 0x94C7 #define PCI_CHIP_RV610_94C8 0x94C8 #define PCI_CHIP_RV610_94C9 0x94C9 #define PCI_CHIP_RV610_94CB 0x94CB #define PCI_CHIP_RV610_94CC 0x94CC #define PCI_CHIP_RV610_94CD 0x94CD #define PCI_CHIP_RV670_9500 0x9500 #define PCI_CHIP_RV670_9501 0x9501 #define PCI_CHIP_RV670_9504 0x9504 #define PCI_CHIP_RV670_9505 0x9505 #define PCI_CHIP_RV670_9506 0x9506 #define PCI_CHIP_RV670_9507 0x9507 #define PCI_CHIP_RV670_9508 0x9508 #define PCI_CHIP_RV670_9509 0x9509 #define PCI_CHIP_RV670_950F 0x950F #define PCI_CHIP_RV670_9511 0x9511 #define PCI_CHIP_RV670_9515 0x9515 #define PCI_CHIP_RV670_9517 0x9517 #define PCI_CHIP_RV670_9519 0x9519 #define PCI_CHIP_RV710_9540 0x9540 #define PCI_CHIP_RV710_9541 0x9541 #define PCI_CHIP_RV710_9542 0x9542 #define PCI_CHIP_RV710_954E 0x954E #define PCI_CHIP_RV710_954F 0x954F #define PCI_CHIP_RV710_9552 0x9552 #define PCI_CHIP_RV710_9553 0x9553 #define PCI_CHIP_RV710_9555 0x9555 #define PCI_CHIP_RV710_9557 0x9557 #define PCI_CHIP_RV710_955F 0x955F #define PCI_CHIP_RV630_9580 0x9580 #define PCI_CHIP_RV630_9581 0x9581 #define PCI_CHIP_RV630_9583 0x9583 #define PCI_CHIP_RV630_9586 0x9586 #define PCI_CHIP_RV630_9587 0x9587 #define PCI_CHIP_RV630_9588 0x9588 #define PCI_CHIP_RV630_9589 0x9589 #define PCI_CHIP_RV630_958A 0x958A #define PCI_CHIP_RV630_958B 0x958B #define PCI_CHIP_RV630_958C 0x958C #define PCI_CHIP_RV630_958D 0x958D #define PCI_CHIP_RV630_958E 0x958E #define PCI_CHIP_RV630_958F 0x958F #define PCI_CHIP_RV620_95C0 0x95C0 #define PCI_CHIP_RV620_95C2 0x95C2 #define PCI_CHIP_RV620_95C4 0x95C4 #define PCI_CHIP_RV620_95C5 0x95C5 #define PCI_CHIP_RV620_95C6 0x95C6 #define PCI_CHIP_RV620_95C7 0x95C7 #define PCI_CHIP_RV620_95C9 0x95C9 #define PCI_CHIP_RV620_95CC 0x95CC #define PCI_CHIP_RV620_95CD 0x95CD #define PCI_CHIP_RV620_95CE 0x95CE #define PCI_CHIP_RV620_95CF 0x95CF #define PCI_CHIP_RV635_9590 0x9590 #define PCI_CHIP_RV635_9596 0x9596 #define PCI_CHIP_RV635_9597 0x9597 #define PCI_CHIP_RV635_9598 0x9598 #define PCI_CHIP_RV635_9599 0x9599 #define PCI_CHIP_RV635_9591 0x9591 #define PCI_CHIP_RV635_9593 0x9593 #define PCI_CHIP_RV635_9595 0x9595 #define PCI_CHIP_RV635_959B 0x959B #define PCI_CHIP_RS780_9610 0x9610 #define PCI_CHIP_RS780_9611 0x9611 #define PCI_CHIP_RS780_9612 0x9612 #define PCI_CHIP_RS780_9613 0x9613 #define PCI_CHIP_RS780_9614 0x9614 #define PCI_CHIP_RS780_9615 0x9615 #define PCI_CHIP_RS780_9616 0x9616 #define PCI_CHIP_SUMO_9640 0x9640 #define PCI_CHIP_SUMO_9641 0x9641 #define PCI_CHIP_SUMO2_9642 0x9642 #define PCI_CHIP_SUMO2_9643 0x9643 #define PCI_CHIP_SUMO2_9644 0x9644 #define PCI_CHIP_SUMO2_9645 0x9645 #define PCI_CHIP_SUMO_9647 0x9647 #define PCI_CHIP_SUMO_9648 0x9648 #define PCI_CHIP_SUMO2_9649 0x9649 #define PCI_CHIP_SUMO_964A 0x964A #define PCI_CHIP_SUMO_964B 0x964B #define PCI_CHIP_SUMO_964C 0x964C #define PCI_CHIP_SUMO_964E 0x964E #define PCI_CHIP_SUMO_964F 0x964F #define PCI_CHIP_RS880_9710 0x9710 #define PCI_CHIP_RS880_9711 0x9711 #define PCI_CHIP_RS880_9712 0x9712 #define PCI_CHIP_RS880_9713 0x9713 #define PCI_CHIP_RS880_9714 0x9714 #define PCI_CHIP_RS880_9715 0x9715 #define PCI_CHIP_PALM_9802 0x9802 #define PCI_CHIP_PALM_9803 0x9803 #define PCI_CHIP_PALM_9804 0x9804 #define PCI_CHIP_PALM_9805 0x9805 #define PCI_CHIP_PALM_9806 0x9806 #define PCI_CHIP_PALM_9807 0x9807 #define PCI_CHIP_PALM_9808 0x9808 #define PCI_CHIP_PALM_9809 0x9809 #define PCI_CHIP_PALM_980A 0x980A #define PCI_CHIP_CYPRESS_6880 0x6880 #define PCI_CHIP_CYPRESS_6888 0x6888 #define PCI_CHIP_CYPRESS_6889 0x6889 #define PCI_CHIP_CYPRESS_688A 0x688A #define PCI_CHIP_CYPRESS_688C 0x688C #define PCI_CHIP_CYPRESS_688D 0x688D #define PCI_CHIP_CYPRESS_6898 0x6898 #define PCI_CHIP_CYPRESS_6899 0x6899 #define PCI_CHIP_CYPRESS_689B 0x689B #define PCI_CHIP_CYPRESS_689E 0x689E #define PCI_CHIP_HEMLOCK_689C 0x689C #define PCI_CHIP_HEMLOCK_689D 0x689D #define PCI_CHIP_JUNIPER_68A0 0x68A0 #define PCI_CHIP_JUNIPER_68A1 0x68A1 #define PCI_CHIP_JUNIPER_68A8 0x68A8 #define PCI_CHIP_JUNIPER_68A9 0x68A9 #define PCI_CHIP_JUNIPER_68B0 0x68B0 #define PCI_CHIP_JUNIPER_68B8 0x68B8 #define PCI_CHIP_JUNIPER_68B9 0x68B9 #define PCI_CHIP_JUNIPER_68BA 0x68BA #define PCI_CHIP_JUNIPER_68BE 0x68BE #define PCI_CHIP_JUNIPER_68BF 0x68BF #define PCI_CHIP_REDWOOD_68C0 0x68C0 #define PCI_CHIP_REDWOOD_68C1 0x68C1 #define PCI_CHIP_REDWOOD_68C7 0x68C7 #define PCI_CHIP_REDWOOD_68C8 0x68C8 #define PCI_CHIP_REDWOOD_68C9 0x68C9 #define PCI_CHIP_REDWOOD_68D8 0x68D8 #define PCI_CHIP_REDWOOD_68D9 0x68D9 #define PCI_CHIP_REDWOOD_68DA 0x68DA #define PCI_CHIP_REDWOOD_68DE 0x68DE #define PCI_CHIP_CEDAR_68E0 0x68E0 #define PCI_CHIP_CEDAR_68E1 0x68E1 #define PCI_CHIP_CEDAR_68E4 0x68E4 #define PCI_CHIP_CEDAR_68E5 0x68E5 #define PCI_CHIP_CEDAR_68E8 0x68E8 #define PCI_CHIP_CEDAR_68E9 0x68E9 #define PCI_CHIP_CEDAR_68F1 0x68F1 #define PCI_CHIP_CEDAR_68F2 0x68F2 #define PCI_CHIP_CEDAR_68F8 0x68F8 #define PCI_CHIP_CEDAR_68F9 0x68F9 #define PCI_CHIP_CEDAR_68FA 0x68FA #define PCI_CHIP_CEDAR_68FE 0x68FE #define PCI_CHIP_CAYMAN_6700 0x6700 #define PCI_CHIP_CAYMAN_6701 0x6701 #define PCI_CHIP_CAYMAN_6702 0x6702 #define PCI_CHIP_CAYMAN_6703 0x6703 #define PCI_CHIP_CAYMAN_6704 0x6704 #define PCI_CHIP_CAYMAN_6705 0x6705 #define PCI_CHIP_CAYMAN_6706 0x6706 #define PCI_CHIP_CAYMAN_6707 0x6707 #define PCI_CHIP_CAYMAN_6708 0x6708 #define PCI_CHIP_CAYMAN_6709 0x6709 #define PCI_CHIP_CAYMAN_6718 0x6718 #define PCI_CHIP_CAYMAN_6719 0x6719 #define PCI_CHIP_CAYMAN_671C 0x671C #define PCI_CHIP_CAYMAN_671D 0x671D #define PCI_CHIP_CAYMAN_671F 0x671F #define PCI_CHIP_BARTS_6720 0x6720 #define PCI_CHIP_BARTS_6721 0x6721 #define PCI_CHIP_BARTS_6722 0x6722 #define PCI_CHIP_BARTS_6723 0x6723 #define PCI_CHIP_BARTS_6724 0x6724 #define PCI_CHIP_BARTS_6725 0x6725 #define PCI_CHIP_BARTS_6726 0x6726 #define PCI_CHIP_BARTS_6727 0x6727 #define PCI_CHIP_BARTS_6728 0x6728 #define PCI_CHIP_BARTS_6729 0x6729 #define PCI_CHIP_BARTS_6738 0x6738 #define PCI_CHIP_BARTS_6739 0x6739 #define PCI_CHIP_BARTS_673E 0x673E #define PCI_CHIP_TURKS_6740 0x6740 #define PCI_CHIP_TURKS_6741 0x6741 #define PCI_CHIP_TURKS_6742 0x6742 #define PCI_CHIP_TURKS_6743 0x6743 #define PCI_CHIP_TURKS_6744 0x6744 #define PCI_CHIP_TURKS_6745 0x6745 #define PCI_CHIP_TURKS_6746 0x6746 #define PCI_CHIP_TURKS_6747 0x6747 #define PCI_CHIP_TURKS_6748 0x6748 #define PCI_CHIP_TURKS_6749 0x6749 #define PCI_CHIP_TURKS_674A 0x674A #define PCI_CHIP_TURKS_6750 0x6750 #define PCI_CHIP_TURKS_6751 0x6751 #define PCI_CHIP_TURKS_6758 0x6758 #define PCI_CHIP_TURKS_6759 0x6759 #define PCI_CHIP_TURKS_675B 0x675B #define PCI_CHIP_TURKS_675D 0x675D #define PCI_CHIP_TURKS_675F 0x675F #define PCI_CHIP_TURKS_6840 0x6840 #define PCI_CHIP_TURKS_6841 0x6841 #define PCI_CHIP_TURKS_6842 0x6842 #define PCI_CHIP_TURKS_6843 0x6843 #define PCI_CHIP_TURKS_6849 0x6849 #define PCI_CHIP_TURKS_6850 0x6850 #define PCI_CHIP_TURKS_6858 0x6858 #define PCI_CHIP_TURKS_6859 0x6859 #define PCI_CHIP_CAICOS_6760 0x6760 #define PCI_CHIP_CAICOS_6761 0x6761 #define PCI_CHIP_CAICOS_6762 0x6762 #define PCI_CHIP_CAICOS_6763 0x6763 #define PCI_CHIP_CAICOS_6764 0x6764 #define PCI_CHIP_CAICOS_6765 0x6765 #define PCI_CHIP_CAICOS_6766 0x6766 #define PCI_CHIP_CAICOS_6767 0x6767 #define PCI_CHIP_CAICOS_6768 0x6768 #define PCI_CHIP_CAICOS_6770 0x6770 #define PCI_CHIP_CAICOS_6771 0x6771 #define PCI_CHIP_CAICOS_6772 0x6772 #define PCI_CHIP_CAICOS_6778 0x6778 #define PCI_CHIP_CAICOS_6779 0x6779 #define PCI_CHIP_CAICOS_677B 0x677B #define PCI_CHIP_ARUBA_9900 0x9900 #define PCI_CHIP_ARUBA_9901 0x9901 #define PCI_CHIP_ARUBA_9903 0x9903 #define PCI_CHIP_ARUBA_9904 0x9904 #define PCI_CHIP_ARUBA_9905 0x9905 #define PCI_CHIP_ARUBA_9906 0x9906 #define PCI_CHIP_ARUBA_9907 0x9907 #define PCI_CHIP_ARUBA_9908 0x9908 #define PCI_CHIP_ARUBA_9909 0x9909 #define PCI_CHIP_ARUBA_990A 0x990A #define PCI_CHIP_ARUBA_990B 0x990B #define PCI_CHIP_ARUBA_990C 0x990C #define PCI_CHIP_ARUBA_990D 0x990D #define PCI_CHIP_ARUBA_990E 0x990E #define PCI_CHIP_ARUBA_990F 0x990F #define PCI_CHIP_ARUBA_9910 0x9910 #define PCI_CHIP_ARUBA_9913 0x9913 #define PCI_CHIP_ARUBA_9917 0x9917 #define PCI_CHIP_ARUBA_9918 0x9918 #define PCI_CHIP_ARUBA_9919 0x9919 #define PCI_CHIP_ARUBA_9990 0x9990 #define PCI_CHIP_ARUBA_9991 0x9991 #define PCI_CHIP_ARUBA_9992 0x9992 #define PCI_CHIP_ARUBA_9993 0x9993 #define PCI_CHIP_ARUBA_9994 0x9994 #define PCI_CHIP_ARUBA_9995 0x9995 #define PCI_CHIP_ARUBA_9996 0x9996 #define PCI_CHIP_ARUBA_9997 0x9997 #define PCI_CHIP_ARUBA_9998 0x9998 #define PCI_CHIP_ARUBA_9999 0x9999 #define PCI_CHIP_ARUBA_999A 0x999A #define PCI_CHIP_ARUBA_999B 0x999B #define PCI_CHIP_ARUBA_999C 0x999C #define PCI_CHIP_ARUBA_999D 0x999D #define PCI_CHIP_ARUBA_99A0 0x99A0 #define PCI_CHIP_ARUBA_99A2 0x99A2 #define PCI_CHIP_ARUBA_99A4 0x99A4 #define PCI_CHIP_TAHITI_6780 0x6780 #define PCI_CHIP_TAHITI_6784 0x6784 #define PCI_CHIP_TAHITI_6788 0x6788 #define PCI_CHIP_TAHITI_678A 0x678A #define PCI_CHIP_TAHITI_6790 0x6790 #define PCI_CHIP_TAHITI_6791 0x6791 #define PCI_CHIP_TAHITI_6792 0x6792 #define PCI_CHIP_TAHITI_6798 0x6798 #define PCI_CHIP_TAHITI_6799 0x6799 #define PCI_CHIP_TAHITI_679A 0x679A #define PCI_CHIP_TAHITI_679B 0x679B #define PCI_CHIP_TAHITI_679E 0x679E #define PCI_CHIP_TAHITI_679F 0x679F #define PCI_CHIP_PITCAIRN_6800 0x6800 #define PCI_CHIP_PITCAIRN_6801 0x6801 #define PCI_CHIP_PITCAIRN_6802 0x6802 #define PCI_CHIP_PITCAIRN_6806 0x6806 #define PCI_CHIP_PITCAIRN_6808 0x6808 #define PCI_CHIP_PITCAIRN_6809 0x6809 #define PCI_CHIP_PITCAIRN_6810 0x6810 #define PCI_CHIP_PITCAIRN_6811 0x6811 #define PCI_CHIP_PITCAIRN_6816 0x6816 #define PCI_CHIP_PITCAIRN_6817 0x6817 #define PCI_CHIP_PITCAIRN_6818 0x6818 #define PCI_CHIP_PITCAIRN_6819 0x6819 #define PCI_CHIP_PITCAIRN_684C 0x684C #define PCI_CHIP_VERDE_6820 0x6820 #define PCI_CHIP_VERDE_6821 0x6821 #define PCI_CHIP_VERDE_6822 0x6822 #define PCI_CHIP_VERDE_6823 0x6823 #define PCI_CHIP_VERDE_6824 0x6824 #define PCI_CHIP_VERDE_6825 0x6825 #define PCI_CHIP_VERDE_6826 0x6826 #define PCI_CHIP_VERDE_6827 0x6827 #define PCI_CHIP_VERDE_6828 0x6828 #define PCI_CHIP_VERDE_6829 0x6829 #define PCI_CHIP_VERDE_682A 0x682A #define PCI_CHIP_VERDE_682B 0x682B #define PCI_CHIP_VERDE_682C 0x682C #define PCI_CHIP_VERDE_682D 0x682D #define PCI_CHIP_VERDE_682F 0x682F #define PCI_CHIP_VERDE_6830 0x6830 #define PCI_CHIP_VERDE_6831 0x6831 #define PCI_CHIP_VERDE_6835 0x6835 #define PCI_CHIP_VERDE_6837 0x6837 #define PCI_CHIP_VERDE_6838 0x6838 #define PCI_CHIP_VERDE_6839 0x6839 #define PCI_CHIP_VERDE_683B 0x683B #define PCI_CHIP_VERDE_683D 0x683D #define PCI_CHIP_VERDE_683F 0x683F #define PCI_CHIP_OLAND_6600 0x6600 #define PCI_CHIP_OLAND_6601 0x6601 #define PCI_CHIP_OLAND_6602 0x6602 #define PCI_CHIP_OLAND_6603 0x6603 #define PCI_CHIP_OLAND_6604 0x6604 #define PCI_CHIP_OLAND_6605 0x6605 #define PCI_CHIP_OLAND_6606 0x6606 #define PCI_CHIP_OLAND_6607 0x6607 #define PCI_CHIP_OLAND_6608 0x6608 #define PCI_CHIP_OLAND_6610 0x6610 #define PCI_CHIP_OLAND_6611 0x6611 #define PCI_CHIP_OLAND_6613 0x6613 #define PCI_CHIP_OLAND_6617 0x6617 #define PCI_CHIP_OLAND_6620 0x6620 #define PCI_CHIP_OLAND_6621 0x6621 #define PCI_CHIP_OLAND_6623 0x6623 #define PCI_CHIP_OLAND_6631 0x6631 #define PCI_CHIP_HAINAN_6660 0x6660 #define PCI_CHIP_HAINAN_6663 0x6663 #define PCI_CHIP_HAINAN_6664 0x6664 #define PCI_CHIP_HAINAN_6665 0x6665 #define PCI_CHIP_HAINAN_6667 0x6667 #define PCI_CHIP_HAINAN_666F 0x666F #define PCI_CHIP_BONAIRE_6640 0x6640 #define PCI_CHIP_BONAIRE_6641 0x6641 #define PCI_CHIP_BONAIRE_6646 0x6646 #define PCI_CHIP_BONAIRE_6647 0x6647 #define PCI_CHIP_BONAIRE_6649 0x6649 #define PCI_CHIP_BONAIRE_6650 0x6650 #define PCI_CHIP_BONAIRE_6651 0x6651 #define PCI_CHIP_BONAIRE_6658 0x6658 #define PCI_CHIP_BONAIRE_665C 0x665C #define PCI_CHIP_BONAIRE_665D 0x665D #define PCI_CHIP_BONAIRE_665F 0x665F #define PCI_CHIP_KABINI_9830 0x9830 #define PCI_CHIP_KABINI_9831 0x9831 #define PCI_CHIP_KABINI_9832 0x9832 #define PCI_CHIP_KABINI_9833 0x9833 #define PCI_CHIP_KABINI_9834 0x9834 #define PCI_CHIP_KABINI_9835 0x9835 #define PCI_CHIP_KABINI_9836 0x9836 #define PCI_CHIP_KABINI_9837 0x9837 #define PCI_CHIP_KABINI_9838 0x9838 #define PCI_CHIP_KABINI_9839 0x9839 #define PCI_CHIP_KABINI_983A 0x983A #define PCI_CHIP_KABINI_983B 0x983B #define PCI_CHIP_KABINI_983C 0x983C #define PCI_CHIP_KABINI_983D 0x983D #define PCI_CHIP_KABINI_983E 0x983E #define PCI_CHIP_KABINI_983F 0x983F #define PCI_CHIP_MULLINS_9850 0x9850 #define PCI_CHIP_MULLINS_9851 0x9851 #define PCI_CHIP_MULLINS_9852 0x9852 #define PCI_CHIP_MULLINS_9853 0x9853 #define PCI_CHIP_MULLINS_9854 0x9854 #define PCI_CHIP_MULLINS_9855 0x9855 #define PCI_CHIP_MULLINS_9856 0x9856 #define PCI_CHIP_MULLINS_9857 0x9857 #define PCI_CHIP_MULLINS_9858 0x9858 #define PCI_CHIP_MULLINS_9859 0x9859 #define PCI_CHIP_MULLINS_985A 0x985A #define PCI_CHIP_MULLINS_985B 0x985B #define PCI_CHIP_MULLINS_985C 0x985C #define PCI_CHIP_MULLINS_985D 0x985D #define PCI_CHIP_MULLINS_985E 0x985E #define PCI_CHIP_MULLINS_985F 0x985F #define PCI_CHIP_KAVERI_1304 0x1304 #define PCI_CHIP_KAVERI_1305 0x1305 #define PCI_CHIP_KAVERI_1306 0x1306 #define PCI_CHIP_KAVERI_1307 0x1307 #define PCI_CHIP_KAVERI_1309 0x1309 #define PCI_CHIP_KAVERI_130A 0x130A #define PCI_CHIP_KAVERI_130B 0x130B #define PCI_CHIP_KAVERI_130C 0x130C #define PCI_CHIP_KAVERI_130D 0x130D #define PCI_CHIP_KAVERI_130E 0x130E #define PCI_CHIP_KAVERI_130F 0x130F #define PCI_CHIP_KAVERI_1310 0x1310 #define PCI_CHIP_KAVERI_1311 0x1311 #define PCI_CHIP_KAVERI_1312 0x1312 #define PCI_CHIP_KAVERI_1313 0x1313 #define PCI_CHIP_KAVERI_1315 0x1315 #define PCI_CHIP_KAVERI_1316 0x1316 #define PCI_CHIP_KAVERI_1317 0x1317 #define PCI_CHIP_KAVERI_1318 0x1318 #define PCI_CHIP_KAVERI_131B 0x131B #define PCI_CHIP_KAVERI_131C 0x131C #define PCI_CHIP_KAVERI_131D 0x131D #define PCI_CHIP_HAWAII_67A0 0x67A0 #define PCI_CHIP_HAWAII_67A1 0x67A1 #define PCI_CHIP_HAWAII_67A2 0x67A2 #define PCI_CHIP_HAWAII_67A8 0x67A8 #define PCI_CHIP_HAWAII_67A9 0x67A9 #define PCI_CHIP_HAWAII_67AA 0x67AA #define PCI_CHIP_HAWAII_67B0 0x67B0 #define PCI_CHIP_HAWAII_67B1 0x67B1 #define PCI_CHIP_HAWAII_67B8 0x67B8 #define PCI_CHIP_HAWAII_67B9 0x67B9 #define PCI_CHIP_HAWAII_67BA 0x67BA #define PCI_CHIP_HAWAII_67BE 0x67BE xserver-xorg-video-ati-7.5.0+git20150819/src/atimodule.c000066400000000000000000000042031256524674500224230ustar00rootroot00000000000000/* * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "ati.h" #include "ativersion.h" /* Module loader interface */ static XF86ModuleVersionInfo ATIVersionRec = { ATI_DRIVER_NAME, MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, XORG_VERSION_CURRENT, ATI_VERSION_MAJOR, ATI_VERSION_MINOR, ATI_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, MOD_CLASS_VIDEODRV, {0, 0, 0, 0} }; /* * ATISetup -- * * This function is called every time the module is loaded. */ static pointer ATISetup ( pointer Module, pointer Options, int *ErrorMajor, int *ErrorMinor ) { static Bool Inited = FALSE; if (!Inited) { Inited = TRUE; ati_gdev_subdriver(Options); } return (pointer)1; } /* The following record must be called atiModuleData */ _X_EXPORT XF86ModuleData atiModuleData = { &ATIVersionRec, ATISetup, NULL }; xserver-xorg-video-ati-7.5.0+git20150819/src/atipciids.h000066400000000000000000000037531256524674500224270ustar00rootroot00000000000000/* * Copyright (c) 1995-2003 by The XFree86 Project, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Except as contained in this notice, the name of the copyright holder(s) * and author(s) shall not be used in advertising or otherwise to promote * the sale, use or other dealings in this Software without prior written * authorization from the copyright holder(s) and author(s). */ /* * This file is a replacement for xf86PciInfo.h moving ATI related PCI IDs * locally to the driver module */ #ifndef _ATIPCIIDS_H #define _ATIPCIIDS_H /* PCI Vendor */ #define PCI_VENDOR_ASUS 0x1043 #define PCI_VENDOR_ATI 0x1002 #define PCI_VENDOR_IBM 0x1014 #define PCI_VENDOR_AMD 0x1022 #define PCI_VENDOR_DELL 0x1028 #define PCI_VENDOR_VIA 0x1106 #define PCI_VENDOR_INTEL 0x8086 #ifndef PCI_VENDOR_HP #define PCI_VENDOR_HP 0x103c #endif #define PCI_VENDOR_SONY 0x104D #include "ati_pciids_gen.h" /* Misc */ #define PCI_CHIP_AMD761 0x700E #endif /* _ATIPCIIDS_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/atipcirename.h000066400000000000000000000061171256524674500231140ustar00rootroot00000000000000/* * Copyright 2007 George Sapountzis * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ /** * Macros for porting drivers from legacy xfree86 PCI code to the pciaccess * library. The main purpose being to facilitate source code compatibility. */ #ifndef ATIPCIRENAME_H #define ATIPCIRENAME_H enum region_type { REGION_MEM, REGION_IO }; typedef struct pci_device *pciVideoPtr; #define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id) #define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id) #define PCI_DEV_REVISION(_pcidev) ((_pcidev)->revision) #define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id) #define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id) /* pci-rework functions take a 'pci_device' parameter instead of a tag */ #define PCI_DEV_TAG(_pcidev) (_pcidev) /* PCI_DEV macros, typically used in printf's, add domain ? XXX */ #define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus) #define PCI_DEV_DEV(_pcidev) ((_pcidev)->dev) #define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func) /* pci-rework functions take a 'pci_device' parameter instead of a tag */ #define PCI_CFG_TAG(_pcidev) (_pcidev) /* PCI_CFG macros, typically used in DRI init, contain the domain */ #define PCI_CFG_BUS(_pcidev) (((_pcidev)->domain << 8) | \ (_pcidev)->bus) #define PCI_CFG_DEV(_pcidev) ((_pcidev)->dev) #define PCI_CFG_FUNC(_pcidev) ((_pcidev)->func) #define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr) #define PCI_REGION_SIZE(_pcidev, _b) ((_pcidev)->regions[(_b)].size) #define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \ pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset)) #define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \ pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset)) #define PCI_WRITE_LONG(_pcidev, _value, _offset) \ pci_device_cfg_write_u32((_pcidev), (_value), (_offset)) #define ATI_DEVICE_MATCH(d, i) \ { PCI_VENDOR_ATI, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) } #endif /* ATIPCIRENAME_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/ativersion.h000066400000000000000000000042741256524674500226400ustar00rootroot00000000000000/* * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef ___ATIVERSION_H___ #define ___ATIVERSION_H___ 1 #undef ATI_NAME #undef ATI_DRIVER_NAME #undef ATI_VERSION_CURRENT #undef ATI_VERSION_EVALUATE #undef ATI_VERSION_STRINGIFY #undef ATI_VERSION_NAME #define ATI_NAME "ATI" #define ATI_DRIVER_NAME "ati" #ifndef ATI_VERSION_EXTRA #define ATI_VERSION_EXTRA "" #endif #define ATI_VERSION_MAJOR PACKAGE_VERSION_MAJOR #define ATI_VERSION_MINOR PACKAGE_VERSION_MINOR #define ATI_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL #define ATI_VERSION_CURRENT \ ((ATI_VERSION_MAJOR << 20) | (ATI_VERSION_MINOR << 10) | ATI_VERSION_PATCH) #define ATI_VERSION_EVALUATE(__x) #__x #define ATI_VERSION_STRINGIFY(_x) ATI_VERSION_EVALUATE(_x) #define ATI_VERSION_NAME \ ATI_VERSION_STRINGIFY(ATI_VERSION_MAJOR) "." \ ATI_VERSION_STRINGIFY(ATI_VERSION_MINOR) "." \ ATI_VERSION_STRINGIFY(ATI_VERSION_PATCH) ATI_VERSION_EXTRA #endif /* ___ATIVERSION_H___ */ xserver-xorg-video-ati-7.5.0+git20150819/src/bicubic_table.h000066400000000000000000000513471256524674500232270ustar00rootroot00000000000000static const uint16_t bicubic_tex_512[] = { 0xb266, 0x3c00, 0x3aaa, 0x3155, 0xb287, 0x3bf0, 0x3aa2, 0x3175, 0xb2a9, 0x3be0, 0x3a9a, 0x3196, 0xb2cc, 0x3bd0, 0x3a92, 0x31b7, 0xb2ee, 0x3bc0, 0x3a89, 0x31d9, 0xb312, 0x3bb0, 0x3a81, 0x31fb, 0xb335, 0x3ba0, 0x3a78, 0x321e, 0xb359, 0x3b90, 0x3a6f, 0x3241, 0xb37d, 0x3b80, 0x3a66, 0x3264, 0xb3a2, 0x3b70, 0x3a5d, 0x3288, 0xb3c7, 0x3b60, 0x3a54, 0x32ad, 0xb3ed, 0x3b51, 0x3a4b, 0x32d1, 0xb409, 0x3b41, 0x3a42, 0x32f7, 0xb41c, 0x3b31, 0x3a38, 0x331c, 0xb42f, 0x3b21, 0x3a2f, 0x3342, 0xb443, 0x3b12, 0x3a25, 0x3369, 0xb456, 0x3b02, 0x3a1c, 0x3390, 0xb46a, 0x3af3, 0x3a12, 0x33b7, 0xb47e, 0x3ae3, 0x3a08, 0x33de, 0xb492, 0x3ad4, 0x39fe, 0x3403, 0xb4a6, 0x3ac5, 0x39f4, 0x3417, 0xb4bb, 0x3ab5, 0x39ea, 0x342b, 0xb4cf, 0x3aa6, 0x39df, 0x3440, 0xb4e4, 0x3a97, 0x39d5, 0x3454, 0xb4f9, 0x3a88, 0x39cb, 0x3469, 0xb50e, 0x3a79, 0x39c0, 0x347e, 0xb523, 0x3a6a, 0x39b6, 0x3493, 0xb539, 0x3a5a, 0x39ab, 0x34a8, 0xb54e, 0x3a4c, 0x39a0, 0x34be, 0xb564, 0x3a3d, 0x3996, 0x34d3, 0xb57a, 0x3a2e, 0x398b, 0x34e9, 0xb590, 0x3a1f, 0x3980, 0x34ff, 0xb5a6, 0x3a10, 0x3975, 0x3515, 0xb5bc, 0x3a02, 0x396a, 0x352b, 0xb5d2, 0x39f3, 0x395f, 0x3541, 0xb5e9, 0x39e4, 0x3954, 0x3557, 0xb5ff, 0x39d6, 0x3948, 0x356e, 0xb616, 0x39c7, 0x393d, 0x3584, 0xb62d, 0x39b9, 0x3932, 0x359b, 0xb644, 0x39ab, 0x3926, 0x35b2, 0xb65b, 0x399c, 0x391b, 0x35c9, 0xb672, 0x398e, 0x3910, 0x35df, 0xb68a, 0x3980, 0x3904, 0x35f6, 0xb6a1, 0x3972, 0x38f8, 0x360e, 0xb6b9, 0x3964, 0x38ed, 0x3625, 0xb6d1, 0x3956, 0x38e1, 0x363c, 0xb6e8, 0x3948, 0x38d6, 0x3653, 0xb700, 0x393a, 0x38ca, 0x366b, 0xb719, 0x392c, 0x38be, 0x3682, 0xb731, 0x391e, 0x38b2, 0x369a, 0xb749, 0x3910, 0x38a7, 0x36b1, 0xb762, 0x3902, 0x389b, 0x36c9, 0xb77a, 0x38f5, 0x388f, 0x36e1, 0xb793, 0x38e7, 0x3883, 0x36f8, 0xb7ac, 0x38da, 0x3877, 0x3710, 0xb7c5, 0x38cc, 0x386b, 0x3728, 0xb7de, 0x38bf, 0x385f, 0x3740, 0xb7f7, 0x38b1, 0x3853, 0x3758, 0xb808, 0x38a4, 0x3847, 0x3770, 0xb815, 0x3897, 0x383b, 0x3788, 0xb821, 0x3889, 0x382f, 0x37a0, 0xb82e, 0x387c, 0x3823, 0x37b8, 0xb83b, 0x386f, 0x3817, 0x37d0, 0xb848, 0x3862, 0x380b, 0x37e8, 0xb855, 0x3855, 0x3800, 0x3800, 0xb862, 0x3848, 0x37e8, 0x380b, 0xb86f, 0x383b, 0x37d0, 0x3817, 0xb87c, 0x382e, 0x37b8, 0x3823, 0xb889, 0x3821, 0x37a0, 0x382f, 0xb897, 0x3815, 0x3788, 0x383b, 0xb8a4, 0x3808, 0x3770, 0x3847, 0xb8b1, 0x37f7, 0x3758, 0x3853, 0xb8bf, 0x37de, 0x3740, 0x385f, 0xb8cc, 0x37c5, 0x3728, 0x386b, 0xb8da, 0x37ac, 0x3710, 0x3877, 0xb8e7, 0x3793, 0x36f8, 0x3883, 0xb8f5, 0x377a, 0x36e1, 0x388f, 0xb902, 0x3762, 0x36c9, 0x389b, 0xb910, 0x3749, 0x36b1, 0x38a7, 0xb91e, 0x3731, 0x369a, 0x38b2, 0xb92c, 0x3719, 0x3682, 0x38be, 0xb93a, 0x3700, 0x366b, 0x38ca, 0xb948, 0x36e8, 0x3653, 0x38d6, 0xb956, 0x36d1, 0x363c, 0x38e1, 0xb964, 0x36b9, 0x3625, 0x38ed, 0xb972, 0x36a1, 0x360e, 0x38f8, 0xb980, 0x368a, 0x35f6, 0x3904, 0xb98e, 0x3672, 0x35df, 0x3910, 0xb99c, 0x365b, 0x35c9, 0x391b, 0xb9ab, 0x3644, 0x35b2, 0x3926, 0xb9b9, 0x362d, 0x359b, 0x3932, 0xb9c7, 0x3616, 0x3584, 0x393d, 0xb9d6, 0x35ff, 0x356e, 0x3948, 0xb9e4, 0x35e9, 0x3557, 0x3954, 0xb9f3, 0x35d2, 0x3541, 0x395f, 0xba02, 0x35bc, 0x352b, 0x396a, 0xba10, 0x35a6, 0x3515, 0x3975, 0xba1f, 0x3590, 0x34ff, 0x3980, 0xba2e, 0x357a, 0x34e9, 0x398b, 0xba3d, 0x3564, 0x34d3, 0x3996, 0xba4c, 0x354e, 0x34be, 0x39a0, 0xba5a, 0x3539, 0x34a8, 0x39ab, 0xba6a, 0x3523, 0x3493, 0x39b6, 0xba79, 0x350e, 0x347e, 0x39c0, 0xba88, 0x34f9, 0x3469, 0x39cb, 0xba97, 0x34e4, 0x3454, 0x39d5, 0xbaa6, 0x34cf, 0x3440, 0x39df, 0xbab5, 0x34bb, 0x342b, 0x39ea, 0xbac5, 0x34a6, 0x3417, 0x39f4, 0xbad4, 0x3492, 0x3403, 0x39fe, 0xbae3, 0x347e, 0x33de, 0x3a08, 0xbaf3, 0x346a, 0x33b7, 0x3a12, 0xbb02, 0x3456, 0x3390, 0x3a1c, 0xbb12, 0x3443, 0x3369, 0x3a25, 0xbb21, 0x342f, 0x3342, 0x3a2f, 0xbb31, 0x341c, 0x331c, 0x3a38, 0xbb41, 0x3409, 0x32f7, 0x3a42, 0xbb51, 0x33ed, 0x32d1, 0x3a4b, 0xbb60, 0x33c7, 0x32ad, 0x3a54, 0xbb70, 0x33a2, 0x3288, 0x3a5d, 0xbb80, 0x337d, 0x3264, 0x3a66, 0xbb90, 0x3359, 0x3241, 0x3a6f, 0xbba0, 0x3335, 0x321e, 0x3a78, 0xbbb0, 0x3312, 0x31fb, 0x3a81, 0xbbc0, 0x32ee, 0x31d9, 0x3a89, 0xbbd0, 0x32cc, 0x31b7, 0x3a92, 0xbbe0, 0x32a9, 0x3196, 0x3a9a, 0xbbf0, 0x3287, 0x3175, 0x3aa2, 0 }; static const uint16_t bicubic_tex_2048[] = { 0xb266, 0x3c00, 0x3aaa, 0x3155, 0xb26e, 0x3bfc, 0x3aa8, 0x315d, 0xb277, 0x3bf8, 0x3aa6, 0x3165, 0xb27f, 0x3bf4, 0x3aa4, 0x316d, 0xb287, 0x3bf0, 0x3aa2, 0x3175, 0xb290, 0x3bec, 0x3aa0, 0x317d, 0xb298, 0x3be8, 0x3a9e, 0x3185, 0xb2a1, 0x3be4, 0x3a9c, 0x318e, 0xb2a9, 0x3be0, 0x3a9a, 0x3196, 0xb2b2, 0x3bdc, 0x3a98, 0x319e, 0xb2ba, 0x3bd8, 0x3a96, 0x31a6, 0xb2c3, 0x3bd4, 0x3a94, 0x31af, 0xb2cc, 0x3bd0, 0x3a92, 0x31b7, 0xb2d4, 0x3bcc, 0x3a90, 0x31bf, 0xb2dd, 0x3bc8, 0x3a8d, 0x31c8, 0xb2e6, 0x3bc4, 0x3a8b, 0x31d0, 0xb2ee, 0x3bc0, 0x3a89, 0x31d9, 0xb2f7, 0x3bbc, 0x3a87, 0x31e1, 0xb300, 0x3bb8, 0x3a85, 0x31ea, 0xb309, 0x3bb4, 0x3a83, 0x31f2, 0xb312, 0x3bb0, 0x3a81, 0x31fb, 0xb31a, 0x3bac, 0x3a7e, 0x3204, 0xb323, 0x3ba8, 0x3a7c, 0x320c, 0xb32c, 0x3ba4, 0x3a7a, 0x3215, 0xb335, 0x3ba0, 0x3a78, 0x321e, 0xb33e, 0x3b9c, 0x3a76, 0x3226, 0xb347, 0x3b98, 0x3a74, 0x322f, 0xb350, 0x3b94, 0x3a71, 0x3238, 0xb359, 0x3b90, 0x3a6f, 0x3241, 0xb362, 0x3b8c, 0x3a6d, 0x3249, 0xb36b, 0x3b88, 0x3a6b, 0x3252, 0xb374, 0x3b84, 0x3a69, 0x325b, 0xb37d, 0x3b80, 0x3a66, 0x3264, 0xb387, 0x3b7c, 0x3a64, 0x326d, 0xb390, 0x3b78, 0x3a62, 0x3276, 0xb399, 0x3b74, 0x3a60, 0x327f, 0xb3a2, 0x3b70, 0x3a5d, 0x3288, 0xb3ab, 0x3b6c, 0x3a5b, 0x3291, 0xb3b5, 0x3b68, 0x3a59, 0x329a, 0xb3be, 0x3b64, 0x3a57, 0x32a3, 0xb3c7, 0x3b60, 0x3a54, 0x32ad, 0xb3d0, 0x3b5c, 0x3a52, 0x32b6, 0xb3da, 0x3b58, 0x3a50, 0x32bf, 0xb3e3, 0x3b54, 0x3a4d, 0x32c8, 0xb3ed, 0x3b51, 0x3a4b, 0x32d1, 0xb3f6, 0x3b4d, 0x3a49, 0x32db, 0xb3ff, 0x3b49, 0x3a46, 0x32e4, 0xb404, 0x3b45, 0x3a44, 0x32ed, 0xb409, 0x3b41, 0x3a42, 0x32f7, 0xb40e, 0x3b3d, 0x3a3f, 0x3300, 0xb412, 0x3b39, 0x3a3d, 0x3309, 0xb417, 0x3b35, 0x3a3b, 0x3313, 0xb41c, 0x3b31, 0x3a38, 0x331c, 0xb421, 0x3b2d, 0x3a36, 0x3326, 0xb426, 0x3b29, 0x3a34, 0x332f, 0xb42a, 0x3b25, 0x3a31, 0x3339, 0xb42f, 0x3b21, 0x3a2f, 0x3342, 0xb434, 0x3b1e, 0x3a2c, 0x334c, 0xb439, 0x3b1a, 0x3a2a, 0x3355, 0xb43e, 0x3b16, 0x3a28, 0x335f, 0xb443, 0x3b12, 0x3a25, 0x3369, 0xb448, 0x3b0e, 0x3a23, 0x3372, 0xb44d, 0x3b0a, 0x3a20, 0x337c, 0xb451, 0x3b06, 0x3a1e, 0x3386, 0xb456, 0x3b02, 0x3a1c, 0x3390, 0xb45b, 0x3afe, 0x3a19, 0x3399, 0xb460, 0x3afb, 0x3a17, 0x33a3, 0xb465, 0x3af7, 0x3a14, 0x33ad, 0xb46a, 0x3af3, 0x3a12, 0x33b7, 0xb46f, 0x3aef, 0x3a0f, 0x33c1, 0xb474, 0x3aeb, 0x3a0d, 0x33ca, 0xb479, 0x3ae7, 0x3a0a, 0x33d4, 0xb47e, 0x3ae3, 0x3a08, 0x33de, 0xb483, 0x3ae0, 0x3a05, 0x33e8, 0xb488, 0x3adc, 0x3a03, 0x33f2, 0xb48d, 0x3ad8, 0x3a00, 0x33fc, 0xb492, 0x3ad4, 0x39fe, 0x3403, 0xb497, 0x3ad0, 0x39fb, 0x3408, 0xb49c, 0x3acc, 0x39f9, 0x340d, 0xb4a1, 0x3ac8, 0x39f6, 0x3412, 0xb4a6, 0x3ac5, 0x39f4, 0x3417, 0xb4ac, 0x3ac1, 0x39f1, 0x341c, 0xb4b1, 0x3abd, 0x39ef, 0x3421, 0xb4b6, 0x3ab9, 0x39ec, 0x3426, 0xb4bb, 0x3ab5, 0x39ea, 0x342b, 0xb4c0, 0x3ab1, 0x39e7, 0x3430, 0xb4c5, 0x3aae, 0x39e5, 0x3435, 0xb4ca, 0x3aaa, 0x39e2, 0x343b, 0xb4cf, 0x3aa6, 0x39df, 0x3440, 0xb4d5, 0x3aa2, 0x39dd, 0x3445, 0xb4da, 0x3a9e, 0x39da, 0x344a, 0xb4df, 0x3a9b, 0x39d8, 0x344f, 0xb4e4, 0x3a97, 0x39d5, 0x3454, 0xb4e9, 0x3a93, 0x39d2, 0x345a, 0xb4ef, 0x3a8f, 0x39d0, 0x345f, 0xb4f4, 0x3a8b, 0x39cd, 0x3464, 0xb4f9, 0x3a88, 0x39cb, 0x3469, 0xb4fe, 0x3a84, 0x39c8, 0x346e, 0xb504, 0x3a80, 0x39c5, 0x3474, 0xb509, 0x3a7c, 0x39c3, 0x3479, 0xb50e, 0x3a79, 0x39c0, 0x347e, 0xb513, 0x3a75, 0x39be, 0x3483, 0xb519, 0x3a71, 0x39bb, 0x3489, 0xb51e, 0x3a6d, 0x39b8, 0x348e, 0xb523, 0x3a6a, 0x39b6, 0x3493, 0xb529, 0x3a66, 0x39b3, 0x3499, 0xb52e, 0x3a62, 0x39b0, 0x349e, 0xb533, 0x3a5e, 0x39ae, 0x34a3, 0xb539, 0x3a5a, 0x39ab, 0x34a8, 0xb53e, 0x3a57, 0x39a8, 0x34ae, 0xb543, 0x3a53, 0x39a6, 0x34b3, 0xb549, 0x3a4f, 0x39a3, 0x34b9, 0xb54e, 0x3a4c, 0x39a0, 0x34be, 0xb554, 0x3a48, 0x399e, 0x34c3, 0xb559, 0x3a44, 0x399b, 0x34c9, 0xb55e, 0x3a40, 0x3998, 0x34ce, 0xb564, 0x3a3d, 0x3996, 0x34d3, 0xb569, 0x3a39, 0x3993, 0x34d9, 0xb56f, 0x3a35, 0x3990, 0x34de, 0xb574, 0x3a32, 0x398d, 0x34e4, 0xb57a, 0x3a2e, 0x398b, 0x34e9, 0xb57f, 0x3a2a, 0x3988, 0x34ef, 0xb585, 0x3a26, 0x3985, 0x34f4, 0xb58a, 0x3a23, 0x3983, 0x34f9, 0xb590, 0x3a1f, 0x3980, 0x34ff, 0xb595, 0x3a1b, 0x397d, 0x3504, 0xb59b, 0x3a18, 0x397a, 0x350a, 0xb5a0, 0x3a14, 0x3978, 0x350f, 0xb5a6, 0x3a10, 0x3975, 0x3515, 0xb5ab, 0x3a0d, 0x3972, 0x351a, 0xb5b1, 0x3a09, 0x396f, 0x3520, 0xb5b6, 0x3a05, 0x396d, 0x3525, 0xb5bc, 0x3a02, 0x396a, 0x352b, 0xb5c1, 0x39fe, 0x3967, 0x3530, 0xb5c7, 0x39fa, 0x3964, 0x3536, 0xb5cd, 0x39f7, 0x3961, 0x353c, 0xb5d2, 0x39f3, 0x395f, 0x3541, 0xb5d8, 0x39ef, 0x395c, 0x3547, 0xb5dd, 0x39ec, 0x3959, 0x354c, 0xb5e3, 0x39e8, 0x3956, 0x3552, 0xb5e9, 0x39e4, 0x3954, 0x3557, 0xb5ee, 0x39e1, 0x3951, 0x355d, 0xb5f4, 0x39dd, 0x394e, 0x3563, 0xb5fa, 0x39d9, 0x394b, 0x3568, 0xb5ff, 0x39d6, 0x3948, 0x356e, 0xb605, 0x39d2, 0x3946, 0x3573, 0xb60b, 0x39cf, 0x3943, 0x3579, 0xb610, 0x39cb, 0x3940, 0x357f, 0xb616, 0x39c7, 0x393d, 0x3584, 0xb61c, 0x39c4, 0x393a, 0x358a, 0xb621, 0x39c0, 0x3937, 0x3590, 0xb627, 0x39bd, 0x3935, 0x3595, 0xb62d, 0x39b9, 0x3932, 0x359b, 0xb633, 0x39b5, 0x392f, 0x35a1, 0xb638, 0x39b2, 0x392c, 0x35a6, 0xb63e, 0x39ae, 0x3929, 0x35ac, 0xb644, 0x39ab, 0x3926, 0x35b2, 0xb64a, 0x39a7, 0x3924, 0x35b7, 0xb64f, 0x39a3, 0x3921, 0x35bd, 0xb655, 0x39a0, 0x391e, 0x35c3, 0xb65b, 0x399c, 0x391b, 0x35c9, 0xb661, 0x3999, 0x3918, 0x35ce, 0xb667, 0x3995, 0x3915, 0x35d4, 0xb66c, 0x3992, 0x3912, 0x35da, 0xb672, 0x398e, 0x3910, 0x35df, 0xb678, 0x398a, 0x390d, 0x35e5, 0xb67e, 0x3987, 0x390a, 0x35eb, 0xb684, 0x3983, 0x3907, 0x35f1, 0xb68a, 0x3980, 0x3904, 0x35f6, 0xb68f, 0x397c, 0x3901, 0x35fc, 0xb695, 0x3979, 0x38fe, 0x3602, 0xb69b, 0x3975, 0x38fb, 0x3608, 0xb6a1, 0x3972, 0x38f8, 0x360e, 0xb6a7, 0x396e, 0x38f6, 0x3613, 0xb6ad, 0x396b, 0x38f3, 0x3619, 0xb6b3, 0x3967, 0x38f0, 0x361f, 0xb6b9, 0x3964, 0x38ed, 0x3625, 0xb6bf, 0x3960, 0x38ea, 0x362b, 0xb6c5, 0x395d, 0x38e7, 0x3630, 0xb6cb, 0x3959, 0x38e4, 0x3636, 0xb6d1, 0x3956, 0x38e1, 0x363c, 0xb6d6, 0x3952, 0x38de, 0x3642, 0xb6dc, 0x394f, 0x38db, 0x3648, 0xb6e2, 0x394b, 0x38d9, 0x364d, 0xb6e8, 0x3948, 0x38d6, 0x3653, 0xb6ee, 0x3944, 0x38d3, 0x3659, 0xb6f4, 0x3941, 0x38d0, 0x365f, 0xb6fa, 0x393d, 0x38cd, 0x3665, 0xb700, 0x393a, 0x38ca, 0x366b, 0xb706, 0x3936, 0x38c7, 0x3671, 0xb70c, 0x3933, 0x38c4, 0x3676, 0xb712, 0x392f, 0x38c1, 0x367c, 0xb719, 0x392c, 0x38be, 0x3682, 0xb71f, 0x3928, 0x38bb, 0x3688, 0xb725, 0x3925, 0x38b8, 0x368e, 0xb72b, 0x3921, 0x38b5, 0x3694, 0xb731, 0x391e, 0x38b2, 0x369a, 0xb737, 0x391a, 0x38af, 0x36a0, 0xb73d, 0x3917, 0x38ad, 0x36a5, 0xb743, 0x3914, 0x38aa, 0x36ab, 0xb749, 0x3910, 0x38a7, 0x36b1, 0xb74f, 0x390d, 0x38a4, 0x36b7, 0xb755, 0x3909, 0x38a1, 0x36bd, 0xb75b, 0x3906, 0x389e, 0x36c3, 0xb762, 0x3902, 0x389b, 0x36c9, 0xb768, 0x38ff, 0x3898, 0x36cf, 0xb76e, 0x38fc, 0x3895, 0x36d5, 0xb774, 0x38f8, 0x3892, 0x36db, 0xb77a, 0x38f5, 0x388f, 0x36e1, 0xb780, 0x38f1, 0x388c, 0x36e7, 0xb787, 0x38ee, 0x3889, 0x36ec, 0xb78d, 0x38eb, 0x3886, 0x36f2, 0xb793, 0x38e7, 0x3883, 0x36f8, 0xb799, 0x38e4, 0x3880, 0x36fe, 0xb79f, 0x38e0, 0x387d, 0x3704, 0xb7a5, 0x38dd, 0x387a, 0x370a, 0xb7ac, 0x38da, 0x3877, 0x3710, 0xb7b2, 0x38d6, 0x3874, 0x3716, 0xb7b8, 0x38d3, 0x3871, 0x371c, 0xb7be, 0x38cf, 0x386e, 0x3722, 0xb7c5, 0x38cc, 0x386b, 0x3728, 0xb7cb, 0x38c9, 0x3868, 0x372e, 0xb7d1, 0x38c5, 0x3865, 0x3734, 0xb7d7, 0x38c2, 0x3862, 0x373a, 0xb7de, 0x38bf, 0x385f, 0x3740, 0xb7e4, 0x38bb, 0x385c, 0x3746, 0xb7ea, 0x38b8, 0x3859, 0x374c, 0xb7f1, 0x38b5, 0x3856, 0x3752, 0xb7f7, 0x38b1, 0x3853, 0x3758, 0xb7fd, 0x38ae, 0x3850, 0x375e, 0xb801, 0x38aa, 0x384d, 0x3764, 0xb805, 0x38a7, 0x384a, 0x376a, 0xb808, 0x38a4, 0x3847, 0x3770, 0xb80b, 0x38a0, 0x3844, 0x3776, 0xb80e, 0x389d, 0x3841, 0x377c, 0xb811, 0x389a, 0x383e, 0x3782, 0xb815, 0x3897, 0x383b, 0x3788, 0xb818, 0x3893, 0x3838, 0x378e, 0xb81b, 0x3890, 0x3835, 0x3794, 0xb81e, 0x388d, 0x3832, 0x379a, 0xb821, 0x3889, 0x382f, 0x37a0, 0xb824, 0x3886, 0x382c, 0x37a6, 0xb828, 0x3883, 0x3829, 0x37ac, 0xb82b, 0x387f, 0x3826, 0x37b2, 0xb82e, 0x387c, 0x3823, 0x37b8, 0xb831, 0x3879, 0x3820, 0x37be, 0xb835, 0x3876, 0x381d, 0x37c4, 0xb838, 0x3872, 0x381a, 0x37ca, 0xb83b, 0x386f, 0x3817, 0x37d0, 0xb83e, 0x386c, 0x3814, 0x37d6, 0xb841, 0x3868, 0x3811, 0x37dc, 0xb845, 0x3865, 0x380e, 0x37e2, 0xb848, 0x3862, 0x380b, 0x37e8, 0xb84b, 0x385f, 0x3808, 0x37ee, 0xb84e, 0x385b, 0x3806, 0x37f4, 0xb852, 0x3858, 0x3803, 0x37fa, 0xb855, 0x3855, 0x3800, 0x3800, 0xb858, 0x3852, 0x37fa, 0x3803, 0xb85b, 0x384e, 0x37f4, 0x3806, 0xb85f, 0x384b, 0x37ee, 0x3808, 0xb862, 0x3848, 0x37e8, 0x380b, 0xb865, 0x3845, 0x37e2, 0x380e, 0xb868, 0x3841, 0x37dc, 0x3811, 0xb86c, 0x383e, 0x37d6, 0x3814, 0xb86f, 0x383b, 0x37d0, 0x3817, 0xb872, 0x3838, 0x37ca, 0x381a, 0xb876, 0x3835, 0x37c4, 0x381d, 0xb879, 0x3831, 0x37be, 0x3820, 0xb87c, 0x382e, 0x37b8, 0x3823, 0xb87f, 0x382b, 0x37b2, 0x3826, 0xb883, 0x3828, 0x37ac, 0x3829, 0xb886, 0x3824, 0x37a6, 0x382c, 0xb889, 0x3821, 0x37a0, 0x382f, 0xb88d, 0x381e, 0x379a, 0x3832, 0xb890, 0x381b, 0x3794, 0x3835, 0xb893, 0x3818, 0x378e, 0x3838, 0xb897, 0x3815, 0x3788, 0x383b, 0xb89a, 0x3811, 0x3782, 0x383e, 0xb89d, 0x380e, 0x377c, 0x3841, 0xb8a0, 0x380b, 0x3776, 0x3844, 0xb8a4, 0x3808, 0x3770, 0x3847, 0xb8a7, 0x3805, 0x376a, 0x384a, 0xb8aa, 0x3801, 0x3764, 0x384d, 0xb8ae, 0x37fd, 0x375e, 0x3850, 0xb8b1, 0x37f7, 0x3758, 0x3853, 0xb8b5, 0x37f1, 0x3752, 0x3856, 0xb8b8, 0x37ea, 0x374c, 0x3859, 0xb8bb, 0x37e4, 0x3746, 0x385c, 0xb8bf, 0x37de, 0x3740, 0x385f, 0xb8c2, 0x37d7, 0x373a, 0x3862, 0xb8c5, 0x37d1, 0x3734, 0x3865, 0xb8c9, 0x37cb, 0x372e, 0x3868, 0xb8cc, 0x37c5, 0x3728, 0x386b, 0xb8cf, 0x37be, 0x3722, 0x386e, 0xb8d3, 0x37b8, 0x371c, 0x3871, 0xb8d6, 0x37b2, 0x3716, 0x3874, 0xb8da, 0x37ac, 0x3710, 0x3877, 0xb8dd, 0x37a5, 0x370a, 0x387a, 0xb8e0, 0x379f, 0x3704, 0x387d, 0xb8e4, 0x3799, 0x36fe, 0x3880, 0xb8e7, 0x3793, 0x36f8, 0x3883, 0xb8eb, 0x378d, 0x36f2, 0x3886, 0xb8ee, 0x3787, 0x36ec, 0x3889, 0xb8f1, 0x3780, 0x36e7, 0x388c, 0xb8f5, 0x377a, 0x36e1, 0x388f, 0xb8f8, 0x3774, 0x36db, 0x3892, 0xb8fc, 0x376e, 0x36d5, 0x3895, 0xb8ff, 0x3768, 0x36cf, 0x3898, 0xb902, 0x3762, 0x36c9, 0x389b, 0xb906, 0x375b, 0x36c3, 0x389e, 0xb909, 0x3755, 0x36bd, 0x38a1, 0xb90d, 0x374f, 0x36b7, 0x38a4, 0xb910, 0x3749, 0x36b1, 0x38a7, 0xb914, 0x3743, 0x36ab, 0x38aa, 0xb917, 0x373d, 0x36a5, 0x38ad, 0xb91a, 0x3737, 0x36a0, 0x38af, 0xb91e, 0x3731, 0x369a, 0x38b2, 0xb921, 0x372b, 0x3694, 0x38b5, 0xb925, 0x3725, 0x368e, 0x38b8, 0xb928, 0x371f, 0x3688, 0x38bb, 0xb92c, 0x3719, 0x3682, 0x38be, 0xb92f, 0x3712, 0x367c, 0x38c1, 0xb933, 0x370c, 0x3676, 0x38c4, 0xb936, 0x3706, 0x3671, 0x38c7, 0xb93a, 0x3700, 0x366b, 0x38ca, 0xb93d, 0x36fa, 0x3665, 0x38cd, 0xb941, 0x36f4, 0x365f, 0x38d0, 0xb944, 0x36ee, 0x3659, 0x38d3, 0xb948, 0x36e8, 0x3653, 0x38d6, 0xb94b, 0x36e2, 0x364d, 0x38d9, 0xb94f, 0x36dc, 0x3648, 0x38db, 0xb952, 0x36d6, 0x3642, 0x38de, 0xb956, 0x36d1, 0x363c, 0x38e1, 0xb959, 0x36cb, 0x3636, 0x38e4, 0xb95d, 0x36c5, 0x3630, 0x38e7, 0xb960, 0x36bf, 0x362b, 0x38ea, 0xb964, 0x36b9, 0x3625, 0x38ed, 0xb967, 0x36b3, 0x361f, 0x38f0, 0xb96b, 0x36ad, 0x3619, 0x38f3, 0xb96e, 0x36a7, 0x3613, 0x38f6, 0xb972, 0x36a1, 0x360e, 0x38f8, 0xb975, 0x369b, 0x3608, 0x38fb, 0xb979, 0x3695, 0x3602, 0x38fe, 0xb97c, 0x368f, 0x35fc, 0x3901, 0xb980, 0x368a, 0x35f6, 0x3904, 0xb983, 0x3684, 0x35f1, 0x3907, 0xb987, 0x367e, 0x35eb, 0x390a, 0xb98a, 0x3678, 0x35e5, 0x390d, 0xb98e, 0x3672, 0x35df, 0x3910, 0xb992, 0x366c, 0x35da, 0x3912, 0xb995, 0x3667, 0x35d4, 0x3915, 0xb999, 0x3661, 0x35ce, 0x3918, 0xb99c, 0x365b, 0x35c9, 0x391b, 0xb9a0, 0x3655, 0x35c3, 0x391e, 0xb9a3, 0x364f, 0x35bd, 0x3921, 0xb9a7, 0x364a, 0x35b7, 0x3924, 0xb9ab, 0x3644, 0x35b2, 0x3926, 0xb9ae, 0x363e, 0x35ac, 0x3929, 0xb9b2, 0x3638, 0x35a6, 0x392c, 0xb9b5, 0x3633, 0x35a1, 0x392f, 0xb9b9, 0x362d, 0x359b, 0x3932, 0xb9bd, 0x3627, 0x3595, 0x3935, 0xb9c0, 0x3621, 0x3590, 0x3937, 0xb9c4, 0x361c, 0x358a, 0x393a, 0xb9c7, 0x3616, 0x3584, 0x393d, 0xb9cb, 0x3610, 0x357f, 0x3940, 0xb9cf, 0x360b, 0x3579, 0x3943, 0xb9d2, 0x3605, 0x3573, 0x3946, 0xb9d6, 0x35ff, 0x356e, 0x3948, 0xb9d9, 0x35fa, 0x3568, 0x394b, 0xb9dd, 0x35f4, 0x3563, 0x394e, 0xb9e1, 0x35ee, 0x355d, 0x3951, 0xb9e4, 0x35e9, 0x3557, 0x3954, 0xb9e8, 0x35e3, 0x3552, 0x3956, 0xb9ec, 0x35dd, 0x354c, 0x3959, 0xb9ef, 0x35d8, 0x3547, 0x395c, 0xb9f3, 0x35d2, 0x3541, 0x395f, 0xb9f7, 0x35cd, 0x353c, 0x3961, 0xb9fa, 0x35c7, 0x3536, 0x3964, 0xb9fe, 0x35c1, 0x3530, 0x3967, 0xba02, 0x35bc, 0x352b, 0x396a, 0xba05, 0x35b6, 0x3525, 0x396d, 0xba09, 0x35b1, 0x3520, 0x396f, 0xba0d, 0x35ab, 0x351a, 0x3972, 0xba10, 0x35a6, 0x3515, 0x3975, 0xba14, 0x35a0, 0x350f, 0x3978, 0xba18, 0x359b, 0x350a, 0x397a, 0xba1b, 0x3595, 0x3504, 0x397d, 0xba1f, 0x3590, 0x34ff, 0x3980, 0xba23, 0x358a, 0x34f9, 0x3983, 0xba26, 0x3585, 0x34f4, 0x3985, 0xba2a, 0x357f, 0x34ef, 0x3988, 0xba2e, 0x357a, 0x34e9, 0x398b, 0xba32, 0x3574, 0x34e4, 0x398d, 0xba35, 0x356f, 0x34de, 0x3990, 0xba39, 0x3569, 0x34d9, 0x3993, 0xba3d, 0x3564, 0x34d3, 0x3996, 0xba40, 0x355e, 0x34ce, 0x3998, 0xba44, 0x3559, 0x34c9, 0x399b, 0xba48, 0x3554, 0x34c3, 0x399e, 0xba4c, 0x354e, 0x34be, 0x39a0, 0xba4f, 0x3549, 0x34b9, 0x39a3, 0xba53, 0x3543, 0x34b3, 0x39a6, 0xba57, 0x353e, 0x34ae, 0x39a8, 0xba5a, 0x3539, 0x34a8, 0x39ab, 0xba5e, 0x3533, 0x34a3, 0x39ae, 0xba62, 0x352e, 0x349e, 0x39b0, 0xba66, 0x3529, 0x3499, 0x39b3, 0xba6a, 0x3523, 0x3493, 0x39b6, 0xba6d, 0x351e, 0x348e, 0x39b8, 0xba71, 0x3519, 0x3489, 0x39bb, 0xba75, 0x3513, 0x3483, 0x39be, 0xba79, 0x350e, 0x347e, 0x39c0, 0xba7c, 0x3509, 0x3479, 0x39c3, 0xba80, 0x3504, 0x3474, 0x39c5, 0xba84, 0x34fe, 0x346e, 0x39c8, 0xba88, 0x34f9, 0x3469, 0x39cb, 0xba8b, 0x34f4, 0x3464, 0x39cd, 0xba8f, 0x34ef, 0x345f, 0x39d0, 0xba93, 0x34e9, 0x345a, 0x39d2, 0xba97, 0x34e4, 0x3454, 0x39d5, 0xba9b, 0x34df, 0x344f, 0x39d8, 0xba9e, 0x34da, 0x344a, 0x39da, 0xbaa2, 0x34d5, 0x3445, 0x39dd, 0xbaa6, 0x34cf, 0x3440, 0x39df, 0xbaaa, 0x34ca, 0x343b, 0x39e2, 0xbaae, 0x34c5, 0x3435, 0x39e5, 0xbab1, 0x34c0, 0x3430, 0x39e7, 0xbab5, 0x34bb, 0x342b, 0x39ea, 0xbab9, 0x34b6, 0x3426, 0x39ec, 0xbabd, 0x34b1, 0x3421, 0x39ef, 0xbac1, 0x34ac, 0x341c, 0x39f1, 0xbac5, 0x34a6, 0x3417, 0x39f4, 0xbac8, 0x34a1, 0x3412, 0x39f6, 0xbacc, 0x349c, 0x340d, 0x39f9, 0xbad0, 0x3497, 0x3408, 0x39fb, 0xbad4, 0x3492, 0x3403, 0x39fe, 0xbad8, 0x348d, 0x33fc, 0x3a00, 0xbadc, 0x3488, 0x33f2, 0x3a03, 0xbae0, 0x3483, 0x33e8, 0x3a05, 0xbae3, 0x347e, 0x33de, 0x3a08, 0xbae7, 0x3479, 0x33d4, 0x3a0a, 0xbaeb, 0x3474, 0x33ca, 0x3a0d, 0xbaef, 0x346f, 0x33c1, 0x3a0f, 0xbaf3, 0x346a, 0x33b7, 0x3a12, 0xbaf7, 0x3465, 0x33ad, 0x3a14, 0xbafb, 0x3460, 0x33a3, 0x3a17, 0xbafe, 0x345b, 0x3399, 0x3a19, 0xbb02, 0x3456, 0x3390, 0x3a1c, 0xbb06, 0x3451, 0x3386, 0x3a1e, 0xbb0a, 0x344d, 0x337c, 0x3a20, 0xbb0e, 0x3448, 0x3372, 0x3a23, 0xbb12, 0x3443, 0x3369, 0x3a25, 0xbb16, 0x343e, 0x335f, 0x3a28, 0xbb1a, 0x3439, 0x3355, 0x3a2a, 0xbb1e, 0x3434, 0x334c, 0x3a2c, 0xbb21, 0x342f, 0x3342, 0x3a2f, 0xbb25, 0x342a, 0x3339, 0x3a31, 0xbb29, 0x3426, 0x332f, 0x3a34, 0xbb2d, 0x3421, 0x3326, 0x3a36, 0xbb31, 0x341c, 0x331c, 0x3a38, 0xbb35, 0x3417, 0x3313, 0x3a3b, 0xbb39, 0x3412, 0x3309, 0x3a3d, 0xbb3d, 0x340e, 0x3300, 0x3a3f, 0xbb41, 0x3409, 0x32f7, 0x3a42, 0xbb45, 0x3404, 0x32ed, 0x3a44, 0xbb49, 0x33ff, 0x32e4, 0x3a46, 0xbb4d, 0x33f6, 0x32db, 0x3a49, 0xbb51, 0x33ed, 0x32d1, 0x3a4b, 0xbb54, 0x33e3, 0x32c8, 0x3a4d, 0xbb58, 0x33da, 0x32bf, 0x3a50, 0xbb5c, 0x33d0, 0x32b6, 0x3a52, 0xbb60, 0x33c7, 0x32ad, 0x3a54, 0xbb64, 0x33be, 0x32a3, 0x3a57, 0xbb68, 0x33b5, 0x329a, 0x3a59, 0xbb6c, 0x33ab, 0x3291, 0x3a5b, 0xbb70, 0x33a2, 0x3288, 0x3a5d, 0xbb74, 0x3399, 0x327f, 0x3a60, 0xbb78, 0x3390, 0x3276, 0x3a62, 0xbb7c, 0x3387, 0x326d, 0x3a64, 0xbb80, 0x337d, 0x3264, 0x3a66, 0xbb84, 0x3374, 0x325b, 0x3a69, 0xbb88, 0x336b, 0x3252, 0x3a6b, 0xbb8c, 0x3362, 0x3249, 0x3a6d, 0xbb90, 0x3359, 0x3241, 0x3a6f, 0xbb94, 0x3350, 0x3238, 0x3a71, 0xbb98, 0x3347, 0x322f, 0x3a74, 0xbb9c, 0x333e, 0x3226, 0x3a76, 0xbba0, 0x3335, 0x321e, 0x3a78, 0xbba4, 0x332c, 0x3215, 0x3a7a, 0xbba8, 0x3323, 0x320c, 0x3a7c, 0xbbac, 0x331a, 0x3204, 0x3a7e, 0xbbb0, 0x3312, 0x31fb, 0x3a81, 0xbbb4, 0x3309, 0x31f2, 0x3a83, 0xbbb8, 0x3300, 0x31ea, 0x3a85, 0xbbbc, 0x32f7, 0x31e1, 0x3a87, 0xbbc0, 0x32ee, 0x31d9, 0x3a89, 0xbbc4, 0x32e6, 0x31d0, 0x3a8b, 0xbbc8, 0x32dd, 0x31c8, 0x3a8d, 0xbbcc, 0x32d4, 0x31bf, 0x3a90, 0xbbd0, 0x32cc, 0x31b7, 0x3a92, 0xbbd4, 0x32c3, 0x31af, 0x3a94, 0xbbd8, 0x32ba, 0x31a6, 0x3a96, 0xbbdc, 0x32b2, 0x319e, 0x3a98, 0xbbe0, 0x32a9, 0x3196, 0x3a9a, 0xbbe4, 0x32a1, 0x318e, 0x3a9c, 0xbbe8, 0x3298, 0x3185, 0x3a9e, 0xbbec, 0x3290, 0x317d, 0x3aa0, 0xbbf0, 0x3287, 0x3175, 0x3aa2, 0xbbf4, 0x327f, 0x316d, 0x3aa4, 0xbbf8, 0x3277, 0x3165, 0x3aa6, 0xbbfc, 0x326e, 0x315d, 0x3aa8, 0 }; xserver-xorg-video-ati-7.5.0+git20150819/src/bicubic_table.py000077500000000000000000000023661256524674500234300ustar00rootroot00000000000000#!/usr/bin/python import struct def half(i): fs, fe, fm = ((i >> 31) & 0x1, (i >> 23) & 0xff, i & 0x7fffff) s, e, m = (fs, 0, 0) if (fe == 0x0): pass if ((fe == 0xff) and (fm == 0x0)): e = 31 elif (fe == 0xff): m = 1 e = 31 else: exp = fe - 127; if (exp < -24): pass elif (exp < -14): temp = 10 - (-14 - exp) m = 2**temp + (m >> (23 - temp)) elif (exp > 15): e = 31 else: e = exp + 15 m = fm >> 13 return ((s << 15) | (e << 10) | m) def texgen(pix): tex = [] for i in range(0,pix,4): a = i / float(pix) a2 = a ** 2 a3 = a ** 3 w0 = 1 / 6.0 * (-a3 + 3 * a2 + -3 * a + 1) w1 = 1 / 6.0 * (3 * a3 + -6 * a2 + 4) w2 = 1 / 6.0 * (-3 * a3 + 3 * a2 + 3 * a + 1) w3 = 1 / 6.0 * a3 tex.append(-(1 - (w1 / (w0 + w1)) + a)) tex.append(1 + (w3 / (w2 + w3)) - a) tex.append(w0 + w1) tex.append(w2 + w3) return tex def printrow(l, offset): seq = [ struct.unpack(' * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include #include "radeon.h" #include "radeon_reg.h" #include "cayman_reg.h" #include "evergreen_state.h" #include "radeon_vbo.h" #include "radeon_exa_shared.h" /* * Setup of default state */ void cayman_set_default_state(ScrnInfoPtr pScrn) { tex_resource_t tex_res; shader_config_t fs_conf; int i; RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->XInited3D) return; memset(&tex_res, 0, sizeof(tex_resource_t)); memset(&fs_conf, 0, sizeof(shader_config_t)); accel_state->XInited3D = TRUE; evergreen_start_3d(pScrn); BEGIN_BATCH(21); EREG(SQ_LDS_ALLOC_PS, 0); PACK0(SQ_ESGS_RING_ITEMSIZE, 6); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); PACK0(SQ_GS_VERT_ITEMSIZE, 4); E32(0); E32(0); E32(0); E32(0); PACK0(SQ_VTX_BASE_VTX_LOC, 2); E32(0); E32(0); END_BATCH(); /* DB */ BEGIN_BATCH(3 + 2); EREG(DB_Z_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(DB_STENCIL_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(DB_HTILE_DATA_BASE, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(52); EREG(DB_DEPTH_INFO, 0); EREG(DB_DEPTH_CONTROL, 0); PACK0(PA_SC_VPORT_ZMIN_0, 2); EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0 EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0 PACK0(DB_RENDER_CONTROL, 5); E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL E32(0); // DB_COUNT_CONTROL E32(0); // DB_DEPTH_VIEW E32(0x2a); // DB_RENDER_OVERRIDE E32(0); // DB_RENDER_OVERRIDE2 PACK0(DB_STENCIL_CLEAR, 2); E32(0); // DB_STENCIL_CLEAR E32(0); // DB_DEPTH_CLEAR EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | (2 << ALPHA_TO_MASK_OFFSET1_shift) | (2 << ALPHA_TO_MASK_OFFSET2_shift) | (2 << ALPHA_TO_MASK_OFFSET3_shift))); EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) | DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ // SX EREG(SX_MISC, 0); // CB PACK0(SX_ALPHA_TEST_CONTROL, 5); E32(0); // SX_ALPHA_TEST_CONTROL E32(0x00000000); //CB_BLEND_RED E32(0x00000000); //CB_BLEND_GREEN E32(0x00000000); //CB_BLEND_BLUE E32(0x00000000); //CB_BLEND_ALPHA EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask); // SC EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | (0 << WINDOW_Y_OFFSET_shift))); EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); EREG(PA_SC_EDGERULE, 0xAAAAAAAA); EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0); END_BATCH(); /* clip boolean is set to always visible -> doesn't matter */ for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192); for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192); BEGIN_BATCH(73); PACK0(PA_SC_MODE_CNTL_0, 2); E32(0); // PA_SC_MODE_CNTL_0 E32(0); // PA_SC_MODE_CNTL_1 PACK0(PA_SC_CENTROID_PRIORITY_0, 27); E32((0 << DISTANCE_0_shift) | (1 << DISTANCE_1_shift) | (2 << DISTANCE_2_shift) | (3 << DISTANCE_3_shift) | (4 << DISTANCE_4_shift) | (5 << DISTANCE_5_shift) | (6 << DISTANCE_6_shift) | (7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0 E32((8 << DISTANCE_8_shift) | (9 << DISTANCE_9_shift) | (10 << DISTANCE_10_shift) | (11 << DISTANCE_11_shift) | (12 << DISTANCE_12_shift) | (13 << DISTANCE_13_shift) | (14 << DISTANCE_14_shift) | (15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1 E32(0); // PA_SC_LINE_CNTL E32(0); // PA_SC_AA_CONFIG E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit)); // PA_SU_VTX_CNTL EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_* E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_* E32(0xFFFFFFFF); // PA_SC_AA_MASK_* E32(0xFFFFFFFF); // PA_SC_AA_MASK_* // CL PACK0(PA_CL_CLIP_CNTL, 8); E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL E32(FACE_bit); // PA_SU_SC_MODE_CNTL E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL E32(0); // PA_CL_VS_OUT_CNTL E32(0); // PA_CL_NANINF_CNTL E32(0); // PA_SU_LINE_STIPPLE_CNTL E32(0); // PA_SU_LINE_STIPPLE_SCALE E32(0); // PA_SU_PRIM_FILTER_CNTL // SU PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); /* src = semantic id 0; mask = semantic id 1 */ EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | (1 << SEMANTIC_1_shift))); PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ E32(((0 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift))); /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ E32(((1 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift))); PACK0(SPI_INPUT_Z, 13); E32(0); // SPI_INPUT_Z E32(0); // SPI_FOG_CNTL E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL E32(0); // SPI_PS_IN_CONTROL_2 E32(0); E32(0); E32(0); E32(0); E32(0); // SPI_GPR_MGMT E32(0); // SPI_LDS_MGMT E32(0); // SPI_STACK_MGMT E32(0); // SPI_WAVE_MGMT_1 E32(0); // SPI_WAVE_MGMT_2 END_BATCH(); // clear FS fs_conf.bo = accel_state->shaders_bo; evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM); // VGT BEGIN_BATCH(46); PACK0(VGT_MAX_VTX_INDX, 4); E32(0xffffff); E32(0); E32(0); E32(0); PACK0(VGT_INSTANCE_STEP_RATE_0, 2); E32(0); E32(0); PACK0(VGT_REUSE_OFF, 2); E32(0); E32(0); PACK0(PA_SU_POINT_SIZE, 17); E32(0); // PA_SU_POINT_SIZE E32(0); // PA_SU_POINT_MINMAX E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL E32(0); // PA_SC_LINE_STIPPLE E32(0); // VGT_OUTPUT_PATH_CNTL E32(0); // VGT_HOS_CNTL E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); // VGT_GS_MODE EREG(VGT_PRIMITIVEID_EN, 0); EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0); EREG(VGT_SHADER_STAGES_EN, 0); PACK0(VGT_STRMOUT_CONFIG, 2); E32(0); E32(0); END_BATCH(); } xserver-xorg-video-ati-7.5.0+git20150819/src/cayman_reg.h000066400000000000000000000301721256524674500225560ustar00rootroot00000000000000/* * Cayman Register documentation * * Copyright (C) 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _CAYMAN_REG_H_ #define _CAYMAN_REG_H_ /* * Register definitions */ #include "cayman_reg_auto.h" enum { SHADER_TYPE_PS, SHADER_TYPE_VS, SHADER_TYPE_GS, SHADER_TYPE_HS, SHADER_TYPE_LS, SHADER_TYPE_CS, SHADER_TYPE_FS, }; /* SET_*_REG offsets + ends */ #define SET_CONFIG_REG_offset 0x00008000 #define SET_CONFIG_REG_end 0x0000ac00 #define SET_CONTEXT_REG_offset 0x00028000 #define SET_CONTEXT_REG_end 0x00029000 #define SET_RESOURCE_offset 0x00030000 #define SET_RESOURCE_end 0x00038000 #define SET_SAMPLER_offset 0x0003c000 #define SET_SAMPLER_end 0x0003c600 #define SET_CTL_CONST_offset 0x0003cff0 #define SET_CTL_CONST_end 0x0003ff0c #define SET_LOOP_CONST_offset 0x0003a200 #define SET_LOOP_CONST_end 0x0003a500 #define SET_BOOL_CONST_offset 0x0003a500 #define SET_BOOL_CONST_end 0x0003a518 /* Packet3 commands */ enum { IT_NOP = 0x10, IT_INDIRECT_BUFFER_END = 0x17, IT_SET_PREDICATION = 0x20, IT_COND_EXEC = 0x22, IT_PRED_EXEC = 0x23, IT_DRAW_INDEX_2 = 0x27, IT_CONTEXT_CONTROL = 0x28, IT_DRAW_INDEX_OFFSET = 0x29, IT_INDEX_TYPE = 0x2A, IT_DRAW_INDEX = 0x2B, IT_DRAW_INDEX_AUTO = 0x2D, IT_DRAW_INDEX_IMMD = 0x2E, IT_NUM_INSTANCES = 0x2F, IT_INDIRECT_BUFFER = 0x32, IT_STRMOUT_BUFFER_UPDATE = 0x34, IT_MEM_SEMAPHORE = 0x39, IT_MPEG_INDEX = 0x3A, IT_WAIT_REG_MEM = 0x3C, IT_MEM_WRITE = 0x3D, IT_SURFACE_SYNC = 0x43, IT_ME_INITIALIZE = 0x44, IT_COND_WRITE = 0x45, IT_EVENT_WRITE = 0x46, IT_EVENT_WRITE_EOP = 0x47, IT_EVENT_WRITE_EOS = 0x48, IT_SET_CONFIG_REG = 0x68, IT_SET_CONTEXT_REG = 0x69, IT_SET_ALU_CONST = 0x6A, IT_SET_BOOL_CONST = 0x6B, IT_SET_LOOP_CONST = 0x6C, IT_SET_RESOURCE = 0x6D, IT_SET_SAMPLER = 0x6E, IT_SET_CTL_CONST = 0x6F, }; /* IT_WAIT_REG_MEM operation encoding */ #define IT_WAIT_ALWAYS (0 << 0) #define IT_WAIT_LT (1 << 0) #define IT_WAIT_LE (2 << 0) #define IT_WAIT_EQ (3 << 0) #define IT_WAIT_NE (4 << 0) #define IT_WAIT_GE (5 << 0) #define IT_WAIT_GT (6 << 0) #define IT_WAIT_REG (0 << 4) #define IT_WAIT_MEM (1 << 4) #define IT_WAIT_ADDR(x) ((x) >> 2) enum { SQ_LDS_ALLOC_PS = 0x288ec, SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c, CP_COHER_CNTL = 0x85f0, DEST_BASE_0_ENA_bit = 1 << 0, DEST_BASE_1_ENA_bit = 1 << 1, SO0_DEST_BASE_ENA_bit = 1 << 2, SO1_DEST_BASE_ENA_bit = 1 << 3, SO2_DEST_BASE_ENA_bit = 1 << 4, SO3_DEST_BASE_ENA_bit = 1 << 5, CB0_DEST_BASE_ENA_bit = 1 << 6, CB1_DEST_BASE_ENA_bit = 1 << 7, CB2_DEST_BASE_ENA_bit = 1 << 8, CB3_DEST_BASE_ENA_bit = 1 << 9, CB4_DEST_BASE_ENA_bit = 1 << 10, CB5_DEST_BASE_ENA_bit = 1 << 11, CB6_DEST_BASE_ENA_bit = 1 << 12, CB7_DEST_BASE_ENA_bit = 1 << 13, DB_DEST_BASE_ENA_bit = 1 << 14, CB8_DEST_BASE_ENA_bit = 1 << 15, CB9_DEST_BASE_ENA_bit = 1 << 16, CB10_DEST_BASE_ENA_bit = 1 << 17, CB11_DEST_BASE_ENA_bit = 1 << 18, FULL_CACHE_ENA_bit = 1 << 20, TC_ACTION_ENA_bit = 1 << 23, CB_ACTION_ENA_bit = 1 << 25, DB_ACTION_ENA_bit = 1 << 26, SH_ACTION_ENA_bit = 1 << 27, SX_ACTION_ENA_bit = 1 << 28, CP_COHER_SIZE = 0x85f4, CP_COHER_BASE = 0x85f8, CP_COHER_STATUS = 0x85fc, MATCHING_GFX_CNTX_mask = 0xff << 0, MATCHING_GFX_CNTX_shift = 0, STATUS_bit = 1 << 31, // SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, // SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, FMT_16=5, FMT_16_FLOAT, FMT_8_8, FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, FMT_1 = 37, FMT_GB_GR=39, FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, FMT_32_32_32_FLOAT=48, // High level register file lengths SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, SQ_FETCH_RESOURCE_ps_num = 176, SQ_FETCH_RESOURCE_vs_num = 160, SQ_FETCH_RESOURCE_gs_num = 160, SQ_FETCH_RESOURCE_hs_num = 160, SQ_FETCH_RESOURCE_ls_num = 160, SQ_FETCH_RESOURCE_cs_num = 176, SQ_FETCH_RESOURCE_fs_num = 32, SQ_FETCH_RESOURCE_all_num = 1024, SQ_FETCH_RESOURCE_offset = 32, SQ_FETCH_RESOURCE_ps = 0, // 0...175 SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335 SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495 SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655 SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815 SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991 SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023 SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, SQ_TEX_SAMPLER_WORD_ps_num = 18, SQ_TEX_SAMPLER_WORD_vs_num = 18, SQ_TEX_SAMPLER_WORD_gs_num = 18, SQ_TEX_SAMPLER_WORD_hs_num = 18, SQ_TEX_SAMPLER_WORD_ls_num = 18, SQ_TEX_SAMPLER_WORD_cs_num = 18, SQ_TEX_SAMPLER_WORD_all_num = 108, SQ_TEX_SAMPLER_WORD_offset = 12, SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17 SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35 SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53 SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71 SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89 SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107 SQ_LOOP_CONST = SQ_LOOP_CONST_0, SQ_LOOP_CONST_ps_num = 32, SQ_LOOP_CONST_vs_num = 32, SQ_LOOP_CONST_gs_num = 32, SQ_LOOP_CONST_hs_num = 32, SQ_LOOP_CONST_ls_num = 32, SQ_LOOP_CONST_cs_num = 32, SQ_LOOP_CONST_all_num = 192, SQ_LOOP_CONST_offset = 4, SQ_LOOP_CONST_ps = 0, // 0...31 SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63 SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95 SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127 SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159 SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191 SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */ SQ_BOOL_CONST_ps_num = 1, SQ_BOOL_CONST_vs_num = 1, SQ_BOOL_CONST_gs_num = 1, SQ_BOOL_CONST_hs_num = 1, SQ_BOOL_CONST_ls_num = 1, SQ_BOOL_CONST_cs_num = 1, SQ_BOOL_CONST_all_num = 6, SQ_BOOL_CONST_offset = 4, SQ_BOOL_CONST_ps = 0, SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num, SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num, SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num, }; #endif xserver-xorg-video-ati-7.5.0+git20150819/src/cayman_reg_auto.h000066400000000000000000010244771256524674500236220ustar00rootroot00000000000000/* * Cayman Register documentation * * Copyright (C) 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _CAYMAN_REG_AUTO #define _CAYMAN_REG_AUTO enum { VGT_VTX_VECT_EJECT_REG = 0x000088b0, PRIM_COUNT_mask = 0x3ff << 0, PRIM_COUNT_shift = 0, VGT_LAST_COPY_STATE = 0x000088c0, SRC_STATE_ID_mask = 0x07 << 0, SRC_STATE_ID_shift = 0, DST_STATE_ID_mask = 0x07 << 16, DST_STATE_ID_shift = 16, VGT_CACHE_INVALIDATION = 0x000088c4, CACHE_INVALIDATION_mask = 0x03 << 0, CACHE_INVALIDATION_shift = 0, VC_ONLY = 0x00, TC_ONLY = 0x01, VC_AND_TC = 0x02, VS_NO_EXTRA_BUFFER_bit = 1 << 5, AUTO_INVLD_EN_mask = 0x03 << 6, AUTO_INVLD_EN_shift = 6, VGT_GS_VERTEX_REUSE = 0x000088d4, VERT_REUSE_mask = 0x1f << 0, VERT_REUSE_shift = 0, VGT_CNTL_STATUS = 0x000088f0, VGT_OUT_INDX_BUSY_bit = 1 << 0, VGT_OUT_BUSY_bit = 1 << 1, VGT_PT_BUSY_bit = 1 << 2, VGT_TE_BUSY_bit = 1 << 3, VGT_VR_BUSY_bit = 1 << 4, VGT_PI_BUSY_bit = 1 << 5, VGT_INVLD_BUSY_bit = 1 << 6, VGT_GS_BUSY_bit = 1 << 7, VGT_HS_BUSY_bit = 1 << 8, VGT_TE11_BUSY_bit = 1 << 9, VGT_BUSY_bit = 1 << 10, VGT_PRIMITIVE_TYPE = 0x00008958, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, DI_PT_NONE = 0x00, DI_PT_POINTLIST = 0x01, DI_PT_LINELIST = 0x02, DI_PT_LINESTRIP = 0x03, DI_PT_TRILIST = 0x04, DI_PT_TRIFAN = 0x05, DI_PT_TRISTRIP = 0x06, DI_PT_UNUSED_0 = 0x07, DI_PT_UNUSED_1 = 0x08, DI_PT_PATCH = 0x09, DI_PT_LINELIST_ADJ = 0x0a, DI_PT_LINESTRIP_ADJ = 0x0b, DI_PT_TRILIST_ADJ = 0x0c, DI_PT_TRISTRIP_ADJ = 0x0d, DI_PT_UNUSED_3 = 0x0e, DI_PT_UNUSED_4 = 0x0f, DI_PT_TRI_WITH_WFLAGS = 0x10, DI_PT_RECTLIST = 0x11, DI_PT_LINELOOP = 0x12, DI_PT_QUADLIST = 0x13, DI_PT_QUADSTRIP = 0x14, DI_PT_POLYGON = 0x15, DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, DI_PT_2D_FILL_RECT_LIST = 0x1a, DI_PT_2D_LINE_STRIP = 0x1b, DI_PT_2D_TRI_STRIP = 0x1c, VGT_INDEX_TYPE = 0x0000895c, INDEX_TYPE_mask = 0x03 << 0, INDEX_TYPE_shift = 0, DI_INDEX_SIZE_16_BIT = 0x00, DI_INDEX_SIZE_32_BIT = 0x01, VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, VGT_NUM_INDICES = 0x00008970, VGT_NUM_INSTANCES = 0x00008974, VGT_SYS_CONFIG = 0x0000898c, DUAL_CORE_EN_bit = 1 << 0, MAX_LS_HS_THDGRP_mask = 0x3f << 1, MAX_LS_HS_THDGRP_shift = 1, PA_CL_CNTL_STATUS = 0x00008a10, CL_BUSY_bit = 1 << 31, PA_CL_ENHANCE = 0x00008a14, CLIP_VTX_REORDER_ENA_bit = 1 << 0, NUM_CLIP_SEQ_mask = 0x03 << 1, NUM_CLIP_SEQ_shift = 1, CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, VE_NAN_PROC_DISABLE_bit = 1 << 4, PA_SU_CNTL_STATUS = 0x00008a50, SU_BUSY_bit = 1 << 31, PA_SU_LINE_STIPPLE_VALUE = 0x00008a60, LINE_STIPPLE_VALUE_mask = 0xffffff << 0, LINE_STIPPLE_VALUE_shift = 0, PA_SC_LINE_STIPPLE_STATE = 0x00008b10, CURRENT_PTR_mask = 0x0f << 0, CURRENT_PTR_shift = 0, CURRENT_COUNT_mask = 0xff << 8, CURRENT_COUNT_shift = 8, SQ_CONFIG = 0x00008c00, VC_ENABLE_bit = 1 << 0, EXPORT_SRC_C_bit = 1 << 1, GFX_PRIO_mask = 0x03 << 2, GFX_PRIO_shift = 2, CS1_PRIO_mask = 0x03 << 4, CS1_PRIO_shift = 4, CS2_PRIO_mask = 0x03 << 6, CS2_PRIO_shift = 6, SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS_mask = 0xff << 0, SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS_shift = 0, SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS_mask = 0xff << 16, SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS_shift = 16, NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, NUM_CLAUSE_TEMP_GPRS_shift = 28, SQ_GLOBAL_GPR_RESOURCE_MGMT_1 = 0x00008c10, PS_GGPR_BASE_mask = 0xff << 0, PS_GGPR_BASE_shift = 0, VS_GGPR_BASE_mask = 0xff << 8, VS_GGPR_BASE_shift = 8, GS_GGPR_BASE_mask = 0xff << 16, GS_GGPR_BASE_shift = 16, ES_GGPR_BASE_mask = 0xff << 24, ES_GGPR_BASE_shift = 24, SQ_GLOBAL_GPR_RESOURCE_MGMT_2 = 0x00008c14, HS_GGPR_BASE_mask = 0xff << 0, HS_GGPR_BASE_shift = 0, LS_GGPR_BASE_mask = 0xff << 8, LS_GGPR_BASE_shift = 8, CS_GGPR_BASE_mask = 0xff << 16, CS_GGPR_BASE_shift = 16, SQ_ESGS_RING_BASE = 0x00008c40, SQ_ESGS_RING_SIZE = 0x00008c44, SQ_GSVS_RING_BASE = 0x00008c48, SQ_GSVS_RING_SIZE = 0x00008c4c, SQ_ESTMP_RING_BASE = 0x00008c50, SQ_ESTMP_RING_SIZE = 0x00008c54, SQ_GSTMP_RING_BASE = 0x00008c58, SQ_GSTMP_RING_SIZE = 0x00008c5c, SQ_VSTMP_RING_BASE = 0x00008c60, SQ_VSTMP_RING_SIZE = 0x00008c64, SQ_PSTMP_RING_BASE = 0x00008c68, SQ_PSTMP_RING_SIZE = 0x00008c6c, SQ_ALU_WORD1_OP3 = 0x00008dfc, SRC2_SEL_mask = 0x1ff << 0, SRC2_SEL_shift = 0, SQ_ALU_SRC_LDS_OQ_A = 0xdb, SQ_ALU_SRC_LDS_OQ_B = 0xdc, SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, SQ_ALU_SRC_TIME_HI = 0xe3, SQ_ALU_SRC_TIME_LO = 0xe4, SQ_ALU_SRC_MASK_HI = 0xe5, SQ_ALU_SRC_MASK_LO = 0xe6, SQ_ALU_SRC_HW_WAVE_ID = 0xe7, SQ_ALU_SRC_SIMD_ID = 0xe8, SQ_ALU_SRC_SE_ID = 0xe9, SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, SQ_ALU_SRC_HW_ALU_ODD = 0xed, SQ_ALU_SRC_LOOP_IDX = 0xee, SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, SQ_ALU_SRC_1_DBL_L = 0xf4, SQ_ALU_SRC_1_DBL_M = 0xf5, SQ_ALU_SRC_0_5_DBL_L = 0xf6, SQ_ALU_SRC_0_5_DBL_M = 0xf7, SQ_ALU_SRC_0 = 0xf8, SQ_ALU_SRC_1 = 0xf9, SQ_ALU_SRC_1_INT = 0xfa, SQ_ALU_SRC_M_1_INT = 0xfb, SQ_ALU_SRC_0_5 = 0xfc, SQ_ALU_SRC_LITERAL = 0xfd, SQ_ALU_SRC_PV = 0xfe, SQ_ALU_SRC_PS = 0xff, SRC2_REL_bit = 1 << 9, SRC2_CHAN_mask = 0x03 << 10, SRC2_CHAN_shift = 10, SQ_CHAN_X = 0x00, SQ_CHAN_Y = 0x01, SQ_CHAN_Z = 0x02, SQ_CHAN_W = 0x03, SRC2_NEG_bit = 1 << 12, SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, SQ_OP3_INST_BFE_UINT = 0x04, SQ_OP3_INST_BFE_INT = 0x05, SQ_OP3_INST_BFI_INT = 0x06, SQ_OP3_INST_FMA = 0x07, SQ_OP3_INST_CNDNE_64 = 0x09, SQ_OP3_INST_FMA_64 = 0x0a, SQ_OP3_INST_LERP_UINT = 0x0b, SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, SQ_OP3_INST_MULADD_UINT24 = 0x10, SQ_OP3_INST_LDS_IDX_OP = 0x11, SQ_OP3_INST_MULADD = 0x14, SQ_OP3_INST_MULADD_M2 = 0x15, SQ_OP3_INST_MULADD_M4 = 0x16, SQ_OP3_INST_MULADD_D2 = 0x17, SQ_OP3_INST_MULADD_IEEE = 0x18, SQ_OP3_INST_CNDE = 0x19, SQ_OP3_INST_CNDGT = 0x1a, SQ_OP3_INST_CNDGE = 0x1b, SQ_OP3_INST_CNDE_INT = 0x1c, SQ_OP3_INST_CNDGT_INT = 0x1d, SQ_OP3_INST_CNDGE_INT = 0x1e, SQ_OP3_INST_MUL_LIT = 0x1f, SQ_ALU_WORD1_LDS_DIRECT_LITERAL_LO = 0x00008dfc, OFFSET_A_mask = 0x1fff << 0, OFFSET_A_shift = 0, STRIDE_A_mask = 0x7f << 13, STRIDE_A_shift = 13, THREAD_REL_A_bit = 1 << 22, SQ_TEX_WORD2 = 0x00008dfc, OFFSET_X_mask = 0x1f << 0, OFFSET_X_shift = 0, OFFSET_Y_mask = 0x1f << 5, OFFSET_Y_shift = 5, OFFSET_Z_mask = 0x1f << 10, OFFSET_Z_shift = 10, SAMPLER_ID_mask = 0x1f << 15, SAMPLER_ID_shift = 15, SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, SQ_TEX_WORD2__SRC_SEL_X_shift = 20, SQ_SEL_X = 0x00, SQ_SEL_Y = 0x01, SQ_SEL_Z = 0x02, SQ_SEL_W = 0x03, SQ_SEL_0 = 0x04, SQ_SEL_1 = 0x05, SQ_TEX_WORD2__SRC_SEL_Y_mask = 0x07 << 23, SQ_TEX_WORD2__SRC_SEL_Y_shift = 23, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_Z_mask = 0x07 << 26, SRC_SEL_Z_shift = 26, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_W_mask = 0x07 << 29, SRC_SEL_W_shift = 29, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, BURST_COUNT_mask = 0x0f << 16, BURST_COUNT_shift = 16, VALID_PIXEL_MODE_bit = 1 << 20, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xff << 22, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, SQ_CF_INST_MEM_STREAM0_BUF0 = 0x40, SQ_CF_INST_MEM_STREAM0_BUF1 = 0x41, SQ_CF_INST_MEM_STREAM0_BUF2 = 0x42, SQ_CF_INST_MEM_STREAM0_BUF3 = 0x43, SQ_CF_INST_MEM_STREAM1_BUF0 = 0x44, SQ_CF_INST_MEM_STREAM1_BUF1 = 0x45, SQ_CF_INST_MEM_STREAM1_BUF2 = 0x46, SQ_CF_INST_MEM_STREAM1_BUF3 = 0x47, SQ_CF_INST_MEM_STREAM2_BUF0 = 0x48, SQ_CF_INST_MEM_STREAM2_BUF1 = 0x49, SQ_CF_INST_MEM_STREAM2_BUF2 = 0x4a, SQ_CF_INST_MEM_STREAM2_BUF3 = 0x4b, SQ_CF_INST_MEM_STREAM3_BUF0 = 0x4c, SQ_CF_INST_MEM_STREAM3_BUF1 = 0x4d, SQ_CF_INST_MEM_STREAM3_BUF2 = 0x4e, SQ_CF_INST_MEM_STREAM3_BUF3 = 0x4f, SQ_CF_INST_MEM_SCRATCH = 0x50, SQ_CF_INST_MEM_RING = 0x52, SQ_CF_INST_EXPORT = 0x53, SQ_CF_INST_EXPORT_DONE = 0x54, SQ_CF_INST_MEM_EXPORT = 0x55, SQ_CF_INST_MEM_RAT = 0x56, SQ_CF_INST_MEM_RAT_CACHELESS = 0x57, SQ_CF_INST_MEM_RING1 = 0x58, SQ_CF_INST_MEM_RING2 = 0x59, SQ_CF_INST_MEM_RING3 = 0x5a, SQ_CF_INST_MEM_EXPORT_COMBINED = 0x5b, SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS = 0x5c, SQ_CF_INST_MEM_RAT_COMBINED = 0x5d, SQ_CF_INST_EXPORT_DONE_END_IS_NEXT = 0x5e, MARK_bit = 1 << 30, BARRIER_bit = 1 << 31, SQ_CF_ALU_WORD1 = 0x00008dfc, KCACHE_MODE1_mask = 0x03 << 0, KCACHE_MODE1_shift = 0, SQ_CF_KCACHE_NOP = 0x00, SQ_CF_KCACHE_LOCK_1 = 0x01, SQ_CF_KCACHE_LOCK_2 = 0x02, SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, KCACHE_ADDR0_mask = 0xff << 2, KCACHE_ADDR0_shift = 2, KCACHE_ADDR1_mask = 0xff << 10, KCACHE_ADDR1_shift = 10, SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, SQ_CF_ALU_WORD1__COUNT_shift = 18, SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, SQ_CF_ALU_WORD1__CF_INST_shift = 26, SQ_CF_INST_ALU = 0x08, SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, SQ_CF_INST_ALU_POP_AFTER = 0x0a, SQ_CF_INST_ALU_POP2_AFTER = 0x0b, SQ_CF_INST_ALU_EXTENDED = 0x0c, SQ_CF_INST_ALU_CONTINUE = 0x0d, SQ_CF_INST_ALU_BREAK = 0x0e, SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, WHOLE_QUAD_MODE_bit = 1 << 30, /* BARRIER_bit = 1 << 31, */ SQ_TEX_WORD1 = 0x00008dfc, SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, SQ_TEX_WORD1__DST_GPR_shift = 0, SQ_TEX_WORD1__DST_REL_bit = 1 << 7, SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_TEX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_SEL_MASK = 0x07, SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_TEX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_TEX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_TEX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, SQ_TEX_WORD1__LOD_BIAS_shift = 21, COORD_TYPE_X_bit = 1 << 28, COORD_TYPE_Y_bit = 1 << 29, COORD_TYPE_Z_bit = 1 << 30, COORD_TYPE_W_bit = 1 << 31, SQ_ALU_WORD1_OP2_MOVA = 0x00008dfc, MOVA_DST_mask = 0x7f << 21, MOVA_DST_shift = 21, SQ_ALU_MOVA_DST_AR_X = 0x00, SQ_ALU_MOVA_DST_CF_PC = 0x01, SQ_ALU_MOVA_DST_CF_IDX0 = 0x02, SQ_ALU_MOVA_DST_CF_IDX1 = 0x03, SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B0 = 0x04, SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B1 = 0x05, SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B2 = 0x06, SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B3 = 0x07, SQ_VTX_WORD0 = 0x00008dfc, VTX_INST_mask = 0x1f << 0, VTX_INST_shift = 0, SQ_VTX_INST_FETCH = 0x00, SQ_VTX_INST_SEMANTIC = 0x01, SQ_VTX_INST_GET_BUFFER_RESINFO = 0x0e, FETCH_TYPE_mask = 0x03 << 5, FETCH_TYPE_shift = 5, SQ_VTX_FETCH_VERTEX_DATA = 0x00, SQ_VTX_FETCH_INSTANCE_DATA = 0x01, SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, FETCH_WHOLE_QUAD_bit = 1 << 7, BUFFER_ID_mask = 0xff << 8, BUFFER_ID_shift = 8, SQ_VTX_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_VTX_WORD0__SRC_GPR_shift = 16, SRC_REL_bit = 1 << 23, SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, SQ_VTX_WORD0__SRC_SEL_X_shift = 24, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ SQ_VTX_WORD0__SRC_SEL_Y_mask = 0x03 << 26, SQ_VTX_WORD0__SRC_SEL_Y_shift = 26, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ STRUCTURED_READ_mask = 0x03 << 28, STRUCTURED_READ_shift = 28, SQ_VTX_STRU_READ_OFF = 0x00, SQ_VTX_STRU_READ_GPR_OFFSET = 0x01, SQ_VTX_STRU_READ_INST_OFFSET = 0x02, LDS_REQ_bit = 1 << 30, COALESCED_READ_bit = 1 << 31, SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, SEL_X_mask = 0x07 << 0, SEL_X_shift = 0, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Y_mask = 0x07 << 3, SEL_Y_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Z_mask = 0x07 << 6, SEL_Z_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_W_mask = 0x07 << 9, SEL_W_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD0 = 0x00008dfc, MEM_INST_mask = 0x1f << 0, MEM_INST_shift = 0, SQ_MEM_INST_MEM = 0x02, SQ_MEM_RD_WORD0__ELEM_SIZE_mask = 0x03 << 5, SQ_MEM_RD_WORD0__ELEM_SIZE_shift = 5, /* FETCH_WHOLE_QUAD_bit = 1 << 7, */ MEM_OP_mask = 0x07 << 8, MEM_OP_shift = 8, SQ_MEM_OP_RD_SCRATCH = 0x00, SQ_MEM_OP_RD_SCATTER = 0x02, SQ_MEM_OP_GDS = 0x04, SQ_MEM_OP_TF_WRITE = 0x05, SQ_MEM_RD_WORD0__UNCACHED_bit = 1 << 11, INDEXED_bit = 1 << 12, SQ_MEM_RD_WORD0__SRC_SEL_Y_mask = 0x03 << 13, SQ_MEM_RD_WORD0__SRC_SEL_Y_shift = 13, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ SQ_MEM_RD_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_MEM_RD_WORD0__SRC_GPR_shift = 16, /* SRC_REL_bit = 1 << 23, */ SQ_MEM_RD_WORD0__SRC_SEL_X_mask = 0x03 << 24, SQ_MEM_RD_WORD0__SRC_SEL_X_shift = 24, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ BURST_CNT_mask = 0x0f << 26, BURST_CNT_shift = 26, /* LDS_REQ_bit = 1 << 30, */ /* COALESCED_READ_bit = 1 << 31, */ SQ_ALU_WORD1 = 0x00008dfc, SQ_ALU_WORD1__ENCODING_mask = 0x07 << 15, SQ_ALU_WORD1__ENCODING_shift = 15, BANK_SWIZZLE_mask = 0x07 << 18, BANK_SWIZZLE_shift = 18, SQ_ALU_VEC_012 = 0x00, SQ_ALU_VEC_021 = 0x01, SQ_ALU_VEC_120 = 0x02, SQ_ALU_VEC_102 = 0x03, SQ_ALU_VEC_201 = 0x04, SQ_ALU_VEC_210 = 0x05, SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, SQ_ALU_WORD1__DST_GPR_shift = 21, SQ_ALU_WORD1__DST_REL_bit = 1 << 28, DST_CHAN_mask = 0x03 << 29, DST_CHAN_shift = 29, CHAN_X = 0x00, CHAN_Y = 0x01, CHAN_Z = 0x02, CHAN_W = 0x03, SQ_ALU_WORD1__CLAMP_bit = 1 << 31, SQ_CF_ALU_WORD0_EXT = 0x00008dfc, KCACHE_BANK_INDEX_MODE0_mask = 0x03 << 4, KCACHE_BANK_INDEX_MODE0_shift = 4, SQ_CF_INDEX_NONE = 0x00, SQ_CF_INDEX_0 = 0x01, SQ_CF_INDEX_1 = 0x02, SQ_CF_INVALID = 0x03, KCACHE_BANK_INDEX_MODE1_mask = 0x03 << 6, KCACHE_BANK_INDEX_MODE1_shift = 6, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK_INDEX_MODE2_mask = 0x03 << 8, KCACHE_BANK_INDEX_MODE2_shift = 8, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK_INDEX_MODE3_mask = 0x03 << 10, KCACHE_BANK_INDEX_MODE3_shift = 10, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK2_mask = 0x0f << 22, KCACHE_BANK2_shift = 22, KCACHE_BANK3_mask = 0x0f << 26, KCACHE_BANK3_shift = 26, KCACHE_MODE2_mask = 0x03 << 30, KCACHE_MODE2_shift = 30, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ SQ_ALU_WORD0_LDS_IDX_OP = 0x00008dfc, SRC0_SEL_mask = 0x1ff << 0, SRC0_SEL_shift = 0, /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC0_REL_bit = 1 << 9, SRC0_CHAN_mask = 0x03 << 10, SRC0_CHAN_shift = 10, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_4_bit = 1 << 12, SRC1_SEL_mask = 0x1ff << 13, SRC1_SEL_shift = 13, /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC1_REL_bit = 1 << 22, SRC1_CHAN_mask = 0x03 << 23, SRC1_CHAN_shift = 23, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_5_bit = 1 << 25, INDEX_MODE_mask = 0x07 << 26, INDEX_MODE_shift = 26, SQ_INDEX_AR_X = 0x00, SQ_INDEX_LOOP = 0x04, SQ_INDEX_GLOBAL = 0x05, SQ_INDEX_GLOBAL_AR_X = 0x06, PRED_SEL_mask = 0x03 << 29, PRED_SEL_shift = 29, SQ_PRED_SEL_OFF = 0x00, SQ_PRED_SEL_ZERO = 0x02, SQ_PRED_SEL_ONE = 0x03, LAST_bit = 1 << 31, SQ_MEM_GDS_WORD2 = 0x00008dfc, SQ_MEM_GDS_WORD2__DST_SEL_X_mask = 0x07 << 0, SQ_MEM_GDS_WORD2__DST_SEL_X_shift = 0, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_Y_mask = 0x07 << 3, SQ_MEM_GDS_WORD2__DST_SEL_Y_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_Z_mask = 0x07 << 6, SQ_MEM_GDS_WORD2__DST_SEL_Z_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_W_mask = 0x07 << 9, SQ_MEM_GDS_WORD2__DST_SEL_W_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_CF_ALLOC_EXPORT_WORD0_RAT = 0x00008dfc, RAT_ID_mask = 0x0f << 0, RAT_ID_shift = 0, RAT_INST_mask = 0x3f << 4, RAT_INST_shift = 4, SQ_EXPORT_RAT_INST_NOP = 0x00, SQ_EXPORT_RAT_INST_STORE_TYPED = 0x01, SQ_EXPORT_RAT_INST_STORE_RAW = 0x02, SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x03, SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x04, SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x05, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x06, SQ_EXPORT_RAT_INST_ADD = 0x07, SQ_EXPORT_RAT_INST_SUB = 0x08, SQ_EXPORT_RAT_INST_RSUB = 0x09, SQ_EXPORT_RAT_INST_MIN_INT = 0x0a, SQ_EXPORT_RAT_INST_MIN_UINT = 0x0b, SQ_EXPORT_RAT_INST_MAX_INT = 0x0c, SQ_EXPORT_RAT_INST_MAX_UINT = 0x0d, SQ_EXPORT_RAT_INST_AND = 0x0e, SQ_EXPORT_RAT_INST_OR = 0x0f, SQ_EXPORT_RAT_INST_XOR = 0x10, SQ_EXPORT_RAT_INST_MSKOR = 0x11, SQ_EXPORT_RAT_INST_INC_UINT = 0x12, SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, RAT_INDEX_MODE_mask = 0x03 << 11, RAT_INDEX_MODE_shift = 11, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_mask = 0x03 << 13, SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_shift = 13, SQ_EXPORT_PIXEL = 0x00, SQ_EXPORT_POS = 0x01, SQ_EXPORT_PARAM = 0x02, X_UNUSED_FOR_SX_EXPORTS = 0x03, RW_GPR_mask = 0x7f << 15, RW_GPR_shift = 15, RW_REL_bit = 1 << 22, INDEX_GPR_mask = 0x7f << 23, INDEX_GPR_shift = 23, SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_mask = 0x03 << 30, SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_shift = 30, SQ_CF_ALU_WORD0 = 0x00008dfc, SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, SQ_CF_ALU_WORD0__ADDR_shift = 0, KCACHE_BANK0_mask = 0x0f << 22, KCACHE_BANK0_shift = 22, KCACHE_BANK1_mask = 0x0f << 26, KCACHE_BANK1_shift = 26, KCACHE_MODE0_mask = 0x03 << 30, KCACHE_MODE0_shift = 30, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ SQ_MEM_GDS_WORD1 = 0x00008dfc, SQ_MEM_GDS_WORD1__DST_GPR_mask = 0x7f << 0, SQ_MEM_GDS_WORD1__DST_GPR_shift = 0, DST_REL_MODE_mask = 0x03 << 7, DST_REL_MODE_shift = 7, SQ_REL_NONE = 0x00, SQ_REL_LOOP = 0x01, SQ_REL_GLOBAL = 0x02, GDS_OP_mask = 0x3f << 9, GDS_OP_shift = 9, SQ_DS_INST_ADD = 0x00, SQ_DS_INST_SUB = 0x01, SQ_DS_INST_RSUB = 0x02, SQ_DS_INST_INC = 0x03, SQ_DS_INST_DEC = 0x04, SQ_DS_INST_MIN_INT = 0x05, SQ_DS_INST_MAX_INT = 0x06, SQ_DS_INST_MIN_UINT = 0x07, SQ_DS_INST_MAX_UINT = 0x08, SQ_DS_INST_AND = 0x09, SQ_DS_INST_OR = 0x0a, SQ_DS_INST_XOR = 0x0b, SQ_DS_INST_MSKOR = 0x0c, SQ_DS_INST_WRITE = 0x0d, SQ_DS_INST_WRITE_REL = 0x0e, SQ_DS_INST_WRITE2 = 0x0f, SQ_DS_INST_CMP_STORE = 0x10, SQ_DS_INST_CMP_STORE_SPF = 0x11, SQ_DS_INST_BYTE_WRITE = 0x12, SQ_DS_INST_SHORT_WRITE = 0x13, SQ_DS_INST_ADD_RET = 0x20, SQ_DS_INST_SUB_RET = 0x21, SQ_DS_INST_RSUB_RET = 0x22, SQ_DS_INST_INC_RET = 0x23, SQ_DS_INST_DEC_RET = 0x24, SQ_DS_INST_MIN_INT_RET = 0x25, SQ_DS_INST_MAX_INT_RET = 0x26, SQ_DS_INST_MIN_UINT_RET = 0x27, SQ_DS_INST_MAX_UINT_RET = 0x28, SQ_DS_INST_AND_RET = 0x29, SQ_DS_INST_OR_RET = 0x2a, SQ_DS_INST_XOR_RET = 0x2b, SQ_DS_INST_MSKOR_RET = 0x2c, SQ_DS_INST_XCHG_RET = 0x2d, SQ_DS_INST_XCHG_REL_RET = 0x2e, SQ_DS_INST_XCHG2_RET = 0x2f, SQ_DS_INST_CMP_XCHG_RET = 0x30, SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, SQ_DS_INST_READ_RET = 0x32, SQ_DS_INST_READ_REL_RET = 0x33, SQ_DS_INST_READ2_RET = 0x34, SQ_DS_INST_READWRITE_RET = 0x35, SQ_DS_INST_BYTE_READ_RET = 0x36, SQ_DS_INST_UBYTE_READ_RET = 0x37, SQ_DS_INST_SHORT_READ_RET = 0x38, SQ_DS_INST_USHORT_READ_RET = 0x39, SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, DS_OFFSET_mask = 0x7f << 16, DS_OFFSET_shift = 16, UAV_INDEX_MODE_mask = 0x03 << 24, UAV_INDEX_MODE_shift = 24, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ UAV_ID_mask = 0x0f << 26, UAV_ID_shift = 26, ALLOC_CONSUME_bit = 1 << 30, BCAST_FIRST_REQ_bit = 1 << 31, SQ_MEM_RD_WORD2 = 0x00008dfc, ARRAY_BASE_mask = 0x1fff << 0, ARRAY_BASE_shift = 0, SQ_MEM_RD_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, SQ_MEM_RD_WORD2__ENDIAN_SWAP_shift = 16, SQ_ENDIAN_NONE = 0x00, SQ_ENDIAN_8IN16 = 0x01, SQ_ENDIAN_8IN32 = 0x02, SQ_MEM_RD_WORD2__ARRAY_SIZE_mask = 0xfff << 20, SQ_MEM_RD_WORD2__ARRAY_SIZE_shift = 20, SQ_CF_ALU_WORD1_EXT = 0x00008dfc, KCACHE_MODE3_mask = 0x03 << 0, KCACHE_MODE3_shift = 0, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ KCACHE_ADDR2_mask = 0xff << 2, KCACHE_ADDR2_shift = 2, KCACHE_ADDR3_mask = 0xff << 10, KCACHE_ADDR3_shift = 10, SQ_CF_ALU_WORD1_EXT__CF_INST_mask = 0x0f << 26, SQ_CF_ALU_WORD1_EXT__CF_INST_shift = 26, /* SQ_CF_INST_ALU = 0x08, */ /* SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, */ /* SQ_CF_INST_ALU_POP_AFTER = 0x0a, */ /* SQ_CF_INST_ALU_POP2_AFTER = 0x0b, */ /* SQ_CF_INST_ALU_EXTENDED = 0x0c, */ /* SQ_CF_INST_ALU_CONTINUE = 0x0d, */ /* SQ_CF_INST_ALU_BREAK = 0x0e, */ /* SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, */ /* BARRIER_bit = 1 << 31, */ SQ_CF_GWS_WORD0 = 0x00008dfc, VALUE_mask = 0x3ff << 0, VALUE_shift = 0, RESOURCE_mask = 0x1f << 16, RESOURCE_shift = 16, SIGN_bit = 1 << 25, VAL_INDEX_MODE_mask = 0x03 << 26, VAL_INDEX_MODE_shift = 26, SQ_GWS_INDEX_NONE = 0x00, SQ_GWS_INDEX_0 = 0x01, SQ_GWS_INDEX_1 = 0x02, SQ_GWS_INDEX_MIX = 0x03, RSRC_INDEX_MODE_mask = 0x03 << 28, RSRC_INDEX_MODE_shift = 28, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ GWS_OPCODE_mask = 0x03 << 30, GWS_OPCODE_shift = 30, SQ_GWS_SEMA_V = 0x00, SQ_GWS_SEMA_P = 0x01, SQ_GWS_BARRIER = 0x02, SQ_GWS_INIT = 0x03, SQ_VTX_WORD2 = 0x00008dfc, SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, SQ_VTX_WORD2__OFFSET_shift = 0, SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ CONST_BUF_NO_STRIDE_bit = 1 << 18, SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, BUFFER_INDEX_MODE_mask = 0x03 << 21, BUFFER_INDEX_MODE_shift = 21, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_ALU_WORD1_OP2_EXECUTE_MASK = 0x00008dfc, EXECUTE_MASK_OP_mask = 0x03 << 5, EXECUTE_MASK_OP_shift = 5, SQ_ALU_EXECUTE_MASK_OP_DEACTIVATE = 0x00, SQ_ALU_EXECUTE_MASK_OP_BREAK = 0x01, SQ_ALU_EXECUTE_MASK_OP_CONTINUE = 0x02, SQ_ALU_EXECUTE_MASK_OP_KILL = 0x03, SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xfff << 0, SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, COMP_MASK_mask = 0x0f << 12, COMP_MASK_shift = 12, SQ_CF_WORD0 = 0x00008dfc, SQ_CF_WORD0__ADDR_mask = 0xffffff << 0, SQ_CF_WORD0__ADDR_shift = 0, JUMPTABLE_SEL_mask = 0x07 << 24, JUMPTABLE_SEL_shift = 24, SQ_CF_JUMPTABLE_SEL_CONST_A = 0x00, SQ_CF_JUMPTABLE_SEL_CONST_B = 0x01, SQ_CF_JUMPTABLE_SEL_CONST_C = 0x02, SQ_CF_JUMPTABLE_SEL_CONST_D = 0x03, SQ_CF_JUMPTABLE_SEL_INDEX_0 = 0x04, SQ_CF_JUMPTABLE_SEL_INDEX_1 = 0x05, SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, /* ARRAY_BASE_mask = 0x1fff << 0, */ /* ARRAY_BASE_shift = 0, */ SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, /* SQ_EXPORT_PIXEL = 0x00, */ /* SQ_EXPORT_POS = 0x01, */ /* SQ_EXPORT_PARAM = 0x02, */ /* X_UNUSED_FOR_SX_EXPORTS = 0x03, */ /* RW_GPR_mask = 0x7f << 15, */ /* RW_GPR_shift = 15, */ /* RW_REL_bit = 1 << 22, */ /* INDEX_GPR_mask = 0x7f << 23, */ /* INDEX_GPR_shift = 23, */ SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x03 << 30, SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30, SQ_MEM_GDS_WORD0 = 0x00008dfc, /* MEM_INST_mask = 0x1f << 0, */ /* MEM_INST_shift = 0, */ /* SQ_MEM_INST_MEM = 0x02, */ /* MEM_OP_mask = 0x07 << 8, */ /* MEM_OP_shift = 8, */ /* SQ_MEM_OP_RD_SCRATCH = 0x00, */ /* SQ_MEM_OP_RD_SCATTER = 0x02, */ /* SQ_MEM_OP_GDS = 0x04, */ /* SQ_MEM_OP_TF_WRITE = 0x05, */ SQ_MEM_GDS_WORD0__SRC_GPR_mask = 0x7f << 11, SQ_MEM_GDS_WORD0__SRC_GPR_shift = 11, SRC_REL_MODE_mask = 0x03 << 18, SRC_REL_MODE_shift = 18, /* SQ_REL_NONE = 0x00, */ /* SQ_REL_LOOP = 0x01, */ /* SQ_REL_GLOBAL = 0x02, */ SQ_MEM_GDS_WORD0__SRC_SEL_X_mask = 0x07 << 20, SQ_MEM_GDS_WORD0__SRC_SEL_X_shift = 20, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_MEM_GDS_WORD0__SRC_SEL_Y_mask = 0x07 << 23, SQ_MEM_GDS_WORD0__SRC_SEL_Y_shift = 23, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SRC_SEL_Z_mask = 0x07 << 26, */ /* SRC_SEL_Z_shift = 26, */ /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_ALU_WORD1_LDS_DIRECT_LITERAL_HI = 0x00008dfc, OFFSET_B_mask = 0x1fff << 0, OFFSET_B_shift = 0, STRIDE_B_mask = 0x7f << 13, STRIDE_B_shift = 13, THREAD_REL_B_bit = 1 << 22, DIRECT_READ_32_bit = 1 << 31, SQ_VTX_WORD1 = 0x00008dfc, SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_VTX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_VTX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_VTX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_VTX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ USE_CONST_FIELDS_bit = 1 << 21, SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, SQ_VTX_WORD1__DATA_FORMAT_shift = 22, SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, SQ_NUM_FORMAT_NORM = 0x00, SQ_NUM_FORMAT_INT = 0x01, SQ_NUM_FORMAT_SCALED = 0x02, SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, SQ_ALU_WORD1_OP2 = 0x00008dfc, SRC0_ABS_bit = 1 << 0, SRC1_ABS_bit = 1 << 1, UPDATE_EXECUTE_MASK_bit = 1 << 2, UPDATE_PRED_bit = 1 << 3, WRITE_MASK_bit = 1 << 4, OMOD_mask = 0x03 << 5, OMOD_shift = 5, SQ_ALU_OMOD_OFF = 0x00, SQ_ALU_OMOD_M2 = 0x01, SQ_ALU_OMOD_M4 = 0x02, SQ_ALU_OMOD_D2 = 0x03, SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x7ff << 7, SQ_ALU_WORD1_OP2__ALU_INST_shift = 7, SQ_OP2_INST_ADD = 0x00, SQ_OP2_INST_MUL = 0x01, SQ_OP2_INST_MUL_IEEE = 0x02, SQ_OP2_INST_MAX = 0x03, SQ_OP2_INST_MIN = 0x04, SQ_OP2_INST_MAX_DX10 = 0x05, SQ_OP2_INST_MIN_DX10 = 0x06, SQ_OP2_INST_SETE = 0x08, SQ_OP2_INST_SETGT = 0x09, SQ_OP2_INST_SETGE = 0x0a, SQ_OP2_INST_SETNE = 0x0b, SQ_OP2_INST_SETE_DX10 = 0x0c, SQ_OP2_INST_SETGT_DX10 = 0x0d, SQ_OP2_INST_SETGE_DX10 = 0x0e, SQ_OP2_INST_SETNE_DX10 = 0x0f, SQ_OP2_INST_FRACT = 0x10, SQ_OP2_INST_TRUNC = 0x11, SQ_OP2_INST_CEIL = 0x12, SQ_OP2_INST_RNDNE = 0x13, SQ_OP2_INST_FLOOR = 0x14, SQ_OP2_INST_ASHR_INT = 0x15, SQ_OP2_INST_LSHR_INT = 0x16, SQ_OP2_INST_LSHL_INT = 0x17, SQ_OP2_INST_MOV = 0x19, SQ_OP2_INST_NOP = 0x1a, SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, SQ_OP2_INST_PRED_SETE = 0x20, SQ_OP2_INST_PRED_SETGT = 0x21, SQ_OP2_INST_PRED_SETGE = 0x22, SQ_OP2_INST_PRED_SETNE = 0x23, SQ_OP2_INST_PRED_SET_INV = 0x24, SQ_OP2_INST_PRED_SET_POP = 0x25, SQ_OP2_INST_PRED_SET_CLR = 0x26, SQ_OP2_INST_PRED_SET_RESTORE = 0x27, SQ_OP2_INST_PRED_SETE_PUSH = 0x28, SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, SQ_OP2_INST_KILLE = 0x2c, SQ_OP2_INST_KILLGT = 0x2d, SQ_OP2_INST_KILLGE = 0x2e, SQ_OP2_INST_KILLNE = 0x2f, SQ_OP2_INST_AND_INT = 0x30, SQ_OP2_INST_OR_INT = 0x31, SQ_OP2_INST_XOR_INT = 0x32, SQ_OP2_INST_NOT_INT = 0x33, SQ_OP2_INST_ADD_INT = 0x34, SQ_OP2_INST_SUB_INT = 0x35, SQ_OP2_INST_MAX_INT = 0x36, SQ_OP2_INST_MIN_INT = 0x37, SQ_OP2_INST_MAX_UINT = 0x38, SQ_OP2_INST_MIN_UINT = 0x39, SQ_OP2_INST_SETE_INT = 0x3a, SQ_OP2_INST_SETGT_INT = 0x3b, SQ_OP2_INST_SETGE_INT = 0x3c, SQ_OP2_INST_SETNE_INT = 0x3d, SQ_OP2_INST_SETGT_UINT = 0x3e, SQ_OP2_INST_SETGE_UINT = 0x3f, SQ_OP2_INST_KILLGT_UINT = 0x40, SQ_OP2_INST_KILLGE_UINT = 0x41, SQ_OP2_INST_PRED_SETE_INT = 0x42, SQ_OP2_INST_PRED_SETGT_INT = 0x43, SQ_OP2_INST_PRED_SETGE_INT = 0x44, SQ_OP2_INST_PRED_SETNE_INT = 0x45, SQ_OP2_INST_KILLE_INT = 0x46, SQ_OP2_INST_KILLGT_INT = 0x47, SQ_OP2_INST_KILLGE_INT = 0x48, SQ_OP2_INST_KILLNE_INT = 0x49, SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, SQ_OP2_INST_FLT_TO_INT = 0x50, SQ_OP2_INST_BFREV_INT = 0x51, SQ_OP2_INST_ADDC_UINT = 0x52, SQ_OP2_INST_SUBB_UINT = 0x53, SQ_OP2_INST_GROUP_BARRIER = 0x54, SQ_OP2_INST_GROUP_SEQ_BEGIN = 0x55, SQ_OP2_INST_GROUP_SEQ_END = 0x56, SQ_OP2_INST_SET_MODE = 0x57, SQ_OP2_INST_SET_CF_IDX0 = 0x58, SQ_OP2_INST_SET_CF_IDX1 = 0x59, SQ_OP2_INST_SET_LDS_SIZE = 0x5a, SQ_OP2_INST_EXP_IEEE = 0x81, SQ_OP2_INST_LOG_CLAMPED = 0x82, SQ_OP2_INST_LOG_IEEE = 0x83, SQ_OP2_INST_RECIP_CLAMPED = 0x84, SQ_OP2_INST_RECIP_FF = 0x85, SQ_OP2_INST_RECIP_IEEE = 0x86, SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x87, SQ_OP2_INST_RECIPSQRT_FF = 0x88, SQ_OP2_INST_RECIPSQRT_IEEE = 0x89, SQ_OP2_INST_SQRT_IEEE = 0x8a, SQ_OP2_INST_SIN = 0x8d, SQ_OP2_INST_COS = 0x8e, SQ_OP2_INST_MULLO_INT = 0x8f, SQ_OP2_INST_MULHI_INT = 0x90, SQ_OP2_INST_MULLO_UINT = 0x91, SQ_OP2_INST_MULHI_UINT = 0x92, SQ_OP2_INST_RECIP_INT = 0x93, SQ_OP2_INST_RECIP_UINT = 0x94, SQ_OP2_INST_RECIP_64 = 0x95, SQ_OP2_INST_RECIP_CLAMPED_64 = 0x96, SQ_OP2_INST_RECIPSQRT_64 = 0x97, SQ_OP2_INST_RECIPSQRT_CLAMPED_64 = 0x98, SQ_OP2_INST_SQRT_64 = 0x99, SQ_OP2_INST_FLT_TO_UINT = 0x9a, SQ_OP2_INST_INT_TO_FLT = 0x9b, SQ_OP2_INST_UINT_TO_FLT = 0x9c, SQ_OP2_INST_BFM_INT = 0xa0, SQ_OP2_INST_FLT32_TO_FLT16 = 0xa2, SQ_OP2_INST_FLT16_TO_FLT32 = 0xa3, SQ_OP2_INST_UBYTE0_FLT = 0xa4, SQ_OP2_INST_UBYTE1_FLT = 0xa5, SQ_OP2_INST_UBYTE2_FLT = 0xa6, SQ_OP2_INST_UBYTE3_FLT = 0xa7, SQ_OP2_INST_BCNT_INT = 0xaa, SQ_OP2_INST_FFBH_UINT = 0xab, SQ_OP2_INST_FFBL_INT = 0xac, SQ_OP2_INST_FFBH_INT = 0xad, SQ_OP2_INST_FLT_TO_UINT4 = 0xae, SQ_OP2_INST_DOT_IEEE = 0xaf, SQ_OP2_INST_FLT_TO_INT_RPI = 0xb0, SQ_OP2_INST_FLT_TO_INT_FLOOR = 0xb1, SQ_OP2_INST_MULHI_UINT24 = 0xb2, SQ_OP2_INST_MBCNT_32HI_INT = 0xb3, SQ_OP2_INST_OFFSET_TO_FLT = 0xb4, SQ_OP2_INST_MUL_UINT24 = 0xb5, SQ_OP2_INST_BCNT_ACCUM_PREV_INT = 0xb6, SQ_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 0xb7, SQ_OP2_INST_SETE_64 = 0xb8, SQ_OP2_INST_SETNE_64 = 0xb9, SQ_OP2_INST_SETGT_64 = 0xba, SQ_OP2_INST_SETGE_64 = 0xbb, SQ_OP2_INST_MIN_64 = 0xbc, SQ_OP2_INST_MAX_64 = 0xbd, SQ_OP2_INST_DOT4 = 0xbe, SQ_OP2_INST_DOT4_IEEE = 0xbf, SQ_OP2_INST_CUBE = 0xc0, SQ_OP2_INST_MAX4 = 0xc1, SQ_OP2_INST_FREXP_64 = 0xc4, SQ_OP2_INST_LDEXP_64 = 0xc5, SQ_OP2_INST_FRACT_64 = 0xc6, SQ_OP2_INST_PRED_SETGT_64 = 0xc7, SQ_OP2_INST_PRED_SETE_64 = 0xc8, SQ_OP2_INST_PRED_SETGE_64 = 0xc9, SQ_OP2_INST_MUL_64 = 0xca, SQ_OP2_INST_ADD_64 = 0xcb, SQ_OP2_INST_MOVA_INT = 0xcc, SQ_OP2_INST_FLT64_TO_FLT32 = 0xcd, SQ_OP2_INST_FLT32_TO_FLT64 = 0xce, SQ_OP2_INST_SAD_ACCUM_PREV_UINT = 0xcf, SQ_OP2_INST_DOT = 0xd0, SQ_OP2_INST_MUL_PREV = 0xd1, SQ_OP2_INST_MUL_IEEE_PREV = 0xd2, SQ_OP2_INST_ADD_PREV = 0xd3, SQ_OP2_INST_MULADD_PREV = 0xd4, SQ_OP2_INST_MULADD_IEEE_PREV = 0xd5, SQ_OP2_INST_INTERP_XY = 0xd6, SQ_OP2_INST_INTERP_ZW = 0xd7, SQ_OP2_INST_INTERP_X = 0xd8, SQ_OP2_INST_INTERP_Z = 0xd9, SQ_OP2_INST_STORE_FLAGS = 0xda, SQ_OP2_INST_LOAD_STORE_FLAGS = 0xdb, SQ_OP2_INST_INTERP_LOAD_P0 = 0xe0, SQ_OP2_INST_INTERP_LOAD_P10 = 0xe1, SQ_OP2_INST_INTERP_LOAD_P20 = 0xe2, SQ_CF_WORD1 = 0x00008dfc, POP_COUNT_mask = 0x07 << 0, POP_COUNT_shift = 0, CF_CONST_mask = 0x1f << 3, CF_CONST_shift = 3, COND_mask = 0x03 << 8, COND_shift = 8, SQ_CF_COND_ACTIVE = 0x00, SQ_CF_COND_FALSE = 0x01, SQ_CF_COND_BOOL = 0x02, SQ_CF_COND_NOT_BOOL = 0x03, SQ_CF_WORD1__COUNT_mask = 0x3f << 10, SQ_CF_WORD1__COUNT_shift = 10, /* VALID_PIXEL_MODE_bit = 1 << 20, */ SQ_CF_WORD1__CF_INST_mask = 0xff << 22, SQ_CF_WORD1__CF_INST_shift = 22, SQ_CF_INST_NOP = 0x00, SQ_CF_INST_TC = 0x01, SQ_CF_INST_VC = 0x02, SQ_CF_INST_GDS = 0x03, SQ_CF_INST_LOOP_START = 0x04, SQ_CF_INST_LOOP_END = 0x05, SQ_CF_INST_LOOP_START_DX10 = 0x06, SQ_CF_INST_LOOP_START_NO_AL = 0x07, SQ_CF_INST_LOOP_CONTINUE = 0x08, SQ_CF_INST_LOOP_BREAK = 0x09, SQ_CF_INST_JUMP = 0x0a, SQ_CF_INST_PUSH = 0x0b, SQ_CF_INST_ELSE = 0x0d, SQ_CF_INST_POP = 0x0e, SQ_CF_INST_CALL = 0x12, SQ_CF_INST_CALL_FS = 0x13, SQ_CF_INST_RETURN = 0x14, SQ_CF_INST_EMIT_VERTEX = 0x15, SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, SQ_CF_INST_CUT_VERTEX = 0x17, SQ_CF_INST_KILL = 0x18, SQ_CF_INST_WAIT_ACK = 0x1a, SQ_CF_INST_TC_ACK = 0x1b, SQ_CF_INST_VC_ACK = 0x1c, SQ_CF_INST_JUMPTABLE = 0x1d, SQ_CF_INST_GLOBAL_WAVE_SYNC = 0x1e, SQ_CF_INST_HALT = 0x1f, SQ_CF_INST_END = 0x20, SQ_CF_INST_LDS_DEALLOC = 0x21, SQ_CF_INST_PUSH_WQM = 0x22, SQ_CF_INST_POP_WQM = 0x23, SQ_CF_INST_ELSE_WQM = 0x24, SQ_CF_INST_JUMP_ANY = 0x25, SQ_CF_INST_REACTIVATE = 0x26, SQ_CF_INST_REACTIVATE_WQM = 0x27, SQ_CF_INST_INTERRUPT = 0x28, SQ_CF_INST_INTERRUPT_AND_SLEEP = 0x29, SQ_CF_INST_SET_PRIORITY = 0x2a, /* BARRIER_bit = 1 << 31, */ SQ_VTX_WORD1_SEM = 0x00008dfc, SEMANTIC_ID_mask = 0xff << 0, SEMANTIC_ID_shift = 0, SQ_TEX_WORD0 = 0x00008dfc, TEX_INST_mask = 0x1f << 0, TEX_INST_shift = 0, SQ_TEX_INST_LD = 0x03, SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, SQ_TEX_INST_GET_LOD = 0x06, SQ_TEX_INST_GET_GRADIENTS_H = 0x07, SQ_TEX_INST_GET_GRADIENTS_V = 0x08, SQ_TEX_INST_SET_TEXTURE_OFFSETS = 0x09, SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, SQ_TEX_INST_PASS = 0x0d, SQ_TEX_INST_SAMPLE = 0x10, SQ_TEX_INST_SAMPLE_L = 0x11, SQ_TEX_INST_SAMPLE_LB = 0x12, SQ_TEX_INST_SAMPLE_LZ = 0x13, SQ_TEX_INST_SAMPLE_G = 0x14, SQ_TEX_INST_GATHER4 = 0x15, SQ_TEX_INST_SAMPLE_G_LB = 0x16, SQ_TEX_INST_GATHER4_O = 0x17, SQ_TEX_INST_SAMPLE_C = 0x18, SQ_TEX_INST_SAMPLE_C_L = 0x19, SQ_TEX_INST_SAMPLE_C_LB = 0x1a, SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, SQ_TEX_INST_SAMPLE_C_G = 0x1c, SQ_TEX_INST_GATHER4_C = 0x1d, SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, SQ_TEX_INST_GATHER4_C_O = 0x1f, INST_MOD_mask = 0x03 << 5, INST_MOD_shift = 5, /* FETCH_WHOLE_QUAD_bit = 1 << 7, */ RESOURCE_ID_mask = 0xff << 8, RESOURCE_ID_shift = 8, SQ_TEX_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_TEX_WORD0__SRC_GPR_shift = 16, /* SRC_REL_bit = 1 << 23, */ SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, RESOURCE_INDEX_MODE_mask = 0x03 << 25, RESOURCE_INDEX_MODE_shift = 25, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SAMPLER_INDEX_MODE_mask = 0x03 << 27, SAMPLER_INDEX_MODE_shift = 27, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_VTX_WORD1_GPR = 0x00008dfc, SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, SQ_ALU_WORD1_LDS_IDX_OP = 0x00008dfc, /* SRC2_SEL_mask = 0x1ff << 0, */ /* SRC2_SEL_shift = 0, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC2_REL_bit = 1 << 9, */ /* SRC2_CHAN_mask = 0x03 << 10, */ /* SRC2_CHAN_shift = 10, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_1_bit = 1 << 12, SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_mask = 0x1f << 13, SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_shift = 13, /* SQ_OP3_INST_BFE_UINT = 0x04, */ /* SQ_OP3_INST_BFE_INT = 0x05, */ /* SQ_OP3_INST_BFI_INT = 0x06, */ /* SQ_OP3_INST_FMA = 0x07, */ /* SQ_OP3_INST_CNDNE_64 = 0x09, */ /* SQ_OP3_INST_FMA_64 = 0x0a, */ /* SQ_OP3_INST_LERP_UINT = 0x0b, */ /* SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, */ /* SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, */ /* SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, */ /* SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, */ /* SQ_OP3_INST_MULADD_UINT24 = 0x10, */ /* SQ_OP3_INST_LDS_IDX_OP = 0x11, */ /* SQ_OP3_INST_MULADD = 0x14, */ /* SQ_OP3_INST_MULADD_M2 = 0x15, */ /* SQ_OP3_INST_MULADD_M4 = 0x16, */ /* SQ_OP3_INST_MULADD_D2 = 0x17, */ /* SQ_OP3_INST_MULADD_IEEE = 0x18, */ /* SQ_OP3_INST_CNDE = 0x19, */ /* SQ_OP3_INST_CNDGT = 0x1a, */ /* SQ_OP3_INST_CNDGE = 0x1b, */ /* SQ_OP3_INST_CNDE_INT = 0x1c, */ /* SQ_OP3_INST_CNDGT_INT = 0x1d, */ /* SQ_OP3_INST_CNDGE_INT = 0x1e, */ /* SQ_OP3_INST_MUL_LIT = 0x1f, */ /* BANK_SWIZZLE_mask = 0x07 << 18, */ /* BANK_SWIZZLE_shift = 18, */ /* SQ_ALU_VEC_012 = 0x00, */ /* SQ_ALU_VEC_021 = 0x01, */ /* SQ_ALU_VEC_120 = 0x02, */ /* SQ_ALU_VEC_102 = 0x03, */ /* SQ_ALU_VEC_201 = 0x04, */ /* SQ_ALU_VEC_210 = 0x05, */ LDS_OP_mask = 0x3f << 21, LDS_OP_shift = 21, /* SQ_DS_INST_ADD = 0x00, */ /* SQ_DS_INST_SUB = 0x01, */ /* SQ_DS_INST_RSUB = 0x02, */ /* SQ_DS_INST_INC = 0x03, */ /* SQ_DS_INST_DEC = 0x04, */ /* SQ_DS_INST_MIN_INT = 0x05, */ /* SQ_DS_INST_MAX_INT = 0x06, */ /* SQ_DS_INST_MIN_UINT = 0x07, */ /* SQ_DS_INST_MAX_UINT = 0x08, */ /* SQ_DS_INST_AND = 0x09, */ /* SQ_DS_INST_OR = 0x0a, */ /* SQ_DS_INST_XOR = 0x0b, */ /* SQ_DS_INST_MSKOR = 0x0c, */ /* SQ_DS_INST_WRITE = 0x0d, */ /* SQ_DS_INST_WRITE_REL = 0x0e, */ /* SQ_DS_INST_WRITE2 = 0x0f, */ /* SQ_DS_INST_CMP_STORE = 0x10, */ /* SQ_DS_INST_CMP_STORE_SPF = 0x11, */ /* SQ_DS_INST_BYTE_WRITE = 0x12, */ /* SQ_DS_INST_SHORT_WRITE = 0x13, */ /* SQ_DS_INST_ADD_RET = 0x20, */ /* SQ_DS_INST_SUB_RET = 0x21, */ /* SQ_DS_INST_RSUB_RET = 0x22, */ /* SQ_DS_INST_INC_RET = 0x23, */ /* SQ_DS_INST_DEC_RET = 0x24, */ /* SQ_DS_INST_MIN_INT_RET = 0x25, */ /* SQ_DS_INST_MAX_INT_RET = 0x26, */ /* SQ_DS_INST_MIN_UINT_RET = 0x27, */ /* SQ_DS_INST_MAX_UINT_RET = 0x28, */ /* SQ_DS_INST_AND_RET = 0x29, */ /* SQ_DS_INST_OR_RET = 0x2a, */ /* SQ_DS_INST_XOR_RET = 0x2b, */ /* SQ_DS_INST_MSKOR_RET = 0x2c, */ /* SQ_DS_INST_XCHG_RET = 0x2d, */ /* SQ_DS_INST_XCHG_REL_RET = 0x2e, */ /* SQ_DS_INST_XCHG2_RET = 0x2f, */ /* SQ_DS_INST_CMP_XCHG_RET = 0x30, */ /* SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, */ /* SQ_DS_INST_READ_RET = 0x32, */ /* SQ_DS_INST_READ_REL_RET = 0x33, */ /* SQ_DS_INST_READ2_RET = 0x34, */ /* SQ_DS_INST_READWRITE_RET = 0x35, */ /* SQ_DS_INST_BYTE_READ_RET = 0x36, */ /* SQ_DS_INST_UBYTE_READ_RET = 0x37, */ /* SQ_DS_INST_SHORT_READ_RET = 0x38, */ /* SQ_DS_INST_USHORT_READ_RET = 0x39, */ /* SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, */ IDX_OFFSET_0_bit = 1 << 27, IDX_OFFSET_2_bit = 1 << 28, /* DST_CHAN_mask = 0x03 << 29, */ /* DST_CHAN_shift = 29, */ /* CHAN_X = 0x00, */ /* CHAN_Y = 0x01, */ /* CHAN_Z = 0x02, */ /* CHAN_W = 0x03, */ IDX_OFFSET_3_bit = 1 << 31, SQ_CF_ENCODING_WORD1 = 0x00008dfc, SQ_CF_ENCODING_WORD1__ENCODING_mask = 0x03 << 28, SQ_CF_ENCODING_WORD1__ENCODING_shift = 28, SQ_CF_ENCODING_INST_CF = 0x00, SQ_CF_ENCODING_INST_ALLOC_EXPORT = 0x01, SQ_CF_ENCODING_INST_ALU0 = 0x02, SQ_CF_ENCODING_INST_ALU1 = 0x03, SQ_ALU_WORD0 = 0x00008dfc, /* SRC0_SEL_mask = 0x1ff << 0, */ /* SRC0_SEL_shift = 0, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC0_REL_bit = 1 << 9, */ /* SRC0_CHAN_mask = 0x03 << 10, */ /* SRC0_CHAN_shift = 10, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC0_NEG_bit = 1 << 12, /* SRC1_SEL_mask = 0x1ff << 13, */ /* SRC1_SEL_shift = 13, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC1_REL_bit = 1 << 22, */ /* SRC1_CHAN_mask = 0x03 << 23, */ /* SRC1_CHAN_shift = 23, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC1_NEG_bit = 1 << 25, /* INDEX_MODE_mask = 0x07 << 26, */ /* INDEX_MODE_shift = 26, */ /* SQ_INDEX_AR_X = 0x00, */ /* SQ_INDEX_LOOP = 0x04, */ /* SQ_INDEX_GLOBAL = 0x05, */ /* SQ_INDEX_GLOBAL_AR_X = 0x06, */ /* PRED_SEL_mask = 0x03 << 29, */ /* PRED_SEL_shift = 29, */ /* SQ_PRED_SEL_OFF = 0x00, */ /* SQ_PRED_SEL_ZERO = 0x02, */ /* SQ_PRED_SEL_ONE = 0x03, */ /* LAST_bit = 1 << 31, */ SQ_MEM_RD_WORD1 = 0x00008dfc, SQ_MEM_RD_WORD1__DST_GPR_mask = 0x7f << 0, SQ_MEM_RD_WORD1__DST_GPR_shift = 0, SQ_MEM_RD_WORD1__DST_REL_bit = 1 << 7, SQ_MEM_RD_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_MEM_RD_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_MEM_RD_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_MEM_RD_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_MEM_RD_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DATA_FORMAT_mask = 0x3f << 22, SQ_MEM_RD_WORD1__DATA_FORMAT_shift = 22, SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_shift = 28, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_MEM_RD_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, SQ_MEM_RD_WORD1__SRF_MODE_ALL_bit = 1 << 31, SQ_LSTMP_RING_BASE = 0x00008e10, SQ_LSTMP_RING_SIZE = 0x00008e14, SQ_HSTMP_RING_BASE = 0x00008e18, SQ_HSTMP_RING_SIZE = 0x00008e1c, SQ_EX_ALLOC_TABLE_SLOTS = 0x00008e48, PIX_SLOTS_mask = 0x7f << 0, PIX_SLOTS_shift = 0, POS_SLOTS_mask = 0x7f << 8, POS_SLOTS_shift = 8, SMX_SLOTS_mask = 0x7f << 16, SMX_SLOTS_shift = 16, SX_EXPORT_BUFFER_SIZES = 0x0000900c, COLOR_BUFFER_SIZE_mask = 0xff << 0, COLOR_BUFFER_SIZE_shift = 0, POSITION_BUFFER_SIZE_mask = 0xff << 8, POSITION_BUFFER_SIZE_shift = 8, SMX_BUFFER_SIZE_mask = 0xff << 16, SMX_BUFFER_SIZE_shift = 16, SX_MEMORY_EXPORT_BASE = 0x00009010, SX_MEMORY_EXPORT_SIZE = 0x00009014, SPI_CONFIG_CNTL = 0x00009100, GPR_WRITE_PRIORITY_mask = 0x3ffff << 0, GPR_WRITE_PRIORITY_shift = 0, SPI_CONFIG_CNTL_1 = 0x0000913c, VTX_DONE_DELAY_mask = 0x0f << 0, VTX_DONE_DELAY_shift = 0, X_DELAY_14_CLKS = 0x00, X_DELAY_16_CLKS = 0x01, X_DELAY_18_CLKS = 0x02, X_DELAY_20_CLKS = 0x03, X_DELAY_22_CLKS = 0x04, X_DELAY_24_CLKS = 0x05, X_DELAY_26_CLKS = 0x06, X_DELAY_28_CLKS = 0x07, X_DELAY_30_CLKS = 0x08, X_DELAY_32_CLKS = 0x09, X_DELAY_34_CLKS = 0x0a, X_DELAY_4_CLKS = 0x0b, X_DELAY_6_CLKS = 0x0c, X_DELAY_8_CLKS = 0x0d, X_DELAY_10_CLKS = 0x0e, X_DELAY_12_CLKS = 0x0f, INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, BC_OPTIMIZE_DISABLE_bit = 1 << 5, PC_LIMIT_ENABLE_bit = 1 << 6, PC_LIMIT_STRICT_bit = 1 << 7, PC_LIMIT_SIZE_mask = 0xffff << 16, PC_LIMIT_SIZE_shift = 16, TD_CNTL = 0x00009494, SYNC_PHASE_SH_mask = 0x03 << 0, SYNC_PHASE_SH_shift = 0, PAD_STALL_EN_bit = 1 << 8, EXTEND_LDS_STALL_mask = 0x03 << 9, EXTEND_LDS_STALL_shift = 9, X_0 = 0x00, EXTEND_LDS_STALL__X_1 = 0x01, X_2 = 0x02, X_3 = 0x03, GATHER4_FLOAT_MODE_bit = 1 << 16, LD_FLOAT_MODE_bit = 1 << 18, GATHER4_DX9_MODE_bit = 1 << 19, TD_STATUS = 0x00009498, BUSY_bit = 1 << 31, DB_SUBTILE_CONTROL = 0x00009858, MSAA1_X_mask = 0x03 << 0, MSAA1_X_shift = 0, MSAA1_Y_mask = 0x03 << 2, MSAA1_Y_shift = 2, MSAA2_X_mask = 0x03 << 4, MSAA2_X_shift = 4, MSAA2_Y_mask = 0x03 << 6, MSAA2_Y_shift = 6, MSAA4_X_mask = 0x03 << 8, MSAA4_X_shift = 8, MSAA4_Y_mask = 0x03 << 10, MSAA4_Y_shift = 10, MSAA8_X_mask = 0x03 << 12, MSAA8_X_shift = 12, MSAA8_Y_mask = 0x03 << 14, MSAA8_Y_shift = 14, MSAA16_X_mask = 0x03 << 16, MSAA16_X_shift = 16, MSAA16_Y_mask = 0x03 << 18, MSAA16_Y_shift = 18, DB_ZPASS_COUNT_LOW = 0x00009870, DB_ZPASS_COUNT_HI = 0x00009874, COUNT_HI_mask = 0x7fffffff << 0, COUNT_HI_shift = 0, TD_PS_BORDER_COLOR_INDEX = 0x0000a400, INDEX_mask = 0x1f << 0, INDEX_shift = 0, TD_PS_BORDER_COLOR_RED = 0x0000a404, TD_PS_BORDER_COLOR_GREEN = 0x0000a408, TD_PS_BORDER_COLOR_BLUE = 0x0000a40c, TD_PS_BORDER_COLOR_ALPHA = 0x0000a410, TD_VS_BORDER_COLOR_INDEX = 0x0000a414, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_VS_BORDER_COLOR_RED = 0x0000a418, TD_VS_BORDER_COLOR_GREEN = 0x0000a41c, TD_VS_BORDER_COLOR_BLUE = 0x0000a420, TD_VS_BORDER_COLOR_ALPHA = 0x0000a424, TD_GS_BORDER_COLOR_INDEX = 0x0000a428, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_GS_BORDER_COLOR_RED = 0x0000a42c, TD_GS_BORDER_COLOR_GREEN = 0x0000a430, TD_GS_BORDER_COLOR_BLUE = 0x0000a434, TD_GS_BORDER_COLOR_ALPHA = 0x0000a438, TD_HS_BORDER_COLOR_INDEX = 0x0000a43c, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_HS_BORDER_COLOR_RED = 0x0000a440, TD_HS_BORDER_COLOR_GREEN = 0x0000a444, TD_HS_BORDER_COLOR_BLUE = 0x0000a448, TD_HS_BORDER_COLOR_ALPHA = 0x0000a44c, TD_LS_BORDER_COLOR_INDEX = 0x0000a450, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_LS_BORDER_COLOR_RED = 0x0000a454, TD_LS_BORDER_COLOR_GREEN = 0x0000a458, TD_LS_BORDER_COLOR_BLUE = 0x0000a45c, TD_LS_BORDER_COLOR_ALPHA = 0x0000a460, TD_CS_BORDER_COLOR_INDEX = 0x0000a464, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_CS_BORDER_COLOR_RED = 0x0000a468, TD_CS_BORDER_COLOR_GREEN = 0x0000a46c, TD_CS_BORDER_COLOR_BLUE = 0x0000a470, TD_CS_BORDER_COLOR_ALPHA = 0x0000a474, DB_RENDER_CONTROL = 0x00028000, DEPTH_CLEAR_ENABLE_bit = 1 << 0, STENCIL_CLEAR_ENABLE_bit = 1 << 1, DEPTH_COPY_bit = 1 << 2, STENCIL_COPY_bit = 1 << 3, RESUMMARIZE_ENABLE_bit = 1 << 4, STENCIL_COMPRESS_DISABLE_bit = 1 << 5, DEPTH_COMPRESS_DISABLE_bit = 1 << 6, COPY_CENTROID_bit = 1 << 7, COPY_SAMPLE_mask = 0x0f << 8, COPY_SAMPLE_shift = 8, DB_COUNT_CONTROL = 0x00028004, ZPASS_INCREMENT_DISABLE_bit = 1 << 0, PERFECT_ZPASS_COUNTS_bit = 1 << 1, SAMPLE_RATE_mask = 0x07 << 4, SAMPLE_RATE_shift = 4, DB_DEPTH_VIEW = 0x00028008, SLICE_START_mask = 0x7ff << 0, SLICE_START_shift = 0, SLICE_MAX_mask = 0x7ff << 13, SLICE_MAX_shift = 13, Z_READ_ONLY_bit = 1 << 24, STENCIL_READ_ONLY_bit = 1 << 25, DB_RENDER_OVERRIDE = 0x0002800c, FORCE_HIZ_ENABLE_mask = 0x03 << 0, FORCE_HIZ_ENABLE_shift = 0, FORCE_OFF = 0x00, FORCE_ENABLE = 0x01, FORCE_DISABLE = 0x02, FORCE_RESERVED = 0x03, FORCE_HIS_ENABLE0_mask = 0x03 << 2, FORCE_HIS_ENABLE0_shift = 2, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_HIS_ENABLE1_mask = 0x03 << 4, FORCE_HIS_ENABLE1_shift = 4, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_SHADER_Z_ORDER_bit = 1 << 6, FAST_Z_DISABLE_bit = 1 << 7, FAST_STENCIL_DISABLE_bit = 1 << 8, NOOP_CULL_DISABLE_bit = 1 << 9, FORCE_COLOR_KILL_bit = 1 << 10, FORCE_Z_READ_bit = 1 << 11, FORCE_STENCIL_READ_bit = 1 << 12, FORCE_FULL_Z_RANGE_mask = 0x03 << 13, FORCE_FULL_Z_RANGE_shift = 13, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, IGNORE_SC_ZRANGE_bit = 1 << 17, DISABLE_FULLY_COVERED_bit = 1 << 18, FORCE_Z_LIMIT_SUMM_mask = 0x03 << 19, FORCE_Z_LIMIT_SUMM_shift = 19, FORCE_SUMM_OFF = 0x00, FORCE_SUMM_MINZ = 0x01, FORCE_SUMM_MAXZ = 0x02, FORCE_SUMM_BOTH = 0x03, MAX_TILES_IN_DTT_mask = 0x1f << 21, MAX_TILES_IN_DTT_shift = 21, DISABLE_TILE_RATE_TILES_bit = 1 << 26, FORCE_Z_DIRTY_bit = 1 << 27, FORCE_STENCIL_DIRTY_bit = 1 << 28, FORCE_Z_VALID_bit = 1 << 29, FORCE_STENCIL_VALID_bit = 1 << 30, PRESERVE_COMPRESSION_bit = 1 << 31, DB_RENDER_OVERRIDE2 = 0x00028010, PARTIAL_SQUAD_LAUNCH_CONTROL_mask = 0x03 << 0, PARTIAL_SQUAD_LAUNCH_CONTROL_shift = 0, PSLC_AUTO = 0x00, PSLC_ON_HANG_ONLY = 0x01, PSLC_ASAP = 0x02, PSLC_COUNTDOWN = 0x03, PARTIAL_SQUAD_LAUNCH_COUNTDOWN_mask = 0x07 << 2, PARTIAL_SQUAD_LAUNCH_COUNTDOWN_shift = 2, DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO_bit = 1 << 5, DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_bit = 1 << 6, DISABLE_COLOR_ON_VALIDATION_bit = 1 << 7, DECOMPRESS_Z_ON_FLUSH_bit = 1 << 8, DB_HTILE_DATA_BASE = 0x00028014, DB_STENCIL_CLEAR = 0x00028028, DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, DB_STENCIL_CLEAR__CLEAR_shift = 0, DB_DEPTH_CLEAR = 0x0002802c, PA_SC_SCREEN_SCISSOR_TL = 0x00028030, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0, PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16, PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, PA_SC_SCREEN_SCISSOR_BR = 0x00028034, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0, PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, DB_DEPTH_INFO = 0x0002803c, ADDR5_SWIZZLE_MASK_mask = 0x0f << 0, ADDR5_SWIZZLE_MASK_shift = 0, DB_Z_INFO = 0x00028040, DB_Z_INFO__FORMAT_mask = 0x03 << 0, DB_Z_INFO__FORMAT_shift = 0, Z_INVALID = 0x00, Z_16 = 0x01, Z_24 = 0x02, Z_32_FLOAT = 0x03, DB_Z_INFO__NUM_SAMPLES_mask = 0x03 << 2, DB_Z_INFO__NUM_SAMPLES_shift = 2, DB_Z_INFO__ARRAY_MODE_mask = 0x0f << 4, DB_Z_INFO__ARRAY_MODE_shift = 4, ARRAY_1D_TILED_THIN1 = 0x02, ARRAY_2D_TILED_THIN1 = 0x04, DB_Z_INFO__TILE_SPLIT_mask = 0x07 << 8, DB_Z_INFO__TILE_SPLIT_shift = 8, ADDR_SURF_TILE_SPLIT_64B = 0x00, ADDR_SURF_TILE_SPLIT_128B = 0x01, ADDR_SURF_TILE_SPLIT_256B = 0x02, ADDR_SURF_TILE_SPLIT_512B = 0x03, ADDR_SURF_TILE_SPLIT_1KB = 0x04, ADDR_SURF_TILE_SPLIT_2KB = 0x05, ADDR_SURF_TILE_SPLIT_4KB = 0x06, DB_Z_INFO__NUM_BANKS_mask = 0x03 << 12, DB_Z_INFO__NUM_BANKS_shift = 12, ADDR_SURF_2_BANK = 0x00, ADDR_SURF_4_BANK = 0x01, ADDR_SURF_8_BANK = 0x02, ADDR_SURF_16_BANK = 0x03, DB_Z_INFO__BANK_WIDTH_mask = 0x03 << 16, DB_Z_INFO__BANK_WIDTH_shift = 16, ADDR_SURF_BANK_WIDTH_1 = 0x00, ADDR_SURF_BANK_WIDTH_2 = 0x01, ADDR_SURF_BANK_WIDTH_4 = 0x02, ADDR_SURF_BANK_WIDTH_8 = 0x03, DB_Z_INFO__BANK_HEIGHT_mask = 0x03 << 20, DB_Z_INFO__BANK_HEIGHT_shift = 20, ADDR_SURF_BANK_HEIGHT_1 = 0x00, ADDR_SURF_BANK_HEIGHT_2 = 0x01, ADDR_SURF_BANK_HEIGHT_4 = 0x02, ADDR_SURF_BANK_HEIGHT_8 = 0x03, DB_Z_INFO__MACRO_TILE_ASPECT_mask = 0x03 << 24, DB_Z_INFO__MACRO_TILE_ASPECT_shift = 24, ADDR_SURF_MACRO_ASPECT_1 = 0x00, ADDR_SURF_MACRO_ASPECT_2 = 0x01, ADDR_SURF_MACRO_ASPECT_4 = 0x02, ADDR_SURF_MACRO_ASPECT_8 = 0x03, ALLOW_EXPCLEAR_bit = 1 << 27, READ_SIZE_bit = 1 << 28, TILE_SURFACE_ENABLE_bit = 1 << 29, ZRANGE_PRECISION_bit = 1 << 31, DB_STENCIL_INFO = 0x00028044, DB_STENCIL_INFO__FORMAT_bit = 1 << 0, DB_STENCIL_INFO__TILE_SPLIT_mask = 0x07 << 8, DB_STENCIL_INFO__TILE_SPLIT_shift = 8, /* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ /* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ /* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ /* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ /* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ /* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ /* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ /* ALLOW_EXPCLEAR_bit = 1 << 27, */ TILE_STENCIL_DISABLE_bit = 1 << 29, DB_Z_READ_BASE = 0x00028048, DB_STENCIL_READ_BASE = 0x0002804c, DB_Z_WRITE_BASE = 0x00028050, DB_STENCIL_WRITE_BASE = 0x00028054, DB_DEPTH_SIZE = 0x00028058, PITCH_TILE_MAX_mask = 0x7ff << 0, PITCH_TILE_MAX_shift = 0, HEIGHT_TILE_MAX_mask = 0x7ff << 11, HEIGHT_TILE_MAX_shift = 11, DB_DEPTH_SLICE = 0x0002805c, SLICE_TILE_MAX_mask = 0x3fffff << 0, SLICE_TILE_MAX_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, PA_SC_WINDOW_OFFSET = 0x00028200, WINDOW_X_OFFSET_mask = 0xffff << 0, WINDOW_X_OFFSET_shift = 0, WINDOW_Y_OFFSET_mask = 0xffff << 16, WINDOW_Y_OFFSET_shift = 16, PA_SC_WINDOW_SCISSOR_TL = 0x00028204, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0, PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, WINDOW_OFFSET_DISABLE_bit = 1 << 31, PA_SC_WINDOW_SCISSOR_BR = 0x00028208, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0, PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, PA_SC_CLIPRECT_RULE = 0x0002820c, CLIP_RULE_mask = 0xffff << 0, CLIP_RULE_shift = 0, PA_SC_CLIPRECT_0_TL = 0x00028210, PA_SC_CLIPRECT_0_TL_num = 4, PA_SC_CLIPRECT_0_TL_offset = 8, PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0, PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16, PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, PA_SC_CLIPRECT_0_BR = 0x00028214, PA_SC_CLIPRECT_0_BR_num = 4, PA_SC_CLIPRECT_0_BR_offset = 8, PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0, PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16, PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, PA_SC_EDGERULE = 0x00028230, ER_TRI_mask = 0x0f << 0, ER_TRI_shift = 0, ER_POINT_mask = 0x0f << 4, ER_POINT_shift = 4, ER_RECT_mask = 0x0f << 8, ER_RECT_shift = 8, ER_LINE_LR_mask = 0x3f << 12, ER_LINE_LR_shift = 12, ER_LINE_RL_mask = 0x3f << 18, ER_LINE_RL_shift = 18, ER_LINE_TB_mask = 0x0f << 24, ER_LINE_TB_shift = 24, ER_LINE_BT_mask = 0x0f << 28, ER_LINE_BT_shift = 28, PA_SU_HARDWARE_SCREEN_OFFSET = 0x00028234, HW_SCREEN_OFFSET_X_mask = 0x1f << 0, HW_SCREEN_OFFSET_X_shift = 0, HW_SCREEN_OFFSET_Y_mask = 0x1f << 8, HW_SCREEN_OFFSET_Y_shift = 8, CB_TARGET_MASK = 0x00028238, TARGET0_ENABLE_mask = 0x0f << 0, TARGET0_ENABLE_shift = 0, TARGET1_ENABLE_mask = 0x0f << 4, TARGET1_ENABLE_shift = 4, TARGET2_ENABLE_mask = 0x0f << 8, TARGET2_ENABLE_shift = 8, TARGET3_ENABLE_mask = 0x0f << 12, TARGET3_ENABLE_shift = 12, TARGET4_ENABLE_mask = 0x0f << 16, TARGET4_ENABLE_shift = 16, TARGET5_ENABLE_mask = 0x0f << 20, TARGET5_ENABLE_shift = 20, TARGET6_ENABLE_mask = 0x0f << 24, TARGET6_ENABLE_shift = 24, TARGET7_ENABLE_mask = 0x0f << 28, TARGET7_ENABLE_shift = 28, CB_SHADER_MASK = 0x0002823c, OUTPUT0_ENABLE_mask = 0x0f << 0, OUTPUT0_ENABLE_shift = 0, OUTPUT1_ENABLE_mask = 0x0f << 4, OUTPUT1_ENABLE_shift = 4, OUTPUT2_ENABLE_mask = 0x0f << 8, OUTPUT2_ENABLE_shift = 8, OUTPUT3_ENABLE_mask = 0x0f << 12, OUTPUT3_ENABLE_shift = 12, OUTPUT4_ENABLE_mask = 0x0f << 16, OUTPUT4_ENABLE_shift = 16, OUTPUT5_ENABLE_mask = 0x0f << 20, OUTPUT5_ENABLE_shift = 20, OUTPUT6_ENABLE_mask = 0x0f << 24, OUTPUT6_ENABLE_shift = 24, OUTPUT7_ENABLE_mask = 0x0f << 28, OUTPUT7_ENABLE_shift = 28, PA_SC_GENERIC_SCISSOR_TL = 0x00028240, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0, PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_GENERIC_SCISSOR_BR = 0x00028244, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0, PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, PA_SC_VPORT_SCISSOR_0_TL_num = 16, PA_SC_VPORT_SCISSOR_0_TL_offset = 8, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, PA_SC_VPORT_SCISSOR_0_BR_num = 16, PA_SC_VPORT_SCISSOR_0_BR_offset = 8, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, PA_SC_VPORT_ZMIN_0 = 0x000282d0, PA_SC_VPORT_ZMIN_0_num = 16, PA_SC_VPORT_ZMIN_0_offset = 8, PA_SC_VPORT_ZMAX_0 = 0x000282d4, PA_SC_VPORT_ZMAX_0_num = 16, PA_SC_VPORT_ZMAX_0_offset = 8, SX_MISC = 0x00028350, MULTIPASS_bit = 1 << 0, SX_SURFACE_SYNC = 0x00028354, SURFACE_SYNC_MASK_mask = 0x3ff << 0, SURFACE_SYNC_MASK_shift = 0, SX_SCATTER_EXPORT_BASE = 0x00028358, SX_SCATTER_EXPORT_SIZE = 0x0002835c, SQ_VTX_SEMANTIC_0 = 0x00028380, SQ_VTX_SEMANTIC_0_num = 32, /* SEMANTIC_ID_mask = 0xff << 0, */ /* SEMANTIC_ID_shift = 0, */ VGT_MAX_VTX_INDX = 0x00028400, VGT_MIN_VTX_INDX = 0x00028404, VGT_INDX_OFFSET = 0x00028408, VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, SX_ALPHA_TEST_CONTROL = 0x00028410, ALPHA_FUNC_mask = 0x07 << 0, ALPHA_FUNC_shift = 0, REF_NEVER = 0x00, REF_LESS = 0x01, REF_EQUAL = 0x02, REF_LEQUAL = 0x03, REF_GREATER = 0x04, REF_NOTEQUAL = 0x05, REF_GEQUAL = 0x06, REF_ALWAYS = 0x07, ALPHA_TEST_ENABLE_bit = 1 << 3, ALPHA_TEST_BYPASS_bit = 1 << 8, CB_BLEND_RED = 0x00028414, CB_BLEND_GREEN = 0x00028418, CB_BLEND_BLUE = 0x0002841c, CB_BLEND_ALPHA = 0x00028420, DB_STENCILREFMASK = 0x00028430, STENCILREF_mask = 0xff << 0, STENCILREF_shift = 0, STENCILMASK_mask = 0xff << 8, STENCILMASK_shift = 8, STENCILWRITEMASK_mask = 0xff << 16, STENCILWRITEMASK_shift = 16, DB_STENCILREFMASK_BF = 0x00028434, STENCILREF_BF_mask = 0xff << 0, STENCILREF_BF_shift = 0, STENCILMASK_BF_mask = 0xff << 8, STENCILMASK_BF_shift = 8, STENCILWRITEMASK_BF_mask = 0xff << 16, STENCILWRITEMASK_BF_shift = 16, SX_ALPHA_REF = 0x00028438, PA_CL_VPORT_XSCALE_0 = 0x0002843c, PA_CL_VPORT_XSCALE_0_num = 16, PA_CL_VPORT_XSCALE_0_offset = 24, PA_CL_VPORT_XOFFSET_0 = 0x00028440, PA_CL_VPORT_XOFFSET_0_num = 16, PA_CL_VPORT_XOFFSET_0_offset = 24, PA_CL_VPORT_YSCALE_0 = 0x00028444, PA_CL_VPORT_YSCALE_0_num = 16, PA_CL_VPORT_YSCALE_0_offset = 24, PA_CL_VPORT_YOFFSET_0 = 0x00028448, PA_CL_VPORT_YOFFSET_0_num = 16, PA_CL_VPORT_YOFFSET_0_offset = 24, PA_CL_VPORT_ZSCALE_0 = 0x0002844c, PA_CL_VPORT_ZSCALE_0_num = 16, PA_CL_VPORT_ZSCALE_0_offset = 24, PA_CL_VPORT_ZOFFSET_0 = 0x00028450, PA_CL_VPORT_ZOFFSET_0_num = 16, PA_CL_VPORT_ZOFFSET_0_offset = 24, PA_CL_UCP_0_X = 0x000285bc, PA_CL_UCP_0_X_num = 6, PA_CL_UCP_0_X_offset = 16, PA_CL_UCP_0_Y = 0x000285c0, PA_CL_UCP_0_Y_num = 6, PA_CL_UCP_0_Y_offset = 16, PA_CL_UCP_0_Z = 0x000285c4, PA_CL_UCP_0_Z_num = 6, PA_CL_UCP_0_Z_offset = 16, PA_CL_UCP_0_W = 0x000285c8, PA_CL_UCP_0_W_num = 6, PA_CL_UCP_0_W_offset = 16, SPI_VS_OUT_ID_0 = 0x0002861c, SPI_VS_OUT_ID_0_num = 10, SEMANTIC_0_mask = 0xff << 0, SEMANTIC_0_shift = 0, SEMANTIC_1_mask = 0xff << 8, SEMANTIC_1_shift = 8, SEMANTIC_2_mask = 0xff << 16, SEMANTIC_2_shift = 16, SEMANTIC_3_mask = 0xff << 24, SEMANTIC_3_shift = 24, SPI_PS_INPUT_CNTL_0 = 0x00028644, SPI_PS_INPUT_CNTL_0_num = 32, SEMANTIC_mask = 0xff << 0, SEMANTIC_shift = 0, DEFAULT_VAL_mask = 0x03 << 8, DEFAULT_VAL_shift = 8, X_0_0F = 0x00, FLAT_SHADE_bit = 1 << 10, CYL_WRAP_mask = 0x0f << 13, CYL_WRAP_shift = 13, PT_SPRITE_TEX_bit = 1 << 17, SPI_VS_OUT_CONFIG = 0x000286c4, VS_PER_COMPONENT_bit = 1 << 0, VS_EXPORT_COUNT_mask = 0x1f << 1, VS_EXPORT_COUNT_shift = 1, VS_HALF_PACK_bit = 1 << 6, VS_EXPORTS_FOG_bit = 1 << 8, VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, VS_OUT_FOG_VEC_ADDR_shift = 9, SPI_PS_IN_CONTROL_0 = 0x000286cc, NUM_INTERP_mask = 0x3f << 0, NUM_INTERP_shift = 0, POSITION_ENA_bit = 1 << 8, POSITION_CENTROID_bit = 1 << 9, POSITION_ADDR_mask = 0x1f << 10, POSITION_ADDR_shift = 10, PARAM_GEN_mask = 0x0f << 15, PARAM_GEN_shift = 15, PERSP_GRADIENT_ENA_bit = 1 << 28, LINEAR_GRADIENT_ENA_bit = 1 << 29, POSITION_SAMPLE_bit = 1 << 30, SPI_PS_IN_CONTROL_1 = 0x000286d0, FRONT_FACE_ENA_bit = 1 << 8, FRONT_FACE_ALL_BITS_bit = 1 << 11, FRONT_FACE_ADDR_mask = 0x1f << 12, FRONT_FACE_ADDR_shift = 12, FOG_ADDR_mask = 0x7f << 17, FOG_ADDR_shift = 17, FIXED_PT_POSITION_ENA_bit = 1 << 24, FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, FIXED_PT_POSITION_ADDR_shift = 25, POSITION_ULC_bit = 1 << 30, SPI_INTERP_CONTROL_0 = 0x000286d4, FLAT_SHADE_ENA_bit = 1 << 0, PNT_SPRITE_ENA_bit = 1 << 1, PNT_SPRITE_OVRD_X_mask = 0x07 << 2, PNT_SPRITE_OVRD_X_shift = 2, SPI_PNT_SPRITE_SEL_0 = 0x00, SPI_PNT_SPRITE_SEL_1 = 0x01, SPI_PNT_SPRITE_SEL_S = 0x02, SPI_PNT_SPRITE_SEL_T = 0x03, SPI_PNT_SPRITE_SEL_NONE = 0x04, PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, PNT_SPRITE_OVRD_Y_shift = 5, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, PNT_SPRITE_OVRD_Z_shift = 8, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_W_mask = 0x07 << 11, PNT_SPRITE_OVRD_W_shift = 11, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_TOP_1_bit = 1 << 14, SPI_INPUT_Z = 0x000286d8, PROVIDE_Z_TO_SPI_bit = 1 << 0, SPI_FOG_CNTL = 0x000286dc, PASS_FOG_THROUGH_PS_bit = 1 << 0, SPI_BARYC_CNTL = 0x000286e0, PERSP_CENTER_ENA_mask = 0x03 << 0, PERSP_CENTER_ENA_shift = 0, X_OFF = 0x00, PERSP_CENTER_ENA__X_ON_AT_CENTER = 0x01, PERSP_CENTER_ENA__X_ON_AT_CENTROID = 0x02, PERSP_CENTROID_ENA_mask = 0x03 << 4, PERSP_CENTROID_ENA_shift = 4, /* X_OFF = 0x00, */ PERSP_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, PERSP_CENTROID_ENA__X_ON_AT_CENTER = 0x02, PERSP_SAMPLE_ENA_mask = 0x03 << 8, PERSP_SAMPLE_ENA_shift = 8, /* X_OFF = 0x00, */ PERSP_PULL_MODEL_ENA_mask = 0x03 << 12, PERSP_PULL_MODEL_ENA_shift = 12, /* X_OFF = 0x00, */ LINEAR_CENTER_ENA_mask = 0x03 << 16, LINEAR_CENTER_ENA_shift = 16, /* X_OFF = 0x00, */ LINEAR_CENTER_ENA__X_ON_AT_CENTER = 0x01, LINEAR_CENTER_ENA__X_ON_AT_CENTROID = 0x02, LINEAR_CENTROID_ENA_mask = 0x03 << 20, LINEAR_CENTROID_ENA_shift = 20, /* X_OFF = 0x00, */ LINEAR_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, LINEAR_CENTROID_ENA__X_ON_AT_CENTER = 0x02, LINEAR_SAMPLE_ENA_mask = 0x03 << 24, LINEAR_SAMPLE_ENA_shift = 24, /* X_OFF = 0x00, */ SPI_PS_IN_CONTROL_2 = 0x000286e4, LINE_STIPPLE_TEX_ADDR_mask = 0xff << 0, LINE_STIPPLE_TEX_ADDR_shift = 0, LINE_STIPPLE_TEX_ENA_bit = 1 << 8, SPI_GPR_MGMT = 0x000286f8, SPI_GPR_MGMT__NUM_PS_GPRS_mask = 0x1f << 0, SPI_GPR_MGMT__NUM_PS_GPRS_shift = 0, SPI_GPR_MGMT__NUM_VS_GPRS_mask = 0x1f << 5, SPI_GPR_MGMT__NUM_VS_GPRS_shift = 5, NUM_GS_GPRS_mask = 0x1f << 10, NUM_GS_GPRS_shift = 10, NUM_ES_GPRS_mask = 0x1f << 15, NUM_ES_GPRS_shift = 15, NUM_HS_GPRS_mask = 0x1f << 20, NUM_HS_GPRS_shift = 20, NUM_LS_GPRS_mask = 0x1f << 25, NUM_LS_GPRS_shift = 25, SPI_LDS_MGMT = 0x000286fc, NUM_PS_LDS_mask = 0xff << 0, NUM_PS_LDS_shift = 0, NUM_LS_LDS_mask = 0xff << 8, NUM_LS_LDS_shift = 8, SPI_STACK_MGMT = 0x00028700, NUM_PS_STACK_mask = 0x1f << 0, NUM_PS_STACK_shift = 0, NUM_VS_STACK_mask = 0x1f << 5, NUM_VS_STACK_shift = 5, NUM_GS_STACK_mask = 0x1f << 10, NUM_GS_STACK_shift = 10, NUM_ES_STACK_mask = 0x1f << 15, NUM_ES_STACK_shift = 15, NUM_HS_STACK_mask = 0x1f << 20, NUM_HS_STACK_shift = 20, NUM_LS_STACK_mask = 0x1f << 25, NUM_LS_STACK_shift = 25, SPI_WAVE_MGMT_1 = 0x00028704, NUM_PS_WAVES_mask = 0x1f << 0, NUM_PS_WAVES_shift = 0, NUM_VS_WAVES_mask = 0x1f << 5, NUM_VS_WAVES_shift = 5, NUM_GS_WAVES_mask = 0x1f << 10, NUM_GS_WAVES_shift = 10, NUM_ES_WAVES_mask = 0x1f << 15, NUM_ES_WAVES_shift = 15, NUM_HS_WAVES_mask = 0x1f << 20, NUM_HS_WAVES_shift = 20, NUM_LS_WAVES_mask = 0x1f << 25, NUM_LS_WAVES_shift = 25, SPI_WAVE_MGMT_2 = 0x00028708, NUM_CS_WAVES_ONE_RING_mask = 0x1f << 0, NUM_CS_WAVES_ONE_RING_shift = 0, NUM_CS_WAVES_MULTI_RING_mask = 0x1f << 5, NUM_CS_WAVES_MULTI_RING_shift = 5, CB_BLEND0_CONTROL = 0x00028780, CB_BLEND0_CONTROL_num = 8, COLOR_SRCBLEND_mask = 0x1f << 0, COLOR_SRCBLEND_shift = 0, BLEND_ZERO = 0x00, BLEND_ONE = 0x01, BLEND_SRC_COLOR = 0x02, BLEND_ONE_MINUS_SRC_COLOR = 0x03, BLEND_SRC_ALPHA = 0x04, BLEND_ONE_MINUS_SRC_ALPHA = 0x05, BLEND_DST_ALPHA = 0x06, BLEND_ONE_MINUS_DST_ALPHA = 0x07, BLEND_DST_COLOR = 0x08, BLEND_ONE_MINUS_DST_COLOR = 0x09, BLEND_SRC_ALPHA_SATURATE = 0x0a, BLEND_BOTH_SRC_ALPHA = 0x0b, BLEND_BOTH_INV_SRC_ALPHA = 0x0c, BLEND_CONSTANT_COLOR = 0x0d, BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, BLEND_SRC1_COLOR = 0x0f, BLEND_INV_SRC1_COLOR = 0x10, BLEND_SRC1_ALPHA = 0x11, BLEND_INV_SRC1_ALPHA = 0x12, BLEND_CONSTANT_ALPHA = 0x13, BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, COLOR_COMB_FCN_mask = 0x07 << 5, COLOR_COMB_FCN_shift = 5, COMB_DST_PLUS_SRC = 0x00, COMB_SRC_MINUS_DST = 0x01, COMB_MIN_DST_SRC = 0x02, COMB_MAX_DST_SRC = 0x03, COMB_DST_MINUS_SRC = 0x04, COLOR_DESTBLEND_mask = 0x1f << 8, COLOR_DESTBLEND_shift = 8, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ ALPHA_SRCBLEND_mask = 0x1f << 16, ALPHA_SRCBLEND_shift = 16, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ ALPHA_COMB_FCN_mask = 0x07 << 21, ALPHA_COMB_FCN_shift = 21, /* COMB_DST_PLUS_SRC = 0x00, */ /* COMB_SRC_MINUS_DST = 0x01, */ /* COMB_MIN_DST_SRC = 0x02, */ /* COMB_MAX_DST_SRC = 0x03, */ /* COMB_DST_MINUS_SRC = 0x04, */ ALPHA_DESTBLEND_mask = 0x1f << 24, ALPHA_DESTBLEND_shift = 24, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ SEPARATE_ALPHA_BLEND_bit = 1 << 29, CB_BLEND0_CONTROL__ENABLE_bit = 1 << 30, PA_CL_POINT_X_RAD = 0x000287d4, PA_CL_POINT_Y_RAD = 0x000287d8, PA_CL_POINT_SIZE = 0x000287dc, PA_CL_POINT_CULL_RAD = 0x000287e0, VGT_DMA_BASE_HI = 0x000287e4, VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, VGT_DMA_BASE = 0x000287e8, VGT_DRAW_INITIATOR = 0x000287f0, SOURCE_SELECT_mask = 0x03 << 0, SOURCE_SELECT_shift = 0, DI_SRC_SEL_DMA = 0x00, DI_SRC_SEL_IMMEDIATE = 0x01, DI_SRC_SEL_AUTO_INDEX = 0x02, DI_SRC_SEL_RESERVED = 0x03, MAJOR_MODE_mask = 0x03 << 2, MAJOR_MODE_shift = 2, DI_MAJOR_MODE_0 = 0x00, DI_MAJOR_MODE_1 = 0x01, NOT_EOP_bit = 1 << 5, USE_OPAQUE_bit = 1 << 6, VGT_IMMED_DATA = 0x000287f4, VGT_EVENT_ADDRESS_REG = 0x000287f8, ADDRESS_LOW_mask = 0xfffffff << 0, ADDRESS_LOW_shift = 0, DB_DEPTH_CONTROL = 0x00028800, STENCIL_ENABLE_bit = 1 << 0, Z_ENABLE_bit = 1 << 1, Z_WRITE_ENABLE_bit = 1 << 2, ZFUNC_mask = 0x07 << 4, ZFUNC_shift = 4, FRAG_NEVER = 0x00, FRAG_LESS = 0x01, FRAG_EQUAL = 0x02, FRAG_LEQUAL = 0x03, FRAG_GREATER = 0x04, FRAG_NOTEQUAL = 0x05, FRAG_GEQUAL = 0x06, FRAG_ALWAYS = 0x07, BACKFACE_ENABLE_bit = 1 << 7, STENCILFUNC_mask = 0x07 << 8, STENCILFUNC_shift = 8, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_mask = 0x07 << 11, STENCILFAIL_shift = 11, STENCIL_KEEP = 0x00, STENCIL_ZERO = 0x01, STENCIL_REPLACE = 0x02, STENCIL_INCR_CLAMP = 0x03, STENCIL_DECR_CLAMP = 0x04, STENCIL_INVERT = 0x05, STENCIL_INCR_WRAP = 0x06, STENCIL_DECR_WRAP = 0x07, STENCILZPASS_mask = 0x07 << 14, STENCILZPASS_shift = 14, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_mask = 0x07 << 17, STENCILZFAIL_shift = 17, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILFUNC_BF_mask = 0x07 << 20, STENCILFUNC_BF_shift = 20, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_BF_mask = 0x07 << 23, STENCILFAIL_BF_shift = 23, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZPASS_BF_mask = 0x07 << 26, STENCILZPASS_BF_shift = 26, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_BF_mask = 0x07 << 29, STENCILZFAIL_BF_shift = 29, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ DB_EQAA = 0x00028804, CB_COLOR_CONTROL = 0x00028808, DEGAMMA_ENABLE_bit = 1 << 3, CB_COLOR_CONTROL__MODE_mask = 0x07 << 4, CB_COLOR_CONTROL__MODE_shift = 4, CB_DISABLE = 0x00, CB_NORMAL = 0x01, CB_ELIMINATE_FAST_CLEAR = 0x02, CB_RESOLVE = 0x03, CB_DECOMPRESS = 0x04, CB_FMASK_DECOMPRESS = 0x05, ROP3_mask = 0xff << 16, ROP3_shift = 16, X_0X00 = 0x00, X_0X05 = 0x05, X_0X0A = 0x0a, X_0X0F = 0x0f, X_0X11 = 0x11, X_0X22 = 0x22, X_0X33 = 0x33, X_0X44 = 0x44, X_0X50 = 0x50, X_0X55 = 0x55, X_0X5A = 0x5a, X_0X5F = 0x5f, X_0X66 = 0x66, X_0X77 = 0x77, X_0X88 = 0x88, X_0X99 = 0x99, X_0XA0 = 0xa0, X_0XA5 = 0xa5, X_0XAA = 0xaa, X_0XAF = 0xaf, X_0XBB = 0xbb, X_0XCC = 0xcc, X_0XDD = 0xdd, X_0XEE = 0xee, X_0XF0 = 0xf0, X_0XF5 = 0xf5, X_0XFA = 0xfa, X_0XFF = 0xff, DB_SHADER_CONTROL = 0x0002880c, Z_EXPORT_ENABLE_bit = 1 << 0, STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, Z_ORDER_mask = 0x03 << 4, Z_ORDER_shift = 4, LATE_Z = 0x00, EARLY_Z_THEN_LATE_Z = 0x01, RE_Z = 0x02, EARLY_Z_THEN_RE_Z = 0x03, KILL_ENABLE_bit = 1 << 6, COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, MASK_EXPORT_ENABLE_bit = 1 << 8, DUAL_EXPORT_ENABLE_bit = 1 << 9, EXEC_ON_HIER_FAIL_bit = 1 << 10, EXEC_ON_NOOP_bit = 1 << 11, ALPHA_TO_MASK_DISABLE_bit = 1 << 12, DB_SOURCE_FORMAT_mask = 0x03 << 13, DB_SOURCE_FORMAT_shift = 13, EXPORT_DB_FULL = 0x00, EXPORT_DB_FOUR16 = 0x01, EXPORT_DB_TWO = 0x02, DEPTH_BEFORE_SHADER_bit = 1 << 15, CONSERVATIVE_Z_EXPORT_mask = 0x03 << 16, CONSERVATIVE_Z_EXPORT_shift = 16, EXPORT_ANY_Z = 0x00, EXPORT_LESS_THAN_Z = 0x01, EXPORT_GREATER_THAN_Z = 0x02, EXPORT_RESERVED = 0x03, PA_CL_CLIP_CNTL = 0x00028810, UCP_ENA_0_bit = 1 << 0, UCP_ENA_1_bit = 1 << 1, UCP_ENA_2_bit = 1 << 2, UCP_ENA_3_bit = 1 << 3, UCP_ENA_4_bit = 1 << 4, UCP_ENA_5_bit = 1 << 5, PS_UCP_Y_SCALE_NEG_bit = 1 << 13, PS_UCP_MODE_mask = 0x03 << 14, PS_UCP_MODE_shift = 14, CLIP_DISABLE_bit = 1 << 16, UCP_CULL_ONLY_ENA_bit = 1 << 17, BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, DX_CLIP_SPACE_DEF_bit = 1 << 19, DIS_CLIP_ERR_DETECT_bit = 1 << 20, VTX_KILL_OR_bit = 1 << 21, DX_RASTERIZATION_KILL_bit = 1 << 22, DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, ZCLIP_NEAR_DISABLE_bit = 1 << 26, ZCLIP_FAR_DISABLE_bit = 1 << 27, PA_SU_SC_MODE_CNTL = 0x00028814, CULL_FRONT_bit = 1 << 0, CULL_BACK_bit = 1 << 1, FACE_bit = 1 << 2, POLY_MODE_mask = 0x03 << 3, POLY_MODE_shift = 3, X_DISABLE_POLY_MODE = 0x00, X_DUAL_MODE = 0x01, POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, POLYMODE_FRONT_PTYPE_shift = 5, X_DRAW_POINTS = 0x00, X_DRAW_LINES = 0x01, X_DRAW_TRIANGLES = 0x02, POLYMODE_BACK_PTYPE_mask = 0x07 << 8, POLYMODE_BACK_PTYPE_shift = 8, /* X_DRAW_POINTS = 0x00, */ /* X_DRAW_LINES = 0x01, */ /* X_DRAW_TRIANGLES = 0x02, */ POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, PROVOKING_VTX_LAST_bit = 1 << 19, PERSP_CORR_DIS_bit = 1 << 20, MULTI_PRIM_IB_ENA_bit = 1 << 21, PA_CL_VTE_CNTL = 0x00028818, VPORT_X_SCALE_ENA_bit = 1 << 0, VPORT_X_OFFSET_ENA_bit = 1 << 1, VPORT_Y_SCALE_ENA_bit = 1 << 2, VPORT_Y_OFFSET_ENA_bit = 1 << 3, VPORT_Z_SCALE_ENA_bit = 1 << 4, VPORT_Z_OFFSET_ENA_bit = 1 << 5, VTX_XY_FMT_bit = 1 << 8, VTX_Z_FMT_bit = 1 << 9, VTX_W0_FMT_bit = 1 << 10, PA_CL_VS_OUT_CNTL = 0x0002881c, CLIP_DIST_ENA_0_bit = 1 << 0, CLIP_DIST_ENA_1_bit = 1 << 1, CLIP_DIST_ENA_2_bit = 1 << 2, CLIP_DIST_ENA_3_bit = 1 << 3, CLIP_DIST_ENA_4_bit = 1 << 4, CLIP_DIST_ENA_5_bit = 1 << 5, CLIP_DIST_ENA_6_bit = 1 << 6, CLIP_DIST_ENA_7_bit = 1 << 7, CULL_DIST_ENA_0_bit = 1 << 8, CULL_DIST_ENA_1_bit = 1 << 9, CULL_DIST_ENA_2_bit = 1 << 10, CULL_DIST_ENA_3_bit = 1 << 11, CULL_DIST_ENA_4_bit = 1 << 12, CULL_DIST_ENA_5_bit = 1 << 13, CULL_DIST_ENA_6_bit = 1 << 14, CULL_DIST_ENA_7_bit = 1 << 15, USE_VTX_POINT_SIZE_bit = 1 << 16, USE_VTX_EDGE_FLAG_bit = 1 << 17, USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, USE_VTX_VIEWPORT_INDX_bit = 1 << 19, USE_VTX_KILL_FLAG_bit = 1 << 20, VS_OUT_MISC_VEC_ENA_bit = 1 << 21, VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, PA_CL_NANINF_CNTL = 0x00028820, VTE_XY_INF_DISCARD_bit = 1 << 0, VTE_Z_INF_DISCARD_bit = 1 << 1, VTE_W_INF_DISCARD_bit = 1 << 2, VTE_0XNANINF_IS_0_bit = 1 << 3, VTE_XY_NAN_RETAIN_bit = 1 << 4, VTE_Z_NAN_RETAIN_bit = 1 << 5, VTE_W_NAN_RETAIN_bit = 1 << 6, VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, VS_XY_NAN_TO_INF_bit = 1 << 8, VS_XY_INF_RETAIN_bit = 1 << 9, VS_Z_NAN_TO_INF_bit = 1 << 10, VS_Z_INF_RETAIN_bit = 1 << 11, VS_W_NAN_TO_INF_bit = 1 << 12, VS_W_INF_RETAIN_bit = 1 << 13, VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, PA_SU_LINE_STIPPLE_CNTL = 0x00028824, LINE_STIPPLE_RESET_mask = 0x03 << 0, LINE_STIPPLE_RESET_shift = 0, EXPAND_FULL_LENGTH_bit = 1 << 2, FRACTIONAL_ACCUM_bit = 1 << 3, DIAMOND_ADJUST_bit = 1 << 4, PA_SU_LINE_STIPPLE_SCALE = 0x00028828, PA_SU_PRIM_FILTER_CNTL = 0x0002882c, TRIANGLE_FILTER_DISABLE_bit = 1 << 0, LINE_FILTER_DISABLE_bit = 1 << 1, POINT_FILTER_DISABLE_bit = 1 << 2, RECTANGLE_FILTER_DISABLE_bit = 1 << 3, TRIANGLE_EXPAND_ENA_bit = 1 << 4, LINE_EXPAND_ENA_bit = 1 << 5, POINT_EXPAND_ENA_bit = 1 << 6, RECTANGLE_EXPAND_ENA_bit = 1 << 7, PRIM_EXPAND_CONSTANT_mask = 0xff << 8, PRIM_EXPAND_CONSTANT_shift = 8, SQ_LSTMP_RING_ITEMSIZE = 0x00028830, ITEMSIZE_mask = 0x7fff << 0, ITEMSIZE_shift = 0, SQ_HSTMP_RING_ITEMSIZE = 0x00028834, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PGM_START_PS = 0x00028840, SQ_PGM_RESOURCES_PS = 0x00028844, NUM_GPRS_mask = 0xff << 0, NUM_GPRS_shift = 0, STACK_SIZE_mask = 0xff << 8, STACK_SIZE_shift = 8, DX10_CLAMP_bit = 1 << 21, UNCACHED_FIRST_INST_bit = 1 << 28, CLAMP_CONSTS_bit = 1 << 31, SQ_PGM_RESOURCES_2_PS = 0x00028848, SINGLE_ROUND_mask = 0x03 << 0, SINGLE_ROUND_shift = 0, SQ_ROUND_NEAREST_EVEN = 0x00, SQ_ROUND_PLUS_INFINITY = 0x01, SQ_ROUND_MINUS_INFINITY = 0x02, SQ_ROUND_TO_ZERO = 0x03, DOUBLE_ROUND_mask = 0x03 << 2, DOUBLE_ROUND_shift = 2, /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, SINGLE_IEEE_MODE_bit = 1 << 8, DOUBLE_IEEE_MODE_bit = 1 << 9, SQ_PGM_EXPORTS_PS = 0x0002884c, EXPORT_MODE_mask = 0x1f << 0, EXPORT_MODE_shift = 0, SQ_PGM_START_VS = 0x0002885c, SQ_PGM_RESOURCES_VS = 0x00028860, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ USE_LS_CONSTS_bit = 1 << 16, /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_VS = 0x00028864, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ /* SINGLE_IEEE_MODE_bit = 1 << 8, */ /* DOUBLE_IEEE_MODE_bit = 1 << 9, */ SQ_PGM_START_GS = 0x00028874, SQ_PGM_RESOURCES_GS = 0x00028878, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_GS = 0x0002887c, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ /* SINGLE_IEEE_MODE_bit = 1 << 8, */ /* DOUBLE_IEEE_MODE_bit = 1 << 9, */ SQ_PGM_START_ES = 0x0002888c, SQ_PGM_RESOURCES_ES = 0x00028890, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* USE_LS_CONSTS_bit = 1 << 16, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_ES = 0x00028894, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ /* SINGLE_IEEE_MODE_bit = 1 << 8, */ /* DOUBLE_IEEE_MODE_bit = 1 << 9, */ SQ_PGM_START_FS = 0x000288a4, SQ_PGM_RESOURCES_FS = 0x000288a8, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ SQ_PGM_START_HS = 0x000288b8, SQ_PGM_RESOURCES_HS = 0x000288bc, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_HS = 0x000288c0, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ /* SINGLE_IEEE_MODE_bit = 1 << 8, */ /* DOUBLE_IEEE_MODE_bit = 1 << 9, */ SQ_PGM_START_LS = 0x000288d0, SQ_PGM_RESOURCES_LS = 0x000288d4, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ USE_VS_CONSTS_bit = 1 << 16, /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_LS = 0x000288d8, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ /* SINGLE_IEEE_MODE_bit = 1 << 8, */ /* DOUBLE_IEEE_MODE_bit = 1 << 9, */ SQ_VTX_SEMANTIC_CLEAR = 0x000288f0, SQ_ESGS_RING_ITEMSIZE = 0x00028900, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSVS_RING_ITEMSIZE = 0x00028904, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_ESTMP_RING_ITEMSIZE = 0x00028908, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSTMP_RING_ITEMSIZE = 0x0002890c, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_VSTMP_RING_ITEMSIZE = 0x00028910, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PSTMP_RING_ITEMSIZE = 0x00028914, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE = 0x0002891c, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_1 = 0x00028920, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_2 = 0x00028924, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_3 = 0x00028928, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSVS_RING_OFFSET_1 = 0x0002892c, SQ_GSVS_RING_OFFSET_1__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_1__OFFSET_shift = 0, SQ_GSVS_RING_OFFSET_2 = 0x00028930, SQ_GSVS_RING_OFFSET_2__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_2__OFFSET_shift = 0, SQ_GSVS_RING_OFFSET_3 = 0x00028934, SQ_GSVS_RING_OFFSET_3__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_3__OFFSET_shift = 0, SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, SQ_ALU_CONST_CACHE_PS_0_num = 16, SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, SQ_ALU_CONST_CACHE_VS_0_num = 16, SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, SQ_ALU_CONST_CACHE_GS_0_num = 16, PA_SU_POINT_SIZE = 0x00028a00, HEIGHT_mask = 0xffff << 0, HEIGHT_shift = 0, PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, PA_SU_POINT_SIZE__WIDTH_shift = 16, PA_SU_POINT_MINMAX = 0x00028a04, MIN_SIZE_mask = 0xffff << 0, MIN_SIZE_shift = 0, PA_SU_POINT_MINMAX__MAX_SIZE_mask = 0xffff << 16, PA_SU_POINT_MINMAX__MAX_SIZE_shift = 16, PA_SU_LINE_CNTL = 0x00028a08, PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, PA_SU_LINE_CNTL__WIDTH_shift = 0, PA_SC_LINE_STIPPLE = 0x00028a0c, LINE_PATTERN_mask = 0xffff << 0, LINE_PATTERN_shift = 0, REPEAT_COUNT_mask = 0xff << 16, REPEAT_COUNT_shift = 16, PATTERN_BIT_ORDER_bit = 1 << 28, AUTO_RESET_CNTL_mask = 0x03 << 29, AUTO_RESET_CNTL_shift = 29, VGT_OUTPUT_PATH_CNTL = 0x00028a10, PATH_SELECT_mask = 0x07 << 0, PATH_SELECT_shift = 0, VGT_OUTPATH_VTX_REUSE = 0x00, VGT_OUTPATH_TESS_EN = 0x01, VGT_OUTPATH_PASSTHRU = 0x02, VGT_OUTPATH_GS_BLOCK = 0x03, VGT_OUTPATH_HS_BLOCK = 0x04, VGT_HOS_CNTL = 0x00028a14, TESS_MODE_mask = 0x03 << 0, TESS_MODE_shift = 0, VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, VGT_HOS_REUSE_DEPTH = 0x00028a20, REUSE_DEPTH_mask = 0xff << 0, REUSE_DEPTH_shift = 0, VGT_GROUP_PRIM_TYPE = 0x00028a24, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, VGT_GRP_3D_POINT = 0x00, VGT_GRP_3D_LINE = 0x01, VGT_GRP_3D_TRI = 0x02, VGT_GRP_3D_RECT = 0x03, VGT_GRP_3D_QUAD = 0x04, VGT_GRP_2D_COPY_RECT_V0 = 0x05, VGT_GRP_2D_COPY_RECT_V1 = 0x06, VGT_GRP_2D_COPY_RECT_V2 = 0x07, VGT_GRP_2D_COPY_RECT_V3 = 0x08, VGT_GRP_2D_FILL_RECT = 0x09, VGT_GRP_2D_LINE = 0x0a, VGT_GRP_2D_TRI = 0x0b, VGT_GRP_PRIM_INDEX_LINE = 0x0c, VGT_GRP_PRIM_INDEX_TRI = 0x0d, VGT_GRP_PRIM_INDEX_QUAD = 0x0e, VGT_GRP_3D_LINE_ADJ = 0x0f, VGT_GRP_3D_TRI_ADJ = 0x10, VGT_GRP_3D_PATCH = 0x11, RETAIN_ORDER_bit = 1 << 14, RETAIN_QUADS_bit = 1 << 15, PRIM_ORDER_mask = 0x07 << 16, PRIM_ORDER_shift = 16, VGT_GRP_LIST = 0x00, VGT_GRP_STRIP = 0x01, VGT_GRP_FAN = 0x02, VGT_GRP_LOOP = 0x03, VGT_GRP_POLYGON = 0x04, VGT_GROUP_FIRST_DECR = 0x00028a28, FIRST_DECR_mask = 0x0f << 0, FIRST_DECR_shift = 0, VGT_GROUP_DECR = 0x00028a2c, DECR_mask = 0x0f << 0, DECR_shift = 0, VGT_GROUP_VECT_0_CNTL = 0x00028a30, COMP_X_EN_bit = 1 << 0, COMP_Y_EN_bit = 1 << 1, COMP_Z_EN_bit = 1 << 2, COMP_W_EN_bit = 1 << 3, VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, SHIFT_mask = 0xff << 16, SHIFT_shift = 16, VGT_GROUP_VECT_1_CNTL = 0x00028a34, /* COMP_X_EN_bit = 1 << 0, */ /* COMP_Y_EN_bit = 1 << 1, */ /* COMP_Z_EN_bit = 1 << 2, */ /* COMP_W_EN_bit = 1 << 3, */ VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, /* SHIFT_mask = 0xff << 16, */ /* SHIFT_shift = 16, */ VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, X_CONV_mask = 0x0f << 0, X_CONV_shift = 0, VGT_GRP_INDEX_16 = 0x00, VGT_GRP_INDEX_32 = 0x01, VGT_GRP_UINT_16 = 0x02, VGT_GRP_UINT_32 = 0x03, VGT_GRP_SINT_16 = 0x04, VGT_GRP_SINT_32 = 0x05, VGT_GRP_FLOAT_32 = 0x06, VGT_GRP_AUTO_PRIM = 0x07, VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, X_OFFSET_mask = 0x0f << 4, X_OFFSET_shift = 4, Y_CONV_mask = 0x0f << 8, Y_CONV_shift = 8, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Y_OFFSET_mask = 0x0f << 12, Y_OFFSET_shift = 12, Z_CONV_mask = 0x0f << 16, Z_CONV_shift = 16, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Z_OFFSET_mask = 0x0f << 20, Z_OFFSET_shift = 20, W_CONV_mask = 0x0f << 24, W_CONV_shift = 24, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ W_OFFSET_mask = 0x0f << 28, W_OFFSET_shift = 28, VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, /* X_CONV_mask = 0x0f << 0, */ /* X_CONV_shift = 0, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* X_OFFSET_mask = 0x0f << 4, */ /* X_OFFSET_shift = 4, */ /* Y_CONV_mask = 0x0f << 8, */ /* Y_CONV_shift = 8, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Y_OFFSET_mask = 0x0f << 12, */ /* Y_OFFSET_shift = 12, */ /* Z_CONV_mask = 0x0f << 16, */ /* Z_CONV_shift = 16, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Z_OFFSET_mask = 0x0f << 20, */ /* Z_OFFSET_shift = 20, */ /* W_CONV_mask = 0x0f << 24, */ /* W_CONV_shift = 24, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* W_OFFSET_mask = 0x0f << 28, */ /* W_OFFSET_shift = 28, */ VGT_GS_MODE = 0x00028a40, VGT_GS_MODE__MODE_mask = 0x03 << 0, VGT_GS_MODE__MODE_shift = 0, GS_OFF = 0x00, GS_SCENARIO_A = 0x01, GS_SCENARIO_B = 0x02, GS_SCENARIO_G = 0x03, GS_SCENARIO_C = 0x04, SPRITE_EN = 0x05, ES_PASSTHRU_bit = 1 << 2, CUT_MODE_mask = 0x03 << 3, CUT_MODE_shift = 3, GS_CUT_1024 = 0x00, GS_CUT_512 = 0x01, GS_CUT_256 = 0x02, GS_CUT_128 = 0x03, MODE_HI_bit = 1 << 8, PA_SC_MODE_CNTL_0 = 0x00028a48, MSAA_ENABLE_bit = 1 << 0, VPORT_SCISSOR_ENABLE_bit = 1 << 1, LINE_STIPPLE_ENABLE_bit = 1 << 2, VGT_ENHANCE = 0x00028a50, VGT_GS_PER_ES = 0x00028a54, GS_PER_ES_mask = 0x7ff << 0, GS_PER_ES_shift = 0, VGT_ES_PER_GS = 0x00028a58, ES_PER_GS_mask = 0x7ff << 0, ES_PER_GS_shift = 0, VGT_GS_PER_VS = 0x00028a5c, GS_PER_VS_mask = 0x0f << 0, GS_PER_VS_shift = 0, VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, OUTPRIM_TYPE_mask = 0x3f << 0, OUTPRIM_TYPE_shift = 0, POINTLIST = 0x00, LINESTRIP = 0x01, TRISTRIP = 0x02, VGT_DMA_SIZE = 0x00028a74, VGT_DMA_MAX_SIZE = 0x00028a78, VGT_DMA_INDEX_TYPE = 0x00028a7c, /* INDEX_TYPE_mask = 0x03 << 0, */ /* INDEX_TYPE_shift = 0, */ VGT_INDEX_16 = 0x00, VGT_INDEX_32 = 0x01, SWAP_MODE_mask = 0x03 << 2, SWAP_MODE_shift = 2, VGT_DMA_SWAP_NONE = 0x00, VGT_DMA_SWAP_16_BIT = 0x01, VGT_DMA_SWAP_32_BIT = 0x02, VGT_DMA_SWAP_WORD = 0x03, VGT_PRIMITIVEID_EN = 0x00028a84, PRIMITIVEID_EN_bit = 1 << 0, VGT_DMA_NUM_INSTANCES = 0x00028a88, VGT_EVENT_INITIATOR = 0x00028a90, EVENT_TYPE_mask = 0x3f << 0, EVENT_TYPE_shift = 0, SAMPLE_STREAMOUTSTATS1 = 0x01, SAMPLE_STREAMOUTSTATS2 = 0x02, SAMPLE_STREAMOUTSTATS3 = 0x03, CACHE_FLUSH_TS = 0x04, CONTEXT_DONE = 0x05, CACHE_FLUSH = 0x06, CS_PARTIAL_FLUSH = 0x07, VGT_STREAMOUT_SYNC = 0x08, RST_PIX_CNT = 0x0d, VS_PARTIAL_FLUSH = 0x0f, PS_PARTIAL_FLUSH = 0x10, FLUSH_HS_OUTPUT = 0x11, FLUSH_LS_OUTPUT = 0x12, CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, ZPASS_DONE = 0x15, CACHE_FLUSH_AND_INV_EVENT = 0x16, PERFCOUNTER_START = 0x17, PERFCOUNTER_STOP = 0x18, PIPELINESTAT_START = 0x19, PIPELINESTAT_STOP = 0x1a, PERFCOUNTER_SAMPLE = 0x1b, FLUSH_ES_OUTPUT = 0x1c, FLUSH_GS_OUTPUT = 0x1d, SAMPLE_PIPELINESTAT = 0x1e, SO_VGTSTREAMOUT_FLUSH = 0x1f, SAMPLE_STREAMOUTSTATS = 0x20, RESET_VTX_CNT = 0x21, BLOCK_CONTEXT_DONE = 0x22, CS_CONTEXT_DONE = 0x23, VGT_FLUSH = 0x24, SQ_NON_EVENT = 0x26, SC_SEND_DB_VPZ = 0x27, BOTTOM_OF_PIPE_TS = 0x28, FLUSH_SX_TS = 0x29, DB_CACHE_FLUSH_AND_INV = 0x2a, FLUSH_AND_INV_DB_DATA_TS = 0x2b, FLUSH_AND_INV_DB_META = 0x2c, FLUSH_AND_INV_CB_DATA_TS = 0x2d, FLUSH_AND_INV_CB_META = 0x2e, CS_DONE = 0x2f, PS_DONE = 0x30, FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, SX_CB_RAT_ACK_REQUEST = 0x32, ADDRESS_HI_mask = 0x1ff << 18, ADDRESS_HI_shift = 18, EXTENDED_EVENT_bit = 1 << 27, VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, RESET_EN_bit = 1 << 0, VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, VGT_REUSE_OFF = 0x00028ab4, REUSE_OFF_bit = 1 << 0, VGT_VTX_CNT_EN = 0x00028ab8, VTX_CNT_EN_bit = 1 << 0, DB_HTILE_SURFACE = 0x00028abc, HTILE_WIDTH_bit = 1 << 0, HTILE_HEIGHT_bit = 1 << 1, LINEAR_bit = 1 << 2, FULL_CACHE_bit = 1 << 3, HTILE_USES_PRELOAD_WIN_bit = 1 << 4, PRELOAD_bit = 1 << 5, PREFETCH_WIDTH_mask = 0x3f << 6, PREFETCH_WIDTH_shift = 6, PREFETCH_HEIGHT_mask = 0x3f << 12, PREFETCH_HEIGHT_shift = 12, DB_SRESULTS_COMPARE_STATE0 = 0x00028ac0, COMPAREFUNC0_mask = 0x07 << 0, COMPAREFUNC0_shift = 0, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ COMPAREVALUE0_mask = 0xff << 4, COMPAREVALUE0_shift = 4, COMPAREMASK0_mask = 0xff << 12, COMPAREMASK0_shift = 12, ENABLE0_bit = 1 << 24, DB_SRESULTS_COMPARE_STATE1 = 0x00028ac4, COMPAREFUNC1_mask = 0x07 << 0, COMPAREFUNC1_shift = 0, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ COMPAREVALUE1_mask = 0xff << 4, COMPAREVALUE1_shift = 4, COMPAREMASK1_mask = 0xff << 12, COMPAREMASK1_shift = 12, ENABLE1_bit = 1 << 24, DB_PRELOAD_CONTROL = 0x00028ac8, START_X_mask = 0xff << 0, START_X_shift = 0, START_Y_mask = 0xff << 8, START_Y_shift = 8, MAX_X_mask = 0xff << 16, MAX_X_shift = 16, MAX_Y_mask = 0xff << 24, MAX_Y_shift = 24, VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, VERTEX_STRIDE_mask = 0x1ff << 0, VERTEX_STRIDE_shift = 0, VGT_GS_MAX_VERT_OUT = 0x00028b38, MAX_VERT_OUT_mask = 0x7ff << 0, MAX_VERT_OUT_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, VGT_SHADER_STAGES_EN = 0x00028b54, LS_EN_mask = 0x03 << 0, LS_EN_shift = 0, LS_STAGE_OFF = 0x00, LS_STAGE_ON = 0x01, CS_STAGE_ON = 0x02, HS_EN_bit = 1 << 2, ES_EN_mask = 0x03 << 3, ES_EN_shift = 3, ES_STAGE_OFF = 0x00, ES_STAGE_DS = 0x01, ES_STAGE_REAL = 0x02, GS_EN_bit = 1 << 5, VS_EN_mask = 0x03 << 6, VS_EN_shift = 6, VS_STAGE_REAL = 0x00, VS_STAGE_DS = 0x01, VS_STAGE_COPY_SHADER = 0x02, DYNAMIC_HS_bit = 1 << 8, VGT_LS_HS_CONFIG = 0x00028b58, NUM_PATCHES_mask = 0xff << 0, NUM_PATCHES_shift = 0, HS_NUM_INPUT_CP_mask = 0x3f << 8, HS_NUM_INPUT_CP_shift = 8, HS_NUM_OUTPUT_CP_mask = 0x3f << 14, HS_NUM_OUTPUT_CP_shift = 14, DB_ALPHA_TO_MASK = 0x00028b70, ALPHA_TO_MASK_ENABLE_bit = 1 << 0, ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, ALPHA_TO_MASK_OFFSET0_shift = 8, ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, ALPHA_TO_MASK_OFFSET1_shift = 10, ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, ALPHA_TO_MASK_OFFSET2_shift = 12, ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, ALPHA_TO_MASK_OFFSET3_shift = 14, OFFSET_ROUND_bit = 1 << 16, PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028b78, POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, PA_SU_POLY_OFFSET_CLAMP = 0x00028b7c, PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028b80, PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028b84, PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028b88, PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028b8c, VGT_GS_INSTANCE_CNT = 0x00028b90, VGT_GS_INSTANCE_CNT__ENABLE_bit = 1 << 0, CNT_mask = 0x7f << 2, CNT_shift = 2, VGT_STRMOUT_CONFIG = 0x00028b94, STREAMOUT_0_EN_bit = 1 << 0, STREAMOUT_1_EN_bit = 1 << 1, STREAMOUT_2_EN_bit = 1 << 2, STREAMOUT_3_EN_bit = 1 << 3, RAST_STREAM_mask = 0x07 << 4, RAST_STREAM_shift = 4, VGT_STRMOUT_BUFFER_CONFIG = 0x00028b98, STREAM_0_BUFFER_EN_mask = 0x0f << 0, STREAM_0_BUFFER_EN_shift = 0, STREAM_1_BUFFER_EN_mask = 0x0f << 4, STREAM_1_BUFFER_EN_shift = 4, STREAM_2_BUFFER_EN_mask = 0x0f << 8, STREAM_2_BUFFER_EN_shift = 8, STREAM_3_BUFFER_EN_mask = 0x0f << 12, STREAM_3_BUFFER_EN_shift = 12, CB_IMMED0_BASE = 0x00028b9c, CB_IMMED0_BASE_num = 12, PA_SC_CENTROID_PRIORITY_0 = 0x00028bd4, DISTANCE_0_mask = 0x0f << 0, DISTANCE_0_shift = 0, DISTANCE_1_mask = 0x0f << 4, DISTANCE_1_shift = 4, DISTANCE_2_mask = 0x0f << 8, DISTANCE_2_shift = 8, DISTANCE_3_mask = 0x0f << 12, DISTANCE_3_shift = 12, DISTANCE_4_mask = 0x0f << 16, DISTANCE_4_shift = 16, DISTANCE_5_mask = 0x0f << 20, DISTANCE_5_shift = 20, DISTANCE_6_mask = 0x0f << 24, DISTANCE_6_shift = 24, DISTANCE_7_mask = 0x0f << 28, DISTANCE_7_shift = 28, PA_SC_CENTROID_PRIORITY_1 = 0x00028bd8, DISTANCE_8_mask = 0x0f << 0, DISTANCE_8_shift = 0, DISTANCE_9_mask = 0x0f << 4, DISTANCE_9_shift = 4, DISTANCE_10_mask = 0x0f << 8, DISTANCE_10_shift = 8, DISTANCE_11_mask = 0x0f << 12, DISTANCE_11_shift = 12, DISTANCE_12_mask = 0x0f << 16, DISTANCE_12_shift = 16, DISTANCE_13_mask = 0x0f << 20, DISTANCE_13_shift = 20, DISTANCE_14_mask = 0x0f << 24, DISTANCE_14_shift = 24, DISTANCE_15_mask = 0x0f << 28, DISTANCE_15_shift = 28, PA_SC_LINE_CNTL = 0x00028bdc, EXPAND_LINE_WIDTH_bit = 1 << 9, LAST_PIXEL_bit = 1 << 10, PERPENDICULAR_ENDCAP_ENA_bit = 1 << 11, DX10_DIAMOND_TEST_ENA_bit = 1 << 12, PA_SC_AA_CONFIG = 0x00028be0, MSAA_NUM_SAMPLES_mask = 0x07 << 0, MSAA_NUM_SAMPLES_shift = 0, AA_MASK_CENTROID_DTMN_bit = 1 << 4, MAX_SAMPLE_DIST_mask = 0x0f << 13, MAX_SAMPLE_DIST_shift = 13, MSAA_EXPOSED_SAMPLES_mask = 0x07 << 20, MSAA_EXPOSED_SAMPLES_shift = 20, DETAIL_TO_EXPOSED_MODE_mask = 0x03 << 24, DETAIL_TO_EXPOSED_MODE_shift = 24, PA_SU_VTX_CNTL = 0x00028be4, PIX_CENTER_bit = 1 << 0, PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, X_TRUNCATE = 0x00, X_ROUND = 0x01, X_ROUND_TO_EVEN = 0x02, X_ROUND_TO_ODD = 0x03, QUANT_MODE_mask = 0x07 << 3, QUANT_MODE_shift = 3, X_1_16TH = 0x00, X_1_8TH = 0x01, X_1_4TH = 0x02, X_1_2 = 0x03, QUANT_MODE__X_1 = 0x04, X_1_256TH = 0x05, X_1_1024TH = 0x06, X_1_4096TH = 0x07, PA_CL_GB_VERT_CLIP_ADJ = 0x00028be8, PA_CL_GB_HORZ_CLIP_ADJ = 0x00028bf0, PA_CL_GB_HORZ_DISC_ADJ = 0x00028bf4, PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x00028bf8, S0_X_mask = 0x0f << 0, S0_X_shift = 0, S0_Y_mask = 0x0f << 4, S0_Y_shift = 4, S1_X_mask = 0x0f << 8, S1_X_shift = 8, S1_Y_mask = 0x0f << 12, S1_Y_shift = 12, S2_X_mask = 0x0f << 16, S2_X_shift = 16, S2_Y_mask = 0x0f << 20, S2_Y_shift = 20, S3_X_mask = 0x0f << 24, S3_X_shift = 24, S3_Y_mask = 0x0f << 28, S3_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x00028bfc, S4_X_mask = 0x0f << 0, S4_X_shift = 0, S4_Y_mask = 0x0f << 4, S4_Y_shift = 4, S5_X_mask = 0x0f << 8, S5_X_shift = 8, S5_Y_mask = 0x0f << 12, S5_Y_shift = 12, S6_X_mask = 0x0f << 16, S6_X_shift = 16, S6_Y_mask = 0x0f << 20, S6_Y_shift = 20, S7_X_mask = 0x0f << 24, S7_X_shift = 24, S7_Y_mask = 0x0f << 28, S7_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x00028c00, S8_X_mask = 0x0f << 0, S8_X_shift = 0, S8_Y_mask = 0x0f << 4, S8_Y_shift = 4, S9_X_mask = 0x0f << 8, S9_X_shift = 8, S9_Y_mask = 0x0f << 12, S9_Y_shift = 12, S10_X_mask = 0x0f << 16, S10_X_shift = 16, S10_Y_mask = 0x0f << 20, S10_Y_shift = 20, S11_X_mask = 0x0f << 24, S11_X_shift = 24, S11_Y_mask = 0x0f << 28, S11_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x00028c04, S12_X_mask = 0x0f << 0, S12_X_shift = 0, S12_Y_mask = 0x0f << 4, S12_Y_shift = 4, S13_X_mask = 0x0f << 8, S13_X_shift = 8, S13_Y_mask = 0x0f << 12, S13_Y_shift = 12, S14_X_mask = 0x0f << 16, S14_X_shift = 16, S14_Y_mask = 0x0f << 20, S14_Y_shift = 20, S15_X_mask = 0x0f << 24, S15_X_shift = 24, S15_Y_mask = 0x0f << 28, S15_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x00028c08, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x00028c0c, /* S4_X_mask = 0x0f << 0, */ /* S4_X_shift = 0, */ /* S4_Y_mask = 0x0f << 4, */ /* S4_Y_shift = 4, */ /* S5_X_mask = 0x0f << 8, */ /* S5_X_shift = 8, */ /* S5_Y_mask = 0x0f << 12, */ /* S5_Y_shift = 12, */ /* S6_X_mask = 0x0f << 16, */ /* S6_X_shift = 16, */ /* S6_Y_mask = 0x0f << 20, */ /* S6_Y_shift = 20, */ /* S7_X_mask = 0x0f << 24, */ /* S7_X_shift = 24, */ /* S7_Y_mask = 0x0f << 28, */ /* S7_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x00028c10, /* S8_X_mask = 0x0f << 0, */ /* S8_X_shift = 0, */ /* S8_Y_mask = 0x0f << 4, */ /* S8_Y_shift = 4, */ /* S9_X_mask = 0x0f << 8, */ /* S9_X_shift = 8, */ /* S9_Y_mask = 0x0f << 12, */ /* S9_Y_shift = 12, */ /* S10_X_mask = 0x0f << 16, */ /* S10_X_shift = 16, */ /* S10_Y_mask = 0x0f << 20, */ /* S10_Y_shift = 20, */ /* S11_X_mask = 0x0f << 24, */ /* S11_X_shift = 24, */ /* S11_Y_mask = 0x0f << 28, */ /* S11_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x00028c14, /* S12_X_mask = 0x0f << 0, */ /* S12_X_shift = 0, */ /* S12_Y_mask = 0x0f << 4, */ /* S12_Y_shift = 4, */ /* S13_X_mask = 0x0f << 8, */ /* S13_X_shift = 8, */ /* S13_Y_mask = 0x0f << 12, */ /* S13_Y_shift = 12, */ /* S14_X_mask = 0x0f << 16, */ /* S14_X_shift = 16, */ /* S14_Y_mask = 0x0f << 20, */ /* S14_Y_shift = 20, */ /* S15_X_mask = 0x0f << 24, */ /* S15_X_shift = 24, */ /* S15_Y_mask = 0x0f << 28, */ /* S15_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x00028c18, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x00028c1c, /* S4_X_mask = 0x0f << 0, */ /* S4_X_shift = 0, */ /* S4_Y_mask = 0x0f << 4, */ /* S4_Y_shift = 4, */ /* S5_X_mask = 0x0f << 8, */ /* S5_X_shift = 8, */ /* S5_Y_mask = 0x0f << 12, */ /* S5_Y_shift = 12, */ /* S6_X_mask = 0x0f << 16, */ /* S6_X_shift = 16, */ /* S6_Y_mask = 0x0f << 20, */ /* S6_Y_shift = 20, */ /* S7_X_mask = 0x0f << 24, */ /* S7_X_shift = 24, */ /* S7_Y_mask = 0x0f << 28, */ /* S7_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x00028c20, /* S8_X_mask = 0x0f << 0, */ /* S8_X_shift = 0, */ /* S8_Y_mask = 0x0f << 4, */ /* S8_Y_shift = 4, */ /* S9_X_mask = 0x0f << 8, */ /* S9_X_shift = 8, */ /* S9_Y_mask = 0x0f << 12, */ /* S9_Y_shift = 12, */ /* S10_X_mask = 0x0f << 16, */ /* S10_X_shift = 16, */ /* S10_Y_mask = 0x0f << 20, */ /* S10_Y_shift = 20, */ /* S11_X_mask = 0x0f << 24, */ /* S11_X_shift = 24, */ /* S11_Y_mask = 0x0f << 28, */ /* S11_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x00028c24, /* S12_X_mask = 0x0f << 0, */ /* S12_X_shift = 0, */ /* S12_Y_mask = 0x0f << 4, */ /* S12_Y_shift = 4, */ /* S13_X_mask = 0x0f << 8, */ /* S13_X_shift = 8, */ /* S13_Y_mask = 0x0f << 12, */ /* S13_Y_shift = 12, */ /* S14_X_mask = 0x0f << 16, */ /* S14_X_shift = 16, */ /* S14_Y_mask = 0x0f << 20, */ /* S14_Y_shift = 20, */ /* S15_X_mask = 0x0f << 24, */ /* S15_X_shift = 24, */ /* S15_Y_mask = 0x0f << 28, */ /* S15_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x00028c28, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x00028c2c, /* S4_X_mask = 0x0f << 0, */ /* S4_X_shift = 0, */ /* S4_Y_mask = 0x0f << 4, */ /* S4_Y_shift = 4, */ /* S5_X_mask = 0x0f << 8, */ /* S5_X_shift = 8, */ /* S5_Y_mask = 0x0f << 12, */ /* S5_Y_shift = 12, */ /* S6_X_mask = 0x0f << 16, */ /* S6_X_shift = 16, */ /* S6_Y_mask = 0x0f << 20, */ /* S6_Y_shift = 20, */ /* S7_X_mask = 0x0f << 24, */ /* S7_X_shift = 24, */ /* S7_Y_mask = 0x0f << 28, */ /* S7_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x00028c30, /* S8_X_mask = 0x0f << 0, */ /* S8_X_shift = 0, */ /* S8_Y_mask = 0x0f << 4, */ /* S8_Y_shift = 4, */ /* S9_X_mask = 0x0f << 8, */ /* S9_X_shift = 8, */ /* S9_Y_mask = 0x0f << 12, */ /* S9_Y_shift = 12, */ /* S10_X_mask = 0x0f << 16, */ /* S10_X_shift = 16, */ /* S10_Y_mask = 0x0f << 20, */ /* S10_Y_shift = 20, */ /* S11_X_mask = 0x0f << 24, */ /* S11_X_shift = 24, */ /* S11_Y_mask = 0x0f << 28, */ /* S11_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x00028c34, /* S12_X_mask = 0x0f << 0, */ /* S12_X_shift = 0, */ /* S12_Y_mask = 0x0f << 4, */ /* S12_Y_shift = 4, */ /* S13_X_mask = 0x0f << 8, */ /* S13_X_shift = 8, */ /* S13_Y_mask = 0x0f << 12, */ /* S13_Y_shift = 12, */ /* S14_X_mask = 0x0f << 16, */ /* S14_X_shift = 16, */ /* S14_Y_mask = 0x0f << 20, */ /* S14_Y_shift = 20, */ /* S15_X_mask = 0x0f << 24, */ /* S15_X_shift = 24, */ /* S15_Y_mask = 0x0f << 28, */ /* S15_Y_shift = 28, */ PA_SC_AA_MASK_X0Y0_X1Y0 = 0x00028c38, AA_MASK_X0Y0_mask = 0xffff << 0, AA_MASK_X0Y0_shift = 0, AA_MASK_X1Y0_mask = 0xffff << 16, AA_MASK_X1Y0_shift = 16, PA_SC_AA_MASK_X0Y1_X1Y1 = 0x00028c3c, AA_MASK_X0Y1_mask = 0xffff << 0, AA_MASK_X0Y1_shift = 0, AA_MASK_X1Y1_mask = 0xffff << 16, AA_MASK_X1Y1_shift = 16, VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, VTX_REUSE_DEPTH_mask = 0xff << 0, VTX_REUSE_DEPTH_shift = 0, VGT_OUT_DEALLOC_CNTL = 0x00028c5c, DEALLOC_DIST_mask = 0x7f << 0, DEALLOC_DIST_shift = 0, CB_COLOR0_BASE = 0x00028c60, CB_COLOR0_BASE_num = 12, CB_COLOR0_BASE_offset = 51, CB_COLOR0_PITCH = 0x00028c64, CB_COLOR0_PITCH_num = 12, CB_COLOR0_PITCH_offset = 51, CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff << 0, CB_COLOR0_PITCH__TILE_MAX_shift = 0, CB_COLOR0_SLICE = 0x00028c68, CB_COLOR0_SLICE_num = 12, CB_COLOR0_SLICE_offset = 51, CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff << 0, CB_COLOR0_SLICE__TILE_MAX_shift = 0, CB_COLOR0_VIEW = 0x00028c6c, CB_COLOR0_VIEW_num = 12, CB_COLOR0_VIEW_offset = 51, /* SLICE_START_mask = 0x7ff << 0, */ /* SLICE_START_shift = 0, */ /* SLICE_MAX_mask = 0x7ff << 13, */ /* SLICE_MAX_shift = 13, */ CB_COLOR0_INFO = 0x00028c70, CB_COLOR0_INFO_num = 12, CB_COLOR0_INFO_offset = 51, ENDIAN_mask = 0x03 << 0, ENDIAN_shift = 0, ENDIAN_NONE = 0x00, ENDIAN_8IN16 = 0x01, ENDIAN_8IN32 = 0x02, ENDIAN_8IN64 = 0x03, CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, CB_COLOR0_INFO__FORMAT_shift = 2, COLOR_INVALID = 0x00, COLOR_8 = 0x01, COLOR_16 = 0x05, COLOR_16_FLOAT = 0x06, COLOR_8_8 = 0x07, COLOR_5_6_5 = 0x08, COLOR_1_5_5_5 = 0x0a, COLOR_4_4_4_4 = 0x0b, COLOR_5_5_5_1 = 0x0c, COLOR_32 = 0x0d, COLOR_32_FLOAT = 0x0e, COLOR_16_16 = 0x0f, COLOR_16_16_FLOAT = 0x10, COLOR_8_24 = 0x11, COLOR_24_8 = 0x13, COLOR_10_11_11 = 0x15, COLOR_10_11_11_FLOAT = 0x16, COLOR_2_10_10_10 = 0x19, COLOR_8_8_8_8 = 0x1a, COLOR_10_10_10_2 = 0x1b, COLOR_X24_8_32_FLOAT = 0x1c, COLOR_32_32 = 0x1d, COLOR_32_32_FLOAT = 0x1e, COLOR_16_16_16_16 = 0x1f, COLOR_16_16_16_16_FLOAT = 0x20, COLOR_32_32_32_32 = 0x22, COLOR_32_32_32_32_FLOAT = 0x23, CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, CB_COLOR0_INFO__ARRAY_MODE_shift = 8, ARRAY_LINEAR_GENERAL = 0x00, ARRAY_LINEAR_ALIGNED = 0x01, /* ARRAY_1D_TILED_THIN1 = 0x02, */ /* ARRAY_2D_TILED_THIN1 = 0x04, */ NUMBER_TYPE_mask = 0x07 << 12, NUMBER_TYPE_shift = 12, NUMBER_UNORM = 0x00, NUMBER_SNORM = 0x01, NUMBER_UINT = 0x04, NUMBER_SINT = 0x05, NUMBER_SRGB = 0x06, NUMBER_FLOAT = 0x07, COMP_SWAP_mask = 0x03 << 15, COMP_SWAP_shift = 15, SWAP_STD = 0x00, SWAP_ALT = 0x01, SWAP_STD_REV = 0x02, SWAP_ALT_REV = 0x03, FAST_CLEAR_bit = 1 << 17, COMPRESSION_bit = 1 << 18, BLEND_CLAMP_bit = 1 << 19, BLEND_BYPASS_bit = 1 << 20, SIMPLE_FLOAT_bit = 1 << 21, CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22, TILE_COMPACT_bit = 1 << 23, SOURCE_FORMAT_mask = 0x03 << 24, SOURCE_FORMAT_shift = 24, EXPORT_4C_32BPC = 0x00, EXPORT_4C_16BPC = 0x01, EXPORT_2C_32BPC_GR = 0x02, EXPORT_2C_32BPC_AR = 0x03, RAT_bit = 1 << 26, RESOURCE_TYPE_mask = 0x07 << 27, RESOURCE_TYPE_shift = 27, BUFFER = 0x00, TEXTURE1D = 0x01, TEXTURE1DARRAY = 0x02, TEXTURE2D = 0x03, TEXTURE2DARRAY = 0x04, TEXTURE3D = 0x05, STRUCTUREDBUFFER = 0x06, SOURCE_NUMBER_TYPE_mask = 0x03 << 30, SOURCE_NUMBER_TYPE_shift = 30, EXPORT_FLOAT = 0x00, EXPORT_INT = 0x01, EXPORT_UNORM = 0x02, EXPORT_SNORM = 0x03, CB_COLOR0_ATTRIB = 0x00028c74, CB_COLOR0_ATTRIB_num = 12, CB_COLOR0_ATTRIB_offset = 51, IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4, CB_COLOR0_ATTRIB__TILE_SPLIT_mask = 0x0f << 5, CB_COLOR0_ATTRIB__TILE_SPLIT_shift = 5, /* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ /* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ /* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ /* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ /* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ /* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ /* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ CB_COLOR0_ATTRIB__NUM_BANKS_mask = 0x03 << 10, CB_COLOR0_ATTRIB__NUM_BANKS_shift = 10, /* ADDR_SURF_2_BANK = 0x00, */ /* ADDR_SURF_4_BANK = 0x01, */ /* ADDR_SURF_8_BANK = 0x02, */ /* ADDR_SURF_16_BANK = 0x03, */ CB_COLOR0_ATTRIB__BANK_WIDTH_mask = 0x03 << 13, CB_COLOR0_ATTRIB__BANK_WIDTH_shift = 13, /* ADDR_SURF_BANK_WIDTH_1 = 0x00, */ /* ADDR_SURF_BANK_WIDTH_2 = 0x01, */ /* ADDR_SURF_BANK_WIDTH_4 = 0x02, */ /* ADDR_SURF_BANK_WIDTH_8 = 0x03, */ CB_COLOR0_ATTRIB__BANK_HEIGHT_mask = 0x03 << 16, CB_COLOR0_ATTRIB__BANK_HEIGHT_shift = 16, /* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ /* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ /* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ /* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_mask = 0x03 << 19, CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift = 19, /* ADDR_SURF_MACRO_ASPECT_1 = 0x00, */ /* ADDR_SURF_MACRO_ASPECT_2 = 0x01, */ /* ADDR_SURF_MACRO_ASPECT_4 = 0x02, */ /* ADDR_SURF_MACRO_ASPECT_8 = 0x03, */ FMASK_BANK_HEIGHT_mask = 0x03 << 22, FMASK_BANK_HEIGHT_shift = 22, /* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ /* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ /* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ /* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ CB_COLOR0_ATTRIB__NUM_SAMPLES_mask = 0x07 << 24, CB_COLOR0_ATTRIB__NUM_SAMPLES_shift = 24, NUM_FRAGMENTS_mask = 0x03 << 27, NUM_FRAGMENTS_shift = 27, FORCE_DST_ALPHA_1_bit = 1 << 31, CB_COLOR0_DIM = 0x00028c78, CB_COLOR0_DIM_num = 12, CB_COLOR0_DIM_offset = 51, WIDTH_MAX_mask = 0xffff << 0, WIDTH_MAX_shift = 0, HEIGHT_MAX_mask = 0xffff << 16, HEIGHT_MAX_shift = 16, CB_COLOR0_CMASK = 0x00028c7c, CB_COLOR0_CMASK_num = 8, CB_COLOR0_CMASK_offset = 60, CB_COLOR0_CMASK_SLICE = 0x00028c80, CB_COLOR0_CMASK_SLICE_num = 8, CB_COLOR0_CMASK_SLICE_offset = 60, CB_COLOR0_CMASK_SLICE__TILE_MAX_mask = 0x3fff << 0, CB_COLOR0_CMASK_SLICE__TILE_MAX_shift = 0, CB_COLOR0_FMASK = 0x00028c84, CB_COLOR0_FMASK_num = 8, CB_COLOR0_FMASK_offset = 60, CB_COLOR0_FMASK_SLICE = 0x00028c88, CB_COLOR0_FMASK_SLICE_num = 8, CB_COLOR0_FMASK_SLICE_offset = 60, CB_COLOR0_FMASK_SLICE__TILE_MAX_mask = 0x3fffff << 0, CB_COLOR0_FMASK_SLICE__TILE_MAX_shift = 0, CB_COLOR0_CLEAR_WORD0 = 0x00028c8c, CB_COLOR0_CLEAR_WORD0_num = 8, CB_COLOR0_CLEAR_WORD0_offset = 60, CB_COLOR0_CLEAR_WORD1 = 0x00028c90, CB_COLOR0_CLEAR_WORD1_num = 8, CB_COLOR0_CLEAR_WORD1_offset = 60, CB_COLOR0_CLEAR_WORD2 = 0x00028c94, CB_COLOR0_CLEAR_WORD2_num = 8, CB_COLOR0_CLEAR_WORD2_offset = 60, CB_COLOR0_CLEAR_WORD3 = 0x00028c98, CB_COLOR0_CLEAR_WORD3_num = 8, CB_COLOR0_CLEAR_WORD3_offset = 60, SQ_ALU_CONST_CACHE_HS_0 = 0x00028f00, SQ_ALU_CONST_CACHE_HS_0_num = 16, SQ_ALU_CONST_CACHE_LS_0 = 0x00028f40, SQ_ALU_CONST_CACHE_LS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x00028f80, SQ_ALU_CONST_BUFFER_SIZE_HS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x00028fc0, SQ_ALU_CONST_BUFFER_SIZE_LS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_shift = 0, SQ_VTX_CONSTANT_WORD0_0 = 0x00030000, SQ_TEX_RESOURCE_WORD0_0 = 0x00030000, DIM_mask = 0x07 << 0, DIM_shift = 0, SQ_TEX_DIM_1D = 0x00, SQ_TEX_DIM_2D = 0x01, SQ_TEX_DIM_3D = 0x02, SQ_TEX_DIM_CUBEMAP = 0x03, SQ_TEX_DIM_1D_ARRAY = 0x04, SQ_TEX_DIM_2D_ARRAY = 0x05, SQ_TEX_DIM_2D_MSAA = 0x06, SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, /* IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, */ SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_mask= 0x03 << 4, SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_shift= 4, PITCH_mask = 0xfff << 6, PITCH_shift = 6, TEX_WIDTH_mask = 0x3fff << 18, TEX_WIDTH_shift = 18, SQ_VTX_CONSTANT_WORD1_0 = 0x00030004, SQ_TEX_RESOURCE_WORD1_0 = 0x00030004, TEX_HEIGHT_mask = 0x3fff << 0, TEX_HEIGHT_shift = 0, TEX_DEPTH_mask = 0x1fff << 14, TEX_DEPTH_shift = 14, SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0x0f << 28, SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28, SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, BASE_ADDRESS_HI_mask = 0xff << 0, BASE_ADDRESS_HI_shift = 0, SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0xfff << 8, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ SQ_TEX_RESOURCE_WORD2_0 = 0x00030008, SQ_VTX_CONSTANT_WORD3_0 = 0x0003000c, CACHE_SWIZZLE_bit = 1 << 0, SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x07 << 3, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x07 << 6, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x07 << 9, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x07 << 12, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD3_0 = 0x0003000c, SQ_TEX_RESOURCE_WORD4_0 = 0x00030010, FORMAT_COMP_X_mask = 0x03 << 0, FORMAT_COMP_X_shift = 0, SQ_FORMAT_COMP_UNSIGNED = 0x00, SQ_FORMAT_COMP_SIGNED = 0x01, SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, FORMAT_COMP_Y_mask = 0x03 << 2, FORMAT_COMP_Y_shift = 2, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_Z_mask = 0x03 << 4, FORMAT_COMP_Z_shift = 4, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_W_mask = 0x03 << 6, FORMAT_COMP_W_shift = 6, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ LOG2_NUM_FRAGMENTS_mask = 0x03 << 14, LOG2_NUM_FRAGMENTS_shift = 14, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ BASE_LEVEL_mask = 0x0f << 28, BASE_LEVEL_shift = 28, SQ_VTX_CONSTANT_WORD4_0 = 0x00030010, SQ_TEX_RESOURCE_WORD5_0 = 0x00030014, LAST_LEVEL_mask = 0x0f << 0, LAST_LEVEL_shift = 0, BASE_ARRAY_mask = 0x1fff << 4, BASE_ARRAY_shift = 4, LAST_ARRAY_mask = 0x1fff << 17, LAST_ARRAY_shift = 17, SQ_TEX_RESOURCE_WORD6_0 = 0x00030018, PERF_MODULATION_mask = 0x07 << 3, PERF_MODULATION_shift = 3, INTERLACED_bit = 1 << 6, SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8, SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x07 << 29, SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29, SQ_ADDR_SURF_TILE_SPLIT_64B = 0x00, SQ_ADDR_SURF_TILE_SPLIT_128B = 0x01, SQ_ADDR_SURF_TILE_SPLIT_256B = 0x02, SQ_ADDR_SURF_TILE_SPLIT_512B = 0x03, SQ_ADDR_SURF_TILE_SPLIT_1KB = 0x04, SQ_ADDR_SURF_TILE_SPLIT_2KB = 0x05, SQ_ADDR_SURF_TILE_SPLIT_4KB = 0x06, SQ_VTX_CONSTANT_WORD7_0 = 0x0003001c, SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30, SQ_TEX_VTX_INVALID_TEXTURE = 0x00, SQ_TEX_VTX_INVALID_BUFFER = 0x01, SQ_TEX_VTX_VALID_TEXTURE = 0x02, SQ_TEX_VTX_VALID_BUFFER = 0x03, SQ_TEX_RESOURCE_WORD7_0 = 0x0003001c, SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f << 0, SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x03 << 6, SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, SQ_ADDR_SURF_MACRO_ASPECT_1 = 0x00, SQ_ADDR_SURF_MACRO_ASPECT_2 = 0x01, SQ_ADDR_SURF_MACRO_ASPECT_4 = 0x02, SQ_ADDR_SURF_MACRO_ASPECT_8 = 0x03, SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x03 << 8, SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, SQ_ADDR_SURF_BANK_WH_1 = 0x00, SQ_ADDR_SURF_BANK_WH_2 = 0x01, SQ_ADDR_SURF_BANK_WH_4 = 0x02, SQ_ADDR_SURF_BANK_WH_8 = 0x03, SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x03 << 10, SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10, /* SQ_ADDR_SURF_BANK_WH_1 = 0x00, */ /* SQ_ADDR_SURF_BANK_WH_2 = 0x01, */ /* SQ_ADDR_SURF_BANK_WH_4 = 0x02, */ /* SQ_ADDR_SURF_BANK_WH_8 = 0x03, */ DEPTH_SAMPLE_ORDER_bit = 1 << 15, SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x03 << 16, SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16, SQ_ADDR_SURF_2_BANK = 0x00, SQ_ADDR_SURF_4_BANK = 0x01, SQ_ADDR_SURF_8_BANK = 0x02, SQ_ADDR_SURF_16_BANK = 0x03, SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x03 << 30, SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30, /* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ /* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ /* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ /* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ SQ_LOOP_CONST_DX10_0 = 0x0003a200, SQ_LOOP_CONST_0 = 0x0003a200, SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, SQ_LOOP_CONST_0__COUNT_shift = 0, INIT_mask = 0xfff << 12, INIT_shift = 12, INC_mask = 0xff << 24, INC_shift = 24, SQ_JUMPTABLE_CONST_0 = 0x0003a200, CONST_A_mask = 0xff << 0, CONST_A_shift = 0, CONST_B_mask = 0xff << 8, CONST_B_shift = 8, CONST_C_mask = 0xff << 16, CONST_C_shift = 16, CONST_D_mask = 0xff << 24, CONST_D_shift = 24, SQ_BOOL_CONST_0 = 0x0003a500, SQ_BOOL_CONST_0_num = 6, SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, CLAMP_X_mask = 0x07 << 0, CLAMP_X_shift = 0, SQ_TEX_WRAP = 0x00, SQ_TEX_MIRROR = 0x01, SQ_TEX_CLAMP_LAST_TEXEL = 0x02, SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, SQ_TEX_CLAMP_HALF_BORDER = 0x04, SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, SQ_TEX_CLAMP_BORDER = 0x06, SQ_TEX_MIRROR_ONCE_BORDER = 0x07, CLAMP_Y_mask = 0x07 << 3, CLAMP_Y_shift = 3, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ CLAMP_Z_mask = 0x07 << 6, CLAMP_Z_shift = 6, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ XY_MAG_FILTER_mask = 0x03 << 9, XY_MAG_FILTER_shift = 9, SQ_TEX_XY_FILTER_POINT = 0x00, SQ_TEX_XY_FILTER_BILINEAR = 0x01, XY_MIN_FILTER_mask = 0x03 << 11, XY_MIN_FILTER_shift = 11, /* SQ_TEX_XY_FILTER_POINT = 0x00, */ /* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ Z_FILTER_mask = 0x03 << 13, Z_FILTER_shift = 13, SQ_TEX_Z_FILTER_NONE = 0x00, SQ_TEX_Z_FILTER_POINT = 0x01, SQ_TEX_Z_FILTER_LINEAR = 0x02, MIP_FILTER_mask = 0x03 << 15, MIP_FILTER_shift = 15, /* SQ_TEX_Z_FILTER_NONE = 0x00, */ /* SQ_TEX_Z_FILTER_POINT = 0x01, */ /* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ BORDER_COLOR_TYPE_mask = 0x03 << 20, BORDER_COLOR_TYPE_shift = 20, SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, SQ_TEX_BORDER_COLOR_REGISTER = 0x03, DEPTH_COMPARE_FUNCTION_mask = 0x07 << 22, DEPTH_COMPARE_FUNCTION_shift = 22, SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, SQ_TEX_DEPTH_COMPARE_LESS = 0x01, SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, FORCE_UNNORMALIZED_bit = 1 << 25, SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff << 0, SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, MAX_LOD_mask = 0xfff << 12, MAX_LOD_shift = 12, PERF_MIP_mask = 0x0f << 24, PERF_MIP_shift = 24, PERF_Z_mask = 0x0f << 28, PERF_Z_shift = 28, SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff << 0, SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, LOD_BIAS_SEC_mask = 0x3f << 14, LOD_BIAS_SEC_shift = 14, MC_COORD_TRUNCATE_bit = 1 << 20, SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21, TRUNCATE_COORD_bit = 1 << 28, SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, SQ_VTX_BASE_VTX_LOC = 0x0003cff0, SQ_VTX_START_INST_LOC = 0x0003cff4, SQ_TEX_SAMPLER_CLEAR = 0x0003ff00, SQ_TEX_RESOURCE_CLEAR = 0x0003ff04, SQ_LOOP_BOOL_CLEAR = 0x0003ff08, PA_CL_GB_VERT_DISC_ADJ = 0x0028be8c, } ; #endif /* _CAYMAN_REG_AUTO */ xserver-xorg-video-ati-7.5.0+git20150819/src/cayman_shader.c000066400000000000000000003573741256524674500232620ustar00rootroot00000000000000/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "cayman_shader.h" #include "cayman_reg.h" /* solid vs --------------------------------------- */ int cayman_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 - always export a param whether it's used or not */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 3 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* solid ps --------------------------------------- */ int cayman_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(3), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 3 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 4 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 5 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 6 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); return i; } /* copy vs --------------------------------------- */ int cayman_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 3 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 6/7 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* copy ps --------------------------------------- */ int cayman_copy_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* CF INST 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(4), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* CF INST 1 */ shader[i++] = CF_DWORD0(ADDR(8), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* CF INST 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* CF INST 3 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 4 interpolate tex coords */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 5 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 6 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 7 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 8/9 TEX INST 0 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), /* R */ DST_SEL_Y(SQ_SEL_Y), /* G */ DST_SEL_Z(SQ_SEL_Z), /* B */ DST_SEL_W(SQ_SEL_W), /* A */ LOD_BIAS(0), COORD_TYPE_X(TEX_UNNORMALIZED), COORD_TYPE_Y(TEX_UNNORMALIZED), COORD_TYPE_Z(TEX_UNNORMALIZED), COORD_TYPE_W(TEX_UNNORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } int cayman_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(8), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 1 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(5), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(2), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 3 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 4 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 5 texX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 6 texY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 7 - padding */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 8/9 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 10/11 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } int cayman_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(6), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(22), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 2 */ shader[i++] = CF_DWORD0(ADDR(30), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 3 */ shader[i++] = CF_ALU_DWORD0(ADDR(10), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(12), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 5 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 6 interpolate tex coords */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 7 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 8 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 9 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 10,11,12,13 */ /* r2.x = MAD(c0.w, r1.x, c0.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c0.w, r1.x, c0.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c0.w, r1.x, c0.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 14,15,16,17 */ /* r2.x = MAD(c1.x, r1.y, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c1.y, r1.y, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c1.z, r1.y, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_W), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 18,19,20,21 */ /* r2.x = MAD(c2.x, r1.z, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* r2.y = MAD(c2.y, r1.z, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* r2.z = MAD(c2.z, r1.z, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 22 */ shader[i++] = CF_DWORD0(ADDR(24), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 23 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(1)); /* 24/25 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 26/27 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_X), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 28/29 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(2), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_X), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(2), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 30 */ shader[i++] = CF_DWORD0(ADDR(32), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 31 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(1)); /* 32/33 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } /* comp vs --------------------------------------- */ int cayman_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(3), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(9), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 2 - end */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* 3 - mask sub */ shader[i++] = CF_DWORD0(ADDR(44), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 4 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(14), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(20), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 6 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT), MARK(0), BARRIER(0)); /* 7 - mask */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(1), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 8 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(1)); /* 9 - non-mask sub */ shader[i++] = CF_DWORD0(ADDR(50), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 10 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(34), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(10), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 11 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 12 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 13 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(1)); /* 14 srcX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 15 srcX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 16 srcX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 17 srcX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 18 srcY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 19 srcY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 20 srcY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 21 srcY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 22 maskX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 23 maskX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 24 maskX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 25 maskX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 26 maskY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 27 maskY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 28 maskY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 29 maskY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 30 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 31 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 32 maskX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 33 maskY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 34 srcX.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 35 srcX.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 36 srcX.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 37 srcX.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 38 srcY.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 39 srcY.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 40 srcY.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 41 srcY.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 42 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 43 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* mask vfetch - 44/45 - dst */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(2), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 46/47 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 48/49 - mask */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(16), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* no mask vfetch - 50/51 - dst */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 52/53 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), STRUCTURED_READ(SQ_VTX_STRU_READ_OFF), LDS_REQ(0), COALESCED_READ(0)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* comp ps --------------------------------------- */ int cayman_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ /* call interp-fetch-mask if boolean1 == true */ shader[i++] = CF_DWORD0(ADDR(12), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(1), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 1 */ /* call read-constant-mask if boolean1 == false */ shader[i++] = CF_DWORD0(ADDR(15), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(1), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 2 */ /* call interp-fetch-src if boolean0 == true */ shader[i++] = CF_DWORD0(ADDR(7), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 3 */ /* call read-constant-src if boolean0 == false */ shader[i++] = CF_DWORD0(ADDR(10), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), BARRIER(0)); /* 4 */ /* src IN mask (GPR2 := GPR1 .* GPR0) */ shader[i++] = CF_ALU_DWORD0(ADDR(17), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 */ /* export pixel data */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 6 */ /* end of program */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_END), BARRIER(1)); /* subroutine interp-fetch-src */ /* 7 */ /* interpolate src */ shader[i++] = CF_ALU_DWORD0(ADDR(21), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 8 */ /* texture fetch src into GPR0 */ shader[i++] = CF_DWORD0(ADDR(26), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 9 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(0)); /* subroutine read-constant-src */ /* 10 */ /* read constants into GPR0 */ shader[i++] = CF_ALU_DWORD0(ADDR(28), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(1), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 11 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(0)); /* subroutine interp-fetch-mask */ /* 12 */ /* interpolate mask */ shader[i++] = CF_ALU_DWORD0(ADDR(32), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 13 */ /* texture fetch mask into GPR1 */ shader[i++] = CF_DWORD0(ADDR(36), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TC), BARRIER(1)); /* 14 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(0)); /* subroutine read-constant-src */ /* 15 */ /* read constants into GPR1 */ shader[i++] = CF_ALU_DWORD0(ADDR(38), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(1), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 16 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), BARRIER(0)); /* ALU clauses */ /* 17 */ /* MUL gpr[0].x gpr[0].x gpr[1].x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 18 */ /* MUL gpr[0].y gpr[0].y gpr[1].y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 19 */ /* MUL gpr[0].z gpr[0].z gpr[1].z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 20 */ /* MUL gpr[0].w gpr[0].w gpr[1].w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 21 */ /* INTERP_XY GPR0.x, GPR0.y PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 22 */ /* INTERP_XY GPR0.y, GPR0.x PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 23 */ /* INTERP_XY GPR0.z, GPR0.y PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 24 */ /* INTERP_XY GPR0.w, GPR0.x PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 25 */ shader[i++] = 0; shader[i++] = 0; /* 26/27 */ /* SAMPLE RID=0 GPR0, GPR0 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 28 */ /* MOV GPR0.x, KC4.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 29 */ /* MOV GPR0.y, KC4.y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 30 */ /* MOV GPR0.z, KC4.z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 31 */ /* MOV GPR0.w, KC4.w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 32 */ /* INTERP_XY GPR1.x, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 33 */ /* INTERP_XY GPR1.y, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 34 */ /* INTERP_XY GPR1.z, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 35 */ /* INTERP_XY GPR1.w, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 36/37 */ /* SAMPLE RID=1 GPR1, GPR1 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(1), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 38 */ /* MOV GPR1.x, KC5.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 39 */ /* MOV GPR1.y, KC5.y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 40 */ /* MOV GPR1.z, KC5.z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 41 */ /* MOV GPR1.w, KC5.w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); return i; } xserver-xorg-video-ati-7.5.0+git20150819/src/cayman_shader.h000066400000000000000000000236061256524674500232530ustar00rootroot00000000000000/* * Cayman shaders * * Copyright (C) 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * Shader macros */ #ifndef __SHADER_H__ #define __SHADER_H__ #include "radeon.h" /* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */ // CF insts // addr #define ADDR(x) (x) // jumptable #define JUMPTABLE_SEL(x) (x) // pc #define POP_COUNT(x) (x) // const #define CF_CONST(x) (x) // cond #define COND(x) (x) // SQ_COND_* // count #define I_COUNT(x) ((x) ? ((x) - 1) : 0) // vpm #define VALID_PIXEL_MODE(x) (x) // cf inst #define CF_INST(x) (x) // SQ_CF_INST_* // wqm #define WHOLE_QUAD_MODE(x) (x) // barrier #define BARRIER(x) (x) //kb0 #define KCACHE_BANK0(x) (x) //kb1 #define KCACHE_BANK1(x) (x) // km0/1 #define KCACHE_MODE0(x) (x) #define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_* // #define KCACHE_ADDR0(x) (x) #define KCACHE_ADDR1(x) (x) #define ALT_CONST(x) (x) #define ARRAY_BASE(x) (x) // export pixel #define CF_PIXEL_MRT0 0 #define CF_PIXEL_MRT1 1 #define CF_PIXEL_MRT2 2 #define CF_PIXEL_MRT3 3 #define CF_PIXEL_MRT4 4 #define CF_PIXEL_MRT5 5 #define CF_PIXEL_MRT6 6 #define CF_PIXEL_MRT7 7 // computed Z #define CF_COMPUTED_Z 61 // export pos #define CF_POS0 60 #define CF_POS1 61 #define CF_POS2 62 #define CF_POS3 63 // export param // 0...31 #define TYPE(x) (x) // SQ_EXPORT_* #define RW_GPR(x) (x) #define RW_REL(x) (x) #define ABSOLUTE 0 #define RELATIVE 1 #define INDEX_GPR(x) (x) #define ELEM_SIZE(x) (x ? (x - 1) : 0) #define BURST_COUNT(x) (x ? (x - 1) : 0) #define MARK(x) (x) // swiz #define SRC_SEL_X(x) (x) // SQ_SEL_* each #define SRC_SEL_Y(x) (x) #define SRC_SEL_Z(x) (x) #define SRC_SEL_W(x) (x) #define CF_DWORD0(addr, jmptbl) cpu_to_le32(((addr) | ((jmptbl) << 24))) #define CF_DWORD1(pc, cf_const, cond, count, vpm, cf_inst, b) \ cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \ ((vpm) << 20) | ((cf_inst) << 22) | ((b) << 31))) #define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))) #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \ cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ ((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))) #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \ ((index_gpr) << 23) | ((es) << 30))) #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, cf_inst, m, b) \ cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \ ((bc) << 16) | ((vpm) << 20) | ((cf_inst) << 22) | ((m) << 30) | ((b) << 31))) // ALU clause insts #define SRC0_SEL(x) (x) #define SRC1_SEL(x) (x) #define SRC2_SEL(x) (x) // src[0-2]_sel // 0-127 GPR // 128-159 kcache constants bank 0 // 160-191 kcache constants bank 1 // 192-255 inline const values // 256-287 kcache constants bank 2 // 288-319 kcache constants bank 3 // 219-255 special SQ_ALU_SRC_* (0, 1, etc.) // 488-520 src param space #define ALU_SRC_GPR_BASE 0 #define ALU_SRC_KCACHE0_BASE 128 #define ALU_SRC_KCACHE1_BASE 160 #define ALU_SRC_INLINE_K_BASE 192 #define ALU_SRC_KCACHE2_BASE 256 #define ALU_SRC_KCACHE3_BASE 288 #define ALU_SRC_PARAM_BASE 448 #define SRC0_REL(x) (x) #define SRC1_REL(x) (x) #define SRC2_REL(x) (x) // elem #define SRC0_ELEM(x) (x) #define SRC1_ELEM(x) (x) #define SRC2_ELEM(x) (x) #define ELEM_X 0 #define ELEM_Y 1 #define ELEM_Z 2 #define ELEM_W 3 // neg #define SRC0_NEG(x) (x) #define SRC1_NEG(x) (x) #define SRC2_NEG(x) (x) // im #define INDEX_MODE(x) (x) // SQ_INDEX_* // ps #define PRED_SEL(x) (x) // SQ_PRED_SEL_* // last #define LAST(x) (x) // abs #define SRC0_ABS(x) (x) #define SRC1_ABS(x) (x) // uem #define UPDATE_EXECUTE_MASK(x) (x) // up #define UPDATE_PRED(x) (x) // wm #define WRITE_MASK(x) (x) // omod #define OMOD(x) (x) // SQ_ALU_OMOD_* // alu inst #define ALU_INST(x) (x) // SQ_ALU_INST_* //bs #define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_* #define DST_GPR(x) (x) #define DST_REL(x) (x) #define DST_ELEM(x) (x) #define CLAMP(x) (x) #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ ((im) << 26) | ((ps) << 29) | ((last) << 31))) #define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ ((de) << 29) | ((clamp) << 31))) // VTX clause insts // vxt insts #define VTX_INST(x) (x) // SQ_VTX_INST_* // fetch type #define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_* #define FETCH_WHOLE_QUAD(x) (x) #define BUFFER_ID(x) (x) #define SRC_GPR(x) (x) #define SRC_REL(x) (x) #define STRUCTURED_READ(x) (x) #define LDS_REQ(x) (x) #define COALESCED_READ(x) (x) #define DST_SEL_X(x) (x) #define DST_SEL_Y(x) (x) #define DST_SEL_Z(x) (x) #define DST_SEL_W(x) (x) #define USE_CONST_FIELDS(x) (x) #define DATA_FORMAT(x) (x) // num format #define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_* // format comp #define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_* // sma #define SRF_MODE_ALL(x) (x) #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 #define SRF_MODE_NO_ZERO 1 #define OFFSET(x) (x) // endian swap #define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_* #define CONST_BUF_NO_STRIDE(x) (x) #define BUFFER_INDEX_MODE(x) (x) #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, ssy, str, ldsr, cr) \ cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((ssy) << 26) | \ ((str) << 28) | ((ldsr) << 30) | ((cr) << 31))) #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) #define VTX_DWORD2(offset, es, cbns, alt_const, bim) \ cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((alt_const) << 20) | ((bim) << 21))) #define VTX_DWORD_PAD cpu_to_le32(0x00000000) // TEX clause insts // tex insts #define TEX_INST(x) (x) // SQ_TEX_INST_* #define INST_MOD(x) (x) #define FETCH_WHOLE_QUAD(x) (x) #define RESOURCE_ID(x) (x) #define RESOURCE_INDEX_MODE(x) (x) #define SAMPLER_INDEX_MODE(x) (x) #define LOD_BIAS(x) (x) //ct #define COORD_TYPE_X(x) (x) #define COORD_TYPE_Y(x) (x) #define COORD_TYPE_Z(x) (x) #define COORD_TYPE_W(x) (x) #define TEX_UNNORMALIZED 0 #define TEX_NORMALIZED 1 #define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */ #define OFFSET_Y(x) (((int)(x) * 2) & 0x1f) #define OFFSET_Z(x) (((int)(x) * 2) & 0x1f) #define SAMPLER_ID(x) (x) #define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \ cpu_to_le32((((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27))) #define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31))) #define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \ cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \ ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29))) #define TEX_DWORD_PAD cpu_to_le32(0x00000000) #endif xserver-xorg-video-ati-7.5.0+git20150819/src/compat-api.h000066400000000000000000000064761256524674500225150ustar00rootroot00000000000000/* * Copyright 2012 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Author: Dave Airlie */ /* this file provides API compat between server post 1.13 and pre it, it should be reused inside as many drivers as possible */ #ifndef COMPAT_API_H #define COMPAT_API_H #ifndef GLYPH_HAS_GLYPH_PICTURE_ACCESSOR #define GetGlyphPicture(g, s) GlyphPicture((g))[(s)->myNum] #define SetGlyphPicture(g, s, p) GlyphPicture((g))[(s)->myNum] = p #endif #ifndef XF86_HAS_SCRN_CONV #define xf86ScreenToScrn(s) xf86Screens[(s)->myNum] #define xf86ScrnToScreen(s) screenInfo.screens[(s)->scrnIndex] #endif #ifndef XF86_SCRN_INTERFACE #define SCRN_ARG_TYPE int #define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = xf86Screens[(arg1)] #define SCREEN_ARG_TYPE int #define SCREEN_PTR(arg1) ScreenPtr pScreen = screenInfo.screens[(arg1)] #define SCREEN_INIT_ARGS_DECL int i, ScreenPtr pScreen, int argc, char **argv #define BLOCKHANDLER_ARGS_DECL int arg, pointer blockData, pointer pTimeout, pointer pReadmask #define BLOCKHANDLER_ARGS arg, blockData, pTimeout, pReadmask #define CLOSE_SCREEN_ARGS_DECL int scrnIndex, ScreenPtr pScreen #define CLOSE_SCREEN_ARGS scrnIndex, pScreen #define ADJUST_FRAME_ARGS_DECL int arg, int x, int y, int flags #define SWITCH_MODE_ARGS_DECL int arg, DisplayModePtr mode, int flags #define FREE_SCREEN_ARGS_DECL int arg, int flags #define VT_FUNC_ARGS_DECL int arg, int flags #define VT_FUNC_ARGS(flags) pScrn->scrnIndex, (flags) #define XF86_ENABLEDISABLEFB_ARG(x) ((x)->scrnIndex) #else #define SCRN_ARG_TYPE ScrnInfoPtr #define SCRN_INFO_PTR(arg1) ScrnInfoPtr pScrn = (arg1) #define SCREEN_ARG_TYPE ScreenPtr #define SCREEN_PTR(arg1) ScreenPtr pScreen = (arg1) #define SCREEN_INIT_ARGS_DECL ScreenPtr pScreen, int argc, char **argv #define BLOCKHANDLER_ARGS_DECL ScreenPtr arg, pointer pTimeout, pointer pReadmask #define BLOCKHANDLER_ARGS arg, pTimeout, pReadmask #define CLOSE_SCREEN_ARGS_DECL ScreenPtr pScreen #define CLOSE_SCREEN_ARGS pScreen #define ADJUST_FRAME_ARGS_DECL ScrnInfoPtr arg, int x, int y #define SWITCH_MODE_ARGS_DECL ScrnInfoPtr arg, DisplayModePtr mode #define FREE_SCREEN_ARGS_DECL ScrnInfoPtr arg #define VT_FUNC_ARGS_DECL ScrnInfoPtr arg #define VT_FUNC_ARGS(flags) pScrn #define XF86_ENABLEDISABLEFB_ARG(x) (x) #endif #endif xserver-xorg-video-ati-7.5.0+git20150819/src/drmmode_display.c000066400000000000000000002162671256524674500236330ustar00rootroot00000000000000/* * Copyright © 2007 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include #include #include "cursorstr.h" #include "damagestr.h" #include "micmap.h" #include "xf86cmap.h" #include "radeon.h" #include "radeon_glamor.h" #include "radeon_reg.h" #include "drmmode_display.h" /* DPMS */ #ifdef HAVE_XEXTPROTO_71 #include #else #define DPMS_SERVER #include #endif #define DEFAULT_NOMINAL_FRAME_RATE 60 static Bool drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height); static Bool RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) { int i = 0; char s1[20]; do { switch(*s) { case ',': s1[i] = '\0'; i = 0; if (strcmp(s1, output_name) == 0) return TRUE; break; case ' ': case '\t': case '\n': case '\r': break; default: s1[i] = *s; i++; break; } } while(*s++); s1[i] = '\0'; if (strcmp(s1, output_name) == 0) return TRUE; return FALSE; } static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn, int width, int height, int depth, int bpp, int pitch, int tiling, struct radeon_bo *bo, struct radeon_surface *psurf) { RADEONInfoPtr info = RADEONPTR(pScrn); ScreenPtr pScreen = pScrn->pScreen; PixmapPtr pixmap; struct radeon_surface *surface; pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth, RADEON_CREATE_PIXMAP_SCANOUT); if (!pixmap) return NULL; if (!(*pScreen->ModifyPixmapHeader)(pixmap, width, height, depth, bpp, pitch, NULL)) { return NULL; } if (!info->use_glamor) exaMoveInPixmap(pixmap); radeon_set_pixmap_bo(pixmap, bo); if (info->ChipFamily >= CHIP_FAMILY_R600) { surface = radeon_get_pixmap_surface(pixmap); if (surface && psurf) *surface = *psurf; else if (surface) { memset(surface, 0, sizeof(struct radeon_surface)); surface->npix_x = width; surface->npix_y = height; surface->npix_z = 1; surface->blk_w = 1; surface->blk_h = 1; surface->blk_d = 1; surface->array_size = 1; surface->last_level = 0; surface->bpe = bpp / 8; surface->nsamples = 1; surface->flags = RADEON_SURF_SCANOUT; /* we are requiring a recent enough libdrm version */ surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); if (tiling & RADEON_TILING_MICRO) { surface->flags = RADEON_SURF_CLR(surface->flags, MODE); surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); } if (tiling & RADEON_TILING_MACRO) { surface->flags = RADEON_SURF_CLR(surface->flags, MODE); surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } if (radeon_surface_best(info->surf_man, surface)) { return NULL; } if (radeon_surface_init(info->surf_man, surface)) { return NULL; } } } if (info->use_glamor && !radeon_glamor_create_textured_pixmap(pixmap, radeon_get_pixmap_private(pixmap))) { pScreen->DestroyPixmap(pixmap); return NULL; } return pixmap; } static void drmmode_destroy_bo_pixmap(PixmapPtr pixmap) { ScreenPtr pScreen = pixmap->drawable.pScreen; (*pScreen->DestroyPixmap)(pixmap); } static void drmmode_ConvertFromKMode(ScrnInfoPtr scrn, drmModeModeInfo *kmode, DisplayModePtr mode) { memset(mode, 0, sizeof(DisplayModeRec)); mode->status = MODE_OK; mode->Clock = kmode->clock; mode->HDisplay = kmode->hdisplay; mode->HSyncStart = kmode->hsync_start; mode->HSyncEnd = kmode->hsync_end; mode->HTotal = kmode->htotal; mode->HSkew = kmode->hskew; mode->VDisplay = kmode->vdisplay; mode->VSyncStart = kmode->vsync_start; mode->VSyncEnd = kmode->vsync_end; mode->VTotal = kmode->vtotal; mode->VScan = kmode->vscan; mode->Flags = kmode->flags; //& FLAG_BITS; mode->name = strdup(kmode->name); if (kmode->type & DRM_MODE_TYPE_DRIVER) mode->type = M_T_DRIVER; if (kmode->type & DRM_MODE_TYPE_PREFERRED) mode->type |= M_T_PREFERRED; xf86SetModeCrtc (mode, scrn->adjustFlags); } static void drmmode_ConvertToKMode(ScrnInfoPtr scrn, drmModeModeInfo *kmode, DisplayModePtr mode) { memset(kmode, 0, sizeof(*kmode)); kmode->clock = mode->Clock; kmode->hdisplay = mode->HDisplay; kmode->hsync_start = mode->HSyncStart; kmode->hsync_end = mode->HSyncEnd; kmode->htotal = mode->HTotal; kmode->hskew = mode->HSkew; kmode->vdisplay = mode->VDisplay; kmode->vsync_start = mode->VSyncStart; kmode->vsync_end = mode->VSyncEnd; kmode->vtotal = mode->VTotal; kmode->vscan = mode->VScan; kmode->flags = mode->Flags; //& FLAG_BITS; if (mode->name) strncpy(kmode->name, mode->name, DRM_DISPLAY_MODE_LEN); kmode->name[DRM_DISPLAY_MODE_LEN-1] = 0; } /* * Retrieves present time in microseconds that is compatible * with units used by vblank timestamps. Depending on the kernel * version and DRM kernel module configuration, the vblank * timestamp can either be in real time or monotonic time */ int drmmode_get_current_ust(int drm_fd, CARD64 *ust) { uint64_t cap_value; int ret; struct timespec now; ret = drmGetCap(drm_fd, DRM_CAP_TIMESTAMP_MONOTONIC, &cap_value); if (ret || !cap_value) /* old kernel or drm_timestamp_monotonic turned off */ ret = clock_gettime(CLOCK_REALTIME, &now); else ret = clock_gettime(CLOCK_MONOTONIC, &now); if (ret) return ret; *ust = ((CARD64)now.tv_sec * 1000000) + ((CARD64)now.tv_nsec / 1000); return 0; } /* * Get current frame count and frame count timestamp of the crtc. */ int drmmode_crtc_get_ust_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc) { ScrnInfoPtr scrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(scrn); drmVBlank vbl; int ret; vbl.request.type = DRM_VBLANK_RELATIVE; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "get vblank counter failed: %s\n", strerror(errno)); return ret; } *ust = ((CARD64)vbl.reply.tval_sec * 1000000) + vbl.reply.tval_usec; *msc = vbl.reply.sequence; return Success; } static void drmmode_do_crtc_dpms(xf86CrtcPtr crtc, int mode) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ScrnInfoPtr scrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(scrn); CARD64 ust; int ret; if (drmmode_crtc->dpms_mode == DPMSModeOn && mode != DPMSModeOn) { drmVBlank vbl; /* * On->Off transition: record the last vblank time, * sequence number and frame period. */ vbl.request.type = DRM_VBLANK_RELATIVE; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) xf86DrvMsg(scrn->scrnIndex, X_ERROR, "%s cannot get last vblank counter\n", __func__); else { CARD64 seq = (CARD64)vbl.reply.sequence; CARD64 nominal_frame_rate, pix_in_frame; ust = ((CARD64)vbl.reply.tval_sec * 1000000) + vbl.reply.tval_usec; drmmode_crtc->dpms_last_ust = ust; drmmode_crtc->dpms_last_seq = seq; nominal_frame_rate = crtc->mode.Clock; nominal_frame_rate *= 1000; pix_in_frame = crtc->mode.HTotal * crtc->mode.VTotal; if (nominal_frame_rate == 0 || pix_in_frame == 0) nominal_frame_rate = DEFAULT_NOMINAL_FRAME_RATE; else nominal_frame_rate /= pix_in_frame; drmmode_crtc->dpms_last_fps = nominal_frame_rate; } } else if (drmmode_crtc->dpms_mode != DPMSModeOn && mode == DPMSModeOn) { /* * Off->On transition: calculate and accumulate the * number of interpolated vblanks while we were in Off state */ ret = drmmode_get_current_ust(info->dri2.drm_fd, &ust); if (ret) xf86DrvMsg(scrn->scrnIndex, X_ERROR, "%s cannot get current time\n", __func__); else if (drmmode_crtc->dpms_last_ust) { CARD64 time_elapsed, delta_seq; time_elapsed = ust - drmmode_crtc->dpms_last_ust; delta_seq = time_elapsed * drmmode_crtc->dpms_last_fps; delta_seq /= 1000000; drmmode_crtc->interpolated_vblanks += delta_seq; } } drmmode_crtc->dpms_mode = mode; } static void drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; /* Disable unused CRTCs */ if (!crtc->enabled || mode != DPMSModeOn) drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, 0, 0, 0, NULL, 0, NULL); else if (drmmode_crtc->dpms_mode != DPMSModeOn) crtc->funcs->set_mode_major(crtc, &crtc->mode, crtc->rotation, crtc->x, crtc->y); } static PixmapPtr create_pixmap_for_fbcon(drmmode_ptr drmmode, ScrnInfoPtr pScrn, int fbcon_id) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pixmap = info->fbcon_pixmap; struct radeon_bo *bo; drmModeFBPtr fbcon; struct drm_gem_flink flink; if (pixmap) return pixmap; fbcon = drmModeGetFB(drmmode->fd, fbcon_id); if (fbcon == NULL) return NULL; if (fbcon->depth != pScrn->depth || fbcon->width != pScrn->virtualX || fbcon->height != pScrn->virtualY) goto out_free_fb; flink.handle = fbcon->handle; if (ioctl(drmmode->fd, DRM_IOCTL_GEM_FLINK, &flink) < 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Couldn't flink fbcon handle\n"); goto out_free_fb; } bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0); if (bo == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Couldn't allocate bo for fbcon handle\n"); goto out_free_fb; } pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height, fbcon->depth, fbcon->bpp, fbcon->pitch, 0, bo, NULL); info->fbcon_pixmap = pixmap; radeon_bo_unref(bo); out_free_fb: drmModeFreeFB(fbcon); return pixmap; } static void destroy_pixmap_for_fbcon(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); /* XXX: The current GPUVM support in the kernel doesn't allow removing * the virtual address range for this BO, so we need to keep around * the pixmap to avoid breaking glamor with GPUVM */ if (info->use_glamor && info->ChipFamily >= CHIP_FAMILY_CAYMAN) return; if (info->fbcon_pixmap) pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); info->fbcon_pixmap = NULL; } #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr src, dst; ScreenPtr pScreen = pScrn->pScreen; int fbcon_id = 0; Bool force; GCPtr gc; int i; for (i = 0; i < xf86_config->num_crtc; i++) { drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[i]->driver_private; if (drmmode_crtc->mode_crtc->buffer_id) fbcon_id = drmmode_crtc->mode_crtc->buffer_id; } if (!fbcon_id) return; if (fbcon_id == drmmode->fb_id) { /* in some rare case there might be no fbcon and we might already * be the one with the current fb to avoid a false deadlck in * kernel ttm code just do nothing as anyway there is nothing * to do */ return; } src = create_pixmap_for_fbcon(drmmode, pScrn, fbcon_id); if (!src) return; dst = pScreen->GetScreenPixmap(pScreen); gc = GetScratchGC(pScrn->depth, pScreen); ValidateGC(&dst->drawable, gc); force = info->accel_state->force; info->accel_state->force = TRUE; (*gc->ops->CopyArea)(&src->drawable, &dst->drawable, gc, 0, 0, pScrn->virtualX, pScrn->virtualY, 0, 0); info->accel_state->force = force; FreeScratchGC(gc); radeon_cs_flush_indirect(pScrn); radeon_bo_wait(info->front_bo); pScreen->canDoBGNoneRoot = TRUE; destroy_pixmap_for_fbcon(pScrn); return; } #endif /* GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 */ static void drmmode_crtc_scanout_destroy(drmmode_ptr drmmode, struct drmmode_scanout *scanout) { if (scanout->pixmap) { drmmode_destroy_bo_pixmap(scanout->pixmap); scanout->pixmap = NULL; } if (scanout->bo) { drmModeRmFB(drmmode->fd, scanout->fb_id); scanout->fb_id = 0; radeon_bo_unmap(scanout->bo); radeon_bo_unref(scanout->bo); scanout->bo = NULL; } if (scanout->damage) { DamageDestroy(scanout->damage); scanout->damage = NULL; } } void drmmode_scanout_free(ScrnInfoPtr scrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); int c; for (c = 0; c < xf86_config->num_crtc; c++) { drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private; drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode, &drmmode_crtc->scanout[0]); drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode, &drmmode_crtc->scanout[1]); } } static void * drmmode_crtc_scanout_allocate(xf86CrtcPtr crtc, struct drmmode_scanout *scanout, int width, int height) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; int size; int ret; unsigned long rotate_pitch; int base_align; /* rotation requires acceleration */ if (info->r600_shadow_fb) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Rotation requires acceleration!\n"); return NULL; } if (scanout->bo) { if (scanout->width == width && scanout->height == height) return scanout->bo->ptr; drmmode_crtc_scanout_destroy(drmmode, scanout); } rotate_pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, drmmode->cpp, 0)) * drmmode->cpp; height = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, 0)); base_align = drmmode_get_base_align(pScrn, drmmode->cpp, 0); size = RADEON_ALIGN(rotate_pitch * height, RADEON_GPU_PAGE_SIZE); scanout->bo = radeon_bo_open(drmmode->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_VRAM, 0); if (scanout->bo == NULL) return NULL; radeon_bo_map(scanout->bo, 1); ret = drmModeAddFB(drmmode->fd, width, height, pScrn->depth, pScrn->bitsPerPixel, rotate_pitch, scanout->bo->handle, &scanout->fb_id); if (ret) ErrorF("failed to add scanout fb\n"); scanout->width = width; scanout->height = height; return scanout->bo->ptr; } static PixmapPtr drmmode_crtc_scanout_create(xf86CrtcPtr crtc, struct drmmode_scanout *scanout, void *data, int width, int height) { ScrnInfoPtr pScrn = crtc->scrn; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; unsigned long rotate_pitch; if (scanout->pixmap) { if (scanout->width == width && scanout->height == height) return scanout->pixmap; drmmode_crtc_scanout_destroy(drmmode, scanout); } if (!data) data = drmmode_crtc_scanout_allocate(crtc, scanout, width, height); rotate_pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, drmmode->cpp, 0)) * drmmode->cpp; scanout->pixmap = drmmode_create_bo_pixmap(pScrn, width, height, pScrn->depth, pScrn->bitsPerPixel, rotate_pitch, 0, scanout->bo, NULL); if (scanout->pixmap == NULL) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Couldn't allocate scanout pixmap for CRTC\n"); return scanout->pixmap; } static void radeon_screen_damage_report(DamagePtr damage, RegionPtr region, void *closure) { /* Only keep track of the extents */ RegionUninit(&damage->damage); damage->damage.data = NULL; } static Bool drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, Rotation rotation, int x, int y) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; int saved_x, saved_y; Rotation saved_rotation; DisplayModeRec saved_mode; uint32_t *output_ids; int output_count = 0; Bool ret = TRUE; int i; int fb_id; drmModeModeInfo kmode; int pitch; uint32_t tiling_flags = 0; int height; if (info->allowColorTiling) { if (info->ChipFamily >= CHIP_FAMILY_R600) tiling_flags |= RADEON_TILING_MICRO; else tiling_flags |= RADEON_TILING_MACRO; } pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->pixel_bytes, tiling_flags)) * info->pixel_bytes; height = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)); if (info->ChipFamily >= CHIP_FAMILY_R600) { pitch = info->front_surface.level[0].pitch_bytes; } if (drmmode->fb_id == 0) { ret = drmModeAddFB(drmmode->fd, pScrn->virtualX, height, pScrn->depth, pScrn->bitsPerPixel, pitch, info->front_bo->handle, &drmmode->fb_id); if (ret < 0) { ErrorF("failed to add fb\n"); return FALSE; } } saved_mode = crtc->mode; saved_x = crtc->x; saved_y = crtc->y; saved_rotation = crtc->rotation; if (mode) { crtc->mode = *mode; crtc->x = x; crtc->y = y; crtc->rotation = rotation; crtc->transformPresent = FALSE; } output_ids = calloc(sizeof(uint32_t), xf86_config->num_output); if (!output_ids) { ret = FALSE; goto done; } if (mode) { ScreenPtr pScreen = pScrn->pScreen; for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; drmmode_output_private_ptr drmmode_output; if (output->crtc != crtc) continue; drmmode_output = output->driver_private; output_ids[output_count] = drmmode_output->mode_output->connector_id; output_count++; } if (!xf86CrtcRotate(crtc)) { goto done; } crtc->funcs->gamma_set(crtc, crtc->gamma_red, crtc->gamma_green, crtc->gamma_blue, crtc->gamma_size); drmmode_ConvertToKMode(crtc->scrn, &kmode, mode); fb_id = drmmode->fb_id; #ifdef RADEON_PIXMAP_SHARING if (crtc->randr_crtc && crtc->randr_crtc->scanout_pixmap) { x = drmmode_crtc->prime_pixmap_x; y = 0; drmmode_crtc_scanout_destroy(drmmode, &drmmode_crtc->scanout[0]); drmmode_crtc_scanout_destroy(drmmode, &drmmode_crtc->scanout[1]); } else #endif if (drmmode_crtc->rotate.fb_id) { fb_id = drmmode_crtc->rotate.fb_id; x = y = 0; drmmode_crtc_scanout_destroy(drmmode, &drmmode_crtc->scanout[0]); drmmode_crtc_scanout_destroy(drmmode, &drmmode_crtc->scanout[1]); } else if (info->tear_free || info->shadow_primary) { for (i = 0; i < (info->tear_free ? 2 : 1); i++) { drmmode_crtc_scanout_create(crtc, &drmmode_crtc->scanout[i], NULL, mode->HDisplay, mode->VDisplay); if (drmmode_crtc->scanout[i].pixmap) { RegionPtr pRegion; BoxPtr pBox; if (!drmmode_crtc->scanout[i].damage) { drmmode_crtc->scanout[i].damage = DamageCreate(radeon_screen_damage_report, NULL, DamageReportRawRegion, TRUE, pScreen, NULL); DamageRegister(&pScreen->GetScreenPixmap(pScreen)->drawable, drmmode_crtc->scanout[i].damage); } pRegion = DamageRegion(drmmode_crtc->scanout[i].damage); RegionUninit(pRegion); pRegion->data = NULL; pBox = RegionExtents(pRegion); pBox->x1 = min(pBox->x1, x); pBox->y1 = min(pBox->y1, y); pBox->x2 = max(pBox->x2, x + mode->HDisplay); pBox->y2 = max(pBox->y2, y + mode->VDisplay); } } if (drmmode_crtc->scanout[0].pixmap && (!info->tear_free || drmmode_crtc->scanout[1].pixmap)) { drmmode_crtc->scanout_id = 0; fb_id = drmmode_crtc->scanout[0].fb_id; x = y = 0; radeon_scanout_update_handler(pScrn, 0, 0, crtc); radeon_bo_wait(drmmode_crtc->scanout[0].bo); } } ret = drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, fb_id, x, y, output_ids, output_count, &kmode); if (ret) xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "failed to set mode: %s", strerror(-ret)); else ret = TRUE; if (crtc->scrn->pScreen) xf86CrtcSetScreenSubpixelOrder(crtc->scrn->pScreen); drmmode_crtc->need_modeset = FALSE; /* go through all the outputs and force DPMS them back on? */ for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; if (output->crtc != crtc) continue; output->funcs->dpms(output, DPMSModeOn); } } if (pScrn->pScreen && !xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) xf86_reload_cursors(pScrn->pScreen); done: if (!ret) { crtc->x = saved_x; crtc->y = saved_y; crtc->rotation = saved_rotation; crtc->mode = saved_mode; } #if defined(XF86_CRTC_VERSION) && XF86_CRTC_VERSION >= 3 else crtc->active = TRUE; #endif free(output_ids); return ret; } static void drmmode_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) { } static void drmmode_set_cursor_position (xf86CrtcPtr crtc, int x, int y) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; drmModeMoveCursor(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, x, y); } static void drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; int i; uint32_t *ptr; uint32_t cursor_size = info->cursor_w * info->cursor_h; /* cursor should be mapped already */ ptr = (uint32_t *)(drmmode_crtc->cursor_bo->ptr); for (i = 0; i < cursor_size; i++) ptr[i] = cpu_to_le32(image[i]); } static void drmmode_hide_cursor (xf86CrtcPtr crtc) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; drmModeSetCursor(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, 0, info->cursor_w, info->cursor_h); } static void drmmode_show_cursor (xf86CrtcPtr crtc) { ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; uint32_t handle = drmmode_crtc->cursor_bo->handle; static Bool use_set_cursor2 = TRUE; if (use_set_cursor2) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); CursorPtr cursor = xf86_config->cursor; int ret; ret = drmModeSetCursor2(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, handle, info->cursor_w, info->cursor_h, cursor->bits->xhot, cursor->bits->yhot); if (ret == -EINVAL) use_set_cursor2 = FALSE; else return; } drmModeSetCursor(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, handle, info->cursor_w, info->cursor_h); } static void * drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; return drmmode_crtc_scanout_allocate(crtc, &drmmode_crtc->rotate, width, height); } static PixmapPtr drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; return drmmode_crtc_scanout_create(crtc, &drmmode_crtc->rotate, data, width, height); } static void drmmode_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; drmmode_crtc_scanout_destroy(drmmode, &drmmode_crtc->rotate); } static void drmmode_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, uint16_t *blue, int size) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; drmModeCrtcSetGamma(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, size, red, green, blue); } #ifdef RADEON_PIXMAP_SHARING static Bool drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix) { ScreenPtr screen = xf86ScrnToScreen(crtc->scrn); PixmapPtr screenpix = screen->GetScreenPixmap(screen); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; int c, total_width = 0, max_height = 0, this_x = 0; if (!ppix) { if (crtc->randr_crtc->scanout_pixmap) PixmapStopDirtyTracking(crtc->randr_crtc->scanout_pixmap, screenpix); drmmode_crtc->prime_pixmap_x = 0; return TRUE; } /* iterate over all the attached crtcs - work out bounding box */ for (c = 0; c < xf86_config->num_crtc; c++) { xf86CrtcPtr iter = xf86_config->crtc[c]; if (!iter->enabled && iter != crtc) continue; if (iter == crtc) { this_x = total_width; total_width += ppix->drawable.width; if (max_height < ppix->drawable.height) max_height = ppix->drawable.height; } else { total_width += iter->mode.HDisplay; if (max_height < iter->mode.VDisplay) max_height = iter->mode.VDisplay; } #ifndef HAS_DIRTYTRACKING2 if (iter != crtc) { ErrorF("Cannot do multiple crtcs without X server dirty tracking 2 interface\n"); return FALSE; } #endif } if (total_width != screenpix->drawable.width || max_height != screenpix->drawable.height) { Bool ret; ret = drmmode_xf86crtc_resize(crtc->scrn, total_width, max_height); if (ret == FALSE) return FALSE; screenpix = screen->GetScreenPixmap(screen); screen->width = screenpix->drawable.width = total_width; screen->height = screenpix->drawable.height = max_height; } drmmode_crtc->prime_pixmap_x = this_x; #ifdef HAS_DIRTYTRACKING_ROTATION PixmapStartDirtyTracking(ppix, screenpix, 0, 0, this_x, 0, RR_Rotate_0); #elif defined(HAS_DIRTYTRACKING2) PixmapStartDirtyTracking2(ppix, screenpix, 0, 0, this_x, 0); #else PixmapStartDirtyTracking(ppix, screenpix, 0, 0); #endif return TRUE; } #endif static const xf86CrtcFuncsRec drmmode_crtc_funcs = { .dpms = drmmode_crtc_dpms, .set_mode_major = drmmode_set_mode_major, .set_cursor_colors = drmmode_set_cursor_colors, .set_cursor_position = drmmode_set_cursor_position, .show_cursor = drmmode_show_cursor, .hide_cursor = drmmode_hide_cursor, .load_cursor_argb = drmmode_load_cursor_argb, .gamma_set = drmmode_crtc_gamma_set, .shadow_create = drmmode_crtc_shadow_create, .shadow_allocate = drmmode_crtc_shadow_allocate, .shadow_destroy = drmmode_crtc_shadow_destroy, .destroy = NULL, /* XXX */ #ifdef RADEON_PIXMAP_SHARING .set_scanout_pixmap = drmmode_set_scanout_pixmap, #endif }; int drmmode_get_crtc_id(xf86CrtcPtr crtc) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; return drmmode_crtc->hw_id; } void drmmode_crtc_hw_id(xf86CrtcPtr crtc) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info ginfo; int r; uint32_t tmp; memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = 0x4; tmp = drmmode_crtc->mode_crtc->crtc_id; ginfo.value = (uintptr_t)&tmp; r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { drmmode_crtc->hw_id = -1; return; } drmmode_crtc->hw_id = tmp; } static unsigned int drmmode_crtc_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, drmModeResPtr mode_res, int num) { xf86CrtcPtr crtc; drmmode_crtc_private_ptr drmmode_crtc; RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); crtc = xf86CrtcCreate(pScrn, &drmmode_crtc_funcs); if (crtc == NULL) return 0; drmmode_crtc = xnfcalloc(sizeof(drmmode_crtc_private_rec), 1); drmmode_crtc->mode_crtc = drmModeGetCrtc(drmmode->fd, mode_res->crtcs[num]); drmmode_crtc->drmmode = drmmode; crtc->driver_private = drmmode_crtc; drmmode_crtc_hw_id(crtc); /* Mark num'th crtc as in use on this device. */ pRADEONEnt->assigned_crtcs |= (1 << num); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Allocated crtc nr. %d to this screen.\n", num); return 1; } static xf86OutputStatus drmmode_output_detect(xf86OutputPtr output) { /* go to the hw and retrieve a new output struct */ drmmode_output_private_ptr drmmode_output = output->driver_private; drmmode_ptr drmmode = drmmode_output->drmmode; xf86OutputStatus status; drmModeFreeConnector(drmmode_output->mode_output); drmmode_output->mode_output = drmModeGetConnector(drmmode->fd, drmmode_output->output_id); if (!drmmode_output->mode_output) return XF86OutputStatusDisconnected; switch (drmmode_output->mode_output->connection) { case DRM_MODE_CONNECTED: status = XF86OutputStatusConnected; break; case DRM_MODE_DISCONNECTED: status = XF86OutputStatusDisconnected; break; default: case DRM_MODE_UNKNOWNCONNECTION: status = XF86OutputStatusUnknown; break; } return status; } static Bool drmmode_output_mode_valid(xf86OutputPtr output, DisplayModePtr pModes) { return MODE_OK; } static DisplayModePtr drmmode_output_get_modes(xf86OutputPtr output) { drmmode_output_private_ptr drmmode_output = output->driver_private; drmModeConnectorPtr koutput = drmmode_output->mode_output; drmmode_ptr drmmode = drmmode_output->drmmode; int i; DisplayModePtr Modes = NULL, Mode; drmModePropertyPtr props; xf86MonPtr mon = NULL; if (!koutput) return NULL; /* look for an EDID property */ for (i = 0; i < koutput->count_props; i++) { props = drmModeGetProperty(drmmode->fd, koutput->props[i]); if (props && (props->flags & DRM_MODE_PROP_BLOB)) { if (!strcmp(props->name, "EDID")) { if (drmmode_output->edid_blob) drmModeFreePropertyBlob(drmmode_output->edid_blob); drmmode_output->edid_blob = drmModeGetPropertyBlob(drmmode->fd, koutput->prop_values[i]); } } if (props) drmModeFreeProperty(props); } if (drmmode_output->edid_blob) { mon = xf86InterpretEDID(output->scrn->scrnIndex, drmmode_output->edid_blob->data); if (mon && drmmode_output->edid_blob->length > 128) mon->flags |= MONITOR_EDID_COMPLETE_RAWDATA; } xf86OutputSetEDID(output, mon); /* modes should already be available */ for (i = 0; i < koutput->count_modes; i++) { Mode = xnfalloc(sizeof(DisplayModeRec)); drmmode_ConvertFromKMode(output->scrn, &koutput->modes[i], Mode); Modes = xf86ModesAdd(Modes, Mode); } return Modes; } static void drmmode_output_destroy(xf86OutputPtr output) { drmmode_output_private_ptr drmmode_output = output->driver_private; int i; if (drmmode_output->edid_blob) drmModeFreePropertyBlob(drmmode_output->edid_blob); for (i = 0; i < drmmode_output->num_props; i++) { drmModeFreeProperty(drmmode_output->props[i].mode_prop); free(drmmode_output->props[i].atoms); } for (i = 0; i < drmmode_output->mode_output->count_encoders; i++) { drmModeFreeEncoder(drmmode_output->mode_encoders[i]); } free(drmmode_output->mode_encoders); free(drmmode_output->props); drmModeFreeConnector(drmmode_output->mode_output); free(drmmode_output); output->driver_private = NULL; } static void drmmode_output_dpms(xf86OutputPtr output, int mode) { drmmode_output_private_ptr drmmode_output = output->driver_private; xf86CrtcPtr crtc = output->crtc; drmModeConnectorPtr koutput = drmmode_output->mode_output; drmmode_ptr drmmode = drmmode_output->drmmode; if (!koutput) return; if (mode != DPMSModeOn && crtc) drmmode_do_crtc_dpms(crtc, mode); drmModeConnectorSetProperty(drmmode->fd, koutput->connector_id, drmmode_output->dpms_enum_id, mode); if (mode == DPMSModeOn && crtc) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; if (drmmode_crtc->need_modeset) drmmode_set_mode_major(crtc, &crtc->mode, crtc->rotation, crtc->x, crtc->y); else drmmode_do_crtc_dpms(crtc, mode); } } static Bool drmmode_property_ignore(drmModePropertyPtr prop) { if (!prop) return TRUE; /* ignore blob prop */ if (prop->flags & DRM_MODE_PROP_BLOB) return TRUE; /* ignore standard property */ if (!strcmp(prop->name, "EDID") || !strcmp(prop->name, "DPMS")) return TRUE; return FALSE; } static void drmmode_output_create_resources(xf86OutputPtr output) { drmmode_output_private_ptr drmmode_output = output->driver_private; drmModeConnectorPtr mode_output = drmmode_output->mode_output; drmmode_ptr drmmode = drmmode_output->drmmode; drmModePropertyPtr drmmode_prop; int i, j, err; drmmode_output->props = calloc(mode_output->count_props, sizeof(drmmode_prop_rec)); if (!drmmode_output->props) return; drmmode_output->num_props = 0; for (i = 0, j = 0; i < mode_output->count_props; i++) { drmmode_prop = drmModeGetProperty(drmmode->fd, mode_output->props[i]); if (drmmode_property_ignore(drmmode_prop)) { drmModeFreeProperty(drmmode_prop); continue; } drmmode_output->props[j].mode_prop = drmmode_prop; drmmode_output->props[j].value = mode_output->prop_values[i]; drmmode_output->num_props++; j++; } for (i = 0; i < drmmode_output->num_props; i++) { drmmode_prop_ptr p = &drmmode_output->props[i]; drmmode_prop = p->mode_prop; if (drmmode_prop->flags & DRM_MODE_PROP_RANGE) { INT32 range[2]; INT32 value = p->value; p->num_atoms = 1; p->atoms = calloc(p->num_atoms, sizeof(Atom)); if (!p->atoms) continue; p->atoms[0] = MakeAtom(drmmode_prop->name, strlen(drmmode_prop->name), TRUE); range[0] = drmmode_prop->values[0]; range[1] = drmmode_prop->values[1]; err = RRConfigureOutputProperty(output->randr_output, p->atoms[0], FALSE, TRUE, drmmode_prop->flags & DRM_MODE_PROP_IMMUTABLE ? TRUE : FALSE, 2, range); if (err != 0) { xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, "RRConfigureOutputProperty error, %d\n", err); } err = RRChangeOutputProperty(output->randr_output, p->atoms[0], XA_INTEGER, 32, PropModeReplace, 1, &value, FALSE, TRUE); if (err != 0) { xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, "RRChangeOutputProperty error, %d\n", err); } } else if (drmmode_prop->flags & DRM_MODE_PROP_ENUM) { p->num_atoms = drmmode_prop->count_enums + 1; p->atoms = calloc(p->num_atoms, sizeof(Atom)); if (!p->atoms) continue; p->atoms[0] = MakeAtom(drmmode_prop->name, strlen(drmmode_prop->name), TRUE); for (j = 1; j <= drmmode_prop->count_enums; j++) { struct drm_mode_property_enum *e = &drmmode_prop->enums[j-1]; p->atoms[j] = MakeAtom(e->name, strlen(e->name), TRUE); } err = RRConfigureOutputProperty(output->randr_output, p->atoms[0], FALSE, FALSE, drmmode_prop->flags & DRM_MODE_PROP_IMMUTABLE ? TRUE : FALSE, p->num_atoms - 1, (INT32 *)&p->atoms[1]); if (err != 0) { xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, "RRConfigureOutputProperty error, %d\n", err); } for (j = 0; j < drmmode_prop->count_enums; j++) if (drmmode_prop->enums[j].value == p->value) break; /* there's always a matching value */ err = RRChangeOutputProperty(output->randr_output, p->atoms[0], XA_ATOM, 32, PropModeReplace, 1, &p->atoms[j+1], FALSE, TRUE); if (err != 0) { xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, "RRChangeOutputProperty error, %d\n", err); } } } } static Bool drmmode_output_set_property(xf86OutputPtr output, Atom property, RRPropertyValuePtr value) { drmmode_output_private_ptr drmmode_output = output->driver_private; drmmode_ptr drmmode = drmmode_output->drmmode; int i; for (i = 0; i < drmmode_output->num_props; i++) { drmmode_prop_ptr p = &drmmode_output->props[i]; if (p->atoms[0] != property) continue; if (p->mode_prop->flags & DRM_MODE_PROP_RANGE) { uint32_t val; if (value->type != XA_INTEGER || value->format != 32 || value->size != 1) return FALSE; val = *(uint32_t *)value->data; drmModeConnectorSetProperty(drmmode->fd, drmmode_output->output_id, p->mode_prop->prop_id, (uint64_t)val); return TRUE; } else if (p->mode_prop->flags & DRM_MODE_PROP_ENUM) { Atom atom; const char *name; int j; if (value->type != XA_ATOM || value->format != 32 || value->size != 1) return FALSE; memcpy(&atom, value->data, 4); name = NameForAtom(atom); /* search for matching name string, then set its value down */ for (j = 0; j < p->mode_prop->count_enums; j++) { if (!strcmp(p->mode_prop->enums[j].name, name)) { drmModeConnectorSetProperty(drmmode->fd, drmmode_output->output_id, p->mode_prop->prop_id, p->mode_prop->enums[j].value); return TRUE; } } } } return TRUE; } static Bool drmmode_output_get_property(xf86OutputPtr output, Atom property) { return TRUE; } static const xf86OutputFuncsRec drmmode_output_funcs = { .dpms = drmmode_output_dpms, .create_resources = drmmode_output_create_resources, .set_property = drmmode_output_set_property, .get_property = drmmode_output_get_property, #if 0 .save = drmmode_crt_save, .restore = drmmode_crt_restore, .mode_fixup = drmmode_crt_mode_fixup, .prepare = drmmode_output_prepare, .mode_set = drmmode_crt_mode_set, .commit = drmmode_output_commit, #endif .detect = drmmode_output_detect, .mode_valid = drmmode_output_mode_valid, .get_modes = drmmode_output_get_modes, .destroy = drmmode_output_destroy }; static int subpixel_conv_table[7] = { 0, SubPixelUnknown, SubPixelHorizontalRGB, SubPixelHorizontalBGR, SubPixelVerticalRGB, SubPixelVerticalBGR, SubPixelNone }; const char *output_names[] = { "None", "VGA", "DVI", "DVI", "DVI", "Composite", "S-video", "LVDS", "CTV", "DIN", "DisplayPort", "HDMI", "HDMI", "TV", "eDP" }; #define NUM_OUTPUT_NAMES (sizeof(output_names) / sizeof(output_names[0])) static xf86OutputPtr find_output(ScrnInfoPtr pScrn, int id) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; drmmode_output_private_ptr drmmode_output; drmmode_output = output->driver_private; if (drmmode_output->output_id == id) return output; } return NULL; } static int parse_path_blob(drmModePropertyBlobPtr path_blob, int *conn_base_id, char **path) { char *conn; char conn_id[5]; int id, len; char *blob_data; if (!path_blob) return -1; blob_data = path_blob->data; /* we only handle MST paths for now */ if (strncmp(blob_data, "mst:", 4)) return -1; conn = strchr(blob_data + 4, '-'); if (!conn) return -1; len = conn - (blob_data + 4); if (len + 1 > 5) return -1; memcpy(conn_id, blob_data + 4, len); conn_id[len] = '\0'; id = strtoul(conn_id, NULL, 10); *conn_base_id = id; *path = conn + 1; return 0; } static void drmmode_create_name(ScrnInfoPtr pScrn, drmModeConnectorPtr koutput, char *name, drmModePropertyBlobPtr path_blob, int *num_dvi, int *num_hdmi) { xf86OutputPtr output; int conn_id; char *extra_path; output = NULL; if (parse_path_blob(path_blob, &conn_id, &extra_path) == 0) output = find_output(pScrn, conn_id); if (output) { snprintf(name, 32, "%s-%s", output->name, extra_path); } else { if (koutput->connector_type >= NUM_OUTPUT_NAMES) snprintf(name, 32, "Unknown%d-%d", koutput->connector_type, koutput->connector_type_id - 1); #ifdef RADEON_PIXMAP_SHARING else if (pScrn->is_gpu) snprintf(name, 32, "%s-%d-%d", output_names[koutput->connector_type], pScrn->scrnIndex - GPU_SCREEN_OFFSET + 1, koutput->connector_type_id - 1); #endif else { /* need to do smart conversion here for compat with non-kms ATI driver */ if (koutput->connector_type_id == 1) { switch(koutput->connector_type) { case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_DVIA: snprintf(name, 32, "%s-%d", output_names[koutput->connector_type], *num_dvi); (*num_dvi)++; break; case DRM_MODE_CONNECTOR_HDMIA: case DRM_MODE_CONNECTOR_HDMIB: snprintf(name, 32, "%s-%d", output_names[koutput->connector_type], *num_hdmi); (*num_hdmi)++; break; case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_DisplayPort: snprintf(name, 32, "%s-%d", output_names[koutput->connector_type], koutput->connector_type_id - 1); break; default: snprintf(name, 32, "%s", output_names[koutput->connector_type]); break; } } else { snprintf(name, 32, "%s-%d", output_names[koutput->connector_type], koutput->connector_type_id - 1); } } } } static unsigned int drmmode_output_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, drmModeResPtr mode_res, int num, int *num_dvi, int *num_hdmi, int dynamic) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); xf86OutputPtr output; drmModeConnectorPtr koutput; drmModeEncoderPtr *kencoders = NULL; drmmode_output_private_ptr drmmode_output; drmModePropertyPtr props; drmModePropertyBlobPtr path_blob = NULL; char name[32]; int i; const char *s; koutput = drmModeGetConnector(drmmode->fd, mode_res->connectors[num]); if (!koutput) return 0; for (i = 0; i < koutput->count_props; i++) { props = drmModeGetProperty(drmmode->fd, koutput->props[i]); if (props && (props->flags & DRM_MODE_PROP_BLOB)) { if (!strcmp(props->name, "PATH")) { path_blob = drmModeGetPropertyBlob(drmmode->fd, koutput->prop_values[i]); drmModeFreeProperty(props); break; } drmModeFreeProperty(props); } } kencoders = calloc(sizeof(drmModeEncoderPtr), koutput->count_encoders); if (!kencoders) { goto out_free_encoders; } for (i = 0; i < koutput->count_encoders; i++) { kencoders[i] = drmModeGetEncoder(drmmode->fd, koutput->encoders[i]); if (!kencoders[i]) { goto out_free_encoders; } } drmmode_create_name(pScrn, koutput, name, path_blob, num_dvi, num_hdmi); if (path_blob) drmModeFreePropertyBlob(path_blob); if (path_blob && dynamic) { /* See if we have an output with this name already * and hook stuff up. */ for (i = 0; i < xf86_config->num_output; i++) { output = xf86_config->output[i]; if (strncmp(output->name, name, 32)) continue; drmmode_output = output->driver_private; drmmode_output->output_id = mode_res->connectors[num]; drmmode_output->mode_output = koutput; for (i = 0; i < koutput->count_encoders; i++) drmModeFreeEncoder(kencoders[i]); free(kencoders); return 0; } } if (xf86IsEntityShared(pScrn->entityList[0])) { if ((s = xf86GetOptValString(info->Options, OPTION_ZAPHOD_HEADS))) { if (!RADEONZaphodStringMatches(pScrn, s, name)) goto out_free_encoders; } else { if (!info->IsSecondary && (num != 0)) goto out_free_encoders; else if (info->IsSecondary && (num != 1)) goto out_free_encoders; } } output = xf86OutputCreate (pScrn, &drmmode_output_funcs, name); if (!output) { goto out_free_encoders; } drmmode_output = calloc(sizeof(drmmode_output_private_rec), 1); if (!drmmode_output) { xf86OutputDestroy(output); goto out_free_encoders; } drmmode_output->output_id = mode_res->connectors[num]; drmmode_output->mode_output = koutput; drmmode_output->mode_encoders = kencoders; drmmode_output->drmmode = drmmode; output->mm_width = koutput->mmWidth; output->mm_height = koutput->mmHeight; output->subpixel_order = subpixel_conv_table[koutput->subpixel]; output->interlaceAllowed = TRUE; output->doubleScanAllowed = TRUE; output->driver_private = drmmode_output; output->possible_crtcs = 0xffffffff; for (i = 0; i < koutput->count_encoders; i++) { output->possible_crtcs &= kencoders[i]->possible_crtcs; } /* work out the possible clones later */ output->possible_clones = 0; for (i = 0; i < koutput->count_props; i++) { props = drmModeGetProperty(drmmode->fd, koutput->props[i]); if (props && (props->flags & DRM_MODE_PROP_ENUM)) { if (!strcmp(props->name, "DPMS")) { drmmode_output->dpms_enum_id = koutput->props[i]; drmModeFreeProperty(props); break; } drmModeFreeProperty(props); } } if (dynamic) { output->randr_output = RROutputCreate(xf86ScrnToScreen(pScrn), output->name, strlen(output->name), output); drmmode_output_create_resources(output); } return 1; out_free_encoders: if (kencoders){ for (i = 0; i < koutput->count_encoders; i++) drmModeFreeEncoder(kencoders[i]); free(kencoders); } drmModeFreeConnector(koutput); return 0; } uint32_t find_clones(ScrnInfoPtr scrn, xf86OutputPtr output) { drmmode_output_private_ptr drmmode_output = output->driver_private, clone_drmout; int i; xf86OutputPtr clone_output; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); int index_mask = 0; if (drmmode_output->enc_clone_mask == 0) return index_mask; for (i = 0; i < xf86_config->num_output; i++) { clone_output = xf86_config->output[i]; clone_drmout = clone_output->driver_private; if (output == clone_output) continue; if (clone_drmout->enc_mask == 0) continue; if (drmmode_output->enc_clone_mask == clone_drmout->enc_mask) index_mask |= (1 << i); } return index_mask; } static void drmmode_clones_init(ScrnInfoPtr scrn, drmmode_ptr drmmode, drmModeResPtr mode_res) { int i, j; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; drmmode_output_private_ptr drmmode_output; drmmode_output = output->driver_private; drmmode_output->enc_clone_mask = 0xff; /* and all the possible encoder clones for this output together */ for (j = 0; j < drmmode_output->mode_output->count_encoders; j++) { int k; for (k = 0; k < mode_res->count_encoders; k++) { if (mode_res->encoders[k] == drmmode_output->mode_encoders[j]->encoder_id) drmmode_output->enc_mask |= (1 << k); } drmmode_output->enc_clone_mask &= drmmode_output->mode_encoders[j]->possible_clones; } } for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; output->possible_clones = find_clones(scrn, output); } } /* returns height alignment in pixels */ int drmmode_get_height_align(ScrnInfoPtr scrn, uint32_t tiling) { RADEONInfoPtr info = RADEONPTR(scrn); int height_align = 1; if (info->ChipFamily >= CHIP_FAMILY_R600) { if (tiling & RADEON_TILING_MACRO) height_align = info->num_channels * 8; else if (tiling & RADEON_TILING_MICRO) height_align = 8; else height_align = 8; } else { if (tiling & RADEON_TILING_MICRO_SQUARE) height_align = 32; else if (tiling) height_align = 16; else height_align = 1; } return height_align; } /* returns pitch alignment in pixels */ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling) { RADEONInfoPtr info = RADEONPTR(scrn); int pitch_align = 1; if (info->ChipFamily >= CHIP_FAMILY_R600) { if (tiling & RADEON_TILING_MACRO) { /* general surface requirements */ pitch_align = MAX(info->num_banks, (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8; /* further restrictions for scanout */ pitch_align = MAX(info->num_banks * 8, pitch_align); } else if (tiling & RADEON_TILING_MICRO) { /* general surface requirements */ pitch_align = MAX(8, (info->group_bytes / (8 * bpe))); /* further restrictions for scanout */ pitch_align = MAX(info->group_bytes / bpe, pitch_align); } else { if (info->have_tiling_info) /* linear aligned requirements */ pitch_align = MAX(64, info->group_bytes / bpe); else /* default to 512 elements if we don't know the real * group size otherwise the kernel may reject the CS * if the group sizes don't match as the pitch won't * be aligned properly. */ pitch_align = 512; } } else { /* general surface requirements */ if (tiling) pitch_align = 256 / bpe; else pitch_align = 64; } return pitch_align; } /* returns base alignment in bytes */ int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling) { RADEONInfoPtr info = RADEONPTR(scrn); int pixel_align = drmmode_get_pitch_align(scrn, bpe, tiling); int height_align = drmmode_get_height_align(scrn, tiling); int base_align = RADEON_GPU_PAGE_SIZE; if (info->ChipFamily >= CHIP_FAMILY_R600) { if (tiling & RADEON_TILING_MACRO) base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe, pixel_align * bpe * height_align); else { if (info->have_tiling_info) base_align = info->group_bytes; else /* default to 512 if we don't know the real * group size otherwise the kernel may reject the CS * if the group sizes don't match as the base won't * be aligned properly. */ base_align = 512; } } return base_align; } static Bool drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[0]->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; RADEONInfoPtr info = RADEONPTR(scrn); struct radeon_bo *old_front = NULL; Bool ret; ScreenPtr screen = xf86ScrnToScreen(scrn); uint32_t old_fb_id; int i, pitch, old_width, old_height, old_pitch; uint32_t screen_size; int cpp = info->pixel_bytes; struct radeon_bo *front_bo; struct radeon_surface surface; struct radeon_surface *psurface; uint32_t tiling_flags = 0, base_align; PixmapPtr ppix = screen->GetScreenPixmap(screen); void *fb_shadow; xRectangle rect; Bool force; GCPtr gc; if (scrn->virtualX == width && scrn->virtualY == height) return TRUE; front_bo = info->front_bo; radeon_cs_flush_indirect(scrn); if (front_bo) radeon_bo_wait(front_bo); if (info->allowColorTiling && !info->shadow_primary) { if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->allowColorTiling2D) { tiling_flags |= RADEON_TILING_MACRO; } else { tiling_flags |= RADEON_TILING_MICRO; } } else tiling_flags |= RADEON_TILING_MACRO; } pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp; height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags)); screen_size = RADEON_ALIGN(pitch * height, RADEON_GPU_PAGE_SIZE); base_align = 4096; if (info->ChipFamily >= CHIP_FAMILY_R600) { memset(&surface, 0, sizeof(struct radeon_surface)); surface.npix_x = width; surface.npix_y = height; surface.npix_z = 1; surface.blk_w = 1; surface.blk_h = 1; surface.blk_d = 1; surface.array_size = 1; surface.last_level = 0; surface.bpe = cpp; surface.nsamples = 1; surface.flags = RADEON_SURF_SCANOUT; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); if (tiling_flags & RADEON_TILING_MICRO) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); } if (tiling_flags & RADEON_TILING_MACRO) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } if (radeon_surface_best(info->surf_man, &surface)) { return FALSE; } if (radeon_surface_init(info->surf_man, &surface)) { return FALSE; } screen_size = surface.bo_size; base_align = surface.bo_alignment; pitch = surface.level[0].pitch_bytes; tiling_flags = 0; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling_flags |= RADEON_TILING_MACRO; tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; if (surface.tile_split) tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; break; case RADEON_SURF_MODE_1D: tiling_flags |= RADEON_TILING_MICRO; break; default: break; } info->front_surface = surface; } xf86DrvMsg(scrn->scrnIndex, X_INFO, "Allocate new frame buffer %dx%d stride %d\n", width, height, pitch / cpp); old_width = scrn->virtualX; old_height = scrn->virtualY; old_pitch = scrn->displayWidth; old_fb_id = drmmode->fb_id; old_front = info->front_bo; scrn->virtualX = width; scrn->virtualY = height; scrn->displayWidth = pitch / cpp; info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align, info->shadow_primary ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM, 0); if (!info->front_bo) goto fail; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (cpp) { case 4: tiling_flags |= RADEON_TILING_SWAP_32BIT; break; case 2: tiling_flags |= RADEON_TILING_SWAP_16BIT; break; } if (info->ChipFamily < CHIP_FAMILY_R600 && info->r600_shadow_fb && tiling_flags) tiling_flags |= RADEON_TILING_SURFACE; #endif if (tiling_flags) radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth, scrn->bitsPerPixel, pitch, info->front_bo->handle, &drmmode->fb_id); if (ret) goto fail; if (!info->r600_shadow_fb) { radeon_set_pixmap_bo(ppix, info->front_bo); psurface = radeon_get_pixmap_surface(ppix); *psurface = info->front_surface; screen->ModifyPixmapHeader(ppix, width, height, -1, -1, pitch, NULL); } else { if (radeon_bo_map(info->front_bo, 1)) goto fail; fb_shadow = calloc(1, screen_size); if (fb_shadow == NULL) goto fail; free(info->fb_shadow); info->fb_shadow = fb_shadow; screen->ModifyPixmapHeader(ppix, width, height, -1, -1, pitch, info->fb_shadow); } #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,9,99,1,0) scrn->pixmapPrivate.ptr = ppix->devPrivate.ptr; #endif if (info->use_glamor) radeon_glamor_create_screen_resources(scrn->pScreen); /* Clear new buffer */ gc = GetScratchGC(ppix->drawable.depth, scrn->pScreen); force = info->accel_state->force; info->accel_state->force = TRUE; ValidateGC(&ppix->drawable, gc); rect.x = 0; rect.y = 0; rect.width = width; rect.height = height; (*gc->ops->PolyFillRect)(&ppix->drawable, gc, 1, &rect); FreeScratchGC(gc); info->accel_state->force = force; radeon_cs_flush_indirect(scrn); radeon_bo_wait(info->front_bo); for (i = 0; i < xf86_config->num_crtc; i++) { xf86CrtcPtr crtc = xf86_config->crtc[i]; if (!crtc->enabled) continue; drmmode_set_mode_major(crtc, &crtc->mode, crtc->rotation, crtc->x, crtc->y); } if (old_fb_id) drmModeRmFB(drmmode->fd, old_fb_id); if (old_front) radeon_bo_unref(old_front); radeon_kms_update_vram_limit(scrn, screen_size); return TRUE; fail: if (info->front_bo) radeon_bo_unref(info->front_bo); info->front_bo = old_front; scrn->virtualX = old_width; scrn->virtualY = old_height; scrn->displayWidth = old_pitch; drmmode->fb_id = old_fb_id; return FALSE; } static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = { drmmode_xf86crtc_resize }; static void drmmode_flip_free(drmmode_flipevtcarrier_ptr flipcarrier) { drmmode_flipdata_ptr flipdata = flipcarrier->flipdata; free(flipcarrier); if (--flipdata->flip_count > 0) return; free(flipdata); } static void drmmode_flip_abort(ScrnInfoPtr scrn, void *event_data) { drmmode_flipevtcarrier_ptr flipcarrier = event_data; drmmode_flipdata_ptr flipdata = flipcarrier->flipdata; if (flipdata->flip_count == 1) flipdata->abort(scrn, flipdata->event_data); drmmode_flip_free(flipcarrier); } static void drmmode_flip_handler(ScrnInfoPtr scrn, uint32_t frame, uint64_t usec, void *event_data) { drmmode_flipevtcarrier_ptr flipcarrier = event_data; drmmode_flipdata_ptr flipdata = flipcarrier->flipdata; /* Is this the event whose info shall be delivered to higher level? */ if (flipcarrier->dispatch_me) { /* Yes: Cache msc, ust for later delivery. */ flipdata->fe_frame = frame; flipdata->fe_usec = usec; } if (flipdata->flip_count == 1) { /* Deliver cached msc, ust from reference crtc to flip event handler */ if (flipdata->event_data) flipdata->handler(scrn, flipdata->fe_frame, flipdata->fe_usec, flipdata->event_data); /* Release framebuffer */ drmModeRmFB(flipdata->drmmode->fd, flipdata->old_fb_id); } drmmode_flip_free(flipcarrier); } static void drm_wakeup_handler(pointer data, int err, pointer p) { drmmode_ptr drmmode = data; fd_set *read_mask = p; if (err >= 0 && FD_ISSET(drmmode->fd, read_mask)) { drmHandleEvent(drmmode->fd, &drmmode->event_context); } } Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); int i, num_dvi = 0, num_hdmi = 0; drmModeResPtr mode_res; unsigned int crtcs_needed = 0; xf86CrtcConfigInit(pScrn, &drmmode_xf86crtc_config_funcs); drmmode->scrn = pScrn; drmmode->cpp = cpp; mode_res = drmModeGetResources(drmmode->fd); if (!mode_res) return FALSE; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing outputs ...\n"); for (i = 0; i < mode_res->count_connectors; i++) crtcs_needed += drmmode_output_init(pScrn, drmmode, mode_res, i, &num_dvi, &num_hdmi, 0); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "%d crtcs needed for screen.\n", crtcs_needed); drmmode->count_crtcs = mode_res->count_crtcs; xf86CrtcSetSizeRange(pScrn, 320, 200, mode_res->max_width, mode_res->max_height); for (i = 0; i < mode_res->count_crtcs; i++) if (!xf86IsEntityShared(pScrn->entityList[0]) || (crtcs_needed && !(pRADEONEnt->assigned_crtcs & (1 << i)))) crtcs_needed -= drmmode_crtc_init(pScrn, drmmode, mode_res, i); /* All ZaphodHeads outputs provided with matching crtcs? */ if (xf86IsEntityShared(pScrn->entityList[0]) && (crtcs_needed > 0)) xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "%d ZaphodHeads crtcs unavailable. Some outputs will stay off.\n", crtcs_needed); /* workout clones */ drmmode_clones_init(pScrn, drmmode, mode_res); #ifdef RADEON_PIXMAP_SHARING xf86ProviderSetup(pScrn, NULL, "radeon"); #endif xf86InitialConfiguration(pScrn, TRUE); drmmode->event_context.version = DRM_EVENT_CONTEXT_VERSION; drmmode->event_context.vblank_handler = radeon_drm_queue_handler; drmmode->event_context.page_flip_handler = radeon_drm_queue_handler; drmModeFreeResources(mode_res); return TRUE; } void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); if (info->dri2.pKernelDRMVersion->version_minor < 4) return; info->drmmode_inited = TRUE; if (pRADEONEnt->fd_wakeup_registered != serverGeneration) { AddGeneralSocket(drmmode->fd); RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, drm_wakeup_handler, drmmode); pRADEONEnt->fd_wakeup_registered = serverGeneration; pRADEONEnt->fd_wakeup_ref = 1; } else pRADEONEnt->fd_wakeup_ref++; } void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); if (info->dri2.pKernelDRMVersion->version_minor < 4 || !info->drmmode_inited) return; if (pRADEONEnt->fd_wakeup_registered == serverGeneration && !--pRADEONEnt->fd_wakeup_ref) { RemoveGeneralSocket(drmmode->fd); RemoveBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, drm_wakeup_handler, drmmode); } } Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr) { drmmode->bufmgr = bufmgr; return TRUE; } void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, struct radeon_bo *bo) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); xf86CrtcPtr crtc = xf86_config->crtc[id]; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_crtc->cursor_bo = bo; } void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y) { xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; if (crtc && crtc->enabled) { drmmode_set_mode_major(crtc, &crtc->mode, crtc->rotation, x, y); } } Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode, Bool set_hw) { xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); int c; for (c = 0; c < config->num_crtc; c++) { xf86CrtcPtr crtc = config->crtc[c]; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; xf86OutputPtr output = NULL; int o; /* Skip disabled CRTCs */ if (!crtc->enabled) { if (set_hw) { drmmode_do_crtc_dpms(crtc, DPMSModeOff); drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, 0, 0, 0, NULL, 0, NULL); } continue; } if (config->output[config->compat_output]->crtc == crtc) output = config->output[config->compat_output]; else { for (o = 0; o < config->num_output; o++) if (config->output[o]->crtc == crtc) { output = config->output[o]; break; } } /* paranoia */ if (!output) continue; /* Mark that we'll need to re-set the mode for sure */ memset(&crtc->mode, 0, sizeof(crtc->mode)); if (!crtc->desiredMode.CrtcHDisplay) { DisplayModePtr mode = xf86OutputFindClosestMode (output, pScrn->currentMode); if (!mode) return FALSE; crtc->desiredMode = *mode; crtc->desiredRotation = RR_Rotate_0; crtc->desiredX = 0; crtc->desiredY = 0; } if (set_hw) { if (!crtc->funcs->set_mode_major(crtc, &crtc->desiredMode, crtc->desiredRotation, crtc->desiredX, crtc->desiredY)) return FALSE; } else { crtc->mode = crtc->desiredMode; crtc->rotation = crtc->desiredRotation; crtc->x = crtc->desiredX; crtc->y = crtc->desiredY; } } return TRUE; } static void drmmode_load_palette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors, VisualPtr pVisual) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); uint16_t lut_r[256], lut_g[256], lut_b[256]; int index, j, i; int c; for (c = 0; c < xf86_config->num_crtc; c++) { xf86CrtcPtr crtc = xf86_config->crtc[c]; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; for (i = 0 ; i < 256; i++) { lut_r[i] = drmmode_crtc->lut_r[i] << 6; lut_g[i] = drmmode_crtc->lut_g[i] << 6; lut_b[i] = drmmode_crtc->lut_b[i] << 6; } switch(pScrn->depth) { case 15: for (i = 0; i < numColors; i++) { index = indices[i]; for (j = 0; j < 8; j++) { lut_r[index * 8 + j] = colors[index].red << 6; lut_g[index * 8 + j] = colors[index].green << 6; lut_b[index * 8 + j] = colors[index].blue << 6; } } break; case 16: for (i = 0; i < numColors; i++) { index = indices[i]; if (i <= 31) { for (j = 0; j < 8; j++) { lut_r[index * 8 + j] = colors[index].red << 6; lut_b[index * 8 + j] = colors[index].blue << 6; } } for (j = 0; j < 4; j++) { lut_g[index * 4 + j] = colors[index].green << 6; } } break; default: for (i = 0; i < numColors; i++) { index = indices[i]; lut_r[index] = colors[index].red << 6; lut_g[index] = colors[index].green << 6; lut_b[index] = colors[index].blue << 6; } break; } /* Make the change through RandR */ if (crtc->randr_crtc) RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); else crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); } } Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); if (xf86_config->num_crtc) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing kms color map\n"); if (!miCreateDefColormap(pScreen)) return FALSE; /* all radeons support 10 bit CLUTs */ if (!xf86HandleColormaps(pScreen, 256, 10, drmmode_load_palette, NULL, CMAP_PALETTED_TRUECOLOR #if 0 /* This option messes up text mode! (eich@suse.de) */ | CMAP_LOAD_EVEN_IF_OFFSCREEN #endif | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; } return TRUE; } void radeon_mode_hotplug(ScrnInfoPtr scrn, drmmode_ptr drmmode) { xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); drmModeResPtr mode_res; int i, j; Bool found; Bool changed = FALSE; mode_res = drmModeGetResources(drmmode->fd); if (!mode_res) goto out; restart_destroy: for (i = 0; i < config->num_output; i++) { xf86OutputPtr output = config->output[i]; drmmode_output_private_ptr drmmode_output = output->driver_private; found = FALSE; for (j = 0; j < mode_res->count_connectors; j++) { if (mode_res->connectors[j] == drmmode_output->output_id) { found = TRUE; break; } } if (found) continue; drmModeFreeConnector(drmmode_output->mode_output); drmmode_output->mode_output = NULL; drmmode_output->output_id = -1; changed = TRUE; if (drmmode->delete_dp_12_displays) { RROutputDestroy(output->randr_output); xf86OutputDestroy(output); goto restart_destroy; } } /* find new output ids we don't have outputs for */ for (i = 0; i < mode_res->count_connectors; i++) { found = FALSE; for (j = 0; j < config->num_output; j++) { xf86OutputPtr output = config->output[j]; drmmode_output_private_ptr drmmode_output; drmmode_output = output->driver_private; if (mode_res->connectors[i] == drmmode_output->output_id) { found = TRUE; break; } } if (found) continue; changed = TRUE; drmmode_output_init(scrn, drmmode, mode_res, i, NULL, NULL, 1); } if (changed) { RRSetChanged(xf86ScrnToScreen(scrn)); RRTellChanged(xf86ScrnToScreen(scrn)); } drmModeFreeResources(mode_res); out: RRGetInfo(xf86ScrnToScreen(scrn), TRUE); } #ifdef HAVE_LIBUDEV static void drmmode_handle_uevents(int fd, void *closure) { drmmode_ptr drmmode = closure; ScrnInfoPtr scrn = drmmode->scrn; struct udev_device *dev; dev = udev_monitor_receive_device(drmmode->uevent_monitor); if (!dev) return; radeon_mode_hotplug(scrn, drmmode); udev_device_unref(dev); } #endif void drmmode_uevent_init(ScrnInfoPtr scrn, drmmode_ptr drmmode) { #ifdef HAVE_LIBUDEV struct udev *u; struct udev_monitor *mon; u = udev_new(); if (!u) return; mon = udev_monitor_new_from_netlink(u, "udev"); if (!mon) { udev_unref(u); return; } if (udev_monitor_filter_add_match_subsystem_devtype(mon, "drm", "drm_minor") < 0 || udev_monitor_enable_receiving(mon) < 0) { udev_monitor_unref(mon); udev_unref(u); return; } drmmode->uevent_handler = xf86AddGeneralHandler(udev_monitor_get_fd(mon), drmmode_handle_uevents, drmmode); drmmode->uevent_monitor = mon; #endif } void drmmode_uevent_fini(ScrnInfoPtr scrn, drmmode_ptr drmmode) { #ifdef HAVE_LIBUDEV if (drmmode->uevent_handler) { struct udev *u = udev_monitor_get_udev(drmmode->uevent_monitor); xf86RemoveGeneralHandler(drmmode->uevent_handler); udev_monitor_unref(drmmode->uevent_monitor); udev_unref(u); } #endif } Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr client, uint32_t new_front_handle, uint64_t id, void *data, int ref_crtc_hw_id, radeon_drm_handler_proc handler, radeon_drm_abort_proc abort) { RADEONInfoPtr info = RADEONPTR(scrn); xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); drmmode_crtc_private_ptr drmmode_crtc = config->crtc[0]->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; unsigned int pitch; int i; uint32_t tiling_flags = 0; int height; drmmode_flipdata_ptr flipdata; drmmode_flipevtcarrier_ptr flipcarrier = NULL; struct radeon_drm_queue_entry *drm_queue = NULL; if (info->allowColorTiling) { if (info->ChipFamily >= CHIP_FAMILY_R600) tiling_flags |= RADEON_TILING_MICRO; else tiling_flags |= RADEON_TILING_MACRO; } pitch = RADEON_ALIGN(scrn->displayWidth, drmmode_get_pitch_align(scrn, info->pixel_bytes, tiling_flags)) * info->pixel_bytes; height = RADEON_ALIGN(scrn->virtualY, drmmode_get_height_align(scrn, tiling_flags)); if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { pitch = info->front_surface.level[0].pitch_bytes; } flipdata = calloc(1, sizeof(drmmode_flipdata_rec)); if (!flipdata) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue: data alloc failed.\n"); goto error; } /* * Create a new handle for the back buffer */ flipdata->old_fb_id = drmmode->fb_id; if (drmModeAddFB(drmmode->fd, scrn->virtualX, height, scrn->depth, scrn->bitsPerPixel, pitch, new_front_handle, &drmmode->fb_id)) goto error; /* * Queue flips on all enabled CRTCs * Note that if/when we get per-CRTC buffers, we'll have to update this. * Right now it assumes a single shared fb across all CRTCs, with the * kernel fixing up the offset of each CRTC as necessary. * * Also, flips queued on disabled or incorrectly configured displays * may never complete; this is a configuration error. */ flipdata->event_data = data; flipdata->drmmode = drmmode; flipdata->handler = handler; flipdata->abort = abort; for (i = 0; i < config->num_crtc; i++) { if (!config->crtc[i]->enabled) continue; flipdata->flip_count++; drmmode_crtc = config->crtc[i]->driver_private; flipcarrier = calloc(1, sizeof(drmmode_flipevtcarrier_rec)); if (!flipcarrier) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue: carrier alloc failed.\n"); goto error; } /* Only the reference crtc will finally deliver its page flip * completion event. All other crtc's events will be discarded. */ flipcarrier->dispatch_me = (drmmode_crtc->hw_id == ref_crtc_hw_id); flipcarrier->flipdata = flipdata; drm_queue = radeon_drm_queue_alloc(scrn, client, id, flipcarrier, drmmode_flip_handler, drmmode_flip_abort); if (!drm_queue) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Allocating DRM queue event entry failed.\n"); goto error; } if (drmModePageFlip(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, drmmode->fb_id, DRM_MODE_PAGE_FLIP_EVENT, drm_queue)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed: %s\n", strerror(errno)); goto error; } flipcarrier = NULL; drm_queue = NULL; } if (flipdata->flip_count > 0) return TRUE; error: if (flipdata && flipdata->flip_count <= 1) { drmModeRmFB(drmmode->fd, drmmode->fb_id); drmmode->fb_id = flipdata->old_fb_id; } if (drm_queue) radeon_drm_abort_entry(drm_queue); else if (flipcarrier) drmmode_flip_abort(scrn, flipcarrier); else if (flipdata && flipdata->flip_count <= 1) free(flipdata); xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Page flip failed: %s\n", strerror(errno)); return FALSE; } xserver-xorg-video-ati-7.5.0+git20150819/src/drmmode_display.h000066400000000000000000000120631256524674500236240ustar00rootroot00000000000000/* * Copyright © 2007 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifndef DRMMODE_DISPLAY_H #define DRMMODE_DISPLAY_H #include "xf86drmMode.h" #ifdef HAVE_LIBUDEV #include "libudev.h" #endif #include "radeon_drm_queue.h" #include "radeon_probe.h" #ifndef DRM_CAP_TIMESTAMP_MONOTONIC #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 #endif typedef struct { int fd; unsigned fb_id; drmModeFBPtr mode_fb; int cpp; struct radeon_bo_manager *bufmgr; ScrnInfoPtr scrn; #ifdef HAVE_LIBUDEV struct udev_monitor *uevent_monitor; InputHandlerProc uevent_handler; #endif drmEventContext event_context; int count_crtcs; Bool delete_dp_12_displays; Bool dri2_flipping; Bool present_flipping; } drmmode_rec, *drmmode_ptr; typedef struct { drmmode_ptr drmmode; unsigned old_fb_id; int flip_count; void *event_data; unsigned int fe_frame; uint64_t fe_usec; radeon_drm_handler_proc handler; radeon_drm_abort_proc abort; } drmmode_flipdata_rec, *drmmode_flipdata_ptr; typedef struct { drmmode_flipdata_ptr flipdata; Bool dispatch_me; } drmmode_flipevtcarrier_rec, *drmmode_flipevtcarrier_ptr; struct drmmode_scanout { struct radeon_bo *bo; PixmapPtr pixmap; DamagePtr damage; unsigned fb_id; int width, height; }; typedef struct { drmmode_ptr drmmode; drmModeCrtcPtr mode_crtc; int hw_id; struct radeon_bo *cursor_bo; struct drmmode_scanout rotate; struct drmmode_scanout scanout[2]; unsigned scanout_id; Bool scanout_update_pending; int dpms_mode; CARD64 dpms_last_ust; uint32_t dpms_last_seq; int dpms_last_fps; uint32_t interpolated_vblanks; uint16_t lut_r[256], lut_g[256], lut_b[256]; int prime_pixmap_x; /* Modeset needed for DPMS on */ Bool need_modeset; } drmmode_crtc_private_rec, *drmmode_crtc_private_ptr; typedef struct { drmModePropertyPtr mode_prop; uint64_t value; int num_atoms; /* if range prop, num_atoms == 1; if enum prop, num_atoms == num_enums + 1 */ Atom *atoms; } drmmode_prop_rec, *drmmode_prop_ptr; typedef struct { drmmode_ptr drmmode; int output_id; drmModeConnectorPtr mode_output; drmModeEncoderPtr *mode_encoders; drmModePropertyBlobPtr edid_blob; int dpms_enum_id; int num_props; drmmode_prop_ptr props; int enc_mask; int enc_clone_mask; } drmmode_output_private_rec, *drmmode_output_private_ptr; extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp); extern void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode); extern void drmmode_fini(ScrnInfoPtr pScrn, drmmode_ptr drmmode); extern Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr); extern void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, struct radeon_bo *bo); void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y); extern Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode, Bool set_hw); #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 extern void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode); #endif extern Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn); extern void drmmode_scanout_free(ScrnInfoPtr scrn); extern void drmmode_uevent_init(ScrnInfoPtr scrn, drmmode_ptr drmmode); extern void drmmode_uevent_fini(ScrnInfoPtr scrn, drmmode_ptr drmmode); extern int drmmode_get_crtc_id(xf86CrtcPtr crtc); extern int drmmode_get_height_align(ScrnInfoPtr scrn, uint32_t tiling); extern int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling); extern int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling); Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr client, uint32_t new_front_handle, uint64_t id, void *data, int ref_crtc_hw_id, radeon_drm_handler_proc handler, radeon_drm_abort_proc abort); int drmmode_crtc_get_ust_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc); int drmmode_get_current_ust(int drm_fd, CARD64 *ust); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_accel.c000066400000000000000000001325521256524674500235620ustar00rootroot00000000000000/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include #include "radeon.h" #include "evergreen_shader.h" #include "radeon_reg.h" #include "evergreen_reg.h" #include "evergreen_state.h" #include "radeon_vbo.h" #include "radeon_exa_shared.h" static const uint32_t EVERGREEN_ROP[16] = { RADEON_ROP3_ZERO, /* GXclear */ RADEON_ROP3_DSa, /* Gxand */ RADEON_ROP3_SDna, /* GXandReverse */ RADEON_ROP3_S, /* GXcopy */ RADEON_ROP3_DSna, /* GXandInverted */ RADEON_ROP3_D, /* GXnoop */ RADEON_ROP3_DSx, /* GXxor */ RADEON_ROP3_DSo, /* GXor */ RADEON_ROP3_DSon, /* GXnor */ RADEON_ROP3_DSxn, /* GXequiv */ RADEON_ROP3_Dn, /* GXinvert */ RADEON_ROP3_SDno, /* GXorReverse */ RADEON_ROP3_Sn, /* GXcopyInverted */ RADEON_ROP3_DSno, /* GXorInverted */ RADEON_ROP3_DSan, /* GXnand */ RADEON_ROP3_ONE, /* GXset */ }; void evergreen_start_3d(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(3); PACK3(IT_CONTEXT_CONTROL, 2); E32(0x80000000); E32(0x80000000); END_BATCH(); } unsigned eg_tile_split(unsigned tile_split) { switch (tile_split) { case 64: tile_split = 0; break; case 128: tile_split = 1; break; case 256: tile_split = 2; break; case 512: tile_split = 3; break; default: case 1024: tile_split = 4; break; case 2048: tile_split = 5; break; case 4096: tile_split = 6; break; } return tile_split; } static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect) { switch (macro_tile_aspect) { default: case 1: macro_tile_aspect = 0; break; case 2: macro_tile_aspect = 1; break; case 4: macro_tile_aspect = 2; break; case 8: macro_tile_aspect = 3; break; } return macro_tile_aspect; } static unsigned eg_bank_wh(unsigned bankwh) { switch (bankwh) { default: case 1: bankwh = 0; break; case 2: bankwh = 1; break; case 4: bankwh = 2; break; case 8: bankwh = 3; break; } return bankwh; } static unsigned eg_nbanks(unsigned nbanks) { switch (nbanks) { default: case 2: nbanks = 0; break; case 4: nbanks = 1; break; case 8: nbanks = 2; break; case 16: nbanks = 3; break; } return nbanks; } /* * Setup of functional groups */ // asic stack/thread/gpr limits - need to query the drm static void evergreen_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf) { uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; uint32_t sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; uint32_t sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; RADEONInfoPtr info = RADEONPTR(pScrn); if ((info->ChipFamily == CHIP_FAMILY_CEDAR) || (info->ChipFamily == CHIP_FAMILY_PALM) || (info->ChipFamily == CHIP_FAMILY_SUMO) || (info->ChipFamily == CHIP_FAMILY_SUMO2) || (info->ChipFamily == CHIP_FAMILY_CAICOS)) sq_config = 0; else sq_config = VC_ENABLE_bit; sq_config |= (EXPORT_SRC_C_bit | (sq_conf->cs_prio << CS_PRIO_shift) | (sq_conf->ls_prio << LS_PRIO_shift) | (sq_conf->hs_prio << HS_PRIO_shift) | (sq_conf->ps_prio << PS_PRIO_shift) | (sq_conf->vs_prio << VS_PRIO_shift) | (sq_conf->gs_prio << GS_PRIO_shift) | (sq_conf->es_prio << ES_PRIO_shift)); sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) | (sq_conf->num_vs_gprs << NUM_VS_GPRS_shift) | (sq_conf->num_temp_gprs << NUM_CLAUSE_TEMP_GPRS_shift)); sq_gpr_resource_mgmt_2 = ((sq_conf->num_gs_gprs << NUM_GS_GPRS_shift) | (sq_conf->num_es_gprs << NUM_ES_GPRS_shift)); sq_gpr_resource_mgmt_3 = ((sq_conf->num_hs_gprs << NUM_HS_GPRS_shift) | (sq_conf->num_ls_gprs << NUM_LS_GPRS_shift)); sq_thread_resource_mgmt = ((sq_conf->num_ps_threads << NUM_PS_THREADS_shift) | (sq_conf->num_vs_threads << NUM_VS_THREADS_shift) | (sq_conf->num_gs_threads << NUM_GS_THREADS_shift) | (sq_conf->num_es_threads << NUM_ES_THREADS_shift)); sq_thread_resource_mgmt_2 = ((sq_conf->num_hs_threads << NUM_HS_THREADS_shift) | (sq_conf->num_ls_threads << NUM_LS_THREADS_shift)); sq_stack_resource_mgmt_1 = ((sq_conf->num_ps_stack_entries << NUM_PS_STACK_ENTRIES_shift) | (sq_conf->num_vs_stack_entries << NUM_VS_STACK_ENTRIES_shift)); sq_stack_resource_mgmt_2 = ((sq_conf->num_gs_stack_entries << NUM_GS_STACK_ENTRIES_shift) | (sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift)); sq_stack_resource_mgmt_3 = ((sq_conf->num_hs_stack_entries << NUM_HS_STACK_ENTRIES_shift) | (sq_conf->num_ls_stack_entries << NUM_LS_STACK_ENTRIES_shift)); BEGIN_BATCH(16); /* disable dyn gprs */ EREG(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); PACK0(SQ_CONFIG, 4); E32(sq_config); E32(sq_gpr_resource_mgmt_1); E32(sq_gpr_resource_mgmt_2); E32(sq_gpr_resource_mgmt_3); PACK0(SQ_THREAD_RESOURCE_MGMT, 5); E32(sq_thread_resource_mgmt); E32(sq_thread_resource_mgmt_2); E32(sq_stack_resource_mgmt_1); E32(sq_stack_resource_mgmt_2); E32(sq_stack_resource_mgmt_3); END_BATCH(); } /* cayman has some minor differences in CB_COLOR*_INFO and _ATTRIB, but none that * we use here. */ void evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain) { uint32_t cb_color_info, cb_color_attrib = 0, cb_color_dim; unsigned pitch, slice, w, h, array_mode, nbanks; uint32_t tile_split, macro_aspect, bankw, bankh; RADEONInfoPtr info = RADEONPTR(pScrn); if (cb_conf->surface) { switch (cb_conf->surface->level[0].mode) { case RADEON_SURF_MODE_1D: array_mode = 2; break; case RADEON_SURF_MODE_2D: array_mode = 4; break; default: array_mode = 0; break; } w = cb_conf->surface->level[0].npix_x; h = cb_conf->surface->level[0].npix_y; pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1; slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1; tile_split = cb_conf->surface->tile_split; macro_aspect = cb_conf->surface->mtilea; bankw = cb_conf->surface->bankw; bankh = cb_conf->surface->bankh; tile_split = eg_tile_split(tile_split); macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); } else { pitch = (cb_conf->w / 8) - 1; h = RADEON_ALIGN(cb_conf->h, 8); slice = ((cb_conf->w * h) / 64) - 1; array_mode = cb_conf->array_mode; w = cb_conf->w; tile_split = 4; macro_aspect = 0; bankw = 0; bankh = 0; } nbanks = info->num_banks; nbanks = eg_nbanks(nbanks); cb_color_attrib |= (tile_split << CB_COLOR0_ATTRIB__TILE_SPLIT_shift)| (nbanks << CB_COLOR0_ATTRIB__NUM_BANKS_shift) | (bankw << CB_COLOR0_ATTRIB__BANK_WIDTH_shift) | (bankh << CB_COLOR0_ATTRIB__BANK_HEIGHT_shift) | (macro_aspect << CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift); cb_color_info = ((cb_conf->endian << ENDIAN_shift) | (cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) | (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) | (cb_conf->number_type << NUMBER_TYPE_shift) | (cb_conf->comp_swap << COMP_SWAP_shift) | (cb_conf->source_format << SOURCE_FORMAT_shift) | (cb_conf->resource_type << RESOURCE_TYPE_shift)); if (cb_conf->blend_clamp) cb_color_info |= BLEND_CLAMP_bit; if (cb_conf->fast_clear) cb_color_info |= FAST_CLEAR_bit; if (cb_conf->compression) cb_color_info |= COMPRESSION_bit; if (cb_conf->blend_bypass) cb_color_info |= BLEND_BYPASS_bit; if (cb_conf->simple_float) cb_color_info |= SIMPLE_FLOAT_bit; if (cb_conf->round_mode) cb_color_info |= CB_COLOR0_INFO__ROUND_MODE_bit; if (cb_conf->tile_compact) cb_color_info |= CB_COLOR0_INFO__TILE_COMPACT_bit; if (cb_conf->rat) cb_color_info |= RAT_bit; /* bit 4 needs to be set for linear and depth/stencil surfaces */ if (cb_conf->non_disp_tiling) cb_color_attrib |= CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit; switch (cb_conf->resource_type) { case BUFFER: /* number of elements in the surface */ cb_color_dim = pitch * slice; break; default: /* w/h of the surface */ cb_color_dim = (((w - 1) << WIDTH_MAX_shift) | ((cb_conf->h - 1) << HEIGHT_MAX_shift)); break; } BEGIN_BATCH(3 + 2); EREG(CB_COLOR0_BASE + (0x3c * cb_conf->id), (cb_conf->base >> 8)); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); /* Set CMASK & FMASK buffer to the offset of color buffer as * we don't use those this shouldn't cause any issue and we * then have a valid cmd stream */ BEGIN_BATCH(3 + 2); EREG(CB_COLOR0_CMASK + (0x3c * cb_conf->id), (0 >> 8)); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(CB_COLOR0_FMASK + (0x3c * cb_conf->id), (0 >> 8)); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); /* tiling config */ BEGIN_BATCH(3 + 2); EREG(CB_COLOR0_ATTRIB + (0x3c * cb_conf->id), cb_color_attrib); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(CB_COLOR0_INFO + (0x3c * cb_conf->id), cb_color_info); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(33); EREG(CB_COLOR0_PITCH + (0x3c * cb_conf->id), pitch); EREG(CB_COLOR0_SLICE + (0x3c * cb_conf->id), slice); EREG(CB_COLOR0_VIEW + (0x3c * cb_conf->id), 0); EREG(CB_COLOR0_DIM + (0x3c * cb_conf->id), cb_color_dim); EREG(CB_COLOR0_CMASK_SLICE + (0x3c * cb_conf->id), 0); EREG(CB_COLOR0_FMASK_SLICE + (0x3c * cb_conf->id), 0); PACK0(CB_COLOR0_CLEAR_WORD0 + (0x3c * cb_conf->id), 4); E32(0); E32(0); E32(0); E32(0); EREG(CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift)); EREG(CB_COLOR_CONTROL, (EVERGREEN_ROP[cb_conf->rop] | (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift))); EREG(CB_BLEND0_CONTROL, cb_conf->blendcntl); END_BATCH(); } void evergreen_set_blend_color(ScrnInfoPtr pScrn, float *color) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(2 + 4); PACK0(CB_BLEND_RED, 4); EFLOAT(color[0]); /* R */ EFLOAT(color[1]); /* G */ EFLOAT(color[2]); /* B */ EFLOAT(color[3]); /* A */ END_BATCH(); } static void evergreen_cp_set_surface_sync(ScrnInfoPtr pScrn, uint32_t sync_type, uint32_t size, uint64_t mc_addr, struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t cp_coher_size; if (size == 0xffffffff) cp_coher_size = 0xffffffff; else cp_coher_size = ((size + 255) >> 8); BEGIN_BATCH(5 + 2); PACK3(IT_SURFACE_SYNC, 4); E32(sync_type); E32(cp_coher_size); E32((mc_addr >> 8)); E32(10); /* poll interval */ RELOC_BATCH(bo, rdomains, wdomain); END_BATCH(); } /* inserts a wait for vline in the command stream */ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop) { RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc; if (!crtc) return; drmmode_crtc = crtc->driver_private; if (!crtc->enabled) return; if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); if (start >= stop) return; BEGIN_BATCH(11); /* set the VLINE range */ EREG(EVERGREEN_VLINE_START_END, /* this is just a marker */ (start << EVERGREEN_VLINE_START_SHIFT) | (stop << EVERGREEN_VLINE_END_SHIFT)); /* tell the CP to poll the VLINE state register */ PACK3(IT_WAIT_REG_MEM, 6); E32(IT_WAIT_REG | IT_WAIT_EQ); E32(IT_WAIT_ADDR(EVERGREEN_VLINE_STATUS)); E32(0); E32(0); // Ref value E32(EVERGREEN_VLINE_STAT); // Mask E32(10); // Wait interval /* add crtc reloc */ PACK3(IT_NOP, 1); E32(drmmode_crtc->mode_crtc->crtc_id); END_BATCH(); } void evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(8); /* Interpolator setup */ EREG(SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift)); PACK0(SPI_PS_IN_CONTROL_0, 3); E32(((num_interp << NUM_INTERP_shift) | LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0 E32(0); // SPI_PS_IN_CONTROL_1 E32(0); // SPI_INTERP_CONTROL_0 END_BATCH(); } void evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; sq_pgm_resources = ((fs_conf->num_gprs << NUM_GPRS_shift) | (fs_conf->stack_size << STACK_SIZE_shift)); if (fs_conf->dx10_clamp) sq_pgm_resources |= DX10_CLAMP_bit; BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_FS, fs_conf->shader_addr >> 8); RELOC_BATCH(fs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(3); EREG(SQ_PGM_RESOURCES_FS, sq_pgm_resources); END_BATCH(); } /* cayman has some minor differences in SQ_PGM_RESOUCES_VS and _RESOURCES_2_VS, * but none that we use here. */ void evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources, sq_pgm_resources_2; sq_pgm_resources = ((vs_conf->num_gprs << NUM_GPRS_shift) | (vs_conf->stack_size << STACK_SIZE_shift)); if (vs_conf->dx10_clamp) sq_pgm_resources |= DX10_CLAMP_bit; if (vs_conf->uncached_first_inst) sq_pgm_resources |= UNCACHED_FIRST_INST_bit; sq_pgm_resources_2 = ((vs_conf->single_round << SINGLE_ROUND_shift) | (vs_conf->double_round << DOUBLE_ROUND_shift)); if (vs_conf->allow_sdi) sq_pgm_resources_2 |= ALLOW_SINGLE_DENORM_IN_bit; if (vs_conf->allow_sd0) sq_pgm_resources_2 |= ALLOW_SINGLE_DENORM_OUT_bit; if (vs_conf->allow_ddi) sq_pgm_resources_2 |= ALLOW_DOUBLE_DENORM_IN_bit; if (vs_conf->allow_ddo) sq_pgm_resources_2 |= ALLOW_DOUBLE_DENORM_OUT_bit; /* flush SQ cache */ evergreen_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, vs_conf->shader_size, vs_conf->shader_addr, vs_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_VS, vs_conf->shader_addr >> 8); RELOC_BATCH(vs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(4); PACK0(SQ_PGM_RESOURCES_VS, 2); E32(sq_pgm_resources); E32(sq_pgm_resources_2); END_BATCH(); } /* cayman has some minor differences in SQ_PGM_RESOUCES_PS and _RESOURCES_2_PS, * but none that we use here. */ void evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources, sq_pgm_resources_2; sq_pgm_resources = ((ps_conf->num_gprs << NUM_GPRS_shift) | (ps_conf->stack_size << STACK_SIZE_shift)); if (ps_conf->dx10_clamp) sq_pgm_resources |= DX10_CLAMP_bit; if (ps_conf->uncached_first_inst) sq_pgm_resources |= UNCACHED_FIRST_INST_bit; if (ps_conf->clamp_consts) sq_pgm_resources |= CLAMP_CONSTS_bit; sq_pgm_resources_2 = ((ps_conf->single_round << SINGLE_ROUND_shift) | (ps_conf->double_round << DOUBLE_ROUND_shift)); if (ps_conf->allow_sdi) sq_pgm_resources_2 |= ALLOW_SINGLE_DENORM_IN_bit; if (ps_conf->allow_sd0) sq_pgm_resources_2 |= ALLOW_SINGLE_DENORM_OUT_bit; if (ps_conf->allow_ddi) sq_pgm_resources_2 |= ALLOW_DOUBLE_DENORM_IN_bit; if (ps_conf->allow_ddo) sq_pgm_resources_2 |= ALLOW_DOUBLE_DENORM_OUT_bit; /* flush SQ cache */ evergreen_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, ps_conf->shader_size, ps_conf->shader_addr, ps_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_PS, ps_conf->shader_addr >> 8); RELOC_BATCH(ps_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(5); PACK0(SQ_PGM_RESOURCES_PS, 3); E32(sq_pgm_resources); E32(sq_pgm_resources_2); E32(ps_conf->export_mode); END_BATCH(); } void evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); /* size reg is units of 16 consts (4 dwords each) */ uint32_t size = const_conf->size_bytes >> 8; if (size == 0) size = 1; #if X_BYTE_ORDER == X_BIG_ENDIAN { uint32_t count = size << 6, *p = const_conf->cpu_ptr; while(count--) { *p = cpu_to_le32(*p); p++; } } #endif /* flush SQ cache */ evergreen_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, const_conf->size_bytes, const_conf->const_addr, const_conf->bo, domain, 0); switch (const_conf->type) { case SHADER_TYPE_VS: BEGIN_BATCH(3); EREG(SQ_ALU_CONST_BUFFER_SIZE_VS_0, size); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(SQ_ALU_CONST_CACHE_VS_0, const_conf->const_addr >> 8); RELOC_BATCH(const_conf->bo, domain, 0); END_BATCH(); break; case SHADER_TYPE_PS: BEGIN_BATCH(3); EREG(SQ_ALU_CONST_BUFFER_SIZE_PS_0, size); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(SQ_ALU_CONST_CACHE_PS_0, const_conf->const_addr >> 8); RELOC_BATCH(const_conf->bo, domain, 0); END_BATCH(); break; default: ErrorF("Unsupported const type %d\n", const_conf->type); break; } } void evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val) { RADEONInfoPtr info = RADEONPTR(pScrn); /* bool register order is: ps, vs/es, gs, hs, ls, cs; one register each * 1 bits per bool; 32 bools each for ps, vs/es, gs, hs, ls, cs. */ BEGIN_BATCH(3); EREG(SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); END_BATCH(); } /* cayman has some minor differences in SQ_VTX_CONSTANT_WORD2_0 and _WORD3_0, * but none that we use here. */ static void evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t sq_vtx_constant_word2, sq_vtx_constant_word3, sq_vtx_constant_word4; sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) | ((res->vtx_size_dw << 2) << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift) | (res->format << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift) | (res->num_format_all << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift) | (res->endian << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)); if (res->clamp_x) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit; if (res->format_comp_all) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; if (res->srf_mode_all) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit; sq_vtx_constant_word3 = ((res->dst_sel_x << SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift) | (res->dst_sel_y << SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift) | (res->dst_sel_z << SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift) | (res->dst_sel_w << SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift)); if (res->uncached) sq_vtx_constant_word3 |= SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit; /* XXX ??? */ sq_vtx_constant_word4 = 0; /* flush vertex cache */ if ((info->ChipFamily == CHIP_FAMILY_CEDAR) || (info->ChipFamily == CHIP_FAMILY_PALM) || (info->ChipFamily == CHIP_FAMILY_SUMO) || (info->ChipFamily == CHIP_FAMILY_SUMO2) || (info->ChipFamily == CHIP_FAMILY_CAICOS) || (info->ChipFamily == CHIP_FAMILY_CAYMAN) || (info->ChipFamily == CHIP_FAMILY_ARUBA)) evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, accel_state->vbo.vb_offset, 0, res->bo, domain, 0); else evergreen_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit, accel_state->vbo.vb_offset, 0, res->bo, domain, 0); BEGIN_BATCH(10 + 2); PACK0(SQ_FETCH_RESOURCE + res->id * SQ_FETCH_RESOURCE_offset, 8); E32(res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS E32((res->vtx_num_entries << 2) - 1); // 1: SIZE E32(sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN E32(sq_vtx_constant_word3); // 3: swizzles E32(sq_vtx_constant_word4); // 4: num elements E32(0); // 5: n/a E32(0); // 6: n/a E32(SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD7_0__TYPE_shift); // 7: TYPE RELOC_BATCH(res->bo, domain, 0); END_BATCH(); } /* cayman has some minor differences in SQ_TEX_CONSTANT_WORD0_0 and _WORD4_0, * but none that we use here. */ void evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; uint32_t sq_tex_resource_word5, sq_tex_resource_word6, sq_tex_resource_word7; uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; if (tex_res->surface) { switch (tex_res->surface->level[0].mode) { case RADEON_SURF_MODE_1D: array_mode = 2; break; case RADEON_SURF_MODE_2D: array_mode = 4; break; default: array_mode = 0; break; } pitch = tex_res->surface->level[0].nblk_x >> 3; tile_split = tex_res->surface->tile_split; macro_aspect = tex_res->surface->mtilea; bankw = tex_res->surface->bankw; bankh = tex_res->surface->bankh; tile_split = eg_tile_split(tile_split); macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); } else { array_mode = tex_res->array_mode; pitch = (tex_res->pitch + 7) >> 3; tile_split = 4; macro_aspect = 0; bankw = 0; bankh = 0; } nbanks = info->num_banks; nbanks = eg_nbanks(nbanks); sq_tex_resource_word0 = (tex_res->dim << DIM_shift); if (tex_res->w) sq_tex_resource_word0 |= ( ((pitch - 1) << PITCH_shift) | ((tex_res->w - 1) << TEX_WIDTH_shift) ); if (tex_res->tile_type) sq_tex_resource_word0 |= SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_bit; sq_tex_resource_word1 = (array_mode << SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift); if (tex_res->h) sq_tex_resource_word1 |= ((tex_res->h - 1) << TEX_HEIGHT_shift); if (tex_res->depth) sq_tex_resource_word1 |= ((tex_res->depth - 1) << TEX_DEPTH_shift); sq_tex_resource_word4 = ((tex_res->format_comp_x << FORMAT_COMP_X_shift) | (tex_res->format_comp_y << FORMAT_COMP_Y_shift) | (tex_res->format_comp_z << FORMAT_COMP_Z_shift) | (tex_res->format_comp_w << FORMAT_COMP_W_shift) | (tex_res->num_format_all << SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift) | (tex_res->endian << SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift) | (tex_res->dst_sel_x << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) | (tex_res->dst_sel_y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) | (tex_res->dst_sel_z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) | (tex_res->dst_sel_w << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift) | (tex_res->base_level << BASE_LEVEL_shift)); if (tex_res->srf_mode_all) sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit; if (tex_res->force_degamma) sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit; sq_tex_resource_word5 = ((tex_res->last_level << LAST_LEVEL_shift) | (tex_res->base_array << BASE_ARRAY_shift) | (tex_res->last_array << LAST_ARRAY_shift)); sq_tex_resource_word6 = ((tex_res->min_lod << SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift) | (tex_res->perf_modulation << PERF_MODULATION_shift) | (tile_split << SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift)); if (tex_res->interlaced) sq_tex_resource_word6 |= INTERLACED_bit; sq_tex_resource_word7 = ((tex_res->format << SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift) | (macro_aspect << SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift) | (nbanks << SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift) | (bankw << SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift) | (bankh << SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift) | (SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD7_0__TYPE_shift)); /* flush texture cache */ evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, tex_res->size, tex_res->base, tex_res->bo, domain, 0); BEGIN_BATCH(10 + 4); PACK0(SQ_FETCH_RESOURCE + tex_res->id * SQ_FETCH_RESOURCE_offset, 8); E32(sq_tex_resource_word0); E32(sq_tex_resource_word1); E32(((tex_res->base) >> 8)); E32(((tex_res->mip_base) >> 8)); E32(sq_tex_resource_word4); E32(sq_tex_resource_word5); E32(sq_tex_resource_word6); E32(sq_tex_resource_word7); RELOC_BATCH(tex_res->bo, domain, 0); RELOC_BATCH(tex_res->mip_bo, domain, 0); END_BATCH(); } /* cayman has some minor differences in SQ_TEX_SAMPLER_WORD0_0, * but none that we use here. */ void evergreen_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2; sq_tex_sampler_word0 = ((s->clamp_x << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift) | (s->clamp_y << CLAMP_Y_shift) | (s->clamp_z << CLAMP_Z_shift) | (s->xy_mag_filter << XY_MAG_FILTER_shift) | (s->xy_min_filter << XY_MIN_FILTER_shift) | (s->z_filter << Z_FILTER_shift) | (s->mip_filter << MIP_FILTER_shift) | (s->border_color << BORDER_COLOR_TYPE_shift) | (s->depth_compare << DEPTH_COMPARE_FUNCTION_shift) | (s->chroma_key << CHROMA_KEY_shift)); sq_tex_sampler_word1 = ((s->min_lod << SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift) | (s->max_lod << MAX_LOD_shift) | (s->perf_mip << PERF_MIP_shift) | (s->perf_z << PERF_Z_shift)); sq_tex_sampler_word2 = ((s->lod_bias << SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift) | (s->lod_bias2 << LOD_BIAS_SEC_shift)); if (s->mc_coord_truncate) sq_tex_sampler_word2 |= MC_COORD_TRUNCATE_bit; if (s->force_degamma) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit; if (s->truncate_coord) sq_tex_sampler_word2 |= TRUNCATE_COORD_bit; if (s->disable_cube_wrap) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit; if (s->type) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__TYPE_bit; BEGIN_BATCH(5); PACK0(SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); E32(sq_tex_sampler_word0); E32(sq_tex_sampler_word1); E32(sq_tex_sampler_word2); END_BATCH(); } /* workarounds for hw bugs in eg+ */ /* only affects screen/window/generic/vport. cliprects are not affected */ static void evergreen_fix_scissor_coordinates(ScrnInfoPtr pScrn, int *x1, int *y1, int *x2, int *y2) { RADEONInfoPtr info = RADEONPTR(pScrn); /* all eg+ asics */ if (*x2 == 0) *x1 = 1; if (*y2 == 0) *y1 = 1; /* cayman/tn only */ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) { /* cliprects aren't affected so we can use them to clip if we need * a true 1x1 clip region */ if ((*x2 == 1) && (*y2 == 1)) *x2 = 2; } } //XXX deal with clip offsets in clip setup void evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2); BEGIN_BATCH(4); PACK0(PA_SC_SCREEN_SCISSOR_TL, 2); E32(((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift))); E32(((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2); BEGIN_BATCH(4); PACK0(PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2); E32(((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift))); END_BATCH(); } void evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2); BEGIN_BATCH(4); PACK0(PA_SC_GENERIC_SCISSOR_TL, 2); E32(((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift))); END_BATCH(); } void evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2); BEGIN_BATCH(4); PACK0(PA_SC_WINDOW_SCISSOR_TL, 2); E32(((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2); E32(((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift))); E32(((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift))); END_BATCH(); } /* * Setup of default state */ void evergreen_set_default_state(ScrnInfoPtr pScrn) { tex_resource_t tex_res; shader_config_t fs_conf; sq_config_t sq_conf; int i; RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) { cayman_set_default_state(pScrn); return; } if (accel_state->XInited3D) return; memset(&tex_res, 0, sizeof(tex_resource_t)); memset(&fs_conf, 0, sizeof(shader_config_t)); accel_state->XInited3D = TRUE; evergreen_start_3d(pScrn); /* SQ */ sq_conf.ps_prio = 0; sq_conf.vs_prio = 1; sq_conf.gs_prio = 2; sq_conf.es_prio = 3; sq_conf.hs_prio = 0; sq_conf.ls_prio = 0; sq_conf.cs_prio = 0; switch (info->ChipFamily) { case CHIP_FAMILY_CEDAR: default: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 96; sq_conf.num_vs_threads = 16; sq_conf.num_gs_threads = 16; sq_conf.num_es_threads = 16; sq_conf.num_hs_threads = 16; sq_conf.num_ls_threads = 16; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; case CHIP_FAMILY_REDWOOD: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 20; sq_conf.num_gs_threads = 20; sq_conf.num_es_threads = 20; sq_conf.num_hs_threads = 20; sq_conf.num_ls_threads = 20; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; case CHIP_FAMILY_JUNIPER: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 20; sq_conf.num_gs_threads = 20; sq_conf.num_es_threads = 20; sq_conf.num_hs_threads = 20; sq_conf.num_ls_threads = 20; sq_conf.num_ps_stack_entries = 85; sq_conf.num_vs_stack_entries = 85; sq_conf.num_gs_stack_entries = 85; sq_conf.num_es_stack_entries = 85; sq_conf.num_hs_stack_entries = 85; sq_conf.num_ls_stack_entries = 85; break; case CHIP_FAMILY_CYPRESS: case CHIP_FAMILY_HEMLOCK: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 20; sq_conf.num_gs_threads = 20; sq_conf.num_es_threads = 20; sq_conf.num_hs_threads = 20; sq_conf.num_ls_threads = 20; sq_conf.num_ps_stack_entries = 85; sq_conf.num_vs_stack_entries = 85; sq_conf.num_gs_stack_entries = 85; sq_conf.num_es_stack_entries = 85; sq_conf.num_hs_stack_entries = 85; sq_conf.num_ls_stack_entries = 85; break; case CHIP_FAMILY_PALM: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 96; sq_conf.num_vs_threads = 16; sq_conf.num_gs_threads = 16; sq_conf.num_es_threads = 16; sq_conf.num_hs_threads = 16; sq_conf.num_ls_threads = 16; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; case CHIP_FAMILY_SUMO: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 96; sq_conf.num_vs_threads = 25; sq_conf.num_gs_threads = 25; sq_conf.num_es_threads = 25; sq_conf.num_hs_threads = 25; sq_conf.num_ls_threads = 25; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; case CHIP_FAMILY_SUMO2: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 96; sq_conf.num_vs_threads = 25; sq_conf.num_gs_threads = 25; sq_conf.num_es_threads = 25; sq_conf.num_hs_threads = 25; sq_conf.num_ls_threads = 25; sq_conf.num_ps_stack_entries = 85; sq_conf.num_vs_stack_entries = 85; sq_conf.num_gs_stack_entries = 85; sq_conf.num_es_stack_entries = 85; sq_conf.num_hs_stack_entries = 85; sq_conf.num_ls_stack_entries = 85; break; case CHIP_FAMILY_BARTS: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 20; sq_conf.num_gs_threads = 20; sq_conf.num_es_threads = 20; sq_conf.num_hs_threads = 20; sq_conf.num_ls_threads = 20; sq_conf.num_ps_stack_entries = 85; sq_conf.num_vs_stack_entries = 85; sq_conf.num_gs_stack_entries = 85; sq_conf.num_es_stack_entries = 85; sq_conf.num_hs_stack_entries = 85; sq_conf.num_ls_stack_entries = 85; break; case CHIP_FAMILY_TURKS: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 20; sq_conf.num_gs_threads = 20; sq_conf.num_es_threads = 20; sq_conf.num_hs_threads = 20; sq_conf.num_ls_threads = 20; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; case CHIP_FAMILY_CAICOS: sq_conf.num_ps_gprs = 93; sq_conf.num_vs_gprs = 46; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 31; sq_conf.num_es_gprs = 31; sq_conf.num_hs_gprs = 23; sq_conf.num_ls_gprs = 23; sq_conf.num_ps_threads = 128; sq_conf.num_vs_threads = 10; sq_conf.num_gs_threads = 10; sq_conf.num_es_threads = 10; sq_conf.num_hs_threads = 10; sq_conf.num_ls_threads = 10; sq_conf.num_ps_stack_entries = 42; sq_conf.num_vs_stack_entries = 42; sq_conf.num_gs_stack_entries = 42; sq_conf.num_es_stack_entries = 42; sq_conf.num_hs_stack_entries = 42; sq_conf.num_ls_stack_entries = 42; break; } evergreen_sq_setup(pScrn, &sq_conf); BEGIN_BATCH(27); EREG(SQ_LDS_ALLOC_PS, 0); EREG(SQ_LDS_RESOURCE_MGMT, 0x10001000); EREG(SQ_DYN_GPR_RESOURCE_LIMIT_1, 0); PACK0(SQ_ESGS_RING_ITEMSIZE, 6); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); PACK0(SQ_GS_VERT_ITEMSIZE, 4); E32(0); E32(0); E32(0); E32(0); PACK0(SQ_VTX_BASE_VTX_LOC, 2); E32(0); E32(0); END_BATCH(); /* DB */ BEGIN_BATCH(3 + 2); EREG(DB_Z_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(DB_STENCIL_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(3 + 2); EREG(DB_HTILE_DATA_BASE, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(49); EREG(DB_DEPTH_CONTROL, 0); PACK0(PA_SC_VPORT_ZMIN_0, 2); EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0 EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0 PACK0(DB_RENDER_CONTROL, 5); E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL E32(0); // DB_COUNT_CONTROL E32(0); // DB_DEPTH_VIEW E32(0x2a); // DB_RENDER_OVERRIDE E32(0); // DB_RENDER_OVERRIDE2 PACK0(DB_STENCIL_CLEAR, 2); E32(0); // DB_STENCIL_CLEAR E32(0); // DB_DEPTH_CLEAR EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | (2 << ALPHA_TO_MASK_OFFSET1_shift) | (2 << ALPHA_TO_MASK_OFFSET2_shift) | (2 << ALPHA_TO_MASK_OFFSET3_shift))); EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) | DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ // SX EREG(SX_MISC, 0); // CB PACK0(SX_ALPHA_TEST_CONTROL, 5); E32(0); // SX_ALPHA_TEST_CONTROL E32(0x00000000); //CB_BLEND_RED E32(0x00000000); //CB_BLEND_GREEN E32(0x00000000); //CB_BLEND_BLUE E32(0x00000000); //CB_BLEND_ALPHA EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask); // SC EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | (0 << WINDOW_Y_OFFSET_shift))); EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); EREG(PA_SC_EDGERULE, 0xAAAAAAAA); EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0); END_BATCH(); /* clip boolean is set to always visible -> doesn't matter */ for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192); for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192); BEGIN_BATCH(57); PACK0(PA_SC_MODE_CNTL_0, 2); E32(0); // PA_SC_MODE_CNTL_0 E32(0); // PA_SC_MODE_CNTL_1 PACK0(PA_SC_LINE_CNTL, 16); E32(0); // PA_SC_LINE_CNTL E32(0); // PA_SC_AA_CONFIG E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit)); // PA_SU_VTX_CNTL EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ E32(0); // PA_SC_AA_SAMPLE_LOCS_0 E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); // PA_SC_AA_SAMPLE_LOCS_7 E32(0xFFFFFFFF); // PA_SC_AA_MASK // CL PACK0(PA_CL_CLIP_CNTL, 8); E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL E32(FACE_bit); // PA_SU_SC_MODE_CNTL E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL E32(0); // PA_CL_VS_OUT_CNTL E32(0); // PA_CL_NANINF_CNTL E32(0); // PA_SU_LINE_STIPPLE_CNTL E32(0); // PA_SU_LINE_STIPPLE_SCALE E32(0); // PA_SU_PRIM_FILTER_CNTL // SU PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); /* src = semantic id 0; mask = semantic id 1 */ EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | (1 << SEMANTIC_1_shift))); PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ E32(((0 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift))); /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ E32(((1 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift))); PACK0(SPI_INPUT_Z, 8); E32(0); // SPI_INPUT_Z E32(0); // SPI_FOG_CNTL E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL E32(0); // SPI_PS_IN_CONTROL_2 E32(0); E32(0); E32(0); E32(0); END_BATCH(); // clear FS fs_conf.bo = accel_state->shaders_bo; evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM); // VGT BEGIN_BATCH(46); PACK0(VGT_MAX_VTX_INDX, 4); E32(0xffffff); E32(0); E32(0); E32(0); PACK0(VGT_INSTANCE_STEP_RATE_0, 2); E32(0); E32(0); PACK0(VGT_REUSE_OFF, 2); E32(0); E32(0); PACK0(PA_SU_POINT_SIZE, 17); E32(0); // PA_SU_POINT_SIZE E32(0); // PA_SU_POINT_MINMAX E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL E32(0); // PA_SC_LINE_STIPPLE E32(0); // VGT_OUTPUT_PATH_CNTL E32(0); // VGT_HOS_CNTL E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); E32(0); // VGT_GS_MODE EREG(VGT_PRIMITIVEID_EN, 0); EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0); EREG(VGT_SHADER_STAGES_EN, 0); PACK0(VGT_STRMOUT_CONFIG, 2); E32(0); E32(0); END_BATCH(); } /* * Commands */ void evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(10); EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type); PACK3(IT_INDEX_TYPE, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); #else E32(draw_conf->index_type); #endif PACK3(IT_NUM_INSTANCES, 1); E32(draw_conf->num_instances); PACK3(IT_DRAW_INDEX_AUTO, 2); E32(draw_conf->num_indices); E32(draw_conf->vgt_draw_initiator); END_BATCH(); } void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; draw_config_t draw_conf; vtx_resource_t vtx_res; if (accel_state->vbo.vb_start_op == -1) return; CLEAR (draw_conf); CLEAR (vtx_res); if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) { radeon_ib_discard(pScrn); radeon_cs_flush_indirect(pScrn); return; } /* Vertex buffer setup */ accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op; vtx_res.id = SQ_FETCH_RESOURCE_vs; vtx_res.vtx_size_dw = vtx_size / 4; vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4; vtx_res.vb_addr = accel_state->vbo.vb_start_op; vtx_res.bo = accel_state->vbo.vb_bo; vtx_res.dst_sel_x = SQ_SEL_X; vtx_res.dst_sel_y = SQ_SEL_Y; vtx_res.dst_sel_z = SQ_SEL_Z; vtx_res.dst_sel_w = SQ_SEL_W; #if X_BYTE_ORDER == X_BIG_ENDIAN vtx_res.endian = SQ_ENDIAN_8IN32; #endif evergreen_set_vtx_resource(pScrn, &vtx_res, RADEON_GEM_DOMAIN_GTT); /* Draw */ draw_conf.prim_type = DI_PT_RECTLIST; draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; draw_conf.num_instances = 1; draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; draw_conf.index_type = DI_INDEX_SIZE_16_BIT; evergreen_draw_auto(pScrn, &draw_conf); /* sync dst surface */ evergreen_cp_set_surface_sync(pScrn, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), accel_state->dst_size, 0, accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain); accel_state->vbo.vb_start_op = -1; accel_state->cbuf.vb_start_op = -1; accel_state->ib_reset_op = 0; } xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_exa.c000066400000000000000000002017051256524674500232650ustar00rootroot00000000000000/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "exa.h" #include "radeon.h" #include "radeon_reg.h" #include "evergreen_shader.h" #include "evergreen_reg.h" #include "evergreen_state.h" #include "radeon_exa_shared.h" #include "radeon_vbo.h" extern int cayman_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int cayman_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int cayman_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int cayman_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int cayman_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader); extern int cayman_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader); extern int cayman_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int cayman_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps); static Bool EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; cb_config_t cb_conf; shader_config_t vs_conf, ps_conf; uint32_t a, r, g, b; float *ps_alu_consts; const_config_t ps_const_conf; struct r600_accel_object dst; if (!RADEONCheckBPP(pPix->drawable.bitsPerPixel)) RADEON_FALLBACK(("EVERGREENCheckDatatype failed\n")); if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel)) RADEON_FALLBACK(("invalid planemask\n")); dst.bo = radeon_get_pixmap_bo(pPix); dst.tiling_flags = radeon_get_pixmap_tiling(pPix); dst.surface = radeon_get_pixmap_surface(pPix); dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8); dst.width = pPix->drawable.width; dst.height = pPix->drawable.height; dst.bpp = pPix->drawable.bitsPerPixel; dst.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, NULL, NULL, &dst, accel_state->solid_vs_offset, accel_state->solid_ps_offset, alu, pm)) return FALSE; CLEAR (cb_conf); CLEAR (vs_conf); CLEAR (ps_conf); CLEAR (ps_const_conf); radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_vbo_check(pScrn, &accel_state->cbuf, 256); radeon_cp_start(pScrn); evergreen_set_default_state(pScrn); evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 1; ps_conf.stack_size = 0; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; cb_conf.comp_swap = 3; /* A */ } else if (accel_state->dst_obj.bpp == 16) { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN16; #endif } else { cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN32; #endif } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; /* Render setup */ if (accel_state->planemask & 0x000000ff) cb_conf.pmask |= 4; /* B */ if (accel_state->planemask & 0x0000ff00) cb_conf.pmask |= 2; /* G */ if (accel_state->planemask & 0x00ff0000) cb_conf.pmask |= 1; /* R */ if (accel_state->planemask & 0xff000000) cb_conf.pmask |= 8; /* A */ cb_conf.rop = accel_state->rop; if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) { cb_conf.array_mode = 0; cb_conf.non_disp_tiling = 1; } evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); evergreen_set_spi(pScrn, 0, 0); /* PS alu constants */ ps_const_conf.size_bytes = 256; ps_const_conf.type = SHADER_TYPE_PS; ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); ps_const_conf.bo = accel_state->cbuf.vb_bo; ps_const_conf.const_addr = accel_state->cbuf.vb_offset; ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts; if (accel_state->dst_obj.bpp == 16) { r = (fg >> 11) & 0x1f; g = (fg >> 5) & 0x3f; b = (fg >> 0) & 0x1f; ps_alu_consts[0] = (float)r / 31; /* R */ ps_alu_consts[1] = (float)g / 63; /* G */ ps_alu_consts[2] = (float)b / 31; /* B */ ps_alu_consts[3] = 1.0; /* A */ } else if (accel_state->dst_obj.bpp == 8) { a = (fg >> 0) & 0xff; ps_alu_consts[0] = 0.0; /* R */ ps_alu_consts[1] = 0.0; /* G */ ps_alu_consts[2] = 0.0; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } else { a = (fg >> 24) & 0xff; r = (fg >> 16) & 0xff; g = (fg >> 8) & 0xff; b = (fg >> 0) & 0xff; ps_alu_consts[0] = (float)r / 255; /* R */ ps_alu_consts[1] = (float)g / 255; /* G */ ps_alu_consts[2] = (float)b / 255; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } radeon_vbo_commit(pScrn, &accel_state->cbuf); evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->dst_pix = pPix; accel_state->fg = fg; return TRUE; } static void EVERGREENDoneSolid(PixmapPtr pPix) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) evergreen_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); evergreen_finish_op(pScrn, 8); } static void EVERGREENSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; if (CS_FULL(info->cs)) { EVERGREENDoneSolid(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); EVERGREENPrepareSolid(accel_state->dst_pix, accel_state->rop, accel_state->planemask, accel_state->fg); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, x1, y1, x2, y2); vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8); vb[0] = (float)x1; vb[1] = (float)y1; vb[2] = (float)x1; vb[3] = (float)y2; vb[4] = (float)x2; vb[5] = (float)y2; radeon_vbo_commit(pScrn, &accel_state->vbo); } static void EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; cb_config_t cb_conf; tex_resource_t tex_res; tex_sampler_t tex_samp; shader_config_t vs_conf, ps_conf; CLEAR (cb_conf); CLEAR (tex_res); CLEAR (tex_samp); CLEAR (vs_conf); CLEAR (ps_conf); radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); evergreen_set_default_state(pScrn); evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 1; ps_conf.stack_size = 0; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* Texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; tex_res.surface = accel_state->src_obj[0].surface; if (accel_state->src_obj[0].bpp == 8) { tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_1; /* R */ tex_res.dst_sel_y = SQ_SEL_1; /* G */ tex_res.dst_sel_z = SQ_SEL_1; /* B */ tex_res.dst_sel_w = SQ_SEL_X; /* A */ } else if (accel_state->src_obj[0].bpp == 16) { tex_res.format = FMT_5_6_5; tex_res.dst_sel_x = SQ_SEL_Z; /* R */ tex_res.dst_sel_y = SQ_SEL_Y; /* G */ tex_res.dst_sel_z = SQ_SEL_X; /* B */ tex_res.dst_sel_w = SQ_SEL_1; /* A */ } else { tex_res.format = FMT_8_8_8_8; tex_res.dst_sel_x = SQ_SEL_Z; /* R */ tex_res.dst_sel_y = SQ_SEL_Y; /* G */ tex_res.dst_sel_z = SQ_SEL_X; /* B */ tex_res.dst_sel_w = SQ_SEL_W; /* A */ } tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 0; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.mc_coord_truncate = 1; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ evergreen_set_tex_sampler (pScrn, &tex_samp); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; cb_conf.comp_swap = 3; /* A */ } else if (accel_state->dst_obj.bpp == 16) { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ } else { cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; /* Render setup */ if (accel_state->planemask & 0x000000ff) cb_conf.pmask |= 4; /* B */ if (accel_state->planemask & 0x0000ff00) cb_conf.pmask |= 2; /* G */ if (accel_state->planemask & 0x00ff0000) cb_conf.pmask |= 1; /* R */ if (accel_state->planemask & 0xff000000) cb_conf.pmask |= 8; /* A */ cb_conf.rop = accel_state->rop; if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) { cb_conf.array_mode = 0; cb_conf.non_disp_tiling = 1; } evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); evergreen_set_spi(pScrn, (1 - 1), 1); } static void EVERGREENDoCopy(ScrnInfoPtr pScrn) { evergreen_finish_op(pScrn, 16); } static void EVERGREENDoCopyVline(PixmapPtr pPix) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) evergreen_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); evergreen_finish_op(pScrn, 16); } static void EVERGREENAppendCopyVertex(ScrnInfoPtr pScrn, int srcX, int srcY, int dstX, int dstY, int w, int h) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + h); vb[6] = (float)srcX; vb[7] = (float)(srcY + h); vb[8] = (float)(dstX + w); vb[9] = (float)(dstY + h); vb[10] = (float)(srcX + w); vb[11] = (float)(srcY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } static Bool EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int xdir, int ydir, int rop, Pixel planemask) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct r600_accel_object src_obj, dst_obj; if (!RADEONCheckBPP(pSrc->drawable.bitsPerPixel)) RADEON_FALLBACK(("EVERGREENCheckDatatype src failed\n")); if (!RADEONCheckBPP(pDst->drawable.bitsPerPixel)) RADEON_FALLBACK(("EVERGREENCheckDatatype dst failed\n")); if (!RADEONValidPM(planemask, pDst->drawable.bitsPerPixel)) RADEON_FALLBACK(("Invalid planemask\n")); dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); accel_state->same_surface = FALSE; src_obj.bo = radeon_get_pixmap_bo(pSrc); dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.surface = radeon_get_pixmap_surface(pDst); src_obj.surface = radeon_get_pixmap_surface(pSrc); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst)) accel_state->same_surface = TRUE; src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = pSrc->drawable.bitsPerPixel; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = pDst->drawable.bitsPerPixel; if (radeon_get_pixmap_shared(pDst) == TRUE) dst_obj.domain = RADEON_GEM_DOMAIN_GTT; else dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, rop, planemask)) return FALSE; if (accel_state->same_surface == TRUE) { unsigned height = RADEON_ALIGN(pDst->drawable.height, drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags)); unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8; if (accel_state->dst_obj.surface) size = accel_state->dst_obj.surface->bo_size; if (accel_state->copy_area_bo) { radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; } accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->copy_area_bo == NULL) RADEON_FALLBACK(("temp copy surface alloc failed\n")); radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, 0, RADEON_GEM_DOMAIN_VRAM); if (radeon_cs_space_check(info->cs)) { radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; return FALSE; } accel_state->copy_area = (void*)accel_state->copy_area_bo; } else EVERGREENDoPrepareCopy(pScrn); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->dst_pix = pDst; accel_state->src_pix = pSrc; accel_state->xdir = xdir; accel_state->ydir = ydir; return TRUE; } static void EVERGREENDoneCopy(PixmapPtr pDst) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (!accel_state->same_surface) EVERGREENDoCopyVline(pDst); if (accel_state->copy_area) accel_state->copy_area = NULL; } static void EVERGREENCopy(PixmapPtr pDst, int srcX, int srcY, int dstX, int dstY, int w, int h) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY)) return; if (CS_FULL(info->cs)) { EVERGREENDoneCopy(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); EVERGREENPrepareCopy(accel_state->src_pix, accel_state->dst_pix, accel_state->xdir, accel_state->ydir, accel_state->rop, accel_state->planemask); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); if (accel_state->same_surface && (srcX + w <= dstX || dstX + w <= srcX || srcY + h <= dstY || dstY + h <= srcY)) { EVERGREENDoPrepareCopy(pScrn); EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); EVERGREENDoCopyVline(pDst); } else if (accel_state->same_surface && accel_state->copy_area) { uint32_t orig_dst_domain = accel_state->dst_obj.domain; uint32_t orig_src_domain = accel_state->src_obj[0].domain; uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags; uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags; struct radeon_bo *orig_bo = accel_state->dst_obj.bo; int orig_rop = accel_state->rop; struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface; struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface; /* src to tmp */ accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; accel_state->dst_obj.bo = accel_state->copy_area_bo; accel_state->dst_obj.tiling_flags = 0; accel_state->rop = 3; accel_state->dst_obj.surface = NULL; EVERGREENDoPrepareCopy(pScrn); EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); EVERGREENDoCopy(pScrn); /* tmp to dst */ accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM; accel_state->src_obj[0].bo = accel_state->copy_area_bo; accel_state->src_obj[0].tiling_flags = 0; accel_state->src_obj[0].surface = NULL; accel_state->dst_obj.domain = orig_dst_domain; accel_state->dst_obj.bo = orig_bo; accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags; accel_state->rop = orig_rop; accel_state->dst_obj.surface = orig_dst_surface; EVERGREENDoPrepareCopy(pScrn); EVERGREENAppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h); EVERGREENDoCopyVline(pDst); /* restore state */ accel_state->src_obj[0].domain = orig_src_domain; accel_state->src_obj[0].bo = orig_bo; accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags; accel_state->src_obj[0].surface = orig_src_surface; } else EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); } struct blendinfo { Bool dst_alpha; Bool src_alpha; uint32_t blend_cntl; }; static struct blendinfo EVERGREENBlendOp[] = { /* Clear */ {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* Src */ {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* Dst */ {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, /* Over */ {0, 1, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* OverReverse */ {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, /* In */ {1, 0, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* InReverse */ {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Out */ {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* OutReverse */ {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Atop */ {1, 1, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* AtopReverse */ {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Xor */ {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Add */ {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, }; struct formatinfo { unsigned int fmt; uint32_t card_fmt; }; static struct formatinfo EVERGREENTexFormats[] = { {PICT_a8r8g8b8, FMT_8_8_8_8}, {PICT_x8r8g8b8, FMT_8_8_8_8}, {PICT_a8b8g8r8, FMT_8_8_8_8}, {PICT_x8b8g8r8, FMT_8_8_8_8}, {PICT_b8g8r8a8, FMT_8_8_8_8}, {PICT_b8g8r8x8, FMT_8_8_8_8}, {PICT_r5g6b5, FMT_5_6_5}, {PICT_a1r5g5b5, FMT_1_5_5_5}, {PICT_x1r5g5b5, FMT_1_5_5_5}, {PICT_a8, FMT_8}, }; static uint32_t EVERGREENGetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) { uint32_t sblend, dblend; sblend = EVERGREENBlendOp[op].blend_cntl & COLOR_SRCBLEND_mask; dblend = EVERGREENBlendOp[op].blend_cntl & COLOR_DESTBLEND_mask; /* If there's no dst alpha channel, adjust the blend op so that we'll treat * it as always 1. */ if (PICT_FORMAT_A(dst_format) == 0 && EVERGREENBlendOp[op].dst_alpha) { if (sblend == (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift)) sblend = (BLEND_ONE << COLOR_SRCBLEND_shift); else if (sblend == (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift)) sblend = (BLEND_ZERO << COLOR_SRCBLEND_shift); } /* If the source alpha is being used, then we should only be in a case where * the source blend factor is 0, and the source blend value is the mask * channels multiplied by the source picture's alpha. */ if (pMask && pMask->componentAlpha && EVERGREENBlendOp[op].src_alpha) { if (dblend == (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)) { dblend = (BLEND_SRC_COLOR << COLOR_DESTBLEND_shift); } else if (dblend == (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)) { dblend = (BLEND_ONE_MINUS_SRC_COLOR << COLOR_DESTBLEND_shift); } /* With some tricks, we can still accelerate PictOpOver with solid src. * This is commonly used for text rendering, so it's worth the extra * effort. */ if (sblend == (BLEND_ONE << COLOR_SRCBLEND_shift)) { sblend = (BLEND_CONSTANT_COLOR << COLOR_SRCBLEND_shift); } } return sblend | dblend; } static Bool EVERGREENGetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: case PICT_a8b8g8r8: case PICT_x8b8g8r8: case PICT_b8g8r8a8: case PICT_b8g8r8x8: *dst_format = COLOR_8_8_8_8; break; case PICT_r5g6b5: *dst_format = COLOR_5_6_5; break; case PICT_a1r5g5b5: case PICT_x1r5g5b5: *dst_format = COLOR_1_5_5_5; break; case PICT_a8: *dst_format = COLOR_8; break; default: RADEON_FALLBACK(("Unsupported dest format 0x%x\n", (int)pDstPicture->format)); } return TRUE; } static Bool EVERGREENCheckCompositeTexture(PicturePtr pPict, PicturePtr pDstPict, int op, int unit) { unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; unsigned int i; for (i = 0; i < sizeof(EVERGREENTexFormats) / sizeof(EVERGREENTexFormats[0]); i++) { if (EVERGREENTexFormats[i].fmt == pPict->format) break; } if (i == sizeof(EVERGREENTexFormats) / sizeof(EVERGREENTexFormats[0])) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); /* for REPEAT_NONE, Render semantics are that sampling outside the source * picture results in alpha=0 pixels. We can implement this with a border color * *if* our source texture has an alpha channel, otherwise we need to fall * back. If we're not transformed then we hope that upper layers have clipped * rendering to the bounds of the source drawable, in which case it doesn't * matter. I have not, however, verified that the X server always does such * clipping. */ /* FIXME evergreen */ if (pPict->transform != 0 && repeatType == RepeatNone && PICT_FORMAT_A(pPict->format) == 0) { if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); } if (!radeon_transform_is_affine_or_scaled(pPict->transform)) RADEON_FALLBACK(("non-affine transforms not supported\n")); return TRUE; } static void EVERGREENXFormSetup(PicturePtr pPict, ScrnInfoPtr pScrn, int unit, float *vs_alu_consts) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; int const_offset = unit * 8; int w, h; if (pPict->pDrawable) { w = pPict->pDrawable->width; h = pPict->pDrawable->height; } else { w = 1; h = 1; } if (pPict->transform != 0) { accel_state->is_transform[unit] = TRUE; accel_state->transform[unit] = pPict->transform; vs_alu_consts[0 + const_offset] = xFixedToFloat(pPict->transform->matrix[0][0]); vs_alu_consts[1 + const_offset] = xFixedToFloat(pPict->transform->matrix[0][1]); vs_alu_consts[2 + const_offset] = xFixedToFloat(pPict->transform->matrix[0][2]); vs_alu_consts[3 + const_offset] = 1.0 / w; vs_alu_consts[4 + const_offset] = xFixedToFloat(pPict->transform->matrix[1][0]); vs_alu_consts[5 + const_offset] = xFixedToFloat(pPict->transform->matrix[1][1]); vs_alu_consts[6 + const_offset] = xFixedToFloat(pPict->transform->matrix[1][2]); vs_alu_consts[7 + const_offset] = 1.0 / h; } else { accel_state->is_transform[unit] = FALSE; vs_alu_consts[0 + const_offset] = 1.0; vs_alu_consts[1 + const_offset] = 0.0; vs_alu_consts[2 + const_offset] = 0.0; vs_alu_consts[3 + const_offset] = 1.0 / w; vs_alu_consts[4 + const_offset] = 0.0; vs_alu_consts[5 + const_offset] = 1.0; vs_alu_consts[6 + const_offset] = 0.0; vs_alu_consts[7 + const_offset] = 1.0 / h; } } static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; unsigned int repeatType; unsigned int i; tex_resource_t tex_res; tex_sampler_t tex_samp; int pix_r, pix_g, pix_b, pix_a; CLEAR (tex_res); CLEAR (tex_samp); for (i = 0; i < sizeof(EVERGREENTexFormats) / sizeof(EVERGREENTexFormats[0]); i++) { if (EVERGREENTexFormats[i].fmt == pPict->format) break; } /* Texture */ if (pPict->pDrawable) { tex_res.w = pPict->pDrawable->width; tex_res.h = pPict->pDrawable->height; repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; } else { tex_res.w = 1; tex_res.h = 1; repeatType = RepeatNormal; } tex_res.id = unit; tex_res.pitch = accel_state->src_obj[unit].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[unit]; tex_res.format = EVERGREENTexFormats[i].card_fmt; tex_res.bo = accel_state->src_obj[unit].bo; tex_res.mip_bo = accel_state->src_obj[unit].bo; tex_res.surface = accel_state->src_obj[unit].surface; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (accel_state->src_obj[unit].bpp) { case 16: tex_res.endian = SQ_ENDIAN_8IN16; break; case 32: tex_res.endian = SQ_ENDIAN_8IN32; break; default : break; } #endif /* component swizzles */ switch (pPict->format) { case PICT_a1r5g5b5: case PICT_a8r8g8b8: pix_r = SQ_SEL_Z; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_X; /* B */ pix_a = SQ_SEL_W; /* A */ break; case PICT_a8b8g8r8: pix_r = SQ_SEL_X; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_Z; /* B */ pix_a = SQ_SEL_W; /* A */ break; case PICT_x8b8g8r8: pix_r = SQ_SEL_X; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_Z; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_b8g8r8a8: pix_r = SQ_SEL_Y; /* R */ pix_g = SQ_SEL_Z; /* G */ pix_b = SQ_SEL_W; /* B */ pix_a = SQ_SEL_X; /* A */ break; case PICT_b8g8r8x8: pix_r = SQ_SEL_Y; /* R */ pix_g = SQ_SEL_Z; /* G */ pix_b = SQ_SEL_W; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_x1r5g5b5: case PICT_x8r8g8b8: case PICT_r5g6b5: pix_r = SQ_SEL_Z; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_X; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_a8: pix_r = SQ_SEL_0; /* R */ pix_g = SQ_SEL_0; /* G */ pix_b = SQ_SEL_0; /* B */ pix_a = SQ_SEL_X; /* A */ break; default: RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format)); } if (unit == 0) { if (!accel_state->msk_pic) { if (PICT_FORMAT_RGB(pPict->format) == 0) { pix_r = SQ_SEL_0; pix_g = SQ_SEL_0; pix_b = SQ_SEL_0; } if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } else { if (accel_state->component_alpha) { if (accel_state->src_alpha) { if (PICT_FORMAT_A(pPict->format) == 0) { pix_r = SQ_SEL_1; pix_g = SQ_SEL_1; pix_b = SQ_SEL_1; pix_a = SQ_SEL_1; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } else { if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } } else { if (PICT_FORMAT_RGB(pPict->format) == 0) { pix_r = SQ_SEL_0; pix_g = SQ_SEL_0; pix_b = SQ_SEL_0; } if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } } } else { if (accel_state->component_alpha) { if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } else { if (PICT_FORMAT_A(pPict->format) == 0) { pix_r = SQ_SEL_1; pix_g = SQ_SEL_1; pix_b = SQ_SEL_1; pix_a = SQ_SEL_1; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } } tex_res.dst_sel_x = pix_r; /* R */ tex_res.dst_sel_y = pix_g; /* G */ tex_res.dst_sel_z = pix_b; /* B */ tex_res.dst_sel_w = pix_a; /* A */ tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 0; evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK; switch (repeatType) { case RepeatNormal: tex_samp.clamp_x = SQ_TEX_WRAP; tex_samp.clamp_y = SQ_TEX_WRAP; break; case RepeatPad: tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; break; case RepeatReflect: tex_samp.clamp_x = SQ_TEX_MIRROR; tex_samp.clamp_y = SQ_TEX_MIRROR; break; case RepeatNone: tex_samp.clamp_x = SQ_TEX_CLAMP_BORDER; tex_samp.clamp_y = SQ_TEX_CLAMP_BORDER; break; default: RADEON_FALLBACK(("Bad repeat 0x%x\n", repeatType)); } switch (pPict->filter) { case PictFilterNearest: tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.mc_coord_truncate = 1; break; case PictFilterBilinear: tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; break; default: RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ evergreen_set_tex_sampler (pScrn, &tex_samp); return TRUE; } static Bool EVERGREENCheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { uint32_t tmp1; PixmapPtr pSrcPixmap, pDstPixmap; /* Check for unsupported compositing operations. */ if (op >= (int) (sizeof(EVERGREENBlendOp) / sizeof(EVERGREENBlendOp[0]))) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); if (pSrcPicture->pDrawable) { pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); if (pSrcPixmap->drawable.width >= 16384 || pSrcPixmap->drawable.height >= 16384) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); } if (!EVERGREENCheckCompositeTexture(pSrcPicture, pDstPicture, op, 0)) return FALSE; } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); if (pDstPixmap->drawable.width >= 16384 || pDstPixmap->drawable.height >= 16384) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); } if (pMaskPicture) { PixmapPtr pMaskPixmap; if (pMaskPicture->pDrawable) { pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); if (pMaskPixmap->drawable.width >= 16384 || pMaskPixmap->drawable.height >= 16384) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); } if (pMaskPicture->componentAlpha) { /* Check if it's component alpha that relies on a source alpha and * on the source value. We can only get one of those into the * single source value that we get to blend with. * * We can cheat a bit if the src is solid, though. PictOpOver * can use the constant blend color to sneak a second blend * source in. */ if (EVERGREENBlendOp[op].src_alpha && (EVERGREENBlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) != (BLEND_ZERO << COLOR_SRCBLEND_shift)) { if (pSrcPicture->pDrawable || op != PictOpOver) RADEON_FALLBACK(("Component alpha not supported with source " "alpha and source value blending.\n")); } } if (!EVERGREENCheckCompositeTexture(pMaskPicture, pDstPicture, op, 1)) return FALSE; } else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); } if (!EVERGREENGetDestFormat(pDstPicture, &tmp1)) return FALSE; return TRUE; } static void EVERGREENSetSolidConsts(ScrnInfoPtr pScrn, float *buf, int format, uint32_t fg, int unit) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float pix_r = 0, pix_g = 0, pix_b = 0, pix_a = 0; uint32_t w = (fg >> 24) & 0xff; uint32_t z = (fg >> 16) & 0xff; uint32_t y = (fg >> 8) & 0xff; uint32_t x = (fg >> 0) & 0xff; float xf = (float)x / 255; /* R */ float yf = (float)y / 255; /* G */ float zf = (float)z / 255; /* B */ float wf = (float)w / 255; /* A */ /* component swizzles */ switch (format) { case PICT_a1r5g5b5: case PICT_a8r8g8b8: pix_r = zf; /* R */ pix_g = yf; /* G */ pix_b = xf; /* B */ pix_a = wf; /* A */ break; case PICT_a8b8g8r8: pix_r = xf; /* R */ pix_g = yf; /* G */ pix_b = zf; /* B */ pix_a = wf; /* A */ break; case PICT_x8b8g8r8: pix_r = xf; /* R */ pix_g = yf; /* G */ pix_b = zf; /* B */ pix_a = 1.0; /* A */ break; case PICT_b8g8r8a8: pix_r = yf; /* R */ pix_g = zf; /* G */ pix_b = wf; /* B */ pix_a = xf; /* A */ break; case PICT_b8g8r8x8: pix_r = yf; /* R */ pix_g = zf; /* G */ pix_b = wf; /* B */ pix_a = 1.0; /* A */ break; case PICT_x1r5g5b5: case PICT_x8r8g8b8: case PICT_r5g6b5: pix_r = zf; /* R */ pix_g = yf; /* G */ pix_b = xf; /* B */ pix_a = 1.0; /* A */ break; case PICT_a8: pix_r = 0.0; /* R */ pix_g = 0.0; /* G */ pix_b = 0.0; /* B */ pix_a = xf; /* A */ break; default: ErrorF("Bad format 0x%x\n", format); } if (unit == 0) { if (!accel_state->msk_pic) { if (PICT_FORMAT_RGB(format) == 0) { pix_r = 0.0; pix_g = 0.0; pix_b = 0.0; } if (PICT_FORMAT_A(format) == 0) pix_a = 1.0; } else { if (accel_state->component_alpha) { if (accel_state->src_alpha) { /* required for PictOpOver */ float cblend[4] = { pix_r / pix_a, pix_g / pix_a, pix_b / pix_a, pix_a / pix_a }; evergreen_set_blend_color(pScrn, cblend); if (PICT_FORMAT_A(format) == 0) { pix_r = 1.0; pix_g = 1.0; pix_b = 1.0; pix_a = 1.0; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } else { if (PICT_FORMAT_A(format) == 0) pix_a = 1.0; } } else { if (PICT_FORMAT_RGB(format) == 0) { pix_r = 0; pix_g = 0; pix_b = 0; } if (PICT_FORMAT_A(format) == 0) pix_a = 1.0; } } } else { if (accel_state->component_alpha) { if (PICT_FORMAT_A(format) == 0) pix_a = 1.0; } else { if (PICT_FORMAT_A(format) == 0) { pix_r = 1.0; pix_g = 1.0; pix_b = 1.0; pix_a = 1.0; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } } buf[0] = pix_r; buf[1] = pix_g; buf[2] = pix_b; buf[3] = pix_a; } static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t dst_format; cb_config_t cb_conf; shader_config_t vs_conf, ps_conf; const_config_t vs_const_conf; struct r600_accel_object src_obj, mask_obj, dst_obj; float *cbuf; uint32_t ps_bool_consts = 0; if (pDst->drawable.bitsPerPixel < 8 || (pSrc && pSrc->drawable.bitsPerPixel < 8)) return FALSE; if (pSrc) { src_obj.bo = radeon_get_pixmap_bo(pSrc); src_obj.surface = radeon_get_pixmap_surface(pSrc); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = pSrc->drawable.bitsPerPixel; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; } dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.surface = radeon_get_pixmap_surface(pDst); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = pDst->drawable.bitsPerPixel; if (radeon_get_pixmap_shared(pDst) == TRUE) dst_obj.domain = RADEON_GEM_DOMAIN_GTT; else dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (pMaskPicture) { if (pMask) { mask_obj.bo = radeon_get_pixmap_bo(pMask); mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8); mask_obj.surface = radeon_get_pixmap_surface(pMask); mask_obj.width = pMask->drawable.width; mask_obj.height = pMask->drawable.height; mask_obj.bpp = pMask->drawable.bitsPerPixel; mask_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; } accel_state->msk_pic = pMaskPicture; if (pMaskPicture->componentAlpha) { accel_state->component_alpha = TRUE; if (EVERGREENBlendOp[op].src_alpha) accel_state->src_alpha = TRUE; else accel_state->src_alpha = FALSE; } else { accel_state->component_alpha = FALSE; accel_state->src_alpha = FALSE; } } else { accel_state->msk_pic = NULL; accel_state->component_alpha = FALSE; accel_state->src_alpha = FALSE; } if (!R600SetAccelState(pScrn, pSrc ? &src_obj : NULL, (pMaskPicture && pMask) ? &mask_obj : NULL, &dst_obj, accel_state->comp_vs_offset, accel_state->comp_ps_offset, 3, 0xffffffff)) return FALSE; if (!EVERGREENGetDestFormat(pDstPicture, &dst_format)) return FALSE; CLEAR (cb_conf); CLEAR (vs_conf); CLEAR (ps_conf); CLEAR (vs_const_conf); if (pMask) radeon_vbo_check(pScrn, &accel_state->vbo, 24); else radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_vbo_check(pScrn, &accel_state->cbuf, 256); radeon_cp_start(pScrn); evergreen_set_default_state(pScrn); evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); if (pSrc) { if (!EVERGREENTextureSetup(pSrcPicture, pSrc, 0)) { radeon_ib_discard(pScrn); radeon_cs_flush_indirect(pScrn); return FALSE; } } else accel_state->is_transform[0] = FALSE; if (pMask) { if (!EVERGREENTextureSetup(pMaskPicture, pMask, 1)) { radeon_ib_discard(pScrn); radeon_cs_flush_indirect(pScrn); return FALSE; } } else accel_state->is_transform[1] = FALSE; if (pSrc) ps_bool_consts |= (1 << 0); if (pMask) ps_bool_consts |= (1 << 1); evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, ps_bool_consts); if (pMask) { evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (1 << 0)); } else { evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (0 << 0)); } /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 5; vs_conf.stack_size = 1; vs_conf.bo = accel_state->shaders_bo; evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 2; ps_conf.stack_size = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.format = dst_format; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: case PICT_a1r5g5b5: case PICT_x1r5g5b5: default: cb_conf.comp_swap = 1; /* ARGB */ break; case PICT_a8b8g8r8: case PICT_x8b8g8r8: cb_conf.comp_swap = 0; /* ABGR */ break; case PICT_b8g8r8a8: case PICT_b8g8r8x8: cb_conf.comp_swap = 3; /* BGRA */ break; case PICT_r5g6b5: cb_conf.comp_swap = 2; /* RGB */ break; case PICT_a8: cb_conf.comp_swap = 3; /* A */ break; } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; cb_conf.blendcntl = EVERGREENGetBlendCntl(op, pMaskPicture, pDstPicture->format); cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit; cb_conf.rop = 3; cb_conf.pmask = 0xf; if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) { cb_conf.array_mode = 0; cb_conf.non_disp_tiling = 1; } #if X_BYTE_ORDER == X_BIG_ENDIAN switch (dst_obj.bpp) { case 16: cb_conf.endian = ENDIAN_8IN16; break; case 32: cb_conf.endian = ENDIAN_8IN32; break; default: break; } #endif evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); if (pMask) evergreen_set_spi(pScrn, (2 - 1), 2); else evergreen_set_spi(pScrn, (1 - 1), 1); /* VS alu constants */ vs_const_conf.size_bytes = 256; vs_const_conf.type = SHADER_TYPE_VS; cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); vs_const_conf.bo = accel_state->cbuf.vb_bo; vs_const_conf.const_addr = accel_state->cbuf.vb_offset; vs_const_conf.cpu_ptr = (uint32_t *)(char *)cbuf; EVERGREENXFormSetup(pSrcPicture, pScrn, 0, cbuf); if (pMask) EVERGREENXFormSetup(pMaskPicture, pScrn, 1, cbuf); if (!pSrc) { /* solid src color */ EVERGREENSetSolidConsts(pScrn, &cbuf[16], pSrcPicture->format, pSrcPicture->pSourcePict->solidFill.color, 0); } if (!pMaskPicture) { /* use identity constant if there is no mask */ cbuf[20] = 1.0; cbuf[21] = 1.0; cbuf[22] = 1.0; cbuf[23] = 1.0; } else if (!pMask) { /* solid mask color */ EVERGREENSetSolidConsts(pScrn, &cbuf[20], pMaskPicture->format, pMaskPicture->pSourcePict->solidFill.color, 1); } radeon_vbo_commit(pScrn, &accel_state->cbuf); evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->composite_op = op; accel_state->dst_pic = pDstPicture; accel_state->src_pic = pSrcPicture; accel_state->dst_pix = pDst; accel_state->msk_pix = pMask; accel_state->src_pix = pSrc; return TRUE; } static void EVERGREENFinishComposite(ScrnInfoPtr pScrn, PixmapPtr pDst, struct radeon_accel_state *accel_state) { int vtx_size; if (accel_state->vsync) evergreen_cp_wait_vline_sync(pScrn, pDst, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); vtx_size = accel_state->msk_pix ? 24 : 16; evergreen_finish_op(pScrn, vtx_size); } static void EVERGREENDoneComposite(PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; EVERGREENFinishComposite(pScrn, pDst, accel_state); } static void EVERGREENComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; if (CS_FULL(info->cs)) { EVERGREENFinishComposite(pScrn, pDst, info->accel_state); radeon_cs_flush_indirect(pScrn); EVERGREENPrepareComposite(info->accel_state->composite_op, info->accel_state->src_pic, info->accel_state->msk_pic, info->accel_state->dst_pic, info->accel_state->src_pix, info->accel_state->msk_pix, info->accel_state->dst_pix); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); if (accel_state->msk_pix) { vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)maskX; vb[5] = (float)maskY; vb[6] = (float)dstX; vb[7] = (float)(dstY + h); vb[8] = (float)srcX; vb[9] = (float)(srcY + h); vb[10] = (float)maskX; vb[11] = (float)(maskY + h); vb[12] = (float)(dstX + w); vb[13] = (float)(dstY + h); vb[14] = (float)(srcX + w); vb[15] = (float)(srcY + h); vb[16] = (float)(maskX + w); vb[17] = (float)(maskY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } else { vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + h); vb[6] = (float)srcX; vb[7] = (float)(srcY + h); vb[8] = (float)(dstX + w); vb[9] = (float)(dstY + h); vb[10] = (float)(srcX + w); vb[11] = (float)(srcY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } } static Bool EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_dst; unsigned char *dst; unsigned size; uint32_t dst_domain; int bpp = pDst->drawable.bitsPerPixel; uint32_t scratch_pitch; uint32_t copy_pitch; uint32_t dst_pitch_hw = exaGetPixmapPitch(pDst) / (bpp / 8); int ret; Bool flush = TRUE; Bool r; int i; struct r600_accel_object src_obj, dst_obj; uint32_t height, base_align; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pDst); if (!driver_priv || !driver_priv->bo) return FALSE; /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ copy_dst = driver_priv->bo; copy_pitch = pDst->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { flush = FALSE; if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) && !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) goto copy; } } scratch_pitch = RADEON_ALIGN(w, drmmode_get_pitch_align(pScrn, (bpp / 8), 0)); height = RADEON_ALIGN(h, drmmode_get_height_align(pScrn, 0)); base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); size = scratch_pitch * height * (bpp / 8); scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } src_obj.pitch = scratch_pitch; src_obj.width = w; src_obj.height = h; src_obj.bpp = bpp; src_obj.domain = RADEON_GEM_DOMAIN_GTT; src_obj.bo = scratch; src_obj.tiling_flags = 0; src_obj.surface = NULL; dst_obj.pitch = dst_pitch_hw; dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = bpp; dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); dst_obj.surface = radeon_get_pixmap_surface(pDst); if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, 3, 0xffffffff)) { goto copy; } copy_dst = scratch; copy_pitch = scratch_pitch * (bpp / 8); flush = FALSE; copy: if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_dst, 0); if (ret) { r = FALSE; goto out; } r = TRUE; size = w * bpp / 8; dst = copy_dst->ptr; if (copy_dst == driver_priv->bo) dst += y * copy_pitch + x * bpp / 8; for (i = 0; i < h; i++) { memcpy(dst + i * copy_pitch, src, size); src += src_pitch; } radeon_bo_unmap(copy_dst); if (copy_dst == scratch) { if (info->accel_state->vsync) RADEONVlineHelperSet(pScrn, x, y, x + w, y + h); /* blit from gart to vram */ EVERGREENDoPrepareCopy(pScrn); EVERGREENAppendCopyVertex(pScrn, 0, 0, x, y, w, h); EVERGREENDoCopyVline(pDst); } out: if (scratch) radeon_bo_unref(scratch); return r; } static Bool EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h, char *dst, int dst_pitch) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pSrc->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_src; unsigned size; uint32_t src_domain = 0; int bpp = pSrc->drawable.bitsPerPixel; uint32_t scratch_pitch; uint32_t copy_pitch; uint32_t src_pitch_hw = exaGetPixmapPitch(pSrc) / (bpp / 8); int ret; Bool flush = FALSE; Bool r; struct r600_accel_object src_obj, dst_obj; uint32_t height, base_align; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pSrc); if (!driver_priv || !driver_priv->bo) return FALSE; /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ copy_src = driver_priv->bo; copy_pitch = pSrc->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { src_domain = radeon_bo_get_src_domain(driver_priv->bo); if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) src_domain = 0; else /* A write may be scheduled */ flush = TRUE; } if (!src_domain) radeon_bo_is_busy(driver_priv->bo, &src_domain); if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) goto copy; } if (!accel_state->allowHWDFS) goto copy; scratch_pitch = RADEON_ALIGN(w, drmmode_get_pitch_align(pScrn, (bpp / 8), 0)); height = RADEON_ALIGN(h, drmmode_get_height_align(pScrn, 0)); base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); size = scratch_pitch * height * (bpp / 8); scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0); accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT; radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain); ret = radeon_cs_space_check(info->cs); if (ret) { goto copy; } src_obj.pitch = src_pitch_hw; src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = bpp; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = radeon_get_pixmap_bo(pSrc); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); src_obj.surface = radeon_get_pixmap_surface(pSrc); dst_obj.pitch = scratch_pitch; dst_obj.width = w; dst_obj.height = h; dst_obj.bo = scratch; dst_obj.bpp = bpp; dst_obj.domain = RADEON_GEM_DOMAIN_GTT; dst_obj.tiling_flags = 0; dst_obj.surface = NULL; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, 3, 0xffffffff)) { goto copy; } /* blit from vram to gart */ EVERGREENDoPrepareCopy(pScrn); EVERGREENAppendCopyVertex(pScrn, x, y, 0, 0, w, h); EVERGREENDoCopy(pScrn); copy_src = scratch; copy_pitch = scratch_pitch * (bpp / 8); flush = TRUE; copy: if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_src, 0); if (ret) { ErrorF("failed to map pixmap: %d\n", ret); r = FALSE; goto out; } r = TRUE; w *= bpp / 8; if (copy_src == driver_priv->bo) size = y * copy_pitch + x * bpp / 8; else size = 0; while (h--) { memcpy(dst, copy_src->ptr + size, w); size += copy_pitch; dst += dst_pitch; } radeon_bo_unmap(copy_src); out: if (scratch) radeon_bo_unref(scratch); return r; } static int EVERGREENMarkSync(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; return ++accel_state->exaSyncMarker; } static void EVERGREENSync(ScreenPtr pScreen, int marker) { return; } static Bool EVERGREENAllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; /* 512 bytes per shader for now */ int size = 512 * 9; accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->shaders_bo == NULL) { ErrorF("Allocating shader failed\n"); return FALSE; } return TRUE; } static Bool EVERGREENLoadShaders(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; RADEONChipFamily ChipSet = info->ChipFamily; uint32_t *shader; int ret; ret = radeon_bo_map(accel_state->shaders_bo, 1); if (ret) { FatalError("failed to map shader %d\n", ret); return FALSE; } shader = accel_state->shaders_bo->ptr; /* solid vs --------------------------------------- */ accel_state->solid_vs_offset = 0; evergreen_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4); /* solid ps --------------------------------------- */ accel_state->solid_ps_offset = 512; evergreen_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4); /* copy vs --------------------------------------- */ accel_state->copy_vs_offset = 1024; evergreen_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4); /* copy ps --------------------------------------- */ accel_state->copy_ps_offset = 1536; evergreen_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4); /* comp vs --------------------------------------- */ accel_state->comp_vs_offset = 2048; evergreen_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4); /* comp ps --------------------------------------- */ accel_state->comp_ps_offset = 2560; evergreen_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); /* xv vs --------------------------------------- */ accel_state->xv_vs_offset = 3072; evergreen_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4); /* xv ps --------------------------------------- */ accel_state->xv_ps_offset = 3584; evergreen_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); radeon_bo_unmap(accel_state->shaders_bo); return TRUE; } static Bool CAYMANLoadShaders(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; RADEONChipFamily ChipSet = info->ChipFamily; uint32_t *shader; int ret; ret = radeon_bo_map(accel_state->shaders_bo, 1); if (ret) { FatalError("failed to map shader %d\n", ret); return FALSE; } shader = accel_state->shaders_bo->ptr; /* solid vs --------------------------------------- */ accel_state->solid_vs_offset = 0; cayman_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4); /* solid ps --------------------------------------- */ accel_state->solid_ps_offset = 512; cayman_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4); /* copy vs --------------------------------------- */ accel_state->copy_vs_offset = 1024; cayman_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4); /* copy ps --------------------------------------- */ accel_state->copy_ps_offset = 1536; cayman_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4); /* comp vs --------------------------------------- */ accel_state->comp_vs_offset = 2048; cayman_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4); /* comp ps --------------------------------------- */ accel_state->comp_ps_offset = 2560; cayman_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); /* xv vs --------------------------------------- */ accel_state->xv_vs_offset = 3072; cayman_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4); /* xv ps --------------------------------------- */ accel_state->xv_ps_offset = 3584; cayman_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); radeon_bo_unmap(accel_state->shaders_bo); return TRUE; } Bool EVERGREENDrawInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); if (info->accel_state->exa == NULL) { xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); return FALSE; } info->accel_state->exa->exa_major = EXA_VERSION_MAJOR; info->accel_state->exa->exa_minor = EXA_VERSION_MINOR; info->accel_state->exa->PrepareSolid = EVERGREENPrepareSolid; info->accel_state->exa->Solid = EVERGREENSolid; info->accel_state->exa->DoneSolid = EVERGREENDoneSolid; info->accel_state->exa->PrepareCopy = EVERGREENPrepareCopy; info->accel_state->exa->Copy = EVERGREENCopy; info->accel_state->exa->DoneCopy = EVERGREENDoneCopy; info->accel_state->exa->MarkSync = EVERGREENMarkSync; info->accel_state->exa->WaitMarker = EVERGREENSync; info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; info->accel_state->exa->UploadToScreen = EVERGREENUploadToScreen; info->accel_state->exa->DownloadFromScreen = EVERGREENDownloadFromScreen; info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 6) info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking; info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking; #endif info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX | EXA_HANDLES_PIXMAPS | EXA_MIXED_PIXMAPS; info->accel_state->exa->pixmapOffsetAlign = 256; info->accel_state->exa->pixmapPitchAlign = 256; info->accel_state->exa->CheckComposite = EVERGREENCheckComposite; info->accel_state->exa->PrepareComposite = EVERGREENPrepareComposite; info->accel_state->exa->Composite = EVERGREENComposite; info->accel_state->exa->DoneComposite = EVERGREENDoneComposite; info->accel_state->exa->maxPitchBytes = 32768; info->accel_state->exa->maxX = 8192; info->accel_state->exa->maxY = 8192; /* not supported yet */ if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n"); info->accel_state->vsync = TRUE; } else info->accel_state->vsync = FALSE; if (!exaDriverInit(pScreen, info->accel_state->exa)) { free(info->accel_state->exa); return FALSE; } info->accel_state->XInited3D = FALSE; info->accel_state->copy_area = NULL; info->accel_state->src_obj[0].bo = NULL; info->accel_state->src_obj[1].bo = NULL; info->accel_state->dst_obj.bo = NULL; info->accel_state->copy_area_bo = NULL; info->accel_state->vbo.vb_start_op = -1; info->accel_state->cbuf.vb_start_op = -1; info->accel_state->finish_op = evergreen_finish_op; info->accel_state->vbo.verts_per_op = 3; info->accel_state->cbuf.verts_per_op = 1; RADEONVlineHelperClear(pScrn); radeon_vbo_init_lists(pScrn); if (!EVERGREENAllocShaders(pScrn, pScreen)) return FALSE; if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) { if (!CAYMANLoadShaders(pScrn)) return FALSE; } else { if (!EVERGREENLoadShaders(pScrn)) return FALSE; } exaMarkSync(pScreen); return TRUE; } xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_reg.h000066400000000000000000000315461256524674500232760ustar00rootroot00000000000000/* * Evergeen Register documentation * * Copyright (C) 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _EVERGREEN_REG_H_ #define _EVERGREEN_REG_H_ /* * Register definitions */ #include "evergreen_reg_auto.h" enum { SHADER_TYPE_PS, SHADER_TYPE_VS, SHADER_TYPE_GS, SHADER_TYPE_HS, SHADER_TYPE_LS, SHADER_TYPE_CS, SHADER_TYPE_FS, }; /* SET_*_REG offsets + ends */ #define SET_CONFIG_REG_offset 0x00008000 #define SET_CONFIG_REG_end 0x0000ac00 #define SET_CONTEXT_REG_offset 0x00028000 #define SET_CONTEXT_REG_end 0x00029000 #define SET_RESOURCE_offset 0x00030000 #define SET_RESOURCE_end 0x00038000 #define SET_SAMPLER_offset 0x0003c000 #define SET_SAMPLER_end 0x0003c600 #define SET_CTL_CONST_offset 0x0003cff0 #define SET_CTL_CONST_end 0x0003ff0c #define SET_LOOP_CONST_offset 0x0003a200 #define SET_LOOP_CONST_end 0x0003a500 #define SET_BOOL_CONST_offset 0x0003a500 #define SET_BOOL_CONST_end 0x0003a518 /* Packet3 commands */ enum { IT_NOP = 0x10, IT_INDIRECT_BUFFER_END = 0x17, IT_SET_PREDICATION = 0x20, IT_COND_EXEC = 0x22, IT_PRED_EXEC = 0x23, IT_DRAW_INDEX_2 = 0x27, IT_CONTEXT_CONTROL = 0x28, IT_DRAW_INDEX_OFFSET = 0x29, IT_INDEX_TYPE = 0x2A, IT_DRAW_INDEX = 0x2B, IT_DRAW_INDEX_AUTO = 0x2D, IT_DRAW_INDEX_IMMD = 0x2E, IT_NUM_INSTANCES = 0x2F, IT_INDIRECT_BUFFER = 0x32, IT_STRMOUT_BUFFER_UPDATE = 0x34, IT_MEM_SEMAPHORE = 0x39, IT_MPEG_INDEX = 0x3A, IT_WAIT_REG_MEM = 0x3C, IT_MEM_WRITE = 0x3D, IT_SURFACE_SYNC = 0x43, IT_ME_INITIALIZE = 0x44, IT_COND_WRITE = 0x45, IT_EVENT_WRITE = 0x46, IT_EVENT_WRITE_EOP = 0x47, IT_EVENT_WRITE_EOS = 0x48, IT_SET_CONFIG_REG = 0x68, IT_SET_CONTEXT_REG = 0x69, IT_SET_ALU_CONST = 0x6A, IT_SET_BOOL_CONST = 0x6B, IT_SET_LOOP_CONST = 0x6C, IT_SET_RESOURCE = 0x6D, IT_SET_SAMPLER = 0x6E, IT_SET_CTL_CONST = 0x6F, }; /* IT_WAIT_REG_MEM operation encoding */ #define IT_WAIT_ALWAYS (0 << 0) #define IT_WAIT_LT (1 << 0) #define IT_WAIT_LE (2 << 0) #define IT_WAIT_EQ (3 << 0) #define IT_WAIT_NE (4 << 0) #define IT_WAIT_GE (5 << 0) #define IT_WAIT_GT (6 << 0) #define IT_WAIT_REG (0 << 4) #define IT_WAIT_MEM (1 << 4) #define IT_WAIT_ADDR(x) ((x) >> 2) /* IT_INDEX_TYPE */ #define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2) enum { SQ_LDS_ALLOC_PS = 0x288ec, SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c, SQ_LDS_RESOURCE_MGMT = 0x8e2c, WAIT_UNTIL = 0x8040, WAIT_CP_DMA_IDLE_bit = 1 << 8, WAIT_CMDFIFO_bit = 1 << 10, WAIT_3D_IDLE_bit = 1 << 15, WAIT_3D_IDLECLEAN_bit = 1 << 17, WAIT_EXTERN_SIG_bit = 1 << 19, CMDFIFO_ENTRIES_mask = 0xf << 20, CMDFIFO_ENTRIES_shift = 20, CP_COHER_CNTL = 0x85f0, DEST_BASE_0_ENA_bit = 1 << 0, DEST_BASE_1_ENA_bit = 1 << 1, SO0_DEST_BASE_ENA_bit = 1 << 2, SO1_DEST_BASE_ENA_bit = 1 << 3, SO2_DEST_BASE_ENA_bit = 1 << 4, SO3_DEST_BASE_ENA_bit = 1 << 5, CB0_DEST_BASE_ENA_bit = 1 << 6, CB1_DEST_BASE_ENA_bit = 1 << 7, CB2_DEST_BASE_ENA_bit = 1 << 8, CB3_DEST_BASE_ENA_bit = 1 << 9, CB4_DEST_BASE_ENA_bit = 1 << 10, CB5_DEST_BASE_ENA_bit = 1 << 11, CB6_DEST_BASE_ENA_bit = 1 << 12, CB7_DEST_BASE_ENA_bit = 1 << 13, DB_DEST_BASE_ENA_bit = 1 << 14, CB8_DEST_BASE_ENA_bit = 1 << 15, CB9_DEST_BASE_ENA_bit = 1 << 16, CB10_DEST_BASE_ENA_bit = 1 << 17, CB11_DEST_BASE_ENA_bit = 1 << 18, FULL_CACHE_ENA_bit = 1 << 20, TC_ACTION_ENA_bit = 1 << 23, VC_ACTION_ENA_bit = 1 << 24, CB_ACTION_ENA_bit = 1 << 25, DB_ACTION_ENA_bit = 1 << 26, SH_ACTION_ENA_bit = 1 << 27, SX_ACTION_ENA_bit = 1 << 28, CP_COHER_SIZE = 0x85f4, CP_COHER_BASE = 0x85f8, CP_COHER_STATUS = 0x85fc, MATCHING_GFX_CNTX_mask = 0xff << 0, MATCHING_GFX_CNTX_shift = 0, STATUS_bit = 1 << 31, // SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, // SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, FMT_16=5, FMT_16_FLOAT, FMT_8_8, FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, FMT_1 = 37, FMT_GB_GR=39, FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, FMT_32_32_32_FLOAT=48, // High level register file lengths SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, SQ_FETCH_RESOURCE_ps_num = 176, SQ_FETCH_RESOURCE_vs_num = 160, SQ_FETCH_RESOURCE_gs_num = 160, SQ_FETCH_RESOURCE_hs_num = 160, SQ_FETCH_RESOURCE_ls_num = 160, SQ_FETCH_RESOURCE_cs_num = 176, SQ_FETCH_RESOURCE_fs_num = 32, SQ_FETCH_RESOURCE_all_num = 1024, SQ_FETCH_RESOURCE_offset = 32, SQ_FETCH_RESOURCE_ps = 0, // 0...175 SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335 SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495 SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655 SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815 SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991 SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023 SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, SQ_TEX_SAMPLER_WORD_ps_num = 18, SQ_TEX_SAMPLER_WORD_vs_num = 18, SQ_TEX_SAMPLER_WORD_gs_num = 18, SQ_TEX_SAMPLER_WORD_hs_num = 18, SQ_TEX_SAMPLER_WORD_ls_num = 18, SQ_TEX_SAMPLER_WORD_cs_num = 18, SQ_TEX_SAMPLER_WORD_all_num = 108, SQ_TEX_SAMPLER_WORD_offset = 12, SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17 SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35 SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53 SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71 SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89 SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107 SQ_LOOP_CONST = SQ_LOOP_CONST_0, SQ_LOOP_CONST_ps_num = 32, SQ_LOOP_CONST_vs_num = 32, SQ_LOOP_CONST_gs_num = 32, SQ_LOOP_CONST_hs_num = 32, SQ_LOOP_CONST_ls_num = 32, SQ_LOOP_CONST_cs_num = 32, SQ_LOOP_CONST_all_num = 192, SQ_LOOP_CONST_offset = 4, SQ_LOOP_CONST_ps = 0, // 0...31 SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63 SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95 SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127 SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159 SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191 SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */ SQ_BOOL_CONST_ps_num = 1, SQ_BOOL_CONST_vs_num = 1, SQ_BOOL_CONST_gs_num = 1, SQ_BOOL_CONST_hs_num = 1, SQ_BOOL_CONST_ls_num = 1, SQ_BOOL_CONST_cs_num = 1, SQ_BOOL_CONST_all_num = 6, SQ_BOOL_CONST_offset = 4, SQ_BOOL_CONST_ps = 0, SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num, SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num, SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num, }; #endif xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_reg_auto.h000066400000000000000000007564361256524674500243420ustar00rootroot00000000000000/* * Evergreen Register documentation * * Copyright (C) 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _EVERGREEN_REG_AUTO_H #define _EVERGREEN_REG_AUTO_H enum { VGT_VTX_VECT_EJECT_REG = 0x000088b0, PRIM_COUNT_mask = 0x3ff << 0, PRIM_COUNT_shift = 0, VGT_LAST_COPY_STATE = 0x000088c0, SRC_STATE_ID_mask = 0x07 << 0, SRC_STATE_ID_shift = 0, DST_STATE_ID_mask = 0x07 << 16, DST_STATE_ID_shift = 16, VGT_CACHE_INVALIDATION = 0x000088c4, CACHE_INVALIDATION_mask = 0x03 << 0, CACHE_INVALIDATION_shift = 0, VC_ONLY = 0x00, TC_ONLY = 0x01, VC_AND_TC = 0x02, VS_NO_EXTRA_BUFFER_bit = 1 << 5, AUTO_INVLD_EN_mask = 0x03 << 6, AUTO_INVLD_EN_shift = 6, VGT_GS_VERTEX_REUSE = 0x000088d4, VERT_REUSE_mask = 0x1f << 0, VERT_REUSE_shift = 0, VGT_CNTL_STATUS = 0x000088f0, VGT_OUT_INDX_BUSY_bit = 1 << 0, VGT_OUT_BUSY_bit = 1 << 1, VGT_PT_BUSY_bit = 1 << 2, VGT_TE_BUSY_bit = 1 << 3, VGT_VR_BUSY_bit = 1 << 4, VGT_GRP_BUSY_bit = 1 << 5, VGT_DMA_REQ_BUSY_bit = 1 << 6, VGT_DMA_BUSY_bit = 1 << 7, VGT_GS_BUSY_bit = 1 << 8, VGT_HS_BUSY_bit = 1 << 9, VGT_TE11_BUSY_bit = 1 << 10, VGT_BUSY_bit = 1 << 11, VGT_PRIMITIVE_TYPE = 0x00008958, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, DI_PT_NONE = 0x00, DI_PT_POINTLIST = 0x01, DI_PT_LINELIST = 0x02, DI_PT_LINESTRIP = 0x03, DI_PT_TRILIST = 0x04, DI_PT_TRIFAN = 0x05, DI_PT_TRISTRIP = 0x06, DI_PT_UNUSED_0 = 0x07, DI_PT_UNUSED_1 = 0x08, DI_PT_PATCH = 0x09, DI_PT_LINELIST_ADJ = 0x0a, DI_PT_LINESTRIP_ADJ = 0x0b, DI_PT_TRILIST_ADJ = 0x0c, DI_PT_TRISTRIP_ADJ = 0x0d, DI_PT_UNUSED_3 = 0x0e, DI_PT_UNUSED_4 = 0x0f, DI_PT_TRI_WITH_WFLAGS = 0x10, DI_PT_RECTLIST = 0x11, DI_PT_LINELOOP = 0x12, DI_PT_QUADLIST = 0x13, DI_PT_QUADSTRIP = 0x14, DI_PT_POLYGON = 0x15, DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, DI_PT_2D_FILL_RECT_LIST = 0x1a, DI_PT_2D_LINE_STRIP = 0x1b, DI_PT_2D_TRI_STRIP = 0x1c, VGT_INDEX_TYPE = 0x0000895c, INDEX_TYPE_mask = 0x03 << 0, INDEX_TYPE_shift = 0, DI_INDEX_SIZE_16_BIT = 0x00, DI_INDEX_SIZE_32_BIT = 0x01, VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, VGT_NUM_INDICES = 0x00008970, VGT_NUM_INSTANCES = 0x00008974, PA_CL_CNTL_STATUS = 0x00008a10, CL_BUSY_bit = 1 << 31, PA_CL_ENHANCE = 0x00008a14, CLIP_VTX_REORDER_ENA_bit = 1 << 0, NUM_CLIP_SEQ_mask = 0x03 << 1, NUM_CLIP_SEQ_shift = 1, CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, VE_NAN_PROC_DISABLE_bit = 1 << 4, PA_SU_CNTL_STATUS = 0x00008a50, SU_BUSY_bit = 1 << 31, PA_SU_LINE_STIPPLE_VALUE = 0x00008a60, LINE_STIPPLE_VALUE_mask = 0xffffff << 0, LINE_STIPPLE_VALUE_shift = 0, PA_SC_LINE_STIPPLE_STATE = 0x00008b10, CURRENT_PTR_mask = 0x0f << 0, CURRENT_PTR_shift = 0, CURRENT_COUNT_mask = 0xff << 8, CURRENT_COUNT_shift = 8, SQ_CONFIG = 0x00008c00, VC_ENABLE_bit = 1 << 0, EXPORT_SRC_C_bit = 1 << 1, CS_PRIO_mask = 0x03 << 18, CS_PRIO_shift = 18, LS_PRIO_mask = 0x03 << 20, LS_PRIO_shift = 20, HS_PRIO_mask = 0x03 << 22, HS_PRIO_shift = 22, PS_PRIO_mask = 0x03 << 24, PS_PRIO_shift = 24, VS_PRIO_mask = 0x03 << 26, VS_PRIO_shift = 26, GS_PRIO_mask = 0x03 << 28, GS_PRIO_shift = 28, ES_PRIO_mask = 0x03 << 30, ES_PRIO_shift = 30, SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, NUM_PS_GPRS_mask = 0xff << 0, NUM_PS_GPRS_shift = 0, NUM_VS_GPRS_mask = 0xff << 16, NUM_VS_GPRS_shift = 16, NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, NUM_CLAUSE_TEMP_GPRS_shift = 28, SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08, NUM_GS_GPRS_mask = 0xff << 0, NUM_GS_GPRS_shift = 0, NUM_ES_GPRS_mask = 0xff << 16, NUM_ES_GPRS_shift = 16, SQ_GPR_RESOURCE_MGMT_3 = 0x00008c0c, NUM_HS_GPRS_mask = 0xff << 0, NUM_HS_GPRS_shift = 0, NUM_LS_GPRS_mask = 0xff << 16, NUM_LS_GPRS_shift = 16, SQ_GLOBAL_GPR_RESOURCE_MGMT_1 = 0x00008c10, PS_GGPR_BASE_mask = 0xff << 0, PS_GGPR_BASE_shift = 0, VS_GGPR_BASE_mask = 0xff << 8, VS_GGPR_BASE_shift = 8, GS_GGPR_BASE_mask = 0xff << 16, GS_GGPR_BASE_shift = 16, ES_GGPR_BASE_mask = 0xff << 24, ES_GGPR_BASE_shift = 24, SQ_GLOBAL_GPR_RESOURCE_MGMT_2 = 0x00008c14, HS_GGPR_BASE_mask = 0xff << 0, HS_GGPR_BASE_shift = 0, LS_GGPR_BASE_mask = 0xff << 8, LS_GGPR_BASE_shift = 8, CS_GGPR_BASE_mask = 0xff << 16, CS_GGPR_BASE_shift = 16, SQ_THREAD_RESOURCE_MGMT = 0x00008c18, NUM_PS_THREADS_mask = 0xff << 0, NUM_PS_THREADS_shift = 0, NUM_VS_THREADS_mask = 0xff << 8, NUM_VS_THREADS_shift = 8, NUM_GS_THREADS_mask = 0xff << 16, NUM_GS_THREADS_shift = 16, NUM_ES_THREADS_mask = 0xff << 24, NUM_ES_THREADS_shift = 24, SQ_THREAD_RESOURCE_MGMT_2 = 0x00008c1c, NUM_HS_THREADS_mask = 0xff << 0, NUM_HS_THREADS_shift = 0, NUM_LS_THREADS_mask = 0xff << 8, NUM_LS_THREADS_shift = 8, SQ_STACK_RESOURCE_MGMT_1 = 0x00008c20, NUM_PS_STACK_ENTRIES_mask = 0xfff << 0, NUM_PS_STACK_ENTRIES_shift = 0, NUM_VS_STACK_ENTRIES_mask = 0xfff << 16, NUM_VS_STACK_ENTRIES_shift = 16, SQ_STACK_RESOURCE_MGMT_2 = 0x00008c24, NUM_GS_STACK_ENTRIES_mask = 0xfff << 0, NUM_GS_STACK_ENTRIES_shift = 0, NUM_ES_STACK_ENTRIES_mask = 0xfff << 16, NUM_ES_STACK_ENTRIES_shift = 16, SQ_STACK_RESOURCE_MGMT_3 = 0x00008c28, NUM_HS_STACK_ENTRIES_mask = 0xfff << 0, NUM_HS_STACK_ENTRIES_shift = 0, NUM_LS_STACK_ENTRIES_mask = 0xfff << 16, NUM_LS_STACK_ENTRIES_shift = 16, SQ_ESGS_RING_BASE = 0x00008c40, SQ_ESGS_RING_SIZE = 0x00008c44, SQ_GSVS_RING_BASE = 0x00008c48, SQ_GSVS_RING_SIZE = 0x00008c4c, SQ_ESTMP_RING_BASE = 0x00008c50, SQ_ESTMP_RING_SIZE = 0x00008c54, SQ_GSTMP_RING_BASE = 0x00008c58, SQ_GSTMP_RING_SIZE = 0x00008c5c, SQ_VSTMP_RING_BASE = 0x00008c60, SQ_VSTMP_RING_SIZE = 0x00008c64, SQ_PSTMP_RING_BASE = 0x00008c68, SQ_PSTMP_RING_SIZE = 0x00008c6c, SQ_CONST_MEM_BASE = 0x00008df8, SQ_ALU_WORD1_OP3 = 0x00008dfc, SRC2_SEL_mask = 0x1ff << 0, SRC2_SEL_shift = 0, SQ_ALU_SRC_LDS_OQ_A = 0xdb, SQ_ALU_SRC_LDS_OQ_B = 0xdc, SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, SQ_ALU_SRC_TIME_HI = 0xe3, SQ_ALU_SRC_TIME_LO = 0xe4, SQ_ALU_SRC_MASK_HI = 0xe5, SQ_ALU_SRC_MASK_LO = 0xe6, SQ_ALU_SRC_HW_WAVE_ID = 0xe7, SQ_ALU_SRC_SIMD_ID = 0xe8, SQ_ALU_SRC_SE_ID = 0xe9, SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, SQ_ALU_SRC_HW_ALU_ODD = 0xed, SQ_ALU_SRC_LOOP_IDX = 0xee, SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, SQ_ALU_SRC_1_DBL_L = 0xf4, SQ_ALU_SRC_1_DBL_M = 0xf5, SQ_ALU_SRC_0_5_DBL_L = 0xf6, SQ_ALU_SRC_0_5_DBL_M = 0xf7, SQ_ALU_SRC_0 = 0xf8, SQ_ALU_SRC_1 = 0xf9, SQ_ALU_SRC_1_INT = 0xfa, SQ_ALU_SRC_M_1_INT = 0xfb, SQ_ALU_SRC_0_5 = 0xfc, SQ_ALU_SRC_LITERAL = 0xfd, SQ_ALU_SRC_PV = 0xfe, SQ_ALU_SRC_PS = 0xff, SRC2_REL_bit = 1 << 9, SRC2_CHAN_mask = 0x03 << 10, SRC2_CHAN_shift = 10, SQ_CHAN_X = 0x00, SQ_CHAN_Y = 0x01, SQ_CHAN_Z = 0x02, SQ_CHAN_W = 0x03, SRC2_NEG_bit = 1 << 12, SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, SQ_OP3_INST_BFE_UINT = 0x04, SQ_OP3_INST_BFE_INT = 0x05, SQ_OP3_INST_BFI_INT = 0x06, SQ_OP3_INST_FMA = 0x07, SQ_OP3_INST_CNDNE_64 = 0x09, SQ_OP3_INST_FMA_64 = 0x0a, SQ_OP3_INST_LERP_UINT = 0x0b, SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, SQ_OP3_INST_MULADD_UINT24 = 0x10, SQ_OP3_INST_LDS_IDX_OP = 0x11, SQ_OP3_INST_MULADD = 0x14, SQ_OP3_INST_MULADD_M2 = 0x15, SQ_OP3_INST_MULADD_M4 = 0x16, SQ_OP3_INST_MULADD_D2 = 0x17, SQ_OP3_INST_MULADD_IEEE = 0x18, SQ_OP3_INST_CNDE = 0x19, SQ_OP3_INST_CNDGT = 0x1a, SQ_OP3_INST_CNDGE = 0x1b, SQ_OP3_INST_CNDE_INT = 0x1c, SQ_OP3_INST_CNDGT_INT = 0x1d, SQ_OP3_INST_CNDGE_INT = 0x1e, SQ_OP3_INST_MUL_LIT = 0x1f, SQ_ALU_WORD1_LDS_DIRECT_LITERAL_LO = 0x00008dfc, OFFSET_A_mask = 0x1fff << 0, OFFSET_A_shift = 0, STRIDE_A_mask = 0x7f << 13, STRIDE_A_shift = 13, THREAD_REL_A_bit = 1 << 22, SQ_TEX_WORD2 = 0x00008dfc, OFFSET_X_mask = 0x1f << 0, OFFSET_X_shift = 0, OFFSET_Y_mask = 0x1f << 5, OFFSET_Y_shift = 5, OFFSET_Z_mask = 0x1f << 10, OFFSET_Z_shift = 10, SAMPLER_ID_mask = 0x1f << 15, SAMPLER_ID_shift = 15, SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, SQ_TEX_WORD2__SRC_SEL_X_shift = 20, SQ_SEL_X = 0x00, SQ_SEL_Y = 0x01, SQ_SEL_Z = 0x02, SQ_SEL_W = 0x03, SQ_SEL_0 = 0x04, SQ_SEL_1 = 0x05, SRC_SEL_Y_mask = 0x07 << 23, SRC_SEL_Y_shift = 23, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_Z_mask = 0x07 << 26, SRC_SEL_Z_shift = 26, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_W_mask = 0x07 << 29, SRC_SEL_W_shift = 29, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, BURST_COUNT_mask = 0x0f << 16, BURST_COUNT_shift = 16, VALID_PIXEL_MODE_bit = 1 << 20, END_OF_PROGRAM_bit = 1 << 21, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xff << 22, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, SQ_CF_INST_MEM_STREAM0_BUF0 = 0x40, SQ_CF_INST_MEM_STREAM0_BUF1 = 0x41, SQ_CF_INST_MEM_STREAM0_BUF2 = 0x42, SQ_CF_INST_MEM_STREAM0_BUF3 = 0x43, SQ_CF_INST_MEM_STREAM1_BUF0 = 0x44, SQ_CF_INST_MEM_STREAM1_BUF1 = 0x45, SQ_CF_INST_MEM_STREAM1_BUF2 = 0x46, SQ_CF_INST_MEM_STREAM1_BUF3 = 0x47, SQ_CF_INST_MEM_STREAM2_BUF0 = 0x48, SQ_CF_INST_MEM_STREAM2_BUF1 = 0x49, SQ_CF_INST_MEM_STREAM2_BUF2 = 0x4a, SQ_CF_INST_MEM_STREAM2_BUF3 = 0x4b, SQ_CF_INST_MEM_STREAM3_BUF0 = 0x4c, SQ_CF_INST_MEM_STREAM3_BUF1 = 0x4d, SQ_CF_INST_MEM_STREAM3_BUF2 = 0x4e, SQ_CF_INST_MEM_STREAM3_BUF3 = 0x4f, SQ_CF_INST_MEM_SCRATCH = 0x50, SQ_CF_INST_MEM_RING = 0x52, SQ_CF_INST_EXPORT = 0x53, SQ_CF_INST_EXPORT_DONE = 0x54, SQ_CF_INST_MEM_EXPORT = 0x55, SQ_CF_INST_MEM_RAT = 0x56, SQ_CF_INST_MEM_RAT_CACHELESS = 0x57, SQ_CF_INST_MEM_RING1 = 0x58, SQ_CF_INST_MEM_RING2 = 0x59, SQ_CF_INST_MEM_RING3 = 0x5a, SQ_CF_INST_MEM_EXPORT_COMBINED = 0x5b, SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS = 0x5c, MARK_bit = 1 << 30, BARRIER_bit = 1 << 31, SQ_CF_ALU_WORD1 = 0x00008dfc, KCACHE_MODE1_mask = 0x03 << 0, KCACHE_MODE1_shift = 0, SQ_CF_KCACHE_NOP = 0x00, SQ_CF_KCACHE_LOCK_1 = 0x01, SQ_CF_KCACHE_LOCK_2 = 0x02, SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, KCACHE_ADDR0_mask = 0xff << 2, KCACHE_ADDR0_shift = 2, KCACHE_ADDR1_mask = 0xff << 10, KCACHE_ADDR1_shift = 10, SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, SQ_CF_ALU_WORD1__COUNT_shift = 18, SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, SQ_CF_ALU_WORD1__CF_INST_shift = 26, SQ_CF_INST_ALU = 0x08, SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, SQ_CF_INST_ALU_POP_AFTER = 0x0a, SQ_CF_INST_ALU_POP2_AFTER = 0x0b, SQ_CF_INST_ALU_EXTENDED = 0x0c, SQ_CF_INST_ALU_CONTINUE = 0x0d, SQ_CF_INST_ALU_BREAK = 0x0e, SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, WHOLE_QUAD_MODE_bit = 1 << 30, /* BARRIER_bit = 1 << 31, */ SQ_TEX_WORD1 = 0x00008dfc, SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, SQ_TEX_WORD1__DST_GPR_shift = 0, SQ_TEX_WORD1__DST_REL_bit = 1 << 7, SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_TEX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_SEL_MASK = 0x07, SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_TEX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_TEX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_TEX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, SQ_TEX_WORD1__LOD_BIAS_shift = 21, COORD_TYPE_X_bit = 1 << 28, COORD_TYPE_Y_bit = 1 << 29, COORD_TYPE_Z_bit = 1 << 30, COORD_TYPE_W_bit = 1 << 31, SQ_VTX_WORD0 = 0x00008dfc, VTX_INST_mask = 0x1f << 0, VTX_INST_shift = 0, SQ_VTX_INST_FETCH = 0x00, SQ_VTX_INST_SEMANTIC = 0x01, SQ_VTX_INST_GET_BUFFER_RESINFO = 0x0e, FETCH_TYPE_mask = 0x03 << 5, FETCH_TYPE_shift = 5, SQ_VTX_FETCH_VERTEX_DATA = 0x00, SQ_VTX_FETCH_INSTANCE_DATA = 0x01, SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, FETCH_WHOLE_QUAD_bit = 1 << 7, BUFFER_ID_mask = 0xff << 8, BUFFER_ID_shift = 8, SQ_VTX_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_VTX_WORD0__SRC_GPR_shift = 16, SRC_REL_bit = 1 << 23, SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, SQ_VTX_WORD0__SRC_SEL_X_shift = 24, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ MEGA_FETCH_COUNT_mask = 0x3f << 26, MEGA_FETCH_COUNT_shift = 26, SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, SEL_X_mask = 0x07 << 0, SEL_X_shift = 0, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Y_mask = 0x07 << 3, SEL_Y_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Z_mask = 0x07 << 6, SEL_Z_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_W_mask = 0x07 << 9, SEL_W_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD0 = 0x00008dfc, MEM_INST_mask = 0x1f << 0, MEM_INST_shift = 0, SQ_MEM_INST_MEM = 0x02, SQ_MEM_RD_WORD0__ELEM_SIZE_mask = 0x03 << 5, SQ_MEM_RD_WORD0__ELEM_SIZE_shift = 5, /* FETCH_WHOLE_QUAD_bit = 1 << 7, */ MEM_OP_mask = 0x07 << 8, MEM_OP_shift = 8, SQ_MEM_OP_RD_SCRATCH = 0x00, SQ_MEM_OP_RD_SCATTER = 0x02, SQ_MEM_OP_GDS = 0x04, SQ_MEM_OP_TF_WRITE = 0x05, SQ_MEM_RD_WORD0__UNCACHED_bit = 1 << 11, INDEXED_bit = 1 << 12, SQ_MEM_RD_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_MEM_RD_WORD0__SRC_GPR_shift = 16, /* SRC_REL_bit = 1 << 23, */ SQ_MEM_RD_WORD0__SRC_SEL_X_mask = 0x03 << 24, SQ_MEM_RD_WORD0__SRC_SEL_X_shift = 24, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ BURST_CNT_mask = 0x0f << 26, BURST_CNT_shift = 26, SQ_ALU_WORD1 = 0x00008dfc, SQ_ALU_WORD1__ENCODING_mask = 0x07 << 15, SQ_ALU_WORD1__ENCODING_shift = 15, BANK_SWIZZLE_mask = 0x07 << 18, BANK_SWIZZLE_shift = 18, SQ_ALU_VEC_012 = 0x00, SQ_ALU_VEC_021 = 0x01, SQ_ALU_VEC_120 = 0x02, SQ_ALU_VEC_102 = 0x03, SQ_ALU_VEC_201 = 0x04, SQ_ALU_VEC_210 = 0x05, SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, SQ_ALU_WORD1__DST_GPR_shift = 21, SQ_ALU_WORD1__DST_REL_bit = 1 << 28, DST_CHAN_mask = 0x03 << 29, DST_CHAN_shift = 29, CHAN_X = 0x00, CHAN_Y = 0x01, CHAN_Z = 0x02, CHAN_W = 0x03, SQ_ALU_WORD1__CLAMP_bit = 1 << 31, SQ_CF_ALU_WORD0_EXT = 0x00008dfc, KCACHE_BANK_INDEX_MODE0_mask = 0x03 << 4, KCACHE_BANK_INDEX_MODE0_shift = 4, SQ_CF_INDEX_NONE = 0x00, SQ_CF_INDEX_0 = 0x01, SQ_CF_INDEX_1 = 0x02, SQ_CF_INVALID = 0x03, KCACHE_BANK_INDEX_MODE1_mask = 0x03 << 6, KCACHE_BANK_INDEX_MODE1_shift = 6, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK_INDEX_MODE2_mask = 0x03 << 8, KCACHE_BANK_INDEX_MODE2_shift = 8, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK_INDEX_MODE3_mask = 0x03 << 10, KCACHE_BANK_INDEX_MODE3_shift = 10, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ KCACHE_BANK2_mask = 0x0f << 22, KCACHE_BANK2_shift = 22, KCACHE_BANK3_mask = 0x0f << 26, KCACHE_BANK3_shift = 26, KCACHE_MODE2_mask = 0x03 << 30, KCACHE_MODE2_shift = 30, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ SQ_ALU_WORD0_LDS_IDX_OP = 0x00008dfc, SRC0_SEL_mask = 0x1ff << 0, SRC0_SEL_shift = 0, /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC0_REL_bit = 1 << 9, SRC0_CHAN_mask = 0x03 << 10, SRC0_CHAN_shift = 10, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_4_bit = 1 << 12, SRC1_SEL_mask = 0x1ff << 13, SRC1_SEL_shift = 13, /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC1_REL_bit = 1 << 22, SRC1_CHAN_mask = 0x03 << 23, SRC1_CHAN_shift = 23, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_5_bit = 1 << 25, INDEX_MODE_mask = 0x07 << 26, INDEX_MODE_shift = 26, SQ_INDEX_AR_X = 0x00, SQ_INDEX_LOOP = 0x04, SQ_INDEX_GLOBAL = 0x05, SQ_INDEX_GLOBAL_AR_X = 0x06, PRED_SEL_mask = 0x03 << 29, PRED_SEL_shift = 29, SQ_PRED_SEL_OFF = 0x00, SQ_PRED_SEL_ZERO = 0x02, SQ_PRED_SEL_ONE = 0x03, LAST_bit = 1 << 31, SQ_MEM_GDS_WORD2 = 0x00008dfc, SQ_MEM_GDS_WORD2__DST_SEL_X_mask = 0x07 << 0, SQ_MEM_GDS_WORD2__DST_SEL_X_shift = 0, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_Y_mask = 0x07 << 3, SQ_MEM_GDS_WORD2__DST_SEL_Y_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_Z_mask = 0x07 << 6, SQ_MEM_GDS_WORD2__DST_SEL_Z_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_GDS_WORD2__DST_SEL_W_mask = 0x07 << 9, SQ_MEM_GDS_WORD2__DST_SEL_W_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_CF_ALLOC_EXPORT_WORD0_RAT = 0x00008dfc, RAT_ID_mask = 0x0f << 0, RAT_ID_shift = 0, RAT_INST_mask = 0x3f << 4, RAT_INST_shift = 4, SQ_EXPORT_RAT_INST_NOP = 0x00, SQ_EXPORT_RAT_INST_STORE_TYPED = 0x01, SQ_EXPORT_RAT_INST_STORE_RAW = 0x02, SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x03, SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x04, SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x05, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x06, SQ_EXPORT_RAT_INST_ADD = 0x07, SQ_EXPORT_RAT_INST_SUB = 0x08, SQ_EXPORT_RAT_INST_RSUB = 0x09, SQ_EXPORT_RAT_INST_MIN_INT = 0x0a, SQ_EXPORT_RAT_INST_MIN_UINT = 0x0b, SQ_EXPORT_RAT_INST_MAX_INT = 0x0c, SQ_EXPORT_RAT_INST_MAX_UINT = 0x0d, SQ_EXPORT_RAT_INST_AND = 0x0e, SQ_EXPORT_RAT_INST_OR = 0x0f, SQ_EXPORT_RAT_INST_XOR = 0x10, SQ_EXPORT_RAT_INST_MSKOR = 0x11, SQ_EXPORT_RAT_INST_INC_UINT = 0x12, SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, RAT_INDEX_MODE_mask = 0x03 << 11, RAT_INDEX_MODE_shift = 11, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_mask = 0x03 << 13, SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_shift = 13, SQ_EXPORT_PIXEL = 0x00, SQ_EXPORT_POS = 0x01, SQ_EXPORT_PARAM = 0x02, X_UNUSED_FOR_SX_EXPORTS = 0x03, RW_GPR_mask = 0x7f << 15, RW_GPR_shift = 15, RW_REL_bit = 1 << 22, INDEX_GPR_mask = 0x7f << 23, INDEX_GPR_shift = 23, SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_mask = 0x03 << 30, SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_shift = 30, SQ_CF_ALU_WORD0 = 0x00008dfc, SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, SQ_CF_ALU_WORD0__ADDR_shift = 0, KCACHE_BANK0_mask = 0x0f << 22, KCACHE_BANK0_shift = 22, KCACHE_BANK1_mask = 0x0f << 26, KCACHE_BANK1_shift = 26, KCACHE_MODE0_mask = 0x03 << 30, KCACHE_MODE0_shift = 30, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ SQ_MEM_GDS_WORD1 = 0x00008dfc, SQ_MEM_GDS_WORD1__DST_GPR_mask = 0x7f << 0, SQ_MEM_GDS_WORD1__DST_GPR_shift = 0, DST_REL_MODE_mask = 0x03 << 7, DST_REL_MODE_shift = 7, SQ_REL_NONE = 0x00, SQ_REL_LOOP = 0x01, SQ_REL_GLOBAL = 0x02, GDS_OP_mask = 0x3f << 9, GDS_OP_shift = 9, SQ_DS_INST_ADD = 0x00, SQ_DS_INST_SUB = 0x01, SQ_DS_INST_RSUB = 0x02, SQ_DS_INST_INC = 0x03, SQ_DS_INST_DEC = 0x04, SQ_DS_INST_MIN_INT = 0x05, SQ_DS_INST_MAX_INT = 0x06, SQ_DS_INST_MIN_UINT = 0x07, SQ_DS_INST_MAX_UINT = 0x08, SQ_DS_INST_AND = 0x09, SQ_DS_INST_OR = 0x0a, SQ_DS_INST_XOR = 0x0b, SQ_DS_INST_MSKOR = 0x0c, SQ_DS_INST_WRITE = 0x0d, SQ_DS_INST_WRITE_REL = 0x0e, SQ_DS_INST_WRITE2 = 0x0f, SQ_DS_INST_CMP_STORE = 0x10, SQ_DS_INST_CMP_STORE_SPF = 0x11, SQ_DS_INST_BYTE_WRITE = 0x12, SQ_DS_INST_SHORT_WRITE = 0x13, SQ_DS_INST_ADD_RET = 0x20, SQ_DS_INST_SUB_RET = 0x21, SQ_DS_INST_RSUB_RET = 0x22, SQ_DS_INST_INC_RET = 0x23, SQ_DS_INST_DEC_RET = 0x24, SQ_DS_INST_MIN_INT_RET = 0x25, SQ_DS_INST_MAX_INT_RET = 0x26, SQ_DS_INST_MIN_UINT_RET = 0x27, SQ_DS_INST_MAX_UINT_RET = 0x28, SQ_DS_INST_AND_RET = 0x29, SQ_DS_INST_OR_RET = 0x2a, SQ_DS_INST_XOR_RET = 0x2b, SQ_DS_INST_MSKOR_RET = 0x2c, SQ_DS_INST_XCHG_RET = 0x2d, SQ_DS_INST_XCHG_REL_RET = 0x2e, SQ_DS_INST_XCHG2_RET = 0x2f, SQ_DS_INST_CMP_XCHG_RET = 0x30, SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, SQ_DS_INST_READ_RET = 0x32, SQ_DS_INST_READ_REL_RET = 0x33, SQ_DS_INST_READ2_RET = 0x34, SQ_DS_INST_READWRITE_RET = 0x35, SQ_DS_INST_BYTE_READ_RET = 0x36, SQ_DS_INST_UBYTE_READ_RET = 0x37, SQ_DS_INST_SHORT_READ_RET = 0x38, SQ_DS_INST_USHORT_READ_RET = 0x39, SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, DS_OFFSET_mask = 0x7f << 16, DS_OFFSET_shift = 16, UAV_INDEX_MODE_mask = 0x03 << 24, UAV_INDEX_MODE_shift = 24, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ UAV_ID_mask = 0x0f << 26, UAV_ID_shift = 26, ALLOC_CONSUME_bit = 1 << 30, BCAST_FIRST_REQ_bit = 1 << 31, SQ_MEM_RD_WORD2 = 0x00008dfc, ARRAY_BASE_mask = 0x1fff << 0, ARRAY_BASE_shift = 0, SQ_MEM_RD_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, SQ_MEM_RD_WORD2__ENDIAN_SWAP_shift = 16, SQ_ENDIAN_NONE = 0x00, SQ_ENDIAN_8IN16 = 0x01, SQ_ENDIAN_8IN32 = 0x02, SQ_MEM_RD_WORD2__ARRAY_SIZE_mask = 0xfff << 20, SQ_MEM_RD_WORD2__ARRAY_SIZE_shift = 20, SQ_CF_ALU_WORD1_EXT = 0x00008dfc, KCACHE_MODE3_mask = 0x03 << 0, KCACHE_MODE3_shift = 0, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ KCACHE_ADDR2_mask = 0xff << 2, KCACHE_ADDR2_shift = 2, KCACHE_ADDR3_mask = 0xff << 10, KCACHE_ADDR3_shift = 10, SQ_CF_ALU_WORD1_EXT__CF_INST_mask = 0x0f << 26, SQ_CF_ALU_WORD1_EXT__CF_INST_shift = 26, /* SQ_CF_INST_ALU = 0x08, */ /* SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, */ /* SQ_CF_INST_ALU_POP_AFTER = 0x0a, */ /* SQ_CF_INST_ALU_POP2_AFTER = 0x0b, */ /* SQ_CF_INST_ALU_EXTENDED = 0x0c, */ /* SQ_CF_INST_ALU_CONTINUE = 0x0d, */ /* SQ_CF_INST_ALU_BREAK = 0x0e, */ /* SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, */ /* BARRIER_bit = 1 << 31, */ SQ_CF_GWS_WORD0 = 0x00008dfc, VALUE_mask = 0x3ff << 0, VALUE_shift = 0, RESOURCE_mask = 0x1f << 16, RESOURCE_shift = 16, SIGN_bit = 1 << 25, VAL_INDEX_MODE_mask = 0x03 << 26, VAL_INDEX_MODE_shift = 26, SQ_GWS_INDEX_NONE = 0x00, SQ_GWS_INDEX_0 = 0x01, SQ_GWS_INDEX_1 = 0x02, SQ_GWS_INDEX_MIX = 0x03, RSRC_INDEX_MODE_mask = 0x03 << 28, RSRC_INDEX_MODE_shift = 28, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ GWS_OPCODE_mask = 0x03 << 30, GWS_OPCODE_shift = 30, SQ_GWS_SEMA_V = 0x00, SQ_GWS_SEMA_P = 0x01, SQ_GWS_BARRIER = 0x02, SQ_GWS_INIT = 0x03, SQ_VTX_WORD2 = 0x00008dfc, SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, SQ_VTX_WORD2__OFFSET_shift = 0, SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ CONST_BUF_NO_STRIDE_bit = 1 << 18, MEGA_FETCH_bit = 1 << 19, SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, BUFFER_INDEX_MODE_mask = 0x03 << 21, BUFFER_INDEX_MODE_shift = 21, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xfff << 0, SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, COMP_MASK_mask = 0x0f << 12, COMP_MASK_shift = 12, SQ_CF_WORD0 = 0x00008dfc, SQ_CF_WORD0__ADDR_mask = 0xffffff << 0, SQ_CF_WORD0__ADDR_shift = 0, JUMPTABLE_SEL_mask = 0x07 << 24, JUMPTABLE_SEL_shift = 24, SQ_CF_JUMPTABLE_SEL_CONST_A = 0x00, SQ_CF_JUMPTABLE_SEL_CONST_B = 0x01, SQ_CF_JUMPTABLE_SEL_CONST_C = 0x02, SQ_CF_JUMPTABLE_SEL_CONST_D = 0x03, SQ_CF_JUMPTABLE_SEL_INDEX_0 = 0x04, SQ_CF_JUMPTABLE_SEL_INDEX_1 = 0x05, SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, /* ARRAY_BASE_mask = 0x1fff << 0, */ /* ARRAY_BASE_shift = 0, */ SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, /* SQ_EXPORT_PIXEL = 0x00, */ /* SQ_EXPORT_POS = 0x01, */ /* SQ_EXPORT_PARAM = 0x02, */ /* X_UNUSED_FOR_SX_EXPORTS = 0x03, */ /* RW_GPR_mask = 0x7f << 15, */ /* RW_GPR_shift = 15, */ /* RW_REL_bit = 1 << 22, */ /* INDEX_GPR_mask = 0x7f << 23, */ /* INDEX_GPR_shift = 23, */ SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x03 << 30, SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30, SQ_MEM_GDS_WORD0 = 0x00008dfc, /* MEM_INST_mask = 0x1f << 0, */ /* MEM_INST_shift = 0, */ /* SQ_MEM_INST_MEM = 0x02, */ /* MEM_OP_mask = 0x07 << 8, */ /* MEM_OP_shift = 8, */ /* SQ_MEM_OP_RD_SCRATCH = 0x00, */ /* SQ_MEM_OP_RD_SCATTER = 0x02, */ /* SQ_MEM_OP_GDS = 0x04, */ /* SQ_MEM_OP_TF_WRITE = 0x05, */ SQ_MEM_GDS_WORD0__SRC_GPR_mask = 0x7f << 11, SQ_MEM_GDS_WORD0__SRC_GPR_shift = 11, SRC_REL_MODE_mask = 0x03 << 18, SRC_REL_MODE_shift = 18, /* SQ_REL_NONE = 0x00, */ /* SQ_REL_LOOP = 0x01, */ /* SQ_REL_GLOBAL = 0x02, */ SQ_MEM_GDS_WORD0__SRC_SEL_X_mask = 0x07 << 20, SQ_MEM_GDS_WORD0__SRC_SEL_X_shift = 20, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SRC_SEL_Y_mask = 0x07 << 23, */ /* SRC_SEL_Y_shift = 23, */ /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SRC_SEL_Z_mask = 0x07 << 26, */ /* SRC_SEL_Z_shift = 26, */ /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_ALU_WORD1_LDS_DIRECT_LITERAL_HI = 0x00008dfc, OFFSET_B_mask = 0x1fff << 0, OFFSET_B_shift = 0, STRIDE_B_mask = 0x7f << 13, STRIDE_B_shift = 13, THREAD_REL_B_bit = 1 << 22, DIRECT_READ_32_bit = 1 << 31, SQ_VTX_WORD1 = 0x00008dfc, SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_VTX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_VTX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_VTX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_VTX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ USE_CONST_FIELDS_bit = 1 << 21, SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, SQ_VTX_WORD1__DATA_FORMAT_shift = 22, SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, SQ_NUM_FORMAT_NORM = 0x00, SQ_NUM_FORMAT_INT = 0x01, SQ_NUM_FORMAT_SCALED = 0x02, SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, SQ_ALU_WORD1_OP2 = 0x00008dfc, SRC0_ABS_bit = 1 << 0, SRC1_ABS_bit = 1 << 1, UPDATE_EXECUTE_MASK_bit = 1 << 2, UPDATE_PRED_bit = 1 << 3, WRITE_MASK_bit = 1 << 4, OMOD_mask = 0x03 << 5, OMOD_shift = 5, SQ_ALU_OMOD_OFF = 0x00, SQ_ALU_OMOD_M2 = 0x01, SQ_ALU_OMOD_M4 = 0x02, SQ_ALU_OMOD_D2 = 0x03, SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x7ff << 7, SQ_ALU_WORD1_OP2__ALU_INST_shift = 7, SQ_OP2_INST_ADD = 0x00, SQ_OP2_INST_MUL = 0x01, SQ_OP2_INST_MUL_IEEE = 0x02, SQ_OP2_INST_MAX = 0x03, SQ_OP2_INST_MIN = 0x04, SQ_OP2_INST_MAX_DX10 = 0x05, SQ_OP2_INST_MIN_DX10 = 0x06, SQ_OP2_INST_SETE = 0x08, SQ_OP2_INST_SETGT = 0x09, SQ_OP2_INST_SETGE = 0x0a, SQ_OP2_INST_SETNE = 0x0b, SQ_OP2_INST_SETE_DX10 = 0x0c, SQ_OP2_INST_SETGT_DX10 = 0x0d, SQ_OP2_INST_SETGE_DX10 = 0x0e, SQ_OP2_INST_SETNE_DX10 = 0x0f, SQ_OP2_INST_FRACT = 0x10, SQ_OP2_INST_TRUNC = 0x11, SQ_OP2_INST_CEIL = 0x12, SQ_OP2_INST_RNDNE = 0x13, SQ_OP2_INST_FLOOR = 0x14, SQ_OP2_INST_ASHR_INT = 0x15, SQ_OP2_INST_LSHR_INT = 0x16, SQ_OP2_INST_LSHL_INT = 0x17, SQ_OP2_INST_MOV = 0x19, SQ_OP2_INST_NOP = 0x1a, SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, SQ_OP2_INST_PRED_SETE = 0x20, SQ_OP2_INST_PRED_SETGT = 0x21, SQ_OP2_INST_PRED_SETGE = 0x22, SQ_OP2_INST_PRED_SETNE = 0x23, SQ_OP2_INST_PRED_SET_INV = 0x24, SQ_OP2_INST_PRED_SET_POP = 0x25, SQ_OP2_INST_PRED_SET_CLR = 0x26, SQ_OP2_INST_PRED_SET_RESTORE = 0x27, SQ_OP2_INST_PRED_SETE_PUSH = 0x28, SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, SQ_OP2_INST_KILLE = 0x2c, SQ_OP2_INST_KILLGT = 0x2d, SQ_OP2_INST_KILLGE = 0x2e, SQ_OP2_INST_KILLNE = 0x2f, SQ_OP2_INST_AND_INT = 0x30, SQ_OP2_INST_OR_INT = 0x31, SQ_OP2_INST_XOR_INT = 0x32, SQ_OP2_INST_NOT_INT = 0x33, SQ_OP2_INST_ADD_INT = 0x34, SQ_OP2_INST_SUB_INT = 0x35, SQ_OP2_INST_MAX_INT = 0x36, SQ_OP2_INST_MIN_INT = 0x37, SQ_OP2_INST_MAX_UINT = 0x38, SQ_OP2_INST_MIN_UINT = 0x39, SQ_OP2_INST_SETE_INT = 0x3a, SQ_OP2_INST_SETGT_INT = 0x3b, SQ_OP2_INST_SETGE_INT = 0x3c, SQ_OP2_INST_SETNE_INT = 0x3d, SQ_OP2_INST_SETGT_UINT = 0x3e, SQ_OP2_INST_SETGE_UINT = 0x3f, SQ_OP2_INST_KILLGT_UINT = 0x40, SQ_OP2_INST_KILLGE_UINT = 0x41, SQ_OP2_INST_PRED_SETE_INT = 0x42, SQ_OP2_INST_PRED_SETGT_INT = 0x43, SQ_OP2_INST_PRED_SETGE_INT = 0x44, SQ_OP2_INST_PRED_SETNE_INT = 0x45, SQ_OP2_INST_KILLE_INT = 0x46, SQ_OP2_INST_KILLGT_INT = 0x47, SQ_OP2_INST_KILLGE_INT = 0x48, SQ_OP2_INST_KILLNE_INT = 0x49, SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, SQ_OP2_INST_FLT_TO_INT = 0x50, SQ_OP2_INST_BFREV_INT = 0x51, SQ_OP2_INST_ADDC_UINT = 0x52, SQ_OP2_INST_SUBB_UINT = 0x53, SQ_OP2_INST_GROUP_BARRIER = 0x54, SQ_OP2_INST_GROUP_SEQ_BEGIN = 0x55, SQ_OP2_INST_GROUP_SEQ_END = 0x56, SQ_OP2_INST_SET_MODE = 0x57, SQ_OP2_INST_SET_CF_IDX0 = 0x58, SQ_OP2_INST_SET_CF_IDX1 = 0x59, SQ_OP2_INST_SET_LDS_SIZE = 0x5a, SQ_OP2_INST_EXP_IEEE = 0x81, SQ_OP2_INST_LOG_CLAMPED = 0x82, SQ_OP2_INST_LOG_IEEE = 0x83, SQ_OP2_INST_RECIP_CLAMPED = 0x84, SQ_OP2_INST_RECIP_FF = 0x85, SQ_OP2_INST_RECIP_IEEE = 0x86, SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x87, SQ_OP2_INST_RECIPSQRT_FF = 0x88, SQ_OP2_INST_RECIPSQRT_IEEE = 0x89, SQ_OP2_INST_SQRT_IEEE = 0x8a, SQ_OP2_INST_SIN = 0x8d, SQ_OP2_INST_COS = 0x8e, SQ_OP2_INST_MULLO_INT = 0x8f, SQ_OP2_INST_MULHI_INT = 0x90, SQ_OP2_INST_MULLO_UINT = 0x91, SQ_OP2_INST_MULHI_UINT = 0x92, SQ_OP2_INST_RECIP_INT = 0x93, SQ_OP2_INST_RECIP_UINT = 0x94, SQ_OP2_INST_RECIP_64 = 0x95, SQ_OP2_INST_RECIP_CLAMPED_64 = 0x96, SQ_OP2_INST_RECIPSQRT_64 = 0x97, SQ_OP2_INST_RECIPSQRT_CLAMPED_64 = 0x98, SQ_OP2_INST_SQRT_64 = 0x99, SQ_OP2_INST_FLT_TO_UINT = 0x9a, SQ_OP2_INST_INT_TO_FLT = 0x9b, SQ_OP2_INST_UINT_TO_FLT = 0x9c, SQ_OP2_INST_BFM_INT = 0xa0, SQ_OP2_INST_FLT32_TO_FLT16 = 0xa2, SQ_OP2_INST_FLT16_TO_FLT32 = 0xa3, SQ_OP2_INST_UBYTE0_FLT = 0xa4, SQ_OP2_INST_UBYTE1_FLT = 0xa5, SQ_OP2_INST_UBYTE2_FLT = 0xa6, SQ_OP2_INST_UBYTE3_FLT = 0xa7, SQ_OP2_INST_BCNT_INT = 0xaa, SQ_OP2_INST_FFBH_UINT = 0xab, SQ_OP2_INST_FFBL_INT = 0xac, SQ_OP2_INST_FFBH_INT = 0xad, SQ_OP2_INST_FLT_TO_UINT4 = 0xae, SQ_OP2_INST_DOT_IEEE = 0xaf, SQ_OP2_INST_FLT_TO_INT_RPI = 0xb0, SQ_OP2_INST_FLT_TO_INT_FLOOR = 0xb1, SQ_OP2_INST_MULHI_UINT24 = 0xb2, SQ_OP2_INST_MBCNT_32HI_INT = 0xb3, SQ_OP2_INST_OFFSET_TO_FLT = 0xb4, SQ_OP2_INST_MUL_UINT24 = 0xb5, SQ_OP2_INST_BCNT_ACCUM_PREV_INT = 0xb6, SQ_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 0xb7, SQ_OP2_INST_SETE_64 = 0xb8, SQ_OP2_INST_SETNE_64 = 0xb9, SQ_OP2_INST_SETGT_64 = 0xba, SQ_OP2_INST_SETGE_64 = 0xbb, SQ_OP2_INST_MIN_64 = 0xbc, SQ_OP2_INST_MAX_64 = 0xbd, SQ_OP2_INST_DOT4 = 0xbe, SQ_OP2_INST_DOT4_IEEE = 0xbf, SQ_OP2_INST_CUBE = 0xc0, SQ_OP2_INST_MAX4 = 0xc1, SQ_OP2_INST_FREXP_64 = 0xc4, SQ_OP2_INST_LDEXP_64 = 0xc5, SQ_OP2_INST_FRACT_64 = 0xc6, SQ_OP2_INST_PRED_SETGT_64 = 0xc7, SQ_OP2_INST_PRED_SETE_64 = 0xc8, SQ_OP2_INST_PRED_SETGE_64 = 0xc9, SQ_OP2_INST_MUL_64 = 0xca, SQ_OP2_INST_ADD_64 = 0xcb, SQ_OP2_INST_MOVA_INT = 0xcc, SQ_OP2_INST_FLT64_TO_FLT32 = 0xcd, SQ_OP2_INST_FLT32_TO_FLT64 = 0xce, SQ_OP2_INST_SAD_ACCUM_PREV_UINT = 0xcf, SQ_OP2_INST_DOT = 0xd0, SQ_OP2_INST_MUL_PREV = 0xd1, SQ_OP2_INST_MUL_IEEE_PREV = 0xd2, SQ_OP2_INST_ADD_PREV = 0xd3, SQ_OP2_INST_MULADD_PREV = 0xd4, SQ_OP2_INST_MULADD_IEEE_PREV = 0xd5, SQ_OP2_INST_INTERP_XY = 0xd6, SQ_OP2_INST_INTERP_ZW = 0xd7, SQ_OP2_INST_INTERP_X = 0xd8, SQ_OP2_INST_INTERP_Z = 0xd9, SQ_OP2_INST_STORE_FLAGS = 0xda, SQ_OP2_INST_LOAD_STORE_FLAGS = 0xdb, SQ_OP2_INST_INTERP_LOAD_P0 = 0xe0, SQ_OP2_INST_INTERP_LOAD_P10 = 0xe1, SQ_OP2_INST_INTERP_LOAD_P20 = 0xe2, SQ_CF_WORD1 = 0x00008dfc, POP_COUNT_mask = 0x07 << 0, POP_COUNT_shift = 0, CF_CONST_mask = 0x1f << 3, CF_CONST_shift = 3, COND_mask = 0x03 << 8, COND_shift = 8, SQ_CF_COND_ACTIVE = 0x00, SQ_CF_COND_FALSE = 0x01, SQ_CF_COND_BOOL = 0x02, SQ_CF_COND_NOT_BOOL = 0x03, SQ_CF_WORD1__COUNT_mask = 0x3f << 10, SQ_CF_WORD1__COUNT_shift = 10, /* VALID_PIXEL_MODE_bit = 1 << 20, */ /* END_OF_PROGRAM_bit = 1 << 21, */ SQ_CF_WORD1__CF_INST_mask = 0xff << 22, SQ_CF_WORD1__CF_INST_shift = 22, SQ_CF_INST_NOP = 0x00, SQ_CF_INST_TC = 0x01, SQ_CF_INST_VC = 0x02, SQ_CF_INST_GDS = 0x03, SQ_CF_INST_LOOP_START = 0x04, SQ_CF_INST_LOOP_END = 0x05, SQ_CF_INST_LOOP_START_DX10 = 0x06, SQ_CF_INST_LOOP_START_NO_AL = 0x07, SQ_CF_INST_LOOP_CONTINUE = 0x08, SQ_CF_INST_LOOP_BREAK = 0x09, SQ_CF_INST_JUMP = 0x0a, SQ_CF_INST_PUSH = 0x0b, SQ_CF_INST_ELSE = 0x0d, SQ_CF_INST_POP = 0x0e, SQ_CF_INST_CALL = 0x12, SQ_CF_INST_CALL_FS = 0x13, SQ_CF_INST_RETURN = 0x14, SQ_CF_INST_EMIT_VERTEX = 0x15, SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, SQ_CF_INST_CUT_VERTEX = 0x17, SQ_CF_INST_KILL = 0x18, SQ_CF_INST_WAIT_ACK = 0x1a, SQ_CF_INST_TC_ACK = 0x1b, SQ_CF_INST_VC_ACK = 0x1c, SQ_CF_INST_JUMPTABLE = 0x1d, SQ_CF_INST_GLOBAL_WAVE_SYNC = 0x1e, SQ_CF_INST_HALT = 0x1f, /* WHOLE_QUAD_MODE_bit = 1 << 30, */ /* BARRIER_bit = 1 << 31, */ SQ_VTX_WORD1_SEM = 0x00008dfc, SEMANTIC_ID_mask = 0xff << 0, SEMANTIC_ID_shift = 0, SQ_TEX_WORD0 = 0x00008dfc, TEX_INST_mask = 0x1f << 0, TEX_INST_shift = 0, SQ_TEX_INST_LD = 0x03, SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, SQ_TEX_INST_GET_LOD = 0x06, SQ_TEX_INST_GET_GRADIENTS_H = 0x07, SQ_TEX_INST_GET_GRADIENTS_V = 0x08, SQ_TEX_INST_SET_TEXTURE_OFFSETS = 0x09, SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, SQ_TEX_INST_PASS = 0x0d, SQ_TEX_INST_SAMPLE = 0x10, SQ_TEX_INST_SAMPLE_L = 0x11, SQ_TEX_INST_SAMPLE_LB = 0x12, SQ_TEX_INST_SAMPLE_LZ = 0x13, SQ_TEX_INST_SAMPLE_G = 0x14, SQ_TEX_INST_GATHER4 = 0x15, SQ_TEX_INST_SAMPLE_G_LB = 0x16, SQ_TEX_INST_GATHER4_O = 0x17, SQ_TEX_INST_SAMPLE_C = 0x18, SQ_TEX_INST_SAMPLE_C_L = 0x19, SQ_TEX_INST_SAMPLE_C_LB = 0x1a, SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, SQ_TEX_INST_SAMPLE_C_G = 0x1c, SQ_TEX_INST_GATHER4_C = 0x1d, SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, SQ_TEX_INST_GATHER4_C_O = 0x1f, INST_MOD_mask = 0x03 << 5, INST_MOD_shift = 5, /* FETCH_WHOLE_QUAD_bit = 1 << 7, */ RESOURCE_ID_mask = 0xff << 8, RESOURCE_ID_shift = 8, SQ_TEX_WORD0__SRC_GPR_mask = 0x7f << 16, SQ_TEX_WORD0__SRC_GPR_shift = 16, /* SRC_REL_bit = 1 << 23, */ SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, RESOURCE_INDEX_MODE_mask = 0x03 << 25, RESOURCE_INDEX_MODE_shift = 25, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SAMPLER_INDEX_MODE_mask = 0x03 << 27, SAMPLER_INDEX_MODE_shift = 27, /* SQ_CF_INDEX_NONE = 0x00, */ /* SQ_CF_INDEX_0 = 0x01, */ /* SQ_CF_INDEX_1 = 0x02, */ /* SQ_CF_INVALID = 0x03, */ SQ_VTX_WORD1_GPR = 0x00008dfc, SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, SQ_ALU_WORD1_LDS_IDX_OP = 0x00008dfc, /* SRC2_SEL_mask = 0x1ff << 0, */ /* SRC2_SEL_shift = 0, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC2_REL_bit = 1 << 9, */ /* SRC2_CHAN_mask = 0x03 << 10, */ /* SRC2_CHAN_shift = 10, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ IDX_OFFSET_1_bit = 1 << 12, SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_mask = 0x1f << 13, SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_shift = 13, /* SQ_OP3_INST_BFE_UINT = 0x04, */ /* SQ_OP3_INST_BFE_INT = 0x05, */ /* SQ_OP3_INST_BFI_INT = 0x06, */ /* SQ_OP3_INST_FMA = 0x07, */ /* SQ_OP3_INST_CNDNE_64 = 0x09, */ /* SQ_OP3_INST_FMA_64 = 0x0a, */ /* SQ_OP3_INST_LERP_UINT = 0x0b, */ /* SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, */ /* SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, */ /* SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, */ /* SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, */ /* SQ_OP3_INST_MULADD_UINT24 = 0x10, */ /* SQ_OP3_INST_LDS_IDX_OP = 0x11, */ /* SQ_OP3_INST_MULADD = 0x14, */ /* SQ_OP3_INST_MULADD_M2 = 0x15, */ /* SQ_OP3_INST_MULADD_M4 = 0x16, */ /* SQ_OP3_INST_MULADD_D2 = 0x17, */ /* SQ_OP3_INST_MULADD_IEEE = 0x18, */ /* SQ_OP3_INST_CNDE = 0x19, */ /* SQ_OP3_INST_CNDGT = 0x1a, */ /* SQ_OP3_INST_CNDGE = 0x1b, */ /* SQ_OP3_INST_CNDE_INT = 0x1c, */ /* SQ_OP3_INST_CNDGT_INT = 0x1d, */ /* SQ_OP3_INST_CNDGE_INT = 0x1e, */ /* SQ_OP3_INST_MUL_LIT = 0x1f, */ /* BANK_SWIZZLE_mask = 0x07 << 18, */ /* BANK_SWIZZLE_shift = 18, */ /* SQ_ALU_VEC_012 = 0x00, */ /* SQ_ALU_VEC_021 = 0x01, */ /* SQ_ALU_VEC_120 = 0x02, */ /* SQ_ALU_VEC_102 = 0x03, */ /* SQ_ALU_VEC_201 = 0x04, */ /* SQ_ALU_VEC_210 = 0x05, */ LDS_OP_mask = 0x3f << 21, LDS_OP_shift = 21, /* SQ_DS_INST_ADD = 0x00, */ /* SQ_DS_INST_SUB = 0x01, */ /* SQ_DS_INST_RSUB = 0x02, */ /* SQ_DS_INST_INC = 0x03, */ /* SQ_DS_INST_DEC = 0x04, */ /* SQ_DS_INST_MIN_INT = 0x05, */ /* SQ_DS_INST_MAX_INT = 0x06, */ /* SQ_DS_INST_MIN_UINT = 0x07, */ /* SQ_DS_INST_MAX_UINT = 0x08, */ /* SQ_DS_INST_AND = 0x09, */ /* SQ_DS_INST_OR = 0x0a, */ /* SQ_DS_INST_XOR = 0x0b, */ /* SQ_DS_INST_MSKOR = 0x0c, */ /* SQ_DS_INST_WRITE = 0x0d, */ /* SQ_DS_INST_WRITE_REL = 0x0e, */ /* SQ_DS_INST_WRITE2 = 0x0f, */ /* SQ_DS_INST_CMP_STORE = 0x10, */ /* SQ_DS_INST_CMP_STORE_SPF = 0x11, */ /* SQ_DS_INST_BYTE_WRITE = 0x12, */ /* SQ_DS_INST_SHORT_WRITE = 0x13, */ /* SQ_DS_INST_ADD_RET = 0x20, */ /* SQ_DS_INST_SUB_RET = 0x21, */ /* SQ_DS_INST_RSUB_RET = 0x22, */ /* SQ_DS_INST_INC_RET = 0x23, */ /* SQ_DS_INST_DEC_RET = 0x24, */ /* SQ_DS_INST_MIN_INT_RET = 0x25, */ /* SQ_DS_INST_MAX_INT_RET = 0x26, */ /* SQ_DS_INST_MIN_UINT_RET = 0x27, */ /* SQ_DS_INST_MAX_UINT_RET = 0x28, */ /* SQ_DS_INST_AND_RET = 0x29, */ /* SQ_DS_INST_OR_RET = 0x2a, */ /* SQ_DS_INST_XOR_RET = 0x2b, */ /* SQ_DS_INST_MSKOR_RET = 0x2c, */ /* SQ_DS_INST_XCHG_RET = 0x2d, */ /* SQ_DS_INST_XCHG_REL_RET = 0x2e, */ /* SQ_DS_INST_XCHG2_RET = 0x2f, */ /* SQ_DS_INST_CMP_XCHG_RET = 0x30, */ /* SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, */ /* SQ_DS_INST_READ_RET = 0x32, */ /* SQ_DS_INST_READ_REL_RET = 0x33, */ /* SQ_DS_INST_READ2_RET = 0x34, */ /* SQ_DS_INST_READWRITE_RET = 0x35, */ /* SQ_DS_INST_BYTE_READ_RET = 0x36, */ /* SQ_DS_INST_UBYTE_READ_RET = 0x37, */ /* SQ_DS_INST_SHORT_READ_RET = 0x38, */ /* SQ_DS_INST_USHORT_READ_RET = 0x39, */ /* SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, */ IDX_OFFSET_0_bit = 1 << 27, IDX_OFFSET_2_bit = 1 << 28, /* DST_CHAN_mask = 0x03 << 29, */ /* DST_CHAN_shift = 29, */ /* CHAN_X = 0x00, */ /* CHAN_Y = 0x01, */ /* CHAN_Z = 0x02, */ /* CHAN_W = 0x03, */ IDX_OFFSET_3_bit = 1 << 31, SQ_CF_ENCODING_WORD1 = 0x00008dfc, SQ_CF_ENCODING_WORD1__ENCODING_mask = 0x03 << 28, SQ_CF_ENCODING_WORD1__ENCODING_shift = 28, SQ_CF_ENCODING_INST_CF = 0x00, SQ_CF_ENCODING_INST_ALLOC_EXPORT = 0x01, SQ_CF_ENCODING_INST_ALU0 = 0x02, SQ_CF_ENCODING_INST_ALU1 = 0x03, SQ_ALU_WORD0 = 0x00008dfc, /* SRC0_SEL_mask = 0x1ff << 0, */ /* SRC0_SEL_shift = 0, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC0_REL_bit = 1 << 9, */ /* SRC0_CHAN_mask = 0x03 << 10, */ /* SRC0_CHAN_shift = 10, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC0_NEG_bit = 1 << 12, /* SRC1_SEL_mask = 0x1ff << 13, */ /* SRC1_SEL_shift = 13, */ /* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ /* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ /* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ /* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ /* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ /* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ /* SQ_ALU_SRC_TIME_HI = 0xe3, */ /* SQ_ALU_SRC_TIME_LO = 0xe4, */ /* SQ_ALU_SRC_MASK_HI = 0xe5, */ /* SQ_ALU_SRC_MASK_LO = 0xe6, */ /* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ /* SQ_ALU_SRC_SIMD_ID = 0xe8, */ /* SQ_ALU_SRC_SE_ID = 0xe9, */ /* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ /* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ /* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ /* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ /* SQ_ALU_SRC_LOOP_IDX = 0xee, */ /* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ /* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ /* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ /* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ /* SQ_ALU_SRC_1_DBL_L = 0xf4, */ /* SQ_ALU_SRC_1_DBL_M = 0xf5, */ /* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ /* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ /* SRC1_REL_bit = 1 << 22, */ /* SRC1_CHAN_mask = 0x03 << 23, */ /* SRC1_CHAN_shift = 23, */ /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC1_NEG_bit = 1 << 25, /* INDEX_MODE_mask = 0x07 << 26, */ /* INDEX_MODE_shift = 26, */ /* SQ_INDEX_AR_X = 0x00, */ /* SQ_INDEX_LOOP = 0x04, */ /* SQ_INDEX_GLOBAL = 0x05, */ /* SQ_INDEX_GLOBAL_AR_X = 0x06, */ /* PRED_SEL_mask = 0x03 << 29, */ /* PRED_SEL_shift = 29, */ /* SQ_PRED_SEL_OFF = 0x00, */ /* SQ_PRED_SEL_ZERO = 0x02, */ /* SQ_PRED_SEL_ONE = 0x03, */ /* LAST_bit = 1 << 31, */ SQ_MEM_RD_WORD1 = 0x00008dfc, SQ_MEM_RD_WORD1__DST_GPR_mask = 0x7f << 0, SQ_MEM_RD_WORD1__DST_GPR_shift = 0, SQ_MEM_RD_WORD1__DST_REL_bit = 1 << 7, SQ_MEM_RD_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_MEM_RD_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_MEM_RD_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_MEM_RD_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_MEM_RD_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_MEM_RD_WORD1__DATA_FORMAT_mask = 0x3f << 22, SQ_MEM_RD_WORD1__DATA_FORMAT_shift = 22, SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_shift = 28, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_MEM_RD_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, SQ_MEM_RD_WORD1__SRF_MODE_ALL_bit = 1 << 31, SQ_LSTMP_RING_BASE = 0x00008e10, SQ_LSTMP_RING_SIZE = 0x00008e14, SQ_HSTMP_RING_BASE = 0x00008e18, SQ_HSTMP_RING_SIZE = 0x00008e1c, SX_EXPORT_BUFFER_SIZES = 0x0000900c, COLOR_BUFFER_SIZE_mask = 0xff << 0, COLOR_BUFFER_SIZE_shift = 0, POSITION_BUFFER_SIZE_mask = 0xff << 8, POSITION_BUFFER_SIZE_shift = 8, SMX_BUFFER_SIZE_mask = 0xff << 16, SMX_BUFFER_SIZE_shift = 16, SX_MEMORY_EXPORT_BASE = 0x00009010, SX_MEMORY_EXPORT_SIZE = 0x00009014, SPI_CONFIG_CNTL = 0x00009100, GPR_WRITE_PRIORITY_mask = 0x3ffff << 0, GPR_WRITE_PRIORITY_shift = 0, SPI_CONFIG_CNTL_1 = 0x0000913c, VTX_DONE_DELAY_mask = 0x0f << 0, VTX_DONE_DELAY_shift = 0, X_DELAY_14_CLKS = 0x00, X_DELAY_16_CLKS = 0x01, X_DELAY_18_CLKS = 0x02, X_DELAY_20_CLKS = 0x03, X_DELAY_22_CLKS = 0x04, X_DELAY_24_CLKS = 0x05, X_DELAY_26_CLKS = 0x06, X_DELAY_28_CLKS = 0x07, X_DELAY_30_CLKS = 0x08, X_DELAY_32_CLKS = 0x09, X_DELAY_34_CLKS = 0x0a, X_DELAY_4_CLKS = 0x0b, X_DELAY_6_CLKS = 0x0c, X_DELAY_8_CLKS = 0x0d, X_DELAY_10_CLKS = 0x0e, X_DELAY_12_CLKS = 0x0f, INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, BC_OPTIMIZE_DISABLE_bit = 1 << 5, PC_LIMIT_ENABLE_bit = 1 << 6, PC_LIMIT_STRICT_bit = 1 << 7, PC_LIMIT_SIZE_mask = 0xffff << 16, PC_LIMIT_SIZE_shift = 16, TD_CNTL = 0x00009494, SYNC_PHASE_SH_mask = 0x03 << 0, SYNC_PHASE_SH_shift = 0, PAD_STALL_EN_bit = 1 << 8, GATHER4_FLOAT_MODE_bit = 1 << 16, TD_STATUS = 0x00009498, BUSY_bit = 1 << 31, TA_CNTL_AUX = 0x00009508, TA_CNTL_AUX__DISABLE_CUBE_WRAP_bit = 1 << 0, DISABLE_CUBE_ANISO_bit = 1 << 1, GETLOD_SELECT_mask = 0x03 << 2, GETLOD_SELECT_shift = 2, X_SAMPLER_AND_RESOURCE_CLAMPED_LOD_IN_RESOURCE= 0x00, DISABLE_IDLE_STALL_bit = 1 << 4, TEX_COORD_PRECISION_bit = 1 << 28, LOD_LOG2_TRUNC_bit = 1 << 29, DB_ZPASS_COUNT_LOW = 0x00009870, DB_ZPASS_COUNT_HI = 0x00009874, COUNT_HI_mask = 0x7fffffff << 0, COUNT_HI_shift = 0, TD_PS_BORDER_COLOR_INDEX = 0x0000a400, INDEX_mask = 0x1f << 0, INDEX_shift = 0, TD_PS_BORDER_COLOR_RED = 0x0000a404, TD_PS_BORDER_COLOR_GREEN = 0x0000a408, TD_PS_BORDER_COLOR_BLUE = 0x0000a40c, TD_PS_BORDER_COLOR_ALPHA = 0x0000a410, TD_VS_BORDER_COLOR_INDEX = 0x0000a414, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_VS_BORDER_COLOR_RED = 0x0000a418, TD_VS_BORDER_COLOR_GREEN = 0x0000a41c, TD_VS_BORDER_COLOR_BLUE = 0x0000a420, TD_VS_BORDER_COLOR_ALPHA = 0x0000a424, TD_GS_BORDER_COLOR_INDEX = 0x0000a428, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_GS_BORDER_COLOR_RED = 0x0000a42c, TD_GS_BORDER_COLOR_GREEN = 0x0000a430, TD_GS_BORDER_COLOR_BLUE = 0x0000a434, TD_GS_BORDER_COLOR_ALPHA = 0x0000a438, TD_HS_BORDER_COLOR_INDEX = 0x0000a43c, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_HS_BORDER_COLOR_RED = 0x0000a440, TD_HS_BORDER_COLOR_GREEN = 0x0000a444, TD_HS_BORDER_COLOR_BLUE = 0x0000a448, TD_HS_BORDER_COLOR_ALPHA = 0x0000a44c, TD_LS_BORDER_COLOR_INDEX = 0x0000a450, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_LS_BORDER_COLOR_RED = 0x0000a454, TD_LS_BORDER_COLOR_GREEN = 0x0000a458, TD_LS_BORDER_COLOR_BLUE = 0x0000a45c, TD_LS_BORDER_COLOR_ALPHA = 0x0000a460, TD_CS_BORDER_COLOR_INDEX = 0x0000a464, /* INDEX_mask = 0x1f << 0, */ /* INDEX_shift = 0, */ TD_CS_BORDER_COLOR_RED = 0x0000a468, TD_CS_BORDER_COLOR_GREEN = 0x0000a46c, TD_CS_BORDER_COLOR_BLUE = 0x0000a470, TD_CS_BORDER_COLOR_ALPHA = 0x0000a474, DB_RENDER_CONTROL = 0x00028000, DEPTH_CLEAR_ENABLE_bit = 1 << 0, STENCIL_CLEAR_ENABLE_bit = 1 << 1, DEPTH_COPY_bit = 1 << 2, STENCIL_COPY_bit = 1 << 3, RESUMMARIZE_ENABLE_bit = 1 << 4, STENCIL_COMPRESS_DISABLE_bit = 1 << 5, DEPTH_COMPRESS_DISABLE_bit = 1 << 6, COPY_CENTROID_bit = 1 << 7, COPY_SAMPLE_mask = 0x07 << 8, COPY_SAMPLE_shift = 8, COLOR_DISABLE_bit = 1 << 12, DB_COUNT_CONTROL = 0x00028004, ZPASS_INCREMENT_DISABLE_bit = 1 << 0, PERFECT_ZPASS_COUNTS_bit = 1 << 1, DB_DEPTH_VIEW = 0x00028008, SLICE_START_mask = 0x7ff << 0, SLICE_START_shift = 0, SLICE_MAX_mask = 0x7ff << 13, SLICE_MAX_shift = 13, Z_READ_ONLY_bit = 1 << 24, STENCIL_READ_ONLY_bit = 1 << 25, DB_RENDER_OVERRIDE = 0x0002800c, FORCE_HIZ_ENABLE_mask = 0x03 << 0, FORCE_HIZ_ENABLE_shift = 0, FORCE_OFF = 0x00, FORCE_ENABLE = 0x01, FORCE_DISABLE = 0x02, FORCE_RESERVED = 0x03, FORCE_HIS_ENABLE0_mask = 0x03 << 2, FORCE_HIS_ENABLE0_shift = 2, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_HIS_ENABLE1_mask = 0x03 << 4, FORCE_HIS_ENABLE1_shift = 4, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_SHADER_Z_ORDER_bit = 1 << 6, FAST_Z_DISABLE_bit = 1 << 7, FAST_STENCIL_DISABLE_bit = 1 << 8, NOOP_CULL_DISABLE_bit = 1 << 9, FORCE_COLOR_KILL_bit = 1 << 10, FORCE_Z_READ_bit = 1 << 11, FORCE_STENCIL_READ_bit = 1 << 12, FORCE_FULL_Z_RANGE_mask = 0x03 << 13, FORCE_FULL_Z_RANGE_shift = 13, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, IGNORE_SC_ZRANGE_bit = 1 << 17, DISABLE_FULLY_COVERED_bit = 1 << 18, FORCE_Z_LIMIT_SUMM_mask = 0x03 << 19, FORCE_Z_LIMIT_SUMM_shift = 19, FORCE_SUMM_OFF = 0x00, FORCE_SUMM_MINZ = 0x01, FORCE_SUMM_MAXZ = 0x02, FORCE_SUMM_BOTH = 0x03, MAX_TILES_IN_DTT_mask = 0x1f << 21, MAX_TILES_IN_DTT_shift = 21, DISABLE_PIXEL_RATE_TILES_bit = 1 << 26, FORCE_Z_DIRTY_bit = 1 << 27, FORCE_STENCIL_DIRTY_bit = 1 << 28, FORCE_Z_VALID_bit = 1 << 29, FORCE_STENCIL_VALID_bit = 1 << 30, PRESERVE_COMPRESSION_bit = 1 << 31, DB_RENDER_OVERRIDE2 = 0x00028010, PARTIAL_SQUAD_LAUNCH_CONTROL_mask = 0x03 << 0, PARTIAL_SQUAD_LAUNCH_CONTROL_shift = 0, PSLC_AUTO = 0x00, PSLC_ON_HANG_ONLY = 0x01, PSLC_ASAP = 0x02, PSLC_COUNTDOWN = 0x03, PARTIAL_SQUAD_LAUNCH_COUNTDOWN_mask = 0x07 << 2, PARTIAL_SQUAD_LAUNCH_COUNTDOWN_shift = 2, DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO_bit = 1 << 5, DB_HTILE_DATA_BASE = 0x00028014, DB_STENCIL_CLEAR = 0x00028028, DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, DB_STENCIL_CLEAR__CLEAR_shift = 0, MIN_mask = 0xff << 16, MIN_shift = 16, DB_DEPTH_CLEAR = 0x0002802c, PA_SC_SCREEN_SCISSOR_TL = 0x00028030, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0, PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16, PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, PA_SC_SCREEN_SCISSOR_BR = 0x00028034, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0, PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, DB_Z_INFO = 0x00028040, DB_Z_INFO__FORMAT_mask = 0x03 << 0, DB_Z_INFO__FORMAT_shift = 0, Z_INVALID = 0x00, Z_16 = 0x01, Z_24 = 0x02, Z_32_FLOAT = 0x03, DB_Z_INFO__ARRAY_MODE_mask = 0x0f << 4, DB_Z_INFO__ARRAY_MODE_shift = 4, ARRAY_LINEAR_GENERAL = 0x00, ARRAY_LINEAR_ALIGNED = 0x01, ARRAY_1D_TILED_THIN1 = 0x02, ARRAY_2D_TILED_THIN1 = 0x04, DB_Z_INFO__TILE_SPLIT_mask = 0x07 << 8, DB_Z_INFO__TILE_SPLIT_shift = 8, ADDR_SURF_TILE_SPLIT_64B = 0x00, ADDR_SURF_TILE_SPLIT_128B = 0x01, ADDR_SURF_TILE_SPLIT_256B = 0x02, ADDR_SURF_TILE_SPLIT_512B = 0x03, ADDR_SURF_TILE_SPLIT_1KB = 0x04, ADDR_SURF_TILE_SPLIT_2KB = 0x05, ADDR_SURF_TILE_SPLIT_4KB = 0x06, DB_Z_INFO__NUM_BANKS_mask = 0x03 << 12, DB_Z_INFO__NUM_BANKS_shift = 12, ADDR_SURF_2_BANK = 0x00, ADDR_SURF_4_BANK = 0x01, ADDR_SURF_8_BANK = 0x02, ADDR_SURF_16_BANK = 0x03, DB_Z_INFO__BANK_WIDTH_mask = 0x03 << 16, DB_Z_INFO__BANK_WIDTH_shift = 16, ADDR_SURF_BANK_WIDTH_1 = 0x00, ADDR_SURF_BANK_WIDTH_2 = 0x01, ADDR_SURF_BANK_WIDTH_4 = 0x02, ADDR_SURF_BANK_WIDTH_8 = 0x03, DB_Z_INFO__BANK_HEIGHT_mask = 0x03 << 20, DB_Z_INFO__BANK_HEIGHT_shift = 20, ADDR_SURF_BANK_HEIGHT_1 = 0x00, ADDR_SURF_BANK_HEIGHT_2 = 0x01, ADDR_SURF_BANK_HEIGHT_4 = 0x02, ADDR_SURF_BANK_HEIGHT_8 = 0x03, DB_Z_INFO__MACRO_TILE_ASPECT_mask = 0x03 << 24, DB_Z_INFO__MACRO_TILE_ASPECT_shift = 24, ADDR_SURF_MACRO_ASPECT_1 = 0x00, ADDR_SURF_MACRO_ASPECT_2 = 0x01, ADDR_SURF_MACRO_ASPECT_4 = 0x02, ADDR_SURF_MACRO_ASPECT_8 = 0x03, ALLOW_EXPCLEAR_bit = 1 << 27, READ_SIZE_bit = 1 << 28, TILE_SURFACE_ENABLE_bit = 1 << 29, DB_Z_INFO__TILE_COMPACT_bit = 1 << 30, ZRANGE_PRECISION_bit = 1 << 31, DB_STENCIL_INFO = 0x00028044, DB_STENCIL_INFO__FORMAT_bit = 1 << 0, DB_STENCIL_INFO__TILE_SPLIT_mask = 0x07 << 8, DB_STENCIL_INFO__TILE_SPLIT_shift = 8, /* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ /* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ /* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ /* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ /* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ /* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ /* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ DB_Z_READ_BASE = 0x00028048, DB_STENCIL_READ_BASE = 0x0002804c, DB_Z_WRITE_BASE = 0x00028050, DB_STENCIL_WRITE_BASE = 0x00028054, DB_DEPTH_SIZE = 0x00028058, PITCH_TILE_MAX_mask = 0x7ff << 0, PITCH_TILE_MAX_shift = 0, HEIGHT_TILE_MAX_mask = 0x7ff << 11, HEIGHT_TILE_MAX_shift = 11, DB_DEPTH_SLICE = 0x0002805c, SLICE_TILE_MAX_mask = 0x3fffff << 0, SLICE_TILE_MAX_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, PA_SC_WINDOW_OFFSET = 0x00028200, WINDOW_X_OFFSET_mask = 0xffff << 0, WINDOW_X_OFFSET_shift = 0, WINDOW_Y_OFFSET_mask = 0xffff << 16, WINDOW_Y_OFFSET_shift = 16, PA_SC_WINDOW_SCISSOR_TL = 0x00028204, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0, PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, WINDOW_OFFSET_DISABLE_bit = 1 << 31, PA_SC_WINDOW_SCISSOR_BR = 0x00028208, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0, PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, PA_SC_CLIPRECT_RULE = 0x0002820c, CLIP_RULE_mask = 0xffff << 0, CLIP_RULE_shift = 0, PA_SC_CLIPRECT_0_TL = 0x00028210, PA_SC_CLIPRECT_0_TL_num = 4, PA_SC_CLIPRECT_0_TL_offset = 8, PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0, PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16, PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, PA_SC_CLIPRECT_0_BR = 0x00028214, PA_SC_CLIPRECT_0_BR_num = 4, PA_SC_CLIPRECT_0_BR_offset = 8, PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0, PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16, PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, PA_SC_EDGERULE = 0x00028230, ER_TRI_mask = 0x0f << 0, ER_TRI_shift = 0, ER_POINT_mask = 0x0f << 4, ER_POINT_shift = 4, ER_RECT_mask = 0x0f << 8, ER_RECT_shift = 8, ER_LINE_LR_mask = 0x3f << 12, ER_LINE_LR_shift = 12, ER_LINE_RL_mask = 0x3f << 18, ER_LINE_RL_shift = 18, ER_LINE_TB_mask = 0x0f << 24, ER_LINE_TB_shift = 24, ER_LINE_BT_mask = 0x0f << 28, ER_LINE_BT_shift = 28, PA_SU_HARDWARE_SCREEN_OFFSET = 0x00028234, HW_SCREEN_OFFSET_X_mask = 0x1f << 0, HW_SCREEN_OFFSET_X_shift = 0, HW_SCREEN_OFFSET_Y_mask = 0x1f << 8, HW_SCREEN_OFFSET_Y_shift = 8, CB_TARGET_MASK = 0x00028238, TARGET0_ENABLE_mask = 0x0f << 0, TARGET0_ENABLE_shift = 0, TARGET1_ENABLE_mask = 0x0f << 4, TARGET1_ENABLE_shift = 4, TARGET2_ENABLE_mask = 0x0f << 8, TARGET2_ENABLE_shift = 8, TARGET3_ENABLE_mask = 0x0f << 12, TARGET3_ENABLE_shift = 12, TARGET4_ENABLE_mask = 0x0f << 16, TARGET4_ENABLE_shift = 16, TARGET5_ENABLE_mask = 0x0f << 20, TARGET5_ENABLE_shift = 20, TARGET6_ENABLE_mask = 0x0f << 24, TARGET6_ENABLE_shift = 24, TARGET7_ENABLE_mask = 0x0f << 28, TARGET7_ENABLE_shift = 28, CB_SHADER_MASK = 0x0002823c, OUTPUT0_ENABLE_mask = 0x0f << 0, OUTPUT0_ENABLE_shift = 0, OUTPUT1_ENABLE_mask = 0x0f << 4, OUTPUT1_ENABLE_shift = 4, OUTPUT2_ENABLE_mask = 0x0f << 8, OUTPUT2_ENABLE_shift = 8, OUTPUT3_ENABLE_mask = 0x0f << 12, OUTPUT3_ENABLE_shift = 12, OUTPUT4_ENABLE_mask = 0x0f << 16, OUTPUT4_ENABLE_shift = 16, OUTPUT5_ENABLE_mask = 0x0f << 20, OUTPUT5_ENABLE_shift = 20, OUTPUT6_ENABLE_mask = 0x0f << 24, OUTPUT6_ENABLE_shift = 24, OUTPUT7_ENABLE_mask = 0x0f << 28, OUTPUT7_ENABLE_shift = 28, PA_SC_GENERIC_SCISSOR_TL = 0x00028240, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0, PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_GENERIC_SCISSOR_BR = 0x00028244, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0, PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, PA_SC_VPORT_SCISSOR_0_TL_num = 16, PA_SC_VPORT_SCISSOR_0_TL_offset = 8, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, PA_SC_VPORT_SCISSOR_0_BR_num = 16, PA_SC_VPORT_SCISSOR_0_BR_offset = 8, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, PA_SC_VPORT_ZMIN_0 = 0x000282d0, PA_SC_VPORT_ZMIN_0_num = 16, PA_SC_VPORT_ZMIN_0_offset = 8, PA_SC_VPORT_ZMAX_0 = 0x000282d4, PA_SC_VPORT_ZMAX_0_num = 16, PA_SC_VPORT_ZMAX_0_offset = 8, SX_MISC = 0x00028350, MULTIPASS_bit = 1 << 0, SQ_VTX_SEMANTIC_0 = 0x00028380, SQ_VTX_SEMANTIC_0_num = 32, /* SEMANTIC_ID_mask = 0xff << 0, */ /* SEMANTIC_ID_shift = 0, */ VGT_MAX_VTX_INDX = 0x00028400, VGT_MIN_VTX_INDX = 0x00028404, VGT_INDX_OFFSET = 0x00028408, VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, SX_ALPHA_TEST_CONTROL = 0x00028410, ALPHA_FUNC_mask = 0x07 << 0, ALPHA_FUNC_shift = 0, REF_NEVER = 0x00, REF_LESS = 0x01, REF_EQUAL = 0x02, REF_LEQUAL = 0x03, REF_GREATER = 0x04, REF_NOTEQUAL = 0x05, REF_GEQUAL = 0x06, REF_ALWAYS = 0x07, ALPHA_TEST_ENABLE_bit = 1 << 3, ALPHA_TEST_BYPASS_bit = 1 << 8, CB_BLEND_RED = 0x00028414, CB_BLEND_GREEN = 0x00028418, CB_BLEND_BLUE = 0x0002841c, CB_BLEND_ALPHA = 0x00028420, DB_STENCILREFMASK = 0x00028430, STENCILREF_mask = 0xff << 0, STENCILREF_shift = 0, STENCILMASK_mask = 0xff << 8, STENCILMASK_shift = 8, STENCILWRITEMASK_mask = 0xff << 16, STENCILWRITEMASK_shift = 16, DB_STENCILREFMASK_BF = 0x00028434, STENCILREF_BF_mask = 0xff << 0, STENCILREF_BF_shift = 0, STENCILMASK_BF_mask = 0xff << 8, STENCILMASK_BF_shift = 8, STENCILWRITEMASK_BF_mask = 0xff << 16, STENCILWRITEMASK_BF_shift = 16, SX_ALPHA_REF = 0x00028438, PA_CL_VPORT_XSCALE_0 = 0x0002843c, PA_CL_VPORT_XSCALE_0_num = 16, PA_CL_VPORT_XSCALE_0_offset = 24, PA_CL_VPORT_XOFFSET_0 = 0x00028440, PA_CL_VPORT_XOFFSET_0_num = 16, PA_CL_VPORT_XOFFSET_0_offset = 24, PA_CL_VPORT_YSCALE_0 = 0x00028444, PA_CL_VPORT_YSCALE_0_num = 16, PA_CL_VPORT_YSCALE_0_offset = 24, PA_CL_VPORT_YOFFSET_0 = 0x00028448, PA_CL_VPORT_YOFFSET_0_num = 16, PA_CL_VPORT_YOFFSET_0_offset = 24, PA_CL_VPORT_ZSCALE_0 = 0x0002844c, PA_CL_VPORT_ZSCALE_0_num = 16, PA_CL_VPORT_ZSCALE_0_offset = 24, PA_CL_VPORT_ZOFFSET_0 = 0x00028450, PA_CL_VPORT_ZOFFSET_0_num = 16, PA_CL_VPORT_ZOFFSET_0_offset = 24, PA_CL_UCP_0_X = 0x000285bc, PA_CL_UCP_0_X_num = 6, PA_CL_UCP_0_X_offset = 16, PA_CL_UCP_0_Y = 0x000285c0, PA_CL_UCP_0_Y_num = 6, PA_CL_UCP_0_Y_offset = 16, PA_CL_UCP_0_Z = 0x000285c4, PA_CL_UCP_0_Z_num = 6, PA_CL_UCP_0_Z_offset = 16, PA_CL_UCP_0_W = 0x000285c8, PA_CL_UCP_0_W_num = 6, PA_CL_UCP_0_W_offset = 16, SPI_VS_OUT_ID_0 = 0x0002861c, SPI_VS_OUT_ID_0_num = 10, SEMANTIC_0_mask = 0xff << 0, SEMANTIC_0_shift = 0, SEMANTIC_1_mask = 0xff << 8, SEMANTIC_1_shift = 8, SEMANTIC_2_mask = 0xff << 16, SEMANTIC_2_shift = 16, SEMANTIC_3_mask = 0xff << 24, SEMANTIC_3_shift = 24, SPI_PS_INPUT_CNTL_0 = 0x00028644, SPI_PS_INPUT_CNTL_0_num = 32, SEMANTIC_mask = 0xff << 0, SEMANTIC_shift = 0, DEFAULT_VAL_mask = 0x03 << 8, DEFAULT_VAL_shift = 8, X_0_0F = 0x00, FLAT_SHADE_bit = 1 << 10, CYL_WRAP_mask = 0x0f << 13, CYL_WRAP_shift = 13, PT_SPRITE_TEX_bit = 1 << 17, SPI_VS_OUT_CONFIG = 0x000286c4, VS_PER_COMPONENT_bit = 1 << 0, VS_EXPORT_COUNT_mask = 0x1f << 1, VS_EXPORT_COUNT_shift = 1, VS_EXPORTS_FOG_bit = 1 << 8, VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, VS_OUT_FOG_VEC_ADDR_shift = 9, SPI_PS_IN_CONTROL_0 = 0x000286cc, NUM_INTERP_mask = 0x3f << 0, NUM_INTERP_shift = 0, POSITION_ENA_bit = 1 << 8, POSITION_CENTROID_bit = 1 << 9, POSITION_ADDR_mask = 0x1f << 10, POSITION_ADDR_shift = 10, PARAM_GEN_mask = 0x0f << 15, PARAM_GEN_shift = 15, PERSP_GRADIENT_ENA_bit = 1 << 28, LINEAR_GRADIENT_ENA_bit = 1 << 29, POSITION_SAMPLE_bit = 1 << 30, SPI_PS_IN_CONTROL_1 = 0x000286d0, FRONT_FACE_ENA_bit = 1 << 8, FRONT_FACE_ALL_BITS_bit = 1 << 11, FRONT_FACE_ADDR_mask = 0x1f << 12, FRONT_FACE_ADDR_shift = 12, FOG_ADDR_mask = 0x7f << 17, FOG_ADDR_shift = 17, FIXED_PT_POSITION_ENA_bit = 1 << 24, FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, FIXED_PT_POSITION_ADDR_shift = 25, POSITION_ULC_bit = 1 << 30, SPI_INTERP_CONTROL_0 = 0x000286d4, FLAT_SHADE_ENA_bit = 1 << 0, PNT_SPRITE_ENA_bit = 1 << 1, PNT_SPRITE_OVRD_X_mask = 0x07 << 2, PNT_SPRITE_OVRD_X_shift = 2, SPI_PNT_SPRITE_SEL_0 = 0x00, SPI_PNT_SPRITE_SEL_1 = 0x01, SPI_PNT_SPRITE_SEL_S = 0x02, SPI_PNT_SPRITE_SEL_T = 0x03, SPI_PNT_SPRITE_SEL_NONE = 0x04, PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, PNT_SPRITE_OVRD_Y_shift = 5, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, PNT_SPRITE_OVRD_Z_shift = 8, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_W_mask = 0x07 << 11, PNT_SPRITE_OVRD_W_shift = 11, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_TOP_1_bit = 1 << 14, SPI_INPUT_Z = 0x000286d8, PROVIDE_Z_TO_SPI_bit = 1 << 0, SPI_FOG_CNTL = 0x000286dc, PASS_FOG_THROUGH_PS_bit = 1 << 0, SPI_BARYC_CNTL = 0x000286e0, PERSP_CENTER_ENA_mask = 0x03 << 0, PERSP_CENTER_ENA_shift = 0, X_OFF = 0x00, PERSP_CENTER_ENA__X_ON_AT_CENTER = 0x01, PERSP_CENTER_ENA__X_ON_AT_CENTROID = 0x02, PERSP_CENTROID_ENA_mask = 0x03 << 4, PERSP_CENTROID_ENA_shift = 4, /* X_OFF = 0x00, */ PERSP_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, PERSP_CENTROID_ENA__X_ON_AT_CENTER = 0x02, PERSP_SAMPLE_ENA_mask = 0x03 << 8, PERSP_SAMPLE_ENA_shift = 8, /* X_OFF = 0x00, */ PERSP_PULL_MODEL_ENA_mask = 0x03 << 12, PERSP_PULL_MODEL_ENA_shift = 12, /* X_OFF = 0x00, */ LINEAR_CENTER_ENA_mask = 0x03 << 16, LINEAR_CENTER_ENA_shift = 16, /* X_OFF = 0x00, */ LINEAR_CENTER_ENA__X_ON_AT_CENTER = 0x01, LINEAR_CENTER_ENA__X_ON_AT_CENTROID = 0x02, LINEAR_CENTROID_ENA_mask = 0x03 << 20, LINEAR_CENTROID_ENA_shift = 20, /* X_OFF = 0x00, */ LINEAR_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, LINEAR_CENTROID_ENA__X_ON_AT_CENTER = 0x02, LINEAR_SAMPLE_ENA_mask = 0x03 << 24, LINEAR_SAMPLE_ENA_shift = 24, /* X_OFF = 0x00, */ SPI_PS_IN_CONTROL_2 = 0x000286e4, LINE_STIPPLE_TEX_ADDR_mask = 0xff << 0, LINE_STIPPLE_TEX_ADDR_shift = 0, LINE_STIPPLE_TEX_ENA_bit = 1 << 8, CB_BLEND0_CONTROL = 0x00028780, CB_BLEND0_CONTROL_num = 8, COLOR_SRCBLEND_mask = 0x1f << 0, COLOR_SRCBLEND_shift = 0, BLEND_ZERO = 0x00, BLEND_ONE = 0x01, BLEND_SRC_COLOR = 0x02, BLEND_ONE_MINUS_SRC_COLOR = 0x03, BLEND_SRC_ALPHA = 0x04, BLEND_ONE_MINUS_SRC_ALPHA = 0x05, BLEND_DST_ALPHA = 0x06, BLEND_ONE_MINUS_DST_ALPHA = 0x07, BLEND_DST_COLOR = 0x08, BLEND_ONE_MINUS_DST_COLOR = 0x09, BLEND_SRC_ALPHA_SATURATE = 0x0a, BLEND_BOTH_SRC_ALPHA = 0x0b, BLEND_BOTH_INV_SRC_ALPHA = 0x0c, BLEND_CONSTANT_COLOR = 0x0d, BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, BLEND_SRC1_COLOR = 0x0f, BLEND_INV_SRC1_COLOR = 0x10, BLEND_SRC1_ALPHA = 0x11, BLEND_INV_SRC1_ALPHA = 0x12, BLEND_CONSTANT_ALPHA = 0x13, BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, COLOR_COMB_FCN_mask = 0x07 << 5, COLOR_COMB_FCN_shift = 5, COMB_DST_PLUS_SRC = 0x00, COMB_SRC_MINUS_DST = 0x01, COMB_MIN_DST_SRC = 0x02, COMB_MAX_DST_SRC = 0x03, COMB_DST_MINUS_SRC = 0x04, COLOR_DESTBLEND_mask = 0x1f << 8, COLOR_DESTBLEND_shift = 8, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ ALPHA_SRCBLEND_mask = 0x1f << 16, ALPHA_SRCBLEND_shift = 16, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ ALPHA_COMB_FCN_mask = 0x07 << 21, ALPHA_COMB_FCN_shift = 21, /* COMB_DST_PLUS_SRC = 0x00, */ /* COMB_SRC_MINUS_DST = 0x01, */ /* COMB_MIN_DST_SRC = 0x02, */ /* COMB_MAX_DST_SRC = 0x03, */ /* COMB_DST_MINUS_SRC = 0x04, */ ALPHA_DESTBLEND_mask = 0x1f << 24, ALPHA_DESTBLEND_shift = 24, /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ SEPARATE_ALPHA_BLEND_bit = 1 << 29, CB_BLEND0_CONTROL__ENABLE_bit = 1 << 30, PA_CL_POINT_X_RAD = 0x000287d4, PA_CL_POINT_Y_RAD = 0x000287d8, PA_CL_POINT_SIZE = 0x000287dc, PA_CL_POINT_CULL_RAD = 0x000287e0, VGT_DMA_BASE_HI = 0x000287e4, VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, VGT_DMA_BASE = 0x000287e8, VGT_DRAW_INITIATOR = 0x000287f0, SOURCE_SELECT_mask = 0x03 << 0, SOURCE_SELECT_shift = 0, DI_SRC_SEL_DMA = 0x00, DI_SRC_SEL_IMMEDIATE = 0x01, DI_SRC_SEL_AUTO_INDEX = 0x02, DI_SRC_SEL_RESERVED = 0x03, MAJOR_MODE_mask = 0x03 << 2, MAJOR_MODE_shift = 2, DI_MAJOR_MODE_0 = 0x00, DI_MAJOR_MODE_1 = 0x01, NOT_EOP_bit = 1 << 5, USE_OPAQUE_bit = 1 << 6, VGT_IMMED_DATA = 0x000287f4, VGT_EVENT_ADDRESS_REG = 0x000287f8, ADDRESS_LOW_mask = 0xfffffff << 0, ADDRESS_LOW_shift = 0, DB_DEPTH_CONTROL = 0x00028800, STENCIL_ENABLE_bit = 1 << 0, Z_ENABLE_bit = 1 << 1, Z_WRITE_ENABLE_bit = 1 << 2, ZFUNC_mask = 0x07 << 4, ZFUNC_shift = 4, FRAG_NEVER = 0x00, FRAG_LESS = 0x01, FRAG_EQUAL = 0x02, FRAG_LEQUAL = 0x03, FRAG_GREATER = 0x04, FRAG_NOTEQUAL = 0x05, FRAG_GEQUAL = 0x06, FRAG_ALWAYS = 0x07, BACKFACE_ENABLE_bit = 1 << 7, STENCILFUNC_mask = 0x07 << 8, STENCILFUNC_shift = 8, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_mask = 0x07 << 11, STENCILFAIL_shift = 11, STENCIL_KEEP = 0x00, STENCIL_ZERO = 0x01, STENCIL_REPLACE = 0x02, STENCIL_INCR_CLAMP = 0x03, STENCIL_DECR_CLAMP = 0x04, STENCIL_INVERT = 0x05, STENCIL_INCR_WRAP = 0x06, STENCIL_DECR_WRAP = 0x07, STENCILZPASS_mask = 0x07 << 14, STENCILZPASS_shift = 14, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_mask = 0x07 << 17, STENCILZFAIL_shift = 17, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILFUNC_BF_mask = 0x07 << 20, STENCILFUNC_BF_shift = 20, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_BF_mask = 0x07 << 23, STENCILFAIL_BF_shift = 23, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZPASS_BF_mask = 0x07 << 26, STENCILZPASS_BF_shift = 26, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_BF_mask = 0x07 << 29, STENCILZFAIL_BF_shift = 29, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ CB_COLOR_CONTROL = 0x00028808, DEGAMMA_ENABLE_bit = 1 << 3, CB_COLOR_CONTROL__MODE_mask = 0x07 << 4, CB_COLOR_CONTROL__MODE_shift = 4, CB_DISABLE = 0x00, CB_NORMAL = 0x01, CB_ELIMINATE_FAST_CLEAR = 0x02, CB_RESOLVE = 0x03, CB_DECOMPRESS = 0x04, CB_FMASK_DECOMPRESS = 0x05, ROP3_mask = 0xff << 16, ROP3_shift = 16, DB_SHADER_CONTROL = 0x0002880c, Z_EXPORT_ENABLE_bit = 1 << 0, STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, Z_ORDER_mask = 0x03 << 4, Z_ORDER_shift = 4, LATE_Z = 0x00, EARLY_Z_THEN_LATE_Z = 0x01, RE_Z = 0x02, EARLY_Z_THEN_RE_Z = 0x03, KILL_ENABLE_bit = 1 << 6, COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, MASK_EXPORT_ENABLE_bit = 1 << 8, DUAL_EXPORT_ENABLE_bit = 1 << 9, EXEC_ON_HIER_FAIL_bit = 1 << 10, EXEC_ON_NOOP_bit = 1 << 11, ALPHA_TO_MASK_DISABLE_bit = 1 << 12, DB_SOURCE_FORMAT_mask = 0x03 << 13, DB_SOURCE_FORMAT_shift = 13, EXPORT_DB_FULL = 0x00, EXPORT_DB_FOUR16 = 0x01, EXPORT_DB_TWO = 0x02, DEPTH_BEFORE_SHADER_bit = 1 << 15, CONSERVATIVE_Z_EXPORT_mask = 0x03 << 16, CONSERVATIVE_Z_EXPORT_shift = 16, EXPORT_ANY_Z = 0x00, EXPORT_LESS_THAN_Z = 0x01, EXPORT_GREATER_THAN_Z = 0x02, EXPORT_RESERVED = 0x03, PA_CL_CLIP_CNTL = 0x00028810, UCP_ENA_0_bit = 1 << 0, UCP_ENA_1_bit = 1 << 1, UCP_ENA_2_bit = 1 << 2, UCP_ENA_3_bit = 1 << 3, UCP_ENA_4_bit = 1 << 4, UCP_ENA_5_bit = 1 << 5, PS_UCP_Y_SCALE_NEG_bit = 1 << 13, PS_UCP_MODE_mask = 0x03 << 14, PS_UCP_MODE_shift = 14, CLIP_DISABLE_bit = 1 << 16, UCP_CULL_ONLY_ENA_bit = 1 << 17, BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, DX_CLIP_SPACE_DEF_bit = 1 << 19, DIS_CLIP_ERR_DETECT_bit = 1 << 20, VTX_KILL_OR_bit = 1 << 21, DX_RASTERIZATION_KILL_bit = 1 << 22, DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, ZCLIP_NEAR_DISABLE_bit = 1 << 26, ZCLIP_FAR_DISABLE_bit = 1 << 27, PA_SU_SC_MODE_CNTL = 0x00028814, CULL_FRONT_bit = 1 << 0, CULL_BACK_bit = 1 << 1, FACE_bit = 1 << 2, POLY_MODE_mask = 0x03 << 3, POLY_MODE_shift = 3, X_DISABLE_POLY_MODE = 0x00, X_DUAL_MODE = 0x01, POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, POLYMODE_FRONT_PTYPE_shift = 5, X_DRAW_POINTS = 0x00, X_DRAW_LINES = 0x01, X_DRAW_TRIANGLES = 0x02, POLYMODE_BACK_PTYPE_mask = 0x07 << 8, POLYMODE_BACK_PTYPE_shift = 8, /* X_DRAW_POINTS = 0x00, */ /* X_DRAW_LINES = 0x01, */ /* X_DRAW_TRIANGLES = 0x02, */ POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, PROVOKING_VTX_LAST_bit = 1 << 19, PERSP_CORR_DIS_bit = 1 << 20, MULTI_PRIM_IB_ENA_bit = 1 << 21, PA_CL_VTE_CNTL = 0x00028818, VPORT_X_SCALE_ENA_bit = 1 << 0, VPORT_X_OFFSET_ENA_bit = 1 << 1, VPORT_Y_SCALE_ENA_bit = 1 << 2, VPORT_Y_OFFSET_ENA_bit = 1 << 3, VPORT_Z_SCALE_ENA_bit = 1 << 4, VPORT_Z_OFFSET_ENA_bit = 1 << 5, VTX_XY_FMT_bit = 1 << 8, VTX_Z_FMT_bit = 1 << 9, VTX_W0_FMT_bit = 1 << 10, PA_CL_VS_OUT_CNTL = 0x0002881c, CLIP_DIST_ENA_0_bit = 1 << 0, CLIP_DIST_ENA_1_bit = 1 << 1, CLIP_DIST_ENA_2_bit = 1 << 2, CLIP_DIST_ENA_3_bit = 1 << 3, CLIP_DIST_ENA_4_bit = 1 << 4, CLIP_DIST_ENA_5_bit = 1 << 5, CLIP_DIST_ENA_6_bit = 1 << 6, CLIP_DIST_ENA_7_bit = 1 << 7, CULL_DIST_ENA_0_bit = 1 << 8, CULL_DIST_ENA_1_bit = 1 << 9, CULL_DIST_ENA_2_bit = 1 << 10, CULL_DIST_ENA_3_bit = 1 << 11, CULL_DIST_ENA_4_bit = 1 << 12, CULL_DIST_ENA_5_bit = 1 << 13, CULL_DIST_ENA_6_bit = 1 << 14, CULL_DIST_ENA_7_bit = 1 << 15, USE_VTX_POINT_SIZE_bit = 1 << 16, USE_VTX_EDGE_FLAG_bit = 1 << 17, USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, USE_VTX_VIEWPORT_INDX_bit = 1 << 19, USE_VTX_KILL_FLAG_bit = 1 << 20, VS_OUT_MISC_VEC_ENA_bit = 1 << 21, VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, PA_CL_NANINF_CNTL = 0x00028820, VTE_XY_INF_DISCARD_bit = 1 << 0, VTE_Z_INF_DISCARD_bit = 1 << 1, VTE_W_INF_DISCARD_bit = 1 << 2, VTE_0XNANINF_IS_0_bit = 1 << 3, VTE_XY_NAN_RETAIN_bit = 1 << 4, VTE_Z_NAN_RETAIN_bit = 1 << 5, VTE_W_NAN_RETAIN_bit = 1 << 6, VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, VS_XY_NAN_TO_INF_bit = 1 << 8, VS_XY_INF_RETAIN_bit = 1 << 9, VS_Z_NAN_TO_INF_bit = 1 << 10, VS_Z_INF_RETAIN_bit = 1 << 11, VS_W_NAN_TO_INF_bit = 1 << 12, VS_W_INF_RETAIN_bit = 1 << 13, VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, PA_SU_LINE_STIPPLE_CNTL = 0x00028824, LINE_STIPPLE_RESET_mask = 0x03 << 0, LINE_STIPPLE_RESET_shift = 0, EXPAND_FULL_LENGTH_bit = 1 << 2, FRACTIONAL_ACCUM_bit = 1 << 3, DIAMOND_ADJUST_bit = 1 << 4, PA_SU_LINE_STIPPLE_SCALE = 0x00028828, PA_SU_PRIM_FILTER_CNTL = 0x0002882c, TRIANGLE_FILTER_DISABLE_bit = 1 << 0, LINE_FILTER_DISABLE_bit = 1 << 1, POINT_FILTER_DISABLE_bit = 1 << 2, RECTANGLE_FILTER_DISABLE_bit = 1 << 3, TRIANGLE_EXPAND_ENA_bit = 1 << 4, LINE_EXPAND_ENA_bit = 1 << 5, POINT_EXPAND_ENA_bit = 1 << 6, RECTANGLE_EXPAND_ENA_bit = 1 << 7, PRIM_EXPAND_CONSTANT_mask = 0xff << 8, PRIM_EXPAND_CONSTANT_shift = 8, SQ_LSTMP_RING_ITEMSIZE = 0x00028830, ITEMSIZE_mask = 0x7fff << 0, ITEMSIZE_shift = 0, SQ_HSTMP_RING_ITEMSIZE = 0x00028834, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PGM_START_PS = 0x00028840, SQ_PGM_RESOURCES_PS = 0x00028844, NUM_GPRS_mask = 0xff << 0, NUM_GPRS_shift = 0, STACK_SIZE_mask = 0xff << 8, STACK_SIZE_shift = 8, DX10_CLAMP_bit = 1 << 21, UNCACHED_FIRST_INST_bit = 1 << 28, CLAMP_CONSTS_bit = 1 << 31, SQ_PGM_RESOURCES_2_PS = 0x00028848, SINGLE_ROUND_mask = 0x03 << 0, SINGLE_ROUND_shift = 0, SQ_ROUND_NEAREST_EVEN = 0x00, SQ_ROUND_PLUS_INFINITY = 0x01, SQ_ROUND_MINUS_INFINITY = 0x02, SQ_ROUND_TO_ZERO = 0x03, DOUBLE_ROUND_mask = 0x03 << 2, DOUBLE_ROUND_shift = 2, /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, SQ_PGM_EXPORTS_PS = 0x0002884c, EXPORT_MODE_mask = 0x1f << 0, EXPORT_MODE_shift = 0, SQ_PGM_START_VS = 0x0002885c, SQ_PGM_RESOURCES_VS = 0x00028860, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_VS = 0x00028864, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ SQ_PGM_START_GS = 0x00028874, SQ_PGM_RESOURCES_GS = 0x00028878, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_GS = 0x0002887c, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ SQ_PGM_START_ES = 0x0002888c, SQ_PGM_RESOURCES_ES = 0x00028890, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_ES = 0x00028894, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ SQ_PGM_START_FS = 0x000288a4, SQ_PGM_RESOURCES_FS = 0x000288a8, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ SQ_PGM_START_HS = 0x000288b8, SQ_PGM_RESOURCES_HS = 0x000288bc, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_HS = 0x000288c0, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ SQ_PGM_START_LS = 0x000288d0, SQ_PGM_RESOURCES_LS = 0x000288d4, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ /* DX10_CLAMP_bit = 1 << 21, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_RESOURCES_2_LS = 0x000288d8, /* SINGLE_ROUND_mask = 0x03 << 0, */ /* SINGLE_ROUND_shift = 0, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* DOUBLE_ROUND_mask = 0x03 << 2, */ /* DOUBLE_ROUND_shift = 2, */ /* SQ_ROUND_NEAREST_EVEN = 0x00, */ /* SQ_ROUND_PLUS_INFINITY = 0x01, */ /* SQ_ROUND_MINUS_INFINITY = 0x02, */ /* SQ_ROUND_TO_ZERO = 0x03, */ /* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ /* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ /* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ /* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ SQ_VTX_SEMANTIC_CLEAR = 0x000288f0, SQ_ESGS_RING_ITEMSIZE = 0x00028900, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSVS_RING_ITEMSIZE = 0x00028904, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_ESTMP_RING_ITEMSIZE = 0x00028908, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSTMP_RING_ITEMSIZE = 0x0002890c, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_VSTMP_RING_ITEMSIZE = 0x00028910, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PSTMP_RING_ITEMSIZE = 0x00028914, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE = 0x0002891c, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_1 = 0x00028920, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_2 = 0x00028924, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE_3 = 0x00028928, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSVS_RING_OFFSET_1 = 0x0002892c, SQ_GSVS_RING_OFFSET_1__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_1__OFFSET_shift = 0, SQ_GSVS_RING_OFFSET_2 = 0x00028930, SQ_GSVS_RING_OFFSET_2__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_2__OFFSET_shift = 0, SQ_GSVS_RING_OFFSET_3 = 0x00028934, SQ_GSVS_RING_OFFSET_3__OFFSET_mask = 0x7fff << 0, SQ_GSVS_RING_OFFSET_3__OFFSET_shift = 0, SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, SQ_ALU_CONST_CACHE_PS_0_num = 16, SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, SQ_ALU_CONST_CACHE_VS_0_num = 16, SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, SQ_ALU_CONST_CACHE_GS_0_num = 16, PA_SU_POINT_SIZE = 0x00028a00, HEIGHT_mask = 0xffff << 0, HEIGHT_shift = 0, PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, PA_SU_POINT_SIZE__WIDTH_shift = 16, PA_SU_POINT_MINMAX = 0x00028a04, MIN_SIZE_mask = 0xffff << 0, MIN_SIZE_shift = 0, PA_SU_POINT_MINMAX__MAX_SIZE_mask = 0xffff << 16, PA_SU_POINT_MINMAX__MAX_SIZE_shift = 16, PA_SU_LINE_CNTL = 0x00028a08, PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, PA_SU_LINE_CNTL__WIDTH_shift = 0, PA_SC_LINE_STIPPLE = 0x00028a0c, LINE_PATTERN_mask = 0xffff << 0, LINE_PATTERN_shift = 0, REPEAT_COUNT_mask = 0xff << 16, REPEAT_COUNT_shift = 16, PATTERN_BIT_ORDER_bit = 1 << 28, AUTO_RESET_CNTL_mask = 0x03 << 29, AUTO_RESET_CNTL_shift = 29, VGT_OUTPUT_PATH_CNTL = 0x00028a10, PATH_SELECT_mask = 0x07 << 0, PATH_SELECT_shift = 0, VGT_OUTPATH_VTX_REUSE = 0x00, VGT_OUTPATH_TESS_EN = 0x01, VGT_OUTPATH_PASSTHRU = 0x02, VGT_OUTPATH_GS_BLOCK = 0x03, VGT_OUTPATH_HS_BLOCK = 0x04, VGT_HOS_CNTL = 0x00028a14, TESS_MODE_mask = 0x03 << 0, TESS_MODE_shift = 0, VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, VGT_HOS_REUSE_DEPTH = 0x00028a20, REUSE_DEPTH_mask = 0xff << 0, REUSE_DEPTH_shift = 0, VGT_GROUP_PRIM_TYPE = 0x00028a24, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, VGT_GRP_3D_POINT = 0x00, VGT_GRP_3D_LINE = 0x01, VGT_GRP_3D_TRI = 0x02, VGT_GRP_3D_RECT = 0x03, VGT_GRP_3D_QUAD = 0x04, VGT_GRP_2D_COPY_RECT_V0 = 0x05, VGT_GRP_2D_COPY_RECT_V1 = 0x06, VGT_GRP_2D_COPY_RECT_V2 = 0x07, VGT_GRP_2D_COPY_RECT_V3 = 0x08, VGT_GRP_2D_FILL_RECT = 0x09, VGT_GRP_2D_LINE = 0x0a, VGT_GRP_2D_TRI = 0x0b, VGT_GRP_PRIM_INDEX_LINE = 0x0c, VGT_GRP_PRIM_INDEX_TRI = 0x0d, VGT_GRP_PRIM_INDEX_QUAD = 0x0e, VGT_GRP_3D_LINE_ADJ = 0x0f, VGT_GRP_3D_TRI_ADJ = 0x10, VGT_GRP_3D_PATCH = 0x11, RETAIN_ORDER_bit = 1 << 14, RETAIN_QUADS_bit = 1 << 15, PRIM_ORDER_mask = 0x07 << 16, PRIM_ORDER_shift = 16, VGT_GRP_LIST = 0x00, VGT_GRP_STRIP = 0x01, VGT_GRP_FAN = 0x02, VGT_GRP_LOOP = 0x03, VGT_GRP_POLYGON = 0x04, VGT_GROUP_FIRST_DECR = 0x00028a28, FIRST_DECR_mask = 0x0f << 0, FIRST_DECR_shift = 0, VGT_GROUP_DECR = 0x00028a2c, DECR_mask = 0x0f << 0, DECR_shift = 0, VGT_GROUP_VECT_0_CNTL = 0x00028a30, COMP_X_EN_bit = 1 << 0, COMP_Y_EN_bit = 1 << 1, COMP_Z_EN_bit = 1 << 2, COMP_W_EN_bit = 1 << 3, VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, SHIFT_mask = 0xff << 16, SHIFT_shift = 16, VGT_GROUP_VECT_1_CNTL = 0x00028a34, /* COMP_X_EN_bit = 1 << 0, */ /* COMP_Y_EN_bit = 1 << 1, */ /* COMP_Z_EN_bit = 1 << 2, */ /* COMP_W_EN_bit = 1 << 3, */ VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, /* SHIFT_mask = 0xff << 16, */ /* SHIFT_shift = 16, */ VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, X_CONV_mask = 0x0f << 0, X_CONV_shift = 0, VGT_GRP_INDEX_16 = 0x00, VGT_GRP_INDEX_32 = 0x01, VGT_GRP_UINT_16 = 0x02, VGT_GRP_UINT_32 = 0x03, VGT_GRP_SINT_16 = 0x04, VGT_GRP_SINT_32 = 0x05, VGT_GRP_FLOAT_32 = 0x06, VGT_GRP_AUTO_PRIM = 0x07, VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, X_OFFSET_mask = 0x0f << 4, X_OFFSET_shift = 4, Y_CONV_mask = 0x0f << 8, Y_CONV_shift = 8, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Y_OFFSET_mask = 0x0f << 12, Y_OFFSET_shift = 12, Z_CONV_mask = 0x0f << 16, Z_CONV_shift = 16, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Z_OFFSET_mask = 0x0f << 20, Z_OFFSET_shift = 20, W_CONV_mask = 0x0f << 24, W_CONV_shift = 24, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ W_OFFSET_mask = 0x0f << 28, W_OFFSET_shift = 28, VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, /* X_CONV_mask = 0x0f << 0, */ /* X_CONV_shift = 0, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* X_OFFSET_mask = 0x0f << 4, */ /* X_OFFSET_shift = 4, */ /* Y_CONV_mask = 0x0f << 8, */ /* Y_CONV_shift = 8, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Y_OFFSET_mask = 0x0f << 12, */ /* Y_OFFSET_shift = 12, */ /* Z_CONV_mask = 0x0f << 16, */ /* Z_CONV_shift = 16, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Z_OFFSET_mask = 0x0f << 20, */ /* Z_OFFSET_shift = 20, */ /* W_CONV_mask = 0x0f << 24, */ /* W_CONV_shift = 24, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* W_OFFSET_mask = 0x0f << 28, */ /* W_OFFSET_shift = 28, */ VGT_GS_MODE = 0x00028a40, VGT_GS_MODE__MODE_mask = 0x03 << 0, VGT_GS_MODE__MODE_shift = 0, GS_OFF = 0x00, GS_SCENARIO_A = 0x01, GS_SCENARIO_B = 0x02, GS_SCENARIO_G = 0x03, GS_SCENARIO_C = 0x04, SPRITE_EN = 0x05, ES_PASSTHRU_bit = 1 << 2, CUT_MODE_mask = 0x03 << 3, CUT_MODE_shift = 3, GS_CUT_1024 = 0x00, GS_CUT_512 = 0x01, GS_CUT_256 = 0x02, GS_CUT_128 = 0x03, MODE_HI_bit = 1 << 8, PA_SC_MODE_CNTL_0 = 0x00028a48, MSAA_ENABLE_bit = 1 << 0, VPORT_SCISSOR_ENABLE_bit = 1 << 1, LINE_STIPPLE_ENABLE_bit = 1 << 2, VGT_ENHANCE = 0x00028a50, VGT_GS_PER_ES = 0x00028a54, GS_PER_ES_mask = 0x7ff << 0, GS_PER_ES_shift = 0, VGT_ES_PER_GS = 0x00028a58, ES_PER_GS_mask = 0x7ff << 0, ES_PER_GS_shift = 0, VGT_GS_PER_VS = 0x00028a5c, GS_PER_VS_mask = 0x0f << 0, GS_PER_VS_shift = 0, VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, OUTPRIM_TYPE_mask = 0x3f << 0, OUTPRIM_TYPE_shift = 0, POINTLIST = 0x00, LINESTRIP = 0x01, TRISTRIP = 0x02, VGT_DMA_SIZE = 0x00028a74, VGT_DMA_MAX_SIZE = 0x00028a78, VGT_DMA_INDEX_TYPE = 0x00028a7c, /* INDEX_TYPE_mask = 0x03 << 0, */ /* INDEX_TYPE_shift = 0, */ VGT_INDEX_16 = 0x00, VGT_INDEX_32 = 0x01, SWAP_MODE_mask = 0x03 << 2, SWAP_MODE_shift = 2, VGT_DMA_SWAP_NONE = 0x00, VGT_DMA_SWAP_16_BIT = 0x01, VGT_DMA_SWAP_32_BIT = 0x02, VGT_DMA_SWAP_WORD = 0x03, VGT_PRIMITIVEID_EN = 0x00028a84, PRIMITIVEID_EN_bit = 1 << 0, VGT_DMA_NUM_INSTANCES = 0x00028a88, VGT_EVENT_INITIATOR = 0x00028a90, EVENT_TYPE_mask = 0x3f << 0, EVENT_TYPE_shift = 0, SAMPLE_STREAMOUTSTATS1 = 0x01, SAMPLE_STREAMOUTSTATS2 = 0x02, SAMPLE_STREAMOUTSTATS3 = 0x03, CACHE_FLUSH_TS = 0x04, CONTEXT_DONE = 0x05, CACHE_FLUSH = 0x06, CS_PARTIAL_FLUSH = 0x07, RST_PIX_CNT = 0x0d, VS_PARTIAL_FLUSH = 0x0f, PS_PARTIAL_FLUSH = 0x10, FLUSH_HS_OUTPUT = 0x11, FLUSH_LS_OUTPUT = 0x12, CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, ZPASS_DONE = 0x15, CACHE_FLUSH_AND_INV_EVENT = 0x16, PERFCOUNTER_START = 0x17, PERFCOUNTER_STOP = 0x18, PIPELINESTAT_START = 0x19, PIPELINESTAT_STOP = 0x1a, PERFCOUNTER_SAMPLE = 0x1b, FLUSH_ES_OUTPUT = 0x1c, FLUSH_GS_OUTPUT = 0x1d, SAMPLE_PIPELINESTAT = 0x1e, SO_VGTSTREAMOUT_FLUSH = 0x1f, SAMPLE_STREAMOUTSTATS = 0x20, RESET_VTX_CNT = 0x21, BLOCK_CONTEXT_DONE = 0x22, CS_CONTEXT_DONE = 0x23, VGT_FLUSH = 0x24, SQ_NON_EVENT = 0x26, SC_SEND_DB_VPZ = 0x27, BOTTOM_OF_PIPE_TS = 0x28, FLUSH_SX_TS = 0x29, DB_CACHE_FLUSH_AND_INV = 0x2a, FLUSH_AND_INV_DB_DATA_TS = 0x2b, FLUSH_AND_INV_DB_META = 0x2c, FLUSH_AND_INV_CB_DATA_TS = 0x2d, FLUSH_AND_INV_CB_META = 0x2e, CS_DONE = 0x2f, PS_DONE = 0x30, FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, ADDRESS_HI_mask = 0xff << 19, ADDRESS_HI_shift = 19, EXTENDED_EVENT_bit = 1 << 27, VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, RESET_EN_bit = 1 << 0, VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, VGT_REUSE_OFF = 0x00028ab4, REUSE_OFF_bit = 1 << 0, VGT_VTX_CNT_EN = 0x00028ab8, VTX_CNT_EN_bit = 1 << 0, DB_HTILE_SURFACE = 0x00028abc, HTILE_WIDTH_bit = 1 << 0, HTILE_HEIGHT_bit = 1 << 1, LINEAR_bit = 1 << 2, FULL_CACHE_bit = 1 << 3, HTILE_USES_PRELOAD_WIN_bit = 1 << 4, PRELOAD_bit = 1 << 5, PREFETCH_WIDTH_mask = 0x3f << 6, PREFETCH_WIDTH_shift = 6, PREFETCH_HEIGHT_mask = 0x3f << 12, PREFETCH_HEIGHT_shift = 12, DB_SRESULTS_COMPARE_STATE0 = 0x00028ac0, COMPAREFUNC0_mask = 0x07 << 0, COMPAREFUNC0_shift = 0, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ COMPAREVALUE0_mask = 0xff << 4, COMPAREVALUE0_shift = 4, COMPAREMASK0_mask = 0xff << 12, COMPAREMASK0_shift = 12, ENABLE0_bit = 1 << 24, DB_SRESULTS_COMPARE_STATE1 = 0x00028ac4, COMPAREFUNC1_mask = 0x07 << 0, COMPAREFUNC1_shift = 0, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ COMPAREVALUE1_mask = 0xff << 4, COMPAREVALUE1_shift = 4, COMPAREMASK1_mask = 0xff << 12, COMPAREMASK1_shift = 12, ENABLE1_bit = 1 << 24, DB_PRELOAD_CONTROL = 0x00028ac8, START_X_mask = 0xff << 0, START_X_shift = 0, START_Y_mask = 0xff << 8, START_Y_shift = 8, MAX_X_mask = 0xff << 16, MAX_X_shift = 16, MAX_Y_mask = 0xff << 24, MAX_Y_shift = 24, VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, VERTEX_STRIDE_mask = 0x1ff << 0, VERTEX_STRIDE_shift = 0, VGT_GS_MAX_VERT_OUT = 0x00028b38, MAX_VERT_OUT_mask = 0x7ff << 0, MAX_VERT_OUT_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, VGT_SHADER_STAGES_EN = 0x00028b54, LS_EN_mask = 0x03 << 0, LS_EN_shift = 0, LS_STAGE_OFF = 0x00, LS_STAGE_ON = 0x01, CS_STAGE_ON = 0x02, HS_EN_bit = 1 << 2, ES_EN_mask = 0x03 << 3, ES_EN_shift = 3, ES_STAGE_OFF = 0x00, ES_STAGE_DS = 0x01, ES_STAGE_REAL = 0x02, GS_EN_bit = 1 << 5, VS_EN_mask = 0x03 << 6, VS_EN_shift = 6, VS_STAGE_REAL = 0x00, VS_STAGE_DS = 0x01, VS_STAGE_COPY_SHADER = 0x02, VGT_LS_HS_CONFIG = 0x00028b58, NUM_PATCHES_mask = 0xff << 0, NUM_PATCHES_shift = 0, HS_NUM_INPUT_CP_mask = 0x3f << 8, HS_NUM_INPUT_CP_shift = 8, HS_NUM_OUTPUT_CP_mask = 0x3f << 14, HS_NUM_OUTPUT_CP_shift = 14, VGT_LS_SIZE = 0x00028b5c, VGT_LS_SIZE__SIZE_mask = 0xff << 0, VGT_LS_SIZE__SIZE_shift = 0, PATCH_CP_SIZE_mask = 0x1fff << 8, PATCH_CP_SIZE_shift = 8, VGT_HS_SIZE = 0x00028b60, VGT_HS_SIZE__SIZE_mask = 0xff << 0, VGT_HS_SIZE__SIZE_shift = 0, /* PATCH_CP_SIZE_mask = 0x1fff << 8, */ /* PATCH_CP_SIZE_shift = 8, */ VGT_LS_HS_ALLOC = 0x00028b64, HS_TOTAL_OUTPUT_mask = 0x1fff << 0, HS_TOTAL_OUTPUT_shift = 0, LS_HS_TOTAL_OUTPUT_mask = 0x1fff << 13, LS_HS_TOTAL_OUTPUT_shift = 13, VGT_HS_PATCH_CONST = 0x00028b68, VGT_HS_PATCH_CONST__SIZE_mask = 0x1fff << 0, VGT_HS_PATCH_CONST__SIZE_shift = 0, VGT_HS_PATCH_CONST__STRIDE_mask = 0x1fff << 13, VGT_HS_PATCH_CONST__STRIDE_shift = 13, DB_ALPHA_TO_MASK = 0x00028b70, ALPHA_TO_MASK_ENABLE_bit = 1 << 0, ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, ALPHA_TO_MASK_OFFSET0_shift = 8, ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, ALPHA_TO_MASK_OFFSET1_shift = 10, ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, ALPHA_TO_MASK_OFFSET2_shift = 12, ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, ALPHA_TO_MASK_OFFSET3_shift = 14, OFFSET_ROUND_bit = 1 << 16, PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028b78, POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, PA_SU_POLY_OFFSET_CLAMP = 0x00028b7c, PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028b80, PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028b84, PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028b88, PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028b8c, VGT_GS_INSTANCE_CNT = 0x00028b90, VGT_GS_INSTANCE_CNT__ENABLE_bit = 1 << 0, CNT_mask = 0x7f << 2, CNT_shift = 2, VGT_STRMOUT_CONFIG = 0x00028b94, STREAMOUT_0_EN_bit = 1 << 0, STREAMOUT_1_EN_bit = 1 << 1, STREAMOUT_2_EN_bit = 1 << 2, STREAMOUT_3_EN_bit = 1 << 3, RAST_STREAM_mask = 0x07 << 4, RAST_STREAM_shift = 4, VGT_STRMOUT_BUFFER_CONFIG = 0x00028b98, STREAM_0_BUFFER_EN_mask = 0x0f << 0, STREAM_0_BUFFER_EN_shift = 0, STREAM_1_BUFFER_EN_mask = 0x0f << 4, STREAM_1_BUFFER_EN_shift = 4, STREAM_2_BUFFER_EN_mask = 0x0f << 8, STREAM_2_BUFFER_EN_shift = 8, STREAM_3_BUFFER_EN_mask = 0x0f << 12, STREAM_3_BUFFER_EN_shift = 12, CB_IMMED0_BASE = 0x00028b9c, CB_IMMED0_BASE_num = 12, PA_SC_LINE_CNTL = 0x00028c00, EXPAND_LINE_WIDTH_bit = 1 << 9, LAST_PIXEL_bit = 1 << 10, PERPENDICULAR_ENDCAP_ENA_bit = 1 << 11, DX10_DIAMOND_TEST_ENA_bit = 1 << 12, PA_SC_AA_CONFIG = 0x00028c04, MSAA_NUM_SAMPLES_mask = 0x03 << 0, MSAA_NUM_SAMPLES_shift = 0, AA_MASK_CENTROID_DTMN_bit = 1 << 4, MAX_SAMPLE_DIST_mask = 0x0f << 13, MAX_SAMPLE_DIST_shift = 13, PA_SU_VTX_CNTL = 0x00028c08, PIX_CENTER_bit = 1 << 0, PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, X_TRUNCATE = 0x00, X_ROUND = 0x01, X_ROUND_TO_EVEN = 0x02, X_ROUND_TO_ODD = 0x03, QUANT_MODE_mask = 0x07 << 3, QUANT_MODE_shift = 3, X_1_16TH = 0x00, X_1_8TH = 0x01, X_1_4TH = 0x02, X_1_2 = 0x03, X_1 = 0x04, X_1_256TH = 0x05, X_1_1024TH = 0x06, X_1_4096TH = 0x07, PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c, PA_CL_GB_VERT_DISC_ADJ = 0x00028c10, PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14, PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18, PA_SC_AA_SAMPLE_LOCS_0 = 0x00028c1c, S0_X_mask = 0x0f << 0, S0_X_shift = 0, S0_Y_mask = 0x0f << 4, S0_Y_shift = 4, S1_X_mask = 0x0f << 8, S1_X_shift = 8, S1_Y_mask = 0x0f << 12, S1_Y_shift = 12, S2_X_mask = 0x0f << 16, S2_X_shift = 16, S2_Y_mask = 0x0f << 20, S2_Y_shift = 20, S3_X_mask = 0x0f << 24, S3_X_shift = 24, S3_Y_mask = 0x0f << 28, S3_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_1 = 0x00028c20, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_2 = 0x00028c24, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_3 = 0x00028c28, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_4 = 0x00028c2c, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_5 = 0x00028c30, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_6 = 0x00028c34, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_7 = 0x00028c38, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_MASK = 0x00028c3c, VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, VTX_REUSE_DEPTH_mask = 0xff << 0, VTX_REUSE_DEPTH_shift = 0, VGT_OUT_DEALLOC_CNTL = 0x00028c5c, DEALLOC_DIST_mask = 0x7f << 0, DEALLOC_DIST_shift = 0, CB_COLOR0_BASE = 0x00028c60, CB_COLOR0_BASE_num = 12, CB_COLOR0_BASE_offset = 51, CB_COLOR0_PITCH = 0x00028c64, CB_COLOR0_PITCH_num = 12, CB_COLOR0_PITCH_offset = 51, CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff << 0, CB_COLOR0_PITCH__TILE_MAX_shift = 0, CB_COLOR0_SLICE = 0x00028c68, CB_COLOR0_SLICE_num = 12, CB_COLOR0_SLICE_offset = 51, CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff << 0, CB_COLOR0_SLICE__TILE_MAX_shift = 0, CB_COLOR0_VIEW = 0x00028c6c, CB_COLOR0_VIEW_num = 12, CB_COLOR0_VIEW_offset = 51, /* SLICE_START_mask = 0x7ff << 0, */ /* SLICE_START_shift = 0, */ /* SLICE_MAX_mask = 0x7ff << 13, */ /* SLICE_MAX_shift = 13, */ CB_COLOR0_INFO = 0x00028c70, CB_COLOR0_INFO_num = 12, CB_COLOR0_INFO_offset = 51, ENDIAN_mask = 0x03 << 0, ENDIAN_shift = 0, ENDIAN_NONE = 0x00, ENDIAN_8IN16 = 0x01, ENDIAN_8IN32 = 0x02, ENDIAN_8IN64 = 0x03, CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, CB_COLOR0_INFO__FORMAT_shift = 2, COLOR_INVALID = 0x00, COLOR_8 = 0x01, COLOR_16 = 0x05, COLOR_16_FLOAT = 0x06, COLOR_8_8 = 0x07, COLOR_5_6_5 = 0x08, COLOR_1_5_5_5 = 0x0a, COLOR_4_4_4_4 = 0x0b, COLOR_5_5_5_1 = 0x0c, COLOR_32 = 0x0d, COLOR_32_FLOAT = 0x0e, COLOR_16_16 = 0x0f, COLOR_16_16_FLOAT = 0x10, COLOR_8_24 = 0x11, COLOR_24_8 = 0x13, COLOR_10_11_11 = 0x15, COLOR_10_11_11_FLOAT = 0x16, COLOR_2_10_10_10 = 0x19, COLOR_8_8_8_8 = 0x1a, COLOR_10_10_10_2 = 0x1b, COLOR_X24_8_32_FLOAT = 0x1c, COLOR_32_32 = 0x1d, COLOR_32_32_FLOAT = 0x1e, COLOR_16_16_16_16 = 0x1f, COLOR_16_16_16_16_FLOAT = 0x20, COLOR_32_32_32_32 = 0x22, COLOR_32_32_32_32_FLOAT = 0x23, CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, CB_COLOR0_INFO__ARRAY_MODE_shift = 8, /* ARRAY_LINEAR_GENERAL = 0x00, */ /* ARRAY_LINEAR_ALIGNED = 0x01, */ /* ARRAY_1D_TILED_THIN1 = 0x02, */ /* ARRAY_2D_TILED_THIN1 = 0x04, */ NUMBER_TYPE_mask = 0x07 << 12, NUMBER_TYPE_shift = 12, NUMBER_UNORM = 0x00, NUMBER_SNORM = 0x01, NUMBER_UINT = 0x04, NUMBER_SINT = 0x05, NUMBER_SRGB = 0x06, NUMBER_FLOAT = 0x07, COMP_SWAP_mask = 0x03 << 15, COMP_SWAP_shift = 15, SWAP_STD = 0x00, SWAP_ALT = 0x01, SWAP_STD_REV = 0x02, SWAP_ALT_REV = 0x03, FAST_CLEAR_bit = 1 << 17, COMPRESSION_bit = 1 << 18, BLEND_CLAMP_bit = 1 << 19, BLEND_BYPASS_bit = 1 << 20, SIMPLE_FLOAT_bit = 1 << 21, CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22, CB_COLOR0_INFO__TILE_COMPACT_bit = 1 << 23, SOURCE_FORMAT_mask = 0x03 << 24, SOURCE_FORMAT_shift = 24, EXPORT_4C_32BPC = 0x00, EXPORT_4C_16BPC = 0x01, RAT_bit = 1 << 26, RESOURCE_TYPE_mask = 0x07 << 27, RESOURCE_TYPE_shift = 27, BUFFER = 0x00, TEXTURE1D = 0x01, TEXTURE1DARRAY = 0x02, TEXTURE2D = 0x03, TEXTURE2DARRAY = 0x04, TEXTURE3D = 0x05, CB_COLOR0_ATTRIB = 0x00028c74, CB_COLOR0_ATTRIB_num = 12, CB_COLOR0_ATTRIB_offset = 51, IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4, CB_COLOR0_ATTRIB__TILE_SPLIT_mask = 0x0f << 5, CB_COLOR0_ATTRIB__TILE_SPLIT_shift = 5, /* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ /* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ /* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ /* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ /* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ /* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ /* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ CB_COLOR0_ATTRIB__NUM_BANKS_mask = 0x03 << 10, CB_COLOR0_ATTRIB__NUM_BANKS_shift = 10, /* ADDR_SURF_2_BANK = 0x00, */ /* ADDR_SURF_4_BANK = 0x01, */ /* ADDR_SURF_8_BANK = 0x02, */ /* ADDR_SURF_16_BANK = 0x03, */ CB_COLOR0_ATTRIB__BANK_WIDTH_mask = 0x03 << 13, CB_COLOR0_ATTRIB__BANK_WIDTH_shift = 13, /* ADDR_SURF_BANK_WIDTH_1 = 0x00, */ /* ADDR_SURF_BANK_WIDTH_2 = 0x01, */ /* ADDR_SURF_BANK_WIDTH_4 = 0x02, */ /* ADDR_SURF_BANK_WIDTH_8 = 0x03, */ CB_COLOR0_ATTRIB__BANK_HEIGHT_mask = 0x03 << 16, CB_COLOR0_ATTRIB__BANK_HEIGHT_shift = 16, /* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ /* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ /* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ /* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_mask = 0x03 << 19, CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift = 19, /* ADDR_SURF_MACRO_ASPECT_1 = 0x00, */ /* ADDR_SURF_MACRO_ASPECT_2 = 0x01, */ /* ADDR_SURF_MACRO_ASPECT_4 = 0x02, */ /* ADDR_SURF_MACRO_ASPECT_8 = 0x03, */ FMASK_BANK_HEIGHT_mask = 0x03 << 22, FMASK_BANK_HEIGHT_shift = 22, /* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ /* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ /* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ /* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ CB_COLOR0_DIM = 0x00028c78, CB_COLOR0_DIM_num = 12, CB_COLOR0_DIM_offset = 51, WIDTH_MAX_mask = 0xffff << 0, WIDTH_MAX_shift = 0, HEIGHT_MAX_mask = 0xffff << 16, HEIGHT_MAX_shift = 16, CB_COLOR0_CMASK = 0x00028c7c, CB_COLOR0_CMASK_num = 8, CB_COLOR0_CMASK_offset = 60, CB_COLOR0_CMASK_SLICE = 0x00028c80, CB_COLOR0_CMASK_SLICE_num = 8, CB_COLOR0_CMASK_SLICE_offset = 60, CB_COLOR0_CMASK_SLICE__TILE_MAX_mask = 0x3fff << 0, CB_COLOR0_CMASK_SLICE__TILE_MAX_shift = 0, CB_COLOR0_FMASK = 0x00028c84, CB_COLOR0_FMASK_num = 8, CB_COLOR0_FMASK_offset = 60, CB_COLOR0_FMASK_SLICE = 0x00028c88, CB_COLOR0_FMASK_SLICE_num = 8, CB_COLOR0_FMASK_SLICE_offset = 60, CB_COLOR0_FMASK_SLICE__TILE_MAX_mask = 0x3fffff << 0, CB_COLOR0_FMASK_SLICE__TILE_MAX_shift = 0, CB_COLOR0_CLEAR_WORD0 = 0x00028c8c, CB_COLOR0_CLEAR_WORD0_num = 8, CB_COLOR0_CLEAR_WORD0_offset = 60, CB_COLOR0_CLEAR_WORD1 = 0x00028c90, CB_COLOR0_CLEAR_WORD1_num = 8, CB_COLOR0_CLEAR_WORD1_offset = 60, CB_COLOR0_CLEAR_WORD2 = 0x00028c94, CB_COLOR0_CLEAR_WORD2_num = 8, CB_COLOR0_CLEAR_WORD2_offset = 60, CB_COLOR0_CLEAR_WORD3 = 0x00028c98, CB_COLOR0_CLEAR_WORD3_num = 8, CB_COLOR0_CLEAR_WORD3_offset = 60, SQ_ALU_CONST_CACHE_HS_0 = 0x00028f00, SQ_ALU_CONST_CACHE_HS_0_num = 16, SQ_ALU_CONST_CACHE_LS_0 = 0x00028f40, SQ_ALU_CONST_CACHE_LS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x00028f80, SQ_ALU_CONST_BUFFER_SIZE_HS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x00028fc0, SQ_ALU_CONST_BUFFER_SIZE_LS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_shift = 0, SQ_VTX_CONSTANT_WORD0_0 = 0x00030000, SQ_TEX_RESOURCE_WORD0_0 = 0x00030000, DIM_mask = 0x07 << 0, DIM_shift = 0, SQ_TEX_DIM_1D = 0x00, SQ_TEX_DIM_2D = 0x01, SQ_TEX_DIM_3D = 0x02, SQ_TEX_DIM_CUBEMAP = 0x03, SQ_TEX_DIM_1D_ARRAY = 0x04, SQ_TEX_DIM_2D_ARRAY = 0x05, SQ_TEX_DIM_2D_MSAA = 0x06, SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, /* IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, */ SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_bit= 1 << 5, PITCH_mask = 0xfff << 6, PITCH_shift = 6, TEX_WIDTH_mask = 0x3fff << 18, TEX_WIDTH_shift = 18, SQ_VTX_CONSTANT_WORD1_0 = 0x00030004, SQ_TEX_RESOURCE_WORD1_0 = 0x00030004, TEX_HEIGHT_mask = 0x3fff << 0, TEX_HEIGHT_shift = 0, TEX_DEPTH_mask = 0x1fff << 14, TEX_DEPTH_shift = 14, SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0x0f << 28, SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28, SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, BASE_ADDRESS_HI_mask = 0xff << 0, BASE_ADDRESS_HI_shift = 0, SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ SQ_TEX_RESOURCE_WORD2_0 = 0x00030008, SQ_VTX_CONSTANT_WORD3_0 = 0x0003000c, SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x07 << 3, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x07 << 6, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x07 << 9, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x07 << 12, SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD3_0 = 0x0003000c, SQ_TEX_RESOURCE_WORD4_0 = 0x00030010, FORMAT_COMP_X_mask = 0x03 << 0, FORMAT_COMP_X_shift = 0, SQ_FORMAT_COMP_UNSIGNED = 0x00, SQ_FORMAT_COMP_SIGNED = 0x01, SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, FORMAT_COMP_Y_mask = 0x03 << 2, FORMAT_COMP_Y_shift = 2, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_Z_mask = 0x03 << 4, FORMAT_COMP_Z_shift = 4, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_W_mask = 0x03 << 6, FORMAT_COMP_W_shift = 6, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ BASE_LEVEL_mask = 0x0f << 28, BASE_LEVEL_shift = 28, SQ_VTX_CONSTANT_WORD4_0 = 0x00030010, SQ_TEX_RESOURCE_WORD5_0 = 0x00030014, LAST_LEVEL_mask = 0x0f << 0, LAST_LEVEL_shift = 0, BASE_ARRAY_mask = 0x1fff << 4, BASE_ARRAY_shift = 4, LAST_ARRAY_mask = 0x1fff << 17, LAST_ARRAY_shift = 17, SQ_TEX_RESOURCE_WORD6_0 = 0x00030018, PERF_MODULATION_mask = 0x07 << 3, PERF_MODULATION_shift = 3, INTERLACED_bit = 1 << 6, SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8, SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x07 << 29, SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29, SQ_ADDR_SURF_TILE_SPLIT_64B = 0x00, SQ_ADDR_SURF_TILE_SPLIT_128B = 0x01, SQ_ADDR_SURF_TILE_SPLIT_256B = 0x02, SQ_ADDR_SURF_TILE_SPLIT_512B = 0x03, SQ_ADDR_SURF_TILE_SPLIT_1KB = 0x04, SQ_ADDR_SURF_TILE_SPLIT_2KB = 0x05, SQ_ADDR_SURF_TILE_SPLIT_4KB = 0x06, SQ_VTX_CONSTANT_WORD7_0 = 0x0003001c, SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30, SQ_TEX_VTX_INVALID_TEXTURE = 0x00, SQ_TEX_VTX_INVALID_BUFFER = 0x01, SQ_TEX_VTX_VALID_TEXTURE = 0x02, SQ_TEX_VTX_VALID_BUFFER = 0x03, SQ_TEX_RESOURCE_WORD7_0 = 0x0003001c, SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f << 0, SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x03 << 6, SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, SQ_ADDR_SURF_MACRO_ASPECT_1 = 0x00, SQ_ADDR_SURF_MACRO_ASPECT_2 = 0x01, SQ_ADDR_SURF_MACRO_ASPECT_4 = 0x02, SQ_ADDR_SURF_MACRO_ASPECT_8 = 0x03, SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x03 << 8, SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, SQ_ADDR_SURF_BANK_WH_1 = 0x00, SQ_ADDR_SURF_BANK_WH_2 = 0x01, SQ_ADDR_SURF_BANK_WH_4 = 0x02, SQ_ADDR_SURF_BANK_WH_8 = 0x03, SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x03 << 10, SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10, /* SQ_ADDR_SURF_BANK_WH_1 = 0x00, */ /* SQ_ADDR_SURF_BANK_WH_2 = 0x01, */ /* SQ_ADDR_SURF_BANK_WH_4 = 0x02, */ /* SQ_ADDR_SURF_BANK_WH_8 = 0x03, */ DEPTH_SAMPLE_ORDER_bit = 1 << 15, SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x03 << 16, SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16, SQ_ADDR_SURF_2_BANK = 0x00, SQ_ADDR_SURF_4_BANK = 0x01, SQ_ADDR_SURF_8_BANK = 0x02, SQ_ADDR_SURF_16_BANK = 0x03, SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x03 << 30, SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30, /* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ /* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ /* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ /* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ SQ_LOOP_CONST_DX10_0 = 0x0003a200, SQ_LOOP_CONST_0 = 0x0003a200, SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, SQ_LOOP_CONST_0__COUNT_shift = 0, INIT_mask = 0xfff << 12, INIT_shift = 12, INC_mask = 0xff << 24, INC_shift = 24, SQ_JUMPTABLE_CONST_0 = 0x0003a200, CONST_A_mask = 0xff << 0, CONST_A_shift = 0, CONST_B_mask = 0xff << 8, CONST_B_shift = 8, CONST_C_mask = 0xff << 16, CONST_C_shift = 16, CONST_D_mask = 0xff << 24, CONST_D_shift = 24, SQ_BOOL_CONST_0 = 0x0003a500, SQ_BOOL_CONST_0_num = 6, SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, SQ_TEX_WRAP = 0x00, SQ_TEX_MIRROR = 0x01, SQ_TEX_CLAMP_LAST_TEXEL = 0x02, SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, SQ_TEX_CLAMP_HALF_BORDER = 0x04, SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, SQ_TEX_CLAMP_BORDER = 0x06, SQ_TEX_MIRROR_ONCE_BORDER = 0x07, CLAMP_Y_mask = 0x07 << 3, CLAMP_Y_shift = 3, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ CLAMP_Z_mask = 0x07 << 6, CLAMP_Z_shift = 6, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ XY_MAG_FILTER_mask = 0x03 << 9, XY_MAG_FILTER_shift = 9, SQ_TEX_XY_FILTER_POINT = 0x00, SQ_TEX_XY_FILTER_BILINEAR = 0x01, XY_MIN_FILTER_mask = 0x03 << 11, XY_MIN_FILTER_shift = 11, /* SQ_TEX_XY_FILTER_POINT = 0x00, */ /* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ Z_FILTER_mask = 0x03 << 13, Z_FILTER_shift = 13, SQ_TEX_Z_FILTER_NONE = 0x00, SQ_TEX_Z_FILTER_POINT = 0x01, SQ_TEX_Z_FILTER_LINEAR = 0x02, MIP_FILTER_mask = 0x03 << 15, MIP_FILTER_shift = 15, /* SQ_TEX_Z_FILTER_NONE = 0x00, */ /* SQ_TEX_Z_FILTER_POINT = 0x01, */ /* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ BORDER_COLOR_TYPE_mask = 0x03 << 20, BORDER_COLOR_TYPE_shift = 20, SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, SQ_TEX_BORDER_COLOR_REGISTER = 0x03, DEPTH_COMPARE_FUNCTION_mask = 0x07 << 22, DEPTH_COMPARE_FUNCTION_shift = 22, SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, SQ_TEX_DEPTH_COMPARE_LESS = 0x01, SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, CHROMA_KEY_mask = 0x03 << 25, CHROMA_KEY_shift = 25, SQ_TEX_CHROMA_KEY_DISABLED = 0x00, SQ_TEX_CHROMA_KEY_KILL = 0x01, SQ_TEX_CHROMA_KEY_BLEND = 0x02, SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff << 0, SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, MAX_LOD_mask = 0xfff << 12, MAX_LOD_shift = 12, PERF_MIP_mask = 0x0f << 24, PERF_MIP_shift = 24, PERF_Z_mask = 0x0f << 28, PERF_Z_shift = 28, SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff << 0, SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, LOD_BIAS_SEC_mask = 0x3f << 14, LOD_BIAS_SEC_shift = 14, MC_COORD_TRUNCATE_bit = 1 << 20, SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21, TRUNCATE_COORD_bit = 1 << 28, SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, SQ_VTX_BASE_VTX_LOC = 0x0003cff0, SQ_VTX_START_INST_LOC = 0x0003cff4, SQ_TEX_SAMPLER_CLEAR = 0x0003ff00, SQ_TEX_RESOURCE_CLEAR = 0x0003ff04, SQ_LOOP_BOOL_CLEAR = 0x0003ff08, } ; #endif /* _EVERGREEN_REG_AUTO_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_shader.c000066400000000000000000003600521256524674500237570ustar00rootroot00000000000000/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "evergreen_shader.h" #include "evergreen_reg.h" /* solid vs --------------------------------------- */ int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_VC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 - always export a param whether it's used or not */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 3 - padding */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* solid ps --------------------------------------- */ int evergreen_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(2), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 3 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 4 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 5 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); return i; } /* copy vs --------------------------------------- */ int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_VC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 3 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 6/7 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* copy ps --------------------------------------- */ int evergreen_copy_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* CF INST 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(3), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* CF INST 1 */ shader[i++] = CF_DWORD0(ADDR(8), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_TC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* CF INST 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 3 interpolate tex coords */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 4 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 5 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 6 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 7 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 8/9 TEX INST 0 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), /* R */ DST_SEL_Y(SQ_SEL_Y), /* G */ DST_SEL_Z(SQ_SEL_Z), /* B */ DST_SEL_W(SQ_SEL_W), /* A */ LOD_BIAS(0), COORD_TYPE_X(TEX_UNNORMALIZED), COORD_TYPE_Y(TEX_UNNORMALIZED), COORD_TYPE_Z(TEX_UNNORMALIZED), COORD_TYPE_W(TEX_UNNORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(6), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_VC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(4), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(2), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 3 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 4 texX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 5 texY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 6/7 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 8/9 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(5), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(21), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ shader[i++] = CF_DWORD0(ADDR(30), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 3 */ shader[i++] = CF_ALU_DWORD0(ADDR(9), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(12), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 5 interpolate tex coords */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 6 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 7 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 8 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 9,10,11,12 */ /* r2.x = MAD(c0.w, r1.x, c0.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c0.w, r1.x, c0.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c0.w, r1.x, c0.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 13,14,15,16 */ /* r2.x = MAD(c1.x, r1.y, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c1.y, r1.y, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c1.z, r1.y, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_W), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 17,18,19,20 */ /* r2.x = MAD(c2.x, r1.z, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* r2.y = MAD(c2.y, r1.z, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* r2.z = MAD(c2.z, r1.z, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 21 */ shader[i++] = CF_DWORD0(ADDR(24), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_TC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 22 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 23 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 24/25 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 26/27 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_X), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 28/29 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(2), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_X), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(2), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 30 */ shader[i++] = CF_DWORD0(ADDR(32), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_TC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 31 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 32/33 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } /* comp vs --------------------------------------- */ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(3), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(9), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_NOP), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 3 - mask sub */ shader[i++] = CF_DWORD0(ADDR(44), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_VC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(14), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(20), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 6 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT), MARK(0), BARRIER(0)); /* 7 - mask */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(1), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 8 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 9 - non-mask sub */ shader[i++] = CF_DWORD0(ADDR(50), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_VC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 10 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(34), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(10), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 11 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* 12 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), BURST_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(0)); /* 13 */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 14 srcX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 15 srcX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 16 srcX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 17 srcX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 18 srcY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 19 srcY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 20 srcY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 21 srcY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 22 maskX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 23 maskX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 24 maskX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 25 maskX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 26 maskY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 27 maskY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 28 maskY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 29 maskY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 30 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 31 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 32 maskX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 33 maskY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 34 srcX.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 35 srcX.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 36 srcX.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 37 srcX.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 38 srcY.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 39 srcY.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 40 srcY.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 41 srcY.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 42 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 43 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_KCACHE0_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* mask vfetch - 44/45 - dst */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(24)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(2), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 46/47 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 48/49 - mask */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(16), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* no mask vfetch - 50/51 - dst */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; /* 52/53 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), BUFFER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = VTX_DWORD_PAD; return i; } /* comp ps --------------------------------------- */ int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t *shader) { int i = 0; /* 0 */ /* call interp-fetch-mask if boolean1 == true */ shader[i++] = CF_DWORD0(ADDR(11), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(1), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 1 */ /* call read-constant-mask if boolean1 == false */ shader[i++] = CF_DWORD0(ADDR(14), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(1), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ /* call interp-fetch-src if boolean0 == true */ shader[i++] = CF_DWORD0(ADDR(6), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 3 */ /* call read-constant-src if boolean0 == false */ shader[i++] = CF_DWORD0(ADDR(9), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 4 */ /* src IN mask (GPR2 := GPR1 .* GPR0) */ shader[i++] = CF_ALU_DWORD0(ADDR(16), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 */ /* export pixel data */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), BURST_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(1), CF_INST(SQ_CF_INST_EXPORT_DONE), MARK(0), BARRIER(1)); /* subroutine interp-fetch-src */ /* 6 */ /* interpolate src */ shader[i++] = CF_ALU_DWORD0(ADDR(20), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 7 */ /* texture fetch src into GPR0 */ shader[i++] = CF_DWORD0(ADDR(24), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_TC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 8 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(0)); /* subroutine read-constant-src */ /* 9 */ /* read constants into GPR0 */ shader[i++] = CF_ALU_DWORD0(ADDR(26), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(1), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 10 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(0)); /* subroutine interp-fetch-mask */ /* 11 */ /* interpolate mask */ shader[i++] = CF_ALU_DWORD0(ADDR(30), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 12 */ /* texture fetch mask into GPR1 */ shader[i++] = CF_DWORD0(ADDR(34), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_TC), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 13 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(0)); /* subroutine read-constant-src */ /* 14 */ /* read constants into GPR1 */ shader[i++] = CF_ALU_DWORD0(ADDR(36), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_LOCK_1)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), ALT_CONST(1), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 15 */ /* return */ shader[i++] = CF_DWORD0(ADDR(0), JUMPTABLE_SEL(SQ_CF_JUMPTABLE_SEL_CONST_A)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), VALID_PIXEL_MODE(0), END_OF_PROGRAM(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(0)); /* ALU clauses */ /* 16 */ /* MUL gpr[0].x gpr[0].x gpr[1].x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 17 */ /* MUL gpr[0].y gpr[0].y gpr[1].y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 18 */ /* MUL gpr[0].z gpr[0].z gpr[1].z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 19 */ /* MUL gpr[0].w gpr[0].w gpr[1].w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 20 */ /* INTERP_XY GPR0.x, GPR0.y PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 21 */ /* INTERP_XY GPR0.y, GPR0.x PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 22 */ /* INTERP_XY GPR0.z, GPR0.y PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 23 */ /* INTERP_XY GPR0.w, GPR0.x PARAM0.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 24/25 */ /* SAMPLE RID=0 GPR0, GPR0 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 26 */ /* MOV GPR0.x, KC4.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 27 */ /* MOV GPR0.y, KC4.y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 28 */ /* MOV GPR0.z, KC4.z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 29 */ /* MOV GPR0.w, KC4.w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 30 */ /* INTERP_XY GPR1.x, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 31 */ /* INTERP_XY GPR1.y, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 32 */ /* INTERP_XY GPR1.z, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 33 */ /* INTERP_XY GPR1.w, PARAM1 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_PARAM_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_INTERP_XY), BANK_SWIZZLE(SQ_ALU_VEC_210), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 34/35 */ /* SAMPLE RID=1 GPR1, GPR1 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), INST_MOD(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(1), SRC_REL(ABSOLUTE), ALT_CONST(0), RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE), SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 36 */ /* MOV GPR1.x, KC5.x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 37 */ /* MOV GPR1.y, KC5.y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 38 */ /* MOV GPR1.z, KC5.z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 39 */ /* MOV GPR1.w, KC5.w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_KCACHE0_BASE + 5), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); return i; } xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_shader.h000066400000000000000000000247631256524674500237720ustar00rootroot00000000000000/* * Evergreen shaders * * Copyright (C) 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * Shader macros */ #ifndef __SHADER_H__ #define __SHADER_H__ #include "radeon.h" /* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */ // CF insts // addr #define ADDR(x) (x) // jumptable #define JUMPTABLE_SEL(x) (x) // pc #define POP_COUNT(x) (x) // const #define CF_CONST(x) (x) // cond #define COND(x) (x) // SQ_COND_* // count #define I_COUNT(x) ((x) ? ((x) - 1) : 0) // vpm #define VALID_PIXEL_MODE(x) (x) // eop #define END_OF_PROGRAM(x) (x) // cf inst #define CF_INST(x) (x) // SQ_CF_INST_* // wqm #define WHOLE_QUAD_MODE(x) (x) // barrier #define BARRIER(x) (x) //kb0 #define KCACHE_BANK0(x) (x) //kb1 #define KCACHE_BANK1(x) (x) // km0/1 #define KCACHE_MODE0(x) (x) #define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_* // #define KCACHE_ADDR0(x) (x) #define KCACHE_ADDR1(x) (x) #define ALT_CONST(x) (x) #define ARRAY_BASE(x) (x) // export pixel #define CF_PIXEL_MRT0 0 #define CF_PIXEL_MRT1 1 #define CF_PIXEL_MRT2 2 #define CF_PIXEL_MRT3 3 #define CF_PIXEL_MRT4 4 #define CF_PIXEL_MRT5 5 #define CF_PIXEL_MRT6 6 #define CF_PIXEL_MRT7 7 // computed Z #define CF_COMPUTED_Z 61 // export pos #define CF_POS0 60 #define CF_POS1 61 #define CF_POS2 62 #define CF_POS3 63 // export param // 0...31 #define TYPE(x) (x) // SQ_EXPORT_* #define RW_GPR(x) (x) #define RW_REL(x) (x) #define ABSOLUTE 0 #define RELATIVE 1 #define INDEX_GPR(x) (x) #define ELEM_SIZE(x) (x ? (x - 1) : 0) #define BURST_COUNT(x) (x ? (x - 1) : 0) #define MARK(x) (x) // swiz #define SRC_SEL_X(x) (x) // SQ_SEL_* each #define SRC_SEL_Y(x) (x) #define SRC_SEL_Z(x) (x) #define SRC_SEL_W(x) (x) #define CF_DWORD0(addr, jmptbl) cpu_to_le32(((addr) | ((jmptbl) << 24))) #define CF_DWORD1(pc, cf_const, cond, count, vpm, eop, cf_inst, wqm, b) \ cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \ ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | ((wqm) << 30) | ((b) << 31))) #define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))) #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \ cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ ((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))) #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \ ((index_gpr) << 23) | ((es) << 30))) #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, eop, cf_inst, m, b) \ cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \ ((bc) << 16) | ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | \ ((m) << 30) | ((b) << 31))) // ALU clause insts #define SRC0_SEL(x) (x) #define SRC1_SEL(x) (x) #define SRC2_SEL(x) (x) // src[0-2]_sel // 0-127 GPR // 128-159 kcache constants bank 0 // 160-191 kcache constants bank 1 // 192-255 inline const values // 256-287 kcache constants bank 2 // 288-319 kcache constants bank 3 // 219-255 special SQ_ALU_SRC_* (0, 1, etc.) // 488-520 src param space #define ALU_SRC_GPR_BASE 0 #define ALU_SRC_KCACHE0_BASE 128 #define ALU_SRC_KCACHE1_BASE 160 #define ALU_SRC_INLINE_K_BASE 192 #define ALU_SRC_KCACHE2_BASE 256 #define ALU_SRC_KCACHE3_BASE 288 #define ALU_SRC_PARAM_BASE 448 #define SRC0_REL(x) (x) #define SRC1_REL(x) (x) #define SRC2_REL(x) (x) // elem #define SRC0_ELEM(x) (x) #define SRC1_ELEM(x) (x) #define SRC2_ELEM(x) (x) #define ELEM_X 0 #define ELEM_Y 1 #define ELEM_Z 2 #define ELEM_W 3 // neg #define SRC0_NEG(x) (x) #define SRC1_NEG(x) (x) #define SRC2_NEG(x) (x) // im #define INDEX_MODE(x) (x) // SQ_INDEX_* // ps #define PRED_SEL(x) (x) // SQ_PRED_SEL_* // last #define LAST(x) (x) // abs #define SRC0_ABS(x) (x) #define SRC1_ABS(x) (x) // uem #define UPDATE_EXECUTE_MASK(x) (x) // up #define UPDATE_PRED(x) (x) // wm #define WRITE_MASK(x) (x) // omod #define OMOD(x) (x) // SQ_ALU_OMOD_* // alu inst #define ALU_INST(x) (x) // SQ_ALU_INST_* //bs #define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_* #define DST_GPR(x) (x) #define DST_REL(x) (x) #define DST_ELEM(x) (x) #define CLAMP(x) (x) #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ ((im) << 26) | ((ps) << 29) | ((last) << 31))) #define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ ((de) << 29) | ((clamp) << 31))) // VTX clause insts // vxt insts #define VTX_INST(x) (x) // SQ_VTX_INST_* // fetch type #define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_* #define FETCH_WHOLE_QUAD(x) (x) #define BUFFER_ID(x) (x) #define SRC_GPR(x) (x) #define SRC_REL(x) (x) #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) #define DST_SEL_X(x) (x) #define DST_SEL_Y(x) (x) #define DST_SEL_Z(x) (x) #define DST_SEL_W(x) (x) #define USE_CONST_FIELDS(x) (x) #define DATA_FORMAT(x) (x) // num format #define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_* // format comp #define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_* // sma #define SRF_MODE_ALL(x) (x) #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 #define SRF_MODE_NO_ZERO 1 #define OFFSET(x) (x) // endian swap #define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_* #define CONST_BUF_NO_STRIDE(x) (x) // mf #define MEGA_FETCH(x) (x) #define BUFFER_INDEX_MODE(x) (x) #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26))) #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) #define VTX_DWORD2(offset, es, cbns, mf, alt_const, bim) \ cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19) | ((alt_const) << 20) | ((bim) << 21))) #define VTX_DWORD_PAD cpu_to_le32(0x00000000) // TEX clause insts // tex insts #define TEX_INST(x) (x) // SQ_TEX_INST_* #define INST_MOD(x) (x) #define FETCH_WHOLE_QUAD(x) (x) #define RESOURCE_ID(x) (x) #define RESOURCE_INDEX_MODE(x) (x) #define SAMPLER_INDEX_MODE(x) (x) #define LOD_BIAS(x) (x) //ct #define COORD_TYPE_X(x) (x) #define COORD_TYPE_Y(x) (x) #define COORD_TYPE_Z(x) (x) #define COORD_TYPE_W(x) (x) #define TEX_UNNORMALIZED 0 #define TEX_NORMALIZED 1 #define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */ #define OFFSET_Y(x) (((int)(x) * 2) & 0x1f) #define OFFSET_Z(x) (((int)(x) * 2) & 0x1f) #define SAMPLER_ID(x) (x) #define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \ cpu_to_le32((((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27))) #define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31))) #define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \ cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \ ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29))) #define TEX_DWORD_PAD cpu_to_le32(0x00000000) extern int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int evergreen_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int evergreen_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader); extern int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader); extern int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_state.h000066400000000000000000000255241256524674500236400ustar00rootroot00000000000000/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: Alex Deucher * */ #ifndef __EVERGREEN_STATE_H__ #define __EVERGREEN_STATE_H__ typedef int bool_t; #define CLEAR(x) memset (&x, 0, sizeof(x)) /* Sequencer / thread handling */ typedef struct { int ps_prio; int vs_prio; int gs_prio; int es_prio; int hs_prio; int ls_prio; int cs_prio; int num_ps_gprs; int num_vs_gprs; int num_gs_gprs; int num_es_gprs; int num_hs_gprs; int num_ls_gprs; int num_cs_gprs; int num_temp_gprs; int num_ps_threads; int num_vs_threads; int num_gs_threads; int num_es_threads; int num_hs_threads; int num_ls_threads; int num_ps_stack_entries; int num_vs_stack_entries; int num_gs_stack_entries; int num_es_stack_entries; int num_hs_stack_entries; int num_ls_stack_entries; } sq_config_t; /* Color buffer / render target */ typedef struct { int id; int w; int h; uint64_t base; int format; int endian; int array_mode; // tiling int non_disp_tiling; int number_type; int read_size; int comp_swap; int tile_mode; int blend_clamp; int clear_color; int blend_bypass; int simple_float; int round_mode; int tile_compact; int source_format; int resource_type; int fast_clear; int compression; int rat; /* 2D related CB state */ uint32_t pmask; int rop; int blend_enable; uint32_t blendcntl; struct radeon_bo *bo; struct radeon_surface *surface; } cb_config_t; /* Shader */ typedef struct { uint64_t shader_addr; uint32_t shader_size; int num_gprs; int stack_size; int dx10_clamp; int clamp_consts; int export_mode; int uncached_first_inst; int single_round; int double_round; int allow_sdi; int allow_sd0; int allow_ddi; int allow_ddo; struct radeon_bo *bo; } shader_config_t; /* Shader consts */ typedef struct { int type; int size_bytes; uint64_t const_addr; struct radeon_bo *bo; uint32_t *cpu_ptr; } const_config_t; /* Vertex buffer / vtx resource */ typedef struct { int id; uint64_t vb_addr; uint32_t vtx_num_entries; uint32_t vtx_size_dw; int clamp_x; int format; int num_format_all; int format_comp_all; int srf_mode_all; int endian; int mem_req_size; int dst_sel_x; int dst_sel_y; int dst_sel_z; int dst_sel_w; int uncached; struct radeon_bo *bo; } vtx_resource_t; /* Texture resource */ typedef struct { int id; int w; int h; int pitch; int depth; int dim; int array_mode; int tile_type; int format; uint64_t base; uint64_t mip_base; uint32_t size; int format_comp_x; int format_comp_y; int format_comp_z; int format_comp_w; int num_format_all; int srf_mode_all; int force_degamma; int endian; int dst_sel_x; int dst_sel_y; int dst_sel_z; int dst_sel_w; int base_level; int last_level; int base_array; int last_array; int perf_modulation; int interlaced; int min_lod; struct radeon_bo *bo; struct radeon_bo *mip_bo; struct radeon_surface *surface; } tex_resource_t; /* Texture sampler */ typedef struct { int id; /* Clamping */ int clamp_x, clamp_y, clamp_z; int border_color; /* Filtering */ int xy_mag_filter, xy_min_filter; int z_filter; int mip_filter; bool_t high_precision_filter; /* ? */ int perf_mip; /* ? 0-7 */ int perf_z; /* ? 3 */ /* LoD selection */ int min_lod, max_lod; /* 0-0x3ff */ int lod_bias; /* 0-0xfff (signed?) */ int lod_bias2; /* ? 0-0xfff (signed?) */ bool_t lod_uses_minor_axis; /* ? */ /* Other stuff */ bool_t point_sampling_clamp; /* ? */ bool_t tex_array_override; /* ? */ bool_t mc_coord_truncate; /* ? */ bool_t force_degamma; /* ? */ bool_t fetch_4; /* ? */ bool_t sample_is_pcf; /* ? */ bool_t type; /* ? */ int depth_compare; /* only depth textures? */ int chroma_key; int truncate_coord; bool_t disable_cube_wrap; } tex_sampler_t; /* Draw command */ typedef struct { uint32_t prim_type; uint32_t vgt_draw_initiator; uint32_t index_type; uint32_t num_instances; uint32_t num_indices; } draw_config_t; #define BEGIN_BATCH(n) \ do { \ radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ } while(0) #define END_BATCH() \ do { \ radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ } while(0) #define RELOC_BATCH(bo, rd, wd) \ do { \ int _ret; \ _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \ if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \ } while(0) #define E32(dword) \ do { \ radeon_cs_write_dword(info->cs, (dword)); \ } while (0) #define EFLOAT(val) \ do { \ union { float f; uint32_t d; } a; \ a.f = (val); \ E32(a.d); \ } while (0) #define PACK3(cmd, num) \ do { \ E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ } while (0) /* write num registers, start at reg */ /* If register falls in a special area, special commands are issued */ #define PACK0(reg, num) \ do { \ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \ PACK3(IT_SET_CONFIG_REG, (num) + 1); \ E32(((reg) - SET_CONFIG_REG_offset) >> 2); \ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \ PACK3(IT_SET_CONTEXT_REG, (num) + 1); \ E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \ PACK3(IT_SET_RESOURCE, num + 1); \ E32(((reg) - SET_RESOURCE_offset) >> 2); \ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \ PACK3(IT_SET_SAMPLER, (num) + 1); \ E32((reg - SET_SAMPLER_offset) >> 2); \ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \ PACK3(IT_SET_CTL_CONST, (num) + 1); \ E32(((reg) - SET_CTL_CONST_offset) >> 2); \ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \ PACK3(IT_SET_LOOP_CONST, (num) + 1); \ E32(((reg) - SET_LOOP_CONST_offset) >> 2); \ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \ PACK3(IT_SET_BOOL_CONST, (num) + 1); \ E32(((reg) - SET_BOOL_CONST_offset) >> 2); \ } else { \ E32(CP_PACKET0 ((reg), (num) - 1)); \ } \ } while (0) /* write a single register */ #define EREG(reg, val) \ do { \ PACK0((reg), 1); \ E32((val)); \ } while (0) void evergreen_start_3d(ScrnInfoPtr pScrn); void evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain); void evergreen_set_blend_color(ScrnInfoPtr pScrn, float *color); void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); void evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp); void evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain); void evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain); void evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain); void evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain); void evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val); void evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain); void evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s); void evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void evergreen_set_default_state(ScrnInfoPtr pScrn); void cayman_set_default_state(ScrnInfoPtr pScrn); void evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf); void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size); extern Bool R600SetAccelState(ScrnInfoPtr pScrn, struct r600_accel_object *src0, struct r600_accel_object *src1, struct r600_accel_object *dst, uint32_t vs_offset, uint32_t ps_offset, int rop, Pixel planemask); extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index); extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index); extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align); extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, int depth, int usage_hint, int bitsPerPixel, int *new_pitch); extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv); extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix); extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p); extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/evergreen_textured_videofuncs.c000066400000000000000000000416711256524674500266050ustar00rootroot00000000000000/* * Copyright 2010 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "exa.h" #include "radeon.h" #include "radeon_reg.h" #include "evergreen_shader.h" #include "evergreen_reg.h" #include "evergreen_state.h" #include "radeon_video.h" #include #include "fourcc.h" #include "damage.h" #include "radeon_exa_shared.h" #include "radeon_vbo.h" /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces note the difference to the parameters used in overlay are due to 10bit vs. float calcs */ static REF_TRANSFORM trans[2] = { {1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */ {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ }; void EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; PixmapPtr pPixmap = pPriv->pPixmap; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); int dstxoff, dstyoff; struct r600_accel_object src_obj, dst_obj; cb_config_t cb_conf; tex_resource_t tex_res; tex_sampler_t tex_samp; shader_config_t vs_conf, ps_conf; /* * y' = y - .0625 * u' = u - .5 * v' = v - .5; * * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' * * DP3 might look like the straightforward solution * but we'd need to move the texture yuv values in * the same reg for this to work. Therefore use MADs. * Brightness just adds to the off constant. * Contrast is multiplication of luminance. * Saturation and hue change the u and v coeffs. * Default values (before adjustments - depend on colorspace): * yco = 1.1643 * uco = 0, -0.39173, 2.017 * vco = 1.5958, -0.8129, 0 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], * * temp = MAD(yco, yuv.yyyy, off) * temp = MAD(uco, yuv.uuuu, temp) * result = MAD(vco, yuv.vvvv, temp) */ /* TODO: calc consts in the shader */ const float Loff = -0.0627; const float Coff = -0.502; float uvcosf, uvsinf; float yco; float uco[3], vco[3], off[3]; float bright, cont, gamma; int ref = pPriv->transform_index; float *ps_alu_consts; const_config_t ps_const_conf; float *vs_alu_consts; const_config_t vs_const_conf; cont = RTFContrast(pPriv->contrast); bright = RTFBrightness(pPriv->brightness); gamma = (float)pPriv->gamma / 1000.0; uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); /* overlay video also does pre-gamma contrast/sat adjust, should we? */ yco = trans[ref].RefLuma * cont; uco[0] = -trans[ref].RefRCr * uvsinf; uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; uco[2] = trans[ref].RefBCb * uvcosf; vco[0] = trans[ref].RefRCr * uvcosf; vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; vco[2] = trans[ref].RefBCb * uvsinf; off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; // XXX gamma = 1.0; CLEAR (cb_conf); CLEAR (tex_res); CLEAR (tex_samp); CLEAR (vs_conf); CLEAR (ps_conf); CLEAR (vs_const_conf); CLEAR (ps_const_conf); dst_obj.bo = radeon_get_pixmap_bo(pPixmap); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); dst_obj.surface = radeon_get_pixmap_surface(pPixmap); dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); src_obj.pitch = pPriv->src_pitch; src_obj.width = pPriv->w; src_obj.height = pPriv->h; src_obj.bpp = 16; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = pPriv->src_bo[pPriv->currentBuffer]; src_obj.tiling_flags = 0; src_obj.surface = NULL; dst_obj.width = pPixmap->drawable.width; dst_obj.height = pPixmap->drawable.height; dst_obj.bpp = pPixmap->drawable.bitsPerPixel; dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->xv_vs_offset, accel_state->xv_ps_offset, 3, 0xffffffff)) return; #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_vbo_check(pScrn, &accel_state->cbuf, 512); radeon_cp_start(pScrn); evergreen_set_default_state(pScrn); evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* PS bool constant */ switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); break; case FOURCC_UYVY: case FOURCC_YUY2: default: evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); break; } /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 3; ps_conf.stack_size = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* Texture */ switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; /* Y texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; tex_res.surface = NULL; tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_X; /* Y */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; /* xxx: switch to bicubic */ tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ evergreen_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 1; tex_res.format = FMT_8; tex_res.w = accel_state->src_obj[0].width >> 1; tex_res.h = accel_state->src_obj[0].height >> 1; tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; tex_res.base = pPriv->planev_offset; tex_res.mip_base = pPriv->planev_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* U or V sampler */ tex_samp.id = 1; evergreen_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 2; tex_res.format = FMT_8; tex_res.w = accel_state->src_obj[0].width >> 1; tex_res.h = accel_state->src_obj[0].height >> 1; tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; tex_res.base = pPriv->planeu_offset; tex_res.mip_base = pPriv->planeu_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ tex_samp.id = 2; evergreen_set_tex_sampler(pScrn, &tex_samp); break; case FOURCC_UYVY: case FOURCC_YUY2: default: accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; /* YUV texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch >> 1; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; tex_res.surface = NULL; if (pPriv->id == FOURCC_UYVY) tex_res.format = FMT_GB_GR; else tex_res.format = FMT_BG_RG; tex_res.dst_sel_x = SQ_SEL_Y; tex_res.dst_sel_y = SQ_SEL_X; tex_res.dst_sel_z = SQ_SEL_Z; tex_res.dst_sel_w = SQ_SEL_1; tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* YUV sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ evergreen_set_tex_sampler(pScrn, &tex_samp); break; } cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; switch (accel_state->dst_obj.bpp) { case 16: if (pPixmap->drawable.depth == 15) { cb_conf.format = COLOR_1_5_5_5; cb_conf.comp_swap = 1; /* ARGB */ } else { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ } #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN16; #endif break; case 32: cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN32; #endif break; default: return; } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; cb_conf.pmask = 0xf; cb_conf.rop = 3; if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) == RADEON_TILING_LINEAR) { cb_conf.array_mode = 1; cb_conf.non_disp_tiling = 1; } evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); evergreen_set_spi(pScrn, (1 - 1), 1); /* PS alu constants */ ps_const_conf.size_bytes = 256; ps_const_conf.type = SHADER_TYPE_PS; ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); ps_const_conf.bo = accel_state->cbuf.vb_bo; ps_const_conf.const_addr = accel_state->cbuf.vb_offset; ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts; ps_alu_consts[0] = off[0]; ps_alu_consts[1] = off[1]; ps_alu_consts[2] = off[2]; ps_alu_consts[3] = yco; ps_alu_consts[4] = uco[0]; ps_alu_consts[5] = uco[1]; ps_alu_consts[6] = uco[2]; ps_alu_consts[7] = gamma; ps_alu_consts[8] = vco[0]; ps_alu_consts[9] = vco[1]; ps_alu_consts[10] = vco[2]; ps_alu_consts[11] = 0.0; radeon_vbo_commit(pScrn, &accel_state->cbuf); evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT); /* VS alu constants */ vs_const_conf.size_bytes = 256; vs_const_conf.type = SHADER_TYPE_VS; vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); vs_const_conf.bo = accel_state->cbuf.vb_bo; vs_const_conf.const_addr = accel_state->cbuf.vb_offset; vs_const_conf.cpu_ptr = (uint32_t *)(char *)vs_alu_consts; vs_alu_consts[0] = 1.0 / pPriv->w; vs_alu_consts[1] = 1.0 / pPriv->h; vs_alu_consts[2] = 0.0; vs_alu_consts[3] = 0.0; radeon_vbo_commit(pScrn, &accel_state->cbuf); evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) evergreen_cp_wait_vline_sync(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } while (nBox--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; float *vb; dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + dsth); vb[6] = (float)srcX; vb[7] = (float)(srcY + srch); vb[8] = (float)(dstX + dstw); vb[9] = (float)(dstY + dsth); vb[10] = (float)(srcX + srcw); vb[11] = (float)(srcY + srch); radeon_vbo_commit(pScrn, &accel_state->vbo); pBox++; } evergreen_finish_op(pScrn, 16); DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } xserver-xorg-video-ati-7.5.0+git20150819/src/pcidb/000077500000000000000000000000001256524674500213565ustar00rootroot00000000000000xserver-xorg-video-ati-7.5.0+git20150819/src/pcidb/ati_pciids.csv000066400000000000000000001225261256524674500242130ustar00rootroot00000000000000"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name" "0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)" "0x3151","RV380_3151","RV380",,,,,,"ATI FireMV 2400 (PCI)" "0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" "0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" "0x3155","RV380_3155","RV380",1,,,,,"ATI FireMV 2400 3155 (PCI)" "0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" "0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380) 3E54 (PCIE)" "0x4136","RS100_4136","RS100",,1,,,1,"ATI Radeon IGP320 (A3) 4136" "0x4137","RS200_4137","RS200",,1,,,1,"ATI Radeon IGP330/340/350 (A4) 4137" "0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500 AD (AGP)" "0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500 AE (AGP)" "0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX AF (AGP)" "0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1 AG (AGP)" "0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE AH (AGP)" "0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800 AI (AGP)" "0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800 AJ (AGP)" "0x414B","R350_AK","R350",,,,,,"ATI FireGL X2 AK (AGP)" "0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600 AP (AGP)" "0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE AQ (AGP)" "0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT AR (AGP)" "0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600 AS (AGP)" "0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2 AT (AGP)" "0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650" "0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360 AV (AGP)" "0x4158","MACH32","MACH32",,,,,, "0x4237","RS250_4237","RS200",,1,,,1,"ATI Radeon 7000 IGP (A4+) 4237" "0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW BB (AGP)" "0x4336","RS100_4336","RS100",1,1,,,1,"ATI Radeon IGP320M (U1) 4336" "0x4337","RS200_4337","RS200",1,1,,,1,"ATI Radeon IGP330M/340M/350M (U2) 4337" "0x4354","MACH64CT","MACH64",,,,,, "0x4358","MACH64CX","MACH64",,,,,, "0x4437","RS250_4437","RS200",1,1,,,1,"ATI Radeon Mobility 7000 IGP 4437" "0x4554","MACH64ET","MACH64",,,,,, "0x4742","MACH64GB","MACH64",,,,,, "0x4744","MACH64GD","MACH64",,,,,, "0x4749","MACH64GI","MACH64",,,,,, "0x474C","MACH64GL","MACH64",,,,,, "0x474D","MACH64GM","MACH64",,,,,, "0x474E","MACH64GN","MACH64",,,,,, "0x474F","MACH64GO","MACH64",,,,,, "0x4750","MACH64GP","MACH64",,,,,, "0x4751","MACH64GQ","MACH64",,,,,, "0x4752","MACH64GR","MACH64",,,,,, "0x4753","MACH64GS","MACH64",,,,,, "0x4754","MACH64GT","MACH64",,,,,, "0x4755","MACH64GU","MACH64",,,,,, "0x4756","MACH64GV","MACH64",,,,,, "0x4757","MACH64GW","MACH64",,,,,, "0x4758","MACH64GX","MACH64",,,,,, "0x4759","MACH64GY","MACH64",,,,,, "0x475A","MACH64GZ","MACH64",,,,,, "0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO If (AGP/PCI)" "0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000 Ig (AGP/PCI)" "0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420) JH (AGP)" "0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420) JI (AGP)" "0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420) JJ (AGP)" "0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420) JK (AGP)" "0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420) JL (AGP)" "0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420) JM (AGP)" "0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18) JN (AGP)" "0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420) (AGP)" "0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420) JP (AGP)" "0x4A54","R420_JT","R420",,,,,,"ATI Radeon X800 VE (R420) JT (AGP)" "0x4B48","R481_4B48","R420",,,,,,"ATI Radeon X850 (R480) (AGP)" "0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480) (AGP)" "0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480) (AGP)" "0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480) (AGP)" "0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480) (AGP)" "0x4C42","MACH64LB","MACH64",,,,,, "0x4C44","MACH64LD","MACH64",,,,,, "0x4C45","RAGE128LE","R128",,,,,, "0x4C46","RAGE128LF","R128",,,,,, "0x4C47","MACH64LG","MACH64",,,,,, "0x4C49","MACH64LI","MACH64",,,,,, "0x4C4D","MACH64LM","MACH64",,,,,, "0x4C4E","MACH64LN","MACH64",,,,,, "0x4C50","MACH64LP","MACH64",,,,,, "0x4C51","MACH64LQ","MACH64",,,,,, "0x4C52","MACH64LR","MACH64",,,,,, "0x4C53","MACH64LS","MACH64",,,,,, "0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7 LW (AGP)" "0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7 LX (AGP)" "0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6 LY (AGP)" "0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6 LZ (AGP)" "0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)" "0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)" "0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)" "0x4C6E","RV280_4C6E","RV280",1,,,,,"ATI FireMV 2400 PCI" "0x4D46","RAGE128MF","R128",,,,,, "0x4D4C","RAGE128ML","R128",,,,,, "0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)" "0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro NE (AGP)" "0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX NF (AGP)" "0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1 NG (AGP)" "0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO NH (AGP)" "0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800 NI (AGP)" "0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2 NK (AGP)" "0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT NJ (AGP)" "0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" "0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NQ (AGP)" "0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11) NR (AGP)" "0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NS (AGP)" "0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10) NT (AGP)" "0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11) NV (AGP)" "0x5041","RAGE128PA","R128",,,,,, "0x5042","RAGE128PB","R128",,,,,, "0x5043","RAGE128PC","R128",,,,,, "0x5044","RAGE128PD","R128",,,,,, "0x5045","RAGE128PE","R128",,,,,, "0x5046","RAGE128PF","R128",,,,,, "0x5047","RAGE128PG","R128",,,,,, "0x5048","RAGE128PH","R128",,,,,, "0x5049","RAGE128PI","R128",,,,,, "0x504A","RAGE128PJ","R128",,,,,, "0x504B","RAGE128PK","R128",,,,,, "0x504C","RAGE128PL","R128",,,,,, "0x504D","RAGE128PM","R128",,,,,, "0x504E","RAGE128PN","R128",,,,,, "0x504F","RAGE128PO","R128",,,,,, "0x5050","RAGE128PP","R128",,,,,, "0x5051","RAGE128PQ","R128",,,,,, "0x5052","RAGE128PR","R128",,,,,, "0x5053","RAGE128PS","R128",,,,,, "0x5054","RAGE128PT","R128",,,,,, "0x5055","RAGE128PU","R128",,,,,, "0x5056","RAGE128PV","R128",,,,,, "0x5057","RAGE128PW","R128",,,,,, "0x5058","RAGE128PX","R128",,,,,, "0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon QD (AGP)" "0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon QE (AGP)" "0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon QF (AGP)" "0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon QG (AGP)" "0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800 QH (AGP)" "0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500 QL (AGP)" "0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100 QM (AGP)" "0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500 QW (AGP/PCI)" "0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500 QX (AGP/PCI)" "0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000 QY (AGP/PCI)" "0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000 QZ (AGP/PCI)" "0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000 515E (PCI)" "0x5245","RAGE128RE","R128",,,,,, "0x5246","RAGE128RF","R128",,,,,, "0x5247","RAGE128RG","R128",,,,,, "0x524B","RAGE128RK","R128",,,,,, "0x524C","RAGE128RL","R128",,,,,, "0x5345","RAGE128SE","R128",,,,,, "0x5346","RAGE128SF","R128",,,,,, "0x5347","RAGE128SG","R128",,,,,, "0x5348","RAGE128SH","R128",,,,,, "0x534B","RAGE128SK","R128",,,,,, "0x534C","RAGE128SL","R128",,,,,, "0x534D","RAGE128SM","R128",,,,,, "0x534E","RAGE128SN","R128",,,,,, "0x5446","RAGE128TF","R128",,,,,, "0x544C","RAGE128TL","R128",,,,,, "0x5452","RAGE128TR","R128",,,,,, "0x5453","RAGE128TS","R128",,,,,, "0x5454","RAGE128TT","R128",,,,,, "0x5455","RAGE128TU","R128",,,,,, "0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22) 5460 (PCIE)" "0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" "0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL 5464 (PCIE)" "0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423) UH (PCIE)" "0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423) UI (PCIE)" "0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423) UJ (PCIE)" "0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423) UK (PCIE)" "0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430) (PCIE)" "0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430) (PCIE)" "0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430) (PCIE)" "0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430) (PCIE)" "0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423) (PCIE)" "0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423) UQ (PCIE)" "0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423) UR (PCIE)" "0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423) UT (PCIE)" "0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" "0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" "0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" "0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" "0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" "0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX 5657 (PCIE)" "0x5654","MACH64VT","MACH64",,,,,, "0x5655","MACH64VU","MACH64",,,,,, "0x5656","MACH64VV","MACH64",,,,,, "0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" "0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" "0x5954","RS480_5954","RS480",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" "0x5955","RS480_5955","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" "0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)" "0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)" "0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)" "0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)" "0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)" "0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)" "0x5974","RS482_5974","RS480",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" "0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" "0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" "0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" "0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" "0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" "0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" "0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28) (PCIE)" "0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28) (PCIE)" "0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28) (PCIE)" "0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850 5D4C (PCIE)" "0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480) (PCIE)" "0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480) (PCIE)" "0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480) (PCIE)" "0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" "0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480) (PCIE)" "0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423) 5D57 (PCIE)" "0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410) (PCIE)" "0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410) (PCIE)" "0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410) (PCIE)" "0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" "0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)" "0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" "0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800" "0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT" "0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800" "0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200" "0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200" "0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300" "0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100" "0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800" "0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800" "0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800" "0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800" "0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800" "0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300" "0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350" "0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600" "0x7141","RV515_7141","RV515",,,,,,"ATI RV505" "0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550" "0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550" "0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL" "0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400" "0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550" "0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit" "0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300" "0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300" "0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300" "0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300" "0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300" "0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300" "0x714F","RV515_714F","RV515",,,,,,"ATI RV505" "0x7151","RV515_7151","RV515",,,,,,"ATI RV505" "0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300" "0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350" "0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300" "0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit" "0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550" "0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600" "0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550" "0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450" "0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550" "0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300" "0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300" "0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350" "0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350" "0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450" "0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300" "0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550" "0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350" "0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250" "0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit" "0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600" "0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650" "0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600" "0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600" "0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200" "0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600" "0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650" "0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650" "0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600" "0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro" "0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400" "0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250" "0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700" "0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" "0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" "0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700" "0x7200","RV515_7200","RV515",,,,,,"ATI Radeon X2300HD" "0x7210","RV515_7210","RV515",1,,,,,"ATI Mobility Radeon HD 2300" "0x7211","RV515_7211","RV515",1,,,,,"ATI Mobility Radeon HD 2300" "0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950" "0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900" "0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950" "0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900" "0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900" "0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900" "0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900" "0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900" "0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900" "0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900" "0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900" "0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900" "0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor" "0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900" "0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950" "0x7281","RV560_7281","RV560",,,,,,"ATI RV560" "0x7283","RV560_7283","RV560",,,,,,"ATI RV560" "0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900" "0x7287","RV560_7287","RV560",,,,,,"ATI RV560" "0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT" "0x7289","RV570_7289","RV570",,,,,,"ATI RV570" "0x728B","RV570_728B","RV570",,,,,,"ATI RV570" "0x728C","RV570_728C","RV570",,,,,,"ATI FireGL V7400" "0x7290","RV560_7290","RV560",,,,,,"ATI RV560" "0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650" "0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650" "0x7297","RV560_7297","RV560",,,,,,"ATI RV560" "0x7834","RS350_7834","RS300",,1,,,1,"ATI Radeon 9100 PRO IGP 7834" "0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP 7835" "0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200" "0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200" "0x793F","RS600_793F","RS600",,1,,,1,"ATI Radeon X1200" "0x7941","RS600_7941","RS600",,1,,,1,"ATI Radeon X1200" "0x7942","RS600_7942","RS600",,1,,,1,"ATI Radeon X1200" "0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740" "0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M" "0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740" "0x796F","RS740_796F","RS740",,1,,,1,"ATI RS740M" "0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT" "0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT" "0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT" "0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro" "0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT" "0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" "0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" "0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" "0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series" "0x9441","RV770_9441","RV770",,,,,,"ATI Radeon HD 4870 x2" "0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series" "0x9443","RV770_9443","RV770",,,,,,"ATI Radeon HD 4850 x2" "0x9444","RV770_9444","RV770",,,,,,"ATI FirePro V8750 (FireGL)" "0x9446","RV770_9446","RV770",,,,,,"ATI FirePro V7760 (FireGL)" "0x944A","RV770_944A","RV770",1,,,,,"ATI Mobility RADEON HD 4850" "0x944B","RV770_944B","RV770",1,,,,,"ATI Mobility RADEON HD 4850 X2" "0x944C","RV770_944C","RV770",,,,,,"ATI Radeon 4800 Series" "0x944E","RV770_944E","RV770",,,,,,"ATI FirePro RV770" "0x9450","RV770_9450","RV770",,,,,,"AMD FireStream 9270" "0x9452","RV770_9452","RV770",,,,,,"AMD FireStream 9250" "0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)" "0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870" "0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98" "0x945E","RV770_945E","RV770",1,,,,,"ATI Mobility RADEON HD 4870" "0x9460","RV790_9460","RV770",,,,,,"ATI Radeon 4800 Series" "0x9462","RV790_9462","RV770",,,,,,"ATI Radeon 4800 Series" "0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750" "0x946B","RV770_946B","RV770",1,,,,,"ATI M98" "0x947A","RV770_947A","RV770",1,,,,,"ATI M98" "0x947B","RV770_947B","RV770",1,,,,,"ATI M98" "0x9480","RV730_9480","RV730",1,,,,,"ATI Mobility Radeon HD 4650" "0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)" "0x9488","RV730_9488","RV730",1,,,,,"ATI Mobility Radeon HD 4670" "0x9489","RV730_9489","RV730",1,,,,,"ATI FirePro M5750" "0x948A","RV730_948A","RV730",1,,,,,"ATI Mobility Radeon HD 4670" "0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)" "0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]" "0x9491","RV730_9491","RV730",,,,,,"ATI RADEON E4600" "0x9495","RV730_9495","RV730",,,,,,"ATI Radeon HD 4600 Series" "0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]" "0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)" "0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)" "0x949F","RV730_949F","RV730",,,,,,"ATI FirePro V3750 (FireGL)" "0x94A0","RV740_94A0","RV740",1,,,,,"ATI Mobility Radeon HD 4830" "0x94A1","RV740_94A1","RV740",1,,,,,"ATI Mobility Radeon HD 4850" "0x94A3","RV740_94A3","RV740",1,,,,,"ATI FirePro M7740" "0x94B1","RV740_94B1","RV740",,,,,,"ATI RV740" "0x94B3","RV740_94B3","RV740",,,,,,"ATI Radeon HD 4770" "0x94B4","RV740_94B4","RV740",,,,,,"ATI Radeon HD 4700 Series" "0x94B5","RV740_94B5","RV740",,,,,,"ATI Radeon HD 4770" "0x94B9","RV740_94B9","RV740",1,,,,,"ATI FirePro M5750" "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" "0x94C4","RV610_94C4","RV610",,,,,,"ATI Radeon HD 2400 PRO AGP" "0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000" "0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610" "0x94C7","RV610_94C7","RV610",,,,,,"ATI Radeon HD 2350" "0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT" "0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" "0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400" "0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" "0x94CD","RV610_94CD","RV610",,,,,,"ATI FireMV 2260" "0x9500","RV670_9500","RV670",,,,,,"ATI RV670" "0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870" "0x9504","RV670_9504","RV670",1,,,,,"ATI Mobility Radeon HD 3850" "0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850" "0x9506","RV670_9506","RV670",1,,,,,"ATI Mobility Radeon HD 3850 X2" "0x9507","RV670_9507","RV670",,,,,,"ATI RV670" "0x9508","RV670_9508","RV670",1,,,,,"ATI Mobility Radeon HD 3870" "0x9509","RV670_9509","RV670",1,,,,,"ATI Mobility Radeon HD 3870 X2" "0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" "0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" "0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850" "0x9517","RV670_9517","RV670",,,,,,"ATI Radeon HD3690" "0x9519","RV670_9519","RV670",,,,,,"AMD Firestream 9170" "0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550" "0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710" "0x9542","RV710_9542","RV710",,,,,,"ATI Radeon RV710" "0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710" "0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350" "0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series" "0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series" "0x9555","RV710_9555","RV710",1,,,,,"ATI Mobility Radeon 4500 Series" "0x9557","RV710_9557","RV710",1,,,,,"ATI FirePro RG220" "0x955F","RV710_955F","RV710",1,,,,,"ATI Mobility Radeon 4330" "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" "0x9586","RV630_9586","RV630",,,,,,"ATI Radeon HD 2600 XT AGP" "0x9587","RV630_9587","RV630",,,,,,"ATI Radeon HD 2600 Pro AGP" "0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT" "0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro" "0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630" "0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini Mobility Radeon HD 2600 XT" "0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" "0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" "0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE" "0x958F","RV630_958F","RV630",1,,,,,"ATI Mobility FireGL Graphics Processor" "0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470" "0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430" "0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series" "0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" "0x95C6","RV620_95C6","RV620",,,,,,"ATI Radeon HD 3450" "0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" "0x95C9","RV620_95C9","RV620",,,,,,"ATI Radeon HD 3450" "0x95CC","RV620_95CC","RV620",,,,,,"ATI FirePro V3700" "0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450" "0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260" "0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260" "0x9590","RV635_9590","RV635",,,,,,"ATI Radeon HD 3600 Series" "0x9596","RV635_9596","RV635",,,,,,"ATI Radeon HD 3650 AGP" "0x9597","RV635_9597","RV635",,,,,,"ATI Radeon HD 3600 PRO" "0x9598","RV635_9598","RV635",,,,,,"ATI Radeon HD 3600 XT" "0x9599","RV635_9599","RV635",,,,,,"ATI Radeon HD 3600 PRO" "0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650" "0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670" "0x9595","RV635_9595","RV635",1,,,,,"ATI Mobility FireGL V5700" "0x959B","RV635_959B","RV635",1,,,,,"ATI Mobility FireGL V5725" "0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" "0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics" "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" "0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics" "0x9615","RS780_9615","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" "0x9616","RS780_9616","RS780",,1,,,1,"ATI Radeon 3000 Graphics" "0x9640","SUMO_9640","SUMO",,1,,,1,"SUMO" "0x9641","SUMO_9641","SUMO",1,1,,,1,"SUMO" "0x9642","SUMO2_9642","SUMO2",,1,,,1,"SUMO2" "0x9643","SUMO2_9643","SUMO2",1,1,,,1,"SUMO2" "0x9644","SUMO2_9644","SUMO2",,1,,,1,"SUMO2" "0x9645","SUMO2_9645","SUMO2",1,1,,,1,"SUMO2" "0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO" "0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO" "0x9649","SUMO2_9649","SUMO2",1,1,,,1,"SUMO2" "0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO" "0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO" "0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO" "0x964E","SUMO_964E","SUMO",1,1,,,1,"SUMO" "0x964F","SUMO_964F","SUMO",1,1,,,1,"SUMO" "0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD 4200" "0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon 4100" "0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200" "0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100" "0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290" "0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4250" "0x9802","PALM_9802","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics" "0x9803","PALM_9803","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics" "0x9804","PALM_9804","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics" "0x9805","PALM_9805","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics" "0x9806","PALM_9806","PALM",,1,,,1,"AMD Radeon HD 6300 Series Graphics" "0x9807","PALM_9807","PALM",,1,,,1,"AMD Radeon HD 6200 Series Graphics" "0x9808","PALM_9808","PALM",,1,,,1,"PALM" "0x9809","PALM_9809","PALM",,1,,,1,"PALM" "0x980A","PALM_980A","PALM",,1,,,1,"PALM" "0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS" "0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x688A","CYPRESS_688A","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x688C","CYPRESS_688C","CYPRESS",,,,,,"AMD Firestream 9370" "0x688D","CYPRESS_688D","CYPRESS",,,,,,"AMD Firestream 9350" "0x6898","CYPRESS_6898","CYPRESS",,,,,,"ATI Radeon HD 5800 Series" "0x6899","CYPRESS_6899","CYPRESS",,,,,,"ATI Radeon HD 5800 Series" "0x689B","CYPRESS_689B","CYPRESS",,,,,,"ATI Radeon HD 5800 Series" "0x689E","CYPRESS_689E","CYPRESS",,,,,,"ATI Radeon HD 5800 Series" "0x689C","HEMLOCK_689C","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series" "0x689D","HEMLOCK_689D","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series" "0x68A0","JUNIPER_68A0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series" "0x68A1","JUNIPER_68A1","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series" "0x68A8","JUNIPER_68A8","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68A9","JUNIPER_68A9","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68B0","JUNIPER_68B0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series" "0x68B8","JUNIPER_68B8","JUNIPER",,,,,,"ATI Radeon HD 5700 Series" "0x68B9","JUNIPER_68B9","JUNIPER",,,,,,"ATI Radeon HD 5700 Series" "0x68BA","JUNIPER_68BA","JUNIPER",,,,,,"ATI Radeon HD 6700 Series" "0x68BE","JUNIPER_68BE","JUNIPER",,,,,,"ATI Radeon HD 5700 Series" "0x68BF","JUNIPER_68BF","JUNIPER",,,,,,"ATI Radeon HD 6700 Series" "0x68C0","REDWOOD_68C0","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series" "0x68C1","REDWOOD_68C1","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series" "0x68C7","REDWOOD_68C7","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5570" "0x68C8","REDWOOD_68C8","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68C9","REDWOOD_68C9","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68D8","REDWOOD_68D8","REDWOOD",,,,,,"ATI Radeon HD 5670" "0x68D9","REDWOOD_68D9","REDWOOD",,,,,,"ATI Radeon HD 5570" "0x68DA","REDWOOD_68DA","REDWOOD",,,,,,"ATI Radeon HD 5500 Series" "0x68DE","REDWOOD_68DE","REDWOOD",,,,,,"REDWOOD" "0x68E0","CEDAR_68E0","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series" "0x68E1","CEDAR_68E1","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series" "0x68E4","CEDAR_68E4","CEDAR",1,,,,,"ATI Mobility Radeon Graphics" "0x68E5","CEDAR_68E5","CEDAR",1,,,,,"ATI Mobility Radeon Graphics" "0x68E8","CEDAR_68E8","CEDAR",,,,,,"CEDAR" "0x68E9","CEDAR_68E9","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68F1","CEDAR_68F1","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter" "0x68F2","CEDAR_68F2","CEDAR",,,,,,"ATI FirePro 2270" "0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR" "0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450" "0x68FA","CEDAR_68FA","CEDAR",,,,,,"CEDAR" "0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR" "0x6700","CAYMAN_6700","CAYMAN",,,,,,"CAYMAN" "0x6701","CAYMAN_6701","CAYMAN",,,,,,"CAYMAN" "0x6702","CAYMAN_6702","CAYMAN",,,,,,"CAYMAN" "0x6703","CAYMAN_6703","CAYMAN",,,,,,"CAYMAN" "0x6704","CAYMAN_6704","CAYMAN",,,,,,"CAYMAN" "0x6705","CAYMAN_6705","CAYMAN",,,,,,"CAYMAN" "0x6706","CAYMAN_6706","CAYMAN",,,,,,"CAYMAN" "0x6707","CAYMAN_6707","CAYMAN",,,,,,"CAYMAN" "0x6708","CAYMAN_6708","CAYMAN",,,,,,"CAYMAN" "0x6709","CAYMAN_6709","CAYMAN",,,,,,"CAYMAN" "0x6718","CAYMAN_6718","CAYMAN",,,,,,"AMD Radeon HD 6900 Series" "0x6719","CAYMAN_6719","CAYMAN",,,,,,"AMD Radeon HD 6900 Series" "0x671C","CAYMAN_671C","CAYMAN",,,,,,"CAYMAN" "0x671D","CAYMAN_671D","CAYMAN",,,,,,"CAYMAN" "0x671F","CAYMAN_671F","CAYMAN",,,,,,"CAYMAN" "0x6720","BARTS_6720","BARTS",1,,,,,"AMD Radeon HD 6900M Series" "0x6721","BARTS_6721","BARTS",1,,,,,"Mobility Radeon HD 6000 Series" "0x6722","BARTS_6722","BARTS",,,,,,"BARTS" "0x6723","BARTS_6723","BARTS",,,,,,"BARTS" "0x6724","BARTS_6724","BARTS",1,,,,,"Mobility Radeon HD 6000 Series" "0x6725","BARTS_6725","BARTS",1,,,,,"Mobility Radeon HD 6000 Series" "0x6726","BARTS_6726","BARTS",,,,,,"BARTS" "0x6727","BARTS_6727","BARTS",,,,,,"BARTS" "0x6728","BARTS_6728","BARTS",,,,,,"BARTS" "0x6729","BARTS_6729","BARTS",,,,,,"BARTS" "0x6738","BARTS_6738","BARTS",,,,,,"AMD Radeon HD 6800 Series" "0x6739","BARTS_6739","BARTS",,,,,,"AMD Radeon HD 6800 Series" "0x673E","BARTS_673E","BARTS",,,,,,"AMD Radeon HD 6700 Series" "0x6740","TURKS_6740","TURKS",1,,,,,"TURKS" "0x6741","TURKS_6741","TURKS",1,,,,,"TURKS" "0x6742","TURKS_6742","TURKS",1,,,,,"TURKS" "0x6743","TURKS_6743","TURKS",1,,,,,"TURKS" "0x6744","TURKS_6744","TURKS",1,,,,,"TURKS" "0x6745","TURKS_6745","TURKS",1,,,,,"TURKS" "0x6746","TURKS_6746","TURKS",,,,,,"TURKS" "0x6747","TURKS_6747","TURKS",,,,,,"TURKS" "0x6748","TURKS_6748","TURKS",,,,,,"TURKS" "0x6749","TURKS_6749","TURKS",,,,,,"TURKS" "0x674A","TURKS_674A","TURKS",,,,,,"TURKS" "0x6750","TURKS_6750","TURKS",,,,,,"TURKS" "0x6751","TURKS_6751","TURKS",,,,,,"TURKS" "0x6758","TURKS_6758","TURKS",,,,,,"TURKS" "0x6759","TURKS_6759","TURKS",,,,,,"TURKS" "0x675B","TURKS_675B","TURKS",,,,,,"TURKS" "0x675D","TURKS_675D","TURKS",,,,,,"TURKS" "0x675F","TURKS_675F","TURKS",,,,,,"TURKS" "0x6840","TURKS_6840","TURKS",1,,,,,"TURKS" "0x6841","TURKS_6841","TURKS",1,,,,,"TURKS" "0x6842","TURKS_6842","TURKS",1,,,,,"TURKS" "0x6843","TURKS_6843","TURKS",1,,,,,"TURKS" "0x6849","TURKS_6849","TURKS",,,,,,"TURKS" "0x6850","TURKS_6850","TURKS",,,,,,"TURKS" "0x6858","TURKS_6858","TURKS",,,,,,"TURKS" "0x6859","TURKS_6859","TURKS",,,,,,"TURKS" "0x6760","CAICOS_6760","CAICOS",1,,,,,"CAICOS" "0x6761","CAICOS_6761","CAICOS",1,,,,,"CAICOS" "0x6762","CAICOS_6762","CAICOS",,,,,,"CAICOS" "0x6763","CAICOS_6763","CAICOS",,,,,,"CAICOS" "0x6764","CAICOS_6764","CAICOS",1,,,,,"CAICOS" "0x6765","CAICOS_6765","CAICOS",1,,,,,"CAICOS" "0x6766","CAICOS_6766","CAICOS",,,,,,"CAICOS" "0x6767","CAICOS_6767","CAICOS",,,,,,"CAICOS" "0x6768","CAICOS_6768","CAICOS",,,,,,"CAICOS" "0x6770","CAICOS_6770","CAICOS",,,,,,"CAICOS" "0x6771","CAICOS_6771","CAICOS",,,,,,"CAICOS" "0x6772","CAICOS_6772","CAICOS",,,,,,"CAICOS" "0x6778","CAICOS_6778","CAICOS",,,,,,"CAICOS" "0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS" "0x677B","CAICOS_677B","CAICOS",,,,,,"CAICOS" "0x9900","ARUBA_9900","ARUBA",1,1,,,,"ARUBA" "0x9901","ARUBA_9901","ARUBA",,1,,,,"ARUBA" "0x9903","ARUBA_9903","ARUBA",1,1,,,,"ARUBA" "0x9904","ARUBA_9904","ARUBA",,1,,,,"ARUBA" "0x9905","ARUBA_9905","ARUBA",,1,,,,"ARUBA" "0x9906","ARUBA_9906","ARUBA",,1,,,,"ARUBA" "0x9907","ARUBA_9907","ARUBA",1,1,,,,"ARUBA" "0x9908","ARUBA_9908","ARUBA",1,1,,,,"ARUBA" "0x9909","ARUBA_9909","ARUBA",1,1,,,,"ARUBA" "0x990A","ARUBA_990A","ARUBA",1,1,,,,"ARUBA" "0x990B","ARUBA_990B","ARUBA",1,1,,,,"ARUBA" "0x990C","ARUBA_990C","ARUBA",,1,,,,"ARUBA" "0x990D","ARUBA_990D","ARUBA",1,1,,,,"ARUBA" "0x990E","ARUBA_990E","ARUBA",,1,,,,"ARUBA" "0x990F","ARUBA_990F","ARUBA",1,1,,,,"ARUBA" "0x9910","ARUBA_9910","ARUBA",1,1,,,,"ARUBA" "0x9913","ARUBA_9913","ARUBA",1,1,,,,"ARUBA" "0x9917","ARUBA_9917","ARUBA",,1,,,,"ARUBA" "0x9918","ARUBA_9918","ARUBA",,1,,,,"ARUBA" "0x9919","ARUBA_9919","ARUBA",,1,,,,"ARUBA" "0x9990","ARUBA_9990","ARUBA",1,1,,,,"ARUBA" "0x9991","ARUBA_9991","ARUBA",,1,,,,"ARUBA" "0x9992","ARUBA_9992","ARUBA",1,1,,,,"ARUBA" "0x9993","ARUBA_9993","ARUBA",,1,,,,"ARUBA" "0x9994","ARUBA_9994","ARUBA",1,1,,,,"ARUBA" "0x9995","ARUBA_9995","ARUBA",1,1,,,,"ARUBA" "0x9996","ARUBA_9996","ARUBA",,1,,,,"ARUBA" "0x9997","ARUBA_9997","ARUBA",1,1,,,,"ARUBA" "0x9998","ARUBA_9998","ARUBA",,1,,,,"ARUBA" "0x9999","ARUBA_9999","ARUBA",1,1,,,,"ARUBA" "0x999A","ARUBA_999A","ARUBA",1,1,,,,"ARUBA" "0x999B","ARUBA_999B","ARUBA",1,1,,,,"ARUBA" "0x999C","ARUBA_999C","ARUBA",,1,,,,"ARUBA" "0x999D","ARUBA_999D","ARUBA",,1,,,,"ARUBA" "0x99A0","ARUBA_99A0","ARUBA",1,1,,,,"ARUBA" "0x99A2","ARUBA_99A2","ARUBA",1,1,,,,"ARUBA" "0x99A4","ARUBA_99A4","ARUBA",,1,,,,"ARUBA" "0x6780","TAHITI_6780","TAHITI",,,,,,"TAHITI" "0x6784","TAHITI_6784","TAHITI",,,,,,"TAHITI" "0x6788","TAHITI_6788","TAHITI",,,,,,"TAHITI" "0x678A","TAHITI_678A","TAHITI",,,,,,"TAHITI" "0x6790","TAHITI_6790","TAHITI",,,,,,"TAHITI" "0x6791","TAHITI_6791","TAHITI",,,,,,"TAHITI" "0x6792","TAHITI_6792","TAHITI",,,,,,"TAHITI" "0x6798","TAHITI_6798","TAHITI",,,,,,"TAHITI" "0x6799","TAHITI_6799","TAHITI",,,,,,"TAHITI" "0x679A","TAHITI_679A","TAHITI",,,,,,"TAHITI" "0x679B","TAHITI_679B","TAHITI",,,,,,"TAHITI" "0x679E","TAHITI_679E","TAHITI",,,,,,"TAHITI" "0x679F","TAHITI_679F","TAHITI",,,,,,"TAHITI" "0x6800","PITCAIRN_6800","PITCAIRN",1,,,,,"PITCAIRN" "0x6801","PITCAIRN_6801","PITCAIRN",1,,,,,"PITCAIRN" "0x6802","PITCAIRN_6802","PITCAIRN",1,,,,,"PITCAIRN" "0x6806","PITCAIRN_6806","PITCAIRN",,,,,,"PITCAIRN" "0x6808","PITCAIRN_6808","PITCAIRN",,,,,,"PITCAIRN" "0x6809","PITCAIRN_6809","PITCAIRN",,,,,,"PITCAIRN" "0x6810","PITCAIRN_6810","PITCAIRN",,,,,,"PITCAIRN" "0x6811","PITCAIRN_6811","PITCAIRN",,,,,,"PITCAIRN" "0x6816","PITCAIRN_6816","PITCAIRN",,,,,,"PITCAIRN" "0x6817","PITCAIRN_6817","PITCAIRN",,,,,,"PITCAIRN" "0x6818","PITCAIRN_6818","PITCAIRN",,,,,,"PITCAIRN" "0x6819","PITCAIRN_6819","PITCAIRN",,,,,,"PITCAIRN" "0x684C","PITCAIRN_684C","PITCAIRN",,,,,,"PITCAIRN" "0x6820","VERDE_6820","VERDE",1,,,,,"VERDE" "0x6821","VERDE_6821","VERDE",1,,,,,"VERDE" "0x6822","VERDE_6822","VERDE",1,,,,,"VERDE" "0x6823","VERDE_6823","VERDE",1,,,,,"VERDE" "0x6824","VERDE_6824","VERDE",1,,,,,"VERDE" "0x6825","VERDE_6825","VERDE",1,,,,,"VERDE" "0x6826","VERDE_6826","VERDE",1,,,,,"VERDE" "0x6827","VERDE_6827","VERDE",1,,,,,"VERDE" "0x6828","VERDE_6828","VERDE",,,,,,"VERDE" "0x6829","VERDE_6829","VERDE",,,,,,"VERDE" "0x682A","VERDE_682A","VERDE",1,,,,,"VERDE" "0x682B","VERDE_682B","VERDE",1,,,,,"VERDE" "0x682C","VERDE_682C","VERDE",,,,,,"VERDE" "0x682D","VERDE_682D","VERDE",1,,,,,"VERDE" "0x682F","VERDE_682F","VERDE",1,,,,,"VERDE" "0x6830","VERDE_6830","VERDE",1,,,,,"VERDE" "0x6831","VERDE_6831","VERDE",1,,,,,"VERDE" "0x6835","VERDE_6835","VERDE",,,,,,"VERDE" "0x6837","VERDE_6837","VERDE",,,,,,"VERDE" "0x6838","VERDE_6838","VERDE",,,,,,"VERDE" "0x6839","VERDE_6839","VERDE",,,,,,"VERDE" "0x683B","VERDE_683B","VERDE",,,,,,"VERDE" "0x683D","VERDE_683D","VERDE",,,,,,"VERDE" "0x683F","VERDE_683F","VERDE",,,,,,"VERDE" "0x6600","OLAND_6600","OLAND",1,,,,,"OLAND" "0x6601","OLAND_6601","OLAND",1,,,,,"OLAND" "0x6602","OLAND_6602","OLAND",1,,,,,"OLAND" "0x6603","OLAND_6603","OLAND",1,,,,,"OLAND" "0x6604","OLAND_6604","OLAND",1,,,,,"OLAND" "0x6605","OLAND_6605","OLAND",1,,,,,"OLAND" "0x6606","OLAND_6606","OLAND",1,,,,,"OLAND" "0x6607","OLAND_6607","OLAND",1,,,,,"OLAND" "0x6608","OLAND_6608","OLAND",,,,,,"OLAND" "0x6610","OLAND_6610","OLAND",,,,,,"OLAND" "0x6611","OLAND_6611","OLAND",,,,,,"OLAND" "0x6613","OLAND_6613","OLAND",,,,,,"OLAND" "0x6617","OLAND_6617","OLAND",1,,,,,"OLAND" "0x6620","OLAND_6620","OLAND",1,,,,,"OLAND" "0x6621","OLAND_6621","OLAND",1,,,,,"OLAND" "0x6623","OLAND_6623","OLAND",1,,,,,"OLAND" "0x6631","OLAND_6631","OLAND",,,,,,"OLAND" "0x6660","HAINAN_6660","HAINAN",1,,,,,"HAINAN" "0x6663","HAINAN_6663","HAINAN",1,,,,,"HAINAN" "0x6664","HAINAN_6664","HAINAN",1,,,,,"HAINAN" "0x6665","HAINAN_6665","HAINAN",1,,,,,"HAINAN" "0x6667","HAINAN_6667","HAINAN",1,,,,,"HAINAN" "0x666F","HAINAN_666F","HAINAN",1,,,,,"HAINAN" "0x6640","BONAIRE_6640","BONAIRE",1,,,,,"BONAIRE" "0x6641","BONAIRE_6641","BONAIRE",1,,,,,"BONAIRE" "0x6646","BONAIRE_6646","BONAIRE",1,,,,,"BONAIRE" "0x6647","BONAIRE_6647","BONAIRE",1,,,,,"BONAIRE" "0x6649","BONAIRE_6649","BONAIRE",,,,,,"BONAIRE" "0x6650","BONAIRE_6650","BONAIRE",,,,,,"BONAIRE" "0x6651","BONAIRE_6651","BONAIRE",,,,,,"BONAIRE" "0x6658","BONAIRE_6658","BONAIRE",,,,,,"BONAIRE" "0x665C","BONAIRE_665C","BONAIRE",,,,,,"BONAIRE" "0x665D","BONAIRE_665D","BONAIRE",,,,,,"BONAIRE" "0x665F","BONAIRE_665F","BONAIRE",,,,,,"BONAIRE" "0x9830","KABINI_9830","KABINI",1,1,,,1,"KABINI" "0x9831","KABINI_9831","KABINI",,1,,,1,"KABINI" "0x9832","KABINI_9832","KABINI",1,1,,,1,"KABINI" "0x9833","KABINI_9833","KABINI",,1,,,1,"KABINI" "0x9834","KABINI_9834","KABINI",1,1,,,1,"KABINI" "0x9835","KABINI_9835","KABINI",,1,,,1,"KABINI" "0x9836","KABINI_9836","KABINI",1,1,,,1,"KABINI" "0x9837","KABINI_9837","KABINI",,1,,,1,"KABINI" "0x9838","KABINI_9838","KABINI",1,1,,,1,"KABINI" "0x9839","KABINI_9839","KABINI",1,1,,,1,"KABINI" "0x983A","KABINI_983A","KABINI",,1,,,1,"KABINI" "0x983B","KABINI_983B","KABINI",1,1,,,1,"KABINI" "0x983C","KABINI_983C","KABINI",,1,,,1,"KABINI" "0x983D","KABINI_983D","KABINI",,1,,,1,"KABINI" "0x983E","KABINI_983E","KABINI",,1,,,1,"KABINI" "0x983F","KABINI_983F","KABINI",,1,,,1,"KABINI" "0x9850","MULLINS_9850","MULLINS",1,1,,,1,"MULLINS" "0x9851","MULLINS_9851","MULLINS",1,1,,,1,"MULLINS" "0x9852","MULLINS_9852","MULLINS",1,1,,,1,"MULLINS" "0x9853","MULLINS_9853","MULLINS",1,1,,,1,"MULLINS" "0x9854","MULLINS_9854","MULLINS",1,1,,,1,"MULLINS" "0x9855","MULLINS_9855","MULLINS",1,1,,,1,"MULLINS" "0x9856","MULLINS_9856","MULLINS",1,1,,,1,"MULLINS" "0x9857","MULLINS_9857","MULLINS",1,1,,,1,"MULLINS" "0x9858","MULLINS_9858","MULLINS",1,1,,,1,"MULLINS" "0x9859","MULLINS_9859","MULLINS",1,1,,,1,"MULLINS" "0x985A","MULLINS_985A","MULLINS",1,1,,,1,"MULLINS" "0x985B","MULLINS_985B","MULLINS",1,1,,,1,"MULLINS" "0x985C","MULLINS_985C","MULLINS",1,1,,,1,"MULLINS" "0x985D","MULLINS_985D","MULLINS",1,1,,,1,"MULLINS" "0x985E","MULLINS_985E","MULLINS",1,1,,,1,"MULLINS" "0x985F","MULLINS_985F","MULLINS",1,1,,,1,"MULLINS" "0x1304","KAVERI_1304","KAVERI",1,1,,,1,"KAVERI" "0x1305","KAVERI_1305","KAVERI",,1,,,1,"KAVERI" "0x1306","KAVERI_1306","KAVERI",1,1,,,1,"KAVERI" "0x1307","KAVERI_1307","KAVERI",,1,,,1,"KAVERI" "0x1309","KAVERI_1309","KAVERI",1,1,,,1,"KAVERI" "0x130A","KAVERI_130A","KAVERI",1,1,,,1,"KAVERI" "0x130B","KAVERI_130B","KAVERI",1,1,,,1,"KAVERI" "0x130C","KAVERI_130C","KAVERI",1,1,,,1,"KAVERI" "0x130D","KAVERI_130D","KAVERI",1,1,,,1,"KAVERI" "0x130E","KAVERI_130E","KAVERI",1,1,,,1,"KAVERI" "0x130F","KAVERI_130F","KAVERI",,1,,,1,"KAVERI" "0x1310","KAVERI_1310","KAVERI",,1,,,1,"KAVERI" "0x1311","KAVERI_1311","KAVERI",,1,,,1,"KAVERI" "0x1312","KAVERI_1312","KAVERI",,1,,,1,"KAVERI" "0x1313","KAVERI_1313","KAVERI",,1,,,1,"KAVERI" "0x1315","KAVERI_1315","KAVERI",,1,,,1,"KAVERI" "0x1316","KAVERI_1316","KAVERI",,1,,,1,"KAVERI" "0x1317","KAVERI_1317","KAVERI",1,1,,,1,"KAVERI" "0x1318","KAVERI_1318","KAVERI",1,1,,,1,"KAVERI" "0x131B","KAVERI_131B","KAVERI",,1,,,1,"KAVERI" "0x131C","KAVERI_131C","KAVERI",,1,,,1,"KAVERI" "0x131D","KAVERI_131D","KAVERI",,1,,,1,"KAVERI" "0x67A0","HAWAII_67A0","HAWAII",,,,,,"HAWAII" "0x67A1","HAWAII_67A1","HAWAII",,,,,,"HAWAII" "0x67A2","HAWAII_67A2","HAWAII",,,,,,"HAWAII" "0x67A8","HAWAII_67A8","HAWAII",,,,,,"HAWAII" "0x67A9","HAWAII_67A9","HAWAII",,,,,,"HAWAII" "0x67AA","HAWAII_67AA","HAWAII",,,,,,"HAWAII" "0x67B0","HAWAII_67B0","HAWAII",,,,,,"HAWAII" "0x67B1","HAWAII_67B1","HAWAII",,,,,,"HAWAII" "0x67B8","HAWAII_67B8","HAWAII",,,,,,"HAWAII" "0x67B9","HAWAII_67B9","HAWAII",,,,,,"HAWAII" "0x67BA","HAWAII_67BA","HAWAII",,,,,,"HAWAII" "0x67BE","HAWAII_67BE","HAWAII",,,,,,"HAWAII" xserver-xorg-video-ati-7.5.0+git20150819/src/pcidb/parse_pci_ids.pl000077500000000000000000000055731256524674500245340ustar00rootroot00000000000000#!/usr/bin/perl # # Copyright 2007 Red Hat Inc. # This crappy script written by Dave Airlie to avoid hassle of adding # ids in every place. # use strict; use warnings; use Text::CSV_XS; my $file = $ARGV[0]; my $atioutfile = 'ati_pciids_gen.h'; my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h'; my $radeonpcidevicematchfile = 'radeon_pci_device_match_gen.h'; my $radeonchipsetfile = 'radeon_chipset_gen.h'; my $radeonchipinfofile = 'radeon_chipinfo_gen.h'; my $csv = Text::CSV_XS->new(); open (CSV, "<", $file) or die $!; open (ATIOUT, ">", $atioutfile) or die; open (PCICHIPSET, ">", $radeonpcichipsetfile) or die; open (PCIDEVICEMATCH, ">", $radeonpcidevicematchfile) or die; open (RADEONCHIPSET, ">", $radeonchipsetfile) or die; open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die; print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n"; print RADEONCHIPSET "SymTabRec RADEONChipsets[] = {\n"; print PCICHIPSET "/* This file is autogenerated please do not edit */\n"; print PCICHIPSET "static PciChipsets RADEONPciChipsets[] = {\n"; print PCIDEVICEMATCH "/* This file is autogenerated please do not edit */\n"; print PCIDEVICEMATCH "static const struct pci_id_match radeon_device_match[] = {\n"; print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n"; print RADEONCHIPINFO "static RADEONCardInfo RADEONCards[] = {\n"; while () { if ($csv->parse($_)) { my @columns = $csv->fields(); if ((substr($columns[0], 0, 1) ne "#")) { print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n"; if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) { print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n"; print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n"; print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n"; print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], "; if ($columns[3] eq "1") { print RADEONCHIPINFO "1, "; } else { print RADEONCHIPINFO "0, "; } if ($columns[4] eq "1") { print RADEONCHIPINFO "1, "; } else { print RADEONCHIPINFO "0, "; } if ($columns[5] eq "1") { print RADEONCHIPINFO "1, "; } else { print RADEONCHIPINFO "0, "; } if ($columns[6] eq "1") { print RADEONCHIPINFO "1, "; } else { print RADEONCHIPINFO "0, "; } if ($columns[7] eq "1") { print RADEONCHIPINFO "1 "; } else { print RADEONCHIPINFO "0 "; } print RADEONCHIPINFO "},\n"; } } } else { my $err = $csv->error_input; print "Failed to parse line: $err"; } } print RADEONCHIPINFO "};\n"; print RADEONCHIPSET " { -1, NULL }\n};\n"; print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n"; print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n"; close CSV; close ATIOUT; close PCICHIPSET; close PCIDEVICEMATCH; close RADEONCHIPSET; close RADEONCHIPINFO; xserver-xorg-video-ati-7.5.0+git20150819/src/r600_exa.c000066400000000000000000001666551256524674500220100ustar00rootroot00000000000000/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "exa.h" #include "radeon.h" #include "radeon_reg.h" #include "r600_shader.h" #include "r600_reg.h" #include "r600_state.h" #include "radeon_exa_shared.h" #include "radeon_vbo.h" /* #define SHOW_VERTEXES */ Bool R600SetAccelState(ScrnInfoPtr pScrn, struct r600_accel_object *src0, struct r600_accel_object *src1, struct r600_accel_object *dst, uint32_t vs_offset, uint32_t ps_offset, int rop, Pixel planemask) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t pitch_align = 0x7; int ret; if (src0) { memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8); if (src0->surface) accel_state->src_size[0] = src0->surface->bo_size; /* bad pitch */ if (accel_state->src_obj[0].pitch & pitch_align) RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch)); } else { memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = 0; } if (src1) { memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object)); accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8); if (src1->surface) { accel_state->src_size[1] = src1->surface->bo_size; } /* bad pitch */ if (accel_state->src_obj[1].pitch & pitch_align) RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch)); } else { memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object)); accel_state->src_size[1] = 0; } if (dst) { memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object)); accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8); if (dst->surface) { accel_state->dst_size = dst->surface->bo_size; } else { accel_state->dst_obj.tiling_flags = 0; } if (accel_state->dst_obj.pitch & pitch_align) RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch)); } else { memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object)); accel_state->dst_size = 0; } if (CS_FULL(info->cs)) radeon_cs_flush_indirect(pScrn); accel_state->rop = rop; accel_state->planemask = planemask; accel_state->vs_size = 512; accel_state->ps_size = 512; accel_state->vs_mc_addr = vs_offset; accel_state->ps_mc_addr = ps_offset; radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->src_obj[0].bo) radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0); if (accel_state->src_obj[1].bo) radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo, accel_state->src_obj[1].domain, 0); if (accel_state->dst_obj.bo) radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain); ret = radeon_cs_space_check(info->cs); if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel operation\n")); return TRUE; } static Bool R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; cb_config_t cb_conf; shader_config_t vs_conf, ps_conf; uint32_t a, r, g, b; float ps_alu_consts[4]; struct r600_accel_object dst; if (!RADEONCheckBPP(pPix->drawable.bitsPerPixel)) RADEON_FALLBACK(("R600CheckDatatype failed\n")); if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel)) RADEON_FALLBACK(("invalid planemask\n")); dst.bo = radeon_get_pixmap_bo(pPix); dst.tiling_flags = radeon_get_pixmap_tiling(pPix); dst.surface = radeon_get_pixmap_surface(pPix); dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8); dst.width = pPix->drawable.width; dst.height = pPix->drawable.height; dst.bpp = pPix->drawable.bitsPerPixel; dst.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, NULL, NULL, &dst, accel_state->solid_vs_offset, accel_state->solid_ps_offset, alu, pm)) return FALSE; CLEAR (cb_conf); CLEAR (vs_conf); CLEAR (ps_conf); radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); r600_set_default_state(pScrn); r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 1; ps_conf.stack_size = 0; ps_conf.uncached_first_inst = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; cb_conf.comp_swap = 3; /* A */ } else if (accel_state->dst_obj.bpp == 16) { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN16; #endif } else { cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN32; #endif } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; /* Render setup */ if (accel_state->planemask & 0x000000ff) cb_conf.pmask |= 4; /* B */ if (accel_state->planemask & 0x0000ff00) cb_conf.pmask |= 2; /* G */ if (accel_state->planemask & 0x00ff0000) cb_conf.pmask |= 1; /* R */ if (accel_state->planemask & 0xff000000) cb_conf.pmask |= 8; /* A */ cb_conf.rop = accel_state->rop; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 0; r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); r600_set_spi(pScrn, 0, 0); /* PS alu constants */ if (accel_state->dst_obj.bpp == 16) { r = (fg >> 11) & 0x1f; g = (fg >> 5) & 0x3f; b = (fg >> 0) & 0x1f; ps_alu_consts[0] = (float)r / 31; /* R */ ps_alu_consts[1] = (float)g / 63; /* G */ ps_alu_consts[2] = (float)b / 31; /* B */ ps_alu_consts[3] = 1.0; /* A */ } else if (accel_state->dst_obj.bpp == 8) { a = (fg >> 0) & 0xff; ps_alu_consts[0] = 0.0; /* R */ ps_alu_consts[1] = 0.0; /* G */ ps_alu_consts[2] = 0.0; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } else { a = (fg >> 24) & 0xff; r = (fg >> 16) & 0xff; g = (fg >> 8) & 0xff; b = (fg >> 0) & 0xff; ps_alu_consts[0] = (float)r / 255; /* R */ ps_alu_consts[1] = (float)g / 255; /* G */ ps_alu_consts[2] = (float)b / 255; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->dst_pix = pPix; accel_state->fg = fg; return TRUE; } static void R600DoneSolid(PixmapPtr pPix) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) r600_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); r600_finish_op(pScrn, 8); } static void R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; if (CS_FULL(info->cs)) { R600DoneSolid(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); R600PrepareSolid(accel_state->dst_pix, accel_state->rop, accel_state->planemask, accel_state->fg); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, x1, y1, x2, y2); vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8); vb[0] = (float)x1; vb[1] = (float)y1; vb[2] = (float)x1; vb[3] = (float)y2; vb[4] = (float)x2; vb[5] = (float)y2; radeon_vbo_commit(pScrn, &accel_state->vbo); } static void R600DoPrepareCopy(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; cb_config_t cb_conf; tex_resource_t tex_res; tex_sampler_t tex_samp; shader_config_t vs_conf, ps_conf; CLEAR (cb_conf); CLEAR (tex_res); CLEAR (tex_samp); CLEAR (vs_conf); CLEAR (ps_conf); radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); r600_set_default_state(pScrn); r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 1; ps_conf.stack_size = 0; ps_conf.uncached_first_inst = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* Texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; tex_res.surface = accel_state->src_obj[0].surface; if (accel_state->src_obj[0].bpp == 8) { tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_1; /* R */ tex_res.dst_sel_y = SQ_SEL_1; /* G */ tex_res.dst_sel_z = SQ_SEL_1; /* B */ tex_res.dst_sel_w = SQ_SEL_X; /* A */ } else if (accel_state->src_obj[0].bpp == 16) { tex_res.format = FMT_5_6_5; tex_res.dst_sel_x = SQ_SEL_Z; /* R */ tex_res.dst_sel_y = SQ_SEL_Y; /* G */ tex_res.dst_sel_z = SQ_SEL_X; /* B */ tex_res.dst_sel_w = SQ_SEL_1; /* A */ } else { tex_res.format = FMT_8_8_8_8; tex_res.dst_sel_x = SQ_SEL_Z; /* R */ tex_res.dst_sel_y = SQ_SEL_Y; /* G */ tex_res.dst_sel_z = SQ_SEL_X; /* B */ tex_res.dst_sel_w = SQ_SEL_W; /* A */ } tex_res.request_size = 1; tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.mc_coord_truncate = 1; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ r600_set_tex_sampler(pScrn, &tex_samp); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; cb_conf.comp_swap = 3; /* A */ } else if (accel_state->dst_obj.bpp == 16) { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ } else { cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; /* Render setup */ if (accel_state->planemask & 0x000000ff) cb_conf.pmask |= 4; /* B */ if (accel_state->planemask & 0x0000ff00) cb_conf.pmask |= 2; /* G */ if (accel_state->planemask & 0x00ff0000) cb_conf.pmask |= 1; /* R */ if (accel_state->planemask & 0xff000000) cb_conf.pmask |= 8; /* A */ cb_conf.rop = accel_state->rop; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 0; r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); r600_set_spi(pScrn, (1 - 1), 1); } static void R600DoCopy(ScrnInfoPtr pScrn) { r600_finish_op(pScrn, 16); } static void R600DoCopyVline(PixmapPtr pPix) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) r600_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); r600_finish_op(pScrn, 16); } static void R600AppendCopyVertex(ScrnInfoPtr pScrn, int srcX, int srcY, int dstX, int dstY, int w, int h) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + h); vb[6] = (float)srcX; vb[7] = (float)(srcY + h); vb[8] = (float)(dstX + w); vb[9] = (float)(dstY + h); vb[10] = (float)(srcX + w); vb[11] = (float)(srcY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } static Bool R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int xdir, int ydir, int rop, Pixel planemask) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct r600_accel_object src_obj, dst_obj; if (!RADEONCheckBPP(pSrc->drawable.bitsPerPixel)) RADEON_FALLBACK(("R600CheckDatatype src failed\n")); if (!RADEONCheckBPP(pDst->drawable.bitsPerPixel)) RADEON_FALLBACK(("R600CheckDatatype dst failed\n")); if (!RADEONValidPM(planemask, pDst->drawable.bitsPerPixel)) RADEON_FALLBACK(("Invalid planemask\n")); dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); accel_state->same_surface = FALSE; src_obj.bo = radeon_get_pixmap_bo(pSrc); dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); src_obj.surface = radeon_get_pixmap_surface(pSrc); dst_obj.surface = radeon_get_pixmap_surface(pDst); if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst)) accel_state->same_surface = TRUE; src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = pSrc->drawable.bitsPerPixel; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = pDst->drawable.bitsPerPixel; if (radeon_get_pixmap_shared(pDst) == TRUE) { dst_obj.domain = RADEON_GEM_DOMAIN_GTT; } else dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, rop, planemask)) return FALSE; if (accel_state->same_surface == TRUE) { unsigned long size = accel_state->dst_obj.surface->bo_size; unsigned long align = accel_state->dst_obj.surface->bo_alignment; if (accel_state->copy_area_bo) { radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; } accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->copy_area_bo == NULL) RADEON_FALLBACK(("temp copy surface alloc failed\n")); radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, 0, RADEON_GEM_DOMAIN_VRAM); if (radeon_cs_space_check(info->cs)) { radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; return FALSE; } accel_state->copy_area = (void*)accel_state->copy_area_bo; } else R600DoPrepareCopy(pScrn); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->dst_pix = pDst; accel_state->src_pix = pSrc; accel_state->xdir = xdir; accel_state->ydir = ydir; return TRUE; } static void R600DoneCopy(PixmapPtr pDst) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (!accel_state->same_surface) R600DoCopyVline(pDst); if (accel_state->copy_area) { accel_state->copy_area = NULL; } } static void R600Copy(PixmapPtr pDst, int srcX, int srcY, int dstX, int dstY, int w, int h) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY)) return; if (CS_FULL(info->cs)) { R600DoneCopy(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); R600PrepareCopy(accel_state->src_pix, accel_state->dst_pix, accel_state->xdir, accel_state->ydir, accel_state->rop, accel_state->planemask); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); if (accel_state->same_surface && (srcX + w <= dstX || dstX + w <= srcX || srcY + h <= dstY || dstY + h <= srcY)) { R600DoPrepareCopy(pScrn); R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); R600DoCopyVline(pDst); } else if (accel_state->same_surface && accel_state->copy_area) { uint32_t orig_dst_domain = accel_state->dst_obj.domain; uint32_t orig_src_domain = accel_state->src_obj[0].domain; uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags; uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags; struct radeon_bo *orig_bo = accel_state->dst_obj.bo; int orig_rop = accel_state->rop; /* src to tmp */ accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; accel_state->dst_obj.bo = accel_state->copy_area_bo; accel_state->dst_obj.tiling_flags = 0; accel_state->rop = 3; R600DoPrepareCopy(pScrn); R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); R600DoCopy(pScrn); /* tmp to dst */ accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM; accel_state->src_obj[0].bo = accel_state->copy_area_bo; accel_state->src_obj[0].tiling_flags = 0; accel_state->dst_obj.domain = orig_dst_domain; accel_state->dst_obj.bo = orig_bo; accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags; accel_state->rop = orig_rop; R600DoPrepareCopy(pScrn); R600AppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h); R600DoCopyVline(pDst); /* restore state */ accel_state->src_obj[0].domain = orig_src_domain; accel_state->src_obj[0].bo = orig_bo; accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags; } else R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); } struct blendinfo { Bool dst_alpha; Bool src_alpha; uint32_t blend_cntl; }; static struct blendinfo R600BlendOp[] = { /* Clear */ {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* Src */ {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* Dst */ {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, /* Over */ {0, 1, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* OverReverse */ {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, /* In */ {1, 0, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* InReverse */ {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Out */ {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, /* OutReverse */ {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Atop */ {1, 1, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* AtopReverse */ {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Xor */ {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, /* Add */ {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, }; struct formatinfo { unsigned int fmt; uint32_t card_fmt; }; static struct formatinfo R600TexFormats[] = { {PICT_a8r8g8b8, FMT_8_8_8_8}, {PICT_x8r8g8b8, FMT_8_8_8_8}, {PICT_a8b8g8r8, FMT_8_8_8_8}, {PICT_x8b8g8r8, FMT_8_8_8_8}, {PICT_b8g8r8a8, FMT_8_8_8_8}, {PICT_b8g8r8x8, FMT_8_8_8_8}, {PICT_r5g6b5, FMT_5_6_5}, {PICT_a1r5g5b5, FMT_1_5_5_5}, {PICT_x1r5g5b5, FMT_1_5_5_5}, {PICT_a8, FMT_8}, }; static uint32_t R600GetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) { uint32_t sblend, dblend; sblend = R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask; dblend = R600BlendOp[op].blend_cntl & COLOR_DESTBLEND_mask; /* If there's no dst alpha channel, adjust the blend op so that we'll treat * it as always 1. */ if (PICT_FORMAT_A(dst_format) == 0 && R600BlendOp[op].dst_alpha) { if (sblend == (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift)) sblend = (BLEND_ONE << COLOR_SRCBLEND_shift); else if (sblend == (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift)) sblend = (BLEND_ZERO << COLOR_SRCBLEND_shift); } /* If the source alpha is being used, then we should only be in a case where * the source blend factor is 0, and the source blend value is the mask * channels multiplied by the source picture's alpha. */ if (pMask && pMask->componentAlpha && R600BlendOp[op].src_alpha) { if (dblend == (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)) { dblend = (BLEND_SRC_COLOR << COLOR_DESTBLEND_shift); } else if (dblend == (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)) { dblend = (BLEND_ONE_MINUS_SRC_COLOR << COLOR_DESTBLEND_shift); } } return sblend | dblend; } static Bool R600GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: case PICT_a8b8g8r8: case PICT_x8b8g8r8: case PICT_b8g8r8a8: case PICT_b8g8r8x8: *dst_format = COLOR_8_8_8_8; break; case PICT_r5g6b5: *dst_format = COLOR_5_6_5; break; case PICT_a1r5g5b5: case PICT_x1r5g5b5: *dst_format = COLOR_1_5_5_5; break; case PICT_a8: *dst_format = COLOR_8; break; default: RADEON_FALLBACK(("Unsupported dest format 0x%x\n", (int)pDstPicture->format)); } return TRUE; } static Bool R600CheckCompositeTexture(PicturePtr pPict, PicturePtr pDstPict, int op, int unit) { unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; unsigned int i; for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) { if (R600TexFormats[i].fmt == pPict->format) break; } if (i == sizeof(R600TexFormats) / sizeof(R600TexFormats[0])) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); /* for REPEAT_NONE, Render semantics are that sampling outside the source * picture results in alpha=0 pixels. We can implement this with a border color * *if* our source texture has an alpha channel, otherwise we need to fall * back. If we're not transformed then we hope that upper layers have clipped * rendering to the bounds of the source drawable, in which case it doesn't * matter. I have not, however, verified that the X server always does such * clipping. */ /* FIXME R6xx */ if (pPict->transform != 0 && repeatType == RepeatNone && PICT_FORMAT_A(pPict->format) == 0) { if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); } if (!radeon_transform_is_affine_or_scaled(pPict->transform)) RADEON_FALLBACK(("non-affine transforms not supported\n")); return TRUE; } static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; unsigned int repeatType; unsigned int i; tex_resource_t tex_res; tex_sampler_t tex_samp; int pix_r, pix_g, pix_b, pix_a; float vs_alu_consts[8]; CLEAR (tex_res); CLEAR (tex_samp); for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) { if (R600TexFormats[i].fmt == pPict->format) break; } /* Texture */ if (pPict->pDrawable) { tex_res.w = pPict->pDrawable->width; tex_res.h = pPict->pDrawable->height; repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; } else { tex_res.w = 1; tex_res.h = 1; repeatType = RepeatNormal; } tex_res.id = unit; tex_res.pitch = accel_state->src_obj[unit].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[unit]; tex_res.format = R600TexFormats[i].card_fmt; tex_res.bo = accel_state->src_obj[unit].bo; tex_res.mip_bo = accel_state->src_obj[unit].bo; tex_res.surface = accel_state->src_obj[unit].surface; tex_res.request_size = 1; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (accel_state->src_obj[unit].bpp) { case 16: tex_res.endian = SQ_ENDIAN_8IN16; break; case 32: tex_res.endian = SQ_ENDIAN_8IN32; break; default : break; } #endif /* component swizzles */ switch (pPict->format) { case PICT_a1r5g5b5: case PICT_a8r8g8b8: pix_r = SQ_SEL_Z; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_X; /* B */ pix_a = SQ_SEL_W; /* A */ break; case PICT_a8b8g8r8: pix_r = SQ_SEL_X; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_Z; /* B */ pix_a = SQ_SEL_W; /* A */ break; case PICT_x8b8g8r8: pix_r = SQ_SEL_X; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_Z; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_b8g8r8a8: pix_r = SQ_SEL_Y; /* R */ pix_g = SQ_SEL_Z; /* G */ pix_b = SQ_SEL_W; /* B */ pix_a = SQ_SEL_X; /* A */ break; case PICT_b8g8r8x8: pix_r = SQ_SEL_Y; /* R */ pix_g = SQ_SEL_Z; /* G */ pix_b = SQ_SEL_W; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_x1r5g5b5: case PICT_x8r8g8b8: case PICT_r5g6b5: pix_r = SQ_SEL_Z; /* R */ pix_g = SQ_SEL_Y; /* G */ pix_b = SQ_SEL_X; /* B */ pix_a = SQ_SEL_1; /* A */ break; case PICT_a8: pix_r = SQ_SEL_0; /* R */ pix_g = SQ_SEL_0; /* G */ pix_b = SQ_SEL_0; /* B */ pix_a = SQ_SEL_X; /* A */ break; default: RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format)); } if (unit == 0) { if (!accel_state->msk_pic) { if (PICT_FORMAT_RGB(pPict->format) == 0) { pix_r = SQ_SEL_0; pix_g = SQ_SEL_0; pix_b = SQ_SEL_0; } if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } else { if (accel_state->component_alpha) { if (accel_state->src_alpha) { if (PICT_FORMAT_A(pPict->format) == 0) { pix_r = SQ_SEL_1; pix_g = SQ_SEL_1; pix_b = SQ_SEL_1; pix_a = SQ_SEL_1; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } else { if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } } else { if (PICT_FORMAT_RGB(pPict->format) == 0) { pix_r = SQ_SEL_0; pix_g = SQ_SEL_0; pix_b = SQ_SEL_0; } if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } } } else { if (accel_state->component_alpha) { if (PICT_FORMAT_A(pPict->format) == 0) pix_a = SQ_SEL_1; } else { if (PICT_FORMAT_A(pPict->format) == 0) { pix_r = SQ_SEL_1; pix_g = SQ_SEL_1; pix_b = SQ_SEL_1; pix_a = SQ_SEL_1; } else { pix_r = pix_a; pix_g = pix_a; pix_b = pix_a; } } } tex_res.dst_sel_x = pix_r; /* R */ tex_res.dst_sel_y = pix_g; /* G */ tex_res.dst_sel_z = pix_b; /* B */ tex_res.dst_sel_w = pix_a; /* A */ tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; if (accel_state->src_obj[unit].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK; switch (repeatType) { case RepeatNormal: tex_samp.clamp_x = SQ_TEX_WRAP; tex_samp.clamp_y = SQ_TEX_WRAP; break; case RepeatPad: tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; break; case RepeatReflect: tex_samp.clamp_x = SQ_TEX_MIRROR; tex_samp.clamp_y = SQ_TEX_MIRROR; break; case RepeatNone: tex_samp.clamp_x = SQ_TEX_CLAMP_BORDER; tex_samp.clamp_y = SQ_TEX_CLAMP_BORDER; break; default: RADEON_FALLBACK(("Bad repeat 0x%x\n", repeatType)); } switch (pPict->filter) { case PictFilterNearest: tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.mc_coord_truncate = 1; break; case PictFilterBilinear: tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; break; default: RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ r600_set_tex_sampler(pScrn, &tex_samp); if (pPict->transform != 0) { accel_state->is_transform[unit] = TRUE; accel_state->transform[unit] = pPict->transform; vs_alu_consts[0] = xFixedToFloat(pPict->transform->matrix[0][0]); vs_alu_consts[1] = xFixedToFloat(pPict->transform->matrix[0][1]); vs_alu_consts[2] = xFixedToFloat(pPict->transform->matrix[0][2]); vs_alu_consts[3] = 1.0 / tex_res.w; vs_alu_consts[4] = xFixedToFloat(pPict->transform->matrix[1][0]); vs_alu_consts[5] = xFixedToFloat(pPict->transform->matrix[1][1]); vs_alu_consts[6] = xFixedToFloat(pPict->transform->matrix[1][2]); vs_alu_consts[7] = 1.0 / tex_res.h; } else { accel_state->is_transform[unit] = FALSE; vs_alu_consts[0] = 1.0; vs_alu_consts[1] = 0.0; vs_alu_consts[2] = 0.0; vs_alu_consts[3] = 1.0 / tex_res.w; vs_alu_consts[4] = 0.0; vs_alu_consts[5] = 1.0; vs_alu_consts[6] = 0.0; vs_alu_consts[7] = 1.0 / tex_res.h; } /* VS alu constants */ r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs + (unit * 2), sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); return TRUE; } static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { uint32_t tmp1; PixmapPtr pSrcPixmap, pDstPixmap; /* Check for unsupported compositing operations. */ if (op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0]))) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); if (pSrcPicture->pDrawable) { pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); if (pSrcPixmap->drawable.width >= 8192 || pSrcPixmap->drawable.height >= 8192) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); } if (!R600CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0)) return FALSE; } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); if (pDstPixmap->drawable.width >= 8192 || pDstPixmap->drawable.height >= 8192) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); } if (pMaskPicture) { PixmapPtr pMaskPixmap; if (pMaskPicture->pDrawable) { pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); if (pMaskPixmap->drawable.width >= 8192 || pMaskPixmap->drawable.height >= 8192) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); } if (pMaskPicture->componentAlpha) { /* Check if it's component alpha that relies on a source alpha and * on the source value. We can only get one of those into the * single source value that we get to blend with. */ if (R600BlendOp[op].src_alpha && (R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) != (BLEND_ZERO << COLOR_SRCBLEND_shift)) { RADEON_FALLBACK(("Component alpha not supported with source " "alpha and source value blending.\n")); } } if (!R600CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1)) return FALSE; } else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); } if (!R600GetDestFormat(pDstPicture, &tmp1)) return FALSE; return TRUE; } static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t dst_format; cb_config_t cb_conf; shader_config_t vs_conf, ps_conf; struct r600_accel_object src_obj, mask_obj, dst_obj; if (pDst->drawable.bitsPerPixel < 8 || (pSrc && pSrc->drawable.bitsPerPixel < 8)) return FALSE; if (!pSrc) { pSrc = RADEONSolidPixmap(pScreen, pSrcPicture->pSourcePict->solidFill.color); if (!pSrc) RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } dst_obj.bo = radeon_get_pixmap_bo(pDst); src_obj.bo = radeon_get_pixmap_bo(pSrc); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); dst_obj.surface = radeon_get_pixmap_surface(pDst); src_obj.surface = radeon_get_pixmap_surface(pSrc); src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = pSrc->drawable.bitsPerPixel; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = pDst->drawable.bitsPerPixel; if (radeon_get_pixmap_shared(pDst) == TRUE) dst_obj.domain = RADEON_GEM_DOMAIN_GTT; else dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (pMaskPicture) { if (!pMask) { pMask = RADEONSolidPixmap(pScreen, pMaskPicture->pSourcePict->solidFill.color); if (!pMask) { if (!pSrcPicture->pDrawable) pScreen->DestroyPixmap(pSrc); RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } } mask_obj.bo = radeon_get_pixmap_bo(pMask); mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); mask_obj.surface = radeon_get_pixmap_surface(pMask); mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8); mask_obj.width = pMask->drawable.width; mask_obj.height = pMask->drawable.height; mask_obj.bpp = pMask->drawable.bitsPerPixel; mask_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; if (!R600SetAccelState(pScrn, &src_obj, &mask_obj, &dst_obj, accel_state->comp_vs_offset, accel_state->comp_ps_offset, 3, 0xffffffff)) return FALSE; accel_state->msk_pic = pMaskPicture; if (pMaskPicture->componentAlpha) { accel_state->component_alpha = TRUE; if (R600BlendOp[op].src_alpha) accel_state->src_alpha = TRUE; else accel_state->src_alpha = FALSE; } else { accel_state->component_alpha = FALSE; accel_state->src_alpha = FALSE; } } else { if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->comp_vs_offset, accel_state->comp_ps_offset, 3, 0xffffffff)) return FALSE; accel_state->msk_pic = NULL; accel_state->component_alpha = FALSE; accel_state->src_alpha = FALSE; } if (!R600GetDestFormat(pDstPicture, &dst_format)) return FALSE; CLEAR (cb_conf); CLEAR (vs_conf); CLEAR (ps_conf); if (pMask) radeon_vbo_check(pScrn, &accel_state->vbo, 24); else radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); r600_set_default_state(pScrn); r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); if (!R600TextureSetup(pSrcPicture, pSrc, 0)) { R600IBDiscard(pScrn); return FALSE; } if (pMask) { if (!R600TextureSetup(pMaskPicture, pMask, 1)) { R600IBDiscard(pScrn); return FALSE; } } else accel_state->is_transform[1] = FALSE; if (pMask) { r600_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (1 << 0)); r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); } else { r600_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (0 << 0)); r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); } /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 5; vs_conf.stack_size = 1; vs_conf.bo = accel_state->shaders_bo; r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 3; ps_conf.stack_size = 1; ps_conf.uncached_first_inst = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.format = dst_format; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: case PICT_a1r5g5b5: case PICT_x1r5g5b5: default: cb_conf.comp_swap = 1; /* ARGB */ break; case PICT_a8b8g8r8: case PICT_x8b8g8r8: cb_conf.comp_swap = 0; /* ABGR */ break; case PICT_b8g8r8a8: case PICT_b8g8r8x8: cb_conf.comp_swap = 3; /* BGRA */ break; case PICT_r5g6b5: cb_conf.comp_swap = 2; /* RGB */ break; case PICT_a8: cb_conf.comp_swap = 3; /* A */ break; } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; cb_conf.blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format); cb_conf.blend_enable = 1; cb_conf.pmask = 0xf; cb_conf.rop = 3; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 0; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (dst_obj.bpp) { case 16: cb_conf.endian = ENDIAN_8IN16; break; case 32: cb_conf.endian = ENDIAN_8IN32; break; default: break; } #endif r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); if (pMask) r600_set_spi(pScrn, (2 - 1), 2); else r600_set_spi(pScrn, (1 - 1), 1); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); accel_state->composite_op = op; accel_state->dst_pic = pDstPicture; accel_state->src_pic = pSrcPicture; accel_state->dst_pix = pDst; accel_state->msk_pix = pMask; accel_state->src_pix = pSrc; return TRUE; } static void R600FinishComposite(ScrnInfoPtr pScrn, PixmapPtr pDst, struct radeon_accel_state *accel_state) { int vtx_size; if (accel_state->vsync) r600_cp_wait_vline_sync(pScrn, pDst, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); vtx_size = accel_state->msk_pic ? 24 : 16; r600_finish_op(pScrn, vtx_size); } static void R600DoneComposite(PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; R600FinishComposite(pScrn, pDst, accel_state); if (!accel_state->src_pic->pDrawable) pScreen->DestroyPixmap(accel_state->src_pix); if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable) pScreen->DestroyPixmap(accel_state->msk_pix); } static void R600Composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; float *vb; /* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ if (CS_FULL(info->cs)) { R600FinishComposite(pScrn, pDst, info->accel_state); radeon_cs_flush_indirect(pScrn); R600PrepareComposite(info->accel_state->composite_op, info->accel_state->src_pic, info->accel_state->msk_pic, info->accel_state->dst_pic, info->accel_state->src_pix, info->accel_state->msk_pix, info->accel_state->dst_pix); } if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); if (accel_state->msk_pic) { vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)maskX; vb[5] = (float)maskY; vb[6] = (float)dstX; vb[7] = (float)(dstY + h); vb[8] = (float)srcX; vb[9] = (float)(srcY + h); vb[10] = (float)maskX; vb[11] = (float)(maskY + h); vb[12] = (float)(dstX + w); vb[13] = (float)(dstY + h); vb[14] = (float)(srcX + w); vb[15] = (float)(srcY + h); vb[16] = (float)(maskX + w); vb[17] = (float)(maskY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } else { vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + h); vb[6] = (float)srcX; vb[7] = (float)(srcY + h); vb[8] = (float)(dstX + w); vb[9] = (float)(dstY + h); vb[10] = (float)(srcX + w); vb[11] = (float)(srcY + h); radeon_vbo_commit(pScrn, &accel_state->vbo); } } static Bool R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_dst; unsigned char *dst; unsigned size; uint32_t dst_domain; int bpp = pDst->drawable.bitsPerPixel; uint32_t scratch_pitch; uint32_t copy_pitch; uint32_t dst_pitch_hw = exaGetPixmapPitch(pDst) / (bpp / 8); int ret; Bool flush = TRUE; Bool r; int i; struct r600_accel_object src_obj, dst_obj; uint32_t height, base_align; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pDst); if (!driver_priv || !driver_priv->bo) return FALSE; /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ copy_dst = driver_priv->bo; copy_pitch = pDst->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { flush = FALSE; if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) && !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) goto copy; } /* use cpu copy for fast fb access */ if (info->is_fast_fb) goto copy; } scratch_pitch = RADEON_ALIGN(w, drmmode_get_pitch_align(pScrn, (bpp / 8), 0)); height = RADEON_ALIGN(h, drmmode_get_height_align(pScrn, 0)); base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); size = scratch_pitch * height * (bpp / 8); scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } src_obj.pitch = scratch_pitch; src_obj.width = w; src_obj.height = h; src_obj.bpp = bpp; src_obj.domain = RADEON_GEM_DOMAIN_GTT; src_obj.bo = scratch; src_obj.tiling_flags = 0; src_obj.surface = NULL; dst_obj.pitch = dst_pitch_hw; dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = bpp; dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); dst_obj.surface = radeon_get_pixmap_surface(pDst); if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, 3, 0xffffffff)) { goto copy; } copy_dst = scratch; copy_pitch = scratch_pitch * (bpp / 8); flush = FALSE; copy: if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_dst, 0); if (ret) { r = FALSE; goto out; } r = TRUE; size = w * bpp / 8; dst = copy_dst->ptr; if (copy_dst == driver_priv->bo) dst += y * copy_pitch + x * bpp / 8; for (i = 0; i < h; i++) { memcpy(dst + i * copy_pitch, src, size); src += src_pitch; } radeon_bo_unmap(copy_dst); if (copy_dst == scratch) { if (info->accel_state->vsync) RADEONVlineHelperSet(pScrn, x, y, x + w, y + h); /* blit from gart to vram */ R600DoPrepareCopy(pScrn); R600AppendCopyVertex(pScrn, 0, 0, x, y, w, h); R600DoCopyVline(pDst); } out: if (scratch) radeon_bo_unref(scratch); return r; } static Bool R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, int h, char *dst, int dst_pitch) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pSrc->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_src; unsigned size; uint32_t src_domain = 0; int bpp = pSrc->drawable.bitsPerPixel; uint32_t scratch_pitch; uint32_t copy_pitch; uint32_t src_pitch_hw = exaGetPixmapPitch(pSrc) / (bpp / 8); int ret; Bool flush = FALSE; Bool r; struct r600_accel_object src_obj, dst_obj; uint32_t height, base_align; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pSrc); if (!driver_priv || !driver_priv->bo) return FALSE; /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ copy_src = driver_priv->bo; copy_pitch = pSrc->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { src_domain = radeon_bo_get_src_domain(driver_priv->bo); if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) src_domain = 0; else /* A write may be scheduled */ flush = TRUE; } if (!src_domain) radeon_bo_is_busy(driver_priv->bo, &src_domain); if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) goto copy; } scratch_pitch = RADEON_ALIGN(w, drmmode_get_pitch_align(pScrn, (bpp / 8), 0)); height = RADEON_ALIGN(h, drmmode_get_height_align(pScrn, 0)); base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); size = scratch_pitch * height * (bpp / 8); scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0); accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT; radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain); ret = radeon_cs_space_check(info->cs); if (ret) { goto copy; } src_obj.pitch = src_pitch_hw; src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; src_obj.bpp = bpp; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = radeon_get_pixmap_bo(pSrc); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); src_obj.surface = radeon_get_pixmap_surface(pSrc); dst_obj.pitch = scratch_pitch; dst_obj.width = w; dst_obj.height = h; dst_obj.bo = scratch; dst_obj.bpp = bpp; dst_obj.domain = RADEON_GEM_DOMAIN_GTT; dst_obj.tiling_flags = 0; dst_obj.surface = NULL; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->copy_vs_offset, accel_state->copy_ps_offset, 3, 0xffffffff)) { goto copy; } /* blit from vram to gart */ R600DoPrepareCopy(pScrn); R600AppendCopyVertex(pScrn, x, y, 0, 0, w, h); R600DoCopy(pScrn); copy_src = scratch; copy_pitch = scratch_pitch * (bpp / 8); flush = TRUE; copy: if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_src, 0); if (ret) { ErrorF("failed to map pixmap: %d\n", ret); r = FALSE; goto out; } r = TRUE; w *= bpp / 8; if (copy_src == driver_priv->bo) size = y * copy_pitch + x * bpp / 8; else size = 0; while (h--) { memcpy(dst, copy_src->ptr + size, w); size += copy_pitch; dst += dst_pitch; } radeon_bo_unmap(copy_src); out: if (scratch) radeon_bo_unref(scratch); return r; } static int R600MarkSync(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; return ++accel_state->exaSyncMarker; } static void R600Sync(ScreenPtr pScreen, int marker) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->exaMarkerSynced != marker) { accel_state->exaMarkerSynced = marker; } } static Bool R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; /* 512 bytes per shader for now */ int size = 512 * 9; accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->shaders_bo == NULL) { ErrorF("Allocating shader failed\n"); return FALSE; } return TRUE; } Bool R600LoadShaders(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; RADEONChipFamily ChipSet = info->ChipFamily; uint32_t *shader; int ret; ret = radeon_bo_map(accel_state->shaders_bo, 1); if (ret) { FatalError("failed to map shader %d\n", ret); return FALSE; } shader = accel_state->shaders_bo->ptr; /* solid vs --------------------------------------- */ accel_state->solid_vs_offset = 0; R600_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4); /* solid ps --------------------------------------- */ accel_state->solid_ps_offset = 512; R600_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4); /* copy vs --------------------------------------- */ accel_state->copy_vs_offset = 1024; R600_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4); /* copy ps --------------------------------------- */ accel_state->copy_ps_offset = 1536; R600_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4); /* comp vs --------------------------------------- */ accel_state->comp_vs_offset = 2048; R600_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4); /* comp ps --------------------------------------- */ accel_state->comp_ps_offset = 2560; R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); /* xv vs --------------------------------------- */ accel_state->xv_vs_offset = 3072; R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4); /* xv ps --------------------------------------- */ accel_state->xv_ps_offset = 3584; R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); radeon_bo_unmap(accel_state->shaders_bo); return TRUE; } Bool R600DrawInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); if (info->accel_state->exa == NULL) { xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); return FALSE; } info->accel_state->exa->exa_major = EXA_VERSION_MAJOR; info->accel_state->exa->exa_minor = EXA_VERSION_MINOR; info->accel_state->exa->PrepareSolid = R600PrepareSolid; info->accel_state->exa->Solid = R600Solid; info->accel_state->exa->DoneSolid = R600DoneSolid; info->accel_state->exa->PrepareCopy = R600PrepareCopy; info->accel_state->exa->Copy = R600Copy; info->accel_state->exa->DoneCopy = R600DoneCopy; info->accel_state->exa->MarkSync = R600MarkSync; info->accel_state->exa->WaitMarker = R600Sync; info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; info->accel_state->exa->UploadToScreen = R600UploadToScreenCS; info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS; info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 6) info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking; info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking; #endif info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX | EXA_HANDLES_PIXMAPS | EXA_MIXED_PIXMAPS; info->accel_state->exa->pixmapOffsetAlign = 256; info->accel_state->exa->pixmapPitchAlign = 256; info->accel_state->exa->CheckComposite = R600CheckComposite; info->accel_state->exa->PrepareComposite = R600PrepareComposite; info->accel_state->exa->Composite = R600Composite; info->accel_state->exa->DoneComposite = R600DoneComposite; info->accel_state->exa->maxPitchBytes = 32768; info->accel_state->exa->maxX = 8192; info->accel_state->exa->maxY = 8192; /* not supported yet */ if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n"); info->accel_state->vsync = TRUE; } else info->accel_state->vsync = FALSE; if (!exaDriverInit(pScreen, info->accel_state->exa)) { free(info->accel_state->exa); return FALSE; } info->accel_state->XInited3D = FALSE; info->accel_state->src_obj[0].bo = NULL; info->accel_state->src_obj[1].bo = NULL; info->accel_state->dst_obj.bo = NULL; info->accel_state->copy_area_bo = NULL; info->accel_state->vbo.vb_start_op = -1; info->accel_state->finish_op = r600_finish_op; info->accel_state->vbo.verts_per_op = 3; RADEONVlineHelperClear(pScrn); radeon_vbo_init_lists(pScrn); if (!R600AllocShaders(pScrn, pScreen)) return FALSE; if (!R600LoadShaders(pScrn)) return FALSE; exaMarkSync(pScreen); return TRUE; } xserver-xorg-video-ati-7.5.0+git20150819/src/r600_reg.h000066400000000000000000000115621256524674500217770ustar00rootroot00000000000000/* * RadeonHD R6xx, R7xx Register documentation * * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. * Copyright (C) 2008-2009 Matthias Hopf * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _R600_REG_H_ #define _R600_REG_H_ /* * Register definitions */ #include "r600_reg_auto_r6xx.h" #include "r600_reg_r6xx.h" #include "r600_reg_r7xx.h" /* SET_*_REG offsets + ends */ #define SET_CONFIG_REG_offset 0x00008000 #define SET_CONFIG_REG_end 0x0000ac00 #define SET_CONTEXT_REG_offset 0x00028000 #define SET_CONTEXT_REG_end 0x00029000 #define SET_ALU_CONST_offset 0x00030000 #define SET_ALU_CONST_end 0x00032000 #define SET_RESOURCE_offset 0x00038000 #define SET_RESOURCE_end 0x0003c000 #define SET_SAMPLER_offset 0x0003c000 #define SET_SAMPLER_end 0x0003cff0 #define SET_CTL_CONST_offset 0x0003cff0 #define SET_CTL_CONST_end 0x0003e200 #define SET_LOOP_CONST_offset 0x0003e200 #define SET_LOOP_CONST_end 0x0003e380 #define SET_BOOL_CONST_offset 0x0003e380 #define SET_BOOL_CONST_end 0x0003e38c /* packet3 IT_SURFACE_BASE_UPDATE bits */ enum { DEPTH_BASE = (1 << 0), COLOR0_BASE = (1 << 1), COLOR1_BASE = (1 << 2), COLOR2_BASE = (1 << 3), COLOR3_BASE = (1 << 4), COLOR4_BASE = (1 << 5), COLOR5_BASE = (1 << 6), COLOR6_BASE = (1 << 7), COLOR7_BASE = (1 << 8), STRMOUT_BASE0 = (1 << 9), STRMOUT_BASE1 = (1 << 10), STRMOUT_BASE2 = (1 << 11), STRMOUT_BASE3 = (1 << 12), COHER_BASE0 = (1 << 13), COHER_BASE1 = (1 << 14), }; /* Packet3 commands */ enum { IT_NOP = 0x10, IT_INDIRECT_BUFFER_END = 0x17, IT_SET_PREDICATION = 0x20, IT_REG_RMW = 0x21, IT_COND_EXEC = 0x22, IT_PRED_EXEC = 0x23, IT_START_3D_CMDBUF = 0x24, IT_DRAW_INDEX_2 = 0x27, IT_CONTEXT_CONTROL = 0x28, IT_DRAW_INDEX_IMMD_BE = 0x29, IT_INDEX_TYPE = 0x2A, IT_DRAW_INDEX = 0x2B, IT_DRAW_INDEX_AUTO = 0x2D, IT_DRAW_INDEX_IMMD = 0x2E, IT_NUM_INSTANCES = 0x2F, IT_STRMOUT_BUFFER_UPDATE = 0x34, IT_INDIRECT_BUFFER_MP = 0x38, IT_MEM_SEMAPHORE = 0x39, IT_MPEG_INDEX = 0x3A, IT_WAIT_REG_MEM = 0x3C, IT_MEM_WRITE = 0x3D, IT_INDIRECT_BUFFER = 0x32, IT_CP_INTERRUPT = 0x40, IT_SURFACE_SYNC = 0x43, IT_ME_INITIALIZE = 0x44, IT_COND_WRITE = 0x45, IT_EVENT_WRITE = 0x46, IT_EVENT_WRITE_EOP = 0x47, IT_ONE_REG_WRITE = 0x57, IT_SET_CONFIG_REG = 0x68, IT_SET_CONTEXT_REG = 0x69, IT_SET_ALU_CONST = 0x6A, IT_SET_BOOL_CONST = 0x6B, IT_SET_LOOP_CONST = 0x6C, IT_SET_RESOURCE = 0x6D, IT_SET_SAMPLER = 0x6E, IT_SET_CTL_CONST = 0x6F, IT_SURFACE_BASE_UPDATE = 0x73, } ; /* IT_WAIT_REG_MEM operation encoding */ #define IT_WAIT_ALWAYS (0 << 0) #define IT_WAIT_LT (1 << 0) #define IT_WAIT_LE (2 << 0) #define IT_WAIT_EQ (3 << 0) #define IT_WAIT_NE (4 << 0) #define IT_WAIT_GE (5 << 0) #define IT_WAIT_GT (6 << 0) #define IT_WAIT_REG (0 << 4) #define IT_WAIT_MEM (1 << 4) #define IT_WAIT_ADDR(x) ((x) >> 2) /* IT_INDEX_TYPE */ #define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2) #endif xserver-xorg-video-ati-7.5.0+git20150819/src/r600_reg_auto_r6xx.h000066400000000000000000005711321256524674500240220ustar00rootroot00000000000000/* * RadeonHD R6xx, R7xx Register documentation * * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. * Copyright (C) 2008-2009 Matthias Hopf * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _AUTOREGS #define _AUTOREGS enum { VGT_VTX_VECT_EJECT_REG = 0x000088b0, PRIM_COUNT_mask = 0x3ff << 0, PRIM_COUNT_shift = 0, VGT_LAST_COPY_STATE = 0x000088c0, SRC_STATE_ID_mask = 0x07 << 0, SRC_STATE_ID_shift = 0, DST_STATE_ID_mask = 0x07 << 16, DST_STATE_ID_shift = 16, VGT_CACHE_INVALIDATION = 0x000088c4, CACHE_INVALIDATION_mask = 0x03 << 0, CACHE_INVALIDATION_shift = 0, VC_ONLY = 0x00, TC_ONLY = 0x01, VC_AND_TC = 0x02, VS_NO_EXTRA_BUFFER_bit = 1 << 5, VGT_GS_PER_ES = 0x000088c8, VGT_ES_PER_GS = 0x000088cc, VGT_GS_VERTEX_REUSE = 0x000088d4, VERT_REUSE_mask = 0x1f << 0, VERT_REUSE_shift = 0, VGT_MC_LAT_CNTL = 0x000088d8, MC_TIME_STAMP_RES_mask = 0x03 << 0, MC_TIME_STAMP_RES_shift = 0, X_0_992_MAX_LATENCY = 0x00, X_0_496_MAX_LATENCY = 0x01, X_0_248_MAX_LATENCY = 0x02, X_0_124_MAX_LATENCY = 0x03, VGT_GS_PER_VS = 0x000088e8, GS_PER_VS_mask = 0x0f << 0, GS_PER_VS_shift = 0, VGT_CNTL_STATUS = 0x000088f0, VGT_OUT_INDX_BUSY_bit = 1 << 0, VGT_OUT_BUSY_bit = 1 << 1, VGT_PT_BUSY_bit = 1 << 2, VGT_TE_BUSY_bit = 1 << 3, VGT_VR_BUSY_bit = 1 << 4, VGT_GRP_BUSY_bit = 1 << 5, VGT_DMA_REQ_BUSY_bit = 1 << 6, VGT_DMA_BUSY_bit = 1 << 7, VGT_GS_BUSY_bit = 1 << 8, VGT_BUSY_bit = 1 << 9, VGT_PRIMITIVE_TYPE = 0x00008958, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, DI_PT_NONE = 0x00, DI_PT_POINTLIST = 0x01, DI_PT_LINELIST = 0x02, DI_PT_LINESTRIP = 0x03, DI_PT_TRILIST = 0x04, DI_PT_TRIFAN = 0x05, DI_PT_TRISTRIP = 0x06, DI_PT_UNUSED_0 = 0x07, DI_PT_UNUSED_1 = 0x08, DI_PT_UNUSED_2 = 0x09, DI_PT_LINELIST_ADJ = 0x0a, DI_PT_LINESTRIP_ADJ = 0x0b, DI_PT_TRILIST_ADJ = 0x0c, DI_PT_TRISTRIP_ADJ = 0x0d, DI_PT_UNUSED_3 = 0x0e, DI_PT_UNUSED_4 = 0x0f, DI_PT_TRI_WITH_WFLAGS = 0x10, DI_PT_RECTLIST = 0x11, DI_PT_LINELOOP = 0x12, DI_PT_QUADLIST = 0x13, DI_PT_QUADSTRIP = 0x14, DI_PT_POLYGON = 0x15, DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, DI_PT_2D_FILL_RECT_LIST = 0x1a, DI_PT_2D_LINE_STRIP = 0x1b, DI_PT_2D_TRI_STRIP = 0x1c, VGT_INDEX_TYPE = 0x0000895c, INDEX_TYPE_mask = 0x03 << 0, INDEX_TYPE_shift = 0, DI_INDEX_SIZE_16_BIT = 0x00, DI_INDEX_SIZE_32_BIT = 0x01, VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, VGT_NUM_INDICES = 0x00008970, VGT_NUM_INSTANCES = 0x00008974, PA_CL_CNTL_STATUS = 0x00008a10, CL_BUSY_bit = 1 << 31, PA_CL_ENHANCE = 0x00008a14, CLIP_VTX_REORDER_ENA_bit = 1 << 0, NUM_CLIP_SEQ_mask = 0x03 << 1, NUM_CLIP_SEQ_shift = 1, CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, VE_NAN_PROC_DISABLE_bit = 1 << 4, PA_SU_CNTL_STATUS = 0x00008a50, SU_BUSY_bit = 1 << 31, PA_SC_LINE_STIPPLE_STATE = 0x00008b10, CURRENT_PTR_mask = 0x0f << 0, CURRENT_PTR_shift = 0, CURRENT_COUNT_mask = 0xff << 8, CURRENT_COUNT_shift = 8, PA_SC_MULTI_CHIP_CNTL = 0x00008b20, LOG2_NUM_CHIPS_mask = 0x07 << 0, LOG2_NUM_CHIPS_shift = 0, MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3, MULTI_CHIP_TILE_SIZE_shift = 3, X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00, X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01, X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02, X_128X128_PIXEL_TILE_PER_CHIP = 0x03, CHIP_TILE_X_LOC_mask = 0x07 << 5, CHIP_TILE_X_LOC_shift = 5, CHIP_TILE_Y_LOC_mask = 0x07 << 8, CHIP_TILE_Y_LOC_shift = 8, CHIP_SUPER_TILE_B_bit = 1 << 11, PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40, S0_X_mask = 0x0f << 0, S0_X_shift = 0, S0_Y_mask = 0x0f << 4, S0_Y_shift = 4, S1_X_mask = 0x0f << 8, S1_X_shift = 8, S1_Y_mask = 0x0f << 12, S1_Y_shift = 12, PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ S2_X_mask = 0x0f << 16, S2_X_shift = 16, S2_Y_mask = 0x0f << 20, S2_Y_shift = 20, S3_X_mask = 0x0f << 24, S3_X_shift = 24, S3_Y_mask = 0x0f << 28, S3_Y_shift = 28, PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c, S4_X_mask = 0x0f << 0, S4_X_shift = 0, S4_Y_mask = 0x0f << 4, S4_Y_shift = 4, S5_X_mask = 0x0f << 8, S5_X_shift = 8, S5_Y_mask = 0x0f << 12, S5_Y_shift = 12, S6_X_mask = 0x0f << 16, S6_X_shift = 16, S6_Y_mask = 0x0f << 20, S6_Y_shift = 20, S7_X_mask = 0x0f << 24, S7_X_shift = 24, S7_Y_mask = 0x0f << 28, S7_Y_shift = 28, PA_SC_CNTL_STATUS = 0x00008be0, MPASS_OVERFLOW_bit = 1 << 30, PA_SC_ENHANCE = 0x00008bf0, FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0, FORCE_EOV_MAX_CLK_CNT_shift = 0, FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12, FORCE_EOV_MAX_TILE_CNT_shift = 12, SQ_CONFIG = 0x00008c00, VC_ENABLE_bit = 1 << 0, EXPORT_SRC_C_bit = 1 << 1, DX9_CONSTS_bit = 1 << 2, ALU_INST_PREFER_VECTOR_bit = 1 << 3, SQ_CONFIG__DX10_CLAMP_bit = 1 << 4, ALU_PREFER_ONE_WATERFALL_bit = 1 << 5, ALU_MAX_ONE_WATERFALL_bit = 1 << 6, CLAUSE_SEQ_PRIO_mask = 0x03 << 8, CLAUSE_SEQ_PRIO_shift = 8, SQ_CL_PRIO_RND_ROBIN = 0x00, SQ_CL_PRIO_MACRO_SEQ = 0x01, SQ_CL_PRIO_NONE = 0x02, PS_PRIO_mask = 0x03 << 24, PS_PRIO_shift = 24, VS_PRIO_mask = 0x03 << 26, VS_PRIO_shift = 26, GS_PRIO_mask = 0x03 << 28, GS_PRIO_shift = 28, ES_PRIO_mask = 0x03 << 30, ES_PRIO_shift = 30, SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, NUM_PS_GPRS_mask = 0xff << 0, NUM_PS_GPRS_shift = 0, NUM_VS_GPRS_mask = 0xff << 16, NUM_VS_GPRS_shift = 16, NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, NUM_CLAUSE_TEMP_GPRS_shift = 28, SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08, NUM_GS_GPRS_mask = 0xff << 0, NUM_GS_GPRS_shift = 0, NUM_ES_GPRS_mask = 0xff << 16, NUM_ES_GPRS_shift = 16, SQ_THREAD_RESOURCE_MGMT = 0x00008c0c, NUM_PS_THREADS_mask = 0xff << 0, NUM_PS_THREADS_shift = 0, NUM_VS_THREADS_mask = 0xff << 8, NUM_VS_THREADS_shift = 8, NUM_GS_THREADS_mask = 0xff << 16, NUM_GS_THREADS_shift = 16, NUM_ES_THREADS_mask = 0xff << 24, NUM_ES_THREADS_shift = 24, SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10, NUM_PS_STACK_ENTRIES_mask = 0xfff << 0, NUM_PS_STACK_ENTRIES_shift = 0, NUM_VS_STACK_ENTRIES_mask = 0xfff << 16, NUM_VS_STACK_ENTRIES_shift = 16, SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14, NUM_GS_STACK_ENTRIES_mask = 0xfff << 0, NUM_GS_STACK_ENTRIES_shift = 0, NUM_ES_STACK_ENTRIES_mask = 0xfff << 16, NUM_ES_STACK_ENTRIES_shift = 16, SQ_ESGS_RING_BASE = 0x00008c40, SQ_ESGS_RING_SIZE = 0x00008c44, SQ_GSVS_RING_BASE = 0x00008c48, SQ_GSVS_RING_SIZE = 0x00008c4c, SQ_ESTMP_RING_BASE = 0x00008c50, SQ_ESTMP_RING_SIZE = 0x00008c54, SQ_GSTMP_RING_BASE = 0x00008c58, SQ_GSTMP_RING_SIZE = 0x00008c5c, SQ_VSTMP_RING_BASE = 0x00008c60, SQ_VSTMP_RING_SIZE = 0x00008c64, SQ_PSTMP_RING_BASE = 0x00008c68, SQ_PSTMP_RING_SIZE = 0x00008c6c, SQ_FBUF_RING_BASE = 0x00008c70, SQ_FBUF_RING_SIZE = 0x00008c74, SQ_REDUC_RING_BASE = 0x00008c78, SQ_REDUC_RING_SIZE = 0x00008c7c, SQ_ALU_WORD1_OP3 = 0x00008dfc, SRC2_SEL_mask = 0x1ff << 0, SRC2_SEL_shift = 0, SQ_ALU_SRC_0 = 0xf8, SQ_ALU_SRC_1 = 0xf9, SQ_ALU_SRC_1_INT = 0xfa, SQ_ALU_SRC_M_1_INT = 0xfb, SQ_ALU_SRC_0_5 = 0xfc, SQ_ALU_SRC_LITERAL = 0xfd, SQ_ALU_SRC_PV = 0xfe, SQ_ALU_SRC_PS = 0xff, SRC2_REL_bit = 1 << 9, SRC2_CHAN_mask = 0x03 << 10, SRC2_CHAN_shift = 10, SQ_CHAN_X = 0x00, SQ_CHAN_Y = 0x01, SQ_CHAN_Z = 0x02, SQ_CHAN_W = 0x03, SRC2_NEG_bit = 1 << 12, SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, SQ_OP3_INST_MUL_LIT = 0x0c, SQ_OP3_INST_MUL_LIT_M2 = 0x0d, SQ_OP3_INST_MUL_LIT_M4 = 0x0e, SQ_OP3_INST_MUL_LIT_D2 = 0x0f, SQ_OP3_INST_MULADD = 0x10, SQ_OP3_INST_MULADD_M2 = 0x11, SQ_OP3_INST_MULADD_M4 = 0x12, SQ_OP3_INST_MULADD_D2 = 0x13, SQ_OP3_INST_MULADD_IEEE = 0x14, SQ_OP3_INST_MULADD_IEEE_M2 = 0x15, SQ_OP3_INST_MULADD_IEEE_M4 = 0x16, SQ_OP3_INST_MULADD_IEEE_D2 = 0x17, SQ_OP3_INST_CNDE = 0x18, SQ_OP3_INST_CNDGT = 0x19, SQ_OP3_INST_CNDGE = 0x1a, SQ_OP3_INST_CNDE_INT = 0x1c, SQ_OP3_INST_CNDGT_INT = 0x1d, SQ_OP3_INST_CNDGE_INT = 0x1e, SQ_TEX_WORD2 = 0x00008dfc, OFFSET_X_mask = 0x1f << 0, OFFSET_X_shift = 0, OFFSET_Y_mask = 0x1f << 5, OFFSET_Y_shift = 5, OFFSET_Z_mask = 0x1f << 10, OFFSET_Z_shift = 10, SAMPLER_ID_mask = 0x1f << 15, SAMPLER_ID_shift = 15, SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, SQ_TEX_WORD2__SRC_SEL_X_shift = 20, SQ_SEL_X = 0x00, SQ_SEL_Y = 0x01, SQ_SEL_Z = 0x02, SQ_SEL_W = 0x03, SQ_SEL_0 = 0x04, SQ_SEL_1 = 0x05, SRC_SEL_Y_mask = 0x07 << 23, SRC_SEL_Y_shift = 23, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_Z_mask = 0x07 << 26, SRC_SEL_Z_shift = 26, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SRC_SEL_W_mask = 0x07 << 29, SRC_SEL_W_shift = 29, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, BURST_COUNT_mask = 0x0f << 17, BURST_COUNT_shift = 17, END_OF_PROGRAM_bit = 1 << 21, VALID_PIXEL_MODE_bit = 1 << 22, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23, SQ_CF_INST_MEM_STREAM0 = 0x20, SQ_CF_INST_MEM_STREAM1 = 0x21, SQ_CF_INST_MEM_STREAM2 = 0x22, SQ_CF_INST_MEM_STREAM3 = 0x23, SQ_CF_INST_MEM_SCRATCH = 0x24, SQ_CF_INST_MEM_REDUCTION = 0x25, SQ_CF_INST_MEM_RING = 0x26, SQ_CF_INST_EXPORT = 0x27, SQ_CF_INST_EXPORT_DONE = 0x28, WHOLE_QUAD_MODE_bit = 1 << 30, BARRIER_bit = 1 << 31, SQ_CF_ALU_WORD1 = 0x00008dfc, KCACHE_MODE1_mask = 0x03 << 0, KCACHE_MODE1_shift = 0, SQ_CF_KCACHE_NOP = 0x00, SQ_CF_KCACHE_LOCK_1 = 0x01, SQ_CF_KCACHE_LOCK_2 = 0x02, SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, KCACHE_ADDR0_mask = 0xff << 2, KCACHE_ADDR0_shift = 2, KCACHE_ADDR1_mask = 0xff << 10, KCACHE_ADDR1_shift = 10, SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, SQ_CF_ALU_WORD1__COUNT_shift = 18, SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, SQ_CF_ALU_WORD1__CF_INST_shift = 26, SQ_CF_INST_ALU = 0x08, SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, SQ_CF_INST_ALU_POP_AFTER = 0x0a, SQ_CF_INST_ALU_POP2_AFTER = 0x0b, SQ_CF_INST_ALU_CONTINUE = 0x0d, SQ_CF_INST_ALU_BREAK = 0x0e, SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, /* WHOLE_QUAD_MODE_bit = 1 << 30, */ /* BARRIER_bit = 1 << 31, */ SQ_TEX_WORD1 = 0x00008dfc, SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, SQ_TEX_WORD1__DST_GPR_shift = 0, SQ_TEX_WORD1__DST_REL_bit = 1 << 7, SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_TEX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_SEL_MASK = 0x07, SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_TEX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_TEX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_TEX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, SQ_TEX_WORD1__LOD_BIAS_shift = 21, COORD_TYPE_X_bit = 1 << 28, COORD_TYPE_Y_bit = 1 << 29, COORD_TYPE_Z_bit = 1 << 30, COORD_TYPE_W_bit = 1 << 31, SQ_VTX_WORD0 = 0x00008dfc, VTX_INST_mask = 0x1f << 0, VTX_INST_shift = 0, SQ_VTX_INST_FETCH = 0x00, SQ_VTX_INST_SEMANTIC = 0x01, FETCH_TYPE_mask = 0x03 << 5, FETCH_TYPE_shift = 5, SQ_VTX_FETCH_VERTEX_DATA = 0x00, SQ_VTX_FETCH_INSTANCE_DATA = 0x01, SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, FETCH_WHOLE_QUAD_bit = 1 << 7, BUFFER_ID_mask = 0xff << 8, BUFFER_ID_shift = 8, SRC_GPR_mask = 0x7f << 16, SRC_GPR_shift = 16, SRC_REL_bit = 1 << 23, SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, SQ_VTX_WORD0__SRC_SEL_X_shift = 24, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ MEGA_FETCH_COUNT_mask = 0x3f << 26, MEGA_FETCH_COUNT_shift = 26, SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, SEL_X_mask = 0x07 << 0, SEL_X_shift = 0, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Y_mask = 0x07 << 3, SEL_Y_shift = 3, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_Z_mask = 0x07 << 6, SEL_Z_shift = 6, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SEL_W_mask = 0x07 << 9, SEL_W_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_ALU_WORD1 = 0x00008dfc, ENCODING_mask = 0x07 << 15, ENCODING_shift = 15, BANK_SWIZZLE_mask = 0x07 << 18, BANK_SWIZZLE_shift = 18, SQ_ALU_VEC_012 = 0x00, SQ_ALU_VEC_021 = 0x01, SQ_ALU_VEC_120 = 0x02, SQ_ALU_VEC_102 = 0x03, SQ_ALU_VEC_201 = 0x04, SQ_ALU_VEC_210 = 0x05, SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, SQ_ALU_WORD1__DST_GPR_shift = 21, SQ_ALU_WORD1__DST_REL_bit = 1 << 28, DST_CHAN_mask = 0x03 << 29, DST_CHAN_shift = 29, CHAN_X = 0x00, CHAN_Y = 0x01, CHAN_Z = 0x02, CHAN_W = 0x03, SQ_ALU_WORD1__CLAMP_bit = 1 << 31, SQ_CF_ALU_WORD0 = 0x00008dfc, SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, SQ_CF_ALU_WORD0__ADDR_shift = 0, KCACHE_BANK0_mask = 0x0f << 22, KCACHE_BANK0_shift = 22, KCACHE_BANK1_mask = 0x0f << 26, KCACHE_BANK1_shift = 26, KCACHE_MODE0_mask = 0x03 << 30, KCACHE_MODE0_shift = 30, /* SQ_CF_KCACHE_NOP = 0x00, */ /* SQ_CF_KCACHE_LOCK_1 = 0x01, */ /* SQ_CF_KCACHE_LOCK_2 = 0x02, */ /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ SQ_VTX_WORD2 = 0x00008dfc, SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, SQ_VTX_WORD2__OFFSET_shift = 0, SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, SQ_ENDIAN_NONE = 0x00, SQ_ENDIAN_8IN16 = 0x01, SQ_ENDIAN_8IN32 = 0x02, CONST_BUF_NO_STRIDE_bit = 1 << 18, MEGA_FETCH_bit = 1 << 19, SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, SRC0_ABS_bit = 1 << 0, SRC1_ABS_bit = 1 << 1, UPDATE_EXECUTE_MASK_bit = 1 << 2, UPDATE_PRED_bit = 1 << 3, WRITE_MASK_bit = 1 << 4, SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5, SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5, SQ_ALU_OMOD_OFF = 0x00, SQ_ALU_OMOD_M2 = 0x01, SQ_ALU_OMOD_M4 = 0x02, SQ_ALU_OMOD_D2 = 0x03, SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, SQ_OP2_INST_ADD = 0x00, SQ_OP2_INST_MUL = 0x01, SQ_OP2_INST_MUL_IEEE = 0x02, SQ_OP2_INST_MAX = 0x03, SQ_OP2_INST_MIN = 0x04, SQ_OP2_INST_MAX_DX10 = 0x05, SQ_OP2_INST_MIN_DX10 = 0x06, SQ_OP2_INST_SETE = 0x08, SQ_OP2_INST_SETGT = 0x09, SQ_OP2_INST_SETGE = 0x0a, SQ_OP2_INST_SETNE = 0x0b, SQ_OP2_INST_SETE_DX10 = 0x0c, SQ_OP2_INST_SETGT_DX10 = 0x0d, SQ_OP2_INST_SETGE_DX10 = 0x0e, SQ_OP2_INST_SETNE_DX10 = 0x0f, SQ_OP2_INST_FRACT = 0x10, SQ_OP2_INST_TRUNC = 0x11, SQ_OP2_INST_CEIL = 0x12, SQ_OP2_INST_RNDNE = 0x13, SQ_OP2_INST_FLOOR = 0x14, SQ_OP2_INST_MOVA = 0x15, SQ_OP2_INST_MOVA_FLOOR = 0x16, SQ_OP2_INST_MOVA_INT = 0x18, SQ_OP2_INST_MOV = 0x19, SQ_OP2_INST_NOP = 0x1a, SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, SQ_OP2_INST_PRED_SETE = 0x20, SQ_OP2_INST_PRED_SETGT = 0x21, SQ_OP2_INST_PRED_SETGE = 0x22, SQ_OP2_INST_PRED_SETNE = 0x23, SQ_OP2_INST_PRED_SET_INV = 0x24, SQ_OP2_INST_PRED_SET_POP = 0x25, SQ_OP2_INST_PRED_SET_CLR = 0x26, SQ_OP2_INST_PRED_SET_RESTORE = 0x27, SQ_OP2_INST_PRED_SETE_PUSH = 0x28, SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, SQ_OP2_INST_KILLE = 0x2c, SQ_OP2_INST_KILLGT = 0x2d, SQ_OP2_INST_KILLGE = 0x2e, SQ_OP2_INST_KILLNE = 0x2f, SQ_OP2_INST_AND_INT = 0x30, SQ_OP2_INST_OR_INT = 0x31, SQ_OP2_INST_XOR_INT = 0x32, SQ_OP2_INST_NOT_INT = 0x33, SQ_OP2_INST_ADD_INT = 0x34, SQ_OP2_INST_SUB_INT = 0x35, SQ_OP2_INST_MAX_INT = 0x36, SQ_OP2_INST_MIN_INT = 0x37, SQ_OP2_INST_MAX_UINT = 0x38, SQ_OP2_INST_MIN_UINT = 0x39, SQ_OP2_INST_SETE_INT = 0x3a, SQ_OP2_INST_SETGT_INT = 0x3b, SQ_OP2_INST_SETGE_INT = 0x3c, SQ_OP2_INST_SETNE_INT = 0x3d, SQ_OP2_INST_SETGT_UINT = 0x3e, SQ_OP2_INST_SETGE_UINT = 0x3f, SQ_OP2_INST_KILLGT_UINT = 0x40, SQ_OP2_INST_KILLGE_UINT = 0x41, SQ_OP2_INST_PRED_SETE_INT = 0x42, SQ_OP2_INST_PRED_SETGT_INT = 0x43, SQ_OP2_INST_PRED_SETGE_INT = 0x44, SQ_OP2_INST_PRED_SETNE_INT = 0x45, SQ_OP2_INST_KILLE_INT = 0x46, SQ_OP2_INST_KILLGT_INT = 0x47, SQ_OP2_INST_KILLGE_INT = 0x48, SQ_OP2_INST_KILLNE_INT = 0x49, SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, SQ_OP2_INST_DOT4 = 0x50, SQ_OP2_INST_DOT4_IEEE = 0x51, SQ_OP2_INST_CUBE = 0x52, SQ_OP2_INST_MAX4 = 0x53, SQ_OP2_INST_MOVA_GPR_INT = 0x60, SQ_OP2_INST_EXP_IEEE = 0x61, SQ_OP2_INST_LOG_CLAMPED = 0x62, SQ_OP2_INST_LOG_IEEE = 0x63, SQ_OP2_INST_RECIP_CLAMPED = 0x64, SQ_OP2_INST_RECIP_FF = 0x65, SQ_OP2_INST_RECIP_IEEE = 0x66, SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, SQ_OP2_INST_RECIPSQRT_FF = 0x68, SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, SQ_OP2_INST_SQRT_IEEE = 0x6a, SQ_OP2_INST_FLT_TO_INT = 0x6b, SQ_OP2_INST_INT_TO_FLT = 0x6c, SQ_OP2_INST_UINT_TO_FLT = 0x6d, SQ_OP2_INST_SIN = 0x6e, SQ_OP2_INST_COS = 0x6f, SQ_OP2_INST_ASHR_INT = 0x70, SQ_OP2_INST_LSHR_INT = 0x71, SQ_OP2_INST_LSHL_INT = 0x72, SQ_OP2_INST_MULLO_INT = 0x73, SQ_OP2_INST_MULHI_INT = 0x74, SQ_OP2_INST_MULLO_UINT = 0x75, SQ_OP2_INST_MULHI_UINT = 0x76, SQ_OP2_INST_RECIP_INT = 0x77, SQ_OP2_INST_RECIP_UINT = 0x78, SQ_OP2_INST_FLT_TO_UINT = 0x79, SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, ARRAY_SIZE_mask = 0xfff << 0, ARRAY_SIZE_shift = 0, COMP_MASK_mask = 0x0f << 12, COMP_MASK_shift = 12, SQ_CF_WORD0 = 0x00008dfc, SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, ARRAY_BASE_mask = 0x1fff << 0, ARRAY_BASE_shift = 0, SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, SQ_EXPORT_PIXEL = 0x00, SQ_EXPORT_POS = 0x01, SQ_EXPORT_PARAM = 0x02, X_UNUSED_FOR_SX_EXPORTS = 0x03, RW_GPR_mask = 0x7f << 15, RW_GPR_shift = 15, RW_REL_bit = 1 << 22, INDEX_GPR_mask = 0x7f << 23, INDEX_GPR_shift = 23, ELEM_SIZE_mask = 0x03 << 30, ELEM_SIZE_shift = 30, SQ_VTX_WORD1 = 0x00008dfc, SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, SQ_VTX_WORD1__DST_SEL_X_shift = 9, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, SQ_VTX_WORD1__DST_SEL_Y_shift = 12, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, SQ_VTX_WORD1__DST_SEL_Z_shift = 15, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, SQ_VTX_WORD1__DST_SEL_W_shift = 18, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ /* SQ_SEL_MASK = 0x07, */ USE_CONST_FIELDS_bit = 1 << 21, SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, SQ_VTX_WORD1__DATA_FORMAT_shift = 22, SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, SQ_NUM_FORMAT_NORM = 0x00, SQ_NUM_FORMAT_INT = 0x01, SQ_NUM_FORMAT_SCALED = 0x02, SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, SQ_ALU_WORD1_OP2 = 0x00008dfc, /* SRC0_ABS_bit = 1 << 0, */ /* SRC1_ABS_bit = 1 << 1, */ /* UPDATE_EXECUTE_MASK_bit = 1 << 2, */ /* UPDATE_PRED_bit = 1 << 3, */ /* WRITE_MASK_bit = 1 << 4, */ FOG_MERGE_bit = 1 << 5, SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6, SQ_ALU_WORD1_OP2__OMOD_shift = 6, /* SQ_ALU_OMOD_OFF = 0x00, */ /* SQ_ALU_OMOD_M2 = 0x01, */ /* SQ_ALU_OMOD_M4 = 0x02, */ /* SQ_ALU_OMOD_D2 = 0x03, */ SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, /* SQ_OP2_INST_ADD = 0x00, */ /* SQ_OP2_INST_MUL = 0x01, */ /* SQ_OP2_INST_MUL_IEEE = 0x02, */ /* SQ_OP2_INST_MAX = 0x03, */ /* SQ_OP2_INST_MIN = 0x04, */ /* SQ_OP2_INST_MAX_DX10 = 0x05, */ /* SQ_OP2_INST_MIN_DX10 = 0x06, */ /* SQ_OP2_INST_SETE = 0x08, */ /* SQ_OP2_INST_SETGT = 0x09, */ /* SQ_OP2_INST_SETGE = 0x0a, */ /* SQ_OP2_INST_SETNE = 0x0b, */ /* SQ_OP2_INST_SETE_DX10 = 0x0c, */ /* SQ_OP2_INST_SETGT_DX10 = 0x0d, */ /* SQ_OP2_INST_SETGE_DX10 = 0x0e, */ /* SQ_OP2_INST_SETNE_DX10 = 0x0f, */ /* SQ_OP2_INST_FRACT = 0x10, */ /* SQ_OP2_INST_TRUNC = 0x11, */ /* SQ_OP2_INST_CEIL = 0x12, */ /* SQ_OP2_INST_RNDNE = 0x13, */ /* SQ_OP2_INST_FLOOR = 0x14, */ /* SQ_OP2_INST_MOVA = 0x15, */ /* SQ_OP2_INST_MOVA_FLOOR = 0x16, */ /* SQ_OP2_INST_MOVA_INT = 0x18, */ /* SQ_OP2_INST_MOV = 0x19, */ /* SQ_OP2_INST_NOP = 0x1a, */ /* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */ /* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */ /* SQ_OP2_INST_PRED_SETE = 0x20, */ /* SQ_OP2_INST_PRED_SETGT = 0x21, */ /* SQ_OP2_INST_PRED_SETGE = 0x22, */ /* SQ_OP2_INST_PRED_SETNE = 0x23, */ /* SQ_OP2_INST_PRED_SET_INV = 0x24, */ /* SQ_OP2_INST_PRED_SET_POP = 0x25, */ /* SQ_OP2_INST_PRED_SET_CLR = 0x26, */ /* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */ /* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */ /* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */ /* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */ /* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */ /* SQ_OP2_INST_KILLE = 0x2c, */ /* SQ_OP2_INST_KILLGT = 0x2d, */ /* SQ_OP2_INST_KILLGE = 0x2e, */ /* SQ_OP2_INST_KILLNE = 0x2f, */ /* SQ_OP2_INST_AND_INT = 0x30, */ /* SQ_OP2_INST_OR_INT = 0x31, */ /* SQ_OP2_INST_XOR_INT = 0x32, */ /* SQ_OP2_INST_NOT_INT = 0x33, */ /* SQ_OP2_INST_ADD_INT = 0x34, */ /* SQ_OP2_INST_SUB_INT = 0x35, */ /* SQ_OP2_INST_MAX_INT = 0x36, */ /* SQ_OP2_INST_MIN_INT = 0x37, */ /* SQ_OP2_INST_MAX_UINT = 0x38, */ /* SQ_OP2_INST_MIN_UINT = 0x39, */ /* SQ_OP2_INST_SETE_INT = 0x3a, */ /* SQ_OP2_INST_SETGT_INT = 0x3b, */ /* SQ_OP2_INST_SETGE_INT = 0x3c, */ /* SQ_OP2_INST_SETNE_INT = 0x3d, */ /* SQ_OP2_INST_SETGT_UINT = 0x3e, */ /* SQ_OP2_INST_SETGE_UINT = 0x3f, */ /* SQ_OP2_INST_KILLGT_UINT = 0x40, */ /* SQ_OP2_INST_KILLGE_UINT = 0x41, */ /* SQ_OP2_INST_PRED_SETE_INT = 0x42, */ /* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */ /* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */ /* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */ /* SQ_OP2_INST_KILLE_INT = 0x46, */ /* SQ_OP2_INST_KILLGT_INT = 0x47, */ /* SQ_OP2_INST_KILLGE_INT = 0x48, */ /* SQ_OP2_INST_KILLNE_INT = 0x49, */ /* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */ /* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */ /* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */ /* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */ /* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */ /* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */ /* SQ_OP2_INST_DOT4 = 0x50, */ /* SQ_OP2_INST_DOT4_IEEE = 0x51, */ /* SQ_OP2_INST_CUBE = 0x52, */ /* SQ_OP2_INST_MAX4 = 0x53, */ /* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */ /* SQ_OP2_INST_EXP_IEEE = 0x61, */ /* SQ_OP2_INST_LOG_CLAMPED = 0x62, */ /* SQ_OP2_INST_LOG_IEEE = 0x63, */ /* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */ /* SQ_OP2_INST_RECIP_FF = 0x65, */ /* SQ_OP2_INST_RECIP_IEEE = 0x66, */ /* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */ /* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */ /* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */ /* SQ_OP2_INST_SQRT_IEEE = 0x6a, */ /* SQ_OP2_INST_FLT_TO_INT = 0x6b, */ /* SQ_OP2_INST_INT_TO_FLT = 0x6c, */ /* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */ /* SQ_OP2_INST_SIN = 0x6e, */ /* SQ_OP2_INST_COS = 0x6f, */ /* SQ_OP2_INST_ASHR_INT = 0x70, */ /* SQ_OP2_INST_LSHR_INT = 0x71, */ /* SQ_OP2_INST_LSHL_INT = 0x72, */ /* SQ_OP2_INST_MULLO_INT = 0x73, */ /* SQ_OP2_INST_MULHI_INT = 0x74, */ /* SQ_OP2_INST_MULLO_UINT = 0x75, */ /* SQ_OP2_INST_MULHI_UINT = 0x76, */ /* SQ_OP2_INST_RECIP_INT = 0x77, */ /* SQ_OP2_INST_RECIP_UINT = 0x78, */ /* SQ_OP2_INST_FLT_TO_UINT = 0x79, */ SQ_CF_WORD1 = 0x00008dfc, POP_COUNT_mask = 0x07 << 0, POP_COUNT_shift = 0, CF_CONST_mask = 0x1f << 3, CF_CONST_shift = 3, COND_mask = 0x03 << 8, COND_shift = 8, SQ_CF_COND_ACTIVE = 0x00, SQ_CF_COND_FALSE = 0x01, SQ_CF_COND_BOOL = 0x02, SQ_CF_COND_NOT_BOOL = 0x03, SQ_CF_WORD1__COUNT_mask = 0x07 << 10, SQ_CF_WORD1__COUNT_shift = 10, CALL_COUNT_mask = 0x3f << 13, CALL_COUNT_shift = 13, COUNT_3_bit = 1 << 19, /* END_OF_PROGRAM_bit = 1 << 21, */ /* VALID_PIXEL_MODE_bit = 1 << 22, */ SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, SQ_CF_WORD1__CF_INST_shift = 23, SQ_CF_INST_NOP = 0x00, SQ_CF_INST_TEX = 0x01, SQ_CF_INST_VTX = 0x02, SQ_CF_INST_VTX_TC = 0x03, SQ_CF_INST_LOOP_START = 0x04, SQ_CF_INST_LOOP_END = 0x05, SQ_CF_INST_LOOP_START_DX10 = 0x06, SQ_CF_INST_LOOP_START_NO_AL = 0x07, SQ_CF_INST_LOOP_CONTINUE = 0x08, SQ_CF_INST_LOOP_BREAK = 0x09, SQ_CF_INST_JUMP = 0x0a, SQ_CF_INST_PUSH = 0x0b, SQ_CF_INST_PUSH_ELSE = 0x0c, SQ_CF_INST_ELSE = 0x0d, SQ_CF_INST_POP = 0x0e, SQ_CF_INST_POP_JUMP = 0x0f, SQ_CF_INST_POP_PUSH = 0x10, SQ_CF_INST_POP_PUSH_ELSE = 0x11, SQ_CF_INST_CALL = 0x12, SQ_CF_INST_CALL_FS = 0x13, SQ_CF_INST_RETURN = 0x14, SQ_CF_INST_EMIT_VERTEX = 0x15, SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, SQ_CF_INST_CUT_VERTEX = 0x17, SQ_CF_INST_KILL = 0x18, /* WHOLE_QUAD_MODE_bit = 1 << 30, */ /* BARRIER_bit = 1 << 31, */ SQ_VTX_WORD1_SEM = 0x00008dfc, SEMANTIC_ID_mask = 0xff << 0, SEMANTIC_ID_shift = 0, SQ_TEX_WORD0 = 0x00008dfc, TEX_INST_mask = 0x1f << 0, TEX_INST_shift = 0, SQ_TEX_INST_VTX_FETCH = 0x00, SQ_TEX_INST_VTX_SEMANTIC = 0x01, SQ_TEX_INST_LD = 0x03, SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, SQ_TEX_INST_GET_LOD = 0x06, SQ_TEX_INST_GET_GRADIENTS_H = 0x07, SQ_TEX_INST_GET_GRADIENTS_V = 0x08, SQ_TEX_INST_GET_LERP = 0x09, SQ_TEX_INST_RESERVED_10 = 0x0a, SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, SQ_TEX_INST_PASS = 0x0d, X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e, SQ_TEX_INST_SAMPLE = 0x10, SQ_TEX_INST_SAMPLE_L = 0x11, SQ_TEX_INST_SAMPLE_LB = 0x12, SQ_TEX_INST_SAMPLE_LZ = 0x13, SQ_TEX_INST_SAMPLE_G = 0x14, SQ_TEX_INST_SAMPLE_G_L = 0x15, SQ_TEX_INST_SAMPLE_G_LB = 0x16, SQ_TEX_INST_SAMPLE_G_LZ = 0x17, SQ_TEX_INST_SAMPLE_C = 0x18, SQ_TEX_INST_SAMPLE_C_L = 0x19, SQ_TEX_INST_SAMPLE_C_LB = 0x1a, SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, SQ_TEX_INST_SAMPLE_C_G = 0x1c, SQ_TEX_INST_SAMPLE_C_G_L = 0x1d, SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f, BC_FRAC_MODE_bit = 1 << 5, /* FETCH_WHOLE_QUAD_bit = 1 << 7, */ RESOURCE_ID_mask = 0xff << 8, RESOURCE_ID_shift = 8, /* SRC_GPR_mask = 0x7f << 16, */ /* SRC_GPR_shift = 16, */ /* SRC_REL_bit = 1 << 23, */ SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, SQ_VTX_WORD1_GPR = 0x00008dfc, SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, SQ_ALU_WORD0 = 0x00008dfc, SRC0_SEL_mask = 0x1ff << 0, SRC0_SEL_shift = 0, /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC0_REL_bit = 1 << 9, SRC0_CHAN_mask = 0x03 << 10, SRC0_CHAN_shift = 10, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC0_NEG_bit = 1 << 12, SRC1_SEL_mask = 0x1ff << 13, SRC1_SEL_shift = 13, /* SQ_ALU_SRC_0 = 0xf8, */ /* SQ_ALU_SRC_1 = 0xf9, */ /* SQ_ALU_SRC_1_INT = 0xfa, */ /* SQ_ALU_SRC_M_1_INT = 0xfb, */ /* SQ_ALU_SRC_0_5 = 0xfc, */ /* SQ_ALU_SRC_LITERAL = 0xfd, */ /* SQ_ALU_SRC_PV = 0xfe, */ /* SQ_ALU_SRC_PS = 0xff, */ SRC1_REL_bit = 1 << 22, SRC1_CHAN_mask = 0x03 << 23, SRC1_CHAN_shift = 23, /* SQ_CHAN_X = 0x00, */ /* SQ_CHAN_Y = 0x01, */ /* SQ_CHAN_Z = 0x02, */ /* SQ_CHAN_W = 0x03, */ SRC1_NEG_bit = 1 << 25, INDEX_MODE_mask = 0x07 << 26, INDEX_MODE_shift = 26, SQ_INDEX_AR_X = 0x00, SQ_INDEX_AR_Y = 0x01, SQ_INDEX_AR_Z = 0x02, SQ_INDEX_AR_W = 0x03, SQ_INDEX_LOOP = 0x04, PRED_SEL_mask = 0x03 << 29, PRED_SEL_shift = 29, SQ_PRED_SEL_OFF = 0x00, SQ_PRED_SEL_ZERO = 0x02, SQ_PRED_SEL_ONE = 0x03, LAST_bit = 1 << 31, SX_EXPORT_BUFFER_SIZES = 0x0000900c, COLOR_BUFFER_SIZE_mask = 0xff << 0, COLOR_BUFFER_SIZE_shift = 0, POSITION_BUFFER_SIZE_mask = 0xff << 8, POSITION_BUFFER_SIZE_shift = 8, SMX_BUFFER_SIZE_mask = 0xff << 16, SMX_BUFFER_SIZE_shift = 16, SX_MEMORY_EXPORT_BASE = 0x00009010, SX_MEMORY_EXPORT_SIZE = 0x00009014, SPI_CONFIG_CNTL = 0x00009100, GPR_WRITE_PRIORITY_mask = 0x1f << 0, GPR_WRITE_PRIORITY_shift = 0, X_PRIORITY_ORDER = 0x00, X_PRIORITY_ORDER_VS = 0x01, DISABLE_INTERP_1_bit = 1 << 5, DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6, DEBUG_THREAD_TYPE_SEL_shift = 6, DEBUG_GROUP_SEL_mask = 0x1f << 8, DEBUG_GROUP_SEL_shift = 8, DEBUG_GRBM_OVERRIDE_bit = 1 << 13, SPI_CONFIG_CNTL_1 = 0x0000913c, VTX_DONE_DELAY_mask = 0x0f << 0, VTX_DONE_DELAY_shift = 0, X_DELAY_10_CLKS = 0x00, X_DELAY_11_CLKS = 0x01, X_DELAY_12_CLKS = 0x02, X_DELAY_13_CLKS = 0x03, X_DELAY_14_CLKS = 0x04, X_DELAY_15_CLKS = 0x05, X_DELAY_16_CLKS = 0x06, X_DELAY_17_CLKS = 0x07, X_DELAY_2_CLKS = 0x08, X_DELAY_3_CLKS = 0x09, X_DELAY_4_CLKS = 0x0a, X_DELAY_5_CLKS = 0x0b, X_DELAY_6_CLKS = 0x0c, X_DELAY_7_CLKS = 0x0d, X_DELAY_8_CLKS = 0x0e, X_DELAY_9_CLKS = 0x0f, INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, TD_FILTER4 = 0x00009400, WEIGHT_1_mask = 0x7ff << 0, WEIGHT_1_shift = 0, WEIGHT_0_mask = 0x7ff << 11, WEIGHT_0_shift = 11, WEIGHT_PAIR_bit = 1 << 22, PHASE_mask = 0x0f << 23, PHASE_shift = 23, DIRECTION_bit = 1 << 27, TD_FILTER4_1 = 0x00009404, TD_FILTER4_1_num = 35, /* WEIGHT_1_mask = 0x7ff << 0, */ /* WEIGHT_1_shift = 0, */ /* WEIGHT_0_mask = 0x7ff << 11, */ /* WEIGHT_0_shift = 11, */ TD_CNTL = 0x00009490, SYNC_PHASE_SH_mask = 0x03 << 0, SYNC_PHASE_SH_shift = 0, SYNC_PHASE_VC_SMX_mask = 0x03 << 4, SYNC_PHASE_VC_SMX_shift = 4, TD0_CNTL = 0x00009494, TD0_CNTL_num = 4, ID_OVERRIDE_mask = 0x03 << 28, ID_OVERRIDE_shift = 28, TD0_STATUS = 0x000094a4, TD0_STATUS_num = 4, BUSY_bit = 1 << 31, TA_CNTL = 0x00009504, GRADIENT_CREDIT_mask = 0x1f << 0, GRADIENT_CREDIT_shift = 0, WALKER_CREDIT_mask = 0x1f << 8, WALKER_CREDIT_shift = 8, ALIGNER_CREDIT_mask = 0x1f << 16, ALIGNER_CREDIT_shift = 16, TD_FIFO_CREDIT_mask = 0x3ff << 22, TD_FIFO_CREDIT_shift = 22, TA_CNTL_AUX = 0x00009508, DISABLE_CUBE_WRAP_bit = 1 << 0, SYNC_GRADIENT_bit = 1 << 24, SYNC_WALKER_bit = 1 << 25, SYNC_ALIGNER_bit = 1 << 26, BILINEAR_PRECISION_bit = 1 << 31, TA0_CNTL = 0x00009510, /* ID_OVERRIDE_mask = 0x03 << 28, */ /* ID_OVERRIDE_shift = 28, */ TA1_CNTL = 0x00009514, /* ID_OVERRIDE_mask = 0x03 << 28, */ /* ID_OVERRIDE_shift = 28, */ TA2_CNTL = 0x00009518, /* ID_OVERRIDE_mask = 0x03 << 28, */ /* ID_OVERRIDE_shift = 28, */ TA3_CNTL = 0x0000951c, /* ID_OVERRIDE_mask = 0x03 << 28, */ /* ID_OVERRIDE_shift = 28, */ TA0_STATUS = 0x00009520, FG_PFIFO_EMPTYB_bit = 1 << 12, FG_LFIFO_EMPTYB_bit = 1 << 13, FG_SFIFO_EMPTYB_bit = 1 << 14, FL_PFIFO_EMPTYB_bit = 1 << 16, FL_LFIFO_EMPTYB_bit = 1 << 17, FL_SFIFO_EMPTYB_bit = 1 << 18, FA_PFIFO_EMPTYB_bit = 1 << 20, FA_LFIFO_EMPTYB_bit = 1 << 21, FA_SFIFO_EMPTYB_bit = 1 << 22, IN_BUSY_bit = 1 << 24, FG_BUSY_bit = 1 << 25, FL_BUSY_bit = 1 << 27, TA_BUSY_bit = 1 << 28, FA_BUSY_bit = 1 << 29, AL_BUSY_bit = 1 << 30, /* BUSY_bit = 1 << 31, */ TA1_STATUS = 0x00009524, /* FG_PFIFO_EMPTYB_bit = 1 << 12, */ /* FG_LFIFO_EMPTYB_bit = 1 << 13, */ /* FG_SFIFO_EMPTYB_bit = 1 << 14, */ /* FL_PFIFO_EMPTYB_bit = 1 << 16, */ /* FL_LFIFO_EMPTYB_bit = 1 << 17, */ /* FL_SFIFO_EMPTYB_bit = 1 << 18, */ /* FA_PFIFO_EMPTYB_bit = 1 << 20, */ /* FA_LFIFO_EMPTYB_bit = 1 << 21, */ /* FA_SFIFO_EMPTYB_bit = 1 << 22, */ /* IN_BUSY_bit = 1 << 24, */ /* FG_BUSY_bit = 1 << 25, */ /* FL_BUSY_bit = 1 << 27, */ /* TA_BUSY_bit = 1 << 28, */ /* FA_BUSY_bit = 1 << 29, */ /* AL_BUSY_bit = 1 << 30, */ /* BUSY_bit = 1 << 31, */ TA2_STATUS = 0x00009528, /* FG_PFIFO_EMPTYB_bit = 1 << 12, */ /* FG_LFIFO_EMPTYB_bit = 1 << 13, */ /* FG_SFIFO_EMPTYB_bit = 1 << 14, */ /* FL_PFIFO_EMPTYB_bit = 1 << 16, */ /* FL_LFIFO_EMPTYB_bit = 1 << 17, */ /* FL_SFIFO_EMPTYB_bit = 1 << 18, */ /* FA_PFIFO_EMPTYB_bit = 1 << 20, */ /* FA_LFIFO_EMPTYB_bit = 1 << 21, */ /* FA_SFIFO_EMPTYB_bit = 1 << 22, */ /* IN_BUSY_bit = 1 << 24, */ /* FG_BUSY_bit = 1 << 25, */ /* FL_BUSY_bit = 1 << 27, */ /* TA_BUSY_bit = 1 << 28, */ /* FA_BUSY_bit = 1 << 29, */ /* AL_BUSY_bit = 1 << 30, */ /* BUSY_bit = 1 << 31, */ TA3_STATUS = 0x0000952c, /* FG_PFIFO_EMPTYB_bit = 1 << 12, */ /* FG_LFIFO_EMPTYB_bit = 1 << 13, */ /* FG_SFIFO_EMPTYB_bit = 1 << 14, */ /* FL_PFIFO_EMPTYB_bit = 1 << 16, */ /* FL_LFIFO_EMPTYB_bit = 1 << 17, */ /* FL_SFIFO_EMPTYB_bit = 1 << 18, */ /* FA_PFIFO_EMPTYB_bit = 1 << 20, */ /* FA_LFIFO_EMPTYB_bit = 1 << 21, */ /* FA_SFIFO_EMPTYB_bit = 1 << 22, */ /* IN_BUSY_bit = 1 << 24, */ /* FG_BUSY_bit = 1 << 25, */ /* FL_BUSY_bit = 1 << 27, */ /* TA_BUSY_bit = 1 << 28, */ /* FA_BUSY_bit = 1 << 29, */ /* AL_BUSY_bit = 1 << 30, */ /* BUSY_bit = 1 << 31, */ TC_STATUS = 0x00009600, TC_BUSY_bit = 1 << 0, TC_INVALIDATE = 0x00009604, START_bit = 1 << 0, TC_CNTL = 0x00009608, FORCE_HIT_bit = 1 << 0, FORCE_MISS_bit = 1 << 1, L2_SIZE_mask = 0x0f << 5, L2_SIZE_shift = 5, _256K = 0x00, _224K = 0x01, _192K = 0x02, _160K = 0x03, _128K = 0x04, _96K = 0x05, _64K = 0x06, _32K = 0x07, L2_DISABLE_LATE_HIT_bit = 1 << 9, DISABLE_VERT_PERF_bit = 1 << 10, DISABLE_INVAL_BUSY_bit = 1 << 11, DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12, PARTITION_MODE_mask = 0x03 << 13, PARTITION_MODE_shift = 13, X_VERTEX = 0x00, MISS_ARB_MODE_bit = 1 << 15, HIT_ARB_MODE_bit = 1 << 16, DISABLE_WRITE_DELAY_bit = 1 << 17, HIT_FIFO_DEPTH_bit = 1 << 18, VC_CNTL = 0x00009700, L2_INVALIDATE_bit = 1 << 0, RESERVED_bit = 1 << 1, CC_FORCE_MISS_bit = 1 << 2, MI_CHAN_SEL_mask = 0x03 << 3, MI_CHAN_SEL_shift = 3, X_MC0_USES_CH_0_1 = 0x00, X_MC0_USES_CH_0_3 = 0x01, X_VC_MC0_IS_ACTIVE = 0x02, X_VC_MC1_IS_DISABLED = 0x03, MI_STEER_DISABLE_bit = 1 << 5, MI_CREDIT_CTR_mask = 0x0f << 6, MI_CREDIT_CTR_shift = 6, MI_CREDIT_WE_bit = 1 << 10, MI_REQ_STALL_THLD_mask = 0x07 << 11, MI_REQ_STALL_THLD_shift = 11, X_LATENCY_EXCEEDS_399_CLOCKS = 0x00, X_LATENCY_EXCEEDS_415_CLOCKS = 0x01, X_LATENCY_EXCEEDS_431_CLOCKS = 0x02, X_LATENCY_EXCEEDS_447_CLOCKS = 0x03, X_LATENCY_EXCEEDS_463_CLOCKS = 0x04, X_LATENCY_EXCEEDS_479_CLOCKS = 0x05, X_LATENCY_EXCEEDS_495_CLOCKS = 0x06, X_LATENCY_EXCEEDS_511_CLOCKS = 0x07, VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14, VC_CNTL__MI_TIMESTAMP_RES_shift = 14, X_1X_SYSTEM_CLOCK = 0x00, X_2X_SYSTEM_CLOCK = 0x01, X_4X_SYSTEM_CLOCK = 0x02, X_8X_SYSTEM_CLOCK = 0x03, X_16X_SYSTEM_CLOCK = 0x04, X_32X_SYSTEM_CLOCK = 0x05, X_64X_SYSTEM_CLOCK = 0x06, X_128X_SYSTEM_CLOCK = 0x07, X_256X_SYSTEM_CLOCK = 0x08, X_512X_SYSTEM_CLOCK = 0x09, X_1024X_SYSTEM_CLOCK = 0x0a, X_2048X_SYSTEM_CLOCK = 0x0b, X_4092X_SYSTEM_CLOCK = 0x0c, X_8192X_SYSTEM_CLOCK = 0x0d, X_16384X_SYSTEM_CLOCK = 0x0e, X_32768X_SYSTEM_CLOCK = 0x0f, VC_CNTL_STATUS = 0x00009704, RP_BUSY_bit = 1 << 0, RG_BUSY_bit = 1 << 1, VC_BUSY_bit = 1 << 2, CLAMP_DETECT_bit = 1 << 3, VC_CONFIG = 0x00009718, WRITE_DIS_bit = 1 << 0, GPR_DATA_PHASE_ADJ_mask = 0x07 << 1, GPR_DATA_PHASE_ADJ_shift = 1, X_LATENCY_BASE_0_CYCLES = 0x00, X_LATENCY_BASE_1_CYCLES = 0x01, X_LATENCY_BASE_2_CYCLES = 0x02, X_LATENCY_BASE_3_CYCLES = 0x03, TD_SIMD_SYNC_ADJ_mask = 0x07 << 4, TD_SIMD_SYNC_ADJ_shift = 4, X_0_CYCLES_DELAY = 0x00, X_1_CYCLES_DELAY = 0x01, X_2_CYCLES_DELAY = 0x02, X_3_CYCLES_DELAY = 0x03, X_4_CYCLES_DELAY = 0x04, X_5_CYCLES_DELAY = 0x05, X_6_CYCLES_DELAY = 0x06, X_7_CYCLES_DELAY = 0x07, SMX_DC_CTL0 = 0x0000a020, WR_GATHER_STREAM0_bit = 1 << 0, WR_GATHER_STREAM1_bit = 1 << 1, WR_GATHER_STREAM2_bit = 1 << 2, WR_GATHER_STREAM3_bit = 1 << 3, WR_GATHER_SCRATCH_bit = 1 << 4, WR_GATHER_REDUC_BUF_bit = 1 << 5, WR_GATHER_RING_BUF_bit = 1 << 6, WR_GATHER_F_BUF_bit = 1 << 7, DISABLE_CACHES_bit = 1 << 8, AUTO_FLUSH_INVAL_EN_bit = 1 << 10, AUTO_FLUSH_EN_bit = 1 << 11, AUTO_FLUSH_CNT_mask = 0xffff << 12, AUTO_FLUSH_CNT_shift = 12, MC_RD_STALL_FACTOR_mask = 0x03 << 28, MC_RD_STALL_FACTOR_shift = 28, MC_WR_STALL_FACTOR_mask = 0x03 << 30, MC_WR_STALL_FACTOR_shift = 30, SMX_DC_CTL1 = 0x0000a024, OP_FIFO_SKID_mask = 0x7f << 0, OP_FIFO_SKID_shift = 0, CACHE_LINE_SIZE_bit = 1 << 8, MULTI_FLUSH_MODE_bit = 1 << 9, MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10, MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10, DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16, DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17, DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18, DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19, SMX_DC_CTL2 = 0x0000a028, INVALIDATE_CACHES_bit = 1 << 0, CACHES_INVALID_bit = 1 << 1, CACHES_DIRTY_bit = 1 << 2, FLUSH_ALL_bit = 1 << 4, FLUSH_GS_THREADS_bit = 1 << 8, FLUSH_ES_THREADS_bit = 1 << 9, SMX_DC_MC_INTF_CTL = 0x0000a02c, MC_RD_REQ_CRED_mask = 0xff << 0, MC_RD_REQ_CRED_shift = 0, MC_WR_REQ_CRED_mask = 0xff << 16, MC_WR_REQ_CRED_shift = 16, TD_PS_SAMPLER0_BORDER_RED = 0x0000a400, TD_PS_SAMPLER0_BORDER_RED_num = 18, TD_PS_SAMPLER0_BORDER_RED_offset = 16, TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404, TD_PS_SAMPLER0_BORDER_GREEN_num = 18, TD_PS_SAMPLER0_BORDER_GREEN_offset = 16, TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408, TD_PS_SAMPLER0_BORDER_BLUE_num = 18, TD_PS_SAMPLER0_BORDER_BLUE_offset = 16, TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c, TD_PS_SAMPLER0_BORDER_ALPHA_num = 18, TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16, TD_VS_SAMPLER0_BORDER_RED = 0x0000a600, TD_VS_SAMPLER0_BORDER_RED_num = 18, TD_VS_SAMPLER0_BORDER_RED_offset = 16, TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604, TD_VS_SAMPLER0_BORDER_GREEN_num = 18, TD_VS_SAMPLER0_BORDER_GREEN_offset = 16, TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608, TD_VS_SAMPLER0_BORDER_BLUE_num = 18, TD_VS_SAMPLER0_BORDER_BLUE_offset = 16, TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c, TD_VS_SAMPLER0_BORDER_ALPHA_num = 18, TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16, TD_GS_SAMPLER0_BORDER_RED = 0x0000a800, TD_GS_SAMPLER0_BORDER_RED_num = 18, TD_GS_SAMPLER0_BORDER_RED_offset = 16, TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804, TD_GS_SAMPLER0_BORDER_GREEN_num = 18, TD_GS_SAMPLER0_BORDER_GREEN_offset = 16, TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808, TD_GS_SAMPLER0_BORDER_BLUE_num = 18, TD_GS_SAMPLER0_BORDER_BLUE_offset = 16, TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c, TD_GS_SAMPLER0_BORDER_ALPHA_num = 18, TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16, TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00, TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18, TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0, TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0, TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3, TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3, DB_DEPTH_SIZE = 0x00028000, PITCH_TILE_MAX_mask = 0x3ff << 0, PITCH_TILE_MAX_shift = 0, SLICE_TILE_MAX_mask = 0xfffff << 10, SLICE_TILE_MAX_shift = 10, DB_DEPTH_VIEW = 0x00028004, SLICE_START_mask = 0x7ff << 0, SLICE_START_shift = 0, SLICE_MAX_mask = 0x7ff << 13, SLICE_MAX_shift = 13, DB_DEPTH_BASE = 0x0002800c, DB_DEPTH_INFO = 0x00028010, DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0, DB_DEPTH_INFO__FORMAT_shift = 0, DEPTH_INVALID = 0x00, DEPTH_16 = 0x01, DEPTH_X8_24 = 0x02, DEPTH_8_24 = 0x03, DEPTH_X8_24_FLOAT = 0x04, DEPTH_8_24_FLOAT = 0x05, DEPTH_32_FLOAT = 0x06, DEPTH_X24_8_32_FLOAT = 0x07, DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3, DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15, DB_DEPTH_INFO__ARRAY_MODE_shift = 15, ARRAY_2D_TILED_THIN1 = 0x04, TILE_SURFACE_ENABLE_bit = 1 << 25, TILE_COMPACT_bit = 1 << 26, ZRANGE_PRECISION_bit = 1 << 31, DB_HTILE_DATA_BASE = 0x00028014, DB_STENCIL_CLEAR = 0x00028028, DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, DB_STENCIL_CLEAR__CLEAR_shift = 0, MIN_mask = 0xff << 16, MIN_shift = 16, DB_DEPTH_CLEAR = 0x0002802c, PA_SC_SCREEN_SCISSOR_TL = 0x00028030, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0, PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, PA_SC_SCREEN_SCISSOR_BR = 0x00028034, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0, PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, CB_COLOR0_BASE = 0x00028040, CB_COLOR0_BASE_num = 8, CB_COLOR0_SIZE = 0x00028060, CB_COLOR0_SIZE_num = 8, /* PITCH_TILE_MAX_mask = 0x3ff << 0, */ /* PITCH_TILE_MAX_shift = 0, */ /* SLICE_TILE_MAX_mask = 0xfffff << 10, */ /* SLICE_TILE_MAX_shift = 10, */ CB_COLOR0_VIEW = 0x00028080, CB_COLOR0_VIEW_num = 8, /* SLICE_START_mask = 0x7ff << 0, */ /* SLICE_START_shift = 0, */ /* SLICE_MAX_mask = 0x7ff << 13, */ /* SLICE_MAX_shift = 13, */ CB_COLOR0_INFO = 0x000280a0, CB_COLOR0_INFO_num = 8, ENDIAN_mask = 0x03 << 0, ENDIAN_shift = 0, ENDIAN_NONE = 0x00, ENDIAN_8IN16 = 0x01, ENDIAN_8IN32 = 0x02, ENDIAN_8IN64 = 0x03, CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, CB_COLOR0_INFO__FORMAT_shift = 2, COLOR_INVALID = 0x00, COLOR_8 = 0x01, COLOR_4_4 = 0x02, COLOR_3_3_2 = 0x03, COLOR_16 = 0x05, COLOR_16_FLOAT = 0x06, COLOR_8_8 = 0x07, COLOR_5_6_5 = 0x08, COLOR_6_5_5 = 0x09, COLOR_1_5_5_5 = 0x0a, COLOR_4_4_4_4 = 0x0b, COLOR_5_5_5_1 = 0x0c, COLOR_32 = 0x0d, COLOR_32_FLOAT = 0x0e, COLOR_16_16 = 0x0f, COLOR_16_16_FLOAT = 0x10, COLOR_8_24 = 0x11, COLOR_8_24_FLOAT = 0x12, COLOR_24_8 = 0x13, COLOR_24_8_FLOAT = 0x14, COLOR_10_11_11 = 0x15, COLOR_10_11_11_FLOAT = 0x16, COLOR_11_11_10 = 0x17, COLOR_11_11_10_FLOAT = 0x18, COLOR_2_10_10_10 = 0x19, COLOR_8_8_8_8 = 0x1a, COLOR_10_10_10_2 = 0x1b, COLOR_X24_8_32_FLOAT = 0x1c, COLOR_32_32 = 0x1d, COLOR_32_32_FLOAT = 0x1e, COLOR_16_16_16_16 = 0x1f, COLOR_16_16_16_16_FLOAT = 0x20, COLOR_32_32_32_32 = 0x22, COLOR_32_32_32_32_FLOAT = 0x23, CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, CB_COLOR0_INFO__ARRAY_MODE_shift = 8, ARRAY_LINEAR_GENERAL = 0x00, ARRAY_LINEAR_ALIGNED = 0x01, /* ARRAY_2D_TILED_THIN1 = 0x04, */ NUMBER_TYPE_mask = 0x07 << 12, NUMBER_TYPE_shift = 12, NUMBER_UNORM = 0x00, NUMBER_SNORM = 0x01, NUMBER_USCALED = 0x02, NUMBER_SSCALED = 0x03, NUMBER_UINT = 0x04, NUMBER_SINT = 0x05, NUMBER_SRGB = 0x06, NUMBER_FLOAT = 0x07, CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15, COMP_SWAP_mask = 0x03 << 16, COMP_SWAP_shift = 16, SWAP_STD = 0x00, SWAP_ALT = 0x01, SWAP_STD_REV = 0x02, SWAP_ALT_REV = 0x03, CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18, CB_COLOR0_INFO__TILE_MODE_shift = 18, TILE_DISABLE = 0x00, TILE_CLEAR_ENABLE = 0x01, TILE_FRAG_ENABLE = 0x02, BLEND_CLAMP_bit = 1 << 20, CLEAR_COLOR_bit = 1 << 21, BLEND_BYPASS_bit = 1 << 22, BLEND_FLOAT32_bit = 1 << 23, SIMPLE_FLOAT_bit = 1 << 24, CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25, /* TILE_COMPACT_bit = 1 << 26, */ SOURCE_FORMAT_bit = 1 << 27, CB_COLOR0_TILE = 0x000280c0, CB_COLOR0_TILE_num = 8, CB_COLOR0_FRAG = 0x000280e0, CB_COLOR0_FRAG_num = 8, CB_COLOR0_MASK = 0x00028100, CB_COLOR0_MASK_num = 8, CMASK_BLOCK_MAX_mask = 0xfff << 0, CMASK_BLOCK_MAX_shift = 0, FMASK_TILE_MAX_mask = 0xfffff << 12, FMASK_TILE_MAX_shift = 12, CB_CLEAR_RED = 0x00028120, CB_CLEAR_GREEN = 0x00028124, CB_CLEAR_BLUE = 0x00028128, CB_CLEAR_ALPHA = 0x0002812c, SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, PA_SC_WINDOW_OFFSET = 0x00028200, WINDOW_X_OFFSET_mask = 0x7fff << 0, WINDOW_X_OFFSET_shift = 0, WINDOW_Y_OFFSET_mask = 0x7fff << 16, WINDOW_Y_OFFSET_shift = 16, PA_SC_WINDOW_SCISSOR_TL = 0x00028204, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0, PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, WINDOW_OFFSET_DISABLE_bit = 1 << 31, PA_SC_WINDOW_SCISSOR_BR = 0x00028208, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0, PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, PA_SC_CLIPRECT_RULE = 0x0002820c, CLIP_RULE_mask = 0xffff << 0, CLIP_RULE_shift = 0, PA_SC_CLIPRECT_0_TL = 0x00028210, PA_SC_CLIPRECT_0_TL_num = 4, PA_SC_CLIPRECT_0_TL_offset = 8, PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0, PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16, PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, PA_SC_CLIPRECT_0_BR = 0x00028214, PA_SC_CLIPRECT_0_BR_num = 4, PA_SC_CLIPRECT_0_BR_offset = 8, PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0, PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16, PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, CB_TARGET_MASK = 0x00028238, TARGET0_ENABLE_mask = 0x0f << 0, TARGET0_ENABLE_shift = 0, TARGET1_ENABLE_mask = 0x0f << 4, TARGET1_ENABLE_shift = 4, TARGET2_ENABLE_mask = 0x0f << 8, TARGET2_ENABLE_shift = 8, TARGET3_ENABLE_mask = 0x0f << 12, TARGET3_ENABLE_shift = 12, TARGET4_ENABLE_mask = 0x0f << 16, TARGET4_ENABLE_shift = 16, TARGET5_ENABLE_mask = 0x0f << 20, TARGET5_ENABLE_shift = 20, TARGET6_ENABLE_mask = 0x0f << 24, TARGET6_ENABLE_shift = 24, TARGET7_ENABLE_mask = 0x0f << 28, TARGET7_ENABLE_shift = 28, CB_SHADER_MASK = 0x0002823c, OUTPUT0_ENABLE_mask = 0x0f << 0, OUTPUT0_ENABLE_shift = 0, OUTPUT1_ENABLE_mask = 0x0f << 4, OUTPUT1_ENABLE_shift = 4, OUTPUT2_ENABLE_mask = 0x0f << 8, OUTPUT2_ENABLE_shift = 8, OUTPUT3_ENABLE_mask = 0x0f << 12, OUTPUT3_ENABLE_shift = 12, OUTPUT4_ENABLE_mask = 0x0f << 16, OUTPUT4_ENABLE_shift = 16, OUTPUT5_ENABLE_mask = 0x0f << 20, OUTPUT5_ENABLE_shift = 20, OUTPUT6_ENABLE_mask = 0x0f << 24, OUTPUT6_ENABLE_shift = 24, OUTPUT7_ENABLE_mask = 0x0f << 28, OUTPUT7_ENABLE_shift = 28, PA_SC_GENERIC_SCISSOR_TL = 0x00028240, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0, PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_GENERIC_SCISSOR_BR = 0x00028244, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0, PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, PA_SC_VPORT_SCISSOR_0_TL_num = 16, PA_SC_VPORT_SCISSOR_0_TL_offset = 8, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, PA_SC_VPORT_SCISSOR_0_BR_num = 16, PA_SC_VPORT_SCISSOR_0_BR_offset = 8, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, PA_SC_VPORT_ZMIN_0 = 0x000282d0, PA_SC_VPORT_ZMIN_0_num = 16, PA_SC_VPORT_ZMIN_0_offset = 8, PA_SC_VPORT_ZMAX_0 = 0x000282d4, PA_SC_VPORT_ZMAX_0_num = 16, PA_SC_VPORT_ZMAX_0_offset = 8, SX_MISC = 0x00028350, MULTIPASS_bit = 1 << 0, SQ_VTX_SEMANTIC_0 = 0x00028380, SQ_VTX_SEMANTIC_0_num = 32, /* SEMANTIC_ID_mask = 0xff << 0, */ /* SEMANTIC_ID_shift = 0, */ VGT_MAX_VTX_INDX = 0x00028400, VGT_MIN_VTX_INDX = 0x00028404, VGT_INDX_OFFSET = 0x00028408, VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, SX_ALPHA_TEST_CONTROL = 0x00028410, ALPHA_FUNC_mask = 0x07 << 0, ALPHA_FUNC_shift = 0, REF_NEVER = 0x00, REF_LESS = 0x01, REF_EQUAL = 0x02, REF_LEQUAL = 0x03, REF_GREATER = 0x04, REF_NOTEQUAL = 0x05, REF_GEQUAL = 0x06, REF_ALWAYS = 0x07, ALPHA_TEST_ENABLE_bit = 1 << 3, ALPHA_TEST_BYPASS_bit = 1 << 8, CB_BLEND_RED = 0x00028414, CB_BLEND_GREEN = 0x00028418, CB_BLEND_BLUE = 0x0002841c, CB_BLEND_ALPHA = 0x00028420, CB_FOG_RED = 0x00028424, CB_FOG_GREEN = 0x00028428, CB_FOG_BLUE = 0x0002842c, DB_STENCILREFMASK = 0x00028430, STENCILREF_mask = 0xff << 0, STENCILREF_shift = 0, STENCILMASK_mask = 0xff << 8, STENCILMASK_shift = 8, STENCILWRITEMASK_mask = 0xff << 16, STENCILWRITEMASK_shift = 16, DB_STENCILREFMASK_BF = 0x00028434, STENCILREF_BF_mask = 0xff << 0, STENCILREF_BF_shift = 0, STENCILMASK_BF_mask = 0xff << 8, STENCILMASK_BF_shift = 8, STENCILWRITEMASK_BF_mask = 0xff << 16, STENCILWRITEMASK_BF_shift = 16, SX_ALPHA_REF = 0x00028438, PA_CL_VPORT_XSCALE_0 = 0x0002843c, PA_CL_VPORT_XSCALE_0_num = 16, PA_CL_VPORT_XSCALE_0_offset = 24, PA_CL_VPORT_XOFFSET_0 = 0x00028440, PA_CL_VPORT_XOFFSET_0_num = 16, PA_CL_VPORT_XOFFSET_0_offset = 24, PA_CL_VPORT_YSCALE_0 = 0x00028444, PA_CL_VPORT_YSCALE_0_num = 16, PA_CL_VPORT_YSCALE_0_offset = 24, PA_CL_VPORT_YOFFSET_0 = 0x00028448, PA_CL_VPORT_YOFFSET_0_num = 16, PA_CL_VPORT_YOFFSET_0_offset = 24, PA_CL_VPORT_ZSCALE_0 = 0x0002844c, PA_CL_VPORT_ZSCALE_0_num = 16, PA_CL_VPORT_ZSCALE_0_offset = 24, PA_CL_VPORT_ZOFFSET_0 = 0x00028450, PA_CL_VPORT_ZOFFSET_0_num = 16, PA_CL_VPORT_ZOFFSET_0_offset = 24, SPI_VS_OUT_ID_0 = 0x00028614, SPI_VS_OUT_ID_0_num = 10, SEMANTIC_0_mask = 0xff << 0, SEMANTIC_0_shift = 0, SEMANTIC_1_mask = 0xff << 8, SEMANTIC_1_shift = 8, SEMANTIC_2_mask = 0xff << 16, SEMANTIC_2_shift = 16, SEMANTIC_3_mask = 0xff << 24, SEMANTIC_3_shift = 24, SPI_PS_INPUT_CNTL_0 = 0x00028644, SPI_PS_INPUT_CNTL_0_num = 32, SEMANTIC_mask = 0xff << 0, SEMANTIC_shift = 0, DEFAULT_VAL_mask = 0x03 << 8, DEFAULT_VAL_shift = 8, X_0_0F = 0x00, FLAT_SHADE_bit = 1 << 10, SEL_CENTROID_bit = 1 << 11, SEL_LINEAR_bit = 1 << 12, CYL_WRAP_mask = 0x0f << 13, CYL_WRAP_shift = 13, PT_SPRITE_TEX_bit = 1 << 17, SEL_SAMPLE_bit = 1 << 18, SPI_VS_OUT_CONFIG = 0x000286c4, VS_PER_COMPONENT_bit = 1 << 0, VS_EXPORT_COUNT_mask = 0x1f << 1, VS_EXPORT_COUNT_shift = 1, VS_EXPORTS_FOG_bit = 1 << 8, VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, VS_OUT_FOG_VEC_ADDR_shift = 9, SPI_PS_IN_CONTROL_0 = 0x000286cc, NUM_INTERP_mask = 0x3f << 0, NUM_INTERP_shift = 0, POSITION_ENA_bit = 1 << 8, POSITION_CENTROID_bit = 1 << 9, POSITION_ADDR_mask = 0x1f << 10, POSITION_ADDR_shift = 10, PARAM_GEN_mask = 0x0f << 15, PARAM_GEN_shift = 15, PARAM_GEN_ADDR_mask = 0x7f << 19, PARAM_GEN_ADDR_shift = 19, BARYC_SAMPLE_CNTL_mask = 0x03 << 26, BARYC_SAMPLE_CNTL_shift = 26, CENTROIDS_ONLY = 0x00, CENTERS_ONLY = 0x01, CENTROIDS_AND_CENTERS = 0x02, UNDEF = 0x03, PERSP_GRADIENT_ENA_bit = 1 << 28, LINEAR_GRADIENT_ENA_bit = 1 << 29, POSITION_SAMPLE_bit = 1 << 30, BARYC_AT_SAMPLE_ENA_bit = 1 << 31, SPI_PS_IN_CONTROL_1 = 0x000286d0, GEN_INDEX_PIX_bit = 1 << 0, GEN_INDEX_PIX_ADDR_mask = 0x7f << 1, GEN_INDEX_PIX_ADDR_shift = 1, FRONT_FACE_ENA_bit = 1 << 8, FRONT_FACE_CHAN_mask = 0x03 << 9, FRONT_FACE_CHAN_shift = 9, FRONT_FACE_ALL_BITS_bit = 1 << 11, FRONT_FACE_ADDR_mask = 0x1f << 12, FRONT_FACE_ADDR_shift = 12, FOG_ADDR_mask = 0x7f << 17, FOG_ADDR_shift = 17, FIXED_PT_POSITION_ENA_bit = 1 << 24, FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, FIXED_PT_POSITION_ADDR_shift = 25, SPI_INTERP_CONTROL_0 = 0x000286d4, FLAT_SHADE_ENA_bit = 1 << 0, PNT_SPRITE_ENA_bit = 1 << 1, PNT_SPRITE_OVRD_X_mask = 0x07 << 2, PNT_SPRITE_OVRD_X_shift = 2, SPI_PNT_SPRITE_SEL_0 = 0x00, SPI_PNT_SPRITE_SEL_1 = 0x01, SPI_PNT_SPRITE_SEL_S = 0x02, SPI_PNT_SPRITE_SEL_T = 0x03, SPI_PNT_SPRITE_SEL_NONE = 0x04, PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, PNT_SPRITE_OVRD_Y_shift = 5, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, PNT_SPRITE_OVRD_Z_shift = 8, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_OVRD_W_mask = 0x07 << 11, PNT_SPRITE_OVRD_W_shift = 11, /* SPI_PNT_SPRITE_SEL_0 = 0x00, */ /* SPI_PNT_SPRITE_SEL_1 = 0x01, */ /* SPI_PNT_SPRITE_SEL_S = 0x02, */ /* SPI_PNT_SPRITE_SEL_T = 0x03, */ /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ PNT_SPRITE_TOP_1_bit = 1 << 14, SPI_INPUT_Z = 0x000286d8, PROVIDE_Z_TO_SPI_bit = 1 << 0, SPI_FOG_CNTL = 0x000286dc, PASS_FOG_THROUGH_PS_bit = 1 << 0, PIXEL_FOG_FUNC_mask = 0x03 << 1, PIXEL_FOG_FUNC_shift = 1, SPI_FOG_NONE = 0x00, SPI_FOG_EXP = 0x01, SPI_FOG_EXP2 = 0x02, SPI_FOG_LINEAR = 0x03, PIXEL_FOG_SRC_SEL_bit = 1 << 3, VS_FOG_CLAMP_DISABLE_bit = 1 << 4, SPI_FOG_FUNC_SCALE = 0x000286e0, SPI_FOG_FUNC_BIAS = 0x000286e4, CB_BLEND0_CONTROL = 0x00028780, CB_BLEND0_CONTROL_num = 8, COLOR_SRCBLEND_mask = 0x1f << 0, COLOR_SRCBLEND_shift = 0, COLOR_COMB_FCN_mask = 0x07 << 5, COLOR_COMB_FCN_shift = 5, COLOR_DESTBLEND_mask = 0x1f << 8, COLOR_DESTBLEND_shift = 8, OPACITY_WEIGHT_bit = 1 << 13, ALPHA_SRCBLEND_mask = 0x1f << 16, ALPHA_SRCBLEND_shift = 16, ALPHA_COMB_FCN_mask = 0x07 << 21, ALPHA_COMB_FCN_shift = 21, ALPHA_DESTBLEND_mask = 0x1f << 24, ALPHA_DESTBLEND_shift = 24, SEPARATE_ALPHA_BLEND_bit = 1 << 29, VGT_DMA_BASE_HI = 0x000287e4, VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, VGT_DMA_BASE = 0x000287e8, VGT_DRAW_INITIATOR = 0x000287f0, SOURCE_SELECT_mask = 0x03 << 0, SOURCE_SELECT_shift = 0, DI_SRC_SEL_DMA = 0x00, DI_SRC_SEL_IMMEDIATE = 0x01, DI_SRC_SEL_AUTO_INDEX = 0x02, DI_SRC_SEL_RESERVED = 0x03, MAJOR_MODE_mask = 0x03 << 2, MAJOR_MODE_shift = 2, DI_MAJOR_MODE_0 = 0x00, DI_MAJOR_MODE_1 = 0x01, SPRITE_EN_bit = 1 << 4, NOT_EOP_bit = 1 << 5, USE_OPAQUE_bit = 1 << 6, VGT_IMMED_DATA = 0x000287f4, VGT_EVENT_ADDRESS_REG = 0x000287f8, ADDRESS_LOW_mask = 0xfffffff << 0, ADDRESS_LOW_shift = 0, DB_DEPTH_CONTROL = 0x00028800, STENCIL_ENABLE_bit = 1 << 0, Z_ENABLE_bit = 1 << 1, Z_WRITE_ENABLE_bit = 1 << 2, ZFUNC_mask = 0x07 << 4, ZFUNC_shift = 4, FRAG_NEVER = 0x00, FRAG_LESS = 0x01, FRAG_EQUAL = 0x02, FRAG_LEQUAL = 0x03, FRAG_GREATER = 0x04, FRAG_NOTEQUAL = 0x05, FRAG_GEQUAL = 0x06, FRAG_ALWAYS = 0x07, BACKFACE_ENABLE_bit = 1 << 7, STENCILFUNC_mask = 0x07 << 8, STENCILFUNC_shift = 8, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_mask = 0x07 << 11, STENCILFAIL_shift = 11, STENCIL_KEEP = 0x00, STENCIL_ZERO = 0x01, STENCIL_REPLACE = 0x02, STENCIL_INCR_CLAMP = 0x03, STENCIL_DECR_CLAMP = 0x04, STENCIL_INVERT = 0x05, STENCIL_INCR_WRAP = 0x06, STENCIL_DECR_WRAP = 0x07, STENCILZPASS_mask = 0x07 << 14, STENCILZPASS_shift = 14, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_mask = 0x07 << 17, STENCILZFAIL_shift = 17, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILFUNC_BF_mask = 0x07 << 20, STENCILFUNC_BF_shift = 20, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ STENCILFAIL_BF_mask = 0x07 << 23, STENCILFAIL_BF_shift = 23, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZPASS_BF_mask = 0x07 << 26, STENCILZPASS_BF_shift = 26, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ STENCILZFAIL_BF_mask = 0x07 << 29, STENCILZFAIL_BF_shift = 29, /* STENCIL_KEEP = 0x00, */ /* STENCIL_ZERO = 0x01, */ /* STENCIL_REPLACE = 0x02, */ /* STENCIL_INCR_CLAMP = 0x03, */ /* STENCIL_DECR_CLAMP = 0x04, */ /* STENCIL_INVERT = 0x05, */ /* STENCIL_INCR_WRAP = 0x06, */ /* STENCIL_DECR_WRAP = 0x07, */ CB_BLEND_CONTROL = 0x00028804, /* COLOR_SRCBLEND_mask = 0x1f << 0, */ /* COLOR_SRCBLEND_shift = 0, */ BLEND_ZERO = 0x00, BLEND_ONE = 0x01, BLEND_SRC_COLOR = 0x02, BLEND_ONE_MINUS_SRC_COLOR = 0x03, BLEND_SRC_ALPHA = 0x04, BLEND_ONE_MINUS_SRC_ALPHA = 0x05, BLEND_DST_ALPHA = 0x06, BLEND_ONE_MINUS_DST_ALPHA = 0x07, BLEND_DST_COLOR = 0x08, BLEND_ONE_MINUS_DST_COLOR = 0x09, BLEND_SRC_ALPHA_SATURATE = 0x0a, BLEND_BOTH_SRC_ALPHA = 0x0b, BLEND_BOTH_INV_SRC_ALPHA = 0x0c, BLEND_CONSTANT_COLOR = 0x0d, BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, BLEND_SRC1_COLOR = 0x0f, BLEND_INV_SRC1_COLOR = 0x10, BLEND_SRC1_ALPHA = 0x11, BLEND_INV_SRC1_ALPHA = 0x12, BLEND_CONSTANT_ALPHA = 0x13, BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, /* COLOR_COMB_FCN_mask = 0x07 << 5, */ /* COLOR_COMB_FCN_shift = 5, */ COMB_DST_PLUS_SRC = 0x00, COMB_SRC_MINUS_DST = 0x01, COMB_MIN_DST_SRC = 0x02, COMB_MAX_DST_SRC = 0x03, COMB_DST_MINUS_SRC = 0x04, /* COLOR_DESTBLEND_mask = 0x1f << 8, */ /* COLOR_DESTBLEND_shift = 8, */ /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ /* OPACITY_WEIGHT_bit = 1 << 13, */ /* ALPHA_SRCBLEND_mask = 0x1f << 16, */ /* ALPHA_SRCBLEND_shift = 16, */ /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ /* ALPHA_COMB_FCN_mask = 0x07 << 21, */ /* ALPHA_COMB_FCN_shift = 21, */ /* COMB_DST_PLUS_SRC = 0x00, */ /* COMB_SRC_MINUS_DST = 0x01, */ /* COMB_MIN_DST_SRC = 0x02, */ /* COMB_MAX_DST_SRC = 0x03, */ /* COMB_DST_MINUS_SRC = 0x04, */ /* ALPHA_DESTBLEND_mask = 0x1f << 24, */ /* ALPHA_DESTBLEND_shift = 24, */ /* BLEND_ZERO = 0x00, */ /* BLEND_ONE = 0x01, */ /* BLEND_SRC_COLOR = 0x02, */ /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ /* BLEND_SRC_ALPHA = 0x04, */ /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ /* BLEND_DST_ALPHA = 0x06, */ /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ /* BLEND_DST_COLOR = 0x08, */ /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ /* BLEND_BOTH_SRC_ALPHA = 0x0b, */ /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ /* BLEND_CONSTANT_COLOR = 0x0d, */ /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ /* BLEND_SRC1_COLOR = 0x0f, */ /* BLEND_INV_SRC1_COLOR = 0x10, */ /* BLEND_SRC1_ALPHA = 0x11, */ /* BLEND_INV_SRC1_ALPHA = 0x12, */ /* BLEND_CONSTANT_ALPHA = 0x13, */ /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ /* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */ CB_COLOR_CONTROL = 0x00028808, FOG_ENABLE_bit = 1 << 0, MULTIWRITE_ENABLE_bit = 1 << 1, DITHER_ENABLE_bit = 1 << 2, DEGAMMA_ENABLE_bit = 1 << 3, SPECIAL_OP_mask = 0x07 << 4, SPECIAL_OP_shift = 4, SPECIAL_NORMAL = 0x00, SPECIAL_DISABLE = 0x01, SPECIAL_FAST_CLEAR = 0x02, SPECIAL_FORCE_CLEAR = 0x03, SPECIAL_EXPAND_COLOR = 0x04, SPECIAL_EXPAND_TEXTURE = 0x05, SPECIAL_EXPAND_SAMPLES = 0x06, SPECIAL_RESOLVE_BOX = 0x07, PER_MRT_BLEND_bit = 1 << 7, TARGET_BLEND_ENABLE_mask = 0xff << 8, TARGET_BLEND_ENABLE_shift = 8, ROP3_mask = 0xff << 16, ROP3_shift = 16, DB_SHADER_CONTROL = 0x0002880c, Z_EXPORT_ENABLE_bit = 1 << 0, STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, Z_ORDER_mask = 0x03 << 4, Z_ORDER_shift = 4, LATE_Z = 0x00, EARLY_Z_THEN_LATE_Z = 0x01, RE_Z = 0x02, EARLY_Z_THEN_RE_Z = 0x03, KILL_ENABLE_bit = 1 << 6, COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, MASK_EXPORT_ENABLE_bit = 1 << 8, DUAL_EXPORT_ENABLE_bit = 1 << 9, EXEC_ON_HIER_FAIL_bit = 1 << 10, EXEC_ON_NOOP_bit = 1 << 11, PA_CL_CLIP_CNTL = 0x00028810, UCP_ENA_0_bit = 1 << 0, UCP_ENA_1_bit = 1 << 1, UCP_ENA_2_bit = 1 << 2, UCP_ENA_3_bit = 1 << 3, UCP_ENA_4_bit = 1 << 4, UCP_ENA_5_bit = 1 << 5, PS_UCP_Y_SCALE_NEG_bit = 1 << 13, PS_UCP_MODE_mask = 0x03 << 14, PS_UCP_MODE_shift = 14, CLIP_DISABLE_bit = 1 << 16, UCP_CULL_ONLY_ENA_bit = 1 << 17, BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, DX_CLIP_SPACE_DEF_bit = 1 << 19, DIS_CLIP_ERR_DETECT_bit = 1 << 20, VTX_KILL_OR_bit = 1 << 21, DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, ZCLIP_NEAR_DISABLE_bit = 1 << 26, ZCLIP_FAR_DISABLE_bit = 1 << 27, PA_SU_SC_MODE_CNTL = 0x00028814, CULL_FRONT_bit = 1 << 0, CULL_BACK_bit = 1 << 1, FACE_bit = 1 << 2, POLY_MODE_mask = 0x03 << 3, POLY_MODE_shift = 3, X_DISABLE_POLY_MODE = 0x00, X_DUAL_MODE = 0x01, POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, POLYMODE_FRONT_PTYPE_shift = 5, X_DRAW_POINTS = 0x00, X_DRAW_LINES = 0x01, X_DRAW_TRIANGLES = 0x02, POLYMODE_BACK_PTYPE_mask = 0x07 << 8, POLYMODE_BACK_PTYPE_shift = 8, /* X_DRAW_POINTS = 0x00, */ /* X_DRAW_LINES = 0x01, */ /* X_DRAW_TRIANGLES = 0x02, */ POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, PROVOKING_VTX_LAST_bit = 1 << 19, PERSP_CORR_DIS_bit = 1 << 20, MULTI_PRIM_IB_ENA_bit = 1 << 21, PA_CL_VTE_CNTL = 0x00028818, VPORT_X_SCALE_ENA_bit = 1 << 0, VPORT_X_OFFSET_ENA_bit = 1 << 1, VPORT_Y_SCALE_ENA_bit = 1 << 2, VPORT_Y_OFFSET_ENA_bit = 1 << 3, VPORT_Z_SCALE_ENA_bit = 1 << 4, VPORT_Z_OFFSET_ENA_bit = 1 << 5, VTX_XY_FMT_bit = 1 << 8, VTX_Z_FMT_bit = 1 << 9, VTX_W0_FMT_bit = 1 << 10, PERFCOUNTER_REF_bit = 1 << 11, PA_CL_VS_OUT_CNTL = 0x0002881c, CLIP_DIST_ENA_0_bit = 1 << 0, CLIP_DIST_ENA_1_bit = 1 << 1, CLIP_DIST_ENA_2_bit = 1 << 2, CLIP_DIST_ENA_3_bit = 1 << 3, CLIP_DIST_ENA_4_bit = 1 << 4, CLIP_DIST_ENA_5_bit = 1 << 5, CLIP_DIST_ENA_6_bit = 1 << 6, CLIP_DIST_ENA_7_bit = 1 << 7, CULL_DIST_ENA_0_bit = 1 << 8, CULL_DIST_ENA_1_bit = 1 << 9, CULL_DIST_ENA_2_bit = 1 << 10, CULL_DIST_ENA_3_bit = 1 << 11, CULL_DIST_ENA_4_bit = 1 << 12, CULL_DIST_ENA_5_bit = 1 << 13, CULL_DIST_ENA_6_bit = 1 << 14, CULL_DIST_ENA_7_bit = 1 << 15, USE_VTX_POINT_SIZE_bit = 1 << 16, USE_VTX_EDGE_FLAG_bit = 1 << 17, USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, USE_VTX_VIEWPORT_INDX_bit = 1 << 19, USE_VTX_KILL_FLAG_bit = 1 << 20, VS_OUT_MISC_VEC_ENA_bit = 1 << 21, VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, PA_CL_NANINF_CNTL = 0x00028820, VTE_XY_INF_DISCARD_bit = 1 << 0, VTE_Z_INF_DISCARD_bit = 1 << 1, VTE_W_INF_DISCARD_bit = 1 << 2, VTE_0XNANINF_IS_0_bit = 1 << 3, VTE_XY_NAN_RETAIN_bit = 1 << 4, VTE_Z_NAN_RETAIN_bit = 1 << 5, VTE_W_NAN_RETAIN_bit = 1 << 6, VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, VS_XY_NAN_TO_INF_bit = 1 << 8, VS_XY_INF_RETAIN_bit = 1 << 9, VS_Z_NAN_TO_INF_bit = 1 << 10, VS_Z_INF_RETAIN_bit = 1 << 11, VS_W_NAN_TO_INF_bit = 1 << 12, VS_W_INF_RETAIN_bit = 1 << 13, VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, SQ_PGM_START_PS = 0x00028840, SQ_PGM_RESOURCES_PS = 0x00028850, NUM_GPRS_mask = 0xff << 0, NUM_GPRS_shift = 0, STACK_SIZE_mask = 0xff << 8, STACK_SIZE_shift = 8, SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21, FETCH_CACHE_LINES_mask = 0x07 << 24, FETCH_CACHE_LINES_shift = 24, UNCACHED_FIRST_INST_bit = 1 << 28, CLAMP_CONSTS_bit = 1 << 31, SQ_PGM_EXPORTS_PS = 0x00028854, EXPORT_MODE_mask = 0x1f << 0, EXPORT_MODE_shift = 0, SQ_PGM_START_VS = 0x00028858, SQ_PGM_RESOURCES_VS = 0x00028868, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21, /* FETCH_CACHE_LINES_mask = 0x07 << 24, */ /* FETCH_CACHE_LINES_shift = 24, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_START_GS = 0x0002886c, SQ_PGM_RESOURCES_GS = 0x0002887c, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21, /* FETCH_CACHE_LINES_mask = 0x07 << 24, */ /* FETCH_CACHE_LINES_shift = 24, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_START_ES = 0x00028880, SQ_PGM_RESOURCES_ES = 0x00028890, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21, /* FETCH_CACHE_LINES_mask = 0x07 << 24, */ /* FETCH_CACHE_LINES_shift = 24, */ /* UNCACHED_FIRST_INST_bit = 1 << 28, */ SQ_PGM_START_FS = 0x00028894, SQ_PGM_RESOURCES_FS = 0x000288a4, /* NUM_GPRS_mask = 0xff << 0, */ /* NUM_GPRS_shift = 0, */ /* STACK_SIZE_mask = 0xff << 8, */ /* STACK_SIZE_shift = 8, */ SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21, SQ_ESGS_RING_ITEMSIZE = 0x000288a8, ITEMSIZE_mask = 0x7fff << 0, ITEMSIZE_shift = 0, SQ_GSVS_RING_ITEMSIZE = 0x000288ac, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_ESTMP_RING_ITEMSIZE = 0x000288b0, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GSTMP_RING_ITEMSIZE = 0x000288b4, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_VSTMP_RING_ITEMSIZE = 0x000288b8, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PSTMP_RING_ITEMSIZE = 0x000288bc, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_FBUF_RING_ITEMSIZE = 0x000288c0, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_REDUC_RING_ITEMSIZE = 0x000288c4, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_GS_VERT_ITEMSIZE = 0x000288c8, /* ITEMSIZE_mask = 0x7fff << 0, */ /* ITEMSIZE_shift = 0, */ SQ_PGM_CF_OFFSET_PS = 0x000288cc, PGM_CF_OFFSET_mask = 0xfffff << 0, PGM_CF_OFFSET_shift = 0, SQ_PGM_CF_OFFSET_VS = 0x000288d0, /* PGM_CF_OFFSET_mask = 0xfffff << 0, */ /* PGM_CF_OFFSET_shift = 0, */ SQ_PGM_CF_OFFSET_GS = 0x000288d4, /* PGM_CF_OFFSET_mask = 0xfffff << 0, */ /* PGM_CF_OFFSET_shift = 0, */ SQ_PGM_CF_OFFSET_ES = 0x000288d8, /* PGM_CF_OFFSET_mask = 0xfffff << 0, */ /* PGM_CF_OFFSET_shift = 0, */ SQ_PGM_CF_OFFSET_FS = 0x000288dc, /* PGM_CF_OFFSET_mask = 0xfffff << 0, */ /* PGM_CF_OFFSET_shift = 0, */ SQ_VTX_SEMANTIC_CLEAR = 0x000288e0, SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, SQ_ALU_CONST_CACHE_PS_0_num = 16, SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, SQ_ALU_CONST_CACHE_VS_0_num = 16, SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, SQ_ALU_CONST_CACHE_GS_0_num = 16, PA_SU_POINT_SIZE = 0x00028a00, PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0, PA_SU_POINT_SIZE__HEIGHT_shift = 0, PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, PA_SU_POINT_SIZE__WIDTH_shift = 16, PA_SU_POINT_MINMAX = 0x00028a04, MIN_SIZE_mask = 0xffff << 0, MIN_SIZE_shift = 0, MAX_SIZE_mask = 0xffff << 16, MAX_SIZE_shift = 16, PA_SU_LINE_CNTL = 0x00028a08, PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, PA_SU_LINE_CNTL__WIDTH_shift = 0, PA_SC_LINE_STIPPLE = 0x00028a0c, LINE_PATTERN_mask = 0xffff << 0, LINE_PATTERN_shift = 0, REPEAT_COUNT_mask = 0xff << 16, REPEAT_COUNT_shift = 16, PATTERN_BIT_ORDER_bit = 1 << 28, AUTO_RESET_CNTL_mask = 0x03 << 29, AUTO_RESET_CNTL_shift = 29, VGT_OUTPUT_PATH_CNTL = 0x00028a10, PATH_SELECT_mask = 0x03 << 0, PATH_SELECT_shift = 0, VGT_OUTPATH_VTX_REUSE = 0x00, VGT_OUTPATH_TESS_EN = 0x01, VGT_OUTPATH_PASSTHRU = 0x02, VGT_OUTPATH_GS_BLOCK = 0x03, VGT_HOS_CNTL = 0x00028a14, TESS_MODE_mask = 0x03 << 0, TESS_MODE_shift = 0, VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, VGT_HOS_REUSE_DEPTH = 0x00028a20, REUSE_DEPTH_mask = 0xff << 0, REUSE_DEPTH_shift = 0, VGT_GROUP_PRIM_TYPE = 0x00028a24, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, VGT_GRP_3D_POINT = 0x00, VGT_GRP_3D_LINE = 0x01, VGT_GRP_3D_TRI = 0x02, VGT_GRP_3D_RECT = 0x03, VGT_GRP_3D_QUAD = 0x04, VGT_GRP_2D_COPY_RECT_V0 = 0x05, VGT_GRP_2D_COPY_RECT_V1 = 0x06, VGT_GRP_2D_COPY_RECT_V2 = 0x07, VGT_GRP_2D_COPY_RECT_V3 = 0x08, VGT_GRP_2D_FILL_RECT = 0x09, VGT_GRP_2D_LINE = 0x0a, VGT_GRP_2D_TRI = 0x0b, VGT_GRP_PRIM_INDEX_LINE = 0x0c, VGT_GRP_PRIM_INDEX_TRI = 0x0d, VGT_GRP_PRIM_INDEX_QUAD = 0x0e, VGT_GRP_3D_LINE_ADJ = 0x0f, VGT_GRP_3D_TRI_ADJ = 0x10, RETAIN_ORDER_bit = 1 << 14, RETAIN_QUADS_bit = 1 << 15, PRIM_ORDER_mask = 0x07 << 16, PRIM_ORDER_shift = 16, VGT_GRP_LIST = 0x00, VGT_GRP_STRIP = 0x01, VGT_GRP_FAN = 0x02, VGT_GRP_LOOP = 0x03, VGT_GRP_POLYGON = 0x04, VGT_GROUP_FIRST_DECR = 0x00028a28, FIRST_DECR_mask = 0x0f << 0, FIRST_DECR_shift = 0, VGT_GROUP_DECR = 0x00028a2c, DECR_mask = 0x0f << 0, DECR_shift = 0, VGT_GROUP_VECT_0_CNTL = 0x00028a30, COMP_X_EN_bit = 1 << 0, COMP_Y_EN_bit = 1 << 1, COMP_Z_EN_bit = 1 << 2, COMP_W_EN_bit = 1 << 3, VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, SHIFT_mask = 0xff << 16, SHIFT_shift = 16, VGT_GROUP_VECT_1_CNTL = 0x00028a34, /* COMP_X_EN_bit = 1 << 0, */ /* COMP_Y_EN_bit = 1 << 1, */ /* COMP_Z_EN_bit = 1 << 2, */ /* COMP_W_EN_bit = 1 << 3, */ VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, /* SHIFT_mask = 0xff << 16, */ /* SHIFT_shift = 16, */ VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, X_CONV_mask = 0x0f << 0, X_CONV_shift = 0, VGT_GRP_INDEX_16 = 0x00, VGT_GRP_INDEX_32 = 0x01, VGT_GRP_UINT_16 = 0x02, VGT_GRP_UINT_32 = 0x03, VGT_GRP_SINT_16 = 0x04, VGT_GRP_SINT_32 = 0x05, VGT_GRP_FLOAT_32 = 0x06, VGT_GRP_AUTO_PRIM = 0x07, VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, X_OFFSET_mask = 0x0f << 4, X_OFFSET_shift = 4, Y_CONV_mask = 0x0f << 8, Y_CONV_shift = 8, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Y_OFFSET_mask = 0x0f << 12, Y_OFFSET_shift = 12, Z_CONV_mask = 0x0f << 16, Z_CONV_shift = 16, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ Z_OFFSET_mask = 0x0f << 20, Z_OFFSET_shift = 20, W_CONV_mask = 0x0f << 24, W_CONV_shift = 24, /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ W_OFFSET_mask = 0x0f << 28, W_OFFSET_shift = 28, VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, /* X_CONV_mask = 0x0f << 0, */ /* X_CONV_shift = 0, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* X_OFFSET_mask = 0x0f << 4, */ /* X_OFFSET_shift = 4, */ /* Y_CONV_mask = 0x0f << 8, */ /* Y_CONV_shift = 8, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Y_OFFSET_mask = 0x0f << 12, */ /* Y_OFFSET_shift = 12, */ /* Z_CONV_mask = 0x0f << 16, */ /* Z_CONV_shift = 16, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* Z_OFFSET_mask = 0x0f << 20, */ /* Z_OFFSET_shift = 20, */ /* W_CONV_mask = 0x0f << 24, */ /* W_CONV_shift = 24, */ /* VGT_GRP_INDEX_16 = 0x00, */ /* VGT_GRP_INDEX_32 = 0x01, */ /* VGT_GRP_UINT_16 = 0x02, */ /* VGT_GRP_UINT_32 = 0x03, */ /* VGT_GRP_SINT_16 = 0x04, */ /* VGT_GRP_SINT_32 = 0x05, */ /* VGT_GRP_FLOAT_32 = 0x06, */ /* VGT_GRP_AUTO_PRIM = 0x07, */ /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ /* W_OFFSET_mask = 0x0f << 28, */ /* W_OFFSET_shift = 28, */ VGT_GS_MODE = 0x00028a40, MODE_mask = 0x03 << 0, MODE_shift = 0, GS_OFF = 0x00, GS_SCENARIO_A = 0x01, GS_SCENARIO_B = 0x02, GS_SCENARIO_G = 0x03, ES_PASSTHRU_bit = 1 << 2, CUT_MODE_mask = 0x03 << 3, CUT_MODE_shift = 3, GS_CUT_1024 = 0x00, GS_CUT_512 = 0x01, GS_CUT_256 = 0x02, GS_CUT_128 = 0x03, PA_SC_MPASS_PS_CNTL = 0x00028a48, MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0, MPASS_PIX_VEC_PER_PASS_shift = 0, MPASS_PS_ENA_bit = 1 << 31, PA_SC_MODE_CNTL = 0x00028a4c, MSAA_ENABLE_bit = 1 << 0, CLIPRECT_ENABLE_bit = 1 << 1, LINE_STIPPLE_ENABLE_bit = 1 << 2, MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3, WALK_ORDER_ENABLE_bit = 1 << 4, HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5, WALK_SIZE_bit = 1 << 6, WALK_ALIGNMENT_bit = 1 << 7, WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8, TILE_COVER_NO_SCISSOR_bit = 1 << 9, KILL_PIX_POST_HI_Z_bit = 1 << 10, KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11, MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12, TILE_COVER_DISABLE_bit = 1 << 13, FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14, FORCE_EOV_TILE_ENABLE_bit = 1 << 15, FORCE_EOV_REZ_ENABLE_bit = 1 << 16, PS_ITER_SAMPLE_bit = 1 << 17, VGT_ENHANCE = 0x00028a50, VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0, VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0, X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00, X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01, X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02, X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03, MISC_mask = 0x3fffffff << 2, MISC_shift = 2, VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, OUTPRIM_TYPE_mask = 0x3f << 0, OUTPRIM_TYPE_shift = 0, POINTLIST = 0x00, LINESTRIP = 0x01, TRISTRIP = 0x02, VGT_DMA_SIZE = 0x00028a74, VGT_DMA_INDEX_TYPE = 0x00028a7c, /* INDEX_TYPE_mask = 0x03 << 0, */ /* INDEX_TYPE_shift = 0, */ VGT_INDEX_16 = 0x00, VGT_INDEX_32 = 0x01, SWAP_MODE_mask = 0x03 << 2, SWAP_MODE_shift = 2, VGT_DMA_SWAP_NONE = 0x00, VGT_DMA_SWAP_16_BIT = 0x01, VGT_DMA_SWAP_32_BIT = 0x02, VGT_DMA_SWAP_WORD = 0x03, VGT_PRIMITIVEID_EN = 0x00028a84, PRIMITIVEID_EN_bit = 1 << 0, VGT_DMA_NUM_INSTANCES = 0x00028a88, VGT_EVENT_INITIATOR = 0x00028a90, EVENT_TYPE_mask = 0x3f << 0, EVENT_TYPE_shift = 0, CACHE_FLUSH_TS = 0x04, CONTEXT_DONE = 0x05, CACHE_FLUSH = 0x06, VIZQUERY_START = 0x07, VIZQUERY_END = 0x08, SC_WAIT_WC = 0x09, MPASS_PS_CP_REFETCH = 0x0a, MPASS_PS_RST_START = 0x0b, MPASS_PS_INCR_START = 0x0c, RST_PIX_CNT = 0x0d, RST_VTX_CNT = 0x0e, VS_PARTIAL_FLUSH = 0x0f, PS_PARTIAL_FLUSH = 0x10, CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, ZPASS_DONE = 0x15, CACHE_FLUSH_AND_INV_EVENT = 0x16, PERFCOUNTER_START = 0x17, PERFCOUNTER_STOP = 0x18, PIPELINESTAT_START = 0x19, PIPELINESTAT_STOP = 0x1a, PERFCOUNTER_SAMPLE = 0x1b, FLUSH_ES_OUTPUT = 0x1c, FLUSH_GS_OUTPUT = 0x1d, SAMPLE_PIPELINESTAT = 0x1e, SO_VGTSTREAMOUT_FLUSH = 0x1f, SAMPLE_STREAMOUTSTATS = 0x20, RESET_VTX_CNT = 0x21, BLOCK_CONTEXT_DONE = 0x22, CR_CONTEXT_DONE = 0x23, VGT_FLUSH = 0x24, CR_DONE_TS = 0x25, SQ_NON_EVENT = 0x26, SC_SEND_DB_VPZ = 0x27, BOTTOM_OF_PIPE_TS = 0x28, DB_CACHE_FLUSH_AND_INV = 0x2a, ADDRESS_HI_mask = 0xff << 19, ADDRESS_HI_shift = 19, EXTENDED_EVENT_bit = 1 << 27, VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, RESET_EN_bit = 1 << 0, VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, VGT_STRMOUT_EN = 0x00028ab0, STREAMOUT_bit = 1 << 0, VGT_REUSE_OFF = 0x00028ab4, REUSE_OFF_bit = 1 << 0, VGT_VTX_CNT_EN = 0x00028ab8, VTX_CNT_EN_bit = 1 << 0, VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, VGT_STRMOUT_BUFFER_EN = 0x00028b20, BUFFER_0_EN_bit = 1 << 0, BUFFER_1_EN_bit = 1 << 1, BUFFER_2_EN_bit = 1 << 2, BUFFER_3_EN_bit = 1 << 3, VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, PA_SC_LINE_CNTL = 0x00028c00, BRES_CNTL_mask = 0xff << 0, BRES_CNTL_shift = 0, USE_BRES_CNTL_bit = 1 << 8, EXPAND_LINE_WIDTH_bit = 1 << 9, LAST_PIXEL_bit = 1 << 10, PA_SC_AA_CONFIG = 0x00028c04, MSAA_NUM_SAMPLES_mask = 0x03 << 0, MSAA_NUM_SAMPLES_shift = 0, AA_MASK_CENTROID_DTMN_bit = 1 << 4, MAX_SAMPLE_DIST_mask = 0x0f << 13, MAX_SAMPLE_DIST_shift = 13, PA_SU_VTX_CNTL = 0x00028c08, PIX_CENTER_bit = 1 << 0, PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, X_TRUNCATE = 0x00, X_ROUND = 0x01, X_ROUND_TO_EVEN = 0x02, X_ROUND_TO_ODD = 0x03, QUANT_MODE_mask = 0x07 << 3, QUANT_MODE_shift = 3, X_1_16TH = 0x00, X_1_8TH = 0x01, X_1_4TH = 0x02, X_1_2 = 0x03, X_1 = 0x04, X_1_256TH = 0x05, PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c, PA_CL_GB_VERT_DISC_ADJ = 0x00028c10, PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14, PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18, PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c, /* S0_X_mask = 0x0f << 0, */ /* S0_X_shift = 0, */ /* S0_Y_mask = 0x0f << 4, */ /* S0_Y_shift = 4, */ /* S1_X_mask = 0x0f << 8, */ /* S1_X_shift = 8, */ /* S1_Y_mask = 0x0f << 12, */ /* S1_Y_shift = 12, */ /* S2_X_mask = 0x0f << 16, */ /* S2_X_shift = 16, */ /* S2_Y_mask = 0x0f << 20, */ /* S2_Y_shift = 20, */ /* S3_X_mask = 0x0f << 24, */ /* S3_X_shift = 24, */ /* S3_Y_mask = 0x0f << 28, */ /* S3_Y_shift = 28, */ PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20, /* S4_X_mask = 0x0f << 0, */ /* S4_X_shift = 0, */ /* S4_Y_mask = 0x0f << 4, */ /* S4_Y_shift = 4, */ /* S5_X_mask = 0x0f << 8, */ /* S5_X_shift = 8, */ /* S5_Y_mask = 0x0f << 12, */ /* S5_Y_shift = 12, */ /* S6_X_mask = 0x0f << 16, */ /* S6_X_shift = 16, */ /* S6_Y_mask = 0x0f << 20, */ /* S6_Y_shift = 20, */ /* S7_X_mask = 0x0f << 24, */ /* S7_X_shift = 24, */ /* S7_Y_mask = 0x0f << 28, */ /* S7_Y_shift = 28, */ CB_CLRCMP_CONTROL = 0x00028c30, CLRCMP_FCN_SRC_mask = 0x07 << 0, CLRCMP_FCN_SRC_shift = 0, CLRCMP_DRAW_ALWAYS = 0x00, CLRCMP_DRAW_NEVER = 0x01, CLRCMP_DRAW_ON_NEQ = 0x04, CLRCMP_DRAW_ON_EQ = 0x05, CLRCMP_FCN_DST_mask = 0x07 << 8, CLRCMP_FCN_DST_shift = 8, /* CLRCMP_DRAW_ALWAYS = 0x00, */ /* CLRCMP_DRAW_NEVER = 0x01, */ /* CLRCMP_DRAW_ON_NEQ = 0x04, */ /* CLRCMP_DRAW_ON_EQ = 0x05, */ CLRCMP_FCN_SEL_mask = 0x03 << 24, CLRCMP_FCN_SEL_shift = 24, CLRCMP_SEL_DST = 0x00, CLRCMP_SEL_SRC = 0x01, CLRCMP_SEL_AND = 0x02, CB_CLRCMP_SRC = 0x00028c34, CB_CLRCMP_DST = 0x00028c38, CB_CLRCMP_MSK = 0x00028c3c, PA_SC_AA_MASK = 0x00028c48, VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, VTX_REUSE_DEPTH_mask = 0xff << 0, VTX_REUSE_DEPTH_shift = 0, VGT_OUT_DEALLOC_CNTL = 0x00028c5c, DEALLOC_DIST_mask = 0x7f << 0, DEALLOC_DIST_shift = 0, DB_RENDER_CONTROL = 0x00028d0c, DEPTH_CLEAR_ENABLE_bit = 1 << 0, STENCIL_CLEAR_ENABLE_bit = 1 << 1, DEPTH_COPY_bit = 1 << 2, STENCIL_COPY_bit = 1 << 3, RESUMMARIZE_ENABLE_bit = 1 << 4, STENCIL_COMPRESS_DISABLE_bit = 1 << 5, DEPTH_COMPRESS_DISABLE_bit = 1 << 6, COPY_CENTROID_bit = 1 << 7, COPY_SAMPLE_mask = 0x07 << 8, COPY_SAMPLE_shift = 8, ZPASS_INCREMENT_DISABLE_bit = 1 << 11, DB_RENDER_OVERRIDE = 0x00028d10, FORCE_HIZ_ENABLE_mask = 0x03 << 0, FORCE_HIZ_ENABLE_shift = 0, FORCE_OFF = 0x00, FORCE_ENABLE = 0x01, FORCE_DISABLE = 0x02, FORCE_RESERVED = 0x03, FORCE_HIS_ENABLE0_mask = 0x03 << 2, FORCE_HIS_ENABLE0_shift = 2, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_HIS_ENABLE1_mask = 0x03 << 4, FORCE_HIS_ENABLE1_shift = 4, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_SHADER_Z_ORDER_bit = 1 << 6, FAST_Z_DISABLE_bit = 1 << 7, FAST_STENCIL_DISABLE_bit = 1 << 8, NOOP_CULL_DISABLE_bit = 1 << 9, FORCE_COLOR_KILL_bit = 1 << 10, FORCE_Z_READ_bit = 1 << 11, FORCE_STENCIL_READ_bit = 1 << 12, FORCE_FULL_Z_RANGE_mask = 0x03 << 13, FORCE_FULL_Z_RANGE_shift = 13, /* FORCE_OFF = 0x00, */ /* FORCE_ENABLE = 0x01, */ /* FORCE_DISABLE = 0x02, */ /* FORCE_RESERVED = 0x03, */ FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, IGNORE_SC_ZRANGE_bit = 1 << 17, DB_HTILE_SURFACE = 0x00028d24, HTILE_WIDTH_bit = 1 << 0, HTILE_HEIGHT_bit = 1 << 1, LINEAR_bit = 1 << 2, FULL_CACHE_bit = 1 << 3, HTILE_USES_PRELOAD_WIN_bit = 1 << 4, PRELOAD_bit = 1 << 5, PREFETCH_WIDTH_mask = 0x3f << 6, PREFETCH_WIDTH_shift = 6, PREFETCH_HEIGHT_mask = 0x3f << 12, PREFETCH_HEIGHT_shift = 12, DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, COMPAREFUNC1_mask = 0x07 << 0, COMPAREFUNC1_shift = 0, /* REF_NEVER = 0x00, */ /* REF_LESS = 0x01, */ /* REF_EQUAL = 0x02, */ /* REF_LEQUAL = 0x03, */ /* REF_GREATER = 0x04, */ /* REF_NOTEQUAL = 0x05, */ /* REF_GEQUAL = 0x06, */ /* REF_ALWAYS = 0x07, */ COMPAREVALUE1_mask = 0xff << 4, COMPAREVALUE1_shift = 4, COMPAREMASK1_mask = 0xff << 12, COMPAREMASK1_shift = 12, ENABLE1_bit = 1 << 24, DB_PRELOAD_CONTROL = 0x00028d30, START_X_mask = 0xff << 0, START_X_shift = 0, START_Y_mask = 0xff << 8, START_Y_shift = 8, MAX_X_mask = 0xff << 16, MAX_X_shift = 16, MAX_Y_mask = 0xff << 24, MAX_Y_shift = 24, DB_PREFETCH_LIMIT = 0x00028d34, DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0, DEPTH_HEIGHT_TILE_MAX_shift = 0, PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8, POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc, PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00, PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04, PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08, PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c, PA_CL_POINT_X_RAD = 0x00028e10, PA_CL_POINT_Y_RAD = 0x00028e14, PA_CL_POINT_SIZE = 0x00028e18, PA_CL_POINT_CULL_RAD = 0x00028e1c, PA_CL_UCP_0_X = 0x00028e20, PA_CL_UCP_0_X_num = 6, PA_CL_UCP_0_X_offset = 16, PA_CL_UCP_0_Y = 0x00028e24, PA_CL_UCP_0_Y_num = 6, PA_CL_UCP_0_Y_offset = 16, PA_CL_UCP_0_Z = 0x00028e28, PA_CL_UCP_0_Z_num = 6, PA_CL_UCP_0_Z_offset = 16, SQ_ALU_CONSTANT0_0 = 0x00030000, SQ_ALU_CONSTANT1_0 = 0x00030004, SQ_ALU_CONSTANT2_0 = 0x00030008, SQ_ALU_CONSTANT3_0 = 0x0003000c, SQ_VTX_CONSTANT_WORD0_0 = 0x00038000, SQ_TEX_RESOURCE_WORD0_0 = 0x00038000, DIM_mask = 0x07 << 0, DIM_shift = 0, SQ_TEX_DIM_1D = 0x00, SQ_TEX_DIM_2D = 0x01, SQ_TEX_DIM_3D = 0x02, SQ_TEX_DIM_CUBEMAP = 0x03, SQ_TEX_DIM_1D_ARRAY = 0x04, SQ_TEX_DIM_2D_ARRAY = 0x05, SQ_TEX_DIM_2D_MSAA = 0x06, SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3, TILE_TYPE_bit = 1 << 7, PITCH_mask = 0x7ff << 8, PITCH_shift = 8, TEX_WIDTH_mask = 0x1fff << 19, TEX_WIDTH_shift = 19, SQ_VTX_CONSTANT_WORD1_0 = 0x00038004, SQ_TEX_RESOURCE_WORD1_0 = 0x00038004, TEX_HEIGHT_mask = 0x1fff << 0, TEX_HEIGHT_shift = 0, TEX_DEPTH_mask = 0x1fff << 13, TEX_DEPTH_shift = 13, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26, SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, BASE_ADDRESS_HI_mask = 0xff << 0, BASE_ADDRESS_HI_shift = 0, SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ SQ_TEX_RESOURCE_WORD2_0 = 0x00038008, SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c, MEM_REQUEST_SIZE_mask = 0x03 << 0, MEM_REQUEST_SIZE_shift = 0, SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c, SQ_TEX_RESOURCE_WORD4_0 = 0x00038010, FORMAT_COMP_X_mask = 0x03 << 0, FORMAT_COMP_X_shift = 0, SQ_FORMAT_COMP_UNSIGNED = 0x00, SQ_FORMAT_COMP_SIGNED = 0x01, SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, FORMAT_COMP_Y_mask = 0x03 << 2, FORMAT_COMP_Y_shift = 2, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_Z_mask = 0x03 << 4, FORMAT_COMP_Z_shift = 4, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ FORMAT_COMP_W_mask = 0x03 << 6, FORMAT_COMP_W_shift = 6, /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ /* SQ_FORMAT_COMP_SIGNED = 0x01, */ /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, /* SQ_NUM_FORMAT_NORM = 0x00, */ /* SQ_NUM_FORMAT_INT = 0x01, */ /* SQ_NUM_FORMAT_SCALED = 0x02, */ SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, /* SQ_ENDIAN_NONE = 0x00, */ /* SQ_ENDIAN_8IN16 = 0x01, */ /* SQ_ENDIAN_8IN32 = 0x02, */ REQUEST_SIZE_mask = 0x03 << 14, REQUEST_SIZE_shift = 14, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, /* SQ_SEL_X = 0x00, */ /* SQ_SEL_Y = 0x01, */ /* SQ_SEL_Z = 0x02, */ /* SQ_SEL_W = 0x03, */ /* SQ_SEL_0 = 0x04, */ /* SQ_SEL_1 = 0x05, */ BASE_LEVEL_mask = 0x0f << 28, BASE_LEVEL_shift = 28, SQ_TEX_RESOURCE_WORD5_0 = 0x00038014, LAST_LEVEL_mask = 0x0f << 0, LAST_LEVEL_shift = 0, BASE_ARRAY_mask = 0x1fff << 4, BASE_ARRAY_shift = 4, LAST_ARRAY_mask = 0x1fff << 17, LAST_ARRAY_shift = 17, SQ_TEX_RESOURCE_WORD6_0 = 0x00038018, MPEG_CLAMP_mask = 0x03 << 0, MPEG_CLAMP_shift = 0, SQ_TEX_MPEG_CLAMP_OFF = 0x00, SQ_TEX_MPEG_9 = 0x01, SQ_TEX_MPEG_10 = 0x02, PERF_MODULATION_mask = 0x07 << 5, PERF_MODULATION_shift = 5, INTERLACED_bit = 1 << 8, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30, SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30, SQ_TEX_VTX_INVALID_TEXTURE = 0x00, SQ_TEX_VTX_INVALID_BUFFER = 0x01, SQ_TEX_VTX_VALID_TEXTURE = 0x02, SQ_TEX_VTX_VALID_BUFFER = 0x03, SQ_VTX_CONSTANT_WORD6_0 = 0x00038018, SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30, SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30, /* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ /* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ /* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ /* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, SQ_TEX_WRAP = 0x00, SQ_TEX_MIRROR = 0x01, SQ_TEX_CLAMP_LAST_TEXEL = 0x02, SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, SQ_TEX_CLAMP_HALF_BORDER = 0x04, SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, SQ_TEX_CLAMP_BORDER = 0x06, SQ_TEX_MIRROR_ONCE_BORDER = 0x07, CLAMP_Y_mask = 0x07 << 3, CLAMP_Y_shift = 3, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ CLAMP_Z_mask = 0x07 << 6, CLAMP_Z_shift = 6, /* SQ_TEX_WRAP = 0x00, */ /* SQ_TEX_MIRROR = 0x01, */ /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ /* SQ_TEX_CLAMP_BORDER = 0x06, */ /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ XY_MAG_FILTER_mask = 0x07 << 9, XY_MAG_FILTER_shift = 9, SQ_TEX_XY_FILTER_POINT = 0x00, SQ_TEX_XY_FILTER_BILINEAR = 0x01, SQ_TEX_XY_FILTER_BICUBIC = 0x02, XY_MIN_FILTER_mask = 0x07 << 12, XY_MIN_FILTER_shift = 12, /* SQ_TEX_XY_FILTER_POINT = 0x00, */ /* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ /* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */ Z_FILTER_mask = 0x03 << 15, Z_FILTER_shift = 15, SQ_TEX_Z_FILTER_NONE = 0x00, SQ_TEX_Z_FILTER_POINT = 0x01, SQ_TEX_Z_FILTER_LINEAR = 0x02, MIP_FILTER_mask = 0x03 << 17, MIP_FILTER_shift = 17, /* SQ_TEX_Z_FILTER_NONE = 0x00, */ /* SQ_TEX_Z_FILTER_POINT = 0x01, */ /* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ BORDER_COLOR_TYPE_mask = 0x03 << 22, BORDER_COLOR_TYPE_shift = 22, SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, SQ_TEX_BORDER_COLOR_REGISTER = 0x03, POINT_SAMPLING_CLAMP_bit = 1 << 24, TEX_ARRAY_OVERRIDE_bit = 1 << 25, DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26, DEPTH_COMPARE_FUNCTION_shift = 26, SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, SQ_TEX_DEPTH_COMPARE_LESS = 0x01, SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, CHROMA_KEY_mask = 0x03 << 29, CHROMA_KEY_shift = 29, SQ_TEX_CHROMA_KEY_DISABLED = 0x00, SQ_TEX_CHROMA_KEY_KILL = 0x01, SQ_TEX_CHROMA_KEY_BLEND = 0x02, LOD_USES_MINOR_AXIS_bit = 1 << 31, SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, MIN_LOD_mask = 0x3ff << 0, MIN_LOD_shift = 0, MAX_LOD_mask = 0x3ff << 10, MAX_LOD_shift = 10, SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20, SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20, SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, LOD_BIAS_SEC_mask = 0xfff << 0, LOD_BIAS_SEC_shift = 0, MC_COORD_TRUNCATE_bit = 1 << 12, SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13, HIGH_PRECISION_FILTER_bit = 1 << 14, PERF_MIP_mask = 0x07 << 15, PERF_MIP_shift = 15, PERF_Z_mask = 0x03 << 18, PERF_Z_shift = 18, FETCH_4_bit = 1 << 26, SAMPLE_IS_PCF_bit = 1 << 27, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, SQ_VTX_BASE_VTX_LOC = 0x0003cff0, SQ_VTX_START_INST_LOC = 0x0003cff4, SQ_LOOP_CONST_DX10_0 = 0x0003e200, SQ_LOOP_CONST_0 = 0x0003e200, SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, SQ_LOOP_CONST_0__COUNT_shift = 0, INIT_mask = 0xfff << 12, INIT_shift = 12, INC_mask = 0xff << 24, INC_shift = 24, SQ_BOOL_CONST_0 = 0x0003e380, SQ_BOOL_CONST_0_num = 3, } ; #endif /* _AUTOREGS */ xserver-xorg-video-ati-7.5.0+git20150819/src/r600_reg_r6xx.h000066400000000000000000000722711256524674500227720ustar00rootroot00000000000000/* * RadeonHD R6xx, R7xx Register documentation * * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. * Copyright (C) 2008-2009 Matthias Hopf * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _R600_REG_R6xx_H_ #define _R600_REG_R6xx_H_ /* * Registers for R6xx chips that are not documented yet */ enum { MM_INDEX = 0x0000, MM_DATA = 0x0004, SRBM_STATUS = 0x0e50, RLC_RQ_PENDING_bit = 1 << 3, RCU_RQ_PENDING_bit = 1 << 4, GRBM_RQ_PENDING_bit = 1 << 5, HI_RQ_PENDING_bit = 1 << 6, IO_EXTERN_SIGNAL_bit = 1 << 7, VMC_BUSY_bit = 1 << 8, MCB_BUSY_bit = 1 << 9, MCDZ_BUSY_bit = 1 << 10, MCDY_BUSY_bit = 1 << 11, MCDX_BUSY_bit = 1 << 12, MCDW_BUSY_bit = 1 << 13, SEM_BUSY_bit = 1 << 14, SRBM_STATUS__RLC_BUSY_bit = 1 << 15, PDMA_BUSY_bit = 1 << 16, IH_BUSY_bit = 1 << 17, CSC_BUSY_bit = 1 << 20, CMC7_BUSY_bit = 1 << 21, CMC6_BUSY_bit = 1 << 22, CMC5_BUSY_bit = 1 << 23, CMC4_BUSY_bit = 1 << 24, CMC3_BUSY_bit = 1 << 25, CMC2_BUSY_bit = 1 << 26, CMC1_BUSY_bit = 1 << 27, CMC0_BUSY_bit = 1 << 28, BIF_BUSY_bit = 1 << 29, IDCT_BUSY_bit = 1 << 30, SRBM_READ_ERROR = 0x0e98, READ_ADDRESS_mask = 0xffff << 2, READ_ADDRESS_shift = 2, READ_REQUESTER_HI_bit = 1 << 24, READ_REQUESTER_GRBM_bit = 1 << 25, READ_REQUESTER_RCU_bit = 1 << 26, READ_REQUESTER_RLC_bit = 1 << 27, READ_ERROR_bit = 1 << 31, SRBM_INT_STATUS = 0x0ea4, RDERR_INT_STAT_bit = 1 << 0, GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, SRBM_INT_ACK = 0x0ea8, RDERR_INT_ACK_bit = 1 << 0, GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, R6XX_MC_VM_FB_LOCATION = 0x2180, VENDOR_DEVICE_ID = 0x4000, HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, D1GRPH_PITCH = 0x6120, D1GRPH_Y_END = 0x6138, GRBM_STATUS = 0x8010, CMDFIFO_AVAIL_mask = 0x1f << 0, CMDFIFO_AVAIL_shift = 0, SRBM_RQ_PENDING_bit = 1 << 5, CP_RQ_PENDING_bit = 1 << 6, CF_RQ_PENDING_bit = 1 << 7, PF_RQ_PENDING_bit = 1 << 8, GRBM_EE_BUSY_bit = 1 << 10, GRBM_STATUS__VC_BUSY_bit = 1 << 11, DB03_CLEAN_bit = 1 << 12, CB03_CLEAN_bit = 1 << 13, VGT_BUSY_NO_DMA_bit = 1 << 16, GRBM_STATUS__VGT_BUSY_bit = 1 << 17, TA03_BUSY_bit = 1 << 18, GRBM_STATUS__TC_BUSY_bit = 1 << 19, SX_BUSY_bit = 1 << 20, SH_BUSY_bit = 1 << 21, SPI03_BUSY_bit = 1 << 22, SMX_BUSY_bit = 1 << 23, SC_BUSY_bit = 1 << 24, PA_BUSY_bit = 1 << 25, DB03_BUSY_bit = 1 << 26, CR_BUSY_bit = 1 << 27, CP_COHERENCY_BUSY_bit = 1 << 28, GRBM_STATUS__CP_BUSY_bit = 1 << 29, CB03_BUSY_bit = 1 << 30, GUI_ACTIVE_bit = 1 << 31, GRBM_STATUS2 = 0x8014, CR_CLEAN_bit = 1 << 0, SMX_CLEAN_bit = 1 << 1, SPI0_BUSY_bit = 1 << 8, SPI1_BUSY_bit = 1 << 9, SPI2_BUSY_bit = 1 << 10, SPI3_BUSY_bit = 1 << 11, TA0_BUSY_bit = 1 << 12, TA1_BUSY_bit = 1 << 13, TA2_BUSY_bit = 1 << 14, TA3_BUSY_bit = 1 << 15, DB0_BUSY_bit = 1 << 16, DB1_BUSY_bit = 1 << 17, DB2_BUSY_bit = 1 << 18, DB3_BUSY_bit = 1 << 19, CB0_BUSY_bit = 1 << 20, CB1_BUSY_bit = 1 << 21, CB2_BUSY_bit = 1 << 22, CB3_BUSY_bit = 1 << 23, GRBM_SOFT_RESET = 0x8020, SOFT_RESET_CP_bit = 1 << 0, SOFT_RESET_CB_bit = 1 << 1, SOFT_RESET_CR_bit = 1 << 2, SOFT_RESET_DB_bit = 1 << 3, SOFT_RESET_PA_bit = 1 << 5, SOFT_RESET_SC_bit = 1 << 6, SOFT_RESET_SMX_bit = 1 << 7, SOFT_RESET_SPI_bit = 1 << 8, SOFT_RESET_SH_bit = 1 << 9, SOFT_RESET_SX_bit = 1 << 10, SOFT_RESET_TC_bit = 1 << 11, SOFT_RESET_TA_bit = 1 << 12, SOFT_RESET_VC_bit = 1 << 13, SOFT_RESET_VGT_bit = 1 << 14, SOFT_RESET_GRBM_GCA_bit = 1 << 15, WAIT_UNTIL = 0x8040, WAIT_CP_DMA_IDLE_bit = 1 << 8, WAIT_CMDFIFO_bit = 1 << 10, WAIT_2D_IDLE_bit = 1 << 14, WAIT_3D_IDLE_bit = 1 << 15, WAIT_2D_IDLECLEAN_bit = 1 << 16, WAIT_3D_IDLECLEAN_bit = 1 << 17, WAIT_EXTERN_SIG_bit = 1 << 19, CMDFIFO_ENTRIES_mask = 0x1f << 20, CMDFIFO_ENTRIES_shift = 20, GRBM_READ_ERROR = 0x8058, /* READ_ADDRESS_mask = 0xffff << 2, */ /* READ_ADDRESS_shift = 2, */ READ_REQUESTER_SRBM_bit = 1 << 28, READ_REQUESTER_CP_bit = 1 << 29, READ_REQUESTER_WU_POLL_bit = 1 << 30, /* READ_ERROR_bit = 1 << 31, */ SCRATCH_REG0 = 0x8500, SCRATCH_REG1 = 0x8504, SCRATCH_REG2 = 0x8508, SCRATCH_REG3 = 0x850c, SCRATCH_REG4 = 0x8510, SCRATCH_REG5 = 0x8514, SCRATCH_REG6 = 0x8518, SCRATCH_REG7 = 0x851c, SCRATCH_UMSK = 0x8540, SCRATCH_ADDR = 0x8544, CP_COHER_CNTL = 0x85f0, DEST_BASE_0_ENA_bit = 1 << 0, DEST_BASE_1_ENA_bit = 1 << 1, SO0_DEST_BASE_ENA_bit = 1 << 2, SO1_DEST_BASE_ENA_bit = 1 << 3, SO2_DEST_BASE_ENA_bit = 1 << 4, SO3_DEST_BASE_ENA_bit = 1 << 5, CB0_DEST_BASE_ENA_bit = 1 << 6, CB1_DEST_BASE_ENA_bit = 1 << 7, CB2_DEST_BASE_ENA_bit = 1 << 8, CB3_DEST_BASE_ENA_bit = 1 << 9, CB4_DEST_BASE_ENA_bit = 1 << 10, CB5_DEST_BASE_ENA_bit = 1 << 11, CB6_DEST_BASE_ENA_bit = 1 << 12, CB7_DEST_BASE_ENA_bit = 1 << 13, DB_DEST_BASE_ENA_bit = 1 << 14, CR_DEST_BASE_ENA_bit = 1 << 15, TC_ACTION_ENA_bit = 1 << 23, VC_ACTION_ENA_bit = 1 << 24, CB_ACTION_ENA_bit = 1 << 25, DB_ACTION_ENA_bit = 1 << 26, SH_ACTION_ENA_bit = 1 << 27, SMX_ACTION_ENA_bit = 1 << 28, CR0_ACTION_ENA_bit = 1 << 29, CR1_ACTION_ENA_bit = 1 << 30, CR2_ACTION_ENA_bit = 1 << 31, CP_COHER_SIZE = 0x85f4, CP_COHER_BASE = 0x85f8, CP_COHER_STATUS = 0x85fc, MATCHING_GFX_CNTX_mask = 0xff << 0, MATCHING_GFX_CNTX_shift = 0, MATCHING_CR_CNTX_mask = 0xffff << 8, MATCHING_CR_CNTX_shift = 8, STATUS_bit = 1 << 31, CP_STALLED_STAT1 = 0x8674, RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, RCIU_STALLED_ON_ME_READ_bit = 1 << 26, RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, CP_STALLED_STAT2 = 0x8678, PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, CP_BUSY_STAT = 0x867c, REG_BUS_FIFO_BUSY_bit = 1 << 0, RING_FETCHING_DATA_bit = 1 << 1, INDR1_FETCHING_DATA_bit = 1 << 2, INDR2_FETCHING_DATA_bit = 1 << 3, STATE_FETCHING_DATA_bit = 1 << 4, PRED_FETCHING_DATA_bit = 1 << 5, COHER_CNTR_NEQ_ZERO_bit = 1 << 6, PFP_PARSING_PACKETS_bit = 1 << 7, ME_PARSING_PACKETS_bit = 1 << 8, RCIU_PFP_BUSY_bit = 1 << 9, RCIU_ME_BUSY_bit = 1 << 10, OUTSTANDING_READ_TAGS_bit = 1 << 11, SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, SEM_FAILED_AND_HOLDING_bit = 1 << 13, SEM_POLLING_FOR_PASS_bit = 1 << 14, _3D_BUSY_bit = 1 << 15, _2D_BUSY_bit = 1 << 16, CP_STAT = 0x8680, CSF_RING_BUSY_bit = 1 << 0, CSF_WPTR_POLL_BUSY_bit = 1 << 1, CSF_INDIRECT1_BUSY_bit = 1 << 2, CSF_INDIRECT2_BUSY_bit = 1 << 3, CSF_STATE_BUSY_bit = 1 << 4, CSF_PREDICATE_BUSY_bit = 1 << 5, CSF_BUSY_bit = 1 << 6, MIU_RDREQ_BUSY_bit = 1 << 7, MIU_WRREQ_BUSY_bit = 1 << 8, ROQ_RING_BUSY_bit = 1 << 9, ROQ_INDIRECT1_BUSY_bit = 1 << 10, ROQ_INDIRECT2_BUSY_bit = 1 << 11, ROQ_STATE_BUSY_bit = 1 << 12, ROQ_PREDICATE_BUSY_bit = 1 << 13, ROQ_ALIGN_BUSY_bit = 1 << 14, PFP_BUSY_bit = 1 << 15, MEQ_BUSY_bit = 1 << 16, ME_BUSY_bit = 1 << 17, QUERY_BUSY_bit = 1 << 18, SEMAPHORE_BUSY_bit = 1 << 19, INTERRUPT_BUSY_bit = 1 << 20, SURFACE_SYNC_BUSY_bit = 1 << 21, DMA_BUSY_bit = 1 << 22, RCIU_BUSY_bit = 1 << 23, CP_STAT__CP_BUSY_bit = 1 << 31, CP_ME_CNTL = 0x86d8, ME_STATMUX_mask = 0xff << 0, ME_STATMUX_shift = 0, ME_HALT_bit = 1 << 28, CP_ME_STATUS = 0x86dc, CP_RB_RPTR = 0x8700, RB_RPTR_mask = 0xfffff << 0, RB_RPTR_shift = 0, CP_RB_WPTR_DELAY = 0x8704, PRE_WRITE_TIMER_mask = 0xfffffff << 0, PRE_WRITE_TIMER_shift = 0, PRE_WRITE_LIMIT_mask = 0x0f << 28, PRE_WRITE_LIMIT_shift = 28, CP_ROQ_RB_STAT = 0x8780, ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, ROQ_RPTR_PRIMARY_shift = 0, ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, ROQ_WPTR_PRIMARY_shift = 16, CP_ROQ_IB1_STAT = 0x8784, ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, ROQ_RPTR_INDIRECT1_shift = 0, ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, ROQ_WPTR_INDIRECT1_shift = 16, CP_ROQ_IB2_STAT = 0x8788, ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, ROQ_RPTR_INDIRECT2_shift = 0, ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, ROQ_WPTR_INDIRECT2_shift = 16, CP_MEQ_STAT = 0x8794, MEQ_RPTR_mask = 0x3ff << 0, MEQ_RPTR_shift = 0, MEQ_WPTR_mask = 0x3ff << 16, MEQ_WPTR_shift = 16, CC_GC_SHADER_PIPE_CONFIG = 0x8950, INACTIVE_QD_PIPES_mask = 0xff << 8, INACTIVE_QD_PIPES_shift = 8, R6XX_MAX_QD_PIPES = 8, INACTIVE_SIMDS_mask = 0xff << 16, INACTIVE_SIMDS_shift = 16, R6XX_MAX_SIMDS = 8, GC_USER_SHADER_PIPE_CONFIG = 0x8954, VC_ENHANCE = 0x9714, DB_DEBUG = 0x9830, PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, DB_WATERMARKS = 0x00009838, DEPTH_FREE_mask = 0x1f << 0, DEPTH_FREE_shift = 0, DEPTH_FLUSH_mask = 0x3f << 5, DEPTH_FLUSH_shift = 5, FORCE_SUMMARIZE_mask = 0x0f << 11, FORCE_SUMMARIZE_shift = 11, DEPTH_PENDING_FREE_mask = 0x1f << 15, DEPTH_PENDING_FREE_shift = 15, DEPTH_CACHELINE_FREE_mask = 0x1f << 20, DEPTH_CACHELINE_FREE_shift = 20, EARLY_Z_PANIC_DISABLE_bit = 1 << 25, LATE_Z_PANIC_DISABLE_bit = 1 << 26, RE_Z_PANIC_DISABLE_bit = 1 << 27, DB_EXTRA_DEBUG_mask = 0x0f << 28, DB_EXTRA_DEBUG_shift = 28, CP_RB_BASE = 0xc100, CP_RB_CNTL = 0xc104, RB_BUFSZ_mask = 0x3f << 0, CP_RB_WPTR = 0xc114, RB_WPTR_mask = 0xfffff << 0, RB_WPTR_shift = 0, CP_RB_RPTR_WR = 0xc108, RB_RPTR_WR_mask = 0xfffff << 0, RB_RPTR_WR_shift = 0, CP_INT_STATUS = 0xc128, DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, SEM_SIGNAL_INT_STAT_bit = 1 << 18, CNTX_BUSY_INT_STAT_bit = 1 << 19, CNTX_EMPTY_INT_STAT_bit = 1 << 20, WAITMEM_SEM_INT_STAT_bit = 1 << 21, PRIV_INSTR_INT_STAT_bit = 1 << 22, PRIV_REG_INT_STAT_bit = 1 << 23, OPCODE_ERROR_INT_STAT_bit = 1 << 24, SCRATCH_INT_STAT_bit = 1 << 25, TIME_STAMP_INT_STAT_bit = 1 << 26, RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, DMA_INT_STAT_bit = 1 << 28, IB2_INT_STAT_bit = 1 << 29, IB1_INT_STAT_bit = 1 << 30, RB_INT_STAT_bit = 1 << 31, // SX_ALPHA_TEST_CONTROL = 0x00028410, ALPHA_FUNC__REF_NEVER = 0, ALPHA_FUNC__REF_ALWAYS = 7, // DB_SHADER_CONTROL = 0x0002880c, Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, // PA_SU_SC_MODE_CNTL = 0x00028814, // POLY_MODE_mask = 0x03 << 3, POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, // POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ // DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, DB_ALPHA_TO_MASK = 0x00028d44, ALPHA_TO_MASK_ENABLE = 1 << 0, ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, ALPHA_TO_MASK_OFFSET0_shift = 8, ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, ALPHA_TO_MASK_OFFSET1_shift = 10, ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, ALPHA_TO_MASK_OFFSET2_shift = 12, ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, ALPHA_TO_MASK_OFFSET3_shift = 14, // SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, // SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, FMT_16=5, FMT_16_FLOAT, FMT_8_8, FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, FMT_1 = 37, FMT_GB_GR=39, FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, FMT_32_32_32_FLOAT=48, // High level register file lengths SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ SQ_ALU_CONSTANT_ps_num = 256, SQ_ALU_CONSTANT_vs_num = 256, SQ_ALU_CONSTANT_all_num = 512, SQ_ALU_CONSTANT_offset = 16, SQ_ALU_CONSTANT_ps = 0, SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ SQ_TEX_RESOURCE_ps_num = 160, SQ_TEX_RESOURCE_vs_num = 160, SQ_TEX_RESOURCE_fs_num = 16, SQ_TEX_RESOURCE_gs_num = 160, SQ_TEX_RESOURCE_all_num = 496, SQ_TEX_RESOURCE_offset = 28, SQ_TEX_RESOURCE_ps = 0, SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ SQ_VTX_RESOURCE_ps_num = 160, SQ_VTX_RESOURCE_vs_num = 160, SQ_VTX_RESOURCE_fs_num = 16, SQ_VTX_RESOURCE_gs_num = 160, SQ_VTX_RESOURCE_all_num = 496, SQ_VTX_RESOURCE_offset = 28, SQ_VTX_RESOURCE_ps = 0, SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ SQ_TEX_SAMPLER_WORD_ps_num = 18, SQ_TEX_SAMPLER_WORD_vs_num = 18, SQ_TEX_SAMPLER_WORD_gs_num = 18, SQ_TEX_SAMPLER_WORD_all_num = 54, SQ_TEX_SAMPLER_WORD_offset = 12, SQ_TEX_SAMPLER_WORD_ps = 0, SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ SQ_LOOP_CONST_ps_num = 32, SQ_LOOP_CONST_vs_num = 32, SQ_LOOP_CONST_gs_num = 32, SQ_LOOP_CONST_all_num = 96, SQ_LOOP_CONST_offset = 4, SQ_LOOP_CONST_ps = 0, SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ SQ_BOOL_CONST_ps_num = 1, SQ_BOOL_CONST_vs_num = 1, SQ_BOOL_CONST_gs_num = 1, SQ_BOOL_CONST_all_num = 3, SQ_BOOL_CONST_offset = 4, SQ_BOOL_CONST_ps = 0, SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, }; #endif xserver-xorg-video-ati-7.5.0+git20150819/src/r600_reg_r7xx.h000066400000000000000000000176711256524674500227760ustar00rootroot00000000000000/* * RadeonHD R6xx, R7xx Register documentation * * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. * Copyright (C) 2008-2009 Matthias Hopf * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _R600_REG_R7xx_H_ #define _R600_REG_R7xx_H_ /* * Register update for R7xx chips */ enum { R7XX_MC_VM_FB_LOCATION = 0x00002024, // GRBM_STATUS = 0x00008010, R7XX_TA_BUSY_bit = 1 << 14, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c, RING0_OFFSET_mask = 0xff << 0, RING0_OFFSET_shift = 0, ISOLATE_ES_ENABLE_bit = 1 << 12, ISOLATE_GS_ENABLE_bit = 1 << 13, VS_PC_LIMIT_ENABLE_bit = 1 << 14, // SQ_ALU_WORD0 = 0x00008dfc, // SRC0_SEL_mask = 0x1ff << 0, // SRC1_SEL_mask = 0x1ff << 13, R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, // INDEX_MODE_mask = 0x07 << 26, R7xx_SQ_INDEX_GLOBAL = 0x05, R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06, R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc, R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, R6xx_FOG_MERGE_bit = 1 << 5, R6xx_OMOD_mask = 0x03 << 6, R7xx_OMOD_mask = 0x03 << 5, R6xx_OMOD_shift = 6, R7xx_OMOD_shift = 5, R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, R7xx_SQ_OP2_INST_FREXP_64 = 0x07, R7xx_SQ_OP2_INST_ADD_64 = 0x17, R7xx_SQ_OP2_INST_MUL_64 = 0x1b, R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c, R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d, R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a, R7xx_SQ_OP2_INST_FRACT_64 = 0x7b, R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c, R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d, R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e, // SQ_ALU_WORD1_OP3 = 0x00008dfc, // SRC2_SEL_mask = 0x1ff << 0, // R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, // R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, // R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, // R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, // SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, R7xx_SQ_OP3_INST_MULADD_64 = 0x08, R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09, R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a, R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b, // SQ_CF_ALU_WORD1 = 0x00008dfc, R6xx_USES_WATERFALL_bit = 1 << 25, R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, // SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, // ARRAY_BASE_mask = 0x1fff << 0, // TYPE_mask = 0x03 << 13, // SQ_EXPORT_PARAM = 0x02, // X_UNUSED_FOR_SX_EXPORTS = 0x03, // ELEM_SIZE_mask = 0x03 << 30, // SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, // SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a, // SQ_CF_WORD1 = 0x00008dfc, // SQ_CF_WORD1__COUNT_mask = 0x07 << 10, R7xx_COUNT_3_bit = 1 << 19, // SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, R7xx_SQ_CF_INST_END_PROGRAM = 0x19, R7xx_SQ_CF_INST_WAIT_ACK = 0x1a, R7xx_SQ_CF_INST_TEX_ACK = 0x1b, R7xx_SQ_CF_INST_VTX_ACK = 0x1c, R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d, // SQ_VTX_WORD0 = 0x00008dfc, // VTX_INST_mask = 0x1f << 0, R7xx_SQ_VTX_INST_MEM = 0x02, // SQ_VTX_WORD2 = 0x00008dfc, R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, // SQ_TEX_WORD0 = 0x00008dfc, // TEX_INST_mask = 0x1f << 0, R7xx_X_MEMORY_READ = 0x02, R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f, R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, R7xx_PA_SC_EDGERULE = 0x00028230, R7xx_SPI_THREAD_GROUPING = 0x000286c8, PS_GROUPING_mask = 0x1f << 0, PS_GROUPING_shift = 0, VS_GROUPING_mask = 0x1f << 8, VS_GROUPING_shift = 8, GS_GROUPING_mask = 0x1f << 16, GS_GROUPING_shift = 16, ES_GROUPING_mask = 0x1f << 24, ES_GROUPING_shift = 24, R7xx_CB_SHADER_CONTROL = 0x000287a0, RT0_ENABLE_bit = 1 << 0, RT1_ENABLE_bit = 1 << 1, RT2_ENABLE_bit = 1 << 2, RT3_ENABLE_bit = 1 << 3, RT4_ENABLE_bit = 1 << 4, RT5_ENABLE_bit = 1 << 5, RT6_ENABLE_bit = 1 << 6, RT7_ENABLE_bit = 1 << 7, // DB_ALPHA_TO_MASK = 0x00028d44, R7xx_OFFSET_ROUND_bit = 1 << 16, // SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, R7xx_TRUNCATE_COORD_bit = 1 << 9, R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10, } ; #endif /* _R600_REG_R7xx_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/r600_shader.c000066400000000000000000003163671256524674500224760ustar00rootroot00000000000000/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "radeon.h" #include "r600_shader.h" #include "r600_reg.h" /* solid vs --------------------------------------- */ int R600_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_VTX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 - always export a param whether it's used or not */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(0), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 3 - padding */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1)); shader[i++] = VTX_DWORD_PAD; return i; } /* solid ps --------------------------------------- */ int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_ALU_DWORD0(ADDR(2), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 3 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 4 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 5 */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MOV), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); return i; } /* copy vs --------------------------------------- */ int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(4)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_VTX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(0), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 3 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1)); shader[i++] = VTX_DWORD_PAD; /* 6/7 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0)); shader[i++] = VTX_DWORD_PAD; return i; } /* copy ps --------------------------------------- */ int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i=0; /* CF INST 0 */ shader[i++] = CF_DWORD0(ADDR(2)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TEX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* CF INST 1 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* TEX INST 0 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), /* R */ DST_SEL_Y(SQ_SEL_Y), /* G */ DST_SEL_Z(SQ_SEL_Z), /* B */ DST_SEL_W(SQ_SEL_W), /* A */ LOD_BIAS(0), COORD_TYPE_X(TEX_UNNORMALIZED), COORD_TYPE_Y(TEX_UNNORMALIZED), COORD_TYPE_Z(TEX_UNNORMALIZED), COORD_TYPE_W(TEX_UNNORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } /* * ; xv vertex shader * 00 VTX: ADDR(4) CNT(2) * 0 VFETCH R1.xy01, R0.x, fc0 MEGA(16) FORMAT(32_32_FLOAT) * FORMAT_COMP(SIGNED) * 1 VFETCH R0.xy01, R0.x, fc0 MINI(8) OFFSET(8) FORMAT(32_32_FLOAT) * FORMAT_COMP(SIGNED) * 01 EXP_DONE: POS0, R1 * 02 EXP_DONE: PARAM0, R0 NO_BARRIER * END_OF_PROGRAM */ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(6)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_VTX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 1 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(4), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(2), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 2 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 3 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 4 texX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 5 texY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 6/7 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1)); shader[i++] = VTX_DWORD_PAD; /* 8/9 */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0)); shader[i++] = VTX_DWORD_PAD; return i; } int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(16)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(24)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ shader[i++] = CF_ALU_DWORD0(ADDR(4), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(12), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 3 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(3)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4,5,6,7 */ /* r2.x = MAD(c0.w, r1.x, c0.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c0.w, r1.x, c0.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c0.w, r1.x, c0.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 8,9,10,11 */ /* r2.x = MAD(c1.x, r1.y, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* r2.y = MAD(c1.y, r1.y, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* r2.z = MAD(c1.z, r1.y, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_W), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 12,13,14,15 */ /* r2.x = MAD(c2.x, r1.z, pv.x) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* r2.y = MAD(c2.y, r1.z, pv.y) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Y), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* r2.z = MAD(c2.z, r1.z, pv.z) */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_Z), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* r2.w = MAD(0, 0, 1) */ shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(SQ_ALU_SRC_0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1), SRC2_REL(ABSOLUTE), SRC2_ELEM(ELEM_X), SRC2_NEG(0), ALU_INST(SQ_OP3_INST_MULADD), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 16 */ shader[i++] = CF_DWORD0(ADDR(18)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TEX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 17 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 18/19 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 20/21 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_MASK), DST_SEL_Z(SQ_SEL_X), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 22/23 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(2), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_MASK), DST_SEL_Y(SQ_SEL_X), DST_SEL_Z(SQ_SEL_MASK), DST_SEL_W(SQ_SEL_MASK), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(2), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 24 */ shader[i++] = CF_DWORD0(ADDR(26)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TEX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 25 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 26/27 */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_1), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } /* comp vs --------------------------------------- */ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(3)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(9)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_NOP), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 3 - mask sub */ shader[i++] = CF_DWORD0(ADDR(44)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(3), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_VTX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(14), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(20), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 6 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 7 - mask */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(1), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 8 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 9 - non-mask sub */ shader[i++] = CF_DWORD0(ADDR(50)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_VTX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 10 - ALU */ shader[i++] = CF_ALU_DWORD0(ADDR(34), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(10), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 11 - dst */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), TYPE(SQ_EXPORT_POS), RW_GPR(1), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), R6xx_ELEM_LOOP(0), BURST_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 12 - src */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), TYPE(SQ_EXPORT_PARAM), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(0)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1), R6xx_ELEM_LOOP(0), BURST_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 13 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 14 srcX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 15 srcX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 16 srcX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 17 srcX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 18 srcY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 19 srcY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 20 srcY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 21 srcY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(3), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 22 maskX.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 23 maskX.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 24 maskX.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 25 maskX.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 26 maskY.x DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 27 maskY.y DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 28 maskY.z DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 29 maskY.w DOT4 - mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(4), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 30 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 31 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(1), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 32 maskX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 2), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 33 maskY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 3), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 34 srcX.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 35 srcX.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 36 srcX.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 37 srcX.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 38 srcY.x DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 39 srcY.y DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 40 srcY.z DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(0)); /* 41 srcY.w DOT4 - non-mask */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(0), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_DOT4), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(0)); /* 42 srcX / w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(0)); /* 43 srcY / h */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_CFILE_BASE + 1), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_AR_X), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(0), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(0)); /* 44/45 - dst - mask */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(24)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(2), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1)); shader[i++] = VTX_DWORD_PAD; /* 46/47 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0)); shader[i++] = VTX_DWORD_PAD; /* 48/49 - mask */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(16), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0)); shader[i++] = VTX_DWORD_PAD; /* 50/51 - dst - non-mask */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(16)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_0), DST_SEL_W(SQ_SEL_1), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1)); shader[i++] = VTX_DWORD_PAD; /* 52/53 - src */ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), FETCH_WHOLE_QUAD(0), BUFFER_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), SRC_SEL_X(SQ_SEL_X), MEGA_FETCH_COUNT(8)); shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), DST_REL(0), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_1), DST_SEL_W(SQ_SEL_0), USE_CONST_FIELDS(0), DATA_FORMAT(FMT_32_32_FLOAT), NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED), FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), #if X_BYTE_ORDER == X_BIG_ENDIAN ENDIAN_SWAP(SQ_ENDIAN_8IN32), #else ENDIAN_SWAP(SQ_ENDIAN_NONE), #endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0)); shader[i++] = VTX_DWORD_PAD; return i; } /* comp ps --------------------------------------- */ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) { int i = 0; /* 0 */ shader[i++] = CF_DWORD0(ADDR(3)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 1 */ shader[i++] = CF_DWORD0(ADDR(7)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_NOT_BOOL), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_CALL), WHOLE_QUAD_MODE(0), BARRIER(0)); /* 2 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(1), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_NOP), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 3 - mask sub */ shader[i++] = CF_DWORD0(ADDR(14)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(2), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TEX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 4 */ shader[i++] = CF_ALU_DWORD0(ADDR(10), KCACHE_BANK0(0), KCACHE_BANK1(0), KCACHE_MODE0(SQ_CF_KCACHE_NOP)); shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), KCACHE_ADDR0(0), KCACHE_ADDR1(0), I_COUNT(4), USES_WATERFALL(0), CF_INST(SQ_CF_INST_ALU), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 5 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(2), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 6 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 7 non-mask sub */ shader[i++] = CF_DWORD0(ADDR(18)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(1), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_TEX), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 8 */ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), TYPE(SQ_EXPORT_PIXEL), RW_GPR(0), RW_REL(ABSOLUTE), INDEX_GPR(0), ELEM_SIZE(1)); shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_Z), SRC_SEL_W(SQ_SEL_W), R6xx_ELEM_LOOP(0), BURST_COUNT(1), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_EXPORT_DONE), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 9 */ shader[i++] = CF_DWORD0(ADDR(0)); shader[i++] = CF_DWORD1(POP_COUNT(0), CF_CONST(0), COND(SQ_CF_COND_ACTIVE), I_COUNT(0), CALL_COUNT(0), END_OF_PROGRAM(0), VALID_PIXEL_MODE(0), CF_INST(SQ_CF_INST_RETURN), WHOLE_QUAD_MODE(0), BARRIER(1)); /* 10 - alu 0 */ /* MUL gpr[2].x gpr[1].x gpr[0].x */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_X), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_X), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_X), CLAMP(1)); /* 11 - alu 1 */ /* MUL gpr[2].y gpr[1].y gpr[0].y */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Y), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Y), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Y), CLAMP(1)); /* 12 - alu 2 */ /* MUL gpr[2].z gpr[1].z gpr[0].z */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_Z), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_Z), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(0)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_Z), CLAMP(1)); /* 13 - alu 3 */ /* MUL gpr[2].w gpr[1].w gpr[0].w */ shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), SRC0_REL(ABSOLUTE), SRC0_ELEM(ELEM_W), SRC0_NEG(0), SRC1_SEL(ALU_SRC_GPR_BASE + 0), SRC1_REL(ABSOLUTE), SRC1_ELEM(ELEM_W), SRC1_NEG(0), INDEX_MODE(SQ_INDEX_LOOP), PRED_SEL(SQ_PRED_SEL_OFF), LAST(1)); shader[i++] = ALU_DWORD1_OP2(ChipSet, SRC0_ABS(0), SRC1_ABS(0), UPDATE_EXECUTE_MASK(0), UPDATE_PRED(0), WRITE_MASK(1), FOG_MERGE(0), OMOD(SQ_ALU_OMOD_OFF), ALU_INST(SQ_OP2_INST_MUL), BANK_SWIZZLE(SQ_ALU_VEC_012), DST_GPR(2), DST_REL(ABSOLUTE), DST_ELEM(ELEM_W), CLAMP(1)); /* 14/15 - src - mask */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 16/17 - mask */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(1), SRC_GPR(1), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(1), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(1), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; /* 18/19 - src - non-mask */ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), BC_FRAC_MODE(0), FETCH_WHOLE_QUAD(0), RESOURCE_ID(0), SRC_GPR(0), SRC_REL(ABSOLUTE), R7xx_ALT_CONST(0)); shader[i++] = TEX_DWORD1(DST_GPR(0), DST_REL(ABSOLUTE), DST_SEL_X(SQ_SEL_X), DST_SEL_Y(SQ_SEL_Y), DST_SEL_Z(SQ_SEL_Z), DST_SEL_W(SQ_SEL_W), LOD_BIAS(0), COORD_TYPE_X(TEX_NORMALIZED), COORD_TYPE_Y(TEX_NORMALIZED), COORD_TYPE_Z(TEX_NORMALIZED), COORD_TYPE_W(TEX_NORMALIZED)); shader[i++] = TEX_DWORD2(OFFSET_X(0), OFFSET_Y(0), OFFSET_Z(0), SAMPLER_ID(0), SRC_SEL_X(SQ_SEL_X), SRC_SEL_Y(SQ_SEL_Y), SRC_SEL_Z(SQ_SEL_0), SRC_SEL_W(SQ_SEL_1)); shader[i++] = TEX_DWORD_PAD; return i; } xserver-xorg-video-ati-7.5.0+git20150819/src/r600_shader.h000066400000000000000000000343521256524674500224720ustar00rootroot00000000000000/* * RadeonHD R6xx, R7xx DRI driver * * Copyright (C) 2008-2009 Alexander Deucher * Copyright (C) 2008-2009 Matthias Hopf * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * Shader macros */ #ifndef __SHADER_H__ #define __SHADER_H__ #include "radeon.h" /* Restrictions of ALU instructions * order of scalar ops is always x,y,z,w,t(rans), last to be indicated by last==1. * max of 3 different src GPRs per instr. * max of 4 different cfile constant components per instr. * max of 2 (different) constants (any type) for t. * bank swizzle (see below). * GPR write stalls read of same register. Auto-replaced by PV/PS, NOP needed if registers are relative to * different indices (gpr,loop,nothing). * may use constant registers or constant cache, but not both. */ /* Bank_swizzle: (pp. 297ff) * Only one of each x,y,z,w GPR component can be loaded per cycle (3 cycles per instr, called 0-2). * per scalar instruction bank_swizzle can select which cycle each operand comes from. e.g.: * SRC0 SRC1 SRC2 SWIZZLE cycle0 cycle1 cycle2 * 1.x 2.x 012 1.x 2.x - * 3.x 1.y 201 1.y - 3.x * 2.x 1.y 102 (1.y) (2.x) - * If data is read in a cycle, multiple scalar instructions can reference it. * Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1. * No restrictions for constants or PV/PS. * t can load multiple components in a single cycle slot, but has to share cycles with xyzw. * t with single constant may not load GPRs or PV/PS in cycle 0 (carefull with ALU_TRANS_210). * t with two constants may only load GPRs or PV/PS in cycle 2. */ /* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */ // CF insts // addr #define ADDR(x) (x) // pc #define POP_COUNT(x) (x) // const #define CF_CONST(x) (x) // cond #define COND(x) (x) // SQ_COND_* // count #define I_COUNT(x) ((x) ? ((x) - 1) : 0) //r7xx #define COUNT_3(x) (x) // call count #define CALL_COUNT(x) (x) // eop #define END_OF_PROGRAM(x) (x) // vpm #define VALID_PIXEL_MODE(x) (x) // cf inst #define CF_INST(x) (x) // SQ_CF_INST_* // wqm #define WHOLE_QUAD_MODE(x) (x) // barrier #define BARRIER(x) (x) //kb0 #define KCACHE_BANK0(x) (x) //kb1 #define KCACHE_BANK1(x) (x) // km0/1 #define KCACHE_MODE0(x) (x) #define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_* // #define KCACHE_ADDR0(x) (x) #define KCACHE_ADDR1(x) (x) // uw #define USES_WATERFALL(x) (x) #define ARRAY_BASE(x) (x) // export pixel #define CF_PIXEL_MRT0 0 #define CF_PIXEL_MRT1 1 #define CF_PIXEL_MRT2 2 #define CF_PIXEL_MRT3 3 #define CF_PIXEL_MRT4 4 #define CF_PIXEL_MRT5 5 #define CF_PIXEL_MRT6 6 #define CF_PIXEL_MRT7 7 // *_FOG: r6xx only #define CF_PIXEL_MRT0_FOG 16 #define CF_PIXEL_MRT1_FOG 17 #define CF_PIXEL_MRT2_FOG 18 #define CF_PIXEL_MRT3_FOG 19 #define CF_PIXEL_MRT4_FOG 20 #define CF_PIXEL_MRT5_FOG 21 #define CF_PIXEL_MRT6_FOG 22 #define CF_PIXEL_MRT7_FOG 23 #define CF_PIXEL_Z 61 // export pos #define CF_POS0 60 #define CF_POS1 61 #define CF_POS2 62 #define CF_POS3 63 // export param // 0...31 #define TYPE(x) (x) // SQ_EXPORT_* #if 0 // type export #define SQ_EXPORT_PIXEL 0 #define SQ_EXPORT_POS 1 #define SQ_EXPORT_PARAM 2 // reserved 3 // type mem #define SQ_EXPORT_WRITE 0 #define SQ_EXPORT_WRITE_IND 1 #define SQ_EXPORT_WRITE_ACK 2 #define SQ_EXPORT_WRITE_IND_ACK 3 #endif #define RW_GPR(x) (x) #define RW_REL(x) (x) #define ABSOLUTE 0 #define RELATIVE 1 #define INDEX_GPR(x) (x) #define ELEM_SIZE(x) (x ? (x - 1) : 0) #define COMP_MASK(x) (x) #define R6xx_ELEM_LOOP(x) (x) #define BURST_COUNT(x) (x ? (x - 1) : 0) // swiz #define SRC_SEL_X(x) (x) // SQ_SEL_* each #define SRC_SEL_Y(x) (x) #define SRC_SEL_Z(x) (x) #define SRC_SEL_W(x) (x) #define CF_DWORD0(addr) cpu_to_le32((addr)) // R7xx has another entry (COUNT3), but that is only used for adding a bit to count. // We allow one more bit for count in the argument of the macro on R7xx instead. // R6xx: [0,7] R7xx: [1,16] #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))) #define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))) #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))) #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ ((es) << 30))) // R7xx apparently doesn't have the ELEM_LOOP entry any more // We still expose it, but ELEM_LOOP is explicitely R6xx now. // TODO: is this just forgotten in the docs, or really not available any more? #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ cpu_to_le32((((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))) #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ ((wqm) << 30) | ((b) << 31))) // ALU clause insts #define SRC0_SEL(x) (x) #define SRC1_SEL(x) (x) #define SRC2_SEL(x) (x) // src[0-2]_sel // 0-127 GPR // 128-159 kcache constants bank 0 // 160-191 kcache constants bank 1 // 248-255 special SQ_ALU_SRC_* (0, 1, etc.) #define ALU_SRC_GPR_BASE 0 #define ALU_SRC_KCACHE0_BASE 128 #define ALU_SRC_KCACHE1_BASE 160 #define ALU_SRC_CFILE_BASE 256 #define SRC0_REL(x) (x) #define SRC1_REL(x) (x) #define SRC2_REL(x) (x) // elem #define SRC0_ELEM(x) (x) #define SRC1_ELEM(x) (x) #define SRC2_ELEM(x) (x) #define ELEM_X 0 #define ELEM_Y 1 #define ELEM_Z 2 #define ELEM_W 3 // neg #define SRC0_NEG(x) (x) #define SRC1_NEG(x) (x) #define SRC2_NEG(x) (x) // im #define INDEX_MODE(x) (x) // SQ_INDEX_* // ps #define PRED_SEL(x) (x) // SQ_PRED_SEL_* // last #define LAST(x) (x) // abs #define SRC0_ABS(x) (x) #define SRC1_ABS(x) (x) // uem #define UPDATE_EXECUTE_MASK(x) (x) // up #define UPDATE_PRED(x) (x) // wm #define WRITE_MASK(x) (x) // fm #define FOG_MERGE(x) (x) // omod #define OMOD(x) (x) // SQ_ALU_OMOD_* // alu inst #define ALU_INST(x) (x) // SQ_ALU_INST_* //bs #define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_* #define DST_GPR(x) (x) #define DST_REL(x) (x) #define DST_ELEM(x) (x) #define CLAMP(x) (x) #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ ((im) << 26) | ((ps) << 29) | ((last) << 31))) // R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) // This is a general chipset macro, but due to selection by chipid typically not usable in static arrays // Fog is NOT USED on R7xx, even if specified. #define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ ((chipfamily) < CHIP_FAMILY_RV770 ? \ R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ ((de) << 29) | ((clamp) << 31))) // VTX clause insts // vxt insts #define VTX_INST(x) (x) // SQ_VTX_INST_* // fetch type #define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_* #define FETCH_WHOLE_QUAD(x) (x) #define BUFFER_ID(x) (x) #define SRC_GPR(x) (x) #define SRC_REL(x) (x) #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) #define SEMANTIC_ID(x) (x) #define DST_SEL_X(x) (x) #define DST_SEL_Y(x) (x) #define DST_SEL_Z(x) (x) #define DST_SEL_W(x) (x) #define USE_CONST_FIELDS(x) (x) #define DATA_FORMAT(x) (x) // num format #define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_* // format comp #define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_* // sma #define SRF_MODE_ALL(x) (x) #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 #define SRF_MODE_NO_ZERO 1 #define OFFSET(x) (x) // endian swap #define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_* #define CONST_BUF_NO_STRIDE(x) (x) // mf #define MEGA_FETCH(x) (x) #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26))) #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ cpu_to_le32((((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) #define VTX_DWORD2(offset, es, cbns, mf) \ cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19))) #define VTX_DWORD_PAD cpu_to_le32(0x00000000) // TEX clause insts // tex insts #define TEX_INST(x) (x) // SQ_TEX_INST_* #define BC_FRAC_MODE(x) (x) #define FETCH_WHOLE_QUAD(x) (x) #define RESOURCE_ID(x) (x) #define R7xx_ALT_CONST(x) (x) #define LOD_BIAS(x) (x) //ct #define COORD_TYPE_X(x) (x) #define COORD_TYPE_Y(x) (x) #define COORD_TYPE_Z(x) (x) #define COORD_TYPE_W(x) (x) #define TEX_UNNORMALIZED 0 #define TEX_NORMALIZED 1 #define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */ #define OFFSET_Y(x) (((int)(x) * 2) & 0x1f) #define OFFSET_Z(x) (((int)(x) * 2) & 0x1f) #define SAMPLER_ID(x) (x) // R7xx has an additional parameter ALT_CONST. We always expose it, but ALT_CONST is R7xx only #define TEX_DWORD0(tex_inst, bfm, fwq, resource_id, src_gpr, sr, ac) \ cpu_to_le32((((tex_inst) << 0) | ((bfm) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \ ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24))) #define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \ cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31))) #define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \ cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \ ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29))) #define TEX_DWORD_PAD cpu_to_le32(0x00000000) extern int R600_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps); extern int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader); extern int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader); extern int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs); extern int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/r600_state.h000066400000000000000000000227271256524674500223470ustar00rootroot00000000000000#ifndef __R600_STATE_H__ #define __R600_STATE_H__ #include "xf86drm.h" typedef int bool_t; #define CLEAR(x) memset (&x, 0, sizeof(x)) /* Sequencer / thread handling */ typedef struct { int ps_prio; int vs_prio; int gs_prio; int es_prio; int num_ps_gprs; int num_vs_gprs; int num_gs_gprs; int num_es_gprs; int num_temp_gprs; int num_ps_threads; int num_vs_threads; int num_gs_threads; int num_es_threads; int num_ps_stack_entries; int num_vs_stack_entries; int num_gs_stack_entries; int num_es_stack_entries; } sq_config_t; /* Color buffer / render target */ typedef struct { int id; int w; int h; uint64_t base; int format; int endian; int array_mode; // tiling int number_type; int read_size; int comp_swap; int tile_mode; int blend_clamp; int clear_color; int blend_bypass; int blend_float32; int simple_float; int round_mode; int tile_compact; int source_format; /* 2D related CB state */ uint32_t pmask; int rop; int blend_enable; uint32_t blendcntl; struct radeon_bo *bo; struct radeon_surface *surface; } cb_config_t; /* Depth buffer */ typedef struct { int w; int h; uint64_t base; int format; int read_size; int array_mode; // tiling int tile_surface_en; int tile_compact; int zrange_precision; struct radeon_bo *bo; } db_config_t; /* Shader */ typedef struct { uint64_t shader_addr; uint32_t shader_size; int num_gprs; int stack_size; int dx10_clamp; int prime_cache_pgm_en; int prime_cache_on_draw; int fetch_cache_lines; int prime_cache_en; int prime_cache_on_const; int clamp_consts; int export_mode; int uncached_first_inst; struct radeon_bo *bo; } shader_config_t; /* Vertex buffer / vtx resource */ typedef struct { int id; uint64_t vb_addr; uint32_t vtx_num_entries; uint32_t vtx_size_dw; int clamp_x; int format; int num_format_all; int format_comp_all; int srf_mode_all; int endian; int mem_req_size; struct radeon_bo *bo; } vtx_resource_t; /* Texture resource */ typedef struct { int id; int w; int h; int pitch; int depth; int dim; int tile_mode; int tile_type; int format; uint64_t base; uint64_t mip_base; uint32_t size; int format_comp_x; int format_comp_y; int format_comp_z; int format_comp_w; int num_format_all; int srf_mode_all; int force_degamma; int endian; int request_size; int dst_sel_x; int dst_sel_y; int dst_sel_z; int dst_sel_w; int base_level; int last_level; int base_array; int last_array; int mpeg_clamp; int perf_modulation; int interlaced; struct radeon_bo *bo; struct radeon_bo *mip_bo; struct radeon_surface *surface; } tex_resource_t; /* Texture sampler */ typedef struct { int id; /* Clamping */ int clamp_x, clamp_y, clamp_z; int border_color; /* Filtering */ int xy_mag_filter, xy_min_filter; int z_filter; int mip_filter; bool_t high_precision_filter; /* ? */ int perf_mip; /* ? 0-7 */ int perf_z; /* ? 3 */ /* LoD selection */ int min_lod, max_lod; /* 0-0x3ff */ int lod_bias; /* 0-0xfff (signed?) */ int lod_bias2; /* ? 0-0xfff (signed?) */ bool_t lod_uses_minor_axis; /* ? */ /* Other stuff */ bool_t point_sampling_clamp; /* ? */ bool_t tex_array_override; /* ? */ bool_t mc_coord_truncate; /* ? */ bool_t force_degamma; /* ? */ bool_t fetch_4; /* ? */ bool_t sample_is_pcf; /* ? */ bool_t type; /* ? */ int depth_compare; /* only depth textures? */ int chroma_key; } tex_sampler_t; /* Draw command */ typedef struct { uint32_t prim_type; uint32_t vgt_draw_initiator; uint32_t index_type; uint32_t num_instances; uint32_t num_indices; } draw_config_t; #define BEGIN_BATCH(n) \ do { \ radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ } while(0) #define END_BATCH() \ do { \ radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ } while(0) #define RELOC_BATCH(bo, rd, wd) \ do { \ int _ret; \ _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \ if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \ } while(0) #define E32(dword) \ do { \ radeon_cs_write_dword(info->cs, (dword)); \ } while (0) #define EFLOAT(val) \ do { \ union { float f; uint32_t d; } a; \ a.f = (val); \ E32(a.d); \ } while (0) #define PACK3(cmd, num) \ do { \ E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ } while (0) /* write num registers, start at reg */ /* If register falls in a special area, special commands are issued */ #define PACK0(reg, num) \ do { \ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \ PACK3(IT_SET_CONFIG_REG, (num) + 1); \ E32(((reg) - SET_CONFIG_REG_offset) >> 2); \ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \ PACK3(IT_SET_CONTEXT_REG, (num) + 1); \ E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \ PACK3(IT_SET_ALU_CONST, (num) + 1); \ E32(((reg) - SET_ALU_CONST_offset) >> 2); \ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \ PACK3(IT_SET_RESOURCE, num + 1); \ E32(((reg) - SET_RESOURCE_offset) >> 2); \ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \ PACK3(IT_SET_SAMPLER, (num) + 1); \ E32((reg - SET_SAMPLER_offset) >> 2); \ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \ PACK3(IT_SET_CTL_CONST, (num) + 1); \ E32(((reg) - SET_CTL_CONST_offset) >> 2); \ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \ PACK3(IT_SET_LOOP_CONST, (num) + 1); \ E32(((reg) - SET_LOOP_CONST_offset) >> 2); \ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \ PACK3(IT_SET_BOOL_CONST, (num) + 1); \ E32(((reg) - SET_BOOL_CONST_offset) >> 2); \ } else { \ E32(CP_PACKET0 ((reg), (num) - 1)); \ } \ } while (0) /* write a single register */ #define EREG(reg, val) \ do { \ PACK0((reg), 1); \ E32((val)); \ } while (0) void R600CPFlushIndirect(ScrnInfoPtr pScrn); void R600IBDiscard(ScrnInfoPtr pScrn); void r600_wait_3d_idle_clean(ScrnInfoPtr pScrn); void r600_wait_3d_idle(ScrnInfoPtr pScrn); void r600_start_3d(ScrnInfoPtr pScrn); void r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain); void r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); void r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp); void r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain); void r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain); void r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain); void r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf); void r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val); void r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain); void r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s); void r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void r600_set_default_state(ScrnInfoPtr pScrn); void r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices); void r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf); void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size); Bool R600SetAccelState(ScrnInfoPtr pScrn, struct r600_accel_object *src0, struct r600_accel_object *src1, struct r600_accel_object *dst, uint32_t vs_offset, uint32_t ps_offset, int rop, Pixel planemask); extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index); extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index); extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align); extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, int depth, int usage_hint, int bitsPerPixel, int *new_pitch); extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv); extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix); extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p); extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/r600_textured_videofuncs.c000066400000000000000000000375631256524674500253170ustar00rootroot00000000000000/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: Alex Deucher * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include "exa.h" #include "radeon.h" #include "radeon_reg.h" #include "r600_shader.h" #include "r600_reg.h" #include "r600_state.h" #include "radeon_video.h" #include #include "fourcc.h" #include "damage.h" #include "radeon_exa_shared.h" #include "radeon_vbo.h" /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces note the difference to the parameters used in overlay are due to 10bit vs. float calcs */ static REF_TRANSFORM trans[2] = { {1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */ {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ }; void R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; PixmapPtr pPixmap = pPriv->pPixmap; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); int dstxoff, dstyoff; struct r600_accel_object src_obj, dst_obj; cb_config_t cb_conf; tex_resource_t tex_res; tex_sampler_t tex_samp; shader_config_t vs_conf, ps_conf; /* * y' = y - .0625 * u' = u - .5 * v' = v - .5; * * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' * * DP3 might look like the straightforward solution * but we'd need to move the texture yuv values in * the same reg for this to work. Therefore use MADs. * Brightness just adds to the off constant. * Contrast is multiplication of luminance. * Saturation and hue change the u and v coeffs. * Default values (before adjustments - depend on colorspace): * yco = 1.1643 * uco = 0, -0.39173, 2.017 * vco = 1.5958, -0.8129, 0 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], * * temp = MAD(yco, yuv.yyyy, off) * temp = MAD(uco, yuv.uuuu, temp) * result = MAD(vco, yuv.vvvv, temp) */ /* TODO: calc consts in the shader */ const float Loff = -0.0627; const float Coff = -0.502; float uvcosf, uvsinf; float yco; float uco[3], vco[3], off[3]; float bright, cont, gamma; int ref = pPriv->transform_index; float ps_alu_consts[12]; float vs_alu_consts[4]; cont = RTFContrast(pPriv->contrast); bright = RTFBrightness(pPriv->brightness); gamma = (float)pPriv->gamma / 1000.0; uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); /* overlay video also does pre-gamma contrast/sat adjust, should we? */ yco = trans[ref].RefLuma * cont; uco[0] = -trans[ref].RefRCr * uvsinf; uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; uco[2] = trans[ref].RefBCb * uvcosf; vco[0] = trans[ref].RefRCr * uvcosf; vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; vco[2] = trans[ref].RefBCb * uvsinf; off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; // XXX gamma = 1.0; /* setup the ps consts */ ps_alu_consts[0] = off[0]; ps_alu_consts[1] = off[1]; ps_alu_consts[2] = off[2]; ps_alu_consts[3] = yco; ps_alu_consts[4] = uco[0]; ps_alu_consts[5] = uco[1]; ps_alu_consts[6] = uco[2]; ps_alu_consts[7] = gamma; ps_alu_consts[8] = vco[0]; ps_alu_consts[9] = vco[1]; ps_alu_consts[10] = vco[2]; ps_alu_consts[11] = 0.0; CLEAR (cb_conf); CLEAR (tex_res); CLEAR (tex_samp); CLEAR (vs_conf); CLEAR (ps_conf); dst_obj.bo = radeon_get_pixmap_bo(pPixmap); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); dst_obj.surface = radeon_get_pixmap_surface(pPixmap); dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); src_obj.pitch = pPriv->src_pitch; src_obj.width = pPriv->w; src_obj.height = pPriv->h; src_obj.bpp = 16; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = pPriv->src_bo[pPriv->currentBuffer]; src_obj.tiling_flags = 0; src_obj.surface = NULL; dst_obj.width = pPixmap->drawable.width; dst_obj.height = pPixmap->drawable.height; dst_obj.bpp = pPixmap->drawable.bitsPerPixel; dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; if (!R600SetAccelState(pScrn, &src_obj, NULL, &dst_obj, accel_state->xv_vs_offset, accel_state->xv_ps_offset, 3, 0xffffffff)) return; #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); r600_set_default_state(pScrn); r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* PS bool constant */ switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); break; case FOURCC_UYVY: case FOURCC_YUY2: default: r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); break; } /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; vs_conf.shader_size = accel_state->vs_size; vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; ps_conf.num_gprs = 3; ps_conf.stack_size = 1; ps_conf.uncached_first_inst = 1; ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* PS alu constants */ r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); /* Texture */ switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; /* Y texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; tex_res.surface = NULL; tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_X; /* Y */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.request_size = 1; tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; /* xxx: switch to bicubic */ tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ r600_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 1; tex_res.format = FMT_8; tex_res.w = accel_state->src_obj[0].width >> 1; tex_res.h = accel_state->src_obj[0].height >> 1; tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; tex_res.base = pPriv->planev_offset; tex_res.mip_base = pPriv->planev_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* U or V sampler */ tex_samp.id = 1; r600_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 2; tex_res.format = FMT_8; tex_res.w = accel_state->src_obj[0].width >> 1; tex_res.h = accel_state->src_obj[0].height >> 1; tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; tex_res.base = pPriv->planeu_offset; tex_res.mip_base = pPriv->planeu_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ tex_samp.id = 2; r600_set_tex_sampler(pScrn, &tex_samp); break; case FOURCC_UYVY: case FOURCC_YUY2: default: accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; /* YUV texture */ tex_res.id = 0; tex_res.w = accel_state->src_obj[0].width; tex_res.h = accel_state->src_obj[0].height; tex_res.pitch = accel_state->src_obj[0].pitch >> 1; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; tex_res.base = 0; tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; if (pPriv->id == FOURCC_UYVY) tex_res.format = FMT_GB_GR; else tex_res.format = FMT_BG_RG; tex_res.dst_sel_x = SQ_SEL_Y; tex_res.dst_sel_y = SQ_SEL_X; tex_res.dst_sel_z = SQ_SEL_Z; tex_res.dst_sel_w = SQ_SEL_1; tex_res.request_size = 1; tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* YUV sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; /* xxx: switch to bicubic */ tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ r600_set_tex_sampler(pScrn, &tex_samp); break; } cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; switch (accel_state->dst_obj.bpp) { case 16: if (pPixmap->drawable.depth == 15) { cb_conf.format = COLOR_1_5_5_5; cb_conf.comp_swap = 1; /* ARGB */ } else { cb_conf.format = COLOR_5_6_5; cb_conf.comp_swap = 2; /* RGB */ } #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN16; #endif break; case 32: cb_conf.format = COLOR_8_8_8_8; cb_conf.comp_swap = 1; /* ARGB */ #if X_BYTE_ORDER == X_BIG_ENDIAN cb_conf.endian = ENDIAN_8IN32; #endif break; default: return; } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; cb_conf.pmask = 0xf; cb_conf.rop = 3; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 1; r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); r600_set_spi(pScrn, (1 - 1), 1); vs_alu_consts[0] = 1.0 / pPriv->w; vs_alu_consts[1] = 1.0 / pPriv->h; vs_alu_consts[2] = 0.0; vs_alu_consts[3] = 0.0; /* VS alu constants */ r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs, sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) r600_cp_wait_vline_sync(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } while (nBox--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; float *vb; dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); vb[0] = (float)dstX; vb[1] = (float)dstY; vb[2] = (float)srcX; vb[3] = (float)srcY; vb[4] = (float)dstX; vb[5] = (float)(dstY + dsth); vb[6] = (float)srcX; vb[7] = (float)(srcY + srch); vb[8] = (float)(dstX + dstw); vb[9] = (float)(dstY + dsth); vb[10] = (float)(srcX + srcw); vb[11] = (float)(srcY + srch); radeon_vbo_commit(pScrn, &accel_state->vbo); pBox++; } r600_finish_op(pScrn, 16); DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } xserver-xorg-video-ati-7.5.0+git20150819/src/r6xx_accel.c000066400000000000000000001152661256524674500225120ustar00rootroot00000000000000/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: Alex Deucher * Matthias Hopf */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "xf86.h" #include #include "radeon.h" #include "r600_shader.h" #include "radeon_reg.h" #include "r600_reg.h" #include "r600_state.h" #include "radeon_vbo.h" #include "radeon_exa_shared.h" static const uint32_t R600_ROP[16] = { RADEON_ROP3_ZERO, /* GXclear */ RADEON_ROP3_DSa, /* Gxand */ RADEON_ROP3_SDna, /* GXandReverse */ RADEON_ROP3_S, /* GXcopy */ RADEON_ROP3_DSna, /* GXandInverted */ RADEON_ROP3_D, /* GXnoop */ RADEON_ROP3_DSx, /* GXxor */ RADEON_ROP3_DSo, /* GXor */ RADEON_ROP3_DSon, /* GXnor */ RADEON_ROP3_DSxn, /* GXequiv */ RADEON_ROP3_Dn, /* GXinvert */ RADEON_ROP3_SDno, /* GXorReverse */ RADEON_ROP3_Sn, /* GXcopyInverted */ RADEON_ROP3_DSno, /* GXorInverted */ RADEON_ROP3_DSan, /* GXnand */ RADEON_ROP3_ONE, /* GXset */ }; /* we try and batch operations together under KMS - but it doesn't work yet without misrendering */ #define KMS_MULTI_OP 1 /* Flush the indirect buffer to the kernel for submission to the card */ void R600CPFlushIndirect(ScrnInfoPtr pScrn) { radeon_cs_flush_indirect(pScrn); } void R600IBDiscard(ScrnInfoPtr pScrn) { radeon_ib_discard(pScrn); } void r600_wait_3d_idle_clean(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); //flush caches, don't generate timestamp BEGIN_BATCH(5); PACK3(IT_EVENT_WRITE, 1); E32(CACHE_FLUSH_AND_INV_EVENT); // wait for 3D idle clean EREG(WAIT_UNTIL, (WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit)); END_BATCH(); } void r600_wait_3d_idle(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(3); EREG(WAIT_UNTIL, WAIT_3D_IDLE_bit); END_BATCH(); } void r600_start_3d(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); if (info->ChipFamily < CHIP_FAMILY_RV770) { BEGIN_BATCH(5); PACK3(IT_START_3D_CMDBUF, 1); E32(0); } else BEGIN_BATCH(3); PACK3(IT_CONTEXT_CONTROL, 2); E32(0x80000000); E32(0x80000000); END_BATCH(); } /* * Setup of functional groups */ // asic stack/thread/gpr limits - need to query the drm static void r600_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf) { uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; RADEONInfoPtr info = RADEONPTR(pScrn); if ((info->ChipFamily == CHIP_FAMILY_RV610) || (info->ChipFamily == CHIP_FAMILY_RV620) || (info->ChipFamily == CHIP_FAMILY_RS780) || (info->ChipFamily == CHIP_FAMILY_RS880) || (info->ChipFamily == CHIP_FAMILY_RV710)) sq_config = 0; // no VC else sq_config = VC_ENABLE_bit; sq_config |= (DX9_CONSTS_bit | ALU_INST_PREFER_VECTOR_bit | (sq_conf->ps_prio << PS_PRIO_shift) | (sq_conf->vs_prio << VS_PRIO_shift) | (sq_conf->gs_prio << GS_PRIO_shift) | (sq_conf->es_prio << ES_PRIO_shift)); sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) | (sq_conf->num_vs_gprs << NUM_VS_GPRS_shift) | (sq_conf->num_temp_gprs << NUM_CLAUSE_TEMP_GPRS_shift)); sq_gpr_resource_mgmt_2 = ((sq_conf->num_gs_gprs << NUM_GS_GPRS_shift) | (sq_conf->num_es_gprs << NUM_ES_GPRS_shift)); sq_thread_resource_mgmt = ((sq_conf->num_ps_threads << NUM_PS_THREADS_shift) | (sq_conf->num_vs_threads << NUM_VS_THREADS_shift) | (sq_conf->num_gs_threads << NUM_GS_THREADS_shift) | (sq_conf->num_es_threads << NUM_ES_THREADS_shift)); sq_stack_resource_mgmt_1 = ((sq_conf->num_ps_stack_entries << NUM_PS_STACK_ENTRIES_shift) | (sq_conf->num_vs_stack_entries << NUM_VS_STACK_ENTRIES_shift)); sq_stack_resource_mgmt_2 = ((sq_conf->num_gs_stack_entries << NUM_GS_STACK_ENTRIES_shift) | (sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift)); BEGIN_BATCH(8); PACK0(SQ_CONFIG, 6); E32(sq_config); E32(sq_gpr_resource_mgmt_1); E32(sq_gpr_resource_mgmt_2); E32(sq_thread_resource_mgmt); E32(sq_stack_resource_mgmt_1); E32(sq_stack_resource_mgmt_2); END_BATCH(); } void r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain) { uint32_t cb_color_info, cb_color_control; unsigned pitch, slice, h, array_mode; RADEONInfoPtr info = RADEONPTR(pScrn); if (cb_conf->surface) { switch (cb_conf->surface->level[0].mode) { case RADEON_SURF_MODE_1D: array_mode = 2; break; case RADEON_SURF_MODE_2D: array_mode = 4; break; default: array_mode = 0; break; } pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1; slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1; } else { array_mode = cb_conf->array_mode; pitch = (cb_conf->w / 8) - 1; h = RADEON_ALIGN(cb_conf->h, 8); slice = ((cb_conf->w * h) / 64) - 1; } cb_color_info = ((cb_conf->endian << ENDIAN_shift) | (cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) | (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) | (cb_conf->number_type << NUMBER_TYPE_shift) | (cb_conf->comp_swap << COMP_SWAP_shift) | (cb_conf->tile_mode << CB_COLOR0_INFO__TILE_MODE_shift)); if (cb_conf->read_size) cb_color_info |= CB_COLOR0_INFO__READ_SIZE_bit; if (cb_conf->blend_clamp) cb_color_info |= BLEND_CLAMP_bit; if (cb_conf->clear_color) cb_color_info |= CLEAR_COLOR_bit; if (cb_conf->blend_bypass) cb_color_info |= BLEND_BYPASS_bit; if (cb_conf->blend_float32) cb_color_info |= BLEND_FLOAT32_bit; if (cb_conf->simple_float) cb_color_info |= SIMPLE_FLOAT_bit; if (cb_conf->round_mode) cb_color_info |= CB_COLOR0_INFO__ROUND_MODE_bit; if (cb_conf->tile_compact) cb_color_info |= TILE_COMPACT_bit; if (cb_conf->source_format) cb_color_info |= SOURCE_FORMAT_bit; BEGIN_BATCH(3 + 2); EREG((CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8)); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); // rv6xx workaround if ((info->ChipFamily > CHIP_FAMILY_R600) && (info->ChipFamily < CHIP_FAMILY_RV770)) { BEGIN_BATCH(2); PACK3(IT_SURFACE_BASE_UPDATE, 1); E32((2 << cb_conf->id)); END_BATCH(); } /* Set CMASK & TILE buffer to the offset of color buffer as * we don't use those this shouldn't cause any issue and we * then have a valid cmd stream */ BEGIN_BATCH(3 + 2); EREG((CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256 RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(3 + 2); EREG((CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256 RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(9); // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib EREG((CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) | (slice << SLICE_TILE_MAX_shift))); EREG((CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) | (0 << SLICE_MAX_shift))); EREG((CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | (0 << FMASK_TILE_MAX_shift))); END_BATCH(); BEGIN_BATCH(3 + 2); EREG((CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(9); EREG(CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift)); cb_color_control = R600_ROP[cb_conf->rop] | (cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift); if (info->ChipFamily == CHIP_FAMILY_R600) { /* no per-MRT blend on R600 */ EREG(CB_COLOR_CONTROL, cb_color_control); EREG(CB_BLEND_CONTROL, cb_conf->blendcntl); } else { if (cb_conf->blend_enable) cb_color_control |= PER_MRT_BLEND_bit; EREG(CB_COLOR_CONTROL, cb_color_control); EREG(CB_BLEND0_CONTROL, cb_conf->blendcntl); } END_BATCH(); } static void r600_cp_set_surface_sync(ScrnInfoPtr pScrn, uint32_t sync_type, uint32_t size, uint64_t mc_addr, struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t cp_coher_size; if (size == 0xffffffff) cp_coher_size = 0xffffffff; else cp_coher_size = ((size + 255) >> 8); BEGIN_BATCH(5 + 2); PACK3(IT_SURFACE_SYNC, 4); E32(sync_type); E32(cp_coher_size); E32((mc_addr >> 8)); E32(10); /* poll interval */ RELOC_BATCH(bo, rdomains, wdomain); END_BATCH(); } /* inserts a wait for vline in the command stream */ void r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop) { RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc; if (!crtc) return; if (!crtc->enabled) return; if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); if (start >= stop) return; drmmode_crtc = crtc->driver_private; BEGIN_BATCH(11); /* set the VLINE range */ EREG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ (start << AVIVO_D1MODE_VLINE_START_SHIFT) | (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); /* tell the CP to poll the VLINE state register */ PACK3(IT_WAIT_REG_MEM, 6); E32(IT_WAIT_REG | IT_WAIT_EQ); E32(IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS)); E32(0); E32(0); // Ref value E32(AVIVO_D1MODE_VLINE_STAT); // Mask E32(10); // Wait interval /* add crtc reloc */ PACK3(IT_NOP, 1); E32(drmmode_crtc->mode_crtc->crtc_id); END_BATCH(); } void r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(8); /* Interpolator setup */ EREG(SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift)); PACK0(SPI_PS_IN_CONTROL_0, 3); E32((num_interp << NUM_INTERP_shift)); E32(0); E32(0); END_BATCH(); } void r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; sq_pgm_resources = ((fs_conf->num_gprs << NUM_GPRS_shift) | (fs_conf->stack_size << STACK_SIZE_shift)); if (fs_conf->dx10_clamp) sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit; BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_FS, fs_conf->shader_addr >> 8); RELOC_BATCH(fs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(6); EREG(SQ_PGM_RESOURCES_FS, sq_pgm_resources); EREG(SQ_PGM_CF_OFFSET_FS, 0); END_BATCH(); } void r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; sq_pgm_resources = ((vs_conf->num_gprs << NUM_GPRS_shift) | (vs_conf->stack_size << STACK_SIZE_shift)); if (vs_conf->dx10_clamp) sq_pgm_resources |= SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit; if (vs_conf->fetch_cache_lines) sq_pgm_resources |= (vs_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); if (vs_conf->uncached_first_inst) sq_pgm_resources |= UNCACHED_FIRST_INST_bit; /* flush SQ cache */ r600_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, vs_conf->shader_size, vs_conf->shader_addr, vs_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_VS, vs_conf->shader_addr >> 8); RELOC_BATCH(vs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(6); EREG(SQ_PGM_RESOURCES_VS, sq_pgm_resources); EREG(SQ_PGM_CF_OFFSET_VS, 0); END_BATCH(); } void r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; sq_pgm_resources = ((ps_conf->num_gprs << NUM_GPRS_shift) | (ps_conf->stack_size << STACK_SIZE_shift)); if (ps_conf->dx10_clamp) sq_pgm_resources |= SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit; if (ps_conf->fetch_cache_lines) sq_pgm_resources |= (ps_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); if (ps_conf->uncached_first_inst) sq_pgm_resources |= UNCACHED_FIRST_INST_bit; if (ps_conf->clamp_consts) sq_pgm_resources |= CLAMP_CONSTS_bit; /* flush SQ cache */ r600_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, ps_conf->shader_size, ps_conf->shader_addr, ps_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); EREG(SQ_PGM_START_PS, ps_conf->shader_addr >> 8); RELOC_BATCH(ps_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(9); EREG(SQ_PGM_RESOURCES_PS, sq_pgm_resources); EREG(SQ_PGM_EXPORTS_PS, ps_conf->export_mode); EREG(SQ_PGM_CF_OFFSET_PS, 0); END_BATCH(); } void r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf) { RADEONInfoPtr info = RADEONPTR(pScrn); int i; const int countreg = count * (SQ_ALU_CONSTANT_offset >> 2); BEGIN_BATCH(2 + countreg); PACK0(SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg); for (i = 0; i < countreg; i++) EFLOAT(const_buf[i]); END_BATCH(); } void r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val) { RADEONInfoPtr info = RADEONPTR(pScrn); /* bool register order is: ps, vs, gs; one register each * 1 bits per bool; 32 bools each for ps, vs, gs. */ BEGIN_BATCH(3); EREG(SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); END_BATCH(); } static void r600_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t sq_vtx_constant_word2; sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) | ((res->vtx_size_dw << 2) << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift) | (res->format << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift) | (res->num_format_all << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift) | (res->endian << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)); if (res->clamp_x) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit; if (res->format_comp_all) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; if (res->srf_mode_all) sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit; /* flush vertex cache */ if ((info->ChipFamily == CHIP_FAMILY_RV610) || (info->ChipFamily == CHIP_FAMILY_RV620) || (info->ChipFamily == CHIP_FAMILY_RS780) || (info->ChipFamily == CHIP_FAMILY_RS880) || (info->ChipFamily == CHIP_FAMILY_RV710)) r600_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, accel_state->vbo.vb_offset, 0, res->bo, domain, 0); else r600_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit, accel_state->vbo.vb_offset, 0, res->bo, domain, 0); BEGIN_BATCH(9 + 2); PACK0(SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7); E32(res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS E32((res->vtx_num_entries << 2) - 1); // 1: SIZE E32(sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN E32(res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!? E32(0); // 4: n/a E32(0); // 5: n/a E32(SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE RELOC_BATCH(res->bo, domain, 0); END_BATCH(); } void r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; uint32_t sq_tex_resource_word5, sq_tex_resource_word6; uint32_t array_mode, pitch; if (tex_res->surface) { switch (tex_res->surface->level[0].mode) { case RADEON_SURF_MODE_1D: array_mode = 2; break; case RADEON_SURF_MODE_2D: array_mode = 4; break; default: array_mode = 0; break; } pitch = tex_res->surface->level[0].nblk_x >> 3; } else { array_mode = tex_res->tile_mode; pitch = (tex_res->pitch + 7) >> 3; } sq_tex_resource_word0 = ((tex_res->dim << DIM_shift) | (array_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift)); if (tex_res->w) sq_tex_resource_word0 |= (((pitch - 1) << PITCH_shift) | ((tex_res->w - 1) << TEX_WIDTH_shift)); if (tex_res->tile_type) sq_tex_resource_word0 |= TILE_TYPE_bit; sq_tex_resource_word1 = (tex_res->format << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift); if (tex_res->h) sq_tex_resource_word1 |= ((tex_res->h - 1) << TEX_HEIGHT_shift); if (tex_res->depth) sq_tex_resource_word1 |= ((tex_res->depth - 1) << TEX_DEPTH_shift); sq_tex_resource_word4 = ((tex_res->format_comp_x << FORMAT_COMP_X_shift) | (tex_res->format_comp_y << FORMAT_COMP_Y_shift) | (tex_res->format_comp_z << FORMAT_COMP_Z_shift) | (tex_res->format_comp_w << FORMAT_COMP_W_shift) | (tex_res->num_format_all << SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift) | (tex_res->endian << SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift) | (tex_res->request_size << REQUEST_SIZE_shift) | (tex_res->dst_sel_x << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) | (tex_res->dst_sel_y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) | (tex_res->dst_sel_z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) | (tex_res->dst_sel_w << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift) | (tex_res->base_level << BASE_LEVEL_shift)); if (tex_res->srf_mode_all) sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit; if (tex_res->force_degamma) sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit; sq_tex_resource_word5 = ((tex_res->last_level << LAST_LEVEL_shift) | (tex_res->base_array << BASE_ARRAY_shift) | (tex_res->last_array << LAST_ARRAY_shift)); sq_tex_resource_word6 = ((tex_res->mpeg_clamp << MPEG_CLAMP_shift) | (tex_res->perf_modulation << PERF_MODULATION_shift) | (SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift)); if (tex_res->interlaced) sq_tex_resource_word6 |= INTERLACED_bit; /* flush texture cache */ r600_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, tex_res->size, tex_res->base, tex_res->bo, domain, 0); BEGIN_BATCH(9 + 4); PACK0(SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7); E32(sq_tex_resource_word0); E32(sq_tex_resource_word1); E32(((tex_res->base) >> 8)); E32(((tex_res->mip_base) >> 8)); E32(sq_tex_resource_word4); E32(sq_tex_resource_word5); E32(sq_tex_resource_word6); RELOC_BATCH(tex_res->bo, domain, 0); RELOC_BATCH(tex_res->mip_bo, domain, 0); END_BATCH(); } void r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2; sq_tex_sampler_word0 = ((s->clamp_x << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift) | (s->clamp_y << CLAMP_Y_shift) | (s->clamp_z << CLAMP_Z_shift) | (s->xy_mag_filter << XY_MAG_FILTER_shift) | (s->xy_min_filter << XY_MIN_FILTER_shift) | (s->z_filter << Z_FILTER_shift) | (s->mip_filter << MIP_FILTER_shift) | (s->border_color << BORDER_COLOR_TYPE_shift) | (s->depth_compare << DEPTH_COMPARE_FUNCTION_shift) | (s->chroma_key << CHROMA_KEY_shift)); if (s->point_sampling_clamp) sq_tex_sampler_word0 |= POINT_SAMPLING_CLAMP_bit; if (s->tex_array_override) sq_tex_sampler_word0 |= TEX_ARRAY_OVERRIDE_bit; if (s->lod_uses_minor_axis) sq_tex_sampler_word0 |= LOD_USES_MINOR_AXIS_bit; sq_tex_sampler_word1 = ((s->min_lod << MIN_LOD_shift) | (s->max_lod << MAX_LOD_shift) | (s->lod_bias << SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift)); sq_tex_sampler_word2 = ((s->lod_bias2 << LOD_BIAS_SEC_shift) | (s->perf_mip << PERF_MIP_shift) | (s->perf_z << PERF_Z_shift)); if (s->mc_coord_truncate) sq_tex_sampler_word2 |= MC_COORD_TRUNCATE_bit; if (s->force_degamma) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit; if (s->high_precision_filter) sq_tex_sampler_word2 |= HIGH_PRECISION_FILTER_bit; if (s->fetch_4) sq_tex_sampler_word2 |= FETCH_4_bit; if (s->sample_is_pcf) sq_tex_sampler_word2 |= SAMPLE_IS_PCF_bit; if (s->type) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__TYPE_bit; BEGIN_BATCH(5); PACK0(SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); E32(sq_tex_sampler_word0); E32(sq_tex_sampler_word1); E32(sq_tex_sampler_word2); END_BATCH(); } //XXX deal with clip offsets in clip setup void r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_SCREEN_SCISSOR_TL, 2); E32(((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift))); E32(((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2); E32(((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift))); END_BATCH(); } void r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_GENERIC_SCISSOR_TL, 2); E32(((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift))); END_BATCH(); } void r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_WINDOW_SCISSOR_TL, 2); E32(((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); E32(((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); PACK0(PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2); E32(((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift))); E32(((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift))); END_BATCH(); } /* * Setup of default state */ void r600_set_default_state(ScrnInfoPtr pScrn) { tex_resource_t tex_res; shader_config_t fs_conf; sq_config_t sq_conf; int i; RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->XInited3D) return; memset(&tex_res, 0, sizeof(tex_resource_t)); memset(&fs_conf, 0, sizeof(shader_config_t)); accel_state->XInited3D = TRUE; r600_start_3d(pScrn); // SQ sq_conf.ps_prio = 0; sq_conf.vs_prio = 1; sq_conf.gs_prio = 2; sq_conf.es_prio = 3; // need to set stack/thread/gpr limits based on the asic // for now just set them low enough so any card will work // see r600_cp.c in the drm switch (info->ChipFamily) { case CHIP_FAMILY_R600: sq_conf.num_ps_gprs = 192; sq_conf.num_vs_gprs = 56; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 136; sq_conf.num_vs_threads = 48; sq_conf.num_gs_threads = 4; sq_conf.num_es_threads = 4; sq_conf.num_ps_stack_entries = 128; sq_conf.num_vs_stack_entries = 128; sq_conf.num_gs_stack_entries = 0; sq_conf.num_es_stack_entries = 0; break; case CHIP_FAMILY_RV630: case CHIP_FAMILY_RV635: sq_conf.num_ps_gprs = 84; sq_conf.num_vs_gprs = 36; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 144; sq_conf.num_vs_threads = 40; sq_conf.num_gs_threads = 4; sq_conf.num_es_threads = 4; sq_conf.num_ps_stack_entries = 40; sq_conf.num_vs_stack_entries = 40; sq_conf.num_gs_stack_entries = 32; sq_conf.num_es_stack_entries = 16; break; case CHIP_FAMILY_RV610: case CHIP_FAMILY_RV620: case CHIP_FAMILY_RS780: case CHIP_FAMILY_RS880: default: sq_conf.num_ps_gprs = 84; sq_conf.num_vs_gprs = 36; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 136; sq_conf.num_vs_threads = 48; sq_conf.num_gs_threads = 4; sq_conf.num_es_threads = 4; sq_conf.num_ps_stack_entries = 40; sq_conf.num_vs_stack_entries = 40; sq_conf.num_gs_stack_entries = 32; sq_conf.num_es_stack_entries = 16; break; case CHIP_FAMILY_RV670: sq_conf.num_ps_gprs = 144; sq_conf.num_vs_gprs = 40; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 136; sq_conf.num_vs_threads = 48; sq_conf.num_gs_threads = 4; sq_conf.num_es_threads = 4; sq_conf.num_ps_stack_entries = 40; sq_conf.num_vs_stack_entries = 40; sq_conf.num_gs_stack_entries = 32; sq_conf.num_es_stack_entries = 16; break; case CHIP_FAMILY_RV770: sq_conf.num_ps_gprs = 192; sq_conf.num_vs_gprs = 56; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 188; sq_conf.num_vs_threads = 60; sq_conf.num_gs_threads = 0; sq_conf.num_es_threads = 0; sq_conf.num_ps_stack_entries = 256; sq_conf.num_vs_stack_entries = 256; sq_conf.num_gs_stack_entries = 0; sq_conf.num_es_stack_entries = 0; break; case CHIP_FAMILY_RV730: case CHIP_FAMILY_RV740: sq_conf.num_ps_gprs = 84; sq_conf.num_vs_gprs = 36; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 188; sq_conf.num_vs_threads = 60; sq_conf.num_gs_threads = 0; sq_conf.num_es_threads = 0; sq_conf.num_ps_stack_entries = 128; sq_conf.num_vs_stack_entries = 128; sq_conf.num_gs_stack_entries = 0; sq_conf.num_es_stack_entries = 0; break; case CHIP_FAMILY_RV710: sq_conf.num_ps_gprs = 192; sq_conf.num_vs_gprs = 56; sq_conf.num_temp_gprs = 4; sq_conf.num_gs_gprs = 0; sq_conf.num_es_gprs = 0; sq_conf.num_ps_threads = 144; sq_conf.num_vs_threads = 48; sq_conf.num_gs_threads = 0; sq_conf.num_es_threads = 0; sq_conf.num_ps_stack_entries = 128; sq_conf.num_vs_stack_entries = 128; sq_conf.num_gs_stack_entries = 0; sq_conf.num_es_stack_entries = 0; break; } r600_sq_setup(pScrn, &sq_conf); /* set fake reloc for unused depth */ BEGIN_BATCH(3 + 2); EREG(DB_DEPTH_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(80); if (info->ChipFamily < CHIP_FAMILY_RV770) { EREG(TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) | (28 << TD_FIFO_CREDIT_shift))); EREG(VC_ENHANCE, 0); EREG(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); EREG(DB_DEBUG, 0x82000000); /* ? */ EREG(DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | (16 << DEPTH_FLUSH_shift) | (0 << FORCE_SUMMARIZE_shift) | (4 << DEPTH_PENDING_FREE_shift) | (16 << DEPTH_CACHELINE_FREE_shift) | 0)); } else { EREG(TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) | (28 << TD_FIFO_CREDIT_shift))); EREG(VC_ENHANCE, 0); EREG(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit); EREG(DB_DEBUG, 0); EREG(DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | (16 << DEPTH_FLUSH_shift) | (0 << FORCE_SUMMARIZE_shift) | (4 << DEPTH_PENDING_FREE_shift) | (4 << DEPTH_CACHELINE_FREE_shift) | 0)); } PACK0(SQ_VTX_BASE_VTX_LOC, 2); E32(0); E32(0); PACK0(SQ_ESGS_RING_ITEMSIZE, 9); E32(0); // SQ_ESGS_RING_ITEMSIZE E32(0); // SQ_GSVS_RING_ITEMSIZE E32(0); // SQ_ESTMP_RING_ITEMSIZE E32(0); // SQ_GSTMP_RING_ITEMSIZE E32(0); // SQ_VSTMP_RING_ITEMSIZE E32(0); // SQ_PSTMP_RING_ITEMSIZE E32(0); // SQ_FBUF_RING_ITEMSIZE E32(0); // SQ_REDUC_RING_ITEMSIZE E32(0); // SQ_GS_VERT_ITEMSIZE // DB EREG(DB_DEPTH_CONTROL, 0); PACK0(DB_RENDER_CONTROL, 2); E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); if (info->ChipFamily < CHIP_FAMILY_RV770) E32(FORCE_SHADER_Z_ORDER_bit); else E32(0); EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | (2 << ALPHA_TO_MASK_OFFSET1_shift) | (2 << ALPHA_TO_MASK_OFFSET2_shift) | (2 << ALPHA_TO_MASK_OFFSET3_shift))); EREG(DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ PACK0(DB_STENCIL_CLEAR, 2); E32(0); // DB_STENCIL_CLEAR E32(0); // DB_DEPTH_CLEAR PACK0(DB_STENCILREFMASK, 3); E32(0); // DB_STENCILREFMASK E32(0); // DB_STENCILREFMASK_BF E32(0); // SX_ALPHA_REF PACK0(CB_CLRCMP_CONTROL, 4); E32(1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC E32(0); // CB_CLRCMP_SRC E32(0); // CB_CLRCMP_DST E32(0); // CB_CLRCMP_MSK EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask); EREG(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); PACK0(SX_ALPHA_TEST_CONTROL, 5); E32(0); // SX_ALPHA_TEST_CONTROL E32(0x00000000); // CB_BLEND_RED E32(0x00000000); // CB_BLEND_GREEN E32(0x00000000); // CB_BLEND_BLUE E32(0x00000000); // CB_BLEND_ALPHA EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | (0 << WINDOW_Y_OFFSET_shift))); if (info->ChipFamily < CHIP_FAMILY_RV770) EREG(R7xx_PA_SC_EDGERULE, 0x00000000); else EREG(R7xx_PA_SC_EDGERULE, 0xAAAAAAAA); EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); END_BATCH(); /* clip boolean is set to always visible -> doesn't matter */ for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) r600_set_clip_rect(pScrn, i, 0, 0, 8192, 8192); for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) r600_set_vport_scissor(pScrn, i, 0, 0, 8192, 8192); BEGIN_BATCH(49); PACK0(PA_SC_MPASS_PS_CNTL, 2); E32(0); if (info->ChipFamily < CHIP_FAMILY_RV770) E32((WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit)); else E32((FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit | 0x00500000)); /* ? */ PACK0(PA_SC_LINE_CNTL, 9); E32(0); // PA_SC_LINE_CNTL E32(0); // PA_SC_AA_CONFIG E32(((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */ EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ E32(0); // PA_SC_AA_SAMPLE_LOCS_MCTX E32(0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M EREG(PA_SC_AA_MASK, 0xFFFFFFFF); PACK0(PA_CL_CLIP_CNTL, 5); E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL E32(FACE_bit); // PA_SU_SC_MODE_CNTL E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL E32(0); // PA_CL_VS_OUT_CNTL E32(0); // PA_CL_NANINF_CNTL PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); E32(0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL E32(0); // PA_SU_POLY_OFFSET_CLAMP E32(0); // PA_SU_POLY_OFFSET_FRONT_SCALE E32(0); // PA_SU_POLY_OFFSET_FRONT_OFFSET E32(0); // PA_SU_POLY_OFFSET_BACK_SCALE E32(0); // PA_SU_POLY_OFFSET_BACK_OFFSET // SPI if (info->ChipFamily < CHIP_FAMILY_RV770) EREG(R7xx_SPI_THREAD_GROUPING, 0); else EREG(R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift)); /* default Interpolator setup */ EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | (1 << SEMANTIC_1_shift))); PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ E32(((0 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift) | SEL_CENTROID_bit)); /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ E32(((1 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift) | SEL_CENTROID_bit)); PACK0(SPI_INPUT_Z, 4); E32(0); // SPI_INPUT_Z E32(0); // SPI_FOG_CNTL E32(0); // SPI_FOG_FUNC_SCALE E32(0); // SPI_FOG_FUNC_BIAS END_BATCH(); // clear FS fs_conf.bo = accel_state->shaders_bo; r600_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM); // VGT BEGIN_BATCH(46); PACK0(VGT_MAX_VTX_INDX, 4); E32(0xffffff); // VGT_MAX_VTX_INDX E32(0); // VGT_MIN_VTX_INDX E32(0); // VGT_INDX_OFFSET E32(0); // VGT_MULTI_PRIM_IB_RESET_INDX EREG(VGT_PRIMITIVEID_EN, 0); EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0); PACK0(VGT_INSTANCE_STEP_RATE_0, 2); E32(0); // VGT_INSTANCE_STEP_RATE_0 E32(0); // VGT_INSTANCE_STEP_RATE_1 PACK0(PA_SU_POINT_SIZE, 17); E32(0); // PA_SU_POINT_SIZE E32(0); // PA_SU_POINT_MINMAX E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL E32(0); // PA_SC_LINE_STIPPLE E32(0); // VGT_OUTPUT_PATH_CNTL E32(0); // VGT_HOS_CNTL E32(0); // VGT_HOS_MAX_TESS_LEVEL E32(0); // VGT_HOS_MIN_TESS_LEVEL E32(0); // VGT_HOS_REUSE_DEPTH E32(0); // VGT_GROUP_PRIM_TYPE E32(0); // VGT_GROUP_FIRST_DECR E32(0); // VGT_GROUP_DECR E32(0); // VGT_GROUP_VECT_0_CNTL E32(0); // VGT_GROUP_VECT_1_CNTL E32(0); // VGT_GROUP_VECT_0_FMT_CNTL E32(0); // VGT_GROUP_VECT_1_FMT_CNTL E32(0); // VGT_GS_MODE PACK0(VGT_STRMOUT_EN, 3); E32(0); // VGT_STRMOUT_EN E32(0); // VGT_REUSE_OFF E32(0); // VGT_VTX_CNT_EN EREG(VGT_STRMOUT_BUFFER_EN, 0); EREG(SX_MISC, 0); END_BATCH(); } /* * Commands */ void r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t i, count; // calculate num of packets count = 2; if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) count += (draw_conf->num_indices + 1) / 2; else count += draw_conf->num_indices; BEGIN_BATCH(8 + count); EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type); PACK3(IT_INDEX_TYPE, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); #else E32(draw_conf->index_type); #endif PACK3(IT_NUM_INSTANCES, 1); E32(draw_conf->num_instances); PACK3(IT_DRAW_INDEX_IMMD, count); E32(draw_conf->num_indices); E32(draw_conf->vgt_draw_initiator); if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) { for (i = 0; i < draw_conf->num_indices; i += 2) { if ((i + 1) == draw_conf->num_indices) E32(indices[i]); else E32((indices[i] | (indices[i + 1] << 16))); } } else { for (i = 0; i < draw_conf->num_indices; i++) E32(indices[i]); } END_BATCH(); } void r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(10); EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type); PACK3(IT_INDEX_TYPE, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); #else E32(draw_conf->index_type); #endif PACK3(IT_NUM_INSTANCES, 1); E32(draw_conf->num_instances); PACK3(IT_DRAW_INDEX_AUTO, 2); E32(draw_conf->num_indices); E32(draw_conf->vgt_draw_initiator); END_BATCH(); } void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; draw_config_t draw_conf; vtx_resource_t vtx_res; if (accel_state->vbo.vb_start_op == -1) return; CLEAR (draw_conf); CLEAR (vtx_res); if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) { R600IBDiscard(pScrn); return; } /* Vertex buffer setup */ accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op; vtx_res.id = SQ_VTX_RESOURCE_vs; vtx_res.vtx_size_dw = vtx_size / 4; vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4; vtx_res.mem_req_size = 1; vtx_res.vb_addr = accel_state->vbo.vb_start_op; vtx_res.bo = accel_state->vbo.vb_bo; #if X_BYTE_ORDER == X_BIG_ENDIAN vtx_res.endian = SQ_ENDIAN_8IN32; #endif r600_set_vtx_resource(pScrn, &vtx_res, RADEON_GEM_DOMAIN_GTT); /* Draw */ draw_conf.prim_type = DI_PT_RECTLIST; draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; draw_conf.num_instances = 1; draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; draw_conf.index_type = DI_INDEX_SIZE_16_BIT; r600_draw_auto(pScrn, &draw_conf); /* XXX drm should handle this in fence submit */ r600_wait_3d_idle_clean(pScrn); /* sync dst surface */ r600_cp_set_surface_sync(pScrn, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), accel_state->dst_size, 0, accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain); accel_state->vbo.vb_start_op = -1; accel_state->ib_reset_op = 0; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon.h000066400000000000000000000625211256524674500217240ustar00rootroot00000000000000/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin * Rickard E. Faith * Alan Hourihane * */ #ifndef _RADEON_H_ #define _RADEON_H_ #include /* For abs() */ #include /* For usleep() */ #include /* For gettimeofday() */ #include "config.h" #include "xf86str.h" #include "compiler.h" /* PCI support */ #include "xf86Pci.h" #include "exa.h" /* Exa and Cursor Support */ #include "xf86Cursor.h" /* DDC support */ #include "xf86DDC.h" /* Xv support */ #include "xf86xv.h" #include "radeon_probe.h" /* DRI support */ #include "xf86drm.h" #include "radeon_drm.h" #ifdef DAMAGE #include "damage.h" #include "globals.h" #endif #include "xf86Crtc.h" #include "X11/Xatom.h" #include "radeon_bo.h" #include "radeon_cs.h" #include "radeon_dri2.h" #include "drmmode_display.h" #include "radeon_surface.h" /* Render support */ #ifdef RENDER #include "picturestr.h" #endif #include "compat-api.h" #include "simple_list.h" #include "atipcirename.h" struct _SyncFence; #ifndef MAX #define MAX(a,b) ((a)>(b)?(a):(b)) #endif #ifndef MIN #define MIN(a,b) ((a)>(b)?(b):(a)) #endif #if HAVE_BYTESWAP_H #include #elif defined(USE_SYS_ENDIAN_H) #include #else #define bswap_16(value) \ ((((value) & 0xff) << 8) | ((value) >> 8)) #define bswap_32(value) \ (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ (uint32_t)bswap_16((uint16_t)((value) >> 16))) #define bswap_64(value) \ (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ << 32) | \ (uint64_t)bswap_32((uint32_t)((value) >> 32))) #endif #if X_BYTE_ORDER == X_BIG_ENDIAN #define le32_to_cpu(x) bswap_32(x) #define le16_to_cpu(x) bswap_16(x) #define cpu_to_le32(x) bswap_32(x) #define cpu_to_le16(x) bswap_16(x) #else #define le32_to_cpu(x) (x) #define le16_to_cpu(x) (x) #define cpu_to_le32(x) (x) #define cpu_to_le16(x) (x) #endif /* Provide substitutes for gcc's __FUNCTION__ on other compilers */ #if !defined(__GNUC__) && !defined(__FUNCTION__) # define __FUNCTION__ __func__ /* C99 */ #endif typedef enum { OPTION_ACCEL, OPTION_SW_CURSOR, OPTION_PAGE_FLIP, OPTION_EXA_PIXMAPS, OPTION_COLOR_TILING, OPTION_COLOR_TILING_2D, #ifdef RENDER OPTION_RENDER_ACCEL, OPTION_SUBPIXEL_ORDER, #endif OPTION_ACCELMETHOD, OPTION_EXA_VSYNC, OPTION_ZAPHOD_HEADS, OPTION_SWAPBUFFERS_WAIT, OPTION_DELETE_DP12, OPTION_DRI3, OPTION_DRI, OPTION_SHADOW_PRIMARY, OPTION_TEAR_FREE, } RADEONOpts; #define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ /* Buffer are aligned on 4096 byte boundaries */ #define RADEON_GPU_PAGE_SIZE 4096 #define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) #define xFixedToFloat(f) (((float) (f)) / 65536) #define RADEON_LOGLEVEL_DEBUG 4 /* for Xv, outputs */ #define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) /* Other macros */ #define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) #define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ (info->ChipFamily == CHIP_FAMILY_RV200) || \ (info->ChipFamily == CHIP_FAMILY_RS100) || \ (info->ChipFamily == CHIP_FAMILY_RS200) || \ (info->ChipFamily == CHIP_FAMILY_RV250) || \ (info->ChipFamily == CHIP_FAMILY_RV280) || \ (info->ChipFamily == CHIP_FAMILY_RS300)) #define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ (info->ChipFamily == CHIP_FAMILY_RV350) || \ (info->ChipFamily == CHIP_FAMILY_R350) || \ (info->ChipFamily == CHIP_FAMILY_RV380) || \ (info->ChipFamily == CHIP_FAMILY_R420) || \ (info->ChipFamily == CHIP_FAMILY_RV410) || \ (info->ChipFamily == CHIP_FAMILY_RS400) || \ (info->ChipFamily == CHIP_FAMILY_RS480)) #define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) #define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) #define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) #define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) #define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM)) #define IS_DCE5_VARIANT ((info->ChipFamily >= CHIP_FAMILY_BARTS)) #define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR) #define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) #define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ (info->ChipFamily == CHIP_FAMILY_R520) || \ (info->ChipFamily == CHIP_FAMILY_RV530) || \ (info->ChipFamily == CHIP_FAMILY_R580) || \ (info->ChipFamily == CHIP_FAMILY_RV560) || \ (info->ChipFamily == CHIP_FAMILY_RV570)) /* RS6xx, RS740 are technically R4xx as well, but the * clipping hardware seems to follow the r3xx restrictions */ #define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ (info->ChipFamily == CHIP_FAMILY_RV410)) #define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ (info->ChipFamily == CHIP_FAMILY_RV350) || \ (info->ChipFamily == CHIP_FAMILY_R350) || \ (info->ChipFamily == CHIP_FAMILY_RV380) || \ (info->ChipFamily == CHIP_FAMILY_R420) || \ (info->ChipFamily == CHIP_FAMILY_RV410) || \ (info->ChipFamily == CHIP_FAMILY_RS690) || \ (info->ChipFamily == CHIP_FAMILY_RS600) || \ (info->ChipFamily == CHIP_FAMILY_RS740) || \ (info->ChipFamily == CHIP_FAMILY_RS400) || \ (info->ChipFamily == CHIP_FAMILY_RS480)) #define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ (info->ChipFamily == CHIP_FAMILY_RV280) || \ (info->ChipFamily == CHIP_FAMILY_RS300) || \ (info->ChipFamily == CHIP_FAMILY_R200)) #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 #define CURSOR_WIDTH_CIK 128 #define CURSOR_HEIGHT_CIK 128 #ifdef USE_GLAMOR struct radeon_pixmap { struct radeon_surface surface; uint_fast32_t gpu_read; uint_fast32_t gpu_write; struct radeon_bo *bo; uint32_t tiling_flags; /* GEM handle for glamor-only pixmaps shared via DRI3 */ Bool handle_valid; uint32_t handle; }; #if HAS_DEVPRIVATEKEYREC extern DevPrivateKeyRec glamor_pixmap_index; #else extern int glamor_pixmap_index; #endif static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { #if HAS_DEVPRIVATEKEYREC return dixGetPrivate(&pixmap->devPrivates, &glamor_pixmap_index); #else return dixLookupPrivate(&pixmap->devPrivates, &glamor_pixmap_index); #endif } static inline void radeon_set_pixmap_private(PixmapPtr pixmap, struct radeon_pixmap *priv) { dixSetPrivate(&pixmap->devPrivates, &glamor_pixmap_index, priv); } #endif /* USE_GLAMOR */ struct radeon_exa_pixmap_priv { struct radeon_bo *bo; uint32_t tiling_flags; struct radeon_surface surface; Bool bo_mapped; Bool shared; }; #define RADEON_2D_EXA_COPY 1 #define RADEON_2D_EXA_SOLID 2 struct radeon_2d_state { int op; // uint32_t dst_pitch_offset; uint32_t src_pitch_offset; uint32_t dp_gui_master_cntl; uint32_t dp_cntl; uint32_t dp_write_mask; uint32_t dp_brush_frgd_clr; uint32_t dp_brush_bkgd_clr; uint32_t dp_src_frgd_clr; uint32_t dp_src_bkgd_clr; uint32_t default_sc_bottom_right; uint32_t dst_domain; struct radeon_bo *dst_bo; struct radeon_bo *src_bo; }; #define DMA_BO_FREE_TIME 1000 struct radeon_dma_bo { struct radeon_dma_bo *next, *prev; struct radeon_bo *bo; int expire_counter; }; struct r600_accel_object { uint32_t pitch; uint32_t width; uint32_t height; int bpp; uint32_t domain; struct radeon_bo *bo; uint32_t tiling_flags; struct radeon_surface *surface; }; struct radeon_vbo_object { int vb_offset; int vb_total; uint32_t vb_size; uint32_t vb_op_vert_size; int32_t vb_start_op; struct radeon_bo *vb_bo; unsigned verts_per_op; }; struct radeon_accel_state { /* Saved values for ScreenToScreenCopy */ int xdir; int ydir; /* render accel */ unsigned short texW[2]; unsigned short texH[2]; Bool XInited3D; /* X itself has the 3D context */ int num_gb_pipes; Bool has_tcl; Bool allowHWDFS; /* EXA */ ExaDriverPtr exa; int exaSyncMarker; int exaMarkerSynced; int engineMode; #define EXA_ENGINEMODE_UNKNOWN 0 #define EXA_ENGINEMODE_2D 1 #define EXA_ENGINEMODE_3D 2 int composite_op; PicturePtr dst_pic; PicturePtr msk_pic; PicturePtr src_pic; PixmapPtr dst_pix; PixmapPtr msk_pix; PixmapPtr src_pix; Bool is_transform[2]; PictTransform *transform[2]; /* Whether we are tiling horizontally and vertically */ Bool need_src_tile_x; Bool need_src_tile_y; /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ Bool src_tile_width; Bool src_tile_height; uint32_t *draw_header; unsigned vtx_count; unsigned num_vtx; Bool vsync; struct radeon_vbo_object vbo; struct radeon_vbo_object cbuf; /* where to discard IB from if we cancel operation */ uint32_t ib_reset_op; struct radeon_dma_bo bo_free; struct radeon_dma_bo bo_wait; struct radeon_dma_bo bo_reserved; Bool use_vbos; void (*finish_op)(ScrnInfoPtr, int); // shader storage struct radeon_bo *shaders_bo; uint32_t solid_vs_offset; uint32_t solid_ps_offset; uint32_t copy_vs_offset; uint32_t copy_ps_offset; uint32_t comp_vs_offset; uint32_t comp_ps_offset; uint32_t xv_vs_offset; uint32_t xv_ps_offset; // shader consts uint32_t solid_vs_const_offset; uint32_t solid_ps_const_offset; uint32_t copy_vs_const_offset; uint32_t copy_ps_const_offset; uint32_t comp_vs_const_offset; uint32_t comp_ps_const_offset; uint32_t comp_mask_ps_const_offset; uint32_t xv_vs_const_offset; uint32_t xv_ps_const_offset; //size/addr stuff struct r600_accel_object src_obj[2]; struct r600_accel_object dst_obj; uint32_t src_size[2]; uint32_t dst_size; uint32_t vs_size; uint64_t vs_mc_addr; uint32_t ps_size; uint64_t ps_mc_addr; // solid/copy void *copy_area; struct radeon_bo *copy_area_bo; Bool same_surface; int rop; uint32_t planemask; uint32_t fg; // composite Bool component_alpha; Bool src_alpha; // vline xf86CrtcPtr vline_crtc; int vline_y1; int vline_y2; Bool force; }; typedef struct { EntityInfoPtr pEnt; pciVideoPtr PciInfo; int Chipset; RADEONChipFamily ChipFamily; Bool (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL); void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); void (*CreateFence) (ScreenPtr pScreen, struct _SyncFence *pFence, Bool initially_triggered); int pix24bpp; /* Depth of pixmap for 24bpp fb */ Bool dac6bits; /* Use 6 bit DAC? */ int pixel_bytes; Bool directRenderingEnabled; struct radeon_dri2 dri2; /* accel */ Bool RenderAccel; /* Render */ Bool allowColorTiling; Bool allowColorTiling2D; uint_fast32_t gpu_flushed; uint_fast32_t gpu_synced; struct radeon_accel_state *accel_state; PixmapPtr fbcon_pixmap; Bool accelOn; Bool use_glamor; Bool shadow_primary; Bool tear_free; Bool exa_pixmaps; Bool exa_force_create; XF86ModReqInfo exaReq; Bool is_fast_fb; /* use direct mapping for fast fb access */ unsigned int xv_max_width; unsigned int xv_max_height; /* general */ OptionInfoPtr Options; DisplayModePtr currentMode; CreateScreenResourcesProcPtr CreateScreenResources; #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 CreateWindowProcPtr CreateWindow; #endif Bool IsSecondary; Bool r600_shadow_fb; void *fb_shadow; void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB struct radeon_2d_state state_2d; struct radeon_bo *front_bo; struct radeon_bo_manager *bufmgr; struct radeon_cs_manager *csm; struct radeon_cs *cs; struct radeon_bo *cursor_bo[32]; uint64_t vram_size; uint64_t gart_size; drmmode_rec drmmode; Bool drmmode_inited; /* r6xx+ tile config */ Bool have_tiling_info; uint32_t tile_config; int group_bytes; int num_channels; int num_banks; int r7xx_bank_op; struct radeon_surface_manager *surf_man; struct radeon_surface front_surface; /* Xv bicubic filtering */ struct radeon_bo *bicubic_bo; /* kms pageflipping */ Bool allowPageFlip; /* Perform vsync'ed SwapBuffers? */ Bool swapBuffersWait; /* cursor size */ int cursor_w; int cursor_h; #ifdef USE_GLAMOR struct { CreateGCProcPtr SavedCreateGC; RegionPtr (*SavedCopyArea)(DrawablePtr, DrawablePtr, GCPtr, int, int, int, int, int, int); void (*SavedPolyFillRect)(DrawablePtr, GCPtr, int, xRectangle*); CloseScreenProcPtr SavedCloseScreen; GetImageProcPtr SavedGetImage; GetSpansProcPtr SavedGetSpans; CreatePixmapProcPtr SavedCreatePixmap; DestroyPixmapProcPtr SavedDestroyPixmap; CopyWindowProcPtr SavedCopyWindow; ChangeWindowAttributesProcPtr SavedChangeWindowAttributes; BitmapToRegionProcPtr SavedBitmapToRegion; #ifdef RENDER CompositeProcPtr SavedComposite; TrianglesProcPtr SavedTriangles; GlyphsProcPtr SavedGlyphs; TrapezoidsProcPtr SavedTrapezoids; AddTrapsProcPtr SavedAddTraps; UnrealizeGlyphProcPtr SavedUnrealizeGlyph; #endif } glamor; #endif /* USE_GLAMOR */ } RADEONInfoRec, *RADEONInfoPtr; /* radeon_accel.c */ extern Bool RADEONAccelInit(ScreenPtr pScreen); extern void RADEONEngineInit(ScrnInfoPtr pScrn); extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); /* radeon_commonfuncs.c */ extern void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); /* radeon_exa.c */ extern unsigned eg_tile_split(unsigned tile_split); extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t); /* radeon_exa_funcs.c */ extern Bool RADEONDrawInit(ScreenPtr pScreen); extern Bool R600DrawInit(ScreenPtr pScreen); extern Bool R600LoadShaders(ScrnInfoPtr pScrn); extern Bool EVERGREENDrawInit(ScreenPtr pScreen); /* radeon_exa.c */ extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset); /* radeon_dri3.c */ Bool radeon_dri3_screen_init(ScreenPtr screen); /* radeon_kms.c */ void radeon_scanout_update_handler(ScrnInfoPtr scrn, uint32_t frame, uint64_t usec, void *event_data); /* radeon_present.c */ Bool radeon_present_screen_init(ScreenPtr screen); /* radeon_sync.c */ extern Bool radeon_sync_init(ScreenPtr screen); extern void radeon_sync_close(ScreenPtr screen); /* radeon_video.c */ extern void RADEONInitVideo(ScreenPtr pScreen); extern void RADEONResetVideo(ScrnInfoPtr pScrn); extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, Bool consider_disabled, int x1, int x2, int y1, int y2); extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int num, const char *file, const char *func, int line); void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size); extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); drmVBlankSeqType radeon_populate_vbl_request_type(xf86CrtcPtr crtc); #if XF86_CRTC_VERSION >= 5 #define RADEON_PIXMAP_SHARING 1 #endif static inline struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix) { #ifdef USE_GLAMOR RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); if (info->use_glamor) { struct radeon_pixmap *priv; priv = radeon_get_pixmap_private(pPix); return priv ? &priv->surface : NULL; } else #endif { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return &driver_priv->surface; } return NULL; } uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); static inline void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo) { #ifdef USE_GLAMOR RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); if (info->use_glamor) { struct radeon_pixmap *priv; priv = radeon_get_pixmap_private(pPix); if (priv == NULL && bo == NULL) return; if (priv) { if (priv->bo == bo) return; if (priv->bo) radeon_bo_unref(priv->bo); if (!bo) { free(priv); priv = NULL; } } if (bo) { uint32_t pitch; if (!priv) { priv = calloc(1, sizeof (struct radeon_pixmap)); if (!priv) goto out; } radeon_bo_ref(bo); priv->bo = bo; radeon_bo_get_tiling(bo, &priv->tiling_flags, &pitch); } out: radeon_set_pixmap_private(pPix, priv); } else #endif /* USE_GLAMOR */ { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); if (driver_priv) { uint32_t pitch; if (driver_priv->bo) radeon_bo_unref(driver_priv->bo); radeon_bo_ref(bo); driver_priv->bo = bo; radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch); } } } static inline struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix) { #ifdef USE_GLAMOR RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); if (info->use_glamor) { struct radeon_pixmap *priv; priv = radeon_get_pixmap_private(pPix); return priv ? priv->bo : NULL; } else #endif { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return driver_priv ? driver_priv->bo : NULL; } return NULL; } static inline Bool radeon_get_pixmap_shared(PixmapPtr pPix) { #ifdef USE_GLAMOR RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); if (info->use_glamor) { ErrorF("glamor sharing todo\n"); return FALSE; } else #endif { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return driver_priv->shared; } return FALSE; } #define CP_PACKET0(reg, n) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) #define CP_PACKET1(reg0, reg1) \ (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) #define CP_PACKET2() \ (RADEON_CP_PACKET2) #define CP_PACKET3(pkt, n) \ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) #define RADEON_VERBOSE 0 #define BEGIN_RING(n) do { \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ } \ radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); \ } while (0) #define ADVANCE_RING() do { \ radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ } while (0) #define OUT_RING(x) do { \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ } \ radeon_cs_write_dword(info->cs, (x)); \ } while (0) #define OUT_RING_REG(reg, val) \ do { \ OUT_RING(CP_PACKET0(reg, 0)); \ OUT_RING(val); \ } while (0) #define OUT_RING_RELOC(x, read_domains, write_domain) \ do { \ int _ret; \ _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ } while(0) #define FLUSH_RING() \ do { \ if (RADEON_VERBOSE) \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "FLUSH_RING in %s\n", __FUNCTION__); \ radeon_cs_flush_indirect(pScrn); \ } while (0) #define CS_FULL(cs) ((cs)->cdw > 15 * 1024) #define RADEON_SWITCH_TO_2D() \ do { \ uint32_t flush = 0; \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ flush = 1; \ break; \ case EXA_ENGINEMODE_3D: \ flush = CS_FULL(info->cs); \ break; \ case EXA_ENGINEMODE_2D: \ flush = CS_FULL(info->cs); \ break; \ } \ if (flush) { \ radeon_cs_flush_indirect(pScrn); \ } \ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ } while (0); #define RADEON_SWITCH_TO_3D() \ do { \ uint32_t flush = 0; \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ flush = 1; \ break; \ case EXA_ENGINEMODE_2D: \ flush = CS_FULL(info->cs); \ break; \ case EXA_ENGINEMODE_3D: \ flush = CS_FULL(info->cs); \ break; \ } \ if (flush) { \ radeon_cs_flush_indirect(pScrn); \ } \ if (!info->accel_state->XInited3D) \ RADEONInit3DEngine(pScrn); \ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ } while (0); /* Memory mapped register access macros */ #define BEGIN_ACCEL_RELOC(n, r) do { \ int _nqw = (n) + (r); \ BEGIN_RING(2*_nqw); \ } while (0) #define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \ driver_priv = exaGetPixmapDriverPrivate(pPix); \ OUT_RING_REG((reg), (value)); \ OUT_RING_RELOC(driver_priv->bo, (rd), (wd)); \ } while(0) #define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0) #define EMIT_WRITE_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, 0, RADEON_GEM_DOMAIN_VRAM) #define OUT_TEXTURE_REG(reg, offset, bo) do { \ OUT_RING_REG((reg), (offset)); \ OUT_RING_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \ } while(0) #define EMIT_COLORPITCH(reg, value, pPix) do { \ driver_priv = exaGetPixmapDriverPrivate(pPix); \ OUT_RING_REG((reg), value); \ OUT_RING_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \ } while(0) static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) { if (pScrn->pScreen) exaWaitSync(pScrn->pScreen); } enum { RADEON_CREATE_PIXMAP_SCANOUT = 0x02000000, RADEON_CREATE_PIXMAP_DRI2 = 0x04000000, RADEON_CREATE_PIXMAP_TILING_MICRO_SQUARE = 0x08000000, RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */ RADEON_CREATE_PIXMAP_SZBUFFER = 0x80000000, /* for eg */ }; #define RADEON_CREATE_PIXMAP_TILING_FLAGS \ (RADEON_CREATE_PIXMAP_TILING_MICRO_SQUARE | \ RADEON_CREATE_PIXMAP_TILING_MACRO | \ RADEON_CREATE_PIXMAP_TILING_MICRO | \ RADEON_CREATE_PIXMAP_DEPTH | \ RADEON_CREATE_PIXMAP_SZBUFFER) /* Compute log base 2 of val. */ static __inline__ int RADEONLog2(int val) { int bits; #if (defined __i386__ || defined __x86_64__) && (defined __GNUC__) __asm volatile("bsrl %1, %0" : "=r" (bits) : "c" (val) ); return bits; #else for (bits = 0; val != 0; val >>= 1, ++bits) ; return bits - 1; #endif } #define RADEON_TILING_MASK 0xff #define RADEON_TILING_LINEAR 0x0 #endif /* _RADEON_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_accel.c000066400000000000000000001171601256524674500230460ustar00rootroot00000000000000/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif /* * Authors: * Kevin E. Martin * Rickard E. Faith * Alan Hourihane * * Credits: * * Thanks to Ani Joshi for providing source * code to his Radeon driver. Portions of this file are based on the * initialization code for that driver. * * References: * * !!!! FIXME !!!! * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April * 1999. * * RAGE 128 Software Development Manual (Technical Reference Manual P/N * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * * Notes on unimplemented XAA optimizations: * * SetClipping: This has been removed as XAA expects 16bit registers * for full clipping. * TwoPointLine: The Radeon supports this. Not Bresenham. * DashedLine with non-power-of-two pattern length: Apparently, there is * no way to set the length of the pattern -- it is always * assumed to be 8 or 32 (or 1024?). * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference * Manual where it states that monochrome expansion of frame * buffer data is not supported. * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid * direct/indirect method. If we had more data registers, * then we could do better. If XAA supported a trigger write * address, the code would be simpler. * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8 * pattern from frame buffer memory. * ImageWrites: Same as CPUToScreenColorExpandFill * */ #include #include #include /* Driver data structures */ #include "radeon.h" #include "radeon_glamor.h" #include "radeon_reg.h" #include "r600_reg.h" #include "radeon_probe.h" #include "radeon_version.h" #include "ati_pciids_gen.h" /* Line support */ #include "miline.h" /* X and server generic header files */ #include "xf86.h" static int RADEONDRMGetNumPipes(ScrnInfoPtr pScrn, int *num_pipes) { RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info np2; np2.value = (unsigned long)num_pipes; np2.request = RADEON_INFO_NUM_GB_PIPES; return drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &np2, sizeof(np2)); } /* Initialize the acceleration hardware */ void RADEONEngineInit(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); info->accel_state->num_gb_pipes = 0; if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { int num_pipes; if(RADEONDRMGetNumPipes(pScrn, &num_pipes) < 0) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to determine num pipes from DRM, falling back to " "manual look-up!\n"); info->accel_state->num_gb_pipes = 0; } else { info->accel_state->num_gb_pipes = num_pipes; } } } int radeon_cs_space_remaining(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); return (info->cs->ndw - info->cs->cdw); } void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) { switch(swap) { case RADEON_HOST_DATA_SWAP_HDW: { unsigned int *d = (unsigned int *)dst; unsigned int *s = (unsigned int *)src; unsigned int nwords = size >> 2; for (; nwords > 0; --nwords, ++d, ++s) *d = ((*s & 0xffff) << 16) | ((*s >> 16) & 0xffff); return; } case RADEON_HOST_DATA_SWAP_32BIT: { unsigned int *d = (unsigned int *)dst; unsigned int *s = (unsigned int *)src; unsigned int nwords = size >> 2; for (; nwords > 0; --nwords, ++d, ++s) #ifdef __powerpc__ asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d)); #else *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00) | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24); #endif return; } case RADEON_HOST_DATA_SWAP_16BIT: { unsigned short *d = (unsigned short *)dst; unsigned short *s = (unsigned short *)src; unsigned int nwords = size >> 1; for (; nwords > 0; --nwords, ++d, ++s) #ifdef __powerpc__ asm volatile("sthbrx %0,0,%1" : : "r" (*s), "r" (d)); #else *d = (*s >> 8) | (*s << 8); #endif return; } } if (src != dst) memcpy(dst, src, size); } Bool RADEONAccelInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); if (info->directRenderingEnabled) { if (info->use_glamor) { if (!radeon_glamor_init(pScreen)) { info->use_glamor = FALSE; return FALSE; } } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { if (!EVERGREENDrawInit(pScreen)) return FALSE; } else if (info->ChipFamily >= CHIP_FAMILY_R600) { if (!R600DrawInit(pScreen)) return FALSE; } else { if (!RADEONDrawInit(pScreen)) return FALSE; } } return TRUE; } static void RADEONInit3DEngineInternal(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t gb_tile_config, vap_cntl; info->accel_state->texW[0] = info->accel_state->texH[0] = info->accel_state->texW[1] = info->accel_state->texH[1] = 1; if (IS_R300_3D || IS_R500_3D) { gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); switch(info->accel_state->num_gb_pipes) { case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; default: case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; } BEGIN_RING(2*3); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); BEGIN_RING(2*3); OUT_RING_REG(R300_GB_AA_CONFIG, 0); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); ADVANCE_RING(); BEGIN_RING(2*4); OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | R300_COLOR_ROUND_NEAREST)); OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | R300_ALPHA0_SHADING_GOURAUD | R300_RGB1_SHADING_GOURAUD | R300_ALPHA1_SHADING_GOURAUD | R300_RGB2_SHADING_GOURAUD | R300_ALPHA2_SHADING_GOURAUD | R300_RGB3_SHADING_GOURAUD | R300_ALPHA3_SHADING_GOURAUD)); OUT_RING_REG(R300_GA_OFFSET, 0); ADVANCE_RING(); BEGIN_RING(2*5); OUT_RING_REG(R300_SU_TEX_WRAP, 0); OUT_RING_REG(R300_SU_POLY_OFFSET_ENABLE, 0); OUT_RING_REG(R300_SU_CULL_MODE, R300_FACE_NEG); OUT_RING_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); OUT_RING_REG(R300_SU_DEPTH_OFFSET, 0); ADVANCE_RING(); /* setup the VAP */ if (info->accel_state->has_tcl) vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); else vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); if ((info->ChipFamily == CHIP_FAMILY_R300) || (info->ChipFamily == CHIP_FAMILY_R350)) vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); else if (info->ChipFamily == CHIP_FAMILY_RV530) vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); else if ((info->ChipFamily == CHIP_FAMILY_RV410) || (info->ChipFamily == CHIP_FAMILY_R420)) vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); else if ((info->ChipFamily == CHIP_FAMILY_R520) || (info->ChipFamily == CHIP_FAMILY_R580) || (info->ChipFamily == CHIP_FAMILY_RV560) || (info->ChipFamily == CHIP_FAMILY_RV570)) vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); else vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); if (info->accel_state->has_tcl) BEGIN_RING(2*15); else BEGIN_RING(2*9); OUT_RING_REG(R300_VAP_VTX_STATE_CNTL, 0); OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); if (info->accel_state->has_tcl) OUT_RING_REG(R300_VAP_CNTL_STATUS, 0); else OUT_RING_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); OUT_RING_REG(R300_VAP_CNTL, vap_cntl); OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); OUT_RING_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); OUT_RING_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_0_SHIFT) | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_1_SHIFT))); OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_2_SHIFT))); if (info->accel_state->has_tcl) { OUT_RING_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); OUT_RING_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); OUT_RING_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); OUT_RING_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); OUT_RING_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); OUT_RING_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); } ADVANCE_RING(); /* pre-load the vertex shaders */ if (info->accel_state->has_tcl) { BEGIN_RING(2*37); /* exa composite shader program */ OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0)); /* PVS inst 0 - dst X,Y */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 1 - src X */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_X)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 2 - src Y */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_Y)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(1) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 3 - src X / w */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(1) | R300_PVS_DST_WE_X)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 4 - src y / h */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(1) | R300_PVS_DST_WE_Y)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(1) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 5 - mask X */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_Z)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(2) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 6 - mask Y */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(3) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 7 - mask X / w */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(2) | R300_PVS_DST_WE_X)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(2) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 8 - mask y / h */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(2) | R300_PVS_DST_WE_Y)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | R300_PVS_SRC_OFFSET(3) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); ADVANCE_RING(); /* Xv shader program */ BEGIN_RING(2*9); OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(1) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); ADVANCE_RING(); /* Xv bicubic shader program */ BEGIN_RING(2*13); OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11)); /* PVS inst 0 */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(0) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(0) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 1 */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(1) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(6) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); /* PVS inst 2 */ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | R300_PVS_DST_OFFSET(2) | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | R300_PVS_SRC_OFFSET(7) | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); ADVANCE_RING(); } /* pre-load the RS instructions */ BEGIN_RING(2*4); if (IS_R300_3D) { /* rasterizer source table * R300_RS_TEX_PTR is the offset into the input RS stream * 0,1 are tex0 * 2,3 are tex1 */ OUT_RING_REG(R300_RS_IP_0, (R300_RS_TEX_PTR(0) | R300_RS_SEL_S(R300_RS_SEL_C0) | R300_RS_SEL_T(R300_RS_SEL_C1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1))); OUT_RING_REG(R300_RS_IP_1, (R300_RS_TEX_PTR(2) | R300_RS_SEL_S(R300_RS_SEL_C0) | R300_RS_SEL_T(R300_RS_SEL_C1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1))); /* src tex */ /* R300_INST_TEX_ID - select the RS source table entry * R300_INST_TEX_ADDR - the FS temp register for the texture data */ OUT_RING_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | R300_RS_INST_TEX_CN_WRITE | R300_INST_TEX_ADDR(0))); /* mask tex */ OUT_RING_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | R300_RS_INST_TEX_CN_WRITE | R300_INST_TEX_ADDR(1))); } else { /* rasterizer source table * R300_RS_TEX_PTR is the offset into the input RS stream * 0,1 are tex0 * 2,3 are tex1 */ OUT_RING_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); OUT_RING_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); /* src tex */ /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data */ OUT_RING_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | R500_RS_INST_TEX_CN_WRITE | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); /* mask tex */ OUT_RING_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | R500_RS_INST_TEX_CN_WRITE | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); } ADVANCE_RING(); if (IS_R300_3D) BEGIN_RING(2*4); else { BEGIN_RING(2*6); OUT_RING_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_RING_REG(R500_US_FC_CTRL, 0); } OUT_RING_REG(R300_US_W_FMT, 0); OUT_RING_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA)); OUT_RING_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA)); OUT_RING_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA)); ADVANCE_RING(); BEGIN_RING(2*3); OUT_RING_REG(R300_FG_DEPTH_SRC, 0); OUT_RING_REG(R300_FG_FOG_BLEND, 0); OUT_RING_REG(R300_FG_ALPHA_FUNC, 0); ADVANCE_RING(); BEGIN_RING(2*13); OUT_RING_REG(R300_RB3D_ABLENDCNTL, 0); OUT_RING_REG(R300_RB3D_ZSTENCILCNTL, 0); OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); OUT_RING_REG(R300_RB3D_BW_CNTL, 0); OUT_RING_REG(R300_RB3D_ZCNTL, 0); OUT_RING_REG(R300_RB3D_ZTOP, 0); OUT_RING_REG(R300_RB3D_ROPCNTL, 0); OUT_RING_REG(R300_RB3D_AARESOLVE_CTL, 0); OUT_RING_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | R300_GREEN_MASK_EN | R300_RED_MASK_EN | R300_ALPHA_MASK_EN)); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); OUT_RING_REG(R300_RB3D_CCTL, 0); OUT_RING_REG(R300_RB3D_DITHER_CTL, 0); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); ADVANCE_RING(); BEGIN_RING(2*5); OUT_RING_REG(R300_SC_EDGERULE, 0xA5294A5); if (IS_R300_3D) { /* clip has offset 1440 */ OUT_RING_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) | (1440 << R300_CLIP_Y_SHIFT))); OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | (4080 << R300_CLIP_Y_SHIFT))); } else { OUT_RING_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | (0 << R300_CLIP_Y_SHIFT))); OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | (4080 << R300_CLIP_Y_SHIFT))); } OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA); OUT_RING_REG(R300_SC_SCREENDOOR, 0xffffff); ADVANCE_RING(); } else if (IS_R200_3D) { BEGIN_RING(2*6); if (info->ChipFamily == CHIP_FAMILY_RS300) { OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); } else { OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, 0); } OUT_RING_REG(R200_PP_CNTL_X, 0); OUT_RING_REG(R200_PP_TXMULTI_CTL_0, 0); OUT_RING_REG(R200_SE_VTX_STATE_CNTL, 0); OUT_RING_REG(R200_SE_VTE_CNTL, 0); OUT_RING_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | R200_VAP_VF_MAX_VTX_NUM); ADVANCE_RING(); BEGIN_RING(2*4); OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, 0); OUT_RING_REG(R200_RE_CNTL, 0); OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | RADEON_BFACE_SOLID | RADEON_FFACE_SOLID | RADEON_VTX_PIX_CENTER_OGL | RADEON_ROUND_MODE_ROUND | RADEON_ROUND_PREC_4TH_PIX)); ADVANCE_RING(); } else { BEGIN_RING(2*2); if ((info->ChipFamily == CHIP_FAMILY_RADEON) || (info->ChipFamily == CHIP_FAMILY_RV200)) OUT_RING_REG(RADEON_SE_CNTL_STATUS, 0); else OUT_RING_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); OUT_RING_REG(RADEON_SE_COORD_FMT, RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 | RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 | RADEON_TEX1_W_ROUTING_USE_W0); ADVANCE_RING(); BEGIN_RING(2*2); OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | RADEON_BFACE_SOLID | RADEON_FFACE_SOLID | RADEON_VTX_PIX_CENTER_OGL | RADEON_ROUND_MODE_ROUND | RADEON_ROUND_PREC_4TH_PIX)); ADVANCE_RING(); } } /* inserts a wait for vline in the command stream */ void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop) { RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc; if (!crtc) return; if (!crtc->enabled) return; if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); if (start >= stop) return; if (!IS_AVIVO_VARIANT) { /* on pre-r5xx vline starts at CRTC scanout */ start -= crtc->y; stop -= crtc->y; } drmmode_crtc = crtc->driver_private; BEGIN_RING(2*3); if (IS_AVIVO_VARIANT) { OUT_RING_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | AVIVO_D1MODE_VLINE_INV)); } else { OUT_RING_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | RADEON_CRTC_GUI_TRIG_VLINE_INV | RADEON_CRTC_GUI_TRIG_VLINE_STALL)); } OUT_RING_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | RADEON_ENG_DISPLAY_SELECT_CRTC0)); OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); OUT_RING(drmmode_crtc->mode_crtc->crtc_id); ADVANCE_RING(); } void RADEONInit3DEngine(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); if (info->directRenderingEnabled) { RADEONInit3DEngineInternal(pScrn); } info->accel_state->XInited3D = TRUE; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_bo_helper.c000066400000000000000000000276361256524674500237460ustar00rootroot00000000000000/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H # include "config.h" #endif #include "radeon.h" #include "radeon_glamor.h" #ifdef RADEON_PIXMAP_SHARING #include "radeon_bo_gem.h" #endif static const unsigned MicroBlockTable[5][3][2] = { /*linear tiled square-tiled */ {{32, 1}, {8, 4}, {0, 0}}, /* 8 bits per pixel */ {{16, 1}, {8, 2}, {4, 4}}, /* 16 bits per pixel */ {{ 8, 1}, {4, 2}, {0, 0}}, /* 32 bits per pixel */ {{ 4, 1}, {0, 0}, {2, 2}}, /* 64 bits per pixel */ {{ 2, 1}, {0, 0}, {0, 0}} /* 128 bits per pixel */ }; /* Return true if macrotiling can be enabled */ static Bool RADEONMacroSwitch(int width, int height, int bpp, uint32_t flags, Bool rv350_mode) { unsigned tilew, tileh, microtiled, logbpp; logbpp = RADEONLog2(bpp / 8); if (logbpp > 4) return 0; microtiled = !!(flags & RADEON_TILING_MICRO); tilew = MicroBlockTable[logbpp][microtiled][0] * 8; tileh = MicroBlockTable[logbpp][microtiled][1] * 8; /* See TX_FILTER1_n.MACRO_SWITCH. */ if (rv350_mode) { return width >= tilew && height >= tileh; } else { return width > tilew && height > tileh; } } /* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that * can hold it. */ struct radeon_bo* radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, int usage_hint, int bitsPerPixel, int *new_pitch, struct radeon_surface *new_surface, uint32_t *new_tiling) { RADEONInfoPtr info = RADEONPTR(pScrn); int pitch, base_align; uint32_t size, heighta; int cpp = bitsPerPixel / 8; uint32_t tiling = 0; struct radeon_surface surface; struct radeon_bo *bo; int domain = RADEON_GEM_DOMAIN_VRAM; if (usage_hint) { if (info->allowColorTiling) { if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO) tiling |= RADEON_TILING_MACRO; if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MICRO) tiling |= RADEON_TILING_MICRO; } if (usage_hint & RADEON_CREATE_PIXMAP_DEPTH) tiling |= RADEON_TILING_MACRO | RADEON_TILING_MICRO; if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP && info->shadow_primary) #ifdef CREATE_PIXMAP_USAGE_SHARED || (usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED #endif ) { tiling = 0; domain = RADEON_GEM_DOMAIN_GTT; } } /* Small pixmaps must not be macrotiled on R300, hw cannot sample them * correctly because samplers automatically switch to macrolinear. */ if (info->ChipFamily >= CHIP_FAMILY_R300 && info->ChipFamily <= CHIP_FAMILY_RS740 && (tiling & RADEON_TILING_MACRO) && !RADEONMacroSwitch(width, height, bitsPerPixel, tiling, info->ChipFamily >= CHIP_FAMILY_RV350)) { tiling &= ~RADEON_TILING_MACRO; } heighta = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling)); pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp; base_align = drmmode_get_base_align(pScrn, cpp, tiling); size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE); memset(&surface, 0, sizeof(struct radeon_surface)); if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { if (width) { surface.npix_x = width; /* need to align height to 8 for old kernel */ surface.npix_y = RADEON_ALIGN(height, 8); surface.npix_z = 1; surface.blk_w = 1; surface.blk_h = 1; surface.blk_d = 1; surface.array_size = 1; surface.last_level = 0; surface.bpe = cpp; surface.nsamples = 1; if (height < 128) { /* disable 2d tiling for small surface to work around * the fact that ddx align height to 8 pixel for old * obscure reason i can't remember */ tiling &= ~RADEON_TILING_MACRO; } surface.flags = RADEON_SURF_SCANOUT; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); if ((tiling & RADEON_TILING_MICRO)) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); } if ((tiling & RADEON_TILING_MACRO)) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) { surface.flags |= RADEON_SURF_ZBUFFER; surface.flags |= RADEON_SURF_SBUFFER; } if (radeon_surface_best(info->surf_man, &surface)) { return NULL; } if (radeon_surface_init(info->surf_man, &surface)) { return NULL; } size = surface.bo_size; base_align = surface.bo_alignment; pitch = surface.level[0].pitch_bytes; tiling = 0; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling |= RADEON_TILING_MACRO; tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; if (surface.tile_split) tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT; break; case RADEON_SURF_MODE_1D: tiling |= RADEON_TILING_MICRO; break; default: break; } } } bo = radeon_bo_open(info->bufmgr, 0, size, base_align, domain, 0); if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0) *new_tiling = tiling; *new_surface = surface; *new_pitch = pitch; return bo; } /* Get GEM handle for the pixmap */ Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle) { struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap); #ifdef USE_GLAMOR ScreenPtr screen = pixmap->drawable.pScreen; RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen)); #endif if (bo) { *handle = bo->handle; return TRUE; } #ifdef USE_GLAMOR if (info->use_glamor) { struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); CARD16 stride; CARD32 size; int fd, r; if (!priv) { priv = calloc(1, sizeof(*priv)); radeon_set_pixmap_private(pixmap, priv); } if (priv->handle_valid) { *handle = priv->handle; return TRUE; } fd = glamor_fd_from_pixmap(screen, pixmap, &stride, &size); if (fd < 0) return FALSE; r = drmPrimeFDToHandle(info->dri2.drm_fd, fd, &priv->handle); close(fd); if (r == 0) { struct drm_radeon_gem_set_tiling args = { .handle = priv->handle }; priv->handle_valid = TRUE; *handle = priv->handle; if (drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_GET_TILING, &args, sizeof(args)) == 0) priv->tiling_flags = args.tiling_flags; return TRUE; } } #endif return FALSE; } uint32_t radeon_get_pixmap_tiling_flags(PixmapPtr pPix) { #ifdef USE_GLAMOR RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); if (info->use_glamor) { struct radeon_pixmap *priv = radeon_get_pixmap_private(pPix); if (!priv || (!priv->bo && !priv->handle_valid)) { uint32_t handle; radeon_get_pixmap_handle(pPix, &handle); priv = radeon_get_pixmap_private(pPix); } return priv ? priv->tiling_flags : 0; } else #endif { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return driver_priv ? driver_priv->tiling_flags : 0; } } #ifdef RADEON_PIXMAP_SHARING Bool radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p) { int handle; if (radeon_gem_prime_share_bo(bo, &handle) != 0) return FALSE; *handle_p = (void *)(long)handle; return TRUE; } static unsigned eg_tile_split_opp(unsigned tile_split) { switch (tile_split) { case 0: tile_split = 64; break; case 1: tile_split = 128; break; case 2: tile_split = 256; break; case 3: tile_split = 512; break; default: case 4: tile_split = 1024; break; case 5: tile_split = 2048; break; case 6: tile_split = 4096; break; } return tile_split; } Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle, struct radeon_surface *surface) { ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_bo *bo; int ihandle = (int)(long)fd_handle; uint32_t size = ppix->devKind * ppix->drawable.height; bo = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size); if (!bo) return FALSE; memset(surface, 0, sizeof(struct radeon_surface)); radeon_set_pixmap_bo(ppix, bo); if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { uint32_t tiling_flags; #ifdef USE_GLAMOR if (info->use_glamor) { tiling_flags = radeon_get_pixmap_private(ppix)->tiling_flags; } else #endif { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(ppix); tiling_flags = driver_priv->tiling_flags; } surface->npix_x = ppix->drawable.width; surface->npix_y = ppix->drawable.height; surface->npix_z = 1; surface->blk_w = 1; surface->blk_h = 1; surface->blk_d = 1; surface->array_size = 1; surface->bpe = ppix->drawable.bitsPerPixel / 8; surface->nsamples = 1; /* we are requiring a recent enough libdrm version */ surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); if (tiling_flags & RADEON_TILING_MACRO) surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); else if (tiling_flags & RADEON_TILING_MICRO) surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); else surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK); surface->stencil_tile_split = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; if (radeon_surface_best(info->surf_man, surface)) { return FALSE; } if (radeon_surface_init(info->surf_man, surface)) { return FALSE; } /* we have to post hack the surface to reflect the actual size of the shared pixmap */ surface->level[0].pitch_bytes = ppix->devKind; surface->level[0].nblk_x = ppix->devKind / surface->bpe; } close(ihandle); /* we have a reference from the alloc and one from set pixmap bo, drop one */ radeon_bo_unref(bo); return TRUE; } #endif /* RADEON_PIXMAP_SHARING */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_bo_helper.h000066400000000000000000000034001256524674500237320ustar00rootroot00000000000000/* * Copyright 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef RADEON_BO_HELPER_H #define RADEON_BO_HELPER_H 1 extern struct radeon_bo* radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, int usage_hint, int bitsPerPixel, int *new_pitch, struct radeon_surface *new_surface, uint32_t *new_tiling); extern Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle); extern uint32_t radeon_get_pixmap_tiling_flags(PixmapPtr pPix); extern Bool radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p); extern Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle, struct radeon_surface *surface); #endif /* RADEON_BO_HELPER_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_chipinfo_gen.h000066400000000000000000001005651256524674500244350ustar00rootroot00000000000000/* This file is autogenerated please do not edit */ static RADEONCardInfo RADEONCards[] = { { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3155, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 }, { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 }, { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4A54, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4B48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, { 0x4C6E, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, { 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, { 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 }, { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, { 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, { 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, { 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9443, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9444, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9446, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x944A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x944B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x944C, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x944E, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9450, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9452, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x945E, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x9460, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9462, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x947B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, { 0x9480, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 }, { 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9488, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 }, { 0x9489, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 }, { 0x948A, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 }, { 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9491, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9495, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x949F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x94A0, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 }, { 0x94A1, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 }, { 0x94A3, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 }, { 0x94B1, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 }, { 0x94B3, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 }, { 0x94B4, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 }, { 0x94B5, CHIP_FAMILY_RV740, 0, 0, 0, 0, 0 }, { 0x94B9, CHIP_FAMILY_RV740, 1, 0, 0, 0, 0 }, { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94CD, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9504, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 }, { 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9506, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 }, { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9508, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 }, { 0x9509, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 }, { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9517, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9519, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x9542, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9555, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9557, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x955F, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958F, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, { 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95C6, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95C9, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CC, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x9590, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, { 0x9596, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, { 0x9597, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, { 0x9598, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, { 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, { 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, { 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, { 0x9595, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, { 0x959B, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, { 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9615, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9616, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, { 0x9640, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 }, { 0x9641, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 }, { 0x9642, CHIP_FAMILY_SUMO2, 0, 1, 0, 0, 1 }, { 0x9643, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 }, { 0x9644, CHIP_FAMILY_SUMO2, 0, 1, 0, 0, 1 }, { 0x9645, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 }, { 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 }, { 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 }, { 0x9649, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 }, { 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 }, { 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 }, { 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 }, { 0x964E, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 }, { 0x964F, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 }, { 0x9710, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, { 0x9711, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, { 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, { 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, { 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, { 0x9715, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, { 0x9802, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9803, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9804, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9805, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9806, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9807, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9808, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x9809, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x980A, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 }, { 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 }, { 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x688A, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x688C, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x688D, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x6898, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x6899, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x689B, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x689E, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 }, { 0x689C, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 }, { 0x689D, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 }, { 0x68A0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 }, { 0x68A1, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 }, { 0x68A8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68A9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68B0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 }, { 0x68B8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68B9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68BA, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68BE, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68BF, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 }, { 0x68C0, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 }, { 0x68C1, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 }, { 0x68C7, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 }, { 0x68C8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68C9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68D8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68D9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68DA, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68DE, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 }, { 0x68E0, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 }, { 0x68E1, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 }, { 0x68E4, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 }, { 0x68E5, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 }, { 0x68E8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68E9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68F1, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68F2, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68FA, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 }, { 0x6700, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6701, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6702, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6703, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6704, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6705, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6706, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6707, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6708, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6709, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6718, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6719, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x671C, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x671D, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x671F, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 }, { 0x6720, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 }, { 0x6721, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 }, { 0x6722, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6723, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6724, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 }, { 0x6725, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 }, { 0x6726, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6727, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6728, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6729, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6738, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6739, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x673E, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 }, { 0x6740, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6741, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6742, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6743, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6744, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6745, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6746, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6747, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6748, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6749, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x674A, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6750, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6751, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6758, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6759, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x675B, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x675D, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x675F, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6840, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6841, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6842, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6843, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 }, { 0x6849, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6850, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6858, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6859, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 }, { 0x6760, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 }, { 0x6761, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 }, { 0x6762, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6763, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6764, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 }, { 0x6765, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 }, { 0x6766, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6767, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6768, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6770, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6771, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6772, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6778, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x677B, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 }, { 0x9900, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9901, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9903, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9904, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9905, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9906, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9907, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9908, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9909, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x990A, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x990B, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x990C, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x990D, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x990E, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x990F, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9910, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9913, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9917, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9918, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9919, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9990, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9991, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9992, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9993, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9994, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9995, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9996, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9997, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x9998, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x9999, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x999A, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x999B, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x999C, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x999D, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x99A0, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x99A2, CHIP_FAMILY_ARUBA, 1, 1, 0, 0, 0 }, { 0x99A4, CHIP_FAMILY_ARUBA, 0, 1, 0, 0, 0 }, { 0x6780, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6784, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6788, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x678A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6790, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6791, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6792, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6798, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6799, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x679A, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x679B, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x679E, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x679F, CHIP_FAMILY_TAHITI, 0, 0, 0, 0, 0 }, { 0x6800, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 }, { 0x6801, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 }, { 0x6802, CHIP_FAMILY_PITCAIRN, 1, 0, 0, 0, 0 }, { 0x6806, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6808, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6809, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6810, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6811, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6816, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6817, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6818, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6819, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x684C, CHIP_FAMILY_PITCAIRN, 0, 0, 0, 0, 0 }, { 0x6820, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6821, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6822, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6823, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6824, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6825, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6826, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6827, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6828, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x6829, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x682A, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x682B, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x682C, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x682D, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x682F, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6830, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6831, CHIP_FAMILY_VERDE, 1, 0, 0, 0, 0 }, { 0x6835, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x6837, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x6838, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x6839, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x683B, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x683D, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x683F, CHIP_FAMILY_VERDE, 0, 0, 0, 0, 0 }, { 0x6600, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6601, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6602, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6603, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6604, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6605, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6606, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6607, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6608, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 }, { 0x6610, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 }, { 0x6611, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 }, { 0x6613, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 }, { 0x6617, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6620, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6621, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6623, CHIP_FAMILY_OLAND, 1, 0, 0, 0, 0 }, { 0x6631, CHIP_FAMILY_OLAND, 0, 0, 0, 0, 0 }, { 0x6660, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x6663, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x6664, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x6665, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x6667, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x666F, CHIP_FAMILY_HAINAN, 1, 0, 0, 0, 0 }, { 0x6640, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 }, { 0x6641, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 }, { 0x6646, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 }, { 0x6647, CHIP_FAMILY_BONAIRE, 1, 0, 0, 0, 0 }, { 0x6649, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x6650, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x6651, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x6658, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x665C, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x665D, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x665F, CHIP_FAMILY_BONAIRE, 0, 0, 0, 0, 0 }, { 0x9830, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x9831, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x9832, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x9833, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x9834, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x9835, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x9836, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x9837, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x9838, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x9839, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x983A, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x983B, CHIP_FAMILY_KABINI, 1, 1, 0, 0, 1 }, { 0x983C, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x983D, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x983E, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x983F, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 }, { 0x9850, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9851, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9852, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9853, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9854, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9855, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9856, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9857, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9858, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x9859, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985A, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985B, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985C, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985D, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985E, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x985F, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, { 0x1304, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x1305, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1306, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x1307, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1309, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130A, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130B, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130C, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130D, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130E, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x130F, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1310, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1311, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1312, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1313, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1315, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1316, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x1317, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x1318, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, { 0x131B, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x131C, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x131D, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, { 0x67A0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67A1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67A2, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67A8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67A9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67AA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67B0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67B1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67B8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67B9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67BA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, { 0x67BE, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 }, }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_chipset_gen.h000066400000000000000000001022561256524674500242740ustar00rootroot00000000000000/* This file is autogenerated please do not edit */ SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, { PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" }, { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, { PCI_CHIP_RV380_3155, "ATI FireMV 2400 3155 (PCI)" }, { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, { PCI_CHIP_R420_JT, "ATI Radeon X800 VE (R420) JT (AGP)" }, { PCI_CHIP_R481_4B48, "ATI Radeon X850 (R480) (AGP)" }, { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, { PCI_CHIP_RV280_4C6E, "ATI FireMV 2400 PCI" }, { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" }, { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" }, { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" }, { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" }, { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" }, { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" }, { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, { PCI_CHIP_R520_7100, "ATI Radeon X1800" }, { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" }, { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" }, { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" }, { PCI_CHIP_R520_7104, "ATI FireGL V7200" }, { PCI_CHIP_R520_7105, "ATI FireGL V5300" }, { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" }, { PCI_CHIP_R520_7108, "ATI Radeon X1800" }, { PCI_CHIP_R520_7109, "ATI Radeon X1800" }, { PCI_CHIP_R520_710A, "ATI Radeon X1800" }, { PCI_CHIP_R520_710B, "ATI Radeon X1800" }, { PCI_CHIP_R520_710C, "ATI Radeon X1800" }, { PCI_CHIP_R520_710E, "ATI FireGL V7300" }, { PCI_CHIP_R520_710F, "ATI FireGL V7350" }, { PCI_CHIP_RV515_7140, "ATI Radeon X1600" }, { PCI_CHIP_RV515_7141, "ATI RV505" }, { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" }, { PCI_CHIP_RV515_7143, "ATI Radeon X1550" }, { PCI_CHIP_RV515_7144, "ATI M54-GL" }, { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" }, { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" }, { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" }, { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" }, { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" }, { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" }, { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" }, { PCI_CHIP_RV515_714D, "ATI Radeon X1300" }, { PCI_CHIP_RV515_714E, "ATI Radeon X1300" }, { PCI_CHIP_RV515_714F, "ATI RV505" }, { PCI_CHIP_RV515_7151, "ATI RV505" }, { PCI_CHIP_RV515_7152, "ATI FireGL V3300" }, { PCI_CHIP_RV515_7153, "ATI FireGL V3350" }, { PCI_CHIP_RV515_715E, "ATI Radeon X1300" }, { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" }, { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" }, { PCI_CHIP_RV515_7181, "ATI Radeon X1600" }, { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" }, { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" }, { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" }, { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" }, { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" }, { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" }, { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" }, { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" }, { PCI_CHIP_RV515_718F, "ATI Radeon X1300" }, { PCI_CHIP_RV515_7193, "ATI Radeon X1550" }, { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" }, { PCI_CHIP_RV515_719B, "ATI FireMV 2250" }, { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" }, { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" }, { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" }, { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" }, { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" }, { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" }, { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" }, { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" }, { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" }, { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" }, { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" }, { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" }, { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" }, { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" }, { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" }, { PCI_CHIP_RV515_7200, "ATI Radeon X2300HD" }, { PCI_CHIP_RV515_7210, "ATI Mobility Radeon HD 2300" }, { PCI_CHIP_RV515_7211, "ATI Mobility Radeon HD 2300" }, { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, { PCI_CHIP_R580_7245, "ATI Radeon X1900" }, { PCI_CHIP_R580_7246, "ATI Radeon X1900" }, { PCI_CHIP_R580_7247, "ATI Radeon X1900" }, { PCI_CHIP_R580_7248, "ATI Radeon X1900" }, { PCI_CHIP_R580_7249, "ATI Radeon X1900" }, { PCI_CHIP_R580_724A, "ATI Radeon X1900" }, { PCI_CHIP_R580_724B, "ATI Radeon X1900" }, { PCI_CHIP_R580_724C, "ATI Radeon X1900" }, { PCI_CHIP_R580_724D, "ATI Radeon X1900" }, { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" }, { PCI_CHIP_R580_724F, "ATI Radeon X1900" }, { PCI_CHIP_RV570_7280, "ATI Radeon X1950" }, { PCI_CHIP_RV560_7281, "ATI RV560" }, { PCI_CHIP_RV560_7283, "ATI RV560" }, { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" }, { PCI_CHIP_RV560_7287, "ATI RV560" }, { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" }, { PCI_CHIP_RV570_7289, "ATI RV570" }, { PCI_CHIP_RV570_728B, "ATI RV570" }, { PCI_CHIP_RV570_728C, "ATI FireGL V7400" }, { PCI_CHIP_RV560_7290, "ATI RV560" }, { PCI_CHIP_RV560_7291, "ATI Radeon X1650" }, { PCI_CHIP_RV560_7293, "ATI Radeon X1650" }, { PCI_CHIP_RV560_7297, "ATI RV560" }, { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, { PCI_CHIP_RS600_793F, "ATI Radeon X1200" }, { PCI_CHIP_RS600_7941, "ATI Radeon X1200" }, { PCI_CHIP_RS600_7942, "ATI Radeon X1200" }, { PCI_CHIP_RS740_796C, "ATI RS740" }, { PCI_CHIP_RS740_796D, "ATI RS740M" }, { PCI_CHIP_RS740_796E, "ATI RS740" }, { PCI_CHIP_RS740_796F, "ATI RS740M" }, { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" }, { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" }, { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" }, { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" }, { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" }, { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV770_9441, "ATI Radeon HD 4870 x2" }, { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV770_9443, "ATI Radeon HD 4850 x2" }, { PCI_CHIP_RV770_9444, "ATI FirePro V8750 (FireGL)" }, { PCI_CHIP_RV770_9446, "ATI FirePro V7760 (FireGL)" }, { PCI_CHIP_RV770_944A, "ATI Mobility RADEON HD 4850" }, { PCI_CHIP_RV770_944B, "ATI Mobility RADEON HD 4850 X2" }, { PCI_CHIP_RV770_944C, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV770_944E, "ATI FirePro RV770" }, { PCI_CHIP_RV770_9450, "AMD FireStream 9270" }, { PCI_CHIP_RV770_9452, "AMD FireStream 9250" }, { PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" }, { PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" }, { PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" }, { PCI_CHIP_RV770_945E, "ATI Mobility RADEON HD 4870" }, { PCI_CHIP_RV790_9460, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV790_9462, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV770_946A, "ATI FirePro M7750" }, { PCI_CHIP_RV770_946B, "ATI M98" }, { PCI_CHIP_RV770_947A, "ATI M98" }, { PCI_CHIP_RV770_947B, "ATI M98" }, { PCI_CHIP_RV730_9480, "ATI Mobility Radeon HD 4650" }, { PCI_CHIP_RV730_9487, "ATI Radeon RV730 (AGP)" }, { PCI_CHIP_RV730_9488, "ATI Mobility Radeon HD 4670" }, { PCI_CHIP_RV730_9489, "ATI FirePro M5750" }, { PCI_CHIP_RV730_948A, "ATI Mobility Radeon HD 4670" }, { PCI_CHIP_RV730_948F, "ATI Radeon RV730 (AGP)" }, { PCI_CHIP_RV730_9490, "ATI RV730XT [Radeon HD 4670]" }, { PCI_CHIP_RV730_9491, "ATI RADEON E4600" }, { PCI_CHIP_RV730_9495, "ATI Radeon HD 4600 Series" }, { PCI_CHIP_RV730_9498, "ATI RV730 PRO [Radeon HD 4650]" }, { PCI_CHIP_RV730_949C, "ATI FirePro V7750 (FireGL)" }, { PCI_CHIP_RV730_949E, "ATI FirePro V5700 (FireGL)" }, { PCI_CHIP_RV730_949F, "ATI FirePro V3750 (FireGL)" }, { PCI_CHIP_RV740_94A0, "ATI Mobility Radeon HD 4830" }, { PCI_CHIP_RV740_94A1, "ATI Mobility Radeon HD 4850" }, { PCI_CHIP_RV740_94A3, "ATI FirePro M7740" }, { PCI_CHIP_RV740_94B1, "ATI RV740" }, { PCI_CHIP_RV740_94B3, "ATI Radeon HD 4770" }, { PCI_CHIP_RV740_94B4, "ATI Radeon HD 4700 Series" }, { PCI_CHIP_RV740_94B5, "ATI Radeon HD 4770" }, { PCI_CHIP_RV740_94B9, "ATI FirePro M5750" }, { PCI_CHIP_RV610_94C0, "ATI RV610" }, { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, { PCI_CHIP_RV610_94C4, "ATI Radeon HD 2400 PRO AGP" }, { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, { PCI_CHIP_RV610_94C6, "ATI RV610" }, { PCI_CHIP_RV610_94C7, "ATI Radeon HD 2350" }, { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, { PCI_CHIP_RV610_94CB, "ATI RADEON E2400" }, { PCI_CHIP_RV610_94CC, "ATI RV610" }, { PCI_CHIP_RV610_94CD, "ATI FireMV 2260" }, { PCI_CHIP_RV670_9500, "ATI RV670" }, { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, { PCI_CHIP_RV670_9504, "ATI Mobility Radeon HD 3850" }, { PCI_CHIP_RV670_9505, "ATI Radeon HD3850" }, { PCI_CHIP_RV670_9506, "ATI Mobility Radeon HD 3850 X2" }, { PCI_CHIP_RV670_9507, "ATI RV670" }, { PCI_CHIP_RV670_9508, "ATI Mobility Radeon HD 3870" }, { PCI_CHIP_RV670_9509, "ATI Mobility Radeon HD 3870 X2" }, { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, { PCI_CHIP_RV670_9517, "ATI Radeon HD3690" }, { PCI_CHIP_RV670_9519, "AMD Firestream 9170" }, { PCI_CHIP_RV710_9540, "ATI Radeon HD 4550" }, { PCI_CHIP_RV710_9541, "ATI Radeon RV710" }, { PCI_CHIP_RV710_9542, "ATI Radeon RV710" }, { PCI_CHIP_RV710_954E, "ATI Radeon RV710" }, { PCI_CHIP_RV710_954F, "ATI Radeon HD 4350" }, { PCI_CHIP_RV710_9552, "ATI Mobility Radeon 4300 Series" }, { PCI_CHIP_RV710_9553, "ATI Mobility Radeon 4500 Series" }, { PCI_CHIP_RV710_9555, "ATI Mobility Radeon 4500 Series" }, { PCI_CHIP_RV710_9557, "ATI FirePro RG220" }, { PCI_CHIP_RV710_955F, "ATI Mobility Radeon 4330" }, { PCI_CHIP_RV630_9580, "ATI RV630" }, { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, { PCI_CHIP_RV630_9586, "ATI Radeon HD 2600 XT AGP" }, { PCI_CHIP_RV630_9587, "ATI Radeon HD 2600 Pro AGP" }, { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" }, { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" }, { PCI_CHIP_RV630_958A, "ATI Gemini RV630" }, { PCI_CHIP_RV630_958B, "ATI Gemini Mobility Radeon HD 2600 XT" }, { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, { PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" }, { PCI_CHIP_RV630_958F, "ATI Mobility FireGL Graphics Processor" }, { PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" }, { PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" }, { PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" }, { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, { PCI_CHIP_RV620_95C6, "ATI Radeon HD 3450" }, { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, { PCI_CHIP_RV620_95C9, "ATI Radeon HD 3450" }, { PCI_CHIP_RV620_95CC, "ATI FirePro V3700" }, { PCI_CHIP_RV620_95CD, "ATI FireMV 2450" }, { PCI_CHIP_RV620_95CE, "ATI FireMV 2260" }, { PCI_CHIP_RV620_95CF, "ATI FireMV 2260" }, { PCI_CHIP_RV635_9590, "ATI Radeon HD 3600 Series" }, { PCI_CHIP_RV635_9596, "ATI Radeon HD 3650 AGP" }, { PCI_CHIP_RV635_9597, "ATI Radeon HD 3600 PRO" }, { PCI_CHIP_RV635_9598, "ATI Radeon HD 3600 XT" }, { PCI_CHIP_RV635_9599, "ATI Radeon HD 3600 PRO" }, { PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" }, { PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" }, { PCI_CHIP_RV635_9595, "ATI Mobility FireGL V5700" }, { PCI_CHIP_RV635_959B, "ATI Mobility FireGL V5725" }, { PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" }, { PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" }, { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, { PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" }, { PCI_CHIP_RS780_9615, "ATI Radeon HD 3200 Graphics" }, { PCI_CHIP_RS780_9616, "ATI Radeon 3000 Graphics" }, { PCI_CHIP_SUMO_9640, "SUMO" }, { PCI_CHIP_SUMO_9641, "SUMO" }, { PCI_CHIP_SUMO2_9642, "SUMO2" }, { PCI_CHIP_SUMO2_9643, "SUMO2" }, { PCI_CHIP_SUMO2_9644, "SUMO2" }, { PCI_CHIP_SUMO2_9645, "SUMO2" }, { PCI_CHIP_SUMO_9647, "SUMO" }, { PCI_CHIP_SUMO_9648, "SUMO" }, { PCI_CHIP_SUMO2_9649, "SUMO2" }, { PCI_CHIP_SUMO_964A, "SUMO" }, { PCI_CHIP_SUMO_964B, "SUMO" }, { PCI_CHIP_SUMO_964C, "SUMO" }, { PCI_CHIP_SUMO_964E, "SUMO" }, { PCI_CHIP_SUMO_964F, "SUMO" }, { PCI_CHIP_RS880_9710, "ATI Radeon HD 4200" }, { PCI_CHIP_RS880_9711, "ATI Radeon 4100" }, { PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" }, { PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" }, { PCI_CHIP_RS880_9714, "ATI Radeon HD 4290" }, { PCI_CHIP_RS880_9715, "ATI Radeon HD 4250" }, { PCI_CHIP_PALM_9802, "AMD Radeon HD 6310 Graphics" }, { PCI_CHIP_PALM_9803, "AMD Radeon HD 6310 Graphics" }, { PCI_CHIP_PALM_9804, "AMD Radeon HD 6250 Graphics" }, { PCI_CHIP_PALM_9805, "AMD Radeon HD 6250 Graphics" }, { PCI_CHIP_PALM_9806, "AMD Radeon HD 6300 Series Graphics" }, { PCI_CHIP_PALM_9807, "AMD Radeon HD 6200 Series Graphics" }, { PCI_CHIP_PALM_9808, "PALM" }, { PCI_CHIP_PALM_9809, "PALM" }, { PCI_CHIP_PALM_980A, "PALM" }, { PCI_CHIP_CYPRESS_6880, "CYPRESS" }, { PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_CYPRESS_688A, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_CYPRESS_688C, "AMD Firestream 9370" }, { PCI_CHIP_CYPRESS_688D, "AMD Firestream 9350" }, { PCI_CHIP_CYPRESS_6898, "ATI Radeon HD 5800 Series" }, { PCI_CHIP_CYPRESS_6899, "ATI Radeon HD 5800 Series" }, { PCI_CHIP_CYPRESS_689B, "ATI Radeon HD 5800 Series" }, { PCI_CHIP_CYPRESS_689E, "ATI Radeon HD 5800 Series" }, { PCI_CHIP_HEMLOCK_689C, "ATI Radeon HD 5900 Series" }, { PCI_CHIP_HEMLOCK_689D, "ATI Radeon HD 5900 Series" }, { PCI_CHIP_JUNIPER_68A0, "ATI Mobility Radeon HD 5800 Series" }, { PCI_CHIP_JUNIPER_68A1, "ATI Mobility Radeon HD 5800 Series" }, { PCI_CHIP_JUNIPER_68A8, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_JUNIPER_68A9, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_JUNIPER_68B0, "ATI Mobility Radeon HD 5800 Series" }, { PCI_CHIP_JUNIPER_68B8, "ATI Radeon HD 5700 Series" }, { PCI_CHIP_JUNIPER_68B9, "ATI Radeon HD 5700 Series" }, { PCI_CHIP_JUNIPER_68BA, "ATI Radeon HD 6700 Series" }, { PCI_CHIP_JUNIPER_68BE, "ATI Radeon HD 5700 Series" }, { PCI_CHIP_JUNIPER_68BF, "ATI Radeon HD 6700 Series" }, { PCI_CHIP_REDWOOD_68C0, "ATI Mobility Radeon HD 5000 Series" }, { PCI_CHIP_REDWOOD_68C1, "ATI Mobility Radeon HD 5000 Series" }, { PCI_CHIP_REDWOOD_68C7, "ATI Mobility Radeon HD 5570" }, { PCI_CHIP_REDWOOD_68C8, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_REDWOOD_68C9, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_REDWOOD_68D8, "ATI Radeon HD 5670" }, { PCI_CHIP_REDWOOD_68D9, "ATI Radeon HD 5570" }, { PCI_CHIP_REDWOOD_68DA, "ATI Radeon HD 5500 Series" }, { PCI_CHIP_REDWOOD_68DE, "REDWOOD" }, { PCI_CHIP_CEDAR_68E0, "ATI Mobility Radeon HD 5000 Series" }, { PCI_CHIP_CEDAR_68E1, "ATI Mobility Radeon HD 5000 Series" }, { PCI_CHIP_CEDAR_68E4, "ATI Mobility Radeon Graphics" }, { PCI_CHIP_CEDAR_68E5, "ATI Mobility Radeon Graphics" }, { PCI_CHIP_CEDAR_68E8, "CEDAR" }, { PCI_CHIP_CEDAR_68E9, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_CEDAR_68F1, "ATI FirePro (FireGL) Graphics Adapter" }, { PCI_CHIP_CEDAR_68F2, "ATI FirePro 2270" }, { PCI_CHIP_CEDAR_68F8, "CEDAR" }, { PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" }, { PCI_CHIP_CEDAR_68FA, "CEDAR" }, { PCI_CHIP_CEDAR_68FE, "CEDAR" }, { PCI_CHIP_CAYMAN_6700, "CAYMAN" }, { PCI_CHIP_CAYMAN_6701, "CAYMAN" }, { PCI_CHIP_CAYMAN_6702, "CAYMAN" }, { PCI_CHIP_CAYMAN_6703, "CAYMAN" }, { PCI_CHIP_CAYMAN_6704, "CAYMAN" }, { PCI_CHIP_CAYMAN_6705, "CAYMAN" }, { PCI_CHIP_CAYMAN_6706, "CAYMAN" }, { PCI_CHIP_CAYMAN_6707, "CAYMAN" }, { PCI_CHIP_CAYMAN_6708, "CAYMAN" }, { PCI_CHIP_CAYMAN_6709, "CAYMAN" }, { PCI_CHIP_CAYMAN_6718, "AMD Radeon HD 6900 Series" }, { PCI_CHIP_CAYMAN_6719, "AMD Radeon HD 6900 Series" }, { PCI_CHIP_CAYMAN_671C, "CAYMAN" }, { PCI_CHIP_CAYMAN_671D, "CAYMAN" }, { PCI_CHIP_CAYMAN_671F, "CAYMAN" }, { PCI_CHIP_BARTS_6720, "AMD Radeon HD 6900M Series" }, { PCI_CHIP_BARTS_6721, "Mobility Radeon HD 6000 Series" }, { PCI_CHIP_BARTS_6722, "BARTS" }, { PCI_CHIP_BARTS_6723, "BARTS" }, { PCI_CHIP_BARTS_6724, "Mobility Radeon HD 6000 Series" }, { PCI_CHIP_BARTS_6725, "Mobility Radeon HD 6000 Series" }, { PCI_CHIP_BARTS_6726, "BARTS" }, { PCI_CHIP_BARTS_6727, "BARTS" }, { PCI_CHIP_BARTS_6728, "BARTS" }, { PCI_CHIP_BARTS_6729, "BARTS" }, { PCI_CHIP_BARTS_6738, "AMD Radeon HD 6800 Series" }, { PCI_CHIP_BARTS_6739, "AMD Radeon HD 6800 Series" }, { PCI_CHIP_BARTS_673E, "AMD Radeon HD 6700 Series" }, { PCI_CHIP_TURKS_6740, "TURKS" }, { PCI_CHIP_TURKS_6741, "TURKS" }, { PCI_CHIP_TURKS_6742, "TURKS" }, { PCI_CHIP_TURKS_6743, "TURKS" }, { PCI_CHIP_TURKS_6744, "TURKS" }, { PCI_CHIP_TURKS_6745, "TURKS" }, { PCI_CHIP_TURKS_6746, "TURKS" }, { PCI_CHIP_TURKS_6747, "TURKS" }, { PCI_CHIP_TURKS_6748, "TURKS" }, { PCI_CHIP_TURKS_6749, "TURKS" }, { PCI_CHIP_TURKS_674A, "TURKS" }, { PCI_CHIP_TURKS_6750, "TURKS" }, { PCI_CHIP_TURKS_6751, "TURKS" }, { PCI_CHIP_TURKS_6758, "TURKS" }, { PCI_CHIP_TURKS_6759, "TURKS" }, { PCI_CHIP_TURKS_675B, "TURKS" }, { PCI_CHIP_TURKS_675D, "TURKS" }, { PCI_CHIP_TURKS_675F, "TURKS" }, { PCI_CHIP_TURKS_6840, "TURKS" }, { PCI_CHIP_TURKS_6841, "TURKS" }, { PCI_CHIP_TURKS_6842, "TURKS" }, { PCI_CHIP_TURKS_6843, "TURKS" }, { PCI_CHIP_TURKS_6849, "TURKS" }, { PCI_CHIP_TURKS_6850, "TURKS" }, { PCI_CHIP_TURKS_6858, "TURKS" }, { PCI_CHIP_TURKS_6859, "TURKS" }, { PCI_CHIP_CAICOS_6760, "CAICOS" }, { PCI_CHIP_CAICOS_6761, "CAICOS" }, { PCI_CHIP_CAICOS_6762, "CAICOS" }, { PCI_CHIP_CAICOS_6763, "CAICOS" }, { PCI_CHIP_CAICOS_6764, "CAICOS" }, { PCI_CHIP_CAICOS_6765, "CAICOS" }, { PCI_CHIP_CAICOS_6766, "CAICOS" }, { PCI_CHIP_CAICOS_6767, "CAICOS" }, { PCI_CHIP_CAICOS_6768, "CAICOS" }, { PCI_CHIP_CAICOS_6770, "CAICOS" }, { PCI_CHIP_CAICOS_6771, "CAICOS" }, { PCI_CHIP_CAICOS_6772, "CAICOS" }, { PCI_CHIP_CAICOS_6778, "CAICOS" }, { PCI_CHIP_CAICOS_6779, "CAICOS" }, { PCI_CHIP_CAICOS_677B, "CAICOS" }, { PCI_CHIP_ARUBA_9900, "ARUBA" }, { PCI_CHIP_ARUBA_9901, "ARUBA" }, { PCI_CHIP_ARUBA_9903, "ARUBA" }, { PCI_CHIP_ARUBA_9904, "ARUBA" }, { PCI_CHIP_ARUBA_9905, "ARUBA" }, { PCI_CHIP_ARUBA_9906, "ARUBA" }, { PCI_CHIP_ARUBA_9907, "ARUBA" }, { PCI_CHIP_ARUBA_9908, "ARUBA" }, { PCI_CHIP_ARUBA_9909, "ARUBA" }, { PCI_CHIP_ARUBA_990A, "ARUBA" }, { PCI_CHIP_ARUBA_990B, "ARUBA" }, { PCI_CHIP_ARUBA_990C, "ARUBA" }, { PCI_CHIP_ARUBA_990D, "ARUBA" }, { PCI_CHIP_ARUBA_990E, "ARUBA" }, { PCI_CHIP_ARUBA_990F, "ARUBA" }, { PCI_CHIP_ARUBA_9910, "ARUBA" }, { PCI_CHIP_ARUBA_9913, "ARUBA" }, { PCI_CHIP_ARUBA_9917, "ARUBA" }, { PCI_CHIP_ARUBA_9918, "ARUBA" }, { PCI_CHIP_ARUBA_9919, "ARUBA" }, { PCI_CHIP_ARUBA_9990, "ARUBA" }, { PCI_CHIP_ARUBA_9991, "ARUBA" }, { PCI_CHIP_ARUBA_9992, "ARUBA" }, { PCI_CHIP_ARUBA_9993, "ARUBA" }, { PCI_CHIP_ARUBA_9994, "ARUBA" }, { PCI_CHIP_ARUBA_9995, "ARUBA" }, { PCI_CHIP_ARUBA_9996, "ARUBA" }, { PCI_CHIP_ARUBA_9997, "ARUBA" }, { PCI_CHIP_ARUBA_9998, "ARUBA" }, { PCI_CHIP_ARUBA_9999, "ARUBA" }, { PCI_CHIP_ARUBA_999A, "ARUBA" }, { PCI_CHIP_ARUBA_999B, "ARUBA" }, { PCI_CHIP_ARUBA_999C, "ARUBA" }, { PCI_CHIP_ARUBA_999D, "ARUBA" }, { PCI_CHIP_ARUBA_99A0, "ARUBA" }, { PCI_CHIP_ARUBA_99A2, "ARUBA" }, { PCI_CHIP_ARUBA_99A4, "ARUBA" }, { PCI_CHIP_TAHITI_6780, "TAHITI" }, { PCI_CHIP_TAHITI_6784, "TAHITI" }, { PCI_CHIP_TAHITI_6788, "TAHITI" }, { PCI_CHIP_TAHITI_678A, "TAHITI" }, { PCI_CHIP_TAHITI_6790, "TAHITI" }, { PCI_CHIP_TAHITI_6791, "TAHITI" }, { PCI_CHIP_TAHITI_6792, "TAHITI" }, { PCI_CHIP_TAHITI_6798, "TAHITI" }, { PCI_CHIP_TAHITI_6799, "TAHITI" }, { PCI_CHIP_TAHITI_679A, "TAHITI" }, { PCI_CHIP_TAHITI_679B, "TAHITI" }, { PCI_CHIP_TAHITI_679E, "TAHITI" }, { PCI_CHIP_TAHITI_679F, "TAHITI" }, { PCI_CHIP_PITCAIRN_6800, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6801, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6802, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6806, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6808, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6809, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6810, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6811, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6816, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6817, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6818, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_6819, "PITCAIRN" }, { PCI_CHIP_PITCAIRN_684C, "PITCAIRN" }, { PCI_CHIP_VERDE_6820, "VERDE" }, { PCI_CHIP_VERDE_6821, "VERDE" }, { PCI_CHIP_VERDE_6822, "VERDE" }, { PCI_CHIP_VERDE_6823, "VERDE" }, { PCI_CHIP_VERDE_6824, "VERDE" }, { PCI_CHIP_VERDE_6825, "VERDE" }, { PCI_CHIP_VERDE_6826, "VERDE" }, { PCI_CHIP_VERDE_6827, "VERDE" }, { PCI_CHIP_VERDE_6828, "VERDE" }, { PCI_CHIP_VERDE_6829, "VERDE" }, { PCI_CHIP_VERDE_682A, "VERDE" }, { PCI_CHIP_VERDE_682B, "VERDE" }, { PCI_CHIP_VERDE_682C, "VERDE" }, { PCI_CHIP_VERDE_682D, "VERDE" }, { PCI_CHIP_VERDE_682F, "VERDE" }, { PCI_CHIP_VERDE_6830, "VERDE" }, { PCI_CHIP_VERDE_6831, "VERDE" }, { PCI_CHIP_VERDE_6835, "VERDE" }, { PCI_CHIP_VERDE_6837, "VERDE" }, { PCI_CHIP_VERDE_6838, "VERDE" }, { PCI_CHIP_VERDE_6839, "VERDE" }, { PCI_CHIP_VERDE_683B, "VERDE" }, { PCI_CHIP_VERDE_683D, "VERDE" }, { PCI_CHIP_VERDE_683F, "VERDE" }, { PCI_CHIP_OLAND_6600, "OLAND" }, { PCI_CHIP_OLAND_6601, "OLAND" }, { PCI_CHIP_OLAND_6602, "OLAND" }, { PCI_CHIP_OLAND_6603, "OLAND" }, { PCI_CHIP_OLAND_6604, "OLAND" }, { PCI_CHIP_OLAND_6605, "OLAND" }, { PCI_CHIP_OLAND_6606, "OLAND" }, { PCI_CHIP_OLAND_6607, "OLAND" }, { PCI_CHIP_OLAND_6608, "OLAND" }, { PCI_CHIP_OLAND_6610, "OLAND" }, { PCI_CHIP_OLAND_6611, "OLAND" }, { PCI_CHIP_OLAND_6613, "OLAND" }, { PCI_CHIP_OLAND_6617, "OLAND" }, { PCI_CHIP_OLAND_6620, "OLAND" }, { PCI_CHIP_OLAND_6621, "OLAND" }, { PCI_CHIP_OLAND_6623, "OLAND" }, { PCI_CHIP_OLAND_6631, "OLAND" }, { PCI_CHIP_HAINAN_6660, "HAINAN" }, { PCI_CHIP_HAINAN_6663, "HAINAN" }, { PCI_CHIP_HAINAN_6664, "HAINAN" }, { PCI_CHIP_HAINAN_6665, "HAINAN" }, { PCI_CHIP_HAINAN_6667, "HAINAN" }, { PCI_CHIP_HAINAN_666F, "HAINAN" }, { PCI_CHIP_BONAIRE_6640, "BONAIRE" }, { PCI_CHIP_BONAIRE_6641, "BONAIRE" }, { PCI_CHIP_BONAIRE_6646, "BONAIRE" }, { PCI_CHIP_BONAIRE_6647, "BONAIRE" }, { PCI_CHIP_BONAIRE_6649, "BONAIRE" }, { PCI_CHIP_BONAIRE_6650, "BONAIRE" }, { PCI_CHIP_BONAIRE_6651, "BONAIRE" }, { PCI_CHIP_BONAIRE_6658, "BONAIRE" }, { PCI_CHIP_BONAIRE_665C, "BONAIRE" }, { PCI_CHIP_BONAIRE_665D, "BONAIRE" }, { PCI_CHIP_BONAIRE_665F, "BONAIRE" }, { PCI_CHIP_KABINI_9830, "KABINI" }, { PCI_CHIP_KABINI_9831, "KABINI" }, { PCI_CHIP_KABINI_9832, "KABINI" }, { PCI_CHIP_KABINI_9833, "KABINI" }, { PCI_CHIP_KABINI_9834, "KABINI" }, { PCI_CHIP_KABINI_9835, "KABINI" }, { PCI_CHIP_KABINI_9836, "KABINI" }, { PCI_CHIP_KABINI_9837, "KABINI" }, { PCI_CHIP_KABINI_9838, "KABINI" }, { PCI_CHIP_KABINI_9839, "KABINI" }, { PCI_CHIP_KABINI_983A, "KABINI" }, { PCI_CHIP_KABINI_983B, "KABINI" }, { PCI_CHIP_KABINI_983C, "KABINI" }, { PCI_CHIP_KABINI_983D, "KABINI" }, { PCI_CHIP_KABINI_983E, "KABINI" }, { PCI_CHIP_KABINI_983F, "KABINI" }, { PCI_CHIP_MULLINS_9850, "MULLINS" }, { PCI_CHIP_MULLINS_9851, "MULLINS" }, { PCI_CHIP_MULLINS_9852, "MULLINS" }, { PCI_CHIP_MULLINS_9853, "MULLINS" }, { PCI_CHIP_MULLINS_9854, "MULLINS" }, { PCI_CHIP_MULLINS_9855, "MULLINS" }, { PCI_CHIP_MULLINS_9856, "MULLINS" }, { PCI_CHIP_MULLINS_9857, "MULLINS" }, { PCI_CHIP_MULLINS_9858, "MULLINS" }, { PCI_CHIP_MULLINS_9859, "MULLINS" }, { PCI_CHIP_MULLINS_985A, "MULLINS" }, { PCI_CHIP_MULLINS_985B, "MULLINS" }, { PCI_CHIP_MULLINS_985C, "MULLINS" }, { PCI_CHIP_MULLINS_985D, "MULLINS" }, { PCI_CHIP_MULLINS_985E, "MULLINS" }, { PCI_CHIP_MULLINS_985F, "MULLINS" }, { PCI_CHIP_KAVERI_1304, "KAVERI" }, { PCI_CHIP_KAVERI_1305, "KAVERI" }, { PCI_CHIP_KAVERI_1306, "KAVERI" }, { PCI_CHIP_KAVERI_1307, "KAVERI" }, { PCI_CHIP_KAVERI_1309, "KAVERI" }, { PCI_CHIP_KAVERI_130A, "KAVERI" }, { PCI_CHIP_KAVERI_130B, "KAVERI" }, { PCI_CHIP_KAVERI_130C, "KAVERI" }, { PCI_CHIP_KAVERI_130D, "KAVERI" }, { PCI_CHIP_KAVERI_130E, "KAVERI" }, { PCI_CHIP_KAVERI_130F, "KAVERI" }, { PCI_CHIP_KAVERI_1310, "KAVERI" }, { PCI_CHIP_KAVERI_1311, "KAVERI" }, { PCI_CHIP_KAVERI_1312, "KAVERI" }, { PCI_CHIP_KAVERI_1313, "KAVERI" }, { PCI_CHIP_KAVERI_1315, "KAVERI" }, { PCI_CHIP_KAVERI_1316, "KAVERI" }, { PCI_CHIP_KAVERI_1317, "KAVERI" }, { PCI_CHIP_KAVERI_1318, "KAVERI" }, { PCI_CHIP_KAVERI_131B, "KAVERI" }, { PCI_CHIP_KAVERI_131C, "KAVERI" }, { PCI_CHIP_KAVERI_131D, "KAVERI" }, { PCI_CHIP_HAWAII_67A0, "HAWAII" }, { PCI_CHIP_HAWAII_67A1, "HAWAII" }, { PCI_CHIP_HAWAII_67A2, "HAWAII" }, { PCI_CHIP_HAWAII_67A8, "HAWAII" }, { PCI_CHIP_HAWAII_67A9, "HAWAII" }, { PCI_CHIP_HAWAII_67AA, "HAWAII" }, { PCI_CHIP_HAWAII_67B0, "HAWAII" }, { PCI_CHIP_HAWAII_67B1, "HAWAII" }, { PCI_CHIP_HAWAII_67B8, "HAWAII" }, { PCI_CHIP_HAWAII_67B9, "HAWAII" }, { PCI_CHIP_HAWAII_67BA, "HAWAII" }, { PCI_CHIP_HAWAII_67BE, "HAWAII" }, { -1, NULL } }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_dri2.c000066400000000000000000001404231256524674500226350ustar00rootroot00000000000000/* * Copyright 2008 Kristian Høgsberg * Copyright 2008 Jérôme Glisse * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon.h" #include "radeon_dri2.h" #include "radeon_video.h" #ifdef DRI2 #include #include #include #include #include "radeon_bo_helper.h" #include "radeon_version.h" #include "radeon_list.h" #include "radeon_bo_gem.h" #include #if DRI2INFOREC_VERSION >= 9 #define USE_DRI2_PRIME #endif #define FALLBACK_SWAP_DELAY 16 #include "radeon_glamor.h" typedef DRI2BufferPtr BufferPtr; struct dri2_buffer_priv { PixmapPtr pixmap; unsigned int attachment; unsigned int refcnt; }; struct dri2_window_priv { xf86CrtcPtr crtc; int vblank_delta; }; #if HAS_DEVPRIVATEKEYREC static DevPrivateKeyRec dri2_window_private_key_rec; #define dri2_window_private_key (&dri2_window_private_key_rec) #else static int dri2_window_private_key_index; DevPrivateKey dri2_window_private_key = &dri2_window_private_key_index; #endif /* HAS_DEVPRIVATEKEYREC */ #define get_dri2_window_priv(window) \ ((struct dri2_window_priv*) \ dixLookupPrivate(&(window)->devPrivates, dri2_window_private_key)) static PixmapPtr get_drawable_pixmap(DrawablePtr drawable) { if (drawable->type == DRAWABLE_PIXMAP) return (PixmapPtr)drawable; else return (*drawable->pScreen->GetWindowPixmap)((WindowPtr)drawable); } static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap) { PixmapPtr old = get_drawable_pixmap(drawable); #ifdef USE_GLAMOR ScreenPtr screen = drawable->pScreen; struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); GCPtr gc; /* With a glamor pixmap, 2D pixmaps are created in texture * and without a static BO attached to it. To support DRI, * we need to create a new textured-drm pixmap and * need to copy the original content to this new textured-drm * pixmap, and then convert the old pixmap to a coherent * textured-drm pixmap which has a valid BO attached to it * and also has a valid texture, thus both glamor and DRI2 * can access it. * */ /* Copy the current contents of the pixmap to the bo. */ gc = GetScratchGC(drawable->depth, screen); if (gc) { ValidateGC(&pixmap->drawable, gc); gc->ops->CopyArea(&old->drawable, &pixmap->drawable, gc, 0, 0, old->drawable.width, old->drawable.height, 0, 0); FreeScratchGC(gc); } radeon_set_pixmap_private(pixmap, NULL); /* And redirect the pixmap to the new bo (for 3D). */ glamor_egl_exchange_buffers(old, pixmap); radeon_set_pixmap_private(old, priv); old->refcnt++; screen->ModifyPixmapHeader(old, old->drawable.width, old->drawable.height, 0, 0, pixmap->devKind, NULL); old->devPrivate.ptr = NULL; screen->DestroyPixmap(pixmap); #endif /* USE_GLAMOR*/ return old; } /* Get GEM flink name for a pixmap */ static Bool radeon_get_flink_name(RADEONInfoPtr info, PixmapPtr pixmap, uint32_t *name) { struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap); struct drm_gem_flink flink; if (bo) return radeon_gem_get_kernel_name(bo, name) == 0; if (radeon_get_pixmap_handle(pixmap, &flink.handle)) { if (drmIoctl(info->dri2.drm_fd, DRM_IOCTL_GEM_FLINK, &flink) != 0) return FALSE; *name = flink.name; return TRUE; } return FALSE; } static BufferPtr radeon_dri2_create_buffer2(ScreenPtr pScreen, DrawablePtr drawable, unsigned int attachment, unsigned int format) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); BufferPtr buffers; struct dri2_buffer_priv *privates; PixmapPtr pixmap, depth_pixmap; int flags; unsigned front_width; uint32_t tiling = 0; unsigned aligned_width = drawable->width; unsigned height = drawable->height; Bool is_glamor_pixmap = FALSE; int depth; int cpp; if (format) { depth = format; switch (depth) { case 15: cpp = 2; break; case 24: cpp = 4; break; default: cpp = depth / 8; } } else { depth = drawable->depth; cpp = drawable->bitsPerPixel / 8; } pixmap = pScreen->GetScreenPixmap(pScreen); front_width = pixmap->drawable.width; pixmap = depth_pixmap = NULL; if (attachment == DRI2BufferFrontLeft) { uint32_t handle; pixmap = get_drawable_pixmap(drawable); if (pScreen != pixmap->drawable.pScreen) pixmap = NULL; else if (info->use_glamor && !radeon_get_pixmap_handle(pixmap, &handle)) { is_glamor_pixmap = TRUE; aligned_width = pixmap->drawable.width; height = pixmap->drawable.height; pixmap = NULL; } else pixmap->refcnt++; } else if (attachment == DRI2BufferStencil && depth_pixmap) { pixmap = depth_pixmap; pixmap->refcnt++; } if (!pixmap && (is_glamor_pixmap || attachment != DRI2BufferFrontLeft)) { /* tile the back buffer */ switch(attachment) { case DRI2BufferDepth: /* macro is the preferred setting, but the 2D detiling for software * fallbacks in mesa still has issues on some configurations */ if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->allowColorTiling2D) { flags = RADEON_CREATE_PIXMAP_TILING_MACRO; } else { flags = RADEON_CREATE_PIXMAP_TILING_MICRO; } if (info->ChipFamily >= CHIP_FAMILY_CEDAR) flags |= RADEON_CREATE_PIXMAP_SZBUFFER; } else if (cpp == 2 && info->ChipFamily >= CHIP_FAMILY_R300) flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO_SQUARE; else flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO; if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON) flags |= RADEON_CREATE_PIXMAP_DEPTH; break; case DRI2BufferDepthStencil: /* macro is the preferred setting, but the 2D detiling for software * fallbacks in mesa still has issues on some configurations */ if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->allowColorTiling2D) { flags = RADEON_CREATE_PIXMAP_TILING_MACRO; } else { flags = RADEON_CREATE_PIXMAP_TILING_MICRO; } if (info->ChipFamily >= CHIP_FAMILY_CEDAR) flags |= RADEON_CREATE_PIXMAP_SZBUFFER; } else if (cpp == 2 && info->ChipFamily >= CHIP_FAMILY_R300) flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO_SQUARE; else flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO; if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON) flags |= RADEON_CREATE_PIXMAP_DEPTH; break; case DRI2BufferBackLeft: case DRI2BufferBackRight: case DRI2BufferFrontLeft: case DRI2BufferFrontRight: case DRI2BufferFakeFrontLeft: case DRI2BufferFakeFrontRight: if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->allowColorTiling2D) { flags = RADEON_CREATE_PIXMAP_TILING_MACRO; } else { flags = RADEON_CREATE_PIXMAP_TILING_MICRO; } } else flags = RADEON_CREATE_PIXMAP_TILING_MACRO; break; default: flags = 0; } if (flags & RADEON_CREATE_PIXMAP_TILING_MICRO) tiling |= RADEON_TILING_MICRO; if (flags & RADEON_CREATE_PIXMAP_TILING_MICRO_SQUARE) tiling |= RADEON_TILING_MICRO_SQUARE; if (flags & RADEON_CREATE_PIXMAP_TILING_MACRO) tiling |= RADEON_TILING_MACRO; if (aligned_width == front_width) aligned_width = pScrn->virtualX; pixmap = (*pScreen->CreatePixmap)(pScreen, aligned_width, height, depth, flags | RADEON_CREATE_PIXMAP_DRI2); } buffers = calloc(1, sizeof *buffers); if (buffers == NULL) goto error; if (attachment == DRI2BufferDepth) { depth_pixmap = pixmap; } if (pixmap) { if (!info->use_glamor) { info->exa_force_create = TRUE; exaMoveInPixmap(pixmap); info->exa_force_create = FALSE; if (exaGetPixmapDriverPrivate(pixmap) == NULL) { /* this happen if pixmap is non accelerable */ goto error; } } if (is_glamor_pixmap) pixmap = fixup_glamor(drawable, pixmap); if (!radeon_get_flink_name(info, pixmap, &buffers->name)) goto error; } privates = calloc(1, sizeof(struct dri2_buffer_priv)); if (privates == NULL) goto error; buffers->attachment = attachment; if (pixmap) { buffers->pitch = pixmap->devKind; buffers->cpp = cpp; } buffers->driverPrivate = privates; buffers->format = format; buffers->flags = 0; /* not tiled */ privates->pixmap = pixmap; privates->attachment = attachment; privates->refcnt = 1; return buffers; error: free(buffers); if (pixmap) (*pScreen->DestroyPixmap)(pixmap); return NULL; } DRI2BufferPtr radeon_dri2_create_buffer(DrawablePtr pDraw, unsigned int attachment, unsigned int format) { return radeon_dri2_create_buffer2(pDraw->pScreen, pDraw, attachment, format); } static void radeon_dri2_destroy_buffer2(ScreenPtr pScreen, DrawablePtr drawable, BufferPtr buffers) { if(buffers) { struct dri2_buffer_priv *private = buffers->driverPrivate; /* Trying to free an already freed buffer is unlikely to end well */ if (private->refcnt == 0) { ScrnInfoPtr scrn = xf86ScreenToScrn(pScreen); xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Attempted to destroy previously destroyed buffer.\ This is a programming error\n"); return; } private->refcnt--; if (private->refcnt == 0) { if (private->pixmap) (*pScreen->DestroyPixmap)(private->pixmap); free(buffers->driverPrivate); free(buffers); } } } void radeon_dri2_destroy_buffer(DrawablePtr pDraw, DRI2BufferPtr buf) { radeon_dri2_destroy_buffer2(pDraw->pScreen, pDraw, buf); } static inline PixmapPtr GetDrawablePixmap(DrawablePtr drawable) { if (drawable->type == DRAWABLE_PIXMAP) return (PixmapPtr)drawable; else { struct _Window *pWin = (struct _Window *)drawable; return drawable->pScreen->GetWindowPixmap(pWin); } } static void radeon_dri2_copy_region2(ScreenPtr pScreen, DrawablePtr drawable, RegionPtr region, BufferPtr dest_buffer, BufferPtr src_buffer) { struct dri2_buffer_priv *src_private = src_buffer->driverPrivate; struct dri2_buffer_priv *dst_private = dest_buffer->driverPrivate; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); DrawablePtr src_drawable; DrawablePtr dst_drawable; RegionPtr copy_clip; GCPtr gc; RADEONInfoPtr info = RADEONPTR(pScrn); Bool vsync; Bool translate = FALSE; int off_x = 0, off_y = 0; PixmapPtr dst_ppix; dst_ppix = dst_private->pixmap; src_drawable = &src_private->pixmap->drawable; dst_drawable = &dst_private->pixmap->drawable; if (src_private->attachment == DRI2BufferFrontLeft) { #ifdef USE_DRI2_PRIME if (drawable->pScreen != pScreen) { src_drawable = DRI2UpdatePrime(drawable, src_buffer); if (!src_drawable) return; } else #endif src_drawable = drawable; } if (dst_private->attachment == DRI2BufferFrontLeft) { #ifdef USE_DRI2_PRIME if (drawable->pScreen != pScreen) { dst_drawable = DRI2UpdatePrime(drawable, dest_buffer); if (!dst_drawable) return; dst_ppix = (PixmapPtr)dst_drawable; if (dst_drawable != drawable) translate = TRUE; } else #endif dst_drawable = drawable; } if (translate && drawable->type == DRAWABLE_WINDOW) { PixmapPtr pPix = GetDrawablePixmap(drawable); off_x = drawable->x - pPix->screen_x; off_y = drawable->y - pPix->screen_y; } gc = GetScratchGC(dst_drawable->depth, pScreen); copy_clip = REGION_CREATE(pScreen, NULL, 0); REGION_COPY(pScreen, copy_clip, region); if (translate) { REGION_TRANSLATE(pScreen, copy_clip, off_x, off_y); } (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0); ValidateGC(dst_drawable, gc); /* If this is a full buffer swap or frontbuffer flush, throttle on the * previous one */ if (dst_private->attachment == DRI2BufferFrontLeft) { if (REGION_NUM_RECTS(region) == 1) { BoxPtr extents = REGION_EXTENTS(pScreen, region); if (extents->x1 == 0 && extents->y1 == 0 && extents->x2 == drawable->width && extents->y2 == drawable->height) { struct radeon_bo *bo = radeon_get_pixmap_bo(dst_ppix); if (bo) radeon_bo_wait(bo); } } } vsync = info->accel_state->vsync; /* Driver option "SwapbuffersWait" defines if we vsync DRI2 copy-swaps. */ info->accel_state->vsync = info->swapBuffersWait; info->accel_state->force = TRUE; (*gc->ops->CopyArea)(src_drawable, dst_drawable, gc, 0, 0, drawable->width, drawable->height, off_x, off_y); info->accel_state->force = FALSE; info->accel_state->vsync = vsync; FreeScratchGC(gc); } void radeon_dri2_copy_region(DrawablePtr pDraw, RegionPtr pRegion, DRI2BufferPtr pDstBuffer, DRI2BufferPtr pSrcBuffer) { return radeon_dri2_copy_region2(pDraw->pScreen, pDraw, pRegion, pDstBuffer, pSrcBuffer); } enum DRI2FrameEventType { DRI2_SWAP, DRI2_FLIP, DRI2_WAITMSC, }; typedef struct _DRI2FrameEvent { XID drawable_id; ClientPtr client; enum DRI2FrameEventType type; unsigned frame; xf86CrtcPtr crtc; OsTimerPtr timer; struct radeon_drm_queue_entry *drm_queue; /* for swaps & flips only */ DRI2SwapEventPtr event_complete; void *event_data; DRI2BufferPtr front; DRI2BufferPtr back; } DRI2FrameEventRec, *DRI2FrameEventPtr; static int DRI2InfoCnt; static void radeon_dri2_ref_buffer(BufferPtr buffer) { struct dri2_buffer_priv *private = buffer->driverPrivate; private->refcnt++; } static void radeon_dri2_unref_buffer(BufferPtr buffer) { if (buffer) { struct dri2_buffer_priv *private = buffer->driverPrivate; radeon_dri2_destroy_buffer(&(private->pixmap->drawable), buffer); } } static void radeon_dri2_client_state_changed(CallbackListPtr *ClientStateCallback, pointer data, pointer calldata) { NewClientInfoRec *clientinfo = calldata; ClientPtr pClient = clientinfo->client; switch (pClient->clientState) { case ClientStateRetained: case ClientStateGone: radeon_drm_abort_client(pClient); break; default: break; } } /* * Get current frame count delta for the specified drawable and CRTC */ static uint32_t radeon_get_msc_delta(DrawablePtr pDraw, xf86CrtcPtr crtc) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; if (pDraw && pDraw->type == DRAWABLE_WINDOW) return drmmode_crtc->interpolated_vblanks + get_dri2_window_priv((WindowPtr)pDraw)->vblank_delta; return drmmode_crtc->interpolated_vblanks; } /* * Get current frame count and timestamp of the specified CRTC */ static Bool radeon_dri2_get_crtc_msc(xf86CrtcPtr crtc, CARD64 *ust, CARD64 *msc) { if (!radeon_crtc_is_enabled(crtc) || drmmode_crtc_get_ust_msc(crtc, ust, msc) != Success) { /* CRTC is not running, extrapolate MSC and timestamp */ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ScrnInfoPtr scrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(scrn); CARD64 now, delta_t, delta_seq; if (!drmmode_crtc->dpms_last_ust) return FALSE; if (drmmode_get_current_ust(info->dri2.drm_fd, &now) != 0) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "%s cannot get current time\n", __func__); return FALSE; } delta_t = now - drmmode_crtc->dpms_last_ust; delta_seq = delta_t * drmmode_crtc->dpms_last_fps; delta_seq /= 1000000; *ust = drmmode_crtc->dpms_last_ust; delta_t = delta_seq * 1000000; delta_t /= drmmode_crtc->dpms_last_fps; *ust += delta_t; *msc = drmmode_crtc->dpms_last_seq; *msc += delta_seq; } return TRUE; } static xf86CrtcPtr radeon_dri2_drawable_crtc(DrawablePtr pDraw, Bool consider_disabled) { ScreenPtr pScreen = pDraw->pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); xf86CrtcPtr crtc = radeon_pick_best_crtc(pScrn, consider_disabled, pDraw->x, pDraw->x + pDraw->width, pDraw->y, pDraw->y + pDraw->height); if (crtc && pDraw->type == DRAWABLE_WINDOW) { struct dri2_window_priv *priv = get_dri2_window_priv((WindowPtr)pDraw); if (priv->crtc && priv->crtc != crtc) { CARD64 ust, mscold, mscnew; radeon_dri2_get_crtc_msc(priv->crtc, &ust, &mscold); radeon_dri2_get_crtc_msc(crtc, &ust, &mscnew); priv->vblank_delta += mscold - mscnew; } priv->crtc = crtc; } return crtc; } static void radeon_dri2_flip_event_abort(ScrnInfoPtr scrn, void *event_data) { free(event_data); } static void radeon_dri2_flip_event_handler(ScrnInfoPtr scrn, uint32_t frame, uint64_t usec, void *event_data) { RADEONInfoPtr info = RADEONPTR(scrn); DRI2FrameEventPtr flip = event_data; unsigned tv_sec, tv_usec; DrawablePtr drawable; ScreenPtr screen; int status; PixmapPtr pixmap; status = dixLookupDrawable(&drawable, flip->drawable_id, serverClient, M_ANY, DixWriteAccess); if (status != Success) goto abort; if (!flip->crtc) goto abort; frame += radeon_get_msc_delta(drawable, flip->crtc); screen = scrn->pScreen; pixmap = screen->GetScreenPixmap(screen); xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "%s:%d fevent[%p] width %d pitch %d (/4 %d)\n", __func__, __LINE__, flip, pixmap->drawable.width, pixmap->devKind, pixmap->devKind/4); tv_sec = usec / 1000000; tv_usec = usec % 1000000; /* We assume our flips arrive in order, so we don't check the frame */ switch (flip->type) { case DRI2_SWAP: /* Check for too small vblank count of pageflip completion, taking wraparound * into account. This usually means some defective kms pageflip completion, * causing wrong (msc, ust) return values and possible visual corruption. */ if ((frame < flip->frame) && (flip->frame - frame < 5)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "%s: Pageflip completion event has impossible msc %u < target_msc %u\n", __func__, frame, flip->frame); /* All-Zero values signal failure of (msc, ust) timestamping to client. */ frame = tv_sec = tv_usec = 0; } DRI2SwapComplete(flip->client, drawable, frame, tv_sec, tv_usec, DRI2_FLIP_COMPLETE, flip->event_complete, flip->event_data); info->drmmode.dri2_flipping = FALSE; break; default: xf86DrvMsg(scrn->scrnIndex, X_WARNING, "%s: unknown vblank event received\n", __func__); /* Unknown type */ break; } abort: radeon_dri2_flip_event_abort(scrn, event_data); } static Bool radeon_dri2_schedule_flip(ScrnInfoPtr scrn, ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back, DRI2SwapEventPtr func, void *data, unsigned int target_msc) { RADEONInfoPtr info = RADEONPTR(scrn); struct dri2_buffer_priv *back_priv; struct radeon_bo *bo; DRI2FrameEventPtr flip_info; /* Main crtc for this drawable shall finally deliver pageflip event. */ xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, FALSE); int ref_crtc_hw_id = crtc ? drmmode_get_crtc_id(crtc) : -1; flip_info = calloc(1, sizeof(DRI2FrameEventRec)); if (!flip_info) return FALSE; flip_info->drawable_id = draw->id; flip_info->client = client; flip_info->type = DRI2_SWAP; flip_info->event_complete = func; flip_info->event_data = data; flip_info->frame = target_msc; flip_info->crtc = crtc; xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "%s:%d fevent[%p]\n", __func__, __LINE__, flip_info); /* Page flip the full screen buffer */ back_priv = back->driverPrivate; bo = radeon_get_pixmap_bo(back_priv->pixmap); if (radeon_do_pageflip(scrn, client, bo->handle, RADEON_DRM_QUEUE_ID_DEFAULT, flip_info, ref_crtc_hw_id, radeon_dri2_flip_event_handler, radeon_dri2_flip_event_abort)) { info->drmmode.dri2_flipping = TRUE; return TRUE; } return FALSE; } static Bool update_front(DrawablePtr draw, DRI2BufferPtr front) { PixmapPtr pixmap; RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(draw->pScreen)); struct dri2_buffer_priv *priv = front->driverPrivate; pixmap = get_drawable_pixmap(draw); pixmap->refcnt++; if (!info->use_glamor) exaMoveInPixmap(pixmap); if (!radeon_get_flink_name(info, pixmap, &front->name)) { (*draw->pScreen->DestroyPixmap)(pixmap); return FALSE; } (*draw->pScreen->DestroyPixmap)(priv->pixmap); front->pitch = pixmap->devKind; front->cpp = pixmap->drawable.bitsPerPixel / 8; priv->pixmap = pixmap; return TRUE; } static Bool can_exchange(ScrnInfoPtr pScrn, DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back) { struct dri2_buffer_priv *front_priv = front->driverPrivate; struct dri2_buffer_priv *back_priv = back->driverPrivate; PixmapPtr front_pixmap; PixmapPtr back_pixmap = back_priv->pixmap; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; for (i = 0; i < xf86_config->num_crtc; i++) { xf86CrtcPtr crtc = xf86_config->crtc[i]; if (crtc->enabled && crtc->rotatedData) return FALSE; } if (!update_front(draw, front)) return FALSE; front_pixmap = front_priv->pixmap; if (front_pixmap->drawable.width != back_pixmap->drawable.width) return FALSE; if (front_pixmap->drawable.height != back_pixmap->drawable.height) return FALSE; if (front_pixmap->drawable.bitsPerPixel != back_pixmap->drawable.bitsPerPixel) return FALSE; if (front_pixmap->devKind != back_pixmap->devKind) return FALSE; return TRUE; } static Bool can_flip(ScrnInfoPtr pScrn, DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back) { RADEONInfoPtr info = RADEONPTR(pScrn); return draw->type == DRAWABLE_WINDOW && info->allowPageFlip && !info->drmmode.present_flipping && pScrn->vtSema && DRI2CanFlip(draw) && can_exchange(pScrn, draw, front, back); } static void radeon_dri2_exchange_buffers(DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back) { struct dri2_buffer_priv *front_priv = front->driverPrivate; struct dri2_buffer_priv *back_priv = back->driverPrivate; struct radeon_bo *front_bo, *back_bo; ScreenPtr screen; RADEONInfoPtr info; RegionRec region; int tmp; region.extents.x1 = region.extents.y1 = 0; region.extents.x2 = front_priv->pixmap->drawable.width; region.extents.y2 = front_priv->pixmap->drawable.width; region.data = NULL; DamageRegionAppend(&front_priv->pixmap->drawable, ®ion); /* Swap BO names so DRI works */ tmp = front->name; front->name = back->name; back->name = tmp; /* Swap pixmap bos */ front_bo = radeon_get_pixmap_bo(front_priv->pixmap); back_bo = radeon_get_pixmap_bo(back_priv->pixmap); radeon_set_pixmap_bo(front_priv->pixmap, back_bo); radeon_set_pixmap_bo(back_priv->pixmap, front_bo); /* Do we need to update the Screen? */ screen = draw->pScreen; info = RADEONPTR(xf86ScreenToScrn(screen)); if (front_bo == info->front_bo) { radeon_bo_ref(back_bo); radeon_bo_unref(info->front_bo); info->front_bo = back_bo; radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), back_bo); } radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap); DamageRegionProcessPending(&front_priv->pixmap->drawable); } static void radeon_dri2_frame_event_abort(ScrnInfoPtr scrn, void *event_data) { DRI2FrameEventPtr event = event_data; TimerCancel(event->timer); TimerFree(event->timer); radeon_dri2_unref_buffer(event->front); radeon_dri2_unref_buffer(event->back); free(event); } static void radeon_dri2_frame_event_handler(ScrnInfoPtr scrn, uint32_t seq, uint64_t usec, void *event_data) { DRI2FrameEventPtr event = event_data; DrawablePtr drawable; int status; int swap_type; BoxRec box; RegionRec region; if (!event->crtc) goto cleanup; status = dixLookupDrawable(&drawable, event->drawable_id, serverClient, M_ANY, DixWriteAccess); if (status != Success) goto cleanup; seq += radeon_get_msc_delta(drawable, event->crtc); switch (event->type) { case DRI2_FLIP: if (can_flip(scrn, drawable, event->front, event->back) && radeon_dri2_schedule_flip(scrn, event->client, drawable, event->front, event->back, event->event_complete, event->event_data, event->frame)) { radeon_dri2_exchange_buffers(drawable, event->front, event->back); break; } /* else fall through to exchange/blit */ case DRI2_SWAP: if (DRI2CanExchange(drawable) && can_exchange(scrn, drawable, event->front, event->back)) { radeon_dri2_exchange_buffers(drawable, event->front, event->back); swap_type = DRI2_EXCHANGE_COMPLETE; } else { box.x1 = 0; box.y1 = 0; box.x2 = drawable->width; box.y2 = drawable->height; REGION_INIT(pScreen, ®ion, &box, 0); radeon_dri2_copy_region(drawable, ®ion, event->front, event->back); swap_type = DRI2_BLIT_COMPLETE; } DRI2SwapComplete(event->client, drawable, seq, usec / 1000000, usec % 1000000, swap_type, event->event_complete, event->event_data); break; case DRI2_WAITMSC: DRI2WaitMSCComplete(event->client, drawable, seq, usec / 1000000, usec % 1000000); break; default: /* Unknown type */ xf86DrvMsg(scrn->scrnIndex, X_WARNING, "%s: unknown vblank event received\n", __func__); break; } cleanup: radeon_dri2_frame_event_abort(scrn, event_data); } drmVBlankSeqType radeon_populate_vbl_request_type(xf86CrtcPtr crtc) { drmVBlankSeqType type = 0; int crtc_id = drmmode_get_crtc_id(crtc); if (crtc_id == 1) type |= DRM_VBLANK_SECONDARY; else if (crtc_id > 1) #ifdef DRM_VBLANK_HIGH_CRTC_SHIFT type |= (crtc_id << DRM_VBLANK_HIGH_CRTC_SHIFT) & DRM_VBLANK_HIGH_CRTC_MASK; #else ErrorF("radeon driver bug: %s called for CRTC %d > 1, but " "DRM_VBLANK_HIGH_CRTC_MASK not defined at build time\n", __func__, crtc_id); #endif return type; } /* * This function should be called on a disabled CRTC only (i.e., CRTC * in DPMS-off state). It will calculate the delay necessary to reach * target_msc from present time if the CRTC were running. */ static CARD32 radeon_dri2_extrapolate_msc_delay(xf86CrtcPtr crtc, CARD64 *target_msc, CARD64 divisor, CARD64 remainder) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); int nominal_frame_rate = drmmode_crtc->dpms_last_fps; CARD64 last_vblank_ust = drmmode_crtc->dpms_last_ust; uint32_t last_vblank_seq = drmmode_crtc->dpms_last_seq; CARD64 now, target_time, delta_t; int64_t d, delta_seq; int ret; CARD32 d_ms; if (!last_vblank_ust) { *target_msc = 0; return FALLBACK_SWAP_DELAY; } ret = drmmode_get_current_ust(info->dri2.drm_fd, &now); if (ret) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s cannot get current time\n", __func__); *target_msc = 0; return FALLBACK_SWAP_DELAY; } delta_seq = *target_msc - last_vblank_seq; delta_seq *= 1000000; target_time = last_vblank_ust; target_time += delta_seq / nominal_frame_rate; d = target_time - now; if (d < 0) { /* we missed the event, adjust target_msc, do the divisor magic */ CARD64 current_msc = last_vblank_seq; delta_t = now - last_vblank_ust; delta_seq = delta_t * nominal_frame_rate; current_msc += delta_seq / 1000000; current_msc &= 0xffffffff; if (divisor == 0) { *target_msc = current_msc; d = 0; } else { *target_msc = current_msc - (current_msc % divisor) + remainder; if ((current_msc % divisor) >= remainder) *target_msc += divisor; *target_msc &= 0xffffffff; delta_seq = *target_msc - last_vblank_seq; delta_seq *= 1000000; target_time = last_vblank_ust; target_time += delta_seq / nominal_frame_rate; d = target_time - now; } } /* * convert delay to milliseconds and add margin to prevent the client * from coming back early (due to timer granularity and rounding * errors) and getting the same MSC it just got */ d_ms = (CARD32)d / 1000; if ((CARD32)d - d_ms * 1000 > 0) d_ms += 2; else d_ms++; return d_ms; } /* * Get current interpolated frame count and frame count timestamp, based on * drawable's crtc. */ static int radeon_dri2_get_msc(DrawablePtr draw, CARD64 *ust, CARD64 *msc) { xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, TRUE); /* Drawable not displayed, make up a value */ if (crtc == NULL) { *ust = 0; *msc = 0; return TRUE; } if (!radeon_dri2_get_crtc_msc(crtc, ust, msc)) return FALSE; *msc += radeon_get_msc_delta(draw, crtc); *msc &= 0xffffffff; return TRUE; } static CARD32 radeon_dri2_deferred_event(OsTimerPtr timer, CARD32 now, pointer data) { DRI2FrameEventPtr event_info = (DRI2FrameEventPtr)data; xf86CrtcPtr crtc = event_info->crtc; ScrnInfoPtr scrn; RADEONInfoPtr info; CARD64 drm_now; int ret; CARD64 delta_t, delta_seq, frame; drmmode_crtc_private_ptr drmmode_crtc; /* * This is emulated event, so its time is current time, which we * have to get in DRM-compatible form (which is a bit messy given * the information that we have at this point). Can't use now argument * because DRM event time may come from monotonic clock, while * DIX timer facility uses real-time clock. */ if (!event_info->crtc) { ErrorF("%s no crtc\n", __func__); if (event_info->drm_queue) radeon_drm_abort_entry(event_info->drm_queue); else radeon_dri2_frame_event_abort(NULL, data); return 0; } scrn = crtc->scrn; info = RADEONPTR(scrn); ret = drmmode_get_current_ust(info->dri2.drm_fd, &drm_now); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "%s cannot get current time\n", __func__); if (event_info->drm_queue) radeon_drm_queue_handler(info->dri2.drm_fd, 0, 0, 0, event_info->drm_queue); else radeon_dri2_frame_event_handler(scrn, 0, 0, data); return 0; } /* * calculate the frame number from current time * that would come from CRTC if it were running */ drmmode_crtc = event_info->crtc->driver_private; delta_t = drm_now - (CARD64)drmmode_crtc->dpms_last_ust; delta_seq = delta_t * drmmode_crtc->dpms_last_fps; delta_seq /= 1000000; frame = (CARD64)drmmode_crtc->dpms_last_seq + delta_seq; if (event_info->drm_queue) radeon_drm_queue_handler(info->dri2.drm_fd, frame, drm_now / 1000000, drm_now % 1000000, event_info->drm_queue); else radeon_dri2_frame_event_handler(scrn, frame, drm_now, data); return 0; } static void radeon_dri2_schedule_event(CARD32 delay, DRI2FrameEventPtr event_info) { event_info->timer = TimerSet(NULL, 0, delay, radeon_dri2_deferred_event, event_info); if (delay == 0) { CARD32 now = GetTimeInMillis(); radeon_dri2_deferred_event(event_info->timer, now, event_info); } } /* * Request a DRM event when the requested conditions will be satisfied. * * We need to handle the event and ask the server to wake up the client when * we receive it. */ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc, CARD64 divisor, CARD64 remainder) { ScreenPtr screen = draw->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); DRI2FrameEventPtr wait_info = NULL; struct radeon_drm_queue_entry *wait = NULL; xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, TRUE); uint32_t msc_delta; drmVBlank vbl; int ret; CARD64 current_msc; /* Truncate to match kernel interfaces; means occasional overflow * misses, but that's generally not a big deal */ target_msc &= 0xffffffff; divisor &= 0xffffffff; remainder &= 0xffffffff; /* Drawable not visible, return immediately */ if (crtc == NULL) goto out_complete; msc_delta = radeon_get_msc_delta(draw, crtc); wait_info = calloc(1, sizeof(DRI2FrameEventRec)); if (!wait_info) goto out_complete; wait_info->drawable_id = draw->id; wait_info->client = client; wait_info->type = DRI2_WAITMSC; wait_info->crtc = crtc; /* * CRTC is in DPMS off state, calculate wait time from current time, * target_msc and last vblank time/sequence when CRTC was turned off */ if (!radeon_crtc_is_enabled(crtc)) { CARD32 delay; target_msc -= msc_delta; delay = radeon_dri2_extrapolate_msc_delay(crtc, &target_msc, divisor, remainder); radeon_dri2_schedule_event(delay, wait_info); DRI2BlockClient(client, draw); return TRUE; } /* Get current count */ vbl.request.type = DRM_VBLANK_RELATIVE; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "get vblank counter failed: %s\n", strerror(errno)); goto out_complete; } current_msc = vbl.reply.sequence + msc_delta; current_msc &= 0xffffffff; wait = radeon_drm_queue_alloc(scrn, client, RADEON_DRM_QUEUE_ID_DEFAULT, wait_info, radeon_dri2_frame_event_handler, radeon_dri2_frame_event_abort); if (!wait) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Allocating DRM queue event entry failed.\n"); goto out_complete; } wait_info->drm_queue = wait; /* * If divisor is zero, or current_msc is smaller than target_msc, * we just need to make sure target_msc passes before waking up the * client. */ if (divisor == 0 || current_msc < target_msc) { /* If target_msc already reached or passed, set it to * current_msc to ensure we return a reasonable value back * to the caller. This keeps the client from continually * sending us MSC targets from the past by forcibly updating * their count on this call. */ if (current_msc >= target_msc) target_msc = current_msc; vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = target_msc - msc_delta; vbl.request.signal = (unsigned long)wait; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "get vblank counter failed: %s\n", strerror(errno)); goto out_complete; } DRI2BlockClient(client, draw); return TRUE; } /* * If we get here, target_msc has already passed or we don't have one, * so we queue an event that will satisfy the divisor/remainder equation. */ vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = current_msc - (current_msc % divisor) + remainder - msc_delta; /* * If calculated remainder is larger than requested remainder, * it means we've passed the last point where * seq % divisor == remainder, so we need to wait for the next time * that will happen. */ if ((current_msc % divisor) >= remainder) vbl.request.sequence += divisor; vbl.request.signal = (unsigned long)wait; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "get vblank counter failed: %s\n", strerror(errno)); goto out_complete; } DRI2BlockClient(client, draw); return TRUE; out_complete: if (wait_info) radeon_dri2_deferred_event(NULL, 0, wait_info); return TRUE; } /* * ScheduleSwap is responsible for requesting a DRM vblank event for the * appropriate frame. * * In the case of a blit (e.g. for a windowed swap) or buffer exchange, * the vblank requested can simply be the last queued swap frame + the swap * interval for the drawable. * * In the case of a page flip, we request an event for the last queued swap * frame + swap interval - 1, since we'll need to queue the flip for the frame * immediately following the received event. * * The client will be blocked if it tries to perform further GL commands * after queueing a swap, though in the Intel case after queueing a flip, the * client is free to queue more commands; they'll block in the kernel if * they access buffers busy with the flip. * * When the swap is complete, the driver should call into the server so it * can send any swap complete events that have been requested. */ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back, CARD64 *target_msc, CARD64 divisor, CARD64 remainder, DRI2SwapEventPtr func, void *data) { ScreenPtr screen = draw->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, TRUE); uint32_t msc_delta; drmVBlank vbl; int ret, flip = 0; DRI2FrameEventPtr swap_info = NULL; struct radeon_drm_queue_entry *swap; CARD64 current_msc; BoxRec box; RegionRec region; /* Truncate to match kernel interfaces; means occasional overflow * misses, but that's generally not a big deal */ *target_msc &= 0xffffffff; divisor &= 0xffffffff; remainder &= 0xffffffff; /* radeon_dri2_frame_event_handler will get called some unknown time in the * future with these buffers. Take a reference to ensure that they won't * get destroyed before then. */ radeon_dri2_ref_buffer(front); radeon_dri2_ref_buffer(back); /* either off-screen or CRTC not usable... just complete the swap */ if (crtc == NULL) goto blit_fallback; msc_delta = radeon_get_msc_delta(draw, crtc); swap_info = calloc(1, sizeof(DRI2FrameEventRec)); if (!swap_info) goto blit_fallback; swap_info->type = DRI2_SWAP; swap_info->drawable_id = draw->id; swap_info->client = client; swap_info->event_complete = func; swap_info->event_data = data; swap_info->front = front; swap_info->back = back; swap_info->crtc = crtc; swap = radeon_drm_queue_alloc(scrn, client, RADEON_DRM_QUEUE_ID_DEFAULT, swap_info, radeon_dri2_frame_event_handler, radeon_dri2_frame_event_abort); if (!swap) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Allocating DRM queue entry failed.\n"); goto blit_fallback; } swap_info->drm_queue = swap; /* * CRTC is in DPMS off state, fallback to blit, but calculate * wait time from current time, target_msc and last vblank * time/sequence when CRTC was turned off */ if (!radeon_crtc_is_enabled(crtc)) { CARD32 delay; *target_msc -= msc_delta; delay = radeon_dri2_extrapolate_msc_delay(crtc, target_msc, divisor, remainder); *target_msc += msc_delta; *target_msc &= 0xffffffff; radeon_dri2_schedule_event(delay, swap_info); return TRUE; } /* Get current count */ vbl.request.type = DRM_VBLANK_RELATIVE; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "first get vblank counter failed: %s\n", strerror(errno)); goto blit_fallback; } current_msc = vbl.reply.sequence + msc_delta; current_msc &= 0xffffffff; /* Flips need to be submitted one frame before */ if (can_flip(scrn, draw, front, back)) { swap_info->type = DRI2_FLIP; flip = 1; } /* Correct target_msc by 'flip' if swap_info->type == DRI2_FLIP. * Do it early, so handling of different timing constraints * for divisor, remainder and msc vs. target_msc works. */ if (*target_msc > 0) *target_msc -= flip; /* * If divisor is zero, or current_msc is smaller than target_msc * we just need to make sure target_msc passes before initiating * the swap. */ if (divisor == 0 || current_msc < *target_msc) { vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; /* If non-pageflipping, but blitting/exchanging, we need to use * DRM_VBLANK_NEXTONMISS to avoid unreliable timestamping later * on. */ if (flip == 0) vbl.request.type |= DRM_VBLANK_NEXTONMISS; vbl.request.type |= radeon_populate_vbl_request_type(crtc); /* If target_msc already reached or passed, set it to * current_msc to ensure we return a reasonable value back * to the caller. This makes swap_interval logic more robust. */ if (current_msc >= *target_msc) *target_msc = current_msc; vbl.request.sequence = *target_msc - msc_delta; vbl.request.signal = (unsigned long)swap; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "divisor 0 get vblank counter failed: %s\n", strerror(errno)); goto blit_fallback; } *target_msc = vbl.reply.sequence + flip + msc_delta; swap_info->frame = *target_msc; return TRUE; } /* * If we get here, target_msc has already passed or we don't have one, * and we need to queue an event that will satisfy the divisor/remainder * equation. */ vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; if (flip == 0) vbl.request.type |= DRM_VBLANK_NEXTONMISS; vbl.request.type |= radeon_populate_vbl_request_type(crtc); vbl.request.sequence = current_msc - (current_msc % divisor) + remainder - msc_delta; /* * If the calculated deadline vbl.request.sequence is smaller than * or equal to current_msc, it means we've passed the last point * when effective onset frame seq could satisfy * seq % divisor == remainder, so we need to wait for the next time * this will happen. * This comparison takes the 1 frame swap delay in pageflipping mode * into account, as well as a potential DRM_VBLANK_NEXTONMISS delay * if we are blitting/exchanging instead of flipping. */ if (vbl.request.sequence <= current_msc) vbl.request.sequence += divisor; /* Account for 1 frame extra pageflip delay if flip > 0 */ vbl.request.sequence -= flip; vbl.request.signal = (unsigned long)swap; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "final get vblank counter failed: %s\n", strerror(errno)); goto blit_fallback; } /* Adjust returned value for 1 fame pageflip offset of flip > 0 */ *target_msc = vbl.reply.sequence + flip + msc_delta; *target_msc &= 0xffffffff; swap_info->frame = *target_msc; return TRUE; blit_fallback: if (swap_info) { swap_info->type = DRI2_SWAP; radeon_dri2_schedule_event(FALLBACK_SWAP_DELAY, swap_info); } else { box.x1 = 0; box.y1 = 0; box.x2 = draw->width; box.y2 = draw->height; REGION_INIT(pScreen, ®ion, &box, 0); radeon_dri2_copy_region(draw, ®ion, front, back); DRI2SwapComplete(client, draw, 0, 0, 0, DRI2_BLIT_COMPLETE, func, data); radeon_dri2_unref_buffer(front); radeon_dri2_unref_buffer(back); } *target_msc = 0; /* offscreen, so zero out target vblank count */ return TRUE; } Bool radeon_dri2_screen_init(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); DRI2InfoRec dri2_info = { 0 }; const char *driverNames[2]; Bool scheduling_works = TRUE; if (!info->dri2.available) return FALSE; info->dri2.device_name = drmGetDeviceNameFromFd(info->dri2.drm_fd); if ( (info->ChipFamily >= CHIP_FAMILY_TAHITI) ) { dri2_info.driverName = SI_DRIVER_NAME; } else if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) { dri2_info.driverName = R600_DRIVER_NAME; } else if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) { dri2_info.driverName = R300_DRIVER_NAME; } else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) { dri2_info.driverName = R200_DRIVER_NAME; } else { dri2_info.driverName = RADEON_DRIVER_NAME; } dri2_info.fd = info->dri2.drm_fd; dri2_info.deviceName = info->dri2.device_name; dri2_info.version = DRI2INFOREC_VERSION; dri2_info.CreateBuffer = radeon_dri2_create_buffer; dri2_info.DestroyBuffer = radeon_dri2_destroy_buffer; dri2_info.CopyRegion = radeon_dri2_copy_region; if (info->dri2.pKernelDRMVersion->version_minor < 4) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for " "sync extension\n"); scheduling_works = FALSE; } if (scheduling_works && info->drmmode.count_crtcs > 2) { #ifdef DRM_CAP_VBLANK_HIGH_CRTC uint64_t cap_value; if (drmGetCap(info->dri2.drm_fd, DRM_CAP_VBLANK_HIGH_CRTC, &cap_value)) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel " "for VBLANKs on CRTC > 1\n"); scheduling_works = FALSE; } else if (!cap_value) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Your kernel does not " "handle VBLANKs on CRTC > 1\n"); scheduling_works = FALSE; } #else xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need to rebuild against a " "newer libdrm to handle VBLANKs on CRTC > 1\n"); scheduling_works = FALSE; #endif } if (scheduling_works) { dri2_info.version = 4; dri2_info.ScheduleSwap = radeon_dri2_schedule_swap; dri2_info.GetMSC = radeon_dri2_get_msc; dri2_info.ScheduleWaitMSC = radeon_dri2_schedule_wait_msc; dri2_info.numDrivers = RADEON_ARRAY_SIZE(driverNames); dri2_info.driverNames = driverNames; driverNames[0] = dri2_info.driverName; if (info->ChipFamily >= CHIP_FAMILY_R300) driverNames[1] = driverNames[0]; else driverNames[1] = NULL; /* no VDPAU support */ if (DRI2InfoCnt == 0) { #if HAS_DIXREGISTERPRIVATEKEY if (!dixRegisterPrivateKey(dri2_window_private_key, PRIVATE_WINDOW, sizeof(struct dri2_window_priv))) { #else if (!dixRequestPrivate(dri2_window_private_key, sizeof(struct dri2_window_priv))) { #endif xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to get DRI2 window private\n"); return FALSE; } AddCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0); } DRI2InfoCnt++; } #if DRI2INFOREC_VERSION >= 9 dri2_info.version = 9; dri2_info.CreateBuffer2 = radeon_dri2_create_buffer2; dri2_info.DestroyBuffer2 = radeon_dri2_destroy_buffer2; dri2_info.CopyRegion2 = radeon_dri2_copy_region2; #endif info->dri2.enabled = DRI2ScreenInit(pScreen, &dri2_info); return info->dri2.enabled; } void radeon_dri2_close_screen(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); if (--DRI2InfoCnt == 0) DeleteCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0); DRI2CloseScreen(pScreen); drmFree(info->dri2.device_name); } #endif /* DRI2 */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_dri2.h000066400000000000000000000033321256524674500226370ustar00rootroot00000000000000/* * Copyright 2008 Jerome Glisse * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef RADEON_DRI2_H #define RADEON_DRI2_H #include struct radeon_dri2 { drmVersionPtr pKernelDRMVersion; int drm_fd; Bool available; Bool enabled; char *device_name; }; #ifdef DRI2 #include "dri2.h" Bool radeon_dri2_screen_init(ScreenPtr pScreen); void radeon_dri2_close_screen(ScreenPtr pScreen); #else static inline Bool radeon_dri2_screen_init(ScreenPtr pScreen) { return FALSE; } static inline void radeon_dri2_close_screen(ScreenPtr pScreen) {} #endif #endif /* RADEON_DRI2_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_dri3.c000066400000000000000000000122511256524674500226330ustar00rootroot00000000000000/* * Copyright © 2013-2014 Intel Corporation * Copyright © 2015 Advanced Micro Devices, Inc. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of the copyright holders not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. The copyright holders make no representations * about the suitability of this software for any purpose. It is provided "as * is" without express or implied warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE * OF THIS SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon.h" #ifdef HAVE_DRI3_H #include "radeon_bo_gem.h" #include "radeon_glamor.h" #include "dri3.h" #include #include #include #include static int radeon_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); drm_magic_t magic; int fd; fd = open(info->dri2.device_name, O_RDWR | O_CLOEXEC); if (fd < 0) return BadAlloc; /* Before FD passing in the X protocol with DRI3 (and increased * security of rendering with per-process address spaces on the * GPU), the kernel had to come up with a way to have the server * decide which clients got to access the GPU, which was done by * each client getting a unique (magic) number from the kernel, * passing it to the server, and the server then telling the * kernel which clients were authenticated for using the device. * * Now that we have FD passing, the server can just set up the * authentication on its own and hand the prepared FD off to the * client. */ if (drmGetMagic(fd, &magic) < 0) { if (errno == EACCES) { /* Assume that we're on a render node, and the fd is * already as authenticated as it should be. */ *out = fd; return Success; } else { close(fd); return BadMatch; } } if (drmAuthMagic(info->dri2.drm_fd, magic) < 0) { close(fd); return BadMatch; } *out = fd; return Success; } static PixmapPtr radeon_dri3_pixmap_from_fd(ScreenPtr screen, int fd, CARD16 width, CARD16 height, CARD16 stride, CARD8 depth, CARD8 bpp) { PixmapPtr pixmap; #ifdef USE_GLAMOR /* Avoid generating a GEM flink name if possible */ if (RADEONPTR(xf86ScreenToScrn(screen))->use_glamor) { pixmap = glamor_pixmap_from_fd(screen, fd, width, height, stride, depth, bpp); if (pixmap) { struct radeon_pixmap *priv = calloc(1, sizeof(struct radeon_pixmap)); if (priv) { radeon_set_pixmap_private(pixmap, priv); return pixmap; } screen->DestroyPixmap(pixmap); } } #endif if (depth < 8) return NULL; switch (bpp) { case 8: case 16: case 32: break; default: return NULL; } pixmap = screen->CreatePixmap(screen, 0, 0, depth, RADEON_CREATE_PIXMAP_DRI2); if (!pixmap) return NULL; if (!screen->ModifyPixmapHeader(pixmap, width, height, 0, bpp, stride, NULL)) goto free_pixmap; if (screen->SetSharedPixmapBacking(pixmap, (void*)(intptr_t)fd)) return pixmap; free_pixmap: fbDestroyPixmap(pixmap); return NULL; } static int radeon_dri3_fd_from_pixmap(ScreenPtr screen, PixmapPtr pixmap, CARD16 *stride, CARD32 *size) { struct radeon_bo *bo; int fd; bo = radeon_get_pixmap_bo(pixmap); if (!bo) { #ifdef USE_GLAMOR ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); if (info->use_glamor) return glamor_fd_from_pixmap(screen, pixmap, stride, size); #endif exaMoveInPixmap(pixmap); bo = radeon_get_pixmap_bo(pixmap); if (!bo) return -1; } if (pixmap->devKind > UINT16_MAX) return -1; if (radeon_gem_prime_share_bo(bo, &fd) < 0) return -1; *stride = pixmap->devKind; *size = bo->size; return fd; } static dri3_screen_info_rec radeon_dri3_screen_info = { .version = 0, .open = radeon_dri3_open, .pixmap_from_fd = radeon_dri3_pixmap_from_fd, .fd_from_pixmap = radeon_dri3_fd_from_pixmap }; Bool radeon_dri3_screen_init(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); if (!dri3_screen_init(screen, &radeon_dri3_screen_info)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "dri3_screen_init failed\n"); return FALSE; } return TRUE; } #else /* !HAVE_DRI3_H */ Bool radeon_dri3_screen_init(ScreenPtr screen) { xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO, "Can't initialize DRI3 because dri3.h not available at " "build time\n"); return FALSE; } #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_drm_queue.c000066400000000000000000000102321256524674500237550ustar00rootroot00000000000000/* * Copyright © 2007 Red Hat, Inc. * Copyright © 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include "radeon.h" #include "radeon_drm_queue.h" #include "radeon_list.h" struct radeon_drm_queue_entry { struct xorg_list list; uint64_t id; void *data; ClientPtr client; ScrnInfoPtr scrn; radeon_drm_handler_proc handler; radeon_drm_abort_proc abort; }; static int radeon_drm_queue_refcnt; static struct xorg_list radeon_drm_queue; /* * Handle a DRM event */ void radeon_drm_queue_handler(int fd, unsigned int frame, unsigned int sec, unsigned int usec, void *user_ptr) { struct radeon_drm_queue_entry *user_data = user_ptr; struct radeon_drm_queue_entry *e, *tmp; xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { if (e == user_data) { xorg_list_del(&e->list); e->handler(e->scrn, frame, (uint64_t)sec * 1000000 + usec, e->data); free(e); break; } } } /* * Enqueue a potential drm response; when the associated response * appears, we've got data to pass to the handler from here */ struct radeon_drm_queue_entry * radeon_drm_queue_alloc(ScrnInfoPtr scrn, ClientPtr client, uint64_t id, void *data, radeon_drm_handler_proc handler, radeon_drm_abort_proc abort) { struct radeon_drm_queue_entry *e; e = calloc(1, sizeof(struct radeon_drm_queue_entry)); if (!e) return NULL; e->client = client; e->scrn = scrn; e->id = id; e->data = data; e->handler = handler; e->abort = abort; xorg_list_add(&e->list, &radeon_drm_queue); return e; } /* * Abort one queued DRM entry, removing it * from the list, calling the abort function and * freeing the memory */ static void radeon_drm_abort_one(struct radeon_drm_queue_entry *e) { xorg_list_del(&e->list); e->abort(e->scrn, e->data); free(e); } /* * Abort drm queue entries for a client */ void radeon_drm_abort_client(ClientPtr client) { struct radeon_drm_queue_entry *e, *tmp; xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { if (e->client == client) radeon_drm_abort_one(e); } } /* * Abort specific drm queue entry */ void radeon_drm_abort_entry(struct radeon_drm_queue_entry *entry) { radeon_drm_abort_one(entry); } /* * Abort specific drm queue entry by ID */ void radeon_drm_abort_id(uint64_t id) { struct radeon_drm_queue_entry *e, *tmp; xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { if (e->id == id) { radeon_drm_abort_one(e); break; } } } /* * Initialize the DRM event queue */ void radeon_drm_queue_init() { if (radeon_drm_queue_refcnt++) return; xorg_list_init(&radeon_drm_queue); } /* * Deinitialize the DRM event queue */ void radeon_drm_queue_close(ScrnInfoPtr scrn) { struct radeon_drm_queue_entry *e, *tmp; xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { if (e->scrn == scrn) radeon_drm_abort_one(e); } radeon_drm_queue_refcnt--; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_drm_queue.h000066400000000000000000000043261256524674500237710ustar00rootroot00000000000000/* * Copyright © 2007 Red Hat, Inc. * Copyright © 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifndef _RADEON_DRM_QUEUE_H_ #define _RADEON_DRM_QUEUE_H_ #define RADEON_DRM_QUEUE_CLIENT_DEFAULT serverClient #define RADEON_DRM_QUEUE_ID_DEFAULT ~0ULL struct radeon_drm_queue_entry; typedef void (*radeon_drm_handler_proc)(ScrnInfoPtr scrn, uint32_t seq, uint64_t usec, void *data); typedef void (*radeon_drm_abort_proc)(ScrnInfoPtr scrn, void *data); void radeon_drm_queue_handler(int fd, unsigned int frame, unsigned int tv_sec, unsigned int tv_usec, void *user_ptr); struct radeon_drm_queue_entry *radeon_drm_queue_alloc(ScrnInfoPtr scrn, ClientPtr client, uint64_t id, void *data, radeon_drm_handler_proc handler, radeon_drm_abort_proc abort); void radeon_drm_abort_client(ClientPtr client); void radeon_drm_abort_entry(struct radeon_drm_queue_entry *entry); void radeon_drm_abort_id(uint64_t id); void radeon_drm_queue_init(); void radeon_drm_queue_close(ScrnInfoPtr scrn); #endif /* _RADEON_DRM_QUEUE_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_exa.c000066400000000000000000000237471256524674500225630ustar00rootroot00000000000000/* * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Eric Anholt * Zack Rusin * Benjamin Herrenschmidt * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon.h" #include "radeon_reg.h" #include "r600_reg.h" #include "radeon_bo_helper.h" #include "radeon_probe.h" #include "radeon_version.h" #include "radeon_exa_shared.h" #include "xf86.h" /***********************************************************************/ #define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86ScreenToScrn(pScr); \ RADEONInfoPtr info = RADEONPTR(pScrn) static struct { int rop; int pattern; } RADEON_ROP[] = { { RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */ { RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */ { RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */ { RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */ { RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */ { RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */ { RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */ { RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */ { RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */ { RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */ { RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */ { RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */ { RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */ { RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */ { RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */ { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ }; static __inline__ uint32_t F_TO_DW(float val) { union { float f; uint32_t l; } tmp; tmp.f = val; return tmp.l; } /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we * require src and dest datatypes to be equal. */ Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) { switch (bpp) { case 8: *type = ATI_DATATYPE_CI8; return TRUE; case 16: *type = ATI_DATATYPE_RGB565; return TRUE; case 24: *type = ATI_DATATYPE_CI8; return TRUE; case 32: *type = ATI_DATATYPE_ARGB8888; return TRUE; default: RADEON_FALLBACK(("Unsupported bpp: %d\n", bpp)); return FALSE; } } static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) { return FALSE; } static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, unsigned int offset, unsigned int pitch) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); if (pitch > 16320 || pitch % info->accel_state->exa->pixmapPitchAlign != 0) RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch)); if (offset % info->accel_state->exa->pixmapOffsetAlign != 0) RADEON_FALLBACK(("Bad offset 0x%08x\n", offset)); pitch = pitch >> 6; *pitch_offset = (pitch << 22) | (offset >> 10); /* If it's the front buffer, we've got to note that it's tiled? */ if (RADEONPixmapIsColortiled(pPix)) *pitch_offset |= RADEON_DST_TILE_MACRO; return TRUE; } Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) { uint32_t pitch; int bpp; bpp = pPix->drawable.bitsPerPixel; if (bpp == 24) bpp = 8; pitch = exaGetPixmapPitch(pPix); return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, 0, pitch); } /** * Returns whether the provided transform is affine. * * transform may be null. */ Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t) { if (t == NULL) return TRUE; /* the shaders don't handle scaling either */ return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1); } Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index) { ScreenPtr pScreen = pPix->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_exa_pixmap_priv *driver_priv; uint32_t possible_domains = ~0U; uint32_t current_domain = 0; Bool can_fail = !(pPix->drawable.bitsPerPixel < 8) && pPix != pScreen->GetScreenPixmap(pScreen); Bool flush = FALSE; int ret; #if X_BYTE_ORDER == X_BIG_ENDIAN /* May need to handle byte swapping in DownloadFrom/UploadToScreen */ if (pPix->drawable.bitsPerPixel > 8) return FALSE; #endif driver_priv = exaGetPixmapDriverPrivate(pPix); if (!driver_priv) return FALSE; /* untile in DFS/UTS */ if (driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)) return FALSE; /* if we have more refs than just the BO then flush */ if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { flush = TRUE; if (can_fail) { possible_domains = radeon_bo_get_src_domain(driver_priv->bo); if (possible_domains == RADEON_GEM_DOMAIN_VRAM) return FALSE; /* use DownloadFromScreen */ } } /* if the BO might end up in VRAM, prefer DownloadFromScreen */ if (can_fail && (possible_domains & RADEON_GEM_DOMAIN_VRAM)) { radeon_bo_is_busy(driver_priv->bo, ¤t_domain); if (current_domain & possible_domains) { if (current_domain == RADEON_GEM_DOMAIN_VRAM) return FALSE; } else if (possible_domains & RADEON_GEM_DOMAIN_VRAM) return FALSE; } if (flush) radeon_cs_flush_indirect(pScrn); /* flush IB */ ret = radeon_bo_map(driver_priv->bo, 1); if (ret) { FatalError("failed to map pixmap %d\n", ret); return FALSE; } driver_priv->bo_mapped = TRUE; pPix->devPrivate.ptr = driver_priv->bo->ptr; return TRUE; } void RADEONFinishAccess_CS(PixmapPtr pPix, int index) { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); if (!driver_priv || !driver_priv->bo_mapped) return; radeon_bo_unmap(driver_priv->bo); driver_priv->bo_mapped = FALSE; pPix->devPrivate.ptr = NULL; } void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_exa_pixmap_priv *new_priv; if (size != 0 && !info->exa_force_create && info->exa_pixmaps == FALSE) return NULL; new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv)); if (!new_priv) return NULL; if (size == 0) return new_priv; new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, align, RADEON_GEM_DOMAIN_VRAM, 0); if (!new_priv->bo) { free(new_priv); ErrorF("Failed to alloc memory\n"); return NULL; } return new_priv; } void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, int depth, int usage_hint, int bitsPerPixel, int *new_pitch) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_exa_pixmap_priv *new_priv; if (width != 0 && height != 0 && !info->exa_force_create && info->exa_pixmaps == FALSE) return NULL; new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv)); if (!new_priv) { return NULL; } if (width == 0 || height == 0) { return new_priv; } new_priv->bo = radeon_alloc_pixmap_bo(pScrn, width, height, depth, usage_hint, bitsPerPixel, new_pitch, &new_priv->surface, &new_priv->tiling_flags); if (!new_priv->bo) { free(new_priv); ErrorF("Failed to alloc memory\n"); return NULL; } return new_priv; } void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv) { struct radeon_exa_pixmap_priv *driver_priv = driverPriv; if (!driverPriv) return; if (driver_priv->bo) radeon_bo_unref(driver_priv->bo); free(driverPriv); } #ifdef RADEON_PIXMAP_SHARING Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **fd_handle) { struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix); if (!radeon_share_pixmap_backing(driver_priv->bo, fd_handle)) return FALSE; driver_priv->shared = TRUE; return TRUE; } Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *fd_handle) { struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix); if (!radeon_set_shared_pixmap_backing(ppix, fd_handle, &driver_priv->surface)) return FALSE; driver_priv->shared = TRUE; return TRUE; } #endif uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix) { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return driver_priv->tiling_flags; } Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix) { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); if (!driver_priv) return FALSE; if (driver_priv->bo) return TRUE; return FALSE; } #define ENTER_DRAW(x) TRACE #define LEAVE_DRAW(x) TRACE /***********************************************************************/ #ifdef RENDER #include "radeon_exa_render.c" #endif #include "radeon_exa_funcs.c" xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_exa_funcs.c000066400000000000000000000514541256524674500237550ustar00rootroot00000000000000/* * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * Copyright 2006 Tungsten Graphics, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Eric Anholt * Zack Rusin * Benjamin Herrenschmidt * Michel Dänzer * */ #include #include #include "radeon.h" #include "exa.h" static int RADEONMarkSync(ScreenPtr pScreen) { RINFO_FROM_SCREEN(pScreen); TRACE; return ++info->accel_state->exaSyncMarker; } static void RADEONSync(ScreenPtr pScreen, int marker) { } static void Emit2DState(ScrnInfoPtr pScrn, int op) { RADEONInfoPtr info = RADEONPTR(pScrn); int has_src; /* don't emit if no operation in progress */ if (info->state_2d.op == 0 && op == 0) return; has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo; if (has_src) { BEGIN_ACCEL_RELOC(10, 2); } else { BEGIN_ACCEL_RELOC(9, 1); } OUT_RING_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right); OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl); OUT_RING_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr); OUT_RING_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr); OUT_RING_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr); OUT_RING_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr); OUT_RING_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask); OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl); OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset); OUT_RING_RELOC(info->state_2d.dst_bo, 0, info->state_2d.dst_domain); if (has_src) { OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset); OUT_RING_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); } ADVANCE_RING(); if (op) info->state_2d.op = op; info->reemit_current2d = Emit2DState; } static void RADEONFlush2D(PixmapPtr pPix) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); TRACE; BEGIN_RING(2*2); OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ADVANCE_RING(); } static void RADEONDone2D(PixmapPtr pPix) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); info->state_2d.op = 0; RADEONFlush2D(pPix); } static Bool RADEONPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t datatype, dst_pitch_offset; struct radeon_exa_pixmap_priv *driver_priv; int ret; TRACE; if (pPix->drawable.bitsPerPixel == 24) RADEON_FALLBACK(("24bpp unsupported\n")); if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); if (!RADEONGetPixmapOffsetPitch(pPix, &dst_pitch_offset)) RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n")); RADEON_SWITCH_TO_2D(); radeon_cs_space_reset_bos(info->cs); driver_priv = exaGetPixmapDriverPrivate(pPix); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n")); driver_priv = exaGetPixmapDriverPrivate(pPix); if (driver_priv) { info->state_2d.dst_bo = driver_priv->bo; info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM; } info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); info->state_2d.dp_brush_bkgd_clr = 0x00000000; info->state_2d.dp_src_frgd_clr = 0xffffffff; info->state_2d.dp_src_bkgd_clr = 0x00000000; info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_BRUSH_SOLID_COLOR | (datatype << 8) | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP[alu].pattern | RADEON_GMC_CLR_CMP_CNTL_DIS); info->state_2d.dp_brush_frgd_clr = fg; info->state_2d.dp_cntl = (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM); info->state_2d.dp_write_mask = pm; info->state_2d.dst_pitch_offset = dst_pitch_offset; info->state_2d.src_pitch_offset = 0; info->state_2d.src_bo = NULL; info->accel_state->dst_pix = pPix; Emit2DState(pScrn, RADEON_2D_EXA_SOLID); return TRUE; } static void RADEONSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); TRACE; if (CS_FULL(info->cs)) { RADEONFlush2D(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); } if (info->accel_state->vsync) RADEONWaitForVLine(pScrn, pPix, radeon_pick_best_crtc(pScrn, FALSE, x1, x2, y1, y2), y1, y2); BEGIN_RING(2*2); OUT_RING_REG(RADEON_DST_Y_X, (y1 << 16) | x1); OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1)); ADVANCE_RING(); } static void RADEONDoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, uint32_t datatype, int rop, Pixel planemask) { RADEONInfoPtr info = RADEONPTR(pScrn); /* setup 2D state */ info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | RADEON_GMC_BRUSH_NONE | (datatype << 8) | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop | RADEON_DP_SRC_SOURCE_MEMORY | RADEON_GMC_CLR_CMP_CNTL_DIS); info->state_2d.dp_cntl = ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) | (info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0)); info->state_2d.dp_brush_frgd_clr = 0xffffffff; info->state_2d.dp_brush_bkgd_clr = 0x00000000; info->state_2d.dp_src_frgd_clr = 0xffffffff; info->state_2d.dp_src_bkgd_clr = 0x00000000; info->state_2d.dp_write_mask = planemask; info->state_2d.dst_pitch_offset = dst_pitch_offset; info->state_2d.src_pitch_offset = src_pitch_offset; info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); Emit2DState(pScrn, RADEON_2D_EXA_COPY); } static Bool RADEONPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int xdir, int ydir, int rop, Pixel planemask) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; struct radeon_exa_pixmap_priv *driver_priv; int ret; TRACE; if (pDst->drawable.bitsPerPixel == 24) RADEON_FALLBACK(("24bpp unsupported")); if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); if (!RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset)) RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch source failed\n")); if (!RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset)) RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch dest failed\n")); RADEON_SWITCH_TO_2D(); radeon_cs_space_reset_bos(info->cs); driver_priv = exaGetPixmapDriverPrivate(pSrc); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); info->state_2d.src_bo = driver_priv->bo; driver_priv = exaGetPixmapDriverPrivate(pDst); info->state_2d.dst_bo = driver_priv->bo; info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM; radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, info->state_2d.dst_domain); ret = radeon_cs_space_check(info->cs); if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n")); info->accel_state->xdir = xdir; info->accel_state->ydir = ydir; info->accel_state->dst_pix = pDst; RADEONDoPrepareCopy(pScrn, src_pitch_offset, dst_pitch_offset, datatype, rop, planemask); return TRUE; } static void RADEONCopy(PixmapPtr pDst, int srcX, int srcY, int dstX, int dstY, int w, int h) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); TRACE; if (CS_FULL(info->cs)) { RADEONFlush2D(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); } if (info->accel_state->xdir < 0) { srcX += w - 1; dstX += w - 1; } if (info->accel_state->ydir < 0) { srcY += h - 1; dstY += h - 1; } if (info->accel_state->vsync) RADEONWaitForVLine(pScrn, pDst, radeon_pick_best_crtc(pScrn, FALSE, dstX, dstX + w, dstY, dstY + h), dstY, dstY + h); BEGIN_RING(2*3); OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX); OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); ADVANCE_RING(); } /* Emit blit with arbitrary source and destination offsets and pitches */ static void RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo, struct radeon_bo *dst_bo, uint32_t datatype, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, int w, int h, uint32_t src_domain, uint32_t dst_domain) { RADEONInfoPtr info = RADEONPTR(pScrn); if (src_bo && dst_bo) { BEGIN_ACCEL_RELOC(6, 2); } else if (src_bo && dst_bo == NULL) { BEGIN_ACCEL_RELOC(6, 1); } else { BEGIN_RING(2*6); } OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | RADEON_GMC_BRUSH_NONE | (datatype << 8) | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_S | RADEON_DP_SRC_SOURCE_MEMORY | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset); if (src_bo) { OUT_RING_RELOC(src_bo, src_domain, 0); } OUT_RING_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset); if (dst_bo) { OUT_RING_RELOC(dst_bo, 0, dst_domain); } OUT_RING_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX); OUT_RING_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); ADVANCE_RING(); BEGIN_RING(2*2); OUT_RING_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ADVANCE_RING(); } static Bool RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) { ScreenPtr pScreen = pDst->drawable.pScreen; RINFO_FROM_SCREEN(pScreen); struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_dst; unsigned char *dst; unsigned size; uint32_t datatype = 0; uint32_t dst_domain; uint32_t dst_pitch_offset; unsigned bpp = pDst->drawable.bitsPerPixel; uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64); uint32_t copy_pitch; uint32_t swap = RADEON_HOST_DATA_SWAP_NONE; int ret; Bool flush = TRUE; Bool r; int i; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pDst); if (!driver_priv || !driver_priv->bo) return FALSE; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (bpp) { case 32: swap = RADEON_HOST_DATA_SWAP_32BIT; break; case 16: swap = RADEON_HOST_DATA_SWAP_16BIT; break; } #endif /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ copy_dst = driver_priv->bo; copy_pitch = pDst->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { flush = FALSE; if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) && !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) goto copy; } /* use cpu copy for fast fb access */ if (info->is_fast_fb) goto copy; } size = scratch_pitch * h; scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } radeon_cs_space_reset_bos(info->cs); radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM); radeon_cs_space_add_persistent_bo(info->cs, scratch, RADEON_GEM_DOMAIN_GTT, 0); ret = radeon_cs_space_check(info->cs); if (ret) { goto copy; } copy_dst = scratch; copy_pitch = scratch_pitch; flush = FALSE; copy: if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_dst, 0); if (ret) { r = FALSE; goto out; } r = TRUE; size = w * bpp / 8; dst = copy_dst->ptr; if (copy_dst == driver_priv->bo) dst += y * copy_pitch + x * bpp / 8; for (i = 0; i < h; i++) { RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap); src += src_pitch; } radeon_bo_unmap(copy_dst); if (copy_dst == scratch) { RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype); RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset); RADEON_SWITCH_TO_2D(); RADEONBlitChunk(pScrn, scratch, driver_priv->bo, datatype, scratch_pitch << 16, dst_pitch_offset, 0, 0, x, y, w, h, RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_VRAM); } out: if (scratch) radeon_bo_unref(scratch); return r; } static Bool RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, int h, char *dst, int dst_pitch) { RINFO_FROM_SCREEN(pSrc->drawable.pScreen); struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *scratch = NULL; struct radeon_bo *copy_src; unsigned size; uint32_t datatype = 0; uint32_t src_domain = 0; uint32_t src_pitch_offset; unsigned bpp = pSrc->drawable.bitsPerPixel; uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64); uint32_t copy_pitch; uint32_t swap = RADEON_HOST_DATA_SWAP_NONE; int ret; Bool flush = FALSE; Bool r; if (bpp < 8) return FALSE; driver_priv = exaGetPixmapDriverPrivate(pSrc); if (!driver_priv || !driver_priv->bo) return FALSE; #if X_BYTE_ORDER == X_BIG_ENDIAN switch (bpp) { case 32: swap = RADEON_HOST_DATA_SWAP_32BIT; break; case 16: swap = RADEON_HOST_DATA_SWAP_16BIT; break; } #endif /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ copy_src = driver_priv->bo; copy_pitch = pSrc->devKind; if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) { src_domain = radeon_bo_get_src_domain(driver_priv->bo); if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) src_domain = 0; else /* A write may be scheduled */ flush = TRUE; } if (!src_domain) radeon_bo_is_busy(driver_priv->bo, &src_domain); if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) goto copy; } size = scratch_pitch * h; scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0); if (scratch == NULL) { goto copy; } radeon_cs_space_reset_bos(info->cs); radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, RADEON_GEM_DOMAIN_GTT); ret = radeon_cs_space_check(info->cs); if (ret) { goto copy; } RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype); RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset); RADEON_SWITCH_TO_2D(); RADEONBlitChunk(pScrn, driver_priv->bo, scratch, datatype, src_pitch_offset, scratch_pitch << 16, x, y, 0, 0, w, h, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_GTT); copy_src = scratch; copy_pitch = scratch_pitch; flush = TRUE; copy: if (flush) FLUSH_RING(); ret = radeon_bo_map(copy_src, 0); if (ret) { ErrorF("failed to map pixmap: %d\n", ret); r = FALSE; goto out; } r = TRUE; w *= bpp / 8; if (copy_src == driver_priv->bo) size = y * copy_pitch + x * bpp / 8; else size = 0; while (h--) { RADEONCopySwap((uint8_t*)dst, copy_src->ptr + size, w, swap); size += copy_pitch; dst += dst_pitch; } radeon_bo_unmap(copy_src); out: if (scratch) radeon_bo_unref(scratch); return r; } Bool RADEONDrawInit(ScreenPtr pScreen) { RINFO_FROM_SCREEN(pScreen); if (info->accel_state->exa == NULL) { xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); return FALSE; } info->accel_state->exa->exa_major = EXA_VERSION_MAJOR; info->accel_state->exa->exa_minor = EXA_VERSION_MINOR; info->accel_state->exa->PrepareSolid = RADEONPrepareSolid; info->accel_state->exa->Solid = RADEONSolid; info->accel_state->exa->DoneSolid = RADEONDone2D; info->accel_state->exa->PrepareCopy = RADEONPrepareCopy; info->accel_state->exa->Copy = RADEONCopy; info->accel_state->exa->DoneCopy = RADEONDone2D; info->accel_state->exa->MarkSync = RADEONMarkSync; info->accel_state->exa->WaitMarker = RADEONSync; info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS; info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS; info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX | EXA_SUPPORTS_OFFSCREEN_OVERLAPS | EXA_HANDLES_PIXMAPS | EXA_MIXED_PIXMAPS; info->accel_state->exa->pixmapOffsetAlign = RADEON_GPU_PAGE_SIZE; info->accel_state->exa->pixmapPitchAlign = 64; #ifdef RENDER if (info->RenderAccel) { if (IS_R300_3D || IS_R500_3D) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R300/R400/R500 type cards.\n"); info->accel_state->exa->CheckComposite = R300CheckComposite; info->accel_state->exa->PrepareComposite = R300PrepareComposite; info->accel_state->exa->Composite = RadeonComposite; info->accel_state->exa->DoneComposite = RadeonDoneComposite; } else if (IS_R200_3D) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R200 type cards.\n"); info->accel_state->exa->CheckComposite = R200CheckComposite; info->accel_state->exa->PrepareComposite = R200PrepareComposite; info->accel_state->exa->Composite = RadeonComposite; info->accel_state->exa->DoneComposite = RadeonDoneComposite; } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R100 type cards.\n"); info->accel_state->exa->CheckComposite = R100CheckComposite; info->accel_state->exa->PrepareComposite = R100PrepareComposite; info->accel_state->exa->Composite = RadeonComposite; info->accel_state->exa->DoneComposite = RadeonDoneComposite; } } #endif info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 6) info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking; info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking; #endif info->accel_state->exa->maxPitchBytes = 16320; info->accel_state->exa->maxX = 8191; info->accel_state->exa->maxY = 8191; if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n"); info->accel_state->vsync = TRUE; } else info->accel_state->vsync = FALSE; RADEONEngineInit(pScrn); if (!exaDriverInit(pScreen, info->accel_state->exa)) { free(info->accel_state->exa); return FALSE; } exaMarkSync(pScreen); return TRUE; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_exa_render.c000066400000000000000000002352201256524674500241110ustar00rootroot00000000000000/* * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Eric Anholt * Zack Rusin * Benjamin Herrenschmidt * Alex Deucher * */ struct blendinfo { Bool dst_alpha; Bool src_alpha; uint32_t blend_cntl; }; static struct blendinfo RadeonBlendOp[] = { /* Clear */ {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, /* Src */ {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, /* Dst */ {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, /* Over */ {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, /* OverReverse */ {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, /* In */ {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, /* InReverse */ {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, /* Out */ {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, /* OutReverse */ {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, /* Atop */ {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, /* AtopReverse */ {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, /* Xor */ {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, /* Add */ {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, }; struct formatinfo { int fmt; uint32_t card_fmt; }; /* Note on texture formats: * TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I) */ static struct formatinfo R100TexFormats[] = { {PICT_a8r8g8b8, RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP}, {PICT_x8r8g8b8, RADEON_TXFORMAT_ARGB8888}, {PICT_r5g6b5, RADEON_TXFORMAT_RGB565}, {PICT_a1r5g5b5, RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP}, {PICT_x1r5g5b5, RADEON_TXFORMAT_ARGB1555}, {PICT_a8, RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP}, }; static struct formatinfo R200TexFormats[] = { {PICT_a8r8g8b8, R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP}, {PICT_x8r8g8b8, R200_TXFORMAT_ARGB8888}, {PICT_a8b8g8r8, R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP}, {PICT_x8b8g8r8, R200_TXFORMAT_ABGR8888}, {PICT_r5g6b5, R200_TXFORMAT_RGB565}, {PICT_a1r5g5b5, R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP}, {PICT_x1r5g5b5, R200_TXFORMAT_ARGB1555}, {PICT_a8, R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP}, }; static struct formatinfo R300TexFormats[] = { {PICT_a8r8g8b8, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)}, {PICT_x8r8g8b8, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)}, {PICT_a8b8g8r8, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)}, {PICT_x8b8g8r8, R300_EASY_TX_FORMAT(Z, Y, X, ONE, W8Z8Y8X8)}, {PICT_b8g8r8a8, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)}, {PICT_b8g8r8x8, R300_EASY_TX_FORMAT(W, Z, Y, ONE, W8Z8Y8X8)}, {PICT_r5g6b5, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)}, {PICT_a1r5g5b5, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)}, {PICT_x1r5g5b5, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W1Z5Y5X5)}, {PICT_a8, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)}, }; /* Common Radeon setup code */ static Bool RADEONGetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: *dst_format = RADEON_COLOR_FORMAT_ARGB8888; break; case PICT_r5g6b5: *dst_format = RADEON_COLOR_FORMAT_RGB565; break; case PICT_a1r5g5b5: case PICT_x1r5g5b5: *dst_format = RADEON_COLOR_FORMAT_ARGB1555; break; case PICT_a8: *dst_format = RADEON_COLOR_FORMAT_RGB8; break; default: RADEON_FALLBACK(("Unsupported dest format 0x%x\n", (int)pDstPicture->format)); } return TRUE; } static Bool R300GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) { switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: case PICT_a8b8g8r8: case PICT_x8b8g8r8: case PICT_b8g8r8a8: case PICT_b8g8r8x8: *dst_format = R300_COLORFORMAT_ARGB8888; break; case PICT_r5g6b5: *dst_format = R300_COLORFORMAT_RGB565; break; case PICT_a1r5g5b5: case PICT_x1r5g5b5: *dst_format = R300_COLORFORMAT_ARGB1555; break; case PICT_a8: *dst_format = R300_COLORFORMAT_I8; break; default: RADEON_FALLBACK(("Unsupported dest format 0x%x\n", (int)pDstPicture->format)); } return TRUE; } static uint32_t RADEONGetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) { uint32_t sblend, dblend; sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; /* If there's no dst alpha channel, adjust the blend op so that we'll treat * it as always 1. */ if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) sblend = RADEON_SRC_BLEND_GL_ONE; else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) sblend = RADEON_SRC_BLEND_GL_ZERO; } /* If the source alpha is being used, then we should only be in a case where * the source blend factor is 0, and the source blend value is the mask * channels multiplied by the source picture's alpha. */ if (pMask && pMask->componentAlpha && RadeonBlendOp[op].src_alpha) { if (dblend == RADEON_DST_BLEND_GL_SRC_ALPHA) { dblend = RADEON_DST_BLEND_GL_SRC_COLOR; } else if (dblend == RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA) { dblend = RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR; } } return sblend | dblend; } union intfloat { float f; uint32_t i; }; /* Check if we need a software-fallback because of a repeating * non-power-of-two texture. * * canTile: whether we can emulate a repeat by drawing in tiles: * possible for the source, but not for the mask. (Actually * we could do tiling for the mask too, but dealing with the * combination of a tiled mask and a tiled source would be * a lot of complexity, so we handle only the most common * case of a repeating mask.) */ static Bool RADEONCheckTexturePOT(PicturePtr pPict, Bool canTile) { int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; if ((repeatType == RepeatNormal || repeatType == RepeatReflect) && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0) && !(repeatType == RepeatNormal && !pPict->transform && canTile)) RADEON_FALLBACK(("NPOT repeating %s unsupported (%dx%d), transform=%d\n", canTile ? "source" : "mask", w, h, pPict->transform != 0)); return TRUE; } /* Determine if the pitch of the pixmap meets the criteria for being * used as a repeating texture: no padding or only a single line texture. */ static Bool RADEONPitchMatches(PixmapPtr pPix) { int w = pPix->drawable.width; int h = pPix->drawable.height; uint32_t txpitch = exaGetPixmapPitch(pPix); if (h > 1 && (RADEON_ALIGN(w * pPix->drawable.bitsPerPixel / 8, 32)) != txpitch) return FALSE; return TRUE; } /* We can't turn on repeats normally for a non-power-of-two dimension, * but if the source isn't transformed, we can get the same effect * by drawing the image in multiple tiles. (A common case that it's * important to get right is drawing a strip of a NPOTxPOT texture * repeating in the POT direction. With tiling, this ends up as a * a single tile on R300 and newer, which is perfect.) * * canTile1d: On R300 and newer, we can repeat a texture that is NPOT in * one direction and POT in the other in the POT direction; on * older chips we can only repeat at all if the texture is POT in * both directions. * * needMatchingPitch: On R100/R200, we can only repeat horizontally if * there is no padding in the texture. Textures with small POT widths * (1,2,4,8) thus can't be tiled. */ static Bool RADEONSetupSourceTile(PicturePtr pPict, PixmapPtr pPix, Bool canTile1d, Bool needMatchingPitch) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = FALSE; info->accel_state->src_tile_width = info->accel_state->src_tile_height = 65536; /* "infinite" */ if (repeatType == RepeatNormal || repeatType == RepeatReflect) { Bool badPitch = needMatchingPitch && !RADEONPitchMatches(pPix); int w = pPict->pDrawable ? pPict->pDrawable->width : 1; int h = pPict->pDrawable ? pPict->pDrawable->height : 1; if (pPict->transform) { if (badPitch) RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", w, (unsigned)exaGetPixmapPitch(pPix))); } else { info->accel_state->need_src_tile_x = (w & (w - 1)) != 0 || badPitch; info->accel_state->need_src_tile_y = (h & (h - 1)) != 0; if ((info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y) && repeatType != RepeatNormal) RADEON_FALLBACK(("Can only tile RepeatNormal at this time\n")); if (!canTile1d) info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y; } if (info->accel_state->need_src_tile_x) info->accel_state->src_tile_width = w; if (info->accel_state->need_src_tile_y) info->accel_state->src_tile_height = h; } return TRUE; } /* R100-specific code */ static Bool R100CheckCompositeTexture(PicturePtr pPict, PicturePtr pDstPict, int op, int unit) { unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; int i; for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++) { if (R100TexFormats[i].fmt == pPict->format) break; } if (i == sizeof(R100TexFormats) / sizeof(R100TexFormats[0])) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); if (pPict->pDrawable && !RADEONCheckTexturePOT(pPict, unit == 0)) return FALSE; if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) { RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); } /* for REPEAT_NONE, Render semantics are that sampling outside the source * picture results in alpha=0 pixels. We can implement this with a border color * *if* our source texture has an alpha channel, otherwise we need to fall * back. If we're not transformed then we hope that upper layers have clipped * rendering to the bounds of the source drawable, in which case it doesn't * matter. I have not, however, verified that the X server always does such * clipping. */ if (pPict->transform != 0 && repeatType == RepeatNone && PICT_FORMAT_A(pPict->format) == 0) { if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); } if (!radeon_transform_is_affine_or_scaled(pPict->transform)) RADEON_FALLBACK(("non-affine transforms not supported\n")); return TRUE; } static Bool R100TextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t txfilter, txformat, txoffset, txpitch; unsigned int repeatType; Bool repeat; int i, w, h; struct radeon_exa_pixmap_priv *driver_priv; if (pPict->pDrawable) { w = pPict->pDrawable->width; h = pPict->pDrawable->height; repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; } else { w = h = 1; repeatType = RepeatNormal; } repeat = (repeatType == RepeatNormal || repeatType == RepeatReflect) && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); txpitch = exaGetPixmapPitch(pPix); txoffset = 0; if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++) { if (R100TexFormats[i].fmt == pPict->format) break; } txformat = R100TexFormats[i].card_fmt; if (RADEONPixmapIsColortiled(pPix)) txoffset |= RADEON_TXO_MACRO_TILE; if (repeat) { if (!RADEONPitchMatches(pPix)) RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", w, (unsigned)txpitch)); txformat |= RADEONLog2(w) << RADEON_TXFORMAT_WIDTH_SHIFT; txformat |= RADEONLog2(h) << RADEON_TXFORMAT_HEIGHT_SHIFT; } else txformat |= RADEON_TXFORMAT_NON_POWER2; txformat |= unit << 24; /* RADEON_TXFORMAT_ST_ROUTE_STQX */ info->accel_state->texW[unit] = w; info->accel_state->texH[unit] = h; switch (pPict->filter) { case PictFilterNearest: txfilter = (RADEON_MAG_FILTER_NEAREST | RADEON_MIN_FILTER_NEAREST); break; case PictFilterBilinear: txfilter = (RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR); break; default: RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } switch (repeatType) { case RepeatNormal: if (txformat & RADEON_TXFORMAT_NON_POWER2) txfilter |= RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST; else txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP; break; case RepeatPad: txfilter |= RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST; break; case RepeatReflect: txfilter |= RADEON_CLAMP_S_MIRROR | RADEON_CLAMP_T_MIRROR; break; case RepeatNone: /* don't set an illegal clamp mode for rects */ if (txformat & RADEON_TXFORMAT_NON_POWER2) txfilter |= RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST; break; } BEGIN_ACCEL_RELOC(5, 1); if (unit == 0) { OUT_RING_REG(RADEON_PP_TXFILTER_0, txfilter); OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat); OUT_RING_REG(RADEON_PP_TEX_SIZE_0, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(RADEON_PP_TEX_PITCH_0, txpitch - 32); EMIT_READ_OFFSET(RADEON_PP_TXOFFSET_0, txoffset, pPix); /* emit a texture relocation */ } else { OUT_RING_REG(RADEON_PP_TXFILTER_1, txfilter); OUT_RING_REG(RADEON_PP_TXFORMAT_1, txformat); OUT_RING_REG(RADEON_PP_TEX_SIZE_1, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(RADEON_PP_TEX_PITCH_1, txpitch - 32); EMIT_READ_OFFSET(RADEON_PP_TXOFFSET_1, txoffset, pPix); /* emit a texture relocation */ } ADVANCE_RING(); if (pPict->transform != 0) { info->accel_state->is_transform[unit] = TRUE; info->accel_state->transform[unit] = pPict->transform; } else { info->accel_state->is_transform[unit] = FALSE; } return TRUE; } static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { PixmapPtr pSrcPixmap, pDstPixmap; uint32_t tmp1; /* Check for unsupported compositing operations. */ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); if (pDstPixmap->drawable.width > 2048 || pDstPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); } if (pSrcPicture->pDrawable) { /* r100 limit should be 2048, there are issues with 2048 * see 197a62704742a4a19736c2637ac92d1dc5ab34ed */ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); if (pSrcPixmap->drawable.width > 2048 || pSrcPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); } } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture) { PixmapPtr pMaskPixmap; if (pMaskPicture->pDrawable) { pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); if (pMaskPixmap->drawable.width > 2048 || pMaskPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); } } else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture->componentAlpha) { /* Check if it's component alpha that relies on a source alpha and * on the source value. We can only get one of those into the * single source value that we get to blend with. */ if (RadeonBlendOp[op].src_alpha && (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != RADEON_SRC_BLEND_GL_ZERO) { RADEON_FALLBACK(("Component alpha not supported with source " "alpha and source value blending.\n")); } } if (!R100CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1)) return FALSE; } if (!R100CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0)) return FALSE; if (!RADEONGetDestFormat(pDstPicture, &tmp1)) return FALSE; return TRUE; } static Bool RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); int ret; info->accel_state->composite_op = op; info->accel_state->dst_pic = pDstPicture; info->accel_state->msk_pic = pMaskPicture; info->accel_state->src_pic = pSrcPicture; info->accel_state->dst_pix = pDst; info->accel_state->msk_pix = pMask; info->accel_state->src_pix = pSrc; radeon_cs_space_reset_bos(info->cs); radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); if (pMask) radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); return TRUE; } static Bool R100PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; RINFO_FROM_SCREEN(pScreen); uint32_t dst_format, dst_pitch, colorpitch; uint32_t pp_cntl, blendcntl, cblend, ablend; int pixel_shift; struct radeon_exa_pixmap_priv *driver_priv; TRACE; if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) RADEON_FALLBACK(("Can't dst alpha blend A8\n")); pixel_shift = pDst->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; if (RADEONPixmapIsColortiled(pDst)) colorpitch |= RADEON_COLOR_TILE_ENABLE; if (!pSrc) { pSrc = RADEONSolidPixmap(pScreen, cpu_to_le32(pSrcPicture->pSourcePict->solidFill.color)); if (!pSrc) RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) return FALSE; if (pMaskPicture && !pMask) { pMask = RADEONSolidPixmap(pScreen, cpu_to_le32(pMaskPicture->pSourcePict->solidFill.color)); if (!pMask) { if (!pSrcPicture->pDrawable) pScreen->DestroyPixmap(pSrc); RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } } RADEONPrepareCompositeCS(op, pSrcPicture, pMaskPicture, pDstPicture, pSrc, pMask, pDst); /* switch to 3D after doing buffer space checks as the latter may flush */ RADEON_SWITCH_TO_3D(); if (!R100TextureSetup(pSrcPicture, pSrc, 0)) return FALSE; pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; if (pMask != NULL) { if (!R100TextureSetup(pMaskPicture, pMask, 1)) return FALSE; pp_cntl |= RADEON_TEX_1_ENABLE; } else { info->accel_state->is_transform[1] = FALSE; } BEGIN_ACCEL_RELOC(10, 2); OUT_RING_REG(RADEON_PP_CNTL, pp_cntl); OUT_RING_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE); EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pDst); EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pDst); /* IN operator: Multiply src by mask components or mask alpha. * BLEND_CTL_ADD is A * B + C. * If a source is a8, we have to explicitly zero its color values. * If the destination is a8, we have to route the alpha to red, I think. * If we're doing component alpha where the source for blending is going to * be the source alpha (and there's no source value used), we have to zero * the source's color values. */ cblend = RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX | RADEON_COLOR_ARG_C_ZERO; ablend = RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX | RADEON_ALPHA_ARG_C_ZERO; if (pDstPicture->format == PICT_a8 || (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha)) { cblend |= RADEON_COLOR_ARG_A_T0_ALPHA; } else if (pSrcPicture->format == PICT_a8) cblend |= RADEON_COLOR_ARG_A_ZERO; else cblend |= RADEON_COLOR_ARG_A_T0_COLOR; ablend |= RADEON_ALPHA_ARG_A_T0_ALPHA; if (pMask) { if (pMaskPicture->componentAlpha && pDstPicture->format != PICT_a8) cblend |= RADEON_COLOR_ARG_B_T1_COLOR; else cblend |= RADEON_COLOR_ARG_B_T1_ALPHA; ablend |= RADEON_ALPHA_ARG_B_T1_ALPHA; } else { cblend |= RADEON_COLOR_ARG_B_ZERO | RADEON_COMP_ARG_B; ablend |= RADEON_ALPHA_ARG_B_ZERO | RADEON_COMP_ARG_B; } OUT_RING_REG(RADEON_PP_TXCBLEND_0, cblend); OUT_RING_REG(RADEON_PP_TXABLEND_0, ablend); if (pMask) OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0 | RADEON_SE_VTX_FMT_ST1)); else OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0)); /* Op operator. */ blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); OUT_RING_REG(RADEON_RB3D_BLENDCNTL, blendcntl); OUT_RING_REG(RADEON_RE_TOP_LEFT, 0); OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, (((pDst->drawable.width - 1) << RADEON_RE_WIDTH_SHIFT) | ((pDst->drawable.height - 1) << RADEON_RE_HEIGHT_SHIFT))); ADVANCE_RING(); return TRUE; } static Bool R200CheckCompositeTexture(PicturePtr pPict, PicturePtr pDstPict, int op, int unit) { unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; int i; for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++) { if (R200TexFormats[i].fmt == pPict->format) break; } if (i == sizeof(R200TexFormats) / sizeof(R200TexFormats[0])) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); if (pPict->pDrawable && !RADEONCheckTexturePOT(pPict, unit == 0)) return FALSE; if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); /* for REPEAT_NONE, Render semantics are that sampling outside the source * picture results in alpha=0 pixels. We can implement this with a border color * *if* our source texture has an alpha channel, otherwise we need to fall * back. If we're not transformed then we hope that upper layers have clipped * rendering to the bounds of the source drawable, in which case it doesn't * matter. I have not, however, verified that the X server always does such * clipping. */ if (pPict->transform != 0 && repeatType == RepeatNone && PICT_FORMAT_A(pPict->format) == 0) { if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); } if (!radeon_transform_is_affine_or_scaled(pPict->transform)) RADEON_FALLBACK(("non-affine transforms not supported\n")); return TRUE; } static Bool R200TextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t txfilter, txformat, txoffset, txpitch; unsigned int repeatType; Bool repeat; int i, w, h; struct radeon_exa_pixmap_priv *driver_priv; if (pPict->pDrawable) { w = pPict->pDrawable->width; h = pPict->pDrawable->height; repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; } else { w = h = 1; repeatType = RepeatNormal; } repeat = (repeatType == RepeatNormal || repeatType == RepeatReflect) && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); txpitch = exaGetPixmapPitch(pPix); txoffset = 0; if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++) { if (R200TexFormats[i].fmt == pPict->format) break; } txformat = R200TexFormats[i].card_fmt; if (RADEONPixmapIsColortiled(pPix)) txoffset |= R200_TXO_MACRO_TILE; if (repeat) { if (!RADEONPitchMatches(pPix)) RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", w, (unsigned)txpitch)); txformat |= RADEONLog2(w) << R200_TXFORMAT_WIDTH_SHIFT; txformat |= RADEONLog2(h) << R200_TXFORMAT_HEIGHT_SHIFT; } else txformat |= R200_TXFORMAT_NON_POWER2; txformat |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT; info->accel_state->texW[unit] = w; info->accel_state->texH[unit] = h; switch (pPict->filter) { case PictFilterNearest: txfilter = (R200_MAG_FILTER_NEAREST | R200_MIN_FILTER_NEAREST); break; case PictFilterBilinear: txfilter = (R200_MAG_FILTER_LINEAR | R200_MIN_FILTER_LINEAR); break; default: RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } switch (repeatType) { case RepeatNormal: if (txformat & R200_TXFORMAT_NON_POWER2) txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; else txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP; break; case RepeatPad: txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; break; case RepeatReflect: txfilter |= R200_CLAMP_S_MIRROR | R200_CLAMP_T_MIRROR; break; case RepeatNone: /* don't set an illegal clamp mode for rect textures */ if (txformat & R200_TXFORMAT_NON_POWER2) txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; break; } BEGIN_ACCEL_RELOC(6, 1); if (unit == 0) { OUT_RING_REG(R200_PP_TXFILTER_0, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_0, txformat); OUT_RING_REG(R200_PP_TXFORMAT_X_0, 0); OUT_RING_REG(R200_PP_TXSIZE_0, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(R200_PP_TXPITCH_0, txpitch - 32); EMIT_READ_OFFSET(R200_PP_TXOFFSET_0, txoffset, pPix); } else { OUT_RING_REG(R200_PP_TXFILTER_1, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_1, txformat); OUT_RING_REG(R200_PP_TXFORMAT_X_1, 0); OUT_RING_REG(R200_PP_TXSIZE_1, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(R200_PP_TXPITCH_1, txpitch - 32); EMIT_READ_OFFSET(R200_PP_TXOFFSET_1, txoffset, pPix); /* emit a texture relocation */ } ADVANCE_RING(); if (pPict->transform != 0) { info->accel_state->is_transform[unit] = TRUE; info->accel_state->transform[unit] = pPict->transform; } else { info->accel_state->is_transform[unit] = FALSE; } return TRUE; } static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { PixmapPtr pSrcPixmap, pDstPixmap; uint32_t tmp1; TRACE; /* Check for unsupported compositing operations. */ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); if (pDstPixmap->drawable.width > 2048 || pDstPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); } if (pSrcPicture->pDrawable) { /* r200 limit should be 2048, there are issues with 2048 * see 197a62704742a4a19736c2637ac92d1dc5ab34ed */ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); if (pSrcPixmap->drawable.width > 2048 || pSrcPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); } } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture) { PixmapPtr pMaskPixmap; if (pMaskPicture->pDrawable) { pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); if (pMaskPixmap->drawable.width > 2048 || pMaskPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); } } else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture->componentAlpha) { /* Check if it's component alpha that relies on a source alpha and * on the source value. We can only get one of those into the * single source value that we get to blend with. */ if (RadeonBlendOp[op].src_alpha && (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != RADEON_SRC_BLEND_GL_ZERO) { RADEON_FALLBACK(("Component alpha not supported with source " "alpha and source value blending.\n")); } } if (!R200CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1)) return FALSE; } if (!R200CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0)) return FALSE; if (!RADEONGetDestFormat(pDstPicture, &tmp1)) return FALSE; return TRUE; } static Bool R200PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; RINFO_FROM_SCREEN(pScreen); uint32_t dst_format, dst_pitch; uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; int pixel_shift; struct radeon_exa_pixmap_priv *driver_priv; TRACE; if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) RADEON_FALLBACK(("Can't dst alpha blend A8\n")); pixel_shift = pDst->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; if (RADEONPixmapIsColortiled(pDst)) colorpitch |= RADEON_COLOR_TILE_ENABLE; if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); if (!pSrc) { pSrc = RADEONSolidPixmap(pScreen, cpu_to_le32(pSrcPicture->pSourcePict->solidFill.color)); if (!pSrc) RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) return FALSE; if (pMaskPicture && !pMask) { pMask = RADEONSolidPixmap(pScreen, cpu_to_le32(pMaskPicture->pSourcePict->solidFill.color)); if (!pMask) { if (!pSrcPicture->pDrawable) pScreen->DestroyPixmap(pSrc); RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } } RADEONPrepareCompositeCS(op, pSrcPicture, pMaskPicture, pDstPicture, pSrc, pMask, pDst); /* switch to 3D after doing buffer space checks as it may flush */ RADEON_SWITCH_TO_3D(); if (!R200TextureSetup(pSrcPicture, pSrc, 0)) return FALSE; pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; if (pMask != NULL) { if (!R200TextureSetup(pMaskPicture, pMask, 1)) return FALSE; pp_cntl |= RADEON_TEX_1_ENABLE; } else { info->accel_state->is_transform[1] = FALSE; } BEGIN_ACCEL_RELOC(12, 2); OUT_RING_REG(RADEON_PP_CNTL, pp_cntl); OUT_RING_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE); EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pDst); EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pDst); OUT_RING_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); if (pMask) OUT_RING_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); else OUT_RING_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); /* IN operator: Multiply src by mask components or mask alpha. * BLEND_CTL_ADD is A * B + C. * If a picture is a8, we have to explicitly zero its color values. * If the destination is a8, we have to route the alpha to red, I think. * If we're doing component alpha where the source for blending is going to * be the source alpha (and there's no source value used), we have to zero * the source's color values. */ cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO; ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO; if (pDstPicture->format == PICT_a8 || (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha)) { cblend |= R200_TXC_ARG_A_R0_ALPHA; } else if (pSrcPicture->format == PICT_a8) cblend |= R200_TXC_ARG_A_ZERO; else cblend |= R200_TXC_ARG_A_R0_COLOR; ablend |= R200_TXA_ARG_A_R0_ALPHA; if (pMask) { if (pMaskPicture->componentAlpha && pDstPicture->format != PICT_a8) cblend |= R200_TXC_ARG_B_R1_COLOR; else cblend |= R200_TXC_ARG_B_R1_ALPHA; ablend |= R200_TXA_ARG_B_R1_ALPHA; } else { cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B; ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B; } OUT_RING_REG(R200_PP_TXCBLEND_0, cblend); OUT_RING_REG(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); OUT_RING_REG(R200_PP_TXABLEND_0, ablend); OUT_RING_REG(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); /* Op operator. */ blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); OUT_RING_REG(RADEON_RB3D_BLENDCNTL, blendcntl); OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, (((pDst->drawable.width - 1) << RADEON_RE_WIDTH_SHIFT) | ((pDst->drawable.height - 1) << RADEON_RE_HEIGHT_SHIFT))); ADVANCE_RING(); return TRUE; } static Bool R300CheckCompositeTexture(PicturePtr pPict, PicturePtr pDstPict, int op, int unit, Bool is_r500) { unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; int i; for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) { if (R300TexFormats[i].fmt == pPict->format) break; } if (i == sizeof(R300TexFormats) / sizeof(R300TexFormats[0])) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); if (pPict->pDrawable && !RADEONCheckTexturePOT(pPict, unit == 0)) { #if 0 struct radeon_exa_pixmap_priv *driver_priv; PixmapPtr pPix; pPix = RADEONGetDrawablePixmap(pPict->pDrawable); driver_priv = exaGetPixmapDriverPrivate(pPix); //TODOradeon_bufmgr_gem_force_gtt(driver_priv->bo); #endif return FALSE; } if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); /* for REPEAT_NONE, Render semantics are that sampling outside the source * picture results in alpha=0 pixels. We can implement this with a border color * *if* our source texture has an alpha channel, otherwise we need to fall * back. If we're not transformed then we hope that upper layers have clipped * rendering to the bounds of the source drawable, in which case it doesn't * matter. I have not, however, verified that the X server always does such * clipping. */ if (pPict->transform != 0 && repeatType == RepeatNone && PICT_FORMAT_A(pPict->format) == 0) { if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); } if (!radeon_transform_is_affine_or_scaled(pPict->transform)) RADEON_FALLBACK(("non-affine transforms not supported\n")); return TRUE; } static Bool R300TextureSetup(PicturePtr pPict, PixmapPtr pPix, int unit) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t txfilter, txformat0, txformat1, txoffset, txpitch, us_format = 0; int w, h; int i, pixel_shift, out_size = 6; unsigned int repeatType; struct radeon_exa_pixmap_priv *driver_priv; TRACE; if (pPict->pDrawable) { w = pPict->pDrawable->width; h = pPict->pDrawable->height; repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; } else { w = h = 1; repeatType = RepeatNormal; } txpitch = exaGetPixmapPitch(pPix); txoffset = 0; if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); /* TXPITCH = pixels (texels) per line - 1 */ pixel_shift = pPix->drawable.bitsPerPixel >> 4; txpitch >>= pixel_shift; txpitch -= 1; if (RADEONPixmapIsColortiled(pPix)) txoffset |= R300_MACRO_TILE; for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) { if (R300TexFormats[i].fmt == pPict->format) break; } txformat1 = R300TexFormats[i].card_fmt; if (IS_R300_3D) { if ((unit == 0) && info->accel_state->msk_pic) txformat1 |= R300_TX_FORMAT_CACHE_HALF_REGION_0; else if (unit == 1) txformat1 |= R300_TX_FORMAT_CACHE_HALF_REGION_1; } txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); if (IS_R500_3D && ((w - 1) & 0x800)) txpitch |= R500_TXWIDTH_11; if (IS_R500_3D && ((h - 1) & 0x800)) txpitch |= R500_TXHEIGHT_11; if (info->ChipFamily == CHIP_FAMILY_R520) { unsigned us_width = (w - 1) & 0x7ff; unsigned us_height = (h - 1) & 0x7ff; unsigned us_depth = 0; if (w > 2048) { us_width = (0x7ff + us_width) >> 1; us_depth |= 0x0d; } if (h > 2048) { us_height = (0x7ff + us_height) >> 1; us_depth |= 0x0e; } us_format = (us_width << R300_TXWIDTH_SHIFT) | (us_height << R300_TXHEIGHT_SHIFT) | (us_depth << R300_TXDEPTH_SHIFT); out_size++; } /* Use TXPITCH instead of TXWIDTH for address computations: we could * omit this if there is no padding, but there is no apparent advantage * in doing so. */ txformat0 |= R300_TXPITCH_EN; txfilter = (unit << R300_TX_ID_SHIFT); switch (repeatType) { case RepeatNormal: if (unit != 0 || !info->accel_state->need_src_tile_x) txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); else txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); if (unit != 0 || !info->accel_state->need_src_tile_y) txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); else txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); break; case RepeatPad: txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST); break; case RepeatReflect: txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_MIRROR) | R300_TX_CLAMP_T(R300_TX_CLAMP_MIRROR); break; case RepeatNone: txfilter |= R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); break; } switch (pPict->filter) { case PictFilterNearest: txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); break; case PictFilterBilinear: txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); break; default: RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } if (repeatType == RepeatNone) out_size++; BEGIN_ACCEL_RELOC(out_size, 1); OUT_RING_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); OUT_RING_REG(R300_TX_FILTER1_0 + (unit * 4), 0); OUT_RING_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); OUT_RING_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); OUT_RING_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); EMIT_READ_OFFSET((R300_TX_OFFSET_0 + (unit * 4)), txoffset, pPix); if (repeatType == RepeatNone) OUT_RING_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); if (info->ChipFamily == CHIP_FAMILY_R520) OUT_RING_REG(R500_US_FORMAT0_0 + (unit * 4), us_format); ADVANCE_RING(); if (pPict->transform != 0) { info->accel_state->is_transform[unit] = TRUE; info->accel_state->transform[unit] = pPict->transform; /* setup the PVS consts */ if (info->accel_state->has_tcl) { info->accel_state->texW[unit] = 1; info->accel_state->texH[unit] = 1; BEGIN_RING(2*9); if (IS_R300_3D) OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_CONST_INDEX(unit * 2)); else OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R500_PVS_VECTOR_CONST_INDEX(unit * 2)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[0][0]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[0][1]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[0][2]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0/w)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[1][0]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[1][1]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(pPict->transform->matrix[1][2]))); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0/h)); ADVANCE_RING(); } else { info->accel_state->texW[unit] = w; info->accel_state->texH[unit] = h; } } else { info->accel_state->is_transform[unit] = FALSE; /* setup the PVS consts */ if (info->accel_state->has_tcl) { info->accel_state->texW[unit] = 1; info->accel_state->texH[unit] = 1; BEGIN_RING(2*9); if (IS_R300_3D) OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_CONST_INDEX(unit * 2)); else OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R500_PVS_VECTOR_CONST_INDEX(unit * 2)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0/w)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(1.0/h)); ADVANCE_RING(); } else { info->accel_state->texW[unit] = w; info->accel_state->texH[unit] = h; } } return TRUE; } static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { uint32_t tmp1; ScreenPtr pScreen = pDstPicture->pDrawable->pScreen; PixmapPtr pSrcPixmap, pDstPixmap; ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); int max_tex_w, max_tex_h, max_dst_w, max_dst_h; TRACE; /* Check for unsupported compositing operations. */ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); if (IS_R500_3D) { max_tex_w = 4096; max_tex_h = 4096; max_dst_w = 4096; max_dst_h = 4096; } else { max_tex_w = 2048; max_tex_h = 2048; if (IS_R400_3D) { max_dst_w = 4021; max_dst_h = 4021; } else { max_dst_w = 2560; max_dst_h = 2560; } } pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); if (pDstPixmap->drawable.width > max_dst_w || pDstPixmap->drawable.height > max_dst_h) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); } if (pSrcPicture->pDrawable) { pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); if (pSrcPixmap->drawable.width > max_tex_w || pSrcPixmap->drawable.height > max_tex_h) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); } } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture) { PixmapPtr pMaskPixmap; if (pMaskPicture->pDrawable) { pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); if (pMaskPixmap->drawable.width > max_tex_w || pMaskPixmap->drawable.height > max_tex_h) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); } } else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill) RADEON_FALLBACK(("Gradient pictures not supported yet\n")); if (pMaskPicture->componentAlpha) { /* Check if it's component alpha that relies on a source alpha and * on the source value. We can only get one of those into the * single source value that we get to blend with. */ if (RadeonBlendOp[op].src_alpha && (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != RADEON_SRC_BLEND_GL_ZERO) { RADEON_FALLBACK(("Component alpha not supported with source " "alpha and source value blending.\n")); } } if (!R300CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1, IS_R500_3D)) return FALSE; } if (!R300CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0, IS_R500_3D)) return FALSE; if (!R300GetDestFormat(pDstPicture, &tmp1)) return FALSE; return TRUE; } static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; RINFO_FROM_SCREEN(pScreen); uint32_t dst_format, dst_pitch; uint32_t txenable, colorpitch; uint32_t blendcntl, output_fmt; uint32_t src_color, src_alpha; uint32_t mask_color, mask_alpha; int pixel_shift; struct radeon_exa_pixmap_priv *driver_priv; TRACE; if (!R300GetDestFormat(pDstPicture, &dst_format)) return FALSE; pixel_shift = pDst->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; if (RADEONPixmapIsColortiled(pDst)) colorpitch |= R300_COLORTILE; colorpitch |= dst_format; if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); if (!pSrc) { pSrc = RADEONSolidPixmap(pScreen, cpu_to_le32(pSrcPicture->pSourcePict->solidFill.color)); if (!pSrc) RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) return FALSE; if (pMaskPicture && !pMask) { pMask = RADEONSolidPixmap(pScreen, cpu_to_le32(pMaskPicture->pSourcePict->solidFill.color)); if (!pMask) { if (!pSrcPicture->pDrawable) pScreen->DestroyPixmap(pSrc); RADEON_FALLBACK(("Failed to create solid scratch pixmap\n")); } } RADEONPrepareCompositeCS(op, pSrcPicture, pMaskPicture, pDstPicture, pSrc, pMask, pDst); /* have to execute switch after doing buffer sizing check as the latter flushes */ RADEON_SWITCH_TO_3D(); if (!R300TextureSetup(pSrcPicture, pSrc, 0)) return FALSE; txenable = R300_TEX_0_ENABLE; if (pMask != NULL) { if (!R300TextureSetup(pMaskPicture, pMask, 1)) return FALSE; txenable |= R300_TEX_1_ENABLE; } else { info->accel_state->is_transform[1] = FALSE; } /* setup the VAP */ if (info->accel_state->has_tcl) { if (pMask) BEGIN_RING(2*10); else BEGIN_RING(2*9); OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); } else { if (pMask) BEGIN_RING(2*6); else BEGIN_RING(2*5); } /* These registers define the number, type, and location of data submitted * to the PVS unit of GA input (when PVS is disabled) * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is * enabled. This memory provides the imputs to the vertex shader program * and ordering is not important. When PVS/TCL is disabled, this field maps * directly to the GA input memory and the order is signifigant. In * PVS_BYPASS mode the order is as follows: * Position * Point Size * Color 0-3 * Textures 0-7 * Fog */ if (pMask) { OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_SIGNED_1)); OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_1, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | (0 << R300_SKIP_DWORDS_2_SHIFT) | (7 << R300_DST_VEC_LOC_2_SHIFT) | R300_LAST_VEC_2 | R300_SIGNED_2)); } else OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_LAST_VEC_1 | R300_SIGNED_1)); /* load the vertex shader * We pre-load vertex programs in RADEONInit3DEngine(): * - exa * - Xv * - Xv bicubic * Here we select the offset of the vertex program we want to use */ if (info->accel_state->has_tcl) { if (pMask) { /* consts used by vertex shaders */ OUT_RING_REG(R300_VAP_PVS_CONST_CNTL, (R300_PVS_CONST_BASE_OFFSET(0) | R300_PVS_MAX_CONST_ADDR(3))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((0 << R300_PVS_FIRST_INST_SHIFT) | (8 << R300_PVS_XYZW_VALID_INST_SHIFT) | (8 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (8 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } else { /* consts used by vertex shaders */ OUT_RING_REG(R300_VAP_PVS_CONST_CNTL, (R300_PVS_CONST_BASE_OFFSET(0) | R300_PVS_MAX_CONST_ADDR(3))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((0 << R300_PVS_FIRST_INST_SHIFT) | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | (4 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } } /* Position and one or two sets of 2 texture coordinates */ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); if (pMask) OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | (2 << R300_TEX_1_COMP_CNT_SHIFT))); else OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); OUT_RING_REG(R300_TX_INVALTAGS, 0x0); OUT_RING_REG(R300_TX_ENABLE, txenable); ADVANCE_RING(); /* shader output swizzling */ switch (pDstPicture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: default: output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA); break; case PICT_a8b8g8r8: case PICT_x8b8g8r8: output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_RED | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_BLUE | R300_OUT_FMT_C3_SEL_ALPHA); break; case PICT_b8g8r8a8: case PICT_b8g8r8x8: output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_ALPHA | R300_OUT_FMT_C1_SEL_RED | R300_OUT_FMT_C2_SEL_GREEN | R300_OUT_FMT_C3_SEL_BLUE); break; case PICT_a8: output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_ALPHA); break; } /* setup pixel shader */ if (IS_R300_3D) { if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) src_color = R300_ALU_RGB_0_0; else src_color = R300_ALU_RGB_SRC0_RGB; if (PICT_FORMAT_A(pSrcPicture->format) == 0) src_alpha = R300_ALU_ALPHA_1_0; else src_alpha = R300_ALU_ALPHA_SRC0_A; if (pMask) { if (pMaskPicture->componentAlpha) { if (RadeonBlendOp[op].src_alpha) { if (PICT_FORMAT_A(pSrcPicture->format) == 0) src_color = R300_ALU_RGB_1_0; else src_color = R300_ALU_RGB_SRC0_AAA; } else src_color = R300_ALU_RGB_SRC0_RGB; mask_color = R300_ALU_RGB_SRC1_RGB; } else { if (PICT_FORMAT_A(pMaskPicture->format) == 0) mask_color = R300_ALU_RGB_1_0; else mask_color = R300_ALU_RGB_SRC1_AAA; } if (PICT_FORMAT_A(pMaskPicture->format) == 0) mask_alpha = R300_ALU_ALPHA_1_0; else mask_alpha = R300_ALU_ALPHA_SRC1_A; } else { mask_color = R300_ALU_RGB_1_0; mask_alpha = R300_ALU_ALPHA_1_0; } /* setup the rasterizer, load FS */ if (pMask) { BEGIN_RING(2*16); /* 4 components: 2 for tex0, 2 for tex1 */ OUT_RING_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1)); OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(0) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(1))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(1) | R300_RGBA_OUT)); } else { BEGIN_RING(2*15); /* 2 components: 2 for tex0 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(0) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(0))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0) | R300_RGBA_OUT)); } OUT_RING_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); OUT_RING_REG(R300_US_CODE_ADDR_0, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0))); OUT_RING_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0))); OUT_RING_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0))); OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */ /* shader output swizzling */ OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt); /* tex inst for src texture */ OUT_RING_REG(R300_US_TEX_INST(0), (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(0) | R300_TEX_ID(0) | R300_TEX_INST(R300_TEX_INST_LD))); if (pMask) { /* tex inst for mask texture */ OUT_RING_REG(R300_US_TEX_INST(1), (R300_TEX_SRC_ADDR(1) | R300_TEX_DST_ADDR(1) | R300_TEX_ID(1) | R300_TEX_INST(R300_TEX_INST_LD))); } /* RGB inst * temp addresses for texture inputs * ALU_RGB_ADDR0 is src tex (temp 0) * ALU_RGB_ADDR1 is mask tex (temp 1) * R300_ALU_RGB_OMASK - output components to write * R300_ALU_RGB_TARGET_A - render target */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(1) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G | R300_ALU_RGB_MASK_B)) | R300_ALU_RGB_TARGET_A)); /* RGB inst * ALU operation */ OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(src_color) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(mask_color) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | R300_ALU_RGB_CLAMP)); /* Alpha inst * temp addresses for texture inputs * ALU_ALPHA_ADDR0 is src tex (0) * ALU_ALPHA_ADDR1 is mask tex (1) * R300_ALU_ALPHA_OMASK - output components to write * R300_ALU_ALPHA_TARGET_A - render target */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(0) | R300_ALU_ALPHA_ADDR1(1) | R300_ALU_ALPHA_ADDR2(0) | R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | R300_ALU_ALPHA_TARGET_A | R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); /* Alpha inst * ALU operation */ OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_SEL_A(src_alpha) | R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_SEL_B(mask_alpha) | R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | R300_ALU_ALPHA_CLAMP)); ADVANCE_RING(); } else { if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) src_color = (R500_ALU_RGB_R_SWIZ_A_0 | R500_ALU_RGB_G_SWIZ_A_0 | R500_ALU_RGB_B_SWIZ_A_0); else src_color = (R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B); if (PICT_FORMAT_A(pSrcPicture->format) == 0) src_alpha = R500_ALPHA_SWIZ_A_1; else src_alpha = R500_ALPHA_SWIZ_A_A; if (pMask) { if (pMaskPicture->componentAlpha) { if (RadeonBlendOp[op].src_alpha) { if (PICT_FORMAT_A(pSrcPicture->format) == 0) src_color = (R500_ALU_RGB_R_SWIZ_A_1 | R500_ALU_RGB_G_SWIZ_A_1 | R500_ALU_RGB_B_SWIZ_A_1); else src_color = (R500_ALU_RGB_R_SWIZ_A_A | R500_ALU_RGB_G_SWIZ_A_A | R500_ALU_RGB_B_SWIZ_A_A); } else src_color = (R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B); mask_color = (R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B); } else { if (PICT_FORMAT_A(pMaskPicture->format) == 0) mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1); else mask_color = (R500_ALU_RGB_R_SWIZ_B_A | R500_ALU_RGB_G_SWIZ_B_A | R500_ALU_RGB_B_SWIZ_B_A); } if (PICT_FORMAT_A(pMaskPicture->format) == 0) mask_alpha = R500_ALPHA_SWIZ_B_1; else mask_alpha = R500_ALPHA_SWIZ_B_A; } else { mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1); mask_alpha = R500_ALPHA_SWIZ_B_1; } BEGIN_RING(2*7); if (pMask) { /* 4 components: 2 for tex0, 2 for tex1 */ OUT_RING_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* 2 RS instructions: 1 for tex0 (src), 1 for tex1 (mask) */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1)); OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(2))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(2))); OUT_RING_REG(R500_US_CODE_OFFSET, 0); } else { OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1))); OUT_RING_REG(R500_US_CODE_OFFSET, 0); } OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */ OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt); ADVANCE_RING(); if (pMask) { BEGIN_RING(2*19); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); /* tex inst for src texture */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* tex inst for mask texture */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(1) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(1) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(1) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); } else { BEGIN_RING(2*13); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); /* tex inst for src texture */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); } /* ALU inst */ /* *_OMASK* - output component write mask */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); /* ALU inst * temp addresses for texture inputs * RGB_ADDR0 is src tex (temp 0) * RGB_ADDR1 is mask tex (temp 1) */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR1(1) | R500_RGB_ADDR2(0))); /* ALU inst * temp addresses for texture inputs * ALPHA_ADDR0 is src tex (temp 0) * ALPHA_ADDR1 is mask tex (temp 1) */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(1) | R500_ALPHA_ADDR2(0))); /* R500_ALU_RGB_TARGET - RGB render target */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | src_color | R500_ALU_RGB_SEL_B_SRC1 | mask_color | R500_ALU_RGB_TARGET(0))); /* R500_ALPHA_RGB_TARGET - alpha render target */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(0) | R500_ALPHA_SEL_A_SRC0 | src_alpha | R500_ALPHA_SEL_B_SRC1 | mask_alpha | R500_ALPHA_TARGET(0))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(0) | R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0)); ADVANCE_RING(); } /* Clear out scissoring */ BEGIN_RING(2*2); if (IS_R300_3D) { OUT_RING_REG(R300_SC_SCISSOR0, ((1440 << R300_SCISSOR_X_SHIFT) | (1440 << R300_SCISSOR_Y_SHIFT))); OUT_RING_REG(R300_SC_SCISSOR1, (((pDst->drawable.width + 1440 - 1) << R300_SCISSOR_X_SHIFT) | ((pDst->drawable.height + 1440 - 1) << R300_SCISSOR_Y_SHIFT))); } else { OUT_RING_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | (0 << R300_SCISSOR_Y_SHIFT))); OUT_RING_REG(R300_SC_SCISSOR1, (((pDst->drawable.width - 1) << R300_SCISSOR_X_SHIFT) | ((pDst->drawable.height - 1) << R300_SCISSOR_Y_SHIFT))); } ADVANCE_RING(); BEGIN_ACCEL_RELOC(3, 2); EMIT_WRITE_OFFSET(R300_RB3D_COLOROFFSET0, 0, pDst); EMIT_COLORPITCH(R300_RB3D_COLORPITCH0, colorpitch, pDst); blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); OUT_RING_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); ADVANCE_RING(); BEGIN_RING(2*1); if (pMask) OUT_RING_REG(R300_VAP_VTX_SIZE, 6); else OUT_RING_REG(R300_VAP_VTX_SIZE, 4); ADVANCE_RING(); return TRUE; } static void RadeonFinishComposite(PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); ENTER_DRAW(0); if (info->accel_state->draw_header) { if (info->ChipFamily < CHIP_FAMILY_R200) { info->accel_state->draw_header[0] = CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, info->accel_state->num_vtx * info->accel_state->vtx_count + 1); info->accel_state->draw_header[2] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else if (IS_R300_3D || IS_R500_3D) { info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, info->accel_state->num_vtx * info->accel_state->vtx_count); info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else { info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, info->accel_state->num_vtx * info->accel_state->vtx_count); info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT)); } info->accel_state->draw_header = NULL; } if (IS_R300_3D || IS_R500_3D) { BEGIN_RING(2*3); OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); } else BEGIN_RING(2*1); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); LEAVE_DRAW(0); } static void RadeonDoneComposite(PixmapPtr pDst) { ScreenPtr pScreen = pDst->drawable.pScreen; RINFO_FROM_SCREEN(pScreen); struct radeon_accel_state *accel_state = info->accel_state; RadeonFinishComposite(pDst); if (!accel_state->src_pic->pDrawable) pScreen->DestroyPixmap(accel_state->src_pix); if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable) pScreen->DestroyPixmap(accel_state->msk_pix); } #define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ OUT_RING(F_TO_DW(_dstX)); \ OUT_RING(F_TO_DW(_dstY)); \ OUT_RING(F_TO_DW(_srcX)); \ OUT_RING(F_TO_DW(_srcY)); \ OUT_RING(F_TO_DW(_maskX)); \ OUT_RING(F_TO_DW(_maskY)); \ } while (0) #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ do { \ OUT_RING(F_TO_DW(_dstX)); \ OUT_RING(F_TO_DW(_dstY)); \ OUT_RING(F_TO_DW(_srcX)); \ OUT_RING(F_TO_DW(_srcY)); \ } while (0) static inline void transformPoint(PictTransform *transform, xPointFixed *point) { PictVector v; v.vector[0] = point->x; v.vector[1] = point->y; v.vector[2] = xFixed1; PictureTransformPoint(transform, &v); point->x = v.vector[0]; point->y = v.vector[1]; } static void RadeonCompositeTile(ScrnInfoPtr pScrn, RADEONInfoPtr info, PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { int vtx_count; xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; static xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; ENTER_DRAW(0); /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ if (CS_FULL(info->cs)) { RadeonFinishComposite(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); info->accel_state->exa->PrepareComposite(info->accel_state->composite_op, info->accel_state->src_pic, info->accel_state->msk_pic, info->accel_state->dst_pic, info->accel_state->src_pix, info->accel_state->msk_pix, info->accel_state->dst_pix); } srcTopLeft.x = IntToxFixed(srcX); srcTopLeft.y = IntToxFixed(srcY); srcTopRight.x = IntToxFixed(srcX + w); srcTopRight.y = IntToxFixed(srcY); srcBottomLeft.x = IntToxFixed(srcX); srcBottomLeft.y = IntToxFixed(srcY + h); srcBottomRight.x = IntToxFixed(srcX + w); srcBottomRight.y = IntToxFixed(srcY + h); if (info->accel_state->is_transform[0]) { if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) { transformPoint(info->accel_state->transform[0], &srcTopLeft); transformPoint(info->accel_state->transform[0], &srcTopRight); transformPoint(info->accel_state->transform[0], &srcBottomLeft); transformPoint(info->accel_state->transform[0], &srcBottomRight); } } if (info->accel_state->msk_pic) { maskTopLeft.x = IntToxFixed(maskX); maskTopLeft.y = IntToxFixed(maskY); maskTopRight.x = IntToxFixed(maskX + w); maskTopRight.y = IntToxFixed(maskY); maskBottomLeft.x = IntToxFixed(maskX); maskBottomLeft.y = IntToxFixed(maskY + h); maskBottomRight.x = IntToxFixed(maskX + w); maskBottomRight.y = IntToxFixed(maskY + h); if (info->accel_state->is_transform[1]) { if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) { transformPoint(info->accel_state->transform[1], &maskTopLeft); transformPoint(info->accel_state->transform[1], &maskTopRight); transformPoint(info->accel_state->transform[1], &maskBottomLeft); transformPoint(info->accel_state->transform[1], &maskBottomRight); } } vtx_count = 6; } else vtx_count = 4; if (info->accel_state->vsync) RADEONWaitForVLine(pScrn, pDst, radeon_pick_best_crtc(pScrn, FALSE, dstX, dstX + w, dstY, dstY + h), dstY, dstY + h); if (info->ChipFamily < CHIP_FAMILY_R200) { if (!info->accel_state->draw_header) { BEGIN_RING(3); info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 3 * vtx_count + 1)); if (info->accel_state->msk_pic) OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_ST1); else OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); } info->accel_state->num_vtx += 3; BEGIN_RING(3 * vtx_count); } else if (IS_R300_3D || IS_R500_3D) { if (!info->accel_state->draw_header) { BEGIN_RING(2); info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 4 * vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); } info->accel_state->num_vtx += 4; BEGIN_RING(4 * vtx_count); } else { if (!info->accel_state->draw_header) { BEGIN_RING(2); info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 3 * vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); } info->accel_state->num_vtx += 3; BEGIN_RING(3 * vtx_count); } if (info->accel_state->msk_pic) { if (IS_R300_3D || IS_R500_3D) { VTX_OUT_MASK((float)dstX, (float)dstY, xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0], xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]); } VTX_OUT_MASK((float)dstX, (float)(dstY + h), xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0], xFixedToFloat(maskBottomLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomLeft.y) / info->accel_state->texH[1]); VTX_OUT_MASK((float)(dstX + w), (float)(dstY + h), xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0], xFixedToFloat(maskBottomRight.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomRight.y) / info->accel_state->texH[1]); VTX_OUT_MASK((float)(dstX + w), (float)dstY, xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0], xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1], xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]); } else { if (IS_R300_3D || IS_R500_3D) { VTX_OUT((float)dstX, (float)dstY, xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]); } VTX_OUT((float)dstX, (float)(dstY + h), xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]); VTX_OUT((float)(dstX + w), (float)(dstY + h), xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]); VTX_OUT((float)(dstX + w), (float)dstY, xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); } ADVANCE_RING(); LEAVE_DRAW(0); } #undef VTX_OUT #undef VTX_OUT_MASK static void RadeonComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int width, int height) { int tileSrcY, tileMaskY, tileDstY; int remainingHeight; RINFO_FROM_SCREEN(pDst->drawable.pScreen); if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) { RadeonCompositeTile(pScrn, info, pDst, srcX, srcY, maskX, maskY, dstX, dstY, width, height); return; } /* Tiling logic borrowed from exaFillRegionTiled */ modulus(srcY, info->accel_state->src_tile_height, tileSrcY); tileMaskY = maskY; tileDstY = dstY; remainingHeight = height; while (remainingHeight > 0) { int remainingWidth = width; int tileSrcX, tileMaskX, tileDstX; int h = info->accel_state->src_tile_height - tileSrcY; if (h > remainingHeight) h = remainingHeight; remainingHeight -= h; modulus(srcX, info->accel_state->src_tile_width, tileSrcX); tileMaskX = maskX; tileDstX = dstX; while (remainingWidth > 0) { int w = info->accel_state->src_tile_width - tileSrcX; if (w > remainingWidth) w = remainingWidth; remainingWidth -= w; RadeonCompositeTile(pScrn, info, pDst, tileSrcX, tileSrcY, tileMaskX, tileMaskY, tileDstX, tileDstY, w, h); tileSrcX = 0; tileMaskX += w; tileDstX += w; } tileSrcY = 0; tileMaskY += h; tileDstY += h; } } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_exa_shared.c000066400000000000000000000133651256524674500241040ustar00rootroot00000000000000/* * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * Copyright 2008 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Eric Anholt * Zack Rusin * Benjamin Herrenschmidt * Alex Deucher * Matthias Hopf */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon.h" #include "radeon_probe.h" #include "radeon_version.h" #include "radeon_vbo.h" PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable) { if (pDrawable->type == DRAWABLE_WINDOW) return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable); else return (PixmapPtr)pDrawable; } void RADEONVlineHelperClear(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; accel_state->vline_crtc = NULL; accel_state->vline_y1 = -1; accel_state->vline_y2 = 0; } void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, FALSE, x1, x2, y1, y2); if (accel_state->vline_y1 == -1) accel_state->vline_y1 = y1; if (y1 < accel_state->vline_y1) accel_state->vline_y1 = y1; if (y2 > accel_state->vline_y2) accel_state->vline_y2 = y2; } Bool RADEONValidPM(uint32_t pm, int bpp) { uint8_t r, g, b, a; Bool ret = FALSE; switch (bpp) { case 8: a = pm & 0xff; if ((a == 0) || (a == 0xff)) ret = TRUE; break; case 16: r = (pm >> 11) & 0x1f; g = (pm >> 5) & 0x3f; b = (pm >> 0) & 0x1f; if (((r == 0) || (r == 0x1f)) && ((g == 0) || (g == 0x3f)) && ((b == 0) || (b == 0x1f))) ret = TRUE; break; case 32: a = (pm >> 24) & 0xff; r = (pm >> 16) & 0xff; g = (pm >> 8) & 0xff; b = (pm >> 0) & 0xff; if (((a == 0) || (a == 0xff)) && ((r == 0) || (r == 0xff)) && ((g == 0) || (g == 0xff)) && ((b == 0) || (b == 0xff))) ret = TRUE; break; default: break; } return ret; } Bool RADEONCheckBPP(int bpp) { switch (bpp) { case 8: case 16: case 32: return TRUE; default: break; } return FALSE; } PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid) { PixmapPtr pPix = pScreen->CreatePixmap(pScreen, 1, 1, 32, 0); struct radeon_bo *bo; exaMoveInPixmap(pPix); bo = radeon_get_pixmap_bo(pPix); if (radeon_bo_map(bo, 1)) { pScreen->DestroyPixmap(pPix); return NULL; } memcpy(bo->ptr, &solid, 4); radeon_bo_unmap(bo); return pPix; } int radeon_cp_start(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (CS_FULL(info->cs)) { radeon_cs_flush_indirect(pScrn); } accel_state->ib_reset_op = info->cs->cdw; accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset; accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset; return 0; } void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; if (vbo->vb_bo) { if (vbo->vb_start_op != vbo->vb_offset) { accel_state->finish_op(pScrn, vert_size); accel_state->ib_reset_op = info->cs->cdw; } /* release the current VBO */ radeon_vbo_put(pScrn, vbo); } /* get a new one */ radeon_vbo_get(pScrn, vbo); return; } void radeon_ib_discard(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); int ret; if (info->accel_state->ib_reset_op) { /* if we have data just reset the CS and ignore the operation */ info->cs->cdw = info->accel_state->ib_reset_op; info->accel_state->ib_reset_op = 0; goto out; } info->accel_state->vbo.vb_offset = 0; info->accel_state->vbo.vb_start_op = -1; info->accel_state->cbuf.vb_offset = 0; info->accel_state->cbuf.vb_start_op = -1; if (CS_FULL(info->cs)) { radeon_cs_flush_indirect(pScrn); return; } radeon_cs_erase(info->cs); ret = radeon_cs_space_check_with_bo(info->cs, info->accel_state->vbo.vb_bo, RADEON_GEM_DOMAIN_GTT, 0); if (ret) ErrorF("space check failed in flush\n"); if (info->accel_state->cbuf.vb_bo) { ret = radeon_cs_space_check_with_bo(info->cs, info->accel_state->cbuf.vb_bo, RADEON_GEM_DOMAIN_GTT, 0); if (ret) ErrorF("space check failed in flush\n"); } out: if (info->dri2.enabled) { info->accel_state->XInited3D = FALSE; info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; } } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_exa_shared.h000066400000000000000000000054221256524674500241040ustar00rootroot00000000000000/* * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * Copyright 2008 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Eric Anholt * Zack Rusin * Benjamin Herrenschmidt * Alex Deucher * Matthias Hopf */ #ifndef RADEON_EXA_SHARED_H #define RADEON_EXA_SHARED_H extern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable); extern void RADEONVlineHelperClear(ScrnInfoPtr pScrn); extern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); extern Bool RADEONValidPM(uint32_t pm, int bpp); extern Bool RADEONCheckBPP(int bpp); extern PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid); #define RADEON_TRACE_FALL 0 #define RADEON_TRACE_DRAW 0 #if RADEON_TRACE_FALL #define RADEON_FALLBACK(x) \ do { \ ErrorF("%s: ", __FUNCTION__); \ ErrorF x; \ return FALSE; \ } while (0) #else #define RADEON_FALLBACK(x) return FALSE #endif #if RADEON_TRACE_DRAW #define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0) #else #define TRACE #endif static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain) { struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain); } extern void radeon_ib_discard(ScrnInfoPtr pScrn); extern int radeon_cp_start(ScrnInfoPtr pScrn); extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size); extern void radeon_vbo_done_composite(PixmapPtr pDst); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_glamor.c000066400000000000000000000237721256524674500232650ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation. * 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include "radeon.h" #include "radeon_bo_helper.h" #include "radeon_glamor.h" #if HAS_DEVPRIVATEKEYREC DevPrivateKeyRec glamor_pixmap_index; #else int glamor_pixmap_index; #endif void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) { RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(dst->drawable.pScreen)); if (!info->use_glamor) return; glamor_egl_exchange_buffers(src, dst); } Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); if (!info->use_glamor) return TRUE; #ifdef HAVE_GLAMOR_GLYPHS_INIT if (!glamor_glyphs_init(screen)) return FALSE; #endif if (!glamor_egl_create_textured_screen_ext(screen, info->front_bo->handle, scrn->displayWidth * info->pixel_bytes, NULL)) return FALSE; return TRUE; } Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { RADEONInfoPtr info = RADEONPTR(scrn); pointer glamor_module; CARD32 version; const char *s; if (!info->dri2.available) return FALSE; s = xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); if (s == NULL && info->ChipFamily < CHIP_FAMILY_TAHITI) return FALSE; if (s && strcasecmp(s, "glamor") != 0) { if (info->ChipFamily >= CHIP_FAMILY_TAHITI) xf86DrvMsg(scrn->scrnIndex, X_WARNING, "EXA not supported, using glamor\n"); else return FALSE; } if (info->ChipFamily < CHIP_FAMILY_R300) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "glamor requires R300 or higher GPU, disabling.\n"); return FALSE; } if (info->ChipFamily < CHIP_FAMILY_RV515) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "glamor may not work (well) with GPUs < RV515.\n"); } if (scrn->depth < 24) { xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING, "glamor requires depth >= 24, disabling.\n"); return FALSE; } #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,15,0,0,0) if (!xf86LoaderCheckSymbol("glamor_egl_init")) { xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING, "glamor requires Load \"glamoregl\" in " "Section \"Module\", disabling.\n"); return FALSE; } #endif /* Load glamor module */ if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) { version = xf86GetModuleVersion(glamor_module); if (version < MODULE_VERSION_NUMERIC(0,3,1)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Incompatible glamor version, required >= 0.3.0.\n"); return FALSE; } else { if (glamor_egl_init(scrn, info->dri2.drm_fd)) { xf86DrvMsg(scrn->scrnIndex, X_INFO, "glamor detected, initialising EGL layer.\n"); } else { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "glamor detected, failed to initialize EGL.\n"); return FALSE; } } } else { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "glamor not available\n"); return FALSE; } info->use_glamor = TRUE; return TRUE; } Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv) { return glamor_egl_create_textured_pixmap(pixmap, priv->bo->handle, pixmap->devKind); } static PixmapPtr radeon_glamor_create_pixmap(ScreenPtr screen, int w, int h, int depth, unsigned usage) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); struct radeon_pixmap *priv; PixmapPtr pixmap, new_pixmap = NULL; if (!RADEON_CREATE_PIXMAP_SHARED(usage)) { if (info->shadow_primary) { if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP) return fbCreatePixmap(screen, w, h, depth, usage); } else { pixmap = glamor_create_pixmap(screen, w, h, depth, usage); if (pixmap) return pixmap; } } if (w > 32767 || h > 32767) return NullPixmap; if (depth == 1) return fbCreatePixmap(screen, w, h, depth, usage); if (usage == CREATE_PIXMAP_USAGE_GLYPH_PICTURE && w <= 32 && h <= 32) return fbCreatePixmap(screen, w, h, depth, usage); pixmap = fbCreatePixmap(screen, 0, 0, depth, usage); if (pixmap == NullPixmap) return pixmap; if (w && h) { int stride; priv = calloc(1, sizeof (struct radeon_pixmap)); if (priv == NULL) goto fallback_pixmap; priv->bo = radeon_alloc_pixmap_bo(scrn, w, h, depth, usage, pixmap->drawable.bitsPerPixel, &stride, &priv->surface, &priv->tiling_flags); if (!priv->bo) goto fallback_priv; radeon_set_pixmap_private(pixmap, priv); screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL); if (!radeon_glamor_create_textured_pixmap(pixmap, priv)) goto fallback_glamor; pixmap->devPrivate.ptr = NULL; } return pixmap; fallback_glamor: if (RADEON_CREATE_PIXMAP_SHARED(usage)) { /* XXX need further work to handle the DRI2 failure case. * Glamor don't know how to handle a BO only pixmap. Put * a warning indicator here. */ xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Failed to create textured DRI2/PRIME pixmap."); return pixmap; } /* Create textured pixmap failed means glamor failed to * create a texture from current BO for some reasons. We turn * to create a new glamor pixmap and clean up current one. * One thing need to be noted, this new pixmap doesn't * has a priv and bo attached to it. It's glamor's responsbility * to take care of it. Glamor will mark this new pixmap as a * texture only pixmap and will never fallback to DDX layer * afterwards. */ new_pixmap = glamor_create_pixmap(screen, w, h, depth, usage); radeon_bo_unref(priv->bo); fallback_priv: free(priv); fallback_pixmap: fbDestroyPixmap(pixmap); if (new_pixmap) return new_pixmap; else return fbCreatePixmap(screen, w, h, depth, usage); } static Bool radeon_glamor_destroy_pixmap(PixmapPtr pixmap) { if (pixmap->refcnt == 1) { if (pixmap->devPrivate.ptr) { struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap); if (bo) radeon_bo_unmap(bo); } glamor_egl_destroy_textured_pixmap(pixmap); radeon_set_pixmap_bo(pixmap, NULL); } fbDestroyPixmap(pixmap); return TRUE; } #ifdef RADEON_PIXMAP_SHARING static Bool radeon_glamor_share_pixmap_backing(PixmapPtr pixmap, ScreenPtr slave, void **handle_p) { struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (!priv) return FALSE; return radeon_share_pixmap_backing(priv->bo, handle_p); } static Bool radeon_glamor_set_shared_pixmap_backing(PixmapPtr pixmap, void *handle) { ScreenPtr screen = pixmap->drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); struct radeon_surface surface; struct radeon_pixmap *priv; if (!radeon_set_shared_pixmap_backing(pixmap, handle, &surface)) return FALSE; priv = radeon_get_pixmap_private(pixmap); priv->surface = surface; if (!radeon_glamor_create_textured_pixmap(pixmap, priv)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to get PRIME drawable for glamor pixmap.\n"); return FALSE; } screen->ModifyPixmapHeader(pixmap, pixmap->drawable.width, pixmap->drawable.height, 0, 0, 0, NULL); return TRUE; } #endif /* RADEON_PIXMAP_SHARING */ Bool radeon_glamor_init(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); #ifdef RENDER #ifdef HAVE_FBGLYPHS UnrealizeGlyphProcPtr SavedUnrealizeGlyph = NULL; #endif PictureScreenPtr ps = NULL; if (info->shadow_primary) { ps = GetPictureScreenIfSet(screen); if (ps) { #ifdef HAVE_FBGLYPHS SavedUnrealizeGlyph = ps->UnrealizeGlyph; #endif info->glamor.SavedGlyphs = ps->Glyphs; info->glamor.SavedTriangles = ps->Triangles; info->glamor.SavedTrapezoids = ps->Trapezoids; } } #endif /* RENDER */ if (!glamor_init(screen, GLAMOR_USE_EGL_SCREEN | GLAMOR_USE_SCREEN | GLAMOR_USE_PICTURE_SCREEN | GLAMOR_INVERTED_Y_AXIS | GLAMOR_NO_DRI3)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to initialize glamor.\n"); return FALSE; } if (!glamor_egl_init_textured_pixmap(screen)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to initialize textured pixmap of screen for glamor.\n"); return FALSE; } #if HAS_DIXREGISTERPRIVATEKEY if (!dixRegisterPrivateKey(&glamor_pixmap_index, PRIVATE_PIXMAP, 0)) #else if (!dixRequestPrivate(&glamor_pixmap_index, 0)) #endif return FALSE; if (info->shadow_primary) radeon_glamor_screen_init(screen); #if defined(RENDER) && defined(HAVE_FBGLYPHS) /* For ShadowPrimary, we need fbUnrealizeGlyph instead of * glamor_unrealize_glyph */ if (ps) ps->UnrealizeGlyph = SavedUnrealizeGlyph; #endif screen->CreatePixmap = radeon_glamor_create_pixmap; screen->DestroyPixmap = radeon_glamor_destroy_pixmap; #ifdef RADEON_PIXMAP_SHARING screen->SharePixmapBacking = radeon_glamor_share_pixmap_backing; screen->SetSharedPixmapBacking = radeon_glamor_set_shared_pixmap_backing; #endif xf86DrvMsg(scrn->scrnIndex, X_INFO, "Use GLAMOR acceleration.\n"); return TRUE; } XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return glamor_xv_init(pScreen, num_adapt); } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_glamor.h000066400000000000000000000064021256524674500232610ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation. * 2012 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef RADEON_GLAMOR_H #define RADEON_GLAMOR_H #include "xf86xv.h" struct radeon_pixmap; #ifdef USE_GLAMOR #define GLAMOR_FOR_XORG 1 #include #include "radeon_surface.h" #ifndef CREATE_PIXMAP_USAGE_SHARED #define CREATE_PIXMAP_USAGE_SHARED RADEON_CREATE_PIXMAP_DRI2 #endif #define RADEON_CREATE_PIXMAP_SHARED(usage) \ (((usage) & ~RADEON_CREATE_PIXMAP_TILING_FLAGS) == RADEON_CREATE_PIXMAP_DRI2 || \ (usage) == CREATE_PIXMAP_USAGE_SHARED) #ifndef GLAMOR_NO_DRI3 #define GLAMOR_NO_DRI3 0 #define glamor_fd_from_pixmap glamor_dri3_fd_from_pixmap #define glamor_pixmap_from_fd glamor_egl_dri3_pixmap_from_fd #endif #ifndef GLAMOR_INVERTED_Y_AXIS #define GLAMOR_INVERTED_Y_AXIS 0 #endif #ifndef GLAMOR_USE_SCREEN #define GLAMOR_USE_SCREEN 0 #endif #ifndef GLAMOR_USE_PICTURE_SCREEN #define GLAMOR_USE_PICTURE_SCREEN 0 #endif Bool radeon_glamor_pre_init(ScrnInfoPtr scrn); Bool radeon_glamor_init(ScreenPtr screen); void radeon_glamor_screen_init(ScreenPtr screen); Bool radeon_glamor_create_screen_resources(ScreenPtr screen); void radeon_glamor_free_screen(int scrnIndex, int flags); Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv); void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst); XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt); #else static inline Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { return FALSE; } static inline Bool radeon_glamor_init(ScreenPtr screen) { return FALSE; } static inline Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { return FALSE; } static inline void radeon_glamor_free_screen(int scrnIndex, int flags) { } static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv) { return TRUE; } static inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {} static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; } static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; } #endif #endif /* RADEON_GLAMOR_H */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_glamor_wrappers.c000066400000000000000000000707121256524674500252040ustar00rootroot00000000000000/* * Copyright © 2001 Keith Packard * 2010 Intel Corporation * 2012,2015 Advanced Micro Devices, Inc. * * Partly based on code Copyright © 2008 Red Hat, Inc. * Partly based on code Copyright © 2000 SuSE, Inc. * * Partly based on code that is Copyright © The XFree86 Project Inc. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that * copyright notice and this permission notice appear in supporting * documentation, and that the name of the opyright holders not be used in * advertising or publicity pertaining to distribution of the software without * specific, written prior permission. The copyright holders make no * representations about the suitability of this software for any purpose. It * is provided "as is" without express or implied warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifdef HAVE_CONFIG_H #include #endif #ifdef USE_GLAMOR #include "radeon.h" #include "radeon_glamor.h" /** * get_drawable_pixmap() returns the backing pixmap for a given drawable. * * @param pDrawable the drawable being requested. * * This function returns the backing pixmap for a drawable, whether it is a * redirected window, unredirected window, or already a pixmap. */ static PixmapPtr get_drawable_pixmap(DrawablePtr pDrawable) { if (pDrawable->type == DRAWABLE_WINDOW) return pDrawable->pScreen-> GetWindowPixmap((WindowPtr) pDrawable); else return (PixmapPtr) pDrawable; } /* Are there any outstanding GPU operations for this pixmap? */ static Bool radeon_glamor_gpu_pending(uint_fast32_t gpu_synced, uint_fast32_t gpu_access) { return (int_fast32_t)(gpu_access - gpu_synced) > 0; } /* * Pixmap CPU access wrappers */ static Bool radeon_glamor_prepare_access_cpu(ScrnInfoPtr scrn, RADEONInfoPtr info, PixmapPtr pixmap, struct radeon_pixmap *priv, Bool need_sync) { struct radeon_bo *bo = priv->bo; int ret; /* When falling back to swrast, flush all pending operations */ if (need_sync) { glamor_block_handler(scrn->pScreen); info->gpu_flushed++; } if (!pixmap->devPrivate.ptr) { ret = radeon_bo_map(bo, 1); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "%s: bo map (tiling_flags %d) failed: %s\n", __FUNCTION__, priv->tiling_flags, strerror(-ret)); return FALSE; } pixmap->devPrivate.ptr = bo->ptr; info->gpu_synced = info->gpu_flushed; } else if (need_sync) { radeon_bo_wait(bo); info->gpu_synced = info->gpu_flushed; } return TRUE; } static Bool radeon_glamor_prepare_access_cpu_ro(ScrnInfoPtr scrn, PixmapPtr pixmap, struct radeon_pixmap *priv) { RADEONInfoPtr info; Bool need_sync; if (!priv) return TRUE; info = RADEONPTR(scrn); need_sync = radeon_glamor_gpu_pending(info->gpu_synced, priv->gpu_write); return radeon_glamor_prepare_access_cpu(scrn, RADEONPTR(scrn), pixmap, priv, need_sync); } static Bool radeon_glamor_prepare_access_cpu_rw(ScrnInfoPtr scrn, PixmapPtr pixmap, struct radeon_pixmap *priv) { RADEONInfoPtr info; uint_fast32_t gpu_synced; Bool need_sync; if (!priv) return TRUE; info = RADEONPTR(scrn); gpu_synced = info->gpu_synced; need_sync = radeon_glamor_gpu_pending(gpu_synced, priv->gpu_write) | radeon_glamor_gpu_pending(gpu_synced, priv->gpu_read); return radeon_glamor_prepare_access_cpu(scrn, info, pixmap, priv, need_sync); } static void radeon_glamor_finish_access_cpu(PixmapPtr pixmap) { /* Nothing to do */ } /* * Pixmap GPU access wrappers */ static Bool radeon_glamor_prepare_access_gpu(struct radeon_pixmap *priv) { return priv != NULL; } static void radeon_glamor_finish_access_gpu_ro(RADEONInfoPtr info, struct radeon_pixmap *priv) { priv->gpu_read = info->gpu_flushed + 1; } static void radeon_glamor_finish_access_gpu_rw(RADEONInfoPtr info, struct radeon_pixmap *priv) { priv->gpu_write = priv->gpu_read = info->gpu_flushed + 1; } /* * GC CPU access wrappers */ static Bool radeon_glamor_prepare_access_gc(ScrnInfoPtr scrn, GCPtr pGC) { struct radeon_pixmap *priv; if (pGC->stipple) { priv = radeon_get_pixmap_private(pGC->stipple); if (!radeon_glamor_prepare_access_cpu_ro(scrn, pGC->stipple, priv)) return FALSE; } if (pGC->fillStyle == FillTiled) { priv = radeon_get_pixmap_private(pGC->tile.pixmap); if (!radeon_glamor_prepare_access_cpu_ro(scrn, pGC->tile.pixmap, priv)) { if (pGC->stipple) radeon_glamor_finish_access_cpu(pGC->stipple); return FALSE; } } return TRUE; } static void radeon_glamor_finish_access_gc(GCPtr pGC) { if (pGC->fillStyle == FillTiled) radeon_glamor_finish_access_cpu(pGC->tile.pixmap); if (pGC->stipple) radeon_glamor_finish_access_cpu(pGC->stipple); } /* * Picture CPU access wrappers */ static void radeon_glamor_picture_finish_access_cpu(PicturePtr picture) { /* Nothing to do */ } static Bool radeon_glamor_picture_prepare_access_cpu_ro(ScrnInfoPtr scrn, PicturePtr picture) { PixmapPtr pixmap; struct radeon_pixmap *priv; if (picture->pDrawable == NULL) return TRUE; pixmap = get_drawable_pixmap(picture->pDrawable); priv = radeon_get_pixmap_private(pixmap); if (!radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) return FALSE; if (picture->alphaMap) { pixmap = get_drawable_pixmap(picture->alphaMap->pDrawable); priv = radeon_get_pixmap_private(pixmap); if (!radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) { radeon_glamor_picture_finish_access_cpu(picture); return FALSE; } } return TRUE; } static Bool radeon_glamor_picture_prepare_access_cpu_rw(ScrnInfoPtr scrn, PicturePtr picture) { PixmapPtr pixmap; struct radeon_pixmap *priv; pixmap = get_drawable_pixmap(picture->pDrawable); priv = radeon_get_pixmap_private(pixmap); if (!radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) return FALSE; if (picture->alphaMap) { pixmap = get_drawable_pixmap(picture->alphaMap->pDrawable); priv = radeon_get_pixmap_private(pixmap); if (!radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { radeon_glamor_picture_finish_access_cpu(picture); return FALSE; } } return TRUE; } /* * GC rendering wrappers */ static void radeon_glamor_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int nspans, DDXPointPtr ppt, int *pwidth, int fSorted) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbFillSpans(pDrawable, pGC, nspans, ppt, pwidth, fSorted); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_set_spans(DrawablePtr pDrawable, GCPtr pGC, char *psrc, DDXPointPtr ppt, int *pwidth, int nspans, int fSorted) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { fbSetSpans(pDrawable, pGC, psrc, ppt, pwidth, nspans, fSorted); radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_put_image(DrawablePtr pDrawable, GCPtr pGC, int depth, int x, int y, int w, int h, int leftPad, int format, char *bits) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { fbPutImage(pDrawable, pGC, depth, x, y, w, h, leftPad, format, bits); radeon_glamor_finish_access_cpu(pixmap); } } static RegionPtr radeon_glamor_copy_plane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, int srcx, int srcy, int w, int h, int dstx, int dsty, unsigned long bitPlane) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pScreen); PixmapPtr dst_pix = get_drawable_pixmap(pDst); struct radeon_pixmap *dst_priv = radeon_get_pixmap_private(dst_pix); RegionPtr ret = NULL; if (radeon_glamor_prepare_access_cpu_rw(scrn, dst_pix, dst_priv)) { PixmapPtr src_pix = get_drawable_pixmap(pSrc); struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pix); if (radeon_glamor_prepare_access_cpu_ro(scrn, src_pix, src_priv)) { ret = fbCopyPlane(pSrc, pDst, pGC, srcx, srcy, w, h, dstx, dsty, bitPlane); radeon_glamor_finish_access_cpu(src_pix); } radeon_glamor_finish_access_cpu(dst_pix); } return ret; } static RegionPtr radeon_glamor_copy_plane_nodstbo(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, int srcx, int srcy, int w, int h, int dstx, int dsty, unsigned long bitPlane) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pScreen); PixmapPtr src_pix = get_drawable_pixmap(pSrc); struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pix); RegionPtr ret = NULL; if (radeon_glamor_prepare_access_cpu_ro(scrn, src_pix, src_priv)) { ret = fbCopyPlane(pSrc, pDst, pGC, srcx, srcy, w, h, dstx, dsty, bitPlane); radeon_glamor_finish_access_cpu(src_pix); } return ret; } static void radeon_glamor_poly_point(DrawablePtr pDrawable, GCPtr pGC, int mode, int npt, DDXPointPtr pptInit) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { fbPolyPoint(pDrawable, pGC, mode, npt, pptInit); radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_poly_lines(DrawablePtr pDrawable, GCPtr pGC, int mode, int npt, DDXPointPtr ppt) { if (pGC->lineWidth == 0) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbPolyLine(pDrawable, pGC, mode, npt, ppt); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } return; } /* fb calls mi functions in the lineWidth != 0 case. */ fbPolyLine(pDrawable, pGC, mode, npt, ppt); } static void radeon_glamor_poly_segment(DrawablePtr pDrawable, GCPtr pGC, int nsegInit, xSegment *pSegInit) { if (pGC->lineWidth == 0) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbPolySegment(pDrawable, pGC, nsegInit, pSegInit); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } return; } /* fb calls mi functions in the lineWidth != 0 case. */ fbPolySegment(pDrawable, pGC, nsegInit, pSegInit); } static void radeon_glamor_poly_fill_rect(DrawablePtr pDrawable, GCPtr pGC, int nrect, xRectangle *prect) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); RADEONInfoPtr info = RADEONPTR(scrn); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if ((info->accel_state->force || (priv && !priv->bo)) && radeon_glamor_prepare_access_gpu(priv)) { info->glamor.SavedPolyFillRect(pDrawable, pGC, nrect, prect); radeon_glamor_finish_access_gpu_rw(info, priv); return; } if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbPolyFillRect(pDrawable, pGC, nrect, prect); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_image_glyph_blt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, unsigned int nglyph, CharInfoPtr *ppci, pointer pglyphBase) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbImageGlyphBlt(pDrawable, pGC, x, y, nglyph, ppci, pglyphBase); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_poly_glyph_blt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, unsigned int nglyph, CharInfoPtr *ppci, pointer pglyphBase) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbPolyGlyphBlt(pDrawable, pGC, x, y, nglyph, ppci, pglyphBase); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_push_pixels(GCPtr pGC, PixmapPtr pBitmap, DrawablePtr pDrawable, int w, int h, int x, int y) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { priv = radeon_get_pixmap_private(pBitmap); if (radeon_glamor_prepare_access_cpu_ro(scrn, pBitmap, priv)) { if (radeon_glamor_prepare_access_gc(scrn, pGC)) { fbPushPixels(pGC, pBitmap, pDrawable, w, h, x, y); radeon_glamor_finish_access_gc(pGC); } radeon_glamor_finish_access_cpu(pBitmap); } radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_push_pixels_nodstbo(GCPtr pGC, PixmapPtr pBitmap, DrawablePtr pDrawable, int w, int h, int x, int y) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); struct radeon_pixmap *priv = radeon_get_pixmap_private(pBitmap); if (radeon_glamor_prepare_access_cpu_ro(scrn, pBitmap, priv)) { fbPushPixels(pGC, pBitmap, pDrawable, w, h, x, y); radeon_glamor_finish_access_cpu(pBitmap); } } static RegionPtr radeon_glamor_copy_area(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable, GCPtr pGC, int srcx, int srcy, int width, int height, int dstx, int dsty) { ScreenPtr screen = pDstDrawable->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); PixmapPtr src_pixmap = get_drawable_pixmap(pSrcDrawable); PixmapPtr dst_pixmap = get_drawable_pixmap(pDstDrawable); struct radeon_pixmap *src_priv = radeon_get_pixmap_private(src_pixmap); struct radeon_pixmap *dst_priv = radeon_get_pixmap_private(dst_pixmap); RegionPtr ret = NULL; if (info->accel_state->force || (src_priv && !src_priv->bo) || (dst_priv && !dst_priv->bo)) { if (!radeon_glamor_prepare_access_gpu(dst_priv)) goto fallback; if (src_priv != dst_priv && !radeon_glamor_prepare_access_gpu(src_priv)) goto fallback; ret = info->glamor.SavedCopyArea(pSrcDrawable, pDstDrawable, pGC, srcx, srcy, width, height, dstx, dsty); radeon_glamor_finish_access_gpu_rw(info, dst_priv); if (src_priv != dst_priv) radeon_glamor_finish_access_gpu_ro(info, src_priv); return ret; } fallback: if (radeon_glamor_prepare_access_cpu_rw(scrn, dst_pixmap, dst_priv)) { if (pSrcDrawable == pDstDrawable || radeon_glamor_prepare_access_cpu_ro(scrn, src_pixmap, src_priv)) { ret = fbCopyArea(pSrcDrawable, pDstDrawable, pGC, srcx, srcy, width, height, dstx, dsty); if (pSrcDrawable != pDstDrawable) radeon_glamor_finish_access_cpu(src_pixmap); } radeon_glamor_finish_access_cpu(dst_pixmap); } return ret; } static RegionPtr radeon_glamor_copy_area_nodstbo(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable, GCPtr pGC, int srcx, int srcy, int width, int height, int dstx, int dsty) { ScreenPtr screen = pDstDrawable->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); PixmapPtr src_pixmap = get_drawable_pixmap(pSrcDrawable); PixmapPtr dst_pixmap = get_drawable_pixmap(pDstDrawable); struct radeon_pixmap *src_priv; RegionPtr ret = NULL; if (src_pixmap != dst_pixmap) { src_priv = radeon_get_pixmap_private(src_pixmap); if (!radeon_glamor_prepare_access_cpu_ro(scrn, src_pixmap, src_priv)) return ret; } ret = fbCopyArea(pSrcDrawable, pDstDrawable, pGC, srcx, srcy, width, height, dstx, dsty); if (src_pixmap != dst_pixmap) radeon_glamor_finish_access_cpu(src_pixmap); return ret; } static const GCOps radeon_glamor_ops = { radeon_glamor_fill_spans, radeon_glamor_set_spans, radeon_glamor_put_image, radeon_glamor_copy_area, radeon_glamor_copy_plane, radeon_glamor_poly_point, radeon_glamor_poly_lines, radeon_glamor_poly_segment, miPolyRectangle, miPolyArc, miFillPolygon, radeon_glamor_poly_fill_rect, miPolyFillArc, miPolyText8, miPolyText16, miImageText8, miImageText16, radeon_glamor_image_glyph_blt, radeon_glamor_poly_glyph_blt, radeon_glamor_push_pixels, }; static GCOps radeon_glamor_nodstbo_ops; /** * radeon_glamor_validate_gc() sets the ops to our implementations, which may be * accelerated or may sync the card and fall back to fb. */ static void radeon_glamor_validate_gc(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable) { ScrnInfoPtr scrn = xf86ScreenToScrn(pGC->pScreen); RADEONInfoPtr info = RADEONPTR(scrn); glamor_validate_gc(pGC, changes, pDrawable); info->glamor.SavedCopyArea = pGC->ops->CopyArea; info->glamor.SavedPolyFillRect = pGC->ops->PolyFillRect; if (radeon_get_pixmap_private(get_drawable_pixmap(pDrawable)) || (pGC->stipple && radeon_get_pixmap_private(pGC->stipple)) || (pGC->fillStyle == FillTiled && radeon_get_pixmap_private(pGC->tile.pixmap))) pGC->ops = (GCOps *)&radeon_glamor_ops; else pGC->ops = &radeon_glamor_nodstbo_ops; } static GCFuncs glamorGCFuncs = { radeon_glamor_validate_gc, miChangeGC, miCopyGC, miDestroyGC, miChangeClip, miDestroyClip, miCopyClip }; /** * radeon_glamor_create_gc makes a new GC and hooks up its funcs handler, so that * radeon_glamor_validate_gc() will get called. */ static int radeon_glamor_create_gc(GCPtr pGC) { static Bool nodstbo_ops_initialized; if (!fbCreateGC(pGC)) return FALSE; if (!nodstbo_ops_initialized) { radeon_glamor_nodstbo_ops = radeon_glamor_ops; radeon_glamor_nodstbo_ops.FillSpans = pGC->ops->FillSpans; radeon_glamor_nodstbo_ops.SetSpans = pGC->ops->SetSpans; radeon_glamor_nodstbo_ops.PutImage = pGC->ops->PutImage; radeon_glamor_nodstbo_ops.CopyArea = radeon_glamor_copy_area_nodstbo; radeon_glamor_nodstbo_ops.CopyPlane = radeon_glamor_copy_plane_nodstbo; radeon_glamor_nodstbo_ops.PolyPoint = pGC->ops->PolyPoint; radeon_glamor_nodstbo_ops.Polylines = pGC->ops->Polylines; radeon_glamor_nodstbo_ops.PolySegment = pGC->ops->PolySegment; radeon_glamor_nodstbo_ops.PolyFillRect = pGC->ops->PolyFillRect; radeon_glamor_nodstbo_ops.ImageGlyphBlt = pGC->ops->ImageGlyphBlt; radeon_glamor_nodstbo_ops.PolyGlyphBlt = pGC->ops->PolyGlyphBlt; radeon_glamor_nodstbo_ops.PushPixels = radeon_glamor_push_pixels_nodstbo; nodstbo_ops_initialized = TRUE; } pGC->funcs = &glamorGCFuncs; return TRUE; } /* * Screen rendering wrappers */ static RegionPtr radeon_glamor_bitmap_to_region(PixmapPtr pPix) { ScrnInfoPtr scrn = xf86ScreenToScrn(pPix->drawable.pScreen); struct radeon_pixmap *priv = radeon_get_pixmap_private(pPix); RegionPtr ret; if (!radeon_glamor_prepare_access_cpu_ro(scrn, pPix, priv)) return NULL; ret = fbPixmapToRegion(pPix); radeon_glamor_finish_access_cpu(pPix); return ret; } static void radeon_glamor_copy_window(WindowPtr pWin, DDXPointRec ptOldOrg, RegionPtr prgnSrc) { ScrnInfoPtr scrn = xf86ScreenToScrn(pWin->drawable.pScreen); PixmapPtr pixmap = get_drawable_pixmap(&pWin->drawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_rw(scrn, pixmap, priv)) { fbCopyWindow(pWin, ptOldOrg, prgnSrc); radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_get_image(DrawablePtr pDrawable, int x, int y, int w, int h, unsigned int format, unsigned long planeMask, char *d) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) { fbGetImage(pDrawable, x, y, w, h, format, planeMask, d); radeon_glamor_finish_access_cpu(pixmap); } } static void radeon_glamor_get_spans(DrawablePtr pDrawable, int wMax, DDXPointPtr ppt, int *pwidth, int nspans, char *pdstStart) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDrawable->pScreen); PixmapPtr pixmap = get_drawable_pixmap(pDrawable); struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap); if (radeon_glamor_prepare_access_cpu_ro(scrn, pixmap, priv)) { fbGetSpans(pDrawable, wMax, ppt, pwidth, nspans, pdstStart); radeon_glamor_finish_access_cpu(pixmap); } } /* * Picture screen rendering wrappers */ #ifdef RENDER static void radeon_glamor_composite(CARD8 op, PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst, INT16 xSrc, INT16 ySrc, INT16 xMask, INT16 yMask, INT16 xDst, INT16 yDst, CARD16 width, CARD16 height) { ScrnInfoPtr scrn = xf86ScreenToScrn(pDst->pDrawable->pScreen); RADEONInfoPtr info; PixmapPtr pixmap; struct radeon_pixmap *dst_priv, *src_priv = NULL, *mask_priv = NULL; Bool gpu_done = FALSE; if (pDst->alphaMap || pSrc->alphaMap || (pMask && pMask->alphaMap)) goto fallback; pixmap = get_drawable_pixmap(pDst->pDrawable); if (&pixmap->drawable != pDst->pDrawable || pixmap->usage_hint != RADEON_CREATE_PIXMAP_SCANOUT) goto fallback; dst_priv = radeon_get_pixmap_private(pixmap); if (!radeon_glamor_prepare_access_gpu(dst_priv)) goto fallback; info = RADEONPTR(scrn); if (!pSrc->pDrawable || ((pixmap = get_drawable_pixmap(pSrc->pDrawable)) && (src_priv = radeon_get_pixmap_private(pixmap)) && radeon_glamor_prepare_access_gpu(src_priv))) { if (!pMask || !pMask->pDrawable || ((pixmap = get_drawable_pixmap(pMask->pDrawable)) && (mask_priv = radeon_get_pixmap_private(pixmap)) && radeon_glamor_prepare_access_gpu(mask_priv))) { info->glamor.SavedComposite(op, pSrc, pMask, pDst, xSrc, ySrc, xMask, yMask, xDst, yDst, width, height); gpu_done = TRUE; if (mask_priv) radeon_glamor_finish_access_gpu_ro(info, mask_priv); } if (src_priv) radeon_glamor_finish_access_gpu_ro(info, src_priv); } radeon_glamor_finish_access_gpu_rw(info, dst_priv); if (gpu_done) return; fallback: if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, pDst)) { if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, pSrc)) { if (!pMask || radeon_glamor_picture_prepare_access_cpu_ro(scrn, pMask)) { fbComposite(op, pSrc, pMask, pDst, xSrc, ySrc, xMask, yMask, xDst, yDst, width, height); if (pMask) radeon_glamor_picture_finish_access_cpu(pMask); } radeon_glamor_picture_finish_access_cpu(pSrc); } radeon_glamor_picture_finish_access_cpu(pDst); } } static void radeon_glamor_add_traps(PicturePtr pPicture, INT16 x_off, INT16 y_off, int ntrap, xTrap *traps) { ScrnInfoPtr scrn = xf86ScreenToScrn(pPicture->pDrawable->pScreen); if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, pPicture)) { fbAddTraps(pPicture, x_off, y_off, ntrap, traps); radeon_glamor_picture_finish_access_cpu(pPicture); } } static void radeon_glamor_glyphs(CARD8 op, PicturePtr src, PicturePtr dst, PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc, int nlist, GlyphListPtr list, GlyphPtr *glyphs) { ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen); if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) { if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) { RADEONInfoPtr info = RADEONPTR(scrn); info->glamor.SavedGlyphs(op, src, dst, maskFormat, xSrc, ySrc, nlist, list, glyphs); radeon_glamor_picture_finish_access_cpu(src); } radeon_glamor_picture_finish_access_cpu(dst); } } static void radeon_glamor_trapezoids(CARD8 op, PicturePtr src, PicturePtr dst, PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc, int ntrap, xTrapezoid *traps) { ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen); if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) { if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) { RADEONInfoPtr info = RADEONPTR(scrn); info->glamor.SavedTrapezoids(op, src, dst, maskFormat, xSrc, ySrc, ntrap, traps); radeon_glamor_picture_finish_access_cpu(src); } radeon_glamor_picture_finish_access_cpu(dst); } } static void radeon_glamor_triangles(CARD8 op, PicturePtr src, PicturePtr dst, PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc, int ntri, xTriangle *tri) { ScrnInfoPtr scrn = xf86ScreenToScrn(dst->pDrawable->pScreen); if (radeon_glamor_picture_prepare_access_cpu_rw(scrn, dst)) { if (radeon_glamor_picture_prepare_access_cpu_ro(scrn, src)) { RADEONInfoPtr info = RADEONPTR(scrn); info->glamor.SavedTriangles(op, src, dst, maskFormat, xSrc, ySrc, ntri, tri); radeon_glamor_picture_finish_access_cpu(src); } radeon_glamor_picture_finish_access_cpu(dst); } } #endif /* RENDER */ /** * radeon_glamor_close_screen() unwraps its wrapped screen functions and tears * down our screen private, before calling down to the next CloseScreen. */ static Bool radeon_glamor_close_screen(CLOSE_SCREEN_ARGS_DECL) { RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pScreen)); #ifdef RENDER PictureScreenPtr ps = GetPictureScreenIfSet(pScreen); #endif pScreen->CreateGC = info->glamor.SavedCreateGC; pScreen->CloseScreen = info->glamor.SavedCloseScreen; pScreen->GetImage = info->glamor.SavedGetImage; pScreen->GetSpans = info->glamor.SavedGetSpans; pScreen->CreatePixmap = info->glamor.SavedCreatePixmap; pScreen->DestroyPixmap = info->glamor.SavedDestroyPixmap; pScreen->CopyWindow = info->glamor.SavedCopyWindow; pScreen->ChangeWindowAttributes = info->glamor.SavedChangeWindowAttributes; pScreen->BitmapToRegion = info->glamor.SavedBitmapToRegion; #ifdef RENDER if (ps) { ps->Composite = info->glamor.SavedComposite; ps->Glyphs = info->glamor.SavedGlyphs; ps->UnrealizeGlyph = info->glamor.SavedUnrealizeGlyph; ps->Trapezoids = info->glamor.SavedTrapezoids; ps->AddTraps = info->glamor.SavedAddTraps; ps->Triangles = info->glamor.SavedTriangles; ps->UnrealizeGlyph = info->glamor.SavedUnrealizeGlyph; } #endif return (*pScreen->CloseScreen) (CLOSE_SCREEN_ARGS); } /** * @param screen screen being initialized */ void radeon_glamor_screen_init(ScreenPtr screen) { RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen)); /* * Replace various fb screen functions */ info->glamor.SavedCloseScreen = screen->CloseScreen; screen->CloseScreen = radeon_glamor_close_screen; info->glamor.SavedCreateGC = screen->CreateGC; screen->CreateGC = radeon_glamor_create_gc; info->glamor.SavedGetImage = screen->GetImage; screen->GetImage = radeon_glamor_get_image; info->glamor.SavedGetSpans = screen->GetSpans; screen->GetSpans = radeon_glamor_get_spans; info->glamor.SavedCreatePixmap = screen->CreatePixmap; info->glamor.SavedDestroyPixmap = screen->DestroyPixmap; info->glamor.SavedCopyWindow = screen->CopyWindow; screen->CopyWindow = radeon_glamor_copy_window; info->glamor.SavedBitmapToRegion = screen->BitmapToRegion; screen->BitmapToRegion = radeon_glamor_bitmap_to_region; #ifdef RENDER { PictureScreenPtr ps = GetPictureScreenIfSet(screen); if (ps) { info->glamor.SavedComposite = ps->Composite; ps->Composite = radeon_glamor_composite; info->glamor.SavedUnrealizeGlyph = ps->UnrealizeGlyph; ps->Glyphs = radeon_glamor_glyphs; ps->Triangles = radeon_glamor_triangles; ps->Trapezoids = radeon_glamor_trapezoids; info->glamor.SavedAddTraps = ps->AddTraps; ps->AddTraps = radeon_glamor_add_traps; } } #endif } #endif /* USE_GLAMOR */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_kms.c000066400000000000000000001634301256524674500225720ustar00rootroot00000000000000/* * Copyright © 2009 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include /* Driver data structures */ #include "radeon.h" #include "radeon_drm_queue.h" #include "radeon_glamor.h" #include "radeon_reg.h" #include "radeon_probe.h" #include "micmap.h" #include "radeon_version.h" #include "shadow.h" #include "atipciids.h" /* DPMS */ #ifdef HAVE_XEXTPROTO_71 #include #else #define DPMS_SERVER #include #endif #include "radeon_chipinfo_gen.h" #include "radeon_bo_gem.h" #include "radeon_cs_gem.h" #include "radeon_vbo.h" extern SymTabRec RADEONChipsets[]; static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); const OptionInfoRec RADEONOptions_KMS[] = { { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, #ifdef USE_GLAMOR { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE }, #endif { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE}, { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE }, { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE }, { -1, NULL, OPTV_NONE, {0}, FALSE } }; const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state; int ret; #ifdef USE_GLAMOR if (info->use_glamor) { glamor_block_handler(pScrn->pScreen); info->gpu_flushed++; return; } #endif if (!info->cs->cdw) return; accel_state = info->accel_state; /* release the current VBO so we don't block on mapping it later */ if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { radeon_vbo_put(pScrn, &info->accel_state->vbo); info->accel_state->vbo.vb_start_op = -1; } /* release the current VBO so we don't block on mapping it later */ if (info->accel_state->cbuf.vb_bo) { radeon_vbo_put(pScrn, &info->accel_state->cbuf); info->accel_state->cbuf.vb_start_op = -1; } radeon_cs_emit(info->cs); radeon_cs_erase(info->cs); if (accel_state->use_vbos) radeon_vbo_flush_bos(pScrn); ret = radeon_cs_space_check_with_bo(info->cs, accel_state->vbo.vb_bo, RADEON_GEM_DOMAIN_GTT, 0); if (ret) ErrorF("space check failed in flush\n"); if (info->reemit_current2d && info->state_2d.op) info->reemit_current2d(pScrn, info->state_2d.op); if (info->dri2.enabled) { info->accel_state->XInited3D = FALSE; info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; } } void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int n, const char *file, const char *func, int line) { RADEONInfoPtr info = RADEONPTR(pScrn); if (info->cs->cdw + n > info->cs->ndw) { radeon_cs_flush_indirect(pScrn); } radeon_cs_begin(info->cs, n, file, func, line); } extern _X_EXPORT int gRADEONEntityIndex; static int getRADEONEntityIndex(void) { return gRADEONEntityIndex; } RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) { DevUnion *pPriv; RADEONInfoPtr info = RADEONPTR(pScrn); pPriv = xf86GetEntityPrivate(info->pEnt->index, getRADEONEntityIndex()); return pPriv->ptr; } /* Allocate our private RADEONInfoRec */ static Bool RADEONGetRec(ScrnInfoPtr pScrn) { if (pScrn->driverPrivate) return TRUE; pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); return TRUE; } /* Free our private RADEONInfoRec */ static void RADEONFreeRec(ScrnInfoPtr pScrn) { RADEONInfoPtr info; if (!pScrn || !pScrn->driverPrivate) return; info = RADEONPTR(pScrn); if (info->fbcon_pixmap) pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); if (info->dri2.drm_fd > 0) { DevUnion *pPriv; RADEONEntPtr pRADEONEnt; pPriv = xf86GetEntityPrivate(pScrn->entityList[0], getRADEONEntityIndex()); pRADEONEnt = pPriv->ptr; pRADEONEnt->fd_ref--; if (!pRADEONEnt->fd_ref) { #ifdef XF86_PDEV_SERVER_FD if (!(pRADEONEnt->platform_dev && pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) #endif drmClose(pRADEONEnt->fd); pRADEONEnt->fd = 0; } } if (info->accel_state) { free(info->accel_state); info->accel_state = NULL; } free(pScrn->driverPrivate); pScrn->driverPrivate = NULL; } static void * radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, CARD32 *size, void *closure) { ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(pScrn); int stride; stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; return ((uint8_t *)info->front_bo->ptr + row * stride + offset); } static void radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) { shadowUpdatePacked(pScreen, pBuf); } static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pixmap; struct radeon_surface *surface; pScreen->CreateScreenResources = info->CreateScreenResources; if (!(*pScreen->CreateScreenResources)(pScreen)) return FALSE; pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; if (!drmmode_set_desired_modes(pScrn, &info->drmmode, FALSE)) return FALSE; drmmode_uevent_init(pScrn, &info->drmmode); if (info->r600_shadow_fb) { pixmap = pScreen->GetScreenPixmap(pScreen); if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, radeonShadowWindow, 0, NULL)) return FALSE; } if (info->dri2.enabled || info->use_glamor) { if (info->front_bo) { PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); radeon_set_pixmap_bo(pPix, info->front_bo); surface = radeon_get_pixmap_surface(pPix); if (surface) { *surface = info->front_surface; } } } if (info->use_glamor) radeon_glamor_create_screen_resources(pScreen); return TRUE; } #ifdef RADEON_PIXMAP_SHARING static void redisplay_dirty(ScreenPtr screen, PixmapDirtyUpdatePtr dirty) { ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); RegionRec pixregion; PixmapRegionInit(&pixregion, dirty->slave_dst); DamageRegionAppend(&dirty->slave_dst->drawable, &pixregion); #ifdef HAS_DIRTYTRACKING_ROTATION PixmapSyncDirtyHelper(dirty); #else PixmapSyncDirtyHelper(dirty, &pixregion); #endif radeon_cs_flush_indirect(pScrn); DamageRegionProcessPending(&dirty->slave_dst->drawable); RegionUninit(&pixregion); } static void radeon_dirty_update(ScreenPtr screen) { RegionPtr region; PixmapDirtyUpdatePtr ent; if (xorg_list_is_empty(&screen->pixmap_dirty_list)) return; xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { region = DamageRegion(ent->damage); if (RegionNotEmpty(region)) { redisplay_dirty(screen, ent); DamageEmpty(ent->damage); } } } #endif static Bool radeon_scanout_extents_intersect(BoxPtr extents, int x, int y, int w, int h) { extents->x1 = max(extents->x1 - x, 0); extents->y1 = max(extents->y1 - y, 0); extents->x2 = min(extents->x2 - x, w); extents->y2 = min(extents->y2 - y, h); return (extents->x1 < extents->x2 && extents->y1 < extents->y2); } static Bool radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id) { drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; ScrnInfoPtr scrn; DamagePtr pDamage; RegionPtr pRegion; DrawablePtr pDraw; ScreenPtr pScreen; GCPtr gc; BoxRec extents; RADEONInfoPtr info; Bool force; if (!xf86_crtc->enabled || drmmode_crtc->dpms_mode != DPMSModeOn || !drmmode_crtc->scanout[scanout_id].pixmap) return FALSE; pDamage = drmmode_crtc->scanout[scanout_id].damage; if (!pDamage) return FALSE; pRegion = DamageRegion(pDamage); if (!RegionNotEmpty(pRegion)) return FALSE; pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; extents = *RegionExtents(pRegion); RegionEmpty(pRegion); if (!radeon_scanout_extents_intersect(&extents, xf86_crtc->x, xf86_crtc->y, pDraw->width, pDraw->height)) return FALSE; pScreen = pDraw->pScreen; gc = GetScratchGC(pDraw->depth, pScreen); scrn = xf86_crtc->scrn; info = RADEONPTR(scrn); force = info->accel_state->force; info->accel_state->force = TRUE; ValidateGC(pDraw, gc); (*gc->ops->CopyArea)(&pScreen->GetScreenPixmap(pScreen)->drawable, pDraw, gc, xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1, extents.x2 - extents.x1, extents.y2 - extents.y1, extents.x1, extents.y1); FreeScratchGC(gc); info->accel_state->force = force; radeon_cs_flush_indirect(scrn); return TRUE; } static void radeon_scanout_update_abort(ScrnInfoPtr scrn, void *event_data) { xf86CrtcPtr xf86_crtc = event_data; drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; drmmode_crtc->scanout_update_pending = FALSE; } void radeon_scanout_update_handler(ScrnInfoPtr scrn, uint32_t frame, uint64_t usec, void *event_data) { radeon_scanout_do_update(event_data, 0); radeon_scanout_update_abort(scrn, event_data); } static void radeon_scanout_update(xf86CrtcPtr xf86_crtc) { drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; struct radeon_drm_queue_entry *drm_queue_entry; ScrnInfoPtr scrn; drmVBlank vbl; DamagePtr pDamage; RegionPtr pRegion; DrawablePtr pDraw; BoxRec extents; if (!xf86_crtc->enabled || drmmode_crtc->scanout_update_pending || !drmmode_crtc->scanout[0].pixmap || drmmode_crtc->dpms_mode != DPMSModeOn) return; pDamage = drmmode_crtc->scanout[0].damage; if (!pDamage) return; pRegion = DamageRegion(pDamage); if (!RegionNotEmpty(pRegion)) return; pDraw = &drmmode_crtc->scanout[0].pixmap->drawable; extents = *RegionExtents(pRegion); if (!radeon_scanout_extents_intersect(&extents, xf86_crtc->x, xf86_crtc->y, pDraw->width, pDraw->height)) return; scrn = xf86_crtc->scrn; drm_queue_entry = radeon_drm_queue_alloc(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, RADEON_DRM_QUEUE_ID_DEFAULT, xf86_crtc, radeon_scanout_update_handler, radeon_scanout_update_abort); if (!drm_queue_entry) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "radeon_drm_queue_alloc failed for scanout update\n"); return; } vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT; vbl.request.type |= radeon_populate_vbl_request_type(xf86_crtc); vbl.request.sequence = 1; vbl.request.signal = (unsigned long)drm_queue_entry; if (drmWaitVBlank(RADEONPTR(scrn)->dri2.drm_fd, &vbl)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "drmWaitVBlank failed for scanout update: %s\n", strerror(errno)); radeon_drm_abort_entry(drm_queue_entry); return; } drmmode_crtc->scanout_update_pending = TRUE; } static void radeon_scanout_flip_abort(ScrnInfoPtr scrn, void *event_data) { drmmode_crtc_private_ptr drmmode_crtc = event_data; drmmode_crtc->scanout_update_pending = FALSE; } static void radeon_scanout_flip_handler(ScrnInfoPtr scrn, uint32_t frame, uint64_t usec, void *event_data) { radeon_scanout_flip_abort(scrn, event_data); } static void radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info, xf86CrtcPtr xf86_crtc) { drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; ScrnInfoPtr scrn; struct radeon_drm_queue_entry *drm_queue_entry; unsigned scanout_id; if (drmmode_crtc->scanout_update_pending) return; scanout_id = drmmode_crtc->scanout_id ^ 1; if (!radeon_scanout_do_update(xf86_crtc, scanout_id)) return; scrn = xf86_crtc->scrn; drm_queue_entry = radeon_drm_queue_alloc(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, RADEON_DRM_QUEUE_ID_DEFAULT, drmmode_crtc, radeon_scanout_flip_handler, radeon_scanout_flip_abort); if (!drm_queue_entry) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Allocating DRM event queue entry failed.\n"); return; } if (drmModePageFlip(drmmode_crtc->drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, drmmode_crtc->scanout[scanout_id].fb_id, DRM_MODE_PAGE_FLIP_EVENT, drm_queue_entry)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in %s: %s\n", __func__, strerror(errno)); return; } drmmode_crtc->scanout_id = scanout_id; drmmode_crtc->scanout_update_pending = TRUE; } static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) { SCREEN_PTR(arg); ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); pScreen->BlockHandler = info->BlockHandler; (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); pScreen->BlockHandler = RADEONBlockHandler_KMS; if (info->tear_free || info->shadow_primary) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int c; for (c = 0; c < xf86_config->num_crtc; c++) { if (info->tear_free) radeon_scanout_flip(pScreen, info, xf86_config->crtc[c]); else radeon_scanout_update(xf86_config->crtc[c]); } } radeon_cs_flush_indirect(pScrn); #ifdef RADEON_PIXMAP_SHARING radeon_dirty_update(pScreen); #endif } static void RADEONBlockHandler_oneshot(BLOCKHANDLER_ARGS_DECL) { SCREEN_PTR(arg); ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS); } static void radeon_flush_callback(CallbackListPtr *list, pointer user_data, pointer call_data) { ScrnInfoPtr pScrn = user_data; if (pScrn->vtSema) radeon_cs_flush_indirect(pScrn); } static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info ginfo; int r; uint32_t tmp = 0; memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = RADEON_INFO_FASTFB_WORKING; ginfo.value = (uintptr_t)&tmp; r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { return FALSE; } if (tmp == 1) return TRUE; return FALSE; } static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info ginfo; int r; uint32_t tmp; memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = RADEON_INFO_FUSION_GART_WORKING; ginfo.value = (uintptr_t)&tmp; r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { return FALSE; } if (tmp == 1) return TRUE; return FALSE; } static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info ginfo; int r; uint32_t tmp; memset(&ginfo, 0, sizeof(ginfo)); if (info->dri2.pKernelDRMVersion->version_minor >= 5) ginfo.request = RADEON_INFO_ACCEL_WORKING2; else ginfo.request = RADEON_INFO_ACCEL_WORKING; ginfo.value = (uintptr_t)&tmp; r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { /* If kernel is too old before 2.6.32 than assume accel is working */ if (r == -EINVAL) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " "information, assuming accel is working\n"); return TRUE; } return FALSE; } if (info->ChipFamily == CHIP_FAMILY_HAWAII) { if (tmp == 2 || tmp == 3) return TRUE; } else if (tmp) { return TRUE; } return FALSE; } /* This is called by RADEONPreInit to set up the default visual */ static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) return FALSE; switch (pScrn->depth) { case 8: case 15: case 16: case 24: break; default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Given depth (%d) is not supported by %s driver\n", pScrn->depth, RADEON_DRIVER_NAME); return FALSE; } xf86PrintDepthBpp(pScrn); info->pix24bpp = xf86GetBppFromDepth(pScrn, pScrn->depth); info->pixel_bytes = pScrn->bitsPerPixel / 8; if (info->pix24bpp == 24) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Radeon does NOT support 24bpp\n"); return FALSE; } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", pScrn->depth, info->pixel_bytes, info->pixel_bytes > 1 ? "s" : "", info->pix24bpp); if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Default visual (%s) is not supported at depth %d\n", xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); return FALSE; } return TRUE; } /* This is called by RADEONPreInit to handle all color weight issues */ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); /* Save flag for 6 bit DAC to use for setting CRTC registers. Otherwise use an 8 bit DAC, even if xf86SetWeight sets pScrn->rgbBits to some value other than 8. */ info->dac6bits = FALSE; if (pScrn->depth > 8) { rgb defaultWeight = { 0, 0, 0 }; if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; } else { pScrn->rgbBits = 8; } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using %d bits per RGB (%d bit DAC)\n", pScrn->rgbBits, info->dac6bits ? 6 : 8); return TRUE; } static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); return FALSE; } /* Check whether direct mapping is used for fast fb access*/ if (RADEONIsFastFBWorking(pScrn)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); info->is_fast_fb = TRUE; } if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || (!RADEONIsAccelWorking(pScrn))) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "GPU accel disabled or not working, using shadowfb for KMS\n"); shadowfb: info->r600_shadow_fb = TRUE; if (!xf86LoadSubModule(pScrn, "shadow")) info->r600_shadow_fb = FALSE; return TRUE; } #ifdef DRI2 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); #endif if (radeon_glamor_pre_init(pScrn)) return TRUE; if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { goto shadowfb; } else if (info->ChipFamily == CHIP_FAMILY_PALM) { info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); } else info->accel_state->allowHWDFS = TRUE; if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_RS400) || (info->ChipFamily == CHIP_FAMILY_RS480) || (info->ChipFamily == CHIP_FAMILY_RS600) || (info->ChipFamily == CHIP_FAMILY_RS690) || (info->ChipFamily == CHIP_FAMILY_RS740)) info->accel_state->has_tcl = FALSE; else { info->accel_state->has_tcl = TRUE; } { int errmaj = 0, errmin = 0; info->exaReq.majorversion = EXA_VERSION_MAJOR; info->exaReq.minorversion = EXA_VERSION_MINOR; if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, &info->exaReq, &errmaj, &errmin)) { LoaderErrorMsg(NULL, "exa", errmaj, errmin); return FALSE; } } return TRUE; } static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); int i; info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); if (!pScrn->chipset) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "ChipID 0x%04x is not recognized\n", info->Chipset); return FALSE; } if (info->Chipset < 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Chipset \"%s\" is not recognized\n", pScrn->chipset); return FALSE; } xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Chipset: \"%s\" (ChipID = 0x%04x)\n", pScrn->chipset, info->Chipset); for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { if (info->Chipset == RADEONCards[i].pci_device_id) { RADEONCardInfo *card = &RADEONCards[i]; info->ChipFamily = card->chip_family; break; } } #ifdef RENDER info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, info->Chipset != PCI_CHIP_RN50_515E && info->Chipset != PCI_CHIP_RN50_5969); #endif return TRUE; } static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86_PDEV_SERVER_FD RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); #endif struct pci_device *dev = info->PciInfo; char *busid; int fd; #ifdef XF86_PDEV_SERVER_FD if (pRADEONEnt->platform_dev) { fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, ODEV_ATTRIB_FD, -1); if (fd != -1) return fd; } #endif #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0) XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", dev->domain, dev->bus, dev->dev, dev->func); #else busid = XNFprintf("pci:%04x:%02x:%02x.%d", dev->domain, dev->bus, dev->dev, dev->func); #endif fd = drmOpen(NULL, busid); if (fd == -1) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] Failed to open DRM device for %s: %s\n", busid, strerror(errno)); free(busid); return fd; } static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); drmSetVersion sv; int err; if (pRADEONEnt->fd) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, " reusing fd for second head\n"); info->drmmode.fd = info->dri2.drm_fd = pRADEONEnt->fd; pRADEONEnt->fd_ref++; return TRUE; } info->dri2.drm_fd = radeon_get_drm_master_fd(pScrn); if (info->dri2.drm_fd == -1) return FALSE; /* Check that what we opened was a master or a master-capable FD, * by setting the version of the interface we'll use to talk to it. * (see DRIOpenDRMMaster() in DRI1) */ sv.drm_di_major = 1; sv.drm_di_minor = 1; sv.drm_dd_major = -1; sv.drm_dd_minor = -1; err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv); if (err != 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] failed to set drm interface version.\n"); drmClose(info->dri2.drm_fd); info->dri2.drm_fd = -1; return FALSE; } pRADEONEnt->fd = info->dri2.drm_fd; pRADEONEnt->fd_ref = 1; info->drmmode.fd = info->dri2.drm_fd; return TRUE; } static Bool r600_get_tile_config(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct drm_radeon_info ginfo; int r; uint32_t tmp; if (info->ChipFamily < CHIP_FAMILY_R600) return FALSE; memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = RADEON_INFO_TILING_CONFIG; ginfo.value = (uintptr_t)&tmp; r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) return FALSE; info->tile_config = tmp; info->r7xx_bank_op = 0; if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { if (info->dri2.pKernelDRMVersion->version_minor >= 7) { switch (info->tile_config & 0xf) { case 0: info->num_channels = 1; break; case 1: info->num_channels = 2; break; case 2: info->num_channels = 4; break; case 3: info->num_channels = 8; break; default: return FALSE; } switch((info->tile_config & 0xf0) >> 4) { case 0: info->num_banks = 4; break; case 1: info->num_banks = 8; break; case 2: info->num_banks = 16; break; default: return FALSE; } switch ((info->tile_config & 0xf00) >> 8) { case 0: info->group_bytes = 256; break; case 1: info->group_bytes = 512; break; default: return FALSE; } } else return FALSE; } else { switch((info->tile_config & 0xe) >> 1) { case 0: info->num_channels = 1; break; case 1: info->num_channels = 2; break; case 2: info->num_channels = 4; break; case 3: info->num_channels = 8; break; default: return FALSE; } switch((info->tile_config & 0x30) >> 4) { case 0: info->num_banks = 4; break; case 1: info->num_banks = 8; break; default: return FALSE; } switch((info->tile_config & 0xc0) >> 6) { case 0: info->group_bytes = 256; break; case 1: info->group_bytes = 512; break; default: return FALSE; } } info->have_tiling_info = TRUE; return TRUE; } static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) { #ifdef RADEON_PIXMAP_SHARING RADEONInfoPtr info = RADEONPTR(pScrn); uint64_t value; int ret; pScrn->capabilities = 0; ret = drmGetCap(info->dri2.drm_fd, DRM_CAP_PRIME, &value); if (ret == 0) { if (value & DRM_PRIME_CAP_EXPORT) { pScrn->capabilities |= RR_Capability_SourceOutput; if (!info->r600_shadow_fb && info->dri2.available) pScrn->capabilities |= RR_Capability_SinkOffload; } if (value & DRM_PRIME_CAP_IMPORT) { pScrn->capabilities |= RR_Capability_SinkOutput; if (!info->r600_shadow_fb && info->dri2.available) pScrn->capabilities |= RR_Capability_SourceOffload; } } #endif } #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 /* When the root window is created, initialize the screen contents from * console if -background none was specified on the command line */ static Bool RADEONCreateWindow_oneshot(WindowPtr pWin) { ScreenPtr pScreen = pWin->drawable.pScreen; ScrnInfoPtr pScrn; RADEONInfoPtr info; Bool ret; if (pWin != pScreen->root) ErrorF("%s called for non-root window %p\n", __func__, pWin); pScrn = xf86ScreenToScrn(pScreen); info = RADEONPTR(pScrn); pScreen->CreateWindow = info->CreateWindow; ret = pScreen->CreateWindow(pWin); if (ret) drmmode_copy_fb(pScrn, &info->drmmode); return ret; } #endif Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) { RADEONInfoPtr info; RADEONEntPtr pRADEONEnt; DevUnion* pPriv; Gamma zeros = { 0.0, 0.0, 0.0 }; uint32_t tiling = 0; int cpp; if (flags & PROBE_DETECT) return TRUE; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONPreInit_KMS\n"); if (pScrn->numEntities != 1) return FALSE; if (!RADEONGetRec(pScrn)) return FALSE; info = RADEONPTR(pScrn); info->IsSecondary = FALSE; info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); if (info->pEnt->location.type != BUS_PCI #ifdef XSERVER_PLATFORM_BUS && info->pEnt->location.type != BUS_PLATFORM #endif ) goto fail; pPriv = xf86GetEntityPrivate(pScrn->entityList[0], getRADEONEntityIndex()); pRADEONEnt = pPriv->ptr; if(xf86IsEntityShared(pScrn->entityList[0])) { if(xf86IsPrimInitDone(pScrn->entityList[0])) { info->IsSecondary = TRUE; } else { xf86SetPrimInitDone(pScrn->entityList[0]); } } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); pScrn->monitor = pScrn->confScreen->monitor; if (!RADEONPreInitVisual(pScrn)) goto fail; xf86CollectOptions(pScrn, NULL); if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) goto fail; memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); if (!RADEONPreInitWeight(pScrn)) goto fail; if (!RADEONPreInitChipType_KMS(pScrn)) goto fail; if (radeon_open_drm_master(pScrn) == FALSE) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); goto fail; } info->dri2.available = FALSE; info->dri2.enabled = FALSE; info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd); if (info->dri2.pKernelDRMVersion == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RADEONDRIGetVersion failed to get the DRM version\n"); goto fail; } if (!RADEONPreInitAccel_KMS(pScrn)) goto fail; radeon_drm_queue_init(); info->allowColorTiling2D = FALSE; RADEONSetupCapabilities(pScrn); /* don't enable tiling if accel is not enabled */ if (!info->r600_shadow_fb) { Bool colorTilingDefault = xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) && info->ChipFamily >= CHIP_FAMILY_R300 && /* this check could be removed sometime after a big mesa release * with proper bit, in the meantime you need to set tiling option in * xorg configuration files */ info->ChipFamily <= CHIP_FAMILY_MULLINS && !info->is_fast_fb; /* 2D color tiling */ if (info->ChipFamily >= CHIP_FAMILY_R600) { info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, info->ChipFamily <= CHIP_FAMILY_MULLINS); } if (info->ChipFamily >= CHIP_FAMILY_R600) { /* set default group bytes, overridden by kernel info below */ info->group_bytes = 256; info->have_tiling_info = FALSE; if (info->dri2.pKernelDRMVersion->version_minor >= 6) { if (r600_get_tile_config(pScrn)) { info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, colorTilingDefault); /* need working DFS for tiling */ if ((info->ChipFamily == CHIP_FAMILY_PALM) && (!info->accel_state->allowHWDFS)) info->allowColorTiling = FALSE; } else info->allowColorTiling = FALSE; } else xf86DrvMsg(pScrn->scrnIndex, X_INFO, "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); } else info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, colorTilingDefault); } else info->allowColorTiling = FALSE; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); #if USE_GLAMOR if (info->use_glamor) { info->shadow_primary = xf86ReturnOptValBool(info->Options, OPTION_SHADOW_PRIMARY, FALSE); if (info->shadow_primary) xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); } #endif info->tear_free = xf86ReturnOptValBool(info->Options, OPTION_TEAR_FREE, FALSE); if (info->tear_free) xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "TearFree enabled\n"); if (info->dri2.pKernelDRMVersion->version_minor >= 8) { info->allowPageFlip = xf86ReturnOptValBool(info->Options, OPTION_PAGE_FLIP, TRUE); if (info->tear_free || info->shadow_primary) { xf86DrvMsg(pScrn->scrnIndex, info->allowPageFlip ? X_WARNING : X_DEFAULT, "KMS Pageflipping: disabled%s\n", info->allowPageFlip ? " because of ShadowPrimary/TearFree" : ""); info->allowPageFlip = FALSE; } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "KMS Pageflipping: %sabled\n", info->allowPageFlip ? "en" : "dis"); } } info->swapBuffersWait = xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? "en" : "dis"); if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { info->drmmode.delete_dp_12_displays = TRUE; } if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); goto fail; } if (info->drmmode.count_crtcs == 1) pRADEONEnt->HasCRTC2 = FALSE; else pRADEONEnt->HasCRTC2 = TRUE; /* fix up cloning on rn50 cards * since they only have one crtc sometimes the xserver doesn't assign * a crtc to one of the outputs even though both outputs have common modes * which results in only one monitor being enabled. Assign a crtc here so * that both outputs light up. */ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; /* XXX: double check crtc mode */ if ((output->probed_modes != NULL) && (output->crtc == NULL)) output->crtc = xf86_config->crtc[0]; } } /* set cursor size */ if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { info->cursor_w = CURSOR_WIDTH_CIK; info->cursor_h = CURSOR_HEIGHT_CIK; } else { info->cursor_w = CURSOR_WIDTH; info->cursor_h = CURSOR_HEIGHT; } { struct drm_radeon_gem_info mminfo; if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) { info->vram_size = mminfo.vram_visible; info->gart_size = mminfo.gart_size; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", (unsigned long long)mminfo.gart_size, (unsigned long long)mminfo.vram_size, (unsigned long long)mminfo.vram_visible); } } if (!info->use_glamor) { info->exa_pixmaps = xf86ReturnOptValBool(info->Options, OPTION_EXA_PIXMAPS, (info->vram_size > (32 * 1024 * 1024) && info->RenderAccel && !info->is_fast_fb)); if (info->exa_pixmaps) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA: Driver will allow EXA pixmaps in VRAM\n"); else xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA: Driver will not allow EXA pixmaps in VRAM\n"); } /* no tiled scanout on r6xx+ yet */ if (info->allowColorTiling) { if (info->ChipFamily >= CHIP_FAMILY_R600) tiling |= RADEON_TILING_MICRO; else tiling |= RADEON_TILING_MACRO; } cpp = pScrn->bitsPerPixel / 8; pScrn->displayWidth = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); /* Set display resolution */ xf86SetDpi(pScrn, 0, 0); /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; if (!xf86SetGamma(pScrn, zeros)) return FALSE; if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; } if (pScrn->modes == NULL #ifdef XSERVER_PLATFORM_BUS && !pScrn->is_gpu #endif ) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); goto fail; } return TRUE; fail: RADEONFreeRec(pScrn); return FALSE; } static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); return xf86_cursors_init (pScreen, info->cursor_w, info->cursor_h, (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | HARDWARE_CURSOR_UPDATE_UNHIDDEN | HARDWARE_CURSOR_ARGB)); } void RADEONBlank(ScrnInfoPtr pScrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); xf86OutputPtr output; xf86CrtcPtr crtc; int o, c; for (c = 0; c < xf86_config->num_crtc; c++) { crtc = xf86_config->crtc[c]; for (o = 0; o < xf86_config->num_output; o++) { output = xf86_config->output[o]; if (output->crtc != crtc) continue; output->funcs->dpms(output, DPMSModeOff); } crtc->funcs->dpms(crtc, DPMSModeOff); } } void RADEONUnblank(ScrnInfoPtr pScrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); xf86OutputPtr output; xf86CrtcPtr crtc; int o, c; for (c = 0; c < xf86_config->num_crtc; c++) { crtc = xf86_config->crtc[c]; if(!crtc->enabled) continue; crtc->funcs->dpms(crtc, DPMSModeOn); for (o = 0; o < xf86_config->num_output; o++) { output = xf86_config->output[o]; if (output->crtc != crtc) continue; output->funcs->dpms(output, DPMSModeOn); } } } static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); Bool unblank; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONSaveScreen(%d)\n", mode); unblank = xf86IsUnblank(mode); if (unblank) SetTimeSinceLastInputEvent(); if ((pScrn != NULL) && pScrn->vtSema) { if (unblank) RADEONUnblank(pScrn); else RADEONBlank(pScrn); } return TRUE; } static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86_PDEV_SERVER_FD RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); #endif int err; #ifdef XF86_PDEV_SERVER_FD if (pRADEONEnt->platform_dev && (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) return TRUE; #endif err = drmSetMaster(info->dri2.drm_fd); if (err) ErrorF("Unable to retrieve master\n"); return err == 0; } static void radeon_drop_drm_master(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86_PDEV_SERVER_FD RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); if (pRADEONEnt->platform_dev && (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) return; #endif drmDropMaster(info->dri2.drm_fd); } /* Called at the end of each server generation. Restore the original * text mode, unmap video memory, and unwrap and call the saved * CloseScreen function. */ static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONCloseScreen\n"); /* Clear mask of assigned crtc's in this generation */ pRADEONEnt->assigned_crtcs = 0; drmmode_uevent_fini(pScrn, &info->drmmode); radeon_drm_queue_close(pScrn); radeon_cs_flush_indirect(pScrn); DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); if (info->accel_state->exa) { exaDriverFini(pScreen); free(info->accel_state->exa); info->accel_state->exa = NULL; } radeon_sync_close(pScreen); if (info->accel_state->use_vbos) radeon_vbo_free_lists(pScrn); radeon_drop_drm_master(pScrn); drmmode_fini(pScrn, &info->drmmode); if (info->dri2.enabled) radeon_dri2_close_screen(pScreen); pScrn->vtSema = FALSE; xf86ClearPrimInitDone(info->pEnt->index); pScreen->BlockHandler = info->BlockHandler; pScreen->CloseScreen = info->CloseScreen; return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); } void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL) { SCRN_INFO_PTR(arg); RADEONInfoPtr info = RADEONPTR(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONFreeScreen\n"); /* when server quits at PreInit, we don't need do this anymore*/ if (!info) return; RADEONFreeRec(pScrn); } Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); int subPixelOrder = SubPixelUnknown; MessageType from; Bool value; int driLevel; const char *s; void *front_ptr; pScrn->fbOffset = 0; miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, miGetDefaultVisualMask(pScrn->depth), pScrn->rgbBits, pScrn->defaultVisual)) return FALSE; miSetPixmapDepths (); if (!radeon_set_drm_master(pScrn)) return FALSE; info->directRenderingEnabled = FALSE; if (info->r600_shadow_fb == FALSE) info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd); if (!info->bufmgr) info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd); if (!info->bufmgr) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "failed to initialise GEM buffer manager"); return FALSE; } drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); if (!info->csm) info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd); if (!info->csm) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "failed to initialise command submission manager"); return FALSE; } if (!info->cs) info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); if (!info->cs) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "failed to initialise command submission buffer"); return FALSE; } radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); if (!radeon_setup_kernel_mem(pScreen)) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); return FALSE; } front_ptr = info->front_bo->ptr; if (info->r600_shadow_fb) { info->fb_shadow = calloc(1, pScrn->displayWidth * pScrn->virtualY * ((pScrn->bitsPerPixel + 7) >> 3)); if (info->fb_shadow == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate shadow framebuffer\n"); info->r600_shadow_fb = FALSE; } else { if (!fbScreenInit(pScreen, info->fb_shadow, pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) return FALSE; } } if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ if (!fbScreenInit(pScreen, front_ptr, pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) return FALSE; } xf86SetBlackWhitePixels(pScreen); if (pScrn->bitsPerPixel > 8) { VisualPtr visual; visual = pScreen->visuals + pScreen->numVisuals; while (--visual >= pScreen->visuals) { if ((visual->class | DynamicClass) == DirectColor) { visual->offsetRed = pScrn->offset.red; visual->offsetGreen = pScrn->offset.green; visual->offsetBlue = pScrn->offset.blue; visual->redMask = pScrn->mask.red; visual->greenMask = pScrn->mask.green; visual->blueMask = pScrn->mask.blue; } } } /* Must be after RGB order fixed */ fbPictureInit (pScreen, 0, 0); #ifdef RENDER if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; PictureSetSubpixelOrder (pScreen, subPixelOrder); } #endif value = FALSE; from = X_DEFAULT; if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) from = X_CONFIG; if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && (driLevel == 2 || driLevel == 3)) { from = X_CONFIG; value = driLevel == 3; } if (value) { value = radeon_sync_init(pScreen) && radeon_present_screen_init(pScreen) && radeon_dri3_screen_init(pScreen); if (!value) from = X_WARNING; } xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); pScrn->vtSema = TRUE; xf86SetBackingStore(pScreen); if (info->directRenderingEnabled) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Direct rendering disabled\n"); } if (info->r600_shadow_fb) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); info->accelOn = FALSE; } else { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing Acceleration\n"); if (RADEONAccelInit(pScreen)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); info->accelOn = TRUE; } else { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Acceleration initialization failed\n"); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); info->accelOn = FALSE; } } /* Init DPMS */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing DPMS\n"); xf86DPMSInit(pScreen, xf86DPMSSet, 0); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing Cursor\n"); /* Set Silken Mouse */ xf86SetSilkenMouse(pScreen); /* Cursor setup */ miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { if (RADEONCursorInit_KMS(pScreen)) { } } /* DGA setup */ #ifdef XFreeXDGA /* DGA is dangerous on kms as the base and framebuffer location may change: * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html */ /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ #endif if (info->r600_shadow_fb == FALSE) { /* Init Xv */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing Xv\n"); RADEONInitVideo(pScreen); } if (info->r600_shadow_fb == TRUE) { if (!shadowSetup(pScreen)) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Shadowfb initialization failed\n"); return FALSE; } } pScrn->pScreen = pScreen; #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) { info->CreateWindow = pScreen->CreateWindow; pScreen->CreateWindow = RADEONCreateWindow_oneshot; } #endif /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ info->CloseScreen = pScreen->CloseScreen; pScreen->CloseScreen = RADEONCloseScreen_KMS; pScreen->SaveScreen = RADEONSaveScreen_KMS; info->BlockHandler = pScreen->BlockHandler; pScreen->BlockHandler = RADEONBlockHandler_oneshot; if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) return FALSE; info->CreateScreenResources = pScreen->CreateScreenResources; pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; #ifdef RADEON_PIXMAP_SHARING pScreen->StartPixmapTracking = PixmapStartDirtyTracking; pScreen->StopPixmapTracking = PixmapStopDirtyTracking; #endif if (!xf86CrtcScreenInit (pScreen)) return FALSE; /* Wrap pointer motion to flip touch screen around */ // info->PointerMoved = pScrn->PointerMoved; // pScrn->PointerMoved = RADEONPointerMoved; if (!drmmode_setup_colormap(pScreen, pScrn)) return FALSE; /* Note unused options */ if (serverGeneration == 1) xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); drmmode_init(pScrn, &info->drmmode); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONScreenInit finished\n"); info->accel_state->XInited3D = FALSE; info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; return TRUE; } Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL) { SCRN_INFO_PTR(arg); RADEONInfoPtr info = RADEONPTR(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT_KMS\n"); radeon_set_drm_master(pScrn); info->accel_state->XInited3D = FALSE; info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; pScrn->vtSema = TRUE; if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE)) return FALSE; return TRUE; } void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL) { SCRN_INFO_PTR(arg); RADEONInfoPtr info = RADEONPTR(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT_KMS\n"); radeon_drop_drm_master(pScrn); xf86RotateFreeShadow(pScrn); drmmode_scanout_free(pScrn); xf86_hide_cursors (pScrn); info->accel_state->XInited3D = FALSE; info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); } Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL) { SCRN_INFO_PTR(arg); Bool ret; ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); return ret; } void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL) { SCRN_INFO_PTR(arg); RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_adjust_frame(pScrn, &info->drmmode, x, y); return; } static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int cpp = info->pixel_bytes; uint32_t screen_size; int pitch, base_align; uint32_t tiling_flags = 0; struct radeon_surface surface; if (info->accel_state->exa != NULL) { xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); return FALSE; } if (!info->use_glamor && info->r600_shadow_fb == FALSE) { info->accel_state->exa = exaDriverAlloc(); if (info->accel_state->exa == NULL) { xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); return FALSE; } } if (info->allowColorTiling && !info->shadow_primary) { if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->allowColorTiling2D) { tiling_flags |= RADEON_TILING_MACRO; } else { tiling_flags |= RADEON_TILING_MICRO; } } else tiling_flags |= RADEON_TILING_MACRO; } pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp; screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch; base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags); if (info->ChipFamily >= CHIP_FAMILY_R600) { if(!info->surf_man) { xf86DrvMsg(pScreen->myNum, X_ERROR, "failed to initialise surface manager\n"); return FALSE; } memset(&surface, 0, sizeof(struct radeon_surface)); surface.npix_x = pScrn->virtualX; surface.npix_y = pScrn->virtualY; surface.npix_z = 1; surface.blk_w = 1; surface.blk_h = 1; surface.blk_d = 1; surface.array_size = 1; surface.last_level = 0; surface.bpe = cpp; surface.nsamples = 1; surface.flags = RADEON_SURF_SCANOUT; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); if (tiling_flags & RADEON_TILING_MICRO) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); } if (tiling_flags & RADEON_TILING_MACRO) { surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } if (radeon_surface_best(info->surf_man, &surface)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "radeon_surface_best failed\n"); return FALSE; } if (radeon_surface_init(info->surf_man, &surface)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "radeon_surface_init failed\n"); return FALSE; } pitch = surface.level[0].pitch_bytes; screen_size = surface.bo_size; base_align = surface.bo_alignment; tiling_flags = 0; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling_flags |= RADEON_TILING_MACRO; tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; if (surface.tile_split) tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; break; case RADEON_SURF_MODE_1D: tiling_flags |= RADEON_TILING_MICRO; break; default: break; } info->front_surface = surface; } { int cursor_size; int c; cursor_size = info->cursor_w * info->cursor_h * 4; cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); for (c = 0; c < xf86_config->num_crtc; c++) { /* cursor objects */ if (info->cursor_bo[c] == NULL) { info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0, cursor_size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (!info->cursor_bo[c]) { ErrorF("Failed to allocate cursor buffer memory\n"); return FALSE; } if (radeon_bo_map(info->cursor_bo[c], 1)) { ErrorF("Failed to map cursor buffer memory\n"); } drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]); } } } screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE); if (info->front_bo == NULL) { info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align, info->shadow_primary ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM, 0); if (info->r600_shadow_fb == TRUE) { if (radeon_bo_map(info->front_bo, 1)) { ErrorF("Failed to map cursor buffer memory\n"); } } #if X_BYTE_ORDER == X_BIG_ENDIAN switch (cpp) { case 4: tiling_flags |= RADEON_TILING_SWAP_32BIT; break; case 2: tiling_flags |= RADEON_TILING_SWAP_16BIT; break; } if (info->ChipFamily < CHIP_FAMILY_R600 && info->r600_shadow_fb && tiling_flags) tiling_flags |= RADEON_TILING_SURFACE; #endif if (tiling_flags) radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); } pScrn->displayWidth = pitch / cpp; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024); radeon_kms_update_vram_limit(pScrn, screen_size); return TRUE; } void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); uint64_t remain_size_bytes; int c; for (c = 0; c < xf86_config->num_crtc; c++) { if (info->cursor_bo[c] != NULL) { new_fb_size += (64 * 4 * 64); } } remain_size_bytes = info->vram_size - new_fb_size; remain_size_bytes = (remain_size_bytes / 10) * 9; if (remain_size_bytes > 0xffffffff) remain_size_bytes = 0xffffffff; radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, (uint32_t)remain_size_bytes); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", (uint32_t)remain_size_bytes / 1024); } /* Used to disallow modes that are not supported by the hardware */ ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, Bool verbose, int flag) { SCRN_INFO_PTR(arg); RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); /* * RN50 has effective maximum mode bandwidth of about 300MiB/s. * XXX should really do this for all chips by properly computing * memory bandwidth and an overhead factor. */ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) return MODE_BANDWIDTH; } /* There are problems with double scan mode at high clocks * They're likely related PLL and display buffer settings. * Disable these modes for now. */ if (mode->Flags & V_DBLSCAN) { if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) return MODE_CLOCK_RANGE; } return MODE_OK; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_list.h000066400000000000000000000030301256524674500227450ustar00rootroot00000000000000/* * Copyright © 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef _RADEON_LIST_H_ #define _RADEON_LIST_H_ #include #include #if !HAVE_XORG_LIST #define xorg_list list #define xorg_list_init list_init #define xorg_list_add list_add #define xorg_list_del list_del #define xorg_list_for_each_entry list_for_each_entry #define xorg_list_for_each_entry_safe list_for_each_entry_safe #endif #endif /* _RADEON_LIST_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_misc.c000066400000000000000000000043641256524674500227330ustar00rootroot00000000000000/* * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon_probe.h" #include "radeon_version.h" #include "xf86.h" /* Module loader interface for subsidiary driver module */ static XF86ModuleVersionInfo RADEONVersionRec = { RADEON_DRIVER_NAME, MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, XORG_VERSION_CURRENT, RADEON_VERSION_MAJOR, RADEON_VERSION_MINOR, RADEON_VERSION_PATCH, ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, MOD_CLASS_VIDEODRV, {0, 0, 0, 0} }; /* * RADEONSetup -- * * This function is called every time the module is loaded. */ static pointer RADEONSetup ( pointer Module, pointer Options, int *ErrorMajor, int *ErrorMinor ) { static Bool Inited = FALSE; if (!Inited) { Inited = TRUE; xf86AddDriver(&RADEON, Module, HaveDriverFuncs); } return (pointer)TRUE; } /* The following record must be called radeonModuleData */ _X_EXPORT XF86ModuleData radeonModuleData = { &RADEONVersionRec, RADEONSetup, NULL }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_pci_chipset_gen.h000066400000000000000000001264051256524674500251310ustar00rootroot00000000000000/* This file is autogenerated please do not edit */ static PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, { PCI_CHIP_RV380_3151, PCI_CHIP_RV380_3151, RES_SHARED_VGA }, { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, { PCI_CHIP_RV380_3155, PCI_CHIP_RV380_3155, RES_SHARED_VGA }, { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA }, { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA }, { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA }, { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA }, { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA }, { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA }, { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA }, { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA }, { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA }, { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA }, { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA }, { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA }, { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA }, { PCI_CHIP_R420_JT, PCI_CHIP_R420_JT, RES_SHARED_VGA }, { PCI_CHIP_R481_4B48, PCI_CHIP_R481_4B48, RES_SHARED_VGA }, { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA }, { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA }, { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA }, { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA }, { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, { PCI_CHIP_RV280_4C6E, PCI_CHIP_RV280_4C6E, RES_SHARED_VGA }, { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA }, { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA }, { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA }, { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA }, { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA }, { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA }, { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA }, { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA }, { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA }, { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA }, { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA }, { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA }, { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA }, { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA }, { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA }, { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA }, { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA }, { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA }, { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA }, { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA }, { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, { PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA }, { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA }, { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA }, { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA }, { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA }, { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA }, { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA }, { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA }, { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA }, { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA }, { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA }, { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA }, { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA }, { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA }, { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA }, { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA }, { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA }, { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA }, { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, { PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA }, { PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA }, { PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA }, { PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA }, { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA }, { PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA }, { PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA }, { PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA }, { PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA }, { PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA }, { PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA }, { PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA }, { PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA }, { PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA }, { PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA }, { PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA }, { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA }, { PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA }, { PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA }, { PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA }, { PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA }, { PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA }, { PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA }, { PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA }, { PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA }, { PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA }, { PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA }, { PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA }, { PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA }, { PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA }, { PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA }, { PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA }, { PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA }, { PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA }, { PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA }, { PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA }, { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA }, { PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA }, { PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA }, { PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA }, { PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA }, { PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA }, { PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA }, { PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA }, { PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA }, { PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA }, { PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA }, { PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA }, { PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA }, { PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA }, { PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA }, { PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA }, { PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA }, { PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA }, { PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA }, { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA }, { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA }, { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA }, { PCI_CHIP_RV515_7200, PCI_CHIP_RV515_7200, RES_SHARED_VGA }, { PCI_CHIP_RV515_7210, PCI_CHIP_RV515_7210, RES_SHARED_VGA }, { PCI_CHIP_RV515_7211, PCI_CHIP_RV515_7211, RES_SHARED_VGA }, { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA }, { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA }, { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA }, { PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA }, { PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA }, { PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA }, { PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA }, { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA }, { PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA }, { PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA }, { PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA }, { PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA }, { PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA }, { PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA }, { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA }, { PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA }, { PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA }, { PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA }, { PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA }, { PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA }, { PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA }, { PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA }, { PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA }, { PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA }, { PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA }, { PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA }, { PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA }, { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA }, { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA }, { PCI_CHIP_RS600_793F, PCI_CHIP_RS600_793F, RES_SHARED_VGA }, { PCI_CHIP_RS600_7941, PCI_CHIP_RS600_7941, RES_SHARED_VGA }, { PCI_CHIP_RS600_7942, PCI_CHIP_RS600_7942, RES_SHARED_VGA }, { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA }, { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA }, { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA }, { PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA }, { PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA }, { PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA }, { PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA }, { PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA }, { PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA }, { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA }, { PCI_CHIP_RV770_9441, PCI_CHIP_RV770_9441, RES_SHARED_VGA }, { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA }, { PCI_CHIP_RV770_9443, PCI_CHIP_RV770_9443, RES_SHARED_VGA }, { PCI_CHIP_RV770_9444, PCI_CHIP_RV770_9444, RES_SHARED_VGA }, { PCI_CHIP_RV770_9446, PCI_CHIP_RV770_9446, RES_SHARED_VGA }, { PCI_CHIP_RV770_944A, PCI_CHIP_RV770_944A, RES_SHARED_VGA }, { PCI_CHIP_RV770_944B, PCI_CHIP_RV770_944B, RES_SHARED_VGA }, { PCI_CHIP_RV770_944C, PCI_CHIP_RV770_944C, RES_SHARED_VGA }, { PCI_CHIP_RV770_944E, PCI_CHIP_RV770_944E, RES_SHARED_VGA }, { PCI_CHIP_RV770_9450, PCI_CHIP_RV770_9450, RES_SHARED_VGA }, { PCI_CHIP_RV770_9452, PCI_CHIP_RV770_9452, RES_SHARED_VGA }, { PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA }, { PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA }, { PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA }, { PCI_CHIP_RV770_945E, PCI_CHIP_RV770_945E, RES_SHARED_VGA }, { PCI_CHIP_RV790_9460, PCI_CHIP_RV790_9460, RES_SHARED_VGA }, { PCI_CHIP_RV790_9462, PCI_CHIP_RV790_9462, RES_SHARED_VGA }, { PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA }, { PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA }, { PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA }, { PCI_CHIP_RV770_947B, PCI_CHIP_RV770_947B, RES_SHARED_VGA }, { PCI_CHIP_RV730_9480, PCI_CHIP_RV730_9480, RES_SHARED_VGA }, { PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA }, { PCI_CHIP_RV730_9488, PCI_CHIP_RV730_9488, RES_SHARED_VGA }, { PCI_CHIP_RV730_9489, PCI_CHIP_RV730_9489, RES_SHARED_VGA }, { PCI_CHIP_RV730_948A, PCI_CHIP_RV730_948A, RES_SHARED_VGA }, { PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA }, { PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA }, { PCI_CHIP_RV730_9491, PCI_CHIP_RV730_9491, RES_SHARED_VGA }, { PCI_CHIP_RV730_9495, PCI_CHIP_RV730_9495, RES_SHARED_VGA }, { PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA }, { PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA }, { PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA }, { PCI_CHIP_RV730_949F, PCI_CHIP_RV730_949F, RES_SHARED_VGA }, { PCI_CHIP_RV740_94A0, PCI_CHIP_RV740_94A0, RES_SHARED_VGA }, { PCI_CHIP_RV740_94A1, PCI_CHIP_RV740_94A1, RES_SHARED_VGA }, { PCI_CHIP_RV740_94A3, PCI_CHIP_RV740_94A3, RES_SHARED_VGA }, { PCI_CHIP_RV740_94B1, PCI_CHIP_RV740_94B1, RES_SHARED_VGA }, { PCI_CHIP_RV740_94B3, PCI_CHIP_RV740_94B3, RES_SHARED_VGA }, { PCI_CHIP_RV740_94B4, PCI_CHIP_RV740_94B4, RES_SHARED_VGA }, { PCI_CHIP_RV740_94B5, PCI_CHIP_RV740_94B5, RES_SHARED_VGA }, { PCI_CHIP_RV740_94B9, PCI_CHIP_RV740_94B9, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA }, { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA }, { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA }, { PCI_CHIP_RV610_94CD, PCI_CHIP_RV610_94CD, RES_SHARED_VGA }, { PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA }, { PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA }, { PCI_CHIP_RV670_9504, PCI_CHIP_RV670_9504, RES_SHARED_VGA }, { PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA }, { PCI_CHIP_RV670_9506, PCI_CHIP_RV670_9506, RES_SHARED_VGA }, { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, { PCI_CHIP_RV670_9508, PCI_CHIP_RV670_9508, RES_SHARED_VGA }, { PCI_CHIP_RV670_9509, PCI_CHIP_RV670_9509, RES_SHARED_VGA }, { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA }, { PCI_CHIP_RV670_9517, PCI_CHIP_RV670_9517, RES_SHARED_VGA }, { PCI_CHIP_RV670_9519, PCI_CHIP_RV670_9519, RES_SHARED_VGA }, { PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA }, { PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA }, { PCI_CHIP_RV710_9542, PCI_CHIP_RV710_9542, RES_SHARED_VGA }, { PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA }, { PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA }, { PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA }, { PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA }, { PCI_CHIP_RV710_9555, PCI_CHIP_RV710_9555, RES_SHARED_VGA }, { PCI_CHIP_RV710_9557, PCI_CHIP_RV710_9557, RES_SHARED_VGA }, { PCI_CHIP_RV710_955F, PCI_CHIP_RV710_955F, RES_SHARED_VGA }, { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, { PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA }, { PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA }, { PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA }, { PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA }, { PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA }, { PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA }, { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, { PCI_CHIP_RV630_958F, PCI_CHIP_RV630_958F, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C6, PCI_CHIP_RV620_95C6, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C9, PCI_CHIP_RV620_95C9, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CC, PCI_CHIP_RV620_95CC, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA }, { PCI_CHIP_RV635_9590, PCI_CHIP_RV635_9590, RES_SHARED_VGA }, { PCI_CHIP_RV635_9596, PCI_CHIP_RV635_9596, RES_SHARED_VGA }, { PCI_CHIP_RV635_9597, PCI_CHIP_RV635_9597, RES_SHARED_VGA }, { PCI_CHIP_RV635_9598, PCI_CHIP_RV635_9598, RES_SHARED_VGA }, { PCI_CHIP_RV635_9599, PCI_CHIP_RV635_9599, RES_SHARED_VGA }, { PCI_CHIP_RV635_9591, PCI_CHIP_RV635_9591, RES_SHARED_VGA }, { PCI_CHIP_RV635_9593, PCI_CHIP_RV635_9593, RES_SHARED_VGA }, { PCI_CHIP_RV635_9595, PCI_CHIP_RV635_9595, RES_SHARED_VGA }, { PCI_CHIP_RV635_959B, PCI_CHIP_RV635_959B, RES_SHARED_VGA }, { PCI_CHIP_RS780_9610, PCI_CHIP_RS780_9610, RES_SHARED_VGA }, { PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA }, { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, { PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA }, { PCI_CHIP_RS780_9615, PCI_CHIP_RS780_9615, RES_SHARED_VGA }, { PCI_CHIP_RS780_9616, PCI_CHIP_RS780_9616, RES_SHARED_VGA }, { PCI_CHIP_SUMO_9640, PCI_CHIP_SUMO_9640, RES_SHARED_VGA }, { PCI_CHIP_SUMO_9641, PCI_CHIP_SUMO_9641, RES_SHARED_VGA }, { PCI_CHIP_SUMO2_9642, PCI_CHIP_SUMO2_9642, RES_SHARED_VGA }, { PCI_CHIP_SUMO2_9643, PCI_CHIP_SUMO2_9643, RES_SHARED_VGA }, { PCI_CHIP_SUMO2_9644, PCI_CHIP_SUMO2_9644, RES_SHARED_VGA }, { PCI_CHIP_SUMO2_9645, PCI_CHIP_SUMO2_9645, RES_SHARED_VGA }, { PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA }, { PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA }, { PCI_CHIP_SUMO2_9649, PCI_CHIP_SUMO2_9649, RES_SHARED_VGA }, { PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA }, { PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA }, { PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA }, { PCI_CHIP_SUMO_964E, PCI_CHIP_SUMO_964E, RES_SHARED_VGA }, { PCI_CHIP_SUMO_964F, PCI_CHIP_SUMO_964F, RES_SHARED_VGA }, { PCI_CHIP_RS880_9710, PCI_CHIP_RS880_9710, RES_SHARED_VGA }, { PCI_CHIP_RS880_9711, PCI_CHIP_RS880_9711, RES_SHARED_VGA }, { PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA }, { PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA }, { PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA }, { PCI_CHIP_RS880_9715, PCI_CHIP_RS880_9715, RES_SHARED_VGA }, { PCI_CHIP_PALM_9802, PCI_CHIP_PALM_9802, RES_SHARED_VGA }, { PCI_CHIP_PALM_9803, PCI_CHIP_PALM_9803, RES_SHARED_VGA }, { PCI_CHIP_PALM_9804, PCI_CHIP_PALM_9804, RES_SHARED_VGA }, { PCI_CHIP_PALM_9805, PCI_CHIP_PALM_9805, RES_SHARED_VGA }, { PCI_CHIP_PALM_9806, PCI_CHIP_PALM_9806, RES_SHARED_VGA }, { PCI_CHIP_PALM_9807, PCI_CHIP_PALM_9807, RES_SHARED_VGA }, { PCI_CHIP_PALM_9808, PCI_CHIP_PALM_9808, RES_SHARED_VGA }, { PCI_CHIP_PALM_9809, PCI_CHIP_PALM_9809, RES_SHARED_VGA }, { PCI_CHIP_PALM_980A, PCI_CHIP_PALM_980A, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_688A, PCI_CHIP_CYPRESS_688A, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_688C, PCI_CHIP_CYPRESS_688C, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_688D, PCI_CHIP_CYPRESS_688D, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_6898, PCI_CHIP_CYPRESS_6898, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_6899, PCI_CHIP_CYPRESS_6899, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_689B, PCI_CHIP_CYPRESS_689B, RES_SHARED_VGA }, { PCI_CHIP_CYPRESS_689E, PCI_CHIP_CYPRESS_689E, RES_SHARED_VGA }, { PCI_CHIP_HEMLOCK_689C, PCI_CHIP_HEMLOCK_689C, RES_SHARED_VGA }, { PCI_CHIP_HEMLOCK_689D, PCI_CHIP_HEMLOCK_689D, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68A0, PCI_CHIP_JUNIPER_68A0, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68A1, PCI_CHIP_JUNIPER_68A1, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68A8, PCI_CHIP_JUNIPER_68A8, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68A9, PCI_CHIP_JUNIPER_68A9, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68B0, PCI_CHIP_JUNIPER_68B0, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68B8, PCI_CHIP_JUNIPER_68B8, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68B9, PCI_CHIP_JUNIPER_68B9, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68BA, PCI_CHIP_JUNIPER_68BA, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68BE, PCI_CHIP_JUNIPER_68BE, RES_SHARED_VGA }, { PCI_CHIP_JUNIPER_68BF, PCI_CHIP_JUNIPER_68BF, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68C0, PCI_CHIP_REDWOOD_68C0, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68C1, PCI_CHIP_REDWOOD_68C1, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68C7, PCI_CHIP_REDWOOD_68C7, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68C8, PCI_CHIP_REDWOOD_68C8, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68C9, PCI_CHIP_REDWOOD_68C9, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68D8, PCI_CHIP_REDWOOD_68D8, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68D9, PCI_CHIP_REDWOOD_68D9, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68DA, PCI_CHIP_REDWOOD_68DA, RES_SHARED_VGA }, { PCI_CHIP_REDWOOD_68DE, PCI_CHIP_REDWOOD_68DE, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E0, PCI_CHIP_CEDAR_68E0, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E1, PCI_CHIP_CEDAR_68E1, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E4, PCI_CHIP_CEDAR_68E4, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E5, PCI_CHIP_CEDAR_68E5, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E8, PCI_CHIP_CEDAR_68E8, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68E9, PCI_CHIP_CEDAR_68E9, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68F1, PCI_CHIP_CEDAR_68F1, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68F2, PCI_CHIP_CEDAR_68F2, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68FA, PCI_CHIP_CEDAR_68FA, RES_SHARED_VGA }, { PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6700, PCI_CHIP_CAYMAN_6700, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6701, PCI_CHIP_CAYMAN_6701, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6702, PCI_CHIP_CAYMAN_6702, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6703, PCI_CHIP_CAYMAN_6703, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6704, PCI_CHIP_CAYMAN_6704, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6705, PCI_CHIP_CAYMAN_6705, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6706, PCI_CHIP_CAYMAN_6706, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6707, PCI_CHIP_CAYMAN_6707, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6708, PCI_CHIP_CAYMAN_6708, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6709, PCI_CHIP_CAYMAN_6709, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6718, PCI_CHIP_CAYMAN_6718, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_6719, PCI_CHIP_CAYMAN_6719, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_671C, PCI_CHIP_CAYMAN_671C, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_671D, PCI_CHIP_CAYMAN_671D, RES_SHARED_VGA }, { PCI_CHIP_CAYMAN_671F, PCI_CHIP_CAYMAN_671F, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6720, PCI_CHIP_BARTS_6720, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6721, PCI_CHIP_BARTS_6721, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6722, PCI_CHIP_BARTS_6722, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6723, PCI_CHIP_BARTS_6723, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6724, PCI_CHIP_BARTS_6724, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6725, PCI_CHIP_BARTS_6725, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6726, PCI_CHIP_BARTS_6726, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6727, PCI_CHIP_BARTS_6727, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6728, PCI_CHIP_BARTS_6728, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6729, PCI_CHIP_BARTS_6729, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6738, PCI_CHIP_BARTS_6738, RES_SHARED_VGA }, { PCI_CHIP_BARTS_6739, PCI_CHIP_BARTS_6739, RES_SHARED_VGA }, { PCI_CHIP_BARTS_673E, PCI_CHIP_BARTS_673E, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6740, PCI_CHIP_TURKS_6740, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6741, PCI_CHIP_TURKS_6741, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6742, PCI_CHIP_TURKS_6742, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6743, PCI_CHIP_TURKS_6743, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6744, PCI_CHIP_TURKS_6744, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6745, PCI_CHIP_TURKS_6745, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6746, PCI_CHIP_TURKS_6746, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6747, PCI_CHIP_TURKS_6747, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6748, PCI_CHIP_TURKS_6748, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6749, PCI_CHIP_TURKS_6749, RES_SHARED_VGA }, { PCI_CHIP_TURKS_674A, PCI_CHIP_TURKS_674A, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6750, PCI_CHIP_TURKS_6750, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6751, PCI_CHIP_TURKS_6751, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6758, PCI_CHIP_TURKS_6758, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6759, PCI_CHIP_TURKS_6759, RES_SHARED_VGA }, { PCI_CHIP_TURKS_675B, PCI_CHIP_TURKS_675B, RES_SHARED_VGA }, { PCI_CHIP_TURKS_675D, PCI_CHIP_TURKS_675D, RES_SHARED_VGA }, { PCI_CHIP_TURKS_675F, PCI_CHIP_TURKS_675F, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6840, PCI_CHIP_TURKS_6840, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6841, PCI_CHIP_TURKS_6841, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6842, PCI_CHIP_TURKS_6842, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6843, PCI_CHIP_TURKS_6843, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6849, PCI_CHIP_TURKS_6849, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6850, PCI_CHIP_TURKS_6850, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6858, PCI_CHIP_TURKS_6858, RES_SHARED_VGA }, { PCI_CHIP_TURKS_6859, PCI_CHIP_TURKS_6859, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6760, PCI_CHIP_CAICOS_6760, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6761, PCI_CHIP_CAICOS_6761, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6762, PCI_CHIP_CAICOS_6762, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6763, PCI_CHIP_CAICOS_6763, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6764, PCI_CHIP_CAICOS_6764, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6765, PCI_CHIP_CAICOS_6765, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6766, PCI_CHIP_CAICOS_6766, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6767, PCI_CHIP_CAICOS_6767, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6768, PCI_CHIP_CAICOS_6768, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6770, PCI_CHIP_CAICOS_6770, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6771, PCI_CHIP_CAICOS_6771, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6772, PCI_CHIP_CAICOS_6772, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6778, PCI_CHIP_CAICOS_6778, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_6779, PCI_CHIP_CAICOS_6779, RES_SHARED_VGA }, { PCI_CHIP_CAICOS_677B, PCI_CHIP_CAICOS_677B, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9900, PCI_CHIP_ARUBA_9900, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9901, PCI_CHIP_ARUBA_9901, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9903, PCI_CHIP_ARUBA_9903, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9904, PCI_CHIP_ARUBA_9904, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9905, PCI_CHIP_ARUBA_9905, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9906, PCI_CHIP_ARUBA_9906, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9907, PCI_CHIP_ARUBA_9907, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9908, PCI_CHIP_ARUBA_9908, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9909, PCI_CHIP_ARUBA_9909, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990A, PCI_CHIP_ARUBA_990A, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990B, PCI_CHIP_ARUBA_990B, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990C, PCI_CHIP_ARUBA_990C, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990D, PCI_CHIP_ARUBA_990D, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990E, PCI_CHIP_ARUBA_990E, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_990F, PCI_CHIP_ARUBA_990F, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9910, PCI_CHIP_ARUBA_9910, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9913, PCI_CHIP_ARUBA_9913, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9917, PCI_CHIP_ARUBA_9917, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9918, PCI_CHIP_ARUBA_9918, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9919, PCI_CHIP_ARUBA_9919, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9990, PCI_CHIP_ARUBA_9990, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9991, PCI_CHIP_ARUBA_9991, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9992, PCI_CHIP_ARUBA_9992, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9993, PCI_CHIP_ARUBA_9993, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9994, PCI_CHIP_ARUBA_9994, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9995, PCI_CHIP_ARUBA_9995, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9996, PCI_CHIP_ARUBA_9996, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9997, PCI_CHIP_ARUBA_9997, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9998, PCI_CHIP_ARUBA_9998, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_9999, PCI_CHIP_ARUBA_9999, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_999A, PCI_CHIP_ARUBA_999A, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_999B, PCI_CHIP_ARUBA_999B, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_999C, PCI_CHIP_ARUBA_999C, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_999D, PCI_CHIP_ARUBA_999D, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_99A0, PCI_CHIP_ARUBA_99A0, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_99A2, PCI_CHIP_ARUBA_99A2, RES_SHARED_VGA }, { PCI_CHIP_ARUBA_99A4, PCI_CHIP_ARUBA_99A4, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6780, PCI_CHIP_TAHITI_6780, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6784, PCI_CHIP_TAHITI_6784, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6788, PCI_CHIP_TAHITI_6788, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_678A, PCI_CHIP_TAHITI_678A, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6790, PCI_CHIP_TAHITI_6790, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6791, PCI_CHIP_TAHITI_6791, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6792, PCI_CHIP_TAHITI_6792, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6798, PCI_CHIP_TAHITI_6798, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_6799, PCI_CHIP_TAHITI_6799, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_679A, PCI_CHIP_TAHITI_679A, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_679B, PCI_CHIP_TAHITI_679B, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_679E, PCI_CHIP_TAHITI_679E, RES_SHARED_VGA }, { PCI_CHIP_TAHITI_679F, PCI_CHIP_TAHITI_679F, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6800, PCI_CHIP_PITCAIRN_6800, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6801, PCI_CHIP_PITCAIRN_6801, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6802, PCI_CHIP_PITCAIRN_6802, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6806, PCI_CHIP_PITCAIRN_6806, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6808, PCI_CHIP_PITCAIRN_6808, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6809, PCI_CHIP_PITCAIRN_6809, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6810, PCI_CHIP_PITCAIRN_6810, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6811, PCI_CHIP_PITCAIRN_6811, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6816, PCI_CHIP_PITCAIRN_6816, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6817, PCI_CHIP_PITCAIRN_6817, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6818, PCI_CHIP_PITCAIRN_6818, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_6819, PCI_CHIP_PITCAIRN_6819, RES_SHARED_VGA }, { PCI_CHIP_PITCAIRN_684C, PCI_CHIP_PITCAIRN_684C, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6820, PCI_CHIP_VERDE_6820, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6821, PCI_CHIP_VERDE_6821, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6822, PCI_CHIP_VERDE_6822, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6823, PCI_CHIP_VERDE_6823, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6824, PCI_CHIP_VERDE_6824, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6825, PCI_CHIP_VERDE_6825, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6826, PCI_CHIP_VERDE_6826, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6827, PCI_CHIP_VERDE_6827, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6828, PCI_CHIP_VERDE_6828, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6829, PCI_CHIP_VERDE_6829, RES_SHARED_VGA }, { PCI_CHIP_VERDE_682A, PCI_CHIP_VERDE_682A, RES_SHARED_VGA }, { PCI_CHIP_VERDE_682B, PCI_CHIP_VERDE_682B, RES_SHARED_VGA }, { PCI_CHIP_VERDE_682C, PCI_CHIP_VERDE_682C, RES_SHARED_VGA }, { PCI_CHIP_VERDE_682D, PCI_CHIP_VERDE_682D, RES_SHARED_VGA }, { PCI_CHIP_VERDE_682F, PCI_CHIP_VERDE_682F, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6830, PCI_CHIP_VERDE_6830, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6831, PCI_CHIP_VERDE_6831, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6835, PCI_CHIP_VERDE_6835, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6837, PCI_CHIP_VERDE_6837, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6838, PCI_CHIP_VERDE_6838, RES_SHARED_VGA }, { PCI_CHIP_VERDE_6839, PCI_CHIP_VERDE_6839, RES_SHARED_VGA }, { PCI_CHIP_VERDE_683B, PCI_CHIP_VERDE_683B, RES_SHARED_VGA }, { PCI_CHIP_VERDE_683D, PCI_CHIP_VERDE_683D, RES_SHARED_VGA }, { PCI_CHIP_VERDE_683F, PCI_CHIP_VERDE_683F, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6600, PCI_CHIP_OLAND_6600, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6601, PCI_CHIP_OLAND_6601, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6602, PCI_CHIP_OLAND_6602, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6603, PCI_CHIP_OLAND_6603, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6604, PCI_CHIP_OLAND_6604, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6605, PCI_CHIP_OLAND_6605, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6606, PCI_CHIP_OLAND_6606, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6607, PCI_CHIP_OLAND_6607, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6608, PCI_CHIP_OLAND_6608, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6610, PCI_CHIP_OLAND_6610, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6611, PCI_CHIP_OLAND_6611, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6613, PCI_CHIP_OLAND_6613, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6617, PCI_CHIP_OLAND_6617, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6620, PCI_CHIP_OLAND_6620, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6621, PCI_CHIP_OLAND_6621, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6623, PCI_CHIP_OLAND_6623, RES_SHARED_VGA }, { PCI_CHIP_OLAND_6631, PCI_CHIP_OLAND_6631, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_6660, PCI_CHIP_HAINAN_6660, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_6663, PCI_CHIP_HAINAN_6663, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_6664, PCI_CHIP_HAINAN_6664, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_6665, PCI_CHIP_HAINAN_6665, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_6667, PCI_CHIP_HAINAN_6667, RES_SHARED_VGA }, { PCI_CHIP_HAINAN_666F, PCI_CHIP_HAINAN_666F, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6640, PCI_CHIP_BONAIRE_6640, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6641, PCI_CHIP_BONAIRE_6641, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6646, PCI_CHIP_BONAIRE_6646, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6647, PCI_CHIP_BONAIRE_6647, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6649, PCI_CHIP_BONAIRE_6649, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6650, PCI_CHIP_BONAIRE_6650, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6651, PCI_CHIP_BONAIRE_6651, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_6658, PCI_CHIP_BONAIRE_6658, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_665C, PCI_CHIP_BONAIRE_665C, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_665D, PCI_CHIP_BONAIRE_665D, RES_SHARED_VGA }, { PCI_CHIP_BONAIRE_665F, PCI_CHIP_BONAIRE_665F, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9830, PCI_CHIP_KABINI_9830, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9831, PCI_CHIP_KABINI_9831, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9832, PCI_CHIP_KABINI_9832, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9833, PCI_CHIP_KABINI_9833, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9834, PCI_CHIP_KABINI_9834, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9835, PCI_CHIP_KABINI_9835, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9836, PCI_CHIP_KABINI_9836, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9837, PCI_CHIP_KABINI_9837, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9838, PCI_CHIP_KABINI_9838, RES_SHARED_VGA }, { PCI_CHIP_KABINI_9839, PCI_CHIP_KABINI_9839, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983A, PCI_CHIP_KABINI_983A, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983B, PCI_CHIP_KABINI_983B, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983C, PCI_CHIP_KABINI_983C, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983D, PCI_CHIP_KABINI_983D, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983E, PCI_CHIP_KABINI_983E, RES_SHARED_VGA }, { PCI_CHIP_KABINI_983F, PCI_CHIP_KABINI_983F, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9850, PCI_CHIP_MULLINS_9850, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9851, PCI_CHIP_MULLINS_9851, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9852, PCI_CHIP_MULLINS_9852, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9853, PCI_CHIP_MULLINS_9853, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9854, PCI_CHIP_MULLINS_9854, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9855, PCI_CHIP_MULLINS_9855, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9856, PCI_CHIP_MULLINS_9856, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9857, PCI_CHIP_MULLINS_9857, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9858, PCI_CHIP_MULLINS_9858, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_9859, PCI_CHIP_MULLINS_9859, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985A, PCI_CHIP_MULLINS_985A, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985B, PCI_CHIP_MULLINS_985B, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985C, PCI_CHIP_MULLINS_985C, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA }, { PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1307, PCI_CHIP_KAVERI_1307, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1309, PCI_CHIP_KAVERI_1309, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130A, PCI_CHIP_KAVERI_130A, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130B, PCI_CHIP_KAVERI_130B, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130C, PCI_CHIP_KAVERI_130C, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130D, PCI_CHIP_KAVERI_130D, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130E, PCI_CHIP_KAVERI_130E, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_130F, PCI_CHIP_KAVERI_130F, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1310, PCI_CHIP_KAVERI_1310, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1311, PCI_CHIP_KAVERI_1311, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1312, PCI_CHIP_KAVERI_1312, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1313, PCI_CHIP_KAVERI_1313, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1315, PCI_CHIP_KAVERI_1315, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1316, PCI_CHIP_KAVERI_1316, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1317, PCI_CHIP_KAVERI_1317, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_1318, PCI_CHIP_KAVERI_1318, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA }, { PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67A0, PCI_CHIP_HAWAII_67A0, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67A1, PCI_CHIP_HAWAII_67A1, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67A2, PCI_CHIP_HAWAII_67A2, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67A8, PCI_CHIP_HAWAII_67A8, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67A9, PCI_CHIP_HAWAII_67A9, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67AA, PCI_CHIP_HAWAII_67AA, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67B0, PCI_CHIP_HAWAII_67B0, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67B1, PCI_CHIP_HAWAII_67B1, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67B8, PCI_CHIP_HAWAII_67B8, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67B9, PCI_CHIP_HAWAII_67B9, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67BA, PCI_CHIP_HAWAII_67BA, RES_SHARED_VGA }, { PCI_CHIP_HAWAII_67BE, PCI_CHIP_HAWAII_67BE, RES_SHARED_VGA }, { -1, -1, RES_UNDEFINED } }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_pci_device_match_gen.h000066400000000000000000000756351256524674500261150ustar00rootroot00000000000000/* This file is autogenerated please do not edit */ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3151, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3155, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E54, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS100_4136, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS200_4137, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_AD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_AE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_AF, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_AG, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_AH, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_AI, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_AJ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_AK, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_AP, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_AQ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV360_AR, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_AS, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_AT, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_4155, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_AV, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS250_4237, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R200_BB, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS100_4336, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS200_4337, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS250_4437, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV250_If, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ig, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JH, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JI, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JJ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JK, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JL, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JM, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JN, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_4A4F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JP, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R420_JT, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R481_4B48, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R481_4B49, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LW, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LX, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LY, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LZ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ld, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lf, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lg, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_4C6E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_ND, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_NE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_NF, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R300_NG, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_NH, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_NI, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R360_NJ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R350_NK, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NP, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NQ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NR, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NS, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NT, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV350_NV, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QF, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QG, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R200_QH, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R200_QL, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R200_QM, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV200_QW, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV200_QX, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV100_QY, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV100_QZ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RN50_515E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5460, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5462, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5464, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UH, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UI, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UJ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UK, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_554C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_554D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_554E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_554F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_5550, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UQ, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UR, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_UT, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_564A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_564B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS480_5955, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5960, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5961, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5962, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5964, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5965, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RN50_5969, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS482_5974, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS485_5975, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A41, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A42, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A61, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A62, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C63, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_5D48, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_5D49, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R430_5D4A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D50, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R480_5D52, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R423_5D57, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E48, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7100, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7101, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7102, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7103, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7104, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7105, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7106, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7108, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_7109, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_710A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_710B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_710C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_710E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R520_710F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7140, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7141, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7142, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7143, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7144, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7145, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7146, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7147, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7149, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_714F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7151, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7152, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7153, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_715E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_715F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7180, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7181, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7183, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7186, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7187, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7188, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_718A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_718B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_718C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_718D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_718F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7193, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7196, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_719B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_719F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C3, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C6, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7200, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7210, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV515_7211, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7245, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7246, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7247, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7248, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7249, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_724F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV570_7280, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7281, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7283, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7284, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7287, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV570_7288, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV570_7289, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV570_728B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV570_728C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7290, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7291, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7293, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV560_7297, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS350_7834, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS600_793F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS600_7941, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS600_7942, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS740_796F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_9400, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_9401, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_9402, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_9403, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_9405, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9441, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9443, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9444, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9446, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_944A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_944B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_944C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_944E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9450, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9452, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_945E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV790_9460, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV790_9462, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_947B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9480, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9488, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9489, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_948A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9491, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9495, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_949F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94A3, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B3, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV740_94B9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C6, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9504, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9506, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9508, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9509, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9517, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9519, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9542, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9555, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_9557, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV710_955F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9586, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9587, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9588, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9589, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C6, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CC, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9590, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9596, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9597, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9598, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9599, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9591, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9593, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_9595, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV635_959B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9610, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9615, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS780_9616, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9640, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9641, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9642, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9643, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9644, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9645, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9649, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9710, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9711, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS880_9715, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9802, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9803, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9804, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9805, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9806, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9807, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9808, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_9809, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PALM_980A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6898, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6899, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BF, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E5, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6700, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6701, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6702, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6703, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6704, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6705, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6706, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6707, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6708, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6709, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6718, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6719, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6720, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6721, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6722, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6723, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6724, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6725, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6726, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6727, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6728, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6729, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6738, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6739, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BARTS_673E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6740, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6741, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6742, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6743, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6744, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6745, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6746, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6747, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6748, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6749, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_674A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6750, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6751, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6758, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6759, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6840, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6841, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6842, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6843, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6849, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6850, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6858, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6859, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6760, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6761, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6762, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6763, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6764, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6765, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6766, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6767, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6768, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6770, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6771, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6772, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6778, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6779, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_677B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9900, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9901, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9903, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9904, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9905, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9906, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9907, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9908, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9909, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9910, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9913, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9917, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9918, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9919, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9990, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9991, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9992, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9993, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9994, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9995, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9996, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9997, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9998, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9999, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_999D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A4, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6780, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6784, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6788, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_678A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6790, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6791, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6792, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6798, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_6799, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_TAHITI_679F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6800, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6801, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6802, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6806, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6808, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6809, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6810, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6811, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6816, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6817, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6818, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_6819, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_PITCAIRN_684C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6820, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6821, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6822, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6823, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6824, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6825, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6826, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6827, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6828, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6829, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_682F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6830, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6831, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6835, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6837, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6838, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_6839, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_VERDE_683F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6600, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6601, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6602, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6603, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6604, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6605, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6606, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6607, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6608, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6610, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6611, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6613, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6617, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6620, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6621, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6623, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_OLAND_6631, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6660, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6663, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6664, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6665, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_6667, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAINAN_666F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6640, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6641, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6646, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6647, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6649, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6650, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6651, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_6658, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_BONAIRE_665F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9830, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9831, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9832, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9833, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9834, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9835, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9836, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9837, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9838, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_9839, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9850, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9851, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9852, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9853, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9854, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9855, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9856, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9857, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9858, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_9859, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1307, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1309, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1310, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1311, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1312, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1313, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1315, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1316, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1317, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1318, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67AA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B8, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B9, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BA, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BE, 0 ), { 0, 0, 0 } }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_present.c000066400000000000000000000304731256524674500234600ustar00rootroot00000000000000/* * Copyright © 2014 Intel Corporation * Copyright © 2015 Advanced Micro Devices, Inc. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of the copyright holders not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. The copyright holders make no representations * about the suitability of this software for any purpose. It is provided "as * is" without express or implied warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE * OF THIS SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "radeon.h" #ifdef HAVE_PRESENT_H #include #include #include #include #include #include #include #include #include #include #include #include #include "radeon_bo_helper.h" #include "radeon_glamor.h" #include "radeon_video.h" #include "present.h" struct radeon_present_vblank_event { uint64_t event_id; xf86CrtcPtr crtc; }; static uint32_t crtc_select(int crtc_id) { if (crtc_id > 1) return crtc_id << DRM_VBLANK_HIGH_CRTC_SHIFT; else if (crtc_id > 0) return DRM_VBLANK_SECONDARY; else return 0; } static RRCrtcPtr radeon_present_get_crtc(WindowPtr window) { ScreenPtr screen = window->drawable.pScreen; ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); xf86CrtcPtr crtc; RRCrtcPtr randr_crtc = NULL; crtc = radeon_pick_best_crtc(pScrn, FALSE, window->drawable.x, window->drawable.x + window->drawable.width, window->drawable.y, window->drawable.y + window->drawable.height); /* Make sure the CRTC is valid and this is the real front buffer */ if (crtc != NULL && !crtc->rotatedData) randr_crtc = crtc->randr_crtc; return randr_crtc; } static int radeon_present_get_ust_msc(RRCrtcPtr crtc, CARD64 *ust, CARD64 *msc) { xf86CrtcPtr xf86_crtc = crtc->devPrivate; drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; if (drmmode_crtc->dpms_mode != DPMSModeOn) return BadAlloc; return drmmode_crtc_get_ust_msc(xf86_crtc, ust, msc); } /* * Flush the DRM event queue when full; this * makes space for new requests */ static Bool radeon_present_flush_drm_events(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[0]->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; struct pollfd p = { .fd = drmmode->fd, .events = POLLIN }; int r; do { r = poll(&p, 1, 0); } while (r == -1 && (errno == EINTR || errno == EAGAIN)); if (r <= 0) return 0; return drmHandleEvent(drmmode->fd, &drmmode->event_context) >= 0; } /* * Called when the queued vblank event has occurred */ static void radeon_present_vblank_handler(ScrnInfoPtr scrn, unsigned int msc, uint64_t usec, void *data) { struct radeon_present_vblank_event *event = data; present_event_notify(event->event_id, usec, msc); free(event); } /* * Called when the queued vblank is aborted */ static void radeon_present_vblank_abort(ScrnInfoPtr scrn, void *data) { struct radeon_present_vblank_event *event = data; free(event); } /* * Queue an event to report back to the Present extension when the specified * MSC has past */ static int radeon_present_queue_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc) { xf86CrtcPtr xf86_crtc = crtc->devPrivate; ScreenPtr screen = crtc->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); int crtc_id = drmmode_get_crtc_id(xf86_crtc); struct radeon_present_vblank_event *event; struct radeon_drm_queue_entry *queue; drmVBlank vbl; int ret; event = calloc(sizeof(struct radeon_present_vblank_event), 1); if (!event) return BadAlloc; event->event_id = event_id; queue = radeon_drm_queue_alloc(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, event_id, event, radeon_present_vblank_handler, radeon_present_vblank_abort); if (!queue) { free(event); return BadAlloc; } vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT | crtc_select(crtc_id); vbl.request.sequence = msc; vbl.request.signal = (unsigned long)queue; for (;;) { ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (!ret) break; if (errno != EBUSY || !radeon_present_flush_drm_events(screen)) { radeon_drm_abort_entry(queue); return BadAlloc; } } return Success; } /* * Remove a pending vblank event from the DRM queue so that it is not reported * to the extension */ static void radeon_present_abort_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc) { radeon_drm_abort_id(event_id); } /* * Flush our batch buffer when requested by the Present extension. */ static void radeon_present_flush(WindowPtr window) { radeon_cs_flush_indirect(xf86ScreenToScrn(window->drawable.pScreen)); } static uint32_t radeon_present_get_pixmap_tiling_flags(RADEONInfoPtr info, PixmapPtr pixmap) { uint32_t tiling_flags = radeon_get_pixmap_tiling_flags(pixmap); /* Micro tiling is always enabled with macro tiling on >= R600, so we * can ignore the micro tiling bit in that case */ if ((tiling_flags & RADEON_TILING_MACRO) && info->ChipFamily >= CHIP_FAMILY_R600) tiling_flags &= ~RADEON_TILING_MICRO; return tiling_flags; } /* * Test to see if page flipping is possible on the target crtc */ static Bool radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap, Bool sync_flip) { ScreenPtr screen = window->drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); PixmapPtr screen_pixmap; xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); int num_crtcs_on; int i; if (!scrn->vtSema) return FALSE; if (!info->allowPageFlip) return FALSE; if (!sync_flip) return FALSE; if (info->drmmode.dri2_flipping) return FALSE; /* The kernel driver doesn't handle flipping between BOs with different * tiling parameters correctly yet */ screen_pixmap = screen->GetScreenPixmap(screen); if (radeon_present_get_pixmap_tiling_flags(info, pixmap) != radeon_present_get_pixmap_tiling_flags(info, screen_pixmap)) return FALSE; for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) { drmmode_crtc_private_ptr drmmode_crtc = config->crtc[i]->driver_private; if (!config->crtc[i]->enabled) continue; if (!drmmode_crtc || drmmode_crtc->rotate.bo != NULL) return FALSE; if (drmmode_crtc->dpms_mode == DPMSModeOn) num_crtcs_on++; } return num_crtcs_on > 0; } /* * Once the flip has been completed on all CRTCs, notify the * extension code telling it when that happened */ static void radeon_present_flip_event(ScrnInfoPtr scrn, uint32_t msc, uint64_t ust, void *pageflip_data) { RADEONInfoPtr info = RADEONPTR(scrn); struct radeon_present_vblank_event *event = pageflip_data; if (!event->crtc) info->drmmode.present_flipping = FALSE; present_event_notify(event->event_id, ust, msc); free(event); } /* * The flip has been aborted, free the structure */ static void radeon_present_flip_abort(ScrnInfoPtr scrn, void *pageflip_data) { struct radeon_present_vblank_event *event = pageflip_data; free(event); } /* * Queue a flip on 'crtc' to 'pixmap' at 'target_msc'. If 'sync_flip' is true, * then wait for vblank. Otherwise, flip immediately */ static Bool radeon_present_flip(RRCrtcPtr crtc, uint64_t event_id, uint64_t target_msc, PixmapPtr pixmap, Bool sync_flip) { ScreenPtr screen = crtc->pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); struct radeon_present_vblank_event *event; xf86CrtcPtr xf86_crtc = crtc->devPrivate; int crtc_id = xf86_crtc ? drmmode_get_crtc_id(xf86_crtc) : -1; uint32_t handle; Bool ret; if (!radeon_present_check_flip(crtc, screen->root, pixmap, sync_flip)) return FALSE; if (!radeon_get_pixmap_handle(pixmap, &handle)) return FALSE; event = calloc(1, sizeof(struct radeon_present_vblank_event)); if (!event) return FALSE; event->event_id = event_id; event->crtc = xf86_crtc; ret = radeon_do_pageflip(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, handle, event_id, event, crtc_id, radeon_present_flip_event, radeon_present_flip_abort); if (!ret) xf86DrvMsg(scrn->scrnIndex, X_ERROR, "present flip failed\n"); else info->drmmode.present_flipping = TRUE; return ret; } /* * Queue a flip back to the normal frame buffer */ static void radeon_present_unflip(ScreenPtr screen, uint64_t event_id) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); struct radeon_present_vblank_event *event; PixmapPtr pixmap = screen->GetScreenPixmap(screen); uint32_t handle; int i; if (!radeon_present_check_flip(NULL, screen->root, pixmap, TRUE)) goto modeset; if (!radeon_get_pixmap_handle(pixmap, &handle)) { ErrorF("%s: radeon_get_pixmap_handle failed, display might freeze\n", __func__); goto modeset; } event = calloc(1, sizeof(struct radeon_present_vblank_event)); if (!event) { ErrorF("%s: calloc failed, display might freeze\n", __func__); goto modeset; } event->event_id = event_id; if (radeon_do_pageflip(scrn, RADEON_DRM_QUEUE_CLIENT_DEFAULT, handle, event_id, event, -1, radeon_present_flip_event, radeon_present_flip_abort)) return; modeset: for (i = 0; i < config->num_crtc; i++) { xf86CrtcPtr crtc = config->crtc[i]; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; if (!crtc->enabled) continue; if (drmmode_crtc->dpms_mode == DPMSModeOn) crtc->funcs->set_mode_major(crtc, &crtc->mode, crtc->rotation, crtc->x, crtc->y); else drmmode_crtc->need_modeset = TRUE; } present_event_notify(event_id, 0, 0); info->drmmode.present_flipping = FALSE; } static present_screen_info_rec radeon_present_screen_info = { .version = 0, .get_crtc = radeon_present_get_crtc, .get_ust_msc = radeon_present_get_ust_msc, .queue_vblank = radeon_present_queue_vblank, .abort_vblank = radeon_present_abort_vblank, .flush = radeon_present_flush, .capabilities = PresentCapabilityNone, .check_flip = radeon_present_check_flip, .flip = radeon_present_flip, .unflip = radeon_present_unflip, }; static Bool radeon_present_has_async_flip(ScreenPtr screen) { #ifdef DRM_CAP_ASYNC_PAGE_FLIP ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); int ret; uint64_t value; ret = drmGetCap(info->dri2.drm_fd, DRM_CAP_ASYNC_PAGE_FLIP, &value); if (ret == 0) return value == 1; #endif return FALSE; } Bool radeon_present_screen_init(ScreenPtr screen) { if (radeon_present_has_async_flip(screen)) radeon_present_screen_info.capabilities |= PresentCapabilityAsync; if (!present_screen_init(screen, &radeon_present_screen_info)) { xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_WARNING, "Present extension disabled because present_screen_init failed\n"); return FALSE; } xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO, "Present extension enabled\n"); return TRUE; } #else /* !HAVE_PRESENT_H */ Bool radeon_present_screen_init(ScreenPtr screen) { xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO, "Present extension disabled because present.h not available at " "build time\n"); return FALSE; } #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_probe.c000066400000000000000000000174351256524674500231120ustar00rootroot00000000000000/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include /* * Authors: * Kevin E. Martin * Rickard E. Faith * KMS support - Dave Airlie */ #include "radeon_probe.h" #include "radeon_version.h" #include "atipciids.h" #include "atipcirename.h" #include "xf86.h" #include "xf86drmMode.h" #include "dri.h" #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) #include #endif #ifdef XSERVER_PLATFORM_BUS #include #endif #include "radeon_chipset_gen.h" #include "radeon_pci_chipset_gen.h" #include "radeon_pci_device_match_gen.h" _X_EXPORT int gRADEONEntityIndex = -1; /* Return the options for supported chipset 'n'; NULL otherwise */ static const OptionInfoRec * RADEONAvailableOptions(int chipid, int busid) { return RADEONOptionsWeak(); } /* Return the string name for supported chipset 'n'; NULL otherwise. */ static void RADEONIdentify(int flags) { xf86PrintChipsets(RADEON_NAME, "Driver for ATI Radeon chipsets", RADEONChipsets); } static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci_dev) { char *busIdString; int ret; if (!xf86LoaderCheckSymbol("DRICreatePCIBusID")) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0, "[KMS] No DRICreatePCIBusID symbol, no kernel modesetting.\n"); return FALSE; } busIdString = DRICreatePCIBusID(pci_dev); ret = drmCheckModesettingSupported(busIdString); #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) if (ret) { if (xf86LoadKernelModule("radeonkms")) ret = drmCheckModesettingSupported(busIdString); } #endif free(busIdString); if (ret) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0, "[KMS] drm report modesetting isn't supported.\n"); return FALSE; } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0, "[KMS] Kernel modesetting enabled.\n"); return TRUE; } static Bool radeon_get_scrninfo(int entity_num, void *pci_dev) { ScrnInfoPtr pScrn = NULL; EntityInfoPtr pEnt; pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets, NULL, NULL, NULL, NULL, NULL); if (!pScrn) return FALSE; if (pci_dev) { if (!radeon_kernel_mode_enabled(pScrn, pci_dev)) { return FALSE; } } pScrn->driverVersion = RADEON_VERSION_CURRENT; pScrn->driverName = RADEON_DRIVER_NAME; pScrn->name = RADEON_NAME; pScrn->Probe = NULL; pScrn->PreInit = RADEONPreInit_KMS; pScrn->ScreenInit = RADEONScreenInit_KMS; pScrn->SwitchMode = RADEONSwitchMode_KMS; pScrn->AdjustFrame = RADEONAdjustFrame_KMS; pScrn->EnterVT = RADEONEnterVT_KMS; pScrn->LeaveVT = RADEONLeaveVT_KMS; pScrn->FreeScreen = RADEONFreeScreen_KMS; pScrn->ValidMode = RADEONValidMode; pEnt = xf86GetEntityInfo(entity_num); /* Create a RADEONEntity for all chips, even with old single head * Radeon, need to use pRADEONEnt for new monitor detection routines. */ { DevUnion *pPriv; xf86SetEntitySharable(entity_num); if (gRADEONEntityIndex == -1) gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); xf86SetEntityInstanceForScreen(pScrn, pEnt->index, xf86GetNumEntityInstances(pEnt->index) - 1); if (!pPriv->ptr) pPriv->ptr = xnfcalloc(sizeof(RADEONEntRec), 1); } free(pEnt); return TRUE; } static Bool radeon_pci_probe( DriverPtr pDriver, int entity_num, struct pci_device *device, intptr_t match_data ) { return radeon_get_scrninfo(entity_num, (void *)device); } static Bool RADEONDriverFunc(ScrnInfoPtr scrn, xorgDriverFuncOp op, void *data) { xorgHWFlags *flag; switch (op) { case GET_REQUIRED_HW_INTERFACES: flag = (CARD32 *)data; (*flag) = 0; return TRUE; #if XORG_VERSION_CURRENT > XORG_VERSION_NUMERIC(1,15,99,0,0) case SUPPORTS_SERVER_FDS: return TRUE; #endif default: return FALSE; } } #ifdef XSERVER_PLATFORM_BUS static Bool radeon_platform_probe(DriverPtr pDriver, int entity_num, int flags, struct xf86_platform_device *dev, intptr_t match_data) { ScrnInfoPtr pScrn; int scr_flags = 0; EntityInfoPtr pEnt; if (!dev->pdev) return FALSE; if (flags & PLATFORM_PROBE_GPU_SCREEN) scr_flags = XF86_ALLOCATE_GPU_SCREEN; pScrn = xf86AllocateScreen(pDriver, scr_flags); if (xf86IsEntitySharable(entity_num)) xf86SetEntityShared(entity_num); xf86AddEntityToScreen(pScrn, entity_num); if (!radeon_kernel_mode_enabled(pScrn, dev->pdev)) return FALSE; pScrn->driverVersion = RADEON_VERSION_CURRENT; pScrn->driverName = RADEON_DRIVER_NAME; pScrn->name = RADEON_NAME; pScrn->Probe = NULL; pScrn->PreInit = RADEONPreInit_KMS; pScrn->ScreenInit = RADEONScreenInit_KMS; pScrn->SwitchMode = RADEONSwitchMode_KMS; pScrn->AdjustFrame = RADEONAdjustFrame_KMS; pScrn->EnterVT = RADEONEnterVT_KMS; pScrn->LeaveVT = RADEONLeaveVT_KMS; pScrn->FreeScreen = RADEONFreeScreen_KMS; pScrn->ValidMode = RADEONValidMode; pEnt = xf86GetEntityInfo(entity_num); /* Create a RADEONEntity for all chips, even with old single head * Radeon, need to use pRADEONEnt for new monitor detection routines. */ { DevUnion *pPriv; RADEONEntPtr pRADEONEnt; xf86SetEntitySharable(entity_num); if (gRADEONEntityIndex == -1) gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); xf86SetEntityInstanceForScreen(pScrn, pEnt->index, xf86GetNumEntityInstances(pEnt->index) - 1); if (!pPriv->ptr) { pPriv->ptr = xnfcalloc(sizeof(RADEONEntRec), 1); pRADEONEnt = pPriv->ptr; } else { pRADEONEnt = pPriv->ptr; } pRADEONEnt->platform_dev = dev; } free(pEnt); return TRUE; } #endif _X_EXPORT DriverRec RADEON = { RADEON_VERSION_CURRENT, RADEON_DRIVER_NAME, RADEONIdentify, NULL, RADEONAvailableOptions, NULL, 0, RADEONDriverFunc, radeon_device_match, radeon_pci_probe, #ifdef XSERVER_PLATFORM_BUS radeon_platform_probe #endif }; xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_probe.h000066400000000000000000000116561256524674500231160ustar00rootroot00000000000000/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin * * Modified by Marc Aurele La France for ATI driver merge. */ #ifndef _RADEON_PROBE_H_ #define _RADEON_PROBE_H_ 1 #include #include "xorg-server.h" #include "xf86str.h" #include "xf86DDC.h" #include "randrstr.h" #include "xf86Crtc.h" #ifdef XSERVER_PLATFORM_BUS #include "xf86platformBus.h" #endif #include "compat-api.h" #include "exa.h" extern DriverRec RADEON; typedef enum { CHIP_FAMILY_UNKNOW, CHIP_FAMILY_LEGACY, CHIP_FAMILY_RADEON, CHIP_FAMILY_RV100, CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ CHIP_FAMILY_RV200, CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ CHIP_FAMILY_R200, CHIP_FAMILY_RV250, CHIP_FAMILY_RS300, /* RS300/RS350 */ CHIP_FAMILY_RV280, CHIP_FAMILY_R300, CHIP_FAMILY_R350, CHIP_FAMILY_RV350, CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ CHIP_FAMILY_R420, /* R420/R423/M18 */ CHIP_FAMILY_RV410, /* RV410, M26 */ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ CHIP_FAMILY_RV515, /* rv515 */ CHIP_FAMILY_R520, /* r520 */ CHIP_FAMILY_RV530, /* rv530 */ CHIP_FAMILY_R580, /* r580 */ CHIP_FAMILY_RV560, /* rv560 */ CHIP_FAMILY_RV570, /* rv570 */ CHIP_FAMILY_RS600, CHIP_FAMILY_RS690, CHIP_FAMILY_RS740, CHIP_FAMILY_R600, /* r600 */ CHIP_FAMILY_RV610, CHIP_FAMILY_RV630, CHIP_FAMILY_RV670, CHIP_FAMILY_RV620, CHIP_FAMILY_RV635, CHIP_FAMILY_RS780, CHIP_FAMILY_RS880, CHIP_FAMILY_RV770, /* r700 */ CHIP_FAMILY_RV730, CHIP_FAMILY_RV710, CHIP_FAMILY_RV740, CHIP_FAMILY_CEDAR, /* evergreen */ CHIP_FAMILY_REDWOOD, CHIP_FAMILY_JUNIPER, CHIP_FAMILY_CYPRESS, CHIP_FAMILY_HEMLOCK, CHIP_FAMILY_PALM, CHIP_FAMILY_SUMO, CHIP_FAMILY_SUMO2, CHIP_FAMILY_BARTS, CHIP_FAMILY_TURKS, CHIP_FAMILY_CAICOS, CHIP_FAMILY_CAYMAN, CHIP_FAMILY_ARUBA, CHIP_FAMILY_TAHITI, CHIP_FAMILY_PITCAIRN, CHIP_FAMILY_VERDE, CHIP_FAMILY_OLAND, CHIP_FAMILY_HAINAN, CHIP_FAMILY_BONAIRE, CHIP_FAMILY_KAVERI, CHIP_FAMILY_KABINI, CHIP_FAMILY_HAWAII, CHIP_FAMILY_MULLINS, CHIP_FAMILY_LAST } RADEONChipFamily; typedef struct { uint32_t pci_device_id; RADEONChipFamily chip_family; int mobility; int igp; int nocrtc2; int nointtvout; int singledac; } RADEONCardInfo; typedef struct { Bool HasCRTC2; /* All cards except original Radeon */ int fd; /* for sharing across zaphod heads */ int fd_ref; unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */ int fd_wakeup_ref; unsigned int assigned_crtcs; #ifdef XSERVER_PLATFORM_BUS struct xf86_platform_device *platform_dev; #endif } RADEONEntRec, *RADEONEntPtr; extern const OptionInfoRec *RADEONOptionsWeak(void); extern Bool RADEONPreInit_KMS(ScrnInfoPtr, int); extern Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL); extern Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL); extern void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL); extern Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL); extern void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL); extern void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL); extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, Bool verbose, int flag); #endif /* _RADEON_PROBE_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_reg.h000066400000000000000000011021151256524674500225540ustar00rootroot00000000000000/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin * Rickard E. Faith * Alan Hourihane * * References: * * !!!! FIXME !!!! * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April * 1999. * * !!!! FIXME !!!! * RAGE 128 Software Development Manual (Technical Reference Manual P/N * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * */ /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ #ifndef _RADEON_REG_H_ #define _RADEON_REG_H_ #define ATI_DATATYPE_VQ 0 #define ATI_DATATYPE_CI4 1 #define ATI_DATATYPE_CI8 2 #define ATI_DATATYPE_ARGB1555 3 #define ATI_DATATYPE_RGB565 4 #define ATI_DATATYPE_RGB888 5 #define ATI_DATATYPE_ARGB8888 6 #define ATI_DATATYPE_RGB332 7 #define ATI_DATATYPE_Y8 8 #define ATI_DATATYPE_RGB8 9 #define ATI_DATATYPE_CI16 10 #define ATI_DATATYPE_VYUY_422 11 #define ATI_DATATYPE_YVYU_422 12 #define ATI_DATATYPE_AYUV_444 14 #define ATI_DATATYPE_ARGB4444 15 /* Registers for 2D/Video/Overlay */ #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ #define RADEON_AGP_BASE 0x0170 #define RADEON_AGP_CNTL 0x0174 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) #define RADEON_STATUS_PCI_CONFIG 0x06 # define RADEON_CAP_LIST 0x100000 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ # define RADEON_AGP_ENABLE (1<<8) #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ #define RADEON_AGP_STATUS 0x0f5c /* PCI */ # define RADEON_AGP_1X_MODE 0x01 # define RADEON_AGP_2X_MODE 0x02 # define RADEON_AGP_4X_MODE 0x04 # define RADEON_AGP_FW_MODE 0x10 # define RADEON_AGP_MODE_MASK 0x17 # define RADEON_AGPv3_MODE 0x08 # define RADEON_AGPv3_4X_MODE 0x01 # define RADEON_AGPv3_8X_MODE 0x02 #define RADEON_ATTRDR 0x03c1 /* VGA */ #define RADEON_ATTRDW 0x03c0 /* VGA */ #define RADEON_ATTRX 0x03c0 /* VGA */ #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc #define RADEON_BASE_CODE 0x0f0b #define RADEON_BIOS_0_SCRATCH 0x0010 # define RADEON_FP_PANEL_SCALABLE (1 << 16) # define RADEON_FP_PANEL_SCALE_EN (1 << 17) # define RADEON_FP_CHIP_SCALE_EN (1 << 18) # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) # define RADEON_DISPLAY_ROT_MASK (3 << 28) # define RADEON_DISPLAY_ROT_00 (0 << 28) # define RADEON_DISPLAY_ROT_90 (1 << 28) # define RADEON_DISPLAY_ROT_180 (2 << 28) # define RADEON_DISPLAY_ROT_270 (3 << 28) #define RADEON_BIOS_1_SCRATCH 0x0014 #define RADEON_BIOS_2_SCRATCH 0x0018 #define RADEON_BIOS_3_SCRATCH 0x001c #define RADEON_BIOS_4_SCRATCH 0x0020 # define RADEON_CRT1_ATTACHED_MASK (3 << 0) # define RADEON_CRT1_ATTACHED_MONO (1 << 0) # define RADEON_CRT1_ATTACHED_COLOR (2 << 0) # define RADEON_LCD1_ATTACHED (1 << 2) # define RADEON_DFP1_ATTACHED (1 << 3) # define RADEON_TV1_ATTACHED_MASK (3 << 4) # define RADEON_TV1_ATTACHED_COMP (1 << 4) # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) # define RADEON_CRT2_ATTACHED_MASK (3 << 8) # define RADEON_CRT2_ATTACHED_MONO (1 << 8) # define RADEON_CRT2_ATTACHED_COLOR (2 << 8) # define RADEON_DFP2_ATTACHED (1 << 11) #define RADEON_BIOS_5_SCRATCH 0x0024 # define RADEON_LCD1_ON (1 << 0) # define RADEON_CRT1_ON (1 << 1) # define RADEON_TV1_ON (1 << 2) # define RADEON_DFP1_ON (1 << 3) # define RADEON_CRT2_ON (1 << 5) # define RADEON_CV1_ON (1 << 6) # define RADEON_DFP2_ON (1 << 7) # define RADEON_LCD1_CRTC_MASK (1 << 8) # define RADEON_LCD1_CRTC_SHIFT 8 # define RADEON_CRT1_CRTC_MASK (1 << 9) # define RADEON_CRT1_CRTC_SHIFT 9 # define RADEON_TV1_CRTC_MASK (1 << 10) # define RADEON_TV1_CRTC_SHIFT 10 # define RADEON_DFP1_CRTC_MASK (1 << 11) # define RADEON_DFP1_CRTC_SHIFT 11 # define RADEON_CRT2_CRTC_MASK (1 << 12) # define RADEON_CRT2_CRTC_SHIFT 12 # define RADEON_CV1_CRTC_MASK (1 << 13) # define RADEON_CV1_CRTC_SHIFT 13 # define RADEON_DFP2_CRTC_MASK (1 << 14) # define RADEON_DFP2_CRTC_SHIFT 14 #define RADEON_BIOS_6_SCRATCH 0x0028 # define RADEON_ACC_MODE_CHANGE (1 << 2) # define RADEON_EXT_DESKTOP_MODE (1 << 3) # define RADEON_LCD_DPMS_ON (1 << 20) # define RADEON_CRT_DPMS_ON (1 << 21) # define RADEON_TV_DPMS_ON (1 << 22) # define RADEON_DFP_DPMS_ON (1 << 23) # define RADEON_DPMS_MASK (3 << 24) # define RADEON_DPMS_ON (0 << 24) # define RADEON_DPMS_STANDBY (1 << 24) # define RADEON_DPMS_SUSPEND (2 << 24) # define RADEON_DPMS_OFF (3 << 24) # define RADEON_SCREEN_BLANKING (1 << 26) # define RADEON_DRIVER_CRITICAL (1 << 27) # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) #define RADEON_BIOS_7_SCRATCH 0x002c # define RADEON_SYS_HOTKEY (1 << 10) # define RADEON_DRV_LOADED (1 << 12) #define RADEON_BIOS_ROM 0x0f30 /* PCI */ #define RADEON_BIST 0x0f0f /* PCI */ #define RADEON_BRUSH_DATA0 0x1480 #define RADEON_BRUSH_DATA1 0x1484 #define RADEON_BRUSH_DATA10 0x14a8 #define RADEON_BRUSH_DATA11 0x14ac #define RADEON_BRUSH_DATA12 0x14b0 #define RADEON_BRUSH_DATA13 0x14b4 #define RADEON_BRUSH_DATA14 0x14b8 #define RADEON_BRUSH_DATA15 0x14bc #define RADEON_BRUSH_DATA16 0x14c0 #define RADEON_BRUSH_DATA17 0x14c4 #define RADEON_BRUSH_DATA18 0x14c8 #define RADEON_BRUSH_DATA19 0x14cc #define RADEON_BRUSH_DATA2 0x1488 #define RADEON_BRUSH_DATA20 0x14d0 #define RADEON_BRUSH_DATA21 0x14d4 #define RADEON_BRUSH_DATA22 0x14d8 #define RADEON_BRUSH_DATA23 0x14dc #define RADEON_BRUSH_DATA24 0x14e0 #define RADEON_BRUSH_DATA25 0x14e4 #define RADEON_BRUSH_DATA26 0x14e8 #define RADEON_BRUSH_DATA27 0x14ec #define RADEON_BRUSH_DATA28 0x14f0 #define RADEON_BRUSH_DATA29 0x14f4 #define RADEON_BRUSH_DATA3 0x148c #define RADEON_BRUSH_DATA30 0x14f8 #define RADEON_BRUSH_DATA31 0x14fc #define RADEON_BRUSH_DATA32 0x1500 #define RADEON_BRUSH_DATA33 0x1504 #define RADEON_BRUSH_DATA34 0x1508 #define RADEON_BRUSH_DATA35 0x150c #define RADEON_BRUSH_DATA36 0x1510 #define RADEON_BRUSH_DATA37 0x1514 #define RADEON_BRUSH_DATA38 0x1518 #define RADEON_BRUSH_DATA39 0x151c #define RADEON_BRUSH_DATA4 0x1490 #define RADEON_BRUSH_DATA40 0x1520 #define RADEON_BRUSH_DATA41 0x1524 #define RADEON_BRUSH_DATA42 0x1528 #define RADEON_BRUSH_DATA43 0x152c #define RADEON_BRUSH_DATA44 0x1530 #define RADEON_BRUSH_DATA45 0x1534 #define RADEON_BRUSH_DATA46 0x1538 #define RADEON_BRUSH_DATA47 0x153c #define RADEON_BRUSH_DATA48 0x1540 #define RADEON_BRUSH_DATA49 0x1544 #define RADEON_BRUSH_DATA5 0x1494 #define RADEON_BRUSH_DATA50 0x1548 #define RADEON_BRUSH_DATA51 0x154c #define RADEON_BRUSH_DATA52 0x1550 #define RADEON_BRUSH_DATA53 0x1554 #define RADEON_BRUSH_DATA54 0x1558 #define RADEON_BRUSH_DATA55 0x155c #define RADEON_BRUSH_DATA56 0x1560 #define RADEON_BRUSH_DATA57 0x1564 #define RADEON_BRUSH_DATA58 0x1568 #define RADEON_BRUSH_DATA59 0x156c #define RADEON_BRUSH_DATA6 0x1498 #define RADEON_BRUSH_DATA60 0x1570 #define RADEON_BRUSH_DATA61 0x1574 #define RADEON_BRUSH_DATA62 0x1578 #define RADEON_BRUSH_DATA63 0x157c #define RADEON_BRUSH_DATA7 0x149c #define RADEON_BRUSH_DATA8 0x14a0 #define RADEON_BRUSH_DATA9 0x14a4 #define RADEON_BRUSH_SCALE 0x1470 #define RADEON_BRUSH_Y_X 0x1474 #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) # define RADEON_BUS_BIOS_DIS_ROM (1 << 12) # define RADEON_BUS_RD_DISCARD_EN (1 << 24) # define RADEON_BUS_RD_ABORT_EN (1 << 25) # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) # define RADEON_BUS_WRT_BURST (1 << 29) # define RADEON_BUS_READ_BURST (1 << 30) #define RADEON_BUS_CNTL1 0x0034 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) #define RADEON_PCIE_INDEX 0x0030 #define RADEON_PCIE_DATA 0x0034 #define R600_PCIE_PORT_INDEX 0x0038 #define R600_PCIE_PORT_DATA 0x003c /* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */ #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 # define RADEON_PCIE_LC_LINK_WIDTH_X0 0 # define RADEON_PCIE_LC_LINK_WIDTH_X1 1 # define RADEON_PCIE_LC_LINK_WIDTH_X2 2 # define RADEON_PCIE_LC_LINK_WIDTH_X4 3 # define RADEON_PCIE_LC_LINK_WIDTH_X8 4 # define RADEON_PCIE_LC_LINK_WIDTH_X12 5 # define RADEON_PCIE_LC_LINK_WIDTH_X16 6 # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 # define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) # define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) # define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) #define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c #define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ # define RADEON_DONT_USE_XTALIN (1 << 4) # define RADEON_SCLK_DYN_START_CNTL (1 << 15) #define RADEON_CLOCK_CNTL_DATA 0x000c #define RADEON_CLOCK_CNTL_INDEX 0x0008 # define RADEON_PLL_WR_EN (1 << 7) # define RADEON_PLL_DIV_SEL (3 << 8) # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) #define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ # define RADEON_M_SPLL_REF_DIV_MASK 0xff # define RADEON_M_SPLL_REF_DIV_SHIFT 0 # define RADEON_MPLL_FB_DIV_MASK 0xff # define RADEON_MPLL_FB_DIV_SHIFT 8 # define RADEON_SPLL_FB_DIV_MASK 0xff # define RADEON_SPLL_FB_DIV_SHIFT 16 #define RADEON_SPLL_CNTL 0x000c /* PLL */ # define RADEON_SPLL_SLEEP (1 << 0) # define RADEON_SPLL_RESET (1 << 1) # define RADEON_SPLL_PCP_MASK 0x7 # define RADEON_SPLL_PCP_SHIFT 8 # define RADEON_SPLL_PVG_MASK 0x7 # define RADEON_SPLL_PVG_SHIFT 11 # define RADEON_SPLL_PDC_MASK 0x3 # define RADEON_SPLL_PDC_SHIFT 14 #define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */ # define RADEON_ENGIN_DYNCLK_MODE (1 << 12) # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) # define RADEON_ACTIVE_HILO_LAT_SHIFT 13 # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) # define RADEON_MC_BUSY (1 << 16) # define RADEON_DLL_READY (1 << 19) # define RADEON_CG_NO1_DEBUG_0 (1 << 24) # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) # define RADEON_DYN_STOP_MODE_MASK (7 << 21) # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) # define RADEON_TVCLK_TURNOFF (1 << 31) #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ # define RADEON_TCL_BYPASS_DISABLE (1 << 20) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8 #define RADEON_CLR_CMP_CLR_SRC 0x15c4 #define RADEON_CLR_CMP_CNTL 0x15c0 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) #define RADEON_CLR_CMP_MASK 0x15cc # define RADEON_CLR_CMP_MSK 0xffffffff #define RADEON_CLR_CMP_MASK_3D 0x1A28 #define RADEON_COMMAND 0x0f04 /* PCI */ #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c #define RADEON_CONFIG_APER_0_BASE 0x0100 #define RADEON_CONFIG_APER_1_BASE 0x0104 #define RADEON_CONFIG_APER_SIZE 0x0108 #define RADEON_CONFIG_BONDS 0x00e8 #define RADEON_CONFIG_CNTL 0x00e0 # define RADEON_CFG_ATI_REV_A11 (0 << 16) # define RADEON_CFG_ATI_REV_A12 (1 << 16) # define RADEON_CFG_ATI_REV_A13 (2 << 16) # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) #define RADEON_CONFIG_MEMSIZE 0x00f8 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 #define RADEON_CONFIG_REG_1_BASE 0x010c #define RADEON_CONFIG_REG_APER_SIZE 0x0110 #define RADEON_CONFIG_XSTRAP 0x00e4 #define RADEON_CONSTANT_COLOR_C 0x1d34 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 #define RADEON_CRC_CMDFIFO_ADDR 0x0740 #define RADEON_CRC_CMDFIFO_DOUT 0x0744 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 # define RADEON_GRPH_START_REQ_MASK (0x7f) # define RADEON_GRPH_START_REQ_SHIFT 0 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH_STOP_REQ_SHIFT 8 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH_CRITICAL_CNTL (1<<28) # define RADEON_GRPH_BUFFER_SIZE (1<<29) # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH_STOP_CNTL (1<<31) #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 # define RADEON_GRPH2_START_REQ_MASK (0x7f) # define RADEON_GRPH2_START_REQ_SHIFT 0 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH2_STOP_REQ_SHIFT 8 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) # define RADEON_GRPH2_BUFFER_SIZE (1<<29) # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH2_STOP_CNTL (1<<31) #define RADEON_CRTC_CRNT_FRAME 0x0214 #define RADEON_CRTC_EXT_CNTL 0x0054 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) # define RADEON_VGA_ATI_LINEAR (1 << 3) # define RADEON_XCRT_CNT_EN (1 << 6) # define RADEON_CRTC_HSYNC_DIS (1 << 8) # define RADEON_CRTC_VSYNC_DIS (1 << 9) # define RADEON_CRTC_DISPLAY_DIS (1 << 10) # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) # define RADEON_CRTC_CRT_ON (1 << 15) #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) #define RADEON_CRTC_GEN_CNTL 0x0050 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC_INTERLACE_EN (1 << 1) # define RADEON_CRTC_CSYNC_EN (1 << 4) # define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) #define RADEON_CRTC2_GEN_CNTL 0x03f8 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC2_INTERLACE_EN (1 << 1) # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) # define RADEON_CRTC2_CRT2_ON (1 << 7) # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) # define RADEON_CRTC2_ICON_EN (1 << 15) # define RADEON_CRTC2_CUR_EN (1 << 16) # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC2_DISP_DIS (1 << 23) # define RADEON_CRTC2_EN (1 << 25) # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) # define RADEON_CRTC2_CSYNC_EN (1 << 27) # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) #define RADEON_CRTC_MORE_CNTL 0x27c # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 # define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0 # define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15) # define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16 # define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30) #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC_H_SYNC_POL (1 << 23) #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_H_SYNC_POL (1 << 23) #define RADEON_CRTC_H_TOTAL_DISP 0x0200 # define RADEON_CRTC_H_TOTAL (0x03ff << 0) # define RADEON_CRTC_H_TOTAL_SHIFT 0 # define RADEON_CRTC_H_DISP (0x01ff << 16) # define RADEON_CRTC_H_DISP_SHIFT 16 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) # define RADEON_CRTC2_H_TOTAL_SHIFT 0 # define RADEON_CRTC2_H_DISP (0x01ff << 16) # define RADEON_CRTC2_H_DISP_SHIFT 16 #define RADEON_CRTC_OFFSET_RIGHT 0x0220 #define RADEON_CRTC_OFFSET 0x0224 # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) #define RADEON_CRTC2_OFFSET 0x0324 # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) #define RADEON_CRTC_OFFSET_CNTL 0x0228 # define RADEON_CRTC_TILE_LINE_SHIFT 0 # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) # define R300_CRTC_X_Y_MODE_EN (1 << 9) # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) # define R300_CRTC_MICRO_TILE_EN (1 << 13) # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) # define R300_CRTC_MACRO_TILE_EN (1 << 15) # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) # define RADEON_CRTC_TILE_EN (1 << 15) # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) #define R300_CRTC_TILE_X0_Y0 0x0350 #define R300_CRTC2_TILE_X0_Y0 0x0358 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC2_TILE_EN (1 << 15) #define RADEON_CRTC_PITCH 0x022c # define RADEON_CRTC_PITCH__SHIFT 0 # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 #define RADEON_CRTC2_PITCH 0x032c #define RADEON_CRTC_STATUS 0x005c # define RADEON_CRTC_VBLANK_SAVE (1 << 1) # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC2_STATUS 0x03fc # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC_V_SYNC_POL (1 << 23) #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_V_SYNC_POL (1 << 23) #define RADEON_CRTC_V_TOTAL_DISP 0x0208 # define RADEON_CRTC_V_TOTAL (0x07ff << 0) # define RADEON_CRTC_V_TOTAL_SHIFT 0 # define RADEON_CRTC_V_DISP (0x07ff << 16) # define RADEON_CRTC_V_DISP_SHIFT 16 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) # define RADEON_CRTC2_V_TOTAL_SHIFT 0 # define RADEON_CRTC2_V_DISP (0x07ff << 16) # define RADEON_CRTC2_V_DISP_SHIFT 16 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) #define RADEON_CRTC2_CRNT_FRAME 0x0314 #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 #define RADEON_CRTC2_STATUS 0x03fc #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define RADEON_CUR_CLR0 0x026c #define RADEON_CUR_CLR1 0x0270 #define RADEON_CUR_HORZ_VERT_OFF 0x0268 #define RADEON_CUR_HORZ_VERT_POSN 0x0264 #define RADEON_CUR_OFFSET 0x0260 # define RADEON_CUR_LOCK (1 << 31) #define RADEON_CUR2_CLR0 0x036c #define RADEON_CUR2_CLR1 0x0370 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 #define RADEON_CUR2_OFFSET 0x0360 # define RADEON_CUR2_LOCK (1 << 31) #define RADEON_DAC_CNTL 0x0058 # define RADEON_DAC_RANGE_CNTL (3 << 0) # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) # define RADEON_DAC_RANGE_CNTL_MASK 0x03 # define RADEON_DAC_BLANKING (1 << 2) # define RADEON_DAC_CMP_EN (1 << 3) # define RADEON_DAC_CMP_OUTPUT (1 << 7) # define RADEON_DAC_8BIT_EN (1 << 8) # define RADEON_DAC_TVO_EN (1 << 10) # define RADEON_DAC_VGA_ADR_EN (1 << 13) # define RADEON_DAC_PDWN (1 << 15) # define RADEON_DAC_MASK_ALL (0xff << 24) #define RADEON_DAC_CNTL2 0x007c # define RADEON_DAC2_TV_CLK_SEL (0 << 1) # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) # define RADEON_DAC2_CMP_EN (1 << 7) # define RADEON_DAC2_CMP_OUT_R (1 << 8) # define RADEON_DAC2_CMP_OUT_G (1 << 9) # define RADEON_DAC2_CMP_OUT_B (1 << 10) # define RADEON_DAC2_CMP_OUTPUT (1 << 11) #define RADEON_DAC_EXT_CNTL 0x0280 # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) # define RADEON_DAC_FORCE_DATA_EN (1 << 5) # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 # define RADEON_DAC_FORCE_DATA_SHIFT 8 #define RADEON_DAC_MACRO_CNTL 0x0d04 # define RADEON_DAC_PDWN_R (1 << 16) # define RADEON_DAC_PDWN_G (1 << 17) # define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_NBLANK (1 << 0) # define RADEON_TV_DAC_NHOLD (1 << 1) # define RADEON_TV_DAC_PEDESTAL (1 << 2) # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) # define RADEON_TV_DAC_CMPOUT (1 << 5) # define RADEON_TV_DAC_STD_MASK (3 << 8) # define RADEON_TV_DAC_STD_PAL (0 << 8) # define RADEON_TV_DAC_STD_NTSC (1 << 8) # define RADEON_TV_DAC_STD_PS2 (2 << 8) # define RADEON_TV_DAC_STD_RS343 (3 << 8) # define RADEON_TV_DAC_BGSLEEP (1 << 6) # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) # define RADEON_TV_DAC_BGADJ_SHIFT 16 # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) # define RADEON_TV_DAC_DACADJ_SHIFT 20 # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) # define RADEON_TV_DAC_RDACDET (1 << 29) # define RADEON_TV_DAC_GDACDET (1 << 30) # define RADEON_TV_DAC_BDACDET (1 << 31) # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) # define R420_TV_DAC_RDACPD (1 << 25) # define R420_TV_DAC_GDACPD (1 << 26) # define R420_TV_DAC_BDACPD (1 << 27) # define R420_TV_DAC_TVENABLE (1 << 28) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 # define RADEON_DISP_DAC_SOURCE_MASK 0x03 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 # define RADEON_DISP_DAC_SOURCE_RMX 0x02 # define RADEON_DISP_DAC_SOURCE_LTU 0x03 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ #define RADEON_DISP_TV_OUT_CNTL 0x0d6c # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) #define RADEON_DAC_CRC_SIG 0x02cc #define RADEON_DAC_DATA 0x03c9 /* VGA */ #define RADEON_DAC_MASK 0x03c6 /* VGA */ #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ #define RADEON_DDA_CONFIG 0x02e0 #define RADEON_DDA_ON_OFF 0x02e4 #define RADEON_DEFAULT_OFFSET 0x16e0 #define RADEON_DEFAULT_PITCH 0x16e4 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define RADEON_DEVICE_ID 0x0f02 /* PCI */ #define RADEON_DISP_MISC_CNTL 0x0d00 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) #define RADEON_DISP_MERGE_CNTL 0x0d60 # define RADEON_DISP_ALPHA_MODE_MASK 0x03 # define RADEON_DISP_ALPHA_MODE_KEY 0 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) #define RADEON_DISP2_MERGE_CNTL 0x0d68 # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c #define RADEON_DP_CNTL 0x16c0 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) # define RADEON_DP_DST_TILE_LINEAR (0 << 3) # define RADEON_DP_DST_TILE_MACRO (1 << 3) # define RADEON_DP_DST_TILE_MICRO (2 << 3) # define RADEON_DP_DST_TILE_BOTH (3 << 3) #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 # define RADEON_DST_Y_MAJOR (1 << 2) # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) #define RADEON_DP_DATATYPE 0x16c4 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) # define RADEON_GMC_SRC_CLIPPING (1 << 2) # define RADEON_GMC_DST_CLIPPING (1 << 3) # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) # define RADEON_GMC_BRUSH_NONE (15 << 4) # define RADEON_GMC_DST_8BPP_CI (2 << 8) # define RADEON_GMC_DST_15BPP (3 << 8) # define RADEON_GMC_DST_16BPP (4 << 8) # define RADEON_GMC_DST_24BPP (5 << 8) # define RADEON_GMC_DST_32BPP (6 << 8) # define RADEON_GMC_DST_8BPP_RGB (7 << 8) # define RADEON_GMC_DST_Y8 (8 << 8) # define RADEON_GMC_DST_RGB8 (9 << 8) # define RADEON_GMC_DST_VYUY (11 << 8) # define RADEON_GMC_DST_YVYU (12 << 8) # define RADEON_GMC_DST_AYUV444 (14 << 8) # define RADEON_GMC_DST_ARGB4444 (15 << 8) # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) # define RADEON_GMC_DST_DATATYPE_SHIFT 8 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) # define RADEON_GMC_CONVERSION_TEMP (1 << 15) # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) # define RADEON_GMC_ROP3_MASK (0xff << 16) # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define RADEON_GMC_3D_FCN_EN (1 << 27) # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) # define RADEON_GMC_WR_MSK_DIS (1 << 30) # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) # define RADEON_ROP3_ZERO 0x00000000 # define RADEON_ROP3_DSa 0x00880000 # define RADEON_ROP3_SDna 0x00440000 # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_DSna 0x00220000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DSx 0x00660000 # define RADEON_ROP3_DSo 0x00ee0000 # define RADEON_ROP3_DSon 0x00110000 # define RADEON_ROP3_DSxn 0x00990000 # define RADEON_ROP3_Dn 0x00550000 # define RADEON_ROP3_SDno 0x00dd0000 # define RADEON_ROP3_Sn 0x00330000 # define RADEON_ROP3_DSno 0x00bb0000 # define RADEON_ROP3_DSan 0x00770000 # define RADEON_ROP3_ONE 0x00ff0000 # define RADEON_ROP3_DPa 0x00a00000 # define RADEON_ROP3_PDna 0x00500000 # define RADEON_ROP3_P 0x00f00000 # define RADEON_ROP3_DPna 0x000a0000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DPx 0x005a0000 # define RADEON_ROP3_DPo 0x00fa0000 # define RADEON_ROP3_DPon 0x00050000 # define RADEON_ROP3_PDxn 0x00a50000 # define RADEON_ROP3_PDno 0x00f50000 # define RADEON_ROP3_Pn 0x000f0000 # define RADEON_ROP3_DPno 0x00af0000 # define RADEON_ROP3_DPan 0x005f0000 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 #define RADEON_DP_MIX 0x16c8 #define RADEON_DP_SRC_BKGD_CLR 0x15dc #define RADEON_DP_SRC_FRGD_CLR 0x15d8 #define RADEON_DP_WRITE_MASK 0x16cc #define RADEON_DST_BRES_DEC 0x1630 #define RADEON_DST_BRES_ERR 0x1628 #define RADEON_DST_BRES_INC 0x162c #define RADEON_DST_BRES_LNTH 0x1634 #define RADEON_DST_BRES_LNTH_SUB 0x1638 #define RADEON_DST_HEIGHT 0x1410 #define RADEON_DST_HEIGHT_WIDTH 0x143c #define RADEON_DST_HEIGHT_WIDTH_8 0x158c #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 #define RADEON_DST_HEIGHT_Y 0x15a0 #define RADEON_DST_LINE_START 0x1600 #define RADEON_DST_LINE_END 0x1604 #define RADEON_DST_LINE_PATCOUNT 0x1608 # define RADEON_BRES_CNTL_SHIFT 8 #define RADEON_DST_OFFSET 0x1404 #define RADEON_DST_PITCH 0x1408 #define RADEON_DST_PITCH_OFFSET 0x142c #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_PITCH_SHIFT 21 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) # define RADEON_DST_TILE_MICRO (2 << 30) # define RADEON_DST_TILE_BOTH (3 << 30) #define RADEON_DST_WIDTH 0x140c #define RADEON_DST_WIDTH_HEIGHT 0x1598 #define RADEON_DST_WIDTH_X 0x1588 #define RADEON_DST_WIDTH_X_INCY 0x159c #define RADEON_DST_X 0x141c #define RADEON_DST_X_SUB 0x15a4 #define RADEON_DST_X_Y 0x1594 #define RADEON_DST_Y 0x1420 #define RADEON_DST_Y_SUB 0x15a8 #define RADEON_DST_Y_X 0x1438 #define RADEON_FCP_CNTL 0x0910 # define RADEON_FCP0_SRC_PCICLK 0 # define RADEON_FCP0_SRC_PCLK 1 # define RADEON_FCP0_SRC_PCLKb 2 # define RADEON_FCP0_SRC_HREF 3 # define RADEON_FCP0_SRC_GND 4 # define RADEON_FCP0_SRC_HREFb 5 #define RADEON_FLUSH_1 0x1704 #define RADEON_FLUSH_2 0x1708 #define RADEON_FLUSH_3 0x170c #define RADEON_FLUSH_4 0x1710 #define RADEON_FLUSH_5 0x1714 #define RADEON_FLUSH_6 0x1718 #define RADEON_FLUSH_7 0x171c #define RADEON_FOG_3D_TABLE_START 0x1810 #define RADEON_FOG_3D_TABLE_END 0x1814 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c #define RADEON_FOG_TABLE_INDEX 0x1a14 #define RADEON_FOG_TABLE_DATA 0x1a18 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 #define RADEON_FP_GEN_CNTL 0x0284 # define RADEON_FP_FPON (1 << 0) # define RADEON_FP_BLANK_EN (1 << 1) # define RADEON_FP_TMDS_EN (1 << 2) # define RADEON_FP_PANEL_FORMAT (1 << 3) # define RADEON_FP_EN_TMDS (1 << 7) # define RADEON_FP_DETECT_SENSE (1 << 8) # define R200_FP_SOURCE_SEL_MASK (3 << 10) # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP_SOURCE_SEL_RMX (2 << 10) # define R200_FP_SOURCE_SEL_TRANS (3 << 10) # define RADEON_FP_SEL_CRTC1 (0 << 13) # define RADEON_FP_SEL_CRTC2 (1 << 13) # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) # define RADEON_FP_DFP_SYNC_SEL (1 << 21) # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) # define RADEON_FP_CRT_SYNC_SEL (1 << 23) # define RADEON_FP_USE_SHADOW_EN (1 << 24) # define RADEON_FP_CRT_SYNC_ALT (1 << 26) #define RADEON_FP2_GEN_CNTL 0x0288 # define RADEON_FP2_BLANK_EN (1 << 1) # define RADEON_FP2_ON (1 << 2) # define RADEON_FP2_PANEL_FORMAT (1 << 3) # define RADEON_FP2_DETECT_SENSE (1 << 8) # define R200_FP2_SOURCE_SEL_MASK (3 << 10) # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP2_SOURCE_SEL_RMX (2 << 10) # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) # define RADEON_FP2_SRC_SEL_MASK (3 << 13) # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) # define RADEON_FP2_FP_POL (1 << 16) # define RADEON_FP2_LP_POL (1 << 17) # define RADEON_FP2_SCK_POL (1 << 18) # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) # define RADEON_FP2_PAD_FLOP_EN (1 << 22) # define RADEON_FP2_CRC_EN (1 << 23) # define RADEON_FP2_CRC_READ_EN (1 << 24) # define RADEON_FP2_DVO_EN (1 << 25) # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) # define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c #define RADEON_FP_HORZ2_STRETCH 0x038c # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) # define RADEON_HORZ_PANEL_SHIFT 16 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) # define RADEON_HORZ_STRETCH_BLEND (1 << 26) # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) # define RADEON_HORZ_AUTO_RATIO (1 << 27) # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 #define RADEON_FP_VERT_STRETCH 0x0290 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 #define RADEON_FP_VERT2_STRETCH 0x0390 # define RADEON_VERT_PANEL_SIZE (0xfff << 12) # define RADEON_VERT_PANEL_SHIFT 12 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 # define RADEON_VERT_STRETCH_RATIO_MAX 4096 # define RADEON_VERT_STRETCH_ENABLE (1 << 25) # define RADEON_VERT_STRETCH_LINEREP (0 << 26) # define RADEON_VERT_STRETCH_BLEND (1 << 26) # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) # define RADEON_VERT_AUTO_RATIO_INC (1 << 31) # define RADEON_VERT_STRETCH_RESERVED 0x71000000 #define RS400_FP_2ND_GEN_CNTL 0x0384 # define RS400_FP_2ND_ON (1 << 0) # define RS400_FP_2ND_BLANK_EN (1 << 1) # define RS400_TMDS_2ND_EN (1 << 2) # define RS400_PANEL_FORMAT_2ND (1 << 3) # define RS400_FP_2ND_EN_TMDS (1 << 7) # define RS400_FP_2ND_DETECT_SENSE (1 << 8) # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) # define RS400_FP_2ND_DETECT_EN (1 << 12) # define RS400_HPD_2ND_SEL (1 << 13) #define RS400_FP2_2_GEN_CNTL 0x0388 # define RS400_FP2_2_BLANK_EN (1 << 1) # define RS400_FP2_2_ON (1 << 2) # define RS400_FP2_2_PANEL_FORMAT (1 << 3) # define RS400_FP2_2_DETECT_SENSE (1 << 8) # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) # define RS400_FP2_2_DVO2_EN (1 << 25) #define RS400_TMDS2_CNTL 0x0394 #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 # define RS400_TMDS2_PLLEN (1 << 0) # define RS400_TMDS2_PLLRST (1 << 1) #define RADEON_GEN_INT_CNTL 0x0040 #define RADEON_GEN_INT_STATUS 0x0044 # define RADEON_VSYNC_INT_AK (1 << 2) # define RADEON_VSYNC_INT (1 << 2) # define RADEON_VSYNC2_INT_AK (1 << 6) # define RADEON_VSYNC2_INT (1 << 6) #define RADEON_GENENB 0x03c3 /* VGA */ #define RADEON_GENFC_RD 0x03ca /* VGA */ #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ #define RADEON_GENMO_RD 0x03cc /* VGA */ #define RADEON_GENMO_WT 0x03c2 /* VGA */ #define RADEON_GENS0 0x03c2 /* VGA */ #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ #define RADEON_GPIO_MONIDB 0x006c #define RADEON_GPIO_CRT2_DDC 0x006c #define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ #define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ # define RADEON_GPIO_A_0 (1 << 0) # define RADEON_GPIO_A_1 (1 << 1) # define RADEON_GPIO_Y_0 (1 << 8) # define RADEON_GPIO_Y_1 (1 << 9) # define RADEON_GPIO_Y_SHIFT_0 8 # define RADEON_GPIO_Y_SHIFT_1 9 # define RADEON_GPIO_EN_0 (1 << 16) # define RADEON_GPIO_EN_1 (1 << 17) # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ #define RADEON_GRPH8_DATA 0x03cf /* VGA */ #define RADEON_GRPH8_IDX 0x03ce /* VGA */ #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 #define RADEON_GUI_SCRATCH_REG2 0x15e8 #define RADEON_GUI_SCRATCH_REG3 0x15ec #define RADEON_GUI_SCRATCH_REG4 0x15f0 #define RADEON_GUI_SCRATCH_REG5 0x15f4 #define RADEON_HEADER 0x0f0e /* PCI */ #define RADEON_HOST_DATA0 0x17c0 #define RADEON_HOST_DATA1 0x17c4 #define RADEON_HOST_DATA2 0x17c8 #define RADEON_HOST_DATA3 0x17cc #define RADEON_HOST_DATA4 0x17d0 #define RADEON_HOST_DATA5 0x17d4 #define RADEON_HOST_DATA6 0x17d8 #define RADEON_HOST_DATA7 0x17dc #define RADEON_HOST_DATA_LAST 0x17e0 #define RADEON_HOST_PATH_CNTL 0x0130 # define RADEON_HDP_SOFT_RESET (1 << 26) # define RADEON_HDP_APER_CNTL (1 << 23) #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ /* Multimedia I2C bus */ #define RADEON_I2C_CNTL_0 0x0090 #define RADEON_I2C_DONE (1 << 0) #define RADEON_I2C_NACK (1 << 1) #define RADEON_I2C_HALT (1 << 2) #define RADEON_I2C_SOFT_RST (1 << 5) #define RADEON_I2C_DRIVE_EN (1 << 6) #define RADEON_I2C_DRIVE_SEL (1 << 7) #define RADEON_I2C_START (1 << 8) #define RADEON_I2C_STOP (1 << 9) #define RADEON_I2C_RECEIVE (1 << 10) #define RADEON_I2C_ABORT (1 << 11) #define RADEON_I2C_GO (1 << 12) #define RADEON_I2C_CNTL_1 0x0094 #define RADEON_I2C_SEL (1 << 16) #define RADEON_I2C_EN (1 << 17) #define RADEON_I2C_DATA 0x0098 #define RADEON_DVI_I2C_CNTL_0 0x02e0 # define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) # define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ # define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ # define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ #define RADEON_DVI_I2C_CNTL_1 0x02e4 #define RADEON_DVI_I2C_DATA 0x02e8 #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ #define RADEON_IO_BASE 0x0f14 /* PCI */ #define RADEON_LATENCY 0x0f0d /* PCI */ #define RADEON_LEAD_BRES_DEC 0x1608 #define RADEON_LEAD_BRES_LNTH 0x161c #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 #define RADEON_LVDS_GEN_CNTL 0x02d0 # define RADEON_LVDS_ON (1 << 0) # define RADEON_LVDS_DISPLAY_DIS (1 << 1) # define RADEON_LVDS_PANEL_TYPE (1 << 2) # define RADEON_LVDS_PANEL_FORMAT (1 << 3) # define RADEON_LVDS_RST_FM (1 << 6) # define RADEON_LVDS_EN (1 << 7) # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) # define RADEON_LVDS_BL_MOD_EN (1 << 16) # define RADEON_LVDS_DIGON (1 << 18) # define RADEON_LVDS_BLON (1 << 19) # define RADEON_LVDS_SEL_CRTC2 (1 << 23) #define RADEON_LVDS_PLL_CNTL 0x02d4 # define RADEON_HSYNC_DELAY_SHIFT 28 # define RADEON_HSYNC_DELAY_MASK (0xf << 28) # define RADEON_LVDS_PLL_EN (1 << 16) # define RADEON_LVDS_PLL_RESET (1 << 17) # define R300_LVDS_SRC_SEL_MASK (3 << 18) # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) # define R300_LVDS_SRC_SEL_RMX (2 << 18) #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_DISPLAY_BASE_ADDR 0x23c #define RADEON_DISPLAY2_BASE_ADDR 0x33c #define RADEON_OV0_BASE_ADDR 0x43c #define RADEON_NB_TOM 0x15c #define R300_MC_INIT_MISC_LAT_TIMER 0x180 # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 # define R300_MC_DISP0R_INIT_LAT_MASK 0xf # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 # define R300_MC_DISP1R_INIT_LAT_MASK 0xf #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) # define RADEON_FORCEON_YCLKA (1 << 18) # define RADEON_FORCEON_YCLKB (1 << 19) # define RADEON_FORCEON_MC (1 << 20) # define RADEON_FORCEON_AIC (1 << 21) # define R300_DISABLE_MC_MCLKA (1 << 21) # define R300_DISABLE_MC_MCLKB (1 << 21) #define RADEON_MCLK_MISC 0x001f /* PLL */ # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_LCD_GPIO_MASK 0x01a0 #define RADEON_GPIOPAD_EN 0x01a0 #define RADEON_LCD_GPIO_Y_REG 0x01a4 #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 #define RADEON_GPIOPAD_MASK 0x0198 #define RADEON_GPIOPAD_A 0x019c #define RADEON_MDGPIO_Y_REG 0x01b4 #define RADEON_MEM_ADDR_CONFIG 0x0148 #define RADEON_MEM_BASE 0x0f10 /* PCI */ #define RADEON_MEM_CNTL 0x0140 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) # define RV100_HALF_MODE (1 << 3) # define R300_MEM_NUM_CHANNELS_MASK 0x03 # define R300_MEM_USE_CD_CH_ONLY (1 << 2) #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ #define RADEON_MEM_INIT_LAT_TIMER 0x0154 #define RADEON_MEM_INTF_CNTL 0x014c #define RADEON_MEM_SDRAM_MODE_REG 0x0158 # define RADEON_SDRAM_MODE_MASK 0xffff0000 # define RADEON_B3MEM_RESET_MASK 0x6fffffff # define RADEON_MEM_CFG_TYPE_DDR (1 << 30) #define RADEON_MEM_STR_CNTL 0x0150 # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) # define R300_MEM_PWRUP_COMPL_C (1 << 2) # define R300_MEM_PWRUP_COMPL_D (1 << 3) # define RADEON_MEM_PWRUP_COMPLETE 0x03 # define R300_MEM_PWRUP_COMPLETE 0x0f #define RADEON_MC_STATUS 0x0150 # define RADEON_MC_IDLE (1 << 2) # define R300_MC_IDLE (1 << 4) #define RADEON_MEM_VGA_RP_SEL 0x003c #define RADEON_MEM_VGA_WP_SEL 0x0038 #define RADEON_MIN_GRANT 0x0f3e /* PCI */ #define RADEON_MM_DATA 0x0004 #define RADEON_MM_INDEX 0x0000 #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ #define RADEON_SEPROM_CNTL1 0x01c0 # define RADEON_SCK_PRESCALE_SHIFT 24 # define RADEON_SCK_PRESCALE_MASK (0xff << 24) #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f # define R300_MC_IND_WR_EN (1 << 8) #define R300_MC_IND_DATA 0x01fc #define R300_MC_READ_CNTL_AB 0x017c # define R300_MEM_RBS_POSITION_A_MASK 0x03 #define R300_MC_READ_CNTL_CD_mcind 0x24 # define R300_MEM_RBS_POSITION_C_MASK 0x03 #define RADEON_N_VIF_COUNT 0x0248 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 #define RADEON_OV0_COLOUR_CNTL 0x04E0 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C # define RADEON_EXCL_VERT_START_MASK 0x000003ff # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 #define RADEON_OV0_FILTER_CNTL 0x04A0 # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 # define RADEON_FILTER_HARDCODED_COEF 0xf # define RADEON_FILTER_COEF_MASK 0xf #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 #define RADEON_OV0_FLAG_CNTL 0x04DC #define RADEON_OV0_GAMMA_000_00F 0x0d40 #define RADEON_OV0_GAMMA_010_01F 0x0d44 #define RADEON_OV0_GAMMA_020_03F 0x0d48 #define RADEON_OV0_GAMMA_040_07F 0x0d4c #define RADEON_OV0_GAMMA_080_0BF 0x0e00 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 #define RADEON_OV0_GAMMA_100_13F 0x0e08 #define RADEON_OV0_GAMMA_140_17F 0x0e0c #define RADEON_OV0_GAMMA_180_1BF 0x0e10 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 #define RADEON_OV0_GAMMA_200_23F 0x0e18 #define RADEON_OV0_GAMMA_240_27F 0x0e1c #define RADEON_OV0_GAMMA_280_2BF 0x0e20 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 #define RADEON_OV0_GAMMA_300_33F 0x0e28 #define RADEON_OV0_GAMMA_340_37F 0x0e2c #define RADEON_OV0_GAMMA_380_3BF 0x0d50 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 #define RADEON_OV0_H_INC 0x0480 #define RADEON_OV0_KEY_CNTL 0x04F4 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L # define RADEON_VIDEO_KEY_FN_NE 0x00000003L # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L # define RADEON_CMP_MIX_MASK 0x00000100L # define RADEON_CMP_MIX_OR 0x00000000L # define RADEON_CMP_MIX_AND 0x00000100L #define RADEON_OV0_LIN_TRANS_A 0x0d20 #define RADEON_OV0_LIN_TRANS_B 0x0d24 #define RADEON_OV0_LIN_TRANS_C 0x0d28 #define RADEON_OV0_LIN_TRANS_D 0x0d2c #define RADEON_OV0_LIN_TRANS_E 0x0d30 #define RADEON_OV0_LIN_TRANS_F 0x0d34 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L #define RADEON_OV0_P1_X_START_END 0x0494 #define RADEON_OV0_P2_X_START_END 0x0498 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C #define RADEON_OV0_P3_X_START_END 0x049C #define RADEON_OV0_REG_LOAD_CNTL 0x0410 # define RADEON_REG_LD_CTL_LOCK 0x00000001L # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L #define RADEON_OV0_SCALE_CNTL 0x0420 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L # define RADEON_SCALER_SIGNED_UV 0x00000010L # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L # define RADEON_SCALER_SOURCE_15BPP 0x00000300L # define RADEON_SCALER_SOURCE_16BPP 0x00000400L # define RADEON_SCALER_SOURCE_32BPP 0x00000600L # define RADEON_SCALER_SOURCE_YUV9 0x00000900L # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L # define RADEON_SCALER_CRTC_SEL 0x00004000L # define RADEON_SCALER_SMART_SWITCH 0x00008000L # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L # define RADEON_SCALER_DIS_LIMIT 0x08000000L # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L # define RADEON_SCALER_INT_EMU 0x20000000L # define RADEON_SCALER_ENABLE 0x40000000L # define RADEON_SCALER_SOFT_RESET 0x80000000L #define RADEON_OV0_STEP_BY 0x0484 #define RADEON_OV0_TEST 0x04F8 #define RADEON_OV0_V_INC 0x0424 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 #define RADEON_OV0_Y_X_START 0x0400 #define RADEON_OV0_Y_X_END 0x0404 #define RADEON_OV1_Y_X_START 0x0600 #define RADEON_OV1_Y_X_END 0x0604 #define RADEON_OVR_CLR 0x0230 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 /* first capture unit */ #define RADEON_CAP0_BUF0_OFFSET 0x0920 #define RADEON_CAP0_BUF1_OFFSET 0x0924 #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C #define RADEON_CAP0_BUF_PITCH 0x0930 #define RADEON_CAP0_V_WINDOW 0x0934 #define RADEON_CAP0_H_WINDOW 0x0938 #define RADEON_CAP0_VBI0_OFFSET 0x093C #define RADEON_CAP0_VBI1_OFFSET 0x0940 #define RADEON_CAP0_VBI_V_WINDOW 0x0944 #define RADEON_CAP0_VBI_H_WINDOW 0x0948 #define RADEON_CAP0_PORT_MODE_CNTL 0x094C #define RADEON_CAP0_TRIG_CNTL 0x0950 #define RADEON_CAP0_DEBUG 0x0954 #define RADEON_CAP0_CONFIG 0x0958 # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 #define RADEON_CAP0_ANC_H_WINDOW 0x0964 #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C #define RADEON_CAP0_BUF_STATUS 0x0970 /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ /* #define RADEON_CAP0_XSHARPNESS 0x097C */ #define RADEON_CAP0_VBI2_OFFSET 0x0980 #define RADEON_CAP0_VBI3_OFFSET 0x0984 #define RADEON_CAP0_ANC2_OFFSET 0x0988 #define RADEON_CAP0_ANC3_OFFSET 0x098C #define RADEON_VID_BUFFER_CONTROL 0x0900 /* second capture unit */ #define RADEON_CAP1_BUF0_OFFSET 0x0990 #define RADEON_CAP1_BUF1_OFFSET 0x0994 #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C #define RADEON_CAP1_BUF_PITCH 0x09A0 #define RADEON_CAP1_V_WINDOW 0x09A4 #define RADEON_CAP1_H_WINDOW 0x09A8 #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 #define RADEON_CAP1_VBI_V_WINDOW 0x09B4 #define RADEON_CAP1_VBI_H_WINDOW 0x09B8 #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC #define RADEON_CAP1_TRIG_CNTL 0x09C0 #define RADEON_CAP1_DEBUG 0x09C4 #define RADEON_CAP1_CONFIG 0x09C8 #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 #define RADEON_CAP1_ANC_H_WINDOW 0x09D4 #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC #define RADEON_CAP1_BUF_STATUS 0x09E0 #define RADEON_CAP1_DWNSC_XRATIO 0x09E8 #define RADEON_CAP1_XSHARPNESS 0x09EC /* misc multimedia registers */ #define RADEON_IDCT_RUNS 0x1F80 #define RADEON_IDCT_LEVELS 0x1F84 #define RADEON_IDCT_CONTROL 0x1FBC #define RADEON_IDCT_AUTH_CONTROL 0x1F88 #define RADEON_IDCT_AUTH 0x1F8C #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ # define RADEON_P2PLL_RESET (1 << 0) # define RADEON_P2PLL_SLEEP (1 << 1) # define RADEON_P2PLL_PVG_MASK (7 << 11) # define RADEON_P2PLL_PVG_SHIFT 11 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define RADEON_P2PLL_DIV_0 0x002c # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ # define RADEON_P2PLL_REF_DIV_MASK 0x03ff # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) # define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define RADEON_PALETTE_DATA 0x00b4 #define RADEON_PALETTE_30_DATA 0x00b8 #define RADEON_PALETTE_INDEX 0x00b0 #define RADEON_PCI_GART_PAGE 0x017c #define RADEON_PIXCLKS_CNTL 0x002d # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) # define R300_DVOCLK_ALWAYS_ONb (1 << 10) # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) #define RADEON_PLANE_3D_MASK_C 0x1d44 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ # define RADEON_PLL_MASK_READ_B (1 << 9) #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ #define RADEON_PMI_DATA 0x0f63 /* PCI */ #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ #define RADEON_PPLL_CNTL 0x0002 /* PLL */ # define RADEON_PPLL_RESET (1 << 0) # define RADEON_PPLL_SLEEP (1 << 1) # define RADEON_PPLL_PVG_MASK (7 << 11) # define RADEON_PPLL_PVG_SHIFT 11 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ # define RADEON_PPLL_FB3_DIV_MASK 0x07ff # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ # define RADEON_PPLL_REF_DIV_MASK 0x03ff # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ #define RADEON_RBBM_GUICNTL 0x172c # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) # define RADEON_SOFT_RESET_SE (1 << 2) # define RADEON_SOFT_RESET_RE (1 << 3) # define RADEON_SOFT_RESET_PP (1 << 4) # define RADEON_SOFT_RESET_E2 (1 << 5) # define RADEON_SOFT_RESET_RB (1 << 6) # define RADEON_SOFT_RESET_HDP (1 << 7) #define RADEON_RBBM_STATUS 0x0e40 # define RADEON_RBBM_FIFOCNT_MASK 0x007f # define RADEON_RBBM_ACTIVE (1 << 31) #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c # define RADEON_RB2D_DC_FLUSH (3 << 0) # define RADEON_RB2D_DC_FREE (3 << 2) # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) #define RADEON_RB2D_DSTCACHE_MODE 0x3428 #define RADEON_DSTCACHE_CTLSTAT 0x1714 #define RADEON_RB3D_ZCACHE_MODE 0x3250 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 #define RADEON_RB3D_DSTCACHE_MODE 0x3258 # define RADEON_RB3D_DC_CACHE_ENABLE (0) # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) # define RADEON_RB3D_DC_CACHE_DISABLE (3) # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) # define RADEON_RB3D_DC_FORCE_RMW (1 << 16) # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf # define RADEON_RB3D_DC_BUSY (1 << 31) #define RADEON_REG_BASE 0x0f18 /* PCI */ #define RADEON_REGPROG_INF 0x0f09 /* PCI */ #define RADEON_REVISION_ID 0x0f08 /* PCI */ #define RADEON_SC_BOTTOM 0x164c #define RADEON_SC_BOTTOM_RIGHT 0x16f0 #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c #define RADEON_SC_LEFT 0x1640 #define RADEON_SC_RIGHT 0x1644 #define RADEON_SC_TOP 0x1648 #define RADEON_SC_TOP_LEFT 0x16ec #define RADEON_SC_TOP_LEFT_C 0x1c88 # define RADEON_SC_SIGN_MASK_LO 0x8000 # define RADEON_SC_SIGN_MASK_HI 0x80000000 #define RADEON_SCLK_CNTL 0x000d /* PLL */ # define RADEON_SCLK_SRC_SEL_MASK 0x0007 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 # define RADEON_SCLK_FORCE_DISP2 (1<<15) # define RADEON_SCLK_FORCE_CP (1<<16) # define RADEON_SCLK_FORCE_HDP (1<<17) # define RADEON_SCLK_FORCE_DISP1 (1<<18) # define RADEON_SCLK_FORCE_TOP (1<<19) # define RADEON_SCLK_FORCE_E2 (1<<20) # define RADEON_SCLK_FORCE_SE (1<<21) # define RADEON_SCLK_FORCE_IDCT (1<<22) # define RADEON_SCLK_FORCE_VIP (1<<23) # define RADEON_SCLK_FORCE_RE (1<<24) # define RADEON_SCLK_FORCE_PB (1<<25) # define RADEON_SCLK_FORCE_TAM (1<<26) # define RADEON_SCLK_FORCE_TDM (1<<27) # define RADEON_SCLK_FORCE_RB (1<<28) # define RADEON_SCLK_FORCE_TV_SCLK (1<<29) # define RADEON_SCLK_FORCE_SUBPIC (1<<30) # define RADEON_SCLK_FORCE_OV0 (1<<31) # define R300_SCLK_FORCE_VAP (1<<21) # define R300_SCLK_FORCE_SR (1<<25) # define R300_SCLK_FORCE_PX (1<<26) # define R300_SCLK_FORCE_TX (1<<27) # define R300_SCLK_FORCE_US (1<<28) # define R300_SCLK_FORCE_SU (1<<30) #define R300_SCLK_CNTL2 0x1e /* PLL */ # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) # define R300_SCLK_FORCE_TCL (1<<13) # define R300_SCLK_FORCE_CBA (1<<14) # define R300_SCLK_FORCE_GA (1<<15) #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 # define RADEON_SCLK_MORE_FORCEON 0x0700 #define RADEON_SDRAM_MODE_REG 0x0158 #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ #define RADEON_SNAPSHOT_F_COUNT 0x0244 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c #define RADEON_SRC_OFFSET 0x15ac #define RADEON_SRC_PITCH 0x15b0 #define RADEON_SRC_PITCH_OFFSET 0x1428 #define RADEON_SRC_SC_BOTTOM 0x165c #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 #define RADEON_SRC_SC_RIGHT 0x1654 #define RADEON_SRC_X 0x1414 #define RADEON_SRC_X_Y 0x1590 #define RADEON_SRC_Y 0x1418 #define RADEON_SRC_Y_X 0x1434 #define RADEON_STATUS 0x0f06 /* PCI */ #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ #define RADEON_SUB_CLASS 0x0f0a /* PCI */ #define RADEON_SURFACE_CNTL 0x0b00 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_INFO 0x0b0c # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) # define R200_SURF_TILE_NONE (0 << 16) # define R200_SURF_TILE_COLOR_MACRO (1 << 16) # define R200_SURF_TILE_COLOR_MICRO (2 << 16) # define R200_SURF_TILE_COLOR_BOTH (3 << 16) # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) # define R300_SURF_TILE_NONE (0 << 16) # define R300_SURF_TILE_COLOR_MACRO (1 << 16) # define R300_SURF_TILE_DEPTH_32BPP (2 << 16) # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) # define RADEON_SURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 #define RADEON_SURFACE1_INFO 0x0b1c #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 #define RADEON_SURFACE2_INFO 0x0b2c #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 #define RADEON_SURFACE3_INFO 0x0b3c #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 #define RADEON_SURFACE4_INFO 0x0b4c #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 #define RADEON_SURFACE5_INFO 0x0b5c #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 #define RADEON_SURFACE6_INFO 0x0b6c #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 #define RADEON_SURFACE7_INFO 0x0b7c #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 #define RADEON_SW_SEMAPHORE 0x013c #define RADEON_TEST_DEBUG_CNTL 0x0120 #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 #define RADEON_TEST_DEBUG_MUX 0x0124 #define RADEON_TEST_DEBUG_OUT 0x012c #define RADEON_TMDS_PLL_CNTL 0x02a8 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 # define RADEON_TMDS_TRANSMITTER_PLLEN 1 # define RADEON_TMDS_TRANSMITTER_PLLRST 2 #define RADEON_TRAIL_BRES_DEC 0x1614 #define RADEON_TRAIL_BRES_ERR 0x160c #define RADEON_TRAIL_BRES_INC 0x1610 #define RADEON_TRAIL_X 0x1618 #define RADEON_TRAIL_X_SUB 0x1620 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ # define RADEON_VCLK_SRC_SEL_MASK 0x03 # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) #define RADEON_VENDOR_ID 0x0f00 /* PCI */ #define RADEON_VGA_DDA_CONFIG 0x02e8 #define RADEON_VGA_DDA_ON_OFF 0x02ec #define RADEON_VID_BUFFER_CONTROL 0x0900 #define RADEON_VIDEOMUX_CNTL 0x0190 /* VIP bus */ #define RADEON_VIPH_CH0_DATA 0x0c00 #define RADEON_VIPH_CH1_DATA 0x0c04 #define RADEON_VIPH_CH2_DATA 0x0c08 #define RADEON_VIPH_CH3_DATA 0x0c0c #define RADEON_VIPH_CH0_ADDR 0x0c10 #define RADEON_VIPH_CH1_ADDR 0x0c14 #define RADEON_VIPH_CH2_ADDR 0x0c18 #define RADEON_VIPH_CH3_ADDR 0x0c1c #define RADEON_VIPH_CH0_SBCNT 0x0c20 #define RADEON_VIPH_CH1_SBCNT 0x0c24 #define RADEON_VIPH_CH2_SBCNT 0x0c28 #define RADEON_VIPH_CH3_SBCNT 0x0c2c #define RADEON_VIPH_CH0_ABCNT 0x0c30 #define RADEON_VIPH_CH1_ABCNT 0x0c34 #define RADEON_VIPH_CH2_ABCNT 0x0c38 #define RADEON_VIPH_CH3_ABCNT 0x0c3c #define RADEON_VIPH_CONTROL 0x0c40 # define RADEON_VIP_BUSY 0 # define RADEON_VIP_IDLE 1 # define RADEON_VIP_RESET 2 # define RADEON_VIPH_EN (1 << 21) #define RADEON_VIPH_DV_LAT 0x0c44 #define RADEON_VIPH_BM_CHUNK 0x0c48 #define RADEON_VIPH_DV_INT 0x0c4c #define RADEON_VIPH_TIMEOUT_STAT 0x0c50 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 #define RADEON_VIPH_REG_DATA 0x0084 #define RADEON_VIPH_REG_ADDR 0x0080 #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) # define RADEON_WAIT_CRTC_VLINE (1 << 3) # define RADEON_WAIT_DMA_VID_IDLE (1 << 8) # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ # define RADEON_WAIT_OV0_FLIP (1 << 11) # define RADEON_WAIT_AGP_FLUSH (1 << 13) # define RADEON_WAIT_2D_IDLE (1 << 14) # define RADEON_WAIT_3D_IDLE (1 << 15) # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) # define RADEON_CMDFIFO_ENTRIES_SHIFT 10 # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f # define RADEON_WAIT_VAP_IDLE (1 << 28) # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ #define RADEON_XDLL_CNTL 0x000c /* PLL */ #define RADEON_XPLL_CNTL 0x000b /* PLL */ /* Registers for 3D/TCL */ #define RADEON_PP_BORDER_COLOR_0 0x1d40 #define RADEON_PP_BORDER_COLOR_1 0x1d44 #define RADEON_PP_BORDER_COLOR_2 0x1d48 #define RADEON_PP_CNTL 0x1c38 # define RADEON_STIPPLE_ENABLE (1 << 0) # define RADEON_SCISSOR_ENABLE (1 << 1) # define RADEON_PATTERN_ENABLE (1 << 2) # define RADEON_SHADOW_ENABLE (1 << 3) # define RADEON_TEX_ENABLE_MASK (0xf << 4) # define RADEON_TEX_0_ENABLE (1 << 4) # define RADEON_TEX_1_ENABLE (1 << 5) # define RADEON_TEX_2_ENABLE (1 << 6) # define RADEON_TEX_3_ENABLE (1 << 7) # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) # define RADEON_PLANAR_YUV_ENABLE (1 << 20) # define RADEON_SPECULAR_ENABLE (1 << 21) # define RADEON_FOG_ENABLE (1 << 22) # define RADEON_ALPHA_TEST_ENABLE (1 << 23) # define RADEON_ANTI_ALIAS_NONE (0 << 24) # define RADEON_ANTI_ALIAS_LINE (1 << 24) # define RADEON_ANTI_ALIAS_POLY (2 << 24) # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) # define RADEON_BUMP_MAP_ENABLE (1 << 26) # define RADEON_BUMPED_MAP_T0 (0 << 27) # define RADEON_BUMPED_MAP_T1 (1 << 27) # define RADEON_BUMPED_MAP_T2 (2 << 27) # define RADEON_TEX_3D_ENABLE_0 (1 << 29) # define RADEON_TEX_3D_ENABLE_1 (1 << 30) # define RADEON_MC_ENABLE (1 << 31) #define RADEON_PP_FOG_COLOR 0x1c18 # define RADEON_FOG_COLOR_MASK 0x00ffffff # define RADEON_FOG_VERTEX (0 << 24) # define RADEON_FOG_TABLE (1 << 24) # define RADEON_FOG_USE_DEPTH (0 << 25) # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) #define RADEON_PP_LUM_MATRIX 0x1d00 #define RADEON_PP_MISC 0x1c14 # define RADEON_REF_ALPHA_MASK 0x000000ff # define RADEON_ALPHA_TEST_FAIL (0 << 8) # define RADEON_ALPHA_TEST_LESS (1 << 8) # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) # define RADEON_ALPHA_TEST_EQUAL (3 << 8) # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) # define RADEON_ALPHA_TEST_GREATER (5 << 8) # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) # define RADEON_ALPHA_TEST_PASS (7 << 8) # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) # define RADEON_CHROMA_FUNC_FAIL (0 << 16) # define RADEON_CHROMA_FUNC_PASS (1 << 16) # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) # define RADEON_CHROMA_KEY_NEAREST (0 << 18) # define RADEON_CHROMA_KEY_ZERO (1 << 18) # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) # define RADEON_SHADOW_PASS_1 (0 << 22) # define RADEON_SHADOW_PASS_2 (1 << 22) # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) #define RADEON_PP_ROT_MATRIX_0 0x1d58 #define RADEON_PP_ROT_MATRIX_1 0x1d5c #define RADEON_PP_TXFILTER_0 0x1c54 #define RADEON_PP_TXFILTER_1 0x1c6c #define RADEON_PP_TXFILTER_2 0x1c84 # define RADEON_MAG_FILTER_NEAREST (0 << 0) # define RADEON_MAG_FILTER_LINEAR (1 << 0) # define RADEON_MAG_FILTER_MASK (1 << 0) # define RADEON_MIN_FILTER_NEAREST (0 << 1) # define RADEON_MIN_FILTER_LINEAR (1 << 1) # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) # define RADEON_MIN_FILTER_MASK (15 << 1) # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) # define RADEON_MAX_ANISO_MASK (7 << 5) # define RADEON_LOD_BIAS_MASK (0xff << 8) # define RADEON_LOD_BIAS_SHIFT 8 # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) # define RADEON_MAX_MIP_LEVEL_SHIFT 16 # define RADEON_YUV_TO_RGB (1 << 20) # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) # define RADEON_WRAPEN_S (1 << 22) # define RADEON_CLAMP_S_WRAP (0 << 23) # define RADEON_CLAMP_S_MIRROR (1 << 23) # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) # define RADEON_CLAMP_S_MASK (7 << 23) # define RADEON_WRAPEN_T (1 << 26) # define RADEON_CLAMP_T_WRAP (0 << 27) # define RADEON_CLAMP_T_MIRROR (1 << 27) # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) # define RADEON_CLAMP_T_MASK (7 << 27) # define RADEON_BORDER_MODE_OGL (0 << 31) # define RADEON_BORDER_MODE_D3D (1 << 31) #define RADEON_PP_TXFORMAT_0 0x1c58 #define RADEON_PP_TXFORMAT_1 0x1c70 #define RADEON_PP_TXFORMAT_2 0x1c88 # define RADEON_TXFORMAT_I8 (0 << 0) # define RADEON_TXFORMAT_AI88 (1 << 0) # define RADEON_TXFORMAT_RGB332 (2 << 0) # define RADEON_TXFORMAT_ARGB1555 (3 << 0) # define RADEON_TXFORMAT_RGB565 (4 << 0) # define RADEON_TXFORMAT_ARGB4444 (5 << 0) # define RADEON_TXFORMAT_ARGB8888 (6 << 0) # define RADEON_TXFORMAT_RGBA8888 (7 << 0) # define RADEON_TXFORMAT_Y8 (8 << 0) # define RADEON_TXFORMAT_VYUY422 (10 << 0) # define RADEON_TXFORMAT_YVYU422 (11 << 0) # define RADEON_TXFORMAT_DXT1 (12 << 0) # define RADEON_TXFORMAT_DXT23 (14 << 0) # define RADEON_TXFORMAT_DXT45 (15 << 0) # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) # define RADEON_TXFORMAT_FORMAT_SHIFT 0 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) # define RADEON_TXFORMAT_WIDTH_SHIFT 8 # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) #define RADEON_PP_CUBIC_FACES_0 0x1d24 #define RADEON_PP_CUBIC_FACES_1 0x1d28 #define RADEON_PP_CUBIC_FACES_2 0x1d2c # define RADEON_FACE_WIDTH_1_SHIFT 0 # define RADEON_FACE_HEIGHT_1_SHIFT 4 # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) # define RADEON_FACE_WIDTH_2_SHIFT 8 # define RADEON_FACE_HEIGHT_2_SHIFT 12 # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) # define RADEON_FACE_WIDTH_3_SHIFT 16 # define RADEON_FACE_HEIGHT_3_SHIFT 20 # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) # define RADEON_FACE_WIDTH_4_SHIFT 24 # define RADEON_FACE_HEIGHT_4_SHIFT 28 # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) #define RADEON_PP_TXOFFSET_0 0x1c5c #define RADEON_PP_TXOFFSET_1 0x1c74 #define RADEON_PP_TXOFFSET_2 0x1c8c # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) # define RADEON_TXO_MACRO_LINEAR (0 << 2) # define RADEON_TXO_MACRO_TILE (1 << 2) # define RADEON_TXO_MICRO_LINEAR (0 << 3) # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) # define RADEON_TXO_OFFSET_MASK 0xffffffe0 # define RADEON_TXO_OFFSET_SHIFT 5 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ #define RADEON_PP_TEX_SIZE_1 0x1d0c #define RADEON_PP_TEX_SIZE_2 0x1d14 # define RADEON_TEX_USIZE_MASK (0x7ff << 0) # define RADEON_TEX_USIZE_SHIFT 0 # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) # define RADEON_TEX_VSIZE_SHIFT 16 # define RADEON_SIGNED_RGB_MASK (1 << 30) # define RADEON_SIGNED_RGB_SHIFT 30 # define RADEON_SIGNED_ALPHA_MASK (1 << 31) # define RADEON_SIGNED_ALPHA_SHIFT 31 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ /* note: bits 13-5: 32 byte aligned stride of texture map */ #define RADEON_PP_TXCBLEND_0 0x1c60 #define RADEON_PP_TXCBLEND_1 0x1c78 #define RADEON_PP_TXCBLEND_2 0x1c90 # define RADEON_COLOR_ARG_A_SHIFT 0 # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) # define RADEON_COLOR_ARG_A_ZERO (0 << 0) # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) # define RADEON_COLOR_ARG_B_SHIFT 5 # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) # define RADEON_COLOR_ARG_B_ZERO (0 << 5) # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) # define RADEON_COLOR_ARG_C_SHIFT 10 # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) # define RADEON_COLOR_ARG_C_ZERO (0 << 10) # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) # define RADEON_COMP_ARG_A (1 << 15) # define RADEON_COMP_ARG_A_SHIFT 15 # define RADEON_COMP_ARG_B (1 << 16) # define RADEON_COMP_ARG_B_SHIFT 16 # define RADEON_COMP_ARG_C (1 << 17) # define RADEON_COMP_ARG_C_SHIFT 17 # define RADEON_BLEND_CTL_MASK (7 << 18) # define RADEON_BLEND_CTL_ADD (0 << 18) # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) # define RADEON_BLEND_CTL_BLEND (3 << 18) # define RADEON_BLEND_CTL_DOT3 (4 << 18) # define RADEON_SCALE_SHIFT 21 # define RADEON_SCALE_MASK (3 << 21) # define RADEON_SCALE_1X (0 << 21) # define RADEON_SCALE_2X (1 << 21) # define RADEON_SCALE_4X (2 << 21) # define RADEON_CLAMP_TX (1 << 23) # define RADEON_T0_EQ_TCUR (1 << 24) # define RADEON_T1_EQ_TCUR (1 << 25) # define RADEON_T2_EQ_TCUR (1 << 26) # define RADEON_T3_EQ_TCUR (1 << 27) # define RADEON_COLOR_ARG_MASK 0x1f # define RADEON_COMP_ARG_SHIFT 15 #define RADEON_PP_TXABLEND_0 0x1c64 #define RADEON_PP_TXABLEND_1 0x1c7c #define RADEON_PP_TXABLEND_2 0x1c94 # define RADEON_ALPHA_ARG_A_SHIFT 0 # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) # define RADEON_ALPHA_ARG_B_SHIFT 4 # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) # define RADEON_ALPHA_ARG_C_SHIFT 8 # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) # define RADEON_ALPHA_ARG_MASK 0xf #define RADEON_PP_TFACTOR_0 0x1c68 #define RADEON_PP_TFACTOR_1 0x1c80 #define RADEON_PP_TFACTOR_2 0x1c98 #define RADEON_RB3D_BLENDCNTL 0x1c20 # define RADEON_COMB_FCN_MASK (3 << 12) # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) # define RADEON_SRC_BLEND_GL_ONE (33 << 16) # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) # define RADEON_SRC_BLEND_MASK (63 << 16) # define RADEON_DST_BLEND_GL_ZERO (32 << 24) # define RADEON_DST_BLEND_GL_ONE (33 << 24) # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) # define RADEON_DST_BLEND_MASK (63 << 24) #define RADEON_RB3D_CNTL 0x1c3c # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_PLANE_MASK_ENABLE (1 << 1) # define RADEON_DITHER_ENABLE (1 << 2) # define RADEON_ROUND_ENABLE (1 << 3) # define RADEON_SCALE_DITHER_ENABLE (1 << 4) # define RADEON_DITHER_INIT (1 << 5) # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) # define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) # define RADEON_COLOR_FORMAT_RGB565 (4 << 10) # define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) # define RADEON_COLOR_FORMAT_RGB332 (7 << 10) # define RADEON_COLOR_FORMAT_Y8 (8 << 10) # define RADEON_COLOR_FORMAT_RGB8 (9 << 10) # define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) # define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) # define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) # define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) #define RADEON_RB3D_COLOROFFSET 0x1c40 # define RADEON_COLOROFFSET_MASK 0xfffffff0 #define RADEON_RB3D_COLORPITCH 0x1c48 # define RADEON_COLORPITCH_MASK 0x000001ff8 # define RADEON_COLOR_TILE_ENABLE (1 << 16) # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) #define RADEON_RB3D_DEPTHOFFSET 0x1c24 #define RADEON_RB3D_DEPTHPITCH 0x1c28 # define RADEON_DEPTHPITCH_MASK 0x00001ff8 # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) #define RADEON_RB3D_PLANEMASK 0x1d84 #define RADEON_RB3D_ROPCNTL 0x1d80 # define RADEON_ROP_MASK (15 << 8) # define RADEON_ROP_CLEAR (0 << 8) # define RADEON_ROP_NOR (1 << 8) # define RADEON_ROP_AND_INVERTED (2 << 8) # define RADEON_ROP_COPY_INVERTED (3 << 8) # define RADEON_ROP_AND_REVERSE (4 << 8) # define RADEON_ROP_INVERT (5 << 8) # define RADEON_ROP_XOR (6 << 8) # define RADEON_ROP_NAND (7 << 8) # define RADEON_ROP_AND (8 << 8) # define RADEON_ROP_EQUIV (9 << 8) # define RADEON_ROP_NOOP (10 << 8) # define RADEON_ROP_OR_INVERTED (11 << 8) # define RADEON_ROP_COPY (12 << 8) # define RADEON_ROP_OR_REVERSE (13 << 8) # define RADEON_ROP_OR (14 << 8) # define RADEON_ROP_SET (15 << 8) #define RADEON_RB3D_STENCILREFMASK 0x1d7c # define RADEON_STENCIL_REF_SHIFT 0 # define RADEON_STENCIL_REF_MASK (0xff << 0) # define RADEON_STENCIL_MASK_SHIFT 16 # define RADEON_STENCIL_VALUE_MASK (0xff << 16) # define RADEON_STENCIL_WRITEMASK_SHIFT 24 # define RADEON_STENCIL_WRITE_MASK (0xff << 24) #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) # define RADEON_Z_TEST_NEVER (0 << 4) # define RADEON_Z_TEST_LESS (1 << 4) # define RADEON_Z_TEST_LEQUAL (2 << 4) # define RADEON_Z_TEST_EQUAL (3 << 4) # define RADEON_Z_TEST_GEQUAL (4 << 4) # define RADEON_Z_TEST_GREATER (5 << 4) # define RADEON_Z_TEST_NEQUAL (6 << 4) # define RADEON_Z_TEST_ALWAYS (7 << 4) # define RADEON_Z_TEST_MASK (7 << 4) # define RADEON_STENCIL_TEST_NEVER (0 << 12) # define RADEON_STENCIL_TEST_LESS (1 << 12) # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) # define RADEON_STENCIL_TEST_EQUAL (3 << 12) # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) # define RADEON_STENCIL_TEST_GREATER (5 << 12) # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) # define RADEON_STENCIL_TEST_MASK (0x7 << 12) # define RADEON_STENCIL_FAIL_KEEP (0 << 16) # define RADEON_STENCIL_FAIL_ZERO (1 << 16) # define RADEON_STENCIL_FAIL_REPLACE (2 << 16) # define RADEON_STENCIL_FAIL_INC (3 << 16) # define RADEON_STENCIL_FAIL_DEC (4 << 16) # define RADEON_STENCIL_FAIL_INVERT (5 << 16) # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) # define RADEON_STENCIL_ZPASS_INC (3 << 20) # define RADEON_STENCIL_ZPASS_DEC (4 << 20) # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) # define RADEON_STENCIL_ZFAIL_INC (3 << 24) # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) #define RADEON_RE_LINE_PATTERN 0x1cd0 # define RADEON_LINE_PATTERN_MASK 0x0000ffff # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 # define RADEON_LINE_PATTERN_START_SHIFT 24 # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) #define RADEON_RE_LINE_STATE 0x1cd4 # define RADEON_LINE_CURRENT_PTR_SHIFT 0 # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 #define RADEON_RE_MISC 0x26c4 # define RADEON_STIPPLE_COORD_MASK 0x1f # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) #define RADEON_RE_SOLID_COLOR 0x1c1c #define RADEON_RE_TOP_LEFT 0x26c0 # define RADEON_RE_LEFT_SHIFT 0 # define RADEON_RE_TOP_SHIFT 16 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 # define RADEON_RE_WIDTH_SHIFT 0 # define RADEON_RE_HEIGHT_SHIFT 16 #define RADEON_SE_CNTL 0x1c4c # define RADEON_FFACE_CULL_CW (0 << 0) # define RADEON_FFACE_CULL_CCW (1 << 0) # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) # define RADEON_BFACE_CULL (0 << 1) # define RADEON_BFACE_SOLID (3 << 1) # define RADEON_FFACE_CULL (0 << 3) # define RADEON_FFACE_SOLID (3 << 3) # define RADEON_FFACE_CULL_MASK (3 << 3) # define RADEON_BADVTX_CULL_DISABLE (1 << 5) # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) # define RADEON_ALPHA_SHADE_SOLID (0 << 10) # define RADEON_ALPHA_SHADE_FLAT (1 << 10) # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) # define RADEON_ALPHA_SHADE_MASK (3 << 10) # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) # define RADEON_SPECULAR_SHADE_MASK (3 << 12) # define RADEON_FOG_SHADE_SOLID (0 << 14) # define RADEON_FOG_SHADE_FLAT (1 << 14) # define RADEON_FOG_SHADE_GOURAUD (2 << 14) # define RADEON_FOG_SHADE_MASK (3 << 14) # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) # define RADEON_WIDELINE_ENABLE (1 << 20) # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) # define RADEON_ROUND_MODE_TRUNC (0 << 28) # define RADEON_ROUND_MODE_ROUND (1 << 28) # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) #define R200_RE_CNTL 0x1c50 # define R200_STIPPLE_ENABLE 0x1 # define R200_SCISSOR_ENABLE 0x2 # define R200_PATTERN_ENABLE 0x4 # define R200_PERSPECTIVE_ENABLE 0x8 # define R200_POINT_SMOOTH 0x20 # define R200_VTX_STQ0_D3D 0x00010000 # define R200_VTX_STQ1_D3D 0x00040000 # define R200_VTX_STQ2_D3D 0x00100000 # define R200_VTX_STQ3_D3D 0x00400000 # define R200_VTX_STQ4_D3D 0x01000000 # define R200_VTX_STQ5_D3D 0x04000000 #define R200_RE_SCISSOR_TL_0 0x1cd8 #define R200_RE_SCISSOR_BR_0 0x1cdc #define R200_RE_SCISSOR_TL_1 0x1ce0 #define R200_RE_SCISSOR_BR_1 0x1ce4 #define R200_RE_SCISSOR_TL_2 0x1ce8 #define R200_RE_SCISSOR_BR_2 0x1cec # define R200_SCISSOR_X_SHIFT 0 # define R200_SCISSOR_Y_SHIFT 16 #define RADEON_SE_CNTL_STATUS 0x2140 # define RADEON_VC_NO_SWAP (0 << 0) # define RADEON_VC_16BIT_SWAP (1 << 0) # define RADEON_VC_32BIT_SWAP (2 << 0) # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) # define RADEON_TCL_BYPASS (1 << 8) #define RADEON_SE_COORD_FMT 0x1c50 # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) # define RADEON_VTX_W0_NORMALIZE (1 << 12) # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) #define RADEON_SE_LINE_WIDTH 0x1db8 #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c # define RADEON_LIGHTING_ENABLE (1 << 0) # define RADEON_LIGHT_IN_MODELSPACE (1 << 1) # define RADEON_LOCAL_VIEWER (1 << 2) # define RADEON_NORMALIZE_NORMALS (1 << 3) # define RADEON_RESCALE_NORMALS (1 << 4) # define RADEON_SPECULAR_LIGHTS (1 << 5) # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) # define RADEON_LIGHT_ALPHA (1 << 7) # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) # define RADEON_LM_SOURCE_STATE_PREMULT 0 # define RADEON_LM_SOURCE_STATE_MULT 1 # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 # define RADEON_EMISSIVE_SOURCE_SHIFT 16 # define RADEON_AMBIENT_SOURCE_SHIFT 18 # define RADEON_DIFFUSE_SOURCE_SHIFT 20 # define RADEON_SPECULAR_SOURCE_SHIFT 22 #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c # define RADEON_MODELVIEW_0_SHIFT 0 # define RADEON_MODELVIEW_1_SHIFT 4 # define RADEON_MODELVIEW_2_SHIFT 8 # define RADEON_MODELVIEW_3_SHIFT 12 # define RADEON_IT_MODELVIEW_0_SHIFT 16 # define RADEON_IT_MODELVIEW_1_SHIFT 20 # define RADEON_IT_MODELVIEW_2_SHIFT 24 # define RADEON_IT_MODELVIEW_3_SHIFT 28 #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 # define RADEON_MODELPROJECT_0_SHIFT 0 # define RADEON_MODELPROJECT_1_SHIFT 4 # define RADEON_MODELPROJECT_2_SHIFT 8 # define RADEON_MODELPROJECT_3_SHIFT 12 # define RADEON_TEXMAT_0_SHIFT 16 # define RADEON_TEXMAT_1_SHIFT 20 # define RADEON_TEXMAT_2_SHIFT 24 # define RADEON_TEXMAT_3_SHIFT 28 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 # define RADEON_TCL_VTX_W0 (1 << 0) # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) # define RADEON_TCL_VTX_FP_ALPHA (1 << 2) # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) # define RADEON_TCL_VTX_FP_SPEC (1 << 4) # define RADEON_TCL_VTX_FP_FOG (1 << 5) # define RADEON_TCL_VTX_PK_SPEC (1 << 6) # define RADEON_TCL_VTX_ST0 (1 << 7) # define RADEON_TCL_VTX_ST1 (1 << 8) # define RADEON_TCL_VTX_Q1 (1 << 9) # define RADEON_TCL_VTX_ST2 (1 << 10) # define RADEON_TCL_VTX_Q2 (1 << 11) # define RADEON_TCL_VTX_ST3 (1 << 12) # define RADEON_TCL_VTX_Q3 (1 << 13) # define RADEON_TCL_VTX_Q0 (1 << 14) # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 # define RADEON_TCL_VTX_NORM0 (1 << 18) # define RADEON_TCL_VTX_XY1 (1 << 27) # define RADEON_TCL_VTX_Z1 (1 << 28) # define RADEON_TCL_VTX_W1 (1 << 29) # define RADEON_TCL_VTX_NORM1 (1 << 30) # define RADEON_TCL_VTX_Z0 (1 << 31) #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 # define RADEON_TCL_COMPUTE_XYZW (1 << 0) # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) # define RADEON_TCL_TEX_INPUT_TEX_0 0 # define RADEON_TCL_TEX_INPUT_TEX_1 1 # define RADEON_TCL_TEX_INPUT_TEX_2 2 # define RADEON_TCL_TEX_INPUT_TEX_3 3 # define RADEON_TCL_TEX_COMPUTED_TEX_0 8 # define RADEON_TCL_TEX_COMPUTED_TEX_1 9 # define RADEON_TCL_TEX_COMPUTED_TEX_2 10 # define RADEON_TCL_TEX_COMPUTED_TEX_3 11 # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 # define RADEON_LIGHT_0_ENABLE (1 << 0) # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) # define RADEON_LIGHT_0_IS_LOCAL (1 << 3) # define RADEON_LIGHT_0_IS_SPOT (1 << 4) # define RADEON_LIGHT_0_DUAL_CONE (1 << 5) # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) # define RADEON_LIGHT_0_SHIFT 0 # define RADEON_LIGHT_1_ENABLE (1 << 16) # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) # define RADEON_LIGHT_1_IS_LOCAL (1 << 19) # define RADEON_LIGHT_1_IS_SPOT (1 << 20) # define RADEON_LIGHT_1_DUAL_CONE (1 << 21) # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) # define RADEON_LIGHT_1_SHIFT 16 #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 # define RADEON_LIGHT_2_SHIFT 0 # define RADEON_LIGHT_3_SHIFT 16 #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 # define RADEON_LIGHT_4_SHIFT 0 # define RADEON_LIGHT_5_SHIFT 16 #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c # define RADEON_LIGHT_6_SHIFT 0 # define RADEON_LIGHT_7_SHIFT 16 #define RADEON_SE_TCL_SHININESS 0x2250 #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) # define RADEON_TEXMAT_0_ENABLE (1 << 4) # define RADEON_TEXMAT_1_ENABLE (1 << 5) # define RADEON_TEXMAT_2_ENABLE (1 << 6) # define RADEON_TEXMAT_3_ENABLE (1 << 7) # define RADEON_TEXGEN_INPUT_MASK 0xf # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 # define RADEON_TEXGEN_INPUT_OBJ 4 # define RADEON_TEXGEN_INPUT_EYE 5 # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 # define RADEON_TEXGEN_0_INPUT_SHIFT 16 # define RADEON_TEXGEN_1_INPUT_SHIFT 20 # define RADEON_TEXGEN_2_INPUT_SHIFT 24 # define RADEON_TEXGEN_3_INPUT_SHIFT 28 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 # define RADEON_UCP_IN_CLIP_SPACE (1 << 0) # define RADEON_UCP_IN_MODEL_SPACE (1 << 1) # define RADEON_UCP_ENABLE_0 (1 << 2) # define RADEON_UCP_ENABLE_1 (1 << 3) # define RADEON_UCP_ENABLE_2 (1 << 4) # define RADEON_UCP_ENABLE_3 (1 << 5) # define RADEON_UCP_ENABLE_4 (1 << 6) # define RADEON_UCP_ENABLE_5 (1 << 7) # define RADEON_TCL_FOG_MASK (3 << 8) # define RADEON_TCL_FOG_DISABLE (0 << 8) # define RADEON_TCL_FOG_EXP (1 << 8) # define RADEON_TCL_FOG_EXP2 (2 << 8) # define RADEON_TCL_FOG_LINEAR (3 << 8) # define RADEON_RNG_BASED_FOG (1 << 10) # define RADEON_LIGHT_TWOSIDE (1 << 11) # define RADEON_BLEND_OP_COUNT_MASK (7 << 12) # define RADEON_BLEND_OP_COUNT_SHIFT 12 # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) # define RADEON_CULL_FRONT_IS_CW (0 << 28) # define RADEON_CULL_FRONT_IS_CCW (1 << 28) # define RADEON_CULL_FRONT (1 << 29) # define RADEON_CULL_BACK (1 << 30) # define RADEON_FORCE_W_TO_ONE (1 << 31) #define RADEON_SE_VPORT_XSCALE 0x1d98 #define RADEON_SE_VPORT_XOFFSET 0x1d9c #define RADEON_SE_VPORT_YSCALE 0x1da0 #define RADEON_SE_VPORT_YOFFSET 0x1da4 #define RADEON_SE_VPORT_ZSCALE 0x1da8 #define RADEON_SE_VPORT_ZOFFSET 0x1dac #define RADEON_SE_ZBIAS_FACTOR 0x1db0 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 #define RADEON_SE_VTX_FMT 0x2080 # define RADEON_SE_VTX_FMT_XY 0x00000000 # define RADEON_SE_VTX_FMT_W0 0x00000001 # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 # define RADEON_SE_VTX_FMT_FPFOG 0x00000020 # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 # define RADEON_SE_VTX_FMT_ST0 0x00000080 # define RADEON_SE_VTX_FMT_ST1 0x00000100 # define RADEON_SE_VTX_FMT_Q1 0x00000200 # define RADEON_SE_VTX_FMT_ST2 0x00000400 # define RADEON_SE_VTX_FMT_Q2 0x00000800 # define RADEON_SE_VTX_FMT_ST3 0x00001000 # define RADEON_SE_VTX_FMT_Q3 0x00002000 # define RADEON_SE_VTX_FMT_Q0 0x00004000 # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 # define RADEON_SE_VTX_FMT_N0 0x00040000 # define RADEON_SE_VTX_FMT_XY1 0x08000000 # define RADEON_SE_VTX_FMT_Z1 0x10000000 # define RADEON_SE_VTX_FMT_W1 0x20000000 # define RADEON_SE_VTX_FMT_N1 0x40000000 # define RADEON_SE_VTX_FMT_Z 0x80000000 #define RADEON_SE_VF_CNTL 0x2084 # define RADEON_VF_PRIM_TYPE_POINT_LIST 1 # define RADEON_VF_PRIM_TYPE_LINE_LIST 2 # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 # define RADEON_VF_PRIM_TYPE_POLYGON 15 # define RADEON_VF_PRIM_WALK_STATE (0<<4) # define RADEON_VF_PRIM_WALK_INDEX (1<<4) # define RADEON_VF_PRIM_WALK_LIST (2<<4) # define RADEON_VF_PRIM_WALK_DATA (3<<4) # define RADEON_VF_COLOR_ORDER_RGBA (1<<6) # define RADEON_VF_RADEON_MODE (1<<8) # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) # define RADEON_VF_PROG_STREAM_ENA (1<<10) # define RADEON_VF_INDEX_SIZE_SHIFT 11 # define RADEON_VF_NUM_VERTICES_SHIFT 16 #define RADEON_SE_PORT_DATA0 0x2000 #define R200_SE_VAP_CNTL 0x2080 # define R200_VAP_TCL_ENABLE 0x00000001 # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 # define R200_VAP_FORCE_W_TO_ONE 0x00010000 # define R200_VAP_D3D_TEX_DEFAULT 0x00020000 # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 # define R200_VAP_VF_MAX_VTX_NUM (9 << 18) # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 #define R200_VF_MAX_VTX_INDX 0x210c #define R200_VF_MIN_VTX_INDX 0x2110 #define R200_SE_VTE_CNTL 0x20b0 # define R200_VPORT_X_SCALE_ENA 0x00000001 # define R200_VPORT_X_OFFSET_ENA 0x00000002 # define R200_VPORT_Y_SCALE_ENA 0x00000004 # define R200_VPORT_Y_OFFSET_ENA 0x00000008 # define R200_VPORT_Z_SCALE_ENA 0x00000010 # define R200_VPORT_Z_OFFSET_ENA 0x00000020 # define R200_VTX_XY_FMT 0x00000100 # define R200_VTX_Z_FMT 0x00000200 # define R200_VTX_W0_FMT 0x00000400 # define R200_VTX_W0_NORMALIZE 0x00000800 # define R200_VTX_ST_DENORMALIZED 0x00001000 #define R200_SE_VAP_CNTL_STATUS 0x2140 # define R200_VC_NO_SWAP (0 << 0) # define R200_VC_16BIT_SWAP (1 << 0) # define R200_VC_32BIT_SWAP (2 << 0) #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 # define R200_EXCLUSIVE_SCISSOR_0 0x01000000 # define R200_EXCLUSIVE_SCISSOR_1 0x02000000 # define R200_EXCLUSIVE_SCISSOR_2 0x04000000 # define R200_SCISSOR_ENABLE_0 0x10000000 # define R200_SCISSOR_ENABLE_1 0x20000000 # define R200_SCISSOR_ENABLE_2 0x40000000 #define R200_PP_TXFILTER_0 0x2c00 #define R200_PP_TXFILTER_1 0x2c20 #define R200_PP_TXFILTER_2 0x2c40 #define R200_PP_TXFILTER_3 0x2c60 #define R200_PP_TXFILTER_4 0x2c80 #define R200_PP_TXFILTER_5 0x2ca0 # define R200_MAG_FILTER_NEAREST (0 << 0) # define R200_MAG_FILTER_LINEAR (1 << 0) # define R200_MAG_FILTER_MASK (1 << 0) # define R200_MIN_FILTER_NEAREST (0 << 1) # define R200_MIN_FILTER_LINEAR (1 << 1) # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) # define R200_MIN_FILTER_MASK (15 << 1) # define R200_MAX_ANISO_1_TO_1 (0 << 5) # define R200_MAX_ANISO_2_TO_1 (1 << 5) # define R200_MAX_ANISO_4_TO_1 (2 << 5) # define R200_MAX_ANISO_8_TO_1 (3 << 5) # define R200_MAX_ANISO_16_TO_1 (4 << 5) # define R200_MAX_ANISO_MASK (7 << 5) # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) # define R200_MAX_MIP_LEVEL_SHIFT 16 # define R200_YUV_TO_RGB (1 << 20) # define R200_YUV_TEMPERATURE_COOL (0 << 21) # define R200_YUV_TEMPERATURE_HOT (1 << 21) # define R200_YUV_TEMPERATURE_MASK (1 << 21) # define R200_WRAPEN_S (1 << 22) # define R200_CLAMP_S_WRAP (0 << 23) # define R200_CLAMP_S_MIRROR (1 << 23) # define R200_CLAMP_S_CLAMP_LAST (2 << 23) # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) # define R200_CLAMP_S_CLAMP_BORDER (4 << 23) # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) # define R200_CLAMP_S_CLAMP_GL (6 << 23) # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) # define R200_CLAMP_S_MASK (7 << 23) # define R200_WRAPEN_T (1 << 26) # define R200_CLAMP_T_WRAP (0 << 27) # define R200_CLAMP_T_MIRROR (1 << 27) # define R200_CLAMP_T_CLAMP_LAST (2 << 27) # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) # define R200_CLAMP_T_CLAMP_BORDER (4 << 27) # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) # define R200_CLAMP_T_CLAMP_GL (6 << 27) # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) # define R200_CLAMP_T_MASK (7 << 27) # define R200_KILL_LT_ZERO (1 << 30) # define R200_BORDER_MODE_OGL (0 << 31) # define R200_BORDER_MODE_D3D (1 << 31) #define R200_PP_TXFORMAT_0 0x2c04 #define R200_PP_TXFORMAT_1 0x2c24 #define R200_PP_TXFORMAT_2 0x2c44 #define R200_PP_TXFORMAT_3 0x2c64 #define R200_PP_TXFORMAT_4 0x2c84 #define R200_PP_TXFORMAT_5 0x2ca4 # define R200_TXFORMAT_I8 (0 << 0) # define R200_TXFORMAT_AI88 (1 << 0) # define R200_TXFORMAT_RGB332 (2 << 0) # define R200_TXFORMAT_ARGB1555 (3 << 0) # define R200_TXFORMAT_RGB565 (4 << 0) # define R200_TXFORMAT_ARGB4444 (5 << 0) # define R200_TXFORMAT_ARGB8888 (6 << 0) # define R200_TXFORMAT_RGBA8888 (7 << 0) # define R200_TXFORMAT_Y8 (8 << 0) # define R200_TXFORMAT_AVYU4444 (9 << 0) # define R200_TXFORMAT_VYUY422 (10 << 0) # define R200_TXFORMAT_YVYU422 (11 << 0) # define R200_TXFORMAT_DXT1 (12 << 0) # define R200_TXFORMAT_DXT23 (14 << 0) # define R200_TXFORMAT_DXT45 (15 << 0) # define R200_TXFORMAT_ABGR8888 (22 << 0) # define R200_TXFORMAT_FORMAT_MASK (31 << 0) # define R200_TXFORMAT_FORMAT_SHIFT 0 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) # define R200_TXFORMAT_NON_POWER2 (1 << 7) # define R200_TXFORMAT_WIDTH_MASK (15 << 8) # define R200_TXFORMAT_WIDTH_SHIFT 8 # define R200_TXFORMAT_HEIGHT_MASK (15 << 12) # define R200_TXFORMAT_HEIGHT_SHIFT 12 # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ # define R200_TXFORMAT_F5_WIDTH_SHIFT 16 # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) # define R200_TXFORMAT_ST_ROUTE_SHIFT 24 # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) #define R200_PP_TXFORMAT_X_0 0x2c08 #define R200_PP_TXFORMAT_X_1 0x2c28 #define R200_PP_TXFORMAT_X_2 0x2c48 #define R200_PP_TXFORMAT_X_3 0x2c68 #define R200_PP_TXFORMAT_X_4 0x2c88 #define R200_PP_TXFORMAT_X_5 0x2ca8 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ #define R200_PP_TXOFFSET_0 0x2d00 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) # define R200_TXO_MACRO_LINEAR (0 << 2) # define R200_TXO_MACRO_TILE (1 << 2) # define R200_TXO_MICRO_LINEAR (0 << 3) # define R200_TXO_MICRO_TILE (1 << 3) # define R200_TXO_OFFSET_MASK 0xffffffe0 # define R200_TXO_OFFSET_SHIFT 5 #define R200_PP_TXOFFSET_1 0x2d18 #define R200_PP_TXOFFSET_2 0x2d30 #define R200_PP_TXOFFSET_3 0x2d48 #define R200_PP_TXOFFSET_4 0x2d60 #define R200_PP_TXOFFSET_5 0x2d78 #define R200_PP_TFACTOR_0 0x2ee0 #define R200_PP_TFACTOR_1 0x2ee4 #define R200_PP_TFACTOR_2 0x2ee8 #define R200_PP_TFACTOR_3 0x2eec #define R200_PP_TFACTOR_4 0x2ef0 #define R200_PP_TFACTOR_5 0x2ef4 #define R200_PP_TXCBLEND_0 0x2f00 # define R200_TXC_ARG_A_ZERO (0) # define R200_TXC_ARG_A_CURRENT_COLOR (2) # define R200_TXC_ARG_A_CURRENT_ALPHA (3) # define R200_TXC_ARG_A_DIFFUSE_COLOR (4) # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) # define R200_TXC_ARG_A_SPECULAR_COLOR (6) # define R200_TXC_ARG_A_SPECULAR_ALPHA (7) # define R200_TXC_ARG_A_TFACTOR_COLOR (8) # define R200_TXC_ARG_A_TFACTOR_ALPHA (9) # define R200_TXC_ARG_A_R0_COLOR (10) # define R200_TXC_ARG_A_R0_ALPHA (11) # define R200_TXC_ARG_A_R1_COLOR (12) # define R200_TXC_ARG_A_R1_ALPHA (13) # define R200_TXC_ARG_A_R2_COLOR (14) # define R200_TXC_ARG_A_R2_ALPHA (15) # define R200_TXC_ARG_A_R3_COLOR (16) # define R200_TXC_ARG_A_R3_ALPHA (17) # define R200_TXC_ARG_A_R4_COLOR (18) # define R200_TXC_ARG_A_R4_ALPHA (19) # define R200_TXC_ARG_A_R5_COLOR (20) # define R200_TXC_ARG_A_R5_ALPHA (21) # define R200_TXC_ARG_A_TFACTOR1_COLOR (26) # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) # define R200_TXC_ARG_A_MASK (31 << 0) # define R200_TXC_ARG_A_SHIFT 0 # define R200_TXC_ARG_B_ZERO (0 << 5) # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) # define R200_TXC_ARG_B_R0_COLOR (10 << 5) # define R200_TXC_ARG_B_R0_ALPHA (11 << 5) # define R200_TXC_ARG_B_R1_COLOR (12 << 5) # define R200_TXC_ARG_B_R1_ALPHA (13 << 5) # define R200_TXC_ARG_B_R2_COLOR (14 << 5) # define R200_TXC_ARG_B_R2_ALPHA (15 << 5) # define R200_TXC_ARG_B_R3_COLOR (16 << 5) # define R200_TXC_ARG_B_R3_ALPHA (17 << 5) # define R200_TXC_ARG_B_R4_COLOR (18 << 5) # define R200_TXC_ARG_B_R4_ALPHA (19 << 5) # define R200_TXC_ARG_B_R5_COLOR (20 << 5) # define R200_TXC_ARG_B_R5_ALPHA (21 << 5) # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) # define R200_TXC_ARG_B_MASK (31 << 5) # define R200_TXC_ARG_B_SHIFT 5 # define R200_TXC_ARG_C_ZERO (0 << 10) # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) # define R200_TXC_ARG_C_R0_COLOR (10 << 10) # define R200_TXC_ARG_C_R0_ALPHA (11 << 10) # define R200_TXC_ARG_C_R1_COLOR (12 << 10) # define R200_TXC_ARG_C_R1_ALPHA (13 << 10) # define R200_TXC_ARG_C_R2_COLOR (14 << 10) # define R200_TXC_ARG_C_R2_ALPHA (15 << 10) # define R200_TXC_ARG_C_R3_COLOR (16 << 10) # define R200_TXC_ARG_C_R3_ALPHA (17 << 10) # define R200_TXC_ARG_C_R4_COLOR (18 << 10) # define R200_TXC_ARG_C_R4_ALPHA (19 << 10) # define R200_TXC_ARG_C_R5_COLOR (20 << 10) # define R200_TXC_ARG_C_R5_ALPHA (21 << 10) # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) # define R200_TXC_ARG_C_MASK (31 << 10) # define R200_TXC_ARG_C_SHIFT 10 # define R200_TXC_COMP_ARG_A (1 << 16) # define R200_TXC_COMP_ARG_A_SHIFT (16) # define R200_TXC_BIAS_ARG_A (1 << 17) # define R200_TXC_SCALE_ARG_A (1 << 18) # define R200_TXC_NEG_ARG_A (1 << 19) # define R200_TXC_COMP_ARG_B (1 << 20) # define R200_TXC_COMP_ARG_B_SHIFT (20) # define R200_TXC_BIAS_ARG_B (1 << 21) # define R200_TXC_SCALE_ARG_B (1 << 22) # define R200_TXC_NEG_ARG_B (1 << 23) # define R200_TXC_COMP_ARG_C (1 << 24) # define R200_TXC_COMP_ARG_C_SHIFT (24) # define R200_TXC_BIAS_ARG_C (1 << 25) # define R200_TXC_SCALE_ARG_C (1 << 26) # define R200_TXC_NEG_ARG_C (1 << 27) # define R200_TXC_OP_MADD (0 << 28) # define R200_TXC_OP_CND0 (2 << 28) # define R200_TXC_OP_LERP (3 << 28) # define R200_TXC_OP_DOT3 (4 << 28) # define R200_TXC_OP_DOT4 (5 << 28) # define R200_TXC_OP_CONDITIONAL (6 << 28) # define R200_TXC_OP_DOT2_ADD (7 << 28) # define R200_TXC_OP_MASK (7 << 28) #define R200_PP_TXCBLEND2_0 0x2f04 # define R200_TXC_TFACTOR_SEL_SHIFT 0 # define R200_TXC_TFACTOR_SEL_MASK 0x7 # define R200_TXC_TFACTOR1_SEL_SHIFT 4 # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) # define R200_TXC_SCALE_SHIFT 8 # define R200_TXC_SCALE_MASK (7 << 8) # define R200_TXC_SCALE_1X (0 << 8) # define R200_TXC_SCALE_2X (1 << 8) # define R200_TXC_SCALE_4X (2 << 8) # define R200_TXC_SCALE_8X (3 << 8) # define R200_TXC_SCALE_INV2 (5 << 8) # define R200_TXC_SCALE_INV4 (6 << 8) # define R200_TXC_SCALE_INV8 (7 << 8) # define R200_TXC_CLAMP_SHIFT 12 # define R200_TXC_CLAMP_MASK (3 << 12) # define R200_TXC_CLAMP_WRAP (0 << 12) # define R200_TXC_CLAMP_0_1 (1 << 12) # define R200_TXC_CLAMP_8_8 (2 << 12) # define R200_TXC_OUTPUT_REG_MASK (7 << 16) # define R200_TXC_OUTPUT_REG_NONE (0 << 16) # define R200_TXC_OUTPUT_REG_R0 (1 << 16) # define R200_TXC_OUTPUT_REG_R1 (2 << 16) # define R200_TXC_OUTPUT_REG_R2 (3 << 16) # define R200_TXC_OUTPUT_REG_R3 (4 << 16) # define R200_TXC_OUTPUT_REG_R4 (5 << 16) # define R200_TXC_OUTPUT_REG_R5 (6 << 16) # define R200_TXC_OUTPUT_MASK_MASK (7 << 20) # define R200_TXC_OUTPUT_MASK_RGB (0 << 20) # define R200_TXC_OUTPUT_MASK_RG (1 << 20) # define R200_TXC_OUTPUT_MASK_RB (2 << 20) # define R200_TXC_OUTPUT_MASK_R (3 << 20) # define R200_TXC_OUTPUT_MASK_GB (4 << 20) # define R200_TXC_OUTPUT_MASK_G (5 << 20) # define R200_TXC_OUTPUT_MASK_B (6 << 20) # define R200_TXC_OUTPUT_MASK_NONE (7 << 20) # define R200_TXC_REPL_NORMAL 0 # define R200_TXC_REPL_RED 1 # define R200_TXC_REPL_GREEN 2 # define R200_TXC_REPL_BLUE 3 # define R200_TXC_REPL_ARG_A_SHIFT 26 # define R200_TXC_REPL_ARG_A_MASK (3 << 26) # define R200_TXC_REPL_ARG_B_SHIFT 28 # define R200_TXC_REPL_ARG_B_MASK (3 << 28) # define R200_TXC_REPL_ARG_C_SHIFT 30 # define R200_TXC_REPL_ARG_C_MASK (3 << 30) #define R200_PP_TXABLEND_0 0x2f08 # define R200_TXA_ARG_A_ZERO (0) # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) # define R200_TXA_ARG_A_DIFFUSE_BLUE (5) # define R200_TXA_ARG_A_SPECULAR_ALPHA (6) # define R200_TXA_ARG_A_SPECULAR_BLUE (7) # define R200_TXA_ARG_A_TFACTOR_ALPHA (8) # define R200_TXA_ARG_A_TFACTOR_BLUE (9) # define R200_TXA_ARG_A_R0_ALPHA (10) # define R200_TXA_ARG_A_R0_BLUE (11) # define R200_TXA_ARG_A_R1_ALPHA (12) # define R200_TXA_ARG_A_R1_BLUE (13) # define R200_TXA_ARG_A_R2_ALPHA (14) # define R200_TXA_ARG_A_R2_BLUE (15) # define R200_TXA_ARG_A_R3_ALPHA (16) # define R200_TXA_ARG_A_R3_BLUE (17) # define R200_TXA_ARG_A_R4_ALPHA (18) # define R200_TXA_ARG_A_R4_BLUE (19) # define R200_TXA_ARG_A_R5_ALPHA (20) # define R200_TXA_ARG_A_R5_BLUE (21) # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) # define R200_TXA_ARG_A_TFACTOR1_BLUE (27) # define R200_TXA_ARG_A_MASK (31 << 0) # define R200_TXA_ARG_A_SHIFT 0 # define R200_TXA_ARG_B_ZERO (0 << 5) # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) # define R200_TXA_ARG_B_R0_ALPHA (10 << 5) # define R200_TXA_ARG_B_R0_BLUE (11 << 5) # define R200_TXA_ARG_B_R1_ALPHA (12 << 5) # define R200_TXA_ARG_B_R1_BLUE (13 << 5) # define R200_TXA_ARG_B_R2_ALPHA (14 << 5) # define R200_TXA_ARG_B_R2_BLUE (15 << 5) # define R200_TXA_ARG_B_R3_ALPHA (16 << 5) # define R200_TXA_ARG_B_R3_BLUE (17 << 5) # define R200_TXA_ARG_B_R4_ALPHA (18 << 5) # define R200_TXA_ARG_B_R4_BLUE (19 << 5) # define R200_TXA_ARG_B_R5_ALPHA (20 << 5) # define R200_TXA_ARG_B_R5_BLUE (21 << 5) # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) # define R200_TXA_ARG_B_MASK (31 << 5) # define R200_TXA_ARG_B_SHIFT 5 # define R200_TXA_ARG_C_ZERO (0 << 10) # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) # define R200_TXA_ARG_C_R0_ALPHA (10 << 10) # define R200_TXA_ARG_C_R0_BLUE (11 << 10) # define R200_TXA_ARG_C_R1_ALPHA (12 << 10) # define R200_TXA_ARG_C_R1_BLUE (13 << 10) # define R200_TXA_ARG_C_R2_ALPHA (14 << 10) # define R200_TXA_ARG_C_R2_BLUE (15 << 10) # define R200_TXA_ARG_C_R3_ALPHA (16 << 10) # define R200_TXA_ARG_C_R3_BLUE (17 << 10) # define R200_TXA_ARG_C_R4_ALPHA (18 << 10) # define R200_TXA_ARG_C_R4_BLUE (19 << 10) # define R200_TXA_ARG_C_R5_ALPHA (20 << 10) # define R200_TXA_ARG_C_R5_BLUE (21 << 10) # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) # define R200_TXA_ARG_C_MASK (31 << 10) # define R200_TXA_ARG_C_SHIFT 10 # define R200_TXA_COMP_ARG_A (1 << 16) # define R200_TXA_COMP_ARG_A_SHIFT (16) # define R200_TXA_BIAS_ARG_A (1 << 17) # define R200_TXA_SCALE_ARG_A (1 << 18) # define R200_TXA_NEG_ARG_A (1 << 19) # define R200_TXA_COMP_ARG_B (1 << 20) # define R200_TXA_COMP_ARG_B_SHIFT (20) # define R200_TXA_BIAS_ARG_B (1 << 21) # define R200_TXA_SCALE_ARG_B (1 << 22) # define R200_TXA_NEG_ARG_B (1 << 23) # define R200_TXA_COMP_ARG_C (1 << 24) # define R200_TXA_COMP_ARG_C_SHIFT (24) # define R200_TXA_BIAS_ARG_C (1 << 25) # define R200_TXA_SCALE_ARG_C (1 << 26) # define R200_TXA_NEG_ARG_C (1 << 27) # define R200_TXA_OP_MADD (0 << 28) # define R200_TXA_OP_CND0 (2 << 28) # define R200_TXA_OP_LERP (3 << 28) # define R200_TXA_OP_CONDITIONAL (6 << 28) # define R200_TXA_OP_MASK (7 << 28) #define R200_PP_TXABLEND2_0 0x2f0c # define R200_TXA_TFACTOR_SEL_SHIFT 0 # define R200_TXA_TFACTOR_SEL_MASK 0x7 # define R200_TXA_TFACTOR1_SEL_SHIFT 4 # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) # define R200_TXA_SCALE_SHIFT 8 # define R200_TXA_SCALE_MASK (7 << 8) # define R200_TXA_SCALE_1X (0 << 8) # define R200_TXA_SCALE_2X (1 << 8) # define R200_TXA_SCALE_4X (2 << 8) # define R200_TXA_SCALE_8X (3 << 8) # define R200_TXA_SCALE_INV2 (5 << 8) # define R200_TXA_SCALE_INV4 (6 << 8) # define R200_TXA_SCALE_INV8 (7 << 8) # define R200_TXA_CLAMP_SHIFT 12 # define R200_TXA_CLAMP_MASK (3 << 12) # define R200_TXA_CLAMP_WRAP (0 << 12) # define R200_TXA_CLAMP_0_1 (1 << 12) # define R200_TXA_CLAMP_8_8 (2 << 12) # define R200_TXA_OUTPUT_REG_MASK (7 << 16) # define R200_TXA_OUTPUT_REG_NONE (0 << 16) # define R200_TXA_OUTPUT_REG_R0 (1 << 16) # define R200_TXA_OUTPUT_REG_R1 (2 << 16) # define R200_TXA_OUTPUT_REG_R2 (3 << 16) # define R200_TXA_OUTPUT_REG_R3 (4 << 16) # define R200_TXA_OUTPUT_REG_R4 (5 << 16) # define R200_TXA_OUTPUT_REG_R5 (6 << 16) # define R200_TXA_DOT_ALPHA (1 << 20) # define R200_TXA_REPL_NORMAL 0 # define R200_TXA_REPL_RED 1 # define R200_TXA_REPL_GREEN 2 # define R200_TXA_REPL_ARG_A_SHIFT 26 # define R200_TXA_REPL_ARG_A_MASK (3 << 26) # define R200_TXA_REPL_ARG_B_SHIFT 28 # define R200_TXA_REPL_ARG_B_MASK (3 << 28) # define R200_TXA_REPL_ARG_C_SHIFT 30 # define R200_TXA_REPL_ARG_C_MASK (3 << 30) #define R200_PP_TXCBLEND_1 0x2f10 #define R200_PP_TXCBLEND2_1 0x2f14 #define R200_PP_TXABLEND_1 0x2f18 #define R200_PP_TXABLEND2_1 0x2f1c #define R200_PP_TXCBLEND_2 0x2f20 #define R200_PP_TXCBLEND2_2 0x2f24 #define R200_PP_TXABLEND_2 0x2f28 #define R200_PP_TXABLEND2_2 0x2f2c #define R200_PP_TXCBLEND_3 0x2f30 #define R200_PP_TXCBLEND2_3 0x2f34 #define R200_PP_TXABLEND_3 0x2f38 #define R200_PP_TXABLEND2_3 0x2f3c #define R200_SE_VTX_FMT_0 0x2088 # define R200_VTX_XY 0 /* always have xy */ # define R200_VTX_Z0 (1<<0) # define R200_VTX_W0 (1<<1) # define R200_VTX_WEIGHT_COUNT_SHIFT (2) # define R200_VTX_PV_MATRIX_SEL (1<<5) # define R200_VTX_N0 (1<<6) # define R200_VTX_POINT_SIZE (1<<7) # define R200_VTX_DISCRETE_FOG (1<<8) # define R200_VTX_SHININESS_0 (1<<9) # define R200_VTX_SHININESS_1 (1<<10) # define R200_VTX_COLOR_NOT_PRESENT 0 # define R200_VTX_PK_RGBA 1 # define R200_VTX_FP_RGB 2 # define R200_VTX_FP_RGBA 3 # define R200_VTX_COLOR_MASK 3 # define R200_VTX_COLOR_0_SHIFT 11 # define R200_VTX_COLOR_1_SHIFT 13 # define R200_VTX_COLOR_2_SHIFT 15 # define R200_VTX_COLOR_3_SHIFT 17 # define R200_VTX_COLOR_4_SHIFT 19 # define R200_VTX_COLOR_5_SHIFT 21 # define R200_VTX_COLOR_6_SHIFT 23 # define R200_VTX_COLOR_7_SHIFT 25 # define R200_VTX_XY1 (1<<28) # define R200_VTX_Z1 (1<<29) # define R200_VTX_W1 (1<<30) # define R200_VTX_N1 (1<<31) #define R200_SE_VTX_FMT_1 0x208c # define R200_VTX_TEX0_COMP_CNT_SHIFT 0 # define R200_VTX_TEX1_COMP_CNT_SHIFT 3 # define R200_VTX_TEX2_COMP_CNT_SHIFT 6 # define R200_VTX_TEX3_COMP_CNT_SHIFT 9 # define R200_VTX_TEX4_COMP_CNT_SHIFT 12 # define R200_VTX_TEX5_COMP_CNT_SHIFT 15 #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 # define R200_OUTPUT_XYZW (1<<0) # define R200_OUTPUT_COLOR_0 (1<<8) # define R200_OUTPUT_COLOR_1 (1<<9) # define R200_OUTPUT_TEX_0 (1<<16) # define R200_OUTPUT_TEX_1 (1<<17) # define R200_OUTPUT_TEX_2 (1<<18) # define R200_OUTPUT_TEX_3 (1<<19) # define R200_OUTPUT_TEX_4 (1<<20) # define R200_OUTPUT_TEX_5 (1<<21) # define R200_OUTPUT_TEX_MASK (0x3f<<16) # define R200_OUTPUT_DISCRETE_FOG (1<<24) # define R200_OUTPUT_PT_SIZE (1<<25) # define R200_FORCE_INORDER_PROC (1<<31) #define R200_PP_CNTL_X 0x2cc4 #define R200_PP_TXMULTI_CTL_0 0x2c1c #define R200_SE_VTX_STATE_CNTL 0x2180 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 #define RADEON_CP_ME_RAM_RADDR 0x07d8 #define RADEON_CP_ME_RAM_DATAH 0x07dc #define RADEON_CP_ME_RAM_DATAL 0x07e0 #define RADEON_CP_RB_BASE 0x0700 #define RADEON_CP_RB_CNTL 0x0704 #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_IB_BASE 0x0738 #define RADEON_CP_IB_BUFSZ 0x073c #define RADEON_CP_CSQ_CNTL 0x0740 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) # define RADEON_CSQ_PRIBM_INDBM (4 << 28) # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) #define RADEON_CP_CSQ_STAT 0x07f8 # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) #define RADEON_CP_CSQ_ADDR 0x07f0 #define RADEON_CP_CSQ_DATA 0x07f4 #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 #define RADEON_CP_RB_WPTR_DELAY 0x0718 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) #define RADEON_AIC_LO_ADDR 0x01dc /* Constants */ #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 #define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 /* CP packet types */ #define RADEON_CP_PACKET0 0x00000000 #define RADEON_CP_PACKET1 0x40000000 #define RADEON_CP_PACKET2 0x80000000 #define RADEON_CP_PACKET3 0xC0000000 # define RADEON_CP_PACKET_MASK 0xC0000000 # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) # define RADEON_CP_PACKET0_REG_MASK 0x000007ff # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 #define RADEON_CP_PACKET3_NOP 0xC0001000 #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 #define RADEON_CP_VC_FRMT_XY 0x00000000 #define RADEON_CP_VC_FRMT_W0 0x00000001 #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 #define RADEON_CP_VC_FRMT_ST0 0x00000080 #define RADEON_CP_VC_FRMT_ST1 0x00000100 #define RADEON_CP_VC_FRMT_Q1 0x00000200 #define RADEON_CP_VC_FRMT_ST2 0x00000400 #define RADEON_CP_VC_FRMT_Q2 0x00000800 #define RADEON_CP_VC_FRMT_ST3 0x00001000 #define RADEON_CP_VC_FRMT_Q3 0x00002000 #define RADEON_CP_VC_FRMT_Q0 0x00004000 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 #define RADEON_CP_VC_FRMT_N0 0x00040000 #define RADEON_CP_VC_FRMT_XY1 0x08000000 #define RADEON_CP_VC_FRMT_Z1 0x10000000 #define RADEON_CP_VC_FRMT_W1 0x20000000 #define RADEON_CP_VC_FRMT_N1 0x40000000 #define RADEON_CP_VC_FRMT_Z 0x80000000 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a #define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 #define RADEON_VS_MATRIX_0_ADDR 0 #define RADEON_VS_MATRIX_1_ADDR 4 #define RADEON_VS_MATRIX_2_ADDR 8 #define RADEON_VS_MATRIX_3_ADDR 12 #define RADEON_VS_MATRIX_4_ADDR 16 #define RADEON_VS_MATRIX_5_ADDR 20 #define RADEON_VS_MATRIX_6_ADDR 24 #define RADEON_VS_MATRIX_7_ADDR 28 #define RADEON_VS_MATRIX_8_ADDR 32 #define RADEON_VS_MATRIX_9_ADDR 36 #define RADEON_VS_MATRIX_10_ADDR 40 #define RADEON_VS_MATRIX_11_ADDR 44 #define RADEON_VS_MATRIX_12_ADDR 48 #define RADEON_VS_MATRIX_13_ADDR 52 #define RADEON_VS_MATRIX_14_ADDR 56 #define RADEON_VS_MATRIX_15_ADDR 60 #define RADEON_VS_LIGHT_AMBIENT_ADDR 64 #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 #define RADEON_VS_LIGHT_SPECULAR_ADDR 80 #define RADEON_VS_LIGHT_DIRPOS_ADDR 88 #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 #define RADEON_VS_UCP_ADDR 116 #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 #define RADEON_VS_FOG_PARAM_ADDR 123 #define RADEON_VS_EYE_VECTOR_ADDR 124 #define RADEON_SS_LIGHT_DCD_ADDR 0 #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 #define RADEON_SS_SHININESS 60 #define RADEON_TV_MASTER_CNTL 0x0800 # define RADEON_TV_ASYNC_RST (1 << 0) # define RADEON_CRT_ASYNC_RST (1 << 1) # define RADEON_RESTART_PHASE_FIX (1 << 3) # define RADEON_TV_FIFO_ASYNC_RST (1 << 4) # define RADEON_VIN_ASYNC_RST (1 << 5) # define RADEON_AUD_ASYNC_RST (1 << 6) # define RADEON_DVS_ASYNC_RST (1 << 7) # define RADEON_CRT_FIFO_CE_EN (1 << 9) # define RADEON_TV_FIFO_CE_EN (1 << 10) # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) # define RADEON_TV_ON (1 << 31) #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 # define RADEON_Y_RED_EN (1 << 0) # define RADEON_C_GRN_EN (1 << 1) # define RADEON_CMP_BLU_EN (1 << 2) # define RADEON_DAC_DITHER_EN (1 << 3) # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 #define RADEON_TV_RGB_CNTL 0x0804 # define RADEON_SWITCH_TO_BLUE (1 << 4) # define RADEON_RGB_DITHER_EN (1 << 5) # define RADEON_RGB_SRC_SEL_MASK (3 << 8) # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) # define RADEON_RGB_SRC_SEL_RMX (1 << 8) # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 # define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) # define RADEON_TVOUT_SCALE_EN (1 << 26) # define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) #define RADEON_TV_SYNC_CNTL 0x0808 # define RADEON_SYNC_OE (1 << 0) # define RADEON_SYNC_OUT (1 << 1) # define RADEON_SYNC_IN (1 << 2) # define RADEON_SYNC_PUB (1 << 3) # define RADEON_SYNC_PD (1 << 4) # define RADEON_TV_SYNC_IO_DRIVE (1 << 5) #define RADEON_TV_HTOTAL 0x080c #define RADEON_TV_HDISP 0x0810 #define RADEON_TV_HSTART 0x0818 #define RADEON_TV_HCOUNT 0x081C #define RADEON_TV_VTOTAL 0x0820 #define RADEON_TV_VDISP 0x0824 #define RADEON_TV_VCOUNT 0x0828 #define RADEON_TV_FTOTAL 0x082c #define RADEON_TV_FCOUNT 0x0830 #define RADEON_TV_FRESTART 0x0834 #define RADEON_TV_HRESTART 0x0838 #define RADEON_TV_VRESTART 0x083c #define RADEON_TV_HOST_READ_DATA 0x0840 #define RADEON_TV_HOST_WRITE_DATA 0x0844 #define RADEON_TV_HOST_RD_WT_CNTL 0x0848 # define RADEON_HOST_FIFO_RD (1 << 12) # define RADEON_HOST_FIFO_RD_ACK (1 << 13) # define RADEON_HOST_FIFO_WT (1 << 14) # define RADEON_HOST_FIFO_WT_ACK (1 << 15) #define RADEON_TV_VSCALER_CNTL1 0x084c # define RADEON_UV_INC_MASK 0xffff # define RADEON_UV_INC_SHIFT 0 # define RADEON_Y_W_EN (1 << 24) # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ # define RADEON_Y_DEL_W_SIG_SHIFT 26 #define RADEON_TV_TIMING_CNTL 0x0850 # define RADEON_H_INC_MASK 0xfff # define RADEON_H_INC_SHIFT 0 # define RADEON_REQ_Y_FIRST (1 << 19) # define RADEON_FORCE_BURST_ALWAYS (1 << 21) # define RADEON_UV_POST_SCALE_BYPASS (1 << 23) # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 #define RADEON_TV_VSCALER_CNTL2 0x0854 # define RADEON_DITHER_MODE (1 << 0) # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) #define RADEON_TV_Y_FALL_CNTL 0x0858 # define RADEON_Y_FALL_PING_PONG (1 << 16) # define RADEON_Y_COEF_EN (1 << 17) #define RADEON_TV_Y_RISE_CNTL 0x085c # define RADEON_Y_RISE_PING_PONG (1 << 16) #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 # define RADEON_YUPSAMP_EN (1 << 0) # define RADEON_UVUPSAMP_EN (1 << 2) #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 # define RADEON_Y_GAIN_LIMIT_SHIFT 0 # define RADEON_UV_GAIN_LIMIT_SHIFT 16 #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c # define RADEON_Y_GAIN_SHIFT 0 # define RADEON_UV_GAIN_SHIFT 16 #define RADEON_TV_MODULATOR_CNTL1 0x0870 # define RADEON_YFLT_EN (1 << 2) # define RADEON_UVFLT_EN (1 << 3) # define RADEON_ALT_PHASE_EN (1 << 6) # define RADEON_SYNC_TIP_LEVEL (1 << 7) # define RADEON_BLANK_LEVEL_SHIFT 8 # define RADEON_SET_UP_LEVEL_SHIFT 16 # define RADEON_SLEW_RATE_LIMIT (1 << 23) # define RADEON_CY_FILT_BLEND_SHIFT 28 #define RADEON_TV_MODULATOR_CNTL2 0x0874 # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff # define RADEON_TV_V_BURST_LEVEL_SHIFT 16 #define RADEON_TV_CRC_CNTL 0x0890 #define RADEON_TV_UV_ADR 0x08ac # define RADEON_MAX_UV_ADR_MASK 0x000000ff # define RADEON_MAX_UV_ADR_SHIFT 0 # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 # define RADEON_TABLE1_BOT_ADR_SHIFT 8 # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 # define RADEON_TABLE3_TOP_ADR_SHIFT 16 # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 # define RADEON_HCODE_TABLE_SEL_SHIFT 25 # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 # define RADEON_VCODE_TABLE_SEL_SHIFT 27 # define RADEON_TV_MAX_FIFO_ADDR 0x1a7 # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ # define RADEON_TV_M0LO_MASK 0xff # define RADEON_TV_M0HI_MASK 0x7 # define RADEON_TV_M0HI_SHIFT 18 # define RADEON_TV_N0LO_MASK 0x1ff # define RADEON_TV_N0LO_SHIFT 8 # define RADEON_TV_N0HI_MASK 0x3 # define RADEON_TV_N0HI_SHIFT 21 # define RADEON_TV_P_MASK 0xf # define RADEON_TV_P_SHIFT 24 # define RADEON_TV_SLIP_EN (1 << 23) # define RADEON_TV_DTO_EN (1 << 28) #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ # define RADEON_TVPLL_RESET (1 << 1) # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) # define RADEON_TVPCP_SHIFT 8 # define RADEON_TVPCP_MASK (7 << 8) # define RADEON_TVPVG_SHIFT 11 # define RADEON_TVPVG_MASK (7 << 11) # define RADEON_TVPDC_SHIFT 14 # define RADEON_TVPDC_MASK (3 << 14) # define RADEON_TVPLL_TEST_DIS (1 << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) #define RS400_DISP2_REQ_CNTL1 0xe30 # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff #define RS400_DISP2_REQ_CNTL2 0xe34 # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff #define RS400_DMIF_MEM_CNTL1 0xe38 # define RS400_DISP2_START_ADR_SHIFT 0 # define RS400_DISP2_START_ADR_MASK 0x3ff # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff #define RS400_DISP1_REQ_CNTL1 0xe3c # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff # define RS690_MC_INDEX_WR_EN (1 << 9) # define RS690_MC_INDEX_WR_ACK 0x7f #define RS690_MC_DATA 0x7c #define RS690_MC_FB_LOCATION 0x100 #define RS690_MC_AGP_LOCATION 0x101 #define RS690_MC_AGP_BASE 0x102 #define RS690_MC_AGP_BASE_2 0x103 #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 #define RS690_MC_STATUS 0x90 #define RS690_MC_STATUS_IDLE (1 << 0) #define RS600_MC_INDEX 0x70 # define RS600_MC_ADDR_MASK 0xffff # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) # define RS600_MC_IND_AIC_RBS (1 << 20) # define RS600_MC_IND_CITF_ARB0 (1 << 21) # define RS600_MC_IND_CITF_ARB1 (1 << 22) # define RS600_MC_IND_WR_EN (1 << 23) #define RS600_MC_DATA 0x74 #define RS600_MC_STATUS 0x0 # define RS600_MC_IDLE (1 << 1) #define RS600_MC_FB_LOCATION 0x4 #define RS600_MC_AGP_LOCATION 0x5 #define RS600_AGP_BASE 0x6 #define RS600_AGP_BASE2 0x7 #define AVIVO_MC_INDEX 0x0070 #define R520_MC_STATUS 0x00 # define R520_MC_STATUS_IDLE (1 << 1) #define RV515_MC_STATUS 0x08 # define RV515_MC_STATUS_IDLE (1 << 4) #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 #define AVIVO_MC_DATA 0x0074 #define RV515_MC_FB_LOCATION 0x1 #define RV515_MC_AGP_LOCATION 0x2 #define RV515_MC_AGP_BASE 0x3 #define RV515_MC_AGP_BASE_2 0x4 #define RV515_MC_CNTL 0x5 # define RV515_MEM_NUM_CHANNELS_MASK 0x3 #define R520_MC_FB_LOCATION 0x4 #define R520_MC_AGP_LOCATION 0x5 #define R520_MC_AGP_BASE 0x6 #define R520_MC_AGP_BASE_2 0x7 #define R520_MC_CNTL0 0x8 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) # define R520_MEM_NUM_CHANNELS_SHIFT 24 # define R520_MC_CHANNEL_SIZE (1 << 23) #define RS780_MC_INDEX 0x28f8 # define RS780_MC_INDEX_MASK 0x1ff # define RS780_MC_INDEX_WR_EN (1 << 9) #define RS780_MC_DATA 0x28fc #define R600_RAMCFG 0x2408 # define R600_CHANSIZE (1 << 7) # define R600_CHANSIZE_OVERRIDE (1 << 10) #define R600_SRBM_STATUS 0x0e50 #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ # define AVIVO_CP_FORCEON (1 << 0) #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ # define AVIVO_E2_FORCEON (1 << 0) #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ # define AVIVO_IDCT_FORCEON (1 << 0) #define AVIVO_HDP_FB_LOCATION 0x134 #define AVIVO_VGA_RENDER_CONTROL 0x0300 # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) #define AVIVO_D1VGA_CONTROL 0x0330 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) #define AVIVO_D2VGA_CONTROL 0x0338 #define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360 #define AVIVO_VGA25_PPLL_REF_DIV 0x0364 #define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368 #define AVIVO_VGA28_PPLL_REF_DIV 0x036c #define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370 #define AVIVO_VGA41_PPLL_REF_DIV 0x0374 #define AVIVO_VGA25_PPLL_FB_DIV 0x0378 #define AVIVO_VGA28_PPLL_FB_DIV 0x037c #define AVIVO_VGA41_PPLL_FB_DIV 0x0380 #define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384 #define AVIVO_VGA25_PPLL_POST_DIV 0x0388 #define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c #define AVIVO_VGA28_PPLL_POST_DIV 0x0390 #define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394 #define AVIVO_VGA41_PPLL_POST_DIV 0x0398 #define AVIVO_VGA25_PPLL_CNTL 0x039c #define AVIVO_VGA28_PPLL_CNTL 0x03a0 #define AVIVO_VGA41_PPLL_CNTL 0x03a4 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 #define AVIVO_EXT2_PPLL_REF_DIV 0x414 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c #define AVIVO_EXT1_PPLL_FB_DIV 0x430 #define AVIVO_EXT2_PPLL_FB_DIV 0x434 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 #define AVIVO_EXT2_PPLL_POST_DIV 0x444 #define AVIVO_EXT1_PPLL_CNTL 0x448 #define AVIVO_EXT2_PPLL_CNTL 0x44c #define AVIVO_P1PLL_CNTL 0x450 #define AVIVO_P2PLL_CNTL 0x454 #define AVIVO_P1PLL_INT_SS_CNTL 0x458 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c #define AVIVO_P1PLL_TMDSA_CNTL 0x460 #define AVIVO_P2PLL_LVTMA_CNTL 0x464 #define AVIVO_PCLK_CRTC1_CNTL 0x480 #define AVIVO_PCLK_CRTC2_CNTL 0x484 #define AVIVO_D1CRTC_H_TOTAL 0x6000 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 #define AVIVO_D1CRTC_H_SYNC_A 0x6008 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c #define AVIVO_D1CRTC_H_SYNC_B 0x6010 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 #define AVIVO_D1CRTC_V_TOTAL 0x6020 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 #define AVIVO_D1CRTC_V_SYNC_A 0x6028 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c #define AVIVO_D1CRTC_V_SYNC_B 0x6030 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 #define AVIVO_D1CRTC_CONTROL 0x6080 # define AVIVO_CRTC_EN (1<<0) #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 /* master controls */ #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc #define AVIVO_D1GRPH_ENABLE 0x6100 #define AVIVO_D1GRPH_CONTROL 0x6104 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) # define AVIVO_D1GRPH_SWAP_RB (1<<16) # define AVIVO_D1GRPH_TILED (1<<20) # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) #define AVIVO_D1GRPH_LUT_SEL 0x6108 #define R600_D1GRPH_SWAP_CONTROL 0x610C # define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) # define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) /* the *_HIGH surface regs are backwards; the D1 regs are in the D2 * block and vice versa. This applies to GRPH, CUR, etc. */ #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c #define AVIVO_D1GRPH_PITCH 0x6120 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 #define AVIVO_D1GRPH_X_START 0x612c #define AVIVO_D1GRPH_Y_START 0x6130 #define AVIVO_D1GRPH_X_END 0x6134 #define AVIVO_D1GRPH_Y_END 0x6138 #define AVIVO_D1GRPH_UPDATE 0x6144 # define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 #define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380 #define AVIVO_D1CUR_CONTROL 0x6400 # define AVIVO_D1CURSOR_EN (1<<0) # define AVIVO_D1CURSOR_MODE_SHIFT 8 # define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) # define AVIVO_D1CURSOR_MODE_24BPP (0x2) #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 #define AVIVO_D1CUR_UPDATE 0x6424 # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) #define AVIVO_DC_LUT_RW_SELECT 0x6480 #define AVIVO_DC_LUT_RW_MODE 0x6484 #define AVIVO_DC_LUT_RW_INDEX 0x6488 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c #define AVIVO_DC_LUT_PWL_DATA 0x6490 #define AVIVO_DC_LUT_30_COLOR 0x6494 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c #define AVIVO_DC_LUT_AUTOFILL 0x64a0 #define AVIVO_DC_LUTA_CONTROL 0x64c0 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff #define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548 # define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff # define AVIVO_DxMODE_PRIORITY_OFF (1 << 16) # define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20) # define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24) #define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c #define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48 #define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c #define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58 # define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf # define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 # define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf # define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 #define AVIVO_D1MODE_DATA_FORMAT 0x6528 # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c #define AVIVO_D1MODE_VLINE_START_END 0x6538 # define AVIVO_D1MODE_VLINE_START_SHIFT 0 # define AVIVO_D1MODE_VLINE_END_SHIFT 16 # define AVIVO_D1MODE_VLINE_INV (1 << 31) #define AVIVO_D1MODE_VLINE_STATUS 0x653c # define AVIVO_D1MODE_VLINE_STAT (1 << 12) #define AVIVO_D1MODE_VIEWPORT_START 0x6580 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 #define AVIVO_D1SCL_UPDATE 0x65cc # define AVIVO_D1SCL_UPDATE_LOCK (1<<16) /* second crtc */ #define AVIVO_D2CRTC_H_TOTAL 0x6800 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 #define AVIVO_D2CRTC_H_SYNC_A 0x6808 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c #define AVIVO_D2CRTC_H_SYNC_B 0x6810 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 #define AVIVO_D2CRTC_V_TOTAL 0x6820 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 #define AVIVO_D2CRTC_V_SYNC_A 0x6828 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c #define AVIVO_D2CRTC_V_SYNC_B 0x6830 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 #define AVIVO_D2CRTC_CONTROL 0x6880 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 #define AVIVO_D2GRPH_ENABLE 0x6900 #define AVIVO_D2GRPH_CONTROL 0x6904 #define AVIVO_D2GRPH_LUT_SEL 0x6908 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 #define AVIVO_D2GRPH_PITCH 0x6920 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 #define AVIVO_D2GRPH_X_START 0x692c #define AVIVO_D2GRPH_Y_START 0x6930 #define AVIVO_D2GRPH_X_END 0x6934 #define AVIVO_D2GRPH_Y_END 0x6938 #define AVIVO_D2GRPH_UPDATE 0x6944 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 #define AVIVO_D2CUR_CONTROL 0x6c00 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 #define AVIVO_D2CUR_SIZE 0x6c10 #define AVIVO_D2CUR_POSITION 0x6c14 #define RS690_DCP_CONTROL 0x6c9c #define AVIVO_D2MODE_DATA_FORMAT 0x6d28 #define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 #define AVIVO_D2SCL_UPDATE 0x6dcc #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 #define AVIVO_DACA_ENABLE 0x7800 # define AVIVO_DAC_ENABLE (1 << 0) #define AVIVO_DACA_SOURCE_SELECT 0x7804 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) # define AVIVO_DAC_SOURCE_TV (2 << 0) #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) #define AVIVO_DACA_POWERDOWN 0x7850 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) # define AVIVO_DACA_POWERDOWN_RED (1 << 24) #define AVIVO_DACB_ENABLE 0x7a00 #define AVIVO_DACB_SOURCE_SELECT 0x7a04 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) #define AVIVO_DACB_POWERDOWN 0x7a50 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) # define AVIVO_DACB_POWERDOWN_RED #define AVIVO_TMDSA_CNTL 0x7880 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 /* 78a8 appears to be some kind of (reasonably tolerant) clock? * 78d0 definitely hits the transmitter, definitely clock. */ /* MYSTERY1 This appears to control dithering? */ #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) #define AVIVO_LVTMA_CNTL 0x7a80 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) #define R500_LVTMA_CLOCK_ENABLE 0x7b00 #define R600_LVTMA_CLOCK_ENABLE 0x7b04 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) # define AVIVO_LVTMA_SYNCEN (1 << 8) # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) # define AVIVO_LVTMA_DIGON (1 << 16) # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) # define AVIVO_LVTMA_DIGON_POL (1 << 18) # define AVIVO_LVTMA_BLON (1 << 24) # define AVIVO_LVTMA_BLON_OVRD (1 << 25) # define AVIVO_LVTMA_BLON_POL (1 << 26) #define R500_LVTMA_PWRSEQ_STATE 0x7af4 #define R600_LVTMA_PWRSEQ_STATE 0x7af8 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 #define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_2 0x7e50 #define AVIVO_GPIO_3 0x7e60 #define AVIVO_DC_GPIO_HPD_MASK 0x7e90 #define AVIVO_DC_GPIO_HPD_A 0x7e94 #define AVIVO_DC_GPIO_HPD_EN 0x7e98 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c #define AVIVO_I2C_STATUS 0x7d30 # define AVIVO_I2C_STATUS_DONE (1 << 0) # define AVIVO_I2C_STATUS_NACK (1 << 1) # define AVIVO_I2C_STATUS_HALT (1 << 2) # define AVIVO_I2C_STATUS_GO (1 << 3) # define AVIVO_I2C_STATUS_MASK 0x7 /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe * DONE? */ # define AVIVO_I2C_STATUS_CMD_RESET 0x7 # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) #define AVIVO_I2C_STOP 0x7d34 #define AVIVO_I2C_START_CNTL 0x7d38 # define AVIVO_I2C_START (1 << 8) # define AVIVO_I2C_CONNECTOR0 (0 << 16) # define AVIVO_I2C_CONNECTOR1 (1 << 16) #define R520_I2C_START (1<<0) #define R520_I2C_STOP (1<<1) #define R520_I2C_RX (1<<2) #define R520_I2C_EN (1<<8) #define R520_I2C_DDC1 (0<<16) #define R520_I2C_DDC2 (1<<16) #define R520_I2C_DDC3 (2<<16) #define R520_I2C_DDC_MASK (3<<16) #define AVIVO_I2C_CONTROL2 0x7d3c # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) #define AVIVO_I2C_CONTROL3 0x7d40 /* Reading is done 4 bytes at a time: read the bottom 8 bits from * 7d44, four times in a row. * Writing is a little more complex. First write DATA with * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic * magic number, zz is, I think, the slave address, and yy is the byte * you want to write. */ #define AVIVO_I2C_DATA 0x7d44 #define R520_I2C_ADDR_COUNT_MASK (0x7) #define R520_I2C_DATA_COUNT_SHIFT (8) #define R520_I2C_DATA_COUNT_MASK (0xF00) #define AVIVO_I2C_CNTL 0x7d50 # define AVIVO_I2C_EN (1 << 0) # define AVIVO_I2C_RESET (1 << 8) #define R600_GENERAL_PWRMGT 0x618 # define R600_OPEN_DRAIN_PADS (1 << 11) #define R600_LOWER_GPIO_ENABLE 0x710 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 #define R600_MC_VM_FB_LOCATION 0x2180 #define R600_MC_VM_AGP_TOP 0x2184 #define R600_MC_VM_AGP_BOT 0x2188 #define R600_MC_VM_AGP_BASE 0x218c #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 #define R700_MC_VM_FB_LOCATION 0x2024 #define R700_MC_VM_AGP_TOP 0x2028 #define R700_MC_VM_AGP_BOT 0x202c #define R700_MC_VM_AGP_BASE 0x2030 #define R600_HDP_NONSURFACE_BASE 0x2c04 #define R600_BUS_CNTL 0x5420 #define R600_CONFIG_CNTL 0x5424 #define R600_CONFIG_MEMSIZE 0x5428 #define R600_CONFIG_F0_BASE 0x542C #define R600_CONFIG_APER_SIZE 0x5430 #define R600_ROM_CNTL 0x1600 # define R600_SCK_OVERWRITE (1 << 1) # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) #define R600_CG_SPLL_FUNC_CNTL 0x600 # define R600_SPLL_BYPASS_EN (1 << 3) #define R600_CG_SPLL_STATUS 0x60c # define R600_SPLL_CHG_STATUS (1 << 1) #define R600_BIOS_0_SCRATCH 0x1724 #define R600_BIOS_1_SCRATCH 0x1728 #define R600_BIOS_2_SCRATCH 0x172c #define R600_BIOS_3_SCRATCH 0x1730 #define R600_BIOS_4_SCRATCH 0x1734 #define R600_BIOS_5_SCRATCH 0x1738 #define R600_BIOS_6_SCRATCH 0x173c #define R600_BIOS_7_SCRATCH 0x1740 /* evergreen */ #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 #define EVERGREEN_D3VGA_CONTROL 0x3e0 #define EVERGREEN_D4VGA_CONTROL 0x3e4 #define EVERGREEN_D5VGA_CONTROL 0x3e8 #define EVERGREEN_D6VGA_CONTROL 0x3ec #define EVERGREEN_P1PLL_SS_CNTL 0x414 #define EVERGREEN_P2PLL_SS_CNTL 0x454 # define EVERGREEN_PxPLL_SS_EN (1 << 12) /* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ #define EVERGREEN_GRPH_ENABLE 0x6800 #define EVERGREEN_GRPH_CONTROL 0x6804 # define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) # define EVERGREEN_GRPH_DEPTH_8BPP 0 # define EVERGREEN_GRPH_DEPTH_16BPP 1 # define EVERGREEN_GRPH_DEPTH_32BPP 2 # define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) /* 8 BPP */ # define EVERGREEN_GRPH_FORMAT_INDEXED 0 /* 16 BPP */ # define EVERGREEN_GRPH_FORMAT_ARGB1555 0 # define EVERGREEN_GRPH_FORMAT_ARGB565 1 # define EVERGREEN_GRPH_FORMAT_ARGB4444 2 # define EVERGREEN_GRPH_FORMAT_AI88 3 # define EVERGREEN_GRPH_FORMAT_MONO16 4 # define EVERGREEN_GRPH_FORMAT_BGRA5551 5 /* 32 BPP */ # define EVERGREEN_GRPH_FORMAT_ARGB8888 0 # define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 # define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 # define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 # define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 # define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 # define EVERGREEN_GRPH_FORMAT_RGB111110 6 # define EVERGREEN_GRPH_FORMAT_BGR101111 7 #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) # define EVERGREEN_GRPH_ENDIAN_NONE 0 # define EVERGREEN_GRPH_ENDIAN_8IN16 1 # define EVERGREEN_GRPH_ENDIAN_8IN32 2 # define EVERGREEN_GRPH_ENDIAN_8IN64 3 # define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) # define EVERGREEN_GRPH_RED_SEL_R 0 # define EVERGREEN_GRPH_RED_SEL_G 1 # define EVERGREEN_GRPH_RED_SEL_B 2 # define EVERGREEN_GRPH_RED_SEL_A 3 # define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) # define EVERGREEN_GRPH_GREEN_SEL_G 0 # define EVERGREEN_GRPH_GREEN_SEL_B 1 # define EVERGREEN_GRPH_GREEN_SEL_A 2 # define EVERGREEN_GRPH_GREEN_SEL_R 3 # define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) # define EVERGREEN_GRPH_BLUE_SEL_B 0 # define EVERGREEN_GRPH_BLUE_SEL_A 1 # define EVERGREEN_GRPH_BLUE_SEL_R 2 # define EVERGREEN_GRPH_BLUE_SEL_G 3 # define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) # define EVERGREEN_GRPH_ALPHA_SEL_A 0 # define EVERGREEN_GRPH_ALPHA_SEL_R 1 # define EVERGREEN_GRPH_ALPHA_SEL_G 2 # define EVERGREEN_GRPH_ALPHA_SEL_B 3 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 # define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) # define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 #define EVERGREEN_GRPH_PITCH 0x6818 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 #define EVERGREEN_GRPH_X_START 0x682c #define EVERGREEN_GRPH_Y_START 0x6830 #define EVERGREEN_GRPH_X_END 0x6834 #define EVERGREEN_GRPH_Y_END 0x6838 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ #define EVERGREEN_CUR_CONTROL 0x6998 # define EVERGREEN_CURSOR_EN (1 << 0) # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) # define EVERGREEN_CURSOR_MONO 0 # define EVERGREEN_CURSOR_24_1 1 # define EVERGREEN_CURSOR_24_8_PRE_MULT 2 # define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) # define EVERGREEN_CURSOR_URGENT_ALWAYS 0 # define EVERGREEN_CURSOR_URGENT_1_8 1 # define EVERGREEN_CURSOR_URGENT_1_4 2 # define EVERGREEN_CURSOR_URGENT_3_8 3 # define EVERGREEN_CURSOR_URGENT_1_2 4 #define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 #define EVERGREEN_CUR_SIZE 0x69a0 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 #define EVERGREEN_CUR_POSITION 0x69a8 #define EVERGREEN_CUR_HOT_SPOT 0x69ac #define EVERGREEN_CUR_COLOR1 0x69b0 #define EVERGREEN_CUR_COLOR2 0x69b4 #define EVERGREEN_CUR_UPDATE 0x69b8 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) /* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ #define EVERGREEN_DC_LUT_RW_MODE 0x69e0 #define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 #define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 #define EVERGREEN_DC_LUT_PWL_DATA 0x69ec #define EVERGREEN_DC_LUT_30_COLOR 0x69f0 #define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 #define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 #define EVERGREEN_DC_LUT_AUTOFILL 0x69fc #define EVERGREEN_DC_LUT_CONTROL 0x6a00 #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 #define EVERGREEN_DATA_FORMAT 0x6b00 # define EVERGREEN_INTERLEAVE_EN (1 << 0) #define EVERGREEN_DESKTOP_HEIGHT 0x6b04 #define EVERGREEN_VLINE_START_END 0x6b08 # define EVERGREEN_VLINE_START_SHIFT 0 # define EVERGREEN_VLINE_END_SHIFT 16 # define EVERGREEN_VLINE_INV (1 << 31) #define EVERGREEN_VLINE_STATUS 0x6bb8 # define EVERGREEN_VLINE_STAT (1 << 12) #define EVERGREEN_VIEWPORT_START 0x6d70 #define EVERGREEN_VIEWPORT_SIZE 0x6d74 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ #define EVERGREEN_CRTC_CONTROL 0x6e70 # define EVERGREEN_CRTC_MASTER_EN (1 << 0) #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 #define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 #define EVERGREEN_DC_GPIO_HPD_A 0x64b4 #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 #define EVERGREEN_DC_GPIO_HPD_Y 0x64bc #define R300_GB_TILE_CONFIG 0x4018 # define R300_ENABLE_TILING (1 << 0) # define R300_PIPE_COUNT_RV350 (0 << 1) # define R300_PIPE_COUNT_R300 (3 << 1) # define R300_PIPE_COUNT_R420_3P (6 << 1) # define R300_PIPE_COUNT_R420 (7 << 1) # define R300_TILE_SIZE_8 (0 << 4) # define R300_TILE_SIZE_16 (1 << 4) # define R300_TILE_SIZE_32 (2 << 4) # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_GB_SELECT 0x401c #define R300_GB_ENABLE 0x4008 #define R300_GB_AA_CONFIG 0x4020 #define R400_GB_PIPE_SELECT 0x402c #define R300_GB_MSPOS0 0x4010 # define R300_MS_X0_SHIFT 0 # define R300_MS_Y0_SHIFT 4 # define R300_MS_X1_SHIFT 8 # define R300_MS_Y1_SHIFT 12 # define R300_MS_X2_SHIFT 16 # define R300_MS_Y2_SHIFT 20 # define R300_MSBD0_Y_SHIFT 24 # define R300_MSBD0_X_SHIFT 28 #define R300_GB_MSPOS1 0x4014 # define R300_MS_X3_SHIFT 0 # define R300_MS_Y3_SHIFT 4 # define R300_MS_X4_SHIFT 8 # define R300_MS_Y4_SHIFT 12 # define R300_MS_X5_SHIFT 16 # define R300_MS_Y5_SHIFT 20 # define R300_MSBD1_SHIFT 24 #define R300_GA_ENHANCE 0x4274 # define R300_GA_DEADLOCK_CNTL (1 << 0) # define R300_GA_FASTSYNC_CNTL (1 << 1) #define R300_GA_POLY_MODE 0x4288 # define R300_FRONT_PTYPE_POINT (0 << 4) # define R300_FRONT_PTYPE_LINE (1 << 4) # define R300_FRONT_PTYPE_TRIANGE (2 << 4) # define R300_BACK_PTYPE_POINT (0 << 7) # define R300_BACK_PTYPE_LINE (1 << 7) # define R300_BACK_PTYPE_TRIANGE (2 << 7) #define R300_GA_ROUND_MODE 0x428c # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) # define R300_COLOR_ROUND_TRUNC (0 << 2) # define R300_COLOR_ROUND_NEAREST (1 << 2) #define R300_GA_COLOR_CONTROL 0x4278 # define R300_RGB0_SHADING_SOLID (0 << 0) # define R300_RGB0_SHADING_FLAT (1 << 0) # define R300_RGB0_SHADING_GOURAUD (2 << 0) # define R300_ALPHA0_SHADING_SOLID (0 << 2) # define R300_ALPHA0_SHADING_FLAT (1 << 2) # define R300_ALPHA0_SHADING_GOURAUD (2 << 2) # define R300_RGB1_SHADING_SOLID (0 << 4) # define R300_RGB1_SHADING_FLAT (1 << 4) # define R300_RGB1_SHADING_GOURAUD (2 << 4) # define R300_ALPHA1_SHADING_SOLID (0 << 6) # define R300_ALPHA1_SHADING_FLAT (1 << 6) # define R300_ALPHA1_SHADING_GOURAUD (2 << 6) # define R300_RGB2_SHADING_SOLID (0 << 8) # define R300_RGB2_SHADING_FLAT (1 << 8) # define R300_RGB2_SHADING_GOURAUD (2 << 8) # define R300_ALPHA2_SHADING_SOLID (0 << 10) # define R300_ALPHA2_SHADING_FLAT (1 << 10) # define R300_ALPHA2_SHADING_GOURAUD (2 << 10) # define R300_RGB3_SHADING_SOLID (0 << 12) # define R300_RGB3_SHADING_FLAT (1 << 12) # define R300_RGB3_SHADING_GOURAUD (2 << 12) # define R300_ALPHA3_SHADING_SOLID (0 << 14) # define R300_ALPHA3_SHADING_FLAT (1 << 14) # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) #define R300_GA_OFFSET 0x4290 #define R500_SU_REG_DEST 0x42c8 #define R300_VAP_CNTL_STATUS 0x2140 # define R300_PVS_BYPASS (1 << 8) #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 #define R300_VAP_CNTL 0x2080 # define R300_PVS_NUM_SLOTS_SHIFT 0 # define R300_PVS_NUM_CNTLRS_SHIFT 4 # define R300_PVS_NUM_FPUS_SHIFT 8 # define R300_VF_MAX_VTX_NUM_SHIFT 18 # define R300_GL_CLIP_SPACE_DEF (0 << 22) # define R300_DX_CLIP_SPACE_DEF (1 << 22) # define R500_TCL_STATE_OPTIMIZATION (1 << 23) #define R300_VAP_VTE_CNTL 0x20B0 # define R300_VPORT_X_SCALE_ENA (1 << 0) # define R300_VPORT_X_OFFSET_ENA (1 << 1) # define R300_VPORT_Y_SCALE_ENA (1 << 2) # define R300_VPORT_Y_OFFSET_ENA (1 << 3) # define R300_VPORT_Z_SCALE_ENA (1 << 4) # define R300_VPORT_Z_OFFSET_ENA (1 << 5) # define R300_VTX_XY_FMT (1 << 8) # define R300_VTX_Z_FMT (1 << 9) # define R300_VTX_W0_FMT (1 << 10) #define R300_VAP_VTX_STATE_CNTL 0x2180 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 # define R300_DATA_TYPE_0_SHIFT 0 # define R300_DATA_TYPE_FLOAT_1 0 # define R300_DATA_TYPE_FLOAT_2 1 # define R300_DATA_TYPE_FLOAT_3 2 # define R300_DATA_TYPE_FLOAT_4 3 # define R300_DATA_TYPE_BYTE 4 # define R300_DATA_TYPE_D3DCOLOR 5 # define R300_DATA_TYPE_SHORT_2 6 # define R300_DATA_TYPE_SHORT_4 7 # define R300_DATA_TYPE_VECTOR_3_TTT 8 # define R300_DATA_TYPE_VECTOR_3_EET 9 # define R300_SKIP_DWORDS_0_SHIFT 4 # define R300_DST_VEC_LOC_0_SHIFT 8 # define R300_LAST_VEC_0 (1 << 13) # define R300_SIGNED_0 (1 << 14) # define R300_NORMALIZE_0 (1 << 15) # define R300_DATA_TYPE_1_SHIFT 16 # define R300_SKIP_DWORDS_1_SHIFT 20 # define R300_DST_VEC_LOC_1_SHIFT 24 # define R300_LAST_VEC_1 (1 << 29) # define R300_SIGNED_1 (1 << 30) # define R300_NORMALIZE_1 (1 << 31) #define R300_VAP_PROG_STREAM_CNTL_1 0x2154 # define R300_DATA_TYPE_2_SHIFT 0 # define R300_SKIP_DWORDS_2_SHIFT 4 # define R300_DST_VEC_LOC_2_SHIFT 8 # define R300_LAST_VEC_2 (1 << 13) # define R300_SIGNED_2 (1 << 14) # define R300_NORMALIZE_2 (1 << 15) # define R300_DATA_TYPE_3_SHIFT 16 # define R300_SKIP_DWORDS_3_SHIFT 20 # define R300_DST_VEC_LOC_3_SHIFT 24 # define R300_LAST_VEC_3 (1 << 29) # define R300_SIGNED_3 (1 << 30) # define R300_NORMALIZE_3 (1 << 31) #define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 # define R300_SWIZZLE_SELECT_X_0_SHIFT 0 # define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 # define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 # define R300_SWIZZLE_SELECT_W_0_SHIFT 9 # define R300_SWIZZLE_SELECT_X 0 # define R300_SWIZZLE_SELECT_Y 1 # define R300_SWIZZLE_SELECT_Z 2 # define R300_SWIZZLE_SELECT_W 3 # define R300_SWIZZLE_SELECT_FP_ZERO 4 # define R300_SWIZZLE_SELECT_FP_ONE 5 # define R300_WRITE_ENA_0_SHIFT 12 # define R300_WRITE_ENA_X 1 # define R300_WRITE_ENA_Y 2 # define R300_WRITE_ENA_Z 4 # define R300_WRITE_ENA_W 8 # define R300_SWIZZLE_SELECT_X_1_SHIFT 16 # define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 # define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 # define R300_SWIZZLE_SELECT_W_1_SHIFT 25 # define R300_WRITE_ENA_1_SHIFT 28 #define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 # define R300_SWIZZLE_SELECT_X_2_SHIFT 0 # define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 # define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 # define R300_SWIZZLE_SELECT_W_2_SHIFT 9 # define R300_WRITE_ENA_2_SHIFT 12 # define R300_SWIZZLE_SELECT_X_3_SHIFT 16 # define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 # define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 # define R300_SWIZZLE_SELECT_W_3_SHIFT 25 # define R300_WRITE_ENA_3_SHIFT 28 #define R300_VAP_PVS_CODE_CNTL_0 0x22D0 # define R300_PVS_FIRST_INST_SHIFT 0 # define R300_PVS_XYZW_VALID_INST_SHIFT 10 # define R300_PVS_LAST_INST_SHIFT 20 #define R300_VAP_PVS_CODE_CNTL_1 0x22D8 # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 # define R300_PVS_CODE_START 0 # define R300_PVS_CONST_START 512 # define R500_PVS_CONST_START 1024 # define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START) # define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START) # define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START) #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 /* PVS instructions */ /* Opcode and dst instruction */ #define R300_PVS_DST_OPCODE(x) ((x) << 0) /* Vector ops */ # define R300_VECTOR_NO_OP 0 # define R300_VE_DOT_PRODUCT 1 # define R300_VE_MULTIPLY 2 # define R300_VE_ADD 3 # define R300_VE_MULTIPLY_ADD 4 # define R300_VE_DISTANCE_VECTOR 5 # define R300_VE_FRACTION 6 # define R300_VE_MAXIMUM 7 # define R300_VE_MINIMUM 8 # define R300_VE_SET_GREATER_THAN_EQUAL 9 # define R300_VE_SET_LESS_THAN 10 # define R300_VE_MULTIPLYX2_ADD 11 # define R300_VE_MULTIPLY_CLAMP 12 # define R300_VE_FLT2FIX_DX 13 # define R300_VE_FLT2FIX_DX_RND 14 /* R500 additions */ # define R500_VE_PRED_SET_EQ_PUSH 15 # define R500_VE_PRED_SET_GT_PUSH 16 # define R500_VE_PRED_SET_GTE_PUSH 17 # define R500_VE_PRED_SET_NEQ_PUSH 18 # define R500_VE_COND_WRITE_EQ 19 # define R500_VE_COND_WRITE_GT 20 # define R500_VE_COND_WRITE_GTE 21 # define R500_VE_COND_WRITE_NEQ 22 # define R500_VE_COND_MUX_EQ 23 # define R500_VE_COND_MUX_GT 24 # define R500_VE_COND_MUX_GTE 25 # define R500_VE_SET_GREATER_THAN 26 # define R500_VE_SET_EQUAL 27 # define R500_VE_SET_NOT_EQUAL 28 /* Math ops */ # define R300_MATH_NO_OP 0 # define R300_ME_EXP_BASE2_DX 1 # define R300_ME_LOG_BASE2_DX 2 # define R300_ME_EXP_BASEE_FF 3 # define R300_ME_LIGHT_COEFF_DX 4 # define R300_ME_POWER_FUNC_FF 5 # define R300_ME_RECIP_DX 6 # define R300_ME_RECIP_FF 7 # define R300_ME_RECIP_SQRT_DX 8 # define R300_ME_RECIP_SQRT_FF 9 # define R300_ME_MULTIPLY 10 # define R300_ME_EXP_BASE2_FULL_DX 11 # define R300_ME_LOG_BASE2_FULL_DX 12 # define R300_ME_POWER_FUNC_FF_CLAMP_B 13 # define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 # define R300_ME_POWER_FUNC_FF_CLAMP_01 15 # define R300_ME_SIN 16 # define R300_ME_COS 17 /* R500 additions */ # define R500_ME_LOG_BASE2_IEEE 18 # define R500_ME_RECIP_IEEE 19 # define R500_ME_RECIP_SQRT_IEEE 20 # define R500_ME_PRED_SET_EQ 21 # define R500_ME_PRED_SET_GT 22 # define R500_ME_PRED_SET_GTE 23 # define R500_ME_PRED_SET_NEQ 24 # define R500_ME_PRED_SET_CLR 25 # define R500_ME_PRED_SET_INV 26 # define R500_ME_PRED_SET_POP 27 # define R500_ME_PRED_SET_RESTORE 28 /* macro */ # define R300_PVS_MACRO_OP_2CLK_MADD 0 # define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 #define R300_PVS_DST_MATH_INST (1 << 6) #define R300_PVS_DST_MACRO_INST (1 << 7) #define R300_PVS_DST_REG_TYPE(x) ((x) << 8) # define R300_PVS_DST_REG_TEMPORARY 0 # define R300_PVS_DST_REG_A0 1 # define R300_PVS_DST_REG_OUT 2 # define R500_PVS_DST_REG_OUT_REPL_X 3 # define R300_PVS_DST_REG_ALT_TEMPORARY 4 # define R300_PVS_DST_REG_INPUT 5 #define R300_PVS_DST_ADDR_MODE_1 (1 << 12) #define R300_PVS_DST_OFFSET(x) ((x) << 13) #define R300_PVS_DST_WE_X (1 << 20) #define R300_PVS_DST_WE_Y (1 << 21) #define R300_PVS_DST_WE_Z (1 << 22) #define R300_PVS_DST_WE_W (1 << 23) #define R300_PVS_DST_VE_SAT (1 << 24) #define R300_PVS_DST_ME_SAT (1 << 25) #define R300_PVS_DST_PRED_ENABLE (1 << 26) #define R300_PVS_DST_PRED_SENSE (1 << 27) #define R300_PVS_DST_DUAL_MATH_OP (1 << 28) #define R300_PVS_DST_ADDR_SEL(x) ((x) << 29) #define R300_PVS_DST_ADDR_MODE_0 (1 << 31) /* src operand instruction */ #define R300_PVS_SRC_REG_TYPE(x) ((x) << 0) # define R300_PVS_SRC_REG_TEMPORARY 0 # define R300_PVS_SRC_REG_INPUT 1 # define R300_PVS_SRC_REG_CONSTANT 2 # define R300_PVS_SRC_REG_ALT_TEMPORARY 3 #define R300_SPARE_0 (1 << 2) #define R300_PVS_SRC_ABS_XYZW (1 << 3) #define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) #define R300_PVS_SRC_OFFSET(x) ((x) << 5) #define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13) #define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16) #define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19) #define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22) # define R300_PVS_SRC_SELECT_X 0 # define R300_PVS_SRC_SELECT_Y 1 # define R300_PVS_SRC_SELECT_Z 2 # define R300_PVS_SRC_SELECT_W 3 # define R300_PVS_SRC_SELECT_FORCE_0 4 # define R300_PVS_SRC_SELECT_FORCE_1 5 #define R300_PVS_SRC_NEG_X (1 << 25) #define R300_PVS_SRC_NEG_Y (1 << 26) #define R300_PVS_SRC_NEG_Z (1 << 27) #define R300_PVS_SRC_NEG_W (1 << 28) #define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29) #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) #define R300_VAP_PVS_CONST_CNTL 0x22d4 # define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0) # define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) # define R300_VTX_COLOR_0_PRESENT (1 << 1) # define R300_VTX_COLOR_1_PRESENT (1 << 2) # define R300_VTX_COLOR_2_PRESENT (1 << 3) # define R300_VTX_COLOR_3_PRESENT (1 << 4) # define R300_VTX_PT_SIZE_PRESENT (1 << 16) #define R300_VAP_OUT_VTX_FMT_1 0x2094 # define R300_TEX_0_COMP_CNT_SHIFT 0 # define R300_TEX_1_COMP_CNT_SHIFT 3 # define R300_TEX_2_COMP_CNT_SHIFT 6 # define R300_TEX_3_COMP_CNT_SHIFT 9 # define R300_TEX_4_COMP_CNT_SHIFT 12 # define R300_TEX_5_COMP_CNT_SHIFT 15 # define R300_TEX_6_COMP_CNT_SHIFT 18 # define R300_TEX_7_COMP_CNT_SHIFT 21 #define R300_VAP_VTX_SIZE 0x20b4 #define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 #define R300_VAP_GB_VERT_DISC_ADJ 0x2224 #define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 #define R300_VAP_GB_HORZ_DISC_ADJ 0x222c #define R300_VAP_CLIP_CNTL 0x221c # define R300_UCP_ENA_0 (1 << 0) # define R300_UCP_ENA_1 (1 << 1) # define R300_UCP_ENA_2 (1 << 2) # define R300_UCP_ENA_3 (1 << 3) # define R300_UCP_ENA_4 (1 << 4) # define R300_UCP_ENA_5 (1 << 5) # define R300_PS_UCP_MODE_SHIFT 14 # define R300_CLIP_DISABLE (1 << 16) # define R300_UCP_CULL_ONLY_ENA (1 << 17) # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 #define R500_VAP_INDEX_OFFSET 0x208c #define R300_SU_TEX_WRAP 0x42a0 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 #define R300_SU_CULL_MODE 0x42b8 # define R300_CULL_FRONT (1 << 0) # define R300_CULL_BACK (1 << 1) # define R300_FACE_POS (0 << 2) # define R300_FACE_NEG (1 << 2) #define R300_SU_DEPTH_SCALE 0x42c0 #define R300_SU_DEPTH_OFFSET 0x42c4 #define R300_RS_COUNT 0x4300 # define R300_RS_COUNT_IT_COUNT_SHIFT 0 # define R300_RS_COUNT_IC_COUNT_SHIFT 7 # define R300_RS_COUNT_HIRES_EN (1 << 18) #define R300_RS_IP_0 0x4310 #define R300_RS_IP_1 0x4314 # define R300_RS_TEX_PTR(x) ((x) << 0) # define R300_RS_COL_PTR(x) ((x) << 6) # define R300_RS_COL_FMT(x) ((x) << 9) # define R300_RS_COL_FMT_RGBA 0 # define R300_RS_COL_FMT_RGB0 2 # define R300_RS_COL_FMT_RGB1 3 # define R300_RS_COL_FMT_000A 4 # define R300_RS_COL_FMT_0000 5 # define R300_RS_COL_FMT_0001 6 # define R300_RS_COL_FMT_111A 8 # define R300_RS_COL_FMT_1110 9 # define R300_RS_COL_FMT_1111 10 # define R300_RS_SEL_S(x) ((x) << 13) # define R300_RS_SEL_T(x) ((x) << 16) # define R300_RS_SEL_R(x) ((x) << 19) # define R300_RS_SEL_Q(x) ((x) << 22) # define R300_RS_SEL_C0 0 # define R300_RS_SEL_C1 1 # define R300_RS_SEL_C2 2 # define R300_RS_SEL_C3 3 # define R300_RS_SEL_K0 4 # define R300_RS_SEL_K1 5 #define R300_RS_INST_COUNT 0x4304 # define R300_INST_COUNT_RS(x) ((x) << 0) # define R300_RS_W_EN (1 << 4) # define R300_TX_OFFSET_RS(x) ((x) << 5) #define R300_RS_INST_0 0x4330 #define R300_RS_INST_1 0x4334 # define R300_INST_TEX_ID(x) ((x) << 0) # define R300_RS_INST_TEX_CN_WRITE (1 << 3) # define R300_INST_TEX_ADDR(x) ((x) << 6) #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 #define R300_TX_FILTER0_1 0x4404 #define R300_TX_FILTER0_2 0x4408 # define R300_TX_CLAMP_S(x) ((x) << 0) # define R300_TX_CLAMP_T(x) ((x) << 3) # define R300_TX_CLAMP_R(x) ((x) << 6) # define R300_TX_CLAMP_WRAP 0 # define R300_TX_CLAMP_MIRROR 1 # define R300_TX_CLAMP_CLAMP_LAST 2 # define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 # define R300_TX_CLAMP_CLAMP_BORDER 4 # define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 # define R300_TX_CLAMP_CLAMP_GL 6 # define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 # define R300_TX_MAG_FILTER_NEAREST (1 << 9) # define R300_TX_MIN_FILTER_NEAREST (1 << 11) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) # define R300_TX_MIN_FILTER_LINEAR (2 << 11) # define R300_TX_ID_SHIFT 28 #define R300_TX_FILTER1_0 0x4440 #define R300_TX_FILTER1_1 0x4444 #define R300_TX_FILTER1_2 0x4448 #define R300_TX_FORMAT0_0 0x4480 #define R300_TX_FORMAT0_1 0x4484 #define R300_TX_FORMAT0_2 0x4488 # define R300_TXWIDTH_SHIFT 0 # define R300_TXHEIGHT_SHIFT 11 # define R300_TXDEPTH_SHIFT 22 # define R300_NUM_LEVELS_SHIFT 26 # define R300_NUM_LEVELS_MASK 0x # define R300_TXPROJECTED (1 << 30) # define R300_TXPITCH_EN (1 << 31) #define R300_TX_FORMAT1_0 0x44c0 #define R300_TX_FORMAT1_1 0x44c4 #define R300_TX_FORMAT1_2 0x44c8 # define R300_TX_FORMAT_X8 0x0 # define R300_TX_FORMAT_X16 0x1 # define R300_TX_FORMAT_Y4X4 0x2 # define R300_TX_FORMAT_Y8X8 0x3 # define R300_TX_FORMAT_Y16X16 0x4 # define R300_TX_FORMAT_Z3Y3X2 0x5 # define R300_TX_FORMAT_Z5Y6X5 0x6 # define R300_TX_FORMAT_Z6Y5X5 0x7 # define R300_TX_FORMAT_Z11Y11X10 0x8 # define R300_TX_FORMAT_Z10Y11X11 0x9 # define R300_TX_FORMAT_W4Z4Y4X4 0xA # define R300_TX_FORMAT_W1Z5Y5X5 0xB # define R300_TX_FORMAT_W8Z8Y8X8 0xC # define R300_TX_FORMAT_W2Z10Y10X10 0xD # define R300_TX_FORMAT_W16Z16Y16X16 0xE # define R300_TX_FORMAT_DXT1 0xF # define R300_TX_FORMAT_DXT3 0x10 # define R300_TX_FORMAT_DXT5 0x11 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ # define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ # define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ # define R300_TX_FORMAT_X24_Y8 0x1e # define R300_TX_FORMAT_X32 0x1e /* Floating point formats */ /* Note - hardware supports both 16 and 32 bit floating point */ # define R300_TX_FORMAT_FL_I16 0x18 # define R300_TX_FORMAT_FL_I16A16 0x19 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A # define R300_TX_FORMAT_FL_I32 0x1B # define R300_TX_FORMAT_FL_I32A32 0x1C # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D /* alpha modes, convenience mostly */ /* if you have alpha, pick constant appropriate to the number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ # define R300_TX_FORMAT_ALPHA_1CH 0x000 # define R300_TX_FORMAT_ALPHA_2CH 0x200 # define R300_TX_FORMAT_ALPHA_4CH 0x600 # define R300_TX_FORMAT_ALPHA_NONE 0xA00 /* Swizzling */ /* constants */ # define R300_TX_FORMAT_X 0 # define R300_TX_FORMAT_Y 1 # define R300_TX_FORMAT_Z 2 # define R300_TX_FORMAT_W 3 # define R300_TX_FORMAT_ZERO 4 # define R300_TX_FORMAT_ONE 5 /* 2.0*Z, everything above 1.0 is set to 0.0 */ # define R300_TX_FORMAT_CUT_Z 6 /* 2.0*W, everything above 1.0 is set to 0.0 */ # define R300_TX_FORMAT_CUT_W 7 # define R300_TX_FORMAT_B_SHIFT 18 # define R300_TX_FORMAT_G_SHIFT 15 # define R300_TX_FORMAT_R_SHIFT 12 # define R300_TX_FORMAT_A_SHIFT 9 /* Convenience macro to take care of layout and swizzling */ # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ ((R300_TX_FORMAT_##B)<devPrivates, &radeon_sync_fence_private_key) static void radeon_sync_fence_set_triggered (SyncFence *fence) { ScreenPtr screen = fence->pScreen; radeon_sync_fence_private *private = SYNC_FENCE_PRIV(fence); /* Flush pending rendering operations */ radeon_cs_flush_indirect(xf86ScreenToScrn(screen)); fence->funcs.SetTriggered = private->set_triggered; fence->funcs.SetTriggered(fence); private->set_triggered = fence->funcs.SetTriggered; fence->funcs.SetTriggered = radeon_sync_fence_set_triggered; } static void radeon_sync_create_fence(ScreenPtr screen, SyncFence *fence, Bool initially_triggered) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen); radeon_sync_fence_private *private = SYNC_FENCE_PRIV(fence); screen_funcs->CreateFence = info->CreateFence; screen_funcs->CreateFence(screen, fence, initially_triggered); info->CreateFence = screen_funcs->CreateFence; screen_funcs->CreateFence = radeon_sync_create_fence; private->set_triggered = fence->funcs.SetTriggered; fence->funcs.SetTriggered = radeon_sync_fence_set_triggered; } Bool radeon_sync_init(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); SyncScreenFuncsPtr screen_funcs; if (!miSyncShmScreenInit(screen)) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "SYNC extension fences disabled because " "miSyncShmScreenInit failed\n"); return FALSE; } if (!dixPrivateKeyRegistered(&radeon_sync_fence_private_key)) { if (!dixRegisterPrivateKey(&radeon_sync_fence_private_key, PRIVATE_SYNC_FENCE, sizeof (radeon_sync_fence_private))) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "SYNC extension fences disabled because " "dixRegisterPrivateKey failed\n"); return FALSE; } } xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO, "SYNC extension fences enabled\n"); screen_funcs = miSyncGetScreenFuncs(screen); info->CreateFence = screen_funcs->CreateFence; screen_funcs->CreateFence = radeon_sync_create_fence; return TRUE; } void radeon_sync_close(ScreenPtr screen) { ScrnInfoPtr scrn = xf86ScreenToScrn(screen); RADEONInfoPtr info = RADEONPTR(scrn); SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen); if (screen_funcs && info->CreateFence) screen_funcs->CreateFence = info->CreateFence; info->CreateFence = NULL; } #else /* !HAVE_MISYNCSHM_H */ Bool radeon_sync_init(ScreenPtr screen) { xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO, "SYNC extension fences disabled because misyncshm.h not " "available at build time\n"); return FALSE; } void radeon_sync_close(ScreenPtr screen) { } #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_textured_video.c000066400000000000000000000606401256524674500250310ustar00rootroot00000000000000/* * Copyright 2008 Alex Deucher * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al. * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include #include #include #include "radeon.h" #include "radeon_reg.h" #include "radeon_probe.h" #include "radeon_video.h" #include #include "fourcc.h" extern void R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); extern void EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); #define IMAGE_MAX_WIDTH 2048 #define IMAGE_MAX_HEIGHT 2048 #define IMAGE_MAX_WIDTH_R500 4096 #define IMAGE_MAX_HEIGHT_R500 4096 #define IMAGE_MAX_WIDTH_R600 8192 #define IMAGE_MAX_HEIGHT_R600 8192 #define IMAGE_MAX_WIDTH_EG 16384 #define IMAGE_MAX_HEIGHT_EG 16384 static Bool RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) { return FALSE; } static __inline__ uint32_t F_TO_DW(float val) { union { float f; uint32_t l; } tmp; tmp.f = val; return tmp.l; } /* Borrowed from Mesa */ static __inline__ uint32_t F_TO_24(float val) { float mantissa; int exponent; uint32_t float24 = 0; if (val == 0.0) return 0; mantissa = frexpf(val, &exponent); /* Handle -ve */ if (mantissa < 0) { float24 |= (1 << 23); mantissa = mantissa * -1.0; } /* Handle exponent, bias of 63 */ exponent += 62; float24 |= (exponent << 16); /* Kill 7 LSB of mantissa */ float24 |= (F_TO_DW(mantissa) & 0x7FFFFF) >> 7; return float24; } static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) { unsigned ur = fr * 255.0 + 0.5; unsigned ug = fg * 255.0 + 0.5; unsigned ub = fb * 255.0 + 0.5; unsigned ua = fa * 255.0 + 0.5; return (ua << 24) | (ur << 16) | (ug << 8) | ub; } /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces note the difference to the parameters used in overlay are due to 10bit vs. float calcs */ static REF_TRANSFORM trans[2] = { {1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */ {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ }; /* Allocates memory, either by resizing the allocation pointed to by mem_struct, * or by freeing mem_struct (if non-NULL) and allocating a new space. The size * is measured in bytes, and the offset from the beginning of card space is * returned. */ static Bool radeon_allocate_video_bo(ScrnInfoPtr pScrn, struct radeon_bo **video_bo_p, int size, int align, int domain) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_bo *video_bo; if (*video_bo_p) radeon_bo_unref(*video_bo_p); video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0); *video_bo_p = video_bo; if (!video_bo) return FALSE; return TRUE; } static void RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { if (pPriv->video_memory != NULL) { radeon_bo_unref(pPriv->video_memory); pPriv->video_memory = NULL; if (pPriv->textured) { pPriv->src_bo[0] = NULL; radeon_bo_unref(pPriv->src_bo[1]); pPriv->src_bo[1] = NULL; } } } static void RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) { RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; if (pPriv->textured) { if (cleanup) { RADEONFreeVideoMemory(pScrn, pPriv); } return; } } #define OUT_ACCEL_REG_F(reg, val) OUT_RING_REG(reg, F_TO_DW(val)) #include "radeon_textured_videofuncs.c" #undef OUT_ACCEL_REG_F static void R600CopyData( ScrnInfoPtr pScrn, unsigned char *src, unsigned char *dst, unsigned int srcPitch, unsigned int dstPitch, unsigned int h, unsigned int w, unsigned int cpp ){ if (cpp == 2) { w *= 2; cpp = 1; } if (srcPitch == dstPitch) memcpy(dst, src, srcPitch * h); else { while (h--) { memcpy(dst, src, srcPitch); src += srcPitch; dst += dstPitch; } } } static int RADEONPutImageTextured(ScrnInfoPtr pScrn, short src_x, short src_y, short drw_x, short drw_y, short src_w, short src_h, short drw_w, short drw_h, int id, unsigned char *buf, short width, short height, Bool sync, RegionPtr clipBoxes, pointer data, DrawablePtr pDraw) { ScreenPtr pScreen = pScrn->pScreen; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; INT32 x1, x2, y1, y2; int srcPitch, srcPitch2, dstPitch, dstPitch2 = 0; int s2offset, s3offset, tmp; int d2line, d3line; int top, nlines, size; BoxRec dstBox; int dst_width = width, dst_height = height; int aligned_height; int h_align = drmmode_get_height_align(pScrn, 0); struct radeon_bo *src_bo; int ret; /* make the compiler happy */ s2offset = s3offset = srcPitch2 = 0; /* Clip */ x1 = src_x; x2 = src_x + src_w; y1 = src_y; y2 = src_y + src_h; dstBox.x1 = drw_x; dstBox.x2 = drw_x + drw_w; dstBox.y1 = drw_y; dstBox.y2 = drw_y + drw_h; if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height)) return Success; if ((x1 >= x2) || (y1 >= y2)) return Success; /* Bicubic filter setup */ pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); if (!(IS_R300_3D || IS_R500_3D)) { pPriv->bicubic_enabled = FALSE; pPriv->bicubic_state = BICUBIC_OFF; } if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { /* * Applying the bicubic filter with a scale of less than 200% * results in a blurred picture, so disable the filter. */ if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) pPriv->bicubic_enabled = FALSE; } if (info->ChipFamily >= CHIP_FAMILY_R600) pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0); else pPriv->hw_align = 64; aligned_height = RADEON_ALIGN(dst_height, h_align); switch(id) { case FOURCC_YV12: case FOURCC_I420: srcPitch = RADEON_ALIGN(width, 4); srcPitch2 = RADEON_ALIGN(width >> 1, 4); if (pPriv->bicubic_state != BICUBIC_OFF) { dstPitch = RADEON_ALIGN(dst_width << 1, pPriv->hw_align); dstPitch2 = 0; } else { dstPitch = RADEON_ALIGN(dst_width, pPriv->hw_align); dstPitch2 = RADEON_ALIGN(dstPitch >> 1, pPriv->hw_align); } break; case FOURCC_UYVY: case FOURCC_YUY2: default: dstPitch = RADEON_ALIGN(dst_width << 1, pPriv->hw_align); srcPitch = (width << 1); srcPitch2 = 0; break; } size = dstPitch * aligned_height + 2 * dstPitch2 * RADEON_ALIGN(((aligned_height + 1) >> 1), h_align); size = RADEON_ALIGN(size, pPriv->hw_align); if (size != pPriv->size) { RADEONFreeVideoMemory(pScrn, pPriv); } if (pPriv->video_memory == NULL) { Bool ret; ret = radeon_allocate_video_bo(pScrn, &pPriv->video_memory, size, pPriv->hw_align, RADEON_GEM_DOMAIN_GTT); if (ret == FALSE) return BadAlloc; pPriv->src_bo[0] = pPriv->video_memory; radeon_allocate_video_bo(pScrn, (void*)&pPriv->src_bo[1], size, pPriv->hw_align, RADEON_GEM_DOMAIN_GTT); } /* Bicubic filter loading */ if (pPriv->bicubic_enabled) { if (info->bicubic_bo == NULL) pPriv->bicubic_enabled = FALSE; } if (pDraw->type == DRAWABLE_WINDOW) pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw); else pPriv->pPixmap = (PixmapPtr)pDraw; /* Force the pixmap into framebuffer so we can draw to it. */ info->exa_force_create = TRUE; exaMoveInPixmap(pPriv->pPixmap); info->exa_force_create = FALSE; /* copy data */ top = (y1 >> 16) & ~1; nlines = ((y2 + 0xffff) >> 16) - top; pPriv->currentBuffer ^= 1; src_bo = pPriv->src_bo[pPriv->currentBuffer]; ret = radeon_bo_map(src_bo, 1); if (ret) return BadAlloc; pPriv->src_addr = src_bo->ptr; pPriv->src_pitch = dstPitch; pPriv->planeu_offset = dstPitch * aligned_height; pPriv->planeu_offset = RADEON_ALIGN(pPriv->planeu_offset, pPriv->hw_align); pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * RADEON_ALIGN(((aligned_height + 1) >> 1), h_align); pPriv->planev_offset = RADEON_ALIGN(pPriv->planev_offset, pPriv->hw_align); pPriv->size = size; pPriv->pDraw = pDraw; switch(id) { case FOURCC_YV12: case FOURCC_I420: s2offset = srcPitch * (RADEON_ALIGN(height, 2)); s3offset = s2offset + (srcPitch2 * ((height + 1) >> 1)); s2offset += ((top >> 1) * srcPitch2); s3offset += ((top >> 1) * srcPitch2); if (pPriv->bicubic_state != BICUBIC_OFF) { if (id == FOURCC_I420) { tmp = s2offset; s2offset = s3offset; s3offset = tmp; } RADEONCopyMungedData(pScrn, buf + (top * srcPitch), buf + s2offset, buf + s3offset, pPriv->src_addr + (top * dstPitch), srcPitch, srcPitch2, dstPitch, nlines, width); } else { if (id == FOURCC_YV12) { tmp = s2offset; s2offset = s3offset; s3offset = tmp; } d2line = pPriv->planeu_offset + ((top >> 1) * dstPitch2); d3line = pPriv->planev_offset + ((top >> 1) * dstPitch2); if (info->ChipFamily >= CHIP_FAMILY_R600) { R600CopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch), srcPitch, dstPitch, nlines, width, 1); R600CopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line, srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1); R600CopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line, srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1); } else { RADEONCopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch), srcPitch, dstPitch, nlines, width, 1); RADEONCopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line, srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1); RADEONCopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line, srcPitch2, dstPitch2, (nlines + 1) >> 1, width >> 1, 1); } } break; case FOURCC_UYVY: case FOURCC_YUY2: default: if (info->ChipFamily >= CHIP_FAMILY_R600) R600CopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch), srcPitch, dstPitch, nlines, width, 2); else RADEONCopyData(pScrn, buf + (top * srcPitch), pPriv->src_addr + (top * dstPitch), srcPitch, dstPitch, nlines, width, 2); break; } /* update cliplist */ if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); } pPriv->id = id; pPriv->src_w = src_w; pPriv->src_h = src_h; pPriv->src_x = src_x; pPriv->src_y = src_y; pPriv->drw_x = drw_x; pPriv->drw_y = drw_y; pPriv->dst_w = drw_w; pPriv->dst_h = drw_h; pPriv->w = width; pPriv->h = height; radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]); if (info->directRenderingEnabled) { if (IS_EVERGREEN_3D) EVERGREENDisplayTexturedVideo(pScrn, pPriv); else if (IS_R600_3D) R600DisplayTexturedVideo(pScrn, pPriv); else if (IS_R500_3D) R500DisplayTexturedVideo(pScrn, pPriv); else if (IS_R300_3D) R300DisplayTexturedVideo(pScrn, pPriv); else if (IS_R200_3D) R200DisplayTexturedVideo(pScrn, pPriv); else RADEONDisplayTexturedVideo(pScrn, pPriv); } return Success; } /* client libraries expect an encoding */ static XF86VideoEncodingRec DummyEncoding[1] = { { 0, "XV_IMAGE", IMAGE_MAX_WIDTH, IMAGE_MAX_HEIGHT, {1, 1} } }; static XF86VideoEncodingRec DummyEncodingR500[1] = { { 0, "XV_IMAGE", IMAGE_MAX_WIDTH_R500, IMAGE_MAX_HEIGHT_R500, {1, 1} } }; static XF86VideoEncodingRec DummyEncodingR600[1] = { { 0, "XV_IMAGE", IMAGE_MAX_WIDTH_R600, IMAGE_MAX_HEIGHT_R600, {1, 1} } }; static XF86VideoEncodingRec DummyEncodingEG[1] = { { 0, "XV_IMAGE", IMAGE_MAX_WIDTH_EG, IMAGE_MAX_HEIGHT_EG, {1, 1} } }; #define NUM_FORMATS 3 static XF86VideoFormatRec Formats[NUM_FORMATS] = { {15, TrueColor}, {16, TrueColor}, {24, TrueColor} }; #define NUM_ATTRIBUTES 2 static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = { {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, {0, 0, 0, NULL} }; #define NUM_ATTRIBUTES_R200 7 static XF86AttributeRec Attributes_r200[NUM_ATTRIBUTES_R200+1] = { {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, {0, 0, 0, NULL} }; #define NUM_ATTRIBUTES_R300 9 static XF86AttributeRec Attributes_r300[NUM_ATTRIBUTES_R300+1] = { {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"}, {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"}, {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, {0, 0, 0, NULL} }; #define NUM_ATTRIBUTES_R500 8 static XF86AttributeRec Attributes_r500[NUM_ATTRIBUTES_R500+1] = { {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"}, {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, {0, 0, 0, NULL} }; #define NUM_ATTRIBUTES_R600 7 static XF86AttributeRec Attributes_r600[NUM_ATTRIBUTES_R600+1] = { {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, {0, 0, 0, NULL} }; static XF86AttributeRec Attributes_eg[NUM_ATTRIBUTES_R600+1] = { {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, {XvSettable | XvGettable, -1, 5, "XV_CRTC"}, {0, 0, 0, NULL} }; static Atom xvBicubic; static Atom xvVSync; static Atom xvBrightness, xvContrast, xvSaturation, xvHue; static Atom xvGamma, xvColorspace; static Atom xvCRTC; #define NUM_IMAGES 4 static XF86ImageRec Images[NUM_IMAGES] = { XVIMAGE_YUY2, XVIMAGE_YV12, XVIMAGE_I420, XVIMAGE_UYVY }; int RADEONGetTexPortAttribute(ScrnInfoPtr pScrn, Atom attribute, INT32 *value, pointer data) { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; if (info->accelOn) RADEON_SYNC(info, pScrn); if (attribute == xvBicubic) *value = pPriv->bicubic_state; else if (attribute == xvVSync) *value = pPriv->vsync; else if (attribute == xvBrightness) *value = pPriv->brightness; else if (attribute == xvContrast) *value = pPriv->contrast; else if (attribute == xvSaturation) *value = pPriv->saturation; else if (attribute == xvHue) *value = pPriv->hue; else if (attribute == xvGamma) *value = pPriv->gamma; else if(attribute == xvColorspace) *value = pPriv->transform_index; else if(attribute == xvCRTC) { int c; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); for (c = 0; c < xf86_config->num_crtc; c++) if (xf86_config->crtc[c] == pPriv->desired_crtc) break; if (c == xf86_config->num_crtc) c = -1; *value = c; } else return BadMatch; return Success; } int RADEONSetTexPortAttribute(ScrnInfoPtr pScrn, Atom attribute, INT32 value, pointer data) { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; RADEON_SYNC(info, pScrn); if (attribute == xvBicubic) pPriv->bicubic_state = ClipValue (value, 0, 2); else if (attribute == xvVSync) pPriv->vsync = ClipValue (value, 0, 1); else if (attribute == xvBrightness) pPriv->brightness = ClipValue (value, -1000, 1000); else if (attribute == xvContrast) pPriv->contrast = ClipValue (value, -1000, 1000); else if (attribute == xvSaturation) pPriv->saturation = ClipValue (value, -1000, 1000); else if (attribute == xvHue) pPriv->hue = ClipValue (value, -1000, 1000); else if (attribute == xvGamma) pPriv->gamma = ClipValue (value, 100, 10000); else if(attribute == xvColorspace) pPriv->transform_index = ClipValue (value, 0, 1); else if(attribute == xvCRTC) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); if ((value < -1) || (value > xf86_config->num_crtc)) return BadValue; if (value < 0) pPriv->desired_crtc = NULL; else pPriv->desired_crtc = xf86_config->crtc[value]; } else return BadMatch; return Success; } Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); int ret; /* Bicubic filter loading */ ret = radeon_allocate_video_bo(pScrn, &info->bicubic_bo, sizeof(bicubic_tex_512), 64, RADEON_GEM_DOMAIN_VRAM); if (ret == FALSE) return FALSE; /* Upload bicubic filter tex */ if (info->ChipFamily < CHIP_FAMILY_R600) { uint8_t *bicubic_addr; int ret; ret = radeon_bo_map(info->bicubic_bo, 1); if (ret) return FALSE; bicubic_addr = info->bicubic_bo->ptr; RADEONCopySwap(bicubic_addr, (uint8_t *)bicubic_tex_512, 1024, #if X_BYTE_ORDER == X_BIG_ENDIAN RADEON_HOST_DATA_SWAP_16BIT #else RADEON_HOST_DATA_SWAP_NONE #endif ); radeon_bo_unmap(info->bicubic_bo); } return TRUE; } #if 0 /* XXX */ static void radeon_unload_bicubic_texture(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); if (info->bicubic_memory != NULL) { radeon_bo_unref(info->bicubic_memory); info->bicubic_memory = NULL; } } #endif static void RADEONQueryBestSize( ScrnInfoPtr pScrn, Bool motion, short vid_w, short vid_h, short drw_w, short drw_h, unsigned int *p_w, unsigned int *p_h, pointer data ){ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; if (!pPriv->textured) { if (vid_w > (drw_w << 4)) drw_w = vid_w >> 4; if (vid_h > (drw_h << 4)) drw_h = vid_h >> 4; } *p_w = drw_w; *p_h = drw_h; } #define FOURCC_RGB24 0x00000000 #define FOURCC_RGBT16 0x54424752 #define FOURCC_RGB16 0x32424752 #define FOURCC_RGBA32 0x41424752 static int RADEONQueryImageAttributes( ScrnInfoPtr pScrn, int id, unsigned short *w, unsigned short *h, int *pitches, int *offsets ){ const RADEONInfoRec * const info = RADEONPTR(pScrn); int size, tmp; if(*w > info->xv_max_width) *w = info->xv_max_width; if(*h > info->xv_max_height) *h = info->xv_max_height; *w = RADEON_ALIGN(*w, 2); if(offsets) offsets[0] = 0; switch(id) { case FOURCC_YV12: case FOURCC_I420: *h = RADEON_ALIGN(*h, 2); size = RADEON_ALIGN(*w, 4); if(pitches) pitches[0] = size; size *= *h; if(offsets) offsets[1] = size; tmp = RADEON_ALIGN(*w >> 1, 4); if(pitches) pitches[1] = pitches[2] = tmp; tmp *= (*h >> 1); size += tmp; if(offsets) offsets[2] = size; size += tmp; break; case FOURCC_RGBA32: size = *w << 2; if(pitches) pitches[0] = size; size *= *h; break; case FOURCC_RGB24: size = *w * 3; if(pitches) pitches[0] = size; size *= *h; break; case FOURCC_RGBT16: case FOURCC_RGB16: case FOURCC_UYVY: case FOURCC_YUY2: default: size = *w << 1; if(pitches) pitches[0] = size; size *= *h; break; } return size; } XF86VideoAdaptorPtr RADEONSetupImageTexturedVideo(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPortPriv; XF86VideoAdaptorPtr adapt; int i; int num_texture_ports = 16; adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports * (sizeof(RADEONPortPrivRec) + sizeof(DevUnion))); if (adapt == NULL) return NULL; xvBicubic = MAKE_ATOM("XV_BICUBIC"); xvVSync = MAKE_ATOM("XV_VSYNC"); xvBrightness = MAKE_ATOM("XV_BRIGHTNESS"); xvContrast = MAKE_ATOM("XV_CONTRAST"); xvSaturation = MAKE_ATOM("XV_SATURATION"); xvHue = MAKE_ATOM("XV_HUE"); xvGamma = MAKE_ATOM("XV_GAMMA"); xvColorspace = MAKE_ATOM("XV_COLORSPACE"); xvCRTC = MAKE_ATOM("XV_CRTC"); adapt->type = XvWindowMask | XvInputMask | XvImageMask; adapt->flags = 0; adapt->name = "Radeon Textured Video"; adapt->nEncodings = 1; if (IS_EVERGREEN_3D) adapt->pEncodings = DummyEncodingEG; else if (IS_R600_3D) adapt->pEncodings = DummyEncodingR600; else if (IS_R500_3D) adapt->pEncodings = DummyEncodingR500; else adapt->pEncodings = DummyEncoding; adapt->nFormats = NUM_FORMATS; adapt->pFormats = Formats; adapt->nPorts = num_texture_ports; adapt->pPortPrivates = (DevUnion*)(&adapt[1]); pPortPriv = (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]); if (IS_EVERGREEN_3D) { adapt->pAttributes = Attributes_eg; adapt->nAttributes = NUM_ATTRIBUTES_R600; } else if (IS_R600_3D) { adapt->pAttributes = Attributes_r600; adapt->nAttributes = NUM_ATTRIBUTES_R600; } else if (IS_R500_3D) { adapt->pAttributes = Attributes_r500; adapt->nAttributes = NUM_ATTRIBUTES_R500; } else if (IS_R300_3D) { adapt->pAttributes = Attributes_r300; adapt->nAttributes = NUM_ATTRIBUTES_R300; } else if (IS_R200_3D) { adapt->pAttributes = Attributes_r200; adapt->nAttributes = NUM_ATTRIBUTES_R200; } else { adapt->pAttributes = Attributes; adapt->nAttributes = NUM_ATTRIBUTES; } adapt->pImages = Images; adapt->nImages = NUM_IMAGES; adapt->PutVideo = NULL; adapt->PutStill = NULL; adapt->GetVideo = NULL; adapt->GetStill = NULL; adapt->StopVideo = RADEONStopVideo; adapt->SetPortAttribute = RADEONSetTexPortAttribute; adapt->GetPortAttribute = RADEONGetTexPortAttribute; adapt->QueryBestSize = RADEONQueryBestSize; adapt->PutImage = RADEONPutImageTextured; adapt->ReputImage = NULL; adapt->QueryImageAttributes = RADEONQueryImageAttributes; for (i = 0; i < num_texture_ports; i++) { RADEONPortPrivPtr pPriv = &pPortPriv[i]; pPriv->textured = TRUE; pPriv->bicubic_state = BICUBIC_OFF; pPriv->vsync = TRUE; pPriv->brightness = 0; pPriv->contrast = 0; pPriv->saturation = 0; pPriv->hue = 0; pPriv->gamma = 1000; pPriv->transform_index = 0; pPriv->desired_crtc = NULL; /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ REGION_NULL(pScreen, &pPriv->clip); adapt->pPortPrivates[i].ptr = (pointer) (pPriv); } if (IS_R500_3D || IS_R300_3D) radeon_load_bicubic_texture(pScrn); info->xv_max_width = adapt->pEncodings->width; info->xv_max_height = adapt->pEncodings->height; return adapt; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_textured_videofuncs.c000066400000000000000000004365061256524674500261000ustar00rootroot00000000000000/* * Copyright 2008 Alex Deucher * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al. * */ #define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ OUT_RING(F_TO_DW(_dstX)); \ OUT_RING(F_TO_DW(_dstY)); \ OUT_RING(F_TO_DW(_srcX)); \ OUT_RING(F_TO_DW(_srcY)); \ OUT_RING(F_TO_DW(_maskX)); \ OUT_RING(F_TO_DW(_maskY)); \ } while (0) #define VTX_OUT_4(_dstX, _dstY, _srcX, _srcY) \ do { \ OUT_RING(F_TO_DW(_dstX)); \ OUT_RING(F_TO_DW(_dstY)); \ OUT_RING(F_TO_DW(_srcX)); \ OUT_RING(F_TO_DW(_srcY)); \ } while (0) static Bool RADEONPrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer]; uint32_t txformat, txsize, txpitch; uint32_t dst_pitch, dst_format; uint32_t colorpitch; int pixel_shift; int scissor_w = MIN(pPixmap->drawable.width, 2048) - 1; int scissor_h = MIN(pPixmap->drawable.height, 2048) - 1; int ret; radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); if (pPriv->bicubic_enabled) radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); driver_priv = exaGetPixmapDriverPrivate(pPixmap); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) { ErrorF("Not enough RAM to hw accel xv operation\n"); return FALSE; } pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pPixmap); RADEON_SWITCH_TO_3D(); /* Same for R100/R200 */ switch (pPixmap->drawable.bitsPerPixel) { case 16: if (pPixmap->drawable.depth == 15) dst_format = RADEON_COLOR_FORMAT_ARGB1555; else dst_format = RADEON_COLOR_FORMAT_RGB565; break; case 32: dst_format = RADEON_COLOR_FORMAT_ARGB8888; break; default: return FALSE; } if (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12) { pPriv->is_planar = TRUE; txformat = RADEON_TXFORMAT_Y8; } else { pPriv->is_planar = FALSE; if (pPriv->id == FOURCC_UYVY) txformat = RADEON_TXFORMAT_YVYU422; else txformat = RADEON_TXFORMAT_VYUY422; } txformat |= RADEON_TXFORMAT_NON_POWER2; colorpitch = dst_pitch >> pixel_shift; if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= RADEON_COLOR_TILE_ENABLE; BEGIN_ACCEL_RELOC(4,2); OUT_RING_REG(RADEON_RB3D_CNTL, dst_format); EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pPixmap); EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pPixmap); OUT_RING_REG(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); ADVANCE_RING(); if (pPriv->is_planar) { /* need 2 texcoord sets (even though they are identical) due to denormalization! hw apparently can't premultiply same coord set by different texture size */ pPriv->vtx_count = 6; txsize = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | (((((pPriv->h + 1 ) >> 1) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); txpitch = RADEON_ALIGN(pPriv->src_pitch >> 1, 64); txpitch -= 32; BEGIN_ACCEL_RELOC(23, 3); OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0 | RADEON_SE_VTX_FMT_ST1)); OUT_RING_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_BLEND_1_ENABLE | RADEON_TEX_2_ENABLE | RADEON_TEX_BLEND_2_ENABLE | RADEON_PLANAR_YUV_ENABLE)); /* Y */ OUT_RING_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR | RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_YUV_TO_RGB); OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0); OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, 0, src_bo); OUT_RING_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_T0_ALPHA | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TEX_SIZE_0, (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(RADEON_PP_TEX_PITCH_0, pPriv->src_pitch - 32); /* U */ OUT_RING_REG(RADEON_PP_TXFILTER_1, RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR | RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST); OUT_RING_REG(RADEON_PP_TXFORMAT_1, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1); OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_1, pPriv->planeu_offset, src_bo); OUT_RING_REG(RADEON_PP_TXCBLEND_1, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TXABLEND_1, RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_T0_ALPHA | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TEX_SIZE_1, txsize); OUT_RING_REG(RADEON_PP_TEX_PITCH_1, txpitch); /* V */ OUT_RING_REG(RADEON_PP_TXFILTER_2, RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR | RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST); OUT_RING_REG(RADEON_PP_TXFORMAT_2, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1); OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_2, pPriv->planev_offset, src_bo); OUT_RING_REG(RADEON_PP_TXCBLEND_2, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TXABLEND_2, RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_T0_ALPHA | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TEX_SIZE_2, txsize); OUT_RING_REG(RADEON_PP_TEX_PITCH_2, txpitch); ADVANCE_RING(); } else { pPriv->vtx_count = 4; BEGIN_ACCEL_RELOC(9, 1); OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0)); OUT_RING_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_RING_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR | RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_YUV_TO_RGB); OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0); OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, 0, src_bo); OUT_RING_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_T0_ALPHA | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX); OUT_RING_REG(RADEON_PP_TEX_SIZE_0, (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(RADEON_PP_TEX_PITCH_0, pPriv->src_pitch - 32); ADVANCE_RING(); } BEGIN_RING(2*2); OUT_RING_REG(RADEON_RE_TOP_LEFT, 0); OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) | (scissor_h << RADEON_RE_HEIGHT_SHIFT))); ADVANCE_RING(); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) RADEONWaitForVLine(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } return TRUE; } static void RADEONDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; int dstxoff, dstyoff; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif if (!RADEONPrepareTexturedVideo(pScrn, pPriv)) return; /* * Rendering of the actual polygon is done in two different * ways depending on chip generation: * * < R300: * * These chips can render a rectangle in one pass, so * handling is pretty straight-forward. * * >= R300: * * These chips can accept a quad, but will render it as * two triangles which results in a diagonal tear. Instead * We render a single, large triangle and use the scissor * functionality to restrict it to the desired rectangle. * Due to guardband limits on r3xx/r4xx, we can only use * the single triangle up to 2560/4021 pixels; above that we * render as a quad. */ while (nBox) { int draw_size = 3 * pPriv->vtx_count + 5; int loop_boxes; if (draw_size > radeon_cs_space_remaining(pScrn)) { radeon_cs_flush_indirect(pScrn); if (!RADEONPrepareTexturedVideo(pScrn, pPriv)) return; } loop_boxes = MIN(radeon_cs_space_remaining(pScrn) / draw_size, nBox); nBox -= loop_boxes; BEGIN_RING(loop_boxes * 3 * pPriv->vtx_count + 5); OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, loop_boxes * 3 * pPriv->vtx_count + 1)); if (pPriv->is_planar) OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_ST1); else OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | ((loop_boxes * 3) << RADEON_CP_VC_CNTL_NUM_SHIFT)); while (loop_boxes--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; if (pPriv->is_planar) { /* * Just render a rect (using three coords). */ VTX_OUT_6((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_6((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); } else { /* * Just render a rect (using three coords). */ VTX_OUT_4((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); } pBox++; } OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); } DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } static Bool R200PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer]; uint32_t txformat; uint32_t txfilter, txsize, txpitch; uint32_t dst_pitch, dst_format; uint32_t colorpitch; int pixel_shift; int scissor_w = MIN(pPixmap->drawable.width, 2048) - 1; int scissor_h = MIN(pPixmap->drawable.height, 2048) - 1; /* note: in contrast to r300, use input biasing on uv components */ const float Loff = -0.0627; float uvcosf, uvsinf; float yco, yoff; float uco[3], vco[3]; float bright, cont, sat; int ref = pPriv->transform_index; float ucscale = 0.25, vcscale = 0.25; Bool needux8 = FALSE, needvx8 = FALSE; int ret; radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); if (pPriv->bicubic_enabled) radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); driver_priv = exaGetPixmapDriverPrivate(pPixmap); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) { ErrorF("Not enough RAM to hw accel xv operation\n"); return FALSE; } pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pPixmap); RADEON_SWITCH_TO_3D(); /* Same for R100/R200 */ switch (pPixmap->drawable.bitsPerPixel) { case 16: if (pPixmap->drawable.depth == 15) dst_format = RADEON_COLOR_FORMAT_ARGB1555; else dst_format = RADEON_COLOR_FORMAT_RGB565; break; case 32: dst_format = RADEON_COLOR_FORMAT_ARGB8888; break; default: return FALSE; } if (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12) { pPriv->is_planar = TRUE; txformat = RADEON_TXFORMAT_I8; } else { pPriv->is_planar = FALSE; if (pPriv->id == FOURCC_UYVY) txformat = RADEON_TXFORMAT_YVYU422; else txformat = RADEON_TXFORMAT_VYUY422; } txformat |= RADEON_TXFORMAT_NON_POWER2; colorpitch = dst_pitch >> pixel_shift; if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= RADEON_COLOR_TILE_ENABLE; BEGIN_ACCEL_RELOC(4,2); OUT_RING_REG(RADEON_RB3D_CNTL, dst_format); EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pPixmap); EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pPixmap); OUT_RING_REG(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); ADVANCE_RING(); txfilter = R200_MAG_FILTER_LINEAR | R200_MIN_FILTER_LINEAR | R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; /* contrast can cause constant overflow, clamp */ cont = RTFContrast(pPriv->contrast); if (cont * trans[ref].RefLuma > 2.0) cont = 2.0 / trans[ref].RefLuma; /* brightness is only from -0.5 to 0.5 should be safe */ bright = RTFBrightness(pPriv->brightness); /* saturation can also cause overflow, clamp */ sat = RTFSaturation(pPriv->saturation); if (sat * trans[ref].RefBCb > 4.0) sat = 4.0 / trans[ref].RefBCb; uvcosf = sat * cos(RTFHue(pPriv->hue)); uvsinf = sat * sin(RTFHue(pPriv->hue)); yco = trans[ref].RefLuma * cont; uco[0] = -trans[ref].RefRCr * uvsinf; uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; uco[2] = trans[ref].RefBCb * uvcosf; vco[0] = trans[ref].RefRCr * uvcosf; vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; vco[2] = trans[ref].RefBCb * uvsinf; yoff = Loff * yco + bright; if ((uco[0] > 2.0) || (uco[2] > 2.0)) { needux8 = TRUE; ucscale = 0.125; } if ((vco[0] > 2.0) || (vco[2] > 2.0)) { needvx8 = TRUE; vcscale = 0.125; } if (pPriv->is_planar) { /* need 2 texcoord sets (even though they are identical) due to denormalization! hw apparently can't premultiply same coord set by different texture size */ pPriv->vtx_count = 6; txsize = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | (((((pPriv->h + 1 ) >> 1) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); txpitch = RADEON_ALIGN(pPriv->src_pitch >> 1, 64); txpitch -= 32; BEGIN_ACCEL_RELOC(36, 3); OUT_RING_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE | RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | RADEON_TEX_BLEND_2_ENABLE); OUT_RING_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); OUT_RING_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); OUT_RING_REG(R200_PP_TXFILTER_0, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_0, txformat); OUT_RING_REG(R200_PP_TXFORMAT_X_0, 0); OUT_RING_REG(R200_PP_TXSIZE_0, (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, 0, src_bo); OUT_RING_REG(R200_PP_TXFILTER_1, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); OUT_RING_REG(R200_PP_TXFORMAT_X_1, 0); OUT_RING_REG(R200_PP_TXSIZE_1, txsize); OUT_RING_REG(R200_PP_TXPITCH_1, txpitch); OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, pPriv->planeu_offset, src_bo); OUT_RING_REG(R200_PP_TXFILTER_2, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); OUT_RING_REG(R200_PP_TXFORMAT_X_2, 0); OUT_RING_REG(R200_PP_TXSIZE_2, txsize); OUT_RING_REG(R200_PP_TXPITCH_2, txpitch); OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, pPriv->planev_offset, src_bo); /* similar to r300 code. Note the big problem is that hardware constants * are 8 bits only, representing 0.0-1.0. We can get that up (using bias * + scale) to -1.0-1.0 (but precision will suffer). AFAIK the hw actually * has 12 bits fractional precision (plus 1 sign bit, 3 range bits) but * the constants not. To get larger range can use output scale, but for * that 2.018 value we need a total scale by 8, which means the constants * really have no accuracy whatsoever (5 fractional bits only). * The only direct way to get high precision "constants" into the fragment * pipe I know of is to use the texcoord interpolator (not color, this one * is 8 bit only too), which seems a bit expensive. We're lucky though it * seems the values we need seem to fit better than worst case (get about * 6 fractional bits for this instead of 5, at least when not correcting for * hue/saturation/contrast/brightness, which is the same as for vco - yco and * yoff get 8 fractional bits). Try to preserve as much accuracy as possible * even with non-default saturation/hue/contrast/brightness adjustments, * it gets a little crazy and ultimately precision might still be lacking. * * A higher precision (8 fractional bits) version might just put uco into * a texcoord, and calculate a new vcoconst in the shader, like so: * cohelper = {1.0, 0.0, 0.0} - shouldn't use 0.5 since not exactly representable * vco = {1.5958 - 1.0, -0.8129 + 1.0, 1.0} * vcocalc = ADD temp, bias/scale(cohelper), vco * would in total use 4 tex units, 4 instructions which seems fairly * balanced for this architecture (instead of 3 + 3 for the solution here) * * temp = MAD(yco, yuv.yyyy, yoff) * temp = MAD(uco, yuv.uuuu, temp) * result = MAD(vco, yuv.vvvv, temp) * * note first mad produces actually scalar, hence we transform * it into a dp2a to get 8 bit precision of yco instead of 7 - * That's assuming hw correctly expands consts to internal precision. * (y * 1 + y * (yco - 1) + yoff) * temp = DP2A / 2 (yco, yuv.yyyy, yoff) * temp = MAD (uco / 4, yuv.uuuu * 2, temp) * result = MAD x2 (vco / 2, yuv.vvvv, temp) * * vco, uco need bias (and hence scale too) * */ /* MAD temp0 / 2, const0.a * 2, temp0, -const0.rgb */ OUT_RING_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_ARG_B_R0_COLOR | R200_TXC_ARG_C_TFACTOR_COLOR | (yoff < 0 ? R200_TXC_NEG_ARG_C : 0) | R200_TXC_OP_DOT2_ADD); OUT_RING_REG(R200_PP_TXCBLEND2_0, (0 << R200_TXC_TFACTOR_SEL_SHIFT) | R200_TXC_SCALE_INV2 | R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); OUT_RING_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_NONE); /* MAD temp0, (const1 - 0.5) * 2, (temp1 - 0.5) * 2, temp0 */ OUT_RING_REG(R200_PP_TXCBLEND_1, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_BIAS_ARG_A | R200_TXC_SCALE_ARG_A | R200_TXC_ARG_B_R1_COLOR | R200_TXC_BIAS_ARG_B | (needux8 ? R200_TXC_SCALE_ARG_B : 0) | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD); OUT_RING_REG(R200_PP_TXCBLEND2_1, (1 << R200_TXC_TFACTOR_SEL_SHIFT) | R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); OUT_RING_REG(R200_PP_TXABLEND_1, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_1, R200_TXA_OUTPUT_REG_NONE); /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp2 - 0.5), temp0 */ OUT_RING_REG(R200_PP_TXCBLEND_2, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_BIAS_ARG_A | R200_TXC_SCALE_ARG_A | R200_TXC_ARG_B_R2_COLOR | R200_TXC_BIAS_ARG_B | (needvx8 ? R200_TXC_SCALE_ARG_B : 0) | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD); OUT_RING_REG(R200_PP_TXCBLEND2_2, (2 << R200_TXC_TFACTOR_SEL_SHIFT) | R200_TXC_SCALE_2X | R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); OUT_RING_REG(R200_PP_TXABLEND_2, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_COMP_ARG_C | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_2, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); /* shader constants */ OUT_RING_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */ yco > 1.0 ? yco - 1.0: yco, yoff < 0 ? -yoff : yoff, /* range special [-1, 1] */ 0.0)); OUT_RING_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */ uco[1] * ucscale + 0.5, /* or [-2, 2] */ uco[2] * ucscale + 0.5, 0.0)); OUT_RING_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */ vco[1] * vcscale + 0.5, /* or [-4, 4] */ vco[2] * vcscale + 0.5, 0.0)); ADVANCE_RING(); } else { pPriv->vtx_count = 4; BEGIN_ACCEL_RELOC(24, 1); OUT_RING_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | RADEON_TEX_BLEND_2_ENABLE); OUT_RING_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); OUT_RING_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); OUT_RING_REG(R200_PP_TXFILTER_0, txfilter); OUT_RING_REG(R200_PP_TXFORMAT_0, txformat); OUT_RING_REG(R200_PP_TXFORMAT_X_0, 0); OUT_RING_REG(R200_PP_TXSIZE_0, (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_RING_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, 0, src_bo); /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */ OUT_RING_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_ARG_B_R0_COLOR | R200_TXC_ARG_C_TFACTOR_COLOR | (yoff < 0 ? R200_TXC_NEG_ARG_C : 0) | R200_TXC_OP_DOT2_ADD); OUT_RING_REG(R200_PP_TXCBLEND2_0, (0 << R200_TXC_TFACTOR_SEL_SHIFT) | R200_TXC_SCALE_INV2 | (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_B_SHIFT) | R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); OUT_RING_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_NONE); /* MAD temp1, (const1 - 0.5) * 2, (temp0.rrr - 0.5) * 2, temp1 */ OUT_RING_REG(R200_PP_TXCBLEND_1, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_BIAS_ARG_A | R200_TXC_SCALE_ARG_A | R200_TXC_ARG_B_R0_COLOR | R200_TXC_BIAS_ARG_B | (needux8 ? R200_TXC_SCALE_ARG_B : 0) | R200_TXC_ARG_C_R1_COLOR | R200_TXC_OP_MADD); OUT_RING_REG(R200_PP_TXCBLEND2_1, (1 << R200_TXC_TFACTOR_SEL_SHIFT) | (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_B_SHIFT) | R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); OUT_RING_REG(R200_PP_TXABLEND_1, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_1, R200_TXA_OUTPUT_REG_NONE); /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp0.bbb - 0.5), temp1 */ OUT_RING_REG(R200_PP_TXCBLEND_2, R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_BIAS_ARG_A | R200_TXC_SCALE_ARG_A | R200_TXC_ARG_B_R0_COLOR | R200_TXC_BIAS_ARG_B | (needvx8 ? R200_TXC_SCALE_ARG_B : 0) | R200_TXC_ARG_C_R1_COLOR | R200_TXC_OP_MADD); OUT_RING_REG(R200_PP_TXCBLEND2_2, (2 << R200_TXC_TFACTOR_SEL_SHIFT) | R200_TXC_SCALE_2X | (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_B_SHIFT) | R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); OUT_RING_REG(R200_PP_TXABLEND_2, R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_ZERO | R200_TXA_COMP_ARG_C | R200_TXA_OP_MADD); OUT_RING_REG(R200_PP_TXABLEND2_2, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); /* shader constants */ OUT_RING_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */ yco > 1.0 ? yco - 1.0: yco, yoff < 0 ? -yoff : yoff, /* range special [-1, 1] */ 0.0)); OUT_RING_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */ uco[1] * ucscale + 0.5, /* or [-2, 2] */ uco[2] * ucscale + 0.5, 0.0)); OUT_RING_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */ vco[1] * vcscale + 0.5, /* or [-4, 4] */ vco[2] * vcscale + 0.5, 0.0)); ADVANCE_RING(); } BEGIN_RING(2*2); OUT_RING_REG(RADEON_RE_TOP_LEFT, 0); OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) | (scissor_h << RADEON_RE_HEIGHT_SHIFT))); ADVANCE_RING(); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) RADEONWaitForVLine(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } return TRUE; } static void R200DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; int dstxoff, dstyoff; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif if (!R200PrepareTexturedVideo(pScrn, pPriv)) return; /* * Rendering of the actual polygon is done in two different * ways depending on chip generation: * * < R300: * * These chips can render a rectangle in one pass, so * handling is pretty straight-forward. * * >= R300: * * These chips can accept a quad, but will render it as * two triangles which results in a diagonal tear. Instead * We render a single, large triangle and use the scissor * functionality to restrict it to the desired rectangle. * Due to guardband limits on r3xx/r4xx, we can only use * the single triangle up to 2560/4021 pixels; above that we * render as a quad. */ while (nBox) { int draw_size = 3 * pPriv->vtx_count + 4; int loop_boxes; if (draw_size > radeon_cs_space_remaining(pScrn)) { radeon_cs_flush_indirect(pScrn); if (!R200PrepareTexturedVideo(pScrn, pPriv)) return; } loop_boxes = MIN(radeon_cs_space_remaining(pScrn) / draw_size, nBox); nBox -= loop_boxes; BEGIN_RING(loop_boxes * 3 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, loop_boxes * 3 * pPriv->vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | ((loop_boxes * 3) << RADEON_CP_VC_CNTL_NUM_SHIFT)); while (loop_boxes--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; if (pPriv->is_planar) { /* * Just render a rect (using three coords). */ VTX_OUT_6((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_6((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); } else { /* * Just render a rect (using three coords). */ VTX_OUT_4((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); } pBox++; } OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); } DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } static Bool R300PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer]; uint32_t txfilter, txformat0, txformat1, txpitch; uint32_t dst_pitch, dst_format; uint32_t txenable, colorpitch; uint32_t output_fmt; int pixel_shift; int ret; radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); if (pPriv->bicubic_enabled) radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); driver_priv = exaGetPixmapDriverPrivate(pPixmap); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) { ErrorF("Not enough RAM to hw accel xv operation\n"); return FALSE; } pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pPixmap); RADEON_SWITCH_TO_3D(); if (pPriv->bicubic_enabled) pPriv->vtx_count = 6; else pPriv->vtx_count = 4; switch (pPixmap->drawable.bitsPerPixel) { case 16: if (pPixmap->drawable.depth == 15) dst_format = R300_COLORFORMAT_ARGB1555; else dst_format = R300_COLORFORMAT_RGB565; break; case 32: dst_format = R300_COLORFORMAT_ARGB8888; break; default: return FALSE; } output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA); colorpitch = dst_pitch >> pixel_shift; colorpitch |= dst_format; if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= R300_COLORTILE; if (((pPriv->bicubic_state == BICUBIC_OFF)) && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) pPriv->is_planar = TRUE; else pPriv->is_planar = FALSE; if (pPriv->is_planar) { txformat1 = R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_HALF_REGION_0; txpitch = pPriv->src_pitch; } else { if (pPriv->id == FOURCC_UYVY) txformat1 = R300_TX_FORMAT_YVYU422; else txformat1 = R300_TX_FORMAT_VYUY422; if (pPriv->bicubic_state != BICUBIC_OFF) txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; /* pitch is in pixels */ txpitch = pPriv->src_pitch / 2; } txpitch -= 1; txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR | (0 << R300_TX_ID_SHIFT)); BEGIN_ACCEL_RELOC(6, 1); OUT_RING_REG(R300_TX_FILTER0_0, txfilter); OUT_RING_REG(R300_TX_FILTER1_0, 0); OUT_RING_REG(R300_TX_FORMAT0_0, txformat0); if (pPriv->is_planar) OUT_RING_REG(R300_TX_FORMAT1_0, txformat1 | R300_TX_FORMAT_CACHE_HALF_REGION_0); else OUT_RING_REG(R300_TX_FORMAT1_0, txformat1); OUT_RING_REG(R300_TX_FORMAT2_0, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_0, 0, src_bo); ADVANCE_RING(); txenable = R300_TEX_0_ENABLE; if (pPriv->is_planar) { txformat0 = ((((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); txpitch = RADEON_ALIGN(pPriv->src_pitch >> 1, 64); txpitch -= 1; txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_MIN_FILTER_LINEAR | R300_TX_MAG_FILTER_LINEAR); BEGIN_ACCEL_RELOC(12, 2); OUT_RING_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT)); OUT_RING_REG(R300_TX_FILTER1_1, 0); OUT_RING_REG(R300_TX_FORMAT0_1, txformat0); OUT_RING_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2); OUT_RING_REG(R300_TX_FORMAT2_1, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_1, pPriv->planeu_offset, src_bo); OUT_RING_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT)); OUT_RING_REG(R300_TX_FILTER1_2, 0); OUT_RING_REG(R300_TX_FORMAT0_2, txformat0); OUT_RING_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3); OUT_RING_REG(R300_TX_FORMAT2_2, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_2, pPriv->planev_offset, src_bo); ADVANCE_RING(); txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; } if (pPriv->bicubic_enabled) { /* Size is 128x1 */ txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) | (0x0 << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); /* Format is 32-bit floats, 4bpp */ txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16); /* Pitch is 127 (128-1) */ txpitch = 0x7f; /* Tex filter */ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) | R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) | R300_TX_MIN_FILTER_NEAREST | R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); BEGIN_ACCEL_RELOC(6, 1); OUT_RING_REG(R300_TX_FILTER0_1, txfilter); OUT_RING_REG(R300_TX_FILTER1_1, 0); OUT_RING_REG(R300_TX_FORMAT0_1, txformat0); OUT_RING_REG(R300_TX_FORMAT1_1, txformat1); OUT_RING_REG(R300_TX_FORMAT2_1, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_1, 0, info->bicubic_bo); ADVANCE_RING(); /* Enable tex 1 */ txenable |= R300_TEX_1_ENABLE; } /* setup the VAP */ if (info->accel_state->has_tcl) { if (pPriv->bicubic_enabled) BEGIN_RING(2*7); else BEGIN_RING(2*6); } else { if (pPriv->bicubic_enabled) BEGIN_RING(2*5); else BEGIN_RING(2*4); } /* These registers define the number, type, and location of data submitted * to the PVS unit of GA input (when PVS is disabled) * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is * enabled. This memory provides the imputs to the vertex shader program * and ordering is not important. When PVS/TCL is disabled, this field maps * directly to the GA input memory and the order is signifigant. In * PVS_BYPASS mode the order is as follows: * Position * Point Size * Color 0-3 * Textures 0-7 * Fog */ if (pPriv->bicubic_enabled) { OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_SIGNED_1)); OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_1, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | (0 << R300_SKIP_DWORDS_2_SHIFT) | (7 << R300_DST_VEC_LOC_2_SHIFT) | R300_LAST_VEC_2 | R300_SIGNED_2)); } else { OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_LAST_VEC_1 | R300_SIGNED_1)); } /* load the vertex shader * We pre-load vertex programs in RADEONInit3DEngine(): * - exa * - Xv * - Xv bicubic * Here we select the offset of the vertex program we want to use */ if (info->accel_state->has_tcl) { if (pPriv->bicubic_enabled) { OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((11 << R300_PVS_FIRST_INST_SHIFT) | (13 << R300_PVS_XYZW_VALID_INST_SHIFT) | (13 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (13 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } else { OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((9 << R300_PVS_FIRST_INST_SHIFT) | (10 << R300_PVS_XYZW_VALID_INST_SHIFT) | (10 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (10 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } } /* Position and one set of 2 texture coordinates */ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); if (pPriv->bicubic_enabled) OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | (2 << R300_TEX_1_COMP_CNT_SHIFT))); else OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt); ADVANCE_RING(); /* setup pixel shader */ if (pPriv->bicubic_state != BICUBIC_OFF) { if (pPriv->bicubic_enabled) { BEGIN_RING(2*79); /* 4 components: 2 for tex0 and 2 for tex1 */ OUT_RING_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1)); /* Pixel stack frame size. */ OUT_RING_REG(R300_US_PIXSIZE, 5); /* Indirection levels */ OUT_RING_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX)); /* Set nodes. */ OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(14) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(6))); /* Nodes are allocated highest first, but executed lowest first */ OUT_RING_REG(R300_US_CODE_ADDR_0, 0); OUT_RING_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0))); OUT_RING_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) | R300_ALU_SIZE(9) | R300_TEX_START(1) | R300_TEX_SIZE(0))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(11) | R300_ALU_SIZE(2) | R300_TEX_START(2) | R300_TEX_SIZE(3) | R300_RGBA_OUT)); /* ** BICUBIC FP ** */ /* texcoord0 => temp0 * texcoord1 => temp1 */ // first node /* TEX temp2, temp1.rrr0, tex1, 1D */ OUT_RING_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(1) | R300_TEX_SRC_ADDR(1) | R300_TEX_DST_ADDR(2))); /* MOV temp1.r, temp1.ggg0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) | R300_ALU_RGB_ADDRD(1) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); // second node /* TEX temp1, temp1, tex1, 1D */ OUT_RING_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(1) | R300_TEX_SRC_ADDR(1) | R300_TEX_DST_ADDR(1))); /* MUL temp3.rg, temp2.ggg0, const0.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) | R300_ALU_RGB_ADDRD(3) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* MUL temp2.rg, temp2.rrr0, const0.rgb */ OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) | R300_ALU_RGB_ADDRD(2) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* MAD temp4.rg, temp1.ggg0, const1.rgb, temp3.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR2(3) | R300_ALU_RGB_ADDRD(4) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* MAD temp5.rg, temp1.ggg0, const1.rgb, temp2.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR2(2) | R300_ALU_RGB_ADDRD(5) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* MAD temp3.rg, temp1.rrr0, const1.rgb, temp3.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR2(3) | R300_ALU_RGB_ADDRD(3) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* MAD temp1.rg, temp1.rrr0, const1.rgb, temp2.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) | R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR2(2) | R300_ALU_RGB_ADDRD(1) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* ADD temp1.rg, temp0.rgb0, temp1.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR2(1) | R300_ALU_RGB_ADDRD(1) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* ADD temp2.rg, temp0.rgb0, temp3.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR2(3) | R300_ALU_RGB_ADDRD(2) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* ADD temp3.rg, temp0.rgb0, temp5.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR2(5) | R300_ALU_RGB_ADDRD(3) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); /* ADD temp0.rg, temp0.rgb0, temp4.rgb0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR2(4) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); // third node /* TEX temp4, temp1.rg--, tex0, 1D */ OUT_RING_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(0) | R300_TEX_SRC_ADDR(1) | R300_TEX_DST_ADDR(4))); /* TEX temp3, temp3.rg--, tex0, 1D */ OUT_RING_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(0) | R300_TEX_SRC_ADDR(3) | R300_TEX_DST_ADDR(3))); /* TEX temp5, temp2.rg--, tex0, 1D */ OUT_RING_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(0) | R300_TEX_SRC_ADDR(2) | R300_TEX_DST_ADDR(5))); /* TEX temp0, temp0.rg--, tex0, 1D */ OUT_RING_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) | R300_TEX_ID(0) | R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(0))); /* LRP temp3, temp1.bbbb, temp4, temp3 -> * - PRESUB temps, temp4 - temp3 * - MAD temp3, temp1.bbbb, temps, temp3 */ OUT_RING_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) | R300_ALU_RGB_ADDR1(4) | R300_ALU_RGB_ADDR2(1) | R300_ALU_RGB_ADDRD(3) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) | R300_ALU_ALPHA_ADDR1(4) | R300_ALU_ALPHA_ADDR2(1) | R300_ALU_ALPHA_ADDRD(3) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A))); /* LRP temp0, temp1.bbbb, temp5, temp0 -> * - PRESUB temps, temp5 - temp0 * - MAD temp0, temp1.bbbb, temps, temp0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0) | R300_ALU_RGB_INSERT_NOP)); OUT_RING_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(5) | R300_ALU_RGB_ADDR2(1) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) | R300_ALU_ALPHA_ADDR1(5) | R300_ALU_ALPHA_ADDR2(1) | R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A))); /* LRP output, temp2.bbbb, temp3, temp0 -> * - PRESUB temps, temp3 - temp0 * - MAD output, temp2.bbbb, temps, temp0 */ OUT_RING_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0))); OUT_RING_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(3) | R300_ALU_RGB_ADDR2(2) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) | R300_ALU_ALPHA_ADDR1(3) | R300_ALU_ALPHA_ADDR2(2) | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A))); /* Shader constants. */ OUT_RING_REG(R300_US_ALU_CONST_R(0), F_TO_24(1.0/(float)pPriv->w)); OUT_RING_REG(R300_US_ALU_CONST_G(0), 0); OUT_RING_REG(R300_US_ALU_CONST_B(0), 0); OUT_RING_REG(R300_US_ALU_CONST_A(0), 0); OUT_RING_REG(R300_US_ALU_CONST_R(1), 0); OUT_RING_REG(R300_US_ALU_CONST_G(1), F_TO_24(1.0/(float)pPriv->h)); OUT_RING_REG(R300_US_ALU_CONST_B(1), 0); OUT_RING_REG(R300_US_ALU_CONST_A(1), 0); ADVANCE_RING(); } else { BEGIN_RING(2*11); /* 2 components: 2 for tex0 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); OUT_RING_REG(R300_US_PIXSIZE, 0); /* highest temp used */ /* Indirection levels */ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX)); OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(1) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(1))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | R300_ALU_SIZE(0) | R300_TEX_START(0) | R300_TEX_SIZE(0) | R300_RGBA_OUT)); /* tex inst */ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(0) | R300_TEX_ID(0) | R300_TEX_INST(R300_TEX_INST_LD))); /* ALU inst */ /* RGB */ OUT_RING_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G | R300_ALU_RGB_MASK_B)) | R300_ALU_RGB_TARGET_A)); OUT_RING_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | R300_ALU_RGB_CLAMP)); /* Alpha */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) | R300_ALU_ALPHA_ADDR1(0) | R300_ALU_ALPHA_ADDR2(0) | R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | R300_ALU_ALPHA_TARGET_A | R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) | R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) | R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | R300_ALU_ALPHA_CLAMP)); ADVANCE_RING(); } } else { /* * y' = y - .0625 * u' = u - .5 * v' = v - .5; * * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' * * DP3 might look like the straightforward solution * but we'd need to move the texture yuv values in * the same reg for this to work. Therefore use MADs. * Brightness just adds to the off constant. * Contrast is multiplication of luminance. * Saturation and hue change the u and v coeffs. * Default values (before adjustments - depend on colorspace): * yco = 1.1643 * uco = 0, -0.39173, 2.017 * vco = 1.5958, -0.8129, 0 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], * * temp = MAD(yco, yuv.yyyy, off) * temp = MAD(uco, yuv.uuuu, temp) * result = MAD(vco, yuv.vvvv, temp) */ /* TODO: don't recalc consts always */ const float Loff = -0.0627; const float Coff = -0.502; float uvcosf, uvsinf; float yco; float uco[3], vco[3], off[3]; float bright, cont, gamma; int ref = pPriv->transform_index; Bool needgamma = FALSE; cont = RTFContrast(pPriv->contrast); bright = RTFBrightness(pPriv->brightness); gamma = (float)pPriv->gamma / 1000.0; uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); /* overlay video also does pre-gamma contrast/sat adjust, should we? */ yco = trans[ref].RefLuma * cont; uco[0] = -trans[ref].RefRCr * uvsinf; uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; uco[2] = trans[ref].RefBCb * uvcosf; vco[0] = trans[ref].RefRCr * uvcosf; vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; vco[2] = trans[ref].RefBCb * uvsinf; off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; if (gamma != 1.0) { needgamma = TRUE; /* note: gamma correction is out = in ^ gamma; gpu can only do LG2/EX2 therefore we transform into in ^ gamma = 2 ^ (log2(in) * gamma). Lots of scalar ops, unfortunately (better solution?) - without gamma that's 3 inst, with gamma it's 10... could use different gamma factors per channel, if that's of any use. */ } if (pPriv->is_planar) { BEGIN_RING(2 * (needgamma ? (28 + 33) : 33)); /* 2 components: same 2 for tex0/1/2 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); OUT_RING_REG(R300_US_PIXSIZE, 2); /* highest temp used */ /* Indirection levels */ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX)); OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(needgamma ? 7 + 3 : 3) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(3))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | R300_ALU_SIZE(needgamma ? 7 + 2 : 2) | R300_TEX_START(0) | R300_TEX_SIZE(2) | R300_RGBA_OUT)); /* tex inst */ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(2) | R300_TEX_ID(0) | R300_TEX_INST(R300_TEX_INST_LD))); OUT_RING_REG(R300_US_TEX_INST_1, (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(1) | R300_TEX_ID(1) | R300_TEX_INST(R300_TEX_INST_LD))); OUT_RING_REG(R300_US_TEX_INST_2, (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(0) | R300_TEX_ID(2) | R300_TEX_INST(R300_TEX_INST_LD))); /* ALU inst */ /* MAD temp2.rgb, const0.aaa, temp2.rgb, const0.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) | R300_ALU_RGB_ADDR1(2) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(2) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop, but need to set up alpha source for rgb usage */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) | R300_ALU_ALPHA_ADDR1(2) | R300_ALU_ALPHA_ADDR2(0) | R300_ALU_ALPHA_ADDRD(2) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MAD temp2.rgb, const1.rgb, temp1.rgb, temp2.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR1(1) | R300_ALU_RGB_ADDR2(2) | R300_ALU_RGB_ADDRD(2) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(2) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MAD result.rgb, const2.rgb, temp0.rgb, temp2.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(2) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) | (needgamma ? 0 : R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB)))); OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | R300_ALU_RGB_CLAMP)); /* write alpha 1 */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | R300_ALU_ALPHA_TARGET_A)); OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0))); if (needgamma) { /* rgb temp0.r = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R))); OUT_RING_REG(R300_US_ALU_RGB_INST(3), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.r */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb temp0.g = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_RGB_INST(4), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.g */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb temp0.b = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B))); OUT_RING_REG(R300_US_ALU_RGB_INST(5), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.b */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MUL const1, temp1, temp0 */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC0_AAA) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop, but set up const1 */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(1)) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.r = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_R))); OUT_RING_REG(R300_US_ALU_RGB_INST(7), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.r */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.g = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_RGB_INST(8), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.g */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.b = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_B))); OUT_RING_REG(R300_US_ALU_RGB_INST(9), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.b */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); } } else { BEGIN_RING(2 * (needgamma ? (28 + 31) : 31)); /* 2 components */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */ /* Indirection levels */ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX)); OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | R300_ALU_CODE_SIZE(needgamma ? 7 + 3 : 3) | R300_TEX_CODE_OFFSET(0) | R300_TEX_CODE_SIZE(1))); OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | R300_ALU_SIZE(needgamma ? 7 + 2 : 2) | R300_TEX_START(0) | R300_TEX_SIZE(0) | R300_RGBA_OUT)); /* tex inst */ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | R300_TEX_DST_ADDR(0) | R300_TEX_ID(0) | R300_TEX_INST(R300_TEX_INST_LD))); /* ALU inst */ /* MAD temp1.rgb, const0.aaa, temp0.ggg, const0.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(1) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_GGG) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop, but need to set up alpha source for rgb usage */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) | R300_ALU_ALPHA_ADDR1(0) | R300_ALU_ALPHA_ADDR2(0) | R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MAD temp1.rgb, const1.rgb, temp0.bbb, temp1.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(1) | R300_ALU_RGB_ADDRD(1) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_BBB) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MAD result.rgb, const2.rgb, temp0.rrr, temp1.rgb */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(1) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) | (needgamma ? 0 : R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB)))); OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RRR) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | R300_ALU_RGB_CLAMP)); /* write alpha 1 */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | R300_ALU_ALPHA_TARGET_A)); OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0))); if (needgamma) { /* rgb temp0.r = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R))); OUT_RING_REG(R300_US_ALU_RGB_INST(3), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.r */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb temp0.g = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_RGB_INST(4), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.g */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb temp0.b = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B))); OUT_RING_REG(R300_US_ALU_RGB_INST(5), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha lg2 temp0, temp0.b */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* MUL const1, temp1, temp0 */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(0) | R300_ALU_RGB_ADDR2(0) | R300_ALU_RGB_ADDRD(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC0_AAA) | R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); /* alpha nop, but set up const1 */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(1)) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.r = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_R))); OUT_RING_REG(R300_US_ALU_RGB_INST(7), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.r */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.g = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_G))); OUT_RING_REG(R300_US_ALU_RGB_INST(8), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.g */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); /* rgb out0.b = op_sop, set up src0 reg */ OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B) | R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_B))); OUT_RING_REG(R300_US_ALU_RGB_INST(9), R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) | R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)); /* alpha ex2 temp0, temp0.b */ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) | R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) | R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) | R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); } } /* Shader constants. */ /* constant 0: off, yco */ OUT_RING_REG(R300_US_ALU_CONST_R(0), F_TO_24(off[0])); OUT_RING_REG(R300_US_ALU_CONST_G(0), F_TO_24(off[1])); OUT_RING_REG(R300_US_ALU_CONST_B(0), F_TO_24(off[2])); OUT_RING_REG(R300_US_ALU_CONST_A(0), F_TO_24(yco)); /* constant 1: uco */ OUT_RING_REG(R300_US_ALU_CONST_R(1), F_TO_24(uco[0])); OUT_RING_REG(R300_US_ALU_CONST_G(1), F_TO_24(uco[1])); OUT_RING_REG(R300_US_ALU_CONST_B(1), F_TO_24(uco[2])); OUT_RING_REG(R300_US_ALU_CONST_A(1), F_TO_24(gamma)); /* constant 2: vco */ OUT_RING_REG(R300_US_ALU_CONST_R(2), F_TO_24(vco[0])); OUT_RING_REG(R300_US_ALU_CONST_G(2), F_TO_24(vco[1])); OUT_RING_REG(R300_US_ALU_CONST_B(2), F_TO_24(vco[2])); OUT_RING_REG(R300_US_ALU_CONST_A(2), F_TO_24(0.0)); ADVANCE_RING(); } BEGIN_ACCEL_RELOC(6, 2); OUT_RING_REG(R300_TX_INVALTAGS, 0); OUT_RING_REG(R300_TX_ENABLE, txenable); EMIT_WRITE_OFFSET(R300_RB3D_COLOROFFSET0, 0, pPixmap); EMIT_COLORPITCH(R300_RB3D_COLORPITCH0, colorpitch, pPixmap); /* no need to enable blending */ OUT_RING_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); OUT_RING_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count); ADVANCE_RING(); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) RADEONWaitForVLine(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } return TRUE; } static void R300DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; int dstxoff, dstyoff; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif if (!R300PrepareTexturedVideo(pScrn, pPriv)) return; /* * Rendering of the actual polygon is done in two different * ways depending on chip generation: * * < R300: * * These chips can render a rectangle in one pass, so * handling is pretty straight-forward. * * >= R300: * * These chips can accept a quad, but will render it as * two triangles which results in a diagonal tear. Instead * We render a single, large triangle and use the scissor * functionality to restrict it to the desired rectangle. * Due to guardband limits on r3xx/r4xx, we can only use * the single triangle up to 2560/4021 pixels; above that we * render as a quad. */ while (nBox--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; Bool use_quad = FALSE; int draw_size = 4 * pPriv->vtx_count + 4 + 2 + 3; if (draw_size > radeon_cs_space_remaining(pScrn)) { radeon_cs_flush_indirect(pScrn); if (!R300PrepareTexturedVideo(pScrn, pPriv)) return; } dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; if (IS_R400_3D) { if ((dstw+dsth) > 4021) use_quad = TRUE; } else { if ((dstw+dsth) > 2560) use_quad = TRUE; } /* * Set up the scissor area to that of the output size. */ BEGIN_RING(2*2); /* R300 has an offset */ OUT_RING_REG(R300_SC_SCISSOR0, (((dstX + 1440) << R300_SCISSOR_X_SHIFT) | ((dstY + 1440) << R300_SCISSOR_Y_SHIFT))); OUT_RING_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1440 - 1) << R300_SCISSOR_X_SHIFT) | ((dstY + dsth + 1440 - 1) << R300_SCISSOR_Y_SHIFT))); ADVANCE_RING(); if (use_quad) { BEGIN_RING(4 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 4 * pPriv->vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else { BEGIN_RING(3 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 3 * pPriv->vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } if (pPriv->bicubic_enabled) { /* * This code is only executed on >= R300, so we don't * have to deal with the legacy handling. */ if (use_quad) { VTX_OUT_6((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h, (float)srcX + 0.5, (float)srcY + 0.5); VTX_OUT_6((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)srcX + 0.5, (float)(srcY + srch) + 0.5); VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h, (float)(srcX + srcw) + 0.5, (float)(srcY + srch) + 0.5); VTX_OUT_6((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h, (float)(srcX + srcw) + 0.5, (float)srcY + 0.5); } else { VTX_OUT_6((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h, (float)srcX + 0.5, (float)srcY + 0.5); VTX_OUT_6((float)dstX, (float)(dstY + dstw + dsth), (float)srcX / pPriv->w, ((float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0)) / pPriv->h, (float)srcX + 0.5, (float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0) + 0.5); VTX_OUT_6((float)(dstX + dstw + dsth), (float)dstY, ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / pPriv->w, (float)srcY / pPriv->h, (float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0) + 0.5, (float)srcY + 0.5); } } else { if (use_quad) { VTX_OUT_4((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h); VTX_OUT_4((float)dstX, (float)(dstY + dsth), (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth), (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); VTX_OUT_4((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); } else { /* * Render a big, scissored triangle. This means * increasing the triangle size and adjusting * texture coordinates. */ VTX_OUT_4((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h); VTX_OUT_4((float)dstX, (float)(dstY + dsth + dstw), (float)srcX / pPriv->w, ((float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0)) / pPriv->h); VTX_OUT_4((float)(dstX + dstw + dsth), (float)dstY, ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / pPriv->w, (float)srcY / pPriv->h); } } /* flushing is pipelined, free/finish is not */ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); ADVANCE_RING(); pBox++; } BEGIN_RING(2*3); OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } static Bool R500PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; struct radeon_exa_pixmap_priv *driver_priv; struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer]; uint32_t txfilter, txformat0, txformat1, txpitch, us_format = 0; uint32_t dst_pitch, dst_format; uint32_t txenable, colorpitch; uint32_t output_fmt; int pixel_shift, out_size = 6; int ret; radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); if (pPriv->bicubic_enabled) radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); driver_priv = exaGetPixmapDriverPrivate(pPixmap); radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); ret = radeon_cs_space_check(info->cs); if (ret) { ErrorF("Not enough RAM to hw accel xv operation\n"); return FALSE; } pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; dst_pitch = exaGetPixmapPitch(pPixmap); RADEON_SWITCH_TO_3D(); if (pPriv->bicubic_enabled) pPriv->vtx_count = 6; else pPriv->vtx_count = 4; switch (pPixmap->drawable.bitsPerPixel) { case 16: if (pPixmap->drawable.depth == 15) dst_format = R300_COLORFORMAT_ARGB1555; else dst_format = R300_COLORFORMAT_RGB565; break; case 32: dst_format = R300_COLORFORMAT_ARGB8888; break; default: return FALSE; } output_fmt = (R300_OUT_FMT_C4_8 | R300_OUT_FMT_C0_SEL_BLUE | R300_OUT_FMT_C1_SEL_GREEN | R300_OUT_FMT_C2_SEL_RED | R300_OUT_FMT_C3_SEL_ALPHA); colorpitch = dst_pitch >> pixel_shift; colorpitch |= dst_format; if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= R300_COLORTILE; if (((pPriv->bicubic_state == BICUBIC_OFF)) && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) pPriv->is_planar = TRUE; else pPriv->is_planar = FALSE; if (pPriv->is_planar) { txformat1 = R300_TX_FORMAT_X8; txpitch = pPriv->src_pitch; } else { if (pPriv->id == FOURCC_UYVY) txformat1 = R300_TX_FORMAT_YVYU422; else txformat1 = R300_TX_FORMAT_VYUY422; if (pPriv->bicubic_state != BICUBIC_OFF) txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; /* pitch is in pixels */ txpitch = pPriv->src_pitch / 2; } txpitch -= 1; txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR | (0 << R300_TX_ID_SHIFT)); if ((pPriv->w - 1) & 0x800) txpitch |= R500_TXWIDTH_11; if ((pPriv->h - 1) & 0x800) txpitch |= R500_TXHEIGHT_11; if (info->ChipFamily == CHIP_FAMILY_R520) { unsigned us_width = (pPriv->w - 1) & 0x7ff; unsigned us_height = (pPriv->h - 1) & 0x7ff; unsigned us_depth = 0; if (pPriv->w > 2048) { us_width = (0x7ff + us_width) >> 1; us_depth |= 0x0d; } if (pPriv->h > 2048) { us_height = (0x7ff + us_height) >> 1; us_depth |= 0x0e; } us_format = (us_width << R300_TXWIDTH_SHIFT) | (us_height << R300_TXHEIGHT_SHIFT) | (us_depth << R300_TXDEPTH_SHIFT); out_size++; } BEGIN_ACCEL_RELOC(out_size, 1); OUT_RING_REG(R300_TX_FILTER0_0, txfilter); OUT_RING_REG(R300_TX_FILTER1_0, 0); OUT_RING_REG(R300_TX_FORMAT0_0, txformat0); OUT_RING_REG(R300_TX_FORMAT1_0, txformat1); OUT_RING_REG(R300_TX_FORMAT2_0, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_0, 0, src_bo); if (info->ChipFamily == CHIP_FAMILY_R520) OUT_RING_REG(R500_US_FORMAT0_0, us_format); ADVANCE_RING(); txenable = R300_TEX_0_ENABLE; if (pPriv->is_planar) { txformat0 = ((((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); txpitch = RADEON_ALIGN(pPriv->src_pitch >> 1, 64); txpitch -= 1; txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | R300_TX_MIN_FILTER_LINEAR | R300_TX_MAG_FILTER_LINEAR); BEGIN_ACCEL_RELOC(12, 2); OUT_RING_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT)); OUT_RING_REG(R300_TX_FILTER1_1, 0); OUT_RING_REG(R300_TX_FORMAT0_1, txformat0); OUT_RING_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8); OUT_RING_REG(R300_TX_FORMAT2_1, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_1, pPriv->planeu_offset, src_bo); OUT_RING_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT)); OUT_RING_REG(R300_TX_FILTER1_2, 0); OUT_RING_REG(R300_TX_FORMAT0_2, txformat0); OUT_RING_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8); OUT_RING_REG(R300_TX_FORMAT2_2, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_2, pPriv->planev_offset, src_bo); ADVANCE_RING(); txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; } if (pPriv->bicubic_enabled) { /* Size is 128x1 */ txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) | (0x0 << R300_TXHEIGHT_SHIFT) | R300_TXPITCH_EN); /* Format is 32-bit floats, 4bpp */ txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16); /* Pitch is 127 (128-1) */ txpitch = 0x7f; /* Tex filter */ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) | R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) | R300_TX_MIN_FILTER_NEAREST | R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); BEGIN_ACCEL_RELOC(6, 1); OUT_RING_REG(R300_TX_FILTER0_1, txfilter); OUT_RING_REG(R300_TX_FILTER1_1, 0); OUT_RING_REG(R300_TX_FORMAT0_1, txformat0); OUT_RING_REG(R300_TX_FORMAT1_1, txformat1); OUT_RING_REG(R300_TX_FORMAT2_1, txpitch); OUT_TEXTURE_REG(R300_TX_OFFSET_1, 0, info->bicubic_bo); ADVANCE_RING(); /* Enable tex 1 */ txenable |= R300_TEX_1_ENABLE; } /* setup the VAP */ if (info->accel_state->has_tcl) { if (pPriv->bicubic_enabled) BEGIN_RING(2*7); else BEGIN_RING(2*6); } else { if (pPriv->bicubic_enabled) BEGIN_RING(2*5); else BEGIN_RING(2*4); } /* These registers define the number, type, and location of data submitted * to the PVS unit of GA input (when PVS is disabled) * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is * enabled. This memory provides the imputs to the vertex shader program * and ordering is not important. When PVS/TCL is disabled, this field maps * directly to the GA input memory and the order is signifigant. In * PVS_BYPASS mode the order is as follows: * Position * Point Size * Color 0-3 * Textures 0-7 * Fog */ if (pPriv->bicubic_enabled) { OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_SIGNED_1)); OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_1, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | (0 << R300_SKIP_DWORDS_2_SHIFT) | (7 << R300_DST_VEC_LOC_2_SHIFT) | R300_LAST_VEC_2 | R300_SIGNED_2)); } else { OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | (0 << R300_DST_VEC_LOC_0_SHIFT) | R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | R300_LAST_VEC_1 | R300_SIGNED_1)); } /* load the vertex shader * We pre-load vertex programs in RADEONInit3DEngine(): * - exa * - Xv * - Xv bicubic * Here we select the offset of the vertex program we want to use */ if (info->accel_state->has_tcl) { if (pPriv->bicubic_enabled) { OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((11 << R300_PVS_FIRST_INST_SHIFT) | (13 << R300_PVS_XYZW_VALID_INST_SHIFT) | (13 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (13 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } else { OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0, ((9 << R300_PVS_FIRST_INST_SHIFT) | (10 << R300_PVS_XYZW_VALID_INST_SHIFT) | (10 << R300_PVS_LAST_INST_SHIFT))); OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1, (10 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } } /* Position and one set of 2 texture coordinates */ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); if (pPriv->bicubic_enabled) OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | (2 << R300_TEX_1_COMP_CNT_SHIFT))); else OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt); ADVANCE_RING(); /* setup pixel shader */ if (pPriv->bicubic_state != BICUBIC_OFF) { if (pPriv->bicubic_enabled) { BEGIN_RING(2*7); /* 4 components: 2 for tex0 and 2 for tex1 */ OUT_RING_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1)); /* Pixel stack frame size. */ OUT_RING_REG(R300_US_PIXSIZE, 5); /* FP length. */ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(13))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(13))); /* Prepare for FP emission. */ OUT_RING_REG(R500_US_CODE_OFFSET, 0); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); ADVANCE_RING(); BEGIN_RING(2*89); /* Pixel shader. * I've gone ahead and annotated each instruction, since this * thing is MASSIVE. :3 * Note: In order to avoid buggies with temps and multiple * inputs, all temps are offset by 2. temp0 -> register2. */ /* TEX temp2, input1.xxxx, tex1, 1D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_R | R500_TEX_SRC_R_SWIZ_R | R500_TEX_SRC_Q_SWIZ_R | R500_TEX_DST_ADDR(2) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* TEX temp5, input1.yyyy, tex1, 1D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | R500_TEX_SRC_S_SWIZ_G | R500_TEX_SRC_T_SWIZ_G | R500_TEX_SRC_R_SWIZ_G | R500_TEX_SRC_Q_SWIZ_G | R500_TEX_DST_ADDR(5) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* MUL temp4, const0.x0x0, temp2.yyxx */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_0 | R500_ALU_RGB_B_SWIZ_A_R | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0)); /* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(5) | R500_RGB_ADDR2(4))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(5) | R500_ALPHA_ADDR2(4))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_0 | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_0 | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_R | R500_ALU_RGB_B_SWIZ_B_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_G | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_A_SWIZ_A)); /* ADD temp3, temp3, input0.xyxy */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) | R500_RGB_ADDR2(0))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) | R500_ALPHA_ADDR2(0))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | R500_ALU_RGB_G_SWIZ_A_1 | R500_ALU_RGB_B_SWIZ_A_1 | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | R500_ALPHA_OP_MAD | R500_ALPHA_SWIZ_A_1 | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_R | R500_ALU_RGBA_A_SWIZ_G)); /* TEX temp1, temp3.zwxy, tex0, 2D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) | R500_TEX_SRC_S_SWIZ_B | R500_TEX_SRC_T_SWIZ_A | R500_TEX_SRC_R_SWIZ_R | R500_TEX_SRC_Q_SWIZ_G | R500_TEX_DST_ADDR(1) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* TEX temp3, temp3.xyzw, tex0, 2D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A | R500_TEX_DST_ADDR(3) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* MAD temp4, const0.0y0y, temp5.yyyy, temp4 */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(5) | R500_RGB_ADDR2(4))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(5) | R500_ALPHA_ADDR2(4))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_0 | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_0 | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_G)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_G | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_G)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_A_SWIZ_A)); /* ADD temp0, temp4, input0.xyxy */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) | R500_RGB_ADDR2(0))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) | R500_ALPHA_ADDR2(0))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | R500_ALU_RGB_G_SWIZ_A_1 | R500_ALU_RGB_B_SWIZ_A_1 | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | R500_ALPHA_OP_MAD | R500_ALPHA_SWIZ_A_1 | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_R | R500_ALU_RGBA_A_SWIZ_G)); /* TEX temp4, temp0.zwzw, tex0, 2D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_B | R500_TEX_SRC_T_SWIZ_A | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A | R500_TEX_DST_ADDR(4) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* TEX temp0, temp0.xyzw, tex0, 2D */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* LRP temp3, temp2.zzzz, temp1, temp3 -> * - PRESUB temps, temp1 - temp3 * - MAD temp2.zzzz, temps, temp3 */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) | R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | R500_RGB_ADDR1(1) | R500_RGB_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) | R500_ALPHA_SRCP_OP_A1_MINUS_A0 | R500_ALPHA_ADDR1(1) | R500_ALPHA_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | R500_ALU_RGB_R_SWIZ_A_B | R500_ALU_RGB_G_SWIZ_A_B | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRCP | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC2 | R500_ALPHA_SWIZ_A_B | R500_ALPHA_SEL_B_SRCP | R500_ALPHA_SWIZ_B_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC0 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_A_SWIZ_A)); /* LRP temp0, temp2.zzzz, temp4, temp0 -> * - PRESUB temps, temp4 - temp1 * - MAD temp2.zzzz, temps, temp0 */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | R500_RGB_ADDR1(4) | R500_RGB_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_SRCP_OP_A1_MINUS_A0 | R500_ALPHA_ADDR1(4) | R500_ALPHA_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | R500_ALU_RGB_R_SWIZ_A_B | R500_ALU_RGB_G_SWIZ_A_B | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRCP | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC2 | R500_ALPHA_SWIZ_A_B | R500_ALPHA_SEL_B_SRCP | R500_ALPHA_SWIZ_B_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC0 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_A_SWIZ_A)); /* LRP output, temp5.zzzz, temp3, temp0 -> * - PRESUB temps, temp3 - temp0 * - MAD temp5.zzzz, temps, temp0 */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_LAST | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | R500_RGB_ADDR1(3) | R500_RGB_ADDR2(5))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_SRCP_OP_A1_MINUS_A0 | R500_ALPHA_ADDR1(3) | R500_ALPHA_ADDR2(5))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | R500_ALU_RGB_R_SWIZ_A_B | R500_ALU_RGB_G_SWIZ_A_B | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRCP | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | R500_ALPHA_OP_MAD | R500_ALPHA_SEL_A_SRC2 | R500_ALPHA_SWIZ_A_B | R500_ALPHA_SEL_B_SRCP | R500_ALPHA_SWIZ_B_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_SEL_C_SRC0 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_A_SWIZ_A)); /* Shader constants. */ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0)); /* const0 = {1 / texture[0].width, 1 / texture[0].height, 0, 0} */ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w)); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h)); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0); ADVANCE_RING(); } else { BEGIN_RING(2*19); /* 2 components: 2 for tex0 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); /* Pixel stack frame size. */ OUT_RING_REG(R300_US_PIXSIZE, 0); /* highest temp used */ /* FP length. */ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1))); /* Prepare for FP emission. */ OUT_RING_REG(R500_US_CODE_OFFSET, 0); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); /* tex inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* ALU inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0)); ADVANCE_RING(); } } else { /* * y' = y - .0625 * u' = u - .5 * v' = v - .5; * * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' * * DP3 might look like the straightforward solution * but we'd need to move the texture yuv values in * the same reg for this to work. Therefore use MADs. * Brightness just adds to the off constant. * Contrast is multiplication of luminance. * Saturation and hue change the u and v coeffs. * Default values (before adjustments - depend on colorspace): * yco = 1.1643 * uco = 0, -0.39173, 2.017 * vco = 1.5958, -0.8129, 0 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], * * temp = MAD(yco, yuv.yyyy, off) * temp = MAD(uco, yuv.uuuu, temp) * result = MAD(vco, yuv.vvvv, temp) */ /* TODO: don't recalc consts always */ const float Loff = -0.0627; const float Coff = -0.502; float uvcosf, uvsinf; float yco; float uco[3], vco[3], off[3]; float bright, cont, gamma; int ref = pPriv->transform_index; cont = RTFContrast(pPriv->contrast); bright = RTFBrightness(pPriv->brightness); gamma = (float)pPriv->gamma / 1000.0; uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); /* overlay video also does pre-gamma contrast/sat adjust, should we? */ yco = trans[ref].RefLuma * cont; uco[0] = -trans[ref].RefRCr * uvsinf; uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; uco[2] = trans[ref].RefBCb * uvcosf; vco[0] = trans[ref].RefRCr * uvcosf; vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; vco[2] = trans[ref].RefBCb * uvsinf; off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; //XXX gamma if (pPriv->is_planar) { BEGIN_RING(2*56); /* 2 components: 2 for tex0 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); /* Pixel stack frame size. */ OUT_RING_REG(R300_US_PIXSIZE, 2); /* highest temp used */ /* FP length. */ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(5))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(5))); /* Prepare for FP emission. */ OUT_RING_REG(R500_US_CODE_OFFSET, 0); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); /* tex inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(2) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* tex inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | R500_TEX_INST_LD | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(1) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* tex inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(2) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* ALU inst */ /* MAD temp2.rgb, const0.aaa, temp2.rgb, const0.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(2) | R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(2) | R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_A | R500_ALU_RGB_G_SWIZ_A_A | R500_ALU_RGB_B_SWIZ_A_A | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(2) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(2) | R500_ALU_RGBA_SEL_C_SRC0 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_0)); /* MAD temp2.rgb, const1.rgb, temp1.rgb, temp2.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(1) | R500_RGB_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(1) | R500_ALPHA_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(2) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(2) | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_0)); /* MAD result.rgb, const2.rgb, temp0.rgb, temp2.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(0) | R500_RGB_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR2(2))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(0) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(0) | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_1)); } else { BEGIN_RING(2*44); /* 2 components: 2 for tex0/1/2 */ OUT_RING_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); /* R300_INST_COUNT_RS - highest RS instruction used */ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0)); /* Pixel stack frame size. */ OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */ /* FP length. */ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(3))); OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(3))); /* Prepare for FP emission. */ OUT_RING_REG(R500_US_CODE_OFFSET, 0); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); /* tex inst */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | R500_DX_S_SWIZ_R | R500_DX_T_SWIZ_R | R500_DX_R_SWIZ_R | R500_DX_Q_SWIZ_R | R500_DY_ADDR(0) | R500_DY_S_SWIZ_R | R500_DY_T_SWIZ_R | R500_DY_R_SWIZ_R | R500_DY_Q_SWIZ_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000); /* ALU inst */ /* MAD temp1.rgb, const0.aaa, temp0.ggg, const0.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(0) | R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_A | R500_ALU_RGB_G_SWIZ_A_A | R500_ALU_RGB_B_SWIZ_A_A | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_G | R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_G)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(1) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(1) | R500_ALU_RGBA_SEL_C_SRC0 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_0)); /* MAD temp1.rgb, const1.rgb, temp0.bbb, temp1.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT | R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(0) | R500_RGB_ADDR2(1))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR2(1))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_B | R500_ALU_RGB_B_SWIZ_B_B | R500_ALU_RGB_G_SWIZ_B_B)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(1) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(1) | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_0)); /* MAD result.rgb, const2.rgb, temp0.rrr, temp1.rgb */ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) | R500_RGB_ADDR0_CONST | R500_RGB_ADDR1(0) | R500_RGB_ADDR2(1))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) | R500_ALPHA_ADDR0_CONST | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR2(1))); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | R500_ALU_RGB_SEL_B_SRC1 | R500_ALU_RGB_R_SWIZ_B_R | R500_ALU_RGB_B_SWIZ_B_R | R500_ALU_RGB_G_SWIZ_B_R)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | R500_ALPHA_ADDRD(1) | R500_ALPHA_SWIZ_A_0 | R500_ALPHA_SWIZ_B_0)); OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | R500_ALU_RGBA_ADDRD(1) | R500_ALU_RGBA_SEL_C_SRC2 | R500_ALU_RGBA_R_SWIZ_R | R500_ALU_RGBA_G_SWIZ_G | R500_ALU_RGBA_B_SWIZ_B | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 | R500_ALU_RGBA_A_SWIZ_1)); } /* Shader constants. */ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0)); /* constant 0: off, yco */ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, off[0]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, off[1]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, off[2]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, yco); /* constant 1: uco */ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, uco[0]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, uco[1]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, uco[2]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, gamma); /* constant 2: vco */ OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, vco[0]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, vco[1]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, vco[2]); OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0.0); ADVANCE_RING(); } BEGIN_ACCEL_RELOC(6, 2); OUT_RING_REG(R300_TX_INVALTAGS, 0); OUT_RING_REG(R300_TX_ENABLE, txenable); EMIT_WRITE_OFFSET(R300_RB3D_COLOROFFSET0, 0, pPixmap); EMIT_COLORPITCH(R300_RB3D_COLORPITCH0, colorpitch, pPixmap); /* no need to enable blending */ OUT_RING_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); OUT_RING_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count); ADVANCE_RING(); if (pPriv->vsync) { xf86CrtcPtr crtc; if (pPriv->desired_crtc) crtc = pPriv->desired_crtc; else crtc = radeon_pick_best_crtc(pScrn, FALSE, pPriv->drw_x, pPriv->drw_x + pPriv->dst_w, pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) RADEONWaitForVLine(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); } return TRUE; } static void R500DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; int dstxoff, dstyoff; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); #ifdef COMPOSITE dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; #else dstxoff = 0; dstyoff = 0; #endif if (!R500PrepareTexturedVideo(pScrn, pPriv)) return; /* * Rendering of the actual polygon is done in two different * ways depending on chip generation: * * < R300: * * These chips can render a rectangle in one pass, so * handling is pretty straight-forward. * * >= R300: * * These chips can accept a quad, but will render it as * two triangles which results in a diagonal tear. Instead * We render a single, large triangle and use the scissor * functionality to restrict it to the desired rectangle. * Due to guardband limits on r3xx/r4xx, we can only use * the single triangle up to 2880 pixels; above that we * render as a quad. */ while (nBox--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; int draw_size = 3 * pPriv->vtx_count + 4 + 2 + 3; if (draw_size > radeon_cs_space_remaining(pScrn)) { radeon_cs_flush_indirect(pScrn); if (!R500PrepareTexturedVideo(pScrn, pPriv)) return; } dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; dsth = pBox->y2 - pBox->y1; srcX = pPriv->src_x; srcX += ((pBox->x1 - pPriv->drw_x) * pPriv->src_w) / (float)pPriv->dst_w; srcY = pPriv->src_y; srcY += ((pBox->y1 - pPriv->drw_y) * pPriv->src_h) / (float)pPriv->dst_h; srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; BEGIN_RING(2*2); OUT_RING_REG(R300_SC_SCISSOR0, (((dstX) << R300_SCISSOR_X_SHIFT) | ((dstY) << R300_SCISSOR_Y_SHIFT))); OUT_RING_REG(R300_SC_SCISSOR1, (((dstX + dstw - 1) << R300_SCISSOR_X_SHIFT) | ((dstY + dsth - 1) << R300_SCISSOR_Y_SHIFT))); ADVANCE_RING(); BEGIN_RING(3 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 3 * pPriv->vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); if (pPriv->bicubic_enabled) { VTX_OUT_6((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h, (float)srcX + 0.5, (float)srcY + 0.5); VTX_OUT_6((float)dstX, (float)(dstY + dstw + dsth), (float)srcX / pPriv->w, ((float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0)) / pPriv->h, (float)srcX + 0.5, (float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0) + 0.5); VTX_OUT_6((float)(dstX + dstw + dsth), (float)dstY, ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / pPriv->w, (float)srcY / pPriv->h, (float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0) + 0.5, (float)srcY + 0.5); } else { /* * Render a big, scissored triangle. This means * increasing the triangle size and adjusting * texture coordinates. */ VTX_OUT_4((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h); VTX_OUT_4((float)dstX, (float)(dstY + dsth + dstw), (float)srcX / pPriv->w, ((float)srcY + (float)srch * (((float)dstw / (float)dsth) + 1.0)) / pPriv->h); VTX_OUT_4((float)(dstX + dstw + dsth), (float)dstY, ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / pPriv->w, (float)srcY / pPriv->h); } /* flushing is pipelined, free/finish is not */ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); ADVANCE_RING(); pBox++; } BEGIN_RING(2*3); OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA); OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } #undef VTX_OUT_4 #undef VTX_OUT_6 xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_vbo.c000066400000000000000000000133101256524674500225550ustar00rootroot00000000000000/* * Copyright © 2009 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Dave Airlie * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include "radeon.h" #include "radeon_bo.h" #include "radeon_cs.h" #define VBO_SIZE (16*1024) /* KMS vertex buffer support - for R600 only but could be used on previous gpus */ static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn); void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo) { if (vbo->vb_bo) { radeon_bo_unmap(vbo->vb_bo); radeon_bo_unref(vbo->vb_bo); vbo->vb_bo = NULL; vbo->vb_total = 0; } vbo->vb_offset = 0; } void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo) { int ret; vbo->vb_bo = radeon_vbo_get_bo(pScrn); if (vbo->vb_bo) { radeon_bo_ref(vbo->vb_bo); ret = radeon_bo_map(vbo->vb_bo, 1); if (ret) FatalError("Failed to map vb %d\n", ret); } vbo->vb_total = VBO_SIZE; vbo->vb_offset = 0; vbo->vb_start_op = vbo->vb_offset; } /* these functions could migrate to libdrm and be shared with the radeon 3D driver */ static int radeon_bo_is_idle(struct radeon_bo *bo) { uint32_t domain; int ret = radeon_bo_is_busy(bo, &domain); return ret != -EBUSY; } void radeon_vbo_init_lists(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; accel_state->use_vbos = TRUE; make_empty_list(&accel_state->bo_free); make_empty_list(&accel_state->bo_wait); make_empty_list(&accel_state->bo_reserved); } void radeon_vbo_free_lists(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_dma_bo *dma_bo, *temp; foreach_s(dma_bo, temp, &accel_state->bo_free) { remove_from_list(dma_bo); radeon_bo_unref(dma_bo->bo); free(dma_bo); } foreach_s(dma_bo, temp, &accel_state->bo_wait) { remove_from_list(dma_bo); radeon_bo_unref(dma_bo->bo); free(dma_bo); } foreach_s(dma_bo, temp, &accel_state->bo_reserved) { remove_from_list(dma_bo); radeon_bo_unref(dma_bo->bo); free(dma_bo); } } void radeon_vbo_flush_bos(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_dma_bo *dma_bo, *temp; const int expire_at = ++accel_state->bo_free.expire_counter + DMA_BO_FREE_TIME; const int time = accel_state->bo_free.expire_counter; foreach_s(dma_bo, temp, &accel_state->bo_wait) { if (dma_bo->expire_counter == time) { ErrorF("leaking dma buffer\n"); while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {} remove_from_list(dma_bo); free(dma_bo); continue; } if (!radeon_bo_is_idle(dma_bo->bo)) continue; if (dma_bo->bo->ptr) { ErrorF("bo with pointer on wait list!\n"); continue; } remove_from_list(dma_bo); dma_bo->expire_counter = expire_at; insert_at_tail(&accel_state->bo_free, dma_bo); } /* move reserved to wait list */ foreach_s(dma_bo, temp, &accel_state->bo_reserved) { remove_from_list(dma_bo); dma_bo->expire_counter = expire_at; insert_at_tail(&accel_state->bo_wait, dma_bo); } /* free bos that have been unused */ foreach_s(dma_bo, temp, &accel_state->bo_free) { if (dma_bo->expire_counter != time) break; /* always keep one hanging around at end */ if (at_end(&accel_state->bo_free, dma_bo)) { dma_bo->expire_counter = time + DMA_BO_FREE_TIME; break; } remove_from_list(dma_bo); radeon_bo_unref(dma_bo->bo); free(dma_bo); } } static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; struct radeon_dma_bo *dma_bo = NULL; struct radeon_bo *bo; if (is_empty_list(&accel_state->bo_free)) { dma_bo = calloc(1, sizeof(struct radeon_dma_bo)); if (!dma_bo) return NULL; again_alloc: dma_bo->bo = radeon_bo_open(info->bufmgr, 0, VBO_SIZE, 0, RADEON_GEM_DOMAIN_GTT, 0); if (!dma_bo->bo) { ErrorF("failure to allocate DMA BO\n"); free(dma_bo); return NULL; } insert_at_head(&accel_state->bo_reserved, dma_bo); } else { dma_bo = last_elem(&accel_state->bo_free); remove_from_list(dma_bo); insert_at_head(&accel_state->bo_reserved, dma_bo); } if (is_empty_list(&accel_state->bo_reserved)) goto again_alloc; bo = first_elem(&accel_state->bo_reserved)->bo; /* need a space check */ if (radeon_cs_space_check_with_bo(info->cs, bo, RADEON_GEM_DOMAIN_GTT, 0)) ErrorF("failed to revalidate\n"); return bo; } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_vbo.h000066400000000000000000000023521256524674500225660ustar00rootroot00000000000000 #ifndef RADEON_VBO_H #define RADEON_VBO_H extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size); extern void radeon_vbo_init_lists(ScrnInfoPtr pScrn); extern void radeon_vbo_free_lists(ScrnInfoPtr pScrn); extern void radeon_vbo_flush_bos(ScrnInfoPtr pScrn); extern void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo); extern void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo); static inline void radeon_vbo_check(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size) { if ((vbo->vb_offset + (vbo->verts_per_op * vert_size)) > vbo->vb_total) { radeon_vb_no_space(pScrn, vbo, vert_size); } } static inline void * radeon_vbo_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size) { void *vb; /* we've ran out of space in the vertex buffer - need to get a new one */ radeon_vbo_check(pScrn, vbo, vert_size); vbo->vb_op_vert_size = vert_size; vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset); return vb; } static inline void radeon_vbo_commit(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo) { vbo->vb_offset += vbo->verts_per_op * vbo->vb_op_vert_size; } #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_version.h000066400000000000000000000050631256524674500234670ustar00rootroot00000000000000/* * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef _RADEON_VERSION_H_ #define _RADEON_VERSION_H_ 1 #undef RADEON_NAME #undef RADEON_DRIVER_NAME #undef R200_DRIVER_NAME #undef RADEON_VERSION_MAJOR #undef RADEON_VERSION_MINOR #undef RADEON_VERSION_PATCH #undef RADEON_VERSION_CURRENT #undef RADEON_VERSION_EVALUATE #undef RADEON_VERSION_STRINGIFY #undef RADEON_VERSION_NAME #define RADEON_NAME "RADEON" #define RADEON_DRIVER_NAME "radeon" #define R200_DRIVER_NAME "r200" #define R300_DRIVER_NAME "r300" #define R600_DRIVER_NAME "r600" #define SI_DRIVER_NAME "radeonsi" #define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR #define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR #define RADEON_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL #ifndef RADEON_VERSION_EXTRA #define RADEON_VERSION_EXTRA "" #endif #define RADEON_VERSION_CURRENT \ ((RADEON_VERSION_MAJOR << 20) | \ (RADEON_VERSION_MINOR << 10) | \ (RADEON_VERSION_PATCH)) #define RADEON_VERSION_EVALUATE(__x) #__x #define RADEON_VERSION_STRINGIFY(_x) RADEON_VERSION_EVALUATE(_x) #define RADEON_VERSION_NAME \ RADEON_VERSION_STRINGIFY(RADEON_VERSION_MAJOR) "." \ RADEON_VERSION_STRINGIFY(RADEON_VERSION_MINOR) "." \ RADEON_VERSION_STRINGIFY(RADEON_VERSION_PATCH) RADEON_VERSION_EXTRA #endif /* _RADEON_VERSION_H_ */ xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_video.c000066400000000000000000000164731256524674500231120ustar00rootroot00000000000000 #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include #include #include #include "radeon.h" #include "radeon_glamor.h" #include "radeon_reg.h" #include "radeon_probe.h" #include "radeon_video.h" #include "xf86.h" #include "dixstruct.h" /* DPMS */ #ifdef HAVE_XEXTPROTO_71 #include #else #define DPMS_SERVER #include #endif #include #include "fourcc.h" #define OFF_DELAY 250 /* milliseconds */ #define FREE_DELAY 15000 #define OFF_TIMER 0x01 #define FREE_TIMER 0x02 #define CLIENT_VIDEO_ON 0x04 #define GET_PORT_PRIVATE(pScrn) \ (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr) static void radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b) { dest->x1 = a->x1 > b->x1 ? a->x1 : b->x1; dest->x2 = a->x2 < b->x2 ? a->x2 : b->x2; dest->y1 = a->y1 > b->y1 ? a->y1 : b->y1; dest->y2 = a->y2 < b->y2 ? a->y2 : b->y2; if (dest->x1 >= dest->x2 || dest->y1 >= dest->y2) dest->x1 = dest->x2 = dest->y1 = dest->y2 = 0; } static void radeon_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box) { if (crtc->enabled) { crtc_box->x1 = crtc->x; crtc_box->x2 = crtc->x + xf86ModeWidth(&crtc->mode, crtc->rotation); crtc_box->y1 = crtc->y; crtc_box->y2 = crtc->y + xf86ModeHeight(&crtc->mode, crtc->rotation); } else crtc_box->x1 = crtc_box->x2 = crtc_box->y1 = crtc_box->y2 = 0; } static int radeon_box_area(BoxPtr box) { return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1); } Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc) { drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; return drmmode_crtc->dpms_mode == DPMSModeOn; } xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, Bool consider_disabled, int x1, int x2, int y1, int y2) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int coverage, best_coverage, c; BoxRec box, crtc_box, cover_box; RROutputPtr primary_output = NULL; xf86CrtcPtr best_crtc = NULL, primary_crtc = NULL; if (!pScrn->vtSema) return NULL; box.x1 = x1; box.x2 = x2; box.y1 = y1; box.y2 = y2; best_coverage = 0; /* Prefer the CRTC of the primary output */ #ifdef HAS_DIXREGISTERPRIVATEKEY if (dixPrivateKeyRegistered(rrPrivKey)) #endif { primary_output = RRFirstOutput(pScrn->pScreen); } if (primary_output && primary_output->crtc) primary_crtc = primary_output->crtc->devPrivate; /* first consider only enabled CRTCs */ for (c = 0; c < xf86_config->num_crtc; c++) { xf86CrtcPtr crtc = xf86_config->crtc[c]; if (!radeon_crtc_is_enabled(crtc)) continue; radeon_crtc_box(crtc, &crtc_box); radeon_box_intersect(&cover_box, &crtc_box, &box); coverage = radeon_box_area(&cover_box); if (coverage > best_coverage || (coverage == best_coverage && crtc == primary_crtc)) { best_crtc = crtc; best_coverage = coverage; } } if (best_crtc || !consider_disabled) return best_crtc; /* if we found nothing, repeat the search including disabled CRTCs */ for (c = 0; c < xf86_config->num_crtc; c++) { xf86CrtcPtr crtc = xf86_config->crtc[c]; radeon_crtc_box(crtc, &crtc_box); radeon_box_intersect(&cover_box, &crtc_box, &box); coverage = radeon_box_area(&cover_box); if (coverage > best_coverage || (coverage == best_coverage && crtc == primary_crtc)) { best_crtc = crtc; best_coverage = coverage; } } return best_crtc; } void RADEONInitVideo(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL; XF86VideoAdaptorPtr texturedAdaptor = NULL; int num_adaptors; /* no overlay or 3D on RN50 */ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) return; num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors); newAdaptors = malloc((num_adaptors + 2) * sizeof(XF86VideoAdaptorPtr *)); if (newAdaptors == NULL) return; memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; if (info->use_glamor) { texturedAdaptor = radeon_glamor_xv_init(pScreen, 16); if (texturedAdaptor != NULL) { adaptors[num_adaptors++] = texturedAdaptor; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video (glamor)\n"); } else xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video (glamor)\n"); } else if ((info->ChipFamily < CHIP_FAMILY_RS400) || (info->directRenderingEnabled) ) { texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); if (texturedAdaptor != NULL) { adaptors[num_adaptors++] = texturedAdaptor; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); } else xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); } else xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n"); if(num_adaptors) xf86XVScreenInit(pScreen, adaptors, num_adaptors); if(texturedAdaptor) { XF86MCAdaptorPtr xvmcAdaptor = RADEONCreateAdaptorXvMC(pScreen, (char *)texturedAdaptor->name); if(xvmcAdaptor) { if(!xf86XvMCScreenInit(pScreen, 1, &xvmcAdaptor)) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[XvMC] Failed to initialize extension.\n"); else xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[XvMC] Extension initialized.\n"); } } if(newAdaptors) free(newAdaptors); } void RADEONCopyData( ScrnInfoPtr pScrn, unsigned char *src, unsigned char *dst, unsigned int srcPitch, unsigned int dstPitch, unsigned int h, unsigned int w, unsigned int bpp ){ /* Get the byte-swapping right for big endian systems */ if ( bpp == 2 ) { w *= 2; bpp = 1; } { int swap = RADEON_HOST_DATA_SWAP_NONE; #if X_BYTE_ORDER == X_BIG_ENDIAN switch(bpp) { case 2: swap = RADEON_HOST_DATA_SWAP_16BIT; break; case 4: swap = RADEON_HOST_DATA_SWAP_32BIT; break; } #endif w *= bpp; if (dstPitch == w && dstPitch == srcPitch) RADEONCopySwap(dst, src, h * dstPitch, swap); else { while (h--) { RADEONCopySwap(dst, src, w, swap); src += srcPitch; dst += dstPitch; } } } } void RADEONCopyMungedData( ScrnInfoPtr pScrn, unsigned char *src1, unsigned char *src2, unsigned char *src3, unsigned char *dst1, unsigned int srcPitch, unsigned int srcPitch2, unsigned int dstPitch, unsigned int h, unsigned int w ){ uint32_t *dst; uint8_t *s1, *s2, *s3; int i, j; w /= 2; for( j = 0; j < h; j++ ) { dst = (pointer)dst1; s1 = src1; s2 = src2; s3 = src3; i = w; while( i > 4 ) { dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); dst[1] = cpu_to_le32(s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24)); dst[2] = cpu_to_le32(s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24)); dst[3] = cpu_to_le32(s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24)); dst += 4; s2 += 4; s3 += 4; s1 += 8; i -= 4; } while( i-- ) { dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); dst++; s2++; s3++; s1 += 2; } dst1 += dstPitch; src1 += srcPitch; if( j & 1 ) { src2 += srcPitch2; src3 += srcPitch2; } } } xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_video.h000066400000000000000000000046141256524674500231110ustar00rootroot00000000000000#ifndef __RADEON_VIDEO_H__ #define __RADEON_VIDEO_H__ #include "xf86i2c.h" #include "i2c_def.h" #include "xf86Crtc.h" #include "bicubic_table.h" #include #define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) /* Xvideo port struct */ typedef struct { uint32_t transform_index; uint32_t gamma; /* gamma value x 1000 */ int brightness; int saturation; int hue; int contrast; unsigned char currentBuffer; RegionRec clip; Time offTime; Time freeTime; xf86CrtcPtr desired_crtc; int size; struct radeon_bo *video_memory; int planeu_offset; int planev_offset; /* bicubic filtering */ Bool bicubic_enabled; int bicubic_state; #define BICUBIC_OFF 0 #define BICUBIC_ON 1 #define BICUBIC_AUTO 2 /* textured video */ Bool textured; DrawablePtr pDraw; PixmapPtr pPixmap; uint32_t src_pitch; uint8_t *src_addr; int id; int src_w, src_h, dst_w, dst_h; int w, h; int drw_x, drw_y; int src_x, src_y; int vsync; Bool is_planar; int vtx_count; int hw_align; struct radeon_bo *src_bo[2]; } RADEONPortPrivRec, *RADEONPortPrivPtr; /* Reference color space transform data */ typedef struct tagREF_TRANSFORM { float RefLuma; float RefRCb; float RefRCr; float RefGCb; float RefGCr; float RefBCb; float RefBCr; } REF_TRANSFORM; #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) #define RTFBrightness(a) (((a)*1.0)/2000.0) #define RTFIntensity(a) (((a)*1.0)/2000.0) #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) #define RTFHue(a) (((a)*3.1416)/1000.0) XF86VideoAdaptorPtr RADEONSetupImageTexturedVideo(ScreenPtr pScreen); XF86MCAdaptorPtr RADEONCreateAdaptorXvMC(ScreenPtr pScreen, char *xv_adaptor_name); void RADEONCopyData(ScrnInfoPtr pScrn, unsigned char *src, unsigned char *dst, unsigned int srcPitch, unsigned int dstPitch, unsigned int h, unsigned int w, unsigned int bpp); void RADEONCopyMungedData(ScrnInfoPtr pScrn, unsigned char *src1, unsigned char *src2, unsigned char *src3, unsigned char *dst1, unsigned int srcPitch, unsigned int srcPitch2, unsigned int dstPitch, unsigned int h, unsigned int w); Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc); #endif xserver-xorg-video-ati-7.5.0+git20150819/src/radeon_xvmc.c000066400000000000000000000064551256524674500227600ustar00rootroot00000000000000/* * Copyright 2010 Christian König * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * * Based on vl_hwmc.c from xf86-video-nouveau * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include "radeon_video.h" #include "compat-api.h" #include #include #include "fourcc.h" #define FOURCC_RGB 0x0000003 static int subpicture_index_list[] = { FOURCC_RGB, FOURCC_IA44, FOURCC_AI44 }; static XF86MCImageIDList subpicture_list = { 3, subpicture_index_list }; static XF86MCSurfaceInfoRec yv12_mpeg2_surface = { FOURCC_YV12, XVMC_CHROMA_FORMAT_420, 0, 2048, 2048, 2048, 2048, XVMC_IDCT | XVMC_MOCOMP | XVMC_MPEG_2, XVMC_SUBPICTURE_INDEPENDENT_SCALING | XVMC_BACKEND_SUBPICTURE, &subpicture_list }; static XF86MCSurfaceInfoPtr surfaces[] = { (XF86MCSurfaceInfoPtr)&yv12_mpeg2_surface, }; static XF86ImageRec rgb_subpicture = { FOURCC_RGB, XvRGB, LSBFirst, { 'R', 'G', 'B', 0x00, 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 }, 32, XvPacked, 1, 24, 0x00FF0000, 0x0000FF00, 0x000000FF, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 'B','G','R','X', 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, XvTopToBottom }; static XF86ImageRec ia44_subpicture = XVIMAGE_IA44; static XF86ImageRec ai44_subpicture = XVIMAGE_AI44; static XF86ImagePtr subpictures[] = { (XF86ImagePtr)&rgb_subpicture, (XF86ImagePtr)&ia44_subpicture, (XF86ImagePtr)&ai44_subpicture }; static XF86MCAdaptorRec adaptor_template = { "", 1, surfaces, 3, subpictures, (xf86XvMCCreateContextProcPtr)NULL, (xf86XvMCDestroyContextProcPtr)NULL, (xf86XvMCCreateSurfaceProcPtr)NULL, (xf86XvMCDestroySurfaceProcPtr)NULL, (xf86XvMCCreateSubpictureProcPtr)NULL, (xf86XvMCDestroySubpictureProcPtr)NULL }; XF86MCAdaptorPtr RADEONCreateAdaptorXvMC(ScreenPtr pScreen, char *xv_adaptor_name) { XF86MCAdaptorPtr adaptor; ScrnInfoPtr pScrn; assert(pScreen); pScrn = xf86ScreenToScrn(pScreen); adaptor = xf86XvMCCreateAdaptorRec(); if (!adaptor) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[XvMC] Memory allocation failed.\n"); return NULL; } *adaptor = adaptor_template; adaptor->name = xv_adaptor_name; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[XvMC] Associated with %s.\n", adaptor->name); return adaptor; } xserver-xorg-video-ati-7.5.0+git20150819/src/simple_list.h000066400000000000000000000113261256524674500227750ustar00rootroot00000000000000/** * \file simple_list.h * Simple macros for type-safe, intrusive lists. * * Intended to work with a list sentinal which is created as an empty * list. Insert & delete are O(1). * * \author * (C) 1997, Keith Whitwell */ /* * Mesa 3-D graphics library * Version: 3.5 * * Copyright (C) 1999-2001 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _SIMPLE_LIST_H #define _SIMPLE_LIST_H struct simple_node { struct simple_node *next; struct simple_node *prev; }; /** * Remove an element from list. * * \param elem element to remove. */ #define remove_from_list(elem) \ do { \ (elem)->next->prev = (elem)->prev; \ (elem)->prev->next = (elem)->next; \ } while (0) /** * Insert an element to the list head. * * \param list list. * \param elem element to insert. */ #define insert_at_head(list, elem) \ do { \ (elem)->prev = list; \ (elem)->next = (list)->next; \ (list)->next->prev = elem; \ (list)->next = elem; \ } while(0) /** * Insert an element to the list tail. * * \param list list. * \param elem element to insert. */ #define insert_at_tail(list, elem) \ do { \ (elem)->next = list; \ (elem)->prev = (list)->prev; \ (list)->prev->next = elem; \ (list)->prev = elem; \ } while(0) /** * Move an element to the list head. * * \param list list. * \param elem element to move. */ #define move_to_head(list, elem) \ do { \ remove_from_list(elem); \ insert_at_head(list, elem); \ } while (0) /** * Move an element to the list tail. * * \param list list. * \param elem element to move. */ #define move_to_tail(list, elem) \ do { \ remove_from_list(elem); \ insert_at_tail(list, elem); \ } while (0) /** * Make a empty list empty. * * \param sentinal list (sentinal element). */ #define make_empty_list(sentinal) \ do { \ (sentinal)->next = sentinal; \ (sentinal)->prev = sentinal; \ } while (0) /** * Get list first element. * * \param list list. * * \return pointer to first element. */ #define first_elem(list) ((list)->next) /** * Get list last element. * * \param list list. * * \return pointer to last element. */ #define last_elem(list) ((list)->prev) /** * Get next element. * * \param elem element. * * \return pointer to next element. */ #define next_elem(elem) ((elem)->next) /** * Get previous element. * * \param elem element. * * \return pointer to previous element. */ #define prev_elem(elem) ((elem)->prev) /** * Test whether element is at end of the list. * * \param list list. * \param elem element. * * \return non-zero if element is at end of list, or zero otherwise. */ #define at_end(list, elem) ((elem) == (list)) /** * Test if a list is empty. * * \param list list. * * \return non-zero if list empty, or zero otherwise. */ #define is_empty_list(list) ((list)->next == (list)) /** * Walk through the elements of a list. * * \param ptr pointer to the current element. * \param list list. * * \note It should be followed by a { } block or a single statement, as in a \c * for loop. */ #define foreach(ptr, list) \ for( ptr=(list)->next ; ptr!=list ; ptr=(ptr)->next ) /** * Walk through the elements of a list. * * Same as #foreach but lets you unlink the current value during a list * traversal. Useful for freeing a list, element by element. * * \param ptr pointer to the current element. * \param t temporary pointer. * \param list list. * * \note It should be followed by a { } block or a single statement, as in a \c * for loop. */ #define foreach_s(ptr, t, list) \ for(ptr=(list)->next,t=(ptr)->next; list != ptr; ptr=t, t=(t)->next) #endif