ngspice-24/0000755000175000017500000000000011711023716013612 5ustar sylvestresylvestrengspice-24/COPYING0000644000175000017500000001540011711023501014635 0ustar sylvestresylvestre12345678901234567890123456789012345678901234567890123456789012345678901234567890 Ngspice-21 Documentation Copyright (c) 2010, Paolo Nenzi, Holger Vogt All rights reserved. Foreword: Spice's name was originally chosen at the University of California, Berkeley. As it is the basis of almost all circuit simulators, the major part of the analogue and mixed signals simulation's code is designed to fit with it. The *spices (generic name for its forks) are heterogeneous in many points due to the work of researchers, electronic designers, software editors, etc. The Ngspice team tries to collect work from the different sources and contribute new functionalities. Thus, the material we manipulate is heterogeneous in licenses. Keeping the licenses as is, is the way to live with that diversity. For release 21 as well, we choose not to relicense. Copyleft is a fundamental question in FOSS development. The choice of a copylefted contribution, or a non copylefted contribution is an important choice that should be respected. Ngspice branch as a whole will not be covered by a specific license. The Ngspice team wants to encourage contributions to ngspice. We let each new developper choose its position regarding copyleft, as we respect the position of the former developpers. In order to keep things clear ngspice team proposes to follow the following guidelines: Each piece of code should be kept under its original contributor's license. As for any project, modifications made in sources covered by a less restrictive license can be covered by a more restrictive license, such as GPL. We do not encourage it. If you feel to add code in a file under a different license than the rest of the file, please use comments to mark the boundaries of the modification, and edit the comments at the begining of the file with correct license and copyright information. We encourage restrictive licenses to be chosen only for new functionalities, written in distinct files, leading to distinct libraries that links depending on a specific configure flag. We encourage non proliferation of licenses (e.g. choosing either GPL, LGPL or new BSD). This heterogenous license status makes it difficult to know which license applies. Please take care of knowing which license aplies to the code you are editing, or conveying and not to commit license infringements, especially to GPL and LGPL which are quite restrictive. On 2007, July 17th spice 3f5 changed from its original license to the new BSD license. (http://embedded.eecs.berkeley.edu/pubs/downloads/spice/index.htm) On 2008, December 1st, tclspice changes license from GPL to LGPLv2, in accordance with Multigig Ltd, the copyright holder. The following table is just a reminder on license status, please don't rely on it: Author License Notes numparam Georg Post LGPL Applies to the code in frontend/numparam adms Laurent Lemaitre LGPL Applies to scripts in the spicelib/dev/adms tclspice Stefan Jones LGPL TCL integration cider U. of California Old BSD Device level simulator xspice Georgia Tech. Public D Mixed signals spice U. of California New BSD Analog circuit simulation ---------------------------------- Cider ----------------------------------- RESEARCH SOFTWARE AGREEMENT This file specifies the terms under which the software and documentation provided with this distribution are provided. Software is distributed as is, completely without warranty or service support. The University of California and its employ- ees are not liable for the condition or performance of the software. The University does not warrant that it owns the copyright or other proprietary rights to all software and documentation provided under this agreement, notwithstanding any copyright notice, and shall not be liable for any infringement of copyright or proprietary rights brought by third parties against the reci- pient of the software and documentation provided under this agreement. THE UNIVERSITY OF CALIFORNIA HEREBY DISCLAIMS ALL IMPLIED WARRANTIES, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE UNIVERSITY IS NOT LIABLE FOR ANY DAMAGES INCURRED BY THE RECIPIENT IN USE OF THE SOFTWARE AND DOCUMENTATION, INCLUDING DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The University of California grants the recipient the right to modify, copy, and redistribute the software and documentation, both within the recipient's organization and externally, subject to the following restrictions: (a) The recipient agrees not to charge for the University of California code itself. The recipient may, however, charge for additions, extensions, or support. (b) In any product based on the software, the recipient agrees to acknowledge the research group that developed the software. This acknowledgement shall appear in the product documentation. (c) The recipient agrees to obey all U.S. Government restric- tions governing redistribution or export of the software and documentation. ---------------------------------- Spice3f5 -------------------------------- Copyright (c) 1985-1991 The Regents of the University of California. All rights reserved. Permission is hereby granted, without written agreement and without license or royalty fees, to use, copy, modify, and distribute this software and its documentation for any purpose, provided that the above copyright notice and the following two paragraphs appear in all copies of this software. IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. ---------------------------------- XSPICE -------------------------------- XSPICE SOFTWARE USER'S MANUAL copyright Copyright 1992 Georgia Tech Research Corporation All Rights Reserved. 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For more info see http://www.lyx.org/ \lyxformat 345 \begin_document \begin_header \textclass book \begin_preamble % Added by lyx2lyx % for proper underlining \PassOptionsToPackage{normalem}{ulem} \usepackage{ulem} \let\cite@rig\cite \newcommand{\b@xcite}[2][\%]{\def\def@pt{\%}\def\pas@pt{#1} \mbox{\ifx\def@pt\pas@pt\cite@rig{#2}\else\cite@rig[#1]{#2}\fi}} \renewcommand{\underbar}[1]{{\let\cite\b@xcite\uline{#1}}} \end_preamble \use_default_options true \language english \inputencoding auto \font_roman times \font_sans helvet \font_typewriter lmtt \font_default_family default \font_sc false \font_osf false \font_sf_scale 100 \font_tt_scale 100 \graphics default \paperfontsize 12 \spacing single \use_hyperref true \pdf_title "ngspice user manual" \pdf_author "Poalo Nenzi, Holger Vogt, Dietmar Warning e.a." \pdf_subject "ngspice circuit simulator" \pdf_keywords "ngspice spice" \pdf_bookmarks true \pdf_bookmarksnumbered false \pdf_bookmarksopen false \pdf_bookmarksopenlevel 1 \pdf_breaklinks true \pdf_pdfborder false \pdf_colorlinks true \pdf_backref false \pdf_pdfusetitle true \pdf_quoted_options "linkcolor=blue, citecolor=black, urlcolor=blue, filecolor=blue,pdfpagelayout=OneColumn, pdfnewwindow=true,pdfstartview=XYZ, plainpages=false, pdfpagelabels,pdftex" \papersize a4paper \use_geometry true \use_amsmath 1 \use_esint 1 \cite_engine basic \use_bibtopic true \paperorientation portrait \leftmargin 2.5cm \topmargin 2cm \rightmargin 2.5cm \bottommargin 3cm \headheight 3cm \headsep 1cm \footskip 2cm \secnumdepth 3 \tocdepth 2 \paragraph_separation skip \defskip medskip \quotes_language english \papercolumns 1 \papersides 2 \paperpagestyle default \tracking_changes false \output_changes false \author "" \end_header \begin_body \begin_layout Title Ngspice Users Manual \begin_inset Newline newline \end_inset Version 24 \begin_inset Newline newline \end_inset \end_layout \begin_layout Author Paolo Nenzi, Holger Vogt \end_layout \begin_layout Standard \begin_inset Newpage newpage \end_inset \end_layout \begin_layout Section* Locations \end_layout \begin_layout Standard The project and download pages of ngspice may be found at \end_layout \begin_layout Standard Ngspice home page \begin_inset CommandInset href LatexCommand href name "http://ngspice.sourceforge.net/" target "http://ngspice.sourceforge.net/" \end_inset \end_layout \begin_layout Standard Project page at sourceforge \begin_inset CommandInset href LatexCommand href name "http://sourceforge.net/projects/ngspice/" target "http://sourceforge.net/projects/ngspice/" \end_inset \end_layout \begin_layout Standard Download page at sourceforge \begin_inset CommandInset href LatexCommand href name "http://sourceforge.net/projects/ngspice/files/" target "http://sourceforge.net/projects/ngspice/files/" \end_inset \end_layout \begin_layout Standard CVS source download \begin_inset CommandInset href LatexCommand href target "http://sourceforge.net/scm/?type=cvs&group_id=38962" \end_inset \end_layout \begin_layout Section* Status \end_layout \begin_layout Standard This manual is a work in progress. Some to-dos are listed in the following. More is surely needed. You are invited to report bugs, missing items, wrongly described items, bad English style etc. \end_layout \begin_layout Subsection* To Do \end_layout \begin_layout Enumerate Review of chapt. 1.3 \end_layout \begin_layout Enumerate hfet1,2, jfet2 model descriptions \end_layout \begin_layout Enumerate tclspice compilation chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Compiling" \end_inset \end_layout \begin_layout Subsection* How to use this manual \end_layout \begin_layout Standard The manual is a \begin_inset Quotes eld \end_inset work in progress \begin_inset Quotes erd \end_inset . It may accompany a specific ngspice release, e.g. ngspice-24 as manual version 24. If its name contains \begin_inset Quotes eld \end_inset Version xxplus \begin_inset Quotes erd \end_inset , it describes the actual code status, found at the date of issue in the concurrent version system (CVS). The manual is intended to provide a complete description of the ngspice functionality, its features, commands, or procedures. It is not a book about learning spice usage, but the novice user may find some hints how to start using ngspice. Chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:AC-coupled-transistor" \end_inset gives a short introduction how to set up and simulate a small circuit. Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" \end_inset is about compiling and installing ngspice from a tarball or the actual CVS source code, which you may find on the \begin_inset CommandInset href LatexCommand href name "ngspice web pages" target "http://ngspice.sourceforge.net/download.html" \end_inset . If you are running a specific LINUX distribution, you may check if it provides ngspice as part of the package. Some are listed \begin_inset CommandInset href LatexCommand href name "here" target "http://ngspice.sourceforge.net/packages.html" \end_inset . \end_layout \begin_layout Subsection* \begin_inset Newpage newpage \end_inset \end_layout \begin_layout Part Ngspice User Manual \end_layout \begin_layout Standard \begin_inset CommandInset toc LatexCommand tableofcontents \end_inset \end_layout \begin_layout Chapter* Prefaces \end_layout \begin_layout Section* Preface to the first edition \end_layout \begin_layout Standard This manual has been assembled from different sources: \end_layout \begin_layout Enumerate The spice3f5 manual, \end_layout \begin_layout Enumerate the XSPICE user's manual, \end_layout \begin_layout Enumerate the CIDER user's manual \end_layout \begin_layout Standard and some original material needed to describe the new features and the newly implemented models. This cut and paste approach, while not being orthodox, allowed ngspice to have a full manual in a fraction of the time that writing a completely new text would have required. The use of \begin_inset ERT status open \begin_layout Plain Layout LaTex \end_layout \end_inset and Lyx instead of \begin_inset ERT status open \begin_layout Plain Layout TeX \end_layout \end_inset info, which was the original encoding for the manual, further helped to reduce the writing effort and improved the quality of the result, at the expense of an on-line version of the manual but, due to the complexity of the software I hardly think that users will ever want to read an on-line text version. \end_layout \begin_layout Standard In writing this text I followed the cut of spice3f5 manual, both in the chapter sequence and presentation of material, mostly because that was already the user manual of spice. \end_layout \begin_layout Standard Ngspice is an open source software, users can download the source code, compile, and run it. This manual has an entire chapter describing program compilation and available options to help users in building ngspice (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" \end_inset ). The source package already comes with all \begin_inset Quotes eld \end_inset safe \begin_inset Quotes erd \end_inset options enabled by default, and activating the others can produce unpredictable results and thus is recommended to expert users only. This is the first ngspice manual and I have removed all the historical material that described the differences between ngspice and spice3, since it was of no use for the user and not so useful for the developer who can look for it in the Changelogs of in the revision control system. \end_layout \begin_layout Standard I want to acknowledge the work dome Emmanuel Rouat and Arno W. Peters for converting to TeXinfo the original spice3f documentation, their effort gave ngspice users the only available documentation that described the changes for many years. A good source of ideas for this manual comes from the on-line spice3f manual written by Charles D.H. Williams ( \begin_inset CommandInset href LatexCommand href name "Spice3f5 User Guide" target "http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/index.html#toc" \end_inset ), constantly updated and useful for some insight that he gives in it. \end_layout \begin_layout Standard As always, errors, omissions and unreadable phrases are only my fault. \end_layout \begin_layout Standard Paolo Nenzi \end_layout \begin_layout Standard Roma, March 24th 2001 \end_layout \begin_layout Quotation Indeed. At the end of the day, this is engineering, and one learns to live \end_layout \begin_layout Quotation within the limitations of the tools. \end_layout \begin_layout Standard Kevin Aylward , Warden of the Kings Ale \end_layout \begin_layout Section* Preface to the actual edition (as of January 2011) \end_layout \begin_layout Standard Due to the wealth of new material and options in ngspice the actual order of chapters has been revised. Several new chapters have been added. Thy lyx text processors has allowed adding internal cross references. The pdf format has become the standard format for distribution of the manual. Within each new ngspice distribution (starting with ngspice-21) a manual edition is provided reflecting the ngspice status at the time of distribution. At the same time, located at \begin_inset CommandInset href LatexCommand href name "ngspice manuals" target "http://ngspice.cvs.sourceforge.net/viewvc/ngspice/ngspice/ng-spice-manuals/" \end_inset , the manual is constantly updated. Every new ngspice feature should enter this manual as soon as it has been made available in the CVS source code. \end_layout \begin_layout Standard Holger Vogt \end_layout \begin_layout Standard Mülheim, 2011 \end_layout \begin_layout Chapter* Acknowledgments \end_layout \begin_layout Section* ngspice contributors \end_layout \begin_layout Standard Spice was originally written at The University of California at Berkeley (USA). \end_layout \begin_layout Standard Since then, there have been many people working on the software, most of them releasing patches to the original code through the Internet. \end_layout \begin_layout Standard The following people have contributed in some way: \end_layout \begin_layout Standard Vera Albrecht, \end_layout \begin_layout Standard Cecil Aswell, \end_layout \begin_layout Standard Giles C. Billingsley, \end_layout \begin_layout Standard Phil Barker, \end_layout \begin_layout Standard Steven Borley, \end_layout \begin_layout Standard Stuart Brorson, \end_layout \begin_layout Standard Mansun Chan, \end_layout \begin_layout Standard Wayne A. Christopher, \end_layout \begin_layout Standard Al Davis, \end_layout \begin_layout Standard Glao S. Dezai, \end_layout \begin_layout Standard Jon Engelbert, \end_layout \begin_layout Standard Daniele Foci, \end_layout \begin_layout Standard Noah Friedman, \end_layout \begin_layout Standard David A. Gates, \end_layout \begin_layout Standard Alan Gillespie, \end_layout \begin_layout Standard John Heidemann, \end_layout \begin_layout Standard Jeffrey M. Hsu, \end_layout \begin_layout Standard JianHui Huang, \end_layout \begin_layout Standard S. Hwang, \end_layout \begin_layout Standard Chris Inbody, \end_layout \begin_layout Standard Gordon M. Jacobs, \end_layout \begin_layout Standard Min-Chie Jeng, \end_layout \begin_layout Standard Beorn Johnson, \end_layout \begin_layout Standard Stefan Jones, \end_layout \begin_layout Standard Kenneth H. Keller, \end_layout \begin_layout Standard Robert Larice, \end_layout \begin_layout Standard Mathew Lew, \end_layout \begin_layout Standard Robert Lindsell, \end_layout \begin_layout Standard Weidong Liu, \end_layout \begin_layout Standard Kartikeya Mayaram, \end_layout \begin_layout Standard Richard D. McRoberts, \end_layout \begin_layout Standard Manfred Metzger, \end_layout \begin_layout Standard Wolfgang Muees, \end_layout \begin_layout Standard Paolo Nenzi, \end_layout \begin_layout Standard Gary W. Ng, \end_layout \begin_layout Standard Hong June Park, \end_layout \begin_layout Standard Stefano Perticaroli, \end_layout \begin_layout Standard Arno Peters, \end_layout \begin_layout Standard Serban-Mihai Popescu, \end_layout \begin_layout Standard Georg Post, \end_layout \begin_layout Standard Thomas L. Quarles, \end_layout \begin_layout Standard Emmanuel Rouat, \end_layout \begin_layout Standard Jean-Marc Routure, \end_layout \begin_layout Standard Jaijeet S. Roychowdhury, \end_layout \begin_layout Standard Lionel Sainte Cluque, \end_layout \begin_layout Standard Takayasu Sakurai, \end_layout \begin_layout Standard Amakawa Shuhei, \end_layout \begin_layout Standard Kanwar Jit Singh, \end_layout \begin_layout Standard Bill Swartz, \end_layout \begin_layout Standard Hitoshi Tanaka, \end_layout \begin_layout Standard Steve Tell, \end_layout \begin_layout Standard Andrew Tuckey, \end_layout \begin_layout Standard Andreas Unger, \end_layout \begin_layout Standard Holger Vogt, \end_layout \begin_layout Standard Dietmar Warning, \end_layout \begin_layout Standard Michael Widlok, \end_layout \begin_layout Standard Charles D.H. Williams, \end_layout \begin_layout Standard Antony Wilson, \end_layout \begin_layout Standard and many others... \end_layout \begin_layout Standard If someone helped in the development and has not been inserted in this list then this omission was unintentional. If you feel you should be on this list then please write to < \begin_inset CommandInset href LatexCommand href target "ngspice-devel@lists.sourceforge.net" type "mailto:" \end_inset >. Do not be shy, we would like to make a list as complete as possible. \end_layout \begin_layout Section* XSPICE \end_layout \begin_layout Standard The XSPICE simulator is based on the SPICE3 program developed by the Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley. The authors of XSPICE gratefully acknowledge UC Berkeley's development and distribution of this software, and their licensing policies which promote further improvements to simulation technology. \end_layout \begin_layout Standard We also gratefully acknowledge the participation and support of our U.S. Air Force sponsors, the Aeronautical Systems Center and the Warner Robins Air Logistics Command, without which the development of XSPICE would not have been possible. \end_layout \begin_layout Chapter Introduction \end_layout \begin_layout Standard Ngspice is a general-purpose circuit simulation program for nonlinear and linear analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent or dependent voltage and current sources, loss-less and lossy transmission lines, switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs. \end_layout \begin_layout Standard Some introductory remarks on how to use ngspice may be found in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Example-Circuits" \end_inset . \end_layout \begin_layout Standard Ngspice is an update of Spice3f5, the last Berkeley's release of Spice3 simulator family. Ngspice is being developed to include new features to existing Spice3f5 and to fix its bugs. Improving a complex software like a circuit simulator is a very hard task and, while some improvements have been made, most of the work has been done on bug fixing and code refactoring. \end_layout \begin_layout Standard Ngspice has built-in models for the semiconductor devices, and the user need specify only the pertinent model parameter values. There are three models for bipolar junction transistors, all based on the integral-charge model of Gummel and Poon; however, if the Gummel-Poon parameter s are not specified, the basic model (BJT) reduces to the simpler Ebers-Moll model. In either case and in either models, charge storage effects, ohmic resistances, and a current-dependent output conductance may be included. The second bipolar model BJT2 adds dc current computation in the substrate diode. The third model (VBIC) contains further enhancements for advanced bipolar devices. \end_layout \begin_layout Standard The semiconductor diode model can be used for either junction diodes or Schottky barrier diodes. There are two models for JFET: the first (JFET) is based on the model of Shichman and Hodges, the second (JFET2) is based on the Parker-Skellern model. All the original six MOSFET models are implemented: MOS1 is described by a square-law I-V characteristic, MOS2 [1] is an analytical model, while MOS3 [1] is a semi-empirical model; MOS6 [2] is a simple analytic model accurate in the short channel region; MOS9, is a slightly modified Level 3 MOSFET model - not to confuse with Philips level 9; BSIM 1 [3, 4]; BSIM2 [5] are the old BSIM (Berkeley Short-channel IGFET Model) models. MOS2, MOS3, and BSIM include second-order effects such as channel-length modulation, subthreshold conduction, scattering-limited velocity saturation, small-size effects, and charge controlled capacitances. The recent MOS models for submicron devices are the BSIM3 ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIM3 web page" target "http://www-device.eecs.berkeley.edu/~bsim3/intro.html" \end_inset ) and BSIM4 ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIM4 web page" target "http://www-device.eecs.berkeley.edu/~bsim3/bsim4_intro.html" \end_inset ) models. Silicon-on-insulator MOS transistors are described by the SOI models from the BSIMSOI family ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIMSOI web page" target "http://www-device.eecs.berkeley.edu/~bsimsoi/" \end_inset ) and the STAG [18] one. There is partial support for a couple of HFET models and one model for MESA devices. \end_layout \begin_layout Standard Ngspice supports mixed-level simulation and provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can provide greater simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for noncritical devices. The mixed-level extensions to ngspice are two: \end_layout \begin_layout Itemize CIDER: a mixed-level circuit and device simulator integrated into ngspice code. CIDER was originally the name of the mixed-level extension made to spice3f5. \end_layout \begin_layout Itemize GSS: GSS (now called GENIUS) TCAD is a 2D simulator developed independently from ngspice. The device simulator itself is free and not included into ngspice, but a socket interface is provided. \end_layout \begin_layout Standard Ngspice supports mixed-signal simulation through the integration of XSPICE code into it. XSPICE software, developed as an extension to Spice3C1 from GeorgiaTech, has been ported to ngspice to provide \begin_inset Quotes eld \end_inset board \begin_inset Quotes erd \end_inset level and mixed-signal simulation. \end_layout \begin_layout Standard New devices can be added to ngspice by two means: the xspice old code-model interface and the new ADMS interface based on Verilog-A and XML. \end_layout \begin_layout Standard Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms. \end_layout \begin_layout Section Simulation Algorithms \end_layout \begin_layout Standard Computer-based circuit simulation is often used as a tool by designers, test engineers, and others who want to analyze the operation of a design without examining the physical circuit. Simulation allows you to change quickly the parameters of many of the circuit elements to determine how they affect the circuit response. Often it is difficult or impossible to change these parameters in a physical circuit. \end_layout \begin_layout Standard However, to be practical, a simulator must execute in a reasonable amount of time. The key to efficient execution is choosing the proper level of modeling abstraction for a given problem. To support a given modeling abstraction, the simulator must provide appropriate algorithms. \end_layout \begin_layout Standard Historically, circuit simulators have supported either an analog simulation algorithm or a digital simulation algorithm. Ngspice inherits the XSPICE framework and supports both analog and digital algorithms and is a \begin_inset Quotes eld \end_inset mixed-mode \begin_inset Quotes erd \end_inset simulator. \end_layout \begin_layout Subsection Analog Simulation \end_layout \begin_layout Standard Analog simulation focuses on the linear and non-linear behavior of a circuit over a continuous time or frequency interval. The circuit response is obtained by iteratively solving Kirchhoff's Laws for the circuit at time steps selected to ensure the solution has converged to a stable value and that numerical approximations of integrations are sufficiently accurate. Since Kirchhoff's laws form a set of simultaneous equations, the simulator operates by solving a matrix of equations at each time point. This matrix processing generally results in slower simulation times when compared to digital circuit simulators. \end_layout \begin_layout Standard The response of a circuit is a function of the applied sources. Ngspice offers a variety of source types including DC, sine-wave, and pulse. In addition to specifying sources, the user must define the type of simulation to be run. This is termed the \begin_inset Quotes eld \end_inset mode of analysis \begin_inset Quotes erd \end_inset . Analysis modes include DC analysis, AC analysis, and transient analysis. For DC analysis, the time-varying behavior of reactive elements is neglected and the simulator calculates the DC solution of the circuit. Swept DC analysis may also be accomplished with ngspice. This is simply the repeated application of DC analysis over a range of DC levels for the input sources. For AC analysis, the simulator determines the response of the circuit, including reactive elements to small-signal sinusoidal inputs over a range of frequencies. The simulator output in this case includes amplitudes and phases as a function of frequency. For transient analysis, the circuit response, including reactive elements, is analyzed to calculate the behavior of the circuit as a function of time. \end_layout \begin_layout Subsection Digital Simulation \end_layout \begin_layout Standard Digital circuit simulation differs from analog circuit simulation in several respects. A primary difference is that a solution of Kirchhoff's laws is not required. Instead, the simulator must only determine whether a change in the logic state of a node has occurred and propagate this change to connected elements. Such a change is called an \begin_inset Quotes eld \end_inset event \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard When an event occurs, the simulator examines only those circuit elements that are affected by the event. As a result, matrix analysis is not required in digital simulators. By comparison, analog simulators must iteratively solve for the behavior of the entire circuit because of the forward and reverse transmission propertie s of analog components. This difference results in a considerable computational advantage for digital circuit simulators, which is reflected in the significantly greater speed of digital simulations. \end_layout \begin_layout Subsection Mixed-Mode Simulation \end_layout \begin_layout Standard Modern circuits often contain a mix of analog and digital circuits. To simulate such circuits efficiently and accurately a mix of analog and digital simulation techniques is required. When analog simulation algorithms are combined with digital simulation algorithms, the result is termed \begin_inset Quotes eld \end_inset mixed-mode simulation \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard Two basic methods of implementing mixed-mode simulation used in practice are the \begin_inset Quotes eld \end_inset native mode \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset glued mode \begin_inset Quotes erd \end_inset approaches. Native mode simulators implement both an analog algorithm and a digital algorithm in the same executable. Glued mode simulators actually use two simulators, one of which is analog and the other digital. This type of simulator must define an input/output protocol so that the two executables can communicate with each other effectively. The communication constraints tend to reduce the speed, and sometimes the accuracy, of the complete simulator. On the other hand, the use of a glued mode simulator allows the component models developed for the separate executables to be used without modification. \end_layout \begin_layout Standard Ngspice is a native mode simulator providing both analog and event-based simulation in the same executable. The underlying algorithms of ngspice (coming from XSPICE and its Code Model Subsystem) allow use of all the standard SPICE models, provide a pre-defined collection of the most common analog and digital functions, and provide an extensible base on which to build additional models. \end_layout \begin_layout Subsubsection User-Defined Nodes \end_layout \begin_layout Standard Ngspice supports creation of \begin_inset Quotes eld \end_inset User-Defined Node \begin_inset Quotes erd \end_inset types. User-Defined Node types allow you to specify nodes that propagate data other than voltages, currents, and digital states. Like digital nodes, User-Defined Nodes use event-driven simulation, but the state value may be an arbitrary data type. A simple example application of User-Defined Nodes is the simulation of a digital signal processing filter algorithm. In this application, each node could assume a real or integer value. More complex applications may define types that involve complex data such as digital data vectors or even non-electronic data. \end_layout \begin_layout Standard Ngspice digital simulation is actually implemented as a special case of this User-Defined Node capability where the digital state is defined by a data structure that holds a Boolean logic state and a strength value. \end_layout \begin_layout Subsection Mixed-Level Simulation \end_layout \begin_layout Standard Ngspice can simulate numerical device models for diodes and transistors in two different ways, either through the integrated DSIM simulator or interfacing to GSS TCAD system. DSIM is an internal C-based device simulator which is part of the CIDER simulator, the mixed-level simulator based on spice3f5. CIDER within ngspice provides circuit analyses, compact models for semiconducto r devices, and one- or two-dimesional numerical device models. \end_layout \begin_layout Subsubsection CIDER (DSIM) \end_layout \begin_layout Standard DSIM provides accurate, one- and two-dimensional numerical device models based on the solution of Poisson's equation, and the electron and hole current-continuity equations. DSIM incorporates many of the same basic physical models found in the Stanford two-dimensional device simulator PISCES. Input to CIDER consists of a SPICE-like description of the circuit and its compact models, and PISCES-like descriptions of the structures of numerical ly modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. CIDER is based on the mixed-level circuit and device simulator CODECS, and is a replacement for this program. The basic algorithms of the two programs are the same. Some of the differences between CIDER and CODECS are described below. The CIDER input format has greater flexibility and allows increased access to physical model parameters. New physical models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation important in scaled-down MOSFETs and a polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included over the range from -50C to 150C. The numerical models can be used to simulate all the basic types of semiconduct or devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the management of device internal states. Post-processing of device states can be performed using the ngnutmeg user interface. \end_layout \begin_layout Subsubsection GSS TCAD \end_layout \begin_layout Standard GSS is a TCAD software which enables two-dimensional numerical simulation of semiconductor device with well-known drift-diffusion and hydrodynamic method. GSS has Basic DDM (drift-diffusion method) solver, Lattice Temperature Corrected DDM solver, EBM (energy balance method) solver and Quantum corrected DDM solver which based on density-gradient theory. The GSS program is directed via input statements by a user specified disk file. Supports triangle mesh generation and adaptive mesh refinement. Employs PMI (physical model interface) to support various materials, including compound semiconductor materials such as SiGe and AlGaAs. Supports DC sweep, transient and AC sweep calculations. The device can be stimulated by voltage or current source(s). \end_layout \begin_layout Standard GSS is no longer updated, but is still available as open source as a limited edition of the commercial GENIUS TCAD tool. \end_layout \begin_layout Section Supported Analyses \end_layout \begin_layout Standard The ngspice simulator supports the following different types of analysis: \end_layout \begin_layout Enumerate DC Analysis (Operating Point and DC Sweep) \end_layout \begin_layout Enumerate AC Small- Signal Analysis \end_layout \begin_layout Enumerate Transient Analysis \end_layout \begin_layout Enumerate Pole-Zero Analysis \end_layout \begin_layout Enumerate Small-Signal Distortion Analysis \end_layout \begin_layout Enumerate Sensitivity Analysis \end_layout \begin_layout Enumerate Noise Analysis \end_layout \begin_layout Standard Applications that are exclusively analog can make use of all analysis modes with the exception of Code Model subsystem that do not implements Pole-Zero, Distortion, Sensitivity and Noise analyses. Event-driven applications that include digital and User-Defined Node types may make use of DC (operating point and DC sweep) and Transient only. \end_layout \begin_layout Standard In order to understand the relationship between the different analyses and the two underlying simulation algorithms of ngspice, it is important to understand what is meant by each analysis type. This is detailed below. \end_layout \begin_layout Standard \end_layout \begin_layout Subsection DC Analyses \end_layout \begin_layout Standard The dc analysis portion of ngspice determines the dc operating point of the circuit with inductors shorted and capacitors opened. The dc analysis options are specified on the \family typewriter .DC \family default , \family typewriter .TF \family default , and \family typewriter .OP \family default control lines. \end_layout \begin_layout Standard There is assumed to be no time dependence on any of the sources within the system description. The simulator algorithm subdivides the circuit into those portions which require the analog simulator algorithm and those which require the event-driven algorithm. Each subsystem block is then iterated to solution, with the interfaces between analog nodes and event-driven nodes iterated for consistency across the entire system. \end_layout \begin_layout Standard Once stable values are obtained for all nodes in the system, the analysis halts and the results may be displayed or printed out as you request them. \end_layout \begin_layout Standard A dc analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an ac small-signal analysis to determine the linearized, small-signal models for nonlinear devices. If requested, the dc small-signal value of a transfer function (ratio of output variable to input source), input resistance, and output resistance is also computed as a part of the dc solution. The dc analysis can also be used to generate dc transfer curves: a specified independent voltage, current source, resistor or temperature \begin_inset Foot status collapsed \begin_layout Plain Layout Temperature ( \family typewriter TEMP \family default ) and resistance sweeps have been introduced in Ngspice, they were not available in the original code of Spice3f5. \end_layout \end_inset is stepped over a user-specified range and the dc output variables are stored for each sequential source value. \end_layout \begin_layout Subsection AC Small-Signal Analysis \end_layout \begin_layout Standard AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the analog system described at a particular frequency or set of frequencies. This analysis is similar to the DC analysis in that it represents the steady-st ate behavior of the described system with a single input node \shape italic at a given set of stimulus frequencies \shape default . \end_layout \begin_layout Standard The program first computes the dc operating point of the circuit and determines linearized, small-signal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed over a user-specified range of frequencies. The desired output of an ac small-signal analysis is usually a transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is convenient to set that input to unity and zero phase, so that output variables have the same value as the transfer function of the output variable with respect to the input. \end_layout \begin_layout Subsection Transient Analysis \end_layout \begin_layout Standard Transient analysis is an extension of DC analysis to the time domain. A transient analysis begins by obtaining a DC solution to provide a point of departure for simulating time-varying behavior. Once the DC solution is obtained, the time-dependent aspects of the system are reintroduced, and the two simulator algorithms incrementally solve for the time varying behavior of the entire system. Inconsistencies in node values are resolved by the two simulation algorithms such that the time-dependent waveforms created by the analysis are consistent across the entire simulated time interval. Resulting time-varying descriptions of node behavior for the specified time interval are accessible to you. \end_layout \begin_layout Standard All sources which are not time dependent (for example, power supplies) are set to their dc value. The transient time interval is specified on a \family typewriter .TRAN \family default control line. \end_layout \begin_layout Subsection Pole-Zero Analysis \end_layout \begin_layout Standard The pole-zero analysis portion of Ngspice computes the poles and/or zeros in the small-signal ac transfer function. The program first computes the dc operating point and then determines the linearized, small-signal models for all the nonlinear devices in the circuit. This circuit is then used to find the poles and zeros of the transfer function. Two types of transfer functions are allowed: one of the form (output voltage)/( input voltage) and the other of the form (output voltage)/(input current). These two types of transfer functions cover all the cases and one can find the poles/zeros of functions like input/output impedance and voltage gain. The input and output ports are specified as two pairs of nodes. The pole-zero analysis works with resistors, capacitors, inductors, linear-cont rolled sources, independent sources, BJTs, MOSFETs, JFETs and diodes. Transmission lines are not supported. The method used in the analysis is a sub-optimal numerical search. For large circuits it may take a considerable time or fail to find all poles and zeros. For some circuits, the method becomes "lost" and finds an excessive number of poles or zeros. \end_layout \begin_layout Subsection Small-Signal Distortion Analysis \end_layout \begin_layout Standard The distortion analysis portion of Ngspice computes steady-state harmonic and intermodulation products for small input signal magnitudes. If signals of a single frequency are specified as the input to the circuit, the complex values of the second and third harmonics are determined at every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis finds out the complex values of the circuit variables at the sum and difference of the input frequencies, and at the difference of the smaller frequency from the second harmonic of the larger frequency. Distortion analysis is supported for the following nonlinear devices: \end_layout \begin_layout Itemize Diodes (DIO), \end_layout \begin_layout Itemize BJT, \end_layout \begin_layout Itemize JFET, \end_layout \begin_layout Itemize MOSFETs (levels 1, 2, 3, 6, 9, BSIM1, BSIM2, BSIM3, BSIM4 and BSIMSOI), \end_layout \begin_layout Itemize MESFETS. \end_layout \begin_layout Standard All linear devices are automatically supported by distortion analysis. If there are switches present in the circuit, the analysis continues to be accurate provided the switches do not change state under the small excitatio ns used for distortion calculations. \end_layout \begin_layout Subsection Sensitivity Analysis \end_layout \begin_layout Standard Ngspice will calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an output variable with respect to all circuit variables, including model parameters. Ngspice calculates the difference in an output variable (either a node voltage or a branch current) by perturbing each parameter of each device independently. Since the method is a numerical approximation, the results may demonstrate second order affects in highly sensitive parameters, or may fail to show very low but non-zero sensitivity. Further, since each variable is perturb by a small fraction of its value, zero-valued parameters are not analyzed (this has the benefit of reducing what is usually a very large amount of data). \end_layout \begin_layout Subsection Noise Analysis \end_layout \begin_layout Standard The noise analysis portion of Ngspice does analysis device-generated noise for the given circuit. When provided with an input source and an output port, the analysis calculates the noise contributions of each device (and each noise generator within the device) to the output port voltage. It also calculates the input noise to the circuit, equivalent to the output noise referred to the specified input source. This is done for every frequency point in a specified range - the calculated value of the noise corresponds to the spectral density of the circuit variable viewed as a stationary Gaussian stochastic process. After calculating the spectral densities, noise analysis integrates these values over the specified frequency range to arrive at the total noise voltage/current (over this frequency range). This calculated value corresponds to the variance of the circuit variable viewed as a stationary Gaussian process. \end_layout \begin_layout Subsection Periodic Steady State Analysis \end_layout \begin_layout Standard (Experimental code, not yet made publicly available!) \end_layout \begin_layout Standard PSS is a radio frequency periodical large-signal dedicated analysis. The implementation is based on a time domain shooting like method which make use of Transient analysis. As it is in early development stage, PSS performs analysis only on autonomous circuits, meaning that it is only able to predict fundamental frequency and amplitude (and also harmonics) for oscillators, VCOs, etc.. The algorithm is based on a minimum search of the error vector taken as the difference of RHS vectors between two occurrences of an estimated period. The convergence is reached when the mean of error vector decrease below a given threshold that can be set as a analysis parameter. Results of this analysis are the basis of every periodical large-signal analysis as PAC or PNoise. \end_layout \begin_layout Section Analysis at Different Temperatures \begin_inset Note Note status open \begin_layout Plain Layout Need review \end_layout \end_inset \end_layout \begin_layout Standard Temperature, in ngspice, is a property associated to the entire circuit, rather an analysis option. Circuit temperature has a default (nominal) value of 27°C (300.15 K) that can be changed using the \family typewriter \series bold TNOM \family default \series default option in an \family typewriter .option \family default control line. All analyses are, thus, performed at circuit temperature, and if you want to simulate circuit behavior at different temperatures you should prepare a netlist for each temperature. \end_layout \begin_layout Standard All input data for ngspice is assumed to have been measured at the circuit nominal temperature. This value can further be overridden for any device which models temperature effects by specifying the \family typewriter \series bold TNOM \family default \series default parameter on the \family typewriter .model \family default itself. Individual instances may further override the circuit temperature through the specification of \family typewriter \series bold TEMP \family default \series default and \family typewriter \series bold DTEMP \family default \series default parameters on the instance. The two options are not independent even if you can specify both on the instance line, the \family typewriter \series bold TEMP \family default \series default option overrides \family typewriter \series bold DTEMP \family default \series default . The algorithm to compute instance temperature is described below: \end_layout \begin_layout Standard \begin_inset Float algorithm placement H wide false sideways false status open \begin_layout Plain Layout IF TEMP is specified THEN \end_layout \begin_layout Plain Layout instance_temperature = TEMP \end_layout \begin_layout Plain Layout ELSE IF \end_layout \begin_layout Plain Layout instance_temperature = circuit_temperature + DTEMP \end_layout \begin_layout Plain Layout END IF \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout Instance temperature computation \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Temperature dependent support is provided for all devices except voltage and current sources (either independent and controlled) and BSIM models. BSIM MOSFETs have an alternate temperature dependency scheme which adjusts all of the model parameters before input to ngspice. \end_layout \begin_layout Standard For details of the BSIM temperature adjustment, see \begin_inset CommandInset citation LatexCommand cite key "key-6" \end_inset and \begin_inset CommandInset citation LatexCommand cite key "key-7" \end_inset . Temperature appears explicitly in the exponential terms of the BJT and diode model equations. In addition, saturation currents have a built-in temperature dependence. The temperature dependence of the saturation current in the BJT models is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{S}\left(T_{1}\right)=I_{S}\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{XTI}\exp\left(\frac{E_{g}q\left(T_{1}T_{0}\right)}{k\left(T_{1}-T_{0}\right)}\right)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $k$ \end_inset is Boltzmann's constant, \begin_inset Formula $q$ \end_inset is the electronic charge, \begin_inset Formula $E_{g}$ \end_inset is the energy gap which is a model parameter, and \begin_inset Formula $XTI$ \end_inset is the saturation current temperature exponent (also a model parameter, and usually equal to 3). \end_layout \begin_layout Standard The temperature dependence of forward and reverse beta is according to the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} B\left(T_{1}\right)=B\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{XTB}\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $T_{0}$ \end_inset and \begin_inset Formula $T_{1}$ \end_inset are in degrees Kelvin, and \begin_inset Formula $XTB$ \end_inset is a user-supplied model parameter. Temperature effects on beta are carried out by appropriate adjustment to the values of \begin_inset Formula $B_{F}$ \end_inset , \begin_inset Formula $I_{SE}$ \end_inset , \begin_inset Formula $B_{R}$ \end_inset , and \begin_inset Formula $I_{SC}$ \end_inset (spice model parameters BF, ISE, BR, and ISC, respectively). \end_layout \begin_layout Standard Temperature dependence of the saturation current in the junction diode model is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{S}\left(T_{1}\right)=I_{S}\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{\frac{XTI}{N}}\exp\left(\frac{E_{g}q\left(T_{1}T_{0}\right)}{Nk\left(T_{1}-T_{0}\right)}\right)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $N$ \end_inset is the emission coefficient, which is a model parameter, and the other symbols have the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature exponent, \begin_inset Formula $XTI$ \end_inset , is usually 2. Temperature appears explicitly in the value of junction potential, U (in Ngspice PHI), for all the device models. \end_layout \begin_layout Standard The temperature dependence is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} U\left(T\right)=\frac{kT}{q}\ln\left(\frac{N_{a}N_{d}}{N_{i}\left(T\right)^{2}}\right)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $k$ \end_inset is Boltzmann's constant, \begin_inset Formula $q$ \end_inset is the electronic charge, \begin_inset Formula $N_{a}$ \end_inset is the acceptor impurity density, \begin_inset Formula $N_{d}$ \end_inset is the donor impurity density, \begin_inset Formula $N_{i}$ \end_inset is the intrinsic carrier concentration, and \begin_inset Formula $E_{g}$ \end_inset is the energy gap. Temperature appears explicitly in the value of surface mobility, \begin_inset Formula $M_{0}$ \end_inset (or \begin_inset Formula $U_{0}$ \end_inset ), for the MOSFET model. \end_layout \begin_layout Standard The temperature dependence is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} M_{0}\left(T\right)=\frac{M_{0}\left(T_{0}\right)}{\left(\frac{T}{T_{0}}\right)^{1.5}}\end{equation} \end_inset \end_layout \begin_layout Standard The effects of temperature on resistors, capacitor and inductors is modeled by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R\left(T\right)=R\left(T_{0}\right)\left[1+TC_{1}\left(T-T_{0}\right)+TC_{2}\left(T-T_{0}\right)^{2}\right]\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $T$ \end_inset is the circuit temperature, \begin_inset Formula $T_{0}$ \end_inset is the nominal temperature, and \begin_inset Formula $TC_{1}$ \end_inset and \begin_inset Formula $TC_{2}$ \end_inset are the first and second order temperature coefficients. \end_layout \begin_layout Section Convergence \end_layout \begin_layout Standard Ngspice uses the Newton-Raphson algorithm to solve nonlinear equations arising from circuit description. The NR algorithm is interactive and terminates when both of the following conditions hold: \end_layout \begin_layout Enumerate The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e-12 Amp), whichever is larger. \end_layout \begin_layout Enumerate The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6 Volt), whichever is larger. \end_layout \begin_layout Subsection Voltage convergence criterion \end_layout \begin_layout Standard The algorithm has reached convergence if the difference between the last iteration \begin_inset Formula $k$ \end_inset and the current one ( \begin_inset Formula $k+1)$ \end_inset : \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \left|v_{n}^{(k+1)}-v_{n}^{(k)}\right|\leq\mathtt{RELTOL}*v_{n_{max}}+\mathtt{VNTOL}\end{equation} \end_inset \end_layout \begin_layout Standard where \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} v_{n_{max}}=\max\left(\left|v_{n}^{(k+1)}\right|,\left|v_{n}^{(k)}\right|\right)\end{equation} \end_inset \end_layout \begin_layout Standard The \family typewriter RELTOL \family default (RELative TOLerance) parameter, which default value is \begin_inset Formula $10^{-3}$ \end_inset , specifies how small the solution update must be, relative to the node voltage, to consider the solution to have converged. The \family typewriter VNTOL \family default (absolute convergence) parameter, which has \begin_inset Formula $1\mu V$ \end_inset as default becomes important when node voltages have near zero values. The relative parameter alone, in such case, would need too strict tolerances, perhaps lower than computer round-off error, and thus convergence would never be achieved. \family typewriter VNTOL \family default forces the algorithm to consider as converged any node whose solution update is lower than its value. \end_layout \begin_layout Subsection Current convergence criterion \end_layout \begin_layout Standard Ngspice checks the convergence on the non-linear functions that describe the non-linear branches in circuit elements. In semiconductor devices the functions defines currents through the device and thus the name of the criterion. \end_layout \begin_layout Standard Ngspice computes the difference between the value of the nonlinear function computed for last voltage and the linear approximation of the same current computed with the actual voltage: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \left|\widehat{i_{branch}^{(k+1)}}-i_{branch}^{(k)}\right|\leq\mathtt{RELTOL}*i_{br_{max}}+\mathtt{ABSTOL}\end{equation} \end_inset \end_layout \begin_layout Standard where \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} i_{br_{max}}=\max\left(\widehat{i_{branch}^{(k+1)}},i_{branch}^{(k)}\right)\end{equation} \end_inset \end_layout \begin_layout Standard In the two expressions above, the \begin_inset Formula $\widehat{i_{branch}}$ \end_inset indicates the linear approximation of the current. \end_layout \begin_layout Subsection Convergence failure \end_layout \begin_layout Standard Although the algorithm used in ngspice has been found to be very reliable, in some cases it fails to converge to a solution. When this failure occurs, the program terminates the job. Failure to converge in dc analysis is usually due to an error in specifying circuit connections, element values, or model parameter values. Regenerative switching circuits or circuits with positive feedback probably will not converge in the dc analysis unless the \family typewriter \series bold OFF \family default \series default option is used for some of the devices in the feedback path, \family typewriter .nodeset \family default control line is used to force the circuit to converge to the desired state. \end_layout \begin_layout Chapter Circuit Description \end_layout \begin_layout Section General Structure and Conventions \end_layout \begin_layout Standard The circuit to be analyzed is described to ngspice by a set of element lines, which define the circuit topology and element values, and a set of control lines, which define the model parameters and the run controls. All lines are assembled in an input file to be read by ngspice. Two lines are essential: \end_layout \begin_layout Itemize The first line in the input file must be the title, which is the only comment line that does not need any special character in the first place. \end_layout \begin_layout Itemize The last line must be \family typewriter .end \family default . \end_layout \begin_layout Standard The order of the remaining lines is arbitrary (except, of course, that continuat ion lines must immediately follow the line being continued). This feature in the ngspice input language dates back to the punched card times where elements were written on separate cards (and cards frequently fell off). Leading white spaces in a line are ignored, as well as empty lines. \end_layout \begin_layout Standard Each element in the circuit is specified by an element line that contains: \end_layout \begin_layout Itemize the element name, \end_layout \begin_layout Itemize the circuit nodes to which the element is connected, \end_layout \begin_layout Itemize and the values of the parameters that determine the electrical characteristics of the element. \end_layout \begin_layout Standard The first letter of the element name specifies the element type. The format for the ngspice element types is given in what follows. In the rest of the manual, the strings \family typewriter XXXXXXX \family default , \family typewriter YYYYYYY \family default , and \family typewriter ZZZZZZZ \family default denote arbitrary alphanumeric strings. \end_layout \begin_layout Standard For example, a resistor name must begin with the letter \family typewriter R \family default and can contain one or more characters. Hence, \family typewriter R \family default , \family typewriter R1 \family default , \family typewriter \series bold \series default RSE \family default , \family typewriter ROUT \family default , and \family typewriter R3AC2ZY \family default are valid resistor names. Details of each type of device are supplied in a following section \begin_inset CommandInset ref LatexCommand ref reference "cha:Circuit-Elements-and" \end_inset . \end_layout \begin_layout Standard Fields on a line are separated by one or more blanks, a comma, an equal ( \family typewriter = \family default ) sign, or a left or right parenthesis; extra spaces are ignored. A line may be continued by entering a \begin_inset Quotes eld \end_inset \family typewriter + \family default \begin_inset Quotes erd \end_inset (plus) in column 1 of the following line; ngspice continues reading beginning with column 2. A name field must begin with a letter (A through Z) and cannot contain any delimiters. A number field may be an integer field (12, -44), a floating point field (3.14159), either an integer or floating point number followed by an integer exponent (1e-14, 2.65e3), or either an integer or a floating point number followed by one of the following scale factors: \end_layout \begin_layout Standard \begin_inset Float table placement H wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Suffix \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout T \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tera \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{12}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Giga \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{9}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mega \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Kilo \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mil \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mil \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $25.4\times10^{-6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout milli \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout u \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout micro \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nano \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-9}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pico \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-12}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout f \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout femto \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-15}$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout Ngspice scale factors \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000, 1000.0, 1000Hz, 1e3, 1.0e3, 1kHz, and 1k all represent the same number. \end_layout \begin_layout Standard Nodes names may be arbitrary character strings and are case insensitive. The ground node must be named \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset (zero). For compatibility reason \begin_inset Quotes eld \end_inset gnd \begin_inset Quotes erd \end_inset is accepted as ground node, and will internally be treated as a global node and be converted to \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset . \series bold Each circuit has to have a ground node (gnd or 0)! \series default Note the difference in ngspice where the nodes are treated as character strings and not evaluated as numbers, thus \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset 00 \begin_inset Quotes erd \end_inset are distinct nodes in ngspice but not in SPICE2. \end_layout \begin_layout Standard Ngspice requires that the following topological constraints are satisfied: \end_layout \begin_layout Itemize The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cut-set of current sources and/or capacitors. \end_layout \begin_layout Itemize Each node in the circuit must have a dc path to ground. \end_layout \begin_layout Itemize Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway). \end_layout \begin_layout Section Basic lines \end_layout \begin_layout Subsection .TITLE line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout POWER AMPLIFIER CIRCUIT \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The title line must be the first in the input file. Its contents are printed verbatim as the heading for each section of output. \end_layout \begin_layout Standard As an alternative you may place a \family typewriter .TITLE \family default line anywhere in your input deck. The first line of your input deck will be overridden by the contents of this line following the .TITLE statement. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout .TITLE line example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ****************************** \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout .TITLE Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard will internally be replaced by \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Internal input deck: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout *TITLE Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection .END Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The ".End" line must always be the last in the input file. Note that the period is an integral part of the name. \end_layout \begin_layout Subsection Comments \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * RF=1K Gain should be 100 \end_layout \begin_layout Plain Layout * Check open-loop gain and phase margin \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The asterisk in the first column indicates that this line is a comment line. Comment lines may be placed anywhere in the circuit description. \end_layout \begin_layout Subsection End-of-line comments \end_layout \begin_layout Standard General Form: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout ; \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout RF2=1K ;Gain should be 100 \end_layout \begin_layout Plain Layout C1=10p $ Check open-loop gain and phase margin \end_layout \end_inset \end_layout \begin_layout Standard ngspice supports comments that begin with single characters ';' or double characters '$ ' or '//' or '--' \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Device-Models" \end_inset Device Models \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .model mname type(pname1=pval1 pname2=pval2 ... ) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .model MOD1 npn (bf=50 is=1e-13 vbf=50) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Most simple circuit elements typically require only a few parameter values. However, some devices (semiconductor devices in particular) that are included in ngspice require many parameter values. Often, many devices in a circuit are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate \family typewriter .model \family default line and assigned a unique model name. The device element lines in ngspice then refer to the model name. \end_layout \begin_layout Standard For these more complex device types, each device element line contains the device name, the nodes to which the device is connected, and the device model name. In addition, other optional parameters may be specified for some devices: geometric factors and an initial condition (see the following section on Transistors ( \begin_inset CommandInset ref LatexCommand ref reference "cha:BJTs" \end_inset to \begin_inset CommandInset ref LatexCommand ref reference "cha:MOSFETs" \end_inset ) and Diodes ( \begin_inset CommandInset ref LatexCommand ref reference "cha:DIODEs" \end_inset ) for more details). \family typewriter mname \family default in the above is the model name, and type is one of the following fifteen types: \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Model Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Semiconductor resistor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Semiconductor capacitor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage controlled switch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current controlled switch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout URC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniform distributed RC model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LTRA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lossy transmission line model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NPN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NPN BJT model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PNP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PNP BJT model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NJF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel JFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PJF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel JFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel MOSFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel MOSFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NMF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel MESFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PMF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel MESFET model \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout Ngspice model types \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard Parameter values are defined by appending the parameter name followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type. Models are listed in the section on each device along with the description of device element lines. Model parameters and their default values are given in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" \end_inset . \end_layout \begin_layout Section Subcircuits \end_layout \begin_layout Standard A subcircuit that consists of ngspice elements can be defined and referenced in a fashion similar to device models. Subcircuits are the way ngspice implements hierarchical modeling, but this is not entirely true because each subcircuit instance is flattened during parsing, and thus ngspice is not a hierarchical simulator. \end_layout \begin_layout Standard The subcircuit is defined in the input deck by a grouping of element cards delimited by the \family typewriter .subckt \family default and the \family typewriter .ends \family default cards (or the keywords defined by the substart and subend options (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset )); the program then automatically inserts the defined group of elements wherever the subcircuit is referenced. Instances of subcircuits within a larger circuit are defined through the use of an instance card which begins with the letter \begin_inset Quotes eld \end_inset \family typewriter X \family default \begin_inset Quotes erd \end_inset . A complete example of all three of these cards follows: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * The following is the instance card: \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout xdiv1 10 7 0 vdivide \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * The following are the subcircuit definition cards: \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .subckt vdivide 1 2 3 \end_layout \begin_layout Plain Layout r1 1 2 10K \end_layout \begin_layout Plain Layout r2 2 3 5K \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \end_inset \end_layout \begin_layout Standard The above specifies a subcircuit with ports numbered \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset 2 \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset 3 \begin_inset Quotes erd \end_inset : \end_layout \begin_layout Itemize Resistor \begin_inset Quotes erd \end_inset R1 \begin_inset Quotes erd \end_inset is connected from port \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset to port \begin_inset Quotes eld \end_inset 2 \begin_inset Quotes erd \end_inset , and has value 10 kOhms. \end_layout \begin_layout Itemize Resistor \begin_inset Quotes eld \end_inset R2 \begin_inset Quotes erd \end_inset is connected from port \begin_inset Quotes eld \end_inset 2 \begin_inset Quotes erd \end_inset to port \begin_inset Quotes eld \end_inset 3 \begin_inset Quotes erd \end_inset , and has value 5 kOhms. \end_layout \begin_layout Standard The instance card, when placed in an ngspice deck, will cause subcircuit port \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset to be equated to circuit node \begin_inset Quotes eld \end_inset 10 \begin_inset Quotes erd \end_inset , while port \begin_inset Quotes eld \end_inset 2 \begin_inset Quotes erd \end_inset will be equated to node \begin_inset Quotes eld \end_inset 7 \begin_inset Quotes erd \end_inset and port \begin_inset Quotes eld \end_inset 3 \begin_inset Quotes erd \end_inset will equated to node \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard There is no limit on the size or complexity of subcircuits, and subcircuits may contain other subcircuits. An example of subcircuit usage is given in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:MOS-Four-Bit" \end_inset . \end_layout \begin_layout Subsection .SUBCKT Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SUBCKT subnam N1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SUBCKT OPAMP 1 2 3 4 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A circuit definition is begun with a \family typewriter .SUBCKT \family default line. SUBNAM is the subcircuit name, and N1, N2, ... are the external nodes, which cannot be zero. The group of element lines which immediately follow the \family typewriter .SUBCKT \family default line define the subcircuit. The last line in a subcircuit definition is the \family typewriter .ENDS \family default line (see below). Control lines may not appear within a subcircuit definition; however, subcircui t definitions may contain anything else, including other subcircuit definitions, device models, and subcircuit calls (see below). Note that any device models or subcircuit definitions included as part of a subcircuit definition are strictly local (i.e., such models and definitions are not known outside the subcircuit definition). Also, any element nodes not included on the \family typewriter .SUBCKT \family default line are strictly local, with the exception of 0 (ground) which is always global. If you use parameters, the \family typewriter .SUBCKT \family default line will be extended (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Subcircuit-parameters" \end_inset ). \end_layout \begin_layout Subsection .ENDS Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ENDS \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ENDS OPAMP \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .ENDS \family default line must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being terminated; if omitted, all subcircuits being defined are terminated. The name is needed only when nested subcircuit definitions are being made. \end_layout \begin_layout Subsection Subcircuit Calls \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout XYYYYYYY N1 SUBNAM \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout X1 2 4 17 3 1 MULTI \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Subcircuits are used in ngspice by specifying pseudo-elements beginning with the letter X, followed by the circuit nodes to be used in expanding the subcircuit. If you use parameters, the subcircuit call will be modified (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Subcircuit-parameters" \end_inset ). \end_layout \begin_layout Section .GLOBAL \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .GLOBAL nodename \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .GLOBAL gnd vcc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Nodes defined in the .GLOBAL statement are available to all circuit and subcircui t blocks independently from any circuit hierarchy. After parsing the circuit, these nodes are accessible from top level. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.INCLUDE" \end_inset .INCLUDE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .INCLUDE filename \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .INCLUDE /users/spice/common/wattmeter.cir \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Frequently, portions of circuit descriptions will be reused in several input files, particularly with common models and subcircuits. In any ngspice input file, the \family typewriter .INCLUDE \family default line may be used to copy some other file as if that second file appeared in place of the \family typewriter .INCLUDE \family default line in the original file. \end_layout \begin_layout Standard There is no restriction on the file name imposed by ngspice beyond those imposed by the local operating system. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.LIB" \end_inset .LIB \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .LIB filename libname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .LIB /users/spice/common/mosfets.lib mos1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .LIB \family default statement allows to include library descriptions into the input file. Inside the *.lib file a library \series bold libname \series default will be selected. The statements of each library inside the *.lib file are enclosed in \family typewriter .LIB libname <...> .ENDL \family default statements. \end_layout \begin_layout Standard If the compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Compatibility" \end_inset ) is set to \family typewriter 'ps' \family default by \family typewriter set ngbehavior=ps \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset ) in spinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) or .spiceinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ), then a simplyfied syntax \family typewriter .LIB filename \family default is available: a warning is issued and \family typewriter filename \family default is simply included as described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCLUDE" \end_inset . \end_layout \begin_layout Section .PARAM Parametric netlists \end_layout \begin_layout Standard Ngspice allows for the definition of parametric attributes in the netlists. This is an enhancement of the ngspice front-end which adds arithmetic functiona lity to the circuit description language. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.param-line" \end_inset .param line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .param = ; = .... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .param pippo=5 \end_layout \begin_layout Plain Layout .param pp=6 \end_layout \begin_layout Plain Layout .param pippp={pippo + pp} \end_layout \begin_layout Plain Layout .param p={pp} \end_layout \begin_layout Plain Layout .param pap='pp+p' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This line assigns numerical values to identifiers. More than one assignment per line is possible using the ';' separator. The \family typewriter .param \family default lines inside subcircuits are copied per call, like any other line. All assignments are executed sequentially through the expanded circuit. Before its first use, a parameter name must have been assigned a value. Expression defining a parameter have to be put into braces \family typewriter {p+p2} \family default , alternatively into single quotes \family typewriter 'p+p2' \family default . \end_layout \begin_layout Subsection Brace expressions in circuit elements: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout { } \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \end_inset \end_layout \begin_layout Standard These are allowed in \family typewriter .model \family default lines and in device lines. A spice number is a floating point number with an optional scaling suffix, immediately glued to the numeric tokens (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Syntax-of-expressions" \end_inset ). Brace expressions ({..}) cannot be used to parametrize node names or parts of names. All identifiers used within an \family typewriter \family default must have known values at the time when the line is evaluated, else an error is flagged. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Subcircuit-parameters" \end_inset Subcircuit parameters \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .subckt node node ... = = ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .subckt myfilter in out rval=100k cval=100nF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold \family default \series default is the name of the subcircuit given by the user. \family typewriter \series bold node \family default \series default is an integer number or an identifier, for one of the external nodes. The first \family typewriter \series bold = \family default \series default introduces an optional section of the line. Each \family typewriter \series bold \family default \series default is a formal parameter, and each \family typewriter \series bold \family default \series default is either a spice number or a brace expression. Inside the \begin_inset Quotes eld \end_inset \family typewriter .subckt \family default \begin_inset Quotes erd \end_inset ... \begin_inset Quotes eld \end_inset \family typewriter .ends \family default \begin_inset Quotes erd \end_inset context, each formal parameter may be used like any identifier that was defined on a .param control line. The \family typewriter \series bold \family default \series default parts are supposed to be default values of the parameters. However, in the current version of , they are not used and each invocation of the subcircuit must supply the _exact_ number of actual parameters. \end_layout \begin_layout Standard The syntax of a subcircuit call (invocation) is: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout X node node ... = = ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout X1 input output myfilter rval=1k cval=1n \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \end_layout \begin_layout Standard Here \family typewriter \series bold \family default \series default is the symbolic name given to that instance of the subcircuit, \family typewriter \series bold \family default \series default is the name of a subcircuit defined beforehand. \family typewriter \series bold node node ... \family default \series default is the list of actual nodes where the subcircuit is connected. \family typewriter \series bold \family default \series default is either a spice number or a brace expression \family typewriter \series bold { } \family default \series default . The sequence of \family typewriter \series bold \family default \series default items on the \family typewriter X \family default line must exactly match the number and the order of formal parameters of the subcircuit. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Subcircuit example with parameters: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Param-example \end_layout \begin_layout Plain Layout .param amplitude= 1V \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .subckt myfilter in out rval=100k cval=100nF \end_layout \begin_layout Plain Layout Ra in p1 {2*rval} \end_layout \begin_layout Plain Layout Rb p1 out {2*rval} \end_layout \begin_layout Plain Layout C1 p1 0 {2*cval} \end_layout \begin_layout Plain Layout Ca in p2 {cval} \end_layout \begin_layout Plain Layout Cb p2 out {cval} \end_layout \begin_layout Plain Layout R1 p2 0 {rval} \end_layout \begin_layout Plain Layout .ends myfilter \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout X1 input output myfilter rval=1k cval=1n \end_layout \begin_layout Plain Layout V1 input 0 AC {amplitude} \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Symbol scope \end_layout \begin_layout Standard \emph on All subcircuit and model names are considered global and must be unique. \emph default The \family typewriter .param \family default symbols that are defined outside of any \begin_inset Quotes eld \end_inset \family typewriter .subckt \family default \begin_inset Quotes erd \end_inset ... \begin_inset Quotes eld \end_inset \family typewriter .ends \family default \begin_inset Quotes erd \end_inset section are global. Inside such a section, the pertaining \begin_inset Quotes eld \end_inset \family typewriter params: \family default \begin_inset Quotes erd \end_inset symbols and any \family typewriter .param \family default assignments are considered local: they mask any global identical names, until the \family typewriter .ends \family default line is encountered. You cannot reassign to a global number inside a \family typewriter .subckt \family default , a local copy is created instead. Scope nesting works up to a level of 10. For example, if the main circuit calls A which has a formal parameter xx, A calls B which has a param. xx, and B calls C which also has a formal param. xx, there will be three versions of 'xx' in the symbol table but only the most local one - belonging to C - is visible. \end_layout \begin_layout Standard \series bold A word of caution: \series default Ngspice allows to define circuits with nested subcircuits. Currently it is not possible however to issue .param statements inside of a .subckt ... .ends section, when there are additional, nested .subckt ... .ends in the same section. This is a bug, which will be removed asap. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Syntax-of-expressions" \end_inset Syntax of expressions \end_layout \begin_layout Standard ( optional parts within [ ...] ): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout An expression may be one of: \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout where is either a spice number or an identifier \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout ( [ , ...] ) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout ( ) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard As expected, atoms, built-in function calls and stuff within parentheses are evaluated before the other operators. The operators are evaluated following a list of precedence close to the one of the C language. For equal precedence binary ops, evaluation goes left to right. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Operator \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Precedence \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Precedence \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unary - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ! \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unary not \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ^ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout power \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout multiply \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout / \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout divide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mod \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout % \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout modulo \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout div \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \backslash \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout integer divide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout + \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout add \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout subtract \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout == \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout equality \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout != \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout un-equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less or equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater or equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout and \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout && \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout and \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout or \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout || \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout or \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The result of logical operators is 1 or 0 , for True or False. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Built-in function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout defined \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout returns 1 if symbol is defined, else 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sqr(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sqrt(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sin(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cos(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exp(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ln(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout arctan(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout abs(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout floor(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Largest integer that is less than or equal to x \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ceil(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Smallest integer that is greater than or equal to x \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pow(x,y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout x raised to the power of y (C runtime library) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pwr(x,y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exp (y * ln (fabs (x))) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout min(x, y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout max(x, y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sgn(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 for x > 0, 0.0 for x == 0, -1.0 for x < 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ternary_fcn(x, y, z) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout x ? y : z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gauss(nom, rvar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation rvar (relative to nominal), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout agauss(nom, avar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation avar (absolute), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unif(nom, rvar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus relative variation (to nominal) uniformly distributed between +/-rvar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout aunif(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus absolute variation uniformly distributed between +/-avar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout limit(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value +/-avar, depending on random number in [-1, 1[ being > 0 or < 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The scaling suffixes (any decorative alphanumeric string may follow): \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout suffix \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout g \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout k \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout u \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout f \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-15 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Note: there are intentional redundancies in expression syntax, e.g. x^y , x**y and pwr(x,y) all have nearly the same result. \end_layout \begin_layout Subsection Reserved words \end_layout \begin_layout Standard In addition to the above function names and to the verbose operators ( not and or div mod ), other words are reserved and cannot be used as parameter names: and, or, not, div, mod, if, else, end, while, macro, funct, defined, include, for, to, downto, is, var, sqr, sqrt, sin, cos, exp, ln, arctan, abs, pwr. \end_layout \begin_layout Subsection Alternative syntax \end_layout \begin_layout Standard The & sign is tolerated to provide some \begin_inset Quotes eld \end_inset historical \begin_inset Quotes erd \end_inset parameter notation: & as the first character of a line is equivalent to: \family typewriter .param \family default . \end_layout \begin_layout Standard Inside a line, the notation \family typewriter &(....) \family default is equivalent to \family typewriter {....} \family default , and \family typewriter &identifier \family default means the same thing as \family typewriter {identifier} \family default . \end_layout \begin_layout Standard Comments in the style of C++ line trailers (//) are detected and erased. \end_layout \begin_layout Standard Warning: this is NOT possible in embedded .control parts of a source file, these lines are outside of this scope. \end_layout \begin_layout Standard Now, there is some possible confusion in ngspice because of multiple numerical expression features. The .param lines and the braces expressions (see next chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:func" \end_inset ) are evaluated in the front-end, that is, just after the subcircuit expansion. (Technically, the X lines are kept as comments in the expanded circuit so that the actual parameters can correctly be substituted). So, after the netlist expansion and before the internal data setup, all number attributes in the circuit are known constants. However, there are some circuit elements in Spice which accept arithmetic expressions that are NOT evaluated at this point, but only later during circuit analysis. These are the arbitrary current and voltage sources (B-sources, \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" \end_inset ), as well as E- and G-sources and R-, L-, or C-devices. The syntactic difference is that "compile-time" expressions are within braces, but "run-time" expressions have no braces. To make things more complicated, the back-end ngspice scripting language also accepts arithmetic/logic expressions that operate on its own scalar or vector data sets ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ). Please see also chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Parameters,-functions,-expressions," \end_inset . \end_layout \begin_layout Standard It would be desirable to have the same expression syntax, operator and function set, and precedence rules, for the three contexts mentioned above. In the current Numparam implementation, that goal is not yet achieved... \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:func" \end_inset .func \end_layout \begin_layout Standard With this line a function may be defined. The syntax of its expression is equivalent to the expression syntax from the .param line ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Syntax-of-expressions" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .func { } \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .func icos(x) {cos(x) - 1} \end_layout \begin_layout Plain Layout .func f(x,y) {x*y} \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard .func will initiate a replacement operation. After reading the input files, and before parameters are evaluated, all occurrences of the \family typewriter icos(x) \family default function will be replaced by \family typewriter cos(x)-1 \family default . All occurrences of \family typewriter f(x,y) \family default will be replaced by \family typewriter x*y \family default . Function statements may be nested to a depth of t.b.d.. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.csparam" \end_inset .csparam \end_layout \begin_layout Standard Create a constant vector (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Vectors" \end_inset ) from a parameter in plot ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Plots" \end_inset ) \begin_inset Quotes eld \end_inset const \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .csparam = \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .param pippo=5 \end_layout \begin_layout Plain Layout .param pp=6 \end_layout \begin_layout Plain Layout .csparam pippp={pippo + pp} \end_layout \begin_layout Plain Layout .param p={pp} \end_layout \begin_layout Plain Layout .csparam pap='pp+p' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In the example shown, vectors pippp, and pap are added to the constants, which already reside in plot \begin_inset Quotes eld \end_inset const \begin_inset Quotes erd \end_inset , with length one and real values. These vectors are generated during circuit parsing and thus cannot be changed later (same as with ordinary parameters). They may be used in ngspice scripts and .control sections (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Interactive-Interpreter" \end_inset ). \end_layout \begin_layout Standard The use of .csparam is still experimental and has to be tested. A simple usage is shown below. \end_layout \begin_layout LyX-Code * test csparam \end_layout \begin_layout LyX-Code .param TEMPS = 27 \end_layout \begin_layout LyX-Code .csparam newt = {3*TEMPS} \end_layout \begin_layout LyX-Code .csparam mytemp = '2 + TEMPS' \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code echo $&newt $&mytemp \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .end \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Parameters,-functions,-expressions," \end_inset Parameters, functions, expressions, and command scripts \end_layout \begin_layout Standard In ngspice there are several ways to describe functional dependencies. In fact there are three independent function parsers, being active before, during, and after the simulation. So it might be due to have a few words on their interdependence. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Parameters" \end_inset Parameters \end_layout \begin_layout Standard Parameters (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ) and functions, either defined within the \family typewriter .param \family default statement or with the \family typewriter .func \family default statement (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:func" \end_inset ) are evaluated \series bold before \series default any simulation is started, that is during the setup of the input and the circuit. Therefore these statements may not contain any simulation output (voltage or current vectors), because it is simply not yet available. The syntax is described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Syntax-of-expressions" \end_inset . During the circuit setup all functions are evaluated, all parameters are replaced by their resulting numerical values. Thus it will not be possible to get feedback from a later stage (during or after simulation) to change any of the parameters. \end_layout \begin_layout Subsection Nonlinear sources \end_layout \begin_layout Standard During the simulation, the B source (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" \end_inset ) and their associated E and G sources, as well as some devices (R, C, L) may contain expressions. These expressions may contain parameters from above (evaluated immediately upon ngspice start up), numerical data, predefined functions, but also node voltages and branch currents which are resulting from the simulation. The source or device values are continuously updated \series bold during \series default the simulation. Therefore the sources are powerful tools to define non-linear behavior, you may even create new 'devices' by yourself. Unfortunately the expression syntax (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset ) and the predefined functions may deviate from the ones for parameters listed in \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset . \end_layout \begin_layout Subsection Control commands, Command scripts \end_layout \begin_layout Standard Commands, as described in detail in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset , may be used interactively, but also as a command script enclosed in \family typewriter .control ... .endc \family default lines. The scripts may contain expressions (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ). The expressions may work upon simulation output vectors (of node voltages, branch currents), as well as upon predefined or user defined vectors and variables, and are invoked \series bold after \series default the simulation. Parameters from \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset are not allowed in these expressions. Again the expression syntax (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ) will deviate from the one for parameters or B sources listed in \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . \end_layout \begin_layout Standard If you want to use parameters from \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset inside your control script, you may apply a trick by defining a voltage source with the parameter as its value, and then have it available as a vector (e.g. after a transient simulation) with a then constant output (the parameter). A feedback from here back into parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Parameters" \end_inset ) is never possible. Also you cannot access non-linear sources of the preceding simulation. However you may start a first simulation inside your control script, then evaluate its output using expressions, change some of the element or model parameters with the \family typewriter alter \family default and \family typewriter altermod \family default statements (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Alter*:-Change-a" \end_inset ) and then automatically start a new simulation. \end_layout \begin_layout Standard Expressions and scripting are powerful tools within ngspice, and we will enhance the examples given in chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Example-Circuits" \end_inset continuously to describe these features. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Circuit-Elements-and" \end_inset Circuit Elements and Models \end_layout \begin_layout Standard Data fields that are enclosed in less-than and greater-than signs ('< >') are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any delimiter. Further, future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With respect to branch voltages and currents, ngspice uniformly uses the associated reference convention (current flows in the direction of voltage drop). \end_layout \begin_layout Section General options and information \end_layout \begin_layout Subsection Simulating more devices in parallel \end_layout \begin_layout Standard If you need to simulate more devices of the same kind in parallel, you can use the \family typewriter \series bold \begin_inset Quotes eld \end_inset m \begin_inset Quotes erd \end_inset \family default \series default (often called parallel multiplier) option which is available for all instances except transmission lines and sources (both independent and controlled). The parallel multiplier is implemented by multiplying the value of \family typewriter \series bold m \family default \series default the element's matrix stamp, thus it cannot be used to accurately simulate larger devices in integrated circuits. The netlist below show how to correctly use the parallel multiplier: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Multiple device example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout d1 2 0 mydiode m=10 \end_layout \begin_layout Plain Layout d01 1 0 mydiode \end_layout \begin_layout Plain Layout d02 1 0 mydiode \end_layout \begin_layout Plain Layout d03 1 0 mydiode \end_layout \begin_layout Plain Layout d04 1 0 mydiode \end_layout \begin_layout Plain Layout d05 1 0 mydiode \end_layout \begin_layout Plain Layout d06 1 0 mydiode \end_layout \begin_layout Plain Layout d07 1 0 mydiode \end_layout \begin_layout Plain Layout d08 1 0 mydiode \end_layout \begin_layout Plain Layout d09 1 0 mydiode \end_layout \begin_layout Plain Layout d10 1 0 mydiode \end_layout \begin_layout Plain Layout ... \end_layout \end_inset \end_layout \begin_layout Plain Layout The \family typewriter d1 \family default instance connected between nodes 2 and 0 is equivalent to the parallel \family typewriter d01-d10 \family default connected between 1 and 0. \end_layout \end_inset \end_layout \begin_layout Subsection Technology scaling \end_layout \begin_layout Standard Still to be implemented and written. \end_layout \begin_layout Subsection Model binning \end_layout \begin_layout Standard Binning is a kind of range partitioning for geometry dependent models like MOSFET's. The purpose is to cover larger geometry ranges (Width and Length) with higher accuracy then the model built-in geometry formulaes. Each size range described by the additional model parameters LMIN, LMAX, WMIN and WMAX has its own model parameter set. These model cards are defined by a number extension, like \begin_inset Quotes eld \end_inset nch.1 \begin_inset Quotes erd \end_inset . NGSPICE has a algorithm to choose the right model card by the requested W and L. \end_layout \begin_layout Standard This is implemented for BSIM3 and BSIM4 model. \end_layout \begin_layout Subsection Transistors and Diodes \end_layout \begin_layout Standard The area factor \family typewriter \series bold \begin_inset Quotes eld \end_inset m \begin_inset Quotes erd \end_inset \family default \series default (often called parallel multiplier) used on the diode, BJT, JFET, and MESFET devices determines the number of equivalent parallel devices of a specified model. The affected parameters are marked with an asterisk under the heading \begin_inset Quotes eld \end_inset area \begin_inset Quotes erd \end_inset in the model descriptions (see the various chapters on models below). Several geometric factors associated with the channel and the drain and source diffusions can be specified on the MOSFET device line. \end_layout \begin_layout Standard Two different forms of initial conditions may be specified for some devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified \family typewriter \series bold OFF \family default \series default , the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the \family typewriter \series bold OFF \family default \series default option can be used to force the solution to correspond to a desired state. If a device is specified \family typewriter \series bold OFF \family default \series default when in reality the device is conducting, the program still obtains the correct solution (assuming the solutions converge) but more iterations are required since the program must independently converge to two separate solutions. \end_layout \begin_layout Standard The \family typewriter .NODESET \family default control line (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.NODESET" \end_inset ) serves a similar purpose as the \family typewriter \series bold OFF \family default \series default option. The \family typewriter .NODESET \family default option is easier to apply and is the preferred means to aid convergence. The second form of initial conditions are specified for use with the transient analysis. These are true \begin_inset Quotes eld \end_inset initial conditions \begin_inset Quotes erd \end_inset as opposed to the convergence aids above. See the description of the \family typewriter .IC \family default control line (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.IC:-Set-Initial" \end_inset ) and the \family typewriter .TRAN \family default control line (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.TRAN:-Transient-Analysis" \end_inset ) for a detailed explanation of initial conditions. \end_layout \begin_layout Section Elementary Devices \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Resistors" \end_inset Resistors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- value \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout R1 1 2 100 \end_layout \begin_layout Plain Layout RC1 12 17 1K \end_layout \begin_layout Plain Layout R2 5 7 1K ac=2K \end_layout \begin_layout Plain Layout RL 1 4 2K m=2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Ngspice has a fairly complex model for resistors. It can simulate both discrete and semiconductor resistors. Semiconductor resistors in ngspice means: resistors described by geometrical parameters. So, do not expect detailed modeling of semiconductor effects. \family typewriter \end_layout \begin_layout Standard \family typewriter n+ \family default and \family typewriter n- \family default are the two element nodes, \family typewriter value \family default is the resistance (in ohms) and may be positive or negative \begin_inset Foot status collapsed \begin_layout Plain Layout A negative resistor modeling an active element can cause convergence problems, please avoid it. \end_layout \end_inset but not zero. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "80col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Simulating small valued resistors: If you need to simulate very small resistors (0.001 Ohm or less), you should use CCVS (transresistance), it is less efficient but improves overall numerical accuracy. Think about that a small resistance is a large conductance. \end_layout \end_inset \end_layout \begin_layout Standard Ngspice can assign a resistor instance a different value for AC analysis, specified using the \family typewriter \series bold ac \family default \series default keyword. This value must not be zero as described above. The AC resistance is used in AC analysis only (not Pole-Zero nor noise). If you do not specify the \family typewriter \series bold ac \family default \series default parameter, it is defaulted to \family typewriter \series bold value \family default \series default . If you want to simulate temperature dependence of a resistor, you need to specify its temperature coefficients, using a \family typewriter .model \family default line, like in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout RE1 1 2 800 newres dtemp=5 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MODEL newres R tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Instance temperature is useful even if resistance does not varies with it, since the thermal noise generated by a resistor depends on its absolute temperature. Resistors in ngspice generates two different noises: thermal and flicker. While thermal noise is always generated in the resistor, to add a flicker noise \begin_inset Foot status collapsed \begin_layout Plain Layout Flicker noise can be used to model carbon resistors. \end_layout \end_inset source you have to add a \family typewriter .model \family default card defining the flicker noise parameters. It is possible to simulate resistors that do not generate any kind of noise using the \family typewriter \series bold noisy \family default \series default keyword and assigning zero to it, as in the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Rmd 134 57 1.5k noisy=0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Ngspice calculates the nominal resistance as described below: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{alignedat}{1}\begin{array}{cc} R_{nom}= & \frac{{{\rm VALUE}*{\rm scale}}}{m}\\ R_{acnom}= & \frac{{{\rm ac}*{\rm scale}}}{m}\end{array}\end{alignedat} \end{equation} \end_inset \end_layout \begin_layout Standard If you are interested in temperature effects or noise equations, read the next section on semiconductor resistors. \end_layout \begin_layout Subsection Semiconductor Resistors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + m= \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout RLOAD 2 10 10K \end_layout \begin_layout Plain Layout RMOD 3 7 RMODEL L=10u W=1u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the more general form of the resistor presented before ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Resistors" \end_inset ) and allows the modeling of temperature effects and for the calculation of the actual resistance value from strictly geometric information and the specifications of the process. If \family typewriter \series bold value \family default \series default is specified, it overrides the geometric information and defines the resistance. If \family typewriter \series bold mname \family default \series default is specified, then the resistance may be calculated from the process informatio n in the model \family typewriter \series bold mname \family default \series default and the given \family typewriter \series bold length \family default \series default and \family typewriter \series bold width \family default \series default . If \family typewriter \series bold value \family default \series default is not specified, then \family typewriter \series bold mname \family default \series default and \family typewriter \series bold length \family default \series default must be specified. If \family typewriter \series bold width \family default \series default is not specified, then it is taken from the default width given in the model. \end_layout \begin_layout Standard The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line and the value specified in \family typewriter \series bold dtemp \family default \series default . \end_layout \begin_layout Subsection Semiconductor Resistor Model (R) \end_layout \begin_layout Standard The resistor model consists of process-related device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available are: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NARROW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout narrowing due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SHORT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout shortening due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-25 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The sheet resistance is used with the narrowing parameter and \family typewriter \series bold l \family default \series default and \family typewriter \series bold w \family default \series default from the resistor device to determine the nominal resistance by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R_{nom}={\rm rsh}\frac{l-{\rm SHORT}}{w-{\rm NARROW}}\end{equation} \end_inset \end_layout \begin_layout Standard \family typewriter \series bold DEFW \family default \series default is used to supply a default value for \family typewriter \series bold w \family default \series default if one is not specified for the device. If either \family typewriter \series bold rsh \family default \series default or \family typewriter \series bold l \family default \series default is not specified, then the standard default resistance value of 1 kOhm is used. \family typewriter \series bold TNOM \family default \series default is used to override the circuit-wide value given on the \family typewriter .options \family default control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R(T)=R({\rm TNOM})\Bigl(1+TC_{1}(T-{\rm TNOM})+TC_{2}(T-{\rm TNOM})^{2}\Bigr)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $R({\rm TNOM})=R_{nom}\vert R_{acnom}$ \end_inset . In the above formula, \begin_inset Quotes eld \end_inset \begin_inset Formula $T$ \end_inset \begin_inset Quotes erd \end_inset represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. If both \family typewriter \series bold temp \family default \series default and \family typewriter \series bold dtemp \family default \series default are specified, the latter is ignored. Ngspice improves spice's resistors noise model, adding flicker noise ( \begin_inset Formula $\nicefrac{1}{f}$ \end_inset ) to it and the \family typewriter \series bold noisy \family default \series default keyword to simulate noiseless resistors. The thermal noise in resistors is modeled according to the equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \bar{i_{R}^{2}}=\frac{{4kT}}{R}\Delta f\end{equation} \end_inset \end_layout \begin_layout Standard where " \begin_inset Formula $k$ \end_inset " is the Boltzmann's constant, and " \begin_inset Formula $T$ \end_inset " the instance temperature. \end_layout \begin_layout Standard Flicker noise model is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \bar{i_{Rfn}^{2}}=\frac{{\rm KF}I_{R}^{{\rm AF}}}{f}\Delta f\end{equation} \end_inset \end_layout \begin_layout Standard A small list of sheet resistances (in \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset ) for conductors is shown below. The table represents typical values for MOS processes in the 0.5 - 1 um \end_layout \begin_layout Standard range. The table is taken from: \emph on N. Weste, K. Eshraghian - Principles of CMOS VLSI Design 2nd Edition, Addison Wesley \emph default . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Min. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Typ. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Max. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inter-metal (metal1 - metal2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.007 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Top-metal (metal3) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.003 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.004 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.05 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Polysilicon (poly) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 30 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Silicide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diffusion (n+, p+) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 25 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Silicided diffusion \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n-well \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5000 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Resistors,-dependent-on" \end_inset Resistors, dependent on expressions (behavioral resistor) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- R = 'expression' \end_layout \begin_layout Plain Layout RXXXXXXX n+ n- 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). An example file is given below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file for non-linear resistor: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Non-linear resistor \end_layout \begin_layout Plain Layout .param R0=1k Vi=1 Vt=0.5 \end_layout \begin_layout Plain Layout * resistor depending on control voltage V(rr) \end_layout \begin_layout Plain Layout R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}' \end_layout \begin_layout Plain Layout * control voltage \end_layout \begin_layout Plain Layout V1 rr 0 PWL(0 0 100u {Vi}) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout tran 100n 100u uic \end_layout \begin_layout Plain Layout plot i(V1) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Capacitors" \end_inset Capacitors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CBYP 13 0 1UF \end_layout \begin_layout Plain Layout COSC 17 23 10U IC=3V \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Ngspice provides a detailed model for capacitors. Capacitors in the netlist can be specified giving their capacitance or their geometrical and physical characteristics. Following the original spice3 "convention", capacitors specified by their geometrical or physical characteristics are called "semiconductor capacitors" and are described in the next section. \end_layout \begin_layout Standard In this first form \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative element nodes, respectively and \family typewriter \series bold value \family default \series default is the capacitance in Farads. \end_layout \begin_layout Standard Capacitance can be specified in the instance line as in the examples above or in a \family typewriter .model \family default line, as in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout C1 15 5 cstd \end_layout \begin_layout Plain Layout C2 2 7 cstd \end_layout \begin_layout Plain Layout .model cstd C cap=3n \end_layout \end_inset \end_layout \begin_layout Plain Layout Both capacitors have a capacitance of 3nF. \end_layout \end_inset \end_layout \begin_layout Standard If you want to simulate temperature dependence of a capacitor, you need to specify its temperature coefficients, using a @command{.model} line, like in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CEB 1 2 1u cap1 dtemp=5 \end_layout \begin_layout Plain Layout .MODEL cap1 C tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The (optional) initial condition is the initial (time zero) value of capacitor voltage (in Volts). Note that the initial conditions (if any) apply only if the \family typewriter \series bold uic \family default \series default option is specified on the \family typewriter .tran \family default control line. \end_layout \begin_layout Standard Ngspice calculates the nominal capacitance as described below: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\rm value}*{\rm scale}}*m}\end{equation} \end_inset \end_layout \begin_layout Subsection Semiconductor Capacitors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CLOAD 2 10 10P \end_layout \begin_layout Plain Layout CMOD 3 7 CMODEL L=10u W=1u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the more general form of the Capacitor presented in section ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Capacitors" \end_inset ), and allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. If \family typewriter \series bold value \family default \series default is specified, it defines the capacitance and both process and geometrical information are discarded. If \family typewriter \series bold value \family default \series default is not specified, the capacitance is calculated from information contained model \family typewriter \series bold mname \family default \series default and the given length and width ( \family typewriter \series bold l \family default \series default , \family typewriter \series bold w \family default \series default keywords, respectively). \end_layout \begin_layout Standard It is possible to specify \family typewriter \series bold mname \family default \series default only, without geometrical dimensions and set the capacitance in the \family typewriter .model \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Capacitors" \end_inset ). \end_layout \begin_layout Subsection Semiconductor Capacitor Model (C) \end_layout \begin_layout Standard The capacitor model contains process information that may be used to compute the capacitance from strictly geometric information. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CAP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout model capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout junction bottom capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout junction sidewall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default device width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default device length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NARROW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout narrowing due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SHORT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout shortening due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout relative dielectric constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THICK \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout insulator thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-9 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The capacitor has a capacitance computed as: \end_layout \begin_layout Standard If \family typewriter \series bold value \family default \series default is specified on the instance line then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\rm value}*{\rm scale}}*m}\end{equation} \end_inset \end_layout \begin_layout Standard If model capacitance is specified then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\rm CAP}*{\rm scale}}*m}\end{equation} \end_inset \end_layout \begin_layout Standard If neither \family typewriter \series bold value \family default \series default nor \family typewriter \series bold CAP \family default \series default are specified, then geometrical and physical parameters are take into account: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} {\rm C_{0}}={\rm CJ}(l-{\rm SHORT})(w-{\rm NARROW})+2{\rm CJSW}(l-{\rm SHORT}+w-{\rm NARROW})\end{equation} \end_inset \end_layout \begin_layout Standard \family typewriter \series bold CJ \family default \series default can be explicitly given on the \family typewriter .model \family default line or calculated by physical parameters. When \family typewriter \series bold CJ \family default \series default is not given, is calculated as: \end_layout \begin_layout Standard If \family typewriter \series bold THICK \family default \series default is not zero: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{array}{cc} {\rm CJ}=\frac{{{\rm DI}*\epsilon_{0}}}{{\rm THICK}} & \mathrm{if\: DI\: is\: specified,}\\ {\rm CJ}=\frac{{\epsilon_{SiO_{2}}}}{{\rm THICK}} & \mathrm{otherwise.}\end{array}\end{equation} \end_inset \end_layout \begin_layout Standard If the relative dielectric constant is not specified the one for SiO2 is used. The values of the constants are: \begin_inset Formula $\epsilon_{0}=8.854214871e-12\frac{F}{m}$ \end_inset and \begin_inset Formula $\epsilon_{SiO_{2}}=3.4531479969e-11\frac{F}{m}$ \end_inset . The nominal capacitance is then computed as: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={C_{0}*{\rm scale}*m}\end{equation} \end_inset \end_layout \begin_layout Standard After the nominal capacitance is calculated, it is adjusted for temperature by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C(T)=C({\rm TNOM})\Bigl(1+TC_{1}(T-{\rm TNOM})+TC_{2}(T-{\rm TNOM})^{2}\Bigr)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $C({\rm TNOM})=C_{nom}$ \end_inset . \end_layout \begin_layout Standard In the above formula, \begin_inset Quotes eld \end_inset \begin_inset Formula $T$ \end_inset \begin_inset Quotes erd \end_inset represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Capacitors,-dependent-on" \end_inset Capacitors, dependent on expressions (behavioral capacitor) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- C = 'expression' \end_layout \begin_layout Plain Layout CXXXXXXX n+ n- 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout C1 cc 0 c = 'V(cc) < {Vt} ? {C1} : {Ch}' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Behavioral Capacitor \end_layout \begin_layout Plain Layout .param Cl=5n Ch=1n Vt=1m Il=100n \end_layout \begin_layout Plain Layout .ic v(cc) = 0 v(cc2) = 0 \end_layout \begin_layout Plain Layout * capacitor depending on control voltage V(cc) \end_layout \begin_layout Plain Layout C1 cc 0 c = 'V(cc) < {Vt} ? {Cl} : {Ch}' \end_layout \begin_layout Plain Layout *C1 cc 0 c ={Ch} \end_layout \begin_layout Plain Layout I1 0 1 {Il} \end_layout \begin_layout Plain Layout Exxx n1-copy n2 n2 cc2 1 \end_layout \begin_layout Plain Layout Cxxx n1-copy n2 1 \end_layout \begin_layout Plain Layout Bxxx cc2 n2 I = '(V(cc2) < {Vt} ? {Cl} : {Ch})' * i(Exxx) \end_layout \begin_layout Plain Layout I2 n2 22 {Il} \end_layout \begin_layout Plain Layout vn2 n2 0 DC 0 \end_layout \begin_layout Plain Layout * measure charge by integrating current \end_layout \begin_layout Plain Layout aint1 %id(1 cc) 2 time_count \end_layout \begin_layout Plain Layout aint2 %id(22 cc2) 3 time_count \end_layout \begin_layout Plain Layout .model time_count int(in_offset=0.0 gain=1.0 \end_layout \begin_layout Plain Layout + out_lower_limit=-1e12 out_upper_limit=1e12 \end_layout \begin_layout Plain Layout + limit_range=1e-9 out_ic=0.0) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout tran 100n 100u \end_layout \begin_layout Plain Layout plot v(2) \end_layout \begin_layout Plain Layout plot v(cc) v(cc2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Inductors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout LYYYYYYY n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout LLINK 42 69 1UH \end_layout \begin_layout Plain Layout LSHUNT 23 51 10U IC=15.7MA \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The inductor device implemented into ngspice has many enhancements over the original one. \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative element nodes, respectively. \family typewriter \series bold value \family default \series default is the inductance in Henry. Inductance can be specified in the instance line as in the examples above or in a \family typewriter .model \family default line, as in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout L1 15 5 indmod1 \end_layout \begin_layout Plain Layout L2 2 7 indmod1 \end_layout \begin_layout Plain Layout .model indmod1 L ind=3n \end_layout \end_inset Both inductors have an inductance of 3nH. \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter \series bold nt \family default \series default is used in conjunction with a \family typewriter .model \family default line, and is used to specify the number of turns of the inductor. If you want to simulate temperature dependence of an inductor, you need to specify its temperature coefficients, using a \family typewriter .model \family default line, like in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Lload 1 2 1u ind1 dtemp=5 \end_layout \begin_layout Plain Layout .MODEL ind1 L tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The (optional) initial condition is the initial (time zero) value of inductor current (in Amps) that flows from \family typewriter \series bold n+ \family default \series default , through the inductor, to \family typewriter \series bold n- \family default \series default . Note that the initial conditions (if any) apply only if the \family typewriter \series bold UIC \family default \series default option is specified on the \family typewriter .tran \family default analysis line. \end_layout \begin_layout Standard Ngspice calculates the nominal inductance as described below: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\rm value}*{\rm scale}}}{m}\end{equation} \end_inset \end_layout \begin_layout Subsection Inductor model \end_layout \begin_layout Standard The inductor model contains physical and geometrical information that may be used to compute the inductance of some common topologies like solenoids and toroids, wound in air or other material with constant magnetic permeability. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IND \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout model inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $H$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSECT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cross section \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m^{2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout number of turns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MU \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout relative magnetic permeability \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The inductor has an inductance computed as: \end_layout \begin_layout Standard If \family typewriter \series bold value \family default \series default is specified on the instance line then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\rm value}*{\rm scale}}}{m}\end{equation} \end_inset \end_layout \begin_layout Standard If model inductance is specified then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\rm IND}*{\rm scale}}}{m}\end{equation} \end_inset \end_layout \begin_layout Standard If neither \family typewriter \series bold value \family default \series default nor \family typewriter \series bold IND \family default \series default are specified, then geometrical and physical parameters are take into account. In the following formulas \end_layout \begin_layout Standard \family typewriter \series bold NT \family default \series default refers to both instance and model parameter (instance parameter overrides model parameter): \end_layout \begin_layout Standard If \family typewriter \series bold LENGTH \family default \series default is not zero: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{cases} L_{nom}=\frac{{{\rm MU}*\mu_{0}*{\rm NT}^{2}*{\rm CSECT}}}{{\rm LENGTH}} & \mathrm{if\:}{\rm MU\mathrm{\: is\: specified,}}\\ L_{nom}=\frac{{\mu_{0}*{\rm NT}^{2}*{\rm CSECT}}}{{\rm LENGTH}} & \mathrm{otherwise.}\end{cases}\end{equation} \end_inset \end_layout \begin_layout Standard with: \begin_inset Formula $\mu_{0}=1.25663706143592e-6\frac{H}{m}$ \end_inset . After the nominal inductance is calculated, it is adjusted for temperature by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L(T)=L({\rm TNOM})\Bigl(1+TC_{1}(T-{\rm TNOM})+TC_{2}(T-{\rm TNOM})^{2}\Bigr)\end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $L({\rm TNOM})=L_{nom}$ \end_inset . In the above formula, \begin_inset Quotes eld \end_inset \begin_inset Formula $T$ \end_inset \begin_inset Quotes erd \end_inset represents the instance temperature, which can be explicitly using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. \end_layout \begin_layout Subsection Coupled (Mutual) Inductors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout KXXXXXXX LYYYYYYY LZZZZZZZ value \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout K43 LAA LBB 0.999 \end_layout \begin_layout Plain Layout KXFRMR L1 L2 0.87 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and \family typewriter \series bold value \family default \series default is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the \begin_inset Quotes eld \end_inset dot \begin_inset Quotes erd \end_inset convention, place a \begin_inset Quotes eld \end_inset dot \begin_inset Quotes erd \end_inset on the first node of each inductor. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Inductors,-dependent-on" \end_inset Inductors, dependent on expressions (behavioral inductor) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout LXXXXXXX n+ n- L = 'expression' \end_layout \begin_layout Plain Layout LXXXXXXX n+ n- 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Variable inductor \end_layout \begin_layout Plain Layout .param Ll=0.5m Lh=5m It=50u Vi=2m \end_layout \begin_layout Plain Layout .ic v(int21) = 0 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * variable inductor depending on control current i(Vm) \end_layout \begin_layout Plain Layout L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}' \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm lll 0 dc 0 \end_layout \begin_layout Plain Layout * voltage on inductor \end_layout \begin_layout Plain Layout V1 l2 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * fixed inductor \end_layout \begin_layout Plain Layout L3 33 331 {Ll} \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm33 331 0 dc 0 \end_layout \begin_layout Plain Layout * voltage on inductor \end_layout \begin_layout Plain Layout V3 33 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * non linear inductor (discrete setup) \end_layout \begin_layout Plain Layout F21 int21 0 B21 -1 \end_layout \begin_layout Plain Layout L21 int21 0 1 \end_layout \begin_layout Plain Layout B21 n1 n2 V = '(i(Vm21) < {It} ? {Ll} : {Lh})' * v(int21) \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm21 n2 0 dc 0 \end_layout \begin_layout Plain Layout V21 n1 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout tran 1u 100u uic \end_layout \begin_layout Plain Layout plot i(Vm) i(vm33) \end_layout \begin_layout Plain Layout plot i(vm21) i(vm33) \end_layout \begin_layout Plain Layout plot i(vm)-i(vm21) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Capacitor or inductor with initial conditions \end_layout \begin_layout Standard The simulator supports the specification of voltage and current initial conditions on capacitor and inductor models, respectively. \series bold These models are not the standard ones supplied with SPICE3, but are in fact code models which can be substituted for the SPICE models when realistic initial conditions are required \series default . For details please refer to chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset . A XSPICE deck example using these models is shown below: \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code * This circuit contains a capacitor and an inductor with \end_layout \begin_layout LyX-Code * initial conditions on them. Each of the components \end_layout \begin_layout LyX-Code * has a parallel resistor so that an exponential decay \end_layout \begin_layout LyX-Code * of the initial condition occurs with a time constant of \end_layout \begin_layout LyX-Code * 1 second. \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code a1 1 0 cap \end_layout \begin_layout LyX-Code .model cap capacitor (c=1000uf ic=1) \end_layout \begin_layout LyX-Code r1 1 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code a2 2 0 ind \end_layout \begin_layout LyX-Code .model ind inductor (l=1H ic=1) \end_layout \begin_layout LyX-Code r2 2 0 1.0 \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code tran 0.01 3 \end_layout \begin_layout LyX-Code plot v(1) v(2) \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .end \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Switches \end_layout \begin_layout Standard Two types of switches are available: a voltage controlled switch (type SXXXXXX, model SW) and a current controlled switch (type WXXXXXXX, model CSW). A switching hysteresis may be defined, as well as on- and off-resistances ( \begin_inset Formula $0 \end_layout \begin_layout Plain Layout WYYYYYYY N+ N- VNAM MODEL \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout s1 1 2 3 4 switch1 ON \end_layout \begin_layout Plain Layout s2 5 6 3 0 sm2 off \end_layout \begin_layout Plain Layout Switch1 1 2 10 0 smodel1 \end_layout \begin_layout Plain Layout w1 1 2 vclock switchmod1 \end_layout \begin_layout Plain Layout W2 3 0 vramp sm1 ON \end_layout \begin_layout Plain Layout wreset 5 6 vclck lossyswitch OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model name is mandatory while the initial conditions are optional. For the voltage controlled switch, nodes 3 and 4 are the positive and negative controlling nodes respectively. For the current controlled switch, the controlling current is that through the specified voltage source. The direction of positive controlling current flow is from the positive node, through the source, to the negative node. \end_layout \begin_layout Standard The instance parameters ON or OFF are required, when the controlling voltage (current) starts inside the range of the hysteresis loop (different outputs during forward vs. backward voltage or current ramp). Then ON or OFF determine the initial state of the switch. \end_layout \begin_layout Subsection Switch Model (SW/CSW) \end_layout \begin_layout Standard The switch model allows an almost ideal switch to be described in ngspice. The switch is not quite ideal, in that the resistance can not change from 0 to infinity, but must always have a finite positive value. By proper selection of the on and off resistances, they can be effectively zero and infinity in comparison to other circuit elements. The parameters available are: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Switch model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout threshold voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout threshold current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hysteresis voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hysteresis current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RON \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout on resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW,CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ROFF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout off resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e+12 (*) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW,CSW \end_layout \end_inset \end_inset \end_layout \begin_layout Standard (*) Or \begin_inset Formula $1/GMIN$ \end_inset , if you have set \begin_inset Formula $GMIN$ \end_inset to any other value, see the \family typewriter .OPTIONS \family default control line ( \begin_inset CommandInset ref LatexCommand ref reference "sub:DC-Solution-Options" \end_inset ) for a description of \begin_inset Formula $GMIN$ \end_inset , its default value results in an off-resistance of 1.0e+12 ohms. \end_layout \begin_layout Standard The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch changing state can cause numerical round-off or tolerance problems leading to erroneous results or time step difficulties. The user of switches can improve the situation by taking the following steps: \end_layout \begin_layout Itemize First, it is wise to set ideal switch impedances just high or low enough to be negligible with respect to other circuit elements. Using switch impedances that are close to "ideal" in all cases aggravates the problem of discontinuities mentioned above. Of course, when modeling real devices such as MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the device being modeled. \end_layout \begin_layout Itemize If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON >1e+12), then the tolerance on errors allowed during transient analysis should be decreased by using the \family typewriter .OPTIONS \family default control line and specifying \family typewriter \series bold TRTOL \family default \series default to be less than the default value of 7.0. \end_layout \begin_layout Itemize When switches are placed around capacitors, then the option \family typewriter \series bold CHGTOL \family default \series default should also be reduced. Suggested values for these two options are 1.0 and 1e-16 respectively. These changes inform ngspice to be more careful around the switch points so that no errors are made due to the rapid change in the circuit. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Switch test \end_layout \begin_layout Plain Layout .tran 2us 5ms \end_layout \begin_layout Plain Layout *switch control voltage \end_layout \begin_layout Plain Layout v1 1 0 DC 0.0 PWL(0 0 2e-3 2 4e-3 0) \end_layout \begin_layout Plain Layout *switch control voltage starting inside hysteresis window \end_layout \begin_layout Plain Layout *please note influence of instance parameters ON, OFF \end_layout \begin_layout Plain Layout v2 2 0 DC 0.0 PWL(0 0.9 2e-3 2 4e-3 0.4) \end_layout \begin_layout Plain Layout *switch control current \end_layout \begin_layout Plain Layout i3 3 0 DC 0.0 PWL(0 0 2e-3 2m 4e-3 0) $ <--- switch control current \end_layout \begin_layout Plain Layout *load voltage \end_layout \begin_layout Plain Layout v4 4 0 DC 2.0 \end_layout \begin_layout Plain Layout *input load for current source i3 \end_layout \begin_layout Plain Layout r3 3 33 10k \end_layout \begin_layout Plain Layout vm3 33 0 dc 0 $ <--- measure the current \end_layout \begin_layout Plain Layout * ouput load resistors \end_layout \begin_layout Plain Layout r10 4 10 10k \end_layout \begin_layout Plain Layout r20 4 20 10k \end_layout \begin_layout Plain Layout r30 4 30 10k \end_layout \begin_layout Plain Layout r40 4 40 10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout s1 10 0 1 0 switch1 OFF \end_layout \begin_layout Plain Layout s2 20 0 2 0 switch1 OFF \end_layout \begin_layout Plain Layout s3 30 0 2 0 switch1 ON \end_layout \begin_layout Plain Layout .model switch1 sw vt=1 vh=0.2 ron=1 roff=10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout w1 40 0 vm3 wswitch1 off \end_layout \begin_layout Plain Layout .model wswitch1 csw it=1m ih=0.2m ron=1 roff=10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot v(1) v(10) \end_layout \begin_layout Plain Layout plot v(10) vs v(1) $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(2) v(20) $ <--- different initial values \end_layout \begin_layout Plain Layout plot v(20) vs v(2) $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(2) v(30) $ <--- different initial values \end_layout \begin_layout Plain Layout plot v(30) vs v(2) $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(40) vs vm3#branch $ <--- current controlled switch hysteresis \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter Voltage and Current Sources \end_layout \begin_layout Section Independent Sources for Voltage or Current \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VXXXXXXX N+ N- < DC/TRAN VALUE> >> \end_layout \begin_layout Plain Layout + >> >> \end_layout \begin_layout Plain Layout IYYYYYYY N+ N- < DC/TRAN VALUE> >> \end_layout \begin_layout Plain Layout + >> >> \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VCC 10 0 DC 6 \end_layout \begin_layout Plain Layout VIN 13 2 0.001 AC 1 SIN(0 1 1MEG) \end_layout \begin_layout Plain Layout ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K) \end_layout \begin_layout Plain Layout VMEAS 12 9 \end_layout \begin_layout Plain Layout VCARRIER 1 0 DISTOF1 0.1 -90.0 \end_layout \begin_layout Plain Layout VMODULATOR 2 0 DISTOF2 0.01 \end_layout \begin_layout Plain Layout IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value forces current to flow out of the \family typewriter \series bold n+ \family default \series default node, through the source, and into the \family typewriter \series bold n- \family default \series default node. Voltage sources, in addition to being used for circuit excitation, are the \begin_inset Quotes eld \end_inset ammeters \begin_inset Quotes erd \end_inset for ngspice, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They of course have no effect on circuit operation since they represent short-circuits. \end_layout \begin_layout Standard \family typewriter \series bold DC \family default \series default / \family typewriter \series bold TRAN \family default \series default is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC. \end_layout \begin_layout Standard \family typewriter \series bold ACMAG \family default \series default is the ac magnitude and \family typewriter \series bold ACPHASE \family default \series default is the ac phase. The source is set to this value in the ac analysis. If \family typewriter \series bold ACMAG \family default \series default is omitted following the keyword \family typewriter \series bold AC \family default \series default , a value of unity is assumed. If \family typewriter \series bold ACPHASE \family default \series default is omitted, a value of zero is assumed. If the source is not an ac small-signal input, the keyword \family typewriter \series bold AC \family default \series default and the ac values are omitted. \end_layout \begin_layout Standard \family typewriter \series bold DISTOF1 \family default \series default and \family typewriter \series bold DISTOF2 \family default \series default are the keywords that specify that the independent source has distortion inputs at the frequencies \family typewriter \series bold F1 \family default \series default and \family typewriter \series bold F2 \family default \series default respectively (see the description of the \family typewriter .DISTO \family default control line). The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively. \end_layout \begin_layout Standard Any independent source can be assigned a time-dependent value for transient analysis. If a source is assigned a time-dependent value, the time-zero value is used for dc analysis. There are eight independent source functions: \end_layout \begin_layout Itemize pulse, \end_layout \begin_layout Itemize exponential, \end_layout \begin_layout Itemize sinusoidal, \end_layout \begin_layout Itemize piece-wise linear, \end_layout \begin_layout Itemize single-frequency FM \end_layout \begin_layout Itemize AM \end_layout \begin_layout Itemize transient noise \end_layout \begin_layout Itemize and random voltages or currents. \end_layout \begin_layout Standard If parameters other than source values are omitted or set to zero, the default values shown are assumed. ( \family typewriter \series bold TSTEP \family default \series default is the printing increment and \family typewriter \series bold TSTOP \family default \series default is the final time (see the \family typewriter .TRAN \family default control line for explanation)). \end_layout \begin_layout Subsection Pulse \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout PULSE(V1 V2 TD TR TF PW PER) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pulsed value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Rise time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fall time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pulse width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PER \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Period \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \end_inset \end_layout \begin_layout Standard A single pulse so specified is described by the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR+PW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR+PW+TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Intermediate points are determined by linear interpolation. \end_layout \begin_layout Subsection Sinusoidal \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout SIN(VO VA FREQ TD THETA) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VIN 3 0 SIN(0 1 100MEG 1NS 1E10) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FREQ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Damping factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{sec}$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V\left(t\right)=\begin{cases} V0 & \mathrm{if\;0\leq t} \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pulsed value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rise delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAU1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rise time constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fall delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD1+TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAU2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fall time constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following formula: \end_layout \begin_layout Standard Let \begin_inset Formula $V21=V2-V1\; V12=V1-V2$ \end_inset : \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V\left(t\right)=\begin{cases} V1 & \mathrm{if}\;0\leq t) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7) r=0 td=15NS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Each pair of values ( \begin_inset Formula $T_{i}$ \end_inset , \begin_inset Formula $V_{i}$ \end_inset ) specifies that the value of the source is \begin_inset Formula $V_{i}$ \end_inset (in Volts or Amps) at time = \begin_inset Formula $T_{i}$ \end_inset . The value of the source at intermediate values of time is determined by using linear interpolation on the input values. The parameter r determines a repeat time point. If r is not given, the whole sequence of values ( \begin_inset Formula $T_{i}$ \end_inset , \begin_inset Formula $V_{i}$ \end_inset ) is issued once, then the output stays at its final value. If \shape italic r = 0 \shape default , the whole sequence from \shape italic time = 0 \shape default to \shape italic time = Tn \shape default is repeated forever. If \shape italic r = 10ns \shape default , the sequence between 10ns and 50ns is repeated forever. the r value has to be one of the time points T1 to Tn of the PWL sequence. If td is given, the whole PWL sequence is delayed by a delay time \shape italic time = td \shape default . The current source still needs to be patched, td and r are not yet available. \end_layout \begin_layout Subsection Single-Frequency FM \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout SFFM(VO VA FC MDI FS) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout V1 12 0 SFFM(0 1M 20K 5 1K) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MDI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation index \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Signal frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V(t)=V_{O}+V_{A}\sin\left(2\pi FCt+MDI\sin\left(2\pi FSt\right)\right)\end{equation} \end_inset \end_layout \begin_layout Subsection Amplitude modulated source (AM) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout AM(VA VO MF FC TD) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout V1 12 0 AM(0.5 1 20K 5MEG 1m) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulating frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Signal delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $s$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V(t)=V_{A}*\left(VO+\sin\left(2\pi MFt\right)\right)*\sin\left(2\pi FCt\right)\end{equation} \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Transient-noise-source" \end_inset Transient noise source \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout TRNOISE(NA NT NALPHA NAMP RTSAM RTSCAPT RTSEMT) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VNoiw 1 0 DC 0 TRNOISE(20n 0.5n 0 0) $ white \end_layout \begin_layout Plain Layout VNoi1of 1 0 DC 0 TRNOISE(0 10p 1.1 12p) $ 1/f \end_layout \begin_layout Plain Layout VNoiw1of 1 0 DC 0 TRNOISE(20 10p 1.1 12p) $ white and 1/f \end_layout \begin_layout Plain Layout IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) $ white, 1/f, RTS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Transient noise is an experimental feature allowing (low frequency) transient noise injection and analysis. See chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:Transient-noise-analysis" \end_inset for a detailed description. NA is the Gaussian noise rms voltage amplitude, NT is the time between sample values (breakpoints will be enforced on multiples of this value). NALPHA (exponent to the frequency dependency), NAMP (rms voltage or current amplitude) are the parameters for 1/f noise, RTSAM the random telegraph signal amplitude, RTSCAPT the mean of the exponential distribution of the trap capture time, and RTSEMT its emission time mean. White Gaussian, 1/f, and RTS noise may be combined into a single statement. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Rms noise amplitude (Gaussian) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Time step \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NALPHA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1/f exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $0<\alpha<2$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NAMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude (1/f) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSCAPT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Trap capture time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSEMT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Trap emission time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard If you set NT and RTSAM to 0, the noise option TRNOISE ... is ignored. Thus you may switch off the noise contribution of an individual voltage source VNOI by the command \end_layout \begin_layout Standard \family typewriter alter @vnoi[trnoise] = [ 0 0 0 0 ] $ no noise \end_layout \begin_layout Standard \family typewriter alter @vrts[trnoise] = [ 0 0 0 0 0 0 0] $ no noise \end_layout \begin_layout Standard See chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Alter*:-Change-a" \end_inset for the alter command. \end_layout \begin_layout Standard You may switch off all TRNOISE noise sources by setting \end_layout \begin_layout Standard \family typewriter set notrnoise \end_layout \begin_layout Standard to your .spiceinit file (for all your simulations) or into your control section in front of the next run or tran command (for this specific and all following simulations). The command \end_layout \begin_layout Standard \family typewriter unset notrnoise \end_layout \begin_layout Standard will reinstate all noise sources. \end_layout \begin_layout Standard The noise generators are implemented into the independent \series bold voltage \series default (vsrc) and \series bold current \series default (isrc) sources. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Random-voltage-source" \end_inset Random voltage source \end_layout \begin_layout Standard The TRRANDOM option yields statistically distributed voltage values, derived from the ngspice random number generator. These values may be used in the transient simulation directly within a circuit, e.g. for generating a specific noise voltage, but especially they may be used in the control of behavioral sources (B, E, G sources \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" \end_inset , voltage controllable A sources \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset , capacitors \begin_inset CommandInset ref LatexCommand ref reference "sub:Capacitors,-dependent-on" \end_inset , inductors \begin_inset CommandInset ref LatexCommand ref reference "sub:Inductors,-dependent-on" \end_inset , or resistors \begin_inset CommandInset ref LatexCommand ref reference "sub:Resistors,-dependent-on" \end_inset ) to simulate the circuit dependence on statistically varying device parameters. A Monte-Carlo simulation may thus be handled in a single simulation run. \end_layout \begin_layout Standard General Form: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout TRRANDOM(TYPE TS >>) \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout VR1 r1 0 dc 0 trrandom (2 10m 0 1) $ Gaussian \end_layout \end_inset \end_layout \begin_layout Standard TYPE determines the random variates generated: 1 is uniformly distributed, 2 Gaussian, 3 exponential, 4 Poisson. TS is the duration of an individual voltage value. TD is a time delay with 0 V output before the random volage values start up. PARAM1 and PARAM2 depend on the type selected. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout TYPE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniform \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Range \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gaussian \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Standard Dev. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Exponential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Poisson \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lambda \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Arbitrary Phase Sources \end_layout \begin_layout Standard The XSPICE option supports arbitrary phase independent sources that output at TIME=0.0 a value corresponding to some specified phase shift. Other versions of SPICE use the TD (delay time) parameter to set phase-shifted sources to their time-zero value until the delay time has elapsed. The XSPICE phase parameter is specified in degrees and is included after the SPICE3 parameters normally used to specify an independent source. Partial XSPICE deck examples of usage for pulse and sine waveforms are shown below: \end_layout \begin_layout LyX-Code * Phase shift is specified after Berkeley defined parameters \end_layout \begin_layout LyX-Code * on the independent source cards. Phase shift for both of the \end_layout \begin_layout LyX-Code * following is specified as +45 degrees \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code v1 1 0 0.0 sin(0 1 1k 0 0 45.0) \end_layout \begin_layout LyX-Code r1 1 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0) \end_layout \begin_layout LyX-Code r2 2 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout Section Linear Dependent Sources \end_layout \begin_layout Standard Ngspice allows circuits to contain linear dependent sources characterized by any of the four equations \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $i=gv$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $v=ev$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $i=fi$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $v=hi$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $g$ \end_inset , \begin_inset Formula $e$ \end_inset , \begin_inset Formula $f$ \end_inset , and \begin_inset Formula $h$ \end_inset are constants representing transconductance, voltage gain, current gain, and transresistance, respectively. Non-linear dependent sources for voltages or currents (B, E, G) are described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" \end_inset . \end_layout \begin_layout Subsection Linear Voltage-Controlled Current Sources (VCCS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX N+ N- NC+ NC- VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout G1 2 0 5 0 0.1MMHO \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative \end_layout \begin_layout Standard node. \family typewriter \series bold nc+ \family default \series default and \family typewriter \series bold nc- \family default \series default are the positive and negative controlling nodes, respectively. \family typewriter \series bold value \family default \series default is the transconductance (in mhos). \end_layout \begin_layout Subsection Linear Voltage-Controlled Voltage Sources (VCVS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX N+ N- NC+ NC- VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout E1 2 3 14 1 2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default is the positive node, and \family typewriter \series bold n- \family default \series default is the negative node. \family typewriter \series bold nc+ \family default \series default and \family typewriter \series bold nc- \family default \series default are the positive and negative controlling nodes, respectively. \family typewriter \series bold value \family default \series default is the \end_layout \begin_layout Standard voltage gain. \end_layout \begin_layout Subsection Linear Current-Controlled Current Sources (CCCS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout FXXXXXXX N+ N- VNAM VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout F1 13 5 VSENS 5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. \family typewriter \series bold vnam \family default \series default is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of \family typewriter \series bold vnam \family default \series default . \family typewriter \series bold value \family default \series default is the current gain. \end_layout \begin_layout Subsection Linear Current-Controlled Voltage Sources (CCVS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout HXXXXXXX n+ n- vnam value \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout HX 5 17 VZ 0.5K \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. \family typewriter \series bold vnam \family default \series default is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of \family typewriter \series bold vnam \family default \series default . \family typewriter \series bold value \family default \series default is the transresistance (in ohms). \end_layout \begin_layout Subsection Polynomial Source Compatibility \end_layout \begin_layout Standard Dependent polynomial sources available in SPICE2G6 are fully supported in ngspice using the XSPICE extension. Dependent polynomial sources are not supported in SPICE3 but were reinstated in XSPICE to allow existing third party models to be incorporated readily into XSPICE. The form used to specify these sources is shown in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Dependent-Polynomial-Sources" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Dependent Polynomial Sources \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Source Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Instance Card \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL VCVS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none EXXXXXXX N+ N- (POLY (ND)) NC1+ NC1- P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL VCCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none GXXXXXXX N+ N- (POLY (ND)) NC1+ NC1- P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL CCCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none FXXXXXXX N+ N- (POLY (ND)) VNAM1 !VNAM2...? P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL CCVS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none HXXXXXXX N+ N- (POLY (ND)) VNAM1 !VNAM2...? P0 (P1...) \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Dependent-Polynomial-Sources" \end_inset Dependent Polynomial Sources \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "sec:Non-linear-Dependent-Sources" \end_inset Non-linear Dependent Sources (Behavioral Sources) \end_layout \begin_layout Standard The non-linear dependent sources B ( see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset ), E (see \begin_inset CommandInset ref LatexCommand ref reference "sec:E-source-(non-linear" \end_inset ), G see ( \begin_inset CommandInset ref LatexCommand ref reference "sec:G-source-(non-linear" \end_inset ) described in this chapter allow to generate voltages or currents which result from evaluating a mathematical expression. Internally E and G sources are converted to the more general B source. All three sources may be used to introduce behavioral modeling and analysis. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:B-source-(ASRC)" \end_inset B source (ASRC) \end_layout \begin_layout Subsection Syntax and usage \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout BXXXXXXX n+ n- \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout B1 0 1 I=cos(v(1))+sin(v(2)) \end_layout \begin_layout Plain Layout B2 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1) \end_layout \begin_layout Plain Layout B3 3 4 I=17 \end_layout \begin_layout Plain Layout B4 3 4 V=exp(pi^i(vdd)) \end_layout \begin_layout Plain Layout B5 2 0 V = V(1) < {Vlow} ? {Vlow} : V(1) > {Vhigh} ? {Vhigh} : V(1) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default is the positive node, and \family typewriter \series bold n- \family default \series default is the negative node. The values of the \family typewriter \series bold V \family default \series default and \family typewriter \series bold I \family default \series default parameters determine the voltages and currents across and through the device, respectively. If \family typewriter \series bold I \family default \series default is given then the device is a current source, and if \family typewriter \series bold V \family default \series default is given the device is a voltage source. One and only one of these parameters must be given. \end_layout \begin_layout Standard The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point. The expressions given for \family typewriter \series bold V \family default \series default and \family typewriter \series bold I \family default \series default may be any function of voltages and currents through voltage sources in the system. In addition, the variables \series bold 'time' \series default and \series bold 'temper' \series default are available in a transient analysis, reflecting the actual simulation time and circuit temperature. The variable \series bold 'hertz' \series default is available in an AC analysis. \series bold 'time' \series default is zero in the AC analysis, \series bold 'hertz' \series default is zero during transient analysis. Using the variable \series bold 'hertz' \series default may cost some CPU time if you have a large circuit, because for each frequency the operating point has to be determined before calculating the AC response. \end_layout \begin_layout Standard The following functions of a single real variable are defined: \end_layout \begin_layout Description Trigonometric \begin_inset space ~ \end_inset functions: cos, sin, tan, acos, asin, atan \end_layout \begin_layout Description Hyperbolic \begin_inset space ~ \end_inset functions: cosh, sinh, acosh, asinh, atanh \end_layout \begin_layout Description Exponential \begin_inset space ~ \end_inset and \begin_inset space ~ \end_inset logarithmic: exp, ln, log \end_layout \begin_layout Description Other: abs, sqrt, u, u2, uramp, floor, ceil \end_layout \begin_layout Description Functions of two variables are: min, max, pow \end_layout \begin_layout Description Functions of three variables are: a ? b:c \end_layout \begin_layout Standard The function \begin_inset Quotes eld \end_inset u \begin_inset Quotes erd \end_inset is the unit step function, with a value of one for arguments greater than zero and a value of zero for arguments less than zero. The function \begin_inset Quotes eld \end_inset u2 \begin_inset Quotes erd \end_inset returns a value of zero for arguments less than zero, one for arguments greater than one and assumes the value of the argument between these limits. The function "uramp" is the integral of the unit step: for an input x, the value is zero if x is less than zero, or if x is greater than zero the value is x. These three functions are useful in synthesizing piece-wise non-linear functions, though convergence may be adversely affected. \end_layout \begin_layout Standard The following standard operators are defined: +, -, *, /, ^, unary - \end_layout \begin_layout Standard Logical operators are !=, <>, >=, <=, ==, >, <, ||, &&, ! . \end_layout \begin_layout Standard A ternary function is defined as \family typewriter a ? b : c \family default , which means \family typewriter IF a, THEN b, ELSE c \family default . Be sure to place a space in front of '?' to allow the parser distinguishing it from other tokens. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: Ternary function \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * B source test Clamped voltage source \end_layout \begin_layout Plain Layout * C. P. Basso "Switched-mode power supplies", New York, 2008 \end_layout \begin_layout Plain Layout .param Vhigh = 4.6 \end_layout \begin_layout Plain Layout .param Vlow = 0.4 \end_layout \begin_layout Plain Layout Vin1 1 0 DC 0 PWL(0 0 1u 5) \end_layout \begin_layout Plain Layout Bcl 2 0 V = V(1) < Vlow ? Vlow : V(1) > Vhigh ? Vhigh : V(1) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout tran 5n 1u \end_layout \begin_layout Plain Layout plot V(2) vs V(1) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is used. If a divisor becomes zero or the argument of log or ln becomes zero, an error will result. Other problems may occur when the argument for a function in a partial derivative enters a region where that function is undefined. \end_layout \begin_layout Standard Parameters may be used like {Vlow} shown in the example above. Parameters will be evaluated upon set up of the circuit, vectors like V(1) will be evaluated during the simulation. \end_layout \begin_layout Standard To get time into the expression you can integrate the current from a constant current source with a capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor). \end_layout \begin_layout Standard Non-linear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent source. Nonlinear resistors, capacitors and inductors are implemented with their linear counterparts by a change of variables implemented with the nonlinear dependent source. The following subcircuit will implement a nonlinear capacitor: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: Non linear capacitor \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .Subckt nlcap pos neg \end_layout \begin_layout Plain Layout * Bx: calculate f(input voltage) \end_layout \begin_layout Plain Layout Bx 1 0 v = f(v(pos,neg)) \end_layout \begin_layout Plain Layout * Cx: linear capacitance \end_layout \begin_layout Plain Layout Cx 2 0 1 \end_layout \begin_layout Plain Layout * Vx: Ammeter to measure current into the capacitor \end_layout \begin_layout Plain Layout Vx 2 1 DC 0Volts \end_layout \begin_layout Plain Layout * Drive the current through Cx back into the circuit \end_layout \begin_layout Plain Layout Fx pos neg Vx 1 \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example for f(v(pos,neg)): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Bx 1 0 V = v(pos,neg)*v(pos,neg) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Non-linear resistors or inductors may be described in a similar manner. An example for a nonlinear resistor using this template is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: Non linear resistor \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * use of 'hertz' variable in nonlinear resistor \end_layout \begin_layout Plain Layout *.param rbase=1k \end_layout \begin_layout Plain Layout * some tests \end_layout \begin_layout Plain Layout B1 1 0 V = hertz*v(33) \end_layout \begin_layout Plain Layout B2 2 0 V = v(33)*hertz \end_layout \begin_layout Plain Layout b3 3 0 V = 6.283e3/(hertz+6.283e3)*v(33) \end_layout \begin_layout Plain Layout V1 33 0 DC 0 AC 1 \end_layout \begin_layout Plain Layout *** Translate R1 10 0 R='1k/sqrt(HERTZ)' to B source *** \end_layout \begin_layout Plain Layout .Subckt nlres pos neg rb=rbase \end_layout \begin_layout Plain Layout * Bx: calculate f(input voltage) \end_layout \begin_layout Plain Layout Bx 1 0 v = -1 / {rb} / sqrt(HERTZ) * v(pos, neg) \end_layout \begin_layout Plain Layout * Rx: linear resistance \end_layout \begin_layout Plain Layout Rx 2 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: Non linear resistor (continued) \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Vx: Ammeter to measure current into the resistor \end_layout \begin_layout Plain Layout Vx 2 1 DC 0Volts \end_layout \begin_layout Plain Layout * Drive the current through Rx back into the circuit \end_layout \begin_layout Plain Layout Fx pos neg Vx 1 \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout Xres 33 10 nlres rb=1k \end_layout \begin_layout Plain Layout *Rres 33 10 1k \end_layout \begin_layout Plain Layout Vres 10 0 DC 0 \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout define check(a,b) vecmax(abs(a - b)) \end_layout \begin_layout Plain Layout ac lin 10 100 1k \end_layout \begin_layout Plain Layout * some checks \end_layout \begin_layout Plain Layout print v(1) v(2) v(3) \end_layout \begin_layout Plain Layout if check(v(1), frequency) < 1e-12 \end_layout \begin_layout Plain Layout echo "INFO: ok" \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot vres#branch \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection par('expression') \end_layout \begin_layout Standard The B source syntax may also be used in output lines like \family typewriter .plot \family default as algebraic expressions for output (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:PiecewiseLinearFunction:-pwl" \end_inset Piecewise \begin_inset space ~ \end_inset Linear \begin_inset space ~ \end_inset Function: pwl \end_layout \begin_layout Standard Both B source types may contain a piece-wise linear dependency of one network variable: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: pwl_current \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Bdio 1 0 I = pwl(v(A), 0,0, 33,10m, 100,33m, 200,50m) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard v(A) is the independent variable x. Each pair of values following describes the x,y functional relation: In this example at node A voltage of 0V the current of 0A is generated - next pair gives 10mA flowing from ground to node 1 at 33V on node A and so forth. \end_layout \begin_layout Standard The same is possible for voltage sources: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: pwl_voltage \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Blimit b 0 V = pwl(v(1), -4,0, -2,2, 2,4, 4,5, 6,5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Monotony of the independent variable in the pwl definition is checked - non-monotonic x entries will stop the program execution. v(1) may be replaced by a controlling current source. v(1) may also be replaced by an expression, e.g. -2*i(Vin). The value pairs may also be parameters, which have to be defined before by a \family typewriter .param \family default statement. An example for the pwl function using all of these options is shown below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: pwl function in B source \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Demonstrates usage of the pwl function in an B source (ASRC) \end_layout \begin_layout Plain Layout * Also emulates the TABLE function with limits \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .param x0=-4 y0=0 \end_layout \begin_layout Plain Layout .param x1=-2 y1=2 \end_layout \begin_layout Plain Layout .param x2=2 y2=-2 \end_layout \begin_layout Plain Layout .param x3=4 y3=1 \end_layout \begin_layout Plain Layout .param xx0=x0-1 \end_layout \begin_layout Plain Layout .param xx3=x3+1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Vin 1 0 DC=0V \end_layout \begin_layout Plain Layout R 1 0 2 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * no limits outside of the tabulated x values (continues linearily) \end_layout \begin_layout Plain Layout Btest2 2 0 I = pwl(v(1), 'x0','y0', 'x1','y1', 'x2','y2', 'x3','y3') \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * like TABLE function with limits: \end_layout \begin_layout Plain Layout Btest3 3 0 I = (v(1) < 'x0') ? 'y0' : (v(1) < 'x3') ? \end_layout \begin_layout Plain Layout + pwl(v(1), 'x0','y0', 'x1','y1', 'x2','y2', 'x3','y3') : 'y3' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * more efficient and elegant TABLE function with limits \end_layout \begin_layout Plain Layout *(voltage controlled): \end_layout \begin_layout Plain Layout Btest4 4 0 I = pwl(v(1), \end_layout \begin_layout Plain Layout + 'xx0','y0', 'x0','y0', \end_layout \begin_layout Plain Layout + 'x1','y1', \end_layout \begin_layout Plain Layout + 'x2','y2', \end_layout \begin_layout Plain Layout + 'x3','y3', 'xx3','y3') \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * more efficient and elegant TABLE function with limits \end_layout \begin_layout Plain Layout * (controlled by current): \end_layout \begin_layout Plain Layout Btest5 5 0 I = pwl(-2*i(Vin), \end_layout \begin_layout Plain Layout + 'xx0','y0', 'x0','y0', \end_layout \begin_layout Plain Layout + 'x1','y1', \end_layout \begin_layout Plain Layout + 'x2','y2', \end_layout \begin_layout Plain Layout + 'x3','y3', 'xx3','y3') \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Rint2 2 0 1 \end_layout \begin_layout Plain Layout Rint3 3 0 1 \end_layout \begin_layout Plain Layout Rint4 4 0 1 \end_layout \begin_layout Plain Layout Rint5 5 0 1 \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout dc Vin -6 6 0.2 \end_layout \begin_layout Plain Layout plot v(2) v(3) v(4)-0.5 v(5)+0.5 \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:E-source-(non-linear" \end_inset E source (non-linear voltage source)* \end_layout \begin_layout Subsection VOL \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX n+ n- vol='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout E41 4 0 vol = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). ' or {, } may be used to delimit the function. \end_layout \begin_layout Subsection VALUE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Optional syntax: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX n+ n- value={expr} \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout E41 4 0 value = {V(3)*V(3)-Offs} \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:table" \end_inset TABLE \end_layout \begin_layout Standard Data may be entered from the listings of a data table similar to the pwl B-Source ( \begin_inset CommandInset ref LatexCommand ref reference "sub:PiecewiseLinearFunction:-pwl" \end_inset ). Data are grouped into x, y pairs. \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). ' or {, } may be used to delimit the function. \series bold Expression \series default delivers the x-value, which is used to generate a corresponding y-value, according to the tabulated value pairs, using linear interpolation. If the x-value is below x0 , y0 is returned, above x2 y2 is returned (limiting function). The value pairs have to be real numbers, parameters are \series bold not \series default allowed! \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Syntax for data entry from table: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Exxx n1 n2 TABLE {expression} = (x0, y0) (x1, y1) (x2, y2) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (simple comparator): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ECMP 11 0 TABLE {V(10,9)} = (-5MV, 0V) (5MV, 5V) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:POLY" \end_inset POLY \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout EXXXX N+ N- (POLY (ND)) NC1+ NC1- (NC2+ NC2-...) P0 (P1...) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ENONLIN 100 101 POLY(2) 3 0 4 0 0.0 13.6 0.2 0.005 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard POLY(ND) Specifies the number of dimensions of the polynomial. The number of pairs of controlling nodes must be equal to the number of dimensions. \end_layout \begin_layout Standard (N+) and (N-) nodes are output nodes. Positive current flows from the (+) node through the source to the (-) node. \end_layout \begin_layout Standard The and are in pairs and define a set of controlling voltages. A particular node can appear more than once, and the output and controlling nodes need not be different. \end_layout \begin_layout Standard The example yields a voltage output controlled by two input voltages v(3,0) and v(4,0). Four polynomal coefficients are given. The equivalent function to generate the output is: \end_layout \begin_layout LyX-Code 0 + 13.6 * v(3) + 0.2 * v(4) + 0.005 * v(3) * v(3) \end_layout \begin_layout Standard Generally you will set the equation according to \end_layout \begin_layout LyX-Code POLY(1) y = p0 + k1*X1 + p2*X1*X1 + p3*X1*X1*X1 + ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code POLY(2) y = p0 + p1*X1 + p2*X2 + \end_layout \begin_layout LyX-Code + p3*X1*X1 + p4*X2*X1 + p5*X2*X2 + \end_layout \begin_layout LyX-Code + p6*X1*X1*X1 + p7*X2*X1*X1 + p8*X2*X2*X1 + \end_layout \begin_layout LyX-Code + p9*X2*X2*X2 + ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code POLY(3) y = p0 + p1*X1 + p2*X2 + p3*X3 + \end_layout \begin_layout LyX-Code + p4*X1*X1 + p5*X2*X1 + p6*X3*X1 + \end_layout \begin_layout LyX-Code + p7*X2*X2 + p8*X2*X3 + p9*X3*X3 + ... \end_layout \begin_layout Standard where X1 is the voltage difference of the first input node pair, X2 of the second pair and so on. Keeping track of all polynomal coefficient obviously becomes rather tedious for larger polynomals. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:LAPLACE" \end_inset LAPLACE \end_layout \begin_layout Standard Currently ngspice does not offer a direct E-Source element with the LAPLACE option. There is however, a XSPICE code model equivalent called \series bold x_fer \series default (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:S-Domain-Transfer-Function" \end_inset ), which you may invoke manually. The XSPICE option has to enabled ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" \end_inset ). AC ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.AC:-Small-Signal-AC" \end_inset ) and transient analysis ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.TRAN:-Transient-Analysis" \end_inset ) is supported. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout The following E-Source: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ELOPASS 4 0 LAPLACE {V(1)} {10 / (s/6800 + 1)} \end_layout \end_inset \end_layout \begin_layout Plain Layout may be replaced by: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout AELOPASS 1 int_4 filter1 \end_layout \begin_layout Plain Layout .model filter1 x_fer(gain=10 int_ic=[0 0] num_coeff=[1] \end_layout \begin_layout Plain Layout + den_coeff=[1 1.47e-4] \end_layout \begin_layout Plain Layout ELOPASS 4 0 int_4 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard where you have the voltage of node 1 as input, an intermediate output node int_4 and an E-source as buffer, so to keep the name 'ELOPASS' available if further processing is required. \end_layout \begin_layout Standard If the controlling expression is more complex than just a voltage node, you may add a B-Source ( \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset ) for evaluating the expression before enmtering the A-device. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout E-Source with complex controlling expression: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ELOPASS 4 0 LAPLACE {V(1)*v(2)} {10 / (s/6800 + 1)} \end_layout \end_inset \end_layout \begin_layout Plain Layout may be replaced by: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout BELOPASS int_1 0 V=V(1)*v(2) \end_layout \begin_layout Plain Layout AELOPASS int_1 int_4 filter1 \end_layout \begin_layout Plain Layout .model filter1 x_fer(gain=10 int_ic=[0 0] num_coeff=[1] \end_layout \begin_layout Plain Layout + den_coeff=[1 1.47e-4] \end_layout \begin_layout Plain Layout ELOPASS 4 0 int_4 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:G-source-(non-linear" \end_inset G source (non-linear current source)* \end_layout \begin_layout Subsection CUR \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX n+ n- cur='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout G51 55 225 cur = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ). \end_layout \begin_layout Subsection VALUE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Optional syntax: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX n+ n- value='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout G51 55 225 value = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection TABLE \end_layout \begin_layout Standard A data entry by a tabulated listing is available with syntax similar to the E-Source (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:table" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Syntax for data entry from table: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Gxxx n1 n2 TABLE {expression} = (x0, y0) (x1, y1) (x2, y2) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (simple comparator with current output and voltage control): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout GCMP 0 11 TABLE {V(10,9)} = (-5MV, 0V) (5MV, 5V) \end_layout \begin_layout Plain Layout R 11 0 1k \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection POLY \end_layout \begin_layout Standard see E-Source at chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:POLY" \end_inset . \end_layout \begin_layout Subsection LAPLACE \end_layout \begin_layout Standard See E-Source, chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:LAPLACE" \end_inset , for an equivalent code model replacement. \end_layout \begin_layout Subsection Example \end_layout \begin_layout Standard An example file is given below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout VCCS, VCVS, non-linear dependency \end_layout \begin_layout Plain Layout .param Vi=1 \end_layout \begin_layout Plain Layout .param Offs='0.01*Vi' \end_layout \begin_layout Plain Layout * VCCS depending on V(3) \end_layout \begin_layout Plain Layout B21 int1 0 V = V(3)*V(3) \end_layout \begin_layout Plain Layout G1 21 22 int1 0 1 \end_layout \begin_layout Plain Layout * measure current through VCCS \end_layout \begin_layout Plain Layout vm 22 0 dc 0 \end_layout \begin_layout Plain Layout R21 21 0 1 \end_layout \begin_layout Plain Layout * new VCCS depending on V(3) \end_layout \begin_layout Plain Layout G51 55 225 cur = 'V(3)*V(3)-Offs' \end_layout \begin_layout Plain Layout * measure current through VCCS \end_layout \begin_layout Plain Layout vm5 225 0 dc 0 \end_layout \begin_layout Plain Layout R51 55 0 1 \end_layout \begin_layout Plain Layout * VCVS depending on V(3) \end_layout \begin_layout Plain Layout B31 int2 0 V = V(3)*V(3) \end_layout \begin_layout Plain Layout E1 1 0 int2 0 1 \end_layout \begin_layout Plain Layout R1 1 0 1 \end_layout \begin_layout Plain Layout * new VCVS depending on V(3) \end_layout \begin_layout Plain Layout E41 4 0 vol = 'V(3)*V(3)-Offs' \end_layout \begin_layout Plain Layout R4 4 0 1 \end_layout \begin_layout Plain Layout * control voltage \end_layout \begin_layout Plain Layout V1 3 0 PWL(0 0 100u {Vi}) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout tran 10n 100u uic \end_layout \begin_layout Plain Layout plot i(E1) i(E41) \end_layout \begin_layout Plain Layout plot i(vm) i(vm5) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard *) To get this functionality, the compatibility mode has to be set in \series bold spinit \series default or \series bold .spiceinit \series default by \family typewriter set ngbehavior=all \family default . \end_layout \begin_layout Chapter Transmission Lines \end_layout \begin_layout Standard Ngspice implements both the original spice3f5 transmission lines models and the one introduced with kspice. The latter provide an improved transient analysis of lossy transmission lines. Unlike spice models, which uses the state-based approach to simulate lossy transmission lines, kspice simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. We use this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has been proved to give a speedup of one to two orders of magnitude over spice3f5. \end_layout \begin_layout Section Lossless Transmission Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout TXXXXXXX N1 N2 N3 N4 Z0=VALUE > \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout T1 1 0 2 0 Z0=50 TD=10NS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes at port 1; \family typewriter \series bold n3 \family default \series default and \family typewriter \series bold n4 \family default \series default are the nodes at port 2. \family typewriter \series bold z0 \family default \series default is the characteristic impedance. The length of the line may be expressed in either of two forms. The transmission delay, \family typewriter \series bold td \family default \series default , may be specified directly (as td=10ns, for example). Alternatively, a frequency \family typewriter \series bold f \family default \series default may be given, together with \family typewriter \series bold nl \family default \series default , the normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency \begin_inset Quotes eld \end_inset f \begin_inset Quotes erd \end_inset . If a frequency is specified but \family typewriter \series bold nl \family default \series default is omitted, 0.25 is assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that although both forms for expressing the line length are indicated as optional, one of the two must be specified. \end_layout \begin_layout Standard Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmission-line elements are required. (see the example in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Transmission-Line-Inverter" \end_inset for further clarification.) The (optional) initial condition specification consists of the voltage and current at each of the transmission line ports. Note that the initial conditions (if any) apply \begin_inset Quotes eld \end_inset only \begin_inset Quotes erd \end_inset if the \family typewriter \series bold UIC \family default \series default option is specified on the \family typewriter .TRAN \family default control line. \end_layout \begin_layout Standard Note that a lossy transmission line (see below) with zero loss may be more accurate than than the lossless transmission line due to implementation details. \end_layout \begin_layout Section Lossy Transmission Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout OXXXXXXX n1 n2 n3 n4 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout O23 1 0 2 0 LOSSYMOD \end_layout \begin_layout Plain Layout OCONNECT 10 5 20 5 INTERCONNECT \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is a two-port convolution model for single conductor lossy transmission lines. \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes at port 1; \family typewriter \series bold n3 \family default \series default and \family typewriter \series bold n4 \family default \series default are the nodes at port 2. Note that a lossy transmission line with zero loss may be more accurate than than the lossless transmission line due to implementation details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Lossy-Transmission-Line" \end_inset Lossy Transmission Line Model (LTRA) \end_layout \begin_layout Standard The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth) models a uniform constant-parameter distributed transmission line. The RC and LC cases may also be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and more accurate than the others. The operation of the LTRA model is based on the convolution of the transmission line's impulse responses with its inputs (see [8]). The LTRA model takes a number of parameters, some of which must be given and some of which are optional. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LEN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout REL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout breakpoint control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout arbitrary unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ABS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout breakpoint control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NOSTEPLIMIT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't limit time-step to less than line delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NOCONTROL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't do complex time-step control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LININTERP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use linear interpolation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MIXEDINTERP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use linear when quadratic seems bad \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout COMPACTREL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout special reltol for history compaction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RELTOL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout COMPACTABS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout special abstol for history compaction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ABSTOL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUNCNR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use Newton-Raphson method for time-step control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUNCDONTCUT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't limit time-step to keep impulse-response errors low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The following types of lines have been implemented so far: \end_layout \begin_layout Itemize RLC (uniform transmission line with series loss only), \end_layout \begin_layout Itemize RC (uniform RC line), \end_layout \begin_layout Itemize LC (lossless transmission line), \end_layout \begin_layout Itemize RG (distributed series resistance and parallel conductance only). \end_layout \begin_layout Standard Any other combination will yield erroneous results and should not be tried. The length \family typewriter \series bold LEN \family default \series default of the line must be specified. \family typewriter \series bold NOSTEPLIMIT \family default \series default is a flag that will remove the default restriction of limiting time-steps to less than the line delay in the RLC case. \family typewriter \series bold NOCONTROL \family default \series default is a flag that prevents the default limiting of the time-step based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in some cases reduce the accuracy of results. \family typewriter \series bold LININTERP \family default \series default is a flag that, when specified, will use linear interpolation instead of the default quadratic interpolation for calculating delayed signals. \family typewriter \series bold MIXEDINTERP \family default \series default is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default quadratic interpolation. \family typewriter \series bold TRUNCDONTCUT \family default \series default is a flag that removes the default cutting of the time-step to limit errors in the actual calculation of impulse-response related quantities. \family typewriter \series bold COMPACTREL \family default \series default and \family typewriter \series bold COMPACTABS \family default \series default are quantities that control the compaction of the past history of values stored for convolution. Larger values of these lower accuracy but usually increase simulation speed. These are to be used with the \family typewriter \series bold TRYTOCOMPACT \family default \series default option, described in the . \family typewriter \series bold OPTIONS \family default \series default section. \family typewriter \series bold TRUNCNR \family default \series default is a flag that turns on the use of Newton-Raphson iterations to determine an appropriate time-step in the time-step control routines. The default is a trial and error procedure by cutting the previous time-step in half. \family typewriter \series bold REL \family default \series default and \family typewriter \series bold ABS \family default \series default are quantities that control the setting of breakpoints. \end_layout \begin_layout Standard The option most worth experimenting with for increasing the speed of simulation is \family typewriter \series bold REL \family default \series default . The default value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy. \end_layout \begin_layout Standard Breakpoints may usually be entirely eliminated if it is expected the circuit will not display sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting many breakpoints. \end_layout \begin_layout Standard \family typewriter \series bold COMPACTREL \family default \series default may also be experimented with when the option \family typewriter \series bold TRYTOCOMPACT \family default \series default is specified in a \family typewriter .OPTIONS \family default card. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but in some cases improve speed. If \family typewriter \series bold TRYTOCOMPACT \family default \series default is not specified on a \family typewriter .OPTIONS \family default card, history compaction is not attempted and accuracy is high. \end_layout \begin_layout Standard \family typewriter \series bold NOCONTROL \family default \series default , \family typewriter \series bold TRUNCDONTCUT \family default \series default and \family typewriter \series bold NOSTEPLIMIT \family default \series default also tend to increase speed at the expense of accuracy. \end_layout \begin_layout Section Uniform Distributed RC Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout UXXXXXXX n1 n2 n3 mname l=len \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout U1 1 2 0 URCMOD L=50U \end_layout \begin_layout Plain Layout URC2 1 12 2 UMODL l=1MIL N=6 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the two element nodes the RC line connects, while \family typewriter \series bold n3 \family default \series default is the node to which the capacitances are connected. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold len \family default \series default is the length of the RC line in meters. \family typewriter \series bold lumps \family default \series default , if specified, is the number of lumped segments to use in modeling the RC line (see the model description for the action taken if this parameter is omitted). \end_layout \begin_layout Subsection Uniform Distributed RC Model (URC) \end_layout \begin_layout Standard The URC model is derived from a model proposed by L. Gertzberrg in 1974. The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with \begin_inset Formula $K$ \end_inset as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} N=\frac{\log\left|F_{{\rm max}}\frac{R}{L}\frac{C}{L}2\pi L^{2}\left|\frac{(K-1)}{K}\right|^{2}\right|}{\log K}\end{equation} \end_inset The URC line is made up strictly of resistor and capacitor segments unless the \family typewriter \series bold ISPERL \family default \series default parameter is given a nonzero value, in which case the capacitors are replaced with reverse biased diodes with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of \family typewriter \series bold ISPERL \family default \series default amps per meter of transmission line and an optional series resistance equivalen t to \family typewriter \series bold RSPERL \family default \series default ohms per meter. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Propagation Constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FMAX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum Frequency of interest \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6.5 Meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation Current per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode Resistance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Section KSPICE Lossy Transmission Lines \end_layout \begin_layout Standard Unlike SPICE3, which uses the state-based approach to simulate lossy transmissio n lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. NGSPICE is using this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has shown to give a speedup of one to two orders of magnitude over SPICE3E. \end_layout \begin_layout Standard Additional Documentation Available: \end_layout \begin_layout Itemize S. Lin and E. S. Kuh, "Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines," Proc. IEEE Multi-Chip Module Conference, 1992, pp. 52-55. \end_layout \begin_layout Itemize S. Lin, M. Marek-Sadowska, and E. S. Kuh, "SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits," European Design Automation Conf., February 1991, pp. 142-148. \end_layout \begin_layout Itemize S. Lin and E. S. Kuh, "Transient Simulation of Lossy Interconnect," Proc. Design Automation Conference, Anaheim, CA, June 1992, pp. 81-86. \end_layout \begin_layout Subsection Single Lossy Transmission Line (TXL) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout YXXXXXXX N1 0 N2 0 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Y1 1 0 2 0 ymod LEN=2 \end_layout \begin_layout Plain Layout .MODEL ymod txl R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes of the two ports; Optional instance parameter \family typewriter \series bold len \family default \series default is the length of the line may be expressed in [m]. \end_layout \begin_layout Standard The TXL model takes a number of parameters: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Model parameter length must be specified. \end_layout \begin_layout Subsection Coupled Multiconductor Line (CPL) \end_layout \begin_layout Standard The CPL multiconductor line model, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss). Up to 8 coupled lines are supported in NGSPICE. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout PXXXXXXX NI1 NI2...NIX GND1 NO1 NO2...NOX GND2 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout P1 in1 in2 0 b1 b2 0 PLINE \end_layout \begin_layout Plain Layout .model PLINE CPL length={Len} \end_layout \begin_layout Plain Layout +R=1 0 1 \end_layout \begin_layout Plain Layout +L={L11} {L12} {L22} \end_layout \begin_layout Plain Layout +G=0 0 0 \end_layout \begin_layout Plain Layout +C={C11} {C12} {C22} \end_layout \begin_layout Plain Layout .param Len=1 Rs=0 \end_layout \begin_layout Plain Layout + C11=9.143579E-11 C12=-9.78265E-12 C22=9.143578E-11 \end_layout \begin_layout Plain Layout + L11=3.83572E-7 L12=8.26253E-8 L22=3.83572E-7 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold ni1 \family default \series default ... \family typewriter \series bold nix \family default \series default are the nodes at port 1 with gnd1; \family typewriter \series bold no1 \family default \series default ... \family typewriter \series bold n \family default \series default ox are the nodes at port 2 with gnd2. Optional instance parameter \family typewriter \series bold len \family default \series default is the length of the lines may be expressed in [m]. \end_layout \begin_layout Standard The CPL model takes a number of parameters: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard All RLGC parameter are given in Maxwell matrix form. For R and G matrix the diagonal elements must be specified, for L and C matrix the lower or upper-triangular elements must specified. Model parameter LENGTH is a scalar and is mandatory. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:DIODEs" \end_inset Diodes \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Junction-Diodes" \end_inset Junction Diodes \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout DXXXXXXX n+ n- mname \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout DBRIDGE 2 10 DIODE1 \end_layout \begin_layout Plain Layout DCLMP 3 7 DMOD AREA=3.0 IC=0.2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The pn junction (diode) implemented in ngspice expands the one found in spice3f5. Perimeter effects and high injection level have been introduced into the original model and temperature dependence of some parameters has been added. \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name. Instance parameters may follow, dedicated to only the diode described in the respective line. \family typewriter \series bold area \family default \series default is the area scale factor, which may scale the saturation current given by the model parameters (and others, see table below). \family typewriter \series bold pj \family default \series default is the perimeter scale factor, scaling the sidewall saturation current and it's associated capacitance. \family typewriter \series bold m \family default \series default is a multiplier to area and perimeter, and \family typewriter \series bold off \family default \series default indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using \family typewriter \series bold ic \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. You should supply the initial voltage across the diode there. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. The temperature of each instance can be can be specified as an offset to the circuit temperature with the \family typewriter \series bold dtemp \family default \series default option. \end_layout \begin_layout Section Diode Model (D) \end_layout \begin_layout Standard The dc characteristics of the diode are determined by the parameters \family typewriter \series bold is \family default \series default and \family typewriter \series bold n \family default \series default . An ohmic resistance, \family typewriter \series bold rs \family default \series default , is included. Charge storage effects are modeled by a transit time, \family typewriter \series bold tt \family default \series default , and a nonlinear depletion layer capacitance which is determined by the parameters \family typewriter \series bold cjo \family default \series default , \family typewriter \series bold vj \family default \series default , and \family typewriter \series bold m \family default \series default . The temperature dependence of the saturation current is defined by the parameters \family typewriter \series bold eg \family default \series default , the energy and \family typewriter \series bold xti \family default \series default , the saturation current temperature exponent. The nominal temperature at which these parameters were measured is \family typewriter \series bold tnom \family default \series default , which defaults to the circuit-wide value specified on the \family typewriter .options \family default control line. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters \family typewriter \series bold bv \family default \series default and \family typewriter \series bold ibv \family default \series default (both of which are positive numbers). \end_layout \begin_layout Subsubsection* Junction DC parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse breakdown voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 40 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current at breakdown voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IK (IKF) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward knee current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse knee current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS (JS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sidewall saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{area}$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Junction capacitance parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJO (CJ0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias junction bottom-wall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJP (CJSW) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias junction sidewall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion bottom-wall capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion sidewall capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout M (MJ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area junction grading coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Periphery junction grading coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.33 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VJ (PB) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Periphery junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transit-time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1ns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Temperature effects \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Activation energy \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $eV$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 1.11 & \mathrm{Si}\\ 0.69 & \mathrm{Sbd}\\ 0.67 & \mathrm{Ge}\end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM (TREF) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS1 (TRS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTT1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTT2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation current temperature exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 3.0 & \mathrm{pn}\\ 2.0 & \mathrm{Sbd}\end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode temperature equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEVC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode capac. temperature equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTA (CTC) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area junct. cap. temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Perimeter junct. cap. temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TCV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Breakdown voltage temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Noise modeling \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Diode models may be described in the input file (or an file included by .inc) according to the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .model mname type(pname1=pval1 pname2=pval2 ... ) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .model DMOD D (bf=50 is=1e-13 vbf=50) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section Diode Equations \end_layout \begin_layout Standard The junction diode is the basic semiconductor device and the simplest one modeled in ngspice, but it's model is quite complex, even if not all the physical phenomena affecting a pn junction are modeled. The diode is modeled in three different regions: \end_layout \begin_layout Itemize \emph on Forward bias \emph default : the anode is more positive than the cathode, the diode is "on" and can conduct large currents. To avoid convergence problems and unrealistic high current, it is better to specify a series resistance to limit current with \family typewriter \series bold rs \family default \series default model parameter. \end_layout \begin_layout Itemize \emph on Reverse bias \emph default : the cathode is more positive than the anode and the diode is "off". A reverse bias diode conducts a small leakage current. \end_layout \begin_layout Itemize \emph on Breakdown \emph default : the breakdown region is model led only if the \family typewriter \series bold bv \family default \series default model parameter is given. When a diode enters breakdown the current increase exponentially (remember to limit it); \family typewriter \series bold bv \family default \series default is a positive value. \end_layout \begin_layout Subsubsection* Parameters Scaling \end_layout \begin_layout Standard Model parameters are scaled using the unit-less parameters \family typewriter \series bold area \family default \series default and \family typewriter \series bold pj \family default \series default and the multiplier \family typewriter \series bold m \family default \series default as depicted below: \end_layout \begin_layout Standard \begin_inset Formula $AREA_{eff}={\rm AREA}\cdot{\rm M}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $PJ_{eff}={\rm PJ}\cdot{\rm M}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IS_{eff}={\rm IS}\cdot AREA_{eff}+{\rm JSW}*PJ_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IBV_{eff}={\rm IBV}\cdot AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IK_{eff}={\rm IK}\cdot AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IKR_{eff}={\rm IKR}\cdot AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $CJ_{eff}={\rm CJ0}\cdot AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $CJP_{eff}={\rm CJP}\cdot PJ_{eff}$ \end_inset \end_layout \begin_layout Subsubsection* Diode DC, Transient and AC model equations \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{D}=\begin{cases} IS_{eff}(e^{\frac{qV_{D}}{NkT}}-1)+V_{D}*GMIN, & \mathrm{if}\; V_{D}\geq-3\frac{NkT}{q}\\ -IS_{eff}[1+(\frac{3NkT}{qV_{D}e})^{3}]+V_{D}*GMIN, & \mathrm{if}\;-BV_{eff} mname \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Q23 10 24 13 QMOD IC=0.6, 5.0 \end_layout \begin_layout Plain Layout Q50A 11 26 4 20 MOD1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold nc \family default \series default , \family typewriter \series bold nb \family default \series default , and \family typewriter \series bold ne \family default \series default are the collector, base, and emitter nodes, respectively. \family typewriter \series bold ns \family default \series default is the (optional) substrate node. If unspecified, ground is used. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default , \family typewriter \series bold areab \family default \series default , \family typewriter \series bold areac \family default \series default are the area factors (emitter, base and collector respectively), and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed. \end_layout \begin_layout Standard The (optional) initial condition specification using \family typewriter \series bold ic=vbe,vce \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on a \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line description for a better way to set transient initial conditions. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. Using \family typewriter \series bold dtemp \family default \series default option you can specify instance's temperature relative to the circuit temperatu re. \end_layout \begin_layout Section BJT Models (NPN/PNP) \end_layout \begin_layout Standard Ngspice provides three BJT device models. The \family typewriter \series bold level \family default \series default keyword specifies the model to be used: \end_layout \begin_layout Itemize level=1 : This is the original spice BJT model, and it is the default model if the \family typewriter \series bold level \family default \series default keyword is not specified on the \family typewriter .model \family default line. \end_layout \begin_layout Itemize level=2 : This is a modified version of the original spice BJT that models both vertical and lateral devices and includes temperature corrections of collector, emitter and base resistors. \end_layout \begin_layout Itemize level=4: Advanced VBIC model (see \begin_inset CommandInset href LatexCommand href target "http://www.designers-guide.org/VBIC/" \end_inset for details) \end_layout \begin_layout Standard The bipolar junction transistor model in ngspice is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model automatically simplifies to the simpler Ebers-Moll model when certain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physical and circuit design thinking. \end_layout \begin_layout Standard The dc model is defined by the parameters \family typewriter \series bold is \family default \series default , \family typewriter \series bold bf \family default \series default , \family typewriter \series bold nf \family default \series default , \family typewriter \series bold ise \family default \series default , \family typewriter \series bold ikf \family default \series default , and \family typewriter \series bold ne \family default \series default which determine the forward current gain characteristics, \family typewriter \series bold is \family default \series default , \family typewriter \series bold br \family default \series default , \family typewriter \series bold nr \family default \series default , \family typewriter \series bold isc \family default \series default , \family typewriter \series bold ikr \family default \series default , and \family typewriter \series bold nc \family default \series default which determine the reverse current gain characteristics, and \family typewriter \series bold vaf \family default \series default and \family typewriter \series bold var \family default \series default which determine the output conductance for forward and reverse regions. \end_layout \begin_layout Standard Level 1 model has among the standard temperature model a extension which is compatible with most foundry provided process design kits (see parameter table below \family typewriter \series bold tlev \family default \series default ). \end_layout \begin_layout Standard Level 1 and 2 model includes substrate saturation current \family typewriter \series bold iss \family default \series default . Three ohmic resistances \family typewriter \series bold rb \family default \series default , \family typewriter \series bold rc \family default \series default , and \family typewriter \series bold re \family default \series default are included, where \family typewriter \series bold rb \family default \series default can be high current dependent. Base charge storage is modelled by forward and reverse transit times, \family typewriter \series bold tf \family default \series default and \family typewriter \series bold tr \family default \series default , the forward transit time \family typewriter \series bold tf \family default \series default being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by \family typewriter \series bold cje \family default \series default , \family typewriter \series bold vje \family default \series default , and \family typewriter \series bold nje \family default \series default for the B-E junction, \family typewriter \series bold cjc \family default \series default , \family typewriter \series bold vjc \family default \series default , and \family typewriter \series bold njc \family default \series default for the B-C junction and \family typewriter \series bold cjs \family default \series default , \family typewriter \series bold vjs \family default \series default , and \family typewriter \series bold mjs \family default \series default for the C-S (Collector-Substrate) junction. \end_layout \begin_layout Standard Level 1 and 2 model defines a substrate capacitance that will be connected to device's base or collector, to model lateral or vertical devices dependent from the parameter \family typewriter \series bold subs \family default \series default . The temperature dependence of the saturation currents, \family typewriter \series bold is \family default \series default and \family typewriter \series bold iss \family default \series default (for level 2 model), is determined by the energy-gap, \family typewriter \series bold eg \family default \series default , and the saturation current temperature exponent, \family typewriter \series bold xti \family default \series default . \end_layout \begin_layout Standard Additionally base current temperature dependence is modeled by the beta temperature exponent \family typewriter \series bold xtb \family default \series default in the new model. The values specified are assumed to have been measured at the temperature \family typewriter \series bold tnom \family default \series default , which can be specified on the \family typewriter .options \family default control line or overridden by a specification on the \family typewriter .model \family default line. \end_layout \begin_layout Standard Level 4 model (VBIC) has the following improvements beyond the GP models: Improved Early effect modeling, Quasi-saturation modeling, Parasitic substrate transistor modeling, Parasitic fixed (oxide) capacitance modeling, Includes an avalanche multiplication model, Improved temperature modeling, Base current is decoupled from collector current, Electrothermal modeling, Smooth, continuous mode. \end_layout \begin_layout Standard The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of spice2 are still accepted. \end_layout \begin_layout Subsubsection* Gummel-Poon BJT Parameters (incl. model extensions) \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameters \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SUBS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate connection: for vertical geometry, -1 for lateral geometry (level 2 only). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transport saturation current. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse saturation current, substrate-to-collector for vertical device or substrate-to-base for lateral (level 2 only). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal maximum forward beta. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward current emission coefficient. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VAF (VA) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward Early voltage. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 200 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Corner for forward beta current roll-off. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.01 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none NKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High current Beta rolloff exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.58 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E leakage saturation current. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-13 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E leakage emission coefficient. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal maximum reverse beta. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse current emission coefficient. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VAR (VB) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse Early voltage. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 200 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Corner for reverse beta high current roll-off. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.01 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C leakage saturation current (area is "areab" for vertical devices and "areac" for lateral). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-13 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C leakage emission coefficient. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero bias base resistance. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IRB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current where base resistance falls halfway to its min value. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RBM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Minimum base resistance at high currents. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Emitter resistance. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Collector resistance. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E zero-bias depletion capacitance. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VJE (PE) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E built-in potential. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.75 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJE (ME) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E junction exponential factor. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.33 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.33 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal forward transit time. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1ns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for bias dependence of TF. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage describing VBC dependence of TF. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ITF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High-current parameter for effect on TF. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PTF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Excess phase at freq=1.0/(TF*2PI) Hz. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout deg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C zero-bias depletion capacitance (area is "areab" for vertical devices and "areac" for lateral). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VJC (PC) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C built-in potential. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.75 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C junction exponential factor. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.33 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XCJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fraction of B-C depletion capacitance connected to internal base node. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal reverse transit time. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10ns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias collector-substrate capacitance (area is "areac" for vertical devices and"areab" for lateral). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VJS (PS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate junction built-in potential. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.75 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJS (MS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate junction exponential factor. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward and reverse beta temperature exponent. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Energy gap for temperature effect on IS. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $eV$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature exponent for effect on IS. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker-noise coefficient. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker-noise exponent. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM (TREF) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BJT temperature equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEVC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BJT capac. temperature equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for RE. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for RE. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for RC . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for RC. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRB1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for RB. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRB2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for RB. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRBM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for RBM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRBM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for RBM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TBF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for BF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TBF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for BF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TBR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for BR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TBR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for BR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TIKF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset 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Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TIKR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for IKR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TIRB1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for IRB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset 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Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for NC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for NE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset 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\end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for NF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VAF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for VAF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VAR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for VAR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TITF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for ITF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TITF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for ITF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for MJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for MJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for MJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for MJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Chapter JFETs \end_layout \begin_layout Section Junction Field-Effect Transistors (JFETs) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout JXXXXXXX nd ng ns mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout J1 7 2 3 JM1 OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , and \family typewriter \series bold ns \family default \series default are the drain, gate, and source nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default is the area factor, and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using \family typewriter \series bold ic=VDS,VGS \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .TRAN \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better way to set initial conditions. The (optional) \family typewriter temp \family default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. \end_layout \begin_layout Section JFET Models (NJF/PJF) \end_layout \begin_layout Subsection Model by Parker and Skellern \end_layout \begin_layout Standard The \series bold level 1 \series default JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters \family typewriter \series bold vto \family default \series default and \family typewriter \series bold beta \family default \series default , which determine the variation of drain current with gate voltage, \family typewriter \series bold lambda \family default \series default , which determines the output conductance, and \family typewriter \series bold is \family default \series default , the saturation current of the two gate junctions. Two ohmic resistances, \family typewriter \series bold rd \family default \series default and \family typewriter \series bold rs \family default \series default , are included. Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the \begin_inset Formula $-\nicefrac{1}{2}$ \end_inset power of junction voltage and are defined by the parameters \family typewriter \series bold cgs \family default \series default , \family typewriter \series bold cgd \family default \series default , and \family typewriter \series bold pb \family default \series default . \end_layout \begin_layout Standard Note that in Spice3f and later, a fitting parameter \begin_inset Quotes eld \end_inset \family typewriter \series bold b \family default \series default \begin_inset Quotes erd \end_inset has been added. For details, see \begin_inset CommandInset citation LatexCommand cite key "key-9" \end_inset . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scaling factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage \begin_inset Formula $V_{T0}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter ( \begin_inset Formula $\beta$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{"}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel-length modulation parameter ( \begin_inset Formula $\lambda$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-S junction capacitance \begin_inset Formula $C_{gs}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-D junction capacitance \begin_inset Formula $C_{gd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate saturation current \begin_inset Formula $I_{S}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Doping tail parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Modified Parker Skellern model \end_layout \begin_layout Standard The level 2 model is an improvement to level 1. Details are available from \begin_inset CommandInset href LatexCommand href name "Macquarie University" target "http://www.engineering.mq.edu.au/research/groups/cnerf/psmodel/index.htm" \end_inset . Some important items are: \end_layout \begin_layout Itemize The description maintains strict continuity in its high-order derivatives, which is essential for prediction of distortion and intermodulation. \end_layout \begin_layout Itemize Frequency dependence of output conductance and transconductance is described as a function of bias. \end_layout \begin_layout Itemize Both drain-gate and source-gate potentials modulate the pinch-off potential, which is consistent with S-parameter and pulsed-bias measurements. \end_layout \begin_layout Itemize Self-heating varies with frequency. \end_layout \begin_layout Itemize Extreme operating regions - subthreshold, forward gate bias, controlled resistance, and breakdown regions - are included. \end_layout \begin_layout Itemize Parameters provide independent fitting to all operating regions. It is not necessary to compromise one region in favor of another. \end_layout \begin_layout Itemize Strict drain-source symmetry is maintained. The transition during drain-source potential reversal is smooth and continuous. \end_layout \begin_layout Standard The model equations are described in this \begin_inset CommandInset href LatexCommand href name "pdf document" target "http://www.engineering.mq.edu.au/research/groups/cnerf/psfet.pdf" \end_inset and in \begin_inset CommandInset citation LatexCommand cite key "key-19" \end_inset . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unit Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Device IDText \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Text \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ACGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance modulation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear-region transconductance scale \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{−4}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias gate-source capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 F \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias gate-drain capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 F \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELTA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thermal reduction coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward bias capacitance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High-frequency VGS feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $0V^{−1}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High-frequency VGD feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFG1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VSG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFG2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VDG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction breakdown current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10−14A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Low-frequency feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFG1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM modulation by VSG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFG2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM modulation by VDG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MVST \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subthreshold modulation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V−1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction ideality factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear-region power-law exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Q \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturated-region power-law exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 Ohm \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 Ohm \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAUD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Relaxation time for thermal reduction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAUG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Relaxation time for gamma feedback \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction breakdown potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VBI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VST \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subthreshold potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance pinch-off reduction factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation-knee potential factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Knee transition parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 Ohm \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 H \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 H \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 H \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CDSS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fixed Drain-source capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 F \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AFAC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-width scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NFING \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of gate fingers scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout None \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nominal Temperature (Not implemented) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 300 K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 300 K \end_layout \end_inset \end_inset \end_layout \begin_layout Chapter MESFETs \end_layout \begin_layout Section MESFETs \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ZXXXXXXX ND NG NS MNAME \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Z1 7 2 3 ZM1 OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section MESFET Models (NMF/PMF) \end_layout \begin_layout Subsection Model by Statz e.a. \end_layout \begin_layout Standard The MESFET model \series bold level 1 \series default is derived from the GaAs FET model of Statz et al. as described in \begin_inset CommandInset citation LatexCommand cite key "key-11" \end_inset . The dc characteristics are defined by the parameters VTO, B, and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. The formula are given by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{d}=\begin{cases} \frac{B(V_{gs}-V_{T})^{2}}{1+b(V_{gs}-V_{T})}\left|1-\left|1-A\frac{V_{ds}}{3}\right|^{3}\right|(1+LV_{ds}) & \mathrm{for\;}0\frac{3}{A}\end{cases}\end{equation} \end_inset \end_layout \begin_layout Standard Two ohmic resistances, \family typewriter \series bold rd \family default \series default and \family typewriter \series bold rs \family default \series default , are included. Charge storage is modeled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters \family typewriter \series bold cgs \family default \series default , \family typewriter \series bold cgd \family default \series default , and \family typewriter \series bold pb \family default \series default . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pinch-off voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Doping tail extending parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ALPHA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation voltage parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel-length modulation parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-S junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-D junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Device instance: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout z1 2 3 0 mesmod area=1.4 \end_layout \end_inset \end_layout \begin_layout Plain Layout Model: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .model mesmod nmf level=1 rd=46 rs=46 vt0=-1.3 \end_layout \begin_layout Plain Layout + lambda=0.03 alpha=3 beta=1.4e-3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Model by Ytterdal e.a. \end_layout \begin_layout Standard \series bold level 2 \series default (and levels 3,4) Copyright 1993: T. Ytterdal, K. Lee, M. Shur and T. A. Fjeldly \end_layout \begin_layout Standard to be written \end_layout \begin_layout Standard M. Shur, T.A. Fjeldly, T. Ytterdal, K. Lee, "Unified GaAs MESFET Model for Circuit Simulation", Int. Journal of High Speed Electronics, vol. 3, no. 2, pp. 201-233, 1992 \end_layout \begin_layout Subsection hfet1 \end_layout \begin_layout Standard \series bold level 5 \end_layout \begin_layout Standard to be written \end_layout \begin_layout Standard no documentation available \end_layout \begin_layout Subsection hfet2 \end_layout \begin_layout Standard \series bold level6 \end_layout \begin_layout Standard to be written \end_layout \begin_layout Standard no documentation available \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:MOSFETs" \end_inset MOSFETs \end_layout \begin_layout Standard Ngspice supports all the original mosfet models present in spice3f5 and almost all the newer ones that have been published and made open-source. Both bulk and SOI (Silicon on Insulator) models are available. When compiled with the cider option, ngspice implements the four terminals numerical model that can be used to simulate a MOSFET (please refer to numerical modeling documentation for additional information and examples). \end_layout \begin_layout Section MOSFET devices \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\sffamily}" inline false status open \begin_layout Plain Layout MXXXXXXX nd ng ns nb mname \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\rmfamily}" inline false status open \begin_layout Plain Layout M1 24 2 0 20 TYPE1 \end_layout \begin_layout Plain Layout M31 2 17 6 10 MODM L=5U W=2U \end_layout \begin_layout Plain Layout M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U \end_layout \end_inset \end_layout \begin_layout Plain Layout Note the suffixes in the example: the suffix \begin_inset Quotes eld \end_inset u \begin_inset Quotes erd \end_inset specifies microns (1e-6 \begin_inset Formula $\mathrm{m}$ \end_inset ) and \begin_inset Quotes eld \end_inset \family typewriter p \family default \begin_inset Quotes erd \end_inset sq-microns (1e-12 \begin_inset Formula $\mathrm{m^{2}}$ \end_inset ). \end_layout \end_inset \begin_inset VSpace medskip \end_inset \end_layout \begin_layout Standard In the instance card, \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , \family typewriter \series bold ns \family default \series default , and \family typewriter \series bold nb \family default \series default are the drain, gate, source, and bulk (substrate) nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name and \family typewriter \series bold m \family default \series default is the multiplicity parameter, which simulates \begin_inset Quotes eld \end_inset m \begin_inset Quotes erd \end_inset paralleled devices. All MOS models support the \begin_inset Quotes eld \end_inset \family typewriter \series bold m \family default \series default \begin_inset Quotes erd \end_inset multiplier parameter. Instance parameters \family typewriter \series bold l \family default \series default and \family typewriter \series bold w \family default \series default , channel length and width respectively, are expressed in meters. The areas of drain and source diffusions: \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default , in squared meters ( \begin_inset Formula $\mathrm{m^{2}}$ \end_inset ). \end_layout \begin_layout Standard If any of \family typewriter \series bold l \family default \series default , \family typewriter \series bold w \family default \series default , \family typewriter \series bold ad \family default \series default , or \family typewriter \series bold as \family default \series default are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. \family typewriter \series bold pd \family default \series default and \family typewriter \series bold ps \family default \series default are the perimeters of the drain and source junctions, in meters. \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance \family typewriter \series bold rsh \family default \series default specified on the \family typewriter .model \family default control line for an accurate representation of the parasitic series drain and source resistance of each transistor. \family typewriter \series bold pd \family default \series default and \family typewriter \series bold ps \family default \series default default to 0.0 while \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default to 1.0. \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using \family typewriter \series bold ic=vds,vgs,vbs \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better and more convenient way to specify transient initial conditions. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. \end_layout \begin_layout Standard The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices. \end_layout \begin_layout Standard BSIM3.2 version is also supporting the instance parameter \family typewriter \series bold delvto \family default \series default and \family typewriter \series bold mulu0 \family default \series default for local mismatch and NBTI (negative bias temperature instability) modeling: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout delvto \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage shift \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.07 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mulu0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Low-field mobility multiplier (U0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.9 \end_layout \end_inset \end_inset \end_layout \begin_layout Section MOSFET models (NMOS/PMOS) \end_layout \begin_layout Standard MOSFET models are the central part of ngspice, probably because they are the most widely used devices in the electronics world. Ngspice provides all the MOSFETs implemented in the original Spice3f and adds several models developed by Berkeley's Device Group and other independent groups. The variable \family typewriter \series bold level \family default \series default specifies the model to be used and a short summary of available device is show in \begin_inset CommandInset ref LatexCommand ref reference "tab:MOSFET-model-summary" \end_inset . \end_layout \begin_layout Standard Note: not all models below are included in the standard ngspice distribution because of copyright restrictions. \end_layout \begin_layout Standard Ngspice provides four MOSFET device models, which differ in the formulation of the I-V characteristic. \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Level \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Version \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Developer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold References \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Shichman-Hodges \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout This is the classical quadratic model. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grove-Frhoman \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [2] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A semi-empirical model (see [1]) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [3] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [5] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [2] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alan Gillespie \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout extensions by Alan Gillespie \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout extensions by Serban Popescu \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v32 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.2 - 3.2.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multi version code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [13] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10, 58 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B4SOI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0 - 4.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multi version code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.6.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.7.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 44 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EKV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EPFL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout adms configured \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 45 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PSP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gildenblatt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout adms configured \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 55 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIFD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 56 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIDD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 57 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIPD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 60 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STAG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SOI3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Southampton \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 61 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HiSIM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.5.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hiroshima \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 62 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HiSIM_HV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hiroshima \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High Voltage Version for LDMOS \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:MOSFET-model-summary" \end_inset MOSFET model summary \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection MOS Level 1 \end_layout \begin_layout Standard This model is also known as the \begin_inset Quotes eld \end_inset Schichman-Hodges \begin_inset Quotes erd \end_inset model. This is the first model written and the one often described in the introductory textbooks of electronics. This model i applicable only to long channel devices and, the use of Meyer's model for the C-V part makes it non charge conserving. \end_layout \begin_layout Subsection MOS Level 2 \end_layout \begin_layout Standard This model tries to overcome the limitations of the Level 1 model addressing several short-channel effect, like velocity saturation. The implementation of this model is complicated and this leads to many convergence problems. C-V calculations can be done with the original Meyer model (non conserving). \end_layout \begin_layout Subsection MOS Level 3 \end_layout \begin_layout Standard This is a semi-empirical model derived from the Level 2 one. This model is often used for digital design and, in the years, has proved to be robust. A discontinuity in the model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option \begin_inset Quotes eld \end_inset \family typewriter \series bold badmos3 \family default \series default \begin_inset Quotes eld \end_inset may be set to use the old implementation (see the section on simulation variables and the \begin_inset Quotes eld \end_inset \family typewriter .options \family default \begin_inset Quotes erd \end_inset line). Ngspice level 3 implementation takes into account length and width mask adjustments ( \family typewriter \series bold xl \family default \series default and \family typewriter \series bold xw \family default \series default ) and device width narrowing due to diffusion ( \family typewriter \series bold wd \family default \series default ). \end_layout \begin_layout Subsection MOS Level 6 \end_layout \begin_layout Standard This model is described in \begin_inset CommandInset citation LatexCommand cite key "key-2" \end_inset . The model can express the current characteristics of short-channel MOSFETs at least down to 0. 25 \begin_inset Formula $\mu m$ \end_inset channel-length, GaAs FET, and resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the spice3 mos level 3 model. The model also enables analytical treatments of circuits in short-channel region and makes up for a missing link between a complicated MOSFET current characteristics and circuit behaviors in the deep submicron region. \end_layout \begin_layout Subsection Notes on Level 1-6 models \end_layout \begin_layout Standard The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters \family typewriter \series bold vto \family default \series default , \family typewriter \series bold kp \family default \series default , \family typewriter \series bold lambda \family default \series default , \family typewriter \series bold phi \family default \series default and \family typewriter \series bold gamma \family default \series default . These parameters are computed by ngspice if process parameters ( \family typewriter \series bold nsub \family default \series default , \family typewriter \series bold tox \family default \series default , ...) are given, but users specified values always override. \family typewriter \series bold vto \family default \series default is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. \end_layout \begin_layout Standard Charge storage is modeled by three constant capacitors, \family typewriter \series bold cgso \family default \series default , \family typewriter \series bold cgdo \family default \series default , and \family typewriter \series bold cgbo \family default \series default which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the \family typewriter \series bold mj \family default \series default and \family typewriter \series bold mjsw \family default \series default power of junction voltage respectively, and are determined by the parameters \family typewriter \series bold cbd \family default \series default , \family typewriter \series bold cbs \family default \series default , \family typewriter \series bold cj \family default \series default , \family typewriter \series bold cjsw \family default \series default , \family typewriter \series bold mj \family default \series default , \family typewriter \series bold mjsw \family default \series default and \family typewriter \series bold pb \family default \series default . \end_layout \begin_layout Standard Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the level 1 model. These voltage-dependent capacitances are included only if \family typewriter \series bold tox \family default \series default is specified in the input description and they are represented using Meyer's formulation. \end_layout \begin_layout Standard There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as \family typewriter \series bold is \family default \series default (in A) or as \family typewriter \series bold js \family default \series default (in \begin_inset Formula $\nicefrac{A}{m^{2}}$ \end_inset ). Whereas the first is an absolute value the second is multiplied by \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default to give the reverse current of the drain and source junctions respectively. \end_layout \begin_layout Standard This methodology has been chosen since there is no sense in relating always junction characteristics with \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances \family typewriter \series bold cbd \family default \series default and \family typewriter \series bold cbs \family default \series default (in F) on one hand, and \family typewriter \series bold cj \family default \series default (in \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset ) on the other. \end_layout \begin_layout Standard The parasitic drain and source series resistance can be expressed as either \family typewriter \series bold rd \family default \series default and \family typewriter \series bold rs \family default \series default (in ohms) or \family typewriter \series bold rsh \family default \series default (in ohms/sq.), the latter being multiplied by the number of squares \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default input on the device line. \end_layout \begin_layout Subsubsection* NGSPICE level 1, 2, 3 and 6 parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LEVEL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Model index \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias threshold voltage ( \begin_inset Formula $V_{T0})$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GAMMA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk threshold parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.37 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface potential (U) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.65 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel length modulation (MOS1 and MOS2 only) ( \begin_inset Formula $\lambda)$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.02 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias B-D junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20fF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CBS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias B-S junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20fF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction saturation current ( \begin_inset Formula $I_{S}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.8 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.87 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGSO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-source overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGDO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-drain overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGBO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-bulk overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain and source diffusion sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias bulk junction bottom cap. per sq-meter of junction area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction bottom grading coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias bulk junction sidewall cap. per meter of junction perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction sidewall grading coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 0.50 & \mathrm{(level}1)\\ 0.33 & \mathrm{(level}2,3)\end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TOX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Oxide thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NSUB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate doping \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NSS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface state density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NFS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fast surface state density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TPG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metallurgical junction depth \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lateral diffusion \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.8M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 600 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 700 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UCRIT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Critical field for mobility degradation (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{V}{cm}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UEXP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Critical field exponent in mobility degradation (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UTRA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transverse field coeff. (mobility) (deleted for MOS2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VMAX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum drift velocity of carriers \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{m}{s}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NEFF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Total channel-charge (fixed and mobile) coefficient (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-26 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELTA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width effect on threshold voltage (MOS2 and MOS3) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility modulation (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Static feedback (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KAPPA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation field factor (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection BSIM Models \end_layout \begin_layout Standard Ngspice implements many of the BSIM models developed by Berkeley's device group. BSIM stands for Berkeley Short-Channel IGFET Model and groups a class of models that are continuously updated. In general, all parameters of BSIM model are obtained from process characteriza tion, in particular level 4 and level 5 (BSIM1 and BSIM2) parameters are can be generated automatically. J. Pierret [4] describes a means of generating a \begin_inset Quotes eld \end_inset process \begin_inset Quotes erd \end_inset file, and the program \family typewriter ngproc2mod \family default provided with ngspice converts this file into a sequence of BSIM1 \begin_inset Quotes erd \end_inset \family typewriter .model \family default \begin_inset Quotes erd \end_inset lines suitable for inclusion in an ngspice input file. \end_layout \begin_layout Standard Parameters marked below with an \family typewriter * \family default in the \family typewriter l/w \family default column also have corresponding parameters with a length and width dependency. For example, \family typewriter \series bold vfb \family default \series default is the basic parameter with units of Volts, and \family typewriter \series bold lvfb \family default \series default and \family typewriter \series bold wvfb \family default \series default also exist and have units of Volt-meter. \end_layout \begin_layout Standard The formula \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} P=P_{0}+\frac{P_{L}}{L_{{\rm effective}}}+\frac{P_{W}}{W_{{\rm effective}}}\end{equation} \end_inset \end_layout \begin_layout Standard is used to evaluate the parameter for the actual device specified with \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{{\rm effective}}=L_{{\rm input}}-DL\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} W_{{\rm effective}}=W_{{\rm input}}-DW\end{equation} \end_inset \end_layout \begin_layout Standard Note that unlike the other models in ngspice, the BSIM models are designed for use with a process characterization system that provides all the parameters , thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes[3]. For more information on BSIM2, see reference [5]. \end_layout \begin_layout Subsection BSIM1 model (level 4) \end_layout \begin_layout Standard BSIM1 model (the first is a long series) is an empirical model. Developers placed less emphasis on device physics and based the model on parametrical polynomial equations to model the various physical effects. This approach pays in terms of circuit simulation behavior but the accuracy degrades in the submicron region. A known problem of this model is the negative output conductance and the convergence problems, both related to poor behavior of the polynomial equations. \end_layout \begin_layout Subsubsection* Ngspice BSIM (level 4) parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold l/w \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VFB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flat-band voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface inversion potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Body effect coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain/source depletion charge-sharing coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias drain-induced barrier-lowering coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MUZ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Shortening of channel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Narrowing of channel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias transverse-field mobility degradation coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias velocity saturation coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2MZ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to substrate bias at v=0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2E \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of drain-induced barrier lowering effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3E \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of drain-induced barrier lowering effect to drain bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2U0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of transverse field mobility degradation effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of velocity saturation effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu m}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MUS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility at zero substrate bias and at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2MS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to substrate bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3MS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to drain bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of velocity saturation effect on drain bias at Vds=Vdd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu m}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TOX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate oxide thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature at which parameters were measured \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Measurement bias range \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGDO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-drain overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGSO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-source overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGBO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-bulk overlap capacitance per meter channel length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XPART \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-oxide capacitance-charge model flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias subthreshold slope coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of subthreshold slope to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ND \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of subthreshold slope to drain bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain and source diffusion sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction current density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Built in potential of source drain junction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grading coefficient of source drain junction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PBSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Built in potential of source, drain junction sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grading coefficient of source drain junction sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction capacitance per unit area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout source drain junction sidewall capacitance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout WDF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction default width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction length reduction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \family typewriter \series bold xpart \family default \series default = 0 selects a 40/60 drain/source charge partition in saturation, while \family typewriter \series bold xpart \family default \series default =1 selects a 0/100 drain/source charge partition. \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , and \family typewriter \series bold ns \family default \series default are the drain, gate, and source nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default is the area factor, and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using \family typewriter \series bold ic=vds,vgs \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better way to set initial conditions. \end_layout \begin_layout Subsection BSIM2 model (level 5) \end_layout \begin_layout Standard This model contains many improvements over BSIM1 and is suitable for analog simulation. Nevertheless, even BSIM2 breaks transistor operation into several distinct regions and this leads to discontinuities in the first derivative in C-V and I-V characteristics that can cause numerical problems during simulation. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:BSIM3-model" \end_inset BSIM3 model (levels 8, 49) \end_layout \begin_layout Standard BSIM3 solves the numerical problems of previous models with the introduction of smoothing functions. It adopts a single equation to describe device characteristics in the operating regions. This approach eliminates the discontinuities in the I-V and C-V characteristics. The original model, BSIM3 evolved through three versions: BSIM3v1, BSIM3v2 and BSIM3v3. Both BSIM3v1 and BSIM3v2 had suffered from many mathematical problems and were replaced by BSIM3v3. The latter is the only surviving release and has itself a long revision history \end_layout \begin_layout Standard The following table summarizes the story of this model: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Release \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Date \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10/30/1995 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 12/09/1996 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 06/16/1998 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Two minor revisions available: BSIM3v3.2.1 and BSIM3v3.2.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 07/29/2005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parallel processing with OpenMP is available for this model. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard BSIM3v2 and 3v3 models has proved for accurate use in 0.18 \begin_inset Formula $\mu m$ \end_inset technologies. The model is publicly available in source code form from University of California, Berkeley at \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://www-device.eecs.berkeley.edu/~bsim3/get.html" \end_inset . \end_layout \begin_layout Standard A detailed description is given in the user's manual available at \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://www-device.eecs.berkeley.edu/~bsim3/ftpv330/Mod_doc/b3v33manu.tar" \end_inset . \end_layout \begin_layout Standard We recommend that you use only the most recent BSIM3 model (version 3.3.0), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to \end_layout \begin_layout Standard \family typewriter VERSION = 3.3.0 \family default . \end_layout \begin_layout Standard The older models will not be supported, they are made available for reference only. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:BSIM4-model" \end_inset BSIM4 model (levels 14, 54) \end_layout \begin_layout Standard This is the newest class of the BSIM family and introduces noise modeling and extrinsic parasitics. BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub-100nm regime. It is a physics-based, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley (see \begin_inset CommandInset href LatexCommand href name "BSIM4 home page" target "http://www-device.eecs.berkeley.edu/~bsim3/bsim4_get.html " \end_inset ). BSIM4 has a long revision history, which is summarized below. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Release \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Date \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Version flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 03/24/2000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10/11/2000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 04/06/2001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.2.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10/05/2001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.2.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 05/09/2003 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.4.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 03/04/2004 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.4.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 07/29/2005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.6.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 12/13/2006 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ... \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.6.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 09/09/2009 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.6.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.7.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 04/08/2011 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.7 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard *) supported in ngspice, using e.g. the \family typewriter version= \family default flag in the parameter file. \end_layout \begin_layout Standard **) Parallel processing using OpenMP support is available for this model. \end_layout \begin_layout Standard Details of any revision are to be found in the Berkeley user's manuals, a pdf download of the most recent edition is to be found \begin_inset CommandInset href LatexCommand href name "here" target "http://www-device.eecs.berkeley.edu/~bsim3/BSIM4/BSIM470/BSIM470_Manual.pdf" \end_inset . \end_layout \begin_layout Standard We recommend that you use only the most recent BSIM4 model (version 4.7.0), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to \end_layout \begin_layout Standard \family typewriter VERSION = 4. \family default 7. \end_layout \begin_layout Standard The older models will typically not be supported, they are made available for reference only. \end_layout \begin_layout Subsection EKV model \end_layout \begin_layout Standard Level 44 model (EKV) is not available in the standard distribution since it is not released in source form by the EKV group. To obtain the code please refer to the ( \begin_inset CommandInset href LatexCommand href name "EKV model home page" target "http://ekv.epfl.ch/" \end_inset , EKV group home page). A verilog-A version is available contributed by Ivan Riis Nielsen 11/2006. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:BSIMSOI-models" \end_inset BSIMSOI models (levels 10, 58, 55, 56, 57) \end_layout \begin_layout Standard BSIMSOI is a SPICE compact model for SOI (Silicon-On-Insulator) circuit design. This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are retained. Four models are supported in ngspice, those based on BSIM3 and modeling fully depleted (FD, level 55), partially depleted (PD, level 57) and both (DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10, 58). Detailed descriptions are beyond the scope of this manual, but see e.g. \begin_inset CommandInset href LatexCommand href name "BSIMSOI_4.3.1_Users_manual" target "http://www-device.eecs.berkeley.edu/~bsimsoi/archive/bsimsoi4p31/BSIMSOI_4.3.1_Users_manual.pdf" \end_inset for a very extensive description of the recent model version. OpenMP support is available for levels 10, 58, version 4.3.1. \end_layout \begin_layout Subsection SOI3 model (level 60) \end_layout \begin_layout Standard see literature citation [18] for a description. \end_layout \begin_layout Subsection HiSIM models of the University of Hiroshima \end_layout \begin_layout Standard There are two model implementations available - see also \begin_inset CommandInset href LatexCommand href name "HiSIM Research Center" target "http://www.hisim.hiroshima-u.ac.jp/" \end_inset : \end_layout \begin_layout Enumerate HiSIM2 model: Surface-Potential-Based MOSFET Model for Circuit Simulation version 2.5.1 - level 61 (see \begin_inset CommandInset href LatexCommand href name "link to HiSIM2" target "http://home.hiroshima-u.ac.jp/usdl/HiSIM2/HiSIM_2.5.1_Release_20110407.zip" \end_inset for source code and manual). \end_layout \begin_layout Enumerate HiSIM_HV model: Surface-Potential-Based HV/LD-MOSFET Model for Circuit Simulatio n version 1.2.2 - level 62 (see \begin_inset CommandInset href LatexCommand href name "link to HiSIM_HV" target "http://home.hiroshima-u.ac.jp/usdl/HiSIM_HV/C-Code/HiSIM_HV_1.2.2_Release_20110629.zip" \end_inset for source code and manual). \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Behavioral-Modeling" \end_inset Mixed-Mode and Behavioral Modeling with XSPICE \end_layout \begin_layout Standard Ngspice implements XSPICE extensions for behavioral and mixed-mode (analog and digital) modeling. In the XSPICE framework this is referred to as code level modeling. Behavioral modelling may benefit dramatically because XSPICE offers a means to add analog functionality programmed in C. Many examples (amplifiers, oscillators, filters ...) are presented in the following. Even more flexibility is available because you may define your own models and use them in addition and in combination with all the already existing ngspice functionality. Mixed mode simulation is speeded up significantly by simulating the digital part in an event driven manner, in that state equations use only a few allowed states and are evaluated only during switching, and not continuously in time and signal as in a pure analog simulator. \end_layout \begin_layout Standard This chapter describes the predefined models available in ngspice, stemming from the original XSPICE simulator. The instructions for writing new code models are given in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" \end_inset . \end_layout \begin_layout Standard To make use of the XSPICE extensions, you need to compile them in. LINUX, CYGWIN, MINGW and other users may add the flag \family typewriter --enable-xspice \family default to their \family typewriter ./configure \family default command and then recompile. The prebuilt ngspice for Windows distribution has XSPICE already enabled. For detailed compiling instructions see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" \end_inset . \end_layout \begin_layout Section Code Model Element & .MODEL Cards \end_layout \begin_layout Standard Ngspice includes a library of predefined \begin_inset Quotes eld \end_inset Code Models \begin_inset Quotes erd \end_inset that can be placed within any circuit description in a manner similar to that used to place standard device models. Code model instance cards always begin with the letter \begin_inset Quotes eld \end_inset A \begin_inset Quotes erd \end_inset , and always make use of a .MODEL card to describe the code model desired. Section of this document goes into greater detail as to how a code model similar to the predefined models may be developed, but once any model is created and linked into the simulator it may be placed using one instance card and one .MODEL card (note here we conform to the SPICE custom of referring to a single logical line of information as a \begin_inset Quotes eld \end_inset card \begin_inset Quotes erd \end_inset ). As an example, the following uses the predefined \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset code model which takes as an input some value on node 1, multiplies it by a gain of 5.0, and outputs the new value to node 2. Note that, by convention, input ports are specified first on code models. Output ports follow the inputs. \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout a1 1 2 amp \end_layout \begin_layout Plain Layout .model amp gain(gain=5.0) \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \end_inset \end_layout \begin_layout Standard In this example the numerical values picked up from single-ended (i.e. ground referenced) input node 1 and output to single-ended output node 2 will be voltages, since in the Interface Specification File for this code model (i.e., gain), the default port type is specified as a voltage (more on this later). However, if you didn't know this, the following modifications to the instance card could be used to insure it: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout a1 %v(1) %v(2) amp \end_layout \begin_layout Plain Layout .model amp gain(gain=5.0) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The specification "%v" preceding the input and output node numbers of the instance card indicate to the simulator that the inputs to the model should be single-ended voltage values. Other possibilities exist, as described later. \end_layout \begin_layout Standard Some of the other features of the instance and .MODEL cards are worth noting. Of particular interest is the portion of the .MODEL card which specifies \family typewriter gain=5.0 \family default . This portion of the card assigns a value to a parameter of the "gain" model. There are other parameters which can be assigned values for this model, and in general code models will have several. In addition to numeric values, code model parameters can take non-numeric values (such as TRUE and FALSE), and even vector values. All of these topics will be discussed at length in the following pages. In general, however, the instance and .MODEL cards which define a code model will follow the abstract form described below. This form illustrates that the number of inputs and outputs and the number of parameters which can be specified is relatively open-ended and can be interpreted in a variety of ways (note that angle-brackets \begin_inset Quotes eld \end_inset < \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset > \begin_inset Quotes erd \end_inset enclose optional inputs): \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout AXXXXXXX <%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d> \end_layout \begin_layout Plain Layout + <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d> \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + <~>... > \end_layout \begin_layout Plain Layout + <%v,%i,%vd,%id,%g,%gd,%h,%hd,%d or %vname> \end_layout \begin_layout Plain Layout + <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, \end_layout \begin_layout Plain Layout or %d> \end_layout \begin_layout Plain Layout + <~>...> \end_layout \begin_layout Plain Layout + MODELNAME \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MODEL MODELNAME MODELTYPE \end_layout \begin_layout Plain Layout + <( PARAMNAME1= <[> VAL1 > PARAMNAME2..>)> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Square brackets ([ ]) are used to enclose vector input nodes. In addition, these brackets are used to delineate vectors of parameters. \end_layout \begin_layout Standard The literal string \begin_inset Quotes eld \end_inset null \begin_inset Quotes erd \end_inset , when included in a node list, is interpreted as no connection at that input to the model. "Null" is not allowed as the name of a model's input or output if the model only has one input or one output. Also, \begin_inset Quotes eld \end_inset null \begin_inset Quotes erd \end_inset should only be used to indicate a missing connection for a code model; use on other XSPICE component is not interpreted as a missing connection, but will be interpreted as an actual node name. \end_layout \begin_layout Standard The tilde, \begin_inset Quotes eld \end_inset ~ \begin_inset Quotes erd \end_inset , when prepended to a digital node name, specifies that the logical value of that node be inverted prior to being passed to the code model. This allows for simple inversion of input and output polarities of a digital model in order to handle logically equivalent cases and others that frequently arise in digital system design. The following example defines a NAND gate, one input of which is inverted: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout a1 [~1 2] 3 nand1 \end_layout \begin_layout Plain Layout .model nand1 d_nand (rise_delay=0.1 fall_delay=0.2) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The optional symbols %v, %i, %vd, etc. specify the type of port the simulator is to expect for the subsequent port or port vector. The meaning of each symbol is given in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Type-Modifiers" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Port Type Modifiers \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modifier \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Interpretation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %v \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended voltage port - one node name or number is expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended current port - one node name or number \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit is expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %g \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended voltage-input, current-output (VCCS) port - one node name or number is expected for each port. This type of port is automatically an input/output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended current-input, voltage-output (CCVS) port - one node name or number is expected for each port. This type of port is automatically an input/output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %d \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a digital port - one node name or number is expected for each port. This type of port may be either an input or an output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %vnam \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents the name of a voltage source, the current through which is taken as an input. This notation is provided primarily in order to allow models defined using SPICE2G6 syntax to operate properly in XSPICE. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %vd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential voltage port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %id \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential current port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %gd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential VCCS port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %hd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential CCVS port - two node names or numbers \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit are expected for each port. \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Port-Type-Modifiers" \end_inset Port Type Modifiers \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The symbols described in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Type-Modifiers" \end_inset may be omitted if the default port type for the model is desired. Note that non-default port types for multi-input or multi-output (vector) ports must be specified by placing one of the symbols in front of EACH vector port. On the other hand, if all ports of a vector port are to be declared as having the same non-default type, then a symbol may be specified immediately prior to the opening bracket of the vector. The following examples should make this clear: \end_layout \begin_layout LyX-Code Example 1: - Specifies two differential voltage connections, one \end_layout \begin_layout LyX-Code to nodes 1 & 2, and one to nodes 3 & 4. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %vd [1 2 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 2: - Specifies two single-ended connections to node 1 and \end_layout \begin_layout LyX-Code at node 2, and one differential connection to \end_layout \begin_layout LyX-Code nodes 3 & 4. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %v [1 2 %vd 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 3: - Identical to the previous example...parenthesis \end_layout \begin_layout LyX-Code are added for additional clarity. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %v [1 2 %vd(3 4)] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 4: - Specifies that the node numbers are to be treated in the \end_layout \begin_layout LyX-Code default fashion for the particular model. \end_layout \begin_layout LyX-Code If this model had ``%v'' as a default for this \end_layout \begin_layout LyX-Code port, then this notation would represent four single-ended \end_layout \begin_layout LyX-Code voltage connections. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code [1 2 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout Standard The parameter names listed on the .MODEL card must be identical to those named in the code model itself. The parameters for each predefined code model are described in detail in Sections \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Analog-Models" \end_inset (analog), \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Hybrid-Models" \end_inset (Hybrid, A/D) and \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Digital-Models" \end_inset (digital) . The steps required in order to specify parameters for user-defined models are described in Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" \end_inset . \end_layout \begin_layout Standard The following is a list of instance card and associated .MODEL card examples showing use of predefined models within an XSPICE deck: \end_layout \begin_layout LyX-Code a1 1 2 amp \end_layout \begin_layout LyX-Code .model amp gain(in_offset=0.1 gain=5.0 out_offset=-0.01) \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a2 %i[1 2] 3 sum1 \end_layout \begin_layout LyX-Code .model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0] \end_layout \begin_layout LyX-Code + out_gain=5.0 out_offset=-0.01) \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a21 %i[1 %vd(2 5) 7 10] 3 sum2 \end_layout \begin_layout LyX-Code .model sum2 summer(out_gain=10.0) \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a5 1 2 limit5 .model limit5 limit(in_offset=0.1 gain=2.5 \end_layout \begin_layout LyX-Code + out_lower.limit=-5.0 out_upper_limit=5.0 limit_domain=0.10 \end_layout \begin_layout LyX-Code + fraction=FALSE) \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a7 2 %id(4 7) xfer.cntl1 \end_layout \begin_layout LyX-Code .model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + input_domain=0.05 fraction=TRUE) \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a8 3 %gd(6 7) switch3 \end_layout \begin_layout LyX-Code .model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6 \end_layout \begin_layout LyX-Code + r_on=10.0 log=TRUE) \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:XSPICE-Analog-Models" \end_inset Analog Models \end_layout \begin_layout Standard The following analog models are supplied with XSPICE. The descriptions included consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the .MODEL card and the specification of all available parameters. \end_layout \begin_layout Subsection Gain \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\small}" inline false status open \begin_layout Plain Layout NAME_TABLE: \end_layout \begin_layout Plain Layout C_Function_Name: cm_gain \end_layout \begin_layout Plain Layout Spice_Model_Name: gain \end_layout \begin_layout Plain Layout Description: "A simple gain block" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout PORT_TABLE: \end_layout \begin_layout Plain Layout Port Name: in out \end_layout \begin_layout Plain Layout Description: "input" "output" \end_layout \begin_layout Plain Layout Direction: in out \end_layout \begin_layout Plain Layout Default_Type: v v \end_layout \begin_layout Plain Layout Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout Plain Layout Vector: no no \end_layout \begin_layout Plain Layout Vector.Bounds: - - \end_layout \begin_layout Plain Layout Null.Allowed: no no \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout PARAMETER_TABLE: \end_layout \begin_layout Plain Layout Parameter_Name: in_offset gain out_offset \end_layout \begin_layout Plain Layout Description: "input offset" "gain" "output offset" \end_layout \begin_layout Plain Layout Data_Type: real real real \end_layout \begin_layout Plain Layout Default_Value: 0.0 1.0 0.0 \end_layout \begin_layout Plain Layout Limits: - - - \end_layout \begin_layout Plain Layout Vector: no no no \end_layout \begin_layout Plain Layout Vector_Bounds: - - - \end_layout \begin_layout Plain Layout Null_Allowed: yes yes yes \end_layout \end_inset \end_layout \begin_layout Description Description: This function is a simple gain block with optional offsets on the input and the output. The input offset is added to the input, the sum is then multiplied by the gain, and the result is produced by adding the output offset. This model will operate in DC, AC, and Transient analysis modes. \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout a1 1 2 amp \end_layout \begin_layout Plain Layout .model amp gain(in_offset=0.1 gain=5.0 \end_layout \begin_layout Plain Layout + out_offset=-0.01) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Summer \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout NAME_TABLE: \end_layout \begin_layout Plain Layout C_Function_Name: cm_summer \end_layout \begin_layout Plain Layout Spice_Model_Name: summer \end_layout \begin_layout Plain Layout Description: "A summer block" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout PORT_TABLE: \end_layout \begin_layout Plain Layout Port Name: in out \end_layout \begin_layout Plain Layout Description: "input vector" "output" \end_layout \begin_layout Plain Layout Direction: in out \end_layout \begin_layout Plain Layout Default_Type: v v \end_layout \begin_layout Plain Layout Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout Plain Layout Vector: yes no \end_layout \begin_layout Plain Layout Vector_Bounds: - - \end_layout \begin_layout Plain Layout Null_Allowed: no no \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout PARAMETER_TABLE: \end_layout \begin_layout Plain Layout Parameter_Name: in_offset in_gain \end_layout \begin_layout Plain Layout Description: "input offset vector" "input gain vector" \end_layout \begin_layout Plain Layout Data_Type: real real \end_layout \begin_layout Plain Layout Default_Value: 0.0 1.0 \end_layout \begin_layout Plain Layout Limits: - - \end_layout \begin_layout Plain Layout Vector: yes yes \end_layout \begin_layout Plain Layout Vector_Bounds: in in \end_layout \begin_layout Plain Layout Null_Allowed: yes yes \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout PARAMETER_TABLE: \end_layout \begin_layout Plain Layout Parameter_Name: out_gain out_offset \end_layout \begin_layout Plain Layout Description: "output gain" "output offset" \end_layout \begin_layout Plain Layout Data_Type: real real \end_layout \begin_layout Plain Layout Default_Value: 1.0 0.0 \end_layout \begin_layout Plain Layout Limits: - - \end_layout \begin_layout Plain Layout Vector: no no \end_layout \begin_layout Plain Layout Vector_Bounds: - - \end_layout \begin_layout Plain Layout Null_Allowed: yes yes \end_layout \end_inset \end_layout \begin_layout Description Description: This function is a summer block with 2-to-N input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are then summed, multiplied by the output gain and added to the output offset. This model will operate in DC, AC, and Transient analysis modes. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a2 [1 2] 3 sum1 \end_layout \begin_layout Plain Layout .model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0] \end_layout \begin_layout Plain Layout + out_gain=5.0 out_offset=-0.01) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Multiplier \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_mult \end_layout \begin_layout LyX-Code Spice_Model_Name: mult \end_layout \begin_layout LyX-Code Description: "multiplier block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input vector" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset in_gain \end_layout \begin_layout LyX-Code Description: "input offset vector" "input gain vector" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: in in \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_gain out_offset \end_layout \begin_layout LyX-Code Description: "output gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a multiplier block with 2-to-N input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are multiplied along with the output gain and are added to the output offset. This model will operate in DC, AC, and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only ONE INPUT of the multiplier is connected to a node which bears an AC signal (this is exemplified by the use of a multiplier to perform a potentiometer function: one input is DC, the other carries the AC signal). \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example SPICE Usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a3 [1 2 3] 4 sigmult \end_layout \begin_layout Plain Layout .model sigmult mult(in_offset=[0.1 0.1 -0.1] \end_layout \begin_layout Plain Layout + in_gain=[10.0 10.0 10.0] out_gain=5.0 out_offset=0.05) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Divider \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_divide \end_layout \begin_layout LyX-Code Spice_Model_Name: divide \end_layout \begin_layout LyX-Code Description: "divider block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: num den out \end_layout \begin_layout LyX-Code Description: "numerator" "denominator" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: v v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_offset num_gain \end_layout \begin_layout LyX-Code Description: "numerator offset" "numerator gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_offset den_gain \end_layout \begin_layout LyX-Code Description: "denominator offset" "denominator gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_lower_limit \end_layout \begin_layout LyX-Code Description: "denominator lower limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-10 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_domain \end_layout \begin_layout LyX-Code Description: "denominator smoothing domain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-10 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: false \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_gain out_offset \end_layout \begin_layout LyX-Code Description: "output gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a two-quadrant divider. It takes two inputs; num (numerator) and den (denominator). Divide offsets its inputs, multiplies them by their respective gains, divides the results, multiplies the quotient by the output gain, and offsets the result. The denominator is limited to a value above zero via a user specified lower limit. This limit is approached through a quadratic smoothing function, the domain of which may be specified as a fraction of the lower limit value (default), or as an absolute value. This model will operate in DC, AC and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only ONE INPUT of the divider is connected to a node which bears an AC signal (this is exemplified by the use of the divider to perform a potentiometer function: one input is DC, the other carries the AC signal). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 1 2 4 divider \end_layout \begin_layout LyX-Code .model divider divide(num_offset=0.1 num_gain=2.5 den_offset=-0.1 \end_layout \begin_layout LyX-Code + den_gain=5.0 den_lower.limit=1e-5 den_domain=1e-6 \end_layout \begin_layout LyX-Code + fraction=FALSE out_gain=1.0 out_offset=0.0) \end_layout \begin_layout Subsection Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_limit \end_layout \begin_layout LyX-Code Spice_Model_Name: limit \end_layout \begin_layout LyX-Code Description: "limit block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC and Transient analysis modes. Note that the limit range is the value BELOW THE UPPER LIMIT AND ABOVE THE LOWER LIMIT at which smoothing of the output begins. For this model, then, the limit range represents the delta WITH RESPECT TO THE OUTPUT LEVEL at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output will begin to smooth out at \begin_inset Formula $\pm$ \end_inset 0.9 volts, which occurs when the input value is at \begin_inset Formula $\pm$ \end_inset 0.4. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a5 1 2 limit5 \end_layout \begin_layout LyX-Code .model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=-5.0 \end_layout \begin_layout LyX-Code + out_upper_limit=5.0 limit_range=0.10 fraction=FALSE) \end_layout \begin_layout Subsection Controlled Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_climit \end_layout \begin_layout LyX-Code Spice_Model_Name: climit \end_layout \begin_layout LyX-Code Description: "controlled limiter block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in cntl_upper \end_layout \begin_layout LyX-Code Description: "input" "upper lim. control input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: cntl_lower out \end_layout \begin_layout LyX-Code Description: "lower limit control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: upper_delta lower_delta \end_layout \begin_layout LyX-Code Description: "output upper delta" "output lower delta" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range fraction \end_layout \begin_layout LyX-Code Description: "upper & lower sm. range" "smoothing %/abs switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The Controlled Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC, and Transient analysis modes. Note that the limit range is the value BELOW THE CNTL_UPPER LIMIT AND ABOVE THE CNTL_LOWER LIMIT at which smoothing of the output begins (minimum positive value of voltage must exist between the CNTL_UPPER input and the CNTL_LOWER input at all times). For this model, then, the limit range represents the delta WITH RESPECT TO THE OUTPUT LEVEL at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output will begin to smooth out at \begin_inset Formula $\pm$ \end_inset 0.9 volts, which occurs when the input value is at \begin_inset Formula $\pm$ \end_inset 0.4. Note also that the Controlled Limiter code tests the input values of cntl_lower and cntl_upper to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between (cntl_upper - upper_delta - limit_range) and (cntl_lower + lower_delta + limit_range) and must be greater than or equal to zero. Note that when the limit range is specified as a fractional value, the limit range used in the above is taken as the calculated fraction of the difference between cntl upper and cntl lower. Still, the potential exists for too great a limit range value to be specified for proper operation, in which case the model will return an error message. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 3 6 8 4 varlimit \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0 \end_layout \begin_layout LyX-Code + lower_delta=0.0 limit_range=0.10 fraction=FALSE) \end_layout \begin_layout Subsection PWL Controlled Source \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_pwl \end_layout \begin_layout LyX-Code Spice_Model_Name: pwl \end_layout \begin_layout LyX-Code Description: "piecewise linear controlled source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: x_array y_array \end_layout \begin_layout LyX-Code Description: "x-element array" "y-element array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_domain fraction \end_layout \begin_layout LyX-Code Description: "input sm. domain" "smoothing %/abs switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 0.01 TRUE \end_layout \begin_layout LyX-Code Limits: [1e-12 0.5] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: last_x_value \end_layout \begin_layout LyX-Code Data_Type: pointer Description: "iteration holding \end_layout \begin_layout LyX-Code variable for limiting" \end_layout \begin_layout Description Description: The Piece-Wise Linear Controlled Source is a single input, single output function similar to the Gain Block. However, the output of the PWL Source is not necessarily linear for all values of input. Instead, it follows an I/O relationship specified by you via the x_array and y_array coordinates. This is detailed below. \begin_inset Newline newline \end_inset The x_array and y_array values represent vectors of coordinate points on the x and y axes, respectively. The x_array values are progressively increasing input coordinate points, and the associated y_array values represent the outputs at those points. There may be as few as two (x_array[n], y_array[n]) pairs specified, or as many as memory and simulation speed allow. This permits you to very finely approximate a non-linear function by capturing multiple input-output coordinate points. \begin_inset Newline newline \end_inset Two aspects of the PWL Controlled Source warrant special attention. These are the handling of endpoints and the smoothing of the described transfer function near coordinate points. \begin_inset Newline newline \end_inset In order to fully specify outputs for values of \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset outside of the bounds of the PWL function (i.e., less than x_array[0] or greater than x_array[n], where n is the largest user-specified coordinate index), the PWL Controlled Source model extends the slope found between the lowest two coordinate pairs and the highest two coordinate pairs. This has the effect of making the transfer function completely linear for \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset less than x_array[0] and \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset greater than x_array[n]. It also has the potentially subtle effect of unrealistically causing an output to reach a very large or small value for large inputs. You should thus keep in mind that the PWL Source does not inherently provide a limiting capability. \begin_inset Newline newline \end_inset In order to diminish the potential for non-convergence of simulations when using the PWL block, a form of smoothing around the x_array, y_array coordinate points is necessary. This is due to the iterative nature of the simulator and its reliance on smooth first derivatives of transfer functions in order to arrive at a matrix solution. Consequently, the \begin_inset Quotes eld \end_inset input_domain \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset fraction \begin_inset Quotes erd \end_inset parameters are included to allow you some control over the amount and nature of the smoothing performed. \begin_inset Newline newline \end_inset \begin_inset Quotes eld \end_inset Fraction \begin_inset Quotes erd \end_inset is a switch that is either TRUE or FALSE. When TRUE (the default setting), the simulator assumes that the specified input domain value is to be interpreted as a fractional figure. Otherwise, it is interpreted as an absolute value. Thus, if fraction=TRUE and input_domain=0.10, The simulator assumes that the smoothing radius about each coordinate point is to be set equal to 10% of the length of either the x_array segment above each coordinate point, or the x_array segment below each coordinate point. The specific segment length chosen will be the smallest of these two for each coordinate point. \begin_inset Newline newline \end_inset On the other hand, if fraction=FALSE and input=0.10, then the simulator will begin smoothing the transfer function at 0.10 volts (or amperes) below each x_array coordinate and will continue the smoothing process for another 0.10 volts (or amperes) above each x_array coordinate point. Since the overlap of smoothing domains is not allowed, checking is done by the model to ensure that the specified input domain value is not excessive. \begin_inset Newline newline \end_inset One subtle consequence of the use of the fraction=TRUE feature of the PWL Controlled Source is that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by considering a function described by three coordinat e pairs, such as (-1,-1), (1,1), and (2,1). In this case, with a 10% input_domain value specified (fraction=TRUE, input domain=0.10), you would expect to see rounding occur between in=0.9 and in=1.1, and nowhere else. On the other hand, if you were to specify the same function using the coordinat e pairs (-100,-100), (1,1) and (201,1), you would find that rounding occurs between in=-19 and in=21. Clearly in the latter case the smoothing might cause an excessive divergence from the intended linearity above and below in=1. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a7 2 4 xfer_cntl1 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + input_domain=0.05 fraction=TRUE) \end_layout \begin_layout Subsection Filesource \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code C_Function_Name: cm_filesource \end_layout \begin_layout LyX-Code Spice_Model_Name: filesource \end_layout \begin_layout LyX-Code Description: "File Source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: timeoffset timescale \end_layout \begin_layout LyX-Code Description: "time offset" "timescale" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: timerelative amplstep \end_layout \begin_layout LyX-Code Description: "relative time" "step amplitude" \end_layout \begin_layout LyX-Code Data_Type: boolean boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: amploffset amplscale \end_layout \begin_layout LyX-Code Description: "ampl offset" "amplscale" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: file \end_layout \begin_layout LyX-Code Description: "file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "filesource.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The File Source is similar to the Piece-Wise Linear Source, except that the waveform data is read from a file instead of being taken from parameter vectors. \begin_inset Newline newline \end_inset The file format is line oriented ASCII. # and ; are comment characters; all characters from a comment character until the end of the line are ignored. \begin_inset Newline newline \end_inset Each line consists of two or more real values. The first value is the time; subsequent values correspond to the outputs. Values are separated by spaces. \begin_inset Newline newline \end_inset Time values are absolute and must be monotonically increasing, unless timerelati ve is set to TRUE, in which case the values specify the interval between two samples and must be positive. Waveforms may be scaled and shifted in the time dimension by setting timescale and timeoffset. \begin_inset Newline newline \end_inset Amplitudes can also be scaled and shifted using amplscale and amploffset. Amplitudes are normally interpolated between two samples, unless amplstep is set to TRUE. \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 %vd([1 0 2 0]) filesrc \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1] \end_layout \begin_layout LyX-Code + timeoffset=0 timescale=1 \end_layout \begin_layout LyX-Code + timerelative=false amplstep=false) \end_layout \begin_layout LyX-Code \begin_inset VSpace 1cm \end_inset \end_layout \begin_layout LyX-Code Example input file: \end_layout \begin_layout LyX-Code # name: sine.m \end_layout \begin_layout LyX-Code # two output ports \end_layout \begin_layout LyX-Code # column 1: time \end_layout \begin_layout LyX-Code # columns 2, 3: values \end_layout \begin_layout LyX-Code 0 0 1 \end_layout \begin_layout LyX-Code 3.90625e-09 0.02454122852291229 0.9996988186962042 \end_layout \begin_layout LyX-Code 7.8125e-09 0.04906767432741801 0.9987954562051724 \end_layout \begin_layout LyX-Code 1.171875e-08 0.07356456359966743 0.9972904566786902 \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection multi_input_pwl block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code C_Function_Name: cm_multi_input_pwl \end_layout \begin_layout LyX-Code Spice_Model_Name: multi_input_pwl \end_layout \begin_layout LyX-Code Description: "multi_input_pwl block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input array" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: vd vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd,id] [vd,id] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: x y \end_layout \begin_layout LyX-Code Description: "x array" "y array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: model \end_layout \begin_layout LyX-Code Description: "model type" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "and" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: Multi-input gate voltage controlled voltage source that supports \series bold and \series default or \series bold or \series default gating. The x's and y's represent the piecewise linear variation of output (y) as a function of input (x). Only one input determines the state of the outputs, seleczable by the parameter \family typewriter model \family default . \series bold and \series default : the smallest value of all the inputs is chosen as the controlling input and determines the output value, \series bold or \series default : the smallest value of all the inputs is chosen as the controlling input and determines the output value. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a82 [1 0 2 0 3 0] 7 0 pwlm \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model pwlm multi_input_pwl((x_array=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + model="and") \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Analog Switch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_aswitch \end_layout \begin_layout LyX-Code Spice_Model_Name: aswitch \end_layout \begin_layout LyX-Code Description: "analog switch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "input" "resistive output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v gd \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_off cntl_on \end_layout \begin_layout LyX-Code Description: "control `off' value" "control `on' value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_off log \end_layout \begin_layout LyX-Code Description: "off resistance" "log/linear switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e12 TRUE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_on \end_layout \begin_layout LyX-Code Description: "on resistance" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Analog Switch is a resistor that varies either logarithmically or linearly between specified values of a controlling input voltage or current. Note that the input is not internally limited. Therefore, if the controlling signal exceeds the specified OFF state or ON state value, the resistance may become excessively large or excessively small (in the case of logarithmic dependence), or may become negative (in the case of linear dependence). For the experienced user, these excursions may prove valuable for modeling certain devices, but in most cases you are advised to add limiting of the controlling input if the possibility of excessive control value variation exists. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a8 3 (6 7) switch3 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6 \end_layout \begin_layout LyX-Code + r_on=10.0 log=TRUE) \end_layout \begin_layout Subsection Zener Diode \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_zener \end_layout \begin_layout LyX-Code Spice_Model_Name: zener \end_layout \begin_layout LyX-Code Description: "zener diode" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: z \end_layout \begin_layout LyX-Code Description: "zener" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: v_breakdown i_breakdown \end_layout \begin_layout LyX-Code Description: "breakdown voltage" "breakdown current" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - 2.0e-2 \end_layout \begin_layout LyX-Code Limits: [1.0e-6 1.0e6] [1.0e-9 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_sat n_forward \end_layout \begin_layout LyX-Code Description: "saturation current" "forward emission coefficient" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] [0.1 10] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_switch \end_layout \begin_layout LyX-Code Description: "switch for on-board limiting (convergence aid)" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: previous_voltage \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Description: "iteration holding variable for limiting" \end_layout \begin_layout Description Description: The Zener Diode models the DC characteristics of most zeners. This model differs from the Diode/Rectifier by providing a user-defined dynamic resistance in the reverse breakdown region. The forward characteristic is defined by only a single point, since most data sheets for zener diodes do not give detailed characteristics in the forward region. \begin_inset Newline newline \end_inset The first three parameters define the DC characteristics of the zener in the breakdown region and are usually explicitly given on the data sheet. \begin_inset Newline newline \end_inset The saturation current refers to the relatively constant reverse current that is produced when the voltage across the zener is negative, but breakdown has not been reached. The reverse leakage current determines the slight increase in reverse current as the voltage across the zener becomes more negative. It is modeled as a resistance parallel to the zener with value v breakdown / i rev. \begin_inset Newline newline \end_inset Note that the limit switch parameter engages an internal limiting function for the zener. This can, in some cases, prevent the simulator from converging to an unrealisti c solution if the voltage across or current into the device is excessive. If use of this feature fails to yield acceptable results, the convlimit option should be tried (add the following statement to the SPICE input deck: .options convlimit) \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 3 4 vref10 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model vref10 zener(v_breakdown=10.0 i_breakdown=0.02 \end_layout \begin_layout LyX-Code + r_breakdown=1.0 i_rev=1e-6 i_sat=1e-12) \end_layout \begin_layout Subsection Current Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_ilimit \end_layout \begin_layout LyX-Code Spice_Model_Name: ilimit \end_layout \begin_layout LyX-Code Description: "current limiter block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in pos_pwr \end_layout \begin_layout LyX-Code Description: "input" "positive power supply" \end_layout \begin_layout LyX-Code Direction: in inout \end_layout \begin_layout LyX-Code Default_Type: v g \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd] [g,gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: neg_pwr out \end_layout \begin_layout LyX-Code Description: "negative power supply" "output" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: g g \end_layout \begin_layout LyX-Code Allowed_Types: [g,gd] [g,gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_out_source r_out_sink \end_layout \begin_layout LyX-Code Description: "sourcing resistance" "sinking resistance" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 1.0 \end_layout \begin_layout LyX-Code Limits: [1.0e-9 1.0e9] [1.0e-9 1.0e9] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_limit_source \end_layout \begin_layout LyX-Code Description: "current sourcing limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_limit_sink \end_layout \begin_layout LyX-Code Description: "current sinking limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: v_pwr_range i_source_range \end_layout \begin_layout LyX-Code Description: "upper & lower power "sourcing current \end_layout \begin_layout LyX-Code supply smoothing range" smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_sink_range \end_layout \begin_layout LyX-Code Description: "sinking current smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_out_domain \end_layout \begin_layout LyX-Code Description: "internal/external voltage delta smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Current Limiter models the behavior of an operational amplifier or comparator device at a high level of abstraction. All of its pins act as inputs; three of the four also act as outputs. The model takes as input a voltage value from the \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset connector. It then applies an offset and a gain, and derives from it an equivalent internal voltage (veq), which it limits to fall between pos pwr and neg pwr. If veq is greater than the output voltage seen on the \begin_inset Quotes eld \end_inset out \begin_inset Quotes erd \end_inset connector, a sourcing current will flow from the output pin. Conversely, if the voltage is less than vout, a sinking current will flow into the output pin. \begin_inset Newline newline \end_inset Depending on the polarity of the current flow, either a sourcing or a sinking resistance value (r_out_source, r_out_sink) is applied to govern the vout/i_out relationship. The chosen resistance will continue to control the output current until it reaches a maximum value specified by either i_limit_source or i_limit_sink. The latter mimics the current limiting behavior of many operational amplifier output stages. \begin_inset Newline newline \end_inset During all operation, the output current is reflected either in the pos_pwr connector current or the neg_pwr current, depending on the polarity of i_out. Thus, realistic power consumption as seen in the supply rails is included in the model. \begin_inset Newline newline \end_inset The user-specified smoothing parameters relate to model operation as follows: v_pwr_range controls the voltage below vpos_pwr and above vneg_pwr inputs beyond which veq [= gain * (vin + voffset)] is smoothed; i_source_range specifies the current below i_limit_source at which smoothing begins, as well as specifying the current increment above i_out=0.0 at which i_pos_pwr begins to transition to zero; i_sink_range serves the same purpose with respect to i_limit_sink and i_neg_pwr that i_source_range serves for i_limit_so urce & i_pos_pwr; r_out_domain specifies the incremental value above and below (veq-vout)=0.0 at which r_out will be set to r_out_source and r_out_sink, respectively. For values of (veq- vout) less than r_out_domain and greater than -r_out_domain , r_out is interpolated smoothly between r_out_source & r_out_sink. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a10 3 10 20 4 amp3 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0 \end_layout \begin_layout LyX-Code + r_out_sink=1.0 i_limit_source=1e-3 \end_layout \begin_layout LyX-Code + i_limit_sink=10e-3 v_pwr_range=0.2 \end_layout \begin_layout LyX-Code + i_source_range=1e-6 i_sink_range=1e-6 \end_layout \begin_layout LyX-Code + r_out_domain=1e-6) \end_layout \begin_layout Subsection Hysteresis Block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_hyst \end_layout \begin_layout LyX-Code Spice_Model_Name: hyst \end_layout \begin_layout LyX-Code Description: "hysteresis block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low in_high \end_layout \begin_layout LyX-Code Description: "input low value" "input high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: hyst out_lower_limit \end_layout \begin_layout LyX-Code Description: "hysteresis" "output lower limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.1 0.0 \end_layout \begin_layout LyX-Code Limits: [0.0 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_upper_limit input_domain \end_layout \begin_layout LyX-Code Description: "output upper limit" "input smoothing domain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.01 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Hysteresis block is a simple buffer stage that provides hysteresis of the output with respect to the input. The in low and in high parameter values specify the center voltage or current inputs about which the hysteresis effect operates. The output values are limited to out lower limit and out upper limit. The value of \begin_inset Quotes eld \end_inset hyst \begin_inset Quotes erd \end_inset is added to the in low and in high points in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a low to a high value. Likewise, the value of \begin_inset Quotes eld \end_inset hyst \begin_inset Quotes erd \end_inset is subtracted from the in high and in low values in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a high to a low value. In fact, the slope of the hysteresis function is never allowed to change abruptly but is smoothly varied whenever the input domain smoothing parameter is set greater than zero. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a11 1 2 schmitt1 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5 \end_layout \begin_layout LyX-Code + out_lower_limit=0.5 out_upper_limit=3.0 \end_layout \begin_layout LyX-Code + input_domain=0.01 fraction=TRUE) \end_layout \begin_layout Subsection Differentiator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dt \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dt \end_layout \begin_layout LyX-Code Description: "time-derivative block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain out_offset \end_layout \begin_layout LyX-Code Description: "gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower limit smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Differentiator block is a simple derivative stage that approximates the time derivative of an input signal by calculating the incremental slope of that signal since the previous time point. The block also includes gain and output offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the radian frequency of analysis multiplied by the gain. \begin_inset Newline newline \end_inset Note that since truncation error checking is not included in the d_dt block, it is not recommended that the model be used to provide an integration function through the use of a feedback loop. Such an arrangement could produce erroneous results. Instead, you should make use of the "integrate" model, which does include truncation error checking for enhanced accuracy. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a12 7 12 slope_gen \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model slope_gen d_dt(out_offset=0.0 gain=1.0 \end_layout \begin_layout LyX-Code + out_lower_limit=1e-12 out_upper_limit=1e12 \end_layout \begin_layout LyX-Code + limit_range=1e-9) \end_layout \begin_layout Subsection Integrator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_int \end_layout \begin_layout LyX-Code Spice_Model_Name: int \end_layout \begin_layout LyX-Code Description: "time-integration block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower limit smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_ic \end_layout \begin_layout LyX-Code Description: "output initial condition" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Integrator block is a simple integration stage that approximate s the integral with respect to time of an input signal. The block also includes gain and input offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergenc e errors resulting from excessively large output values. Note that these limits specify integrator behavior similar to that found in an operational amplifier-based integration stage, in that once a limit is reached, additional storage does not occur. Thus, the input of a negative value to an integrator which is currently driving at the out upper limit level will immediately cause a drop in the output, regardless of how long the integrator was previously summing positive inputs. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the gain divided by the radian frequency of analysis. \begin_inset Newline newline \end_inset Note that truncation error checking is included in the \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset block. This should provide for a more accurate simulation of the time integration function, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a13 7 12 time_count \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model time_count int(in_offset=0.0 gain=1.0 \end_layout \begin_layout LyX-Code + out_lower_limit=-1e12 out_upper_limit=1e12 \end_layout \begin_layout LyX-Code + limit_range=1e-9 out_ic=0.0) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:S-Domain-Transfer-Function" \end_inset S-Domain Transfer Function \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_s_xfer \end_layout \begin_layout LyX-Code Spice_Model_Name: s_xfer \end_layout \begin_layout LyX-Code Description: "s-domain transfer function" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_coeff \end_layout \begin_layout LyX-Code Description: "numerator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_coeff \end_layout \begin_layout LyX-Code Description: "denominator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: int_ic \end_layout \begin_layout LyX-Code Description: "integrator stage initial conditions" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: den_coeff \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: denormalized_freq \end_layout \begin_layout LyX-Code Description: "denorm. corner freq.(radians) for 1 rad/s coeffs" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The s-domain transfer function is a single input, single output transfer function in the Laplace transform variable \begin_inset Quotes eld \end_inset s \begin_inset Quotes erd \end_inset that allows for flexible modulation of the frequency domain characteristics of a signal. Ac and transient simulations are supported. The code model may be configured to produce an arbitrary s-domain transfer function with the following restrictions: \end_layout \begin_layout LyX-Code 1. The degree of the numerator polynomial cannot exceed that \end_layout \begin_layout LyX-Code of the denominator polynomial in the variable "s". \end_layout \begin_layout LyX-Code 2. The coefficients for a polynomial must be stated \end_layout \begin_layout LyX-Code explicitly. That is, if a coefficient is zero, it must be \end_layout \begin_layout LyX-Code included as an input to the num coeff or den coeff vector. \end_layout \begin_layout Standard The order of the coefficient parameters is from that associated with the highest-powered term decreasing to that of the lowest. Thus, for the coefficient parameters specified below, the equation in \begin_inset Quotes eld \end_inset s \begin_inset Quotes erd \end_inset is shown: \end_layout \begin_layout LyX-Code .model filter s_xfer(gain=0.139713 int_ic=[0 0 0] \end_layout \begin_layout LyX-Code + num_coeff=[1.0 0.0 0.07464102] \end_layout \begin_layout LyX-Code + den_coeff=[1.0 0.998942 0.01170077]) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ...specifies a transfer function of the form... \end_layout \begin_layout Standard \align center \begin_inset Formula $N(s)=0.139713\cdot\{\frac{s^{2}+0.7464102}{s^{2}+0.998942s+0.00117077}\}$ \end_inset \end_layout \begin_layout Standard The s-domain transfer function includes \series bold gain \series default and \series bold in_offset \series default (input offset) parameters to allow for tailoring of the required signal. There are no limits on the internal signal values or on the output value of the s-domain transfer function, so you are cautioned to specify gain and coefficient values that will not cause the model to produce excessively large values. In AC analysis, the value returned is equal to the real and imaginary component s of the total s-domain transfer function at each frequency of interest. \end_layout \begin_layout Standard The \series bold denormalized_freq \series default term allows you to specify coefficients for a normalized filter (i.e. one in which the frequency of interest is 1 rad/s). Once these coefficients are included, specifying the denormalized frequency value \begin_inset Quotes eld \end_inset shifts \begin_inset Quotes erd \end_inset the corner frequency to the actual one of interest. As an example, the following transfer function describes a Chebyshev low-pass filter with a corner (pass-band) frequency of 1 rad/s: \end_layout \begin_layout Standard \align center \begin_inset Formula $N(s)=0.139713\cdot\{\frac{1.0}{s^{2}+1.09773s+1.10251}\}$ \end_inset \end_layout \begin_layout Standard In order to define an s_xfer model for the above, but with the corner frequency equal to 1500 rad/s (9425 Hz), the following instance and model lines would be needed: \end_layout \begin_layout LyX-Code a12 node1 node2 cheby1 \end_layout \begin_layout LyX-Code .model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251] \end_layout \begin_layout LyX-Code + int_ic=[0 0 0] denormalized_freq=1500) \end_layout \begin_layout Standard In the above, you add the normalized coefficients and scale the filter through the use of the denormalized freq parameter. Similar results could have been achieved by performing the denormalization prior to specification of the coefficients, and setting denormalized freq to the value 1.0 (or not specifying the frequency, as the default is 1.0 rad/s) Note in the above that frequencies are ALWAYS SPECIFIED AS RADIANS/SECON D. \end_layout \begin_layout Standard Truncation error checking is included in the s-domain transfer block. This should provide for more accurate simulations, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive. \end_layout \begin_layout Standard The \series bold int_ic \series default parameter is an array that must be of the same size as the array of values specified for the \series bold den_coeff \series default parameter. Even if a 0 start value is required, you have to add the specific int_ic vector to the set of coefficients (see the examples above and below). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a14 9 22 cheby_LP_3KHz \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model cheby_LP_3KHz s_xfer(in_offset=0.0 gain=1.0 int_ic=[0 0 0] \end_layout \begin_layout LyX-Code + num_coeff=[1.0] \end_layout \begin_layout LyX-Code + den_coeff=[1.0 1.42562 1.51620]) \end_layout \begin_layout Subsection Slew Rate Block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_slew \end_layout \begin_layout LyX-Code Spice_Model_Name: slew \end_layout \begin_layout LyX-Code Description: "A simple slew rate follower block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_slope \end_layout \begin_layout LyX-Code Description: "maximum rising slope value" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_slope \end_layout \begin_layout LyX-Code Description: "maximum falling slope value" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: range \end_layout \begin_layout LyX-Code Description: "smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.1 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a simple slew rate block that limits the absolute slope of the output with respect to time to some maximum or value. The actual slew rate effects of over-driving an amplifier circuit can thus be accurately modeled by cascading the amplifier with this model. The units used to describe the maximum rising and falling slope values are expressed in volts or amperes per second. Thus a desired slew rate of 0.5 V/ \begin_inset Formula $\mu s$ \end_inset will be expressed as 0.5e+6, etc. \begin_inset Newline newline \end_inset The slew rate block will continue to raise or lower its output until the difference between the input and the output values is zero. Thereafter, it will resume following the input signal, unless the slope again exceeds its rise or fall slope limits. The range input specifies a smoothing region above or below the input value. Whenever the model is slewing and the output comes to within the input + or - the range value, the partial derivative of the output with respect to the input will begin to smoothly transition from 0.0 to 1.0. When the model is no longer slewing (output = input), dout/din will equal 1.0. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a15 1 2 slew1 \end_layout \begin_layout LyX-Code .model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6) \end_layout \begin_layout Subsection Inductive Coupling \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_lcouple \end_layout \begin_layout LyX-Code Spice_Model_Name: lcouple \end_layout \begin_layout LyX-Code Description: "inductive coupling (for use with 'core' model)" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: l mmf_out \end_layout \begin_layout LyX-Code Description: "inductor" "mmf output (in ampere-turns)" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: hd hd \end_layout \begin_layout LyX-Code Allowed_Types: [h,hd] [hd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_turns \end_layout \begin_layout LyX-Code Description: "number of inductor turns" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a conceptual model which is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is normally used in conjunction with the \begin_inset Quotes eld \end_inset core \begin_inset Quotes erd \end_inset model, but can also be used with resistors, hysteresis blocks, etc. to build up systems which mock the behavior of linear and nonlinear components. \begin_inset Newline newline \end_inset The lcouple takes as an input (on the \begin_inset Quotes eld \end_inset l \begin_inset Quotes erd \end_inset port) a current. This current value is multiplied by the num_turns value, N, to produce an output value (a voltage value which appears on the mmf_out port). The mmf_out acts similar to a magnetomotive force in a magnetic circuit; when the lcouple is connected to the \begin_inset Quotes eld \end_inset core \begin_inset Quotes erd \end_inset model, or to some other resistive device, a current will flow. This current value (which is modulated by whatever the lcouple is connected to) is then used by the lcouple to calculate a voltage \begin_inset Quotes eld \end_inset seen \begin_inset Quotes erd \end_inset at the \begin_inset Quotes eld \end_inset l \begin_inset Quotes erd \end_inset port. The voltage is a function of the derivative with respect to time of the current value seen at mmf_out. \begin_inset Newline newline \end_inset The most common use for lcouples will be as a building block in the construction of transformer models. To create a transformer with a single input and a single output, you would require two lcouple models plus one \begin_inset Quotes eld \end_inset core \begin_inset Quotes erd \end_inset model. The process of building up such a transformer is described under the descriptio n of the \begin_inset Quotes eld \end_inset core \begin_inset Quotes erd \end_inset model, below. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a150 (7 0) (9 10) lcouple1 \end_layout \begin_layout LyX-Code .model lcouple1 lcouple(num_turns=10.0) \end_layout \begin_layout Subsection Magnetic Core \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_core \end_layout \begin_layout LyX-Code Spice_Model_Name: core \end_layout \begin_layout LyX-Code Description: "magnetic core" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: mc \end_layout \begin_layout LyX-Code Description: "magnetic core" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [g,gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: H_array B_array \end_layout \begin_layout LyX-Code Description: "magnetic field array" "flux density array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: area length \end_layout \begin_layout LyX-Code Description: "cross-sectional area" "core length" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_domain \end_layout \begin_layout LyX-Code Description: "input sm. domain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.01 \end_layout \begin_layout LyX-Code Limits: [1e-12 0.5] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/abs switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: mode \end_layout \begin_layout LyX-Code Description: "mode switch (1 = pwl, 2 = hyst)" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: [1 2] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low in_high \end_layout \begin_layout LyX-Code Description: "input low value" "input high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: hyst out_lower_limit \end_layout \begin_layout LyX-Code Description: "hysteresis" "output lower limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.1 0.0 \end_layout \begin_layout LyX-Code Limits: [0 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_upper_limit \end_layout \begin_layout LyX-Code Description: "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a conceptual model which is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is almost always expected to be used in conjunction with the \begin_inset Quotes eld \end_inset lcouple \begin_inset Quotes erd \end_inset model to build up systems which mock the behavior of linear and nonlinear magnetic components. There are two fundamental modes of operation for the core model. These are the pwl mode (which is the default, and which is the most likely to be of use to you) and the hysteresis mode. These are detailed below. \end_layout \begin_layout Standard \align center PWL Mode (mode = 1) \end_layout \begin_layout Standard The core model in PWL mode takes as input a voltage which it treats as a magnetomotive force (mmf) value. This value is divided by the total effective length of the core to produce a value for the Magnetic Field Intensity, H. This value of H is then used to find the corresponding Flux Density, B, using the piecewise linear relationship described by you in the H array / B array coordinate pairs. B is then multiplied by the cross-sectional area of the core to find the Flux value, which is output as a current. The pertinent mathematical equations are listed below: \end_layout \begin_layout Standard \align center H = mmf =L, where L = Length \end_layout \begin_layout Standard Here H, the Magnetic Field Intensity, is expressed in ampere-turns/meter. \end_layout \begin_layout Standard \align center B = f (H) \end_layout \begin_layout Standard The B value is derived from a piecewise linear transfer function described to the model via the (H_array[],B_array[]) parameter coordinate pairs. This transfer function does not include hysteretic effects; for that, you would need to substitute a HYST model for the core. \end_layout \begin_layout Standard \align center \begin_inset Formula $\phi$ \end_inset = BA, where A = Area \end_layout \begin_layout Standard The final current allowed to flow through the core is equal to \begin_inset Formula $\phi$ \end_inset . This value in turn is used by the "lcouple" code model to obtain a value for the voltage reflected back across its terminals to the driving electrical circuit. \end_layout \begin_layout Standard The following example code shows the use of two \begin_inset Quotes eld \end_inset lcouple \begin_inset Quotes erd \end_inset models and one core model to produce a simple primary/secondary transformer. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a1 (2 0) (3 0) primary \end_layout \begin_layout LyX-Code .model primary lcouple (num_turns = 155) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 (3 4) iron_core \end_layout \begin_layout LyX-Code .model iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0 \end_layout \begin_layout LyX-Code + 63 125 188 250 375 500 1000] \end_layout \begin_layout LyX-Code + B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3 \end_layout \begin_layout LyX-Code + -1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4 \end_layout \begin_layout LyX-Code + 6.25e-4 1.5e-3 1.93e-3 2.33e-3 \end_layout \begin_layout LyX-Code + 2.63e-3 3.13e-3] \end_layout \begin_layout LyX-Code + area = 0.01 length = 0.01) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 (5 0) (4 0) secondary \end_layout \begin_layout LyX-Code .model secondary lcouple (num_turns = 310) \end_layout \begin_layout Standard \align center HYSTERESIS Mode (mode = 2) \end_layout \begin_layout Standard The core model in HYSTERESIS mode takes as input a voltage which it treats as a magnetomotive force (mmf) value. This value is used as input to the equivalent of a hysteresis code model block. The parameters defining the input low and high values, the output low and high values, and the amount of hysteresis are as in that model. The output from this mode, as in PWL mode, is a current value which is seen across the mc port. An example of the core model used in this fashion is shown below: \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a1 (2 0) (3 0) primary \end_layout \begin_layout LyX-Code .model primary lcouple (num_turns = 155) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 (3 4) iron_core \end_layout \begin_layout LyX-Code .model iron_core core (mode = 2 in_low=-7.0 in_high=7.0 \end_layout \begin_layout LyX-Code + out_lower_limit=-2.5e-4 out_upper_limit=2.5e-4 \end_layout \begin_layout LyX-Code + hyst = 2.3 ) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 (5 0) (4 0) secondary \end_layout \begin_layout LyX-Code .model secondary lcouple (num_turns = 310) \end_layout \begin_layout Standard \emph on One final note to be made about the two core model nodes is that certain parameters are available in one mode, but not in the other \emph default . In particular, the in_low, in_high, out_lower_limit, out_upper_limit, and hysteresis parameters are not available in PWL mode. Likewise, the H_array, B_array, area, and length values are unavailable in HYSTERESIS mode. The input domain and fraction parameters are common to both modes (though their behavior is somewhat different; for explanation of the input domain and fraction values for the HYSTERESIS mode, you should refer to the hysteresis code model discussion). \end_layout \begin_layout Subsection Controlled Sine Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_sine \end_layout \begin_layout LyX-Code Spice_Model_Name: sine \end_layout \begin_layout LyX-Code Description: "controlled sine wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0e3 \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a controlled sine wave oscillator with parameteriz able values of low and high peak output. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl array and freq array pairs. From the curve, a frequency value is determined, and the oscillator will output a sine wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl array and the freq array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code asine 1 2 in_sine \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code .model in_sine sine(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = -5.0 \end_layout \begin_layout LyX-Code + out_high = 5.0) \end_layout \begin_layout Subsection Controlled Triangle Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_triangle \end_layout \begin_layout LyX-Code Spice_Model_Name: triangle \end_layout \begin_layout LyX-Code Description: "controlled triangle wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0e3 \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_duty \end_layout \begin_layout LyX-Code Description: "rise time duty cycle" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.5 \end_layout \begin_layout LyX-Code Limits: [1e-10 0.999999999] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled triangle/ramp wave oscillator with parametrizable values of low and high peak output and rise time duty cycle. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs. \begin_inset Newline newline \end_inset From the curve, a frequency value is determined, and the oscillator will output a triangle wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 ramp1 \end_layout \begin_layout LyX-Code .model ramp1 triangle(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = -5.0 \end_layout \begin_layout LyX-Code + out_high = 5.0 duty_cycle = 0.9) \end_layout \begin_layout Subsection Controlled Square Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_square \end_layout \begin_layout LyX-Code Spice_Model_Name: square \end_layout \begin_layout LyX-Code Description: "controlled square wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0e3 \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER.TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: duty_cycle rise_time \end_layout \begin_layout LyX-Code Description: "duty cycle" "output rise time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-6 0.999999] - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_time \end_layout \begin_layout LyX-Code Description: "output fall time" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled square wave oscillator with parametri zable values of low and high peak output, duty cycle, rise time, and fall time. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs. From the curve, a frequency value is determined, and the oscillator will output a square wave at that frequency. \begin_inset Newline newline \end_inset From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 pulse1 \end_layout \begin_layout LyX-Code .model pulse1 square(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = 0.0 \end_layout \begin_layout LyX-Code + out_high = 4.5 duty_cycle = 0.2 \end_layout \begin_layout LyX-Code + rise_time = 1e-6 fall_time = 2e-6) \end_layout \begin_layout Subsection Controlled One-Shot \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_oneshot \end_layout \begin_layout LyX-Code Spice_Model_Name: oneshot \end_layout \begin_layout LyX-Code Description: "controlled one-shot" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk cntl_in \end_layout \begin_layout LyX-Code Description: "clock input" "control input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clear out \end_layout \begin_layout LyX-Code Description: "clear signal" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_trig retrig \end_layout \begin_layout LyX-Code Description: "clock trigger value" "retrigger switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 0.5 FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: pos_edge_trig \end_layout \begin_layout LyX-Code Description: "positive/negative edge trigger switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array pw_array \end_layout \begin_layout LyX-Code Description: "control array" "pulse width array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - [0.00 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output low value" "output high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_time rise_time \end_layout \begin_layout LyX-Code Description: "output fall time" "output rise time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay \end_layout \begin_layout LyX-Code Description: "output delay from trigger" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_delay \end_layout \begin_layout LyX-Code Description: "output delay from pw" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled oneshot with parametrizable values of low and high peak output, input trigger value level, delay, and output rise and fall times. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and pw_array pairs. From the curve, a pulse width value is determined. The one-shot will output a pulse of that width, triggered by the clock signal (rising or falling edge), delayed by the delay value, and with specified rise and fall times. A positive slope on the clear input will immediately terminate the pulse, which resets with its fall time. \begin_inset Newline newline \end_inset From the above, it is easy to see that array sizes of 2 for both the cntl_array and the pw_array will yield a linear variation of the pulse width with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 3 4 pulse2 \end_layout \begin_layout LyX-Code .model pulse2 oneshot(cntl_array = [-1 0 10 11] \end_layout \begin_layout LyX-Code + pw_array=[1e-6 1e-6 1e-4 1e-4] \end_layout \begin_layout LyX-Code + clk_trig = 0.9 pos_edge_trig = FALSE \end_layout \begin_layout LyX-Code + out_low = 0.0 out_high = 4.5 \end_layout \begin_layout LyX-Code + rise_delay = 20.0-9 fall_delay = 35.0e-9) \end_layout \begin_layout Subsection Capacitance Meter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_cmeter \end_layout \begin_layout LyX-Code Spice_Model_Name: cmeter \end_layout \begin_layout LyX-Code Description: "capacitance meter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain \end_layout \begin_layout LyX-Code Description: "gain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The capacitance meter is a sensing device which is attached to a circuit node and produces as an output a scaled value equal to the total capacitance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models which must sense a capacitance value and alter their behavior based upon it. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code atest1 1 2 ctest \end_layout \begin_layout LyX-Code .model ctest cmeter(gain=1.0e12) \end_layout \begin_layout Subsection Inductance Meter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_lmeter \end_layout \begin_layout LyX-Code Spice_Model_Name: lmeter \end_layout \begin_layout LyX-Code Description: "inductance meter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain \end_layout \begin_layout LyX-Code Description: "gain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The inductance meter is a sensing device which is attached to a circuit node and produces as an output a scaled value equal to the total inductance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models which must sense an inductance value and alter their behavior based upon it. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code atest2 1 2 ltest \end_layout \begin_layout LyX-Code .model ltest lmeter(gain=1.0e6) \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:XSPICE-Hybrid-Models" \end_inset Hybrid Models \end_layout \begin_layout Standard The following hybrid models are supplied with XSPICE. The descriptions included below consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the .MODEL card and the specification of all available parameters. \end_layout \begin_layout Standard A note should be made with respect to the use of hybrid models for other than simple digital-to-analog and analog-to-digital translations. The hybrid models represented in this section address that specific need, but in the development of user-defined nodes you may find a need to translate not only between digital and analog nodes, but also between real and digital, real and int, etc. In most cases such translations will not need to be as involved or as detailed as shown in the following. \end_layout \begin_layout Subsection Digital-to-Analog Node Bridge \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_dac_bridge \end_layout \begin_layout LyX-Code Spice_Model_Name: dac_bridge \end_layout \begin_layout LyX-Code Description: "digital-to-analog node bridge" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d v \end_layout \begin_layout LyX-Code Allowed_Types: [d] [v,vd,i,id,d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low \end_layout \begin_layout LyX-Code Description: "0-valued analog output" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out.high \end_layout \begin_layout LyX-Code Description: "1-valued analog output" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_undef input_load \end_layout \begin_layout LyX-Code Description: "U-valued analog output" "input load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t_rise t_fall \end_layout \begin_layout LyX-Code Description: "rise time 0->1" "fall time 1->0" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The dac_bridge is the first of two node bridge devices designed to allow for the ready transfer of digital information to analog values and back again. The second device is the adc_bridge (which takes an analog value and maps it to a digital one).The dac_bridge takes as input a digital value from a digital node. This value by definition may take on only one of the values \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset U \begin_inset Quotes erd \end_inset . The dac_bridge then outputs the value \begin_inset Quotes eld \end_inset out_low \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset out_high \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset out_undef \begin_inset Quotes erd \end_inset , or ramps linearly toward one of these \begin_inset Quotes eld \end_inset final \begin_inset Quotes erd \end_inset values from its current analog output level. The speed at which this ramping occurs depends on the values of \begin_inset Quotes eld \end_inset t_rise \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset t_fall \begin_inset Quotes erd \end_inset . These parameters are interpreted by the model such that the rise or fall slope generated is always constant. \series bold Note \series default \series bold that the dac_bridge includes test code in its cfunc.mod file for determining the presence of the out_undef parameter. If this parameter is not specified by you, and if out_high and out_low values are specified, then out_undef is assigned the value of the arithmetic mean of out_high and out_low. \series default This simplifies coding of output buffers, where typically a logic family will include an out_low and out_high voltage, but not an out_undef value. This model also posts an input load value (in farads) based on the parameter input load. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code abridge1 [7] [2] dac1 \end_layout \begin_layout LyX-Code .model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2 \end_layout \begin_layout LyX-Code + input_load = 5.0e-12 t_rise = 50e-9 \end_layout \begin_layout LyX-Code + t_fall = 20e-9) \end_layout \begin_layout Subsection Analog-to-Digital Node Bridge \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_adc_bridge \end_layout \begin_layout LyX-Code Spice_Model_Name: adc_bridge \end_layout \begin_layout LyX-Code Description: "analog-to-digital node bridge" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v d \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,d] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low \end_layout \begin_layout LyX-Code Description: "maximum 0-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_high \end_layout \begin_layout LyX-Code Description: "minimum 1-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 2.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The adc_bridge is one of two node bridge devices designed to allow for the ready transfer of analog information to digital values and back again. The second device is the dac_bridge (which takes a digital value and maps it to an analog one). The adc_bridge takes as input an analog value from an analog node. This value by definition may be in the form of a voltage, or a current. If the input value is less than or equal to in_low, then a digital output value of \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset is generated. If the input is greater than or equal to in_high, a digital output value of \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset is generated. If neither of these is true, then a digital \begin_inset Quotes eld \end_inset UNKNOWN \begin_inset Quotes erd \end_inset value is output. Note that unlike the case of the dac_bridge, no ramping time or delay is associated with the adc_bridge. Rather, the continuous ramping of the input value provides for any associated delays in the digitized signal. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code abridge2 [1] [8] adc_buff \end_layout \begin_layout LyX-Code .model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5) \end_layout \begin_layout Subsection Controlled Digital Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_osc \end_layout \begin_layout LyX-Code Spice_Model_Name: d_osc \end_layout \begin_layout LyX-Code Description: "controlled digital oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v d \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0e6 \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: duty_cycle init_phase \end_layout \begin_layout LyX-Code Description: "duty cycle" "initial phase of output" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 0 \end_layout \begin_layout LyX-Code Limits: [1e-6 0.999999] [-180.0 +360.0] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1e-9 1e-9 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital oscillator is a hybrid model which accepts as input a voltage or current. This input is compared to the voltage-to-frequency transfer characteristic specified by the cntl_array/freq_array coordinate pairs, and a frequency is obtained which represents a linear interpolation or extrapolation based on those pairs. A digital time-varying signal is then produced with this fundamental frequency. \begin_inset Newline newline \end_inset The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays which can be specified independently. In addition, the duty cycle and the phase of the waveform are also variable and can be set by you. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a5 1 8 var_clock \end_layout \begin_layout LyX-Code .model var_clock d_osc(cntl_array = [-2 -1 1 2] \end_layout \begin_layout LyX-Code + freq_array = [1e3 1e3 10e3 10e3] \end_layout \begin_layout LyX-Code + duty_cycle = 0.4 init_phase = 180.0 \end_layout \begin_layout LyX-Code + rise_delay = 10e-9 fall_delay=8e-9) \end_layout \begin_layout Subsection Node bridge from digital to real with enable \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: d_to_real \end_layout \begin_layout LyX-Code C_Function_Name: ucm_d_to_real \end_layout \begin_layout LyX-Code Description: "Node bridge from digital to real with enable" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in enable out \end_layout \begin_layout LyX-Code Description: "input" "enable" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: d d real \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] [real] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: zero one delay \end_layout \begin_layout LyX-Code Description: "value for 0" "value for 1" "delay" \end_layout \begin_layout LyX-Code Data_Type: real real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 1e-9 \end_layout \begin_layout LyX-Code Limits: - - [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes yes \end_layout \begin_layout Subsection A Z**-1 block working on real data \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_delay \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_delay \end_layout \begin_layout LyX-Code Description: "A Z ** -1 block working on real data" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in clk out \end_layout \begin_layout LyX-Code Description: "input" "clock" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: real d real \end_layout \begin_layout LyX-Code Allowed_Types: [real] [d] [real] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay \end_layout \begin_layout LyX-Code Description: "delay from clk to out" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-9 \end_layout \begin_layout LyX-Code Limits: [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Subsection A gain block for event-driven real data \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_gain \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_gain \end_layout \begin_layout LyX-Code Description: "A gain block for event-driven real data" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: real real \end_layout \begin_layout LyX-Code Allowed_Types: [real] [real] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain out_offset \end_layout \begin_layout LyX-Code Description: "input offset" "gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - - \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay ic \end_layout \begin_layout LyX-Code Description: "delay" "initial condition" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Subsection Node bridge from real to analog voltage \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_to_v \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_to_v \end_layout \begin_layout LyX-Code Description: "Node bridge from real to analog voltage" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: real v \end_layout \begin_layout LyX-Code Allowed_Types: [real] [v, vd, i, id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain transition_time \end_layout \begin_layout LyX-Code Description: "gain" "output transition time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 1e-9 \end_layout \begin_layout LyX-Code Limits: - [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:XSPICE-Digital-Models" \end_inset Digital Models \end_layout \begin_layout Standard The following digital models are supplied with XSPICE. The descriptions included below consist of an example model Interface Specifica tion File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the .MODEL card and the specification of all available parameters. Note that these models have not been finalized at this time. \end_layout \begin_layout Standard Some information common to all digital models and/or digital nodes is included here. The following are general rules which should make working with digital nodes and models more straightforward: \end_layout \begin_layout Enumerate All digital nodes are initialized to ZERO at the start of a simulation (i.e., when INIT=TRUE). This means that a model need not post an explicit value to an output node upon initialization if its output would normally be a ZERO (although posting such would certainly cause no harm). \end_layout \begin_layout Subsection Buffer \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_buffer \end_layout \begin_layout LyX-Code Spice_Model_Name: d_buffer \end_layout \begin_layout LyX-Code Description: "digital one-bit-wide buffer" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The buffer is a single-input, single-output digital buffer which produces as output a time-delayed copy of its input. The delays associated with an output rise and those associated with an output fall may be different. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 1 8 buff1 \end_layout \begin_layout LyX-Code .model buff1 d_buffer(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Inverter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_inverter \end_layout \begin_layout LyX-Code Spice_Model_Name: d_inverter \end_layout \begin_layout LyX-Code Description: "digital one-bit-wide inverter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The inverter is a single-input, single-output digital inverter which produces as output an inverted, time- delayed copy of its input. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 1 8 inv1 \end_layout \begin_layout LyX-Code .model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection And \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_and \end_layout \begin_layout LyX-Code Spice_Model_Name: d_and \end_layout \begin_layout LyX-Code Description: "digital `and' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `and' gate is an n-input, single-output `and' gate which produces an active \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset value if, and only if, all of its inputs are also \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset values. If ANY of the inputs is a \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset , the output will also be a \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset ; if neither of these conditions holds, the output will be unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2] 8 and1 \end_layout \begin_layout LyX-Code .model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Nand \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_nand \end_layout \begin_layout LyX-Code Spice_Model_Name: d_nand \end_layout \begin_layout LyX-Code Description: "digital `nand' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `nand' gate is an n-input, single-output `nand' gate which produces an active \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset value if and only if all of its inputs are \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset values. If ANY of the inputs is a \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset , the output will be a \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset ; if neither of these conditions holds, the output will be unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2 3] 8 nand1 \end_layout \begin_layout LyX-Code .model nand1 d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Or \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_or \end_layout \begin_layout LyX-Code Spice_Model_Name: d_or \end_layout \begin_layout LyX-Code Description: "digital `or' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `or' gate is an n-input, single-output `or' gate which produces an active \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset value if at least one of its inputs is a \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset value. The gate produces a \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset value if all inputs are \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset ; if neither of these two conditions holds, the output is unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2 3] 8 or1 \end_layout \begin_layout LyX-Code .model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Nor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_nor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_nor \end_layout \begin_layout LyX-Code Description: "digital `nor' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `nor' gate is an n-input, single-output `nor' gate which produces an active \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset value if at least one of its inputs is a \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset value. The gate produces a \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset value if all inputs are \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset ; if neither of these two conditions holds, the output is unknown. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code anor12 [1 2 3 4] 8 nor12 \end_layout \begin_layout LyX-Code .model nor12 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Xor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_xor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_xor \end_layout \begin_layout LyX-Code Description: "digital exclusive-or gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `xor' gate is an n-input, single-output `xor' gate which produces an active \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset value if an odd number of its inputs are also \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset values. The delays associated with an output rise and those associated with an output fall may be specified independently. \begin_inset Newline newline \end_inset The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 [1 2] 8 xor3 \end_layout \begin_layout LyX-Code .model xor3 d_xor(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Xnor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_xnor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_xnor \end_layout \begin_layout LyX-Code Description: "digital exclusive-nor gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital `xnor' gate is an n-input, single-output `xnor' gate which produces an active \begin_inset Quotes eld \end_inset 0 \begin_inset Quotes erd \end_inset value if an odd number of its inputs are also \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset values. It produces a \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset output when an even number of \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset values occurs on its inputs. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 [1 2] 8 xnor3 \end_layout \begin_layout LyX-Code .model xnor3 d_xnor(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Tristate \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_tristate \end_layout \begin_layout LyX-Code Spice_Model_Name: d_tristate \end_layout \begin_layout LyX-Code Description: "digital tristate buffer" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in enable out \end_layout \begin_layout LyX-Code Description: "input" "enable" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: d d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] [d] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay \end_layout \begin_layout LyX-Code Description: "delay" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_load \end_layout \begin_layout LyX-Code Description: "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital tristate is a simple tristate gate which can be configured to allow for open-collector behavior, as well as standard tristate behavior. The state seen on the input line is reflected in the output. The state seen on the enable line determines the strength of the output. Thus, a ONE forces the output to its state with a STRONG strength. A ZERO forces the output to go to a HI_IMPEDANCE strength. The delays associated with an output state or strength change cannot be specified independently, nor may they be specified independently for rise or fall conditions; other gate models may be used to provide such delays if needed. The model posts input and enable load values (in farads) based on the parameter s input load and enable.The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output with the specified delay. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. Likewise, any UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength value. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 1 2 8 tri7 \end_layout \begin_layout LyX-Code .model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12 \end_layout \begin_layout LyX-Code + enable_load = 0.5e-12) \end_layout \begin_layout Subsection Pullup \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_pullup \end_layout \begin_layout LyX-Code Spice_Model_Name: d_pullup \end_layout \begin_layout LyX-Code Description: "digital pullup resistor" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: load \end_layout \begin_layout LyX-Code Description: "load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital pullup resistor is a device which emulates the behavior of an analog resistance value tied to a high voltage level. The pullup may be used in conjunction with tristate buffers to provide open-collector wired \begin_inset Quotes eld \end_inset or \begin_inset Quotes erd \end_inset constructs, or any other logical constructs which rely on a resistive pullup common to many tristated output devices. The model posts an input load value (in farads) based on the parameters \begin_inset Quotes eld \end_inset load \begin_inset Quotes erd \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 9 pullup1 \end_layout \begin_layout LyX-Code .model pullup1 d_pullup(load = 20.0e-12) \end_layout \begin_layout Subsection Pulldown \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_pulldown \end_layout \begin_layout LyX-Code Spice_Model_Name: d_pulldown \end_layout \begin_layout LyX-Code Description: "digital pulldown resistor" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: load \end_layout \begin_layout LyX-Code Description: "load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital pulldown resistor is a device which emulates the behavior of an analog resistance value tied to a low voltage level. The pulldown may be used in conjunction with tristate buffers to provide open-collector wired \begin_inset Quotes eld \end_inset or \begin_inset Quotes erd \end_inset constructs, or any other logical constructs which rely on a resistive pulldown common to many tristated output devices. The model posts an input load value (in farads) based on the parameters \begin_inset Quotes eld \end_inset load \begin_inset Quotes erd \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 9 pulldown1 \end_layout \begin_layout LyX-Code .model pulldown1 d_pulldown(load = 20.0e-12) \end_layout \begin_layout Subsection D Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dff \end_layout \begin_layout LyX-Code Description: "digital d-type flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data clk \end_layout \begin_layout LyX-Code Description: "input data" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynch. set" "asynch. reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load clk_load \end_layout \begin_layout LyX-Code Description: "data load value (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector.Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital d-type flip flop is a one-bit, edge-triggered storage element which will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_dff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN output. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a7 1 2 3 4 5 6 flop1 \end_layout \begin_layout LyX-Code .model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection JK Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_jkff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_jkff \end_layout \begin_layout LyX-Code Description: "digital jk-type flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: j k \end_layout \begin_layout LyX-Code Description: "j input" "k input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk \end_layout \begin_layout LyX-Code Description: "clock" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynchronous set" "asynchronous reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: jk_load clk_load \end_layout \begin_layout LyX-Code Description: "j,k load values (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital jk-type flip flop is a one-bit, edge-triggered storage element which will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_jkff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN automatically. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 1 2 3 4 5 6 7 flop2 \end_layout \begin_layout LyX-Code .model flop2 d_jkff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection Toggle Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_tff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_tff \end_layout \begin_layout LyX-Code Description: "digital toggle flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: t clk \end_layout \begin_layout LyX-Code Description: "toggle input" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT.TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t_load clk_load \end_layout \begin_layout LyX-Code Description: "toggle load value (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default.Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital toggle-type flip flop is a one-bit, edge-triggered storage element which will toggle its current state whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_tff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than t immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 2 12 4 5 6 3 flop3 \end_layout \begin_layout LyX-Code .model flop3 d_tff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9 t_load = 0.2e-12) \end_layout \begin_layout Subsection Set-Reset Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_srff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_srff \end_layout \begin_layout LyX-Code Description: "digital set-reset flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: s r \end_layout \begin_layout LyX-Code Description: "set input" "reset input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk \end_layout \begin_layout LyX-Code Description: "clock" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynchronous set" "asynchronous reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_load clk_load \end_layout \begin_layout LyX-Code Description: "set/reset loads (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital sr-type flip flop is a one-bit, edge-triggered storage element which will store data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored (i.e., the \begin_inset Quotes eld \end_inset out \begin_inset Quotes erd \end_inset value) will depend on the s and r input pin values, and will be: \end_layout \begin_layout LyX-Code out=ONE if s=ONE and r=ZERO; \end_layout \begin_layout LyX-Code out=ZERO if s=ZERO and r=ONE; \end_layout \begin_layout LyX-Code out=previous value if s=ZERO and r=ZERO; \end_layout \begin_layout LyX-Code out=UNKNOWN if s=ONE and r=ONE; \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_srff have separate load values and delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduct ion of the output characteristics of different IC fabrication technologies. \end_layout \begin_layout Standard Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN. \end_layout \begin_layout Standard Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 2 12 4 5 6 3 14 flop7 \end_layout \begin_layout LyX-Code .model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection D Latch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dlatch \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dlatch \end_layout \begin_layout LyX-Code Description: "digital d-type latch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data enable \end_layout \begin_layout LyX-Code Description: "input data" "enable input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverter data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_delay \end_layout \begin_layout LyX-Code Description: "delay from data" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from enable" "delay from SET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from RESET" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load enable_load \end_layout \begin_layout LyX-Code Description: "data load (F)" "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital d-type latch is a one-bit, level-sensitive storage element which will output the value on the data line whenever the enable input line is high (ONE). The value on the data line is stored (i.e., held on the out line) whenever the enable line is low (ZERO). \begin_inset Newline newline \end_inset In addition, asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d_dlatch (i.e., data changing with enable=ONE, enable changing to ONE from ZERO with a new value on data, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduct ion of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than on the data line when enable=ZERO immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 12 4 5 6 3 14 latch1 \end_layout \begin_layout LyX-Code .model latch1 d_dlatch(data_delay = 13.0e-9 enable_delay = 22.0e-9 \end_layout \begin_layout LyX-Code + set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 \end_layout \begin_layout LyX-Code + rise_delay = 10.0e-9 fall_delay = 3e-9) \end_layout \begin_layout Subsection Set-Reset Latch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_srlatch \end_layout \begin_layout LyX-Code Spice_Model_Name: d_srlatch \end_layout \begin_layout LyX-Code Description: "digital sr-type latch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: s r \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] r \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: enable \end_layout \begin_layout LyX-Code Description: "enable" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_delay \end_layout \begin_layout LyX-Code Description: "delay from s or r input change" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from enable" "delay from SET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from RESET" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_load enable_load \end_layout \begin_layout LyX-Code Description: "s & r input loads (F)" "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital sr-type latch is a one-bit, level-sensitive storage element which will output the value dictated by the state of the s and r pins whenever the enable input line is high (ONE). This value is stored (i.e., held on the out line) whenever the enable line is low (ZERO). The particular value chosen is as shown below: \end_layout \begin_layout LyX-Code s=ZERO, r=ZERO => out=current value (i.e., not change in output) \end_layout \begin_layout LyX-Code s=ZERO, r=ONE => out=ZERO \end_layout \begin_layout LyX-Code s=ONE, r=ZERO => out=ONE \end_layout \begin_layout LyX-Code s=ONE, r=ONE => out=UNKNOWN \end_layout \begin_layout Standard Asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to ONE from ZERO with an output-changing combination of s and r, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduct ion of the output characteristics of different IC fabrication technologies. \end_layout \begin_layout Standard Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 12 4 5 6 3 14 16 latch2 \end_layout \begin_layout LyX-Code .model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9 \end_layout \begin_layout LyX-Code + set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 \end_layout \begin_layout LyX-Code + rise_delay = 10.0e-9 fall_delay = 3e-9) \end_layout \begin_layout Subsection State Machine \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_state \end_layout \begin_layout LyX-Code Spice_Model_Name: d_state \end_layout \begin_layout LyX-Code Description: "digital state machine" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in clk \end_layout \begin_layout LyX-Code Description: "input" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: reset out \end_layout \begin_layout LyX-Code Description: "reset" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no yes \end_layout \begin_layout LyX-Code Vector_Bounds: - [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay reset_delay \end_layout \begin_layout LyX-Code Description: "delay from CLK" "delay from RESET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: Parameter_Name: state_file \end_layout \begin_layout LyX-Code Description: "state transition specification file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "state.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_state \end_layout \begin_layout LyX-Code Description: "default state on RESET & at DC" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_load \end_layout \begin_layout LyX-Code Description: "clock loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_load \end_layout \begin_layout LyX-Code Description: "reset loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital state machine provides for straightforward descriptions of clocked combinational logic blocks with a variable number of inputs and outputs and with an unlimited number of possible states. The model can be configured to behave as virtually any type of counter or clocked combinatorial logic block and can be used to replace very large digital circuit schematics with an identically functional but faster representa tion. \begin_inset Newline newline \end_inset The d state model is configured through the use of a state definition file (state.in) which resides in a directory of your choosing. The file defines all states to be understood by the model, plus input bit combinations which trigger changes in state. An example state.in file is shown below: \end_layout \begin_layout LyX-Code ----------- begin file ------------- \end_layout \begin_layout LyX-Code * This is an example state.in file. This file \end_layout \begin_layout LyX-Code * defines a simple 2-bit counter with one input. The \end_layout \begin_layout LyX-Code * value of this input determines whether the counter counts \end_layout \begin_layout LyX-Code * up (in = 1) or down (in = 0). \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 0 0s 0s 0 -> 3 \end_layout \begin_layout LyX-Code 1 -> 1 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 1 0s 1z 0 -> 0 \end_layout \begin_layout LyX-Code 1 -> 2 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 2 1z 0s 0 -> 1 \end_layout \begin_layout LyX-Code 1 -> 3 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 3 1z 1z 0 -> 2 \end_layout \begin_layout LyX-Code 3 1z 1z 1 -> 0 \end_layout \begin_layout LyX-Code ------------------ end file --------------- \end_layout \begin_layout Standard Several attributes of the above file structure should be noted. First, ALL LINES IN THE FILE MUST BE ONE OF FOUR TYPES. These are: \end_layout \begin_layout Enumerate A comment, beginning with a \begin_inset Quotes eld \end_inset * \begin_inset Quotes erd \end_inset in the first column. \end_layout \begin_layout Enumerate A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that input be encountered. The first line of a state definition must ALWAYS be a header line. \end_layout \begin_layout Enumerate A continuation line, which is a partial description of a state, consisting of an input value and the state that the model will assume should that input be encountered. Note that continuation lines may only be used after the initial header line definition for a state. \end_layout \begin_layout Enumerate A line containing nothing but whitespace (space, form-feed, newline, carriage return, tab, vertical tab). \end_layout \begin_layout Standard A line which is not one of the above will cause a file-loading error. Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character "->" is used to underline the state transition implied by the input preceding it. This particular character is not critical in of itself, and can be replaced with any other character or non-broken combination of characters that you prefer (e.g. \begin_inset Quotes eld \end_inset ==> \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset >> \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset : \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset resolves_to \begin_inset Quotes erd \end_inset , etc.) \end_layout \begin_layout Standard The order of the output and input bits in the file is important; the first column is always interpreted to refer to the \begin_inset Quotes eld \end_inset zeroth \begin_inset Quotes erd \end_inset bit of input and output. Thus, in the file above, the output from state 1 sets out[0] to \begin_inset Quotes eld \end_inset 0s \begin_inset Quotes erd \end_inset , and out[1] to \begin_inset Quotes eld \end_inset 1z \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard The state numbers need not be in any particular order, but a state definition (which consists of the sum total of all lines which define the state, its outputs, and all methods by which a state can be exited) must be made on contiguous line numbers; a state definition cannot be broken into sub-blocks and distributed randomly throughout the file. On the other hand, the state definition can be broken up by as many comment lines as you desire. \end_layout \begin_layout Standard Header files may be used throughout the state.in file, and continuation lines can be discarded completely if you so choose: continuation lines are primarily provided as a convenience. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1 \end_layout \begin_layout LyX-Code .model state1 d_state(clk_delay = 13.0e-9 reset_delay = 27.0e-9 \end_layout \begin_layout LyX-Code + state_file = newstate.txt reset_state = 2) \end_layout \begin_layout Subsection Frequency Divider \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_fdiv \end_layout \begin_layout LyX-Code Spice_Model_Name: d_fdiv \end_layout \begin_layout LyX-Code Description: "digital frequency divider" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: freq_in freq_out \end_layout \begin_layout LyX-Code Description: "frequency input" "frequency output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: div_factor high_cycles \end_layout \begin_layout LyX-Code Description: "divide factor" "# of cycles for high out" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 2 1 \end_layout \begin_layout LyX-Code Limits: [1 -] [1 div_factor-1] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_count \end_layout \begin_layout LyX-Code Description: "divider initial count value" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: in in \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: freq_in_load \end_layout \begin_layout LyX-Code Description: "freq_in load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital frequency divider is a programmable step-down divider which accepts an arbitrary divisor (div_factor), a duty-cycle term (high_cycles ), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 3 7 divider \end_layout \begin_layout LyX-Code .model divider d_fdiv(div_factor = 5 high_cycles = 3 \end_layout \begin_layout LyX-Code + i_count = 4 rise_delay = 23e-9 \end_layout \begin_layout LyX-Code + fall_delay = 9e-9) \end_layout \begin_layout Subsection RAM \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_ram \end_layout \begin_layout LyX-Code Spice_Model_Name: d_ram \end_layout \begin_layout LyX-Code Description: "digital random-access memory" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data_in data_out \end_layout \begin_layout LyX-Code Description: "data input line(s)" "data output line(s)" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] data_in \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: address write_en \end_layout \begin_layout LyX-Code Description: "address input line(s)" "write enable line" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: select \end_layout \begin_layout LyX-Code Description: "chip select line(s)" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 16] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: select_value \end_layout \begin_layout LyX-Code Description: "decimal active value for select line comparison" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: [0 32767] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ic \end_layout \begin_layout LyX-Code Description: "initial bit state @ dc" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 2 \end_layout \begin_layout LyX-Code Limits: [0 2] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: read_delay \end_layout \begin_layout LyX-Code Description: "read delay from address/select/write.en active" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 100.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load address_load \end_layout \begin_layout LyX-Code Description: "data_in load value (F)" "addr. load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: select_load \end_layout \begin_layout LyX-Code Description: "select load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_load \end_layout \begin_layout LyX-Code Description: "enable line load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital RAM is an M-wide, N-deep random access memory element with programmable select lines, tristated data out lines, and a single write/~read line. The width of the RAM words (M) is set through the use of the word width parameter. The depth of the RAM (N) is set by the number of address lines input to the device. The value of N is related to the number of address input lines (P) by the following equation: \begin_inset Formula \[ 2^{P}=N\] \end_inset There is no reset line into the device. However, an initial value for all bits may be specified by setting the ic parameter to either 0 or 1. In reading a word from the ram, the read delay value is invoked, and output will not appear until that delay has been satisfied. Separate rise and fall delays are not supported for this device. \begin_inset Newline newline \end_inset Note that UNKNOWN inputs on the address lines are not allowed during a write. In the event that an address line does indeed go unknown during a write, THE ENTIRE CONTENTS OF THE RAM WILL BE SET TO UNKNOWN. This is in contrast to the data in lines being set to unknown during a write; in that case, only the selected word will be corrupted, and this is corrected once the data lines settle back to a known value. Note that protection is added to the write en line such that extended UNKNOWN values on that line are interpreted as ZERO values. This is the equivalent of a read operation and will not corrupt the contents of the RAM. A similar mechanism exists for the select lines. If they are unknown, then it is assumed that the chip is not selected. \begin_inset Newline newline \end_inset Detailed timing-checking routines are not provided in this model, other than for the enable delay and select delay restrictions on read operations. You are advised, therefore, to carefully check the timing into and out of the RAM for correct read and write cycle times, setup and hold times, etc. for the particular device they are attempting to model. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2 \end_layout \begin_layout LyX-Code .model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9) \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Digital Source \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_source \end_layout \begin_layout LyX-Code Spice_Model_Name: d_source \end_layout \begin_layout LyX-Code Description: "digital signal source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_file \end_layout \begin_layout LyX-Code Description: "digital input vector filename" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "source.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout Description Description: The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The model reads input from the input file and, at the times specified in the file, generates the inputs along with the strengths listed. \end_layout \begin_layout Description The format of the input file is as shown below. Note that comment lines are delineated through the use of a single \begin_inset Quotes eld \end_inset * \begin_inset Quotes erd \end_inset character in the first column of a line. This is similar to the way the SPICE program handles comments. \end_layout \begin_layout LyX-Code * T c n n n . . . \end_layout \begin_layout LyX-Code * i l o o o . . . \end_layout \begin_layout LyX-Code * m o d d d . . . \end_layout \begin_layout LyX-Code * e c e e e . . . \end_layout \begin_layout LyX-Code * k a b c . . . \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 0.0000 Uu Uu Us Uu . . . \end_layout \begin_layout LyX-Code 1.234e-9 0s 1s 1s 0z . . . \end_layout \begin_layout LyX-Code 1.376e-9 0s 0s 1s 0z . . . \end_layout \begin_layout LyX-Code 2.5e-7 1s 0s 1s 0z . . . \end_layout \begin_layout LyX-Code 2.5006e-7 1s 1s 1s 0z . . . \end_layout \begin_layout LyX-Code 5.0e-7 0s 1s 1s 0z . . . \end_layout \begin_layout Standard Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate the time and strength/state tokens. The order of the input columns is important; the first column is always interpreted to mean \begin_inset Quotes eld \end_inset time \begin_inset Quotes erd \end_inset . The second through the N'th columns map to the out[0] through out[N-2] output nodes. A non-commented line which does not contain enough tokens to completely define all outputs for the digital source will cause an error. Also, time values must increase monotonically or an error will result in reading the source file. \end_layout \begin_layout Standard Errors will also occur if a line exists in source.txt which is neither a comment nor vector line. The only exception to this is in the case of a line that is completely blank; this is treated as a comment (note that such lines often occur at the end of text within a file; ignoring these in particular prevents nuisance errors on the part of the simulator). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector \end_layout \begin_layout LyX-Code .model input_vector d_source(input_file = source_simple.text) \end_layout \begin_layout Section Predefined Node Types \end_layout \begin_layout Standard The following prewritten node types are included with the XSPICE simulator. These, along with the digital node type built into the simulator, should provide you not only with valuable event-driven modeling capabilities, but also with examples to use for guidance in creating new UDN types. \end_layout \begin_layout Subsection Real Node Type \end_layout \begin_layout Standard The \begin_inset Quotes eld \end_inset real \begin_inset Quotes erd \end_inset node type provides for event-driven simulation with double-precision floating point data. This type is useful for evaluating sampled-data filters and systems. The type implements all optional functions for User-Defined Nodes, including inversion and node resolution. For inversion, the sign of the value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. \end_layout \begin_layout Subsection Int Node Type \end_layout \begin_layout Standard The \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset node type provides for event-driven simulation with integer data. This type is useful for evaluating round-off error effects in sampled-data systems. The type implements all optional functions for User-Defined Nodes, including inversion and node resolution. For inversion, the sign of the integer value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. \end_layout \begin_layout Standard \end_layout \begin_layout Chapter Verilog A Device models \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard The ngspice-adms interface will implement extra HICUM level0 and level2 ( \begin_inset CommandInset href LatexCommand href name "HICUM model web page" target "http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html" \end_inset ), MEXTRAM( \begin_inset CommandInset href LatexCommand href name "MEXTRAM model web page" target "http://mextram.ewi.tudelft.nl/" \end_inset ), EKV( \begin_inset CommandInset href LatexCommand href name "EKV model web page" target "http://ekv.epfl.ch/" \end_inset ) and PSP( \begin_inset CommandInset href LatexCommand href name "NXP MOS model 9 web page" target "http://www.nxp.com/models/mos_models/model9/index.html" \end_inset ) models written in Verilog-A behavior language. \end_layout \begin_layout Section adms \end_layout \begin_layout Standard To compile Verilog-A compact models into ngspice-ready C models the the program admsXml is required. Details of this software are described in \begin_inset CommandInset href LatexCommand href name "adms home page" target "http://mot-adms.sourceforge.net" \end_inset . \end_layout \begin_layout Section How to integrate a Verilog-A model into ngspice \end_layout \begin_layout Subsection How to setup a *.va model for ngspice \end_layout \begin_layout Standard The root entry for new Verilog-A models is \backslash src \backslash spicelib \backslash devices \backslash adms. Below the modelname entry the Verilog-A code should reside in folder admsva \begin_inset Newline newline \end_inset (e.g.: ng-spice-rework \backslash src \backslash spicelib \backslash devices \backslash adms \backslash ekv \backslash admsva \backslash ekv.va). The file extension is fixed to .va. \end_layout \begin_layout Standard Certain files must modified to create the interface to ngspice - see the guideline README.adms in the ngspice root. \end_layout \begin_layout Subsection Adding admsXml to your build environment \end_layout \begin_layout Standard To facilitate the installation of adms, a source code package has been assembled for use with ngspice, available as a zip file for \begin_inset CommandInset href LatexCommand href name "download" target "http://ngspice.sourceforge.net/adms2/adms-svn-ngspice-src.zip" \end_inset . It is based on adms source code from the subversion repository downloaded on August 1st, 2010, and has been slightly modified (see ChangeLog). \end_layout \begin_layout Standard Under OS LINUX (tested with SUSE 11.2, 64 bit) you may expand the zip file and run \begin_inset Newline newline \end_inset \family typewriter ./autogen_lin.sh \family default , followed by ' \family typewriter make \family default ' and ' \family typewriter make install \family default '. \end_layout \begin_layout Standard Under OS CYGWIN (tested with actual CYGWIN on MS Windows 7, 64 bit), please use \family typewriter ./autogen_cyg.sh \family default , followed by ' \family typewriter make \family default ' and ' \family typewriter make install \family default '. \end_layout \begin_layout Standard Under OS MINGW, a direct compilation would require the additional installation of perl module XML-LibXML which is not as straightforward as it should be. However you may start with a CYGWIN compile as described above. If you then go to your MSYS window, cd to the adms top directory and start \family typewriter ./mingw-compile.sh \family default , you will obtain admsXml.exe, copied to MSYS /bin, and you are ready to go. To facilitate installation under MS Windows, a \family typewriter \series bold admsXml.exe \family default \series default \begin_inset CommandInset href LatexCommand href name "zipped binary" target "http://ngspice.sourceforge.net/adms2/adms-admsXml-Win32-bin.zip" \end_inset is available. Just copy it to MSYS /bin directory and start working on your verilog models. \end_layout \begin_layout Standard A short test of a successful installation is: \end_layout \begin_layout Standard \family typewriter $ admsXml -v \end_layout \begin_layout Standard \family typewriter $ [usage..] release name="admsXml" version="2.3.0" date="Aug 4 2010" \begin_inset Newline newline \end_inset time="10:24:18" \end_layout \begin_layout Standard Compilation of admsXml with MS Visual Studio is not possible, because the source code has variable declarations not only at the top of a block, but deliberately also in the following lines. This is o.k. by the C99 standard, but not supported by MS Visual Studio. \end_layout \begin_layout Chapter Mixed-Level Simulation (ngspice with TCAD) \end_layout \begin_layout Section Cider \end_layout \begin_layout Standard Ngspice implements mixed-level simulation through the merging of its code with CIDER (details see chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" \end_inset ). \end_layout \begin_layout Standard CIDER is a mixed-level circuit and device simulator that provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can provide greater simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for noncritical devices. \end_layout \begin_layout Standard CIDER couples the latest version of SPICE3 (version 3F.2) [JOHN92] to a internal C-based device simulator, DSIM. SPICE3 provides circuit analyses, compact models for semiconductor devices, and an interactive user interface. DSIM provides accurate, one- and two-dimensional numerical device models based on the solution of Poisson's equation, and the electron and hole current-continuity equations. DSIM incorporates many of the same basic physical models found in the the Stanford two-dimensional device simulator PISCES [PINT85]. Input to CIDER consists of a SPICE-like description of the circuit and its compact models, and PISCES-like descriptions of the structures of numerical ly modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. For example, SPICE3F.2 input files should run without modification, producing identical results. \end_layout \begin_layout Standard CIDER is based on the mixed-level circuit and device simulator CODECS [MAYA88] and is a replacement for this program. The basic algorithms of the two programs are the same. Some of the differences between CIDER and CODECS are described below. The CIDER input format has greater flexibility and allows increased access to physical model parameters. New physical models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation [GATE90] that is important in scaled-down MOSFETs and a polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included for most physical models over the range from -50°C to 150°C. The numerical models can be used to simulate all the basic types of semiconduct or devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the management of device internal states. Post-processing of device states can be performed using the NUTMEG user interface of SPICE3. Previously computed states can be loaded into the program to provide accurate initial guesses for subsequent analyses. Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms. \end_layout \begin_layout Standard Berkeley tradition calls for the naming of new versions of programs by affixing a (number, letter, number) triplet to the end of the program name. Under this scheme, CIDER should instead be named CODECS2A.l. However, tradition has been broken in this case because major incompatibilities exist between the two programs and because it was observed that the acronym CODECS is already used in the analog design community to refer to coder-decoder circuits. \end_layout \begin_layout Standard Details of the basic semiconductor equations and the physical models used by CIDER are not provided in this manual. Unfortunately, no other single source exists which describes all of the relevant background material. Comprehensive reviews of device simulation can be found in [PINT90] and the book [SELB84]. CODECS and its inversion-layer mobility model are described in [MAYA88] and LGATE90], respectively. PISCES and its models are described in [PINT85]. Temperature dependencies for the PISCES models used by CIDER are available in [SOLL90]. \end_layout \begin_layout Section GSS, Genius \end_layout \begin_layout Standard For LINUX users the cooperation of the TCAD software GSS with ngspice might be of interest, see \begin_inset CommandInset href LatexCommand href target "http://ngspice.sourceforge.net/gss.html" \end_inset . This project is no longer maintained however, but has moved into the Genius simulator, still available as open source \begin_inset CommandInset href LatexCommand href name "cogenda genius" target "http://www.cogenda.com/article/download" \end_inset . \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Analyses-and-Output" \end_inset Analyses and Output Control \end_layout \begin_layout Standard The command lines described in this chapter are specifying analyses and outpus within the circuit description file. They start with a \begin_inset Quotes eld \end_inset . \begin_inset Quotes erd \end_inset (dot commands). Specifying analyses and plots (or tables) in the input file with dot commands is used with batch runs. Batch mode is entered when either the \family typewriter \series bold -b \family default \series default option is given or when the default input source is redirected from a file (see also chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Batch-mode" \end_inset ). In batch mode, the analyses specified by the control lines in the input file (e.g. \begin_inset Quotes eld \end_inset \family typewriter .ac \family default \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset \family typewriter .tran \family default \begin_inset Quotes erd \end_inset , etc.) are immediately executed. If the \family typewriter \series bold -r \family default \series default rawfile option is given then all data generated is written to a ngspice rawfile. The rawfile may later be read by the interactive mode of ngspice using the \begin_inset Quotes eld \end_inset \family sans load \family default \begin_inset Quotes erd \end_inset command (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Load:-Load-rawfile" \end_inset ). In this case, the \family typewriter .save \family default line (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Batch-Output" \end_inset ) may be used to record the value of internal device variables (see Appendix, chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" \end_inset ). \end_layout \begin_layout Standard If a rawfile is not specified, then output plots (in \begin_inset Quotes eld \end_inset line-printer \begin_inset Quotes erd \end_inset form) and tables can be printed according to the \family typewriter .print \family default , \family typewriter .plot \family default , and \family typewriter .four \family default control lines, described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Batch-Output" \end_inset . \end_layout \begin_layout Standard If ngspice is started in interactive mode (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Interactive-mode" \end_inset ), the dot commands are not executed immediately, but are waiting for manually giving the command \begin_inset Quotes eld \end_inset \family sans run \family default \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard A a much larger set of commands (including command similar to the dot commands) exists in the interactive command interpreter (detailed in section \begin_inset CommandInset ref LatexCommand ref reference "chap:Interactive-Interpreter" \end_inset ). These commands are used inside \end_layout \begin_layout LyX-Code \family typewriter .control \end_layout \begin_layout LyX-Code < commands > \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout Standard sections (.control ... .endc sections) of the input file like a script. Ngspice may now be started in interactive mode (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Interactive-mode-with" \end_inset ), but still executing the dot commands immediately, if command \begin_inset Quotes eld \end_inset \family sans run \family default \begin_inset Quotes erd \end_inset is added to the script. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Simulator-Variables" \end_inset Simulator Variables (.options) \end_layout \begin_layout Standard Various parameters of the simulations available in Ngspice can be altered to control the accuracy, speed, or default values for some devices. These parameters may be changed via the \begin_inset Quotes eld \end_inset \family sans option \family default \begin_inset Quotes erd \end_inset command (described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Option*:" \end_inset ) or via the \begin_inset Quotes eld \end_inset \family typewriter .options \family default \begin_inset Quotes erd \end_inset line: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .options opt1 opt2 ... (or opt=optval ...) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .options reltol=.005 trtol=8 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The options line allows the user to reset program control and user options for specific simulation purposes. Options specified to Ngspice via the \begin_inset Quotes eld \end_inset \family typewriter \series bold option \family default \series default \begin_inset Quotes erd \end_inset command (see chapt. ) are also passed on as if specified on a \family typewriter .options \family default line. Any combination of the following options may be included, in any order. \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset (below) represents some positive number. \end_layout \begin_layout Subsection General Options \end_layout \begin_layout Description ACCT causes accounting and run time statistics to be printed. \end_layout \begin_layout Description NOACCT no printing of statistics, no printing of the Initial Transient Solution. \end_layout \begin_layout Description NOINIT suppresses only printing of the Initial Transient Solution, maybe combined with ACCT. \end_layout \begin_layout Description LIST causes the summary listing of the input data to be printed. \end_layout \begin_layout Description NOMOD suppresses the printout of the model parameters. \end_layout \begin_layout Description NOPAGE suppresses page ejects. \end_layout \begin_layout Description NODE causes the printing of the node table. \end_layout \begin_layout Description OPTS causes the option values to be printed. \end_layout \begin_layout Description TEMP=x Resets the operating temperature of the circuit. The default value is 27 \begin_inset Formula $°C$ \end_inset (300K). TEMP can be overridden by a temperature specification on any temperature dependent instance \end_layout \begin_layout Description TNOM=x resets the nominal temperature at which device parameters are measured. The default value is 27 \begin_inset Formula $°C$ \end_inset (300 deg K). TNOM can be overridden by a specification on any temperature dependent device model. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:DC-Solution-Options" \end_inset DC Solution Options \end_layout \begin_layout Standard The following options controls properties pertaining to DC analysis and algorithms. Since transient analysis is based on DC many of the options affect the latter one. \end_layout \begin_layout Description ABSTOL=x resets the absolute current error tolerance of the program. The default value is 1 pA. \end_layout \begin_layout Description GMIN=x resets the value of GMIN, the minimum conductance allowed by the program. The default value is 1.0e-12. \end_layout \begin_layout Description ITL1=x resets the dc iteration limit. The default is 100. \end_layout \begin_layout Description ITL2=x resets the dc transfer curve iteration limit. The default is 50. \end_layout \begin_layout Description KEEPOPINFO Retain the operating point information when either an AC, Distortion, or Pole-Zero analysis is run. This is particularly useful if the circuit is large and you do not want to run a (redundant) ".OP" analysis. \end_layout \begin_layout Description PIVREL=x resets the relative ratio between the largest column entry and an acceptable pivot value. The default value is 1.0e-3. In the numerical pivoting algorithm the allowed minimum pivot value is determined by EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL) where MAXVAL is the maximum element in the column where a pivot is sought (partial pivoting). \end_layout \begin_layout Description PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted as a pivot. The default value is 1.0e-13. \end_layout \begin_layout Description RELTOL=x resets the relative error tolerance of the program. The default value is 0.001 (0.1%). \end_layout \begin_layout Description RSHUNT=x introduces a resistor from each analog node to ground. The value of the resistor should be high enough to not interfere with circuit operations. \end_layout \begin_layout Description VNTOL=x resets the absolute voltage error tolerance of the program. The default value is 1 \begin_inset Formula $\mu V$ \end_inset . \end_layout \begin_layout Subsubsection Matrix Conditioning info \end_layout \begin_layout Standard In most SPICE-based simulators, problems can arise with certain circuit topologies. One of the most common problems is the absence of a DC path to ground at some node. This may happen, for example, when two capacitors are connected in series with no other connection at the common node or when certain code models are cascaded. The result is an ill-conditioned or nearly singular matrix that prevents the simulation from completing. XSPICE introduces a new \begin_inset Quotes eld \end_inset rshunt \begin_inset Quotes erd \end_inset option to help eliminate this problem. When used, this option inserts resistors to ground at all the analog nodes in the circuit. In general, the value of \begin_inset Quotes eld \end_inset rshunt \begin_inset Quotes erd \end_inset should be set to some very high resistance (e.g. 1000 Meg Ohms or greater) so that the operation of the circuit is essentially unaffected, but the matrix problems are corrected. If you should encounter a \begin_inset Quotes eld \end_inset no DC path to ground \begin_inset Quotes erd \end_inset or a \begin_inset Quotes eld \end_inset matrix is nearly singular \begin_inset Quotes erd \end_inset error message with your circuit, you should try adding the following .option card to your circuit description deck. \end_layout \begin_layout LyX-Code .option rshunt = 1.0e12 \end_layout \begin_layout Standard Usually a value of 1.0e12 is sufficient to correct the matrix problems. However, if you still have problems, you may wish to try lowering this value to 1.0e10 or 1.0e9. \end_layout \begin_layout Subsection Transient Analysis Options \end_layout \begin_layout Description CHGTOL=x resets the charge tolerance of the program. The default value is 1.0e-14. \end_layout \begin_layout Description CONVSTEP=x relative step limit applied to code models. \end_layout \begin_layout Description CONVABSSTEP=x absolute step limit applied to code models. \end_layout \begin_layout Description GMINSTEPS=x [*] sets number of Gmin steps to be attempted. If the value is set to zero, the gmin stepping algorithm is disabled. In such case the source stepping algorithm becomes the standard when the standard procedure fails to converge to a solution. \end_layout \begin_layout Description ITL3=x resets the lower transient analysis iteration limit. the default value is 4. (Note: not implemented in Spice3). \end_layout \begin_layout Description ITL4=x resets the transient analysis time-point iteration limit. the default is 10. \end_layout \begin_layout Description ITL5=x resets the transient analysis total iteration limit. the default is 5000. Set ITL5=0 to omit this test. (Note: not implemented in Spice3). \end_layout \begin_layout Description ITL6=x [*] synonym for SRCSTEPS. \end_layout \begin_layout Description MAXEVITER=x sets the number of event iterations that are allowed at an analysis point \end_layout \begin_layout Description MAXOPALTER=x specifies the maximum number of analog/event alternations that the simulator can use in solving a hybrid circuit. \end_layout \begin_layout Description MAXORD=x [*] specifies the maximum order for the numerical integration method used by SPICE. Possible values for the Gear method are from 2 (the default) to 6. Using the value 1 with the trapezoidal method specifies backward Euler integration. \end_layout \begin_layout Description METHOD=name sets the numerical integration method used by SPICE. Possible names are "Gear" or "trapezoidal" (or just "trap"). The default is trapezoidal. \end_layout \begin_layout Description NOOPALTER=TRUE|FALSE if set to false alternations between analog/event are enabled. \end_layout \begin_layout Description RAMPTIME=x this options sets the rate of change of independent supplies and code model inductors and capacitors with initial conditions specified. \end_layout \begin_layout Description SRCSTEPS=x [*] a non-zero value causes SPICE to use a source-stepping method to find the DC operating point. Its value specifies the number of steps. \end_layout \begin_layout Description \begin_inset CommandInset label LatexCommand label name "des:TRTOL" \end_inset TRTOL=x resets the transient error tolerance. The default value is 7. This parameter is an estimate of the factor by which ngspice overestimates the actual truncation error. If XSPICE is enabled and 'A' devices included, the value is internally set to 1 for higher precision. This will cost a factor of two in cpu time during transient analysis. \end_layout \begin_layout Subsection MOSFET Specific options \end_layout \begin_layout Description BADMOS3 Use the older version of the MOS3 model with the \begin_inset Quotes eld \end_inset kappa \begin_inset Quotes erd \end_inset discontinuity. \end_layout \begin_layout Description DEFAD=x resets the value for MOS drain diffusion area; the default is 0.0. \end_layout \begin_layout Description DEFAS=x resets the value for MOS source diffusion area; the default is 0.0. \end_layout \begin_layout Description DEFL=x resets the value for MOS channel length; the default is 100.0 \begin_inset Formula $\mu m$ \end_inset . \end_layout \begin_layout Description DEFW=x resets the value for MOS channel width; the default is 100.0 \begin_inset Formula $\mu m$ \end_inset . \end_layout \begin_layout Subsection Transmission Lines Specific Options \end_layout \begin_layout Description TRYTOCOMPACT Applicable only to the LTRA model (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Lossy-Transmission-Line" \end_inset ). When specified, the simulator tries to condense LTRA transmission line's past history of input voltages and currents. \end_layout \begin_layout Subsection Precedence of option and .options commands \end_layout \begin_layout Standard There are various ways to set the above mentioned options in Ngspice. If no \family typewriter option \family default or \family typewriter .options \family default lines are set by the user, internal default values are given for each of the simulator variables. \end_layout \begin_layout Standard You may set options in the init files \series bold spinit \series default or \series bold .spiceinit \series default via the \family typewriter \series bold option \family default \series default command (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Option*:" \end_inset ). The values given here will supersede the default values. If you set options via the \family typewriter .options \family default line in your input file, their values will supersede the default and init file data. Finally if you set options inside a .control ... .endc section, these values will supersede any values of the respective simulator variables given so far. \end_layout \begin_layout Section Initial Conditions \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.NODESET" \end_inset .NODESET: Specify Initial Node Voltage Guesses \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .NODESET V(NODNUM)=VAL V(NODNUM)=VAL ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .NODESET V(12)=4.5 V(4)=2.23 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .nodeset \family default line helps the program find the dc or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restriction is then released and the iteration continues to the true solution. The \family typewriter .nodeset \family default line may be necessary for convergence on bistable or a-stable circuits. In general, this line should not be necessary. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.IC:-Set-Initial" \end_inset .IC: Set Initial Conditions \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ic v(nodnum)=val v(nodnum)=val ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ic v(11)=5 v(4)=-5 v(2)=2.2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .ic \family default line is for setting transient initial conditions. It has two different interpretations, depending on whether the \family typewriter \series bold uic \family default \series default parameter is specified on the \family typewriter .tran \family default control line. Also, one should not confuse this line with the \family typewriter .nodeset \family default line. The \family typewriter .nodeset \family default line is only to help dc convergence, and does not affect final bias solution (except for multi-stable circuits). The two interpretations of this line are as follows: \end_layout \begin_layout Enumerate When the \family typewriter \series bold uic \family default \series default parameter is specified on the \family typewriter .tran \family default line, then the node voltages specified on the \family typewriter .ic \family default control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions. This is equivalent to specifying the \family typewriter \series bold ic=... \family default \series default parameter on each device line, but is much more convenient. The \family typewriter \series bold ic=... \family default \series default parameter can still be specified and takes precedence over the \family typewriter .ic \family default values. Since no dc bias (initial transient) solution is computed before the transient analysis, one should take care to specify all dc source voltages on the \family typewriter .ic \family default control line if they are to be used to compute device initial conditions. \end_layout \begin_layout Enumerate When the \family typewriter \series bold uic \family default \series default parameter is not specified on the \family typewriter .tran \family default control line, the dc bias (initial transient) solution is computed before the transient analysis. In this case, the node voltages specified on the \family typewriter .ic \family default control line is forced to the desired initial values during the bias solution. During transient analysis, the constraint on these node voltages is removed. This is the preferred method since it allows ngspice to compute a consistent dc solution. \end_layout \begin_layout Section Analyses \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.AC:-Small-Signal-AC" \end_inset .AC: Small-Signal AC Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ac dec nd fstart fstop \end_layout \begin_layout Plain Layout .ac oct no fstart fstop \end_layout \begin_layout Plain Layout .ac lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .ac dec 10 1 10K \end_layout \begin_layout Plain Layout .ac dec 10 1K 100MEG \end_layout \begin_layout Plain Layout .ac lin 100 1 100HZ \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold dec \family default \series default stands for decade variation, and \family typewriter \series bold nd \family default \series default is the number of points per decade. \family typewriter \series bold oct \family default \series default stands for octave variation, and \family typewriter \series bold no \family default \series default is the number of points per octave. \family typewriter \series bold lin \family default \series default stands for linear variation, and \family typewriter \series bold np \family default \series default is the number of points. \family typewriter \series bold fstart \family default \series default is the starting frequency, and \family typewriter \series bold fstop \family default \series default is the final frequency. If this line is included in the input file, ngspice performs an AC analysis of the circuit over the specified frequency range. Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value. Typically it does not make much sense to specify more than one ac source. If you do, the result will be a superposition of all sources, thus difficult to interpret. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Basic RC circuit \end_layout \begin_layout Plain Layout r 1 2 1.0 \end_layout \begin_layout Plain Layout c 2 0 1.0 \end_layout \begin_layout Plain Layout vin 1 0 dc 0 ac 1 $ <--- the ac source \end_layout \begin_layout Plain Layout .options noacct \end_layout \begin_layout Plain Layout .ac dec 10 .01 10 \end_layout \begin_layout Plain Layout .plot ac vdb(2) xlog \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In this ac (or 'small signal') analysis all non-linear devices are linearized around their actual dc operating point. All Ls and Cs get their imaginary value, depending on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the ac value (Vin equals to 1 in the example above). The resulting node voltages (and branch currents) are complex vectors. Therefore you have to be careful using the plot command. Especially you may use the variants of vxx(node) described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.PRINT-Lines" \end_inset like \family typewriter vdb(2) \family default (see example above). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.DC:-DC-Transfer" \end_inset .DC: DC Transfer Function \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .dc srcnam vstart vstop vincr [src2 start2 stop2 incr2] \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .dc VIN 0.25 5.0 0.25 \end_layout \begin_layout Plain Layout .dc VDS 0 10 .5 VGS 0 5 1 \end_layout \begin_layout Plain Layout .dc VCE 0 10 .25 IB 0 10U 1U \end_layout \begin_layout Plain Layout .dc RLoad 1k 2k 100 \end_layout \begin_layout Plain Layout .dc TEMP -15 75 5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .dc \family default line defines the dc transfer curve source and sweep limits (again with capacitors open and inductors shorted). \family typewriter \series bold srcnam \family default \series default is the name of an independent voltage or current source, a resistor or the circuit temperature. \family typewriter \series bold vstart \family default \series default , \family typewriter \series bold vstop \family default \series default , and \family typewriter \series bold vincr \family default \series default are the starting, final, and incrementing values respectively. The first example causes the value of the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts. A second source ( \family typewriter \series bold src2 \family default \series default ) may optionally be specified with associated sweep parameters. In this case, the first source is swept over its range for each value of the second source. This option can be useful for obtaining semiconductor device output characteris tics. See the example circuit description on transistor characteristics ( \begin_inset CommandInset ref LatexCommand ref reference "sec:MOSFET-Characterization" \end_inset ). \end_layout \begin_layout Subsection .DISTO: Distortion Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .disto dec nd fstart fstop \end_layout \begin_layout Plain Layout .disto oct no fstart fstop \end_layout \begin_layout Plain Layout .disto lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .disto dec 10 1kHz 100Mhz \end_layout \begin_layout Plain Layout .disto dec 10 1kHz 100Mhz 0.9 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .disto \family default line does a small-signal distortion analysis of the circuit. A multi-dimensional Volterra series analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the operating point. Terms of up to third order are used in the series expansions. \end_layout \begin_layout Standard If the optional parameter \family typewriter \series bold f2overf1 \family default \series default is not specified, \family typewriter .disto \family default does a harmonic analysis - i.e., it analyses distortion in the circuit using only a single input frequency \begin_inset Formula $F_{1}$ \end_inset , which is swept as specified by arguments of the \family typewriter .disto \family default command exactly as in the \family typewriter .ac \family default command. Inputs at this frequency may be present at more than one input source, and their magnitudes and phases are specified by the arguments of the \family typewriter \series bold distof1 \family default \series default keyword in the input file lines for the input sources (see the description for independent sources). (The arguments of the \family typewriter \series bold distof2 \family default \series default keyword are not relevant in this case). \end_layout \begin_layout Standard The analysis produces information about the AC values of all node voltages and branch currents at the harmonic frequencies \begin_inset Formula $2F_{1}$ \end_inset and , vs. the input frequency \begin_inset Formula $F_{1}$ \end_inset as it is swept. (A value of 1 (as a complex distortion output) signifies \begin_inset Formula $\cos(2\pi(2F_{1})t)$ \end_inset at \begin_inset Formula $2F_{1}$ \end_inset and \begin_inset Formula $\cos(2\pi(3F_{1})t)$ \end_inset at \begin_inset Formula $3F_{1}$ \end_inset , using the convention that 1 at the input fundamental frequency is equivalent to \begin_inset Formula $\cos(2\pi F_{1}t)$ \end_inset .) The distortion component desired ( \begin_inset Formula $2F_{1}$ \end_inset or \begin_inset Formula $3F_{1}$ \end_inset ) can be selected using commands in ngnutmeg, and then printed or plotted. (Normally, one is interested primarily in the magnitude of the harmonic components, so the magnitude of the AC distortion value is looked at). It should be noted that these are the AC values of the actual harmonic components, and are not equal to HD2 and HD3. To obtain HD2 and HD3, one must divide by the corresponding AC values at \begin_inset Formula $F_{1}$ \end_inset , obtained from an \family typewriter .ac \family default line. This division can be done using ngnutmeg commands. \end_layout \begin_layout Standard If the optional \family typewriter \series bold f2overf1 \family default \series default parameter is specified, it should be a real number between (and not equal to) 0.0 and 1.0; in this case, \family typewriter .disto \family default does a spectral analysis. It considers the circuit with sinusoidal inputs at two different frequencies \begin_inset Formula $F_{1}$ \end_inset and \begin_inset Formula $F_{2}$ \end_inset . \begin_inset Formula $F_{1}$ \end_inset is swept according to the \family typewriter .disto \family default control line options exactly as in the \family typewriter .ac \family default control line. \begin_inset Formula $F_{2}$ \end_inset is kept fixed at a single frequency as \begin_inset Formula $F_{1}$ \end_inset sweeps - the value at which it is kept fixed is equal to \family typewriter f2overf1 \family default times \family typewriter fstart \family default . Each independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for distortion, at the frequencies \begin_inset Formula $F_{1}$ \end_inset and \begin_inset Formula $F_{2}$ \end_inset . The magnitude and phase of the \begin_inset Formula $F_{1}$ \end_inset component are specified by the arguments of the \family typewriter \series bold distof1 \family default \series default keyword in the source's input line (see the description of independent sources); the magnitude and phase of the \begin_inset Formula $F_{2}$ \end_inset component are specified by the arguments of the \family typewriter \series bold distof2 \family default \series default keyword. The analysis produces plots of all node voltages/branch currents at the intermodulation product frequencies \begin_inset Formula $F_{1}+F_{2}$ \end_inset , \begin_inset Formula $F_{1}-F_{2}$ \end_inset , and \begin_inset Formula $(2F_{1})-F_{2}$ \end_inset , vs the swept frequency \begin_inset Formula $F_{1}$ \end_inset . The IM product of interest may be selected using the \family sans setplot \family default command, and displayed with the print and plot commands. It is to be noted as in the harmonic analysis case, the results are the actual AC voltages and currents at the intermodulation frequencies, and need to be normalized with respect to \family typewriter .ac \family default values to obtain the IM parameters. \end_layout \begin_layout Standard If the \family typewriter \series bold distof1 \family default \series default or \family typewriter \series bold distof2 \family default \series default keywords are missing from the description of an independent source, then that source is assumed to have no input at the corresponding frequency. The default values of the magnitude and phase are 1.0 and 0.0 respectively. The phase should be specified in degrees. \end_layout \begin_layout Standard It should be carefully noted that the number \family typewriter \series bold f2overf1 \family default \series default should ideally be an irrational number, and that since this is not possible in practice, efforts should be made to keep the denominator in its fractional representation as large as possible, certainly above 3, for accurate results (i.e., if \family typewriter \series bold f2overf1 \family default \series default is represented as a fraction \begin_inset Formula $\nicefrac{A}{B}$ \end_inset , where \begin_inset Formula $A$ \end_inset and \begin_inset Formula $B$ \end_inset are integers with no common factors, \begin_inset Formula $B$ \end_inset should be as large as possible; note that \begin_inset Formula $A49/100$ \end_inset \begin_inset Formula $F_{1}=F_{2}$ \end_inset . In this case, there are two very closely spaced frequency components at \begin_inset Formula $F_{2}$ \end_inset and \begin_inset Formula $F_{1}-F_{2}$ \end_inset . One of the advantages of the Volterra series technique is that it computes distortions at mix frequencies expressed symbolically (i.e. \begin_inset Formula $nF_{1}+mF_{2}$ \end_inset ), therefore one is able to obtain the strengths of distortion components accurately even if the separation between them is very small, as opposed to transient analysis for example. The disadvantage is of course that if two of the mix frequencies coincide, the results are not merged together and presented (though this could presumably be done as a postprocessing step). Currently, the interested user should keep track of the mix frequencies himself or herself and add the distortions at coinciding mix frequencies together should it be necessary. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.NOISE:-Noise-Analysis" \end_inset .NOISE: Noise Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .noise v(output <,ref>) src ( dec | lin | oct ) pts fstart fstop \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .noise v(5) VIN dec 10 1kHZ 100Mhz \end_layout \begin_layout Plain Layout .noise v(5,3) V1 oct 8 1.0 1.0e6 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .noise \family default line does a noise analysis of the circuit. \family typewriter \series bold output \family default \series default is the node at which the total output noise is desired; if \family typewriter \series bold ref \family default \series default is specified, then the noise voltage \family typewriter \series bold v(output) - v(ref) \family default \series default is calculated. By default, \family typewriter \series bold ref \family default \series default is assumed to be ground. \family typewriter \series bold src \family default \series default is the name of an independent source to which input noise is referred. \family typewriter \series bold pts \family default \series default , \family typewriter \series bold fstart \family default \series default and \family typewriter \series bold fstop \family default \series default are \family typewriter .ac \family default type parameters that specify the frequency range over which plots are desired. \family typewriter \series bold pts_per_summary \family default \series default is an optional integer; if specified, the noise contributions of each noise generator is produced every \family typewriter \series bold pts_per_summary \family default \series default frequency points. The \family typewriter .noise \family default control line produces two plots: \end_layout \begin_layout Enumerate one for the Noise Spectral Density curves and \end_layout \begin_layout Enumerate one for the total Integrated Noise over the specified frequency range. \end_layout \begin_layout Standard All noise voltages/currents are in squared units ( \begin_inset Formula $\nicefrac{V^{2}}{Hz}$ \end_inset and \begin_inset Formula $\nicefrac{A^{2}}{Hz}$ \end_inset for spectral density, \begin_inset Formula $V^{2}$ \end_inset and \begin_inset Formula $A^{2}$ \end_inset for integrated noise). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.OP:-Operating-Point" \end_inset .OP: Operating Point Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .op \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The inclusion of this line in an input file directs ngspice to determine the dc operating point of the circuit with inductors shorted and capacitors opened. \end_layout \begin_layout Standard Note: a DC analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an AC small-signal, Noise, and Pole-Zero analysis to determine the linearized, small-signal models for nonlinear devices (see the KEEPOPINFO variable \begin_inset CommandInset ref LatexCommand ref reference "sub:DC-Solution-Options" \end_inset ). \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection .PZ: Pole-Zero Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .pz node1 node2 node3 node4 cur pol \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 cur zer \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 cur pz \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 vol pol \end_layout \begin_layout Plain Layout .pz node1 node2 NODE3 node4 vol zer \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 vol pz \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .pz 1 0 3 0 cur pol \end_layout \begin_layout Plain Layout .pz 2 3 5 0 vol zer \end_layout \begin_layout Plain Layout .pz 4 1 4 1 cur pz \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold cur \family default \series default stands for a transfer function of the type (output voltage)/(input current) while \family typewriter \series bold vol \family default \series default stands for a transfer function of the type (output voltage)/(input voltage). \family typewriter \series bold pol \family default \series default stands for pole analysis only, \family typewriter \series bold zer \family default \series default for zero analysis only and \family typewriter \series bold pz \family default \series default for both. This feature is provided mainly because if there is a nonconvergence in finding poles or zeros, then, at least the other can be found. Finally, \family typewriter \series bold node1 \family default \series default and \family typewriter \series bold node2 \family default \series default are the two input nodes and \family typewriter \series bold node3 \family default \series default and \family typewriter \series bold node4 \family default \series default are the two output nodes. Thus, there is complete freedom regarding the output and input ports and the type of transfer function. \end_layout \begin_layout Standard In interactive mode, the command syntax is the same except that the first field is \family sans pz \family default instead of \family typewriter .pz \family default . To print the results, one should use the command \begin_inset Quotes eld \end_inset \family sans print all \family default \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Subsection .SENS: DC or Small-Signal AC Sensitivity Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SENS OUTVAR \end_layout \begin_layout Plain Layout .SENS OUTVAR AC DEC ND FSTART FSTOP \end_layout \begin_layout Plain Layout .SENS OUTVAR AC OCT NO FSTART FSTOP \end_layout \begin_layout Plain Layout .SENS OUTVAR AC LIN NP FSTART FSTOP \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SENS V(1,OUT) \end_layout \begin_layout Plain Layout .SENS V(OUT) AC DEC 10 100 100k \end_layout \begin_layout Plain Layout .SENS I(VTEST) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The sensitivity of OUTVAR to all non-zero device parameters is calculated when the SENS analysis is specified. OUTVAR is a circuit variable (node voltage or voltage-source branch current). The first form calculates sensitivity of the DC operating-point value of OUTVAR. The second form calculates sensitivity of the AC values of OUTVAR. The parameters listed for AC sensitivity are the same as in an AC analysis (see ".AC" above). The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or per percent change of input). \end_layout \begin_layout Subsection .TF: Transfer Function Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .tf outvar insrc \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .tf v(5, 3) VIN \end_layout \begin_layout Plain Layout .tf i(VLOAD) VIN \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .tf \family default line defines the small-signal output and input for the dc small-signal analysis. \family typewriter \series bold outvar \family default \series default is the small signal output variable and \family typewriter \series bold insrc \family default \series default is the small-signal input source. If this line is included, ngspice computes the dc small-signal value of the transfer function (output/input), input resistance, and output resistance. For the first example, ngspice would compute the ratio of V(5, 3) to VIN, the small-signal input resistance at VIN, and the small signal output resistanc e measured across nodes 5 and 3. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.TRAN:-Transient-Analysis" \end_inset .TRAN: Transient Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .tran tstep tstop > \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .tran 1ns 100ns \end_layout \begin_layout Plain Layout .tran 1ns 1000ns 500ns \end_layout \begin_layout Plain Layout .tran 10ns 1us \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold tstep \family default \series default is the printing or plotting increment for line-printer output. For use with the post-processor, \family typewriter \series bold tstep \family default \series default is the suggested computing increment. \family typewriter \series bold tstop \family default \series default is the final time, and \family typewriter \series bold tstart \family default \series default is the initial time. If \family typewriter \series bold tstart \family default \series default is omitted, it is assumed to be zero. The transient analysis always begins at time zero. In the interval , the circuit is analyzed (to reach a steady state), but no outputs are stored. In the interval < \family typewriter \series bold tstart \family default \series default , \family typewriter \series bold tstop \family default \series default >, the circuit is analyzed and outputs are stored. \family typewriter \series bold tmax \family default \series default is the maximum stepsize that ngspice uses; for default, the program chooses either \family typewriter \series bold tstep \family default \series default or ( \family typewriter \series bold tstop \family default \series default - \family typewriter \series bold tstart \family default \series default )/50.0, whichever is smaller. \family typewriter \series bold tmax \family default \series default is useful when one wishes to guarantee a computing interval which is smaller than the printer increment, \family typewriter \series bold tstep \family default \series default . \end_layout \begin_layout Standard \family typewriter \series bold uic \family default \series default (use initial conditions) is an optional keyword which indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the \family typewriter .ic \family default control line has been specified, then the node voltages on the \family typewriter .ic \family default line are used to compute the initial conditions for the devices. Look at the description on the \family typewriter .ic \family default control line for its interpretation when \family typewriter \series bold uic \family default \series default is not specified. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Transient-noise-analysis" \end_inset Transient noise analysis (at low frequency) \end_layout \begin_layout Standard In contrast to the analysis types described above the transient noise simulation (noise current or voltage versus time) is not implemented as a dot command, but is integrated with the independent voltage source vsrc (isrc still not yet available) (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Transient-noise-source" \end_inset ) and used in combination with the \series bold .tran \series default transient analysis ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.TRAN:-Transient-Analysis" \end_inset ). \end_layout \begin_layout Standard Transient noise analysis deals with noise currents or voltages added to your circuits as a time dependent signal of randomly generated voltage excursion on top of a fixed dc voltage. The sequence of voltage values has random amplitude, but equidistant time intervals, selectable by the user (parameter NT). The resulting voltage waveform is differentiable and thus does not require any modifications of the matrix solving algorithms. \end_layout \begin_layout Standard White noise is generated by the ngspice random number generator, applying the Box-Muller transform. Values are generated on the fly, each time when a breakpoint is hit. \end_layout \begin_layout Standard The 1/f noise is generated with an algorithm provided by N. J. Kasdin (“Discrete simulation of colored noise and stochastic processes and \begin_inset Formula $1/f^{a}$ \end_inset power law noise generation”, Proceedings of the IEEE, Volume 83, Issue 5, May 1995 Page(s):802 – 827). The noise sequence (one for each voltage/current source with 1/f selected) is generated upon start up of the simulator and stored for later use. The number of point is determined by the total simulation time divided by NT, rounded up the the nearest power of 2. Each time a breakpoint ( \begin_inset Formula $n\star NT$ \end_inset , relevant to the noise signal) is hit, the next value is retrieved from the sequence. \end_layout \begin_layout Standard If you want a random, but reproducible sequence, you may select a seed value for the random number generator by adding \end_layout \begin_layout Standard \family typewriter set rndseed=nn \end_layout \begin_layout Standard to the spinit or .spiceinit file, nn being a positive integer number. \end_layout \begin_layout Standard The transient noise analysis will allow the simulation of the three most important noise sources. Thermal noise is described by the Gaussian white noise. Flicker noise (pink noise or 1 over f noise) with an exponent between 0 and 2 is provided as well. Shot noise is dependent on the current flowing through a device and may be simulated by applying a non-linear source as demonstrated in the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Shot noise test with B source, diode \end_layout \begin_layout Plain Layout * voltage on device (diode, forward) \end_layout \begin_layout Plain Layout Vdev out 0 DC 0 PULSE(0.4 0.45 10u) \end_layout \begin_layout Plain Layout * diode, forward direction, to be modeled with noise \end_layout \begin_layout Plain Layout D1 mess 0 DMOD \end_layout \begin_layout Plain Layout .model DMOD D IS=1e-14 N=1 \end_layout \begin_layout Plain Layout X1 0 mess out ishot \end_layout \begin_layout Plain Layout * device between 1 and 2 \end_layout \begin_layout Plain Layout * new output terminals of device including noise: 1 and 3 \end_layout \begin_layout Plain Layout .subckt ishot 1 2 3 \end_layout \begin_layout Plain Layout * white noise source with rms 1V \end_layout \begin_layout Plain Layout * 20000 sample points \end_layout \begin_layout Plain Layout VNG 0 11 DC 0 TRNOISE(1 1n 0 0) \end_layout \begin_layout Plain Layout *measure the current i(v1) \end_layout \begin_layout Plain Layout V1 2 3 DC 0 \end_layout \begin_layout Plain Layout * calculate the shot noise \end_layout \begin_layout Plain Layout * sqrt(2*current*q*bandwidth) \end_layout \begin_layout Plain Layout BI 1 3 I=sqrt(2*abs(i(v1))*1.6e-19*1e7)*v(11) \end_layout \begin_layout Plain Layout .ends ishot \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .tran 1n 20u \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot (-1)*i(vdev) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The selection of the delta time step (NT) is worth discussing. Gaussian white noise has unlimited bandwidth and thus unlimited energy content. This is unrealistic. The bandwidth of real noise is limited, but it is still called "White" if it is the same level throughout the frequency range of interest, e.g. the bandwidth of your system. Thus you may select NT to be a factor of 10 smaller than the frequency limit of your circuit. A thorough analysis is still needed to clarify the appropriate factor! The transient method is probably most suited for circuits including switches, which are not amenable to the small signal .NOISE analysis (chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.NOISE:-Noise-Analysis" \end_inset ). \end_layout \begin_layout Standard This is the price you have to pay for transient noise analysis: the number of required time steps for simulation will increase, and thus the simulation time. But modern computers deliver a lot of speed, and it may be well worth of trying and experimenting. \end_layout \begin_layout Standard In addition to white and 1/f noise the independent voltage and current sources offer a random telegraph signal (RTS) noise source, also known as burst noise or popcorn noise, again for transient analysis. For each voltage (current) source offering RTS noise an individual noise amplitude is required for input, as well as a mean capture time and a mean emission time. The amplitude resembles the influence of a single trap on the current or voltage. The capture and emission times emulate the filling and emptying of the trap, typically following a Poisson process. They are generated from an random exponential distribution with their respectiv e mean values given by the user. To simulate an ensemble of traps, you may combine several current or voltage sources with different parameters. \end_layout \begin_layout Standard All three sources (white, 1/f, and RTS) may be combined in a single command line. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout RTS noise example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * white noise, 1/f noise, RTS noise \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage source \end_layout \begin_layout Plain Layout VRTS2 13 12 DC 0 trnoise(0 0 0 0 5m 18u 30u) \end_layout \begin_layout Plain Layout VRTS3 11 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) \end_layout \begin_layout Plain Layout VALL 12 11 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout VW1of 21 0 DC trnoise(1m 1u 1.0 0.1m) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * current source \end_layout \begin_layout Plain Layout IRTS2 10 0 DC 0 trnoise(0 0 0 0 5m 18u 30u) \end_layout \begin_layout Plain Layout IRTS3 10 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) \end_layout \begin_layout Plain Layout IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) \end_layout \begin_layout Plain Layout R10 10 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout IW1of 9 0 DC trnoise(1m 1u 1.0 0.1m) \end_layout \begin_layout Plain Layout Rall 9 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * sample points \end_layout \begin_layout Plain Layout .tran 1u 500u \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot v(13) v(21) \end_layout \begin_layout Plain Layout plot v(10) v(9) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Some details on RTS noise modeling are available in a recent article \begin_inset CommandInset citation LatexCommand cite key "key-20" \end_inset , available \begin_inset CommandInset href LatexCommand href name "here" target "http://www.see.ed.ac.uk/~tbt/iscas09.pdf" \end_inset . \end_layout \begin_layout Standard \series bold Anyhow this transient noise feature is still experimental! \series default \end_layout \begin_layout Standard The following questions (among others) are to be solved: \end_layout \begin_layout Itemize clarify the theoretical background \end_layout \begin_layout Itemize noise limit of plain ngspice (numerical solver, fft etc.) \end_layout \begin_layout Itemize time step (NT) selection \end_layout \begin_layout Itemize calibration of noise spectral density \end_layout \begin_layout Itemize how to generate noise from a transistor model \end_layout \begin_layout Itemize application benefits and limits \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.PSS:-Periodic_Steady_State-Analysis" \end_inset .PSS: Periodic Steady State Analysis \end_layout \begin_layout Standard (Experimental code, not yet made publicly available!) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .pss gfreq tstab oscnob psspoints harms sciter steadycoeff \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .pss 150 200e-3 2 1024 11 50 5e-3 uic \end_layout \begin_layout Plain Layout .pss 624e6 1u v_plus 1024 10 150 5e-3 uic \end_layout \begin_layout Plain Layout .pss 624e6 500n bout 1024 10 100 5e-3 uic \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold gfreq \family default \series default is guessed frequency of fundamental suggested by user. When performing transient analysis the PSS algorithm tries to infer a new rough guess \family typewriter \series bold rgfreq \family default \series default on the fundamental. If \family typewriter \series bold gfreq \family default \series default is out of \begin_inset Formula $\pm$ \end_inset 10% with respect to \family typewriter \series bold rgfreq \family default \series default then \family typewriter \series bold gfreq \family default \series default is discarded. \end_layout \begin_layout Standard \family typewriter \series bold tstab \family default \series default is stabilization time before the shooting begin to search for the PSS. It has to be noticed that this parameter heavily influence the possibility to reach the PSS. Thus is a good practice to ensure a circuit to have a right \family typewriter \series bold tstab \family default \series default , e.g. perfoming a separate TRAN analysis before to run PSS analysis. \end_layout \begin_layout Standard \family typewriter \series bold oscnob \family default \series default is the node or branch where the oscillation dynamic is expected. PSS analysis will give a brief report of harmonic content at this node or branch. \end_layout \begin_layout Standard \family typewriter \series bold psspoints \family default \series default is number of step in evaluating predicted period after convergence is reached. It is useful only in Time Domain plots. However this number should be higher than 2 times the requested \family typewriter \series bold harms \family default \series default . Otherwise the PSS analysis will properly adjust it. \end_layout \begin_layout Standard \family typewriter \series bold harms \family default \series default number of harmonics to be calculated as requested by the user. \end_layout \begin_layout Standard \family typewriter \series bold sciter \family default \series default number of allowed shooting cycle iterations. Default is 50. \end_layout \begin_layout Standard \family typewriter \series bold steady_coeff \family default \series default is the weighting ceofficient for calculating the Global Convergence Error (GCE) which is the reference value in order to infer is convergence is reached. The lower \family typewriter \series bold steady_coeff \family default \series default is set, the higher the accuracy of predicted frequency can be reached but at longer analysis time and \family typewriter \series bold sciter \family default \series default number. Default is 1e-3. \end_layout \begin_layout Standard \family typewriter \series bold uic \family default \series default (use initial conditions) is an optional keyword which indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the \family typewriter .ic \family default control line has been specified, then the node voltages on the \family typewriter .ic \family default line are used to compute the initial conditions for the devices. Look at the description on the \family typewriter .ic \family default control line for its interpretation when \family typewriter \series bold uic \family default \series default is not specified. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sub:.MEAS" \end_inset Measurements after Op, Ac, and Transient Analysis \end_layout \begin_layout Subsection .meas(ure) \end_layout \begin_layout Standard The \series bold .meas \series default or \series bold .measure \series default statement (and its equivalent \series bold meas \series default command, see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Meas*:-Mesurements-on" \end_inset ) are used to analyze the output data of a tran, ac, or dc simulation. The command is executed immediately after the simulation has finished. \end_layout \begin_layout Subsection batch versus interactive mode \end_layout \begin_layout Standard .meas analysis may not be used in batch mode ( \family typewriter \series bold -b \family default \series default command line option), if an output file (rawfile) is given at the same time ( \family typewriter \series bold -r \series default rawfile \family default command line option). In this batch mode ngspice will write its simulation output data directly to the output file. The data is not kept in memory, thus is no longer available for further analysis. This is made to allow a very large output stream with only a relatively small memory usage. For .meas to be active you need to run the batch mode with a \family typewriter .plot \family default or \family typewriter .print \family default command. A better alternative may be to start ngspice in interactive mode. \end_layout \begin_layout Standard If you need batch like operation, you may add a \family typewriter .control ... .endc \family default section to the input file: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout *input file \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .tran 1ns 1000ns \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout ********************************* \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write outputfile data \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout ********************************* \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard and start ngspice in interactive mode, e.g. by running the command \end_layout \begin_layout Standard \family typewriter ngspice inputfile \family default . \end_layout \begin_layout Standard .meas then prints its user-defined data analysis to the standard output. The analysis includes propagation, delay, rise time, fall time, peak-to-peak voltage, minimum or maximum voltage, the integral or derivative over a specified period and several other user defined values. \end_layout \begin_layout Subsection General remarks \end_layout \begin_layout Standard The measure type \series bold {DC|AC|TRAN|SP \series default } depends on the data which are to be evaluated, either originating from a dc analysis, an ac analysis, a transient simulation. \series bold SP \series default to analyse a spectrum from the \family typewriter spec \family default or \family typewriter fft \family default commands is only available when executed in a \family typewriter meas \family default command, see \begin_inset CommandInset ref LatexCommand ref reference "sub:Meas*:-Mesurements-on" \end_inset . \end_layout \begin_layout Standard \series bold result \series default will be a vector containing the result of the measurement. \series bold trig_variable \series default , \series bold targ_variable \series default , and \series bold out_variable \series default are vectors stemming from the simulation, e.g. a voltage vector v(out). \end_layout \begin_layout Standard \series bold VAL=val \series default expects a real number val. It may be as well a parameter in '' or {} expanding to a real number. \end_layout \begin_layout Standard \series bold TD=td \series default and \series bold AT=time \series default expect a time value if measure type is \series bold tran \series default . For \series bold ac \series default and \series bold sp \series default \series bold AT \series default will be a frequency value, TD is ignored. For \series bold dc \series default analysis \series bold AT \series default is a voltage (or current), \series bold TD \series default is ignored as well. \end_layout \begin_layout Standard \series bold CROSS=# \series default requires an integer number #. \series bold CROSS=LAST \series default is possible as well. The same is expected by \series bold RISE \series default and \series bold FALL \series default . \end_layout \begin_layout Standard Frequency and time values may start at 0 and extend to positive real numbers. Voltage (or current) inputs for the independent (scale) axis in a dc analysis may start or end at arbitrary real valued numbers. \end_layout \begin_layout Standard \series bold * \end_layout \begin_layout Standard \series bold ************ \end_layout \begin_layout Standard \series bold Be careful because not all of the .measure commands have been implemented so far! \end_layout \begin_layout Standard \series bold 'deriv' and 'error' is missing \end_layout \begin_layout Standard \series bold ************ \end_layout \begin_layout Standard * \end_layout \begin_layout Subsection Input \end_layout \begin_layout Standard In the following lines you will get some explanation on the .measure commands. A simple simulation file with two sines of different frequencies may serve as an example. The transient simulation delivers time as the independent variable and two voltages as output (dependent variables). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout File: simple-meas-tran.sp \end_layout \begin_layout Plain Layout * Simple .measurement examples \end_layout \begin_layout Plain Layout * transient simulation of two sine signals with different frequencies \end_layout \begin_layout Plain Layout vac1 1 0 DC 0 sin(0 1 1k 0 0) \end_layout \begin_layout Plain Layout vac2 2 0 DC 0 sin(0 1.2 0.9k 0 0) \end_layout \begin_layout Plain Layout .tran 10u 5m \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .measure tran ... $ for the different inputs see below! \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot v(1) v(2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard After displaying the general syntax of the .measurement statement, some examples are posted, referring to the input file given above. \end_layout \begin_layout Subsection Trig Targ \end_layout \begin_layout Standard .measure according to general form 1 measures the difference in dc voltage, frequency or time between two points selected from one or two output vectors. The current examples all are using transient simulation. Measurements for \series bold tran \series default analysis start after a delay time td. If you run other examples with \series bold ac \series default simulation or \series bold sp \series default ectrum analysis, time may be replaced by frequency, after a \series bold dc \series default simulation the independent variable may become a voltage or current. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 1: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result TRIG trig_variable VAL=val TARG targ_variable VAL=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement example (for use in the input file given above): \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5 V for the first time on its first rising slope (TRIG) versus reaching 0.5 V again on its second rising slope (TARG). I.e. it measures the signal period. \end_layout \begin_layout Standard Output: \end_layout \begin_layout Standard \family typewriter tdiff = 1.000000e-003 targ= 1.083343e-003 trig= 8.334295e-005 \end_layout \begin_layout Standard Measure statement example: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5 V for the first time on its rising slope versus reaching 0.5 V on its rising slope for the third time (i.e. two periods). \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5V for the first time on its rising slope versus reaching 0.5 V on its first falling slope. \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0V its third falling slope versus v(2) reaching 0 V on its third falling slope. \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1 \end_layout \begin_layout Standard measures the time difference between v(1) crossing -0.6 V for the first time (any slope) versus v(2) crossing -0.8 V for the first time (any slope). \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3 \end_layout \begin_layout Standard measures the time difference between the time point 1ms versus the time when v(2) crosses -0.8 V for the third time (any slope). \end_layout \begin_layout Subsection Find ... When \end_layout \begin_layout Standard The \series bold FIND \series default and \series bold WHEN \series default functions allow to measure any dependent or independent time, frequency, or dc parameter, when two signals cross each other or a signal crosses a given value. Measurements start after a delay TD and may be restricted to a range between FROM and TO. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 2: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result WHEN out_variable=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran teval WHEN v(2)=0.7 CROSS=LAST \end_layout \begin_layout Standard measures the time point when v(2) crosses 0.7 V for the last time (any slope). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 3: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result WHEN out_variable=out_variable2 \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran teval WHEN v(2)=v(1) RISE=LAST \end_layout \begin_layout Standard measures the time point when v(2) and v(1) are equal, v(2) rising for the last time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 4: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable WHEN out_variable2=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) WHEN v(1)=-0.4 FALL=LAST \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point when v(1) equals a value of -0.4, v(1) falling for the last time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 5: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable WHEN out_variable2=out_variable 3 \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) WHEN v(1)=v(3) FALL=2 \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point when v(1) crosses v(3), v(1) falling for the second time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 6: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable AT=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) AT=2m \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point 2 ms (given by AT=time). \end_layout \begin_layout Subsection AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 7: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result {AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT} out_variable \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statements: \end_layout \begin_layout Standard \family typewriter .measure tran ymax MAX v(2) from=2m to=3m \end_layout \begin_layout Standard returns the maximum value of v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Standard \family typewriter .measure tran tymax MAX_AT v(2) from=2m to=3m \end_layout \begin_layout Standard returns the time point of the maximum value of v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Standard \family typewriter .measure tran ypp PP v(1) from=2m to=4m \end_layout \begin_layout Standard returns the peak to peak value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Standard \family typewriter .measure tran yrms RMS v(1) from=2m to=4m \end_layout \begin_layout Standard returns the root mean square value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Standard \family typewriter .measure tran yavg AVG v(1) from=2m to=4m \end_layout \begin_layout Standard returns the average value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Subsection Integ \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 8: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result INTEG out_variable \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yint INTEG v(2) from=2m to=3m \end_layout \begin_layout Standard returns the area under v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Subsection param \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 9: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result param='expression' \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .param fval=5 \end_layout \begin_layout Standard \family typewriter .measure tran yadd param='fval + 7' \end_layout \begin_layout Standard will evaluate the given expression fval + 7 and return the value 12. \end_layout \begin_layout Standard \family typewriter .param vout_diff=50k \end_layout \begin_layout Standard \family typewriter .meas tran bw_chk param='(vout_diff < 100k) ? 1 : 0' \end_layout \begin_layout Standard will evaluate the given ternary function and return the value 1. \end_layout \begin_layout Standard 'Expression' is evaluated according to the rules given in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Syntax-of-expressions" \end_inset during start up of ngspice. Thus it may not contain vectors like v(10), e.g. anything resulting from a simulation. \end_layout \begin_layout Subsection par('expression') \end_layout \begin_layout Standard The \family typewriter \series bold par('expression') \family default \series default option ( \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ) allows to use algebraic expressions in the \family typewriter .measure \family default lines. Every out_variable may be replaced by par('expression') within the general forms 1-9 described above. Internally par('expression') will be substituted by a vector according to the rules of the B source (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset ). A typical example of the general form is shown below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form 10: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND par('expression') AT=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran vtest find par('(v(2)*v(1))') AT=2.3m \end_layout \begin_layout Standard will return the product of the two voltages at time point 2.3 ms. \end_layout \begin_layout Subsection Deriv \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable AT=val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable WHEN out_variable2=val + \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable \end_layout \begin_layout Plain Layout + WHEN out_variable2=out_variable3 \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold .MEASURE {DC|AC|TRAN|SP} result DERIV \family default ... is not yet available. \end_layout \begin_layout Subsection More examples \end_layout \begin_layout Standard Some other examples, also showing the use of parameters, are given below. Corresponding demonstration input files are distributed with ngspice in folder /examples/measure. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Other examples: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1 targ v(out) \end_layout \begin_layout Plain Layout +val='vp/2' rise=1 \end_layout \begin_layout Plain Layout .meas tran test_data1 trig AT = 1n targ v(out) val='vp/2' rise=3 \end_layout \begin_layout Plain Layout .meas tran out_slew trig v(out) val='0.2*vp' rise=2 targ v(out) \end_layout \begin_layout Plain Layout +val='0.8*vp' rise=2 \end_layout \begin_layout Plain Layout .meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' \end_layout \begin_layout Plain Layout .meas tran skew when v(out)=0.6 \end_layout \begin_layout Plain Layout .meas tran skew2 when v(out)=skew_meas \end_layout \begin_layout Plain Layout .meas tran skew3 when v(out)=skew_meas fall=2 \end_layout \begin_layout Plain Layout .meas tran skew4 when v(out)=skew_meas fall=LAST \end_layout \begin_layout Plain Layout .meas tran skew5 FIND v(out) AT=2n \end_layout \begin_layout Plain Layout .meas tran v0_min min i(v0) from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_avg avg i(v0) from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_integ integ i(v0) from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_rms rms i(v0) from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas dc is_at FIND i(vs) AT=1 \end_layout \begin_layout Plain Layout .meas dc is_max max i(vs) from=0 to=3.5 \end_layout \begin_layout Plain Layout .meas dc vds_at when i(vs)=0.01 \end_layout \begin_layout Plain Layout .meas ac vout_at FIND v(out) AT=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_atd FIND vdb(out) AT=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_max max v(out) from=1k to=10MEG \end_layout \begin_layout Plain Layout .meas ac freq_at when v(out)=0.1 \end_layout \begin_layout Plain Layout .meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out) val=0.1 fall=1 \end_layout \begin_layout Plain Layout .meas ac fixed_diff trig AT = 10k targ v(out) val=0.1 rise=1 \end_layout \begin_layout Plain Layout .meas ac vout_avg avg v(out) from=10k to=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_integ integ v(out) from=20k to=500k \end_layout \begin_layout Plain Layout .meas ac freq_at2 when v(out)=0.1 fall=LAST \end_layout \begin_layout Plain Layout .meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0' \end_layout \begin_layout Plain Layout .meas ac vout_rms rms v(out) from=10 to=1G \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Batch-Output" \end_inset Batch Output \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.SAVE-Lines" \end_inset .SAVE: Name vector(s) to be saved in raw file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .save vector vector vector ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .save i(vin) input output \end_layout \begin_layout Plain Layout .save @m1[id] \end_layout \begin_layout Plain Layout .save all @m2[vdsat] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The vectors listed on the .SAVE line are recorded in the rawfile for use later with ngspice or ngnutmeg (ngnutmeg is just the data-analysis half of ngspice, without the ability to simulate). The standard vector names are accepted. If no .SAVE line is given, then the default set of vectors are saved (node voltages and voltage source branch currents). If .SAVE lines are given, only those vectors specified are saved. For more discussion on internal device data, e.g. @m1[id], see Appendix, chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" \end_inset . If you want to save internal data in addition to the default vector set, add the parameter \series bold all \series default to the vectors to be saved. See also the section on the interactive command interpreter (chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset ) for information on how to use the rawfile. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.PRINT-Lines" \end_inset .PRINT Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .print prtype ov1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .print tran v(4) i(vin) \end_layout \begin_layout Plain Layout .print dc v(2) i(vsrc) v(23, 17) \end_layout \begin_layout Plain Layout .print ac vm(4, 2) vr(7) vp(8, 3) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .print \family default line defines the contents of a tabular listing of one to eight output variables. \family typewriter \series bold prtype \family default \series default is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired. The form for voltage or current output variables is the same as given in the previous section for the print command; Spice2 restricts the output variable to the following forms (though this restriction is not enforced by ngspice): \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout V(N1<,N2>) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \noindent specifies the voltage difference between nodes N1 and N2. If N2 (and the preceding comma) is omitted, ground (0) is assumed. See the print command in the previous section for more details. For compatibility with spice2, the following five additional values can be accessed for the ac analysis by replacing the "V" in V(N1,N2) with: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout VR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real part \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Imaginary part \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Magnitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20log10(magnitude) \end_layout \end_inset \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout I(VXXXXXXX) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout specifies the current flowing in the independent voltage source named VXXXXXXX. Positive current flows from the positive node, through the source, to the negative node. (Not yet implemented: For the ac analysis, the corresponding replacements for the letter I may be made in the same way as described for voltage outputs.) \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Output variables for the noise and distortion analyses have a different general form from that of the other analyses. There is no limit on the number of \family typewriter .print \family default lines for each type of analysis. The \family typewriter \series bold par('expression') \family default \series default option ( \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ) allows to use algebraic expressions in the \family typewriter .print \family default lines. \series bold .width \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.width" \end_inset ) selects the maximum number of characters per line. \end_layout \begin_layout Subsection .PLOT Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .plot pltype ov1 <(plo1, phi1)> ... ov8> \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .plot dc v(4) v(5) v(1) \end_layout \begin_layout Plain Layout .plot tran v(17, 5) (2, 5) i(vin) v(17) (1, 9) \end_layout \begin_layout Plain Layout .plot ac vm(5) vm(31, 24) vdb(5) vp(5) \end_layout \begin_layout Plain Layout .plot disto hd2 hd3(R) sim2 \end_layout \begin_layout Plain Layout .plot tran v(5, 3) v(4) (0, 5) v(7) (0, 10) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .plot \family default line defines the contents of one plot of from one to eight output variables. \family typewriter \series bold pltype \family default \series default is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired. The syntax for the \family typewriter \series bold ov \shape italic i \family default \series default \shape default is identical to that for the \family typewriter .print \family default line and for the plot command in the interactive mode. \end_layout \begin_layout Standard The overlap of two or more traces on any plot is indicated by the letter \begin_inset Quotes eld \end_inset X \begin_inset Quotes erd \end_inset . When more than one output variable appears on the same plot, the first variable specified is printed as well as plotted. If a printout of all variables is desired, then a companion \family typewriter .print \family default line should be included. There is no limit on the number of \family typewriter .plot \family default lines specified for each type of analysis. The \family typewriter \series bold par('expression') \family default \series default option ( \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ) allows to use algebraic expressions in the \family typewriter .plot \family default lines. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.FOUR:-Fourier-Analysis" \end_inset .FOUR: Fourier Analysis of Transient Analysis Output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .four freq ov1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .four 100K v(5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .four \family default (or Fourier) line controls whether ngspice performs a Fourier analysis as a part of the transient analysis. \family typewriter \series bold freq \family default \series default is the fundamental frequency, and \family typewriter \series bold ov1 \family default \series default is the desired vector to be analyzed. The Fourier analysis is performed over the interval , where TSTOP is the final time specified for the transient analysis, and period is one period of the fundamental frequency. The dc component and the first nine harmonics are determined. For maximum accuracy, TMAX (see the \family typewriter .tran \family default line) should be set to period/100.0 (or less for very high-Q circuits). The \family typewriter \series bold par('expression') \family default \series default option ( \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ) allows to use algebraic expressions in the \family typewriter .four \family default lines. \end_layout \begin_layout Subsection .PROBE: Name vector(s) to be saved in raw file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .probe vector \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .probe i(vin) input output \end_layout \begin_layout Plain Layout .probe @m1[id] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Same as .SAVE (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.SAVE-Lines" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:par('expression'):-Algebraic-expressions" \end_inset par('expression'): Algebraic expressions for output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout par('expression') \end_layout \begin_layout Plain Layout output=par('expression') $ not in .measure \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .four 1001 sq1=par('v(1)*v(1)') \end_layout \begin_layout Plain Layout .measure tran vtest find par('(v(2)*v(1))') AT=2.3m \end_layout \begin_layout Plain Layout .print tran output=par('v(1)/v(2)') v(1) v(2) \end_layout \begin_layout Plain Layout .plot dc v(1) diff=par('(v(4)-v(2))/0.01') out222 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In the output lines \family typewriter .four, .plot, .print, .save \family default and in the \family typewriter .measure \family default evaluation it is possible to add algebraic expression for output, in addition to vectors. All of these output lines accept \family typewriter \series bold par('expression') \family default \series default , where expression is any expression as has already been defined for the B source (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" \end_inset ). Thus \family typewriter \series bold expression \family default \series default may contain predefined functions, numerical values, constants, simulator output like v(n1) or i(vdb), parameters predefined by a .param statement, and the variables hertz, temper, and time. \end_layout \begin_layout Standard Internally expression is replaced by an internally generated voltage node, which is the output of a B source, one node and B source per par('...'). Several par('...') are allowed in each line, up to 99 per input file. The internal nodes are named pa_00 to pa_99. If your input file already contains such node names, an error will occur, unless you rename these nodes. \end_layout \begin_layout Standard In \family typewriter .four, .plot, .print, .save, \family default but not in \family typewriter .measure, \family default an alternative syntax \begin_inset Newline newline \end_inset \family typewriter \series bold output=par('expression') \family default \series default is possible. \family typewriter \series bold par('expression') \family default \series default may be used as described above. \family typewriter \series bold output \family default \series default is the name of the new node to replace the expression. So \family typewriter \series bold output \family default \series default has to be unique and a valid node name. \end_layout \begin_layout Standard The syntax of \family typewriter \series bold output=par('expression') \family default \series default is strict, no spaces between par and (', or between ( and ' are allowed, (' and ') both are required. Also there is not much error checking on your input, if there is a typo, for example, an error may pop up at an unexpected place. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:.width" \end_inset .width \end_layout \begin_layout Standard Set the width of a print-out or plot with the following card: \end_layout \begin_layout Standard \family typewriter .with out = 256 \end_layout \begin_layout Standard Parameter \series bold out \series default yields the maximum number of characters plotted in a row, if printing in columns or an ASCII-plot is selected. \end_layout \begin_layout Chapter Starting ngspice \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard Ngspice consists of the simulator and a front-end for data analysis and plotting. Input to the simulator is a netlist file, including commands for circuit analysis and output control. Interactive ngspice can plot data from a simulation on a PC or a workstation display. \end_layout \begin_layout Standard Ngspice on LINUX (and OSs like Cygwin, BCD, Solaris ...) uses the X Window System for plotting (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:LINUX" \end_inset ) if the environment variable DISPLAY is available. Otherwise, a console mode (non-graphical) interface is used. If you are using X on a workstation, the DISPLAY variable should already be set; if you want to display graphics on a system different from the one you are running ngspice or ngutmeg on, DISPLAY should be of the form "machine:0.0". See the appropriate documentation on the X Window System for more details. \end_layout \begin_layout Standard The MS Windows versions of ngspice and ngnutmeg will have a native graphics interface (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:MS-Windows" \end_inset ). \end_layout \begin_layout Standard The front-end may be run as a separate "stand-alone" program under the name ngnutmeg. ngnutmeg is a subset of ngspice dedicated to data evaluation, still made available for historical reasons. Ngnutmeg will read in the "raw" data output file created by ngspice -r or by the write command during an interactive ngspice session. \end_layout \begin_layout Section Where to obtain ngspice \end_layout \begin_layout Standard The actual distribution of ngspice may be downloaded from the \begin_inset CommandInset href LatexCommand href name "ngspice download web page" target "http://sourceforge.net/projects/ngspice/files/" \end_inset . The installation for LINUX or MS Windows is described in the file \series bold INSTALL \series default to be found in the top level directory. \end_layout \begin_layout Standard If you want to check out the source code which is actually under development, you may have a look at the ngspice source code repository, which is stored using the concurrent version system (CVS). The CVS repository may be browsed on the \begin_inset CommandInset href LatexCommand href name "CVS web page" target "http://ngspice.cvs.sourceforge.net/viewvc/ngspice/ngspice/ng-spice-rework/" \end_inset , also useful for downloading individual files. You may however download (or check out) the complete source code tree from the console window (LINUX, CYGWIN or MSYS/MINGW) by issuing the command (in a single line) \end_layout \begin_layout Standard \family typewriter cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice \begin_inset Newline newline \end_inset -lf co -P ngspice/ng-spice-rework \end_layout \begin_layout Standard You need to have CVS installed, which is available for all three OSs. The whole source tree is then available in /ngspice/ng-spice -rework. Compilation and local installation is again described in \series bold INSTALL \series default . If you later want to update your files and download the recent changes from the repository, cd into the ng-spice-rework directory and just type \end_layout \begin_layout Standard \family typewriter cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice \begin_inset Newline newline \end_inset -lf update -d -P \end_layout \begin_layout Section Command line options for starting ngspice and ngnutmeg \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Command Synopsis: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice [ -o logfile ] [ -r rawfile] [ -b ] [ -i ] [ input file ... ] \end_layout \begin_layout Plain Layout ngnutmeg [ - ] [ datafile ... ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Options are: \end_layout \begin_layout Standard \noindent \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Option \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Long option \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meaning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \align left Don't try to load the default data file ("rawspice.raw") if no other files are given (ngnutmeg only). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --no-spiceinit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Don't try to source the file ".spiceinit" upon start-up. Normally ngspice and ngnutmeg try to find the file in the current directory, and if it is not found then in the user's home directory (obsolete). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -t TERM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --terminal=TERM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The program is being run on a terminal with mfb name term (obsolete). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -b \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --batch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \noindent Run in batch mode. Ngspice reads the default input source (e.g. keyboard) or reads the given input file and performs the analyses specified; output is either Spice2-like line-printer plots ("ascii plots") or a ngspice rawfile. See the following section for details. Note that if the input source is not a terminal (e.g. using the IO redirection notation of "<") ngspice defaults to batch mode (-i overrides). This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --server \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Run in server mode. This is like batch mode, except that a temporary rawfile is used and then written to the standard output, preceded by a line with a single "@", after the simulation is done. This mode is used by the ngspice daemon. This option is valid for ngspice only. \end_layout \begin_layout Plain Layout Example for using pipes from the console window: \end_layout \begin_layout Plain Layout \family typewriter cat adder.cir|ngspice -s|more \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --interactive \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Run in interactive mode. This is useful if the standard input is not a terminal but interactive mode is desired. Command completion is not available unless the standard input is a terminal, however. This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -r FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --rawfile=FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Use rawfile as the default file into which the results of the simulation are saved. This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --pipe \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Allow a program (e.g., xcircuit) to act as a GUI frontend for ngspice through a pipe. Thus ngspice will assume that the input pipe is a tty and allows to run in interactive mode. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -o FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --output=FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout All logs generated during a batch run (-b) will be saved in outfile. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --help \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A short help statement of the command line syntax. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -v \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --version \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Prints a version information. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -a \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout --autorun \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Start simulation immediately, as if a control section \end_layout \begin_layout Plain Layout \family typewriter .control \end_layout \begin_layout Plain Layout \family typewriter run \end_layout \begin_layout Plain Layout \family typewriter .endc \end_layout \begin_layout Plain Layout had been added to the input file. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Further arguments to ngspice are taken to be ngspice input files, which are read and saved (if running in batch mode then they are run immediately). Ngspice accepts Spice3 (and also most Spice2) input files, and outputs ASCII plots, Fourier analyses, and node printouts as specified in \family typewriter .plot \family default , \family typewriter .four \family default , and \family typewriter .print \family default cards. If an out parameter is given on a \family typewriter .width \family default card ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.width" \end_inset ), the effect is the same as \family sans set width = .... \family default Since ngspice ASCII plots do not use multiple ranges, however, if vectors together on a \family typewriter .plot \family default card have different ranges they do not provide as much information as they do in a scalable graphics plot. \end_layout \begin_layout Standard For ngnutmeg, further arguments are taken to be data files in binary or ASCII raw file format (generated with -r in batch mode or the \series bold write \series default (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Write:-Write-data" \end_inset ) command) which are loaded into ngnutmeg. If the file is in binary format, it may be only partially completed (useful for examining output before the simulation is finished). One file may contain any number of data sets from different analyses. \end_layout \begin_layout Section Starting options \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Batch-mode" \end_inset Batch mode \end_layout \begin_layout Standard Let's take as an example the Four-Bit binary adder MOS circuit shown in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:MOS-Four-Bit" \end_inset , stored in a file \series bold adder-mos.cir \series default . You may start the simulation immediately by calling \end_layout \begin_layout Standard \family typewriter ngspice -b -r adder.raw -o adder.log adder-mos.cir \end_layout \begin_layout Standard ngspice will start, simulate according to the .tran command and store the output data in a rawfile adder.raw. Comments, warnings and infos go to log file adder.log. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Interactive-mode" \end_inset Interactive mode \end_layout \begin_layout Standard If you call \end_layout \begin_layout Standard \family typewriter ngspice adder-mos.cir \end_layout \begin_layout Standard ngspice will start, load the circuit file, parse the circuit and then wait for your input. You may then start the simulation by issuing the \family typewriter run \family default command, and following completion you may analyze the data by any of the commands given in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Interactive-mode-with" \end_inset Interactive mode with control file or control section \end_layout \begin_layout Standard If you add the following control section to your input file adder-mos.cir, you may call \end_layout \begin_layout Standard \family typewriter ngspice adder-mos.cir \end_layout \begin_layout Standard and see ngspice starting, simulating and then plotting immediately. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control section: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot vcc#branch \end_layout \begin_layout Plain Layout rusage all \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Any suitable command listed in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset may be added to the control section, as well as control structures described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" \end_inset . Batch-like behavior may be obtained by changing the control section to \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control section with batch-like behavior: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write adder.raw vcc#branch \end_layout \begin_layout Plain Layout quit \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you put this control section into a file, say adder-start.sp, you may just add the line \end_layout \begin_layout Standard \family typewriter .include adder-start.sp \end_layout \begin_layout Standard to your input file adder-mos.cir to obtain the batch-like behavior. In the following example the line \family typewriter .tran ... \family default from the input file is overridden by the \series bold tran \series default command given in the control section. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control section overriding the .tran command: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noaskquit \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout tran 1n 500n \end_layout \begin_layout Plain Layout plot vcc#branch \end_layout \begin_layout Plain Layout rusage all \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Standard-configuration-file" \end_inset Standard configuration file spinit \end_layout \begin_layout Standard Upon start up ngspice reads its configuration file \family typewriter \series bold spinit \family default \series default . \family typewriter \series bold spinit \family default \series default may be found in \begin_inset Newline newline \end_inset C: \backslash Spice \backslash share \backslash ngspice \backslash scripts (Windows) or /usr/local/share/ngspice/scripts (LINUX). The path may be overridden by setting the environmental variable SPICE_LIB_DIR to a path where /scripts will be added. ngspice for Windows will also search for \family typewriter \series bold spinit \family default \series default in the directory where ngspice.exe resides. If \family typewriter \series bold spinit \family default \series default is not found, a warning message is issued, but ngspice will continue (but of course without code models etc.). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Standard spinit contents: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Standard ngspice init file \end_layout \begin_layout Plain Layout alias exit quit \end_layout \begin_layout Plain Layout alias acct rusage all \end_layout \begin_layout Plain Layout set x11lineararcs \end_layout \begin_layout Plain Layout *set rndseed=12 \end_layout \begin_layout Plain Layout *set filetype=ascii \end_layout \begin_layout Plain Layout *set ngdebug \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout *unset brief \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout strcmp __flag $program "ngspice" \end_layout \begin_layout Plain Layout if $__flag = 0 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * For SPICE2 POLYs, edit the below line to point to the location \end_layout \begin_layout Plain Layout * of your codemodel. \end_layout \begin_layout Plain Layout codemodel C:/Spice/lib/spice/spice2poly.cm \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * The other codemodels \end_layout \begin_layout Plain Layout codemodel C:/Spice/lib/spice/analog.cm \end_layout \begin_layout Plain Layout codemodel C:/Spice/lib/spice/digital.cm \end_layout \begin_layout Plain Layout codemodel C:/Spice/lib/spice/xtradev.cm \end_layout \begin_layout Plain Layout codemodel C:/Spice/lib/spice/xtraevt.cm \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout unset __flag \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard spinit contains a script which is run upon start up of ngspice. You may find details of scripting in the next chapter. Aliases (name equivalences) are set. \family typewriter set filetype=ascii \family default will yield ASCII output in the output data file (rawfile), a more compact binary format is used otherwise. The asterisk '*' will comment out this line. If used by ngspice, spinit will then load the XSPICE code models from their absolute paths. You may also define relative paths here. \family typewriter set ngdebug \family default will yield a lot of additional debug output. Any other contents of the script. e.g. plotting preferences, may be included here and started automatically by ngspice. The compatibility mode of ngspice has to be set in spinit by \family typewriter set ngbehavior=all. \end_layout \begin_layout Standard If the standard path for the libraries (see standard spinit above or \family typewriter /usr/local/lib/spice \family default under CYGWIN and LINUX) is not adequate, you may add for example the ./configure options \family typewriter --prefix=/usr --libdir=/usr/lib64 \family default to set the codemodel search path to \family typewriter /usr/lib64/spice \family default . Besides the standard \family typewriter lib \family default only \family typewriter lib64 \family default is acknowledged. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:User-defined-configuration" \end_inset User defined configuration file .spiceinit \end_layout \begin_layout Standard In addition to \family typewriter \series bold spinit \family default \series default you may define a file \family typewriter \series bold .spiceinit \family default \series default and put it into the current directory or in your home directory. This file will be read in and executed after \family typewriter \series bold spinit \family default \series default , but before any other input file is read. It may contain any script and override the commands given in \family typewriter \series bold spinit \family default \series default . If the command line option \family typewriter -n \family default is used upon ngspice start up, this file will be ignored. \end_layout \begin_layout Section Environmental variables \end_layout \begin_layout Subsection Ngspice specific variables \end_layout \begin_layout Description SPICE_LIB_DIR default: /usr/local/share/ngspice (LINUX, CYGWIN), C: \backslash Spice \backslash share \backslash ngspice (Windows) \end_layout \begin_layout Description SPICE_EXEC_DIR default: /usr/local/bin (LINUX, CYGWIN), C: \backslash Spice \backslash bin (Windows) \end_layout \begin_layout Description SPICE_BUGADDR default: http://ngspice.sourceforge.net/bugrep.html \begin_inset Newline newline \end_inset Where to send bug reports on ngspice. \end_layout \begin_layout Description SPICE_EDITOR default: vi (LINUX, CYGWIN), notepad.exe (MINGW, Visual Studio) \begin_inset Newline newline \end_inset Set the editor called in the \series bold edit \series default command. Always overrides the EDITOR env. variable. \end_layout \begin_layout Description SPICE_ASCIIRAWFILE default: 0 \begin_inset Newline newline \end_inset Format of the rawfile. 0 for binary, and 1 for ascii. \end_layout \begin_layout Description SPICE_NEWS default: $SPICE_LIB_DIR/news \begin_inset Newline newline \end_inset A file which is copied verbatim to stdout when ngspice starts in interactive mode. \end_layout \begin_layout Description SPICE_HELP_DIR default: $SPICE_LIB_DIR/helpdir \begin_inset Newline newline \end_inset Help directory, not used in Windows mode \end_layout \begin_layout Description SPICE_HOST default: empty string \begin_inset Newline newline \end_inset Used in the \series bold rspice \series default command (probably obsolete, to be documented) \end_layout \begin_layout Description SPICE_SCRIPTS default: $SPICE_LIB_DIR/scripts \begin_inset Newline newline \end_inset In this directory the spinit file will be searched. \end_layout \begin_layout Description SPICE_PATH default: $SPICE_EXEC_DIR/ngspice \begin_inset Newline newline \end_inset Used in the \series bold aspice \series default command (probably obsolete, to be documented) \end_layout \begin_layout Description NGSPICE_MEAS_PRECISION default: 5 \begin_inset Newline newline \end_inset Sets the number of digits if output values are printed by the \series bold meas(ure) \series default command. \end_layout \begin_layout Description SPICE_NO_DATASEG_CHECK default: undefined \begin_inset Newline newline \end_inset If defined, will suppress memory resource info (probably obsolete, not used on Windows or where the /proc information system is available.) \end_layout \begin_layout Description NGSPICE_INPUT_DIR default: undefined \begin_inset Newline newline \end_inset If defined, using a valid directory name,, will add the given directory to the search path when looking for input files (*.cir, *.inc, *.lib). \end_layout \begin_layout Subsection Common environment variables \end_layout \begin_layout Standard \series bold TERM LINES COLS DISPLAY HOME PATH EDITOR SHELL POSIXLY_CORRECT \end_layout \begin_layout Section Memory usage \end_layout \begin_layout Standard Ngspice started with batch option (-b) and rawfile output (-r rawfile) will store all simulation data immediately into the rawfile without keeping them in memory. Thus very large circuits may be simulated, the memory requested upon ngspice start up will depend on the circuit size, but will not increase during simulation. \end_layout \begin_layout Standard If you start ngspice in interactive mode or interactively with control section, all data will be kept in memory, to be available for later evaluation. A large circuit may outgrow even Gigabytes of memory. The same may happen after a very long simulation run with many vectors and many time steps to be stored. Issuing the \family typewriter save \family default command will help to reduce memory requirements by saving only the data defined by the command. \end_layout \begin_layout Section Simulation time \end_layout \begin_layout Standard Simulating large circuits may take an considerable amount of CPU time. If this is of importance, you should compile ngspice with the flags for optimum speed, set during configuring ngspice compilation. Under LINUX, MINGW, and CYGWIN you should select the following option to disable the debug mode, which slows down ngspice: \end_layout \begin_layout Standard \family typewriter ./configure --disable-debug \end_layout \begin_layout Standard Adding \family typewriter --disable-debug \family default will set the -O2 optimization flag for compiling and linking. \end_layout \begin_layout Standard Under MS Visual Studio, you will have to select the \series bold release \series default version which includes optimization for speed. \end_layout \begin_layout Standard If you have selected XSPICE (see chapters \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "par:XSPICE-Software-User's" \end_inset ) as part of your compilation configuration (by adding the option \family typewriter --enable-xspice \family default to your \family typewriter ./configure \family default command), the value of \series bold trtol \series default (see \begin_inset CommandInset ref LatexCommand ref reference "des:TRTOL" \end_inset ) is set internally to 1 (instead of default 7) for higher precision if XSPICE code model 'A' devices included in the circuit. This may double or even triple the CPU time needed for any transient simulation , because the amount of time steps and thus iteration steps is more than doubled. For MS Visual Studio compilation there is currently no simple way to exclude XSPICE during compilation. \end_layout \begin_layout Standard You may enforce higher speed setting the \series bold option \series default \family typewriter trtol=7 \family default in your \series bold .spiceinit \series default initialization file (via the option command \begin_inset CommandInset ref LatexCommand ref reference "sub:Option*:" \end_inset ) or in your circuit input file (via an .options line \begin_inset CommandInset ref LatexCommand ref reference "sec:Simulator-Variables" \end_inset ) to obtain standard spice3 tolerances and a speed gain of two. Beware however of convergence or precision issues if you use XSPICE 'A' devices. \end_layout \begin_layout Standard If your circuit comprises mostly of MOS transistors, and you have a multi-core processor at hand, you may benefit from OpenMP parallel processing, as described next ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-on-multi-core" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Ngspice-on-multi-core" \end_inset Ngspice on multi-core processors using OpenMP \end_layout \begin_layout Subsection Introduction \end_layout \begin_layout Standard Today's computers typically come with CPUs having more than one core. It will thus be useful to enhance ngspice to make use of such multi-core processors. \end_layout \begin_layout Standard Using circuits comprising mostly of transistors and e.g. the BSIM3 model, around 2/3 of the CPU time is spent in evaluating the model equations (e.g. in the BSIM3Load() function). The same happens with other advanced transistor models. Thus this function should be paralleled, if possible. Resulting from that the parallel processing has to be within a dedicated device model. Interestingly solving the matrix takes only about 10% of the CPU time, so paralleling the matrix solver is of secondary interest here! \end_layout \begin_layout Standard A recent publication [1] has described a way to exactly do that using OpenMP, which is available on many platforms and is easy to use, especially if you want to parallel processing of a for-loop. \end_layout \begin_layout Standard I have chosen the BSIM3 version 3.3.0 model, located in the BSIM3 directory, as the first example. The BSIM3load() function in b3ld.c contains two nested for-loops using linked lists (models and instances, e.g. individual transistors). Unfortunately OpenMP requires a loop with an integer index. So in file B3set.c an array is defined, filled with pointers to all instances of BSIM3 and stored in model->BSIM3InstanceArray. \end_layout \begin_layout Standard BSIM3load() is now a wrapper function, calling the for-loop, which runs through functions BSIM3LoadOMP(), once per instance. Inside BSIM3LoadOMP() the model equations are calculated. \end_layout \begin_layout Standard Typically you now need to synchronize the activities, in that storing the results into the matrix has to be guarded. The trick offered by the authors now is that the storage is moved out of the BSIM3LoadOMP() function. Inside BSIM3LoadOMP() the updated data are stored in extra locations locally per instance, defined in bsim3def.h. Only after the complete for-loop is exercised, the update to the matrix is done in an extra function BSIM3LoadRhsMat() in the main thread after the paralleled loop. No extra synchronization is required. \end_layout \begin_layout Standard Then the thread programming needed is only a single line!! \end_layout \begin_layout Standard \family typewriter #pragma omp parallel for num_threads(nthreads) private(here) \end_layout \begin_layout Standard introducing the for-loop. \end_layout \begin_layout Standard This of course is made possible only thanks to the OpenMP guys and the clever trick on no synchronization introduced by the above cited authors. \end_layout \begin_layout Standard The time-measuring function \family typewriter getrusage() \family default used with LINUX or Cygwin to determine the CPU time usage (with the \family typewriter rusage \family default option enabled) counts tics from every core, adds them up, and thus reports a CPU time value enlarged by a factor of 8 if 8 threads have been chosen. So now ngspice is forced to use \family typewriter ftime \family default for time measuring if OpenMP is selected. \end_layout \begin_layout Subsection Some results \end_layout \begin_layout Standard Some results on an inverter chain with 627 CMOS inverters, running for 200ns, compiled with Visual Studio professional 2008 on Windows 7 (full optimization) or gcc 4.4, SUSE LINUX 11.2, -O2, on a i7 860 machine with four real cores (and 4 virtuals using hyperthreading) are shown in table \begin_inset CommandInset ref LatexCommand ref reference "tab:OpenMP-performance" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:OpenMP-performance" \end_inset OpenMP performance \end_layout \end_inset \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter Threads \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter CPU time [s] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter CPU time [s] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Windows \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter LINUX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 1 (standard) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 167 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 165 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 1 (OpenMP) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 174 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 167 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 110 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 110 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 95 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 94-120 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 83 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 107 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 94 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 90 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 8 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 93 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 91 \end_layout \end_inset \end_inset \end_layout \end_inset \end_layout \begin_layout Standard So we see a ngspice speed up of nearly a factor of two! Even on an older notebook with dual core processor, I have got more than 1.5x improvement using two threads. Similar results are to be expected from BSIM4. \end_layout \begin_layout Subsection Usage \end_layout \begin_layout Standard To state it clearly: OpenMP is installed inside the model equations of a particular model. So for the moment it is available only in \series bold BSIM3 version 3.3.0 \series default , not in version 3.2.4 nor in any other BSIM3 model, in \series bold BSIM4 versions 4.6.5 \series default or \series bold 4.7 \series default , not in any other BSIM4 model, and in B4SOI, version 4.3.1, not in any other SOI model. Older parameter files of version 4.6.x (x any number up to 5) are accepted, you have to check for compatibility. \end_layout \begin_layout Standard Under \series bold LINUX \series default you may run \end_layout \begin_layout Standard \family typewriter ./autogen.sh \end_layout \begin_layout Standard \family typewriter ./configure ... \series bold --enable-openmp \end_layout \begin_layout Standard \family typewriter make install \end_layout \begin_layout Standard The same has been tested under MS Windows with \series bold CYGWIN \series default and \series bold MINGW \series default as well and delivers similar results. \end_layout \begin_layout Standard Under \series bold MS Windows \series default with \series bold Visual Studio Professional \series default you have to place an additional preprocessor flag \series bold USE_OMP \series default , and then enable \series bold /openmp \series default . Visual Studio Express is not sufficient due to lack of OpenMP support. Even Visual Studio Professional lacks debugging support for OpenMP. There are local preprocessor flags (USE_OMP3 in bsim3def.h, USE_OMP4 in bsim4def.h, and USE_OMP4SOI in b4soidef.h) which you may modify individually if you want to switch off OpenMP in only one of the models BSIM3, BSIM4, or B4SOI. \end_layout \begin_layout Standard The number of threads has to be set manually by placing \end_layout \begin_layout Standard \family typewriter set num_threads=4 \end_layout \begin_layout Standard into spinit or .spiceinit. If OpenMP is enabled, but num_threads not set, a default value \family typewriter num_threads=2 \family default is set internally. \end_layout \begin_layout Standard If you run a circuit, please keep in mind to select BSIM3 (levels 8, 49) version 3.3.0 ( \begin_inset CommandInset ref LatexCommand ref reference "sub:BSIM3-model" \end_inset ), by placing this version number into your parameter files, BSIM4 (levels 14, 54) version 4.6.5 or 4.7 ( \begin_inset CommandInset ref LatexCommand ref reference "sub:BSIM4-model" \end_inset ), or B4SOI (levels 10, 58) version 4.3.1 ( \begin_inset CommandInset ref LatexCommand ref reference "sub:BSIMSOI-models" \end_inset ). \end_layout \begin_layout Standard If you run ./configure without \family typewriter --enable-openmp \family default (or without USE_OMP preprocessor flag under MS Windows), you will get the standard, not paralleled BSIM3 and BSIM4 model, as has been available from Berkeley. If OpenMP is selected and the number of threads set to 1, there will be only a very slight CPU time disadvantage (typ. 3%) compared to the standard, non OpenMP build. \end_layout \begin_layout Subsection Literature \end_layout \begin_layout Standard [1] R.K. Perng, T.-H. Weng, and K.-C. Li: "On Performance Enhancement of Circuit Simulation Using Multithreaded Techniques", IEEE International Conference on Computational Science and Engineering, 2009, pp. 158-165 \end_layout \begin_layout Section Server mode option -s \end_layout \begin_layout Standard A program may write the spice input to the console. This output is redirected to ngspice via '|'. ngspice called with the -s option writes its output to the console, which again is redirected to a receiving program by '|'. In the following simple example \series bold cat \series default reads the input file and prints it content to the console, which is redirected to ngspice by a first pipe, ngspice transfers its output (similar to a raw file, see below) to \series bold less \series default via another pipe. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example command line: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout cat input.cir|ngspice -s|less \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Under MS Windows you will need to compile ngspice as a console application (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:ngspice-mingw-or" \end_inset ) for this server mode usage. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout test -s \end_layout \begin_layout Plain Layout v1 1 0 1 \end_layout \begin_layout Plain Layout r1 1 0 2k \end_layout \begin_layout Plain Layout .options filetype=ascii \end_layout \begin_layout Plain Layout .save i(v1) \end_layout \begin_layout Plain Layout .dc v1 -1 1 0.5 \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you start ngspice console with \end_layout \begin_layout LyX-Code ngspice -s \end_layout \begin_layout Standard you may type in the above circuit line by line (not to forget the first line, which is a title and will be ignored). If you close your input with \family typewriter ctrl Z \family default , and \family typewriter return \family default , you will get the following output (this is valid for MINGW only) on the console, like a raw file: \end_layout \begin_layout LyX-Code Circuit: test -s \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset Title: test -s \end_layout \begin_layout LyX-Code Date: Sun Jan 15 18:57:13 2012 \end_layout \begin_layout LyX-Code Plotname: DC transfer characteristic \end_layout \begin_layout LyX-Code Flags: real \end_layout \begin_layout LyX-Code No. Variables: 2 \end_layout \begin_layout LyX-Code No. Points: 0 \end_layout \begin_layout LyX-Code Variables: \end_layout \begin_layout LyX-Code No. of Data Columns : 2 \end_layout \begin_layout LyX-Code 0 v(v-sweep) voltage \end_layout \begin_layout LyX-Code 1 i(v1) current \end_layout \begin_layout LyX-Code Values: \end_layout \begin_layout LyX-Code 0 -1.000000000000000e+000 \end_layout \begin_layout LyX-Code 5.000000000000000e-004 \end_layout \begin_layout LyX-Code 1 -5.000000000000000e-001 \end_layout \begin_layout LyX-Code 2.500000000000000e-004 \end_layout \begin_layout LyX-Code 2 0.000000000000000e+000 \end_layout \begin_layout LyX-Code 0.000000000000000e+000 \end_layout \begin_layout LyX-Code 3 5.000000000000000e-001 \end_layout \begin_layout LyX-Code -2.500000000000000e-004 \end_layout \begin_layout LyX-Code 4 1.000000000000000e+000 \end_layout \begin_layout LyX-Code -5.000000000000000e-004 \end_layout \begin_layout LyX-Code @@@ 122 5 \end_layout \begin_layout Standard The number \family typewriter 5 \family default of the last line \family typewriter @@@ 122 5 \family default shows the number of data points, which is missing in the above line \family typewriter No. Points: 0 \family default because at the time of writing to the console it has not yet been available. \end_layout \begin_layout Standard \family typewriter ctrl Z \family default is not usable here in LINUX, a patch to install \family typewriter ctrl D \family default instead is being evaluated. \end_layout \begin_layout LyX-Code \end_layout \begin_layout Section Ngspice control via input, output fifos \end_layout \begin_layout Standard The following bash script (under LINUX) \end_layout \begin_layout Standard - launches ngspice in another thread. \end_layout \begin_layout Standard - writes some commands in ngspice input \end_layout \begin_layout Standard - reads the output and prints them on the console. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout #!/usr/bin/env bash \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout NGSPICE_COMMAND="ngspice" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout rm input.fifo \end_layout \begin_layout Plain Layout rm output.fifo \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout mkfifo input.fifo \end_layout \begin_layout Plain Layout mkfifo output.fifo \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout $NGSPICE_COMMAND -p -i output.fifo & \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout exec 3>input.fifo \end_layout \begin_layout Plain Layout echo "I can write to input.fifo" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "Start processing..." \end_layout \begin_layout Plain Layout echo "" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "source circuit.cir" >&3 \end_layout \begin_layout Plain Layout echo "set noaskquit" >&3 \end_layout \begin_layout Plain Layout echo "set nobreak" >&3 \end_layout \begin_layout Plain Layout echo "tran 0.01ms 0.1ms">&3 \end_layout \begin_layout Plain Layout echo "print n0" >&3 \end_layout \begin_layout Plain Layout echo "quit" >&3 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "Try to open output.fifo ..." \end_layout \begin_layout Plain Layout exec 4&- \end_layout \begin_layout Plain Layout exec 4>&- \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "End processing" \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The input file for \series bold spice \series default is: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Circuit.cir: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Circuit.cir \end_layout \begin_layout Plain Layout V1 n0 0 SIN(0 10 1kHz) \end_layout \begin_layout Plain Layout C1 n1 n0 3.3nF \end_layout \begin_layout Plain Layout R1 0 n1 1k \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Compatibility" \end_inset Compatibility \end_layout \begin_layout Standard ngspice is a direct derivative of spice3f5 from UC Berkeley and thus inherits all of the commands available in its predecessor. Thanks to the open source policy of UCB (original spice3 from 1994 is still available \begin_inset CommandInset href LatexCommand href name "here" target "http://embedded.eecs.berkeley.edu/pubs/downloads/spice/index.htm" \end_inset ), several commercial variants have sprung off, either being more dedicated to IC design or more concentrating on simulating discrete and board level electronics. None of the commercial and almost none of the freely downloadable spice providers publishes the source code. All of them have proceeded with the development, by adding functionality, or by adding a more dedicated user interface. Some have kept the original spice syntax for their netlist description, others have quickly changed some if not many of the commands, functions and procedures. Thus it is difficult, if not impossible, to offer a simulator which aknowledges all of these netlist dialects. ngspice includes some features which enhance compatibility which are included automatically. This selection may be controlled to some extend by setting the compitibility mode. Others may be invoked by the user by small additions to the netlist input file. Some of them are listed in this chapter, some will be integrated into ngspice at a later stage, others will be added if they are reported by users. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Compatibility-mode" \end_inset Compatibility mode \end_layout \begin_layout Standard The variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset ) ngbehavior sets the compatibility mode. \family typewriter 'all' \family default is set as the default value. \family typewriter 'spice3' \family default as invoked by the command \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=spice3 \family default \end_layout \begin_layout Standard in \family typewriter \series bold spinit \family default \series default or \family typewriter \series bold .spiceinit \family default \series default will disable some of the advanced ngspice features. \family typewriter 'ps' \family default will enable including a library by a simple \family typewriter .lib \family default statement which is not compatible to the more comfortable library handling described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:.LIB" \end_inset . \end_layout \begin_layout Subsection Missing functions \end_layout \begin_layout Standard You may add one or more function definitions to your input file, as listed below. \end_layout \begin_layout LyX-Code .func LIMIT(x,a,b) {min(max(x, a), b)} \end_layout \begin_layout LyX-Code .func PWR(x,a) {abs(x) ** a} \end_layout \begin_layout LyX-Code .func PWRS(x,a) {sgn(x) * PWR(x,a)} \end_layout \begin_layout LyX-Code .func stp(x) {u(x)} \end_layout \begin_layout Subsection Devices \end_layout \begin_layout Subsubsection E Source with LAPLACE \end_layout \begin_layout Standard see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:LAPLACE" \end_inset . \end_layout \begin_layout Subsubsection VSwitch \end_layout \begin_layout Standard The VSwitch \end_layout \begin_layout LyX-Code S1 2 3 11 0 SW \end_layout \begin_layout LyX-Code .MODEL SW VSWITCH(VON=5V VOFF=0V RON=0.1 ROFF=100K) \end_layout \begin_layout Standard may become \end_layout \begin_layout LyX-Code a1 11 (2 3) sw \end_layout \begin_layout LyX-Code .MODEL SW aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e5 \end_layout \begin_layout LyX-Code + r_on=0.1 log=TRUE) \end_layout \begin_layout Standard The XSPICE option has to be enabled. \end_layout \begin_layout Subsection Controls and commands \end_layout \begin_layout Subsubsection .lib \end_layout \begin_layout Standard The ngspice .lib command (see \begin_inset CommandInset ref LatexCommand ref reference "sec:.LIB" \end_inset ) requires two parameters, a file name followed by a library name. If no library name is given, the line \end_layout \begin_layout LyX-Code .lib filename \end_layout \begin_layout Standard should be replaced by \end_layout \begin_layout LyX-Code .inc filename \end_layout \begin_layout Standard Alternatively, the compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Compatibility-mode" \end_inset ) may be set to \family typewriter 'ps' \family default . \end_layout \begin_layout Subsubsection .step \end_layout \begin_layout Standard Repeated analysis in ngspice if offered by a short script inside of a .control section (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Parameter-sweep" \end_inset ) added to the input file. A simple application (multiple dc sweeps) is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file with parameter sweep \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout parameter sweep \end_layout \begin_layout Plain Layout * resistive divider, R1 swept from start_r to stop_r \end_layout \begin_layout Plain Layout * replaces .STEP R1 1k 10k 1k \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout R1 1 2 1k \end_layout \begin_layout Plain Layout R2 2 0 1k \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout VDD 1 0 DC 1 \end_layout \begin_layout Plain Layout .dc VDD 0 1 .1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout let start_r = 1k \end_layout \begin_layout Plain Layout let stop_r = 10k \end_layout \begin_layout Plain Layout let delta_r = 1k \end_layout \begin_layout Plain Layout let r_act = start_r \end_layout \begin_layout Plain Layout * loop \end_layout \begin_layout Plain Layout while r_act le stop_r \end_layout \begin_layout Plain Layout alter r1 r_act \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write dc-sweep.out v(2) \end_layout \begin_layout Plain Layout set appendwrite \end_layout \begin_layout Plain Layout let r_act = r_act + delta_r \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2) \end_layout \begin_layout Plain Layout + dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section Reporting bugs and errors \end_layout \begin_layout Standard Ngspice is a complex piece of software. The source code contains over 1500 files. Various models and simulation procedures are provided, some of them not used and tested intensively. Therefore errors may be found, some still evolving from the original spice3f5 code, others introduced during the ongoing code enhancements. \end_layout \begin_layout Standard If you happen to experience an error during the usage of ngspice, please send a report to the development team. Ngspice is hosted on sourceforge, the preferred place to post a bug report is the \begin_inset CommandInset href LatexCommand href name "ngspice bug tracker" target "http://sourceforge.net/tracker/?group_id=38962&atid=423915" \end_inset . We would prefer to have your bug tested against the actual source code available at CVS, but of course a report using the most recent ngspice release is welcome! Please provide the following information with your report: \end_layout \begin_layout Standard Ngspice version \end_layout \begin_layout Standard Operating system \end_layout \begin_layout Standard Small input file to reproduce the bug \end_layout \begin_layout Standard Actual output versus the expected output \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Interactive-Interpreter" \end_inset Interactive Interpreter \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard The simulation flow in ngspice (input, simulation, output) may be controlled by dot commands (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Analyses-and-Output" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "sub:Batch-mode" \end_inset ) in batch mode. There is, however, a much more powerful control scheme available in ngspice, traditionally coined \begin_inset Quotes eld \end_inset Interactive Interpreter \begin_inset Quotes erd \end_inset , but being much more than just that. In fact there are several ways to use this feature, truely interactively by typing commands to the input, but also running command sequences as scripts or as part of your input deck in a quasi batch mode. \end_layout \begin_layout Standard You may type in expressions, functions ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ) or commands ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset ) into the input console to elaborate on data already achieved from the interactive simulation session. \end_layout \begin_layout Standard Sequences of commands, functions and control structures ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" \end_inset ) may be assembled as a script ( \begin_inset CommandInset ref LatexCommand ref reference "sec:SCRIPTS" \end_inset ) into a file, and then activated by just typing the file name into the console input of an interactive ngspice session. \end_layout \begin_layout Standard Finally, and most useful, is it to add a script to the input file, in addition the the netlist and dot commands. This is achieved by enclosing the script into \family typewriter .control ... .endc \family default (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Interactive-mode-with" \end_inset , and \begin_inset CommandInset ref LatexCommand ref reference "sub:Parameter-sweep" \end_inset for an example). This feature enables a wealth of control options. You may set internal ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset ) and other variables, start a simulation, evaluate the simulation output, start a new simulation based on these data, and finally make use of many options for outputting the data (graphically or into output files). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Expressions,-Functions,-and" \end_inset Expressions, Functions, and Constants \end_layout \begin_layout Standard Ngspice and ngnutmeg store data in the form of vectors: time, voltage, etc. Each vector has a type, and vectors can be operated on and combined algebraical ly in ways consistent with their types. Vectors are normally created as the output of a simulation, or when a data file (output raw file) is read in again (ngspice, ngnutmeg, see the \family sans load \family default command \begin_inset CommandInset ref LatexCommand ref reference "sub:Load:-Load-rawfile" \end_inset ), or when the initial data-file is loaded directly into ngnutmeg. They can also be created with the \family sans let \family default command 8 \begin_inset CommandInset ref LatexCommand ref reference "sub:Let:-Assign-a" \end_inset ). \end_layout \begin_layout Standard An expression is an algebraic formula involving vectors and scalars (a scalar is a vector of length 1) and the following operations: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout + - * / ^ % , \end_layout \end_inset \end_layout \begin_layout Standard % is the modulo operator, and the comma operator has two meanings: if it is present in the argument list of a user definable function, it serves to separate the arguments. Otherwise, the term \family typewriter x , y \family default is synonymous with \family typewriter x + j(y) \family default . Also available are the logical operations & (and), | (or), ! (not), and the relational operations <, >, >=, <=, =, and <> (not equal). If used in an algebraic expression they work like they would in C, producing values of 0 or 1. The relational operators have the following synonyms: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Operator \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Synonym \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout le \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ne \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout and \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout & \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout or \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout | \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ! \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eq \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout = \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The operators are useful when < and > might be confused with IO redirection (which is almost always). It is however safe to use < and > with the \family typewriter \series bold define \family default \series default command ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Define:-Define-a" \end_inset ). \end_layout \begin_layout Standard The following functions are available: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mag(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Magnitude of vector (same as abs(vector)). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ph(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cph(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase of vector. Continuous values, no discontinuity at ±PI. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout j(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i(sqrt(-1)) times vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout real(vector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The real component of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout imag(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The imaginary part of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout db(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20 log10(mag(vector)). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout log(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The logarithm (base 10) of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ln(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The natural logarithm (base e) of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exp(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout e to the vector power. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout abs(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The absolute value of vector (same as mag). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sqrt(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The square root of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sin(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The sine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cos(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The cosine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout tan(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout atan(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The inverse tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sinh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic sine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cosh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic cosine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout tanh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout floor(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Largest integer that is less than or equal to vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ceil(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Smallest integer that is greater than or equal to vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout norm(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The vector normalized to 1 (i.e, the largest magnitude of any component is 1). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mean(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a scalar (a length 1 vector) that is the mean of the elements of vector (elements values added, divided by number of elements). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout avg(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The average of a vector. \begin_inset Newline newline \end_inset Returns a vector where each element is the mean of the preceding elements of the input vector (including the actual element). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout group_delay(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Calculates the group delay -dphase[rad]/dω[rad/s]. Input is the complex vector of a system transfer function versus frequency, resembling damping and phase per frequency value. Output is a vector of group delay values (real values of delay times) versus frequency. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vector(number) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a vector of length number, with elements 0, 1, ... number - 1. If number is a vector then just the first element is taken, and if it isn't an integer then the floor of the magnitude is used. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unitvec(number) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a vector of length number, all elements having a value 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The length of vector. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout interpolate(plot.vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result of interpolating the named vector onto the scale of the current plot. This function uses the variable polydegree to determine the degree of interpola tion. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout deriv(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Calculates the derivative of the given vector. This uses numeric differentiation by interpolating a polynomial and may not produce satisfactory results (particularly with iterated differentiation). The implementation only calculates the derivative with respect to the real component of that vector's scale. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecd(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Compute the differential of a vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecmin(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with minimum value. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecmax(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with maximum value. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Several functions offering statistical procedures are listed in the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rnd(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A vector with each component a random integer between 0 and the absolute value of the input vector's corresponding integer element value. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sgauss(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random numbers drawn from a Gaussian distribution (real value, mean = 0 , standard deviation = 1). The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sgauss(0) will return a single value of a random number as a vector of length 1.. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sunif(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random real numbers uniformly distributed in the interval [-1 .. 1[. The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sunif(0) will return a single value of a random number as a vector of length 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout poisson(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements being integers drawn from a Poisson distribut ion. The elements of the input vector (real numbers) are the expected numbers λ. Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exponential(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements (real numbers) drawn from an exponential distribution. The elements of the input vector are the respective mean values (real numbers). Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard An input vector may be either the name of a vector already defined or a floating-point number (a scalar). A scalar will result in an output vector of length 1. A number may be written in any format acceptable to ngspice, such as 14.6Meg or -1.231e-4. Note that you can either use scientific notation or one of the abbreviations like MEG or G, but not both. As with ngspice, a number may have trailing alphabetic characters. \end_layout \begin_layout Standard The notation \family sans expr [num] \family default denotes the num'th element of expr. For multi-dimensional vectors, a vector of one less dimension is returned. Also for multi-dimensional vectors, the notation \family sans expr[m][n] \family default will return the nth element of the mth subvector. To get a subrange of a vector, use the form \family sans expr[lower, upper] \family default . To reference vectors in a plot that is not the current plot (see the \family sans setplot \family default command, below), the notation \family sans plotname.vecname \family default can be used. Either a plotname or a vector name may be the wildcard \family sans all \family default . If the plotname is \family sans all \family default , matching vectors from all plots are specified, and if the vector name is all, all vectors in the specified plots are referenced. Note that you may not use binary operations on expressions involving wildcards - it is not obvious what \family sans all + all \family default should denote, for instance. Thus some (contrived) examples of expressions are: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Expressions example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout cos(TIME) + db(v(3)) \end_layout \begin_layout Plain Layout sin(cos(log([1 2 3 4 5 6 7 8 9 10]))) \end_layout \begin_layout Plain Layout TIME * rnd(v(9)) - 15 * cos(vin#branch) ^ [7.9e5 8] \end_layout \begin_layout Plain Layout not ((ac3.FREQ[32] & tran1.TIME[10]) gt 3) \end_layout \begin_layout Plain Layout (sunif(0) ge 0) ? 1.0 : 2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Vector names in ngspice may have look like \family sans @dname[param] \family default , where dname is either the name of a device instance or of a device model. This vector contains the value of the param parameter of the device or model. See Appendix, chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" \end_inset for details of which parameters are available. The value is a vector of length 1. This function is also available with the show command, and is available with variables for convenience for command scripts. \end_layout \begin_layout Standard There are a number of pre-defined constants in ngspice, which you may use by their name. They are stored in plot ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Plots" \end_inset ) \begin_inset Quotes eld \end_inset const \begin_inset Quotes erd \end_inset and are listed in the table below: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\pi$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.14159... \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout e \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $e$ \end_inset (the base of natural logarithms) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.71828... \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout c \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $c$ \end_inset (the speed of light) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 299,792,500 \begin_inset Formula $\nicefrac{m}{sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i (the square root of -1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{-1}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout kelvin \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout (absolute zero in centigrade) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -273.15 \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout echarge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout q (the charge of an electron) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.60219e-19 C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boltz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout k (Boltzmann's constant) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.38062e-23 \begin_inset Formula $\nicefrac{J}{K}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout planck \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout h (Planck's constant) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6.62620e-34 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout yes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FALSE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard These constants are all given in MKS units. If you define another variable with a name that conflicts with one of these then it takes precedence. \end_layout \begin_layout Standard Additional constants may be generated during circuit setup (see .csparam, \begin_inset CommandInset ref LatexCommand ref reference "sec:.csparam" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Plots" \end_inset Plots \end_layout \begin_layout Standard The output vectors of any analysis are stored in plots, a traditional SPICE notion. A plot is a group of vectors. A first \family typewriter \series bold tran \family default \series default command will generate several vectors within a plot tran1. A subsequent \family typewriter \series bold tran \family default \series default command will store their vectors in tran2. Then a \family typewriter \series bold linearize \family default \series default command will linearize all vectors from tran2 and store them in tran3, which then becomes the current plot. A \family typewriter \series bold fft \family default \series default will generate a plot spec1, again now the current plot. The \family typewriter \series bold display \family default \series default command always will show all vectors in the current plot. \family typewriter \series bold Setplot \family default \series default followed by Return will show all plots. \family typewriter \series bold Setplot name \family default \series default will change the current plot to 'name' (e.g. \family typewriter \series bold setplot tran2 \family default \series default will make tran2 the current plot). A sequence \family typewriter \series bold name.vector \family default \series default may be used to access the vector from a foreign plot. \end_layout \begin_layout Standard You may generate plots by yourself: \family typewriter \series bold setplot new \family default \series default will generate a new plot named unknown1, \family typewriter \series bold set curplottitle= \begin_inset Quotes erd \end_inset a new plot \begin_inset Quotes erd \end_inset \family default \series default will set a title, set \family typewriter \series bold curplotname=myplot \family default \series default will set its name as a short description, set \family typewriter \series bold curplotdate= \begin_inset Quotes erd \end_inset Sat Aug 28 10:49:42 2010 \begin_inset Quotes erd \end_inset \family default \series default will set its date. Note that strings with spaces have to be given with double quotes. \end_layout \begin_layout Standard Of course the notion 'plot' will be used by this manual also in its more common meaning, denoting a graphics plot or being a \family typewriter \series bold plot \family default \series default command. Be careful to get the correct meaning. \end_layout \begin_layout Section Command Interpretation \end_layout \begin_layout Standard On the ngspice console window (or into the Windows GUI) you may directly type in any command from \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset . IO redirection is available (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Output-redirection" \end_inset for an example) - the symbols >, >>, >&, >>&, and < have the same effects as in the C-shell. \end_layout \begin_layout Standard You may type multiple commands on one line, separated by semicolons. If a word is typed as a command, and there is no built-in command with that name, the directories in the \family typewriter sourcepath \family default list are searched in order for the file. If it is found, it is read in as a command file (as if it were sourced). Before it is read, however, the variables \family typewriter \series bold argc \family default \series default and \family typewriter \series bold argv \family default \series default are set to the number of words following the file-name on the command line, and a list of those words respectively. After the file is finished, these variables are unset. Note that if a command file calls another, it must save its \family typewriter \series bold argv \family default \series default and \family typewriter \series bold argc \family default \series default since they are altered. Also, command files may not be re-entrant since there are no local variables. (Of course, the procedures may explicitly manipulate a stack...) This way one can write scripts analogous to shell scripts for ngnutmeg and ngspice. \end_layout \begin_layout Standard Note that for the script to work with ngspice, it must begin with a blank line (or whatever else, since it is thrown away) and then a line with \family typewriter .control \family default on it. This is an unfortunate result of the source command being used for both circuit input and command file execution. Note also that this allows the user to merely type the name of a circuit file as a command and it is automatically run. The commands are executed immediately, without running any analyses that may be specified in the circuit (to execute the analyses before the script executes, include a \begin_inset Quotes eld \end_inset \family sans run \family default \begin_inset Quotes erd \end_inset command in the script). \end_layout \begin_layout Standard There are various command scripts installed in \family typewriter /usr/local/lib/spice/scripts \family default (or whatever the path is on your machine), and the default \family typewriter sourcepath \family default includes this directory, so you can use these command files (almost) like built-in commands. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Commands" \end_inset Commands \end_layout \begin_layout Standard Commands marked with a * are only available in ngspice, not in ngnutmeg. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Ac*:-Perform-an" \end_inset Ac*: Perform an AC, small-signal frequency response analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ac ( DEC | OCT | LIN ) N Fstart Fstop \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do an small signal ac analysis (see also chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.AC:-Small-Signal-AC" \end_inset ) over the specified frequency range. \end_layout \begin_layout Standard \family typewriter \series bold DEC \family default \series default decade variation, and \family typewriter \series bold N \family default \series default is the number of points per decade. \end_layout \begin_layout Standard \family typewriter \series bold OCT \family default \series default stands for octave variation, and \family typewriter \series bold N \family default \series default is the number of points per octave. \end_layout \begin_layout Standard \family typewriter \series bold LIN \family default \series default stands for linear variation, and \family typewriter \series bold N \family default \series default is the number of points. \end_layout \begin_layout Standard \family typewriter \series bold fstart \family default \series default is the starting frequency, and \family typewriter \series bold fstop \family default \series default is the final frequency. \end_layout \begin_layout Standard Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value. \end_layout \begin_layout Standard In this ac analysis all non-linear devices are linearized around their actual dc operating point. All Ls and Cs get their imaginary value, depending on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the ac value (Iin equals to 1 in the example below). The resulting node voltages (and branch currents) are complex vectors. Therefore you have to be careful using the plot command. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * AC test \end_layout \begin_layout Plain Layout Iin 1 0 AC 1 \end_layout \begin_layout Plain Layout R1 1 2 100 \end_layout \begin_layout Plain Layout L1 2 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout AC LIN 101 10 10K \end_layout \begin_layout Plain Layout plot v(2) $ real part ! \end_layout \begin_layout Plain Layout plot mag(v(2)) $ magnitude \end_layout \begin_layout Plain Layout plot db(v(2)) $ same as vdb(2) \end_layout \begin_layout Plain Layout plot imag(v(2)) \end_layout \begin_layout Plain Layout plot real(v(2)) \end_layout \begin_layout Plain Layout plot phase(v(2)) $ phase in rad \end_layout \begin_layout Plain Layout plot 180/PI*phase(v(2)) $ phase in deg \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In addition to the plot examples given above you may use the variants of vxx(node) described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.PRINT-Lines" \end_inset like \family typewriter vdb(2) \family default . \end_layout \begin_layout Subsection Alias: Create an alias for a command \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout alias [word] [text ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Causes word to be aliased to text. History substitutions may be used, as in C-shell aliases. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Alter*:-Change-a" \end_inset Alter*: Change a device or model parameter \end_layout \begin_layout Standard Alter changes the value for a device or a specified parameter of a device or model. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout alter dev = \end_layout \begin_layout Plain Layout alter dev param = \end_layout \begin_layout Plain Layout alter @dev[param] = \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard must be real (complex isn't handled right now, integer is fine though, but no strings. For booleans, use 0/1. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Old style (pre 3f4): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout alter device value \end_layout \begin_layout Plain Layout alter device parameter value [ parameter value ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Using the old style, its first form is used by simple devices which have one principal value (resistors, capacitors, etc.) where the second form is for more complex devices (bjt's, etc.). Model parameters can be changed with the second form if the name contains a "#". For specifying vectors as values, start the vector with "[", followed by the values in the vector, and end with "]". Be sure to place a space between each of the values and before and after the "[" and "]". \end_layout \begin_layout Standard Some examples are given below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Examples (Spice3f4 style): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout alter vd = 0.1 \end_layout \begin_layout Plain Layout alter vg dc = 0.6 \end_layout \begin_layout Plain Layout alter @m1[w]= 15e-06 \end_layout \begin_layout Plain Layout alter @vg[sin] [ -1 1.5 2MEG ] \end_layout \begin_layout Plain Layout alter @Vi[pwl] = [ 0 1.2 100p 0 ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Altermod*:-Change-a" \end_inset Altermod*: Change model parameter(s) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout altermod mod param = \end_layout \begin_layout Plain Layout altermod @mod[param] = \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout altermod nc1 tox = 10e-9 \end_layout \begin_layout Plain Layout altermod @nc1[tox] = 10e-9 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Altermod operates on models and is used to change model parameters. The above example will change the parameter \family typewriter tox \family default in all devices using the model \family typewriter nc1 \family default , which is defined as \end_layout \begin_layout LyX-Code *** BSIM3v3 model \end_layout \begin_layout LyX-Code .MODEL nc1 nmos LEVEL=8 version = 3.2.2 \end_layout \begin_layout LyX-Code + acm = 2 mobmod = 1 capmod = 1 noimod = 1 \end_layout \begin_layout LyX-Code + rs = 2.84E+03 rd = 2.84E+03 rsh = 45 \end_layout \begin_layout LyX-Code + tox = 20E-9 xj = 0.25E-6 nch = 1.7E+17 \end_layout \begin_layout LyX-Code + ... \end_layout \begin_layout Standard If you invoke the model by the MOS device \end_layout \begin_layout Standard \family typewriter M1 d g s b nc1 w=10u l=1u \end_layout \begin_layout Standard you might also insert the device name M1 for \family typewriter mod \family default as in \end_layout \begin_layout Standard \family typewriter altermod M1 tox = 10e-9 \end_layout \begin_layout Standard The model parameter \family typewriter tox \family default will be modified, however not only for device M1, but for all devices using the associated MOS model nc1! \end_layout \begin_layout Standard If you want to run corner simulations within a single simulation flow, the following option of altermod may be of help. The parameter set with name \family typewriter modn \family default may be overrun by the altermod command specifying a model file. All parameter values fitting to the existing model which is defined as \family typewriter modn \family default will be modified. As usual the 'reset' command (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Reset*:-Reset-an" \end_inset ) restores the original values. The model file (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" \end_inset ) has to use the standard specifications for an input file, the .model section is the relevant part. However the first line in the model file will be ignored by the input parser, so it should contain only some title information. The \family typewriter .model \family default statement should appear then in the second or any later line. More than one .model section may reside in the file. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout altermod mod1 [mod2 .. mod15] file = \end_layout \begin_layout Plain Layout altermod mod1 [mod2 .. mod15] file \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout altermod nch file = BSIM3_nmos.mod \end_layout \begin_layout Plain Layout altermod pch nch file BSIM4_mos.mod \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Be careful that the new model file corresponds to the existing model selected by \family typewriter modn \family default . The existing models are defined during circuit setup at start up of ngspice. Models have been included by \family typewriter .model \family default statements ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" \end_inset ) in your input file or included by the \family typewriter .include \family default command. In the example given above, the models nch (or nch and pch) have to be already available before calling \family typewriter altermod \family default . If they are not found in the active circuit, ngspice will terminate with an error message. There is no checking however of the version and level parameters! So you have to be responsible for offering model data of the same model level (e.g. level 8 for BSIM3). Thus no new model is selectable by \family typewriter altermod \family default , but the parameters of the existing model(s) may be changed (partially, completely, temporarily). \end_layout \begin_layout Subsection Asciiplot: Plot values using old-style character plots \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout asciiplot plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Produce a line printer plot of the vectors. The plot is sent to the standard output, so you can put it into a file with \family sans asciiplot args ... > file \family default . The set options width, height, and nobreak determine the width and height of the plot, and whether there are page breaks, respectively. Note that you will have problems if you try to asciiplot something with an X-scale that isn't monotonic (i.e, something like sin(TIME) ), because asciiplot uses a simple-minded linear interpolation. The asciiplot command doesn't deal with log scales or the delta keywords. \end_layout \begin_layout Subsection Aspice*: Asynchronous ngspice run \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout aspice input-file [output-file] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Start an ngspice run, and when it is finished load the resulting data. The raw data is kept in a temporary file. If output-file is specified then the diagnostic output is directed into that file, otherwise it is thrown away. \end_layout \begin_layout Subsection Bug: Mail a bug report \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout bug \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Send a bug report. Please include a short summary of the problem, the version number and name of the operating system that you are running, the version of ngspice that you are running, and the relevant ngspice input file. (If you have defined \family typewriter BUGADDR \family default , the mail is delivered to there.) \end_layout \begin_layout Subsection Cd: Change directory \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout cd [directory] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Change the current working directory to directory, or to the user's home directory if none is given. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Cdump:-Dump-the" \end_inset Cdump: Dump the control flow to the screen \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout cdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Dumps the control sequence to the screen (all statements inside the .control ... .endc structure before the line with cdump). Indentations show the structure of the sequence. The example below is printed if you add \series bold cdump \series default to /examples/Monte_Carlo/MonteCarlo.sp. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example (abbreviated): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout let mc_runs=5 \end_layout \begin_layout Plain Layout let run=0 \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) \end_layout \begin_layout Plain Layout define limit(nom, avar) (nom + ((sgauss(0) >=0) ? avar : -avar)) \end_layout \begin_layout Plain Layout dowhile run < mc_runs \end_layout \begin_layout Plain Layout alter c1=unif(1e-09, 0.1) \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout ac oct 100 250k 10meg \end_layout \begin_layout Plain Layout meas ac bw trig vdb(out) val=-10 rise=1 targ vdb(out) val=-10 fall=1 \end_layout \begin_layout Plain Layout set run="$&run" \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout let run=run + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot db({$scratch}.allv) \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout print {$scratch}.bwh \end_layout \begin_layout Plain Layout cdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Codemodel:-Load-an" \end_inset Codemodel*: Load an XSPICE code model library \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout codemodel [library file] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Load a XSPICE code model shared library file (e.g. analog.cm ...). Only available if ngspice is compiled with the XSPICE option (--enable-xspice) or with the Windows executable distributed since ngspice21. This command has to be called from spinit (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) (or .spiceinit for personal code models, \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Compose:-Compose-a" \end_inset Compose: Compose a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout compose name values value1 [ value2 ... ] \end_layout \begin_layout Plain Layout compose name parm = val [ parm = val ... ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The first form takes the values and creates a new vector, the values may be arbitrary expressions. \end_layout \begin_layout Standard The second form has the following possible parameters: \end_layout \begin_layout Description start The value at which the vector should start. \end_layout \begin_layout Description stop The value at which the vector should end. \end_layout \begin_layout Description step The difference between successive elements. \end_layout \begin_layout Description lin The number of points, linearly spaced.. \end_layout \begin_layout Subsection Dc*: Perform a DC-sweep analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout dc Source-Name Vstart Vstop Vincr [ Source2 Vstart2 Vstop2 Vincr2 ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do a dc transfer curve analysis. See the previous chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.DC:-DC-Transfer" \end_inset for more details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Define:-Define-a" \end_inset Define: Define a function \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout define function(arg1, arg2, ...) expression \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Define the user-definable function with the name function and arguments arg1, arg2, ... to be expression, which may involve the arguments. When the function is later used, the arguments it is given are substituted for the formal arguments when it is parsed. If expression is not present, any definition for function is printed, and if there are no arguments to define then all currently active definitions are printed. Note that you may have different functions defined with the same name but different arities. Some useful definitions are: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout define max(x,y) (x > y) * x + (x <= y) * y \end_layout \begin_layout Plain Layout define min(x,y) (x < y) * x + (x >= y) * y \end_layout \begin_layout Plain Layout define limit(nom, avar) (nom + ((sgauss(0) >= 0) ? avar : -avar)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Deftype: Define a new type for a vector or plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout deftype [v | p] typename abbrev \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard defines types for vectors and plots. abbrev will be used to parse things like abbrev(name) and to label axes with M, instead of numbers. It may be omitted. Also, the command "deftype p plottype pattern ..." will assign plottype as the name to any plot with one of the patterns in its Name: field. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout deftype v capacitance F \end_layout \begin_layout Plain Layout settype capacitance moscap \end_layout \begin_layout Plain Layout plot moscap vs v(cc) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Delete*: Remove a trace or breakpoint \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout delete [ debug-number ... ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Delete the specified breakpoints and traces. The debug numbers are those shown by the status command (unless you do status > file, in which case the debug numbers are not printed). \end_layout \begin_layout Subsection Destroy: Delete an output data set \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout destroy [plotnames | all] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Release the memory holding the output data (the given plot or all plots) for the specified runs. \end_layout \begin_layout Subsection Devhelp: information on available devices \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout devhelp [[-csv] device_name [parameter]] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Devhelp command shows the user information about the devices available in the simulator. If called without arguments, it simply displays the list of available devices in the simulator. The name of the device is the name used inside the simulator to access that device. If the user specifies a device name, then all the parameters of that device (model and instance parameters) will be printed. Parameter description includes the internal ID of the parameter (id#), the name used in the model card or on the instance line (Name), the direction (Dir) and the description of the parameter (Description). All the fields are self-explanatory, except the \begin_inset Quotes eld \end_inset direction \begin_inset Quotes erd \end_inset . Direction can be \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset out \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset inout \begin_inset Quotes erd \end_inset and corresponds to a \begin_inset Quotes eld \end_inset write-only \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset read-only \begin_inset Quotes erd \end_inset or a \begin_inset Quotes eld \end_inset read/write \begin_inset Quotes erd \end_inset parameter. Read-only parameters can be read but not set, write only can be set but not read and read/write can be both set and read by the user. \end_layout \begin_layout Standard The \begin_inset Quotes eld \end_inset -csv \begin_inset Quotes erd \end_inset option prints the fields separated by a comma, for direct import into a spreadsheet. This option is used to generate the simulator documentation. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout devhelp \end_layout \begin_layout Plain Layout devhelp resistor \end_layout \begin_layout Plain Layout devhelp capacitor ic \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Diff: Compare vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout diff plot1 plot2 [vec ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Compare all the vectors in the specified plots, or only the named vectors if any are given. If there are different vectors in the two plots, or any values in the vectors differ significantly, the difference is reported. The variables \family sans diff_abstol \family default , \family sans diff_reltol \family default , and \family sans diff_vntol \family default are used to determine a significant difference. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Display:-List-known" \end_inset Display: List known vectors and types \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout display [varname ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Prints a summary of currently defined vectors, or of the names specified. The vectors are sorted by name unless the variable \family sans nosort \family default is set. The information given is the name of the vector, the length, the type of the vector, and whether it is real or complex data. Additionally, one vector is labeled [scale]. When a command such as plot is given without a \family sans vs \family default argument, this scale is used for the X-axis. It is always the first vector in a rawfile, or the first vector defined in a new plot. If you undefine the scale (i.e, \family sans let TIME = [] \family default ), one of the remaining vectors becomes the new scale (which one is unpredictabl e). You may set the scale to another vector of the plot with the command \family typewriter \series bold \family sans \series default setscale \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Setscale:-Set-the" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Echo:-Print-text" \end_inset Echo: Print text \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout echo [text...] [$variable] ["$&vector"] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Echos the given text, variable or vector to the screen. \series bold echo \series default without parameters issues a blank line. \end_layout \begin_layout Subsection Edit*: Edit the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout edit [ file ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print the current ngspice input file into a file, call up the editor on that file and allow the user to modify it, and then read it back in, replacing the original file. If a file-name is given, then edit that file and load it, making the circuit the current one. The editor may be defined in \series bold .spiceinit \series default or \series bold spinit \series default by a command line like \family typewriter \end_layout \begin_layout Standard \family typewriter set editor=emacs \end_layout \begin_layout Standard Using MS Winows, to allow the \series bold edit \series default command calling an editor, you will have to add the editor's path to the PATH variable of the command prompt windows (see \begin_inset CommandInset href LatexCommand href name "here" target "http://en.wikipedia.org/wiki/Environment_variable#Examples_of_DOS_environment_variables" \end_inset ). \series bold edit \series default then calls cmd.exe with e.g. notepad++ and \family typewriter file \family default as parameter, if you have set \end_layout \begin_layout Standard \family typewriter set editor=notepad++.exe \end_layout \begin_layout Standard to \series bold .spiceinit \series default or \series bold spinit \series default . \end_layout \begin_layout Subsection Eprint*: Print an event driven node (only used with XSPICE option) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout eprint node \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print an event driven node generated or used by an XSPICE 'A' device. These nodes are vectors not organized in plots. See chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Running-example-C3" \end_inset for an example. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:fft:-fast-Fourier" \end_inset FFT: fast Fourier transform of vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout fft vector1 [vector2] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This analysis provides a fast Fourier transform of the input vector(s). fft is much faster than spec ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Spec:-Create-a" \end_inset ) (about a factor of 50 to 100 for larger vectors) ! \end_layout \begin_layout Standard The fft command will create a new plot consisting of the Fourier transforms of the vectors given on the command line. Each vector given should be a transient analysis result, i.e. it should have ‘time’ as a scale. You will have got these vectors by the \family typewriter \series bold tran Tstep Tstop Tstart \family default \series default command. \end_layout \begin_layout Standard The vector should have a linear equidistant time scale. Therefore linearization using the \family typewriter \series bold linearize \family default \series default command is recommended before running fft. Be careful selecting a Tstep value small enough for good interpolation, e.g. much smaller than any signal period to be resolved by \family typewriter \series bold fft \family default \series default (see \family typewriter \series bold linearize \family default \series default command). The Fast Fourier Transform will be computed using a window function as given with the specwindow variable. Its code is based on the FFT function provided at http://local.wasp.uwa.edu.au/~pbo urke/other/dft/, downloaded April 5th, 2008. A new plot named spec \family typewriter \series bold x \family default \series default will be generated with a new vector (having the same name as the input vector, see command above) containing the transformed data. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout How to compute the fft from a transient simulation output: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 8 -> setplot tran1 \end_layout \begin_layout Plain Layout ngspice 9 -> linearize V(2) \end_layout \begin_layout Plain Layout ngspice 9 -> set specwindow=blackman \end_layout \begin_layout Plain Layout ngspice 10 -> fft V(2) \end_layout \begin_layout Plain Layout ngspice 11 -> plot mag(V(2)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter Linearize \family default will create a new vector V(2) in a new plot \family typewriter \series bold tran2 \family default \series default . The command \family typewriter fft V(2) \family default will create a new plot \family typewriter \series bold spec1 \family default \series default with vector V(2) holding the resulting data. \end_layout \begin_layout Standard The variables listed in the following table control operation of the \family typewriter \series bold fft \family default \series default command. Each can be set with the set command before calling \family typewriter \series bold fft \family default \series default . \end_layout \begin_layout Subparagraph specwindow: \end_layout \begin_layout Standard This variable is set to one of the following strings, which will determine the type of windowing used for the Fourier transform in the spec command. If not set, the default is "hanning". \end_layout \begin_layout Description none No windowing \end_layout \begin_layout Description rectangular Rectangular window \end_layout \begin_layout Description bartlet Bartlett (also triangle) window \end_layout \begin_layout Description blackman Blackman window \end_layout \begin_layout Description hanning Hanning (also hann or cosine) window \end_layout \begin_layout Description hamming Hamming window \end_layout \begin_layout Description gaussian Gaussian window \end_layout \begin_layout Description flattop Flat top window \end_layout \begin_layout Standard \begin_inset Float figure placement H wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/fft_windows.png width 70line% \end_inset \begin_inset Caption \begin_layout Plain Layout Spec and FFT window functions (Gaussian order = 4) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subparagraph specwindoworder: \end_layout \begin_layout Standard This can be set to an integer in the range 2-8. This sets the order when the Gaussian window is used in the spec command. If not set, order 2 is used. \end_layout \begin_layout Subsection Fourier: Perform a Fourier transform \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout fourier fundamental_frequency [value ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Does a fourier analysis of each of the given values, using the first 10 multiples of the fundamental frequency (or the first nfreqs, if that variable is set - see below). The output is like that of the \family typewriter .four \family default ngspice line (chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.FOUR:-Fourier-Analysis" \end_inset ). The values may be any valid expression. The values are interpolated onto a fixed-space grid with the number of points given by the fourgridsize variable, or 200 if it is not set. The interpolation is of degree polydegree if that variable is set, or 1. If polydegree is 0, then no interpolation is done. This is likely to give erroneous results if the time scale is not monotonic, though. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Gnuplot:-Graphics-output" \end_inset Gnuplot: Graphics output via Gnuplot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout gnuplot file plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Like plot, but using gnuplot for graphics output and further data manipulation. ngspice creates a file called \family typewriter file.plt \family default containing the gnuplot command sequence, a file called \family typewriter file.data \family default containing the data to be plotted, and a file called \family typewriter file.eps \family default containing a postscript hard-copy of the plot. On LINUX gnuplot is called via xterm, which offers a gnuplot console to manipulate the data. On Windows a gnuplot command console window is opened as well as the plot window. Of course you have to have gnuplot installed properly on your system. This option will work with Gnuplot version 4.2.6, not with version 4.4, but again with 4.5 (as of August 2011). \end_layout \begin_layout Subsection Hardcopy: Save a plot to a file for printing \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout hardcopy file plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Just like plot, except that it creates a file called \family typewriter file \family default containing the plot. The file is a postscript image. As an alternative the plot(5) format is available by setting the hcopydevtype variable to \family typewriter \series bold plot5 \family default \series default , and can be printed by either the plot(1) program or lpr with the -g flag. \end_layout \begin_layout Subsection Inventory: Print circuit inventory \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout inventory \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This commands accepts no argument and simply prints the number of instances of a particular device in a loaded netlist. \end_layout \begin_layout Subsection Help: Print summaries of Ngspice commands \end_layout \begin_layout Standard Prints help. This help information, however, is spice3f5-like, stemming from 1991 and thus is outdated. If the argument \family typewriter \series bold all \family default \series default is given, a short description of everything you could possibly type is printed. If commands are given, descriptions of those commands are printed. Otherwise help for only a few major commands is printed. On Windows this \series bold help \series default command is no longer available. Spice3f5 compatible help may be found at \begin_inset CommandInset href LatexCommand href name "Spice 3 User manual" target "http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/" \end_inset . For ngspice please use this manual. \end_layout \begin_layout Subsection History: Review previous commands \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout history [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print out the history, or the last \family typewriter number \family default commands typed at the keyboard. \end_layout \begin_layout Subsection Iplot*: Incremental plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout iplot [ node ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Incrementally plot the values of the nodes while ngspice runs. The \family sans iplot \family default command can be used with the where command to find trouble spots in a transient simulation. \end_layout \begin_layout Subsection Jobs*: List active asynchronous ngspice runs \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout jobs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Report on the asynchronous ngspice jobs currently running. Ngnutmeg checks to see if the jobs are finished every time you execute a command. If it is done then the data is loaded and becomes available. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Let:-Assign-a" \end_inset Let: Assign a value to a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout let name = expr \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Creates a new vector called name with the value specified by expr, an expression as described above. If expr is [] (a zero-length vector) then the vector becomes undefined. Individual elements of a vector may be modified by appending a subscript to name (ex. name[0]). If there are no arguments, let is the same as display. \end_layout \begin_layout Standard The command \series bold let \series default creates a vector in the current plot, use \series bold setplot \series default \begin_inset CommandInset ref LatexCommand eqref reference "sub:Setplot:-Switch-the" \end_inset to create a new plot. \end_layout \begin_layout Standard See also \series bold unlet \series default \begin_inset CommandInset ref LatexCommand eqref reference "sub:Unlet:-Delete-the" \end_inset , \series bold compose \series default \begin_inset CommandInset ref LatexCommand eqref reference "sub:Compose:-Compose-a" \end_inset . \end_layout \begin_layout Subsection Linearize*: Interpolate to a linear scale \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout linearize vec ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Create a new plot with all of the vectors in the current plot, or only those mentioned as arguments to the command, all data linearized onto an equidistant time scale. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout How compute the fft from a transient simulation output: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 8 -> setplot tran1 \end_layout \begin_layout Plain Layout ngspice 9 -> linearize V(2) \end_layout \begin_layout Plain Layout ngspice 9 -> set specwindow=blackman \end_layout \begin_layout Plain Layout ngspice 10 -> fft V(2) \end_layout \begin_layout Plain Layout ngspice 11 -> plot mag(V(2))tstep \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter Linearize \family default will create new vectors \series bold vec \series default or renew all vectors of the current plot if no arguments are given. The new vectors are interpolated onto a linear time scale, which is determined by the values of \family typewriter tstep \family default , \family typewriter tstart \family default , and \family typewriter tstop \family default in the currently active transient analysis. The currently loaded input file must include a transient analysis (a tran command may be run interactively before the last reset, alternately), and the current plot must be from this transient analysis. The length of the new vector is \family typewriter (tstop - tstart) / tstep + 1.5 \family default . This command is needed for example if you want to do a fft analysis ( \begin_inset CommandInset ref LatexCommand ref reference "sub:fft:-fast-Fourier" \end_inset ). Please note that the parameter \family typewriter tstep \family default of your transient analysis (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.TRAN:-Transient-Analysis" \end_inset ) has to be small enough to get adequate resolution, otherwise the command \family typewriter linearize \family default will do sub-sampling of your signal. \end_layout \begin_layout Subsection Listing*: Print a listing of the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout listing [logical] [physical] [deck] [expand] [param] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If the \series bold logical \series default argument is given, the listing is with all continuation lines collapsed into one line, and if the \series bold physical \series default argument is given the lines are printed out as they were found in the file. The default is logical. A \series bold deck \series default listing is just like the physical listing, except without the line numbers it recreates the input file verbatim (except that it does not preserve case). If the word \series bold expand \series default is present, the circuit is printed with all subcircuits expanded. The option \series bold param \series default allows to print all parameters and their actual values. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Load:-Load-rawfile" \end_inset Load: Load rawfile data \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout load [filename] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Loads either binary or ascii format rawfile data from the files named. The default file-name is rawspice.raw, or the argument to the -r flag if there was one. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Meas*:-Mesurements-on" \end_inset Meas*: Mesurements on simulation data \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form (example): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout MEAS {DC|AC|TRAN|SP} result TRIG trig_variable VAL=val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout TARG targ_variable VAL=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Most of the input forms found in \begin_inset CommandInset ref LatexCommand ref reference "sub:.MEAS" \end_inset may be used here with the command \family typewriter meas \family default instead of \family typewriter .meas(ure) \family default . Using meas inside the .control ... .endc section offers additional features compared to the .meas use. meas will print the results as usual, but in addition will store its measuremen t result (typically the token \family typewriter \series bold result \family default \series default given in the command line) in a vector. This vector may be used in following command lines of the script as an input value of another command. For details of the command see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.MEAS" \end_inset . The measurement type \series bold SP \series default is only available here, because a \family typewriter fft \family default command will prepare the data for \series bold SP \series default measurement. \end_layout \begin_layout Standard Unfortunately \series bold par('expression') \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:par('expression'):-Algebraic-expressions" \end_inset ) will not work here, i.e. inside the .control section. You may use an expression by the \series bold let \series default command instead, giving \family typewriter let vec_new = expression \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Replacement for par('expression') in meas inside the .control section \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout let vdiff = v(n1)-v(n0) \end_layout \begin_layout Plain Layout meas tran vtest find vdiff at=0.04e-3 \end_layout \begin_layout Plain Layout *the following will not do here: \end_layout \begin_layout Plain Layout *meas tran vtest find par('v(n1)-v(n0)') at=0.04e-3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Noise*: Noise analysis \end_layout \begin_layout Standard See the .NOISE analysis ( \begin_inset CommandInset ref LatexCommand ref reference "sub:.NOISE:-Noise-Analysis" \end_inset ) for details. \end_layout \begin_layout Standard The \family typewriter \series bold noise \family default \series default command will generate two plots (typically named noise1 and noise2) with Noise Spectral Density Curves and Integrated Noise data. To write these data into output file(s), you may use the following command sequence: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Command sequence for writing noise data to file(s): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout tran 1e-6 1e-3 \end_layout \begin_layout Plain Layout write test_tran.raw \end_layout \begin_layout Plain Layout noise V(out) vinp dec 333 1 1e8 16 \end_layout \begin_layout Plain Layout print inoise_total onoise_total \end_layout \begin_layout Plain Layout *first option to get all of the output (two files) \end_layout \begin_layout Plain Layout setplot noise1 \end_layout \begin_layout Plain Layout write test_noise1.raw all \end_layout \begin_layout Plain Layout setplot noise2 \end_layout \begin_layout Plain Layout write test_noise2.raw all \end_layout \begin_layout Plain Layout * second option (all in one raw-file) \end_layout \begin_layout Plain Layout write testall.raw noise1.all noise2.all \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Op*: Perform an operating point analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout op \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do an operating point analysis. See chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.OP:-Operating-Point" \end_inset for more details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Option*:" \end_inset Option*: Set a ngspice option \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout option [option=val] [option=val] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set any of the simulator variables as listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Simulator-Variables" \end_inset . See this chapter also for more information on the available options. The \family typewriter \series bold option \family default \series default command without any argument lists the actual options set in the simulator (to be verified). Multiple options may be set in a single line. \end_layout \begin_layout Standard The following example demonstrates a control section, which may be added to your circuit file to test the influence of variable trtol on the number of iterations and on the simulation time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Command sequence for testing option trtol: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noinit \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout option trtol=1 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=1 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=3 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=3 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=5 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=5 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=7 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=7 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout plot tran1.v(out25) tran1.v(out50) v(out25) v(out50) \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Plot:-Plot-values" \end_inset Plot: Plot values on the display \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout plot exprs [ylimit ylo yhi] [xlimit xlo xhi] [xindices xilo xihi] \end_layout \begin_layout Plain Layout [xcompress comp] [xdelta xdel] [ydelta ydel] [xlog] [ylog] [loglog] \end_layout \begin_layout Plain Layout [vs xname] [xlabel word] [ylabel word] [title word] [samep] \end_layout \begin_layout Plain Layout [linear] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Plot the given vectors or exprs on the screen (if you are on a graphics terminal). The xlimit and ylimit arguments determine the high and low x- and y-limits of the axes, respectively. The xindices arguments determine what range of points are to be plotted - everything between the xilo'th point and the xihi'th point is plotted. The xcompress argument specifies that only one out of every comp points should be plotted. If an xdelta or a ydelta parameter is present, it specifies the spacing between grid lines on the X- and Y-axis. These parameter names may be abbreviated to xl, yl, xind, xcomp, xdel, and ydel respectively. \end_layout \begin_layout Standard The xname argument is an expression to use as the scale on the x-axis. If xlog or ylog are present then the X or Y scale, respectively, is logarithmic (loglog is the same as specifying both). The xlabel and ylabel arguments cause the specified labels to be used for the X and Y axes, respectively. \end_layout \begin_layout Standard If samep is given, the values of the other parameters (other than xname) from the previous plot, hardcopy, or asciiplot command is used unless re-define d on the command line. \end_layout \begin_layout Standard The title argument is used in the place of the plot name at the bottom of the graph. \end_layout \begin_layout Standard The linear keyword is used to override a default logscale plot (as in the output for an AC analysis). \end_layout \begin_layout Standard Finally, the keyword \family typewriter \series bold polar \family default \series default generates a polar plot. To produce a smith plot, use the keyword \family typewriter \series bold smith \family default \series default . Note that the data is transformed, so for smith plots you will see the data transformed by the function (x-1)/(x+1). To produce a polar plot with a smith grid but without performing the smith transform, use the keyword \family typewriter \series bold smithgrid \family default \series default . \end_layout \begin_layout Standard If you specify \family typewriter \series bold plot all \family default \series default , all vectors (including the scale vector) are plotted versus the scale vector (see commands display ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Display:-List-known" \end_inset ) or setscale ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Setscale:-Set-the" \end_inset ) on viewing the vectors of the current plot). The command \family typewriter \series bold plot ally \family default \series default will not plot the scale vector, but all other 'real' y values. The command \family typewriter \series bold plot alli \family default \series default will yield all current vectors, the command \family typewriter \series bold plot allv \family default \series default all voltage vectors. \end_layout \begin_layout Standard If the vector name to be plotted contains -, or / or other tokens which may be taken for operators of an expression, and plotting fails, try enclosing the name in double quotes, e.g. \family typewriter \series bold plot \begin_inset Quotes eld \end_inset /vout \begin_inset Quotes erd \end_inset \family default \series default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Print:-Print-values" \end_inset Print: Print values \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout print [col] [line] expr ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Prints the vector(s) described by the expression expr. If the col argument is present, print the vectors named side by side. If line is given, the vectors are printed horizontally. col is the default, unless all the vectors named have a length of one, in which case line is the default. The options width, length, and nobreak are effective for this command (see asciiplot). If the expression is all, all of the vectors available are printed. Thus print col all > file prints everything in the file in SPICE2 format. The scale vector (time, frequency) is always in the first column unless the variable noprintscale is true. You may use the vectors alli, allv, ally with the print command, but then the scale vector will not be printed. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout set width=300 \end_layout \begin_layout Plain Layout print all \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout set length=500 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Quit: Leave Ngspice or Nutmeg \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout quit \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Quit ngnutmeg or ngspice. Ngspice will ask for an acknowledgment if parameters have not been saved. If \series bold 'set noaskquit' \series default is specified, ngspice will terminate immediately. \end_layout \begin_layout Subsection Rehash: Reset internal hash tables \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout rehash \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Recalculate the internal hash tables used when looking up UNIX commands, and make all UNIX commands in the user's PATH available for command completion. This is useless unless you have set unixcom first (see above). \end_layout \begin_layout Subsection Remcirc*: Remove the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout remcirc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command removes the current circuit from the list of circuits sourced into ngspice. To select a specific circuit, use \series bold setcirc \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Setcirc*:-Change-the" \end_inset ). To load another circuit, refer to \series bold source \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Source:-Read-a" \end_inset ). The new actual circuit will the circuit on top of the list of the remaining circuits. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Reset*:-Reset-an" \end_inset Reset*: Reset an analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout reset \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Throw out any intermediate data in the circuit (e.g, after a breakpoint or after one or more analyses have been done already), and re-parse the input file. The circuit can then be re-run from it's initial state, overriding the affect of any set or alter commands. \end_layout \begin_layout Standard \series bold Reset \series default may be required in simulation loops preceeding any \series bold run \series default (or \series bold tran \series default ...) command. \end_layout \begin_layout Subsection Reshape: Alter the dimensionality or dimensions of a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout reshape vector vector ... \end_layout \begin_layout Plain Layout or \end_layout \begin_layout Plain Layout reshape vector vector ... [ dimension, dimension, ... ] \end_layout \begin_layout Plain Layout or \end_layout \begin_layout Plain Layout reshape vector vector ... [ dimension ][ dimension ] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command changes the dimensions of a vector or a set of vectors. The final dimension may be left off and it will be filled in automatically. If no dimensions are specified, then the dimensions of the first vector are copied to the other vectors. An error message of the form 'dimensions of x were inconsistent' can be ignored. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Resume*:-Continue-a" \end_inset Resume*: Continue a simulation after a stop \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout resume \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Resume a simulation after a stop or interruption (control-C). \end_layout \begin_layout Subsection Rspice*: Remote ngspice submission \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout rspice input file \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Runs a ngspice remotely taking the input file as a ngspice input file, or the current circuit if no argument is given. Ngnutmeg or ngspice waits for the job to complete, and passes output from the remote job to the user's standard output. When the job is finished the data is loaded in as with aspice. If the variable \family sans rhost \family default is set, ngnutmeg connects to this host instead of the default remote ngspice server machine. This command uses the \begin_inset Quotes eld \end_inset rsh \begin_inset Quotes erd \end_inset command and thereby requires authentication via a \begin_inset Quotes eld \end_inset \family typewriter .rhosts \family default \begin_inset Quotes erd \end_inset file or other equivalent method. Note that \begin_inset Quotes eld \end_inset \family sans rsh \family default \begin_inset Quotes erd \end_inset refers to the \begin_inset Quotes eld \end_inset remote shell \begin_inset Quotes erd \end_inset program, which may be \begin_inset Quotes eld \end_inset \family sans remsh \family default \begin_inset Quotes erd \end_inset on your system; to override the default name of \begin_inset Quotes eld \end_inset \family sans rsh \family default \begin_inset Quotes erd \end_inset , set the variable \family typewriter remote_shell \family default . If the variable \family typewriter rprogram \family default is set, then \family sans rspice \family default uses this as the pathname to the program to run on the remote system. \end_layout \begin_layout Standard Note: \family sans rspice \family default will not acknowledge elements that have been changed via the \begin_inset Quotes eld \end_inset \family sans alter \family default \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset \family sans altermod \family default \begin_inset Quotes erd \end_inset commands. \end_layout \begin_layout Subsection Run*: Run analysis from the input file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout run [rawfile] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Run the simulation as specified in the input file. If there were any of the control lines .ac, .op, .tran, or .dc, they are executed. The output is put in \series bold rawfile \series default if it was given, in addition to being available interactively. \end_layout \begin_layout Subsection Rusage: Resource usage \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout rusage [resource ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print resource usage statistics. If any resources are given, just print the usage of that resource. Most resources require that a circuit be loaded. Currently valid resources are: \end_layout \begin_layout Description decklineno Number of lines in deck \end_layout \begin_layout Description netloadtime Nelist loading time \end_layout \begin_layout Description netparsetime Netlist parsing time \end_layout \begin_layout Description elapsed The amount of time elapsed since the last rusage elapsed call. \end_layout \begin_layout Description faults Number of page faults and context switches (BSD only). \end_layout \begin_layout Description space Data space used. \end_layout \begin_layout Description time CPU time used so far. \end_layout \begin_layout Description temp Operating temperature. \end_layout \begin_layout Description tnom Temperature at which device parameters were measured. \end_layout \begin_layout Description equations Circuit Equations \end_layout \begin_layout Description time Total Analysis Time \end_layout \begin_layout Description totiter Total iterations \end_layout \begin_layout Description accept Accepted time-points \end_layout \begin_layout Description rejected Rejected time-points \end_layout \begin_layout Description loadtime Time spent loading the circuit matrix and RHS. \end_layout \begin_layout Description reordertime Matrix reordering time \end_layout \begin_layout Description lutime L-U decomposition time \end_layout \begin_layout Description solvetime Matrix solve time \end_layout \begin_layout Description trantime Transient analysis time \end_layout \begin_layout Description tranpoints Transient time-points \end_layout \begin_layout Description traniter Transient iterations \end_layout \begin_layout Description trancuriters Transient iterations for the last time point* \end_layout \begin_layout Description tranlutime Transient L-U decomposition time \end_layout \begin_layout Description transolvetime Transient matrix solve time \end_layout \begin_layout Description everything All of the above. \end_layout \begin_layout Standard * listed incorrectly as "Transient iterations per point". \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Save*:-Save-a" \end_inset Save*: Save a set of outputs \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout save [all | allv | alli | output ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Save a set of outputs, discarding the rest. Maybe used to dramatically reduce memory (RAM) requirements if only a few useful nodes or branches are saved. If a node has been mentioned in a save command, it appears in the working plot after a run has completed, or in the rawfile if ngspice is run in batch mode. If a node is traced or plotted (see below) it is also saved. For backward compatibility, if there are no save commands given, all outputs are saved. \end_layout \begin_layout Standard When the keyword \begin_inset Quotes eld \end_inset \family sans all \family default \begin_inset Quotes erd \end_inset or the keyword \begin_inset Quotes eld \end_inset \family sans allv \family default \begin_inset Quotes erd \end_inset , appears in the save command, all node voltages, voltage source currents and inductor currents are saved in addition to any other values listed. If the keyword \begin_inset Quotes eld \end_inset \family sans alli \family default \begin_inset Quotes erd \end_inset appears in the save command, all device currents are saved. \end_layout \begin_layout Standard Note: the current implementation saves only the currents of devices which have internal nodes, i.e. MOSFETs with non zero RD and RS; BJTs with non-zero RC, RB and RE; DIODEs with non-zero RS; etc. Resistor and capacitor currents are not saved with this option. These deficiencies will be addressed in a later revision. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Save voltage and current: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout save vd_node vs#branch \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Note: \family typewriter save \family default will not accept vectors (in contrast to \family typewriter .save \family default ). Nodes or branches have to be specified for \family typewriter \family default ! In the \family typewriter .control .... .endc \family default section \family typewriter save \family default should occur before the \family typewriter run \family default or \family typewriter tran \family default command to become effective. \family typewriter \series bold Save \family default \series default allows to store and later access internal device parameters. e.g. in a command like \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Save internal parameters: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout save all @mn1[gm] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard which saves all analysis output data plus \family typewriter \series bold gm \family default \series default of transistor mn1 to the internal memory (see also \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ). \end_layout \begin_layout Standard \family typewriter save \family default may store data from a device residing indside of a subcircuit: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Save internal parameters: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout save @m.xmos3.mn1[gm] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Please see chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" \end_inset for an explanation of the syntax. \end_layout \begin_layout Subsection Sens*: Run a sensitivity analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout sens output_variable \end_layout \begin_layout Plain Layout sens output_variable ac ( DEC | OCT | LIN ) N Fstart Fstop \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Perform a Sensitivity analysis. \family typewriter output_variable \family default is either a node voltage (ex. \begin_inset Quotes eld \end_inset \family typewriter v(1) \family default \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset \family typewriter v(A,out) \family default \begin_inset Quotes erd \end_inset ) or a current through a voltage source (ex. \begin_inset Quotes eld \end_inset \family typewriter i(vtest) \family default \begin_inset Quotes erd \end_inset ). The first form calculates DC sensitivities, the second form calculates AC sensitivities. The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or per percent change of input). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Set:-Set-the" \end_inset Set: Set the value of a variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout set [word] \end_layout \begin_layout Plain Layout set [word = value] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set the value of word to be value, if it is present. You can set any word to be any value, numeric or string. If no value is given then the value is the Boolean 'true'. If you enter a string containing spaces, you have to enclose it with double quotes. \end_layout \begin_layout Standard The value of word may be inserted into a command by writing \family typewriter $word \family default . If a variable is set to a list of values that are enclosed in parentheses (which must be separated from their values by white space), the value of the variable is the list. \end_layout \begin_layout Standard The variables used by ngspice are listed in section \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset . \end_layout \begin_layout Standard \family typewriter \series bold Set \family default \series default entered without any parameter will list all variables set, and their values, if applicable. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Setcirc*:-Change-the" \end_inset Setcirc*: Change the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout setcirc [circuit name] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The current circuit is the one that is used for the simulation commands below. When a circuit is loaded with the source command (see below, \begin_inset CommandInset ref LatexCommand ref reference "sub:Source:-Read-a" \end_inset ) it becomes the current circuit. \end_layout \begin_layout Standard \family typewriter \series bold Setcirc \family default \series default followed by 'return' without any parameter will list all circuits loaded. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Setplot:-Switch-the" \end_inset Setplot: Switch the current set of vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout setplot [plotname] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set the current plot to the plot with the given name, or if no name is given, prompt the user with a menu. (Note that the plots are named as they are loaded, with names like \family typewriter tran1 \family default or \family typewriter op2 \family default . These names are shown by the \family sans setplot \family default and \family sans display \family default commands and are used by diff, below.) If the \begin_inset Quotes eld \end_inset \family typewriter New plot \family default \begin_inset Quotes erd \end_inset item is selected, the current plot becomes one with no vectors defined. \end_layout \begin_layout Standard Note that here the word \begin_inset Quotes eld \end_inset plot \begin_inset Quotes erd \end_inset refers to a group of vectors that are the result of one ngspice run. When more than one file is loaded in, or more than one plot is present in one file, ngspice keeps them separate and only shows you the vectors in the current plot. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Setscale:-Set-the" \end_inset Setscale: Set the scale vector for the current plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout setscale [vector] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Defines the scale vector for the current plot. If no argument is given, the current scale vector is printed. The scale vector delivers the values for the x-axis in a 2D plot. \end_layout \begin_layout Subsection Settype: Set the type of a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout settype type vector ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Change the type of the named vectors to \family typewriter type \family default . Type names can be found in the following table. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout notype \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pole \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout zero \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout s-param \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout temp-sweep \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Celsius \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout res-sweep \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ohms \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout onoise-spectrum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout (V or A)^2/Hz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout impedance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ohms \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout onoise-integrated \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V or A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout admittance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mhos \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inoise-spectrum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout (V or A)^2/Hz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout power \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inoise-integrated \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V or A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Degree \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout decibel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout dB \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Shell: Call the command interpreter \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout shell [ command ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Call the operating system's command interpreter; execute the specified command or call for interactive use. \end_layout \begin_layout Subsection Shift: Alter a list variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout shift [varname] [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If \family typewriter varname \family default is the name of a list variable, it is shifted to the left by number elements (i.e, the number leftmost elements are removed). The default \family typewriter varname \family default is \family typewriter argv \family default , and the default number is 1. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Show*:-List-device" \end_inset Show*: List device state \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout show devices [ : parameters ] , ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The show command prints out tables summarizing the operating condition of selected devices. If \family typewriter devices \family default is missing, a default set of devices are listed, if \family typewriter devices \family default is a single letter, devices of that type are listed. A device's full name may be specified to list only that device. Finally, devices may be selected by model by using the form \begin_inset Quotes eld \end_inset #modelname \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard If no parameters are specified, the values for a standard set of parameters are listed. If the list of parameters contains a \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset , the default set of parameters is listed along with any other specified parameters. \end_layout \begin_layout Standard For both devices and parameters, the word \begin_inset Quotes eld \end_inset all \begin_inset Quotes erd \end_inset has the obvious meaning. \end_layout \begin_layout Standard Note: there must be spaces separating the \begin_inset Quotes eld \end_inset : \begin_inset Quotes erd \end_inset that divides the device list from the parameter list. \end_layout \begin_layout Subsection Showmod*: List model parameter values \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout showmod models [ : parameters ] , ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The showmod command operates like the show command (above) but prints out model parameter values. The applicable forms for \family typewriter models \family default are a single letter specifying the device type letter (e.g. m, or c), a device name (e.g. m.xbuf22.m4b), or #modelname (e.g. #p1). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Source:-Read-a" \end_inset Source: Read a ngspice input file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout source infile \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For ngspice: read the ngspice input file \series bold infile \series default , containing a circuit netlist. Ngnutmeg and ngspice commands may be included in the file, and must be enclosed between the lines \family typewriter .control \family default and \family typewriter .endc \family default . These commands are executed immediately after the circuit is loaded, so a control line of \family typewriter ac ... \family default works the same as the corresponding .ac card. The first line in any input file is considered a title line and not parsed but kept as the name of the circuit. Thus, a ngspice command script in \series bold infile \series default must begin with a blank line and then with a .control line. Also, any line starting with the characters *# is considered as a control line (.control and .endc is placed around this line automatically.). The exception to these rules are the files \series bold spinit \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) and \series bold .spiceinit \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ). \end_layout \begin_layout Standard For ngutmeg: reads commands from the file \series bold infile \series default . Lines beginning with the character * are considered comments and are ignored. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Spec:-Create-a" \end_inset Spec: Create a frequency domain plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spec start_freq stop_freq step_freq vector [vector ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Calculates a new complex vector containing the Fourier transform of the input vector (typically the linearized result of a transient analysis). The default behavior is to use a Hanning window, but this can be changed by setting the variables specwindow and specwindoworder appropriately. \end_layout \begin_layout Standard Typical usage: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 13 -> linearize \end_layout \begin_layout Plain Layout ngspice 14 -> set specwindow = "blackman" \end_layout \begin_layout Plain Layout ngspice 15 -> spec 10 1000000 1000 v(out) \end_layout \begin_layout Plain Layout ngspice 16 -> plot mag(v(out)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Possible values for specwindow are: none, hanning, cosine, rectangular, hamming, triangle, bartlet, blackman, gaussian and flattop. In the case of a gaussian window specwindoworder is a number specifying its order. For a list of window functions see \begin_inset CommandInset ref LatexCommand ref reference "sub:fft:-fast-Fourier" \end_inset . \end_layout \begin_layout Subsection Status*: Display breakpoint information \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout status \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Display all of the traces and breakpoints currently in effect. \end_layout \begin_layout Subsection Step*: Run a fixed number of time-points \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout step [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Iterate number times, or once, and then stop. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Stop*:-Set-a" \end_inset Stop*: Set a breakpoint \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout stop [ after n] [ when value cond value ] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set a breakpoint. The argument after \family typewriter \series bold n \family default \series default means stop after iteration number \begin_inset Quotes eld \end_inset n \begin_inset Quotes erd \end_inset , and the argument \family typewriter \series bold when value cond value \family default \series default means stop when the first value is in the given relation with the second value, the possible relations being \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Symbol \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meaning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout = \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eq \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout equal to \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ne \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than or equal to \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout le \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than or equal to \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Symbol or alias may be used alternatively. All stop commands have to be given in the control flow before the run command. The values above may be node names in the running circuit, or real values. If more than one condition is given, e.g. \end_layout \begin_layout Standard \family typewriter stop after 4 when v(1) > 4 when v(2) < 2 \family default , \end_layout \begin_layout Standard the conjunction of the conditions is implied. If the condition is met, the simulation and control flow are interrupted, and ngspice waits for user input. \end_layout \begin_layout Standard In a transient simulation the '=' or 'eq' will only work with vector 'time' in commands like \end_layout \begin_layout Standard \family typewriter stop when time = 200n \family default . \end_layout \begin_layout Standard Internally a breakpoint will be set at the time requested. Multiple breakpoints may be set. If the first stop condition is met, the simulation is interrupted, the commands following run or tran (e.g. alter or altermod) are executed, then the simulation may continue at the first resume command. The next breakpoint requires another resume to continue automatically. Otherwise the simulation stops and ngspice waits for user input. \end_layout \begin_layout Standard If you try to stop at \end_layout \begin_layout Standard \family typewriter stop when V(1) eq 1 \family default \end_layout \begin_layout Standard (or similar) during a transient simulation, you probably will miss this point, because it is not very likely that at any time step the vector v(1) will have the exact value of 1. Then ngspice simply will not stop. \end_layout \begin_layout Subsection Strcmp: Compare two strings \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout strcmp _flag $string1 "string2" \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The command compares two strings, either given by a variable (string1) or as a string in quotes ( \begin_inset Quotes eld \end_inset string2 \begin_inset Quotes erd \end_inset ). _flag is set as an output variable to '0', if both strings are equal. A value greater than zero indicates that the first character that does not match has a greater value in str1 than in str2; and a value less than zero indicates the opposite (like the C strcmp function). \end_layout \begin_layout Subsection Sysinfo*: Print system information \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout sysinfo \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The command prints system information useful for sending bug report to developer s. Information consists of: \end_layout \begin_layout Itemize Name of the operating system, \end_layout \begin_layout Itemize CPU type, \end_layout \begin_layout Itemize Number of physical processors (not available under Windows OS), number of logical processors, \end_layout \begin_layout Itemize Total amount of DRAM available, \end_layout \begin_layout Itemize DRAM currently available. \end_layout \begin_layout Standard The example below shows the use of this command. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 1 -> sysinfo \end_layout \begin_layout Plain Layout OS: CYGWIN_NT-5.1 1.5.25(0.156/4/2) 2008-06-12 19:34 \end_layout \begin_layout Plain Layout CPU: Intel(R) Pentium(R) 4 CPU 3.40GHz \end_layout \begin_layout Plain Layout Logical processors: 2 \end_layout \begin_layout Plain Layout Total DRAM available = 1535.480469 MB. \end_layout \begin_layout Plain Layout DRAM currently available = 984.683594 MB. \end_layout \begin_layout Plain Layout ngspice 2 -> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command has been tested under Windows OS and LINUX. It may not be available in your operating system environment. \end_layout \begin_layout Subsection Tf*: Run a Transfer Function analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout tf output_node input_source \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family sans tf \family default command performs a transfer function analysis, returning: \end_layout \begin_layout Itemize the transfer function (output/input), \end_layout \begin_layout Itemize output resistance, \end_layout \begin_layout Itemize and input resistance \end_layout \begin_layout Standard between the given output node and the given input source. The analysis assumes a small-signal DC (slowly varying) input. The following example file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * Tf test circuit \end_layout \begin_layout Plain Layout vs 1 0 dc 5 \end_layout \begin_layout Plain Layout r1 1 2 100 \end_layout \begin_layout Plain Layout r2 2 3 50 \end_layout \begin_layout Plain Layout r3 3 0 150 \end_layout \begin_layout Plain Layout r4 2 0 200 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout tf v(3,5) vs \end_layout \begin_layout Plain Layout print all \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard will yield the following output: \end_layout \begin_layout Standard \family typewriter transfer_function = 3.750000e-001 \end_layout \begin_layout Standard \family typewriter output_impedance_at_v(3,5) = 6.662500e+001 \end_layout \begin_layout Standard \family typewriter vs#input_impedance = 2.000000e+002 \end_layout \begin_layout Subsection Trace*: Trace nodes \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout trace [ node ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For every step of an analysis, the value of the node is printed. Several traces may be active at once. Tracing is not applicable for all analyses. To remove a trace, use the delete command. \end_layout \begin_layout Subsection Tran*: Perform a transient analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout tran Tstep Tstop [ Tstart [ Tmax ] ] [ UIC ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Perform a transient analysis. See chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:.TRAN:-Transient-Analysis" \end_inset of this manual for more details. \end_layout \begin_layout Subsection Transpose: Swap the elements in a multi-dimensional data set \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout transpose vector vector ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command transposes a multidimensional vector. No analysis in ngspice produces multidimensional vectors, although the DC transfer curve may be run with two varying sources. You must use the \begin_inset Quotes eld \end_inset \family sans reshape \family default \begin_inset Quotes erd \end_inset command to reform the one-dimensional vectors into two dimensional vectors. In addition, the default scale is incorrect for plotting. You must plot versus the vector corresponding to the second source, but you must also refer only to the first segment of this second source vector. For example (circuit to produce the transfer characteristic of a MOS transistor ): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout How to produce the transfer characteristic of a MOS transistor: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice > dc vgg 0 5 1 vdd 0 5 1 \end_layout \begin_layout Plain Layout ngspice > plot i(vdd) \end_layout \begin_layout Plain Layout ngspice > reshape all [6,6] \end_layout \begin_layout Plain Layout ngspice > transpose i(vdd) v(drain) \end_layout \begin_layout Plain Layout ngspice > plot i(vdd) vs v(drain)[0] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Unalias: Retract an alias \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout unalias [word ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Removes any aliases present for the words. \end_layout \begin_layout Subsection Undefine: Retract a definition \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout undefine function \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Definitions for the named user-defined functions are deleted. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Unlet:-Delete-the" \end_inset Unlet: Delete the specified vector(s) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout unlet vector [ vector ... ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Delete the specified vector(s). See also \series bold let \series default \begin_inset CommandInset ref LatexCommand eqref reference "sub:Let:-Assign-a" \end_inset . \end_layout \begin_layout Subsection Unset: Clear a variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout unset [word ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Clear the value of the specified variable(s) (word). \end_layout \begin_layout Subsection Version: Print the version of ngspice \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout version [-s | -f | ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print out the version of ngnutmeg that is running, if invoked without argument or with \series bold -s \series default or \series bold -f \series default . If the argument is a \series bold \series default (any string different from \series bold -s \series default or \series bold -f \series default is considered a \series bold \series default ), the command checks to make sure that the arguments match the current version of ngspice. (This is mainly used as a \family typewriter Command: \family default line in rawfiles.) \end_layout \begin_layout Standard Options description: \end_layout \begin_layout Itemize No option: The output of the command is the message you can see when running ngspice from the command line, no more no less. \end_layout \begin_layout Itemize \series bold -s \series default (hort): A shorter version of the message you see when calling ngspice from the command line. \end_layout \begin_layout Itemize \series bold -f \series default (ull): You may want to use this option if you want to know what extensions are included into the simulator and what compilation switches are active. A list of compilation options and included extensions is appended to the normal (not short) message. May be useful when sending bug reports. \end_layout \begin_layout Standard The following example shows what the command returns is some situations: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Use of the version command: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 10 -> version \end_layout \begin_layout Plain Layout ****** \end_layout \begin_layout Plain Layout ** ngspice-24 : Circuit level simulation program \end_layout \begin_layout Plain Layout ** The U. C. Berkeley CAD Group \end_layout \begin_layout Plain Layout ** Copyright 1985-1994, Regents of the University of California. \end_layout \begin_layout Plain Layout ** Please get your ngspice manual from \end_layout \begin_layout Plain Layout http://ngspice.sourceforge.net/docs.html \end_layout \begin_layout Plain Layout ** Please file your bug-reports at \end_layout \begin_layout Plain Layout http://ngspice.sourceforge.net/bugrep.html \end_layout \begin_layout Plain Layout ** Creation Date: Jan 1 2011 13:36:34 \end_layout \begin_layout Plain Layout ****** \end_layout \begin_layout Plain Layout ngspice 2 -> \end_layout \begin_layout Plain Layout ngspice 11 -> version 14 \end_layout \begin_layout Plain Layout Note: rawfile is version 14 (current version is 24) \end_layout \begin_layout Plain Layout ngspice 12 -> version 24 \end_layout \begin_layout Plain Layout ngspice 13 -> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Quote Note for developers: The option listing returned when \family sans version \family default is called with the \family typewriter \series bold -f \family default \series default flag is built at compile time using \family typewriter #ifdef \family default blocks. When new compile switches are added, if you want them to appear on the list, you have to modify the code in \family typewriter misccoms.c \family default . \end_layout \begin_layout Subsection Where*: Identify troublesome node or device \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout where \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When performing a transient or operating point analysis, the name of the last node or device to cause non-convergence is saved. The where command prints out this information so that you can examine the circuit and either correct the problem or make a bug report. You may do this either in the middle of a run or after the simulator has given up on the analysis. For transient simulation, the \family sans iplot \family default command can be used to monitor the progress of the analysis. When the analysis slows down severely or hangs, interrupt the simulator (with control-C) and issue the where command. Note that only one node or device is printed; there may be problems with more than one node. \end_layout \begin_layout Subsection Wrdata: Write data to a file (simple table) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout wrdata [file] [vecs] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Writes out the vectors to \family typewriter file \family default . \end_layout \begin_layout Standard This is a very simple printout of data in array form. Column one is the default scale data, column two the simulated data. If more than one vector is given, the third column again is the default scale, the fourth the data of the second vector. The default format is ASCII. All vectors have to stem from the same plot, otherwise a seg fault may occur. No further information is written to the file, so you have to keep track of your multiple outputs. The format may be changed in the near future. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout output example from two vectors: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout 0.000000e+000 -1.845890e-006 0.000000e+000 0.000000e+000 \end_layout \begin_layout Plain Layout 7.629471e+006 4.243518e-006 7.629471e+006 -4.930171e-006 \end_layout \begin_layout Plain Layout 1.525894e+007 -5.794628e-006 1.525894e+007 4.769020e-006 \end_layout \begin_layout Plain Layout 2.288841e+007 5.086875e-006 2.288841e+007 -3.670687e-006 \end_layout \begin_layout Plain Layout 3.051788e+007 -3.683623e-006 3.051788e+007 1.754215e-006 \end_layout \begin_layout Plain Layout 3.814735e+007 1.330798e-006 3.814735e+007 -1.091843e-006 \end_layout \begin_layout Plain Layout 4.577682e+007 -3.804620e-007 4.577682e+007 2.274678e-006 \end_layout \begin_layout Plain Layout 5.340630e+007 9.047444e-007 5.340630e+007 -3.815083e-006 \end_layout \begin_layout Plain Layout 6.103577e+007 -2.792511e-006 6.103577e+007 4.766727e-006 \end_layout \begin_layout Plain Layout 6.866524e+007 5.657498e-006 6.866524e+007 -2.397679e-006 \end_layout \begin_layout Plain Layout .... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If variable \series bold appendwrite \series default is set, the data may be added to an existing file. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Write:-Write-data" \end_inset Write: Write data to a file (Spice3f5 format) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout write [file] [exprs] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Writes out the expressions to \family typewriter file \family default . \end_layout \begin_layout Standard First vectors are grouped together by plots, and written out as such (i.e, if the expression list contained three vectors from one plot and two from another, then two plots are written, one with three vectors and one with two). Additionally, if the scale for a vector isn't present, it is automatically written out as well. \end_layout \begin_layout Standard The default format is a compact binary, but this can be changed to ASCII with the \family sans set filetype=ascii \family default command. The default file name is \family typewriter rawspice.raw \family default , or the argument to the \family typewriter \series bold -r \family default \series default flag on the command line, if there was one, and the default expression list is all. \end_layout \begin_layout Standard If variable \series bold appendwrite \series default is set, the data may be added to an existing file. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Wrs2p:-Write-scattering" \end_inset Wrs2p: Write scattering parameters to file (Touchstone® format) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout wrs2p [file] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Writes out the s-parameters of a two-port to \family typewriter file \family default . \end_layout \begin_layout Standard In the active plot the following is required: vectors \series bold frequency, S11 S12 S21 S22 \series default , all having the same length and having complex values (as a result of an ac analysis), and vector \series bold Rbase \series default . For details how to generate these data see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Scattering-parameters" \end_inset . \end_layout \begin_layout Standard The file format is Touchstone® Version 1, ASCII, frequency in Hz, real and imaginary parts of \series bold Snn \series default versus frequency. \end_layout \begin_layout Standard The default file name is \family typewriter s-param.s2p \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout output example: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout !2-port S-parameter file \end_layout \begin_layout Plain Layout !Title: test for scattering parameters \end_layout \begin_layout Plain Layout !Generated by ngspice at Sat Oct 16 13:51:18 2010 \end_layout \begin_layout Plain Layout # Hz S RI R 50 \end_layout \begin_layout Plain Layout !freq ReS11 ImS11 ReS21 ... \end_layout \begin_layout Plain Layout 2.500000e+006 -1.358762e-003 -1.726349e-002 9.966563e-001 \end_layout \begin_layout Plain Layout 5.000000e+006 -5.439573e-003 -3.397117e-002 9.867253e-001 \end_layout \begin_layout Plain Layout .... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Xgraph: use the xgraph(1) program for plotting. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout xgraph file [exprs] [plot options] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The ngspice/ngnutmeg xgraph command plots data like the plot command but via \family sans xgraph \family default , a popular X11 plotting program. If file is either \begin_inset Quotes eld \end_inset \family typewriter \series bold temp \family default \series default \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset \family typewriter \series bold tmp \family default \series default \begin_inset Quotes erd \end_inset a temporary file is used to hold the data while being plotted. For available plot options, see the \family sans plot \family default command. All options except for polar or smith plots are supported. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Control-Structures" \end_inset Control Structures \end_layout \begin_layout Subsection While - End \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout while condition \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard While condition, an arbitrary algebraic expression, is true, execute the statements. \end_layout \begin_layout Subsection Repeat - End \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout repeat [number] \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Execute the statements number times, or forever if no argument is given. \end_layout \begin_layout Subsection Dowhile - End \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout dowhile condition \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The same as while, except that the condition is tested after the statements are executed. \end_layout \begin_layout Subsection Foreach - End \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout foreach var value ... \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The statements are executed once for each of the values, each time with the variable \family typewriter \series bold var \family default \series default set to the current one. ( \family typewriter \series bold var \family default \series default can be accessed by the \family typewriter \series bold $var \family default \series default notation - see below). \end_layout \begin_layout Subsection If - Then - Else \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout if condition \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout else \end_layout \begin_layout Plain Layout statement \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If the condition is non-zero then the first set of statements are executed, otherwise the second set. The else and the second set of statements may be omitted. \end_layout \begin_layout Subsection Label \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout label word \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If a statement of the form goto word is encountered, control is transferred to this point, otherwise this is a no-op. \end_layout \begin_layout Subsection Goto \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout goto word \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If a statement of the form label word is present in the block or an enclosing block, control is transferred there. Note that if the label is at the top level, it must be before the goto statement (i.e, a forward goto may occur only within a block). A block to just include goto on the top level may look like \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example noop block to include forward goto on top level: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout if (1) \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout goto gohere \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout label gohere \end_layout \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Continue \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout continue \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If there is a while, dowhile, or foreach block enclosing this statement, control passes to the test, or in the case of foreach, the next value is taken. Otherwise an error results. \end_layout \begin_layout Subsection Break \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout break \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If there is a while, dowhile, or foreach block enclosing this statement, control passes out of the block. Otherwise an error results. \end_layout \begin_layout Standard Of course, control structures may be nested. When a block is entered and the input is the terminal, the prompt becomes a number of >'s corresponding to the number of blocks the user has entered. The current control structures may be examined with the debugging command cdump (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Cdump:-Dump-the" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Variables" \end_inset Variables \end_layout \begin_layout Standard The operation of both ngutmeg and ngspice may be affected by setting variables with the \begin_inset Quotes eld \end_inset \family sans set \family default \begin_inset Quotes erd \end_inset command ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Set:-Set-the" \end_inset ). In addition to the variables mentioned below, the \begin_inset Quotes eld \end_inset \family sans set \family default \begin_inset Quotes erd \end_inset command in ngspice also affects the behavior of the simulator via the options previously described under the section on \begin_inset Quotes eld \end_inset \family typewriter .OPTIONS \family default \begin_inset Quotes erd \end_inset ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Simulator-Variables" \end_inset ). You also may define new variables or alter existing variables inside .control ... .endc for later use in your user-defined script (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:SCRIPTS" \end_inset ). \end_layout \begin_layout Standard The following list is in alphabetical order. All of them are acknowledged by ngspice. Frontend variables (e.g. on circuits and simulation) are not defined in ngnutmeg. The predefined variables which may be set or altered by the \begin_inset Quotes eld \end_inset \family sans set \family default \begin_inset Quotes erd \end_inset command are: \end_layout \begin_layout Description appendwrite Append to the file when a write command is issued, if one already exists. \end_layout \begin_layout Description brief If set to \family typewriter FALSE \family default , the netlist will be printed. \end_layout \begin_layout Description colorN These variables determine the colors used, if X is being run on a color display. N may be between 0 and 15. Color 0 is the background, color 1 is the grid and text color, and colors 2 through 15 are used in order for vectors plotted. The value of the color variables should be names of colors, which may be found in the file \family typewriter /usr/lib/rgb.txt \family default . ngspice for Windows does support only white background (color0=white with black grid and text) or or color0=black with white grid and text. \end_layout \begin_layout Description cpdebug Print control debugging information. \end_layout \begin_layout Description curplotdate Sets the date of the current plot. \end_layout \begin_layout Description curplotname Sets the name of the current plot. \end_layout \begin_layout Description curplottitle Sets the title (a short description) of the current plot. \end_layout \begin_layout Description debug If set then a lot of debugging information is printed. \end_layout \begin_layout Description device The name ( \family typewriter /dev/tty?? \family default ) of the graphics device. If this variable isn't set then the user's terminal is used. To do plotting on another monitor you probably have to set both the device and term variables. (If device is set to the name of a file, nutmeg dumps the graphics control codes into this file -- this is useful for saving plots.) \end_layout \begin_layout Description diff_abstol The relative tolerance used by the \series bold diff \series default command (default is 1e-12). \end_layout \begin_layout Description diff_reltol The relative tolerance used by the \series bold diff \series default command (default is 0.001). \end_layout \begin_layout Description diff_vntol The absolute tolerance for voltage type vectors used by the \series bold diff \series default command (default is 1e-6). \end_layout \begin_layout Description echo Print out each command before it is executed. \end_layout \begin_layout Description editor The editor to use for the edit command. \end_layout \begin_layout Description filetype This can be either \family typewriter \series bold ascii \family default \series default or \family typewriter \series bold binary \family default \series default , and determines the format of the raw file (compact binary or text editor readable ascii). The default is \family typewriter \series bold binary \family default \series default . \end_layout \begin_layout Description fourgridsize How many points to use for interpolating into when doing Fourier analysis. \end_layout \begin_layout Description gridsize If this variable is set to an integer, this number is used as the number of equally spaced points to use for the Y axis when plotting. Otherwise the current scale is used (which may not have equally spaced points). If the current scale isn't strictly monotonic, then this option has no effect. \end_layout \begin_layout Description gridstyle Sets the grid during plotting with the plot command. Will be overridden by direct entry of gridstyle in the plot command. A linear grid is standard for both x and y axis. Allowed values are \family typewriter \series bold lingrid loglog xlog ylog smith smithgrid polar nogrid \family default \series default . \end_layout \begin_layout Description hcopydev If this is set, when the hardcopy command is run the resulting file is automatically printed on the printer named hcopydev with the command \family typewriter lpr -Phcopydev -g file \family default . \end_layout \begin_layout Description hcopyfont This variable specifies the font name for hardcopy output plots. The value is device dependent. \end_layout \begin_layout Description hcopyfontsize This is a scaling factor for the font used in hardcopy plots. \end_layout \begin_layout Description hcopydevtype This variable specifies the type of the printer output to use in the hardcopy command. If \series bold hcopydevtype \series default is not set, Postscript format is assumed. \family typewriter plot (5) \family default is recognized as an alternative output format. When used in conjunction with \series bold hcopydev \series default , \series bold hcopydevtype \series default should specify a format supported by the printer. \end_layout \begin_layout Description hcopyscale This is a scaling factor for the font used in hardcopy plots (between 0 and 10). \end_layout \begin_layout Description hcopywidth Sets width of the hardcopy plot. \end_layout \begin_layout Description hcopyheight Sets height of the hardcopy plot. \end_layout \begin_layout Description hcopypscolor Sets the color of the hardcopy output. If not set, black & white plotting is assumed with different linestyles for each output vector plotted. Setting to any valid color integer value yields a colored plot background (0: black 1: white, others see below) and colored solid lines. This is valid for postscript only. \end_layout \begin_layout Description hcopypstxcolor This variable sets the color of the text in the postscript hardcopy output. If not set, black is assumed on white background, white on black background. Valid colors are 0: black 1: white 2: red 3: blue 4: orange 5: green 6: pink 7: brown 8: khaki 9: plum 10: orchid 11: violet 12: maroon 13: turquoise 14: sienna 15: coral 16: cyan 17: magenta 18: gray for smith grid 19: gray for smith grid 20: gray for normal grid \end_layout \begin_layout Description height The length of the page for asciiplot and print col. \end_layout \begin_layout Description history The number of events to save in the history list. \end_layout \begin_layout Description lprplot5 This is a \family typewriter printf(3s) \family default style format string used to specify the command to use for sending plot(5)-styl e plots to a printer or plotter. The first parameter supplied is the printer name, the second parameter supplied is a file name containing the plot. Both parameters are strings. It is trivial to cause ngspice to abort by supplying a unreasonable format string. \end_layout \begin_layout Description lprps This is a \family typewriter printf(3s) \family default style format string used to specify the command to use for sending Postscript plots to a printer or plotter. The first parameter supplied is the printer name, the second parameter supplied is a file name containing the plot. Both parameters are strings. It is trivial to cause ngspice to abort by supplying a unreasonable format string. \end_layout \begin_layout Description modelcard The name of the model card (normally \family typewriter .MODEL \family default ) \end_layout \begin_layout Description nfreqs The number of frequencies to compute in the Fourier command. (Defaults to 10.) \end_layout \begin_layout Description ngbehavior Sets the compatibility mode of ngspice. To be set in spinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) or .spiceinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ).Its value \family typewriter 'all' \family default will inprove compatibility to commercial simulators. Full compatibility is however \series bold not \series default the intension of ngspice! This value may be set as a standard in the future. \family typewriter 'ps' \family default , \family typewriter 'hs' \family default and \family typewriter 'spice3' \family default are available. See chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Compatibility" \end_inset . \end_layout \begin_layout Description noaskquit Do not check to make sure that there are no circuits suspended and no plots unsaved. Normally ngspice warns the user when he tries to quit if this is the case. \end_layout \begin_layout Description nobjthack BJTs can have either 3 or 4 nodes, which makes it difficult for the subcircuit expansion routines to decide what to rename. If the fourth parameter has been declared as a model name, then it is assumed that there are 3 nodes, otherwise it is considered a node. To disable this, you can set the variable "nobjthack" which forces BJTs to have 4 nodes (for the purposes of subcircuit expansion, at least). \end_layout \begin_layout Description nobreak Don't have asciiplot and print col break between pages. \end_layout \begin_layout Description noasciiplotvalue Don't print the first vector plotted to the left when doing an asciiplot. \end_layout \begin_layout Description nobjthack Assume that BJTs have 4 nodes. \end_layout \begin_layout Description noclobber Don't overwrite existing files when doing IO redirection. \end_layout \begin_layout Description noglob Don't expand the global characters `*', `?', `[', and `]'. This is the default. \end_layout \begin_layout Description nomoremode If nomoremode is not set, whenever a large amount of data is being printed to the screen (e.g, the print or asciiplot commands), the output is stopped every screenful and continues when a carriage return is typed. If nomoremode is set then data scrolls off the screen without check. \end_layout \begin_layout Description nonomatch If noglob is unset and a global expression cannot be matched, use the global characters literally instead of complaining. \end_layout \begin_layout Description noparse Don't attempt to parse input files when they are read in (useful for debugging). Of course, they cannot be run if they are not parsed. \end_layout \begin_layout Description noprintscale Don't print the scale in the leftmost column when a print col command is given. \end_layout \begin_layout Description nosort Don't have display sort the variable names. \end_layout \begin_layout Description nosubckt Don't expand subcircuits. \end_layout \begin_layout Description notrnoise Switch off the transient noise sources (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Transient-noise-source" \end_inset ). \end_layout \begin_layout Description numdgt The number of digits to print when printing tables of data (a, print col). The default precision is 6 digits. On the VAX, approximately 16 decimal digits are available using double precision, so p should not be more than 16. If the number is negative, one fewer digit is printed to ensure constant widths in tables. \end_layout \begin_layout Description num_threads The number of of threads to be used if OpenMP (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-on-multi-core" \end_inset ) is selected. The default value is 2. \end_layout \begin_layout Description plotstyle This should be one of \family typewriter \series bold linplot \family default \series default , \family typewriter \series bold combplot \family default \series default , or \family typewriter \series bold pointplot \family default \series default . \family typewriter \series bold linplot \family default \series default , the default, causes points to be plotted as parts of connected lines. \family typewriter \series bold combplot \family default \series default causes a comb plot to be done. It plots vectors by drawing a vertical line from each point to the X-axis, as opposed to joining the points. \family typewriter \series bold pointplot \family default \series default causes each point to be plotted separately. \end_layout \begin_layout Description pointchars Set a string as a list of characters to be used as points in a point plot. Standard is ox*+#abcdefhgijklmnpqrstuvwyz. Characters §€ are not allowed. \end_layout \begin_layout Description polydegree The degree of the polynomial that the plot command should fit to the data. If polydegree is N, then nutmeg fits a degree N polynomial to every set of N points and draw 10 intermediate points in between each end point. If the points aren't monotonic, then it tries rotating the curve and reducing the degree until a fit is achieved. \end_layout \begin_layout Description polysteps The number of points to interpolate between every pair of points available when doing curve fitting. The default is 10. \end_layout \begin_layout Description program The name of the current program (argv[0]). \end_layout \begin_layout Description prompt The prompt, with the character `!' replaced by the current event number. Single quotes ' ' are required around the string entered! \end_layout \begin_layout Description rawfile The default name for rawfiles created. \end_layout \begin_layout Description remote_shell Overrides the name used for generating rspice runs (default is "rsh"). \end_layout \begin_layout Description renumber Renumber input lines when an input file has .includes. \end_layout \begin_layout Description rndseed Seed value for random number generator (used by sgauss, sunif, and rnd functions). If not set, the process Id is used as seed value. \end_layout \begin_layout Description rhost The machine to use for remote ngspice runs, instead of the default one (see the description of the rspice command, below). \end_layout \begin_layout Description rprogram The name of the remote program to use in the rspice command. \end_layout \begin_layout Description sourcepath A list of the directories to search when a source command is given. The default is the current directory and the standard ngspice library ( \family typewriter /usr/local/lib/ngspice \family default , or whatever LIBPATH is #defined to in the ngspice source. \end_layout \begin_layout Description specwindow Windowing for commands \family typewriter \series bold spec \family default \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Spec:-Create-a" \end_inset ) or \family typewriter \series bold fft \family default \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:fft:-fast-Fourier" \end_inset ). May be one of the following: \family typewriter \begin_inset Newline newline \end_inset bartlet blackman cosine gaussian hamming hanning none rectangular triangle \family default . \end_layout \begin_layout Description specwindoworder Integer value 2 - 8 (default 2), used by commands \family typewriter \series bold spec \family default \series default or \family typewriter \series bold fft \family default \series default . \end_layout \begin_layout Description spicepath The program to use for the aspice command. The default is /cad/bin/spice. \end_layout \begin_layout Description strict_errorhandling If set by the user, an error detected during circuit parsing will immediately lead ngspice to exit with exit code 1 (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Error-handling" \end_inset ). May be set in files spinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) or .spiceinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ) only. \end_layout \begin_layout Description subend The card to end subcircuits (normally \family typewriter .ends \family default ). \end_layout \begin_layout Description subinvoke The prefix to invoke subcircuits (normally \family typewriter X \family default ). \end_layout \begin_layout Description substart The card to begin subcircuits (normally \family typewriter .subckt \family default ). \end_layout \begin_layout Description term The mfb name of the current terminal. \end_layout \begin_layout Description ticmarks An integer value n, n tics (a small 'x') will be set on your graph. (Arrangement of the tics ?) \end_layout \begin_layout Description ticlist A list of integers, e.g. ( 4 14 24 ) to set tics (small 'x') on your graph.(Arrangement of the tics ?) \end_layout \begin_layout Description units If this is \series bold degrees \series default , then all the trig functions will use degrees instead of radians. \end_layout \begin_layout Description unixcom If a command isn't defined, try to execute it as a UNIX command. Setting this option has the effect of giving a rehash command, below. This is useful for people who want to use ngnutmeg as a login shell. \end_layout \begin_layout Description wfont Set the font for the graphics plot in MS Windows. Typical fonts are \family typewriter courier, times, arial \family default and all others found on your machine. Default is \family typewriter courier \family default . \end_layout \begin_layout Description wfont_size The size of the windows font. Default is depending on systems settings, something like \end_layout \begin_layout Description width The width of the page for asciiplot and print col (see also \begin_inset CommandInset ref LatexCommand ref reference "sub:.width" \end_inset ). \end_layout \begin_layout Description x11lineararcs Some X11 implementations have poor arc drawing. If you set this option, Ngspice will plot using an approximation to the curve using straight lines. \end_layout \begin_layout Description xbrushwidth Linewidth for grid, border and graph. \end_layout \begin_layout Description xfont Set the font for the graphics plot in X11 (LINUX, Cygwin, etc.). Input format has still to be checked. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:SCRIPTS" \end_inset Scripts \end_layout \begin_layout Standard Expressions, functions, constants, commands, variables, vectors, and control structures may be assembled into scripts within a .control ... .endc section of the input file. The script allows to automate a more complex ngspice behavior: simulations are performed, output data are the analyzed, simulations repeated with modified parameters, output vectors for plotting are assembled. The ngspice scripting language is not very powerful, but easily integrated into the simulation flow. \end_layout \begin_layout Standard The ngspice input file for scripting contains the usual circuit netlist, modelcards, and a script, enclosed in the .control .. .endc section. ngspice is started in interactive mode with the input file in the command line (or sourced later with the \family typewriter \series bold source \family default \series default command). After reading the input file, the command sequence is immediately processed. Variables or vectors set by previous commands may be used in commands following their definition. data may be stored, plotted or grouped into new vectors for additional charts supporting data evaluation. \end_layout \begin_layout Subsection Variables \end_layout \begin_layout Standard Variables are defined and initialized with the \family typewriter \series bold set \family default \series default command ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset ). \family typewriter set output=10 \family default will defined the variable \family typewriter output \family default and set it to a (real) number 10. Predefined variables, which are used inside ngspice for specific purposes, are listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset . Variables are accessible globally. The values of variables may be used in commands by writing \family typewriter $varname \family default where the value of the variable is to appear, e.g. \family typewriter $output \family default . The special variables \family typewriter $$ \family default and \family typewriter $< \family default refer to the process ID of the program and a line of input which is read from the terminal when the variable is evaluated, respectively. If a variable has a name of the form \family typewriter $&word \family default , then word is considered a vector (see below), and its value is taken to be the value of the variable. If \family typewriter $foo \family default is a valid variable, and is of type list, then the expression \family typewriter $foo[low-high] \family default represents a range of elements. Either the upper index or the lower may be left out, and the reverse of a list may be obtained with \family typewriter $foo[len-0] \family default . Also, the notation \family typewriter $?foo \family default evaluates to 1 if the variable foo is defined, 0 otherwise, and \family typewriter $#foo \family default evaluates to the number of elements in foo if it is a list, 1 if it is a number or string, and 0 if it is a Boolean variable. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Vectors" \end_inset Vectors \end_layout \begin_layout Standard Ngspice and ngnutmeg data is in the form of vectors: time, voltage, etc. Each vector has a type, and vectors can be operated on and combined algebraical ly in ways consistent with their types. Vectors are normally created as a result of a transient or dc simulation. They are also established when a data file is read in (see the \family sans load \family default command \begin_inset CommandInset ref LatexCommand ref reference "sub:Load:-Load-rawfile" \end_inset ). They can also be created with the \family sans let \family default command \begin_inset CommandInset ref LatexCommand ref reference "sub:Let:-Assign-a" \end_inset inside a script. If a variable has a name of the form $&word, then 'word' is considered a vector, and its value is taken to be the value of the variable. \end_layout \begin_layout Subsection Commands \end_layout \begin_layout Standard Commands have been described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset . \end_layout \begin_layout Subsection control structures \end_layout \begin_layout Standard Control structures have been described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" \end_inset . Some simple examples will be given below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control structure examples: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout Test sequences for ngspice control structures \end_layout \begin_layout Plain Layout *vectors are used (except foreach) \end_layout \begin_layout Plain Layout *start in interactive mode \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * test sequence for while, dowhile \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo enter loop with "$&loop" \end_layout \begin_layout Plain Layout dowhile loop < 3 \end_layout \begin_layout Plain Layout echo within dowhile loop "$&loop" \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo after dowhile loop "$&loop" \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout while loop < 3 \end_layout \begin_layout Plain Layout echo within while loop "$&loop" \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo after while loop "$&loop" \end_layout \begin_layout Plain Layout let loop = 3 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo enter loop with "$&loop" \end_layout \begin_layout Plain Layout dowhile loop < 3 \end_layout \begin_layout Plain Layout echo within dowhile loop "$&loop" $ output expected \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo after dowhile loop "$&loop" \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let loop = 3 \end_layout \begin_layout Plain Layout while loop < 3 \end_layout \begin_layout Plain Layout echo within while loop "$&loop" $ no output expected \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo after while loop "$&loop" \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control structure examples (continued): \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout * test for while, repeat, if, break \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout while loop < 4 \end_layout \begin_layout Plain Layout let index = 0 \end_layout \begin_layout Plain Layout repeat \end_layout \begin_layout Plain Layout let index = index + 1 \end_layout \begin_layout Plain Layout if index > 4 \end_layout \begin_layout Plain Layout break \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo index "$&index" loop "$&loop" \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * test sequence for foreach \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout foreach outvar 0 0.5 1 1.5 \end_layout \begin_layout Plain Layout echo parameters: $outvar $ foreach parameters are variables, \end_layout \begin_layout Plain Layout $ not vectors! \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * test for if ... else ... end \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout let index = 1 \end_layout \begin_layout Plain Layout dowhile loop < 10 \end_layout \begin_layout Plain Layout let index = index * 2 \end_layout \begin_layout Plain Layout if index < 128 \end_layout \begin_layout Plain Layout echo "$&index" lt 128 \end_layout \begin_layout Plain Layout else \end_layout \begin_layout Plain Layout echo "$&index" ge 128 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * simple test for label, goto \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout label starthere \end_layout \begin_layout Plain Layout echo start "$&loop" \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout if loop < 3 \end_layout \begin_layout Plain Layout goto starthere \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo end "$&loop" \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control structure examples (continued): \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout * test for label, nested goto \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout label starthere1 \end_layout \begin_layout Plain Layout echo start nested "$&loop" \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout if loop < 3 \end_layout \begin_layout Plain Layout if loop < 3 \end_layout \begin_layout Plain Layout goto starthere1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo end "$&loop" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * test for label, goto \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout let index = 0 \end_layout \begin_layout Plain Layout label starthere2 \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout echo We are at start with index "$&index" and loop "$&loop" \end_layout \begin_layout Plain Layout if index < 6 \end_layout \begin_layout Plain Layout label inhere \end_layout \begin_layout Plain Layout let index = index + 1 \end_layout \begin_layout Plain Layout if loop < 3 \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout if index > 1 \end_layout \begin_layout Plain Layout echo jump2 \end_layout \begin_layout Plain Layout goto starthere2 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo jump \end_layout \begin_layout Plain Layout goto inhere \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo We are at end with index "$&index" and loop "$&loop" \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Control structure examples (continued): \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout * test goto in while loop \end_layout \begin_layout Plain Layout let loop = 0 \end_layout \begin_layout Plain Layout if 1 $ outer loop to allow nested forward label 'endlabel' \end_layout \begin_layout Plain Layout while loop < 10 \end_layout \begin_layout Plain Layout if loop > 5 \end_layout \begin_layout Plain Layout echo jump \end_layout \begin_layout Plain Layout goto endlabel \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout let loop = loop + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo before $ never reached \end_layout \begin_layout Plain Layout label endlabel \end_layout \begin_layout Plain Layout echo after "$&loop" \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout *test for using variables, simple test for label, goto \end_layout \begin_layout Plain Layout set loop = 0 \end_layout \begin_layout Plain Layout label starthe \end_layout \begin_layout Plain Layout echo start $loop \end_layout \begin_layout Plain Layout let loop = $loop + 1 $ expression needs vector at lhs \end_layout \begin_layout Plain Layout set loop = "$&loop" $ convert vector contents to variable \end_layout \begin_layout Plain Layout if $loop < 3 \end_layout \begin_layout Plain Layout goto starthe \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout echo end $loop \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Example script 'spectrum' \end_layout \begin_layout Standard A typical example script named \series bold spectrum \series default is delivered with the ngspice distribution. Even if it is made obsolete by the internal \series bold spec \series default command (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Spec:-Create-a" \end_inset ) and especially by the much faster \series bold fft \series default command (see \begin_inset CommandInset ref LatexCommand ref reference "sub:fft:-fast-Fourier" \end_inset ), it may act as a good example for getting acquainted with the ngspice (or nutmeg) post-processor language. \end_layout \begin_layout Standard As a suitable input for spectrum you may run a ring-oscillator, delivered with ngspice in e.g. test/bsim3soi/ring51_41.cir. For an adequate resolution you will need a simulation time of 1 µs. Then a small control script may start ngspice by loading the R.O. simulation data and start \series bold spectrum \series default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Small script to start ngspice, read the simulation data and start spectrum: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * test for script 'spectrum' \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout load ring51_41.out \end_layout \begin_layout Plain Layout spectrum 10MEG 2500MEG 1MEG v(out25) v(out50) \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Example script for random numbers \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Generation and test of random numbers with Gaussian distribution \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * agauss test in ngspice \end_layout \begin_layout Plain Layout * generate a sequence of gaussian distributed random numbers. \end_layout \begin_layout Plain Layout * test the distribution by sorting the numbers into \end_layout \begin_layout Plain Layout * a histogram (buckets) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) \end_layout \begin_layout Plain Layout let mc_runs = 200 \end_layout \begin_layout Plain Layout let run = 0 \end_layout \begin_layout Plain Layout let no_buck = 8 $ number of buckets \end_layout \begin_layout Plain Layout let bucket = unitvec(no_buck) $ each element contains 1 \end_layout \begin_layout Plain Layout let delta = 3e-11 $ width of each bucket, depends \end_layout \begin_layout Plain Layout $ on avar and sig \end_layout \begin_layout Plain Layout let lolimit = 1e-09 - 3*delta \end_layout \begin_layout Plain Layout let hilimit = 1e-09 + 3*delta \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout dowhile run < mc_runs \end_layout \begin_layout Plain Layout let val = agauss(1e-09, 1e-10, 3) $ get the random number \end_layout \begin_layout Plain Layout if (val < lolimit) \end_layout \begin_layout Plain Layout let bucket[0] = bucket[0] + 1 $ 'lowest' bucket \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout let part = 1 \end_layout \begin_layout Plain Layout dowhile part < (no_buck - 1) \end_layout \begin_layout Plain Layout if ((val < (lolimit + part*delta)) & \end_layout \begin_layout Plain Layout + (val > (lolimit + (part-1)*delta))) \end_layout \begin_layout Plain Layout let bucket[part] = bucket[part] + 1 \end_layout \begin_layout Plain Layout break \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout let part = part + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout if (val > hilimit) \end_layout \begin_layout Plain Layout * 'highest' bucket \end_layout \begin_layout Plain Layout let bucket[no_buck - 1] = bucket[no_buck - 1] + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout let run = run + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout let part = 0 \end_layout \begin_layout Plain Layout dowhile part < no_buck \end_layout \begin_layout Plain Layout let value = bucket[part] - 1 \end_layout \begin_layout Plain Layout set value = "$&value" \end_layout \begin_layout Plain Layout * print the buckets' contents \end_layout \begin_layout Plain Layout echo $value \end_layout \begin_layout Plain Layout let part = part + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Parameter-sweep" \end_inset Parameter sweep \end_layout \begin_layout Standard While there is no direct command to sweep a device parameter during simulation, you may use a script to emulate such behavior. The example input file contains of an resistive divider with R1 and R2, where R1 is swept from a start to a stop value inside of the control section, using the \family typewriter alter \family default command (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Alter*:-Change-a" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file with parameter sweep \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout parameter sweep \end_layout \begin_layout Plain Layout * resistive divider, R1 swept from start_r to stop_r \end_layout \begin_layout Plain Layout VDD 1 0 DC 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout R1 1 2 1k \end_layout \begin_layout Plain Layout R2 2 0 1k \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout let start_r = 1k \end_layout \begin_layout Plain Layout let stop_r = 10k \end_layout \begin_layout Plain Layout let delta_r = 1k \end_layout \begin_layout Plain Layout let r_act = start_r \end_layout \begin_layout Plain Layout * loop \end_layout \begin_layout Plain Layout while r_act le stop_r \end_layout \begin_layout Plain Layout alter r1 r_act \end_layout \begin_layout Plain Layout op \end_layout \begin_layout Plain Layout print v(2) \end_layout \begin_layout Plain Layout let r_act = r_act + delta_r \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Output-redirection" \end_inset Output redirection \end_layout \begin_layout Standard The console outputs delivered by commands like \series bold print \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Print:-Print-values" \end_inset ), \series bold echo \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Echo:-Print-text" \end_inset ), or others may be redirected into a text file. \family typewriter 'print vec > filename' \family default will generate a new file or overwrite an existing file named 'filename', \family typewriter 'echo text >> filename' \family default will append the new data to the file 'filename'. Output redirection may be mixed with commands like \series bold wrdata \series default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file with output redirection > and >> \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout ** MOSFET Gain Stage (AC): Benchmarking Implementation of BSIM4.0.0 by Weidong Liu 5/16/2000. \end_layout \begin_layout Plain Layout ** output redirection into file \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout M1 3 2 0 0 N1 L=1u W=4u \end_layout \begin_layout Plain Layout Rsource 1 2 100k \end_layout \begin_layout Plain Layout Rload 3 vdd 25k \end_layout \begin_layout Plain Layout Vdd vdd 0 1.8 \end_layout \begin_layout Plain Layout Vin 1 0 1.2 ac 0.1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout ac dec 10 100 1000Meg \end_layout \begin_layout Plain Layout plot v(2) v(3) \end_layout \begin_layout Plain Layout let flen = length(frequency) $ length of the vector \end_layout \begin_layout Plain Layout let loopcounter = 0 \end_layout \begin_layout Plain Layout echo output test > text.txt $ start new file test.txt \end_layout \begin_layout Plain Layout * loop \end_layout \begin_layout Plain Layout while loopcounter lt flen \end_layout \begin_layout Plain Layout let vout2 = v(2)[loopcounter] $ generate a single point complex vector \end_layout \begin_layout Plain Layout let vout2re = real(vout2) $ generate a single point real vector \end_layout \begin_layout Plain Layout let vout2im = imag(vout2) $ generate a single point imaginary vector \end_layout \begin_layout Plain Layout let vout3 = v(3)[loopcounter] $ generate a single point complex vector \end_layout \begin_layout Plain Layout let vout3re = real(vout3) $ generate a single point real vector \end_layout \begin_layout Plain Layout let vout3im = imag(vout3) $ generate a single point imaginary vector \end_layout \begin_layout Plain Layout let freq = frequency[loopcounter] $ generate a single point vector \end_layout \begin_layout Plain Layout echo bbb "$&freq" "$&vout2re" "$&vout2im" "$&vout3re" "$&vout3im" >> \end_layout \begin_layout Plain Layout +text.txt $ append text and data to file (continued fromm line above) \end_layout \begin_layout Plain Layout let loopcounter = loopcounter + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MODEL N1 NMOS LEVEL=14 VERSION=4.3.0 TNOM=27 \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Scattering-parameters" \end_inset Scattering parameters (s-parameters) \end_layout \begin_layout Subsection Intro \end_layout \begin_layout Standard A command line script, available from the ngspice distribution at examples/contr ol_structs/s-param.cir, together with the command wrs2p (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Wrs2p:-Write-scattering" \end_inset ) allows to calculate, print and plot the scattering parameters S11, S21, S12, and S22 of any two port circuit at varying frequencies. \end_layout \begin_layout Standard The printed output using wrs2p is a \series bold Touchstone® version 1 \series default format file. The file follows the format according to The Touchstone File Format Specificati on, Version 2.0, available from \begin_inset CommandInset href LatexCommand href name "here" target "http://www.eda.org/ibis/touchstone_ver2.0/" \end_inset . An example is given as number 13 on page 15 of that specification. \end_layout \begin_layout Subsection S-parameter measurement basics \end_layout \begin_layout Standard S-parameters allow a two-port description not just by permutating \begin_inset Formula $I_{1}$ \end_inset , \begin_inset Formula $U_{1}$ \end_inset , \begin_inset Formula $I_{2}$ \end_inset , \begin_inset Formula $U_{2}$ \end_inset , but using a superposition, leading to a power view of the port (We only look at two-ports here, because multi-ports are not (yet?) implemented.). \end_layout \begin_layout Standard You may start with the effective power, being negative or positive \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} P=u\cdot i\end{equation} \end_inset \end_layout \begin_layout Standard The value of \begin_inset Formula $P$ \end_inset may be the difference of two real numbers, with \begin_inset Formula $K$ \end_inset being another real number. \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} ui=P=a^{2}-b^{2}=(a+b)(a-b)=(a+b)(KK^{-1})(a-b)=\left\{ K(a+b)\right\} \left\{ K^{-1}(a-b)\right\} \end{equation} \end_inset \end_layout \begin_layout Standard Thus you get \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} K^{-1}u=a+b\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} Ki=a-b\end{equation} \end_inset \end_layout \begin_layout Standard and finally \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} a=\frac{u+K^{2}i}{2K}\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} b=\frac{u-K^{2}i}{2K}\end{equation} \end_inset \end_layout \begin_layout Standard By introducing the reference resistance \begin_inset Formula $Z_{0}:=K^{2}>0$ \end_inset we get finally the Heaviside transformation \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} a=\frac{u+Z_{0}i}{2\sqrt{Z_{0}}},\quad b=\frac{u-Z_{0}i}{2\sqrt{Z_{0}}}\end{equation} \end_inset \end_layout \begin_layout Standard In case of our two-port we subject our variables to a Heaviside transformation \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} a_{1}=\frac{U_{1}+Z_{0}I_{1}}{2\sqrt{Z_{0}}}\quad b_{1}=\frac{U_{1}-Z_{0}I_{1}}{2\sqrt{Z_{0}}}\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} a_{2}=\frac{U_{2}+Z_{0}I_{2}}{2\sqrt{Z_{0}}}\quad b_{2}=\frac{U_{2}-Z_{0}I_{2}}{2\sqrt{Z_{0}}}\end{equation} \end_inset \end_layout \begin_layout Standard The s-matrix for a two-port then is \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \left(\begin{array}{c} b_{1}\\ b_{2}\end{array}\right)=\left(\begin{array}{cc} s_{11} & s_{12}\\ s_{21} & s_{22}\end{array}\right)\left(\begin{array}{c} a_{1}\\ a_{2}\end{array}\right)\end{equation} \end_inset \end_layout \begin_layout Standard Two obtain \begin_inset Formula $s_{11}$ \end_inset we have to set \begin_inset Formula $a_{2}=0$ \end_inset . This is accomplished by loading the output port exactly with the reference resistance \begin_inset Formula $Z_{0},$ \end_inset which sinks a current \begin_inset Formula $I_{2}=-U_{2}/Z_{0}$ \end_inset from the port. \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} s_{11}=\left(\frac{b_{1}}{a_{1}}\right)_{a_{2}=0}\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} s_{11}=\frac{U_{1}-Z_{0}I_{1}}{U_{1}+Z_{0}I_{1}}\label{eq:}\end{equation} \end_inset \end_layout \begin_layout Standard Loading the input port from an ac source \begin_inset Formula $U_{0}$ \end_inset via a resistor with resistance value \begin_inset Formula $Z_{0}$ \end_inset , we obtain the relation \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} U_{0}=Z_{0}I_{1}+U_{1}\end{equation} \end_inset \end_layout \begin_layout Standard Entering this into \begin_inset CommandInset ref LatexCommand ref reference "eq:" \end_inset , we get \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} s_{11}=\frac{2U_{1}-U_{0}}{U_{0}}\label{eq:-2}\end{equation} \end_inset \end_layout \begin_layout Standard For \begin_inset Formula $s_{21}$ \end_inset we obtain similarly \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} s_{21}=\left(\frac{b_{2}}{a_{1}}\right)_{a_{2}=0}\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} s_{21}=\frac{U_{2}-Z_{0}I_{2}}{U_{1}+Z_{0}I_{1}}=\frac{2U_{2}}{U_{0}}\label{eq:-1}\end{equation} \end_inset \end_layout \begin_layout Standard Equations \begin_inset CommandInset ref LatexCommand ref reference "eq:-2" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "eq:-1" \end_inset now tell us how to measure \begin_inset Formula $s_{11}$ \end_inset and \begin_inset Formula $s_{21}$ \end_inset : Measure \begin_inset Formula $U_{1}$ \end_inset at the input port, multiply by 2 using an E source, subtracting \begin_inset Formula $U_{0}$ \end_inset which for simplicity is set to 1, and divide by \begin_inset Formula $U_{0}$ \end_inset . At the same time measure \begin_inset Formula $U_{2}$ \end_inset at the output port, multiply by 2 and divide by \begin_inset Formula $U_{0}$ \end_inset . Biasing and measuring is done by subcircuit S_PARAM. To obtain \begin_inset Formula $s_{22}$ \end_inset and \begin_inset Formula $s_{12}$ \end_inset , you have to exchange the input and output ports of your two-port and do the same measurement again. This is achieved by switching resistors from low ( \begin_inset Formula $1m\Omega$ \end_inset ) to high ( \begin_inset Formula $1T\Omega$ \end_inset \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none ) and thus switching the input and output ports. \end_layout \begin_layout Subsection Usage \end_layout \begin_layout Standard Copy and then edit s-param.cir. You will find this file in directory /examples/control_structs of the ngspice distribution. \end_layout \begin_layout Standard The reference resistance (often called characteristic impedance) for the measurements is added as a parameter \end_layout \begin_layout Standard \family typewriter .param Rbase=50 \end_layout \begin_layout Standard The bias voltages at the input and output ports of the circuit are set as parameters as well: \end_layout \begin_layout Standard \family typewriter .param Vbias_in=1 Vbias_out=2 \end_layout \begin_layout Standard Place your circuit at the appropriate place in the input file, e.g. replacing the existing example circuits. The input port of your circuit has two nodes \series bold in, 0 \series default . The output port has the two nodes \series bold out, 0 \series default . The bias voltages are connected to your circuit via the resistances of value \series bold Rbase \series default at the input and output respectively. This may be of importance for the operating point calculations if your circuit draws a large dc current. \end_layout \begin_layout Standard Now edit the ac commands (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Ac*:-Perform-an" \end_inset ) according to the circuit provided, e.g. \end_layout \begin_layout Standard \family typewriter ac lin 100 2.5MEG 250MEG $ use for Tschebyschef \end_layout \begin_layout Standard Be careful to keep both ac lines in the .control ... .endc section the same and only change both in equal measure! \end_layout \begin_layout Standard Select the plot commands (lin/log, or smith grid) or the 'write to file' commands (write, wrdata, or wrs2p) according to your needs. \end_layout \begin_layout Standard Run ngspice in interactive mode \end_layout \begin_layout Standard \family typewriter ngspice s-param.cir \end_layout \begin_layout Section MISCELLANEOUS (old stuff, has to be checked for relevance) \end_layout \begin_layout Standard C-shell type quoting with \begin_inset Quotes eld \end_inset and \begin_inset Quotes eld \end_inset , and backquote substitution may be used. Within single quotes, no further substitution (like history substitution) is done, and within double quotes, the words are kept together but further substitution is done. Any text between backquotes is replaced by the result of executing the text as a command to the shell. \end_layout \begin_layout Standard History substitutions, similar to C-shell history substitutions, are also available - see the C-shell manual page for all of the details. The characters ~, @{, and @} have the same effects as they do in the C-Shell, i.e., home directory and alternative expansion. It is possible to use the wildcard characters *, ?, [, and ] also, but only if you unset noglob first. This makes them rather useless for typing algebraic expressions, so you should set noglob again after you are done with wildcard expansion. Note that the pattern [^abc] matchs all characters except a, b, and c. \end_layout \begin_layout Standard If X is being used, the cursor may be positioned at any point on the screen when the window is up and characters typed at the keyboard are added to the window at that point. The window may then be sent to a printer using the xpr(1) program. \end_layout \begin_layout Section Bugs (old stuff, has to be checked for relevance) \end_layout \begin_layout Standard When defining aliases like alias pdb plot db( '!:1' - '!:2' ) you must be careful to quote the argument list substitutions in this manner. If you quote the whole argument it might not work properly. \end_layout \begin_layout Standard In a user-defined function, the arguments cannot be part of a name that uses the plot.vec syntax. For example: define check(v(1)) cos(tran1.v(1)) does not work. \end_layout \begin_layout Standard The @@name[param] notation might not work with trace, iplot, etc. yet. \end_layout \begin_layout Chapter Ngspice User Interfaces \end_layout \begin_layout Standard ngspice offers a variety of user interfaces. For an overview (several screen shots) please have a look at the \begin_inset CommandInset href LatexCommand href name "ngspice web page" target "http://sourceforge.net/project/screenshots.php?group_id=38962" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:MS-Windows" \end_inset MS Windows Graphical User Interface \end_layout \begin_layout Standard If compiled properly (e.g. using the --with-windows flag for ./configure under MINGW), ngspice for Windows offers a simple graphical user interface. In fact this interface does not offer much more for data input than a console would offer, e.g. command line inputs, command history and program text output. First of all it applies the Windows api for data plotting. If you run the sample input file given below, you will get an output as shown in fig. 16.1. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout *****Single NMOS Transistor For BSIM3V3.1 general purpose check (Id-Vd) *** \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** circuit description *** \end_layout \begin_layout Plain Layout m1 2 1 3 0 n1 L=0.6u W=10.0u \end_layout \begin_layout Plain Layout vgs 1 0 3.5 \end_layout \begin_layout Plain Layout vds 2 0 3.5 \end_layout \begin_layout Plain Layout vss 3 0 0 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .dc vds 0 3.5 0.05 vgs 0 3.5 0.5 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot vss#branch \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * UCB parameters BSIM3v3.2 \end_layout \begin_layout Plain Layout .include ../Exam_BSIM3/Modelcards/modelcard.nmos \end_layout \begin_layout Plain Layout .include ../Exam_BSIM3/Modelcards/modelcard.pmos \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The GUI consists of an I/O port (lower window) and a graphics window, created by the \family typewriter plot \family default command. \end_layout \begin_layout Standard \begin_inset Float figure placement H wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/ng-win-out.png width 70line% \end_inset \begin_inset Caption \begin_layout Plain Layout MS Windows GUI \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The output window displays messages issued by ngspice. You may scroll the window to get more of the text. The input box (white box) may be activated by a mouse click to accept any of the valid ngspice commends. The lower left output bar displays the actual input file. ngspice progress during setup and simulation is shown in the progress window ( \begin_inset Quotes eld \end_inset --ready-- \begin_inset Quotes erd \end_inset ). The Quit button allow to interrupt ngspice. If ngspice is actively simulating, due to using only a single thread, this interrupt has to wait until the window is accessible from within ngspice, e.g. during an update of the progress window. \end_layout \begin_layout Standard In the plot window there is the upper left button, which activated a drop down menu. You may select to print the plot window shown (a very simple printer interface, to be improved), set up any of the printers available on your computer, or issue a postscript file of the actual plot window, either black&white or colored. \end_layout \begin_layout Standard Instead of plotting with black background, you may set the background to any other color, preferably to \begin_inset Quotes eld \end_inset white \begin_inset Quotes erd \end_inset using the command shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Input file modification for white background: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout * white background \end_layout \begin_layout Plain Layout set color0=white \end_layout \begin_layout Plain Layout * black grid and text (only needed with X11, automatic with MS Win) \end_layout \begin_layout Plain Layout set color1=black \end_layout \begin_layout Plain Layout * wider grid and plot lines \end_layout \begin_layout Plain Layout set xbrushwidth=2 \end_layout \begin_layout Plain Layout plot vss#branch \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Float figure placement H wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/ng-win-out-white.png width 70line% \end_inset \begin_inset Caption \begin_layout Plain Layout Plotting with white background \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section MS Windows Console \end_layout \begin_layout Standard If the --with-windows flag for ./configure under MINGW is omitted or console_debu g or console_release is selected in the MS Visual Studio configuration manager, then ngspice will compile without any internal graphical input or output capability. This may be useful if you apply ngspice in a pipe inside the MSYS window, or use it being called from another program, and just generating output files from a given input. The \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Plot:-Plot-values" \end_inset ) command will not do and leads to an error message. \end_layout \begin_layout Standard You still may generate graphics output plots or prints by gnuplot ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Gnuplot:-Graphics-output" \end_inset ), if installed properly ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Gnuplot" \end_inset ), or by selecting a suitable printing option ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Printing-options" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:LINUX" \end_inset LINUX \end_layout \begin_layout Standard If ngspice is compiled with the --with-x flag for ./configure, the standard user interface is a console for input and the X11 graphics system for output with the interactive \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Plot:-Plot-values" \end_inset ) command. For more sophisticated input user interfaces please have a look at chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Integration-with-CAD" \end_inset . \end_layout \begin_layout Section CygWin \end_layout \begin_layout Standard The CygWin interface is similar to the LINUX interface ( \begin_inset CommandInset ref LatexCommand ref reference "sec:LINUX" \end_inset ), i.e. console input and X11 graphics output. To avoid the warning of a missing graphical user interface, you have to start the X11 window manager by issuing the commands \end_layout \begin_layout Standard \family typewriter $ export DISPLAY=:0.0 \end_layout \begin_layout Standard \family typewriter $ xwin -multiwindow -clipboard & \end_layout \begin_layout Standard inside of the CygWin window before starting ngspice. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Error-handling" \end_inset Error handling \end_layout \begin_layout Standard Error messages and error handling in ngspice have grown over the years, include a lot of \begin_inset Quotes eld \end_inset traditional \begin_inset Quotes erd \end_inset behaviour und thus are not very systematic and consistent. \end_layout \begin_layout Standard Error messages may occur with the token 'Error:'. Often the errors are non-recoverable and will lead to exiting ngspice with error code 1. Sometimes, however, you will get an error message, but ngspice will continue, and may either bail out later because the error has propagated into the simulation, sometimes ngspice will continue, deliver wrong results and exit with error code 0 (no error detected!). \end_layout \begin_layout Standard In addition ngspice may issue warning messages like 'Warning: ...'. These should cover recoverable errors only. \end_layout \begin_layout Standard So there is still work to be done to define a consistent error messaging, recovery or exiting. A first step is the user defiable variable \family sans \series bold strict_errorhandling \family default \series default . This variable may be set in files spinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) or .spiceinit ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ) to immediately stop ngspice, after an error is detected during parsing the circuit. An error message is sent, the ngspice exit code is 1. This behaviour deviates from traditional spice errror handling and thus is introduced as an option only. \end_layout \begin_layout Standard XSPICE error messages are explained in chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Error-Messages" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Printing-options" \end_inset Postscript printing options \end_layout \begin_layout Standard This info is compiled from Roger L. Traylor's \begin_inset CommandInset href LatexCommand href name "web page" target "http://web.engr.oregonstate.edu/~traylor/ece391/ngspice_printing" \end_inset . All the commands and variables you can set are described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset . The corresponding input file for the examples given below is listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:AC-coupled-transistor" \end_inset . Just add the .control section to this file and run in interactive mode by \end_layout \begin_layout Standard \family typewriter ngspice xspice_c1_print.cir \end_layout \begin_layout Standard ================================================================ \end_layout \begin_layout Standard One way is to setup your printing like this: \end_layout \begin_layout Standard \family typewriter .control \end_layout \begin_layout Standard \family typewriter set hcopydevtype=postscript \end_layout \begin_layout Standard \family typewriter op \end_layout \begin_layout Standard \family typewriter run \end_layout \begin_layout Standard \family typewriter plot vcc coll emit \end_layout \begin_layout Standard \family typewriter hardcopy temp.ps vcc coll emit \end_layout \begin_layout Standard \family typewriter .endc \end_layout \begin_layout Standard Then print the postscript file temp.ps to a postscript printer. \end_layout \begin_layout Standard ================================================================ \end_layout \begin_layout Standard You can add color traces to it if you wish: \end_layout \begin_layout Standard \family typewriter .control \end_layout \begin_layout Standard \family typewriter set hcopydevtype=postscript \end_layout \begin_layout Standard \family typewriter * allow color and set background color if set to value > 0 \end_layout \begin_layout Standard \family typewriter set hcopypscolor=1 \end_layout \begin_layout Standard \family typewriter *color0 is background color \end_layout \begin_layout Standard \family typewriter *color1 is the grid and text color \end_layout \begin_layout Standard \family typewriter *colors 2-15 are for the vectors \end_layout \begin_layout Standard \family typewriter set color0=rgb:f/f/f \end_layout \begin_layout Standard \family typewriter set color1=rgb:0/0/0 \end_layout \begin_layout Standard \family typewriter op \end_layout \begin_layout Standard \family typewriter run \end_layout \begin_layout Standard \family typewriter hardcopy temp.ps vcc coll emit \end_layout \begin_layout Standard \family typewriter .endc \end_layout \begin_layout Standard Then print the postscript file temp.ps to a postscript printer. \end_layout \begin_layout Standard ================================================================ \end_layout \begin_layout Standard You can also direct your output directly to a designated printer (not available in MS Windows): \end_layout \begin_layout Standard \family typewriter .control \end_layout \begin_layout Standard \family typewriter set hcopydevtype=postscript \end_layout \begin_layout Standard \family typewriter *send output to the printer kec3112-clr \end_layout \begin_layout Standard \family typewriter set hcopydev=kec3112-clr \end_layout \begin_layout Standard \family typewriter hardcopy out.tmp vcc coll emit \end_layout \begin_layout Standard ================================================================= \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Gnuplot" \end_inset Gnuplot \end_layout \begin_layout Standard Install GnuPlot (on LINUX available from the distribution, on Windows available \begin_inset CommandInset href LatexCommand href name "here" target "http://www.tatsuromatsuoka.com/gnuplot/Eng/winbin/" \end_inset ). On Windows expand the zip file to a directory of your choice, add the path /gnuplot/bin to the PATH variable, and go... The command to invoke Gnuplot ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Gnuplot:-Graphics-output" \end_inset ) is limited however to x/y plots (no polar etc.). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Integration-with-CAD" \end_inset Integration with CAD software and \begin_inset Quotes eld \end_inset third party \begin_inset Quotes erd \end_inset GUIs \end_layout \begin_layout Standard In this chapter you will find some links and comments on GUIs for ngspice offered from other projects and on the integration of ngspice into a circuit development flow. The data given rely mostly on information available from the web and thus is out of our control. It also may be far from complete. The GUIs KJWaves and GNUSpiceGUI help you to navigate the commands to need to perform your simulation. XCircuit and the GEDA tools gschem and gnetlist offer integrating schematic capture and simulation. \end_layout \begin_layout Subsection KJWaves \end_layout \begin_layout Standard KJWaves was written to be a cross-platform SPICE tool in pure Java. It aids in viewing, modifying, and simulating SPICE CIRCUIT files. Output from SPICE3 (ngspice) can be read and displayed. Resulting graphs may be printed and saved. The Java executable will run under LINUX and Windows (and maybe other OSs). The development site is available at \begin_inset CommandInset href LatexCommand href target "http://sourceforge.net/projects/kjwaves/" \end_inset . You may find the project home page at \begin_inset CommandInset href LatexCommand href target "http://www.comefly.us/" \end_inset . \end_layout \begin_layout Subsection GNU Spice GUI \end_layout \begin_layout Standard Another GUI, to be found at \begin_inset CommandInset href LatexCommand href target "http://sourceforge.net/projects/gspiceui/" \end_inset . \end_layout \begin_layout Subsection XCircuit \end_layout \begin_layout Standard CYGWIN and especially LINUX users may find \begin_inset CommandInset href LatexCommand href name "XCircuit" target "http://opencircuitdesign.com/xcircuit/" \end_inset valuable to establish a development flow including \begin_inset CommandInset href LatexCommand href name "schematic capture" target "http://opencircuitdesign.com/xcircuit/tutorial/tutorial2.html" \end_inset and circuit simulation. \end_layout \begin_layout Subsection GEDA \end_layout \begin_layout Standard The \begin_inset CommandInset href LatexCommand href name "gEDA project" target "http://www.gpleda.org/" \end_inset is developing a full GPL‘d suite and toolkit of Electronic Design Automation tools for use with a LINUX. Ngspice may be integrated into the development flow. Two web sites offer tutorials using gschem and gnetlist with ngspice: \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://geda.seul.org/wiki/geda:csygas" \end_inset \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://geda.seul.org/wiki/geda:ngspice_and_gschem" \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:TCLspice" \end_inset TCLspice \end_layout \begin_layout Standard Spice historically comes as a simulation engine with a Command Line Interface. Spice engine now can be used with friendly Graphical User Interfaces. Tclspice represent a third approach to interfacing ngspice simulation functiona lity. Tclspice is nothing more than a new way of compiling and using spice source code Spice is no longer considered as a standalone program but as a library invoked by a TCL interpreter. It either permits direct simulation in a friendly TCL shell (this is quite analogous to the command line interface of ngspice), or it permits the elaboration of more complex, more specific, or more user friendly simulation programs, by writing TCL scripts. \end_layout \begin_layout Section tclspice framework \end_layout \begin_layout Standard The technical difference between the ngspice CLI interface and tclspice is that the CLI interface is compiled as a standalone program, whereas tclspice is a shared object. Tclspice is designed to work with tools that expand the capabilities of ngspice: TCL for the scripting and programming language interface and BLT for data processing and display. This two tools give tclspice all of its relevance, with the insurance that the functionality is maintained by competent people. \end_layout \begin_layout Standard Making tclspice (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Compiling" \end_inset ) produces two files: libspice.so and pkgIndex.tcl. libspice.so is the executable binary that the TCL interpreter calls to handle spice commands. pkgIndex.tcl take place in the TCL directory tree, providing the spice package \begin_inset Foot status open \begin_layout Plain Layout package has to be understood as the TCL package \end_layout \end_inset to the TCL user. \end_layout \begin_layout Standard BLT is a TCL package. It is quite well documented. It permits to handle mathematical vector data structure for calculus and display, in a Tk interpreter like wish. \end_layout \begin_layout Section tclspice documentation \end_layout \begin_layout Standard A detailed documentation on \begin_inset CommandInset href LatexCommand href name "tclspice commands" target "http://tclspice.sourceforge.net/docs/tclspice_com.html" \end_inset is available on the \begin_inset CommandInset href LatexCommand href name "original tclspice web page" target "http://tclspice.sourceforge.net/" \end_inset . \end_layout \begin_layout Section spicetoblt \end_layout \begin_layout Standard Tclspice opens its doors to TCL and BLT with a single specific command spicetobl t. \end_layout \begin_layout Standard TCLspice gets its identity in the command spice::vectoblt This command copies data computed by the simulation engine into a tcl variable. vectoblt is composed of three words: vec, to and blt. Vec means spice vector data. To is the English preposition, and blt is a useful tcl package providing a vector data structure. Example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout blt::vector create Iex \end_layout \begin_layout Plain Layout spice::vectoblt Vex#branch Iex \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Here an empty blt vector is created. It is then filled with the vector representation of the current flowing out of source Vex. Vex#branch is native spices syntax. Iex is the name of the BLT vector. \end_layout \begin_layout Standard The reverse operation is handled by native spice commands, such as alter, let and set. \end_layout \begin_layout Section Running TCLspice \end_layout \begin_layout Standard TCLspice consists of a library or a package to include in your tcl console or script: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout load /somepath/libspice.so \end_layout \begin_layout Plain Layout package require spice \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Then you can execute any native spice command by preceding it with spice:: For example if you want to source the testCapa.cir netlist, type the following: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::source testCapa.cir \end_layout \begin_layout Plain Layout spice::spicetoblt example... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Plotting data is not a matter of spice, but of tcl. Once the data is stored in a blt vector, it can be plotted. Example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout blt::graph .cimvd -title "Cim = f(Vd)" \end_layout \begin_layout Plain Layout pack .cimvd \end_layout \begin_layout Plain Layout .cimvd element create line1 -xdata Vcmd -ydata Cim \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard With blt::graph a plotting structure is allocated in memory. With pack it is placed into the output window, and becomes visible. The last command, and not the least, plots the function Cim = f(Vcmd), where Cim and Vcmd are two BLT vectors. \end_layout \begin_layout Section examples \end_layout \begin_layout Subsection Active capacitor measurement \end_layout \begin_layout Standard In this crude implementation of a circuit described by Marc KODRNJA, in his PhD thesis that I found on the Internet. This simulation outputs a graph representing the virtual capacitance versus the command voltage. The function \begin_inset Formula $C=f(V)$ \end_inset is calculated point by point. For each control voltage value, the virtual capacitance is calculated with the voltage and intensity across the output port in a frequency simulation. A control value that should be as close to zero as possible is calculated to assess simulation success. \end_layout \begin_layout Subsubsection Invocation: \end_layout \begin_layout Standard This script can be invoked by typing wish testbench1.tcl \end_layout \begin_layout Subsubsection testbench1.tcl \end_layout \begin_layout Standard This line loads the simulator capabilities \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout package require spice \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is a comment (Quite useful if you intend to live with other Human beings) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout # Test of virtual capacitore circuit \end_layout \begin_layout Plain Layout # Vary the control voltage and log the resulting capacitance \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A good example of the calling of a spice command: precede it with spice:: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::source "testCapa.cir" \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This reminds that any regular TCL command is of course possible \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout set n 30 set dv 0.2 \end_layout \begin_layout Plain Layout set vmax [expr $dv/2] \end_layout \begin_layout Plain Layout set vmin [expr -1 * $dv/2] \end_layout \begin_layout Plain Layout set pas [expr $dv/ $n] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard BLT vector is the structure used to manipulate data. Instantiate the vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout blt::vector create Ctmp \end_layout \begin_layout Plain Layout blt::vector create Cim \end_layout \begin_layout Plain Layout blt::vector create check \end_layout \begin_layout Plain Layout blt::vector create Vcmd \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Data is, in my coding style, plotted into graph objects. Instantiate the graph \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout blt::graph .cimvd -title "Cim = f(Vd)" \end_layout \begin_layout Plain Layout blt::graph .checkvd -title "Rim = f(Vd)" \end_layout \begin_layout Plain Layout blt::vector create Iex \end_layout \begin_layout Plain Layout blt::vector create freq \end_layout \begin_layout Plain Layout blt::graph .freqanal -title "Analyse frequentielle" \end_layout \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # First simulation: A simple AC plot \end_layout \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout set v [expr {$vmin + $n * $pas / 4}] \end_layout \begin_layout Plain Layout spice::alter vd = $v \end_layout \begin_layout Plain Layout spice::op \end_layout \begin_layout Plain Layout spice::ac dec 10 100 100k \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Retrieve a the intensity of the current across Vex source \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::vectoblt {Vex#branch} Iex \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Retrieve the frequency at which the current have been assessed \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::vectoblt {frequency} freq \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Room the graph in the display window \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout pack .freqanal \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Plot the function Iex =f(V) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .freqanal element create line1 -xdata freq -ydata Iex \end_layout \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # Second simulation: Capacitance versus voltage control \end_layout \begin_layout Plain Layout # for {set i 0} {[expr $n - $i]} {incr i } \end_layout \begin_layout Plain Layout # { set v [expr {$vmin + $i * $pas}] \end_layout \begin_layout Plain Layout spice::alter vd = $v \end_layout \begin_layout Plain Layout spice::op spice::ac dec 10 100 100k \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Image capacitance is calculated by spice, instead of TCL there is no objective reason \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::let Cim = real(mean(Vex#branch/(2*Pi*i*frequency*(V(5)-V(6))))) \end_layout \begin_layout Plain Layout spice::vectoblt Cim Ctmp \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Build function vector point by point \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Cim append $Ctmp(0:end) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Build a control vector to check simulation success \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout spice::let err = real(mean(sqrt((Vex#branch- \end_layout \begin_layout Plain Layout (2*Pi*i*frequency*Cim*V(5)-V(6)))^2))) \end_layout \begin_layout Plain Layout spice::vectoblt err Ctmp check \end_layout \begin_layout Plain Layout append $Ctmp(0:end) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Build abscissa vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout FALTA ALGO... Vcmd append $v } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout pack .cimvd \end_layout \begin_layout Plain Layout .cimvd element create line1 -xdata Vcmd -ydata Cim \end_layout \begin_layout Plain Layout pack .checkvd \end_layout \begin_layout Plain Layout .checkvd element create line1 -xdata Vcmd -ydata check \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Optimization-of-a" \end_inset Optimization of a linearization circuit for a Thermistor \end_layout \begin_layout Standard This example is both the first and the last optimization program I wrote for an electronic circuit. It is far from perfect. \end_layout \begin_layout Standard The temperature response of a CTN is exponential. It is thus nonlinear. In a battery charger application floating voltage varies linearly with temperature. A TL431 voltage reference sees its output voltage controlled by two resistors (r10, r12) and a thermistor (r11). The simulation is run at a given temperature. The thermistor is modeled in spice by a regular resistor. Its resistivity is assessed by the TCL script. It is set with a spice::alter command before running the simulation. This script uses an iterative optimization approach to try to converge to a set of two resistor values which minimizes the error between the expected floating voltage and the TL431 output. \end_layout \begin_layout Subsubsection Invocation: \end_layout \begin_layout Standard This script can be executed by the user by simply executing the file in a terminal. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ./testbench3.tcl \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Two issues are important to point out \begin_inset Foot status open \begin_layout Plain Layout For those who are really interested in optimizing circuits: Some parameters are very important for quick and correct convergence. The optimizer walks step by step to a local minimum of the cost function you define. Starting from an initial vector YOU provide, it converges step by step. Consider trying another start vector if the result is not the one you expected. \end_layout \begin_layout Plain Layout The optimizer will carry on walking until it reaches a vector which resulting cost is smaller than the target cost YOU provide it. You will also provide a maximum iteration count in case the target can not be achieved. Balance your time, specifications, and every other parameters. For a balance between quick and accurate convergence adjust the "factor" variable, at the beginning of minimumSteepestDescent in the file differentiate.t cl. \end_layout \end_inset : \end_layout \begin_layout Itemize During optimization loop, graphical display of the current temperature response is not yet possible and I don't know why. Each time a simulation is performed, some memory is allocated for it. \end_layout \begin_layout Itemize The simulation result remains in memory until the libspice library is unloaded (typically: when the tcl script ends) or when a spice::clean command is performed. In this kind of simulation, not cleaning the memory space will freeze your computer and you'll have to restart it. Be aware of that. \end_layout \begin_layout Subsubsection testbench3.tcl \end_layout \begin_layout Standard This calls the shell sh who then runs wish with the file itself. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout #!/bin/sh \end_layout \begin_layout Plain Layout # WishFix \backslash \end_layout \begin_layout Plain Layout exec wish "$0" ${1+"$@"} \end_layout \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Regular package for simulation \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout package require spice \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Here the important line is source differentiate.tcl which contains optimization library \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout source differentiate.tcl \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Generates a temperature vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout proc temperatures_calc {temp_inf temp_sup points} { \end_layout \begin_layout Plain Layout set tstep [ expr " ( $temp_sup - $temp_inf ) / $points " ] \end_layout \begin_layout Plain Layout set t $temp_inf \end_layout \begin_layout Plain Layout set temperatures "" \end_layout \begin_layout Plain Layout for { set i 0 } { $i < $points } { incr i } { \end_layout \begin_layout Plain Layout set t [ expr { $t + $tstep } ] \end_layout \begin_layout Plain Layout set temperatures "$temperatures $t" \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout return $temperatures } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard generates thermistor resistivity as a vector, typically run: thermistance_calc res B [ temperatures_calc temp_inf temp_sup points ] \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout proc thermistance_calc { res B points } { \end_layout \begin_layout Plain Layout set tzero 273.15 \end_layout \begin_layout Plain Layout set tref 25 \end_layout \begin_layout Plain Layout set thermistance "" \end_layout \begin_layout Plain Layout foreach t $points { \end_layout \begin_layout Plain Layout set res_temp [expr " $res * exp ( $B * ( 1 / ($tzero + $t) - 1 / ( $tzero + $tref ) ) ) " ] \end_layout \begin_layout Plain Layout set thermistance "$thermistance $res_temp" \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout return $thermistance } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard generates the expected floating value as a vector, typically run: tref_calc res B [ temperatures_calc temp_inf temp_sup points ] \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout proc tref_calc { points } { \end_layout \begin_layout Plain Layout set tref "" \end_layout \begin_layout Plain Layout foreach t $points { \end_layout \begin_layout Plain Layout set tref " $tref [ expr " 6 * (2.275-0.005*($t - 20) ) - 9" ] " \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout return $tref } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In the optimization algorithm, this function computes the effective floating voltage at the given temperature. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout ### NOTE: \end_layout \begin_layout Plain Layout ### As component values are modified by a spice::alter Component values can be considered as global variable. \end_layout \begin_layout Plain Layout ### R10 and R12 are not passed to iteration function because it is expected to be correct, ie to have been modified soon before proc iteration { t } { set tzero 273.15 spice::alter r11 = [ thermistance_calc 10000 3900 $t ] \end_layout \begin_layout Plain Layout # Temperature simulation often crashes. Comment it out... \end_layout \begin_layout Plain Layout #spice::set temp = [ expr " $tzero + $t " ] \end_layout \begin_layout Plain Layout spice::op \end_layout \begin_layout Plain Layout spice::vectoblt vref_temp tref_tmp \end_layout \begin_layout Plain Layout ###NOTE: \end_layout \begin_layout Plain Layout ###As the library is executed once for the whole script execution, it is important to manage the memory \end_layout \begin_layout Plain Layout ###and regularly destroy unused data set. The data computed here will not be reused. Clean it \end_layout \begin_layout Plain Layout spice::destroy all return [ tref_tmp range 0 0 ] } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the cost function optimization algorithm will try to minimize. It is a square norm of the error across the temperature range [-25:75]°C (square norm: norme 2 in french I'm not sure of the English translation) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout proc cost { r10 r12 } { \end_layout \begin_layout Plain Layout tref_blt length 0 \end_layout \begin_layout Plain Layout spice::alter r10 = $r10 \end_layout \begin_layout Plain Layout spice::alter r12 = $r12 \end_layout \begin_layout Plain Layout foreach point [ temperatures_blt range 0 [ expr " [temperatures_blt length ] - 1" ] ] { \end_layout \begin_layout Plain Layout tref_blt append [ iteration $point ] \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout set result [ blt::vector expr " 1000 * sum(( tref_blt - expected_blt )^2 )" ] \end_layout \begin_layout Plain Layout disp_curve $r10 $r12 \end_layout \begin_layout Plain Layout return $result } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This function displays the expected and effective value of the voltage, as well as the r10 and r12 resistor values \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout proc disp_curve { r10 r12 } { .g configure -title "Valeurs optimales: R10 = $r10 R12 = $r12" } \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Main loop starts here \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # Optimization \end_layout \begin_layout Plain Layout # blt::vector create tref_tmp \end_layout \begin_layout Plain Layout blt::vector create tref_blt \end_layout \begin_layout Plain Layout blt::vector create expected_blt \end_layout \begin_layout Plain Layout blt::vector create temperatures_blt temperatures_blt \end_layout \begin_layout Plain Layout append [ temperatures_calc -25 75 30 ] expected_blt \end_layout \begin_layout Plain Layout append [ tref_calc [temperatures_blt range 0 [ expr " [ temperatures_blt length ] - 1" ] ] ] \end_layout \begin_layout Plain Layout blt::graph .g \end_layout \begin_layout Plain Layout pack .g -side top -fill both -expand true \end_layout \begin_layout Plain Layout .g element create real -pixels 4 -xdata temperatures_blt -ydata tref_blt \end_layout \begin_layout Plain Layout .g element create expected -fill red -pixels 0 -dashes dot -xdata temperatures_bl t -ydata expected_blt \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Source the circuit and optimize it, result is retrieved in r10r12 variable and affected to r10 and r12 with a regular expression. A bit ugly. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout spice::source FB14.cir \end_layout \begin_layout Plain Layout set r10r12 [ ::math::optimize::minimumSteepestDescent cost { 10000 10000 } 0.1 50 ] \end_layout \begin_layout Plain Layout regexp {([0-9.]*) ([0-9.]*)} $r10r12 r10r12 r10 r12 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Outputs optimization result \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout # \end_layout \begin_layout Plain Layout # Results \end_layout \begin_layout Plain Layout # spice::alter r10 = $r10 \end_layout \begin_layout Plain Layout spice::alter r12 = $r12 \end_layout \begin_layout Plain Layout foreach point [ temperatures_blt range 0 [ expr " [temperatures_blt length ] - 1" ] ] { \end_layout \begin_layout Plain Layout tref_blt append [ iteration $point ] \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout disp_curve $r10 $r12 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Progressive display \end_layout \begin_layout Standard This example is quite simple but it is very interesting. It displays a transient simulation result on the fly. You may now be familiar with most of the lines of this script. It uses the ability of BLT objects to automatically update. When the vector data is modified, the strip-chart display is modified according ly. \end_layout \begin_layout Subsubsection testbench2.tcl \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout #!/bin/sh \end_layout \begin_layout Plain Layout # WishFix \backslash \end_layout \begin_layout Plain Layout exec wish -f "$0" ${1+"$@"} \end_layout \begin_layout Plain Layout ### \end_layout \begin_layout Plain Layout package require BLT package require spice \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard this avoids to type blt:: before the blt class commands \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout namespace import blt::* \end_layout \begin_layout Plain Layout wm title . "Vector Test script" \end_layout \begin_layout Plain Layout wm geometry . 800x600+40+40 pack propagate . false \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A strip chart with labels but without data is created and displayed (packed) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout stripchart .chart \end_layout \begin_layout Plain Layout pack .chart -side top -fill both -expand true \end_layout \begin_layout Plain Layout .chart axis configure x -title "Time" spice::source example.cir \end_layout \begin_layout Plain Layout spice::bg \end_layout \begin_layout Plain Layout run after 1000 vector \end_layout \begin_layout Plain Layout create a0 vector \end_layout \begin_layout Plain Layout create b0 vectorry \end_layout \begin_layout Plain Layout create a1 vector \end_layout \begin_layout Plain Layout create b1 vector \end_layout \begin_layout Plain Layout create stime \end_layout \begin_layout Plain Layout proc bltupdate {} { \end_layout \begin_layout Plain Layout puts [spice::spice_data] \end_layout \begin_layout Plain Layout spice::spicetoblt a0 a0 \end_layout \begin_layout Plain Layout spice::spicetoblt b0 b0 \end_layout \begin_layout Plain Layout spice::spicetoblt a1 a1 \end_layout \begin_layout Plain Layout spice::spicetoblt b1 b1 \end_layout \begin_layout Plain Layout spice::spicetoblt time stime \end_layout \begin_layout Plain Layout after 100 bltupdate } \end_layout \begin_layout Plain Layout bltupdate .chart element create a0 -color red -xdata stime -ydata a0 \end_layout \begin_layout Plain Layout .chart element create b0 -color blue -xdata stime -ydata b0 \end_layout \begin_layout Plain Layout .chart element create a1 -color yellow -xdata stime -ydata a1 \end_layout \begin_layout Plain Layout .chart element create b1 -color black -xdata stime -ydata b1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Compiling" \end_inset Compiling \end_layout \begin_layout Subsection LINUX \end_layout \begin_layout Standard Get tcl8.4 from your distribution. You will need the blt plotting package (compatible to the old tcl 8.4 only) from \begin_inset CommandInset href LatexCommand href name "here" target "http://sourceforge.net/projects/blt/files/BLT/BLT%202.4z/" \end_inset . See also the actual \begin_inset CommandInset href LatexCommand href name "blt wiki" target "http://wiki.tcl.tk/199" \end_inset . \end_layout \begin_layout LyX-Code ./configure --with-tcl .. \end_layout \begin_layout LyX-Code make \end_layout \begin_layout LyX-Code sudo make install \end_layout \begin_layout Subsection MS Windows \end_layout \begin_layout Standard Can be done, but is tedious (Windows XP, 32 bit). Not tested on Windows 7. \end_layout \begin_layout Standard T.b.d. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Example-Circuits" \end_inset Example Circuits \end_layout \begin_layout Standard This section starts with an ngspice example to walk you through the basic features of ngspice using its command line user interface. The operation of ngspice will be illustrated through several examples (chapters 20.1 to 20.7). \end_layout \begin_layout Standard The first example uses the simple one-transistor amplifier circuit illustrated in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Transistor-Amplifier-Simulation" \end_inset . \begin_inset Float figure wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Example_Circuit_C1.gif width 80line% scaleBeforeRotation \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Transistor-Amplifier-Simulation" \end_inset Transistor Amplifier Simulation Example \end_layout \end_inset \end_layout \end_inset This circuit is constructed entirely with ngspice compatible devices and is used to introduce basic concepts, including: \end_layout \begin_layout Itemize Invoking the simulator: \end_layout \begin_layout Itemize Running simulations in different analysis modes \end_layout \begin_layout Itemize Printing and plotting analog results \end_layout \begin_layout Itemize Examining status, including execution time and memory usage \end_layout \begin_layout Itemize Exiting the simulator \end_layout \begin_layout Standard The remainder of the section (from chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Differential-Pair" \end_inset onwards) lists several circuits, which have been accompanying any ngspice distribution, and may be regarded as the \begin_inset Quotes eld \end_inset classical \begin_inset Quotes erd \end_inset SPICE circuits. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:AC-coupled-transistor" \end_inset AC coupled transistor amplifier \end_layout \begin_layout Standard The circuit shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Transistor-Amplifier-Simulation" \end_inset is a simple one-transistor amplifier. The input signal is amplified with a gain of approximately -(Rc/Re) = -(3.9K/1K) = -3.9. The circuit description file for this example is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout A Berkeley SPICE3 compatible circuit \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * This circuit contains only Berkeley SPICE3 components. \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * The circuit is an AC coupled transistor amplifier with \end_layout \begin_layout Plain Layout * a sinewave input at node "1", a gain of approximately -3.9, \end_layout \begin_layout Plain Layout * and output on node "coll". \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .tran 1e-5 2e-3 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout vcc vcc 0 12.0 \end_layout \begin_layout Plain Layout vin 1 0 0.0 ac 1.0 sin(0 1 1k) \end_layout \begin_layout Plain Layout ccouple 1 base 10uF \end_layout \begin_layout Plain Layout rbias1 vcc base 100k \end_layout \begin_layout Plain Layout rbias2 base 0 24k \end_layout \begin_layout Plain Layout q1 coll base emit generic \end_layout \begin_layout Plain Layout rcollector vcc coll 3.9k \end_layout \begin_layout Plain Layout remitter emit 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .model generic npn \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard To simulate this circuit, move into a directory under your user account and copy the file \family typewriter xspice_c1.cir \family default from directory \family typewriter /examples/xspice/ \family default . \end_layout \begin_layout LyX-Code $ cp /examples/xspice/xspice_c1.cir xspice_c1.cir \end_layout \begin_layout Standard Now invoke the simulator on this circuit as follows: \end_layout \begin_layout LyX-Code $ ngspice xspice_c1.cir \end_layout \begin_layout Standard After a few moments, you should see the ngspice prompt: \end_layout \begin_layout LyX-Code ngspice 1 -> \end_layout \begin_layout Standard At this point, ngspice has read-in the circuit description and checked it for errors. If any errors had been encountered, messages describing them would have been output to your terminal. Since no messages were printed for this circuit, the syntax of the circuit description was correct. \end_layout \begin_layout Standard To see the circuit description read by the simulator you can issue the following command: \end_layout \begin_layout LyX-Code ngspice 1 -> listing \end_layout \begin_layout Standard The simulator shows you the circuit description currently in memory: \end_layout \begin_layout LyX-Code a berkeley spice3 compatible circuit \end_layout \begin_layout LyX-Code 1 : a berkeley spice3 compatible circuit \end_layout \begin_layout LyX-Code 2 : .global gnd \end_layout \begin_layout LyX-Code 10 : .tran 1e-5 2e-3 \end_layout \begin_layout LyX-Code 12 : vcc vcc 0 12.0 \end_layout \begin_layout LyX-Code 13 : vin 1 0 0.0 ac 1.0 sin(0 1 1k) \end_layout \begin_layout LyX-Code 14 : ccouple 1 base 10uf \end_layout \begin_layout LyX-Code 15 : rbias1 vcc base 100k \end_layout \begin_layout LyX-Code 16 : rbias2 base 0 24k \end_layout \begin_layout LyX-Code 17 : q1 coll base emit generic \end_layout \begin_layout LyX-Code 18 : rcollector vcc coll 3.9k \end_layout \begin_layout LyX-Code 19 : remitter emit 0 1k \end_layout \begin_layout LyX-Code 21 : .model generic npn \end_layout \begin_layout LyX-Code 24 : .end \end_layout \begin_layout Standard The title of this circuit is \begin_inset Quotes eld \end_inset A Berkeley SPICE3 compatible circuit \begin_inset Quotes erd \end_inset . The circuit description contains a transient analysis control command \family typewriter .TRAN 1E-5 2E-3 \family default requesting a total simulated time of 2ms with a maximum time-step of 10us. The remainder of the lines in the circuit description describe the circuit of Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Transistor-Amplifier-Simulation" \end_inset . \end_layout \begin_layout Standard Now, execute the simulation by entering the \begin_inset Quotes eld \end_inset run \begin_inset Quotes erd \end_inset command: \end_layout \begin_layout LyX-Code ngspice 1 -> run \end_layout \begin_layout Standard The simulator will run the simulation and when execution is completed, will return with the ngspice prompt. When the prompt returns, issue the rusage command again to see how much time and memory has been used now. \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard To examine the results of this transient analysis, we can use the \begin_inset Quotes eld \end_inset plot \begin_inset Quotes erd \end_inset command. First we will plot the nodes labeled \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset base \begin_inset Quotes erd \end_inset . \end_layout \begin_layout LyX-Code ngspice 2 -> plot v(1) base \end_layout \begin_layout Standard The simulator responds by displaying an X Window System plot similar to that shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:node-1-and" \end_inset . \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/C4.gif scale 50 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:node-1-and" \end_inset node 1 and node 'base' versus time \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard Notice that we have named one of the nodes in the \emph on circuit description \emph default with a number ( \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset ), while the others are words ( \begin_inset Quotes eld \end_inset base \begin_inset Quotes erd \end_inset ). This was done to illustrate ngspice's special requirements for plotting nodes labeled with numbers. Numeric labels are allowed in ngspice for backwards compatibility with SPICE2. However, they require special treatment in some commands such as \begin_inset Quotes eld \end_inset plot \begin_inset Quotes erd \end_inset . The \begin_inset Quotes eld \end_inset plot \begin_inset Quotes erd \end_inset command is designed to allow expressions in its argument list in addition to names of results data to be plotted. For example, the expression \family typewriter plot (base - 1) \family default would plot the result of subtracting 1 from the value of node \begin_inset Quotes eld \end_inset base \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard If we had desired to plot the difference between the voltage at node \begin_inset Quotes eld \end_inset base \begin_inset Quotes erd \end_inset and node \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset , we would need to enclose the node name \begin_inset Quotes eld \end_inset 1 \begin_inset Quotes erd \end_inset in the construction v( ) producing a command such as \family typewriter plot (base - v(1)) \family default . \end_layout \begin_layout Standard Now, issue the following command to examine the voltages on two of the internal nodes of the transistor amplifier circuit: \end_layout \begin_layout LyX-Code ngspice 3 -> plot vcc coll emit \end_layout \begin_layout Standard The plot shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:VCC,-Collector-and" \end_inset should appear. Notice in the circuit description that the power supply voltage source and the node it is connected to both have the name "vcc". The plot command above has plotted the node voltage "vcc". However, it is also possible to plot branch currents through voltage sources in a circuit. ngspice always adds the special suffix "#branch" to voltage source names. Hence, to plot the current into the voltage source named "vcc", we would use a command such as plot vcc#branch. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/C5.gif scale 50 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:VCC,-Collector-and" \end_inset VCC, Collector and Emitter Voltages \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard Now let's run a simple DC simulation of this circuit and examine the bias voltages with the "print" command. One way to do this is to quit the simulator using the "quit" command, edit the input file to change the ".tran" line to ".op" (for 'operating point analysis'), re-invoke the simulator, and then issue the "run" command. However, ngspice allows analysis mode changes directly from the ngspice prompt. All that is required is to enter the control line, e.g. op (without the leading "."). ngspice will interpret the information on the line and start the new analysis run immediately, without the need to enter a new "run" command. \end_layout \begin_layout Standard To run the DC simulation of the transistor amplifier, issue the following command: \end_layout \begin_layout LyX-Code ngspice 4 -> op \end_layout \begin_layout Standard After a moment the ngspice prompt returns. Now issue the "print" command to examine the emitter, base, and collector DC bias voltages. \end_layout \begin_layout LyX-Code ngspice 5 -> print emit base coll \end_layout \begin_layout Standard ngspice responds with: \end_layout \begin_layout LyX-Code emit = 1.293993e+00 base = 2.074610e+00 coll = 7.003393e+00 \end_layout \begin_layout Standard To run an AC analysis, enter the following command: \end_layout \begin_layout LyX-Code ngspice 6 -> ac dec 10 0.01 100 \end_layout \begin_layout Standard This command runs a small-signal swept AC analysis of the circuit to compute the magnitude and phase responses. In this example, the sweep is logarithmic with "decade" scaling, 10 points per decade, and lower and upper frequencies of 0.01 Hz and 100 Hz. Since the command sweeps through a range of frequencies, the results are vectors of values and are examined with the plot command. Issue to the following command to plot the response curve at node "coll": \end_layout \begin_layout LyX-Code ngspice 7 -> plot coll \end_layout \begin_layout Standard This plot shows the AC gain from input to the collector. (Note that our input source in the circuit description "vin" contained parameters of the form "AC 1.0" designating that a unit-amplitude AC signal was applied at this point.) \end_layout \begin_layout Standard To produce a more traditional "Bode" gain phase plot with logarithmic scaling on the frequency axis, we use the expression capability of the "plot" command and the built-in Nutmeg functions db( ), log( ), and ph( ) together with the vs keyword: \end_layout \begin_layout LyX-Code ngspice 8 -> plot db(coll) ph(coll) vs log(frequency) \end_layout \begin_layout Standard The last analysis supported by ngspice is a swept DC analysis. To perform this analysis, issue the following command: \end_layout \begin_layout LyX-Code ngspice 9 -> dc vcc 0 15 0.1 \end_layout \begin_layout Standard This command sweeps the supply voltage "vcc" from 0 to 15 volts in 0.1 volt increments. To plot the results, issue the command: \end_layout \begin_layout LyX-Code ngspice 10 -> plot emit base coll \end_layout \begin_layout Standard Finally, to exit the simulator, use the "quit" command, and you will be returned to the operating system prompt. \end_layout \begin_layout LyX-Code ngspice 11 -> quit \end_layout \begin_layout Standard So long. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Differential-Pair" \end_inset Differential Pair \end_layout \begin_layout Standard The following deck determines the dc operating point of a simple differential pair. In addition, the ac small-signal response is computed over the frequency range 1Hz to 100MEGHz. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout SIMPLE DIFFERENTIAL PAIR \end_layout \begin_layout Plain Layout VCC 7 0 12 \end_layout \begin_layout Plain Layout VEE 8 0 -12 \end_layout \begin_layout Plain Layout VIN 1 0 AC 1 \end_layout \begin_layout Plain Layout RS1 1 2 1K \end_layout \begin_layout Plain Layout RS2 6 0 1K \end_layout \begin_layout Plain Layout Q1 3 2 4 MOD1 \end_layout \begin_layout Plain Layout Q2 5 6 4 MOD1 \end_layout \begin_layout Plain Layout RC1 7 3 10K \end_layout \begin_layout Plain Layout RC2 7 5 10K \end_layout \begin_layout Plain Layout RE 4 8 10K \end_layout \begin_layout Plain Layout .MODEL MOD1 NPN BF=50 VAF=50 IS=1.E-12 RB=100 CJC=.5PF TF=.6NS \end_layout \begin_layout Plain Layout .TF V(5) VIN \end_layout \begin_layout Plain Layout .AC DEC 10 1 100MEG \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:MOSFET-Characterization" \end_inset MOSFET Characterization \end_layout \begin_layout Standard The following deck computes the output characteristics of a MOSFET device over the range 0-10V for VDS and 0-5V for VGS. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout MOS OUTPUT CHARACTERISTICS \end_layout \begin_layout Plain Layout .OPTIONS NODE NOPAGE \end_layout \begin_layout Plain Layout VDS 3 0 \end_layout \begin_layout Plain Layout VGS 2 0 \end_layout \begin_layout Plain Layout M1 1 2 0 0 MOD1 L=4U W=6U AD=10P AS=10P \end_layout \begin_layout Plain Layout * VIDS MEASURES ID, WE COULD HAVE USED VDS, BUT ID WOULD BE NEGATIVE \end_layout \begin_layout Plain Layout VIDS 3 1 \end_layout \begin_layout Plain Layout .MODEL MOD1 NMOS VTO=-2 NSUB=1.0E15 UO=550 \end_layout \begin_layout Plain Layout .DC VDS 0 10 .5 VGS 0 5 1 \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section RTL Inverter \end_layout \begin_layout Standard The following deck determines the dc transfer curve and the transient pulse response of a simple RTL inverter. The input is a pulse from 0 to 5 Volts with delay, rise, and fall times of 2ns and a pulse width of 30ns. The transient interval is 0 to 100ns, with printing to be done every nanosecond. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout SIMPLE RTL INVERTER \end_layout \begin_layout Plain Layout VCC 4 0 5 \end_layout \begin_layout Plain Layout VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS \end_layout \begin_layout Plain Layout RB 1 2 10K \end_layout \begin_layout Plain Layout Q1 3 2 0 Q1 \end_layout \begin_layout Plain Layout RC 3 4 1K \end_layout \begin_layout Plain Layout .MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF \end_layout \begin_layout Plain Layout .DC VIN 0 5 0.1 \end_layout \begin_layout Plain Layout .TRAN 1NS 100NS \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section Four-Bit Binary Adder (Bipolar) \end_layout \begin_layout Standard The following deck simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout *** SUBCIRCUIT DEFINITIONS \end_layout \begin_layout Plain Layout .SUBCKT NAND 1 2 3 4 \end_layout \begin_layout Plain Layout * NODES: INPUT(2), OUTPUT, VCC \end_layout \begin_layout Plain Layout Q1 9 5 1 QMOD \end_layout \begin_layout Plain Layout D1CLAMP 0 1 DMOD \end_layout \begin_layout Plain Layout Q2 9 5 2 QMOD \end_layout \begin_layout Plain Layout D2CLAMP 0 2 DMOD \end_layout \begin_layout Plain Layout RB 4 5 4K \end_layout \begin_layout Plain Layout R1 4 6 1.6K \end_layout \begin_layout Plain Layout Q3 6 9 8 QMOD \end_layout \begin_layout Plain Layout R2 8 0 1K \end_layout \begin_layout Plain Layout RC 4 7 130 \end_layout \begin_layout Plain Layout Q4 7 6 10 QMOD \end_layout \begin_layout Plain Layout DVBEDROP 10 3 DMOD \end_layout \begin_layout Plain Layout Q5 3 8 0 QMOD \end_layout \begin_layout Plain Layout .ENDS NAND \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Continue 4 Bit adder : \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SUBCKT ONEBIT 1 2 3 4 5 6 \end_layout \begin_layout Plain Layout * NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC \end_layout \begin_layout Plain Layout X1 1 2 7 6 NAND \end_layout \begin_layout Plain Layout X2 1 7 8 6 NAND \end_layout \begin_layout Plain Layout X3 2 7 9 6 NAND \end_layout \begin_layout Plain Layout X4 8 9 10 6 NAND \end_layout \begin_layout Plain Layout X5 3 10 11 6 NAND \end_layout \begin_layout Plain Layout X6 3 11 12 6 NAND \end_layout \begin_layout Plain Layout X7 10 11 13 6 NAND \end_layout \begin_layout Plain Layout X8 12 13 4 6 NAND \end_layout \begin_layout Plain Layout X9 11 7 5 6 NAND \end_layout \begin_layout Plain Layout .ENDS ONEBIT \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 \end_layout \begin_layout Plain Layout * NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, \end_layout \begin_layout Plain Layout * CARRY-IN, CARRY-OUT, VCC \end_layout \begin_layout Plain Layout X1 1 2 7 5 10 9 ONEBIT \end_layout \begin_layout Plain Layout X2 3 4 10 6 8 9 ONEBIT \end_layout \begin_layout Plain Layout .ENDS TWOBIT \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 \end_layout \begin_layout Plain Layout * NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), \end_layout \begin_layout Plain Layout * OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC \end_layout \begin_layout Plain Layout X1 1 2 3 4 9 10 13 16 15 TWOBIT \end_layout \begin_layout Plain Layout X2 5 6 7 8 11 12 16 14 15 TWOBIT \end_layout \begin_layout Plain Layout .ENDS FOURBIT \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout *** DEFINE NOMINAL CIRCUIT \end_layout \begin_layout Plain Layout .MODEL DMOD D \end_layout \begin_layout Plain Layout .MODEL QMOD NPN(BF=75 RB=100 CJE=1PF CJC=3PF) \end_layout \begin_layout Plain Layout VCC 99 0 DC 5V \end_layout \begin_layout Plain Layout VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) \end_layout \begin_layout Plain Layout VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) \end_layout \begin_layout Plain Layout VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) \end_layout \begin_layout Plain Layout VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) \end_layout \begin_layout Plain Layout VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) \end_layout \begin_layout Plain Layout VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) \end_layout \begin_layout Plain Layout VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) \end_layout \begin_layout Plain Layout VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) \end_layout \begin_layout Plain Layout X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT \end_layout \begin_layout Plain Layout RBIT0 9 0 1K \end_layout \begin_layout Plain Layout RBIT1 10 0 1K \end_layout \begin_layout Plain Layout RBIT2 11 0 1K \end_layout \begin_layout Plain Layout RBIT3 12 0 1K \end_layout \begin_layout Plain Layout RCOUT 13 0 1K \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout *** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN) \end_layout \begin_layout Plain Layout .TRAN 1NS 6400NS \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:MOS-Four-Bit" \end_inset Four-Bit Binary Adder (MOS) \end_layout \begin_layout Standard The following deck simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout *** SUBCIRCUIT DEFINITIONS \end_layout \begin_layout Plain Layout .SUBCKT NAND in1 in2 out VDD \end_layout \begin_layout Plain Layout * NODES: INPUT(2), OUTPUT, VCC \end_layout \begin_layout Plain Layout M1 out in2 Vdd Vdd p1 W=3u L=1u \end_layout \begin_layout Plain Layout M2 net.1 in2 0 0 n1 W=3u L=2u \end_layout \begin_layout Plain Layout M3 out in1 Vdd Vdd p1 W=3u L=1u \end_layout \begin_layout Plain Layout M4 out in1 net.1 0 n1 W=3u L=2u \end_layout \begin_layout Plain Layout .ENDS NAND \end_layout \begin_layout Plain Layout .SUBCKT ONEBIT 1 2 3 4 5 6 AND \end_layout \begin_layout Plain Layout X2 1 7 8 6 NAND \end_layout \begin_layout Plain Layout X3 2 7 9 6 NAND \end_layout \begin_layout Plain Layout X4 8 9 10 6 NAND \end_layout \begin_layout Plain Layout X5 3 10 11 6 NAND \end_layout \begin_layout Plain Layout X6 3 11 12 6 NAND \end_layout \begin_layout Plain Layout X7 10 11 13 6 NAND \end_layout \begin_layout Plain Layout X8 12 13 4 6 NAND \end_layout \begin_layout Plain Layout X9 11 7 5 6 NAND \end_layout \begin_layout Plain Layout .ENDS ONEBIT \end_layout \begin_layout Plain Layout .SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 \end_layout \begin_layout Plain Layout * NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, \end_layout \begin_layout Plain Layout * CARRY-IN, CARRY-OUT, VCC \end_layout \begin_layout Plain Layout X1 1 2 7 5 10 9 ONEBIT \end_layout \begin_layout Plain Layout X2 3 4 10 6 8 9 ONEBIT \end_layout \begin_layout Plain Layout .ENDS TWOBIT \end_layout \begin_layout Plain Layout .SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 \end_layout \begin_layout Plain Layout *NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), \end_layout \begin_layout Plain Layout * OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, \end_layout \begin_layout Plain Layout * CARRY-OUT, VCC \end_layout \begin_layout Plain Layout X1 1 2 3 4 9 10 13 16 15 TWOBIT \end_layout \begin_layout Plain Layout X2 5 6 7 8 11 12 16 14 15 TWOBIT \end_layout \begin_layout Plain Layout .ENDS FOURBIT \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Continue 4 Bit adder MOS: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout *** DEFINE NOMINAL CIRCUIT \end_layout \begin_layout Plain Layout VCC 99 0 DC 3.3V \end_layout \begin_layout Plain Layout VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) \end_layout \begin_layout Plain Layout VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) \end_layout \begin_layout Plain Layout VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) \end_layout \begin_layout Plain Layout VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) \end_layout \begin_layout Plain Layout VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) \end_layout \begin_layout Plain Layout VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) \end_layout \begin_layout Plain Layout VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) \end_layout \begin_layout Plain Layout VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) \end_layout \begin_layout Plain Layout X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT \end_layout \begin_layout Plain Layout .option acct \end_layout \begin_layout Plain Layout .TRAN 1NS 1000NS \end_layout \begin_layout Plain Layout *.save VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B \end_layout \begin_layout Plain Layout *.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .include ./Modelcards/modelcard.nmos \end_layout \begin_layout Plain Layout .include ./Modelcards/modelcard.pmos \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Transmission-Line-Inverter" \end_inset Transmission-Line Inverter \end_layout \begin_layout Standard The following deck simulates a transmission-line inverter. Two transmission-line elements are required since two propagation modes are excited. In the case of a coaxial line, the first line (T1) models the inner conductor with respect to the shield, and the second line (T2) models the shield with respect to the outside world. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout TRANSMISSION-LINE INVERTER \end_layout \begin_layout Plain Layout V1 1 0 PULSE(0 1 0 0.1N) \end_layout \begin_layout Plain Layout R1 1 2 50 \end_layout \begin_layout Plain Layout X1 2 0 0 4 TLINE \end_layout \begin_layout Plain Layout R2 4 0 50 \end_layout \begin_layout Plain Layout .SUBCKT TLINE 1 2 3 4 \end_layout \begin_layout Plain Layout T1 1 2 3 4 Z0=50 TD=1.5NS \end_layout \begin_layout Plain Layout T2 2 0 4 0 Z0=100 TD=1NS \end_layout \begin_layout Plain Layout .ENDS TLINE \end_layout \begin_layout Plain Layout .TRAN 0.1NS 20NS \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Statistical-circuit-analysis" \end_inset Statistical circuit analysis \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard Real circuits do not operate in a world with fixed values of device parameters, power supplies and environmental data. Even if a ngspice output offers 5 digits or more of precision, this should not mislead you thinking that your circuits will behave exactly the same. All physical parameters influencing a circuit (e.g. MOS Source/drain resistance, threshold voltage, transconductance) are distribut ed parameters, often following a Gaussian distribution with a mean value \begin_inset Formula $\mu$ \end_inset and a standard deviation \begin_inset Formula $\sigma$ \end_inset . \end_layout \begin_layout Standard To obtain circuits operating reliably under varying parameters, it might be necessary to simulate them taking certain parameter spreads into account. ngspice offers several methods supporting this task. A powerful random number generator is working in the background. Its seed value is derived from the process id upon start-up of ngspice. If you need reproducible random numbers, you may start ngspice setting the command \family typewriter \series bold set rndseed= \family default \series default into spinit or .spiceinit. The following three chapters offer a short introduction to the statistical methods available in ngspice. The diversity of approaches stems from historical reasons, and from some efforts to make ngspice compatible to other simulators. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Using-random-param(eters)" \end_inset Using random param(eters) \end_layout \begin_layout Standard The ngspice frontend (with its 'numparam' parser) contains the .param (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:.param-line" \end_inset ) and .func (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:func" \end_inset ) commands. Among the built-in functions supported (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Syntax-of-expressions" \end_inset ) you will find the following statistical functions: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Built-in function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none gauss(nom, rvar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation rvar (relative to nominal), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none agauss(nom, avar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation avar (absolute), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none unif(nom, rvar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none nominal value plus relative variation (to nominal) uniformly distributed between +/-rvar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none aunif(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none nominal value plus absolute variation uniformly distributed between +/-avar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none limit(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none nominal value +/-avar, depending on random number in [-1, 1[ being > 0 or < 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The frontend parser evaluates all \family typewriter .param \family default or \family typewriter .func \family default statements upon start-up of ngspice, before the circuit is evaluated. The parameters aga, aga2, lim obtain their numerical values once. If the random function appears in a device card (e.g. \family typewriter v11 11 0 'agauss(1,2,3)' \family default ), a new random number is generated. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Random number example using parameters: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout * random number tests \end_layout \begin_layout Plain Layout .param aga = agauss(1,2,3) \end_layout \begin_layout Plain Layout .param aga2='2*aga' \end_layout \begin_layout Plain Layout .param lim=limit(0,1.2) \end_layout \begin_layout Plain Layout .func rgauss(a,b,c) '5*agauss(a,b,c)' \end_layout \begin_layout Plain Layout * always same value as defined above \end_layout \begin_layout Plain Layout v1 1 0 'lim' \end_layout \begin_layout Plain Layout v2 2 0 'lim' \end_layout \begin_layout Plain Layout * may be a different value \end_layout \begin_layout Plain Layout v3 3 0 'limit(0,1.2)' \end_layout \begin_layout Plain Layout * always new random values \end_layout \begin_layout Plain Layout v11 11 0 'agauss(1,2,3)' \end_layout \begin_layout Plain Layout v12 12 0 'agauss(1,2,3)' \end_layout \begin_layout Plain Layout v13 13 0 'agauss(1,2,3)' \end_layout \begin_layout Plain Layout * same value as defined above \end_layout \begin_layout Plain Layout v14 14 0 'aga' \end_layout \begin_layout Plain Layout v15 15 0 'aga' \end_layout \begin_layout Plain Layout v16 16 0 'aga2' \end_layout \begin_layout Plain Layout * using .func, new random values \end_layout \begin_layout Plain Layout v17 17 0 'rgauss(0,2,3)' \end_layout \begin_layout Plain Layout v18 18 0 'rgauss(0,2,3)' \end_layout \begin_layout Plain Layout .op \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout print v(1) v(2) v(3) v(11) v(12) v(13) \end_layout \begin_layout Plain Layout print v(14) v(15) v(16) v(17) v(18) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard So v1, v2, and v3 will get the same value, whereas v4 might differ. v11, v12, and v13 will get different values, v14, v15, and v16 will obtain the values set above in the .param statements. \family typewriter .func \family default will start its replacement algorithm, \family typewriter rgauss(a,b,c) \family default will be replaced everywhere by \family typewriter 5*agauss(a,b,c) \family default . \end_layout \begin_layout Standard Thus device and model parameters may obtain statistically distributed starting values. You simply set a model parameter not to a fixed numerical value, but insert a 'parameter' instead, which may consist of a token defined in a \family typewriter .param \family default card, by calling \family typewriter .func \family default or by using a built-in function, including the statistical functions described above. The parameter values will be evaluated once immediately after reading the input file. \end_layout \begin_layout Standard \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Behavioral-sources-(B," \end_inset Behavioral sources (B, E, G, R, L, C) with random control \end_layout \begin_layout Standard All sources listed in the section header may contain parameters, which will be evaluated \series bold before \series default simulation starts, as described in the previous section ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Using-random-param(eters)" \end_inset ). In addition the nonlinear voltage or current sources (B-source, \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" \end_inset ) as well as their derivatives E and G, but also the behavioral R, L, and C may be controlled \series bold during \series default simulation by a random independent voltage source V with TRRANDOM option (chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Random-voltage-source" \end_inset ). \end_layout \begin_layout Standard An example circuit, a Wien bridge oscillator from input file \family typewriter /examples/Monte_Carlo/OpWien.sp \family default is distributed with ngspice or available at CVS. The two frequency determining pairs of R and C are varied statistically using four independent Gaussian voltage sources as the controlling units. An excerpt of this command sequence is shown below. The total simulation time \family typewriter ttime \family default is divided into 100 equally spaced blocks. Each block will get a new set of control voltages, e.g. \family typewriter VR2 \family default , which is Gaussian distributed, mean 0 and absolute deviation 1. The resistor value is calculated with ±10% spread, the factor 0.033 will set this 10% to be a deviation of 1 sigma from nominal value. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Examples for control of a behavioral resistor: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * random resistor \end_layout \begin_layout Plain Layout .param res = 10k \end_layout \begin_layout Plain Layout .param ttime=12000m \end_layout \begin_layout Plain Layout .param varia=100 \end_layout \begin_layout Plain Layout .param ttime10 = 'ttime/varia' \end_layout \begin_layout Plain Layout * random control voltage (Gaussian distribution) \end_layout \begin_layout Plain Layout VR2 r2 0 dc 0 trrandom (2 'ttime10' 0 1) \end_layout \begin_layout Plain Layout * behavioral resistor \end_layout \begin_layout Plain Layout R2 4 6 R = 'res + 0.033 * res*V(r2)' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard So within a single simulation run you will obtain 100 different frequency values issued by the Wien bridge oscillator. The voltage sequence VR2 is shown below. \end_layout \begin_layout Standard \begin_inset Graphics filename Images/vr2-trrandom.gif scale 60 \end_inset \end_layout \begin_layout Section ngspice scripting language \end_layout \begin_layout Standard The ngspice scripting language is described in detail in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:SCRIPTS" \end_inset . All commands listed in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" \end_inset are available, as well as the built-in functions decried in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset , the control structures listed in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" \end_inset , and the predefined variables from chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" \end_inset . Variables and functions are typically evaluated after a simulation run. You may created loops with several simulation runs and change device and model parameters with the \series bold alter \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Alter*:-Change-a" \end_inset ) or \series bold altermod \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Altermod*:-Change-a" \end_inset ) commands, as shown in the next section \begin_inset CommandInset ref LatexCommand ref reference "sec:Monte-Carlo-Simulation" \end_inset . You may even interrupt a simulation run by proper usage of the \series bold stop \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Stop*:-Set-a" \end_inset ) and \series bold resume \series default ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Resume*:-Continue-a" \end_inset ) commands. After stop you may change device or model parameters and then go on with resume, continuing the simulation with the new parameter values. \end_layout \begin_layout Standard The statistical functions provided for scripting are listed in the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rnd(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A vector with each component a random integer between 0 and the absolute value of the input vector's corresponding integer element value. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sgauss(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random numbers drawn from a Gaussian distribution (real value, mean = 0 , standard deviation = 1). The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sgauss(0) will return a single value of a random number as a vector of length 1.. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sunif(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random real numbers uniformly distributed in the interval [-1 .. 1[. The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sunif(0) will return a single value of a random number as a vector of length 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout poisson(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements being integers drawn from a Poisson distribut ion. The elements of the input vector (real numbers) are the expected numbers λ. Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exponential(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements (real numbers) drawn from an exponential distribution. The elements of the input vector are the respective mean values (real numbers). Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Monte-Carlo-Simulation" \end_inset Monte-Carlo Simulation \end_layout \begin_layout Standard The ngspice scripting language may be used to run Monte-Carlo simulations with statistically varying device or model parameters. Calls to the functions sgauss(0) or sunif(0) (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" \end_inset ) will return Gaussian or uniform distributed random numbers (real numbers), stored in a vector. You may define (see \begin_inset CommandInset ref LatexCommand ref reference "sub:Define:-Define-a" \end_inset ) your own function using sgauss or sunif, e.g. to change the mean or range. In a loop (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" \end_inset ) then you may call the alter ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Alter*:-Change-a" \end_inset ) or altermod ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Altermod*:-Change-a" \end_inset ) statements with random parameters followed by an analysis like op, dc, ac, tran or other. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Example-1-1" \end_inset Example 1 \end_layout \begin_layout Standard The first examples is a LC band pass filter, where L and C device parameters will be changed 100 times. Each change is followed by an ac analysis. All graphs of output voltage versus frequency are plotted. The file is available in the distribution as /examples/Monte_Carlo/MonteCarlo.sp as well as from the \begin_inset CommandInset href LatexCommand href name "CVS repository" target "http://ngspice.cvs.sourceforge.net/viewvc/ngspice/ngspice/ng-spice-rework/examples/Monte_Carlo/MonteCarlo.sp?view=log" \end_inset . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Monte-Carlo example 1 \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Perform Monte Carlo simulation in ngspice \end_layout \begin_layout Plain Layout V1 N001 0 AC 1 DC 0 \end_layout \begin_layout Plain Layout R1 N002 N001 141 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout C1 OUT 0 1e-09 \end_layout \begin_layout Plain Layout L1 OUT 0 10e-06 \end_layout \begin_layout Plain Layout C2 N002 0 1e-09 \end_layout \begin_layout Plain Layout L2 N002 0 10e-06 \end_layout \begin_layout Plain Layout L3 N003 N002 40e-06 \end_layout \begin_layout Plain Layout C3 OUT N003 250e-12 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout R2 0 OUT 141 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout let mc_runs = 100 \end_layout \begin_layout Plain Layout let run = 1 \end_layout \begin_layout Plain Layout set curplot = new $ create a new plot \end_layout \begin_layout Plain Layout set scratch = $curplot $ store its name to 'scratch' \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout define unif(nom, var) (nom + nom*var * sunif(0)) \end_layout \begin_layout Plain Layout define aunif(nom, avar) (nom + avar * sunif(0)) \end_layout \begin_layout Plain Layout define gauss(nom, var, sig) (nom + nom*var/sig * sgauss(0)) \end_layout \begin_layout Plain Layout define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout dowhile run <= mc_runs \end_layout \begin_layout Plain Layout * alter c1 = unif(1e-09, 0.1) \end_layout \begin_layout Plain Layout * alter l1 = aunif(10e-06, 2e-06) \end_layout \begin_layout Plain Layout * alter c2 = aunif(1e-09, 100e-12) \end_layout \begin_layout Plain Layout * alter l2 = unif(10e-06, 0.2) \end_layout \begin_layout Plain Layout * alter l3 = aunif(40e-06, 8e-06) \end_layout \begin_layout Plain Layout * alter c3 = unif(250e-12, 0.15) \end_layout \begin_layout Plain Layout alter c1 = gauss(1e-09, 0.1, 3) \end_layout \begin_layout Plain Layout alter l1 = agauss(10e-06, 2e-06, 3) \end_layout \begin_layout Plain Layout alter c2 = agauss(1e-09, 100e-12, 3) \end_layout \begin_layout Plain Layout alter l2 = gauss(10e-06, 0.2, 3) \end_layout \begin_layout Plain Layout alter l3 = agauss(40e-06, 8e-06, 3) \end_layout \begin_layout Plain Layout alter c3 = gauss(250e-12, 0.15, 3) \end_layout \begin_layout Plain Layout ac oct 100 250K 10Meg \end_layout \begin_layout Plain Layout set run ="$&run" $ create a variable from the vector \end_layout \begin_layout Plain Layout set dt = $curplot $ store the current plot to dt \end_layout \begin_layout Plain Layout setplot $scratch $ make 'scratch' the active plot \end_layout \begin_layout Plain Layout * store the output vector to plot 'scratch' \end_layout \begin_layout Plain Layout let vout{$run}={$dt}.v(out) \end_layout \begin_layout Plain Layout setplot $dt $ go back to the previous plot \end_layout \begin_layout Plain Layout let run = run + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot db({$scratch}.all) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Example 2 \end_layout \begin_layout Standard A more sophisticated input file for Monte Carlo simulation is distributed with the file /examples/Monte_Carlo/MCring.sp ( \begin_inset CommandInset href LatexCommand href name "or CVS repository" target "http://ngspice.cvs.sourceforge.net/viewvc/ngspice/ngspice/ng-spice-rework/examples/Monte_Carlo/MC_ring.sp?view=log" \end_inset ). Due to its length it is not reproduced here, but some comments on its enhanceme nts over example 1 ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Example-1-1" \end_inset ) are presented in the following. \end_layout \begin_layout Standard A 25-stage ring oscillator is the circuit used with a transient simulation. It comprises of CMOS inverters, modeled with BSIM3. Several model parameters (vth, u0, tox, L, and W) shall be varied statistically between each simulation run. The frequency of oscillation will be measured by a fft and stored. Finally a histogram of all measured frequencies will be plotted. \end_layout \begin_layout Standard The function calls to \family typewriter sunif(0) \family default and \family typewriter sgauss(0) \family default return uniformly or Gaussian distributed random numbers. A function \family typewriter unif \family default , defined by the line \end_layout \begin_layout Standard \family typewriter define unif(nom, var) (nom + (nom*var) * sunif(0)) \end_layout \begin_layout Standard will return a value with mean \family typewriter nom \family default and deviation \family typewriter var \family default relative to \family typewriter nom \family default . \end_layout \begin_layout Standard The line \end_layout \begin_layout Standard \family typewriter set n1vth0=@n1[vth0] \end_layout \begin_layout Standard will store the threshold voltage vth0, given by the model parameter set, into a variable \family typewriter n1vth0 \family default , ready to be used by \family typewriter unif \family default , \family typewriter aunif \family default , \family typewriter gauss \family default , or \family typewriter agauss \family default function calls. \end_layout \begin_layout Standard In the simulation loop the altermod command changes the model parameters before a call to tran. After the transient simulation the resulting vector is linearized, a fft is calculated, and the maximum of the fft signal is measured by the \family typewriter meas \family default command and stored in a vector maxffts. Finally the contents of the vector maxffts is plotted in a histogram. \end_layout \begin_layout Standard For more details, please have a look at the strongly commented input file MCring.sp. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Data-evaluation-with" \end_inset Data evaluation with Gnuplot \end_layout \begin_layout Standard Run the example file /examples/Monte_Carlo/OpWien.sp, described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Behavioral-sources-(B," \end_inset . Generate a plot with Gnuplot by the ngspice command \end_layout \begin_layout Standard \family typewriter gnuplot \family default \family typewriter pl4mag v4mag xlimit 500 1500 \end_layout \begin_layout Standard Open and run the command file in the Gnuplot command line window by \end_layout \begin_layout Standard \family typewriter load 'pl-v4mag.p' \end_layout \begin_layout Standard A Gaussian curve will be fitted to the simulation data. The mean oscillator frequency and its deviation are printed in the curve fitting log in the Gnuplot window. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Gnuplot script for data evaluation: \end_layout \begin_layout Plain Layout \begin_inset listings lstparams "basicstyle={\ttfamily},showstringspaces=false" inline false status open \begin_layout Plain Layout # This file: pl-v4mag.p \end_layout \begin_layout Plain Layout # ngspice file OpWien.sp \end_layout \begin_layout Plain Layout # ngspice command: \end_layout \begin_layout Plain Layout # gnuplot pl4mag v4mag xlimit 500 1500 \end_layout \begin_layout Plain Layout # a gnuplot manual: \end_layout \begin_layout Plain Layout # http://www.duke.edu/~hpgavin/gnuplot.html \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout # Gauss function to be fitted \end_layout \begin_layout Plain Layout f1(x)=(c1/(a1*sqrt(2*3.14159))*exp(-((x-b1)**2)/(2*a1**2))) \end_layout \begin_layout Plain Layout # Gauss function to plot start graph \end_layout \begin_layout Plain Layout f2(x)=(c2/(a2*sqrt(2*3.14159))*exp(-((x-b2)**2)/(2*a2**2))) \end_layout \begin_layout Plain Layout # start values \end_layout \begin_layout Plain Layout a1=50 ; b1=900 ; c1=50 \end_layout \begin_layout Plain Layout # keep start values in a2, b2, c2 \end_layout \begin_layout Plain Layout a2=a1 ; b2=b1 ; c2=c1 \end_layout \begin_layout Plain Layout # curve fitting \end_layout \begin_layout Plain Layout fit f1(x) 'pl4mag.data' using 1:2 via a1, b1, c1 \end_layout \begin_layout Plain Layout # plot original and fitted curves with new a1, b1, c1 \end_layout \begin_layout Plain Layout plot "pl4mag.data" using 1:2 with lines, f1(x), f2(x) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Graphics filename Images/gnuplot-stat-an.gif scale 50 \end_inset \end_layout \begin_layout Standard pl4mag.data is the simulation data, f2(x) the starting curve, f1(x) the fitted Gaussian distribution. \end_layout \begin_layout Standard This is just a simple example. You might explore the powerful built-in functions of Gnuplot to do a much more sophisticated statistical data analysis. \end_layout \begin_layout Chapter Circuit optimization with ngspice \end_layout \begin_layout Section Optimization of a circuit \end_layout \begin_layout Standard Your circuit design (analog, maybe mixed-signal) has already the best circuit topology. There might be still some room for parameter selection, e.g. the geometries of transistors or values of passive elements, to best fit the specific purpose. This is, what (automatic) circuit optimization will deliver. In addition you may fine-tune, optimize and verify the circuit over voltage, process or temperature corners. So circuit optimization is a valuable tool in the hands of an experienced designer. It will relieve you from the routine task of 'endless' repetitions of re-simula ting your design. \end_layout \begin_layout Standard You have to choose circuit variables as parameters to be varied during optimizat ion (e.g. device size, component values, bias inputs etc.). Then you may pose performance constraints onto you circuits (e.g. Vnode < 1.2V, gain > 50 etc.). Optimization objectives are the variables to be minimized or maximized. The n objectives and m constraints are assembled into a cost function. \end_layout \begin_layout Standard The optimization flow is now the following: The circuit is loaded. Several (perhaps only one) simulations are started with a suitable starter set of variables. Measurements are done on the simulator output to check for the performance constraints and optimization objectives. These data are fed into the optimizer to evaluate the cost function. A sophisticated algorithm now determines a new set of circuit variables for the next simulator run(s). Stop conditions have to be defined by the user to tell the simulator when to finish (e.g. fall below a cost function value, parameter changes fall below a certain threshold, number of iterations exceeded). \end_layout \begin_layout Standard The optimizer algorithms, its parameters and the starting point influence the convergence behavior. The algorithms have to provide measures to reaching the global optimum, not to stick to a local one, and thus are tantamount for the quality of the optimizer. \end_layout \begin_layout Standard ngspice does not have an integral optimization processor. Thus this chapter will rely on work done by third parties to introduce ngspice optimization capability.ngspice provides the simulation engine, a script or program controls the simulator and provides the optimizer functiona lity. \end_layout \begin_layout Standard Four optimizers are presented here, using ngspice scripting language, using tclspice, using a Python script, and using ASCO, a c-coded optimization program. \end_layout \begin_layout Section ngspice optimizer using ngspice scripts \end_layout \begin_layout Standard Friedrich Schmidt (see \begin_inset CommandInset href LatexCommand href name "his web site" target "http://members.aon.at/fschmid7/page_2_1.html" \end_inset ) has intensively used circuit optimization during his development of Nonlinear loadflow computation with Spice based simulators. He has provided an optimizer using the internal ngspice scripting language (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:SCRIPTS" \end_inset ). His original scripts are found \begin_inset CommandInset href LatexCommand href name "here" target "http://members.aon.at/fschmid7/examples_new.zip" \end_inset . A slightly modified and concentrated set of his scripts is available from the \begin_inset CommandInset href LatexCommand href name "ngspice optimizer directory" target "http://ngspice.sourceforge.net/optimizers/ngspice-optimizer.7z" \end_inset . \end_layout \begin_layout Standard The simple example given in the scripts is o.k. with current ngspice. Real circuits have still to be tested. \end_layout \begin_layout Section ngspice optimizer using tclspice \end_layout \begin_layout Standard ngspice offers another scripting capability, namely the tcl/tk based tclspice option (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:TCLspice" \end_inset ). An optimization procedure may be written using a tcl script. An example is provided in chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:Optimization-of-a" \end_inset . \end_layout \begin_layout Section ngspice optimizer using a Python script \end_layout \begin_layout Standard Werner Hoch has developed a ngspice optimization procedure based on the 'differential evolution' algorithm \begin_inset CommandInset citation LatexCommand cite key "key-21" \end_inset . On his \begin_inset CommandInset href LatexCommand href name "web page" target "http://www.h-renrew.de/h/python_spice/optimisation.html" \end_inset he provides a Python script containing the control flow and algorithms. \end_layout \begin_layout Section ngspice optimizer using ASCO \end_layout \begin_layout Standard The \begin_inset CommandInset href LatexCommand href name "ASCO optimizer" target "http://asco.sourceforge.net/index.html" \end_inset , developed by Joao Ramos, also applies the 'differential evolution' algorithm \begin_inset CommandInset citation LatexCommand cite key "key-21" \end_inset . An enhanced version 0.4.7.1, adding ngspice as a simulation engine, may be downloaded \begin_inset CommandInset href LatexCommand href name "here" target "http://ngspice.sourceforge.net/optimizers/asco-dist.7z" \end_inset (7z archive format). Included are executable files (asco, asco-mpi, ngspice-c for MS Windows). The source code should also compile and function under LINUX (not yet tested). \end_layout \begin_layout Standard ASCO is a standalone executable, which communicates with ngspice via ngspice input and output files. Several optimization examples, originally provided by J. Ramos for other simulators, are prepared for use with ngspice. Parallel processing on a multi-core computer has been tested using MPI ( \begin_inset CommandInset href LatexCommand href name "MPICH2" target "http://www.mcs.anl.gov/research/projects/mpich2/" \end_inset ) under MS Windows. A processor network will be supported as well. A MS Windows console application ngspice_c.exe is included in the archive. Several stand alone tools are provided, but not tested yet. \end_layout \begin_layout Standard Setting up an optimization project with ASCO requires advanced know-how of using ngspice. There are several sources of information. First of all the examples provided with the distribution give hints how to start with ASCO. The original ASCO manual is provided as well, or is available \begin_inset CommandInset href LatexCommand href name "here" target "http://asco.sourceforge.net/manual.html" \end_inset . It elaborates on the examples, using a commercial simulator, and provides a detailed description how to set up ASCO. Installation of ASCO and MPI (under Windows) is described in a file INSTALL. \end_layout \begin_layout Standard Some remarks on how to set up ASCO for ngspice are given in the following sections (more to be added). These a meant not as a complete description, but are an addition the the ASCO manual. \end_layout \begin_layout Subsection Three stage operational amplifier \end_layout \begin_layout Standard This example is taken from chapter 6.2.2 \begin_inset Quotes eld \end_inset Tutorial #2 \begin_inset Quotes erd \end_inset from the ASCO manual. The directory examples/ngspice/amp3 contains four files: \end_layout \begin_layout Paragraph* amp3.cfg \end_layout \begin_layout Standard This file contains all configuration data for this optimization. Of special interest is the following section, which sets the required measureme nts and the constraints on the measured parameters: \end_layout \begin_layout LyX-Code # Measurements # \end_layout \begin_layout LyX-Code ac_power:VDD:MIN:0 \end_layout \begin_layout LyX-Code dc_gain:VOUT:GE:122 \end_layout \begin_layout LyX-Code unity_gain_frequency:VOUT:GE:3.15E6 \end_layout \begin_layout LyX-Code phase_margin:VOUT:GE:51.8 \end_layout \begin_layout LyX-Code phase_margin:VOUT:LE:70 \end_layout \begin_layout LyX-Code amp3_slew_rate:VOUT:GE:0.777E6 \end_layout \begin_layout LyX-Code # \end_layout \begin_layout Standard Each of these entries is linked to a file in the /extract subdirectory, having exactly the same names as given here, e.g. ac_power, dc_gain, unity_gain, phase_margin, and amp3_slew_rate. Each of these files contains an # Info # section, which is currently not used. The # Commands # section may contain a measurement command (including ASCO parameter #SYMBOL#, see file /extract/unity_gain_frequency). It also may contain a .control section (see file /extract/phase_margin_min). During set-up #SYMBOL# is replaced by the file name, a leading 'z', and a trailing number according to the above sequence, starting with 0. \end_layout \begin_layout Paragraph* amp3.sp \end_layout \begin_layout Standard This is the basic circuit description. Entries like #LM2# are ASCO-specific, defined in the # Parameters # section of file amp3.cfg. ASCO will replace these parameter placeholders with real values for simulation, determined by the optimization algorithm. The .control ... .endc section is specific to ngspice. Entries to this section may deliver work-arounds of some commands not available in ngspice, but used in other simulators. You may also define additional measurements, get access to variables and vectors, or define some data manipulation. In this example the .control section contains an op measurement, required later for slew rate calculation, as well as the ac simulation, which has to occur before any further data evaluation. Data from the op simulation are stored in a plot op1. Its name is saved in variable dt. The ac measurements sets another plot ac1. To retrieve op data from the former plot, you have to use the {$dt}. notation (see file /extract/amp3_slew_rate). \end_layout \begin_layout Paragraph* n.typ, p.typ \end_layout \begin_layout Standard MOSFET parameter files, to be included by amp3.sp. \end_layout \begin_layout Subsubsection* Testing the set-up \end_layout \begin_layout Standard Copy asco-test.exe and ngspice_c.exe (console executable of ngspice) into the directory, and run \end_layout \begin_layout Standard \family typewriter $ asco-test -ngspice amp3 \end_layout \begin_layout Standard from the console window. Several files will be created during checking. If you look at .sp: this is the input file for ngspice_c, generated by ASCO. You will find the additional .measure commands and .control sections. The 'quit' command will be added automatically just before the .end command in its own .control section. asco-test will display error messages on the console, if the simulation or communication with ASCO is not o.k.. The output file .out, generated by ngspice during each simulation , contains symbols like zac_power0, zdc_gain1, zunity_gain_frequency2, zphase_ma rgin3, zphase_margin4, and zamp3_slew_rate5. These are used to communicate the ngspice output data to ASCO. ASCO is searching for something like 'zdc_gain1 =', and then takes the next token as the input value. Calling phase_margin twice in amp3.cfg has lead to two measurements in two .control sections with different symbols (zphase_margin3, zphase_margin4). \end_layout \begin_layout Standard A failing test may result in an error message from ASCO. Sometimes, however, ASCO freezes after some output statements. This may happen if ngspice issues an error message which cannot be handled by ASCO. Here it may help calling ngspice directly with the input file generated by ASCO: \end_layout \begin_layout Standard \family typewriter $ ngspice_c .sp \end_layout \begin_layout Standard Thus you may evaluate the ngspice messages directly. \end_layout \begin_layout Subsubsection* Running the simulation \end_layout \begin_layout Standard Copy (w)asco.exe, (w)asco-mpi.exe and ngspice_c.exe (console executable of ngspice) into the directory, and run \end_layout \begin_layout Standard \family typewriter $ asco -ngspice amp3 \end_layout \begin_layout Standard or alternatively (if MPICH is installed) \end_layout \begin_layout Standard \family typewriter $ mpiexec -n 7 asco-mpi -ngspice amp3 \end_layout \begin_layout Standard The following graph \begin_inset CommandInset ref LatexCommand ref reference "fig:Optimization-speed" \end_inset shows the acceleration of the optimization simulation on a multi-core processor (i7 with 4 real or 8 virtual cores), 500 generations, if -n is varied. Speed is tripled, a mere 15 min suffices to optimize 21 parameters of the amplifier. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \noindent \align center \begin_inset Graphics filename Images/optim-speed.gif scale 40 \end_inset \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Optimization-speed" \end_inset Optimization speed \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Digital inverter \end_layout \begin_layout Standard This example is taken from chapter 6.2.1 \begin_inset Quotes eld \end_inset Tutorial #1 \begin_inset Quotes erd \end_inset from the ASCO manual. In addition to the features alreday mentioned above, it adds Monte-Carlo and corner simulations. The file inv.cfg contains the following section: \end_layout \begin_layout LyX-Code #Optimization Flow# \end_layout \begin_layout LyX-Code Alter:yes $do we want to do corner analysis? \end_layout \begin_layout LyX-Code MonteCarlo:yes $do we want to do MonteCarlo analysis? \end_layout \begin_layout LyX-Code AlterMC cost:3.00 $point at which we want to start ALTER and/or \begin_inset Newline newline \end_inset MONTECARLO \end_layout \begin_layout LyX-Code ExecuteRF:no $Execute or no the RF module to add RF parasitics? \end_layout \begin_layout LyX-Code SomethingElse: $ \end_layout \begin_layout LyX-Code # \end_layout \begin_layout Standard Monte Carlo is switched on. It uses the AGAUSS function (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Using-random-param(eters)" \end_inset ). Its parameters are generated by ASCO from the data supplied by the inv.cfg section #Monte Carlo#. According to the paper by Pelgrom on MOS transistor matching \begin_inset CommandInset citation LatexCommand cite key "key-22" \end_inset the AGAUSS parameters are calculated as \begin_inset Formula \begin{equation} W=AGAUSS\left(W,\frac{ABeta}{\sqrt{2\cdot W\cdot L\cdot m}}\cdot\frac{W}{100}\cdot10^{-6},1\right)\end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} delvto=AGAUSS\left(0,\frac{AVT}{\sqrt{2\cdot W\cdot L\cdot m}}\cdot10^{-9},1\right)\end{equation} \end_inset \end_layout \begin_layout Standard The .ALTER command is not available in ngspice. However, a new option in ngspice to the altermod command ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Altermod*:-Change-a" \end_inset ) enables the simulation of design corners. The #Alter# section in inv.cfg gives details. Specific to ngspice, again several .control section are used. \end_layout \begin_layout LyX-Code # ALTER # \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code * gate oxide thickness varied \end_layout \begin_layout LyX-Code altermod nm pm file [b3.min b3.typ b3.max] \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code * power supply variation \end_layout \begin_layout LyX-Code alter vdd=[2.0 2.1 2.2] \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code run \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code # \end_layout \begin_layout Standard NMOS (nm) and PMOS (pm) model parameter sets are loaded from three different model files, each containing both NMOS and PMOS sets. b3.typ is assembled from the original parameter files n.typ and p.typ, provided with original ASCO, with some adaptation to ngspice BSIM3. The min and max sets are artificially created in that only the gate oxide thickness deviates ±1 nm from what is found in model file b3.typ. In addition the power supply voltage is varied, so in total you will find 3 x 3 simulation combinations in the input file .sp (after running asco-test). \end_layout \begin_layout Subsection Bandpass \end_layout \begin_layout Standard This example is taken from chapter 6.2.4 \begin_inset Quotes eld \end_inset Tutorial #4 \begin_inset Quotes erd \end_inset from the ASCO manual. S11 in the passband is to be maximised. S21 is used to extract side lobe parameters. The .net command is not available in ngspice, so S11 and S21 are derived with a script in file bandpass.sp as described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Scattering-parameters" \end_inset . The measurements requested in bandpass.cfg as \end_layout \begin_layout LyX-Code # Measurements # \end_layout \begin_layout LyX-Code Left_Side_Lobe:---:LE:-20 \end_layout \begin_layout LyX-Code Pass_Band_Ripple:---:GE:-1 \end_layout \begin_layout LyX-Code Right_Side_Lobe:---:LE:-20 \end_layout \begin_layout LyX-Code S11_In_Band:---:MAX:--- \end_layout \begin_layout LyX-Code # \end_layout \begin_layout Standard are realized as 'measure' commands inside of control sections (see files in directory extract). The result of a 'measure' statement is a vector, which may be processed by commands in the following lines. In file extract/S1_In_Band #Symbol# is made available only after a short calculation (inversion of sign), using the 'print' command. 'quit' has been added to this entry because it will become the final control section in .sp. A disadvantage of 'measure' inside of a .control section is, that parameters from .param statements may not be used (as is done in example \begin_inset CommandInset ref LatexCommand ref reference "sub:Class-E-power-amplifier" \end_inset ). \end_layout \begin_layout Standard The bandpass example includes the calculation of RF parasitic elements defined in rfmodule.cfg (see chapt. 7.5 of the ASCO manual). This calculation is invoked by setting \end_layout \begin_layout LyX-Code ExecuteRF:yes $Execute or no the RF module to add RF parasitics? \end_layout \begin_layout Standard in bandpass.cfg. The two subcircuits LBOND_sub and CSMD_sub are generated in .sp to simulate these effects. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Class-E-power-amplifier" \end_inset Class-E power amplifier \end_layout \begin_layout Standard This example is taken from chapter 6.2.3 \begin_inset Quotes eld \end_inset Tutorial #3 \begin_inset Quotes erd \end_inset from the ASCO manual. In this example the ASCO post processing is applied in file extract/P_OUT (see chapter 7.4 of the ASCO manual.). In this example .measurement statements are used. They allow using parameters from .param statements, because they will be located outside of .control sections, but do not allow to do data post processin g inside of ngspice. You may use ASCO post processing instead. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Notes" \end_inset Notes \end_layout \begin_layout Section Glossary \end_layout \begin_layout Description card A logical SPICE input line. A card may be extended through the use of the \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset sign in SPICE, thereby allowing it to take up multiple lines in a SPICE deck. \end_layout \begin_layout Description code model A model of a device, function, component, etc. which is based solely on a C programming language-based function. In addition to the code models included with the XSPICE option of the ngspice simulator, you can use code models that you develop for circuit modeling. \end_layout \begin_layout Description deck A collection of SPICE cards which together specify all input information required in order to perform an analysis. A \begin_inset Quotes eld \end_inset deck \begin_inset Quotes erd \end_inset of \begin_inset Quotes eld \end_inset cards \begin_inset Quotes erd \end_inset will in fact be contained within a file on the host computer system. \end_layout \begin_layout Description element \series bold card \series default A single, logical line in an ngspice circuit description deck which describes a circuit element. Circuit elements are connected to each other to form circuits (e.g., a logical card which describes a resistor, such as R1 2 0 10K, is an element card). \end_layout \begin_layout Description instance A unique occurrence of a circuit element. See \begin_inset Quotes eld \end_inset element card \begin_inset Quotes erd \end_inset , in which the instance \begin_inset Quotes eld \end_inset R1 \begin_inset Quotes erd \end_inset is specified as a unique element (instance) in a hypothetical circuit descripti on. \end_layout \begin_layout Description macro A macro, in the context of this document, refers to a C language macro which supports the construction of user-defined models by simplifying input/out put and parameter-passing operations within the Model Definition File. \end_layout \begin_layout Description .mod Refers to the Model Definition File in XSPICE. The file suffix reflects the file-name of the model definition file: cfunc.mod. \end_layout \begin_layout Description .model Refers to a model card associated with an element card in ngspice. A model card allows for data defining an instance to be conveniently located in the ngspice deck such that the general layout of the elements is more readable. \end_layout \begin_layout Description Nutmeg The ngspice default post-processor. This provides a simple stand-alone simulator interface which can be used with the ngspice simulator to display and plot simulator raw files. \end_layout \begin_layout Description subcircuit A \begin_inset Quotes eld \end_inset device \begin_inset Quotes erd \end_inset within an ngspice deck which is defined in terms of a group of element cards and which can be referenced in other parts of the ngspice deck through element cards. \end_layout \begin_layout Section Acronyms and Abbreviations \end_layout \begin_layout Description ATE Automatic Test Equipment \end_layout \begin_layout Description CAE Computer-Aided Engineering \end_layout \begin_layout Description CCCS Current Controlled Current Source. \end_layout \begin_layout Description CCVS Current Controlled Voltage Source. \end_layout \begin_layout Description FET Field Effect Transistor \end_layout \begin_layout Description IDD Interface Design Document \end_layout \begin_layout Description IFS Refers to the Interface Specification File. The abbreviation reflects the file name of the Interface Specification File: ifspec.ifs. \end_layout \begin_layout Description MNA Modified Nodal Analysis \end_layout \begin_layout Description MOSFET Metal Oxide Semiconductor Field Effect Transistor \end_layout \begin_layout Description PWL Piece-Wise Linear \end_layout \begin_layout Description RAM Random Access Memory \end_layout \begin_layout Description ROM Read Only Memory \end_layout \begin_layout Description SDD Software Design Document \end_layout \begin_layout Description SI Simulator Interface \end_layout \begin_layout Description SPICE Simulation Program with Integrated Circuit Emphasis. This program was developed at the University of California at Berkeley and is the origin of ngspice. \end_layout \begin_layout Description SPICE3 Version 3 of SPICE. \end_layout \begin_layout Description SRS Software Requirements Specification \end_layout \begin_layout Description SUM Software User's Manual \end_layout \begin_layout Description UCB University of California at Berkeley \end_layout \begin_layout Description UDN User-Defined Node(s) \end_layout \begin_layout Description VCCS Voltage Controlled Current Source. \end_layout \begin_layout Description VCVS Voltage Controlled Voltage Source \end_layout \begin_layout Description XSPICE Extended SPICE; option to ngspice integrating predefined or user defined code models for event-driven mixed-signal simulation. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "1" key "key-1" \end_inset A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2 ERL Memo No. ERL M80/7, Electronics Research Laboratory University of California, Berkeley, October 1980 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "2" key "key-2" \end_inset T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series-connected MOSFET Structure \begin_inset CommandInset href LatexCommand href name "ERL Memo No. ERL M90/19" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1429.html" \end_inset , Electronics Research Laboratory, University of California, Berkeley, March 1990 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "3" key "key-3" \end_inset B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of BSIM ERL Memo No. ERL M85/42, Electronics Research Laboratory University of California, Berkeley, May 1985 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "4" key "key-4" \end_inset J. R. Pierret, A MOS Parameter Extraction Program for the BSIM Model ERL Memo Nos. ERL M84/99 and M84/100, Electronics Research Laboratory University of Californi a, Berkeley, November 1984 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "5" key "key-5" \end_inset Min-Chie Jeng, Design and Modeling of Deep Submicrometer MOSFETSs \begin_inset CommandInset href LatexCommand href name "ERL Memo Nos. ERL M90/90" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1601.html" \end_inset , Electronics Research Laboratory, University of California, Berkeley, October 1990 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "6" key "key-6" \end_inset Soyeon Park, Analysis and SPICE implementation of High Temperature Effects on MOSFET, Master's thesis, University of California, Berkeley, December 1986. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "7" key "key-7" \end_inset Clement Szeto, Simulation of Temperature Effects in MOSFETs (STEIM), Master's thesis, University of California, Berkeley, May 1988. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "8" key "key-8" \end_inset J.S. Roychowdhury and D.O. Pederson, Efficient Transient Simulation of Lossy Interconnect, Proc. of the 28th ACM/IEEE Design Automation Conference, June 17-21 1991, San Francisco \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "9" key "key-9" \end_inset A. E. Parker and D. J. Skellern, An Improved FET Model for Computer Simulators, IEEE Trans CAD, vol. 9, no. 5, pp. 551-553, May 1990. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "10" key "key-10" \end_inset R. Saleh and A. Yang, Editors, Simulation and Modeling, IEEE Circuits and Devices, vol. 8, no. 3, pp. 7-8 and 49, May 1992. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "11" key "key-11" \end_inset H.Statz et al., GaAs FET Device and Circuit Simulation in SPICE, IEEE Transactions on Electron Devices, V34, Number 2, February 1987, pp160-169. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "12" key "key-12" \end_inset Weidong Liu et al.: \begin_inset Quotes eld \end_inset BSIM3v3.2.3 MOSFET Model User's Manual \begin_inset Quotes erd \end_inset , \begin_inset CommandInset href LatexCommand href name "BSIM3v3.2.3" target "http://www-device.eecs.berkeley.edu/~bsim3/ftpv323/Mod_doc/BSIM3v323_manu.tarBSIM3v3.2.3" \end_inset \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "13" key "key-13" \end_inset Weidong Lui et al.: \begin_inset Quotes eld \end_inset BSIM3.v3.3.0 MOSFET Model User's Manual \begin_inset Quotes erd \end_inset , \begin_inset CommandInset href LatexCommand href name "BSIM3v3.3.0" target "http://www-device.eecs.berkeley.edu/~bsim3/ftpv330/Mod_doc/b3v33manu.tar" \end_inset \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "14" key "key-14" \end_inset \begin_inset Quotes eld \end_inset SPICE3.C1 Nutmeg Programmer's Manual \begin_inset Quotes erd \end_inset , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California, April, 1987. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "15" key "key-15" \end_inset Thomas L. Quarles: \begin_inset CommandInset href LatexCommand href name "SPICE3 Version 3C1 User's Guide" target "www.eecs.berkeley.edu/Pubs/TechRpts/1989/ERL-89-46.pdf" \end_inset , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California, April, 1989. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "16" key "key-16" \end_inset Brian Kernighan and Dennis Ritchie: \begin_inset Quotes eld \end_inset The C Programming Language \begin_inset Quotes erd \end_inset , Second Edition, Prentice-Hall, Englewood Cliffs, New Jersey, 1988. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "17" key "key-17" \end_inset \begin_inset Quotes eld \end_inset Code-Level Modeling in XSPICE \begin_inset Quotes erd \end_inset , F.L. Cox, W.B. Kuhn, J.P. Murray, and S.D. Tynor, published in the Proceedings of the 1992 International Symposium on Circuits and Systems, San Diego, CA, May 1992, vol 2, pp. 871-874. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "18" key "key-18" \end_inset \begin_inset Quotes erd \end_inset A Physically Based Compact Model of Partially Depleted SOI MOSFETs for Analog Circuit Simulation \begin_inset Quotes erd \end_inset , Mike S. L. Lee, Bernard M. Tenbroek, William Redman-White, James Benson, and Michael J. Uren, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001, pp. 110-121 \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "19" key "key-19" \end_inset \begin_inset Quotes erd \end_inset A Realistic Large-signal MESFET Model for SPICE \begin_inset Quotes erd \end_inset , A. E. Parker, and D. J. Skellern, IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 9, Sept. 1997, pp. 1563-1571. \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "20" key "key-20" \end_inset \begin_inset Quotes erd \end_inset Integrating RTS Noise into Circuit Analysis \begin_inset Quotes erd \end_inset , T. B. Tang and A. F. Murray, IEEE ISCAS, 2009, Proc. of IEEE ISCAS, Taipei, Taiwan, May 2009, pp 585-588 ( \begin_inset CommandInset href LatexCommand href name "link" target "http://www.see.ed.ac.uk/~tbt/iscas09.pdf" \end_inset ) \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "21" key "key-21" \end_inset R. Storn, and K. Price: \begin_inset Quotes eld \end_inset Differential Evolution \begin_inset Quotes erd \end_inset , technical report TR-95-012, ICSI, March 1995, see \begin_inset CommandInset href LatexCommand href name "report download" target "http://www.icsi.berkeley.edu/~storn/TR-95-012.pdf" \end_inset , or the \begin_inset CommandInset href LatexCommand href name "DE web page" target "http://www.icsi.berkeley.edu/~storn/code.html" \end_inset \end_layout \begin_layout Bibliography \begin_inset CommandInset bibitem LatexCommand bibitem label "22" key "key-22" \end_inset M. J. M. Pelgrom e.a.: \begin_inset Quotes eld \end_inset Matching Properties of MOS Transistors \begin_inset Quotes erd \end_inset , IEEE J. Sol. State Circ, vol. 24, no. 5, Oct. 1989, pp. 1433-1440 \end_layout \begin_layout Standard \begin_inset Newpage newpage \end_inset \end_layout \begin_layout Part \begin_inset CommandInset label LatexCommand label name "par:XSPICE-Software-User's" \end_inset XSPICE Software User's Manual \end_layout \begin_layout Chapter XSPICE Basics \end_layout \begin_layout Section ngspice with the XSPICE option \end_layout \begin_layout Standard The XSPICE option allows you to add event-driven simulation capabilities to NGSPICE. NGSPICE now is the main software program that performs mathematical simulation of a circuit specified by you, the user. It takes input in the form of commands and circuit descriptions and produces output data (e.g. voltages, currents, digital states, and waveforms) that describe the circuit’s behavior. \end_layout \begin_layout Standard Plain NGSPICE is designed for analog simulation and is based exclusively on matrix solution techniques. The XSPICE option adds even-driven simulation capabilities. Thus, designs that contain significant portions of digital circuitry can be efficiently simulated together with analog components. NGSPICE with XSPICE option also includes a \begin_inset Quotes eld \end_inset User-Defined Node \begin_inset Quotes erd \end_inset capability that allows event-driven simulations to be carried out with any type of data. \end_layout \begin_layout Standard The XSPICE option has been developed by the Computer Science and Information Technology Laboratory at Georgia Tech Research Institute of the Georgia Institute of Technology, Atlanta, Georgia 30332 at around 1990 and enhanced by the NGSPICE team. The manual is based on the original XSPICE user's manual, made available from \begin_inset CommandInset href LatexCommand href name "Georgia Tech" target "http://users.ece.gatech.edu/~mrichard/Xspice/" \end_inset . \end_layout \begin_layout Standard In the following, the term \begin_inset Quotes eld \end_inset XSPICE \begin_inset Quotes erd \end_inset may be read as \begin_inset Quotes eld \end_inset NGSPICE with XSPICE code model subsystem enabled \begin_inset Quotes erd \end_inset . You may enable the option by adding \family typewriter --enable-xspice \family default to the \family typewriter ./configure \family default command. The MS Windows distribution already contains the XSPICE option. \end_layout \begin_layout Section The XSPICE Code Model Subsystem \end_layout \begin_layout Standard The new component of ngspice, the Code Model Subsystem, provides the tools needed to model the various parts of your system. While NGSPICE is targeted primarily at integrated circuit (IC) analysis, XSPICE includes features to model and simulate board-level and system-level designs as well. The Code Model Subsystem is central to this new capability, providing XSPICE with an extensive set of models to use in designs and allowing you to add your own models to this model set. \end_layout \begin_layout Standard The NGSPICE simulator at the core of XSPICE includes built-in models for discrete components commonly found within integrated circuits. These \begin_inset Quotes eld \end_inset model primitives \begin_inset Quotes erd \end_inset include components such as resistors, capacitors, diodes, and transistors. The XSPICE Code Model Subsystem extends this set of primitives in two ways. First, it provides a library of over 40 additional primitives, including summers, integrators, digital gates, controlled oscillators, s-domain transfer functions, and digital state machines. See chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset for a description of the library entries. Second, it adds a code model generator to ngspice which provides a set of programming utilities to make it easy for you to create your own models by writing them in the C programming language. \end_layout \begin_layout Standard The code models are generated upon compiling ngspice. They are stored in shared libraries, which may be distributed independently from the ngspice sources. Upon runtime ngspice will load the code model libraries and make the code model instances available for simulation. \end_layout \begin_layout Section XSPICE Top-Level Diagram \end_layout \begin_layout Standard A top-level diagram of the XSPICE system integrated into ngspice is shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:ngspice/XSPICE-Top-Level-Diagram" \end_inset . The XSPICE Simulator is made up of the NGSPICE core, the event-driven algorithm , circuit description syntax parser extensions, a loading routine for code models, and the Nutmeg user interface. The XSPICE Code Model Subsystem consists of the Code Model Generator, 5 standard code model library sources with more than 40 code models, the sources for Node Type Libraries, and all the interfaces to User-Defined Code Models and to User-Defined Node Types. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/XSPICE-Toplevel.gif width 100line% \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:ngspice/XSPICE-Top-Level-Diagram" \end_inset ngspice/XSPICE Top-Level Diagram \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Execution-Procedures" \end_inset Execution Procedures \end_layout \begin_layout Standard This chapter covers operation of the XSPICE simulator and the Code Model Subsystem. It begins with background material on simulation and modeling and then discusses the analysis modes supported in XSPICE and the circuit description syntax used for modeling. Detailed descriptions of the predefined Code Models and Node Types provided in the XSPICE libraries are also included. \end_layout \begin_layout Section Simulation and Modeling Overview \end_layout \begin_layout Standard This section introduces the concepts of circuit simulation and modeling. It is intended primarily for users who have little or no previous experience with circuit simulators, and also for those who have not used circuit simulator s recently. However, experienced SPICE users may wish to scan the material presented here since it provides background for new Code Model and User-Defined Node capabilities of the XSPICE option. \end_layout \begin_layout Standard \end_layout \begin_layout Subsection Describing the Circuit \end_layout \begin_layout Standard This section provides an overview of the circuit description syntax expected by the XSPICE simulator. A general understanding of circuit description syntax will be helpful to you should you encounter problems with your circuit and need to examine the simulator's error messages, or should you wish to develop your own models. \end_layout \begin_layout Standard This section will introduce you to the creation of circuit description input files using the Nutmeg user interface. Note that this material is presented in an overview form. Details of circuit description syntax are given later in this chapter and in the previous chapters of this manual. \end_layout \begin_layout Subsubsection Example Circuit Description Input \end_layout \begin_layout Standard Although different SPICE-based simulators may include various enhancements to the basic version from the University of California at Berkeley, most use a similar approach in describing circuits. This approach involves capturing the information present in a circuit schematic in the form of a text file that follows a defined format. This format requires the assignment of alphanumeric identifiers to each circuit node, the assignment of component identifiers to each circuit device, and the definition of the significant parameters for each device. For example, the circuit description below shows the equivalent input file for the circuit shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-1" \end_inset . \end_layout \begin_layout LyX-Code \size small Small Signal Amplifier \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small *This circuit simulates a simple small signal amplifier. \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small Vin Input 0 0 SIN(0 .1 500Hz) \end_layout \begin_layout LyX-Code \size small R_source Input Amp_In 100 \end_layout \begin_layout LyX-Code \size small C1 Amp_In 0 1uF \end_layout \begin_layout LyX-Code \size small R_Amp_Input Amp_In 0 1MEG \end_layout \begin_layout LyX-Code \size small E1 (Amp:Out 0) (Amp_In 0) -10 \end_layout \begin_layout LyX-Code \size small R_Load Amp_Out 0 1000 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .Tran 1.0u 0.01 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .end \end_layout \begin_layout Standard \begin_inset Float figure wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Example_Circuit_1.gif width 100line% clip \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Example-Circuit-1" \end_inset Example Circuit 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This file exhibits many of the most important properties common to all SPICE circuit description files including the following: \end_layout \begin_layout Itemize The first line of the file is always interpreted as the title of the circuit. The title may consist of any text string. \end_layout \begin_layout Itemize Lines which provide user comments, but no circuit information, are begun by an asterisk. \end_layout \begin_layout Itemize A circuit device is specified by a device name, followed by the node(s) to which it is connected, and then by any required parameter information. \end_layout \begin_layout Itemize The first character of a device name tells the simulator what kind of device it is (e.g. R = resistor, C = capacitor, E = voltage controlled voltage source). \end_layout \begin_layout Itemize Nodes may be labeled with any alphanumeric identifier. The only specific labeling requirement is that 0 must be used for ground. \end_layout \begin_layout Itemize A line that begins with a dot is a \begin_inset Quotes eld \end_inset control directive \begin_inset Quotes erd \end_inset . Control directives are used most frequently for specifying the type of analysis the simulator is to carry out. \end_layout \begin_layout Itemize An \begin_inset Quotes eld \end_inset .end \begin_inset Quotes erd \end_inset statement must be included at the end of the file. \end_layout \begin_layout Itemize With the exception of the Title and .end statements, the order in which the circuit file is defined is arbitrary. \end_layout \begin_layout Itemize All identifiers are case insensitive - the identifier `npn' is equivalent to `NPN' and to `nPn'. \end_layout \begin_layout Itemize Spaces and parenthesis are treated as white space. \end_layout \begin_layout Itemize Long lines may be continued on a succeeding line by beginning the next line with a `+' in the first column. \end_layout \begin_layout Standard In this example, the title of the circuit is `Small Signal Amplifier'. Three comment lines are included before the actual circuit description begins. The first device in the circuit is voltage source `Vin', which is connected between node `Input' and `0' (ground). The parameters after the nodes specify that the source has an initial value of 0, a wave shape of `SIN', and a DC offset, amplitude, and frequency of 0, .1, and 500 respectively. The next device in the circuit is resistor `R_Source', which is connected between nodes `Input' and `Amp_In', with a value of 100 Ohms. The remaining device lines in the file are interpreted similarly. \end_layout \begin_layout Standard The control directive that begins with `.Tran' specifies that the simulator should carry out a simulation using the Transient analysis mode. In this example, the parameters to the transient analysis control directive specify that the maximum time-step allowed is 1 microsecond and that the circuit should be simulated for 0.01 seconds of circuit time. \end_layout \begin_layout Standard Other control cards are used for other analysis modes. For example, if a frequency response plot is desired, perhaps to determine the effect of the capacitor in the circuit, the following statement will instruct the simulator to perform a frequency analysis from 100 Hz to 10 MHz in decade intervals with ten points per decade. \end_layout \begin_layout LyX-Code \size small .ac dec 10 100 10meg \end_layout \begin_layout Standard To determine the quiescent operating point of the circuit, the following statement may be inserted in the file. \end_layout \begin_layout LyX-Code .op \end_layout \begin_layout Standard A fourth analysis type supported by ngspice is swept DC analysis. An example control statement for the analysis mode is \end_layout \begin_layout LyX-Code \size small .dc Vin -0.1 0.2 .05 \end_layout \begin_layout Standard This statement specifies a DC sweep which varies the source Vin from -100 millivolts to +200 millivolts in steps of 50 millivolts. \end_layout \begin_layout Subsubsection Models and Subcircuits \end_layout \begin_layout Standard The file discussed in the previous section illustrated the most basic syntax rules of a circuit description file. However, ngspice (and other SPICE-based simulators) include many other features which allow for accurate modeling of semiconductor devices such as diodes and transistors and for grouping elements of a circuit into a macro or `subcircuit' description which can be reused throughout a circuit description. For instance, the file shown below is a representation of the schematic shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-2" \end_inset . \end_layout \begin_layout LyX-Code \size small Small Signal Amplifier with Limit Diodes \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small *This circuit simulates a small signal amplifier \end_layout \begin_layout LyX-Code \size small *with a diode limiter. \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .dc Vin -1 1 .05 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small Vin Input 0 DC 0 \end_layout \begin_layout LyX-Code \size small R_source Input Amp_In 100 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small D_Neg 0 Amp_In 1n4148 \end_layout \begin_layout LyX-Code \size small D_Pos Amp_In 0 1n4148 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small C1 Amp_In 0 1uF \end_layout \begin_layout LyX-Code \size small X1 Amp_In 0 Amp.Out Amplifier \end_layout \begin_layout LyX-Code \size small R_Load Amp_Out 0 1000 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00 \end_layout \begin_layout LyX-Code \size small + tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 \end_layout \begin_layout LyX-Code \size small + ibv=1.000E-04) \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .subckt Amplifier Input Common Output \end_layout \begin_layout LyX-Code \size small E1 (Output Common) (Input Common) -10 \end_layout \begin_layout LyX-Code \size small R_Input Input Common 1meg \end_layout \begin_layout LyX-Code \size small .ends Amplifier \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .end \end_layout \begin_layout Standard \begin_inset Float figure wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Example_Circuit_2.gif lyxscale 75 width 100line% scaleBeforeRotation clip \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Example-Circuit-2" \end_inset Example Circuit 2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the same basic circuit as in the initial example, with the addition of two components and some changes to the simulation file. The two diodes have been included to illustrate the use of device models, and the amplifier is implemented with a subcircuit. Additionally, this file shows the use of the swept DC control card. \end_layout \begin_layout Paragraph Device Models \end_layout \begin_layout Standard Device models allow you to specify, when required, many of the parameters of the devices being simulated. In this example, model statements are used to define the silicon diodes. Electrically, the diodes serve to limit the voltage at the amplifier input to values between about \begin_inset Formula $\pm$ \end_inset 700 millivolts. The diode is simulated by first declaring the \begin_inset Quotes eld \end_inset instance \begin_inset Quotes erd \end_inset of each diode with a device statement. Instead of attempting to provide parameter information separately for both diodes, the label \begin_inset Quotes eld \end_inset 1n4148 \begin_inset Quotes erd \end_inset alerts the simulator that a separate model statement is included in the file which provides the necessary electrical specifications for the device ( \begin_inset Quotes eld \end_inset 1n4148 \begin_inset Quotes erd \end_inset is the part number for the type of diode the model is meant to simulate). \end_layout \begin_layout Standard The model statement that provides this information is: \end_layout \begin_layout LyX-Code \size small .model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00 \end_layout \begin_layout LyX-Code \size small + tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 \end_layout \begin_layout LyX-Code \size small + bv=1.000E+02 ibv=1.000E-04) \end_layout \begin_layout Standard The model statement always begins with the string \begin_inset Quotes eld \end_inset .model \begin_inset Quotes erd \end_inset followed by an identifier and the model type (D for diode, NPN for NPN transistors, etc). \end_layout \begin_layout Standard The optional parameters (`is', `rs', `n', `etc.') shown in this example configure the simulator's mathematical model of the diode to match the specific behavior of a particular part (e.g. a \begin_inset Quotes eld \end_inset 1n4148 \begin_inset Quotes erd \end_inset ). \end_layout \begin_layout Paragraph Subcircuits \end_layout \begin_layout Standard In some applications, describing a device by embedding the required elements in the main circuit file, as is done for the amplifier in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-1" \end_inset , is not desirable. A hierarchical approach may be taken by using subcircuits. An example of a subcircuit statement is shown in the second circuit file: \end_layout \begin_layout LyX-Code \size small X1 Amp_In 0 Amp_Out \end_layout \begin_layout Standard Amplifier Subcircuits are always identified by a device label beginning with \begin_inset Quotes eld \end_inset X \begin_inset Quotes erd \end_inset . Just as with other devices, all of the connected nodes are specified. Notice, in this example, that three nodes are used. Finally, the name of the subcircuit is specified. Elsewhere in the circuit file, the simulator looks for a statement of the form: \end_layout \begin_layout LyX-Code \size small .subckt ... \end_layout \begin_layout Standard This statement specifies that the lines that follow are part of the Amplifier subcircuit, and that the three nodes listed are to be treated wherever they occur in the subcircuit definition as referring, respectively, to the nodes on the main circuit from which the subcircuit was called. Normal device, model, and comment statements may then follow. The subcircuit definition is concluded with a statement of the form: \end_layout \begin_layout LyX-Code \size small .ends \end_layout \begin_layout Subsubsection XSPICE Code Models \end_layout \begin_layout Standard In the previous example, the specification of the amplifier was accomplished by using a NGSPICE Voltage Controlled Voltage Source device. This is an idealization of the actual amplifier. Practical amplifiers include numerous non-ideal effects, such as offset error voltages and non-ideal input and output impedances. The accurate simulation of complex, real-world components can lead to cumbersom e subcircuit files, long simulation run times, and difficulties in synthesizing the behavior to be modeled from a limited set of internal devices known to the simulator. \end_layout \begin_layout Standard To address these problems, XSPICE allows you to create Code Models which simulate complex, non-ideal effects without the need to develop a subcircuit design. For example, the following file provides simulation of the circuit in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-2" \end_inset , but with the subcircuit amplifier replaced with a Code Model called `Amp' that models several non-ideal effects including input and output impedance and input offset voltage. \end_layout \begin_layout LyX-Code \size small Small Signal Amplifier \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small *This circuit simulates a small signal amplifier \end_layout \begin_layout LyX-Code \size small *with a diode limiter. \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .dc Vin -1 1 .05 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small Vin Input 0 DC 0 \end_layout \begin_layout LyX-Code \size small R_source Input Amp_In 100 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small D_Neg 0 Amp_In 1n4148 \end_layout \begin_layout LyX-Code \size small D_Pos Amp_In 0 1n4148 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small C1 Amp_In 0 1uF \end_layout \begin_layout LyX-Code \size small A1 Amp_In 0 Amp_Out Amplifier \end_layout \begin_layout LyX-Code \size small R_Load Amp_Out 0 1000 \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00 \end_layout \begin_layout LyX-Code \size small + tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 \end_layout \begin_layout LyX-Code \size small + ibv=1.000E-04) \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .model Amplifier Amp (gain = -10 in_offset = 1e-3 \end_layout \begin_layout LyX-Code \size small + rin = 1meg rout = 0.4) \end_layout \begin_layout LyX-Code \size small * \end_layout \begin_layout LyX-Code \size small .end \end_layout \begin_layout Standard A statement with a device label beginning with \begin_inset Quotes eld \end_inset A \begin_inset Quotes erd \end_inset alerts the simulator that the device uses a Code Model. The model statement is similar in form to the one used to specify the diode. The model label `Amp' directs XSPICE to use the code model with that name. Parameter information has been added to specify a gain of -10, an input offset of 1 millivolt, an input impedance of 1 meg ohm, and an output impedance of 0.4 ohm. Subsequent sections of this document detail the steps required to create such a Code Model and include it in the XSPICE simulator. \end_layout \begin_layout Subsubsection Node Bridge Models \end_layout \begin_layout Standard When a mixed-mode simulator is used, some method must be provided for translatin g data between the different simulation algorithms. XSPICE's Code Model support allows you to develop models that work under the analog simulation algorithm, the event-driven simulation algorithm, or both at once. \end_layout \begin_layout Standard In XSPICE, models developed for the express purpose of translating between the different algorithms or between different User-Defined Node types are called \begin_inset Quotes eld \end_inset Node Bridge \begin_inset Quotes erd \end_inset models. For translations between the built-in analog and digital types, predefined node bridge models are included in the XSPICE Code Model Library. \end_layout \begin_layout Subsubsection Practical Model Development \end_layout \begin_layout Standard In practice, developing models often involves using a combination of NGSPICE passive devices, device models, subcircuits, and XSPICE Code Models. XSPICE's Code Models may be seen as an extension to the set of device models offered in standard NGSPICE. The collection of over 40 predefined Code Models included with XSPICE provides you with an enriched set of modeling primitives with which to build subcircuit models. In general, you should first attempt to construct your models from these available primitives. This is often the quickest and easiest method. \end_layout \begin_layout Standard If you find that you cannot easily design a subcircuit to accomplish your goal using the available primitives, then you should turn to the code modeling approach. Because they are written in a general purpose programming language (C), code models enable you to simulate virtually any behavior for which you can develop a set of equations or algorithms. \end_layout \begin_layout Standard \end_layout \begin_layout Section Circuit Description Syntax \end_layout \begin_layout Standard If you need to debug a simulation, if you are planning to develop your own models, or if you are using the XSPICE simulator through the Nutmeg user interface, you will need to become familiar with the circuit description language. \end_layout \begin_layout Standard The previous sections presented example circuit description input files. The following sections provide more detail on XSPICE circuit descriptions with particular emphasis on the syntax for creating and using models. First, the language and syntax of the NGSPICE simulator are described and references to additional information are given. Next, XSPICE extensions to the ngspice syntax are detailed. Finally, various enhancements to NGSPICE operation are discussed including polynomial sources, arbitrary phase sources, supply ramping, matrix conditionin g, convergence options, and debugging support. \end_layout \begin_layout Standard \end_layout \begin_layout Subsection XSPICE Syntax Extensions \end_layout \begin_layout Standard In the preceding discussion, NGSPICE syntax was reviewed, and those features of NGSPICE that are specifically supported by the XSPICE simulator were enumerated. In addition to these features, there exist extensions to the NGSPICE capabiliti es that provide much more flexibility in describing and simulating a circuit. The following sections describe these capabilities, as well as the syntax required to make use of them. \end_layout \begin_layout Subsubsection Convergence Debugging Support \end_layout \begin_layout Standard When a simulation is failing to converge, the simulator can be asked to return convergence diagnostic information that may be useful in identifying the areas of the circuit in which convergence problems are occurring. When running through the Nutmeg user interface, these messages are written directly to the terminal. \end_layout \begin_layout Subsubsection Digital Nodes \end_layout \begin_layout Standard Support is included for digital nodes that are simulated by an event-driven algorithm. Because the event-driven algorithm is faster than the standard SPICE matrix solution algorithm, and because all \begin_inset Quotes eld \end_inset digital \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset real \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset and User-Defined Node types make use of the event-driven algorithm, reduced simulation time for circuits that include these models can be anticipated compared to simulation of the same circuit using analog code models and nodes. \end_layout \begin_layout Subsubsection User-Defined Nodes \end_layout \begin_layout Standard Support is provided for User Defined Nodes that operate with the event-driven algorithm. These nodes allow the passing of arbitrary data structures among models. The real and integer node types supplied with XSPICE are actually predefined User-Defined Node types. \end_layout \begin_layout Subsubsection Supply Ramping \end_layout \begin_layout Standard A supply ramping function is provided by the simulator as an option to a transient analysis to simulate the turn-on of power supplies to a board level circuit. To enable this option, the compile time flag \series bold XSPICE_EXP \series default has to be set, e.g. by adding \family typewriter CFLAGS="-DXSPICE_EXP" \family default to the ./configure command line. The supply ramping function linearly ramps the values of all independent sources and the capacitor and inductor code models (code model extension) with initial conditions toward their final value at a rate which you define. A complete ngspice deck example of usage of the \family typewriter \series bold ramptime \family default \series default option is shown below. \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \begin_inset listings inline false status open \begin_layout Plain Layout Supply ramping option \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * This circuit demonstrates the use of the option \end_layout \begin_layout Plain Layout * "ramptime" which ramps independent sources and the \end_layout \begin_layout Plain Layout * capacitor and inductor initial conditions from \end_layout \begin_layout Plain Layout * zero to their final value during the time period \end_layout \begin_layout Plain Layout * specified. \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .tran 0.1 5 \end_layout \begin_layout Plain Layout .option ramptime=0.2 \end_layout \begin_layout Plain Layout * a1 1 0 cap \end_layout \begin_layout Plain Layout .model cap capacitor (c=1000uf ic=1) \end_layout \begin_layout Plain Layout r1 1 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout a2 2 0 ind \end_layout \begin_layout Plain Layout .model ind inductor (l=1H ic=1) \end_layout \begin_layout Plain Layout r2 2 0 1.0 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout v1 3 0 1.0 \end_layout \begin_layout Plain Layout r3 3 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout i1 4 0 1e-3 \end_layout \begin_layout Plain Layout r4 4 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout v2 5 0 0.0 sin(0 1 0.3 0 0 45.0) \end_layout \begin_layout Plain Layout r5 5 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sub:How-to-create" \end_inset How to create code models \end_layout \begin_layout Standard The following instruction to create an additional code model uses the ngspice infrastructure and some 'intelligent' copy and paste. As an example an extra code model d_xxor is created in the xtradev shared library, reusing the existing d_xor model from the digital library. More detailed information will be made available in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" \end_inset . \end_layout \begin_layout Standard You should have downloaded ngspice, either the most recent distribution or from the CVS sources, and compiled and installed it properly according to your operating system and the instructions given in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" \end_inset of the Appendix, especially chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Compilation-using-an" \end_inset (for LINUX users), or chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:How-to-make" \end_inset for MINGW and MS Windows (MS Visual Studio will not do, because we not yet have integrated the code model generator into this compiler! You may however use all code models later with any ngspice executable.) . Then Cd into directory ng-spice-rework/src/xspice/icm/xtradev. \end_layout \begin_layout Standard Create a new directory \end_layout \begin_layout Standard \family typewriter mkdir d_xxor \end_layout \begin_layout Standard Copy the two files cfunc.mod and ifspec.ifs from ng-spice-rework/src/xspice/icm/di gital/d_xor to ng-spice-rework/src/xspice/icm/xtradev/d_xxor. These two files may serve as a template for your new model! \end_layout \begin_layout Standard For simplicity reasons we do only a very simple editing to these files here, in fact the functionality is not changed, just the name translated to a new model. Edit the new cfunc.mod: In lines 5, 28, 122, 138, 167, 178 replace the old name (d_xor) by the new name d_xxor. Edit the new ifspec.ifs: In lines 16, 23, 24 replace cm_d_xor by cm_d_xxor and d_xor by d_xxor. \end_layout \begin_layout Standard Make ngspice aware of the new code model by editing file \begin_inset Newline newline \end_inset ng-spice-rework/src/xspice/icm/xtradev/modpath.lst: \end_layout \begin_layout Standard Add a line with the new model name d_xxor. \end_layout \begin_layout Standard Redo ngspice by entering directory ng-spice-rework/release, and issuing the commands: \end_layout \begin_layout Standard \family typewriter make \end_layout \begin_layout Standard \family typewriter sudo make install \end_layout \begin_layout Standard \series bold And that's it! \series default In ng-spice-rework/release/src/xspice/icm/xtradev/ you now will find cfunc.c and ifspec.c and the corresponding object files. The new code model d_xxor resides in the shared library xtradev.cm, and is available after ngspice is started. As a test example you may edit \begin_inset Newline newline \end_inset ng-spice-rework/src/xspice/examples/digital_models1.deck, and change line 60 to the new model: \end_layout \begin_layout Standard \family typewriter .model d_xor1 d_xxor (rise_delay=1.0e-6 fall_delay=2.0e-6 input_load=1.0e-12) \end_layout \begin_layout Standard The complete input file follows: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Code Model Test: new xxor \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** analysis type *** \end_layout \begin_layout Plain Layout .tran .01s 4s \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** input sources *** \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout v2 200 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) ) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout v1 100 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) \end_layout \begin_layout Plain Layout + (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** resistors to ground *** \end_layout \begin_layout Plain Layout r1 100 0 1k \end_layout \begin_layout Plain Layout r2 200 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** adc_bridge blocks *** \end_layout \begin_layout Plain Layout aconverter [200 100] [2 1] adc_bridge1 \end_layout \begin_layout Plain Layout .model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 \end_layout \begin_layout Plain Layout + rise_delay=1.0e-12 fall_delay=1.0e-12) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** xor block *** \end_layout \begin_layout Plain Layout a7 [1 2] 70 d_xor1 \end_layout \begin_layout Plain Layout .model d_xor1 d_xxor (rise_delay=1.0e-6 fall_delay=2.0e-6 \end_layout \begin_layout Plain Layout + input_load=1.0e-12) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** dac_bridge blocks **** \end_layout \begin_layout Plain Layout abridge1 [70] [out] dac1 \end_layout \begin_layout Plain Layout .model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 \end_layout \begin_layout Plain Layout + out_undef = 2.2 input_load = 5.0e-12 t_rise = 50e-9 \end_layout \begin_layout Plain Layout + t_fall = 20e-9) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout *** simulation and plotting *** \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot allv \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard An analog input, delivered by the pwl voltage sources, is transformed into the digital domain by an adc_bridge, processed by the new code model d_xxor, and then translated back into the analog domain. \end_layout \begin_layout Standard If you want to change the functionality of the new model, you have to edit ifspec.ifs for the code model interface and cfunc.mod for the detailed functional ity of the new model. Please see chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" \end_inset , especially chapters \begin_inset CommandInset ref LatexCommand ref reference "sub:Interface-Specification-File" \end_inset ff. for any details. And of course you make take the existing analog, digital, mixed signal and other existing code models (to be found in the subdirectories to ng-spice-r ework/release/src/xspice/icm) as stimulating examples for your work. \end_layout \begin_layout Chapter Example circuits \end_layout \begin_layout Standard The following chapter is designed to demonstrate XSPICE features. The first example circuit models the circuit of Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-2" \end_inset using the XSPICE gain block code model to substitute for the more complex and computationally expensive ngspice transistor model. This example illustrates one way in which XSPICE code models can be used to raise the level of abstraction in circuit modeling to improve simulation speed. \end_layout \begin_layout Standard The next example, shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Example-Circuit-C3" \end_inset , illustrates many of the more advanced features offered by XSPICE. This circuit is a mixed-mode design incorporating digital data, analog data, and User-Defined Node data together in the same simulation. Some of the important features illustrated include: \end_layout \begin_layout Itemize Creating and compiling Code Models \end_layout \begin_layout Itemize Creating an XSPICE executable that incorporates these new models \end_layout \begin_layout Itemize The use of "node bridge" models to translate data between the data types in the simulation \end_layout \begin_layout Itemize Plotting analog and event-driven (digital and User-Defined Node) data \end_layout \begin_layout Itemize Using the "eprint" command to print event-driven data \end_layout \begin_layout Standard Throughout these examples, we assume that ngspice with XSPICE option has already been installed on your system and that your user account has been set up with the proper search path and environment variable data. \end_layout \begin_layout Standard The examples also assume that you are running under LINUX and will use standard LINUX commands such as \begin_inset Quotes eld \end_inset cp \begin_inset Quotes erd \end_inset for copying files, etc. If you are using a different set up, with different operating system command names, you should be able to translate the commands shown into those suitable for your installation. Finally, file system path-names given in the examples assume that ngspice + XSPICE has been installed on your system in directory \begin_inset Quotes eld \end_inset /usr/local/xspice-1-0 \begin_inset Quotes erd \end_inset . If your installation is different, you should substitute the appropriate root path-name where appropriate. \end_layout \begin_layout Section Amplifier with XSPICE model \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset \end_layout \begin_layout Standard The circuit, as has been shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "cap:Example-Circuit-2" \end_inset , is extended here by using the XSPICE code model "gain". The ngspice circuit description for this circuit is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout A transistor amplifier circuit \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .tran 1e-5 2e-3 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout vin 1 0 0.0 ac 1.0 sin(0 1 1k) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout ccouple 1 in 10uF \end_layout \begin_layout Plain Layout rzin in 0 19.35k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout aamp in aout gain_block \end_layout \begin_layout Plain Layout .model gain_block gain (gain = -3.9 out_offset = 7.003) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout rzout aout coll 3.9k \end_layout \begin_layout Plain Layout rbig coll 0 1e12 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Notice the component "aamp". This is an XSPICE code model device. All XSPICE code model devices begin with the letter "a" to distinguish them from other ngspice devices. The actual code model used is referenced through a user-defined identifier at the end of the line - in this case"gain_block". The type of code model used and its parameters appear on the associated .model card. In this example, the gain has been specified as -3.9 to approximate the gain of the transistor amplifier, and the output offset (out_offset) has been set to 7.003 according to the DC bias point information obtained from the DC analysis in Example 1. \end_layout \begin_layout Standard Notice also that input and output impedances of the one-transistor amplifier circuit are modeled with the resistors "rzin" and "rzout", since the "gain" code model defaults to an ideal voltage-input, voltage-output device with infinite input impedance and zero output impedance. \end_layout \begin_layout Standard Lastly, note that a special resistor "rbig" with value "1e12" has been included at the opposite side of the output impedance resistor "rzout". This resistor is required by ngspice's matrix solution formula. Without it, the resistor "rzout" would have only one connection to the circuit, and an ill-formed matrix could result. One way to avoid such problems without adding resistors explicitly is to use the ngspice "rshunt" option described in this document under ngspice Syntax Extensions/General Enhancements. \end_layout \begin_layout Standard To simulate this circuit, copy the file xspice_c2.cir from the directory /src/xspice/examples into a directory in your account. \end_layout \begin_layout LyX-Code $ cp /examples/xspice/xspice_c2.cir xspice_c2.cir \end_layout \begin_layout Standard Invoke the simulator on this circuit: \end_layout \begin_layout LyX-Code $ ngspice xspice_c2.cir \end_layout \begin_layout Standard After a few moments, you should see the ngspice prompt: \end_layout \begin_layout LyX-Code ngspice 1 -> \end_layout \begin_layout Standard Now issue the "run" command and when the prompt returns, issue the "plot" command to examine the voltage at the node "coll". \end_layout \begin_layout LyX-Code ngspice 1 -> run \end_layout \begin_layout LyX-Code ngspice 2 -> plot coll \end_layout \begin_layout Standard The resulting waveform closely matches that from the original transistor amplifier circuit simulated in Example 1. \end_layout \begin_layout Standard When you are done, enter the "quit" command to leave the simulator and return to the command line. \end_layout \begin_layout LyX-Code ngspice 3 -> quit \end_layout \begin_layout Standard So long. \end_layout \begin_layout Standard Using the "rusage" command, you can verify that this abstract model of the transistor amplifier runs somewhat faster than the full circuit of Example 1. This is because the code model is less complex computationally. This demonstrates one important use of XSPICE code models - to reduce run time by modeling circuits at a higher level of abstraction. Speed improvements vary and are most pronounced when a large amount of low-level circuitry can be replaced by a small number of code models and additional components. \end_layout \begin_layout Section XSPICE advanced usage \end_layout \begin_layout Subsection Circuit example C3 \end_layout \begin_layout Standard An equally important use of code models is in creating models for circuits and systems that do not easily lend themselves to synthesis using standard ngspice primitives (resistors, capacitors, diodes, transistors, etc.). This occurs often when trying to create models of ICs for use in simulating board-level designs. Creating models of operational amplifiers such as an LM741 or timer ICs such as an LM555 is greatly simplified through the use of XSPICE code models. Another example of code model use is shown in the next example where a complete sampled-data system is simulated using XSPICE analog, digital, and User-Defined Node types simultaneously. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Example_Circuit_C3.gif width 100line% \end_inset \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Example-Circuit-C3" \end_inset Example Circuit C3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The circuit shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Example-Circuit-C3" \end_inset is designed to demonstrate several of the more advanced features of XSPICE. In this example, you will be introduced to the process of creating code models and linking them into ngspice. You will also learn how to print and plot the results of event-driven analysis data. The ngspice/XSPICE circuit description for this example is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Mixed IO types \end_layout \begin_layout Plain Layout * This circuit contains a mixture of IO types, including \end_layout \begin_layout Plain Layout * analog, digital, user-defined (real), and 'null'. \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * The circuit demonstrates the use of the digital and \end_layout \begin_layout Plain Layout * user-defined node capability to model system-level designs \end_layout \begin_layout Plain Layout * such as sampled-data filters. The simulated circuit \end_layout \begin_layout Plain Layout * contains a digital oscillator enabled after 100us. The \end_layout \begin_layout Plain Layout * square wave oscillator output is divided by 8 with a \end_layout \begin_layout Plain Layout * ripple counter. The result is passed through a digital \end_layout \begin_layout Plain Layout * filter to convert it to a sine wave. \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .tran 1e-5 1e-3 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout v1 1 0 0.0 pulse(0 1 1e-4 1e-6) \end_layout \begin_layout Plain Layout r1 1 0 1k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout abridge1 [1] [enable] atod \end_layout \begin_layout Plain Layout .model atod adc_bridge \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout aclk [enable clk] clk nand \end_layout \begin_layout Plain Layout .model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout adiv2 div2_out clk NULL NULL NULL div2_out dff \end_layout \begin_layout Plain Layout adiv4 div4_out div2_out NULL NULL NULL div4_out dff \end_layout \begin_layout Plain Layout adiv8 div8_out div4_out NULL NULL NULL div8_out dff \end_layout \begin_layout Plain Layout .model dff d_dff \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example (continued): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout abridge2 div8_out enable filt_in node_bridge2 \end_layout \begin_layout Plain Layout .model node_bridge2 d_to_real (zero=-1 one=1) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout xfilter filt_in clk filt_out dig_filter \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout abridge3 filt_out a_out node_bridge3 \end_layout \begin_layout Plain Layout .model node_bridge3 real_to_v \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout rlpf1 a_out oa_minus 10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout xlpf 0 oa_minus lpf_out opamp \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout rlpf2 oa_minus lpf_out 10k \end_layout \begin_layout Plain Layout clpf lpf_out oa_minus 0.01uF \end_layout \begin_layout Plain Layout *************************************** \end_layout \begin_layout Plain Layout .subckt dig_filter filt_in clk filt_out \end_layout \begin_layout Plain Layout .model n0 real_gain (gain=1.0) \end_layout \begin_layout Plain Layout .model n1 real_gain (gain=2.0) \end_layout \begin_layout Plain Layout .model n2 real_gain (gain=1.0) \end_layout \begin_layout Plain Layout .model g1 real_gain (gain=0.125) \end_layout \begin_layout Plain Layout .model zm1 real_delay \end_layout \begin_layout Plain Layout .model d0a real_gain (gain=-0.75) \end_layout \begin_layout Plain Layout .model d1a real_gain (gain=0.5625) \end_layout \begin_layout Plain Layout .model d0b real_gain (gain=-0.3438) \end_layout \begin_layout Plain Layout .model d1b real_gain (gain=1.0) \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout an0a filt_in x0a n0 \end_layout \begin_layout Plain Layout an1a filt_in x1a n1 \end_layout \begin_layout Plain Layout an2a filt_in x2a n2 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout az0a x0a clk x1a zm1 \end_layout \begin_layout Plain Layout az1a x1a clk x2a zm1 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout ad0a x2a x0a d0a \end_layout \begin_layout Plain Layout ad1a x2a x1a d1a \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout az2a x2a filt1_out g1 \end_layout \begin_layout Plain Layout az3a filt1_out clk filt2_in zm1 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout an0b filt2_in x0b n0 \end_layout \begin_layout Plain Layout an1b filt2_in x1b n1 \end_layout \begin_layout Plain Layout an2b filt2_in x2b n2 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout az0b x0b clk x1b zm1 \end_layout \begin_layout Plain Layout az1b x1b clk x2b zm1 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout ad0 x2b x0b d0b \end_layout \begin_layout Plain Layout ad1 x2b x1b d1b \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout az2b x2b clk filt_out zm1 \end_layout \begin_layout Plain Layout .ends dig_filter \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example (continued): \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .subckt opamp plus minus out \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout r1 plus minus 300k \end_layout \begin_layout Plain Layout a1 %vd (plus minus) outint lim \end_layout \begin_layout Plain Layout .model lim limit (out_lower_limit = -12 out_upper_limit = 12 \end_layout \begin_layout Plain Layout + fraction = true limit_range = 0.2 gain=300e3) \end_layout \begin_layout Plain Layout r3 outint out 50.0 \end_layout \begin_layout Plain Layout r2 out 0 1e12 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .ends opamp \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This circuit is a high-level design of a sampled-data filter. An analog step waveform (created from a ngspice "pulse" waveform) is introduced as "v1" and converted to digital by code model instance "abridge". This digital data is used to enable a Nand-Gate oscillator ("aclk") after a short delay. The Nand-Gate oscillator generates a square-wave clock signal with a period of approximately two times the gate delay, which is specified as 1e-5 seconds. This 50 KHz clock is divided by a series of D Flip Flops ("adiv2", "adiv4", "adiv8") to produce a square-wave at approximately 6.25 KHz. Note particularly the use of the reserved word "NULL" for certain nodes on the D Flip Flops. This tells the code model that there is no node connected to these ports of the flip flop. \end_layout \begin_layout Standard The divide-by-8 and enable waveforms are converted by the instance "abridge2" to the format required by the User-Defined Node type "real", which expected real-valued data. The output of this instance on node "filt_in" is a real valued square wave which oscillates between values of -1 and 1. Note that the associated code model "d_to_real" is not part of the original XSPICE code model library but has been added later to ngspice. \end_layout \begin_layout Standard This signal is then passed through subcircuit "xfilter" which contains a digital low-pass filter clocked by node "clk". The result of passing this square-wave through the digital low-pass filter is the production of a sampled sine wave (the filter passes only the fundamenta l of the square-wave input) on node "filt_out". This signal is then converted back to ngspice analog data on node "a_out" by node bridge instance "abridge3". \end_layout \begin_layout Standard The resulting analog waveform is then passed through an op-amp-based low-pass analog filter constructed around subcircuit "xlpf" to produce the final output at analog node "lpf_out". \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Running-example-C3" \end_inset Running example C3 \end_layout \begin_layout Standard Now copy the file "xspice_c3.cir" from directory /examples/xspice/ into the current directory: \end_layout \begin_layout LyX-Code $ cp /examples/xspice/xspice_c3.cir xspice_c3.cir \end_layout \begin_layout Standard and invoke the new simulator executable as you did in the previous examples. \end_layout \begin_layout LyX-Code $ ngspice xspice_c3.cir \end_layout \begin_layout Standard Execute the simulation with the "run" command. \end_layout \begin_layout LyX-Code ngspice 1 -> run \end_layout \begin_layout Standard After a short time, the ngspice prompt should return. Results of this simulation are examined in the manner illustrated in the previous two examples. You can use the "plot" command to plot either analog nodes, event-driven nodes, or both. For example, you can plot the values of the sampled-data filter input node and the analog low-pass filter output node as follows: \end_layout \begin_layout LyX-Code ngspice 2 -> plot filt_in lpf_out \end_layout \begin_layout Standard The plot shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Nutmeg-Plot-of-1" \end_inset should appear. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Filter-IO.gif scale 60 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Nutmeg-Plot-of-1" \end_inset Nutmeg Plot of Filter Input and Output \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard You can also plot data from nodes inside a subcircuit. For example, to plot the data on node "x1a" in subcircuit "xfilter", create a pathname to this node with a dot separator. \end_layout \begin_layout LyX-Code ngspice 3 -> plot xfilter.x1a \end_layout \begin_layout Standard The output from this command is shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Nutmeg-Plot-of" \end_inset . Note that the waveform contains vertical segments. These segments are caused by the non-zero delays in the "real gain" models used within the subcircuit. Each vertical segment is actually a step with a width equal to the model delay (1e-9 seconds). \end_layout \begin_layout Standard Plotting nodes internal to subcircuits works for both analog and event-driven nodes. \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/Subc-filter.gif scale 60 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Nutmeg-Plot-of" \end_inset Nutmeg Plot of Subcircuit Internal Node \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard To examine data such as the closely spaced events inside the subcircuit at node "xfilter.x1a", it is often convenient to use the "eprint" command to produce a tabular listing of events. Try this by entering the following command: \end_layout \begin_layout LyX-Code ngspice 4 -> eprint xfilter.x1a \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code **** Results Data **** \end_layout \begin_layout LyX-Code Time or Step \end_layout \begin_layout LyX-Code xfilter.x1a \end_layout \begin_layout LyX-Code 0.000000000e+000 0.000000e+000 \begin_inset space \qquad{} \end_inset 1.010030000e-004 2.000000e+000 \end_layout \begin_layout LyX-Code 1.010040000e-004 2.562500e+000 \begin_inset space \qquad{} \end_inset 1.210020000e-004 2.812500e+000 \end_layout \begin_layout LyX-Code 1.210030000e-004 4.253906e+000 \begin_inset space \qquad{} \end_inset 1.410020000e-004 2.332031e+000 \end_layout \begin_layout LyX-Code 1.410030000e-004 3.283447e+000 \begin_inset space \qquad{} \end_inset 1.610020000e-004 2.014893e+000 \end_layout \begin_layout LyX-Code 1.610030000e-004 1.469009e+000 \begin_inset space \qquad{} \end_inset 1.810020000e-004 2.196854e+000 \end_layout \begin_layout LyX-Code 1.810030000e-004 1.176232e+000 \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code 9.610030000e-004 3.006294e-001 \begin_inset space \qquad{} \end_inset 9.810020000e-004 2.304755e+000 \end_layout \begin_layout LyX-Code 9.810030000e-004 9.506230e-001 \begin_inset space \qquad{} \end_inset 9.810090000e-004 -3.049377e+000 \end_layout \begin_layout LyX-Code 9.810100000e-004 -4.174377e+000 \end_layout \begin_layout LyX-Code **** Messages **** \end_layout \begin_layout LyX-Code **** Statistics **** \end_layout \begin_layout LyX-Code Operating point analog/event alternations: 1 \end_layout \begin_layout LyX-Code Operating point load calls: 37 \end_layout \begin_layout LyX-Code Operating point event passes: 2 \end_layout \begin_layout LyX-Code Transient analysis load calls: 4299 \end_layout \begin_layout LyX-Code Transient analysis timestep backups: 87 \end_layout \begin_layout Standard This command produces a tabular listing of event-times in the first column and node values in the second column. The 1 ns delays can be clearly seen in the fifth decimal place of the event times. \end_layout \begin_layout Standard Note that the eprint command also gives statistics from the event-driven algorithm portion of XSPICE. For this example, the simulator alternated between the analog solution algorithm and the event-driven algorithm one time while performing the initial DC operating point solution prior to the start of the transient analysis. During this operating point analysis, 37 total calls were made to event-driven code model functions, and two separate event passes or iterations were required before the event nodes obtained stable values. Once the transient analysis commenced, there were 4299 total calls to event-dri ven code model functions. Lastly, the analog simulation algorithm performed 87 time-step backups that forced the event-driven simulator to backup its state data and its event queues. \end_layout \begin_layout Standard A similar output is obtained when printing the values of digital nodes. For example, print the values of the node "div8 out" as follows: \end_layout \begin_layout LyX-Code ngspice 5 -> eprint div8_out \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code **** Results Data **** \end_layout \begin_layout LyX-Code Time or Step \end_layout \begin_layout LyX-Code div8_out \end_layout \begin_layout LyX-Code 0.000000000e+000 1s \end_layout \begin_layout LyX-Code 1.810070000e-004 0s \end_layout \begin_layout LyX-Code 2.610070000e-004 1s \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code 9.010070000e-004 1s \end_layout \begin_layout LyX-Code 9.810070000e-004 0s \end_layout \begin_layout LyX-Code **** Messages **** \end_layout \begin_layout LyX-Code **** Statistics **** \end_layout \begin_layout LyX-Code Operating point analog/event alternations: 1 \end_layout \begin_layout LyX-Code Operating point load calls: 37 \end_layout \begin_layout LyX-Code Operating point event passes: 2 \end_layout \begin_layout LyX-Code Transient analysis load calls: 4299 \end_layout \begin_layout LyX-Code Transient analysis timestep backups: 87 \end_layout \begin_layout Standard From this printout, we see that digital node values are composed of a two character string. The first character (0, 1, or U) gives the state of the node (logic zero, logic one, or unknown logic state). The second character (s, r, z, u) gives the "strength" of the logic state (strong, resistive, hi-impedance, or undetermined). \end_layout \begin_layout Standard If you wish, examine other nodes in this circuit with either the plot or eprint commands. When you are done, enter the "quit" command to exit the simulator and return to the operating system prompt: \end_layout \begin_layout LyX-Code ngspice 6 -> quit \end_layout \begin_layout Standard So long. \end_layout \begin_layout Standard \begin_inset CommandInset index_print LatexCommand printindex \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Code-Models-and" \end_inset Code Models and User-Defined Nodes \end_layout \begin_layout Standard The following sections explain the steps required to create code models and User-Defined Nodes (UDNs), store them in shared libraries and load them into the simulator at runtime. The ngspice simulator already includes XSPICE libraries of predefined models and node types that span the analog and digital domains. These have been detailed earlier in this document (see Sections \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Analog-Models" \end_inset , \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Hybrid-Models" \end_inset , and \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Digital-Models" \end_inset ). However, the real power of the XSPICE is in its support for extending these libraries with new models written by users. ngspice includes an XSPICE code model generator. Adding code models to ngspice will require a model definition plus some simple file operations, which are explained in this chapter. \end_layout \begin_layout Standard The original manual cited an XSPICE \begin_inset Quotes eld \end_inset Code Model Toolkit \begin_inset Quotes erd \end_inset that enabled one to define new models and node data types to be passed between them offline, independent from ngspice. Whereas this Toolkit is still available in the original source code distributio n at the \begin_inset CommandInset href LatexCommand href name "XSPICE web page" target "http://users.ece.gatech.edu/~mrichard/Xspice/" \end_inset , it is neither required nor supported any more. \end_layout \begin_layout Standard So we make use of the existing XSPICE infrastructure provided with ngspice to create new code models. With an 'intelligent' copy and paste, and the many available code models serving as a guide you will be quickly able to create your own models. You have to have a compiler (gcc) available under LINUX, MS Windows (Cygwin, MINGW), maybe also for other OSs, including supporting software (Flex, Bison, and the autotools if you start from CVS sources). The compilation procedures for ngspice are described in detail in chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" \end_inset . Adding a code model may then require defining the functionality , interface, and eventually user defined nodes. Compiling into a shared library is only a simple 'make', loading the shared lib(s) into ngspice is done by the ngspice command \series bold codemodel \series default ... (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Codemodel:-Load-an" \end_inset ). This will allow you to either add some code model to an existing library, or you may generate a new library with your own code models. The latter is of interest if you want to distribute your code models independen tly from the ngspice sources or executables. \end_layout \begin_layout Standard These new code models are handled by ngspice in a manner analogous to its treating of SPICE devices and XSPICE Predefined Code Models. The basic steps required to create sources for new code models or User-Defined Nodes, compile them and load them into ngspice are similar. They consist of 1) creating the code model or UserDefined Node (UDN) directory and its associated model or data files, 2) inform ngspice about which code model or UDN directories have to be compiled and linked into ngspice, 3) compile them into a shared lib, and 4) load them into the ngspice simulator upon runtime. All code models finally reside in dynamically linkable shared libraries (*.cm), which in fact are .so files under LINUX or dlls under MS Windows. Currently we have 5 of them (analog.cm, digital.cm, spice2poly.cm, xtradev.cm, xtraevt.cm). Upon start up of ngspice they are dynamically loaded into the simulator by the ngspice \series bold codemodel \series default command (which is located in file .spinit (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ) for the standard code models). Once you have added your new code model into one of these libraries (or have created a new library file, e.g. my-own.cm), instances of the model can be placed into any simulator deck that describes a circuit of interest and simulated along with all of the other components in that circuit. \end_layout \begin_layout Standard A quick entry to get a new code model has already been presented in chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:How-to-create" \end_inset . You may find the details of the XSPICE language in chapters \begin_inset CommandInset ref LatexCommand ref reference "sub:Interface-Specification-File" \end_inset ff. \end_layout \begin_layout Section Code Model Data Type Definitions \end_layout \begin_layout Standard There are three data types which you can incorporate into a model and which have already been used extensively in the code model library included with the simulator. These are detailed below: \end_layout \begin_layout Paragraph Boolean_t \end_layout \begin_layout Standard The Boolean type is an enumerated type which can take on values of FALSE (integer value 0) or TRUE (integer value 1). Alternative names for these enumerations are MIF FALSE and MIF TRUE, respective ly. \end_layout \begin_layout Paragraph Complex_t \end_layout \begin_layout Standard The Complex type is a structure composed of two double values. The first of these is the .real type, and the second is the .imag type. Typically these values are accessed as shown: \end_layout \begin_layout Standard For complex value \begin_inset Quotes eld \end_inset data \begin_inset Quotes erd \end_inset , the real portion is \begin_inset Quotes eld \end_inset data.real \begin_inset Quotes erd \end_inset , and the imaginary portion is \begin_inset Quotes eld \end_inset data.imag \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Paragraph Digital_State_t \end_layout \begin_layout Standard The Digital State type is an enumerated value which can be either ZERO (integer value 0), ONE (integer value 1), or UNKNOWN (integer value 2). \end_layout \begin_layout Paragraph Digital_Strength_t \end_layout \begin_layout Standard The Digital Strength type is an enumerated value which can be either STRONG (integer value 0), RESISTIVE (integer value 1), HI IMPEDANCE (integer value 2) or UNDETERMINED (integer value 3). \end_layout \begin_layout Paragraph Digital_t \end_layout \begin_layout Standard The Digital type is a composite of the Digital_State_t and Digital_Strength_t enumerated data types. The actual variable names within the Digital type are .state and .strength and are accessed as shown below: \end_layout \begin_layout Standard For Digital_t value \begin_inset Quotes eld \end_inset data \begin_inset Quotes erd \end_inset , the state portion is \begin_inset Quotes eld \end_inset data.state \begin_inset Quotes erd \end_inset , and the strength portion is \begin_inset Quotes eld \end_inset data.strength \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Creating-Code-Models" \end_inset Creating Code Models \end_layout \begin_layout Standard The following description deals with extending one of the five existing code model libraries. Adding a new library is described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Adding-a-new" \end_inset . The first step in creating a new code model within XSPICE is to create a model directory inside of the selected library directory. The new directory name is the name of the new code model. As an example you may add a directory \series bold d_counter \series default to the library directory \series bold digital \series default . \end_layout \begin_layout LyX-Code \family typewriter cd ng-spice-rework/src/xspice/icm/digital \end_layout \begin_layout LyX-Code \family typewriter mkdir d_counter \end_layout \begin_layout Standard Into this new directory you copy the following template files: \end_layout \begin_layout Itemize Interface Specification File (ifspec.ifs) \end_layout \begin_layout Itemize Model Definition File (cfunc.mod) \end_layout \begin_layout Standard You may choose any of the existing files which are similar to the new code model you intend to integrate. The template Interface Specification File (ifspec.ifs) is edited to define the model's inputs, outputs, parameters, etc (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Interface-Specification-File" \end_inset ). You then edit the template Model Definition File (cfunc.mod) to include the C-language source code that defines the model behavior (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Model-Definition-File" \end_inset ). As a final step you have to notify ngspice of the new code model. You have to edit the file \series bold modpath.lst \series default which resides in the library directory ng-spice-rework/src/xspice/icm/digital. Just add the entry \series bold d_counter \series default to this file. \end_layout \begin_layout Standard The Interface Specification File is a text file that describes, in a tabular format, information needed for the code model to be properly interpreted by the simulator when it is placed with other circuit components into a SPICE deck. This information includes such things as the parameter names, parameter default values, and the name of the model itself. The specific format presented to you in the Interface Specification File template must be followed exactly, but is quite straightforward. A detailed description of the required syntax, along with numerous examples, is included in Section \begin_inset CommandInset ref LatexCommand ref reference "sub:Interface-Specification-File" \end_inset . \end_layout \begin_layout Standard The Model Definition File contains a C programming language function definition. This function specifies the operations to be performed within the model on the data passed to it by the simulator. Special macros are provided that allow the function to retrieve input data and return output data. Similarly, macros are provided to allow for such things as storage of informati on between iteration time-points and sending of error messages. Section \begin_inset CommandInset ref LatexCommand ref reference "sec:Model-Definition-File" \end_inset describes the form and function of the Model Definition File in detail and lists the support macros provided within the simulator for use in code models. \end_layout \begin_layout Standard To allow compiling and linking (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Compiling-and-linking" \end_inset ) you have at least to adapt the names of the functions inside of the two copied files to get unique function and model names. If for example you have chosen ifspec.ifs and cfunc.mod from model d_fdiv as your template, simply replace all entries \series bold d_fdiv \series default by \series bold d_counter \series default inside of the two files. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sub:Creating-User-Defined-Nodes" \end_inset Creating User-Defined Nodes \end_layout \begin_layout Standard In addition to providing the capability of adding new models to the simulator, a facility exists which allows node types other than those found in standard SPICE to be created. Models may be constructed which pass information back and forth via these nodes. Such models are constructed in the manner described in the previous sections, with appropriate changes to the Interface Specification and Model Definition Files. \end_layout \begin_layout Standard Because of the need of electrical engineers to have ready access to both digital and analog simulation capabilities, the \begin_inset Quotes eld \end_inset digital \begin_inset Quotes erd \end_inset node type is provided as a built-in node type along with standard SPICE analog nodes. For \begin_inset Quotes eld \end_inset digital \begin_inset Quotes erd \end_inset nodes, extensive support is provided in the form of macros and functions so that you can treat this node type as a standard type analogous to standard SPICE analog nodes when creating and using code models. In addition to \begin_inset Quotes eld \end_inset analog \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset digital \begin_inset Quotes erd \end_inset nodes, the node types \begin_inset Quotes eld \end_inset real \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset are also provided with the simulator. These were created using the User-Defined Node (UDN) creation facilities described below and may serve as a template for further node types. \end_layout \begin_layout Standard The first step in creating a new node type within XSPICE is to set up a node type directory along with the appropriate template files needed. \end_layout \begin_layout LyX-Code \family typewriter cd ng-spice-rework/src/xspice/icm/xtraevt \end_layout \begin_layout LyX-Code \family typewriter mkdir \family default \end_layout \begin_layout Standard should be the name of the new type to be defined. Copy file udnfunc.c from /icm/xtraevt/int into the new directory. Edit this file according to the new type you want to create. \end_layout \begin_layout Standard Notify ngspice about this new UDN directory by editing \begin_inset Newline newline \end_inset ng-spice-rework/src/xspice/icm/xtraevt/udnpath.lst. Add a new line containing . For compiling and linking see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Compiling-and-linking" \end_inset . \end_layout \begin_layout Standard The UDN Definition File contains a set of C language functions. These functions perform operations such as allocating space for data structures , initializing them, and comparing them to each other. Section \begin_inset CommandInset ref LatexCommand ref reference "sec:User-Defined-Node-Definition" \end_inset describes the form and function of the User-Defined Node Definition File in detail and includes an example UDN Definition File. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Adding-a-new" \end_inset Adding a new code model library \end_layout \begin_layout Standard A group of code models may be assembled into a library. A new library is a means to distribute new code models, independently from the existing ones. This is the way to generate a new code model library: \end_layout \begin_layout LyX-Code \family typewriter cd ng-spice-rework/src/xspice/icm/ \end_layout \begin_layout LyX-Code \family typewriter mkdir \family default \end_layout \begin_layout Standard is the name of the new library. Copy empty files modpath.lst and udnpath.lst into this directory. \end_layout \begin_layout Standard Edit file ng-spice-rework/src/xspice/icm/GNUmakefile.in, add to the end of line 10, which starts with CMDIRS = ... . \end_layout \begin_layout Standard That's all you have to do about a new library! Of course it is empty right now, so you have to define at least one code model according to the procedure described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Creating-Code-Models" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Compiling-and-linking" \end_inset Compiling and loading the new code model (library) \end_layout \begin_layout Standard Compiling is now as simple as issuing the commands \end_layout \begin_layout LyX-Code cd ng-spice-rework/release \end_layout \begin_layout LyX-Code make \end_layout \begin_layout LyX-Code sudo make install \end_layout \begin_layout Standard if you have installed ngspice according to chapter \begin_inset CommandInset ref LatexCommand ref reference "sub:Compilation-using-an" \end_inset . This procedure will install the code model libraries into a directory / lib/spice/, e.g. C:/Spice/lib/spice/ for standard Windows install or /usr/local/lib/spice/ for LINUX. \end_layout \begin_layout Standard Thus the code model libraries are not linked into ngspice at compile time, by may be loaded at runtime using the \series bold codemodel \series default command (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Codemodel:-Load-an" \end_inset ). This is done automatically for the predefined code model libraries upon starting ngspice. The appropriate commands are provided in the start up file spinit (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" \end_inset ). So if you have added a new code model inside of one of the existing libraries, nothing has to be done, you will have immediate access to your new model. \end_layout \begin_layout Standard If you have generated a new code model library, e.g. new_lib.cm, then you have to add the line \end_layout \begin_layout LyX-Code @XSPICEINIT@ codemodel @prefix@/@libname@/spice/new_lib.cm \end_layout \begin_layout Standard to spinit.in in ng-spice-rework/src. This will create a new spinit if ngspice is recompiled from scratch. \end_layout \begin_layout Standard To avoid the need for recompilation of ngspice, you also may directly edit the file spinit by adding the line \end_layout \begin_layout LyX-Code codemodel C:/Spice/lib/spice/new_lib.cm \end_layout \begin_layout Standard (OS MS Windows) or the appropriate LINUX equivalent. Upon starting ngspice, the new library will be loaded and you have access to the new code model(s). The \series bold codemodel \series default command has to be executed upon start-up of ngspice, so that the model information is available as soon as the circuit is parsed. Failing to do so will lead to an error message of a model missing. So spinit (or .spiceinit for personal code model libraries) is the correct place for \series bold codemodel \series default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sub:Interface-Specification-File" \end_inset Interface Specification File \end_layout \begin_layout Standard The Interface Specification (IFS) file is a text file that describes the model's naming information, its expected input and output ports, its expected parameters, and any variables within the model that are to be used for storage of data across an entire simulation. These four types of data are described to the simulator in IFS file sections labeled NAME TABLE, PORT TABLE, PARAMETER TABLE and STATIC VAR TABLE, respectiv ely. An example IFS file is given below. The example is followed by detailed descriptions of each of the entries, what they signify, and what values are acceptable for them. Keywords are case insensitive. \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: ucm_xfer \end_layout \begin_layout LyX-Code Spice_Model_Name: xfer \end_layout \begin_layout LyX-Code Description: "arbitrary transfer function" \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_coeff \end_layout \begin_layout LyX-Code Description: "numerator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_coeff \end_layout \begin_layout LyX-Code Description: "denominator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: int_ic \end_layout \begin_layout LyX-Code Description: "integrator stage initial conditions" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: den_coeff \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: x \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Description: "x-coefficient array" \end_layout \begin_layout Subsection The Name Table \end_layout \begin_layout Standard The name table is introduced by the \begin_inset Quotes eld \end_inset Name_Table: \begin_inset Quotes erd \end_inset keyword. It defines the code model's C function name, the name used on a .MODEL card, and an optional textual description. The following sections define the valid fields that may be specified in the Name Table. \end_layout \begin_layout Subsubsection C Function Name \end_layout \begin_layout Standard The C function name is a valid C identifier which is the name of the function for the code model. It is introduced by the \begin_inset Quotes eld \end_inset C_Function_Name: \begin_inset Quotes erd \end_inset keyword followed by a valid C identifier. To reduce the chance of name conflicts, it is recommended that user-written code model names use the prefix \begin_inset Quotes eld \end_inset ucm_ \begin_inset Quotes erd \end_inset for this entry. Thus, in the example given above, the model name is \begin_inset Quotes eld \end_inset xfer \begin_inset Quotes erd \end_inset , but the C function is \begin_inset Quotes eld \end_inset ucm_xfer \begin_inset Quotes erd \end_inset . Note that when you subsequently write the model function in the Model Definitio n File, this name must agree with that of the function (i.e., \begin_inset Quotes eld \end_inset ucm_xfer \begin_inset Quotes erd \end_inset ), or an error will result in the linking step. \end_layout \begin_layout Subsubsection SPICE Model Name \end_layout \begin_layout Standard The SPICE model name is a valid SPICE identifier that will be used on SPICE .MODEL cards to refer to this code model. It may or may not be the same as the C function name. It is introduced by the \begin_inset Quotes eld \end_inset Spice_Model_Name: \begin_inset Quotes erd \end_inset keyword followed by a valid SPICE identifier. \end_layout \begin_layout Paragraph Description \end_layout \begin_layout Standard The description string is used to describe the purpose and function of the code model. It is introduced by the \begin_inset Quotes eld \end_inset Description: \begin_inset Quotes erd \end_inset keyword followed by a C string literal. \end_layout \begin_layout Subsection The Port Table \end_layout \begin_layout Standard The port table is introduced by the \begin_inset Quotes eld \end_inset Port_Table: \begin_inset Quotes erd \end_inset keyword. It defines the set of valid ports available to the code model. The following sections define the valid fields that may be specified in the port table. \end_layout \begin_layout Subsubsection Port Name \end_layout \begin_layout Standard The port name is a valid SPICE identifier. It is introduced by the \begin_inset Quotes eld \end_inset Port_Name: \begin_inset Quotes erd \end_inset keyword followed by the name of the port. Note that this port name will be used to obtain and return input and output values within the model function. This will be discussed in more detail in the next section. \end_layout \begin_layout Subsubsection Description \end_layout \begin_layout Standard The description string is used to describe the purpose and function of the code model. It is introduced by the \begin_inset Quotes eld \end_inset Description: \begin_inset Quotes erd \end_inset keyword followed by a C string literal. \end_layout \begin_layout Subsubsection Direction \end_layout \begin_layout Standard The direction of a port specifies the data flow direction through the port. A direction must be one of \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset out \begin_inset Quotes erd \end_inset , or \begin_inset Quotes eld \end_inset inout \begin_inset Quotes erd \end_inset . It is introduced by the \begin_inset Quotes eld \end_inset Direction: \begin_inset Quotes erd \end_inset keyword followed by a valid direction value. \end_layout \begin_layout Subsubsection Default Type \end_layout \begin_layout Standard The Default_Type field specifies the type of a port. These types are identical to those used to define the port types on a SPICE deck instance card (see Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Type-Modifiers" \end_inset ), but without the percent sign (%) preceding them. Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Types" \end_inset summarizes the allowable types. \end_layout \begin_layout Subsubsection Allowed Types \end_layout \begin_layout Standard A port must specify the types it is allowed to assume. An allowed type value must be a list of type names (a blank or comma separated list of names delimited by square brackets, e.g. \begin_inset Quotes eld \end_inset [v vd i id] \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset [d] \begin_inset Quotes erd \end_inset ). The type names must be taken from those listed in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Types" \end_inset . \end_layout \begin_layout Subsubsection Vector \end_layout \begin_layout Standard A port which is a vector can be thought of as a bus. The Vector field is introduced with the \begin_inset Quotes eld \end_inset Vector: \begin_inset Quotes erd \end_inset keyword followed by a Boolean value: \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Default Types \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Valid Directions \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout d \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout digital \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout g \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance (VCCS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout differential conductance (VCCS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance (CCVS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout differential resistance (CCVS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout id \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout differential current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout v \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout differential voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout user-defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout in or out \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Port-Types" \end_inset Port Types \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The values \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset are equivalent and specify that this port is a vector. Likewise, \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset specify that the port is not a vector. Vector ports must have a corresponding vector bounds field that specifies valid sizes of the vector port. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "sub:Ports-Vector-Bounds" \end_inset Vector Bounds \end_layout \begin_layout Standard If a port is a vector, limits on its size must be specified in the vector bounds field. The Vector Bounds field specifies the upper and lower bounds on the size of a vector. The Vector Bounds field is usually introduced by the \begin_inset Quotes eld \end_inset Vector_Bounds: \begin_inset Quotes erd \end_inset keyword followed by a range of integers (e.g. \begin_inset Quotes eld \end_inset [1 7] \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset [3, 20] \begin_inset Quotes erd \end_inset ). The lower bound of the vector specifies the minimum number of elements in the vector; the upper bound specifies the maximum number of elements. If the range is unconstrained, or the associated port is not a vector, the vector bounds may be specified by a hyphen ( \begin_inset Quotes eld \end_inset - \begin_inset Quotes erd \end_inset ). Using the hyphen convention, partial constraints on the vector bound may be defined (e.g., \begin_inset Quotes eld \end_inset [2, -] \begin_inset Quotes erd \end_inset indicates that the least number of port elements allowed is two, but there is no maximum number). \end_layout \begin_layout Subsubsection Null Allowed \end_layout \begin_layout Standard In some cases, it is desirable to permit a port to remain unconnected to any electrical node in a circuit. The Null_Allowed field specifies whether this constitutes an error for a particular port. The Null_Allowed field is introduced by the \begin_inset Quotes eld \end_inset Null_Allowed: \begin_inset Quotes erd \end_inset keyword and is followed by a boolean constant: \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset . The values \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset are equivalent and specify that it is legal to leave this port unconnected. \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset specify that the port must be connected. \end_layout \begin_layout Subsection The Parameter Table \end_layout \begin_layout Standard The parameter table is introduced by the \begin_inset Quotes eld \end_inset Parameter_Table: \begin_inset Quotes erd \end_inset keyword. It defines the set of valid parameters available to the code model. The following sections define the valid fields that may be specified in the parameter table. \end_layout \begin_layout Subsubsection Parameter Name \end_layout \begin_layout Standard The parameter name is a valid SPICE identifier which will be used on SPICE .MODEL cards to refer to this parameter. It is introduced by the \begin_inset Quotes eld \end_inset Parameter_Name: \begin_inset Quotes erd \end_inset keyword followed by a valid SPICE identifier. \end_layout \begin_layout Subsubsection Description \end_layout \begin_layout Standard The description string is used to describe the purpose and function of the parameter. It is introduced by the \begin_inset Quotes eld \end_inset Description: \begin_inset Quotes erd \end_inset keyword followed by a string literal. \end_layout \begin_layout Subsubsection Data Type \end_layout \begin_layout Standard The parameter's data type is specified by the Data Type field. The Data Type field is introduced by the keyword \begin_inset Quotes eld \end_inset Data_Type: \begin_inset Quotes erd \end_inset and is followed by a valid data type. Valid data types include boolean, complex, int, real, and string. \end_layout \begin_layout Subsubsection Null Allowed \end_layout \begin_layout Standard The Null_Allowed field is introduced by the \begin_inset Quotes eld \end_inset Null_Allowed: \begin_inset Quotes erd \end_inset keyword and is followed by a boolean literal. A value of \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset specify that it is valid for the corresponding SPICE .MODEL card to omit a value for this parameter. If the parameter is omitted, the default value is used. If there is no default value, an undefined value is passed to the code model, and the PARAM_NULL( ) macro will return a value of \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset so that defaulting can be handled within the model itself. If the value of Null_Allowed is \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset , then the simulator will flag an error if the SPICE .MODEL card omits a value for this parameter. \end_layout \begin_layout Subsubsection Default Value \end_layout \begin_layout Standard If the Null_Allowed field specifies \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset for this parameter, then a default value may be specified. This value is supplied for the parameter in the event that the SPICE .MODEL card does not supply a value for the parameter. The default value must be of the correct type. The Default Value field is introduced by the \begin_inset Quotes eld \end_inset Default_Value: \begin_inset Quotes erd \end_inset keyword and is followed by a numeric, boolean, complex, or string literal, as appropriate. \end_layout \begin_layout Subsubsection Limits \end_layout \begin_layout Standard Integer and real parameters may be constrained to accept a limited range of values. The following range syntax is used whenever such a range of values is required. A range is specified by a square bracket followed by a value representing a lower bound separated by space from another value representing an upper bound and terminated with a closing square bracket (e.g. \begin_inset Quotes erd \end_inset [0 10] \begin_inset Quotes erd \end_inset ). The lower and upper bounds are inclusive. Either the lower or the upper bound may be replaced by a hyphen ( \begin_inset Quotes eld \end_inset - \begin_inset Quotes erd \end_inset ) to indicate that the bound is unconstrained (e.g. \begin_inset Quotes eld \end_inset [10 -] \begin_inset Quotes erd \end_inset is read as \begin_inset Quotes eld \end_inset the range of values greater than or equal to 10 \begin_inset Quotes erd \end_inset ). For a totally unconstrained range, a single hyphen with no surrounding brackets may be used. The parameter value limit is introduced by the \begin_inset Quotes eld \end_inset Limits: \begin_inset Quotes erd \end_inset keyword and is followed by a range. \end_layout \begin_layout Subsubsection Vector \end_layout \begin_layout Standard The Vector field is used to specify whether a parameter is a vector or a scalar. Like the PORT TABLE Vector field, it is introduced by the \begin_inset Quotes eld \end_inset Vector: \begin_inset Quotes erd \end_inset keyword and followed by a boolean value. \begin_inset Quotes eld \end_inset TRUE \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset YES \begin_inset Quotes erd \end_inset specify that the parameter is a vector. \begin_inset Quotes eld \end_inset FALSE \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset NO \begin_inset Quotes erd \end_inset specify that it is a scalar. \end_layout \begin_layout Subsubsection Vector Bounds \end_layout \begin_layout Standard The valid sizes for a vector parameter are specified in the same manner as are port sizes (see Section \begin_inset CommandInset ref LatexCommand ref reference "sub:Ports-Vector-Bounds" \end_inset ). However, in place of using a numeric range to specify valid vector bounds it is also possible to specify the name of a port. When a parameter's vector bounds are specified in this way, the size of the vector parameter must be the same as the associated vector port. \end_layout \begin_layout Subsection Static Variable Table \end_layout \begin_layout Standard The Static Variable table is introduced by the \begin_inset Quotes eld \end_inset Static_Var_Table: \begin_inset Quotes erd \end_inset keyword. It defines the set of valid static variables available to the code model. These are variables whose values are retained between successive invocations of the code model by the simulator. The following sections define the valid fields that may be specified in the Static Variable Table. \end_layout \begin_layout Subsubsection Name \end_layout \begin_layout Standard The Static variable name is a valid C identifier that will be used in the code model to refer to this static variable. It is introduced by the \begin_inset Quotes eld \end_inset Static_Var_Name: \begin_inset Quotes erd \end_inset keyword followed by a valid C identifier. \end_layout \begin_layout Subsubsection Description \end_layout \begin_layout Standard The description string is used to describe the purpose and function of the static variable. It is introduced by the \begin_inset Quotes eld \end_inset Description: \begin_inset Quotes erd \end_inset keyword followed by a string literal. \end_layout \begin_layout Subsubsection Data Type \end_layout \begin_layout Standard The static variable's data type is specified by the Data Type field. The Data Type field is introduced by the keyword \begin_inset Quotes eld \end_inset Data_Type: \begin_inset Quotes erd \end_inset and is followed by a valid data type. Valid data types include boolean, complex, int, real, string and pointer. \end_layout \begin_layout Standard Note that pointer types are used to specify vector values; in such cases, the allocation of memory for vectors must be handled by the code model through the use of the malloc() or calloc() C function. Such allocation must only occur during the initialization cycle of the model (which is identified in the code model by testing the INIT macro for a value of TRUE). Otherwise, memory will be unnecessarily allocated each time the model is called. \end_layout \begin_layout Standard Following is an example of the method used to allocate memory to be referenced by a static pointer variable \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset and subsequently use the allocated memory. The example assumes that the value of \begin_inset Quotes eld \end_inset size \begin_inset Quotes erd \end_inset is at least 2, else an error would result. The references to \family typewriter STATIC_VAR(x) \family default that appear in the example illustrate how to set the value of, and then access, a static variable named \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset . In order to use the variable \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset in this manner, it must be declared in the Static Variable Table of the code model's Interface Specification File. \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout /* Define local pointer variable */ \end_layout \begin_layout Plain Layout double *local.x; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Allocate storage to be referenced by the static variable x. */ \end_layout \begin_layout Plain Layout /* Do this only if this is the initial call of the code model. */ \end_layout \begin_layout Plain Layout if (INIT == TRUE) { \end_layout \begin_layout Plain Layout STATIC_VAR(x) = calloc(size, sizeof(double)); \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Assign the value from the static pointer value to the local */ \end_layout \begin_layout Plain Layout /* pointer variable. */ \end_layout \begin_layout Plain Layout local_x = STATIC_VAR(x); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Assign values to first two members of the array */ \end_layout \begin_layout Plain Layout local_x[0] = 1.234; \end_layout \begin_layout Plain Layout local_x[1] = 5.678; \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Model-Definition-File" \end_inset Model Definition File \end_layout \begin_layout Standard The Model Definition File is a C source code file that defines a code model's behavior given input values which are passed to it by the simulator. The file itself is always given the name \begin_inset Quotes eld \end_inset cfunc.mod \begin_inset Quotes erd \end_inset . In order to allow for maximum flexibility, passing of input, output, and simulator-specific information is handled through accessor macros, which are described below. In addition, certain predefined library functions (e.g. smoothing interpolators, complex arithmetic routines) are included in the simulator in order to ease the burden of the code model programmer. These are also described below. \end_layout \begin_layout Subsection Macros \end_layout \begin_layout Standard The use of the accessor macros is illustrated in the following example. Note that the argument to most accessor macros is the name of a parameter or port as defined in the Interface Specification File. Note also that all accessor macros except \begin_inset Quotes eld \end_inset ARGS \begin_inset Quotes erd \end_inset resolve to an lvalue (C language terminology for something that can be assigned a value). Accessor macros do not implement expressions or assignments. \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout void code.model(ARGS) /* private structure accessed by \end_layout \begin_layout Plain Layout accessor macros */ \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout /* The following code fragments are intended to show how */ \end_layout \begin_layout Plain Layout /* information in the argument list is accessed. The reader */ \end_layout \begin_layout Plain Layout /* should not attempt to relate one fragment to another. */ \end_layout \begin_layout Plain Layout /* Consider each fragment as a separate example. */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout double p,/* variable for use in the following code fragments */ \end_layout \begin_layout Plain Layout x, /* variable for use in the following code fragments */ \end_layout \begin_layout Plain Layout y; /* variable for use in the following code fragments */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout int i, /* indexing variable for use in the following */ \end_layout \begin_layout Plain Layout j; /* indexing variable for use in the following */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout UDN_Example_Type *a_ptr, /* A pointer used to access a User- \end_layout \begin_layout Plain Layout Defined Node type */ \end_layout \begin_layout Plain Layout *y_ptr; /* A pointer used to access a User- \end_layout \begin_layout Plain Layout Defined Node type */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Initializing and outputting a User-Defined Node result */ \end_layout \begin_layout Plain Layout if(INIT) { \end_layout \begin_layout Plain Layout OUTPUT(y) = malloc(sizeof(user.defined.struct)); \end_layout \begin_layout Plain Layout y_ptr = OUTPUT(y); \end_layout \begin_layout Plain Layout y_ptr->component1 = 0.0; \end_layout \begin_layout Plain Layout y_ptr->component2 = 0.0; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout else { \end_layout \begin_layout Plain Layout y_ptr = OUTPUT(y); \end_layout \begin_layout Plain Layout y_ptr->component1 = x1; \end_layout \begin_layout Plain Layout y_ptr->component2 = x2; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Determining analysis type */ \end_layout \begin_layout Plain Layout if(ANALYSIS == AC) { \end_layout \begin_layout Plain Layout /* Perform AC analysis-dependent operations here */ \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing a parameter value from the .model card */ \end_layout \begin_layout Plain Layout p = PARAM(gain); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing a vector parameter from the .model card */ \end_layout \begin_layout Plain Layout for(i = 0; i < PARAM_SIZE(in_offset); i++) \end_layout \begin_layout Plain Layout p = PARAM(in_offset[i]); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing the value of a simple real-valued input */ \end_layout \begin_layout Plain Layout x = INPUT(a); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing a vector input and checking for null port */ \end_layout \begin_layout Plain Layout if( ! PORT_NULL(a)) \end_layout \begin_layout Plain Layout for(i = 0; i < PORT_SIZE(a); i++) \end_layout \begin_layout Plain Layout x = INPUT(a[i]); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing a digital input */ \end_layout \begin_layout Plain Layout x = INPUT(a); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Accessing the value of a User-Defined Node input... */ \end_layout \begin_layout Plain Layout /* This node type includes two elements in its definition. */ \end_layout \begin_layout Plain Layout a_ptr = INPUT(a); \end_layout \begin_layout Plain Layout x = a_ptr->component1; \end_layout \begin_layout Plain Layout y = a_ptr->component2; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting a simple real-valued result */ \end_layout \begin_layout Plain Layout OUTPUT(out1) = 0.0; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting a vector result and checking for null */ \end_layout \begin_layout Plain Layout if( ! PORT_NULL(a)) \end_layout \begin_layout Plain Layout for(i = 0; i < PORT.SIZE(a); i++) \end_layout \begin_layout Plain Layout OUTPUT(a[i]) = 0.0; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting the partial of output out1 w.r.t. input a */ \end_layout \begin_layout Plain Layout PARTIAL(out1,a) = PARAM(gain); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting the partial of output out2(i) w.r.t. input b(j) */ \end_layout \begin_layout Plain Layout for(i = 0; i < PORT_SIZE(out2); i++) { \end_layout \begin_layout Plain Layout for(j = 0; j < PORT_SIZE(b); j++) { \end_layout \begin_layout Plain Layout PARTIAL(out2[i],b[j]) = 0.0; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting gain from input c to output out3 in an \end_layout \begin_layout Plain Layout AC analysis */ \end_layout \begin_layout Plain Layout complex_gain_real = 1.0; \end_layout \begin_layout Plain Layout complex_gain_imag = 0.0; \end_layout \begin_layout Plain Layout AC_GAIN(out3,c) = complex_gain; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting a digital result */ \end_layout \begin_layout Plain Layout OUTPUT_STATE(out4) = ONE; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Outputting the delay for a digital or user-defined output */ \end_layout \begin_layout Plain Layout OUTPUT_DELAY(out5) = 1.0e-9; \end_layout \begin_layout Plain Layout } \end_layout \end_inset \end_layout \begin_layout Subsubsection Macro Definitions \end_layout \begin_layout Standard The full set of accessor macros is listed below. Arguments shown in parenthesis are examples only. Explanations of the accessor macros are provided in the subsections below. \end_layout \begin_layout LyX-Code \series bold Circuit Data: \end_layout \begin_layout LyX-Code ARGS \end_layout \begin_layout LyX-Code CALL_TYPE \end_layout \begin_layout LyX-Code INIT \end_layout \begin_layout LyX-Code ANALYSIS \end_layout \begin_layout LyX-Code FIRST_TIMEPOINT \end_layout \begin_layout LyX-Code TIME \end_layout \begin_layout LyX-Code T(n) \end_layout \begin_layout LyX-Code RAD_FREQ \end_layout \begin_layout LyX-Code TEMPERATURE \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Parameter Data: \end_layout \begin_layout LyX-Code PARAM(gain) \end_layout \begin_layout LyX-Code PARAM_SIZE(gain) \end_layout \begin_layout LyX-Code PARAM_NULL(gain) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Port Data: \end_layout \begin_layout LyX-Code PORT_SIZE(a) \end_layout \begin_layout LyX-Code PORT_NULL(a) \end_layout \begin_layout LyX-Code LOAD(a) \end_layout \begin_layout LyX-Code TOTAL_LOAD(a) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Input Data: \end_layout \begin_layout LyX-Code INPUT(a) \end_layout \begin_layout LyX-Code INPUT_STATE(a) \end_layout \begin_layout LyX-Code INPUT_STRENGTH(a) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Output Data: \end_layout \begin_layout LyX-Code OUTPUT(y) \end_layout \begin_layout LyX-Code OUTPUT_CHANGED(a) \end_layout \begin_layout LyX-Code OUTPUT_DELAY(y) \end_layout \begin_layout LyX-Code OUTPUT_STATE(a) \end_layout \begin_layout LyX-Code OUTPUT_STRENGTH(a) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Partial Derivatives: \end_layout \begin_layout LyX-Code PARTIAL(y,a) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold AC Gains: \end_layout \begin_layout LyX-Code AC_GAIN(y,a) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Static Variable: \end_layout \begin_layout LyX-Code STATIC_VAR(x) \end_layout \begin_layout Subsubsection Circuit Data \end_layout \begin_layout LyX-Code ARGS \end_layout \begin_layout LyX-Code CALL_TYPE \end_layout \begin_layout LyX-Code INIT \end_layout \begin_layout LyX-Code ANALYSIS \end_layout \begin_layout LyX-Code FIRST_TIMEPOINT \end_layout \begin_layout LyX-Code TIME \end_layout \begin_layout LyX-Code T(n) \end_layout \begin_layout LyX-Code RAD_FREQ \end_layout \begin_layout LyX-Code TEMPERATURE \end_layout \begin_layout Description ARGS is a macro which is passed in the argument list of every code model. It is there to provide a way of referencing each model to all of the remaining macro values. It must be present in the argument list of every code model; it must also be the only argument present in the argument list of every code model. \end_layout \begin_layout Description CALL_TYPE is a macro which returns one of two possible symbolic constants. These are EVENT and ANALOG. Testing may be performed by a model using CALL TYPE to determine whether it is being called by the analog simulator or the event-driven simulator. This will, in general, only be of value to a hybrid model such as the adc bridge or the dac bridge. \end_layout \begin_layout Description INIT is an integer (int) that takes the value 1 or 0 depending on whether this is the first call to the code model instance or not, respectively. \end_layout \begin_layout Description ANALYSIS is an enumerated integer that takes values of DC, AC, or TRANSIENT. FIRST TIMEPOINT is an integer that takes the value 1 or 0 depending on whether this is the first call for this instance at the current analysis step (i.e., time-point) or not, respectively. \end_layout \begin_layout Description TIME is a double representing the current analysis time in a transient analysis. T(n) is a double vector giving the analysis time for a specified time-point in a transient analysis, where n takes the value 0 or 1. T(0) is equal to TIME. T(1) is the last accepted time-point. (T(0) - T(1)) is the time-step (i.e., the delta-time value) associated with the current time. \end_layout \begin_layout Description RAD_FREQ is a double representing the current analysis frequency in an AC analysis expressed in units of radians per second. \end_layout \begin_layout Description TEMPERATURE is a double representing the current analysis temperature. \end_layout \begin_layout Subsubsection Parameter Data \end_layout \begin_layout LyX-Code PARAM(gain) \end_layout \begin_layout LyX-Code PARAM_SIZE(gain) \end_layout \begin_layout LyX-Code PARAM_NULL(gain) \end_layout \begin_layout Description PARAM(gain) resolves to the value of the scalar (i.e., non-vector) parameter \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset which was defined in the Interface Specification File tables. The type of \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset is the type given in the ifspec.ifs file. The same accessor macro can be used regardless of type. If \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset is a string, then PARAM(gain) would resolve to a pointer. PARAM(gain[n]) resolves to the value of the nth element of a vector parameter \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Description PARAM_SIZE(gain) resolves to an integer (int) representing the size of the \begin_inset Quotes eld \end_inset gain \begin_inset Quotes erd \end_inset vector (which was dynamically determined when the SPICE deck was read). PARAM_SIZE(gain) is undefined if gain is a scalar. \end_layout \begin_layout Description PARAM_NULL(gain) resolves to an integer with value 0 or 1 depending on whether a value was specified for gain, or whether the value is defaulted, respectively. \end_layout \begin_layout Subsubsection Port Data \end_layout \begin_layout LyX-Code PORT_SIZE(a) \end_layout \begin_layout LyX-Code PORT_NULL(a) \end_layout \begin_layout LyX-Code LOAD(a) \end_layout \begin_layout LyX-Code TOTAL_LOAD(a) \end_layout \begin_layout Description PORT_SIZE(a) resolves to an integer (int) representing the size of the \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset port (which was dynamically determined when the SPICE deck was read). PORT_SIZE(a) is undefined if gain is a scalar. \end_layout \begin_layout Description PORT_NULL(a) resolves to an integer (int) with value 0 or 1 depending on whether the SPICE deck has a node specified for this port, or has specified that the port is null, respectively. \end_layout \begin_layout Description LOAD(a) is used in a digital model to post a capacitive load value to a particular input or output port during the INIT pass of the simulator. All values posted for a particular event-driven node using the LOAD() macro are summed, producing a total load value which \end_layout \begin_layout Description TOTAL_LOAD(a) returns a double value which represents the total capacitive load seen on a specified node to which a digital code model is connected. This information may be used after the INIT pass by the code model to modify the delays it posts with its output states and strengths. Note that this macro can also be used by non-digital event-driven code models (see LOAD(), above). \end_layout \begin_layout Subsubsection Input Data \end_layout \begin_layout LyX-Code INPUT(a) \end_layout \begin_layout LyX-Code INPUT_STATE(a) \end_layout \begin_layout LyX-Code INPUT_STRENGTH(a) \end_layout \begin_layout Description INPUT(a) resolves to the value of the scalar input \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset that was defined in the Interface Specification File tables ( \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset can be either a scalar port or a port value from a vector; in the latter case, the notation used would be \begin_inset Quotes eld \end_inset a[i] \begin_inset Quotes erd \end_inset , where \begin_inset Quotes eld \end_inset i \begin_inset Quotes erd \end_inset is the index value for the port). The type of \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset is the type given in the ifspec.ifs file. The same accessor macro can be used regardless of type. \end_layout \begin_layout Description INPUT_STATE(a) resolves to the state value defined for digital node types. These will be one of the symbolic constants ZERO, ONE, or UNKNOWN. \end_layout \begin_layout Description INPUT_STRENGTH(a) resolves to the strength with which a digital input node is being driven. This is determined by a resolution algorithm which looks at all outputs to a node and determines its final driven strength. This value in turn is passed to a code model when requested by this macro. Possible strength values are: \begin_inset Newline newline \end_inset 1. STRONG \begin_inset Newline newline \end_inset 2. RESISTIVE \begin_inset Newline newline \end_inset 3. HI_IMPEDANCE \begin_inset Newline newline \end_inset 4. UNDETERMINED \end_layout \begin_layout Subsubsection Output Data \end_layout \begin_layout LyX-Code OUTPUT(y) \end_layout \begin_layout LyX-Code OUTPUT_CHANGED(a) \end_layout \begin_layout LyX-Code OUTPUT_DELAY(y) \end_layout \begin_layout LyX-Code OUTPUT_STATE(a) \end_layout \begin_layout LyX-Code OUTPUT_STRENGTH(a) \end_layout \begin_layout Description OUTPUT(y) resolves to the value of the scalar output \begin_inset Quotes eld \end_inset y \begin_inset Quotes erd \end_inset that was defined in the Interface Specification File tables. The type of \begin_inset Quotes eld \end_inset y \begin_inset Quotes erd \end_inset is the type given in the ifspec.ifs file. The same accessor macro can be used regardless of type. If \begin_inset Quotes eld \end_inset y \begin_inset Quotes erd \end_inset is a vector, then OUTPUT(y) would resolve to a pointer. \end_layout \begin_layout Description OUTPUT_CHANGED(a) may be assigned one of two values for any particular output from a digital code model. If assigned the value TRUE (the default), then an output state, strength and delay must be posted by the model during the call. If, on the other hand, no change has occurred during that pass, the OUTPUT_CHAN GED(a) value for an output can be set to FALSE. In this case, no state, strength or delay values need subsequently be posted by the model. Remember that this macro applies to a single output port. If a model has multiple outputs that have not changed, OUTPUT_CHANGED(a) must be set to FALSE for each of them. \end_layout \begin_layout Description OUTPUT_DELAY(y) may be assigned a double value representing a delay associated with a particular digital or User-Defined Node output port. Note that this macro must be set for each digital or User-Defined Node output from a model during each pass, unless the OUTPUT_CHANGED(a) macro is invoked (see above). Note also that a non-zero value must be assigned to OUTPUT_DELAY(). Assigning a value of zero (or a negative value) will cause an error. \end_layout \begin_layout Description OUTPUT_STATE(a) may be assigned a state value for a digital output node. Valid values are ZERO, ONE, and UNKNOWN. This is the normal way of posting an output state from a digital code model. \end_layout \begin_layout Description OUTPUT_STRENGTH(a) may be assigned a strength value for a digital output node. This is the normal way of posting an output strength from a digital code model. Valid values are: \begin_inset Newline newline \end_inset 1. STRONG \begin_inset Newline newline \end_inset 2. RESISTIVE \begin_inset Newline newline \end_inset 3. HI_IMPEDANCE \begin_inset Newline newline \end_inset 4. UNDETERMINED \end_layout \begin_layout Subsubsection Partial Derivatives \end_layout \begin_layout LyX-Code PARTIAL(y,a) \end_layout \begin_layout LyX-Code PARTIAL(y[n],a) \end_layout \begin_layout LyX-Code PARTIAL(y,a[m]) \end_layout \begin_layout LyX-Code PARTIAL(y[n],a[m]) \end_layout \begin_layout Description PARTIAL(y,a) resolves to the value of the partial derivative of scalar output \begin_inset Quotes eld \end_inset y \begin_inset Quotes erd \end_inset with respect to scalar input \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset . The type is always double since partial derivatives are only defined for nodes with real valued quantities (i.e., analog nodes). \end_layout \begin_layout Standard The remaining uses of PARTIAL are shown for the cases in which either the output, the input, or both are vectors. \end_layout \begin_layout Standard Partial derivatives are required by the simulator to allow it to solve the non-linear equations that describe circuit behavior for analog nodes. Since coding of partial derivatives can become difficult and error-prone for complex analog models, you may wish to consider using the cm analog auto partial() code model support function instead of using this macro. \end_layout \begin_layout Subsubsection AC Gains \end_layout \begin_layout LyX-Code AC_GAIN(y,a) \end_layout \begin_layout LyX-Code AC_GAIN(y[n],a) \end_layout \begin_layout LyX-Code AC_GAIN(y,a[m]) \end_layout \begin_layout LyX-Code AC_GAIN(y[n],a[m]) \end_layout \begin_layout Description AC_GAIN(y,a) resolves to the value of the AC analysis gain of scalar output \begin_inset Quotes eld \end_inset y \begin_inset Quotes erd \end_inset from scalar input \begin_inset Quotes eld \end_inset a \begin_inset Quotes erd \end_inset . The type is always a structure ( \begin_inset Quotes eld \end_inset Complex_t \begin_inset Quotes erd \end_inset ) defined in the standard code model header file: \end_layout \begin_layout LyX-Code typedef struct Complex_s { \end_layout \begin_layout LyX-Code double real; /* The real part of the complex number */ \end_layout \begin_layout LyX-Code double imag; /* The imaginary part of the complex number */ \end_layout \begin_layout LyX-Code }Complex_t; \end_layout \begin_layout Standard The remaining uses of AC_GAIN are shown for the cases in which either the output, the input, or both are vectors. \end_layout \begin_layout Subsubsection Static Variables \end_layout \begin_layout LyX-Code STATIC_VAR(x) \end_layout \begin_layout Description STATIC_VAR(x) resolves to an lvalue or a pointer which is assigned the value of some scalar code model result or state defined in the Interface Spec File tables, or a pointer to a value or a vector of values. The type of \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset is the type given in the Interface Specification File. The same accessor macro can be used regardless of type since it simply resolves to an lvalue. If \begin_inset Quotes eld \end_inset x \begin_inset Quotes erd \end_inset is a vector, then STATIC_VAR(x) would resolve to a pointer. In this case, the code model is responsible for allocating storage for the vector and assigning the pointer to the allocated storage to STATIC_VAR(x). \end_layout \begin_layout Subsubsection Accessor Macros \end_layout \begin_layout Standard Table \begin_inset CommandInset ref LatexCommand ref reference "tab:Accessor-macros" \end_inset describes the accessor macros available to the Model Definition File programmer and their C types. The PARAM and STATIC_VAR macros, whose types are labeled CD (context dependent) , return the type defined in the Interface Specification File. Arguments listed with \begin_inset Quotes eld \end_inset [i] \begin_inset Quotes erd \end_inset take an optional square bracket delimited index if the corresponding port or parameter is a vector. The index may be any C expression - possibly involving calls to other accessor macros (e.g., \begin_inset Quotes erd \end_inset \family typewriter OUTPUT(out[PORT_SIZE(out)-1]) \family default \begin_inset Quotes erd \end_inset ) \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Args \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none AC_GAIN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Complex_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none y[i],x[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none AC gain of output y with respect to input x \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ANALYSIS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type of analysis: DC, AC, TRANSIENT. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ARGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mif_Private_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Standard argument to all code model function. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none CALL \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none TYPE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Type of model evaluation call: ANALOG or EVENT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout INIT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Boolean_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Is this the first call to the model? \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout INPUT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double or void* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Value of analog input port, or value of structure pointer for User-Defined Node port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout INPUT_STATE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none State of a digital input: ZERO, ONE, or UNKNOWN. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout INPUT_STRENGHT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Strength of digital input: STRONG, RESISTIVE, HI IMPEDANCE, or UNDETERMINED \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout INPUT_TYPE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout char* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The port type of the input. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LOAD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The digital load value placed on a port by this model. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MESSAGE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout char* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A message output by a model on an event-driven node. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double or void* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Value of the analog output port or value of structure pointer for User-Defined Node port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_CHANGED \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Boolean_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Has a new value been assigned to this event-driven output by the model? \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_DELAY \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Delay in seconds for an event-driven output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_STATE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout State of a digital output: ZERO, ONE, or UNKNOWN. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_STRENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout enum \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Strength of digital output: STRONG, RESISTIVE, HI_IMPEDANCE, or UNDETERMINED. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_TYPE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout char* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The port type of the output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value of the parameter. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM_NULL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Boolean_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Was the parameter not included on the SPICE .model \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit card ? \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM_SIZE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout int \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Size of parameter vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARTIAL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout y[i],x[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Partial derivative of output y with respect to input x. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PORT_NULL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mif_Boolean_t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Has this port been specified as unconnected? \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PORT_SIZE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout int \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Size of port vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RAD_FREQ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current analysis frequency in radians per second. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STATIC_VAR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Value of a static variable \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STATIC_VAR_SIZE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout int \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Size of static var vector (currently unused). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout T(n) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout int \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout index \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Current and previous analysis times (T(0) = TIME = current analysis time, T(1) = previous analysis time) \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEMPERATURE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Current analysis temperature \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TIME \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Current analysis time (same as T(0)) \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TOTAL_LOAD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout name[i] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The total of all loads on the node attached to this event driven port. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:Accessor-macros" \end_inset Accessor macros \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Subsection Function Library \end_layout \begin_layout Subsubsection Overview \end_layout \begin_layout Standard Aside from the accessor macros, the simulator also provides a library of functions callable from within code models. The header file containing prototypes to these functions is automatically inserted into the Model Definition File for you. The complete list of available functions follows: \end_layout \begin_layout LyX-Code \series bold Smoothing Functions: \end_layout \begin_layout LyX-Code void cm_smooth_corner \end_layout \begin_layout LyX-Code void cm_smooth_discontinuity \end_layout \begin_layout LyX-Code double cm_smooth_pwl \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Model State Storage Functions: \end_layout \begin_layout LyX-Code void cm_analog_alloc \end_layout \begin_layout LyX-Code void cm_event_alloc \end_layout \begin_layout LyX-Code void *cm_analog_get_ptr \end_layout \begin_layout LyX-Code void *cm_event_get_ptr \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Integration and Convergence Functions: \end_layout \begin_layout LyX-Code int cm_analog_integrate \end_layout \begin_layout LyX-Code int cm_analog_converge \end_layout \begin_layout LyX-Code void cm_analog_not_converged \end_layout \begin_layout LyX-Code void cm_analog_auto_partial \end_layout \begin_layout LyX-Code double cm_analog_ramp_factor \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Message Handling Functions: \end_layout \begin_layout LyX-Code char *cm_message_get_errmsg \end_layout \begin_layout LyX-Code void cm_message_send \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Breakpoint Handling Functions: \end_layout \begin_layout LyX-Code int cm_analog_set_temp_bkpt \end_layout \begin_layout LyX-Code int cm_analog_set_perm_bkpt \end_layout \begin_layout LyX-Code int cm_event_queue \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Special Purpose Functions: \end_layout \begin_layout LyX-Code void cm_climit_fcn \end_layout \begin_layout LyX-Code double cm_netlist_get_c \end_layout \begin_layout LyX-Code double cm_netlist_get_l \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold Complex Math Functions: \end_layout \begin_layout LyX-Code complex_t cm_complex_set \end_layout \begin_layout LyX-Code complex_t cm_complex_add \end_layout \begin_layout LyX-Code complex_t cm_complex_sub \end_layout \begin_layout LyX-Code complex_t cm_complex_mult \end_layout \begin_layout LyX-Code complex_t cm_complex_div \end_layout \begin_layout Subsubsection Smoothing Functions \end_layout \begin_layout LyX-Code void \end_layout \begin_layout LyX-Code cm_smooth_corner(x_input, x_center, y_center, domain, \end_layout \begin_layout LyX-Code lower_slope, upper_slope, y_output, dy_dx) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double x_input; /* The value of the x input */ \end_layout \begin_layout LyX-Code double x_center; /* The x intercept of the two slopes */ \end_layout \begin_layout LyX-Code double y_center; /* The y intercept of the two slopes */ \end_layout \begin_layout LyX-Code double domain; /* The smoothing domain */ \end_layout \begin_layout LyX-Code double lower_slope; /* The lower slope */ \end_layout \begin_layout LyX-Code double upper_slope; /* The upper slope */ \end_layout \begin_layout LyX-Code double *y_output; /* The smoothed y output */ \end_layout \begin_layout LyX-Code double *dy_dx; /* The partial of y wrt x */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void \end_layout \begin_layout LyX-Code cm_smooth_discontinuity(x_input, x_lower, y_lower, x_upper, y_upper \end_layout \begin_layout LyX-Code y_output, dy_dx) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double x_input; /* The x value at which to compute y */ \end_layout \begin_layout LyX-Code double x_lower; /* The x value of the lower corner */ \end_layout \begin_layout LyX-Code double y_lower; /* The y value of the lower corner */ \end_layout \begin_layout LyX-Code double x_upper; /* The x value of the upper corner */ \end_layout \begin_layout LyX-Code double y_upper; /* The y value of the upper corner */ \end_layout \begin_layout LyX-Code double *y_output; /* The computed smoothed y value */ \end_layout \begin_layout LyX-Code double *dy_dx; /* The partial of y wrt x */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double \end_layout \begin_layout LyX-Code cm_smooth_pwl(x_input, x, y, size, input_domain, dout_din) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double x_input; /* The x input value */ \end_layout \begin_layout LyX-Code double *x; /* The vector of x values */ \end_layout \begin_layout LyX-Code double *y; /* The vector of y values */ \end_layout \begin_layout LyX-Code int size; /* The size of the xy vectors */ \end_layout \begin_layout LyX-Code double input_domain; /* The smoothing domain */ \end_layout \begin_layout LyX-Code double *dout_din; /* The partial of the output wrt the input */ \end_layout \begin_layout Standard \series bold cm_smooth_corner() \series default automates smoothing between two arbitrarily-sloped lines that meet at a single center point. You specify the center point (x_center, y_center), plus a domain (x-valued delta) above and below x_center. This defines a smoothing region about the center point. Then, the slopes of the meeting lines outside of this smoothing region are specified (lower_slope, upper_slope). The function then interpolates a smoothly-varying output (*y_output) and its derivative (*dy_dx) for the x_input value. This function helps to automate the smoothing of piecewise-linear functions, for example. Such smoothing aids the simulator in achieving convergence. \end_layout \begin_layout Standard \series bold cm_smooth_discontinuity() \series default allows you to obtain a smoothly-transitioning output (*y_output) that varies between two static values (y_lower, y_upper) as an independent variable (x_input) transitions between two values (x_lower, x_upper). This function is useful in interpolating between resistances or voltage levels that change abruptly between two values. \end_layout \begin_layout Standard \series bold cm_smooth_pwl() \series default duplicates much of the functionality of the predefined pwl code model. The cm smooth pwl() takes an input value plus x-coordinate and y-coordinate vector values along with the total number of coordinate points used to describe the piecewise linear transfer function and returns the interpolated or extrapolated value of the output based on that transfer function. More detail is available by looking at the description of the pwl code model. Note that the output value is the function's returned value. \end_layout \begin_layout Subsubsection Model State Storage Functions \end_layout \begin_layout LyX-Code void cm_analog_alloc(tag, size) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int tag; /* The user-specified tag for this block of memory */ \end_layout \begin_layout LyX-Code int size; /* The number of bytes to allocate */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void cm_event_alloc(tag, size) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int tag; /* The user-specified tag for the memory block */ \end_layout \begin_layout LyX-Code int size; /* The number of bytes to be allocated */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void *cm_analog_get_ptr(tag, timepoint) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int tag; /* The user-specified tag for this block of memory */ \end_layout \begin_layout LyX-Code int timepoint; /* The timepoint of interest - 0=current 1=previous */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void *cm_event_get_ptr(tag, timepoint) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int tag; /* The user-specified tag for the memory block */ \end_layout \begin_layout LyX-Code int timepoint; /* The timepoint - 0=current, 1=previous */ \end_layout \begin_layout Standard \series bold cm_analog_alloc() \series default and \series bold cm_event_alloc() \series default allow you to allocate storage space for analog and event-driven model state information. The storage space is not static, but rather represents a storage vector of two values which rotate with each accepted simulator time-point evaluation. This is explained more fully below. The \begin_inset Quotes eld \end_inset tag \begin_inset Quotes erd \end_inset parameter allows you to specify an integer tag when allocating space. This allows more than one rotational storage location per model to be allocated. The \begin_inset Quotes eld \end_inset size \begin_inset Quotes erd \end_inset parameter specifies the size in bytes of the storage (computed by the C language \begin_inset Quotes eld \end_inset sizeof() \begin_inset Quotes erd \end_inset operator). Both cm_analog_alloc() and cm_event_alloc() will \series bold not \series default return pointers to the allocated space, as has been available (and buggy) from the original XSPICE code. cm_analog_alloc() should be used by an analog model; cm_event_alloc() should be used by an event-driven model. \end_layout \begin_layout Standard \series bold *cm_analog_get_ptr() \series default and \series bold *cm_event_get_ptr() \series default retrieve the pointer location of the rotational storage space previously allocated by cm_analog_alloc() or cm_event_alloc(). \series bold Important notice: \series default These functions must be called only after \series bold all \series default memory allocation (all calls to cm_analog_alloc() or cm_event_alloc()) have been done. All pointers returned between calls to memory allocation will become obsolete (point to freed memory because of an internal realloc). The functions take the integer \begin_inset Quotes eld \end_inset tag \begin_inset Quotes erd \end_inset used to allocate the space, and an integer from 0 to 1 which specifies the time-point with which the desired state variable is associated (e.g. timepoint = 0 will retrieve the address of storage for the current time-point; timepoint = 1 will retrieve the address of storage for the last accepted time-point). \series bold Note that once a model is exited, storage to the current time-point state storage location (i.e., timepoint = 0) will, upon the next time-point iteration, be rotated to the previous location (i.e., timepoint = 1). \series default When rotation is done, a copy of the old \begin_inset Quotes eld \end_inset timepoint = 0 \begin_inset Quotes erd \end_inset storage value is placed in the new \begin_inset Quotes eld \end_inset timepoint = 0 \begin_inset Quotes erd \end_inset storage location. Thus, if a value does not change for a particular iteration, specific writing to \begin_inset Quotes eld \end_inset timepoint = 0 \begin_inset Quotes erd \end_inset storage is not required. These features allow a model coder to constantly know which piece of state information is being dealt with within the model function at each time-point. \end_layout \begin_layout Subsubsection Integration and Convergence Functions \end_layout \begin_layout LyX-Code int cm_analog_integrate(integrand, integral, partial) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double integrand; /* The integrand */ \end_layout \begin_layout LyX-Code double *integral; /* The current and returned value of integral */ \end_layout \begin_layout LyX-Code double *partial; /* The partial derivative of integral wrt integrand */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int cm_analog_converge(state) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double *state; /* The state to be converged */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void cm_analog_not_converged() \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code void cm_analog_auto_partial() \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double cm_ramp_factor() \end_layout \begin_layout Standard \series bold cm_analog_integrate() \series default takes as input the integrand (the input to the integrator) and produces as output the integral value and the partial of the integral with respect to the integrand. The integration itself is with respect to time, and the pointer to the integral value must have been previously allocated using cm_analog_alloc() and *cm_analog_get_ptr(). This is required because of the need for the integrate routine itself to have access to previously-computed values of the integral. \end_layout \begin_layout Standard \series bold cm_analog_converge() \series default takes as an input the address of a state variable that was previously allocated using cm_analog_alloc() and *cm_analog_get_ptr(). The function itself serves to notify the simulator that for each time-step taken, that variable must be iterated upon until it converges. \end_layout \begin_layout Standard \series bold cm_analog_not_converged() \series default is a function that can and should be called by an analog model whenever it performs internal limiting of one or more of its inputs to aid in reaching convergence. This causes the simulator to call the model again at the current time-point and continue solving the circuit matrix. A new time-point will not be attempted until the code model returns without calling the cm_analog_not_converged() function. For circuits which have trouble reaching a converged state (often due to multiple inputs changing too quickly for the model to react in a reasonable fashion), the use of this function is virtually mandatory. \end_layout \begin_layout Standard \series bold cm_analog_auto_partial() \series default may be called at the end of a code model function in lieu of calculating the values of partial derivatives explicitly in the function. When this function is called, no values should be assigned to the PARTIAL macro since these values will be computed automatically by the simulator. The automatic calculation of partial derivatives can save considerable time in designing and coding a model, since manual computation of partial derivatives can become very complex and error-prone for some models. However, the automatic evaluation may also increase simulation run time significantly. Function cm_analog_auto_partial() causes the model to be called N additional times (for a model with N inputs) with each input varied by a small amount (1e-6 for voltage inputs and 1e-12 for current inputs). The values of the partial derivatives of the outputs with respect to the inputs are then approximated by the simulator through divided difference calculations. \end_layout \begin_layout Standard \series bold cm_analog_ramp_factor() \series default will then return a value from 0.0 to 1.0, which indicates whether or not a ramp time value requested in the SPICE analysis deck (with the use of .option ramptime=) has elapsed. If the RAMPTIME option is used, then cm_analog_ramp_factor returns a 0.0 value during the DC operating point solution and a value which is between 0.0 and 1.0 during the ramp. A 1.0 value is returned after the ramp is over or if the RAMPTIME option is not used. This value is intended as a multiplication factor to be used with all model outputs which would ordinarily experience a \begin_inset Quotes eld \end_inset power-up \begin_inset Quotes erd \end_inset transition. Currently, all sources within the simulator are automatically ramped to the "final" time-zero value if a RAMPTIME option is specified. \end_layout \begin_layout Subsubsection Message Handling Functions \end_layout \begin_layout LyX-Code char *cm_message_get_errmsg() \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int cm_message_send(char *msg) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code char *msg; /* The message to output. */ \end_layout \begin_layout Standard \series bold *cm_message_get_errmsg() \series default is a function designed to be used with other library functions to provide a way for models to handle error situations. More specifically, whenever a library function which returns type \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset is executed from a model, it will return an integer value, n. If this value is not equal to zero (0), then an error condition has occurred (likewise, functions which return pointers will return a NULL value if an error has occurred). At that point, the model can invoke *cm_message_get_errmsg to obtain a pointer to an error message. This can then in turn be displayed to the user or passed to the simulator interface through the cm_message_send() function. The C code required for this is as follows: \end_layout \begin_layout LyX-Code err = cm_analog_integrate(in, &out, &dout_din); \end_layout \begin_layout LyX-Code if (err) { \end_layout \begin_layout LyX-Code cm_message_send(cm_message_get_errmsg()); \end_layout \begin_layout LyX-Code } \end_layout \begin_layout LyX-Code else { ... \end_layout \begin_layout Standard \series bold cm_message_send() \series default sends messages to either the standard output screen or to the simulator interface, depending on which is in use. \end_layout \begin_layout Subsubsection Breakpoint Handling Functions \end_layout \begin_layout LyX-Code int cm_analog_set_perm_bkpt(time) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double time; /* The time of the breakpoint to be set */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int cm_analog_set_temp_bkpt(time) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double time; /* The time of the breakpoint to be set */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code int cm_event_queue(time) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double time; /* The time of the event to be queued */ \end_layout \begin_layout Standard \series bold cm_analog_set_perm_bkpt() \series default takes as input a time value. This value is posted to the analog simulator algorithm and is used to force the simulator to choose that value as a breakpoint at some time in the future. The simulator may choose as the next time-point a value less than the input, but not greater. Also, regardless of how many time-points pass before the breakpoint is reached, it will not be removed from posting. Thus, a breakpoint is guaranteed at the passed time value. Note that a breakpoint may also be set for a time prior to the current time, but this will result in an error if the posted breakpoint is prior to the last accepted time (i.e., T(1)). \end_layout \begin_layout Standard \series bold cm_analog_set_temp_bkpt() \series default takes as input a time value. This value is posted to the simulator and is used to force the simulator, for the next time-step only, to not exceed the passed time value. The simulator may choose as the next time-point a value less than the input, but not greater. In addition, once the next time-step is chosen, the posted value is removed regardless of whether it caused the break at the given time-point. This function is useful in the event that a time-point needs to be retracted after its first posting in order to recalculate a new breakpoint based on new input data (for controlled oscillators, controlled one-shots, etc), since temporary breakpoints automatically \begin_inset Quotes eld \end_inset go away \begin_inset Quotes erd \end_inset if not reposted each time-step. Note that a breakpoint may also be set for a time prior to the current time, but this will result in an error if the posted breakpoint is prior to the last accepted time (i.e., T(1)). \end_layout \begin_layout Standard \series bold cm_event_queue() \series default is similar to cm_analog_set_perm_bkpt(), but functions with event-driven models. When invoked, this function causes the model to be queued for calling at the specified time. All other details applicable to cm_analog_set_perm_bkpt() apply to this function as well. \end_layout \begin_layout Subsubsection Special Purpose Functions \end_layout \begin_layout LyX-Code void \end_layout \begin_layout LyX-Code cm_climit_fcn(in, in_offset, cntl_upper, cntl_lower, lower_delta, upper_delta, \end_layout \begin_layout LyX-Code limit_range, gain, fraction, out_final, pout_pin_final, \end_layout \begin_layout LyX-Code pout_pcntl_lower_final, pout_pcntl_upper_final) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double in; /* The input value */ \end_layout \begin_layout LyX-Code double in-offset; /* The input offset */ \end_layout \begin_layout LyX-Code double cntl_upper; /* The upper control input value */ \end_layout \begin_layout LyX-Code double cntl_lower; /* The lower control input value */ \end_layout \begin_layout LyX-Code double lower_delta; /* The delta from control to limit value */ \end_layout \begin_layout LyX-Code double upper_delta; /* The delta from control to limit value */ \end_layout \begin_layout LyX-Code double limit_range; /* The limiting range */ \end_layout \begin_layout LyX-Code double gain; /* The gain from input to output */ \end_layout \begin_layout LyX-Code int percent; /* The fraction vs. absolute range flag */ \end_layout \begin_layout LyX-Code double *out_final; /* The output value */ \end_layout \begin_layout LyX-Code double *pout_pin_final; /* The partial of output wrt input */ \end_layout \begin_layout LyX-Code double *pout_pcntl_lower_final; /* The partial of output wrt lower \end_layout \begin_layout LyX-Code control input */ \end_layout \begin_layout LyX-Code double *pout_pcntl_upper:final; /* The partial of output wrt upper \end_layout \begin_layout LyX-Code control input */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double cm_netlist_get_c() \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double cm_netlist_get_l() \end_layout \begin_layout Standard \series bold cm_climit_fcn() \series default is a very specific function that mimics the behavior of the climit code model (see the Predefined Models section). In brief, the cm_climit_fcn() takes as input an \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset value, an offset, and controlling upper and lower values. Parameter values include delta values for the controlling inputs, a smoothing range, gain, and fraction switch values. Outputs include the final value, plus the partial derivatives of the output with respect to signal input, and both control inputs. These all operate identically to the similarly-named inputs and parameters of the climit model. \end_layout \begin_layout Standard The function performs a limit on the \begin_inset Quotes eld \end_inset in \begin_inset Quotes erd \end_inset value, holding it to within some delta of the controlling inputs, and handling smoothing, etc. The cm_climit_fcn() was originally used in the ilimit code model to handle much of the primary limiting in that model, and can be used by a code model developer to take care of limiting in larger models that require it. See the detailed description of the climit model for more in-depth description. \end_layout \begin_layout Standard \series bold cm_netlist_get_c() \series default and \series bold cm_netlist_get_l() \series default functions search the analog circuitry to which their input is connected, and total the capacitance or inductance, respectively, found at that node. The functions, as they are currently written, assume they are called by a model which has only one single-ended analog input port. \end_layout \begin_layout Subsubsection Complex Math Functions \end_layout \begin_layout LyX-Code Complex_t cm_complex_set (real_part, imag_part) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code double real_part; /* The real part of the complex number */ \end_layout \begin_layout LyX-Code double imag_part; /* The imaginary part of the complex number */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t cm_complex_add (x, y) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t x; /* The first operand of x + y */ \end_layout \begin_layout LyX-Code Complex_t y; /* The second operand of x + y */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t cm_complex_sub (x, y) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t x; /* The first operand of x - y */ \end_layout \begin_layout LyX-Code Complex_t y; /* The second operand of x - y */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t cm_complex_mult (x, y) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t x; /* The first operand of x * y */ \end_layout \begin_layout LyX-Code Complex_t y; /* The second operand of x * y */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t cm_complex_div (x, y) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Complex_t x; /* The first operand of x / y */ \end_layout \begin_layout LyX-Code Complex_t y; /* The second operand of x / y */ \end_layout \begin_layout Standard \series bold cm_complex_set() \series default takes as input two doubles, and converts these to a Complex_t. The first double is taken as the real part, and the second is taken as the imaginary part of the resulting complex value. \end_layout \begin_layout Standard \series bold cm_complex_add() \series default , \series bold cm_complex_sub() \series default , \series bold cm_complex_mult() \series default , and \series bold cm_complex_div() \series default each take two complex values as inputs and return the result of a complex addition, subtraction, multiplication, or division, respectively. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:User-Defined-Node-Definition" \end_inset User-Defined Node Definition File \end_layout \begin_layout Standard The User-Defined Node Definition File (udnfunc.c) defines the C functions which implement basic operations on user-defined nodes such as data structure creation, initialization, copying, and comparison. Unlike the Model Definition File which uses the Code Model Preprocessor to translate Accessor Macros, the User-Defined Node Definition file is a pure C language file. This file uses macros to isolate you from data structure definitions, but the macros are defined in a standard header file (EVTudn.h), and translations are performed by the standard C Preprocessor. \end_layout \begin_layout Standard When a directory is created for a new User-Defined Node with `mkudndir', a structure of type 'Evt_Udn_Info_t' is placed at the bottom of the User-Define d Node Definition File. \end_layout \begin_layout Standard This structure contains the type name for the node, a description string, and pointers to each of the functions that define the node. This structure is complete except for a text string that describes the node type. This string is stubbed out and may be edited by you if desired. \end_layout \begin_layout Subsection Macros \end_layout \begin_layout Standard You must code the functions described in the following section using the macros appropriate for the particular function. You may elect whether not to provide the optional functions. \end_layout \begin_layout Standard It is an error to use a macro not defined for a function. Note that a review of the sample directories for the \begin_inset Quotes eld \end_inset real \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset UDN types will make the function usage clearer. \end_layout \begin_layout Standard The macros used in the User-Defined Node Definition File to access and assign data values are defined in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:User-Defined-Node-Macros" \end_inset . The translations of the macros and of macros used in the function argument lists are defined in the document \bar under Interface Design Document for the XSPICE Simulator of the \begin_inset Newline newline \end_inset Automatic Test Equipment Software Support Environment (ATESSE) \bar default . \end_layout \begin_layout Standard \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none MALLOCED \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PTR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Assign pointer to allocated structure to this macro \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none STRUCT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PTR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A pointer to a structure of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STRUCT_PTR_1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A pointer to a structure of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STRUCT_PTR_2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A pointer to a structure of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none EQUAL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Mif \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Boolean \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Assign TRUE or FALSE to this macro according to the results of structure comparison \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none INPUT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none STRUCT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PTR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A pointer to a structure of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OUTPUT_STRUCT_PTR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A pointer to a structure of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none INPUT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none STRUCT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PTR \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none ARRAY \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none void ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none An array of pointers to structures of the defined type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none INPUT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none STRUCT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PTR \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none ARRAY \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none SIZE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none int \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none The size of the array \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none STRUCT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none MEMBER \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none ID \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none char * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none A string naming some part of the structure \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PLOT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none VA \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none double \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none The value of the specified structure member for plotting purposes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none PRINT \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit _ \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none VAL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none char * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none The value of the specified structure member \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit for printing purposes \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:User-Defined-Node-Macros" \end_inset User-Defined Node Macros \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Function Library \end_layout \begin_layout Standard The functions (required and optional) that define a User-Defined Node are listed below. For optional functions, the function \begin_inset Quotes eld \end_inset stub \begin_inset Quotes erd \end_inset can be deleted from the udnfunc.c file template created by \begin_inset Quotes eld \end_inset mkudndir \begin_inset Quotes erd \end_inset , and the pointer in the Evt_Udn_Info_t structure can be changed to NULL. \end_layout \begin_layout Standard Required functions: \end_layout \begin_layout LyX-Code \series bold create \series default Allocate data structure used as inputs and outputs to \end_layout \begin_layout LyX-Code code models. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold initialize \series default Set structure to appropriate initial value for first use as \end_layout \begin_layout LyX-Code model input. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold copy \series default Make a copy of the contents into created but possibly \end_layout \begin_layout LyX-Code uninitialized structure. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold compare \series default Determine if two structures are equal in value. \end_layout \begin_layout Standard Optional functions: \end_layout \begin_layout LyX-Code \series bold dismantle \series default Free allocations inside structure (but not structure itself). \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold invert \series default Invert logical value of structure. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold resolve \series default Determine the resultant when multiple outputs are connected \end_layout \begin_layout LyX-Code to a node. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold plot_val \series default Output a real value for specified structure component for \end_layout \begin_layout LyX-Code plotting purposes. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold print_val \series default Output a string value for specified structure component for \end_layout \begin_layout LyX-Code printing. \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \series bold ipc_val \series default Output a binary representation of the structure suitable \end_layout \begin_layout LyX-Code for sending over the IPC channel. \end_layout \begin_layout Standard The required actions for each of these functions are described in the following subsections. In each function, \begin_inset Quotes eld \end_inset mkudndir \begin_inset Quotes erd \end_inset replaces the XXX with the node type name specified by you when mkudndir is invoked. The macros used in implementing the functions are described in a later section. \end_layout \begin_layout Subsubsection Function udn_XXX_create \end_layout \begin_layout Standard Allocate space for the data structure defined for the User-Defined Node to pass data between models. Then assign pointer created by the storage allocator (e.g. malloc) to MALLOCED_PTR. \end_layout \begin_layout Subsubsection Function udn_XXX_initialize \end_layout \begin_layout Standard Assign STRUCT_PTR to a pointer variable of defined type and then initialize the value of the structure. \end_layout \begin_layout Subsubsection Function udn_XXX_compare \end_layout \begin_layout Standard Assign STRUCT_PTR_1 and STRUCT_PTR_2 to pointer variables of the defined type. Compare the two structures and assign either TRUE or FALSE to EQUAL. \end_layout \begin_layout Subsubsection Function udn_XXX_copy \end_layout \begin_layout Standard Assign INPUT_STRUCT_PTR and OUTPUT_STRUCT_PTR to pointer variables of the defined type and then copy the elements of the input structure to the output structure. \end_layout \begin_layout Subsubsection Function udn_XXX_dismantle \end_layout \begin_layout Standard Assign STRUCT_PTR to a pointer variable of defined type and then free any allocated substructures (but not the structure itself!). If there are no substructures, the body of this function may be left null. \end_layout \begin_layout Subsubsection Function udn_XXX_invert \end_layout \begin_layout Standard Assign STRUCT_PTR to a pointer variable of the defined type, and then invert the logical value of the structure. \end_layout \begin_layout Subsubsection Function udn XXX resolve \end_layout \begin_layout Standard Assign INPUT_STRUCT_PTR_ARRAY to a variable declared as an array of pointers of the defined type - e.g.: \end_layout \begin_layout LyX-Code **struct_array; \end_layout \begin_layout LyX-Code struct_array = INPUT_STRUCT_PTR_ARRAY; \end_layout \begin_layout Standard Then, the number of elements in the array may be determined from the integer valued INPUT_STRUCT_PTR_ARRAY_SIZE macro. \end_layout \begin_layout Standard Assign OUTPUT_STRUCT_PTR to a pointer variable of the defined type. Scan through the array of structures, compute the resolved value, and assign it into the output structure. \end_layout \begin_layout Subsubsection Function udn_XXX_plot_val \end_layout \begin_layout Standard Assign STRUCT_PTR to a pointer variable of the defined type. Then, access the member of the structure specified by the string in STRUCT_MEMB ER_ID and assign some real valued quantity for this member to PLOT_VALUE. \end_layout \begin_layout Subsubsection Function udn_XXX_print_val \end_layout \begin_layout Standard Assign STRUCT_PTR to a pointer variable of the defined type. Then, access the member of the structure specified by the string in STRUCT_MEMB ER_ID and assign some string valued quantity for this member to PRINT_VALUE. \end_layout \begin_layout Standard If the string is not static, a new string should be allocated on each call. Do not free the allocated strings. \end_layout \begin_layout Subsubsection Function udn XXX ipc val \end_layout \begin_layout Standard Use STRUCT_PTR to access the value of the node data. Assign to IPC_VAL a binary representation of the data. Typically this can be accomplished by simply assigning STRUCT_PTR to IPC_VAL. \end_layout \begin_layout Standard Assign to IPC_VAL_SIZE an integer representing the size of the binary data in bytes. \end_layout \begin_layout Subsection Example UDN Definition File \end_layout \begin_layout Standard The following is an example UDN Definition File which is included with the XSPICE system. It illustrates the definition of the functions described above for a User-Defin ed Node type which is included with the XSPICE system: in this case, the \begin_inset Quotes eld \end_inset int \begin_inset Quotes erd \end_inset (for \begin_inset Quotes eld \end_inset integer \begin_inset Quotes erd \end_inset ) node type. \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout #include "EVTudn.h" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void *malloc(unsigned); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_create(CREATE_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout /* Malloc space for an int */ \end_layout \begin_layout Plain Layout MALLOCED_PTR = malloc(sizeof(int)); \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_dismantle(DISMANTLE_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout /* Do nothing. There are no internally \end_layout \begin_layout Plain Layout malloc'ed things to dismantle */ \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_initialize(INITIALIZE_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_struct = STRUCT_PTR; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Initialize to zero */ \end_layout \begin_layout Plain Layout *int.struct = 0; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_invert(INVERT_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_struct = STRUCT_PTR; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Invert the state */ \end_layout \begin_layout Plain Layout *int_struct = -(*int.struct); \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_copy(COPY_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_from_struct = INPUT_STRUCT_PTR; \end_layout \begin_layout Plain Layout int *int_to_struct = OUTPUT_STRUCT_PTR; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Copy the structure */ \end_layout \begin_layout Plain Layout *int_to_struct = *int_from_struct; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_resolve(RESOLVE_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int **array = INPUT_STRUCT_PTR_ARRAY; \end_layout \begin_layout Plain Layout int *out = OUTPUT_STRUCT_PTR; \end_layout \begin_layout Plain Layout int num.struct = INPUT_STRUCT_PTR_ARRAY_SIZE; \end_layout \begin_layout Plain Layout int sum; \end_layout \begin_layout Plain Layout int i; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Sum the values */ \end_layout \begin_layout Plain Layout for(i = 0, sum = 0; i ! num_struct; i++) \end_layout \begin_layout Plain Layout sum += *(array[i]); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Assign the result */ \end_layout \begin_layout Plain Layout *out = sum; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_compare(COMPARE_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_struct1 = STRUCT_PTR_1; \end_layout \begin_layout Plain Layout int *int_struct2 = STRUCT_PTR_2; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Compare the structures */ \end_layout \begin_layout Plain Layout if((*int_struct1) == (*int_struct2)) \end_layout \begin_layout Plain Layout EQUAL = TRUE; \end_layout \begin_layout Plain Layout else \end_layout \begin_layout Plain Layout EQUAL = FALSE; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_plot_val(PLOT_VAL_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_struct = STRUCT_PTR; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Output a value for the int struct */ \end_layout \begin_layout Plain Layout PLOT_VAL = *int_struct; \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_print_val(PRINT_VAL_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout int *int_struct = STRUCT_PTR; \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Allocate space for the printed value */ \end_layout \begin_layout Plain Layout PRINT_VAL = malloc(30); \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* Print the value into the string */ \end_layout \begin_layout Plain Layout sprintf(PRINT_VAL, "%8d", *int_struct); \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout void udn_int_ipc_val(IPC_VAL_ARGS) \end_layout \begin_layout Plain Layout { \end_layout \begin_layout Plain Layout /* Simply return the structure and its size */ \end_layout \begin_layout Plain Layout IPC_VAL = STRUCT_PTR; \end_layout \begin_layout Plain Layout IPC_VAL_SIZE = sizeof(int); \end_layout \begin_layout Plain Layout } \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout /* ---------------------------------------------------------- */ \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Evt_Udn_Info_t udn_int_info = { \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout "int", \end_layout \begin_layout Plain Layout "integer valued data", \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout udn_int_create, \end_layout \begin_layout Plain Layout udn_int_dismantle, \end_layout \begin_layout Plain Layout udn_int_initialize, \end_layout \begin_layout Plain Layout udn_int_invert, \end_layout \begin_layout Plain Layout udn_int_copy, \end_layout \begin_layout Plain Layout udn_int_resolve, \end_layout \begin_layout Plain Layout udn_int_compare, \end_layout \begin_layout Plain Layout udn_int_plot_val, \end_layout \begin_layout Plain Layout udn_int_print_val, \end_layout \begin_layout Plain Layout udn_int_ipc_val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout }; \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Error-Messages" \end_inset Error Messages \end_layout \begin_layout Standard Error messages may be subdivided into three categories. These are: \end_layout \begin_layout Enumerate Error messages generated during the development of a code model (Preprocessor Error Messages). \end_layout \begin_layout Enumerate Error messages generated by the simulator during a simulation run (Simulator Error Messages). \end_layout \begin_layout Enumerate Error messages generated by individual code models (Code Model Error Messages). \end_layout \begin_layout Standard These messages will be explained in detail in the following subsections. \end_layout \begin_layout Section Preprocessor Error Messages \end_layout \begin_layout Standard The following is a list of error messages that may be encountered when invoking the directory-creation and code modeling preprocessor tools. These are listed individually, and explanations follow the name/listing. \end_layout \begin_layout LyX-Code Usage: cmpp [-ifs] [-mod []] [-lst] \end_layout \begin_layout Standard The Code Model Preprocessor (cmpp) command was invoked incorrectly. \end_layout \begin_layout LyX-Code ERROR - Too few arguments \end_layout \begin_layout Standard The Code Model Preprocessor (cmpp) command was invoked with too few arguments. \end_layout \begin_layout LyX-Code ERROR - Too many arguments \end_layout \begin_layout Standard The Code Model Preprocessor (cmpp) command was invoked with too many arguments. \end_layout \begin_layout LyX-Code ERROR - Unrecognized argument \end_layout \begin_layout Standard The Code Model Preprocessor (cmpp) command was invoked with an invalid argument. \end_layout \begin_layout LyX-Code ERROR - File not found: s \end_layout \begin_layout Standard The specified file was not found, or could not be opened for read access. \end_layout \begin_layout LyX-Code ERROR - Line of exceeds XX characters \end_layout \begin_layout Standard The specified line was too long. \end_layout \begin_layout LyX-Code ERROR - Pathname on line of \end_layout \begin_layout LyX-Code exceeds XX characters. \end_layout \begin_layout Standard The specified line was too long. \end_layout \begin_layout LyX-Code ERROR - No pathnames found in file: \end_layout \begin_layout Standard The indicated modpath.lst file does not have pathnames properly listed. \end_layout \begin_layout LyX-Code ERROR - Problems reading ifspec.ifs in directory \end_layout \begin_layout Standard The Interface Specification File (ifspec.ifs) for the code model could not be read. \end_layout \begin_layout LyX-Code ERROR - Model name is same as internal SPICE model name \end_layout \begin_layout Standard A model has been given the same name as an intrinsic SPICE device. \end_layout \begin_layout LyX-Code ERROR - Model name '' in directory: \end_layout \begin_layout LyX-Code is same as \end_layout \begin_layout LyX-Code model name '' in directory: \end_layout \begin_layout Standard Two models in different directories have the same name. \end_layout \begin_layout LyX-Code ERROR - C function name '' in directory: , \end_layout \begin_layout LyX-Code is same as \end_layout \begin_layout LyX-Code C function name '' in directory: \end_layout \begin_layout Standard Two C language functions in separate model directories have the same names; these would cause a collision when linking the final executable. \end_layout \begin_layout LyX-Code ERROR - Problems opening CMextrn.h for write \end_layout \begin_layout Standard The temporary file CMextern.h used in building the XSPICE simulator executable could not be created or opened. Check permissions on directory. \end_layout \begin_layout LyX-Code ERROR - Problems opening CMinfo.h for write \end_layout \begin_layout Standard The temporary file CMinfo.h used in building the XSPICE simulator executable could not be created or opened. Check permissions on directory. \end_layout \begin_layout LyX-Code ERROR - Problems opening objects.inc file for write \end_layout \begin_layout Standard The temporary file objects.inc used in building the XSPICE simulator executable could not be created or opened. Check permissions on directory. \end_layout \begin_layout LyX-Code ERROR - Could not open input .mod file: \end_layout \begin_layout Standard The Model Definition File that contains the definition of the Code Model's behavior (usually cfunc.mod) was not found or could not be read. \end_layout \begin_layout LyX-Code ERROR - Could not open output .c: \end_layout \begin_layout Standard The indicated C language file that the preprocessor creates could not be created or opened. Check permissions on directory. \end_layout \begin_layout LyX-Code Error parsing .mod file: \end_layout \begin_layout Standard Problems were encountered by the preprocessor in interpreting the indicated Model Definition File. \end_layout \begin_layout LyX-Code ERROR - File not found: \end_layout \begin_layout Standard The indicated file was not found or could not be opened. \end_layout \begin_layout LyX-Code Error parsing interface specification file \end_layout \begin_layout Standard Problems were encountered by the preprocessor in interpreting the indicated Interface Specification File. \end_layout \begin_layout LyX-Code ERROR - Can't create file: \end_layout \begin_layout Standard The indicated file could not be created or opened. Check permissions on directory. \end_layout \begin_layout LyX-Code ERROR - write.port.info() - Number of allowed types cannot be zero \end_layout \begin_layout Standard There must be at least one port type specified in the list of allowed types. \end_layout \begin_layout LyX-Code illegal quoted character in string (expected " \backslash " or " \backslash \backslash ") \end_layout \begin_layout Standard A string was found with an illegal quoted character in it. \end_layout \begin_layout LyX-Code unterminated string literal \end_layout \begin_layout Standard A string was found that was not terminated. \end_layout \begin_layout LyX-Code Unterminated comment \end_layout \begin_layout Standard A comment was found that was not terminated. \end_layout \begin_layout LyX-Code Port '' not found \end_layout \begin_layout Standard The indicated port name was not found in the Interface Specification File. \end_layout \begin_layout LyX-Code Port type 'vnam' is only valid for 'in' ports \end_layout \begin_layout Standard The port type `vnam' was used for a port with direction `out' or `inout'. This type is only allowed on `in' ports. \end_layout \begin_layout LyX-Code Port types 'g', 'gd', 'h', 'hd' are only valid for 'inout' ports \end_layout \begin_layout Standard Port type `g', `gd', `h', or `hd' was used for a port with direction `out' or `in'. These types are only allowed on `inout' ports. \end_layout \begin_layout LyX-Code Invalid parameter type - POINTER type valid only for STATIC_VARs \end_layout \begin_layout Standard The type POINTER was used in a section of the Interface Specification file other than the STATIC_VAR section. \end_layout \begin_layout LyX-Code Port default type is not an allowed type \end_layout \begin_layout Standard A default type was specified that is not one of the allowed types for the port. \end_layout \begin_layout LyX-Code Incompatible port types in `allowed_types' clause \end_layout \begin_layout Standard Port types listed under `Allowed_Types' in the Interface Specification File must all have the same underlying data type. It is illegal to mix analog and eventdriven types in a list of allowed types. \end_layout \begin_layout LyX-Code Invalid parameter type (saw - expected ) \end_layout \begin_layout Standard A parameter value was not compatible with the specified type for the parameter. \end_layout \begin_layout LyX-Code Named range not allowed for limits \end_layout \begin_layout Standard A name was found where numeric limits were expected. \end_layout \begin_layout LyX-Code Direction of port '' in () \end_layout \begin_layout LyX-Code is not or INOUT \end_layout \begin_layout Standard A problem exists with the direction of one of the elements of a port vector. \end_layout \begin_layout LyX-Code Port '' is an array - subscript required \end_layout \begin_layout Standard A port was referenced that is specified as an array (vector) in the Interface Specification File. A subscript is required (e.g. myport[i]) \end_layout \begin_layout LyX-Code Parameter '' is an array - subscript required \end_layout \begin_layout Standard A parameter was referenced that is specified as an array (vector) in the Interface Specification File. A subscript is required (e.g. myparam[i]) \end_layout \begin_layout LyX-Code Port '' is not an array - subscript prohibited \end_layout \begin_layout Standard A port was referenced that is not specified as an array (vector) in the Interface Specification File. A subscript is not allowed. \end_layout \begin_layout LyX-Code Parameter '' is not an array - subscript prohibited \end_layout \begin_layout Standard A parameter was referenced that is not specified as an array (vector) in the Interface Specification File. A subscript is not allowed. \end_layout \begin_layout LyX-Code Static variable '' is not an array - subscript prohibited \end_layout \begin_layout Standard Array static variables are not supported. Use a POINTER type for the static variable. \end_layout \begin_layout LyX-Code Buffer overflow - try reducing the complexity of CM-macro array subscripts \end_layout \begin_layout Standard The argument to a code model accessor macro was too long. \end_layout \begin_layout LyX-Code Unmatched ) \end_layout \begin_layout Standard An open ( was found with no corresponding closing ). \end_layout \begin_layout LyX-Code Unmatched ] \end_layout \begin_layout Standard An open [ was found with no corresponding closing ]. \end_layout \begin_layout Section Simulator Error Messages \end_layout \begin_layout Standard The following is a list of error messages that may be encountered while attempting to run a simulation (with the exception of those error messages generated by individual code models). Most of these errors are generated by the simulator while attempting to parse a SPICE deck. These are listed individually, and explanations follow the name/listing. \end_layout \begin_layout LyX-Code ERROR - Scalar port expected, [ found \end_layout \begin_layout Standard A scalar connection was expected for a particular port on the code model, but the symbol [ which is used to begin a vector connection list was found. \end_layout \begin_layout LyX-Code ERROR - Unexpected ] \end_layout \begin_layout Standard A ] was found where not expected. Most likely caused by a missing [. \end_layout \begin_layout LyX-Code ERROR - Unexpected [ - Arrays of arrays not allowed \end_layout \begin_layout Standard A [ character was found within an array list already begun with another [ character. \end_layout \begin_layout LyX-Code ERROR - Tilde not allowed on analog nodes \end_layout \begin_layout Standard The tilde character ~was found on an analog connection. This symbol, which performs state inversion, is only allowed on digital nodes and on User-Defined Nodes only if the node type definition allows it. \end_layout \begin_layout LyX-Code ERROR - Not enough ports \end_layout \begin_layout Standard An insufficient number of node connections was supplied on the instance line. Check the Interface Specification File for the model to determine the required connections and their types. \end_layout \begin_layout LyX-Code ERROR - Expected node/instance identifier \end_layout \begin_layout Standard A special token (e.g. [ ] < > ...) was found when not expected. \end_layout \begin_layout LyX-Code ERROR - Expected node identifier \end_layout \begin_layout Standard A special token (e.g. [ ] < > ...) was found when not expected. \end_layout \begin_layout LyX-Code ERROR - unable to find definition of model \end_layout \begin_layout Standard A .model line for the referenced model was not found. \end_layout \begin_layout LyX-Code ERROR - model: %s - Array parameter expected - No array delimiter found \end_layout \begin_layout Standard An array (vector) parameter was expected on the .model card, but enclosing [ ] characters were not found to delimit its values. \end_layout \begin_layout LyX-Code ERROR - model: %s - Unexpected end of model card \end_layout \begin_layout Standard The end of the indicated .model line was reached before all required information was supplied. \end_layout \begin_layout LyX-Code ERROR - model: %s - Array parameter must have at least one value \end_layout \begin_layout Standard An array parameter was encountered that had no values. \end_layout \begin_layout LyX-Code ERROR - model: %s - Bad boolean value \end_layout \begin_layout Standard A bad values was supplied for a Boolean. Value used must be TRUE, FALSE, T, or F. \end_layout \begin_layout LyX-Code ERROR - model: %s - Bad integer, octal, or hex value \end_layout \begin_layout Standard A badly formed integer value was found. \end_layout \begin_layout LyX-Code ERROR - model: %s - Bad real value \end_layout \begin_layout Standard A badly formed real value was found. \end_layout \begin_layout LyX-Code ERROR - model: %s - Bad complex value \end_layout \begin_layout Standard A badly formed complex number was found. Complex numbers must be enclosed in < > delimiters. \end_layout \begin_layout Section Code Model Error Messages \end_layout \begin_layout Standard The following is a list of error messages that may be encountered while attempting to run a simulation with certain code models. These are listed alphabetically based on the name of the code model, and explanations follow the name and listing. \end_layout \begin_layout Subsection Code Model aswitch \end_layout \begin_layout LyX-Code cntl_error: \end_layout \begin_layout LyX-Code *****ERROR***** \end_layout \begin_layout LyX-Code ASWITCH: CONTROL voltage delta less than 1.0e-12 \end_layout \begin_layout Standard This message occurs as a result of the cntl_off and cntl_on values \family typewriter \series bold --with-editline=yes \family default \series default being less than 1.0e-12 volts/amperes apart. \end_layout \begin_layout Subsection Code Model climit \end_layout \begin_layout LyX-Code climit_range_error: \end_layout \begin_layout LyX-Code **** ERROR **** \end_layout \begin_layout LyX-Code * CLIMIT function linear range less than zero. * \end_layout \begin_layout Standard This message occurs whenever the difference between the upper and lower control input values are close enough that there is no effective room for proper limiting to occur; this indicates an error in the control input values. \end_layout \begin_layout Subsection Code Model core \end_layout \begin_layout LyX-Code allocation_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code CORE: Allocation calloc failed! \end_layout \begin_layout Standard This message is a generic message related to allocating sufficient storage for the H and B array values. \end_layout \begin_layout LyX-Code limit_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code CORE: Violation of 50% rule in breakpoints! \end_layout \begin_layout Standard This message occurs whenever the input domain value is an absolute value and the H coordinate points are spaced too closely together (overlap of the smoothing regions will occur unless the H values are redefined). \end_layout \begin_layout Subsection Code Model d_osc \end_layout \begin_layout LyX-Code d_osc_allocation_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code D_OSC: Error allocating VCO block storage \end_layout \begin_layout Standard Generic block storage allocation error. \end_layout \begin_layout LyX-Code d_osc_array_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code D_OSC: Size of control array different than frequency array \end_layout \begin_layout Standard Error occurs when there is a different number of control array members than frequency array members. \end_layout \begin_layout LyX-Code d_osc_negative_freq_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code D_OSC: The extrapolated value for frequency \end_layout \begin_layout LyX-Code has been found to be negative... \end_layout \begin_layout LyX-Code Lower frequency level has been clamped to 0.0 Hz. \end_layout \begin_layout Standard Occurs whenever a control voltage is input to a model which would ordinarily (given the specified control/freq coordinate points) cause that model to attempt to generate an output oscillating at zero frequency. In this case, the output will be clamped to some DC value until the control voltage returns to a more reasonable value. \end_layout \begin_layout Subsection Code Model d_source \end_layout \begin_layout LyX-Code loading_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code D_SOURCE: source.txt file was not read successfully. \end_layout \begin_layout Standard This message occurs whenever the d source model has experienced any difficulty in loading the source.txt (or user-specified) file. This will occur with any of the following problems: \end_layout \begin_layout Itemize Width of a vector line of the source file is incorrect. \end_layout \begin_layout Itemize A time-point value is duplicated or is otherwise not monotonically increasing. \end_layout \begin_layout Itemize One of the output values was not a valid 12-State value (0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u, 1u, Uu). \end_layout \begin_layout Subsection Code Model d_state \end_layout \begin_layout LyX-Code loading_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code D_STATE: state.in file was not read successfully. \end_layout \begin_layout LyX-Code The most common cause of this problem is a trailing \end_layout \begin_layout LyX-Code blank line in the state.in file \end_layout \begin_layout Standard This error occurs when the state.in file (or user-named state machine input file) has not been read successfully. This is due to one of the following: \end_layout \begin_layout Itemize The counted number of tokens in one of the file's input lines does not equal that required to define either a state header or a continuation line (Note that all comment lines are ignored, so these will never cause the error to occur). \end_layout \begin_layout Itemize An output state value was defined using a symbol which was invalid (i.e., it was not one of the following: 0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u, 1u, Uu). \end_layout \begin_layout Itemize An input value was defined using a symbol which was invalid (i.e., it was not one of the following: 0, 1, X, or x). \end_layout \begin_layout LyX-Code index_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code D_STATE: An error exists in the ordering of states values \end_layout \begin_layout LyX-Code in the states->state[] array. This is usually caused \end_layout \begin_layout LyX-Code by non-contiguous state definitions in the state.in file \end_layout \begin_layout Standard This error is caused by the different state definitions in the input file being non-contiguous. In general, it will refer to the different states not being defined uniquely, or being \begin_inset Quotes eld \end_inset broken up \begin_inset Quotes erd \end_inset in some fashion within the state.in file. \end_layout \begin_layout Subsection Code Model oneshot \end_layout \begin_layout LyX-Code oneshot_allocation_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code ONESHOT: Error allocating oneshot block storage \end_layout \begin_layout Standard Generic storage allocation error. \end_layout \begin_layout LyX-Code oneshot_array_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code ONESHOT: Size of control array different than pulse-width array \end_layout \begin_layout Standard This error indicates that the control array and pulse-width arrays are of different sizes. \end_layout \begin_layout LyX-Code oneshot_pw_clamp: \end_layout \begin_layout LyX-Code **** Warning **** \end_layout \begin_layout LyX-Code ONESHOT: Extrapolated Pulse-Width Limited to zero \end_layout \begin_layout Standard This error indicates that for the current control input, a pulse-width of less than zero is indicated. The model will consequently limit the pulse width to zero until the control input returns to a more reasonable value. \end_layout \begin_layout Subsection Code Model pwl \end_layout \begin_layout LyX-Code allocation_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code PWL: Allocation calloc failed! \end_layout \begin_layout Standard Generic storage allocation error. \end_layout \begin_layout LyX-Code limit_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code PWL: Violation of 50% rule in breakpoints! \end_layout \begin_layout Standard This error message indicates that the pwl model has an absolute value for its input domain, and that the x_array coordinates are so close together that the required smoothing regions would overlap. To fix the problem, you can either spread the x_array coordinates out or make the input domain value smaller. \end_layout \begin_layout Subsection Code Model s_xfer \end_layout \begin_layout LyX-Code num_size_error: \end_layout \begin_layout LyX-Code ***ERROR*** \end_layout \begin_layout LyX-Code S_XFER: Numerator coefficient array size greater than \end_layout \begin_layout LyX-Code denominator coefficient array size. \end_layout \begin_layout Standard This error message indicates that the order of the numerator polynomial specified is greater than that of the denominator. For the s_xfer model, the orders of numerator and denominator polynomials must be equal, or the order of the denominator polynomial must be greater than that or the numerator. \end_layout \begin_layout Subsection Code Model sine \end_layout \begin_layout LyX-Code allocation_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code SINE: Error allocating sine block storage \end_layout \begin_layout Standard Generic storage allocation error. \end_layout \begin_layout LyX-Code sine_freq_clamp: \end_layout \begin_layout LyX-Code **** Warning **** \end_layout \begin_layout LyX-Code SINE: Extrapolated frequency limited to 1e-16 Hz \end_layout \begin_layout Standard This error occurs whenever the controlling input value is such that the output frequency ordinarily would be set to a negative value. Consequently, the output frequency has been clamped to a near-zero value. \end_layout \begin_layout LyX-Code array_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code SINE: Size of control array different than frequency array \end_layout \begin_layout Standard This error message normally occurs whenever the controlling input array and the frequency array are different sizes. \end_layout \begin_layout Subsection Code Model square \end_layout \begin_layout LyX-Code square_allocation_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code SQUARE: Error allocating square block storage \end_layout \begin_layout Standard Generic storage allocation error. \end_layout \begin_layout LyX-Code square_freq_clamp: \end_layout \begin_layout LyX-Code **** WARNING **** \end_layout \begin_layout LyX-Code SQUARE: Frequency extrapolation limited to 1e-16 \end_layout \begin_layout Standard This error occurs whenever the controlling input value is such that the output frequency ordinarily would be set to a negative value. Consequently, the output frequency has been clamped to a near-zero value. \end_layout \begin_layout LyX-Code square_array_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code SQUARE: Size of control array different than frequency array \end_layout \begin_layout Standard This error message normally occurs whenever the controlling input array and the frequency array are different sizes. \end_layout \begin_layout Subsection Code Model triangle \end_layout \begin_layout LyX-Code triangle_allocation_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code TRIANGLE: Error allocating triangle block storage \end_layout \begin_layout Standard Generic storage allocation error. \end_layout \begin_layout LyX-Code triangle_freq_clamp: \end_layout \begin_layout LyX-Code **** Warning **** \end_layout \begin_layout LyX-Code TRIANGLE: Extrapolated Minimum Frequency Set to 1e-16 Hz \end_layout \begin_layout Standard This error occurs whenever the controlling input value is such that the output frequency ordinarily would be set to a negative value. Consequently, the output frequency has been clamped to a near-zero value. \end_layout \begin_layout LyX-Code triangle_array_error: \end_layout \begin_layout LyX-Code **** Error **** \end_layout \begin_layout LyX-Code TRIANGLE: Size of control array different than frequency array \end_layout \begin_layout Standard This error message normally occurs whenever the controlling input array and the frequency array are different sizes. \end_layout \begin_layout Part CIDER \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:CIDER-User’s-Manual" \end_inset CIDER User’s Manual \end_layout \begin_layout Standard The CIDER User’s Manual that follows is derived from the original manual being part of the \begin_inset CommandInset href LatexCommand href name "PhD thesis" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/2382.html" \end_inset from David A. Gates from UC Berkeley. Unfortunately the manual here is not yet complete, so please refer to the thesis for detailed information. Literatur on CODECS, the predecessor of CIDER, is available here from UCB: \begin_inset CommandInset href LatexCommand href name "TechRpt ERL-90-96" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1611.html" \end_inset and \begin_inset CommandInset href LatexCommand href name "TechRpt ERL-88-71" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/1118.htmlTechRpt " \end_inset . \end_layout \begin_layout Section SPECIFICATION \end_layout \begin_layout Standard Overview of numerical-device specification \end_layout \begin_layout Standard The input to CIDER consists of a SPICE-like description of a circuit, its analyses and its compact device models, and PISCES-like descriptions of numerically analyzed device models. For a description of the SPICE input format, consult the SPICE3 Users Manual [JOHN92]. \end_layout \begin_layout Standard To simulate devices numerically, two types of input must be added to the input file. The first is a model description in which the common characteristics of a device class are collected. In the case of numerical models, this provides all the information needed to construct a device cross-section, such as, for example, the doping profile. The second type of input consists of one or more element lines that specify instances of a numerical model, describe their connection to the rest of the circuit, and provide additional element-specific information such as device layout dimensions ans initial bias information. \end_layout \begin_layout Standard The format of a numerical device model description differs from the standard approach used for SPICE3 compact models. It begins the same way with one line containing the .MODEL keyword followed by the name of the model, device type and modeling level. However, instead of providing a single long list of parameters and their values, numerical model parameters are grouped onto \series bold cards \series default . Each type of card has its own set of valid parameters. In all cases, the relative ordering of different types of cards is unimportant. However, for cards of the same type (such as mesh-specification cards), their order in the input file can be important in determining the device structure. \end_layout \begin_layout Standard Each card begins on a separate line of the input file. In order to let CIDER know that card lines are continuations of a numerical model description, each must begin with the continuation character \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset . If there are too many parameters on a given card to allow it fit on a single line, the card can be continued by adding a second \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset to the beginning of the next line. However, the name and value of a parameter should always appear on the same line. \end_layout \begin_layout Standard Several features are provided to make the numerical model format more convenient. \end_layout \begin_layout Standard Blank space can follow the initial \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset to separate it from the name of a card or the card continuation \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset . Blank lines are also permitted, as long as they also begin with an initial \begin_inset Quotes eld \end_inset + \begin_inset Quotes erd \end_inset . Parentheses and commas can be used to visually group or separate parameter definitions. In addition, while it is common to add an equal sign between a parameter and its value, this is not strictly necessary. \end_layout \begin_layout Standard The name of any card can be abbreviated, provided that the abbreviation is unique. Parameter name abbreviations can also be used if they are unique in the list of a card's parameters. Numeric parameter values are treated identically as in SPICE3, so exponential notation, engineering scale factors and units can be attached to parameter values: \family typewriter tau=10ns, nc=3.0e19cm^-3 \family default . In SPICE3, the value of a FLAG model parameter is changed to TRUE simply by listing its name on the model line. In CIDER, the value of a numerical model FLAG parameter can be turned back to FALSE by preceding it by a caret \begin_inset Quotes eld \end_inset ^ \begin_inset Quotes erd \end_inset . This minimizes the amount of input change needed when features such as debugging are turned on and off. In certain cases it is necessary to include file names in the input description and these names may contain capital letters. If the file name is part of an element line, the inout parser will convert these capitals to lowercase letters. To protect capitalization at any time, simply enclose the string in double quotes \begin_inset Quotes eld \end_inset \begin_inset Quotes erd \end_inset \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard The remainder of this manual describes how numerically analyzed elements and models can be used in CIDER simulations. The manual consists of three parts. First, all of the model cards and their parameters are described. This is followed by a section describing the three basic types of numerical models and their corresponding element lines. In the final section, several complete examples of CIDER simulations are presented. \end_layout \begin_layout Standard Several conventions are used in the card descriptions. In the card synopses, the name of a card is followed by a list of parameter classes. Each class is represented by a section in the card parameter table, in the same order as it appears in the synopsis line. Classes which contain optional parameters are surrounded by brackets: [...]. Sometimes it only makes sense for a single parameter to take effect. (For example, a material can not simultaneously be both Si and SiO2.) In such cases, the various choices are listed sequentially, separated by colons. The same parameter often has a number of different acceptable names, some of which are listed in the parameter tables. \begin_inset Foot status collapsed \begin_layout Plain Layout Some of the possibilities are not listed in order to shorten the lengths of the parameter tables. This makes the use of parameter abbreviations somewhat troublesome since an unlisted parameter may abbreviate to the same name as one that is listed. CIDER will produce a warning when this occurs. Many of the undocumented parameter names are the PISCES names for the same parameters. The adventurous soul can discover these names by delving through the \begin_inset Quotes eld \end_inset cards \begin_inset Quotes erd \end_inset directory of the source code distribution looking for the C parameter tables. \end_layout \end_inset These aliases are separated by vertical bars: \begin_inset Quotes eld \end_inset | \begin_inset Quotes erd \end_inset . Finally, in the card examples, the model continuation pluses have been removed from the card lines for clarity's sake. \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard The model description for a two-dimensional numerical diode might look something like what follows. This example demonstrates many of the features of the input format described above. Notice how the .MODEL line and the leading pluses form a border around the model description: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout Example: Numerical diode \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .MODEL M_NUMERICAL NUPD LEVEL=2 \end_layout \begin_layout Plain Layout + cardnamel numberl=val1 (number2 val2), (number3 = val3) \end_layout \begin_layout Plain Layout + cardname2 numberl=val1 string1 = name1 \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + cardname3 numberl=val1, flag1, ^flag2 \end_layout \begin_layout Plain Layout + + number2=val2, flag3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The element line for an instance of this model might look something like the following. Double quotes are used to protect the file name from decapitalization: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout dl 1 2 M_NUMERICAL area=lOOpm^2 ic.file = "diode.IC" \end_layout \end_inset \end_layout \begin_layout Section BOUNDARY, INTERFACE \end_layout \begin_layout Standard Specify properties of a domain boundary or the interface between two boundaries \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout boundary domain [bounding-box] [properties] \end_layout \begin_layout Plain Layout interface domain neighbor [bounding-box] [properties] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The boundary and interface cards are used to set surface physics parameters along the boundary of a specified domain. Normally, the parameters apply to the entire boundary, but there are two ways to restrict the area of interest. If a neighboring domain is also specified, the parameters are only set on the interface between the two domains. In addition, if a bounding box is given, only that portion of the boundary or interface inside the bounding box will be set. \end_layout \begin_layout Standard If a semiconductor-insulator interface is specified, then an estimate of the width of any inversion or accumulation layer that may form at the interface can be provided. If the surface mobility model (cf. \series bold models \series default card) is enabled, then the model will apply to all semiconductor portions of the device within this estimated distance of the interface. If a point lies within the estimated layer width of more than one interface, it belong to the interface specified first in the input file. If the layer width given is less than or equal to zero, it is automatically replaced by an estimate calculated from the doping near the interface. As a consequence, if the doping varies so will the layer width estimate. \end_layout \begin_layout Standard Each edge of the bounding box can be specified in terms of its location or its mesh-index in the relevant dimension, or defaulted to the respective boundary of the simulation mesh. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of primary domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Neighbor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of neighboring domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X location of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : IX.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X mesh-index of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X location of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : IX.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X mesh-index of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y location of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : IY.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y mesh-index of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y location of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IY.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y mesh-index of bounding box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Qf \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fixed interface charge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{C}{cm^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface recombination velocity - electrons \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm}{s}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface recombination velocity - holes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm}{s}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Layer.Width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width of surface layer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard The following shows how the surface recombination velocities at an Si-SiO2 interface might be set: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout interface dom=l neigh=2 sn=l.Oe4 sp=l.Oe4 \end_layout \end_inset \end_layout \begin_layout Standard In a MOSFET with a 2.0 \begin_inset Formula $\mu m$ \end_inset gate width and 0.1 \begin_inset Formula $\mu m$ \end_inset source and drain overlap, the surface channel can be restricted to the region between the metallurgical junctions and within 100 \begin_inset Formula $\dot{A}$ \end_inset ( 0.01 \begin_inset Formula $\mu m$ \end_inset ) of the interface: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout interface dom=l neigh=2 x.l=l.l x.h=2.9 layer.w=0.01 \end_layout \end_inset \end_layout \begin_layout Standard The inversion layer width in the previous example can be automatically determine d by setting the estimate to 0.0: \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout interface dom=l neigh=% x.l=l.l x.h=2.9 layer.w=0.0 \end_layout \end_inset \end_layout \begin_layout Section COMMENT \end_layout \begin_layout Standard Add explanatory comments to a device definition \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout comment [text] \end_layout \begin_layout Plain Layout * [text] \end_layout \begin_layout Plain Layout $ [text] \end_layout \begin_layout Plain Layout # [text] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard Annotations can be added to a device definition using the comment card. All text on a comment card is ignored. Several popular commenting characters are also supported as aliases: '*' from SPICE, '$' from PISCES, and '#' from LINUX shell scripts. \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard A SPICE-like comment is followed by a PISCES-like comment and shell script comment: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * CIDER and SPICE would ignore this input line \end_layout \begin_layout Plain Layout $ CIDER and PISCES would ignore this , but SPICE wouldn't \end_layout \begin_layout Plain Layout # CIDER and LINUX Shell scripts would ignore this input line \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section CONTACT \end_layout \begin_layout Standard Specify properties of an electrode \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout contact number [workfunction] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The properties of an electrode can be set using the contact card. The only changeable property is the work-function of the electrode material and this only affects contacts made to an insulating material. All contacts to semiconductor material are assumed to be ohmic in nature. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of the electrode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Work-function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Work-function of electrode material. ( eV ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard The following shows how the work-function of the gate contact of a MOSFET might be changed to a value appropriate for a P+ polysilicon gate: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout contact num=2 workf=5.29 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard electrode, material \end_layout \begin_layout Section DOMAIN, REGION \end_layout \begin_layout Standard Identify material-type for section of a device \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout domain number material [position] \end_layout \begin_layout Plain Layout region number material [position] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard A device is divided into one or more rectilinear domains, each of which has a unique identification number and is composed of a particular material. \end_layout \begin_layout Standard Domain (aka region) cards are used to build up domains by associating a material type with a box-shaped section of the device. A single domain may be the union 0f multiple boxes. When multiple domain cards overlap in space, the one occurring last in the input file will determine the ID number and material type of the overlapped region. \end_layout \begin_layout Standard Each edge of a domain box can be specified in terms of its location or mesh-inde x in the relevant dimension, or defaulted to the respective boundary of the simulation mesh. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of this domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of material used by this domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X location of domain box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IX.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X mesh-index of domain box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X location of domain box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IX-High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X mesh-index of domain box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y location of domain box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IY.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y mesh-index of domain box \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y location of domain box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IY.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y mesh-index of domain box \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard Create a 4.0 pm wide by 2.0 pm high domain out of material #1: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout domain num=l material=l x.l=O.O x.h=4.0 y.l=O.O y.h=2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The next example defines the two domains that would be typical of a planar MOSFET simulation. One occupies all of the mesh below y = 0 and the other occupies the mesh above y = 0. Because the x values are left unspecified, the low and high x boundaries default to the edges of the mesh: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout domain n=l m=l y.l=O.O \end_layout \begin_layout Plain Layout domain n=2 m=2 y.h=O.O \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard x.mesh, material \end_layout \begin_layout Section DOPING \end_layout \begin_layout Standard Add dopant to regions of a device \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout doping [domains] profile-type [lateral-profile-type] [axis] \end_layout \begin_layout Plain Layout [impurity-type1 [constant-box] [profile-specifications] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard Doping cards are used to add impurities to the various domains of a device. Initially each domain is dopant-free. Each new doping card creates a new doping profile that defines the dopant concentration as a function of position. The doping at a particular location is then the sum over all profiles of the concentration values at that position. Each profile can be restricted to a subset of a device's domains by supplying a list of the desired domains. \end_layout \begin_layout Standard Otherwise, all domains are doped by each profile. \end_layout \begin_layout Standard A profile has uniform concentration inside the constant box. Outside this region, it varies according to the primary an lateral profile shapes. In 1D devices the lateral shape is unused and in 2D devices the y-axis is the default axis for the primary profile. Several analytic functions can be used to define the primary profile shape. Alternatively, empirical or simulated profile data can be extracted from a file. For the analytic profiles, the doping is the product of a profile function (e.g. Gaussian) and a reference concentration, which is either the constant concentra tion of a uniform profile, or the peak concentration for any of the other functions. If concentration data is used instead take from an ASCII file containing a list of location-concentration pairs or a SUPREM3 exported file, the name of the file must be provided. If necessary, the final concentration at a point is then found by multiplying the primary profile concentration by the value of the lateral profile function at that point. Empirical profiles must first be normalized by the value at 0.0 to provide a usable profile functions. Alternatively, the second dimension can be included by assigning the same concentration to all points equidistant from the edges of the constant box. The contours of the profile are the circular. \end_layout \begin_layout Standard Unless otherwise specified, the added impurities are assumes to be N type. However, the name of a specific dopant species is needed when extracting concentration information for that impurity from a SUPREM3 exported file. \end_layout \begin_layout Standard Several parameters are used to adjust the basic shape of a profile functions so that the final, constructed profile, matches the doping profile in the real device. The constant box region should coincide with a region of constant concentration in the device. For uniform profiles its boundaries default to the mesh boundaries. For the other profiles the constant box starts as a point and only acquires width or height if both the appropriate edges are specified. The location of the peak of the primary profile can be moved away from the edge of the constant box. \begin_inset Float figure wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/CIDER_Conc_profile1.gif width 100line% \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:1D-doping-profiles" \end_inset 1D doping profiles with location > 0. \end_layout \end_inset \end_layout \end_inset A positive location places the peak outside the constant box (cf. Fig. \begin_inset CommandInset ref LatexCommand ref reference "fig:1D-doping-profiles" \end_inset ), and a negative value puts it inside the constant box (cf. Fig. \begin_inset CommandInset ref LatexCommand ref reference "fig:1D-doping-profiles_lt0" \end_inset ). \begin_inset Float figure wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/CIDER_Conc_profile2.gif width 100line% \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:1D-doping-profiles_lt0" \end_inset 1D doping profiles with location < 0. \end_layout \end_inset \end_layout \end_inset The concentration in the constant box is then equal to the value of the profile when it intersects the edge of the constant box. The argument of the profile function is a distance expressed in terms of the characteristic length (by default equal to \begin_inset Formula $1\mu m$ \end_inset ). The longer this length, the more gradually the profile will change. For example, in Fig. A.1 and Fig A.2, the profiles marked (a) have characteristic lengths twice those of the profiles marked (b). The location and characteristic length for the lateral profile are multiplied by the lateral ratio. This allows the use of different length scales for the primary and lateral profiles. For rotated profiles, this scaling is taken into account, and the profile contours are elliptical rather than circular. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Domains \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Int List \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout List of domains to dope \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniform: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Primary profile type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Erfc: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Exponential: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Suprem3: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ascii: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ascii Suprem3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout InFile \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Name of Suprem3, Ascii or Ascii Suprem3 input file \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Rotate: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lateral profile type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Unif: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Lin: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Gauss: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Erfc: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lat.Exp \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.Axis:Y.Axis \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Primary profile direction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N.Type: P.Type: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Impurity type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Donor: Acceptor: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phosphorus: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Arsenic: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Antimony: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Boron \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X location of constant box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X location of constant box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y location of constant box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y location of constant box, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conic | Peak.conic \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dopant concentration, ( \begin_inset Formula $cm^{-3}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Location | Range \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Location of profile edge/peak, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Char.Length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Characteristic length of profile, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ratio.Lat \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ratio of lateral to primary distances \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard This first example adds a uniform background P-type doping of \begin_inset Formula $1.0\times10^{16}cm^{-3}$ \end_inset to an entire device: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout doping uniform p.type conc=l.0el6 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A Gaussian implantation with rotated lateral falloff, such as might be used for a MOSFET source, is then added: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout doping gauss lat.rotate n.type conc=l.0el9 \end_layout \begin_layout Plain Layout + x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.2 ratio=0.7 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Alternatively, an error-function falloff could be used: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout doping gauss lat.erfc conc=l.0el9 \end_layout \begin_layout Plain Layout + x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.2 ratio=0.7 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Finally, the MOSFET channel implant is extracted from an ASCII-format SUPREM3 file. The lateral profile is uniform, so that the implant is confined between \begin_inset Formula $X=1\mu m$ \end_inset and \begin_inset Formula $X=3\mu m$ \end_inset . The profile begins at \begin_inset Formula $Y=0\mu m$ \end_inset (the high Y value defaults equal to the low Y value): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout doping ascii suprem3 infile=implant.s3 lat.unif boron \end_layout \begin_layout Plain Layout + x.l=1.0 x.h=3.0 y.l=0.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard domain, mobility, contact, boundary \end_layout \begin_layout Section ELECTRODE \end_layout \begin_layout Standard Set location of a contact to the device \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout electrode [number] [position] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard Each device has several electrodes which are used to connect the device to the rest of the circuit. The number of electrodes depends on the type of device. For example, a MOSFET needs 4 electrodes. A particular electrode can be identified by its position in the list of circuit nodes on the device element line. For example, the drain node of a MOSFET is electrode number 1, while the bulk node is electrode number 4. Electrodes for which an ID number has not been specified are assigned values sequentially in the order they appear in the input file. \end_layout \begin_layout Standard For lD devices, the positions of two of the electrodes are predefined to be at the ends of the simulation mesh. The first electrode is at the low end of the mesh, and the last electrode is at the high end. The position of the special lD BJT base contact is set on the options card. Thus, electrode cards are used exclusively for 2D devices. \end_layout \begin_layout Standard Each card associates a portion of the simulation mesh with a particular electrode. In contrast to domains, which are specified only in terms of boxes, electrodes can also be specified in terms of line segments. Boxes and segments for the same electrode do not have to overlap. If they don’t, it is assumed that the electrode is wired together outside the area covered by the simulation mesh. However, pieces of different electrodes \bar under must not \bar default overlap, since this would represent a short circuit. Each electrode box or segment can be specified in terms of the locations or mesh-indices of its boundaries. A missing value defaults to the corresponding mesh boundary. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of this domain \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X location of electrode, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IX.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest X mesh-index of electrode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X location of electrode, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IX.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest X mesh-index of electrode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y location of electrode, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IY.Low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lowest Y mesh-index of electrode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y location of electrode, ( \begin_inset Formula $\mu m$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :IY.High \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Highest Y mesh-index of electrode \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard The following shows how the four contacts of a MOSFET might be specified: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * DRAIN \end_layout \begin_layout Plain Layout electrode x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 \end_layout \begin_layout Plain Layout * GATE \end_layout \begin_layout Plain Layout electrode x.l=1.0 x.h=3.0 iy.l=0 iy.h=0 \end_layout \begin_layout Plain Layout * SOURCE \end_layout \begin_layout Plain Layout electrode x.l=3.0 x.h=4.0 y.l=0.0 y.h=0.0 \end_layout \begin_layout Plain Layout * BULK \end_layout \begin_layout Plain Layout electrode x.l=0.0 x.h=4.0 y.l=2.0 y.h=2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The numbering option can be used when specifying bipolar transistors with dual base contacts: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * EMITTER \end_layout \begin_layout Plain Layout electrode num=3 x.l=1.0 x.h=2.0 y.l=0.0 y.h=0.0 \end_layout \begin_layout Plain Layout * BASE \end_layout \begin_layout Plain Layout electrode num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 \end_layout \begin_layout Plain Layout electrode num=2 x.l=2.5 x.h=3.0 y.l=0.0 y.h=0.0 \end_layout \begin_layout Plain Layout * COLLECTOR \end_layout \begin_layout Plain Layout electrode num=1 x.l=0.0 x.h=3.0 y.l=1.0 y.h=1.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard domain, contact \end_layout \begin_layout Section END \end_layout \begin_layout Standard Terminate processing of a device definition \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The end card stops processing of a device definition. It may appear anywhere within a definition. Subsequent continuation lines of the definition will be ignored. If no end card is supplied, all the cards will be processed. \end_layout \begin_layout Section MATERIAL \end_layout \begin_layout Standard Specify physical properties of a material \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout material number type [physical-constants] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The material card is used to create an entry in the list of materials used in a device. Each entry needs a unique identification number and the type of the material. Default values are assigned to the physical properties of the material. Most material parameters are accessible either here or on the \family typewriter mobility \family default or \family typewriter contact \family default cards. However, some parameters remain inaccessible (e.g. the ionization coefficient parameters). Parameters for most physical effect models are collected here. Mobility parameters are handled separately by the \family typewriter mobility \family default card. Properties of electrode materials are set using the \family typewriter contact \family default card. \end_layout \begin_layout Subsection PARAMETERS \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of this material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Semiconductor : Silicon \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type of this material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Polysilicon : GaAs \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Insulator : Oxide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Nitride \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Affinity \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron affinity (eV) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Permittivity \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dielectric permittivity ( \begin_inset Formula $\nicefrac{F}{cm}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nc \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conduction band density ( \begin_inset Formula $cm^{-3}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nv \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Valence band density ( \begin_inset Formula $cm^{-3}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Eg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Energy band gap (eV) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout dEg.dT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap narrowing with temperature ( \begin_inset Formula $\nicefrac{eV}{°K}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Eg.Tref \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap reference temperature, ( °K ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout dEg.dN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap narrowing with N doping, ( \begin_inset Formula $\nicefrac{eV}{cm^{-3}}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Eg.Nref \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap reference concentration - N type, ( \begin_inset Formula $cm^{-3}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout dEg.dP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap narrowing with P doping, ( \begin_inset Formula $\nicefrac{eV}{cm^{-3}}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Eg.Pref \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap reference concentration - P type, ( \begin_inset Formula $cm^{-3}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH lifetime - electrons, (sec) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH.Nref \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH reference concentration - electrons ( \begin_inset Formula $cm^{-3})$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH lifetime - holes, (sec) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH.Pref \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH reference concentration - holes ( \begin_inset Formula $cm^{-3})$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Auger coefficient - electrons ( \begin_inset Formula $\nicefrac{cm^{6}}{sec}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Auger coefficient - holes ( \begin_inset Formula $\nicefrac{cm^{6}}{sec}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ARichN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Richardson constant - electrons, ( \begin_inset Formula $\nicefrac{A}{\frac{cm^{2}}{°K^{2}}}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ARichP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Richardson constant - holes, ( \begin_inset Formula $\nicefrac{A}{\frac{cm^{2}}{°K^{2}}}$ \end_inset ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard Set the type of material #1 to silicon, then adjust the values of the temperatur e-dependent bandgap model parameters: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout material num=1 silicon eg=1.12 deg.dt=4.7e-4 eg.tref=640.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The recombination lifetimes can be set to extremely short values to simulate imperfect semiconductor material: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout material num=2 silicon tn=1ps tp=1ps \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard domain, mobility, contact, boundary \end_layout \begin_layout Section METHOD \end_layout \begin_layout Standard Choose types and parameters of numerical methods \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout method [types] [parameters] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The method card controls which numerical methods are used during a simulation and the parameters of these methods. Most of these methods are optimizations that reduce run time, but may sacrifice accuracy or reliable convergence. \end_layout \begin_layout Standard For majority-carrier devices such as MOSFETs, one carrier simulations can be used to save simulation time. The systems of equations in AC analysis may be solved using either direct or successive-over-relaxation techniques. Successive-over-relaxation is faster, but at high frequencies, it may fail to converge or may converge to the wrong answer. In some cases, it is desirable to obtain AC parameters as functions of DC bias conditions. If necessary, a one-point AC analysis is performed at a predefined frequency in order to obtain these small-signal parameters. The default for this frequency is 1 Hz. The Jacobian matrix for DC and transient analyses can be simplified by ignoring the derivatives of the mobility with respect to the solution variables. However, the resulting analysis may have convergence problems. Additionally, if they are ignored during AC analyses, incorrect results may be obtained. \end_layout \begin_layout Standard A damped Newton method is used as the primary solution technique for the device-level partial differential equations. This algorithm is based on an iterative loop that terminates when the error in the solution is small enough or the iteration limit is reached. Error tolerances are used when determining if the error is “small enough”. The tolerances are expressed in terms of an absolute, solution-independent error and a relative, solution-dependent error. The absolute-error limit can be set on this card. The relative error is computed by multiplying the size of the solution by the circuit level SPICE parameter RELTOL. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OneCarrier \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Solve for majority carriers only \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AC analysis \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AC analysis method, ( either DIRECT or SOR) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NoMobDeriv \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ignore mobility derivatives \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AC analysis frequency, ( Hz ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ItLim \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Newton iteration limit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DevTol \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum residual error in device equations \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard Use one carrier simulation for a MOSFET, and choose direct method AC analysis to ensure accurate, high frequency results: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout method onec ac.an=direct \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Tolerate no more than \begin_inset Formula $10^{-10}$ \end_inset as the absolute error in device-level equations, and perform no more than 15 Newton iterations in any one loop: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout method devtol=1e-10 itlim=15 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section Mobility \end_layout \begin_layout Standard Specify types and parameters of mobility models \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout mobility material [carrier] [parameters] [models] [initialize] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Description \end_layout \begin_layout Standard The mobility model is one of the most complicated models of a material's physical properties. As a result, separate cards are needed to set up this model for a given material. \end_layout \begin_layout Standard Mobile carriers in a device are divided into a number of different classes, each of which has different mobility modelling. There are three levels of division. First, electrons and holes are obviously handled separately. Second, carriers in surface inversion or accumulation layers are treated differently than carriers in the bulk. Finally, bulk carriers can be either majority or minority carriers. \end_layout \begin_layout Standard For surface carriers, the normal-field mobility degradation model has three user-modifiable parameters. For bulk carriers, the ionized impurity scattering model has four controllable parameters. Different sets of parameters are maintained for each of the four bulk carrier types: majority-electron, minority-electron, majority-hole and minority-hole. Velocity saturation modelling can be applied to both surface and bulk carriers. However, only two sets of parameters are maintained: one for electrons and one for holes. These must be changed on a majority carrier card (i.e. when the majority flag is set). \end_layout \begin_layout Standard Several models for the physical effects are available, along with appropriate default values. Initially, a universal set of default parameters usable with all models is provided. These can be overridden by defaults specific to a particular model by setting the initialization flag. These can then be changed directly on the card itself. The bulk ionized impurity models are the Caughey-Thomas (CT) model and the Scharfetter-Gummel (SG) model [CAUG671, [SCHA69]. Three alternative sets of defaults are available for the Caughey-Thomas expression. They are the Arora (AR) parameters for Si [AROR82], the University of Florida (UF) parameters for minority carriers in Si [SOLL90], and a set of parameters appropriate for GaAs (GA). The velocity-saturation models are the Caughey-Thomas (CT) and Scharfetter-Gumm el (SG) models for Si, and the PISCES model for GaAs (GA). There is also a set of Arora (AR) parameters for the Caughey-Thomas model. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID number of material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron : Hole \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobile carrier \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Majority : Minority \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobile carrier type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MUS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum surface mobility, ( cm2/Vs ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EC.A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface mobility 1st-order critical field, ( V/cm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EC.B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real Surface mobility 2nd-order critical field, ( V2/cm2 ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MuMax \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum bulk mobility, ( cm2/Vs ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MuMin \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Minimum bulk mobility, ( cm2/Vs) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NtRef \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ionized impurity reference concentration, ( cm-3 ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NtExp \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ionized impurity exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Vsat \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation velocity, ( cm/s ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Vwarm \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Warm carrier reference velocity, ( cm/s ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ConcModel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ionized impurity model, ( CT, AR, UF, SG, Dr GA ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FieldModel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Velocity saturation model, ( CT, AR, SG, or GA ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Init \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Copy model-specific defaults \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard The following set of cards completely updates the bulk mobility parameters for material #1: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout mobility mat=l concmod=sg fieldmod=sg \end_layout \begin_layout Plain Layout mobility mat=l elec major mumax=1000.0 mumin=l00.0 \end_layout \begin_layout Plain Layout + ntref=l.0el6 ntexp=0.8 vsat=l.0e7 vwarm=3.0e6 \end_layout \begin_layout Plain Layout mobility mat=l elec minor mumax=1000.0 mumin=200.O \end_layout \begin_layout Plain Layout + ntref=l.0el7 ntexp=0.9 \end_layout \begin_layout Plain Layout mobility mat=l hole major mumax=500.0 mumin=50.0 \end_layout \begin_layout Plain Layout + ntref=l.0el6 ntexp=0.7 vsat=8.0e6 vwarm=l.0e6 \end_layout \begin_layout Plain Layout mobility mat=l hole minor mumax=500.0 mumin=150.0 \end_layout \begin_layout Plain Layout + ntref=l.0el7 ntexp=0.8 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The electron surface mobility is changed by the following: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout mobility mat=l elec mus=800.0 ec.a=3.0e5 ec.b=9.0e5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Finally, the default Scharfetter-Gummel parameters can be used in Si with the GaAs velocity-saturation model (even though it doesn't make physical sense!): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout mobility mat=l init elec major fieldmodel=sg \end_layout \begin_layout Plain Layout mobility mat=l init hole major fieldmodel=sg \end_layout \begin_layout Plain Layout mobility mat=l fieldmodel=ga \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard material \end_layout \begin_layout Subsection BUGS \end_layout \begin_layout Standard The surface mobility model does not include temperature-dependence for the transverse-field parameters. Those parameters will need to be adjusted by hand. \end_layout \begin_layout Section MODELS \end_layout \begin_layout Standard Specify which physical models should be simulated \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout models [model flags] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The models card indicates which physical effects should be modeled during a simulation. Initially, none of the effects are included. A flag can be set false by preceding by a caret. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BGN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap narrowing \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SRH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Shockley-Reed-Hall recombination \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ConcTau \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Concentration-dependent SRH lifetimes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Auger \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Auger recombination \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Avalanche \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Local avalanche generation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TempMob \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature-dependent mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ConcMob \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Concentration-dependent mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FieldMob \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lateral-field-dependent mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TransMob \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transverse-field-dependent surface mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SurfMob \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Activate surface mobility model \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard Turn on bandgap narrowing, and all of the generation-recombination effects: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout models bgn srh conctau auger aval \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Amend the first card by turning on lateral- and transverse-field-dependent mobility in surface charge layers, and lateral-field-dependent mobility in the bulk. Also, this line turns avalanche generation modeling off. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout models surfmob transmob fieldmob ^aval \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection See also \end_layout \begin_layout Standard material, mobility \end_layout \begin_layout Subsection Bugs \end_layout \begin_layout Standard The local avalanche generation model for 2D devices does not compute the necessary contributions to the device-level Jacobian matrix. If this model is used, it may cause convergence difficulties and it will cause AC analyses to produce incorrect results. \end_layout \begin_layout Section OPTIONS \end_layout \begin_layout Standard Provide optional device-specific information \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout options [device-type] [initial-state] [dimensions] \end_layout \begin_layout Plain Layout [measurement-temperature] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The options card functions as a catch-all for various information related to the circuit-device interface. The type of a device can be specified here, but will be defaulted if none is given. Device type is used primarily to determine how to limit the changes in voltage between the terminals of a device. It also helps determine what kind of boundary conditions are used as defaults for the device electrodes. \end_layout \begin_layout Standard A previously calculated state, stored in the named initial-conditions file, can be loaded at the beginning of an analysis. If it is necessary for each instance of a numerical model to start in a different state, then the unique flag can be used to generate unique filenames for each instance by appending the instance name to the given filename. This is the same method used by CIDER to generate unique filenames when the states are originally saved. If a particular state file does not fit. this pattern, the filename can be entered directly on the instance line. \end_layout \begin_layout Standard Mask dimension defaults can be set so that device sizes can be specified in terms of area or width. Dimensions for the special lD BJT base contact can also be controlled. The measurement temperature of material parameters, normally taken to be the circuit default, can be overridden. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Diode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : Bipolar|BJT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bipolar transistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : MOSFET \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS field-effect transistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : JFET \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Junction field-effect transistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout : MESFET \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MES field-effect transistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IC.File \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial-conditions filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unique \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Append instance name to filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DefA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Mask Area, (m²) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DefW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Mask Width, (m) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DefL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Mask Length, (m) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Base.Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lD BJT base area relative to emitter area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Base.Length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real lD BJT base contact length, (µm) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Base.Depth \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lD BJT base contact depth, (µm) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNom \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nominal measurement temperature, (°C) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard Normally, a 'numos' device model is used for MOSFET devices. However, it can be changed into a bipolar-with-substrate-contact model, by specifying a bipolar structure using the other cards, and indicating the device-structure type as shown here. The default length is set to 1.0 µm so that when mask area is specified on the element line it can be devided by this default to obtain the device width. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout options bipolar defl=1.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Specify that a 1D BJT has base area 1/10th that of the emitter, has an effective depth of 0.2 µm and a length between the internal and external base contacts \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout options base.area=0.1 base.depth=0.2 base.len=1.5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If a circuit contains two instances of a bipolar transistor model named 'q1' and 'q2', the following line tells the simulator to look for initial conditions in the 'OP1.q2', respectively. The period in the middle of the names is added automatically: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout options unique ic.file="OP1" \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection See also \end_layout \begin_layout Standard numd, nbjt, numos \end_layout \begin_layout Section OUTPUT \end_layout \begin_layout Standard Identify information to be printed or saved \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout output [debugging-flags] [general-info] [saved-solutions] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The output card is used to control the amount of information that is either presented to or saved for the user. Three types of information are available. Debugging information is available as a means to monitor program execution. This is useful during long simulations when one is unsure about whether the program has become trapped at some stage of the simulation. General information about a device such as material parameters and resource usage can be obtained. Finally, information about the internal and external states of a device is available. Since this data is best interpreted using a post-processor, a facility is available for saving device solutions in auxiliary output files. Solution filenames are automatically generated by the simulator. If the named file already exists, the file will be overwritten. A filename unique to a particular circuit or run can be generated by providing a root filename. This root name will be added onto the beginning of the automatically generated name. This feature can be used to store solutions in a directory other than the current one by specifying the root filename as the path of the desired directory. Solutions are only saved for those devices that specify the ‘save’ parameter on their instance lines. \end_layout \begin_layout Standard The various physical values that can be saved are named below. By default, the following values are saved: the doping, the electron and hole concentrations, the potential, the electric field, the electron and hole current densities, and the displacement current density. Values can be added to or deleted from this list by turning the appropriate flag on or off. For vector-valued quantities in two dimensions, both the X and Y components are saved. The vector magnitude can be obtained during post-processing. \end_layout \begin_layout Standard Saved solutions can be used in conjunction with the \series bold options \series default card and instance lines to reuse previously calculated solutions as initial guesses for new solutions.For example, it is typical to initialize the device to a known state prior to beginning any DC transfer curve or operating point analysis. This state is an ideal candidate to be saved for later use when it is known that many analyses will be performed on a particular device structure. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout All.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Debug all analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OP.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .OP analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DC.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .DC analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRAN.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .TRAN analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AC.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .AC analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PZ.Debug \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .PZ analyses \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Physical material information \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Statistics | Resources \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resource usage information \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RootFile \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Root of output file names \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Psi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Equ.Psi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Equilibrium potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Vac.Psi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Vacuum potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Doping \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Net doping ( cm³ ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N.Conc \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron concentration ( cm³ ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P.Conc \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hole concentration ( cm³ ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PhiN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron quasi-fermi potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PhiP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hole quasi-fermi potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PhiC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conduction band potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PhiV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Valence band potential ( V ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout E.Field \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electric field ( V/cm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conduction current density ( A/cm² ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Displacement current density ( A/cm² ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron current density ( A/cm² ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hole current density ( A/cm² ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Total current density ( A/cm² ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unet \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Net recombination ( 1/cm³ s ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MuN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Electron mobility (low-field) ( cm²/Vs ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MuP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hole mobility (low-field) ( cm²/Vs ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard The following example activates all potentially valuable diagnostic output: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout output all.debug mater stat \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Energy band diagrams generally contain the potential, the quasi-fermi levels, the energies and the vacuum energy. The following example enables saving of the r values needed to make energy band diagrams: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout output phin phjp phic phiv vac.psi \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Sometimes it is desirable to save certain key solutions, and then reload them subsequent simulations. In such cases only the essential values ( 9,n, and p 1 saved. This example turns off the nonessential default values (and indicates th ones explicitly): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout output psi n.conc p.conc ^e.f ^jn ^jp ^jd \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard options, numd, nbjt, numos \end_layout \begin_layout Section TITLE \end_layout \begin_layout Standard Provide a label for this device’s output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout title [text] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The title card provides a label for use as a heading in various output files. The text can be any length, but titles that fit on a single line will produce more aesthetically pleasing output. \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard Set the title for a minimum gate length NMOSFET in a 1.0µm BiCMOS proces \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout title L=1.0um NMOS Device, 1.0um BiCMOS Process \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection BUGS \end_layout \begin_layout Standard The title is currently treated like a comment. \end_layout \begin_layout Section X.MESH, Y.MESH \end_layout \begin_layout Standard Define locations of lines and nodes in a mesh \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout x.mesh position numbering-method [spacing-parameters] \end_layout \begin_layout Plain Layout y.mesh position numbering-method [spacing-parameters] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard The domains of a device are discretized onto a rectangular finite-difference mesh using x.mesh cards for 1D devices, or x.mesh and y.mesh cards for 2D devices. Both uniform and non-uniform meshes can be specified. \end_layout \begin_layout Standard A typical mesh for a 2D device is shown in Figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Typical-mesh-for" \end_inset . \end_layout \begin_layout Standard \begin_inset Float figure placement h wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/mesh-3a.gif scale 40 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Typical-mesh-for" \end_inset Typical mesh for 2D devices \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The mesh is divided into intervals by the \emph on reference \emph default lines. The other lines in each interval are automatically generated by CIDER using the mesh spacing parameters. In general, each new mesh card adds one reference line and multiple automatic lines to the mesh. Conceptually, a 1D mesh is similar to a 2D mesh except that there are no reference or automatic lines needed in the second dimension. \end_layout \begin_layout Standard The location of a reference line in the mesh must either be given explicitly (using \emph on Location \emph default ) or defined implicitly relative to the location of the previous reference line (by using \emph on Width \emph default ). (If the first card in either direction is specified using \emph on Width \emph default , an initial reference line is automatically generated at location 0.0.) The line number of the reference line can be given explicitly, in which case the automatic lines are evenly spaced within the interval, and the number of lines is determined from the difference between the current line number and that of the previous reference line. However, if the interval width is given, then the line number is interpreted directly as the number of additional lines to add to the mesh. \end_layout \begin_layout Standard For a nonuniformly spaced interval, the number of automatic lines has to be determined using the mesh spacing parameters. Nonuniform spacing is triggered by providing a desired ratio for the lengths of the spaces between adjacent pairs of lines. This ratio should always be greater than one, indicating the ratio of larger spaces to smaller spaces. In addition to the ratio, one or both of the space widths at the ends of the interval must be provided. If only one is given, it will be the smallest space and the largest space will be at the opposite end of the interval. If both are given, the largest space will be in the middle of the interval. In certain cases it is desirable to limit the growth of space widths in order to control the solution accuracy. This can be accomplished by specifying a maximum space size, but this option is only available when one of the two end lengths is given. Note that once the number of new lines is determined using the desired ratio, the actual spacing ratio may be adjusted so that the spaces exactly fill the interval. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Location \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Location of this mesh line, ( µm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :Width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width between this and previous mesh lines, ( µm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number | Node \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of this mesh line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout :Ratio \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ratio of sizes of adjacent spaces \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout H.Start | H1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Space size at start of interval, ( µm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout H.End | H2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Space size at end of interval, ( µm ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout H.Max | H3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum space size inside interval, ( µm ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard A 50 node, uniform mesh for a 5 µm long semiconductor resistor can be specified as: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout x.mesh loc=0.0 n=1 \end_layout \begin_layout Plain Layout x.mesh loc=5.0 n=50 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard An accurate mesh for a 1D diode needs fine spacing near the junction. In this example, the junction is assumed to be 0.75 µm deep. The spacing near the diode ends is limited to a maximum of 0.1 µm: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout x.mesh w=0.75 h.e=0.001 h.m=0.l ratio=1.5 \end_layout \begin_layout Plain Layout x.mesh w=2.25 h.s=0.001 h.m=0.l ratio=1.5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The vertical mesh spacing of a MOSFET can generally be specified as uniform through the gate oxide, very fine for the surface inversion layer, moderate down to the so source/drain junction depth, and then increasing all the way to the bulk contact: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout y.mesh loc=-0.04 node=1 \end_layout \begin_layout Plain Layout y.mesh loc=0.0 node=6 \end_layout \begin_layout Plain Layout y.mesh width=0.5 h.start=0.001 h.max=.05 ratio=2.0 \end_layout \begin_layout Plain Layout y.mesh width=2.5 h.start=0.05 ratio=2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard domain \end_layout \begin_layout Section NUMD \end_layout \begin_layout Standard Diode / two-terminal numerical models and elements \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Model: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .MODEL model-name NUMD [level] \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Element: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout DXXXXXXX nl n2 model-name [geometry] [temperature] [initial-conditions] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Output: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE [small-signal values] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard NUMD is the name for a diode numerical model. In addition, this same model can be used to simulate other two-terminal structures such as semiconductor resistors and MOS capacitors. See the \series bold options \series default card for more information on how to customize the device type. \end_layout \begin_layout Standard Both 1D and 2D devices are supported. These correspond to the LEVEL=l and LEVEL=2 models, respectively. If left unspecified, it is assumed that the device is one-dimensional. \end_layout \begin_layout Standard All numerical two-terminal element names begin with the letter ‘D. The element name is then followed by the names of the positive (n1) and negative (n2) nodes. After this must come the name of the model used for the element. The remaining information can come in any order. The layout dimensions of an element are specified relative to the geometry of a default device. For 1D devices, the default device has an area of 1m², and for 2D devices, the default device has a width of 1 m. However, these defaults can be overridden on an \series bold options \series default card. The operating temperature of a device can be set independently from that of the rest of the circuit in order to simulate non-isothermal circuit operation. Finally, the name of a file containing an initial state for the device can be specified. Remember that if the filename contains capital letters, they must be protected by surrounding the filename with double quotes. Alternatively, the device can be placed in an OFF state (thermal equilibrium) at the beginning of the analysis. For more information on the use of initial conditions, see the NGSPICE User’s Manual, chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Junction-Diodes" \end_inset . \end_layout \begin_layout Standard In addition to the element input parameters, there are output-only parameters that can be shown using the NGSPICE \family typewriter show \family default command ( \begin_inset CommandInset ref LatexCommand ref reference "sub:Show*:-List-device" \end_inset ) or captured using the \family typewriter save/.SAVE ( \family default \begin_inset CommandInset ref LatexCommand ref reference "sub:Save*:-Save-a" \end_inset \family typewriter / \family default \begin_inset CommandInset ref LatexCommand ref reference "sub:.SAVE-Lines" \end_inset \family typewriter ) \family default command. These parameters are the elements of the indefinite conductance (G), capacitanc e (C), and admittance (Y) matrices where \begin_inset Formula $Y=G+j\omega C$ \end_inset . By default, the parameters are computed at 1 Hz. Each element is accessed using the name of the matrix (g, c or y) followed by the node indices of the output terminal and the input terminal (e.g. g11). Beware that names are case-sensitive for \family typewriter save/show \family default , so lower-case letters must be used. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Level \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dimensionality of numerical model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative area factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative width factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temp \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Element operating temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IC.File \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial-conditions filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Device initially in OFF state \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conductance element \begin_inset Formula $G_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance element \begin_inset Formula $C_{ij}$ \end_inset , ( F ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout yIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Admittance element \begin_inset Formula $Y_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard A one-dimensional numerical switching-diode element/model pair with an area twice that of the default device (which has a size of l µm x 1 µm) can be specified using: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout DSWITCH 1 2 M_SWITCH_DIODE AREA=2 \end_layout \begin_layout Plain Layout .MODEL M_SWITCH_DIODE NUMD \end_layout \begin_layout Plain Layout + options defa=1p ... \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A two-dimensional two-terminal MOS capacitor with a width of 20 µm and an initial condition of 3 V is created by: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout DMOSCAP 11 12 M_MOSCAP W=20um IC=3v \end_layout \begin_layout Plain Layout .MODEL M_MOSCAP NUMD LEVEL=2 \end_layout \begin_layout Plain Layout + options moscap defw=1m \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The next example shows how both the width and area factors can be used to create a power diode with area twice that of a 6µm-wide device (i.e. a 12µm-wide device). The device is assumed to be operating at a temperature of 100°C: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout D1 POSN NEGN POWERMOD AREA=2 W=6um TEMP=100.0 \end_layout \begin_layout Plain Layout .MODEL POWERMOD NUMD LEVEL=2 \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This example saves all the small-signal parameters of the previous diode: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE @d1[g11] @d1[g12] @d1[g21] @d1[g22] \end_layout \begin_layout Plain Layout .SAVE @d1[c11] @d1[c12] @d1[c21] @d1[c22] \end_layout \begin_layout Plain Layout .SAVE @d1[y11] @d1[y12] @d1[y21] @d1[y22] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard options, output \end_layout \begin_layout Subsection BUGS \end_layout \begin_layout Standard Convergence problems may be experienced when simulating MOS capacitors due to singularities in the current-continuity equations. \end_layout \begin_layout Section NBJT \end_layout \begin_layout Standard Bipolar / three-terminal numerical models and elements \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Model: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .MODEL model-name NBJT [level] \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Element: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout QXXXXXXX nl n2 n3 model-name [geometry] \end_layout \begin_layout Plain Layout + [temperature] [initial-conditions] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Output: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE [small-signal values] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard NBJT is the name for a bipolar transistor numerical model. In addition, the 2D model can be used to simulate other three-terminal structures such as a JFET or MESFET. However, the 1D model is customized with a special base contact, and cannot be used for other purposes. See the options card for more information on how to customize the device type and setup the 1D base contact. \end_layout \begin_layout Standard Both 1”and 2D devices are supported. These correspond to the LEVEL=l and models, respectively. If left unspecified, it is assumed that the device is one-dimensional. \end_layout \begin_layout Standard All numerical three-terminal element names begin with the letter 'Q'. If the device is a bipolar transistor, then the nodes are specified in the order: collector (nl), base (n2), emitter (n3). For a JFET or MESFET, the node order is: drain (n1), gate (n2), source (n3). After this must come the name of the model used for the element. The remaining information can come in any order. The layout dimensions of an element are specified relative to the geometry of a default device. For the 1D BJT, the default device has an area of lm², and for 2D devices, the default device has a width of lm. In addition, it is assumed that the default 1D BJT has a base contact with area equal to the emitter area, length of 1µm and a depth automatically determined from the device doping profile. However, all these defaults can be overridden on an options card. \end_layout \begin_layout Standard The operating temperature of a device can be set independently from the rest of that of the circuit in order to simulate non-isothermal circuit operation. Finally, the name of a file containing an initial state for the device can be specified. Remember that if the filename contains capital letters, they must be protected by surrounding the filename with double quotes. Alternatively, the device can be placed in an OFF state (thermal equilibrium) at the beginning of the analysis. For more information on the use of initial conditions, see the NGSPICE User’s Manual. \end_layout \begin_layout Standard In addition to the element input parameters, there are output-only parameters that can be shown using the SPICE showcommand or captured using the \family typewriter save/.SAVE \family default command. These parameters are the elements of the indefinite conductance (G), capacitanc e (C), and admittance (Y) matrices where Y = G +jwC. By default, the parameters are computed at 1Hz. Each element is accessed using the name of the matrix (g, c or y) followed by the node indices of the output terminal and the input terminal (e.g. g11). Beware that parameter names are case-sensitive for \family typewriter save/show \family default , so lower-case letters must be used. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Level \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dimensionality of numerical model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative area factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative width factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temp \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Element operating temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IC.File \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial-conditions filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Device initially in OFF state \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conductance element \begin_inset Formula $G_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance element \begin_inset Formula $C_{ij}$ \end_inset , ( F ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout yIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Admittance element \begin_inset Formula $Y_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard A one-dimensional numerical bipolar transistor with an emitter stripe 4 times as wide as the default device is created using: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Q2 1 2 3 M_BJT AREA=4 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This example saves the output conductance (go), transconductance (gm) and input conductance (gpi) of the previous transistor in that order: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE @q2[g11] @q2[g12] @q2[g22] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The second example is for a two-dimensional JFET with a width of 5pm and initial conditions obtained from file "IC.jfet": \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout QJ1 11 12 13 M_JFET W=5um IC.FILE="IC.jfet" \end_layout \begin_layout Plain Layout .MODEL M_JFET NBJT LEVEL=2 \end_layout \begin_layout Plain Layout + options jfet \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A final example shows how to use symmetry to simulate half of a 2D BJT, avoiding having the user double the area of each instance: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout Q2 NC2 NB2 NE2 BJTMOD AREA=1 \end_layout \begin_layout Plain Layout Q3 NC3 NB3 NE3 BJTMOD AREA=1 \end_layout \begin_layout Plain Layout .MODEL BJTMOD NBJT LEVEL=2 \end_layout \begin_layout Plain Layout + options defw=2um \end_layout \begin_layout Plain Layout + * Define half of the device now \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard options, output \end_layout \begin_layout Subsection BUGS \end_layout \begin_layout Standard MESFETs cannot be simulated properly yet because Schottky contacts have not been implemented. \end_layout \begin_layout Section NUMOS \end_layout \begin_layout Standard MOSFET / four-terminal numerical models and elements \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Model: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .MODEL model-name NUMOS [level] \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Element: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout MXXXXXXX nl n2 n3 n4 model-name [geometry] \end_layout \begin_layout Plain Layout + [temperature] [initial-conditions] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout SYNOPSIS Output: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE [small-signal values] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection DESCRIPTION \end_layout \begin_layout Standard NUMOS is the name for a MOSFET numerical model. In addition, the 2D model can be used to simulate other four-terminal structure s such as integrated bipolar and JFET devices with substrate contacts. However, silicon controlled rectifiers (SCRs) cannot be simulated because of the snapback in the transfer characteristic. See the \series bold options \series default card for more information on how to customize the device type. The LEVEL parameter of two- and three-terminal devices is not needed, because only 2D devices are supported. However, it will accepted and ignored if provided. \end_layout \begin_layout Standard All numerical four-terminal element names begin with the letter ‘M’. If the device is a MOSFET, or JFET with a bulk contact, then the nodes are specified in the order: drain (n1), gate (n2), source (n3), bulk (n4). If the device is a BJT, the node order is: collector (n1), base (n2), emitter (n3), substrate (n4). After this must come the name of the model 1used for the element. The remaining information can come in any order. The layout dimensions of an element are specified relative to the geometry of a default device. The default device has a width of lm. However, this default can be overridden on an \series bold options \series default card. In addition, the element line will accept a length parameter, L, but does not use it in any calculations. This is provided to enable somewhat greater compatibility between numerical MOSFET models and the standard SPICE3 compact MOSFET models. \end_layout \begin_layout Standard The operating temperature of a device can be set independently from that of the rest of the circuit in order to simulate non-isothermal circuit operation. Finally, the name of a file containing an initial state for the device can be specified. Remember that if the filename contains capital letters, they must be protected by surrounding the filename with double quotes. Alternatively, the device can be placed in an OFF state (thermal equilibrium) at the beginning of the analysis. For more information on the use of initial conditions, see the NGSPICE User’s Manual. \end_layout \begin_layout Standard In addition to the element input parameters, there are output-only parameters that can be shown using the SPICE \family typewriter show \family default command or captured using the \family typewriter save/.SAVE \family default command. \end_layout \begin_layout Standard These parameters are the elements of the indefinite conductance (G), capacitance (C), and admittance (Y) matrices where Y = G+jwC. By default, the parameters are computed at 1 Hz. Each element is accessed using the name of the matrix (g, c or y) followed by the node indices of the output terminal and the input terminal (e.g. g11). Beware that parameter names are case-sensitive for \family typewriter save/show \family default , so lower-case letters must be used. \end_layout \begin_layout Subsection Parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Level \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dimensionality of numerical model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative area factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multiplicative width factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unused length factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temp \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Element operating temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IC.File \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout String \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial-conditions filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Device initially in OFF state \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Conductance element \begin_inset Formula $G_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance element \begin_inset Formula $C_{ij}$ \end_inset , ( F ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout yIJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Admittance element \begin_inset Formula $Y_{ij}$ \end_inset , ( \begin_inset Formula $\Omega$ \end_inset ) \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection EXAMPLES \end_layout \begin_layout Standard A numerical MOSFET with a gate width of 5µm and length of 1µm is described below. However, the model can only be used for lµm length devices, so the length parameter is redundant. The device is initially biased near its threshhold by taking an initialstate from the file "NM1.vth". \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout M1 1 2 3 4 M_NMOS_1UM W=5um L=1um IC.FILE="NM1.vth" \end_layout \begin_layout Plain Layout .MODEL MNMOS_1UM NUMOS \end_layout \begin_layout Plain Layout + * Description of a lum device \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This example saves the definite admittance matrix of the previous MOSFET where the source terminal (3) is used as the reference. (The definite admittance matrix is formed by deleting the third row and column from the indefinite admittance matrix.) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout .SAVE @m1[y11] @m1[y12] @ml[y14] \end_layout \begin_layout Plain Layout .SAVE @m1[y21] @m1[y22] @ml[y24] \end_layout \begin_layout Plain Layout .SAVE @m1[y41] @m1[y42] @ml[y44] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Bipolar transistors are usually specified in terms of their area relative to a unit device. The following example creates a unit-sized device: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout MQ1 NC NB NE NS N_BJT \end_layout \begin_layout Plain Layout .MODEL M_BJT NUMOS LEVEL=2 \end_layout \begin_layout Plain Layout + options bipolar defw=5um \end_layout \begin_layout Plain Layout + ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection SEE ALSO \end_layout \begin_layout Standard options, output \end_layout \begin_layout Section Cider examples \end_layout \begin_layout Standard The original \begin_inset CommandInset href LatexCommand href name "Cider User's manual" target "http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/2382.html" \end_inset , in its Appendix A, lists a lot of examples, starting at page 226. We do not reproduce these pages here, but ask you to refer to the original document. If you experience any difficulties downloading it, please send a note to the \begin_inset CommandInset href LatexCommand href name "ngspice users' mailing list" target "http://sourceforge.net/mailarchive/forum.php?forum_name=ngspice-users" \end_inset . \end_layout \begin_layout Part Appendices \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Model-and-Device" \end_inset Model and Device Parameters \end_layout \begin_layout Standard The following tables summarize the parameters available on each of the devices and models in ngspice. There are two tables for each type of device supported by ngspice. Input parameters to instances and models are parameters that can occur on an instance or model definition line in the form \family typewriter keyword=value \family default where \family typewriter keyword \family default is the parameter name as given in the tables. Default input parameters (such as the resistance of a resistor or the capacitan ce of a capacitor) obviously do not need the keyword specified. \end_layout \begin_layout Standard Output parameters are those additional parameters which are available for many types of instances for the output of operating point and debugging information. These parameters are specified as \family typewriter @device[keyword] \family default and are available for the most recent point computed or, if specified in a \family typewriter .save \family default statement, for an entire simulation as a normal output vector. Thus, to monitor the gate-to-source capacitance of a MOSFET, a command \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout save @m1[cgs] \end_layout \end_inset \end_layout \begin_layout Standard given before a transient simulation causes the specified capacitance value to be saved at each time-point, and a subsequent command such as \end_layout \begin_layout Standard \begin_inset listings inline false status open \begin_layout Plain Layout plot @m1[cgs] \end_layout \end_inset \end_layout \begin_layout Standard produces the desired plot. (Note that the \family sans show \family default command does not use this format). \end_layout \begin_layout Standard Some variables are listed as both input and output, and their output simply returns the previously input value, or the default value after the simulation has been run. Some parameter are input only because the output system can not handle variables of the given type yet, or the need for them as output variables has not been apparent. Many such input variables are available as output variables in a different format, such as the initial condition vectors that can be retrieved as individual initial condition values. Finally, internally derived values are output only and are provided for debugging and operating point output purposes. \end_layout \begin_layout Standard If you want to access a device parameter of a device used inside of a subcircuit , you may use the syntax as shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 width "100col%" special "none" height "1in" height_special "totalheight" status open \begin_layout Plain Layout General form: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout @device_identifier.subcircuit_name. \end_layout \begin_layout Plain Layout +.device_name[parameter] \end_layout \end_inset \end_layout \begin_layout Plain Layout Example input file: \end_layout \begin_layout Plain Layout \begin_inset listings inline false status open \begin_layout Plain Layout * transistor output characteristics \end_layout \begin_layout Plain Layout * two nested subcircuits \end_layout \begin_layout Plain Layout vdd d1 0 2.0 \end_layout \begin_layout Plain Layout vss vsss 0 0 \end_layout \begin_layout Plain Layout vsig g1 vsss 0 \end_layout \begin_layout Plain Layout xmos1 d1 g1 vsss level1 \end_layout \begin_layout Plain Layout .subckt level1 d3 g3 v3 \end_layout \begin_layout Plain Layout xmos2 d3 g3 v3 level2 \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout .subckt level2 d4 g4 v4 \end_layout \begin_layout Plain Layout m1 d4 g4 v4 v4 nmos w=1e-5 l=3.5e-007 \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout .dc vdd 0 5 0.1 vsig 0 5 1 \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout save all @m.xmos1.xmos2.m1[vdsat] \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot vss#branch $ current measured at the top level \end_layout \begin_layout Plain Layout plot @m.xmos1.xmos2.m1[vdsat] \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .MODEL NMOS NMOS LEVEL = 8 \end_layout \begin_layout Plain Layout +VERSION = 3.2.4 TNOM = 27 TOX = 7.4E-9 \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The device identifier is the first letter extracted from the device name, e.g. m for a MOS transistor. \end_layout \begin_layout Standard Please note that the parameter tables presented below do not provide the detailed information available about the parameters provided in the section on each device and model, but are provided as a quick reference guide. \end_layout \begin_layout Section Elementary Devices \end_layout \begin_layout Subsection Resistor \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Resistor.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Capacitor - Fixed capacitor \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Capacitor.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Inductor - Fixed inductor \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Inductor.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Mutual - Mutual Inductor \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Mutual.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Section Voltage and current sources \end_layout \begin_layout Subsection ASRC - Arbitrary source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/ASRC.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Isource - Independent current source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Isource.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Vsource - Independent voltage source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Vsource.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection CCCS - Current controlled current source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/CCCS.lyx" \end_inset \end_layout \begin_layout Subsection CCVS - Current controlled voltage source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/CCVS.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection VCCS - Voltage controlled current source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/VCCS.lyx" \end_inset \end_layout \begin_layout Subsection VCVS - Voltage controlled voltage source \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/VCVS.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Section Transmission Lines \end_layout \begin_layout Subsection CplLines - Simple Coupled Multiconductor Lines \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/CplLines.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection LTRA - Lossy transmission line \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/LTRA.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection Tranline - Lossless transmission line \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/Tranline.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection TransLine - Simple Lossy Transmission Line \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/TransLine.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection URC - Uniform R. C. line \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/URC.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Section BJTs \end_layout \begin_layout Subsection BJT - Bipolar Junction Transistor \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/BJT.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection BJT - Bipolar Junction Transistor Level 2 \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/BJT2.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection VBIC - Vertical Bipolar Inter-Company Model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/VBIC.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Section MOSFETs \end_layout \begin_layout Subsection MOS1 - Level 1 MOSFET model with Meyer capacitance model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/MOS1.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection MOS2 - Level 2 MOSFET model with Meyer capacitance model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/MOS2.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection MOS3 - Level 3 MOSFET model with Meyer capacitance model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/MOS3.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection MOS6 - Level 6 MOSFET model with Meyer capacitance model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/MOS6.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection MOS9 - Modified Level 3 MOSFET model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/MOS9.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection BSIM1 - Berkeley Short Channel IGFET Model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/BSIM1.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection BSIM2 - Berkeley Short Channel IGFET Model \end_layout \begin_layout Standard \begin_inset CommandInset include LatexCommand input filename "Tables/BSIM2.lyx" \end_inset \begin_inset Newpage pagebreak \end_inset \end_layout \begin_layout Subsection BSIM3 \end_layout \begin_layout Standard Detailed descriptions will not be given here. Please refer to the excellent \begin_inset CommandInset href LatexCommand href name "pdf manual" target "http://www-device.eecs.berkeley.edu/~bsim3/ftpv330/Mod_doc/b3v33manu.tar" \end_inset issued by University of California at Berkeley. \end_layout \begin_layout Subsection BSIM4 \end_layout \begin_layout Standard Detailed descriptions will not be given here. Please refer to the excellent \begin_inset CommandInset href LatexCommand href name "pdf manual" target "http://www-device.eecs.berkeley.edu/~bsim3/BSIM4/BSIM470/BSIM470_Manual.pdf" \end_inset issued by University of California at Berkeley. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Compilation-notes" \end_inset Compilation notes \end_layout \begin_layout Standard This file describes the procedures to install ngspice from sources. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Ngspice-Installation-under" \end_inset Ngspice Installation under LINUX (and other 'UNIXes') \end_layout \begin_layout Subsection Prerequisites \end_layout \begin_layout Standard Ngspice is written in C and thus a complete C compilation environment is needed. Almost any UNIX comes with a complete C development environment. Ngspice is developed on GNU/Linux with gcc and GNU make. \end_layout \begin_layout Standard The following software must be installed in your system to compile ngspice: \series bold bison \series default , \series bold flex, \series default and \series bold X11 \series default headers and libs. \end_layout \begin_layout Standard The X11 headers and libraries are typically available in an X11 development package from your LINUX distribution. \end_layout \begin_layout Standard If you want to compile the CVS source you need additional software: \series bold autoconf, automake, libtool, texinfo \series default . \end_layout \begin_layout Standard The following software may be needed when enabling additional features: \series bold editline, tcl/tk, blt. \end_layout \begin_layout Subsection Install from CVS \end_layout \begin_layout Standard This section describes how to install from source code taken direct from CVS. This will give you access to the most recent enhancements and corrections. However be careful as the code in CVS may be unstable. For user install instructions using source from released distributions, please see the sections titled 'Basic Install' and 'Advanced Install'. \end_layout \begin_layout Standard Download source from CVS as described on the \begin_inset CommandInset href LatexCommand href name "sourceforge ngspice CVS page" target "http://sourceforge.net/scm/?type=cvs&group_id=38962" \end_inset . Define and enter a directory of your choice, e.g. \family typewriter /home/myname/software/ \family default . Download the source code from CVS, for example by anonymous access by issuing the command \end_layout \begin_layout LyX-Code cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice \begin_inset Newline newline \end_inset co -P ngspice/ng-spice-rework \end_layout \begin_layout Standard You will find the sources in directory \family typewriter /home/myname/software/ngspice/ng-spice-rework \family default . Now enter the ngspice top level directory \family typewriter ng-spice-rework \family default (where the file INSTALL can be found). \end_layout \begin_layout Standard The project uses the GNU build process. You should be able to do the following: \end_layout \begin_layout Standard \family typewriter $ ./autogen.sh \end_layout \begin_layout Standard \family typewriter $ ./configure --with-x --enable-xspice --enable-cider \begin_inset Newline newline \end_inset --disable-debug --with-readline=yes \end_layout \begin_layout Standard \family typewriter $ make \end_layout \begin_layout Standard \family typewriter $ sudo make install \end_layout \begin_layout Standard See the section titled 'Advanced Install' for instructions about arguments that can be passed to \family typewriter ./configure \family default to customize the build and installation. The following arguments are already used here and may be called sort of \begin_inset Quotes eld \end_inset standard \begin_inset Quotes erd \end_inset : \end_layout \begin_layout Standard \family typewriter \series bold --enable-xspice \family default \series default Include the XSPICE extensions (see chapters \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" \end_inset ) \family typewriter \end_layout \begin_layout Standard \family typewriter \series bold --enable-cider \family default \series default Include CIDER numerical device simulator (see chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" \end_inset ) \end_layout \begin_layout Standard \family typewriter \series bold --disable-debug \family default \series default No debugging information included (optimized and compact code) \end_layout \begin_layout Standard \family typewriter \series bold --with-readline=yes \family default \series default Include an editor for the input command line (command history, backspace, insert etc.). If readline is not available, editline may be used. \end_layout \begin_layout Standard If a problem is found with the build process, please submit a report to the Ngspice development team. Please provide information about your system and any \family typewriter ./configure \family default arguments you are using, together with any error messages. Ideally you would have tried to fix the problem yourself first. If you have fixed the problem then the development team will love to hear from you. \end_layout \begin_layout Subsection Install from a tarball, e.g. ngspice-rework-24.tgz \end_layout \begin_layout Standard This covers installation from a tarball (for example ngspice-rework-24.tgz, to be found at http://sourceforge.net/projects/ngspice/files/). After downloading the tar ball to a local directory unpack it using: \end_layout \begin_layout Standard \family typewriter $ tar -zxvf ngspice-rework-24.tgz \end_layout \begin_layout Standard Now change directories in to the top-level source directory (where this text from the INSTALL file can be found). \end_layout \begin_layout Standard You should be able to do: \end_layout \begin_layout Standard \family typewriter $ ./configure --with-x --enable-xspice --disable-debug --with-readline=yes \end_layout \begin_layout Standard \family typewriter $ make \end_layout \begin_layout Standard \family typewriter $ sudo make install \end_layout \begin_layout Standard The default install dir is /usr/local/bin \end_layout \begin_layout Standard See the section titled 'Advanced Install' for instructions about arguments that can be passed to \family typewriter ./configure \family default to customize the build and installation. \end_layout \begin_layout Subsection Advanced Install \end_layout \begin_layout Standard Some extra options can be provided to './configure'. To get all available options do: \end_layout \begin_layout Standard \family typewriter $ ./configure --help \end_layout \begin_layout Standard Some of these options are generic to the GNU build process that is used by Ngspice, other are specific to Ngspice. \end_layout \begin_layout Standard The following sections provide some guidance and descriptions for many, but not all, of these options. \end_layout \begin_layout Subsubsection Options Specific to Using Ngspice \end_layout \begin_layout Standard \family typewriter \series bold --enable-adms \family default \series default ADMS is an experimental model compiler that translates Verilog-A compact models into C code that can be compiled into ngspice. This is still experimental, but working with some limitations to the models (e.g. no noise models). If you want to use it, please refer to the \begin_inset CommandInset href LatexCommand href name "ADMS section" target "http://ngspice.sourceforge.net/admshowto.html" \end_inset on ngspice web site . \end_layout \begin_layout Standard \family typewriter \series bold --enable-cider \family default \series default Cider is a mixed-level simulator that couples Spice3 and DSIM to simulate devices from their technological parameters. This part of the simulator is not compiled by default. \end_layout \begin_layout Standard \family typewriter \series bold --enable-ndev \family default \series default Enable NDEV interface, (experimental) A TCP/IP interface to external device simulator such as GSS. For more information, please visit the homepage of GSS at \begin_inset CommandInset href LatexCommand href target "http://gss-tcad.sourceforge.net" \end_inset \end_layout \begin_layout Standard \family typewriter \series bold --enable-newpred \family default \series default Enable the NEWPRED symbol in the code. \end_layout \begin_layout Standard \family typewriter \series bold --enable-xspice \family default \series default Enable XSpice enhancements, (experimental) A mixed signal simulator built upon spice3 with codemodel dynamic loading support. See chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" \end_inset and section \begin_inset CommandInset ref LatexCommand ref reference "par:XSPICE-Software-User's" \end_inset for details. \end_layout \begin_layout Standard \family typewriter \series bold --with-editline=yes \family default \series default Enables the use of the BSD editline library (libedit). \begin_inset Newline newline \end_inset See \begin_inset CommandInset href LatexCommand href target "http://www.thrysoee.dk/editline/" \end_inset . \end_layout \begin_layout Standard \family typewriter \series bold --with-readline=yes \family default \series default Enable \begin_inset CommandInset href LatexCommand href name "GNU readline support" target "http://tiswww.case.edu/php/chet/readline/rltop.html" \end_inset for the command line interface. \end_layout \begin_layout Standard \family typewriter \series bold --with-tcl=tcldir \family default \series default When configured with this option the tcl module "tclspice" is compiled and installed instead of plain ngspice. \end_layout \begin_layout Standard \family typewriter \series bold --enable-openmp \family default \series default Compile ngspice for multi-core processors. Paralleling is done by OpenMP (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-on-multi-core" \end_inset ). \end_layout \begin_layout Standard The following options are seldom used today, not tested, some may even no longer be implemented. \end_layout \begin_layout Standard \family typewriter \series bold --enable-capbypass \family default \series default Bypass calculation of cbd/cbs in the mosfets if the vbs/vbd voltages are unchanged. \end_layout \begin_layout Standard \family typewriter \series bold --enable-capzerobypass \family default \series default Bypass all the cbd/cbs calculations if Czero is zero. This is enabled by default since rework-18. \end_layout \begin_layout Standard \family typewriter \series bold --enable-cluster \family default \series default Clustering code for distributed simulation. This is a contribution never tested. This code comes from TCLspice implementation and is implemented for transient analysis only. \end_layout \begin_layout Standard \family typewriter \series bold --enable-expdevices \family default \series default Enable experimental devices. This option is used by developers to mask devices under development. Almost useless for users. \end_layout \begin_layout Standard \family typewriter \series bold --enable-experimental \family default \series default This enables some experimental code. Specifically it enables: * support for altering options in interactive mode by adding the interactive keyword 'options'. * The ability to save and load snapshots: adds interactive keywords 'savesnap' and 'loadsnap'. \end_layout \begin_layout Standard \family typewriter \series bold --enable-help \family default \series default Force building nghelp. This is deprecated. \end_layout \begin_layout Standard \family typewriter \series bold --enable-newtrunc \family default \series default Enable the newtrunc option \end_layout \begin_layout Standard \family typewriter \series bold --enable-nodelimiting \family default \series default Experimental damping scheme \end_layout \begin_layout Standard \family typewriter \series bold --enable-nobypass \family default \series default Don't bypass recalculations of slowly changing variables \end_layout \begin_layout Standard \family typewriter \series bold --enable-nosqrt \family default \series default Use always log/exp for non-linear capacitances --enable-predictor Enable a predictor method for convergence \end_layout \begin_layout Standard \family typewriter \series bold --enable-sense2 \family default \series default Use spice2 sensitivity analysis \end_layout \begin_layout Standard \family typewriter \series bold --enable-xgraph \family default \series default Compile the Xgraph plotting program. Xgraph is a plotting package for X11 and was once very popular. \end_layout \begin_layout Subsubsection Options Useful for Debugging Ngspice \end_layout \begin_layout Standard \family typewriter \series bold --disable-debug \family default \series default This option will remove the '-g' option passed to the compiler. This speeds up execution time (and compilation) a *lot*, and is recommended for normal use. \end_layout \begin_layout Standard The following options are seldom used today, not tested, some may even no longer be implemented. \end_layout \begin_layout Standard \family typewriter \series bold --enable-ansi \family default \series default Configure will try to find an option for your compiler so that it expects ansi-C. \end_layout \begin_layout Standard \family typewriter \series bold --enable-asdebug \family default \series default Debug sensitivity code *ASDEBUG*. \end_layout \begin_layout Standard \family typewriter \series bold --enable-blktmsdebug \family default \series default Debug distortion code *BLOCKTIMES* \end_layout \begin_layout Standard \family typewriter \series bold --enable-checkergcc \family default \series default Option for compilation with checkergcc. \end_layout \begin_layout Standard \family typewriter \series bold --enable-cpdebug \family default \series default Enable ngspice shell code debug. \end_layout \begin_layout Standard \family typewriter \series bold --enable-ftedebug \family default \series default Enable ngspice frontend debug. \end_layout \begin_layout Standard \family typewriter \series bold --enable-gc \family default \series default Enable the Boehm-Weiser Conservative Garbage Collector. \end_layout \begin_layout Standard \family typewriter \series bold --enable-pzdebug \family default \series default Debug pole/zero code. \end_layout \begin_layout Standard \family typewriter \series bold --enable-sensdebug \family default \series default Debug sensitivity code *SENSDEBUG*. \end_layout \begin_layout Standard \family typewriter \series bold --enable-smltmsdebug \family default \series default Debug distortion code *SMALLTIMES* \end_layout \begin_layout Standard \family typewriter \series bold --enable-smoketest \family default \series default Enable smoketest compile. \end_layout \begin_layout Standard \family typewriter \series bold --enable-stepdebug \family default \series default Turns on debugging of convergence steps in transient analysis \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:Compilation-using-an" \end_inset Compilation using an user defined directory tree for object files \end_layout \begin_layout Standard The procedures described above will store the *.o files (output of the compilatio n step) into the directories where the sources (*.c) are located. This may not be the best option if you want for example to maintain a debug version and in parallel a release version of ngspice ( \family typewriter ./configure --disable-debug \family default ). So if you intend to create a separate object file tree like ng-spice-rework/ngb uild/release, you may do the following, starting from the default directory ng-spice-rework: \end_layout \begin_layout Standard \family typewriter mkdir -p release \end_layout \begin_layout Standard \family typewriter cd release \end_layout \begin_layout Standard \family typewriter ../configure \end_layout \begin_layout Standard \family typewriter make install \end_layout \begin_layout Standard This will create an object file directory tree, similar to the source file directory tree, the object files are now separated from the source files. For the debug version, you may do the same as described above, replacing 'release' by 'debug', and obtain another separated object file directory tree. If you already have run \family typewriter ./configure \family default in ng-spice-rework, you have to do a maintainer-clean, before the above procedure will work. \end_layout \begin_layout Subsection Compilers and Options \end_layout \begin_layout Standard Some systems require unusual options for compilation or linking that the `configure' script does not know about. You can give `configure' initial values for variables by setting them in the environment. Using a Bourne-compatible shell, you can do that on the command line like this: \end_layout \begin_layout Standard \family typewriter CC=c89 \end_layout \begin_layout Standard \family typewriter CFLAGS=-O2 \end_layout \begin_layout Standard \family typewriter LIBS=-lposix \end_layout \begin_layout Standard \family typewriter ./configure \end_layout \begin_layout Standard Or on systems that have the `env' program, you can do it like this: \end_layout \begin_layout Standard \family typewriter env CPPFLAGS=-I/usr/local/include \end_layout \begin_layout Standard \family typewriter LDFLAGS=-s \end_layout \begin_layout Standard \family typewriter ./configure \end_layout \begin_layout Subsection Compiling For Multiple Architectures \end_layout \begin_layout Standard You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you must use a version of `make' that supports the `VPATH' variable, such as GNU `make'. `cd' to the directory where you want the object files and executables to go and run the `configure' script. `configure' automatically checks for the source code in the directory that `configure' is in and in `..'. \end_layout \begin_layout Standard If you have to use a `make' that does not supports the `VPATH' variable, you have to compile the package for one architecture at a time in the source code directory. After you have installed the package for one architecture, use `make distclean' before reconfiguring for another architecture. \end_layout \begin_layout Subsection Installation Names \end_layout \begin_layout Standard By default, `make install' will install the package's files in `/usr/local/bin', `/usr/local/man', etc. You can specify an installation prefix other than `/usr/local' by giving `configure' the option `--prefix=PATH'. \end_layout \begin_layout Standard You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you give `configure' the option `--exec-prefix=PATH', the package will use PATH as the prefix for installing programs and libraries. Documentation and other data files will still use the regular prefix. \end_layout \begin_layout Standard In addition, if you use an unusual directory layout you can give options like `--bindir=PATH' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. \end_layout \begin_layout Standard If the package supports it, you can cause programs to be installed with an extra prefix or suffix on their names by giving `configure' the option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. \end_layout \begin_layout Standard When installed on MinGW with MSYS alternative paths are not fully supported. See 'How to make ngspice with MINGW and MSYS' below for details. \end_layout \begin_layout Subsection Optional Features \end_layout \begin_layout Standard Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The `README' should mention any `--enable-' and `--with-' options that the package recognizes. \end_layout \begin_layout Standard For packages that use the X Window System, `configure' can usually find the X include and library files automatically, but if it doesn't, you can use the `configure' options `--x-includes=DIR' and `--x-libraries=DIR' to specify their locations. \end_layout \begin_layout Subsection Specifying the System Type \end_layout \begin_layout Standard There may be some features `configure' can not figure out automatically, but needs to determine by the type of host the package will run on. Usually `configure' can figure that out, but if it prints a message saying it can not guess the host type, give it the `--host=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name with three fields: CPU-COMPANY-SYSTEM \end_layout \begin_layout Standard See the file `config.sub' for the possible values of each field. If `config.sub' isn't included in this package, then this package doesn't need to know the host type. \end_layout \begin_layout Standard If you are building compiler tools for cross-compiling, you can also use the `--target=TYPE' option to select the type of system they will produce code for and the `--build=TYPE' option to select the type of system on which you are compiling the package. \end_layout \begin_layout Subsection Sharing Defaults \end_layout \begin_layout Standard If you want to set default values for `configure' scripts to share, you can create a site shell script called `config.site' that gives default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/ config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. A warning: not all `configure' scripts look for a site script. \end_layout \begin_layout Subsection Operation Controls \end_layout \begin_layout Standard `configure' recognizes the following options to control how it operates. \end_layout \begin_layout Standard \family typewriter \series bold `--cache-file=FILE' \family default \series default Use and save the results of the tests in FILE instead of `./config.cache'. Set FILE to `/dev/null' to disable caching, for debugging `configure'. \end_layout \begin_layout Standard \family typewriter \series bold `--help' \family default \series default Print a summary of the options to `configure', and exit. \end_layout \begin_layout Standard \family typewriter \series bold `--quiet' `--silent' `-q' \family default \series default Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). \end_layout \begin_layout Standard \family typewriter \series bold `--srcdir=DIR' \family default \series default Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. \end_layout \begin_layout Standard \family typewriter \series bold `--version' \family default \series default Print the version of Autoconf used to generate the `configure' script, and exit. \end_layout \begin_layout Standard \family typewriter \series bold `configure' \family default \series default also accepts some other, not widely useful, options. \end_layout \begin_layout Section NGSPICE COMPILATION UNDER WINDOWS OS \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:How-to-make" \end_inset How to make ngspice with MINGW and MSYS \end_layout \begin_layout Standard Creating ngspice with MINGW is now a straight forward procedure, if you have MSYS/MINGW installed properly. Unfortunately the installation is rather tedious because you will need several enhancements to the standard install, especially if you want to include XSpice. Some links are given below which describe the procedures. The default installation location of ngspice is the Windows path C: \backslash spice. The install path can be altered by passing \family typewriter --prefix=NEWPATH \family default as an argument to \family typewriter ./configure \family default during the build process. \end_layout \begin_layout Standard Put the install path you desire inside "", e.g. \family typewriter "D:/NewSpice" \family default . Be careful to use forward slashes "/", not backward slashes " \backslash " (something still to be fixed). Then add \family typewriter --prefix="D:/NewSpice" \family default as an argument to \family typewriter ./configure \family default in the normal way. \end_layout \begin_layout Standard The procedure of compiling a distribution (for example, a the most recent stable distribution from the ngspice website, e.g. ngspice-24.tar.gz), is as follows: \end_layout \begin_layout Standard \family typewriter $ cd ng-spice-rework \end_layout \begin_layout Standard \family typewriter $ cd release \end_layout \begin_layout Standard \family typewriter $ ../configure --with-windows \family default ...and other options \family typewriter \end_layout \begin_layout Standard \family typewriter $ make \end_layout \begin_layout Standard \family typewriter $ make install \end_layout \begin_layout Standard The useful options are: \end_layout \begin_layout Standard \family typewriter \series bold --enable-xspice \family default \series default (this requires FLEX and BISON available in MSYS, see below). \end_layout \begin_layout Standard \family typewriter \series bold --enable-cider \end_layout \begin_layout Standard \family typewriter \series bold --disable-debug \family default \series default (-O2 optimization, no debug information) \end_layout \begin_layout Standard A complete ngspice (release version, no debug info, optimized executable) may be made available just by \end_layout \begin_layout Standard \family typewriter $ cd ng-spice-rework \end_layout \begin_layout Standard \family typewriter $ ./compile_min.sh \end_layout \begin_layout Standard If you want to compile the CVS source you need additional software packages \series bold cvs, autoconf, automake, libtool, \series default available from the MSYS distribution \series bold . \end_layout \begin_layout Standard Define and enter a directory of your choice, e.g. /d/spice/. Download the source code from CVS, for example by anonymous access by issuing the command \end_layout \begin_layout LyX-Code cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice co -P ngspice/ng-spice-rework \end_layout \begin_layout Standard You will find the sources in directory \family typewriter /d/spice/ngspice/ng-spice-rework \family default . Now enter the ngspice top level directory \family typewriter ng-spice-rework \family default . To compile the code just obtained from the CVS repository the procedure is a little bit different: \end_layout \begin_layout Standard \family typewriter $ cd ng-spice-rework \end_layout \begin_layout Standard \family typewriter $ ./autogen.sh \end_layout \begin_layout Standard \family typewriter $ mkdir release \end_layout \begin_layout Standard \family typewriter $ cd release \end_layout \begin_layout Standard \family typewriter $ ../configure --with-windows \family default ...and other options \family typewriter \end_layout \begin_layout Standard \family typewriter $ make \end_layout \begin_layout Standard \family typewriter $ make install \end_layout \begin_layout Standard The user defined build tree saves the object files, instead of putting them into the source tree, in a release (and a debug) tree. Please see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:Compilation-using-an" \end_inset for instructions. \end_layout \begin_layout Standard If you need updating your local source code tree from CVS, just enter \family typewriter ng-spice-rework \family default and issue the command \end_layout \begin_layout LyX-Code cvs -z3 -q -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice -lf update -d -P \end_layout \begin_layout Standard MINGW and MSYS can be downloaded from \begin_inset CommandInset href LatexCommand href target "http://www.mingw.org/" \end_inset . The making of the code models *.cm for XSpice and one of the ngspice parsers require the installation of BISON and FLEX to MSYS. A typical installation was tested with: bison-2.0-MSYS.tar.gz flex-2.5.4a-1-bin.zip libiconv-1.9.2-1-bin.zip libintl-0.14.4-bin.zip \end_layout \begin_layout Standard Bison 2.0 is now superseded by newer releases \begin_inset Newline newline \end_inset (Bison 2.3, see \begin_inset CommandInset href LatexCommand href target "http://sourceforge.net/project/showfiles.php?group_id=2435&package_id=67879" \end_inset ) \end_layout \begin_layout Standard The last three are from \begin_inset CommandInset href LatexCommand href target " http://sourceforge.net/project/showfiles.php?group_id=23617" \end_inset . \end_layout \begin_layout Standard You may also look at \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://www.mingw.org/wiki/HOWTO_Install_the_MinGW_GCC_Compiler_Suite" \end_inset \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://www.mingw.org/wiki/MSYS " \end_inset \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href target "http://www.mingw.org/wiki/HOWTO_Create_an_MSYS_Build_Environment." \end_inset \end_layout \begin_layout Subsection 64 Bit executables with MINGW-w64 \end_layout \begin_layout Standard \series bold Procedure: \end_layout \begin_layout Standard Install MSYS, plus bison, flex, auto tools, perl, libiconv, libintl \end_layout \begin_layout Standard Install MINGW-w64, activate OpenMP support \end_layout \begin_layout Standard See either \begin_inset CommandInset href LatexCommand href target "http://mingw-w64.sourceforge.net/" \end_inset or \begin_inset CommandInset href LatexCommand href target "http://tdm-gcc.tdragon.net/" \end_inset \end_layout \begin_layout Standard (allows to generate both 32 or 64 bit executables by setting flag -m32 or -m64) \end_layout \begin_layout Standard Set path to compiler in msys/xx/etc/fstab (e.g. c:/MinGW64 /mingw) \end_layout \begin_layout Standard Start compiling with \end_layout \begin_layout Standard './compile_min.sh' or './compile_min.sh 64' \end_layout \begin_layout Standard Options used in the script: \end_layout \begin_layout Standard --adms and --enable-adms ADMS is an experimental model compiler that translates Verilog-A compact models into C code that can be compiled into ngspice. This is still experimental, but working with some limitations to the models (e.g. no noise models). If you want to use it, please refer to the \begin_inset CommandInset href LatexCommand href name "ADMS section" target "http://ngspice.sourceforge.net/admshowto.html" \end_inset on ngspice web site . \end_layout \begin_layout Standard CIDER, XSPICE, and OpenMP may be selected at will. \end_layout \begin_layout Standard --disable-debug will give O2 optimization (versus O0 for debug) and removes all debugging info. \end_layout \begin_layout Standard The install script will copy all files to C: \backslash Spice or C: \backslash Spice64, the code models for XSPICE will be stored in C: \backslash Spice \backslash lib \backslash spice or C: \backslash Spice64 \backslash lib \backslash spice respectively. \end_layout \begin_layout Standard \series bold A word of caution: \series default Be aware that there might be some bugs in your 64 bit code. We still have some compiler warnings about integer incompatibility (e.g. integer versus size_t etc.)! We will take care of that for the next release. \end_layout \begin_layout Subsection make ngspice with MS Visual Studio 2008 \end_layout \begin_layout Standard ngspice may be compiled with MS Visual Studio 2008. Support for MS Visual Studio 2010 is not yet available. \end_layout \begin_layout Standard CIDER and XSPICE are included, but the code models for XSPICE (*.cm) are not (yet) made. You may however use the code models (which in fact are dlls) created with MINGW, as e.g. found in the ngspice binary distribution. There is currently no installation procedure provided, you may however install the executable manually as described in the installation tree below. The directory (visualc) with its files vngspice.sln (project starter) and vngspice.vcproj (project contents) allows to compile and link ngspice with MS Visual Studio 2008. The project is probably not compatible with Visual Studio 2005 and not yet with 2010. \end_layout \begin_layout Standard /visualc/include contains a dedicated config.h file. It contains the preprocessor definitions required to properly compile the code. strings.h has been necessary during setting up the project. \end_layout \begin_layout Standard Install Microsoft Visual Studio 2008 C++ . The MS VS 2008 C++ Express Edition (which is available at no cost from \begin_inset CommandInset href LatexCommand href target "http://www.microsoft.com/express/product/default.aspx" \end_inset ) is adequate, if you do not wish to have OpenMP or 64 bit support. So the express edition will allow a 32 bit Release and a Debug version of ngspice, using the Win32 flag. In addition you may select a console version without graphics interface. The professional edition will offer Release and Debug and Console also for 64 bit (flag x64), as well as an OpenMP variant for 32 or 64 bit. \end_layout \begin_layout Standard \series bold Procedure: \end_layout \begin_layout Standard Goto /ng-spice-rework/visualc. \end_layout \begin_layout Standard Start MS Visual Studio 2008 by double click onto vngspice.sln. After MS Visual Studio has opened up, select debug or release version by checking 'Erstellen' , 'Konfigurations-Manager' 'Debug' or 'Release'. Start making ngspice (called vngspice.exe) by selecting 'Erstellen' and 'vngspice neu erstellen'. Object files will be created and stored in visualc/debug or visualc/release. The executable will be stored to visualc/debug/bin or visualc/release/bin. \end_layout \begin_layout Standard An installation tree (as provided with MINGW make install) and also used by vngspice in its current distribution is shown in the following table (maybe created manually): \begin_inset Float table wide false sideways false status open \begin_layout Plain Layout C: \backslash Spice \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset bin \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.exe \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset nghelp.exe \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngmakeidx.exe \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngnutmeg.exe \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset cmpp.exe \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset lib \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset spice \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset analog.cm \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset digital.cm \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset spice2poly.cm \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset extradev.cm \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset extravt.cm \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset share \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset info \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset dir \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.info \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.info-1 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset .. \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.info-10 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset man \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset man1 \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngmultidec.1 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngnutmeg.1 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngsconvert.1 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.1 \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ng-spice-rework \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset helpdir \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.idx \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ngspice.txt \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset scripts \backslash \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset ciderinit \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset devaxis \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset devload \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset setplot \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset spectrum \end_layout \begin_layout Plain Layout \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset \begin_inset space \hspace{} \length 5mm \end_inset spinit \end_layout \begin_layout Plain Layout \begin_inset Caption \begin_layout Plain Layout ngspice standard installation tree under MS Windows \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you intend to install vngspice into another directory, e.g. D: \backslash MySpice, you have to edit /visualc/include/config.h and alter the following entries from: \end_layout \begin_layout Standard \family typewriter #define NGSPICEBINDIR "C:/Spice/bin" \end_layout \begin_layout Standard \family typewriter #define NGSPICEDATADIR "C:/Spice/share/ng-spice-rework" \end_layout \begin_layout Standard to \end_layout \begin_layout Standard \family typewriter #define NGSPICEBINDIR "D:/MySpice/bin" \end_layout \begin_layout Standard \family typewriter #define NGSPICEDATADIR "D:/MySpice/share/ng-spice-rework" \family default \end_layout \begin_layout Standard nghelp.exe is deprecated and no longer offered, but still available in the binary distribution. If the code model files *.cm are not available, you will get warning messages, but you may use ngspice in the normal way (of course without XSPICE extensions). \series bold To-Do \series default : Some commands in how-to-ngspice-vstudio.txt and mentioned above have to be translated to English. \end_layout \begin_layout Subsection make ngspice with pure CYGWIN \end_layout \begin_layout Standard If you don't have libdl.a you may need to link libcygwin.a to libdl.a symbolically. \end_layout \begin_layout Standard for example: \end_layout \begin_layout Standard \family typewriter $ cd /lib $ ln -s libcygwin.a libdl.a. \end_layout \begin_layout Standard The procedure of compiling is the same as with Linux (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" \end_inset ). \end_layout \begin_layout Subsection make ngspice with CYGWIN and external MINGW32 \end_layout \begin_layout Subsubsection* The next two compilation options are deprecated and not tested. \end_layout \begin_layout Standard according to http://www.geocrawler.com/lists/3/SourceForge/6013/0/7321042/ \end_layout \begin_layout Standard \family typewriter $ cd ng-spice-rework \end_layout \begin_layout Standard \family typewriter $ export PATH="/cygdrive/g/gcc_mingw/bin:$PATH" \end_layout \begin_layout Standard \family typewriter $ autoconf \end_layout \begin_layout Standard \family typewriter $ rm config.cache \end_layout \begin_layout Standard \family typewriter $ ./configure --with-windows --prefix="/cygdrive/g/gcc_mingw/bin" \end_layout \begin_layout Standard \family typewriter $ make clean \end_layout \begin_layout Standard \family typewriter $ make 2> make.err \end_layout \begin_layout Standard \family typewriter $ cp config.h config_ming.h \end_layout \begin_layout Standard ngspice.exe is o.k.,but make tests does not work (cannot direct console output into file). Needs to add .save "what" "where.test" to every input (*.cir) file. Also all given output files have to be adapted to WINDOWS (CR/LF instead of only LF at each line ending) for allowing proper comparison. \end_layout \begin_layout Subsection make ngspice with CYGWIN and internal MINGW32 (use config.h made above) \end_layout \begin_layout Standard \family typewriter $ cd ng-spice-rework \end_layout \begin_layout Standard \family typewriter $ rm config.cache \end_layout \begin_layout Standard \family typewriter $ export CFLAGS="-mno-cygwin -g -O2" \end_layout \begin_layout Standard \family typewriter $ export LDFLAGS="-L/lib/mingw" \end_layout \begin_layout Standard \family typewriter $ export CPPFLAGS="-I/usr/include/mingw" \end_layout \begin_layout Standard \family typewriter $ ./configure --with-windows \end_layout \begin_layout Standard \family typewriter $ cp config_ming.h config.h \end_layout \begin_layout Standard \family typewriter $ make clean \end_layout \begin_layout Standard \family typewriter $ make 2> make.err \end_layout \begin_layout Standard \family typewriter ./configure \family default does not work correctly: It finds headers and libs which are not really available in the -mno-cygwin port of MINGW32. Therefore config.h is not o.k. \end_layout \begin_layout Standard To-Do: find appropriate presets for variables ? rewrite tests for headers and libs (search exclusively in mingw directories) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:ngspice-mingw-or" \end_inset ngspice mingw or cygwin console executable \end_layout \begin_layout Standard If you omit the configure flag \begin_inset Quotes eld \end_inset --with-windows \begin_inset Quotes erd \end_inset , you will obtain a console application. \end_layout \begin_layout LyX-Code ./configure --enable-xspice --enable-cider --enable-openmp \begin_inset Newline newline \end_inset --disable-debug CFLAGS=-m32 LDFLAGS=-m32 prefix=C:/Spice \end_layout \begin_layout Standard is an example for TDM mingw, 32 Bit ngspice console. \end_layout \begin_layout Section Reporting errors \end_layout \begin_layout Standard Setting up ngspice is a complex task. The source code contains over 1500 files. ngspice should run on various operating systems. Therefore errors may be found, some still evolving from the original spice3f5 code, others introduced during the ongoing code enhancements. \end_layout \begin_layout Standard If you happen to experience an error during compilation of ngspice, please send a report to the development team. Ngspice is hosted on sourceforge, the preferred place to post a bug report is the \begin_inset CommandInset href LatexCommand href name "ngspice bug tracker" target "http://sourceforge.net/tracker/?group_id=38962&atid=423915" \end_inset . We would prefer to have your bug tested against the actual source code available at CVS, but of course a report using the most recent ngspice release is welcome! Please provide the following information with your report: \end_layout \begin_layout Standard Ngspice version \end_layout \begin_layout Standard Operating system \end_layout \begin_layout Standard Small input file to reproduce the bug (if to report a runtime error) \end_layout \begin_layout Standard Actual output versus the expected output \end_layout \begin_layout Chapter Copyrights and licenses \end_layout \begin_layout Section Documentation license \end_layout \begin_layout Subsection Spice documentation copyright \end_layout \begin_layout Standard Copyright 1996 The Regents of the University of California. \end_layout \begin_layout Standard Permission to use, copy, modify, and distribute this software and its documentat ion for educational, research and non-profit purposes, without fee, and without a written agreement is hereby granted, provided that the above copyright notice, this paragraph and the following three paragraphs appear in all copies. This software program and documentation are copyrighted by The Regents of the University of California. The software program and documentation are supplied "as is", without any accompanying services from The Regents. The Regents does not warrant that the operation of the program will be uninterrupted or error-free. The end-user understands that the program was developed for research purposes and is advised not to rely exclusively on the program for any reason. \end_layout \begin_layout Standard IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. \end_layout \begin_layout Subsection XSPICE SOFTWARE copyright \end_layout \begin_layout Standard \noindent Code added to SPICE3 to create the XSPICE Simulator and the XSPICE Code Model Subsystem was developed at the Computer Science and Information Technolog y Laboratory, Georgia Tech Research Institute, Atlanta GA, and is covered by license agreement the following copyright: \end_layout \begin_layout Standard \noindent Copyright © 1992 Georgia Tech Research Corporation All Rights Reserved. This material may be reproduced by or for the U.S. Government pursuant to the copyright license under the clause at DFARS 252.227-7013 (Oct. 1988) \end_layout \begin_layout Standard \noindent Refer to U.C. Berkeley and Georgia Tech license agreements for additional information. \end_layout \begin_layout Subsection CIDER RESEARCH SOFTWARE AGREEMENT (superseded by \begin_inset CommandInset ref LatexCommand ref reference "sub:New,-modified-BSD" \end_inset ) \end_layout \begin_layout Standard This chapter specifies the terms under which the CIDER software and documentatio n coming with the original distribution are provided. This agreement is superseded by \begin_inset CommandInset ref LatexCommand ref reference "sub:New,-modified-BSD" \end_inset , the \begin_inset Quotes eld \end_inset modified \begin_inset Quotes erd \end_inset BSD licence. \end_layout \begin_layout Standard Software is distributed as is, completely without warranty or service support. The University of California and its employees are not liable for the condition or performance of the software. \end_layout \begin_layout Standard The University does not warrant that it owns the copyright or other proprietary rights to all software and documentation provided under this agreement, notwithstanding any copyright notice, and shall not be liable for any infringem ent of copyright or proprietary rights brought by third parties against the recipient of the software and documentation provided under this agreement. \end_layout \begin_layout Standard THE UNIVERSITY OF CALIFORNIA HEREBY DISCLAIMS ALL IMPLIED WARRANTIES, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE UNIVERSITY IS NOT LIABLE FOR ANY DAMAGES INCURRED BY THE RECIPIENT IN USE OF THE SOFTWARE AND DOCUMENTATION, INCLUDING DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. \end_layout \begin_layout Standard The University of California grants the recipient the right to modify, copy, and redistribute the software and documentation, both within the recipient's organization and externally, subject to the following restrictions: \end_layout \begin_layout Standard (a) The recipient agrees not to charge for the University of California code itself. The recipient may, however, charge for additions, extensions, or support. \end_layout \begin_layout Standard (b) In any product based on the software, the recipient agrees to acknowledge the research group that developed the software. This acknowledgment shall appear in the product documentation. \end_layout \begin_layout Standard (c) The recipient agrees to obey all U.S. Government restrictions governing redistribution or export of the software and documentation. \end_layout \begin_layout Standard All BSD licenses have been changed to the \begin_inset Quotes eld \end_inset modified \begin_inset Quotes erd \end_inset BSD license by UCB in 1999 (see chapt. \begin_inset CommandInset ref LatexCommand ref reference "sub:New,-modified-BSD" \end_inset ). \end_layout \begin_layout Section ngspice license \end_layout \begin_layout Standard The SPICE license is the \series bold \begin_inset Quotes eld \end_inset Modified \begin_inset Quotes erd \end_inset BSD license \series default , (see \begin_inset CommandInset href LatexCommand href target "http://embedded.eecs.berkeley.edu/pubs/downloads/spice/index.htm" \end_inset ). \series bold ngspice adopts this \begin_inset Quotes eld \end_inset Modified \begin_inset Quotes erd \end_inset BSD license as well for all of its source code (except of tclspice, which is under LGPLv2)! \end_layout \begin_layout Standard ******************************************************************************** ************* \end_layout \begin_layout Standard Copyright (c) 1985-1991 The Regents of the University of California. \end_layout \begin_layout Standard All rights reserved. \end_layout \begin_layout Standard Permission is hereby granted, without written agreement and without license or royalty fees, to use, copy, modify, and distribute this software and its documentation for any purpose, provided that the above copyright notice and the following two paragraphs appear in all copies of this software. \end_layout \begin_layout Standard IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. \end_layout \begin_layout Standard ******************************************************************************** ************** \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "sub:New,-modified-BSD" \end_inset \begin_inset Quotes eld \end_inset Modified \begin_inset Quotes erd \end_inset BSD license \end_layout \begin_layout Standard All \begin_inset Quotes eld \end_inset old \begin_inset Quotes erd \end_inset BSD licenses (of SPICE or CIDER) have been changed to the \begin_inset Quotes eld \end_inset modified \begin_inset Quotes erd \end_inset BSD license according to the following publication (see \begin_inset CommandInset href LatexCommand href target "ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change" \end_inset ): \end_layout \begin_layout Standard July 22, 1999 \end_layout \begin_layout Standard To All Licensees, Distributors of Any Version of BSD: \end_layout \begin_layout Standard As you know, certain of the Berkeley Software Distribution ("BSD") source code files require that further distributions of products containing all or portions of the software, acknowledge within their advertising materials that such products contain software developed by UC Berkeley and its contributo rs. \end_layout \begin_layout Standard Specifically, the provision reads: \end_layout \begin_layout Standard " 3. All advertising materials mentioning features or use of this software must display the following acknowledgment: This product includes software developed by the University of California, Berkeley and its contributors." \end_layout \begin_layout Standard Effective immediately, licensees and distributors are no longer required to include the acknowledgment within advertising materials. Accordingly, the foregoing paragraph of those BSD Unix files containing it is hereby deleted in its entirety. \end_layout \begin_layout Standard William Hoskins \end_layout \begin_layout Standard Director, Office of Technology Licensing \end_layout \begin_layout Standard University of California, Berkeley \end_layout \begin_layout Subsection Linking to GPLd libraries (e.g. readline): \end_layout \begin_layout Standard The readline manual at \begin_inset CommandInset href LatexCommand href target "http://tiswww.case.edu/php/chet/readline/rltop.html" \end_inset states: Readline is free software, distributed under the terms of the GNU General Public License, version 3. This means that if you want to use Readline in a program that you release or distribute to anyone, the program must be free software and have a GPL-compa tible license. \end_layout \begin_layout Standard According to \begin_inset CommandInset href LatexCommand href target "http://www.gnu.org/licenses/license-list.html" \end_inset , the \series bold modified BSD license \series default , thus also the ngspice license, belong to the family of \series bold GPL-Compatible Free Software Licenses \series default . Therefore the linking restrictions to readline, which have existed with the old BSD license, are no longer in effect. \end_layout \end_body \end_document ngspice-24/Tables/0000755000175000017500000000000011711023501015014 5ustar sylvestresylvestrengspice-24/Tables/BJT2.lyx0000644000175000017500000052473311711023501016271 0ustar sylvestresylvestre#LyX 1.6.4 created this file. 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Until the bug is fixed you can use this workaround: CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash `configure' Invocation ====================== `configure' recognizes the following options to control how it operates. `--help' `-h' Print a summary of the options to `configure', and exit. `--version' `-V' Print the version of Autoconf used to generate the `configure' script, and exit. `--cache-file=FILE' Enable the cache: use and save the results of the tests in FILE, traditionally `config.cache'. FILE defaults to `/dev/null' to disable caching. `--config-cache' `-C' Alias for `--cache-file=config.cache'. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `configure' also accepts some other, not widely useful, options. Run `configure --help' for more details. ngspice-24/AUTHORS0000644000175000017500000000020711711023501014651 0ustar sylvestresylvestrePaolo Nenzi Holger Vogt Dietmar Warning and many other contributors who provided the original spice3, CIDER and XSPICE documentation. ngspice-24/ChangeLog0000644000175000017500000002515511711023501015364 0ustar sylvestresylvestre ============================ ngspice-24 ================================== 2012-01-28 Robert Larice fix incompatibility with lyx 1.6 caused by an empty layout section: \begin_layout Standard \end_layout 2012-01-27 Holger Vogt * small updates, prepare release 24 2012-01-15 Holger Vogt * 16.11 2012-01-01 Holger Vogt * 16.11, 31.2.7 2012-01-01 Holger Vogt * 2.10, 16.13 2011-12-26 Holger Vogt * floor, ceil functions 2011-12-25 Holger Vogt * compatibility chapt. 16.13 2011-12-21 Holger Vogt * usage of int_ic in s_xfer chapt. 12.2.16 * update chapts. 5.2, 5.3: E- or G-Source with TABLE 2011-12-17 Holger Vogt * error handling chapt. 18.5 * chapt. 5.2, 5.3 2011-12-10 Holger Vogt * updates to chapts. 15 and 17 2011-12-07 Holger Vogt * new 12.2.9 multi_input_pwl block 2011-11-27 Holger Vogt * new 17.4.44 Remcirc 2011-11-26 Holger Vogt * new 17.7.8 Output redirection 2011-11-20 Holger Vogt * small update in intro 2011-11-05 Holger Vogt * small update to chapt. 31, 32 2011-11-01 Holger Vogt * small update to chapt. 31 2011-10-30 Holger Vogt * hisim_hv 1.2.2 in chapt. 11.2.14 2011-10-29 Holger Vogt * small updates to chapts. 2 and 6 2011-10-22 Holger Vogt * bug no. 3426444 * conversion to lyx16 improved 2011-10-17 Holger Vogt * moved back to lyx16 format for compatibility with debian stable * small addition to 17.4.40 2011-10-03 Holger Vogt * small corrections 2011-10-02 Holger Vogt * chapt. 17.4.4 altermod updated * chapt. 22.5.2 ASCO inv updated 2011-09-18 Holger Vogt * chapt. 17.4.4 altermod updated 2011-09-16 Holger Vogt * chapt. 22 updated 2011-09-15 Holger Vogt * chapt. 17.4.59 60 update on show, showmod 2011-09-14 Holger Vogt * chapt. 17.4.4 update on altermod 2011-09-11 Holger Vogt * chapt. 22 extended by op-amp example 2011-09-09 Holger Vogt * new chapt. 22 on circuit optimization inserted * several typos removed 2011-08-30 Holger Vogt * chapt. 26.4 2011-08-29 Holger Vogt * chapt. 26 2011-08-28 Holger Vogt * chapt. 23, 26 * images/XSPICE-Toplevel.gif 2011-08-27 Holger Vogt * chapt. 24.3 on how to create new code models * chapt. 26 on how to create new code models 2011-08-26 Holger Vogt * 29 device parameters from nested subcircuits 2011-08-09 Holger Vogt * 18.6 on Gnuplot added 2011-08-09 Holger Vogt * 15.3 uic to end of line 2011-08-06 Holger Vogt * add fcn cph(vector) to chapt. 17.1 2011-08-04 Paolo Nenzi * Added manual entries for PSS as written by Stefano Perticaroli and added * Stefano to ngspice contributors. * lyx updated to version 2.0 (not backward compatible). 2011-07-17 Holger Vogt * new fcns sinh, cosh, tanh chapt. 17 2011-07-16 Holger Vogt * Update chapt. 18 2011-07-10 Holger Vogt * 17.1 add NGSPICE_INPUT_DIR 2011-07-09 Holger Vogt * Update to chapters 20, 25 2011-07-03 Holger Vogt * 7.3 2011-06-23 Holger Vogt * new code model 'filesource' 2011-06-23 Holger Vogt * BSIM4.7 2011-06-05 Holger Vogt * update command 'destroy' ============================ ngspice-23 ================================== 2011-06-01 Holger Vogt * bug no. 3310132 fixed 2011-05-29 Holger Vogt * prepare for release 23 2011-05-24 Holger Vogt * update to MOS models (HiSIM) 2011-05-07 Dietmar Warning * MOS instance parameter delvto and mulu0 * First binning description 2011-05-04 Dietmar Warning * update of MOS table, add HiSIM HV model 2011-04-12 Dietmar Warning * update of MOS table 2011-03-18 Dietmar Warning * bjt nkf introduction 2011-03-16 Holger Vogt * 17.4.33 par('expression') not applicable 2011-03-05 Holger Vogt * 24.2.1.4 supply ramping updated 2011-02-22 Dietmar Warning * diode & bjt temperature model update 2011-02-22 Holger Vogt * Parameter sweep 17.7 2011-02-19 Holger Vogt * .measure 15.4 2011-02-15 Holger Vogt * CIDER manual, chapt. 28 2011-02-12 Holger Vogt * chapt. 21 on statistical analyis, various updates * new images added 2011-01-23 Holger Vogt * add 2 images, chapt. 27 2011-01-21 Holger Vogt * chapt. 22 update 2011-01-19 Holger Vogt * chapt. 25, example 3 update 2011-01-16 Holger Vogt * 4.1.8 TRRANDOM option to voltage source added 2011-01-11 Holger Vogt * 15.4.7 .width 2011-01-09 Holger Vogt * small updates 2011-01-08 Holger Vogt * 17.4.9 command 'cdump' 2011-01-03 Holger Vogt * small updates 2011-01-01 Holger Vogt * small updates 2011-01-01 Holger Vogt * new format (12 pt, Times Roman) * several updates 2010-12-29 Holger Vogt * 2.8.5 new functions for numparam 2010-12-25 Holger Vogt * 16.3.10 update to RTS transient noise 2010-12-18 Holger Vogt * 4.2.6, 16.3.10 RTS transient noise 2010-12-17 Holger Vogt * update 4.2.6 2010-12-13 Holger Vogt * chapt. 4.2.6 2010-12-11 Holger Vogt * chapt. 6.1 2010-11-27 Holger Vogt * 13.2.21 controlled one-shot * 4.2.6, 16.3.10 transient noise 2010-11-13 Holger Vogt * 3.2.14, 3.2.15 switch * 13.2.21 controlled one-shot 2010-11-01 Holger Vogt * 10.2.2 Modified Parker Skellern model 2010-10-31 Dietmar Warning * few corrections in 16.1.3 2010-10-25 Holger Vogt * 'linearize' only in ngspice 2010-10-25 Holger Vogt * scattering parameters in chapt. 18.9.2 2010-10-16 Holger Vogt * scattering parameters in chapt. 18.9 * new command wrs2p in chapt. 18.4.75 2010-10-15 Holger Vogt * more on licenses (now chapt. 32) 2010-10-13 Dietmar Warning * trtol setting if xspice enabled and no 'A' devices 2010-10-12 Holger Vogt * on licenses (readline linking) 2010-10-09 Holger Vogt * more on Monte Carlo (18.8) 2010-10-05 Dietmar Warning * small corrections regarding mos9 and adms 2010-10-03 Holger Vogt * decription on .ac and ac 2010-09-23 Holger Vogt * ngspice-22 2010-09-20 Holger Vogt * chapt. 2.8.1 2010-09-19 Holger Vogt * MINGW 64 bit support 2010-09-11 Holger Vogt * more on .measure 16.3.10 2010-09-08 Holger Vogt * start with .measure 16.3.10 2010-09-06 Holger Vogt * still version 21plus * 18.4.35 plot alli allv ally 2010-09-06 Holger Vogt * Version 22 2010-09-05 Holger Vogt * 18.4.50 Setscale 2010-09-02 Holger Vogt * 18.8 Monte-Carlo Simulation 2010-08-28 Holger Vogt * update 18.4, 18.7 2010-08-25 Holger Vogt * update 2.10 2010-08-24 Holger Vogt * tf, pipe, server etc. 2010-08-22 Holger Vogt * JFET, MESFET 2010-08-19 Holger Vogt * 17.2 Where to get ngspice 2010-08-17 Holger Vogt * Add a new chapter 14 on adms 2010-07-17 Holger Vogt * deftype 17.4.13 (already existing in ngspice) 2010-07-11 Holger Vogt * Chapt. 15.1.6 on options, new command 'option' 17.4.33 2010-07-11 Holger Vogt * Chapt. 16.7 update on trtol 2010-07-10 Holger Vogt * Chapt. 15.4.6 par('expression'): Algebraic expressions for output 2010-07-08 Holger Vogt * Chapt. 16.7 on simulation time added 2010-07-02 Holger Vogt * Chapt. 17.7.5 Example script 'spectrum' 2010-07-02 Holger Vogt * Chapt. 2.2.1 .TITLE added * Chapt. 16 BSOI OpenMP added * Chapt. 2.10 on parameters, non-linear sources and control scripts 2010-06-28 Holger Vogt * Chapt. 16.7 on OpenMP BSIM4 added 2010-06-22 Holger Vogt * version 21plus ****************** rework-21 ******************* 2010-06-20 Holger Vogt * manual.lyx, COPYING: copyright updates * NEWS small intro 2010-06-20 Robert Larice * Makefile: removed * .cvsignore, * AUTHORS, COPYING, NEWS, README, * INSTALL, * config/install-sh, config/missing, * Makefile.am, configure.ac, new files ng-spice-manual is a package of its own now. 2010-06-20 Holger Vogt * SOI stag model level number added 2010-06-16 Holger Vogt * Some corrections to chap. 16 2010-06-14 Holger Vogt * Final Update version 21, add chapter on environmental variables 2010-06-12 Robert Larice * Add capability to generate the pdf * Add capability to upload the pdf 2010-06-12 Holger Vogt * Remove pdf binary 2010-06-10 Holger Vogt * Version 21 2010-06-05 Holger Vogt * various updates (chapts. 1, 2 e.a.) 2010-06-05 Holger Vogt * update on spinit, .spiceinit and command line options 2010-06-04 Holger Vogt * chapt. 17.4.44 small update on 'save' command 2010-05-27 Holger Vogt * chapt. 6.1 new example 2010-05-26 Holger Vogt * chapt. 27 update on XSPICE api using cm_analog_alloc() and cm_event_alloc() 2010-05-18 Holger Vogt * update on enabling XSPICE 2010-05-13 Holger Vogt * update on vectors, new links added 2010-05-09 Holger Vogt * variable ngbehavior, some updates 2010-05-08 Holger Vogt * non linear sources (E, G) and non-linear elements (R, C, L) 2010-04-06 Holger Vogt * update Chapt. 6 (thanks to R. Larice) 2010-04-04 Holger Vogt * update .lib, .global, resistor 2010-03-29 Holger Vogt * updates in chapt. 17.4 2010-03-27 Holger Vogt * reshuffling of chapter, errors removed * ngspice start options explained 2010-03-20 Holger Vogt * hertz for B source 2010-03-07 Holger Vogt * time and temper for B source 2010-03-06 Holger Vogt * small updates, fixes 2010-03-02 Holger Vogt * option 'param' added to command 'listing' * pdf with hyperlinks inside the text 2010-03-01 Dietmar Warning * update fft window functions 2010-02-28 Holger Vogt * ternary function in B source (chapt. 5.6) 2010-02-27 Holger Vogt * Independent voltage source PWL update, Chapt. 4.2.4 * new command wrdata 2010-01-12 Holger Vogt * some updates on the fft and noise commands, section on plots added. 2010-01-27 Dietmar Warning * update kspice transmissionline chapter 2010-01-02 Holger Vogt * compose command added xfont, wfont, wfont_size variables added 2010-01-01 Holger Vogt * gnuplot command added 2009-12-31 Holger Vogt * update on availabilty and description of internal variables 2009-12-30 Holger Vogt * update on variable plotstyle 2009-12-28 Holger Vogt * some formatting, update to manual.pdf chapters 15, 16 reorganized, started to describe scripting spinit, strcmp added 2009-12-22 Dietmar Warning * a bit more precise B pwl description 2009-12-19 Holger Vogt * update on chapt. 14 .measure * update on chapt. 15 save * formatting various sections 2009-12-15 Holger Vogt * chapt. 14 start describing .measure 2009-12-07 Holger Vogt * chapt. 15 command line options updated 2009-12-06 Holger Vogt * chapt. 15.3 alter and altermod modified 2009-12-04 Dietmar Warning * first trx and cpl descriptions - but more as a placeholder 2009-11-21 Holger Vogt * description of .func in chap. 2.9 added. * chapter 26 on installation updated 2009-11-21 Holger Vogt * chapter 16 on GUIs introduced 2009-11-21 Holger Vogt * formatting the output (still much to be done!) chapter 15.1 functions added 2009-11-20 Holger Vogt * chapter 15.5 description postscript variables updated 2009-11-19 Holger Vogt * variable hcopypscolor 2009-11-07 Holger Vogt * replace . by _ in several codemodel descriptions of chapter 12 ngspice-24/README0000644000175000017500000000132411711023501014462 0ustar sylvestresylvestreThis Package contains the `Ngspice Users Manual' DESCRIPTION: ============ The Manual is composed from several LyX and image files. This Package provides rules to: * generate a pdf file from those. * install the pdf somewhere * build a tar-ball, for distribution USAGE: ====== eventually run: autoreconf -Wno-portability --install To `install' do something like: ./configure ; make ; make install Please read `INSTALL' for detailed instructions. REQUIREMENTS: ============= You need: `LyX' `TeX' and something like `texlive-lang-greek' You need: `GNU make' (wildcards are used) BUGS: ===== This Package does not support: Parallel Build Trees (a.k.a. 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