\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7)
\end_layout
\begin_layout Plain Layout
+ r=0 td=15NS
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Each pair of values (
\begin_inset Formula $T_{i}$
\end_inset
,
\begin_inset Formula $V_{i}$
\end_inset
) specifies that the value of the source is
\begin_inset Formula $V_{i}$
\end_inset
(in Volts or Amps) at time =
\begin_inset Formula $T_{i}$
\end_inset
.
The value of the source at intermediate values of time is determined by
using linear interpolation on the input values.
The parameter
\emph on
r
\emph default
determines a repeat time point.
If
\emph on
r
\emph default
is not given, the whole sequence of values (
\begin_inset Formula $T_{i}$
\end_inset
,
\begin_inset Formula $V_{i}$
\end_inset
) is issued once, then the output stays at its final value.
If
\shape italic
r = 0
\shape default
, the whole sequence from time 0 to time
\shape italic
Tn
\shape default
is repeated forever.
If
\shape italic
r = 10ns
\shape default
, the sequence between 10ns and 50ns is repeated forever.
the
\emph on
r
\emph default
value has to be one of the time points T1 to Tn of the PWL sequence.
If
\emph on
td
\emph default
is given, the whole PWL sequence is delayed by the value of
\shape italic
td
\shape default
.
\end_layout
\begin_layout Subsection
Single-Frequency FM
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General Form (the PHASE parameters are only possible when XSPICE is enabled):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
SFFM(VO VA FC MDI FS PHASEC PHASES)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
V1 12 0 SFFM(0 1M 20K 5 1K)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default value
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Offset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Amplitude
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Carrier frequency
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{TSTOP}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $Hz$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MDI
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Modulation index
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Signal frequency
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{TSTOP}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $Hz$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHASEC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
carrier phase
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
degrees
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHASES
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
signal phase
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
degrees
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
The shape of the waveform is described by the following equation:
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
V(t)=V_{O}+V_{A}\sin\left(2\pi\cdot FC\cdot t+MDI\:\sin\left(2\pi\cdot FS\cdot t+PHASES\right)+PHASEC\right)
\end{equation}
\end_inset
\end_layout
\begin_layout Subsection
Amplitude modulated source (AM)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General Form (the PHASE parameter is only possible when XSPICE is enabled):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
AM(VA VO MF FC TD PHASES)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
V1 12 0 AM(0.5 1 20K 5MEG 1m)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default value
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Amplitude
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Offset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Modulating frequency
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $Hz$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Carrier frequency
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{TSTOP}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $Hz$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Signal delay
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $s$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHASES
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Phase
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
degrees
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
The shape of the waveform is described by the following equation:
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
V(t)=V_{A}\left(VO+\sin\left(2\pi\cdot MF\cdot t\right)+PHASES\right)\sin\left(2\pi\cdot FC\cdot t+PHASES\right)
\end{equation}
\end_inset
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Transient-noise-source"
\end_inset
Transient noise source
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General Form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
TRNOISE(NA NT NALPHA NAMP RTSAM RTSCAPT RTSEMT)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
VNoiw 1 0 DC 0 TRNOISE(20n 0.5n 0 0) $ white
\end_layout
\begin_layout Plain Layout
VNoi1of 1 0 DC 0 TRNOISE(0 10p 1.1 12p) $ 1/f
\end_layout
\begin_layout Plain Layout
VNoiw1of 1 0 DC 0 TRNOISE(20 10p 1.1 12p) $ white and 1/f
\end_layout
\begin_layout Plain Layout
IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
\end_layout
\begin_layout Plain Layout
$ white, 1/f, RTS
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Transient noise is an experimental feature allowing (low frequency) transient
noise injection and analysis.
See Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Transient-noise-analysis"
\end_inset
for a detailed description.
\family typewriter
NA
\family default
is the Gaussian noise rms voltage amplitude,
\family typewriter
NT
\family default
is the time between sample values (breakpoints will be enforced on multiples
of this value).
\family typewriter
NALPHA
\family default
(exponent to the frequency dependency),
\family typewriter
NAMP
\family default
(rms voltage or current amplitude) are the parameters for 1/f noise,
\family typewriter
RTSAM
\family default
the random telegraph signal amplitude,
\family typewriter
RTSCAPT
\family default
the mean of the exponential distribution of the trap capture time, and
\family typewriter
RTSEMT
\family default
its emission time mean.
White Gaussian, 1/f, and
\family typewriter
RTS
\family default
noise may be combined into a single statement.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default value
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Rms noise amplitude (Gaussian)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Time step
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $sec$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NALPHA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1/f exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $0<\alpha<2$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NAMP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Amplitude (1/f)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RTSAM
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Amplitude
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
,
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RTSCAPT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Trap capture time
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $sec$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RTSEMT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Trap emission time
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $sec$
\end_inset
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
If you set
\family typewriter
NT
\family default
and
\family typewriter
RTSAM
\family default
to 0, the noise option
\family typewriter
TRNOISE
\family default
...
is ignored.
Thus you may switch off the noise contribution of an individual voltage
source
\family typewriter
VNOI
\family default
by the command
\end_layout
\begin_layout Standard
\family typewriter
alter @vnoi[trnoise] = [ 0 0 0 0 ] $ no noise
\end_layout
\begin_layout Standard
\family typewriter
alter @vrts[trnoise] = [ 0 0 0 0 0 0 0] $ no noise
\end_layout
\begin_layout Standard
See Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Alter*:-Change-a"
\end_inset
for the alter command.
\end_layout
\begin_layout Standard
You may switch off all
\family typewriter
TRNOISE
\family default
noise sources by setting
\end_layout
\begin_layout Standard
\family typewriter
set notrnoise
\end_layout
\begin_layout Standard
to your
\family sans
.spiceinit
\family default
file (for all your simulations) or into your control section in front of
the next run or tran command (for this specific and all following simulations).
The command
\end_layout
\begin_layout Standard
\family typewriter
unset notrnoise
\end_layout
\begin_layout Standard
will reinstate all noise sources.
\end_layout
\begin_layout Standard
The noise generators are implemented into the independent
\series bold
voltage
\series default
(vsrc) and
\series bold
current
\series default
(isrc) sources.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Random-voltage-source"
\end_inset
Random voltage source
\end_layout
\begin_layout Standard
The
\family typewriter
TRRANDOM
\family default
option yields statistically distributed voltage values, derived from the
ngspice random number generator.
These values may be used in the transient simulation directly within a
circuit, e.g.
for generating a specific noise voltage, but especially they may be used
in the control of behavioral sources (B, E, G sources
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Non-linear-Dependent-Sources"
\end_inset
, voltage controllable A sources
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Behavioral-Modeling"
\end_inset
, capacitors
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Capacitors,-dependent-on"
\end_inset
, inductors
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Inductors,-dependent-on"
\end_inset
, or resistors
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Resistors,-dependent-on"
\end_inset
) to simulate the circuit dependence on statistically varying device parameters.
A Monte-Carlo simulation may thus be handled in a single simulation run.
\end_layout
\begin_layout Standard
General Form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
TRRANDOM(TYPE TS | >>)
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
VR1 r1 0 dc 0 trrandom (2 10m 0 1) $ Gaussian
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
TYPE
\family default
determines the random variates generated: 1 is uniformly distributed, 2
Gaussian, 3 exponential, 4 Poisson.
\family typewriter
TS
\family default
is the duration of an individual voltage value.
\family typewriter
TD
\family default
is a time delay with 0 V output before the random voltage values start
up.
\family typewriter
PARAM1
\family default
and
\family typewriter
PARAM2
\family default
depend on the type selected.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
TYPE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
description
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PARAM1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PARAM2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Uniform
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Range
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Offset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gaussian
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Standard Dev.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Mean
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Exponential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Mean
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Offset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Poisson
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Lambda
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Offset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Subsection
External voltage or current input
\end_layout
\begin_layout Standard
General Form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
EXTERNAL
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Vex 1 0 dc 0 external
\end_layout
\begin_layout Plain Layout
Iex i1 i2 dc 0 external
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Voltages or currents may be set from the calling process, if ngspice is
compiled as a shared library and loaded by the process.
See Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Callback-functions-1"
\end_inset
for an explanation.
\end_layout
\begin_layout Subsection
Arbitrary Phase Sources
\end_layout
\begin_layout Standard
The XSPICE option supports arbitrary phase independent sources that output
at TIME=0.0 a value corresponding to some specified phase shift.
Other versions of SPICE use the TD (delay time) parameter to set phase-shifted
sources to their time-zero value until the delay time has elapsed.
The XSPICE phase parameter is specified in degrees and is included after
the SPICE3 parameters normally used to specify an independent source.
Partial XSPICE deck examples of usage for pulse and sine waveforms are
shown below:
\end_layout
\begin_layout LyX-Code
* Phase shift is specified after Berkeley defined parameters
\end_layout
\begin_layout LyX-Code
* on the independent source cards.
Phase shift for both of the
\end_layout
\begin_layout LyX-Code
* following is specified as +45 degrees
\end_layout
\begin_layout LyX-Code
*
\end_layout
\begin_layout LyX-Code
v1 1 0 0.0 sin(0 1 1k 0 0 45.0)
\end_layout
\begin_layout LyX-Code
r1 1 0 1k
\end_layout
\begin_layout LyX-Code
*
\end_layout
\begin_layout LyX-Code
v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0)
\end_layout
\begin_layout LyX-Code
r2 2 0 1k
\end_layout
\begin_layout LyX-Code
*
\end_layout
\begin_layout Section
Linear Dependent Sources
\end_layout
\begin_layout Standard
Ngspice allows circuits to contain linear dependent sources characterized
by any of the four equations
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $i=gv$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $v=ev$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $i=fi$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $v=hi$
\end_inset
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
where
\begin_inset Formula $g$
\end_inset
,
\begin_inset Formula $e$
\end_inset
,
\begin_inset Formula $f$
\end_inset
, and
\begin_inset Formula $h$
\end_inset
are constants representing transconductance, voltage gain, current gain,
and transresistance, respectively.
Non-linear dependent sources for voltages or currents (B, E, G) are described
in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Non-linear-Dependent-Sources"
\end_inset
.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Gxxxx:-Linear-Voltage-Controlled"
\end_inset
Gxxxx: Linear Voltage-Controlled Current Sources (VCCS)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
GXXXXXXX N+ N- NC+ NC- VALUE
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
G1 2 0 5 0 0.1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n+
\family default
\series default
and
\family typewriter
\series bold
n-
\family default
\series default
are the positive and negative nodes, respectively.
Current flow is from the positive node, through the source, to the negative
\end_layout
\begin_layout Standard
node.
\family typewriter
\series bold
nc+
\family default
\series default
and
\family typewriter
\series bold
nc-
\family default
\series default
are the positive and negative controlling nodes, respectively.
\family typewriter
\series bold
value
\family default
\series default
is the transconductance (in mhos).
\family typewriter
m
\family default
is an optional multiplier to the output current.
\family typewriter
val
\family default
may be a numerical value or an expression according to
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Syntax-of-expressions"
\end_inset
containing references to other parameters.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Exxxx:-Linear-Voltage-Controlled"
\end_inset
Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
EXXXXXXX N+ N- NC+ NC- VALUE
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
E1 2 3 14 1 2.0
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n+
\family default
\series default
is the positive node, and
\family typewriter
\series bold
n-
\family default
\series default
is the negative node.
\family typewriter
\series bold
nc+
\family default
\series default
and
\family typewriter
\series bold
nc-
\family default
\series default
are the positive and negative controlling nodes, respectively.
\family typewriter
\series bold
value
\family default
\series default
is the voltage gain.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Fxxxx:-Linear-Current-Controlled"
\end_inset
Fxxxx: Linear Current-Controlled Current Sources (CCCS)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
FXXXXXXX N+ N- VNAM VALUE
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
F1 13 5 VSENS 5 m=2
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n+
\family default
\series default
and
\family typewriter
\series bold
n-
\family default
\series default
are the positive and negative nodes, respectively.
Current flow is from the positive node, through the source, to the negative
node.
\family typewriter
\series bold
vnam
\family default
\series default
is the name of a voltage source through which the controlling current flows.
The direction of positive controlling current flow is from the positive
node, through the source, to the negative node of
\family typewriter
\series bold
vnam
\family default
\series default
.
\family typewriter
\series bold
value
\family default
\series default
is the current gain.
\family typewriter
m
\family default
is an optional multiplier to the output current.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Hxxxx:-Linear-Current-Controlled"
\end_inset
Hxxxx: Linear Current-Controlled Voltage Sources (CCVS)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
HXXXXXXX n+ n- vnam value
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
HX 5 17 VZ 0.5K
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n+
\family default
\series default
and
\family typewriter
\series bold
n-
\family default
\series default
are the positive and negative nodes, respectively.
\family typewriter
\series bold
vnam
\family default
\series default
is the name of a voltage source through which the controlling current flows.
The direction of positive controlling current flow is from the positive
node, through the source, to the negative node of
\family typewriter
\series bold
vnam
\family default
\series default
.
\family typewriter
\series bold
value
\family default
\series default
is the transresistance (in ohms).
\end_layout
\begin_layout Subsection
Polynomial Source Compatibility
\end_layout
\begin_layout Standard
Dependent polynomial sources available in SPICE2G6 are fully supported in
ngspice using the XSPICE extension (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:ngspice-with-the"
\end_inset
).
The form used to specify these sources is shown in Table
\begin_inset CommandInset ref
LatexCommand ref
reference "cap:Dependent-Polynomial-Sources"
\end_inset
.
For details on its usage please see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:POLY"
\end_inset
.
\end_layout
\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
Dependent Polynomial Sources
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
Source Type
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
Instance Card
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
POLYNOMIAL VCVS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
EXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
POLYNOMIAL VCCS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
GXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
POLYNOMIAL CCCS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
FXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
POLYNOMIAL CCVS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
HXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
\begin_inset CommandInset label
LatexCommand label
name "cap:Dependent-Polynomial-Sources"
\end_inset
Dependent Polynomial Sources
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "sec:Non-linear-Dependent-Sources"
\end_inset
Non-linear Dependent Sources (Behavioral Sources)
\end_layout
\begin_layout Standard
The non-linear dependent sources B ( see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:B-source-(ASRC)"
\end_inset
), E (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:E-source-(non-linear"
\end_inset
), G see (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:G-source-(non-linear"
\end_inset
) described in this chapter allow to generate voltages or currents that
result from evaluating a mathematical expression.
Internally E and G sources are converted to the more general B source.
All three sources may be used to introduce behavioral modeling and analysis.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:B-source-(ASRC)"
\end_inset
Bxxxx: Nonlinear dependent source (ASRC)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Syntax-and-usage"
\end_inset
Syntax and usage
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
BXXXXXXX n+ n-
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
B1 0 1 I=cos(v(1))+sin(v(2))
\end_layout
\begin_layout Plain Layout
B2 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1)
\end_layout
\begin_layout Plain Layout
B3 3 4 I=17
\end_layout
\begin_layout Plain Layout
B4 3 4 V=exp(pi^i(vdd))
\end_layout
\begin_layout Plain Layout
B5 2 0 V = V(1) < {Vlow} ? {Vlow} :
\end_layout
\begin_layout Plain Layout
+ V(1) > {Vhigh} ? {Vhigh} : V(1)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n+
\family default
\series default
is the positive node, and
\family typewriter
\series bold
n-
\family default
\series default
is the negative node.
The values of the
\family typewriter
\series bold
V
\family default
\series default
and
\family typewriter
\series bold
I
\family default
\series default
parameters determine the voltages and currents across and through the device,
respectively.
If
\family typewriter
\series bold
I
\family default
\series default
is given then the device is a current source, and if
\family typewriter
\series bold
V
\family default
\series default
is given the device is a voltage source.
One and only one of these parameters must be given.
\end_layout
\begin_layout Standard
A simple model is implemented for temperature behavior by the formula:
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
I(T)=I({\rm TNOM})\:\Bigl(1+TC_{1}(T-{\rm TNOM})+TC_{2}(T-{\rm TNOM})^{2}\Bigr)
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
or
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
V(T)=V({\rm TNOM})\Bigl(1+TC_{1}(T-{\rm TNOM})+TC_{2}(T-{\rm TNOM})^{2}\Bigr)
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
In the above formula, `
\begin_inset Formula $T$
\end_inset
' represents the instance temperature, which can be explicitly set using
the
\family typewriter
\series bold
temp
\family default
\series default
keyword or calculated using the circuit temperature and
\family typewriter
\series bold
dtemp
\family default
\series default
, if present.
If both
\family typewriter
\series bold
temp
\family default
\series default
and
\family typewriter
\series bold
dtemp
\family default
\series default
are specified, the latter is ignored.
\end_layout
\begin_layout Standard
The small-signal AC behavior of the nonlinear source is a linear dependent
source (or sources) with a proportionality constant equal to the derivative
(or derivatives) of the source at the DC operating point.
The expressions given for
\family typewriter
\series bold
V
\family default
\series default
and
\family typewriter
\series bold
I
\family default
\series default
may be any function of voltages and currents through voltage sources in
the system.
\end_layout
\begin_layout Standard
The following functions of a single real variable are defined:
\end_layout
\begin_layout Description
Trigonometric
\begin_inset space ~
\end_inset
functions: cos, sin, tan, acos, asin, atan
\end_layout
\begin_layout Description
Hyperbolic
\begin_inset space ~
\end_inset
functions: cosh, sinh, acosh, asinh, atanh
\end_layout
\begin_layout Description
Exponential
\begin_inset space ~
\end_inset
and
\begin_inset space ~
\end_inset
logarithmic: exp, ln, log, log10 (ln, log with base e, log10 with base 10)
\end_layout
\begin_layout Description
Other: abs, sqrt, u, u2, uramp, floor, ceil
\end_layout
\begin_layout Description
Functions of two variables are: min, max, pow
\end_layout
\begin_layout Description
Functions of three variables are: a ? b:c
\end_layout
\begin_layout Standard
The function `
\family typewriter
u
\family default
' is the unit step function, with a value of one for arguments greater than
zero and a value of zero for arguments less than zero.
The function `
\family typewriter
u2
\family default
' returns a value of zero for arguments less than zero, one for arguments
greater than one and assumes the value of the argument between these limits.
The function `
\family typewriter
uramp
\family default
' is the integral of the unit step: for an input x, the value is zero if
x is less than zero, or if x is greater than zero the value is x.
These three functions are useful in synthesizing piece-wise non-linear
functions, though convergence may be adversely affected.
\end_layout
\begin_layout Standard
The following standard operators are defined:
\family typewriter
+
\family default
,
\family typewriter
-
\family default
,
\family typewriter
*
\family default
,
\family typewriter
/
\family default
,
\family typewriter
^
\family default
, unary
\family typewriter
-
\end_layout
\begin_layout Standard
Logical operators are
\family typewriter
!=
\family default
,
\family typewriter
<>
\family default
,
\family typewriter
>=
\family default
,
\family typewriter
<=
\family default
,
\family typewriter
==
\family default
,
\family typewriter
>
\family default
,
\family typewriter
<
\family default
,
\family typewriter
||
\family default
,
\family typewriter
&&
\family default
,
\family typewriter
!
\family default
.
\end_layout
\begin_layout Standard
A ternary function is defined as
\family typewriter
a ? b : c
\family default
, which means
\family typewriter
IF a, THEN b, ELSE c
\family default
.
Be sure to place a space in front of `
\family typewriter
?
\family default
' to allow the parser distinguishing it from other tokens.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example: Ternary function
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
* B source test Clamped voltage source
\end_layout
\begin_layout Plain Layout
* C.
P.
Basso "Switched-mode power supplies", New York, 2008
\end_layout
\begin_layout Plain Layout
.param Vhigh = 4.6
\end_layout
\begin_layout Plain Layout
.param Vlow = 0.4
\end_layout
\begin_layout Plain Layout
Vin1 1 0 DC 0 PWL(0 0 1u 5)
\end_layout
\begin_layout Plain Layout
Bcl 2 0 V = V(1) < Vlow ? Vlow : V(1) > Vhigh ? Vhigh : V(1)
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
unset askquit
\end_layout
\begin_layout Plain Layout
tran 5n 1u
\end_layout
\begin_layout Plain Layout
plot V(2) vs V(1)
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
If the argument of log, ln, or sqrt becomes less than zero, the absolute
value of the argument is used.
If a divisor becomes zero or the argument of log or ln becomes zero, an
error will result.
Other problems may occur when the argument for a function in a partial
derivative enters a region where that function is undefined.
\end_layout
\begin_layout Standard
Parameters may be used like {Vlow} shown in the example above.
Parameters will be evaluated upon set up of the circuit, vectors like V(1)
will be evaluated during the simulation.
\end_layout
\begin_layout Standard
To get time into the expression you can integrate the current from a constant
current source with a capacitor and use the resulting voltage (don't forget
to set the initial voltage across the capacitor).
\end_layout
\begin_layout Standard
Non-linear resistors, capacitors, and inductors may be synthesized with
the nonlinear dependent source.
Nonlinear resistors, capacitors and inductors are implemented with their
linear counterparts by a change of variables implemented with the nonlinear
dependent source.
The following subcircuit will implement a nonlinear capacitor:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example: Non linear capacitor
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.Subckt nlcap pos neg
\end_layout
\begin_layout Plain Layout
* Bx: calculate f(input voltage)
\end_layout
\begin_layout Plain Layout
Bx 1 0 v = f(v(pos,neg))
\end_layout
\begin_layout Plain Layout
* Cx: linear capacitance
\end_layout
\begin_layout Plain Layout
Cx 2 0 1
\end_layout
\begin_layout Plain Layout
* Vx: Ammeter to measure current into the capacitor
\end_layout
\begin_layout Plain Layout
Vx 2 1 DC 0Volts
\end_layout
\begin_layout Plain Layout
* Drive the current through Cx back into the circuit
\end_layout
\begin_layout Plain Layout
Fx pos neg Vx 1
\end_layout
\begin_layout Plain Layout
.ends
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example for f(v(pos,neg)):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Bx 1 0 V = v(pos,neg)*v(pos,neg)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Non-linear resistors or inductors may be described in a similar manner.
An example for a nonlinear resistor using this template is shown below.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example: Non linear resistor
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
* use of 'hertz' variable in nonlinear resistor
\end_layout
\begin_layout Plain Layout
*.param rbase=1k
\end_layout
\begin_layout Plain Layout
* some tests
\end_layout
\begin_layout Plain Layout
B1 1 0 V = hertz*v(33)
\end_layout
\begin_layout Plain Layout
B2 2 0 V = v(33)*hertz
\end_layout
\begin_layout Plain Layout
b3 3 0 V = 6.283e3/(hertz+6.283e3)*v(33)
\end_layout
\begin_layout Plain Layout
V1 33 0 DC 0 AC 1
\end_layout
\begin_layout Plain Layout
*** Translate R1 10 0 R='1k/sqrt(HERTZ)' to B source ***
\end_layout
\begin_layout Plain Layout
.Subckt nlres pos neg rb=rbase
\end_layout
\begin_layout Plain Layout
* Bx: calculate f(input voltage)
\end_layout
\begin_layout Plain Layout
Bx 1 0 v = -1 / {rb} / sqrt(HERTZ) * v(pos, neg)
\end_layout
\begin_layout Plain Layout
* Rx: linear resistance
\end_layout
\begin_layout Plain Layout
Rx 2 0 1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example: Non linear resistor (continued)
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
* Vx: Ammeter to measure current into the resistor
\end_layout
\begin_layout Plain Layout
Vx 2 1 DC 0Volts
\end_layout
\begin_layout Plain Layout
* Drive the current through Rx back into the circuit
\end_layout
\begin_layout Plain Layout
Fx pos neg Vx 1
\end_layout
\begin_layout Plain Layout
.ends
\end_layout
\begin_layout Plain Layout
Xres 33 10 nlres rb=1k
\end_layout
\begin_layout Plain Layout
*Rres 33 10 1k
\end_layout
\begin_layout Plain Layout
Vres 10 0 DC 0
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
define check(a,b) vecmax(abs(a - b))
\end_layout
\begin_layout Plain Layout
ac lin 10 100 1k
\end_layout
\begin_layout Plain Layout
* some checks
\end_layout
\begin_layout Plain Layout
print v(1) v(2) v(3)
\end_layout
\begin_layout Plain Layout
if check(v(1), frequency) < 1e-12
\end_layout
\begin_layout Plain Layout
echo "INFO: ok"
\end_layout
\begin_layout Plain Layout
end
\end_layout
\begin_layout Plain Layout
plot vres#branch
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Special-B-Source-Variables"
\end_inset
Special B-Source Variables time, temper, hertz
\end_layout
\begin_layout Standard
The special variables
\series bold
time
\series default
and
\series bold
temper
\series default
are available in a transient analysis, reflecting the actual simulation
time and circuit temperature.
\series bold
temper
\series default
returns the circuit temperature, given in degree C (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:.temp"
\end_inset
).
The variable
\series bold
hertz
\series default
is available in an AC analysis.
\series bold
time
\series default
is zero in the AC analysis,
\series bold
hertz
\series default
is zero during transient analysis.
Using the variable
\series bold
hertz
\series default
may cost some CPU time if you have a large circuit, because for each frequency
the operating point has to be determined before calculating the AC response.
\end_layout
\begin_layout Subsection
par(
\series medium
\shape italic
'expression'
\series default
\shape default
)
\end_layout
\begin_layout Standard
The B source syntax may also be used in output lines like
\family typewriter
.plot
\family default
as algebraic expressions for output (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:par('expression'):-Algebraic-expressions"
\end_inset
).
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:PiecewiseLinearFunction:-pwl"
\end_inset
Piecewise
\begin_inset space ~
\end_inset
Linear
\begin_inset space ~
\end_inset
Function: pwl
\end_layout
\begin_layout Standard
Both B source types may contain a piece-wise linear dependency of one network
variable:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\family typewriter
pwl_current
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Bdio 1 0 I = pwl(v(A), 0,0, 33,10m, 100,33m, 200,50m)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
v(A) is the independent variable x.
Each pair of values following describes the x,y functional relation: In
this example at node A voltage of 0V the current of 0A is generated - next
pair gives 10mA flowing from ground to node 1 at 33V on node A and so forth.
\end_layout
\begin_layout Standard
The same is possible for voltage sources:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\family typewriter
pwl_voltage
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Blimit b 0 V = pwl(v(1), -4,0, -2,2, 2,4, 4,5, 6,5)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Monotony of the independent variable in the pwl definition is checked -
non-monotonic x entries will stop the program execution.
v(1) may be replaced by a controlling current source.
v(1) may also be replaced by an expression, e.g.
\begin_inset Formula $-2\;i(V_{in})$
\end_inset
.
The value pairs may also be parameters, and have to be predefined by a
\family typewriter
.param
\family default
statement.
An example for the pwl function using all of these options is shown below.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example: pwl function in B source
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Demonstrates usage of the pwl function in an B source (ASRC)
\end_layout
\begin_layout Plain Layout
* Also emulates the TABLE function with limits
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.param x0=-4 y0=0
\end_layout
\begin_layout Plain Layout
.param x1=-2 y1=2
\end_layout
\begin_layout Plain Layout
.param x2=2 y2=-2
\end_layout
\begin_layout Plain Layout
.param x3=4 y3=1
\end_layout
\begin_layout Plain Layout
.param xx0=x0-1
\end_layout
\begin_layout Plain Layout
.param xx3=x3+1
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
Vin 1 0 DC=0V
\end_layout
\begin_layout Plain Layout
R 1 0 2
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* no limits outside of the tabulated x values
\end_layout
\begin_layout Plain Layout
* (continues linearily)
\end_layout
\begin_layout Plain Layout
Btest2 2 0 I = pwl(v(1),'x0','y0','x1','y1','x2','y2','x3','y3')
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* like TABLE function with limits:
\end_layout
\begin_layout Plain Layout
Btest3 3 0 I = (v(1) < 'x0') ? 'y0' : (v(1) < 'x3') ?
\end_layout
\begin_layout Plain Layout
+ pwl(v(1),'x0','y0','x1','y1','x2','y2','x3','y3') : 'y3'
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* more efficient and elegant TABLE function with limits
\end_layout
\begin_layout Plain Layout
*(voltage controlled):
\end_layout
\begin_layout Plain Layout
Btest4 4 0 I = pwl(v(1),
\end_layout
\begin_layout Plain Layout
+ 'xx0','y0', 'x0','y0',
\end_layout
\begin_layout Plain Layout
+ 'x1','y1',
\end_layout
\begin_layout Plain Layout
+ 'x2','y2',
\end_layout
\begin_layout Plain Layout
+ 'x3','y3', 'xx3','y3')
\end_layout
\begin_layout Plain Layout
*
\end_layout
\begin_layout Plain Layout
* more efficient and elegant TABLE function with limits
\end_layout
\begin_layout Plain Layout
* (controlled by current):
\end_layout
\begin_layout Plain Layout
Btest5 5 0 I = pwl(-2*i(Vin),
\end_layout
\begin_layout Plain Layout
+ 'xx0','y0', 'x0','y0',
\end_layout
\begin_layout Plain Layout
+ 'x1','y1',
\end_layout
\begin_layout Plain Layout
+ 'x2','y2',
\end_layout
\begin_layout Plain Layout
+ 'x3','y3', 'xx3','y3')
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
Rint2 2 0 1
\end_layout
\begin_layout Plain Layout
Rint3 3 0 1
\end_layout
\begin_layout Plain Layout
Rint4 4 0 1
\end_layout
\begin_layout Plain Layout
Rint5 5 0 1
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
dc Vin -6 6 0.2
\end_layout
\begin_layout Plain Layout
plot v(2) v(3) v(4)-0.5 v(5)+0.5
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:E-source-(non-linear"
\end_inset
Exxxx: non-linear voltage source
\end_layout
\begin_layout Subsection
VOL
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
EXXXXXXX n+ n- vol='expr'
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
E41 4 0 vol = 'V(3)*V(3)-Offs'
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\series bold
Expression
\series default
may be an equation or an expression containing node voltages or branch
currents (in the form of i(vm)) and any other terms as given for the B
source and described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:B-source-(ASRC)"
\end_inset
.
It may contain parameters (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.param-line"
\end_inset
) and the special variables
\family typewriter
time
\family default
,
\family typewriter
temper
\family default
,
\family typewriter
hertz
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Special-B-Source-Variables"
\end_inset
).
\family typewriter
'
\family default
or
\family typewriter
{ }
\family default
may be used to delimit the function.
\end_layout
\begin_layout Subsection
VALUE
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Optional syntax:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
EXXXXXXX n+ n- value={expr}
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
E41 4 0 value = {V(3)*V(3)-Offs}
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The '=' sign is optional.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:table"
\end_inset
TABLE
\end_layout
\begin_layout Standard
Data may be entered from the listings of a data table similar to the pwl
B-Source (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:PiecewiseLinearFunction:-pwl"
\end_inset
).
Data are grouped into x, y pairs.
\series bold
Expression
\series default
may be an equation or an expression containing node voltages or branch
currents (in the form of i(vm)) and any other terms as given for the B
source and described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:B-source-(ASRC)"
\end_inset
.
It may contain parameters (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.param-line"
\end_inset
).
\family typewriter
'
\family default
or
\family typewriter
{
\family default
\family typewriter
}
\family default
may be used to delimit the function.
\series bold
Expression
\series default
delivers the x-value, which is used to generate a corresponding y-value
according to the tabulated value pairs, using linear interpolation.
If the x-value is below x0 , y0 is returned, above x2 y2 is returned (limiting
function).
The value pairs have to be real numbers, parameters are
\emph on
not
\emph default
allowed.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Syntax for data entry from table:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Exxx n1 n2 TABLE {expression} = (x0, y0) (x1, y1) (x2, y2)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Example (simple comparator):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
ECMP 11 0 TABLE {V(10,9)} = (-5mV, 0V) (5mV, 5V)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
An '=' sign may follow the keyword
\family typewriter
TABLE
\family default
.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:POLY"
\end_inset
POLY
\end_layout
\begin_layout Standard
Polynomial sources are only available when the XSPICE option (see
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Compilation-notes"
\end_inset
) is enabled.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
EXXXX N+ N- POLY(ND) NC1+ NC1- (NC2+ NC2-...) P0 (P1...)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
ENONLIN 100 101 POLY(2) 3 0 4 0 0.0 13.6 0.2 0.005
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
POLY(ND) Specifies the number of dimensions of the polynomial.
The number of pairs of controlling nodes must be equal to the number of
dimensions.
\end_layout
\begin_layout Standard
(N+) and (N-) nodes are output nodes.
Positive current flows from the (+) node through the source to the (-)
node.
\end_layout
\begin_layout Standard
The
\family typewriter
\family default
and
\family typewriter
\family default
are in pairs and define a set of controlling voltages.
A particular node can appear more than once, and the output and controlling
nodes need not be different.
\end_layout
\begin_layout Standard
The example yields a voltage output controlled by two input voltages v(3,0)
and v(4,0).
Four polynomial coefficients are given.
The equivalent function to generate the output is:
\end_layout
\begin_layout LyX-Code
0 + 13.6 * v(3) + 0.2 * v(4) + 0.005 * v(3) * v(3)
\end_layout
\begin_layout Standard
Generally you will set the equation according to
\end_layout
\begin_layout LyX-Code
POLY(1) y = p0 + k1*X1 + p2*X1*X1 + p3*X1*X1*X1 + ...
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
POLY(2) y = p0 + p1*X1 + p2*X2 +
\end_layout
\begin_layout LyX-Code
+ p3*X1*X1 + p4*X2*X1 + p5*X2*X2 +
\end_layout
\begin_layout LyX-Code
+ p6*X1*X1*X1 + p7*X2*X1*X1 + p8*X2*X2*X1 +
\end_layout
\begin_layout LyX-Code
+ p9*X2*X2*X2 + ...
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
POLY(3) y = p0 + p1*X1 + p2*X2 + p3*X3 +
\end_layout
\begin_layout LyX-Code
+ p4*X1*X1 + p5*X2*X1 + p6*X3*X1 +
\end_layout
\begin_layout LyX-Code
+ p7*X2*X2 + p8*X2*X3 + p9*X3*X3 + ...
\end_layout
\begin_layout Standard
where X1 is the voltage difference of the first input node pair, X2 of the
second pair and so on.
Keeping track of all polynomial coefficient is rather tedious for large
polynomials.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:LAPLACE"
\end_inset
LAPLACE
\end_layout
\begin_layout Standard
Currently ngspice does not offer a direct E-Source element with the LAPLACE
option.
There is however a XSPICE code model equivalent called
\series bold
s_xfer
\series default
(see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:S-Domain-Transfer-Function"
\end_inset
), which you may invoke manually.
The XSPICE option has to be enabled (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Ngspice-Installation-under"
\end_inset
).
AC (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.AC:-Small-Signal-AC"
\end_inset
) and transient analysis (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.TRAN:-Transient-Analysis"
\end_inset
) is supported.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
The following E-Source:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
ELOPASS 4 0 LAPLACE {V(1)}
\end_layout
\begin_layout Plain Layout
+ {5 * (s/100 + 1) / (s^2/42000 + s/60 + 1)}
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
may be replaced by:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
AELOPASS 1 int_4 filter1
\end_layout
\begin_layout Plain Layout
.model filter1 s_xfer(gain=5
\end_layout
\begin_layout Plain Layout
+ num_coeff=[{1/100} 1]
\end_layout
\begin_layout Plain Layout
+ den_coeff=[{1/42000} {1/60} 1]
\end_layout
\begin_layout Plain Layout
+ int_ic=[0 0])
\end_layout
\begin_layout Plain Layout
ELOPASS 4 0 int_4 0 1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
where you have the voltage of node 1 as input, an intermediate output node
int_4 and an E-source as buffer to keep the name `ELOPASS' available if
further processing is required.
\end_layout
\begin_layout Standard
If the controlling expression is more complex than just a voltage node,
you may add a B-Source (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:B-source-(ASRC)"
\end_inset
) for evaluating the expression before entering the A-device.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
E-Source with complex controlling expression:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
ELOPASS 4 0 LAPLACE {V(1)*v(2)} {10 / (s/6800 + 1)}
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
may be replaced by:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
BELOPASS int_1 0 V=V(1)*v(2)
\end_layout
\begin_layout Plain Layout
AELOPASS int_1 int_4 filter1
\end_layout
\begin_layout Plain Layout
.model filter1 s_xfer(gain=10
\end_layout
\begin_layout Plain Layout
+ num_coeff=[1]
\end_layout
\begin_layout Plain Layout
+ den_coeff=[{1/6800} 1]
\end_layout
\begin_layout Plain Layout
+ int_ic=[0])
\end_layout
\begin_layout Plain Layout
ELOPASS 4 0 int_4 0 1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:G-source-(non-linear"
\end_inset
Gxxxx: non-linear current source
\end_layout
\begin_layout Subsection
CUR
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
GXXXXXXX n+ n- cur='expr'
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
G51 55 225 cur = 'V(3)*V(3)-Offs'
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\series bold
Expression
\series default
may be an equation or an expression containing node voltages or branch
currents (in the form of i(vm)) and any other terms as given for the B
source and described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:B-source-(ASRC)"
\end_inset
.
It may contain parameters (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.param-line"
\end_inset
) and special variables (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Special-B-Source-Variables"
\end_inset
).
\family typewriter
m
\family default
is an optional multiplier to the output current.
\family typewriter
val
\family default
may be a numerical value or an expression according to
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Syntax-of-expressions"
\end_inset
containing only references to other parameters (no node voltages or branch
currents!), because it is evaluated before the simulation commences.
\end_layout
\begin_layout Subsection
VALUE
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Optional syntax:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
GXXXXXXX n+ n- value='expr'
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
G51 55 225 value = 'V(3)*V(3)-Offs'
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The '=' sign is optional.
\end_layout
\begin_layout Subsection
TABLE
\end_layout
\begin_layout Standard
A data entry by a tabulated listing is available with syntax similar to
the E-Source (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:table"
\end_inset
).
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Syntax for data entry from table:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Gxxx n1 n2 TABLE {expression} =
\end_layout
\begin_layout Plain Layout
+ (x0, y0) (x1, y1) (x2, y2)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Example (simple comparator with current output and voltage control):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
GCMP 0 11 TABLE {V(10,9)} = (-5MV, 0V) (5MV, 5V)
\end_layout
\begin_layout Plain Layout
R 11 0 1k
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
m
\family default
is an optional multiplier to the output current.
\family typewriter
val
\family default
may be a numerical value or an expression according to
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Syntax-of-expressions"
\end_inset
containing only references to other parameters (no node voltages or branch
currents!), because it is evaluated before the simulation commences.
An '=' sign may follow the keyword
\family typewriter
TABLE
\family default
.
\end_layout
\begin_layout Subsection
POLY
\end_layout
\begin_layout Standard
see E-Source at Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:POLY"
\end_inset
.
\end_layout
\begin_layout Subsection
LAPLACE
\end_layout
\begin_layout Standard
See E-Source, Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:LAPLACE"
\end_inset
, for an equivalent code model replacement.
\end_layout
\begin_layout Subsection
Example
\end_layout
\begin_layout Standard
An example file is given below.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example input file:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
VCCS, VCVS, non-linear dependency
\end_layout
\begin_layout Plain Layout
.param Vi=1
\end_layout
\begin_layout Plain Layout
.param Offs='0.01*Vi'
\end_layout
\begin_layout Plain Layout
* VCCS depending on V(3)
\end_layout
\begin_layout Plain Layout
B21 int1 0 V = V(3)*V(3)
\end_layout
\begin_layout Plain Layout
G1 21 22 int1 0 1
\end_layout
\begin_layout Plain Layout
* measure current through VCCS
\end_layout
\begin_layout Plain Layout
vm 22 0 dc 0
\end_layout
\begin_layout Plain Layout
R21 21 0 1
\end_layout
\begin_layout Plain Layout
* new VCCS depending on V(3)
\end_layout
\begin_layout Plain Layout
G51 55 225 cur = 'V(3)*V(3)-Offs'
\end_layout
\begin_layout Plain Layout
* measure current through VCCS
\end_layout
\begin_layout Plain Layout
vm5 225 0 dc 0
\end_layout
\begin_layout Plain Layout
R51 55 0 1
\end_layout
\begin_layout Plain Layout
* VCVS depending on V(3)
\end_layout
\begin_layout Plain Layout
B31 int2 0 V = V(3)*V(3)
\end_layout
\begin_layout Plain Layout
E1 1 0 int2 0 1
\end_layout
\begin_layout Plain Layout
R1 1 0 1
\end_layout
\begin_layout Plain Layout
* new VCVS depending on V(3)
\end_layout
\begin_layout Plain Layout
E41 4 0 vol = 'V(3)*V(3)-Offs'
\end_layout
\begin_layout Plain Layout
R4 4 0 1
\end_layout
\begin_layout Plain Layout
* control voltage
\end_layout
\begin_layout Plain Layout
V1 3 0 PWL(0 0 100u {Vi})
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
unset askquit
\end_layout
\begin_layout Plain Layout
tran 10n 100u uic
\end_layout
\begin_layout Plain Layout
plot i(E1) i(E41)
\end_layout
\begin_layout Plain Layout
plot i(vm) i(vm5)
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section
Debugging a behavioral source
\end_layout
\begin_layout Standard
The B, E, G, sources and the behavioral R, C, L elements are powerful tools
to set up user defined models.
Unfortunately debugging these models is not very comfortable.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example input file with bug (log(-2)):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
B source debugging
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
V1 1 0 1
\end_layout
\begin_layout Plain Layout
V2 2 0 -2
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
E41 4 0 vol = 'V(1)*log(V(2))'
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
tran 1 1
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The input file given above results in an error message:
\end_layout
\begin_layout Standard
\family typewriter
Error: -2 out of range for log
\end_layout
\begin_layout Standard
In this trivial example, the reason and location for the bug is obvious.
However, if you have several equations using behavioral sources, and several
occurrences of the log function, then debugging is nearly impossible.
\end_layout
\begin_layout Standard
However, if the variable
\series bold
ngdebug
\series default
(see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Variables"
\end_inset
) is set (e.g.
in file
\family sans
.spiceinit
\family default
), a more distinctive error message is issued that (after some closer investigat
ion) will reveal the location and value of the buggy parameter.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Detailed error message for input file with bug (log(-2)):
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Error: -2 out of range for log
\end_layout
\begin_layout Plain Layout
calling PTeval, tree =
\end_layout
\begin_layout Plain Layout
(v0) * (log (v1))
\end_layout
\begin_layout Plain Layout
d / d v0 : log (v1)
\end_layout
\begin_layout Plain Layout
d / d v1 : (v0) * ((0.434294) / (v1))
\end_layout
\begin_layout Plain Layout
values: var0 = 1
\end_layout
\begin_layout Plain Layout
var1 = -2
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
If variable
\family typewriter
strict_errorhandling
\family default
(see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Variables"
\end_inset
) is set, ngspice exits after this message.
If not, gmin and source stepping may be started, typically without success.
\end_layout
\begin_layout Chapter
Transmission Lines
\end_layout
\begin_layout Standard
Ngspice implements both the original SPICE3f5 transmission lines models
and the one introduced with KSPICE.
The latter provide an improved transient analysis of lossy transmission
lines.
Unlike SPICE models that use the state-based approach to simulate lossy
transmission lines, KSPICE simulates lossy transmission lines and coupled
multiconductor line systems using the recursive convolution method.
The impulse response of an arbitrary transfer function can be determined
by deriving a recursive convolution from the Pade approximations of the
function.
We use this approach for simulating each transmission line's characteristics
and each multiconductor line's modal functions.
This method of lossy transmission line simulation has been proved to give
a speedup of one to two orders of magnitude over SPICE3f5.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Lossless-Transmission-Lines"
\end_inset
Lossless Transmission Lines
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
TXXXXXXX N1 N2 N3 N4 Z0=VALUE
\end_layout
\begin_layout Plain Layout
+ >
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
T1 1 0 2 0 Z0=50 TD=10NS
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n1
\family default
\series default
and
\family typewriter
\series bold
n2
\family default
\series default
are the nodes at port 1;
\family typewriter
\series bold
n3
\family default
\series default
and
\family typewriter
\series bold
n4
\family default
\series default
are the nodes at port 2.
\family typewriter
\series bold
z0
\family default
\series default
is the characteristic impedance.
The length of the line may be expressed in either of two forms.
The transmission delay,
\family typewriter
\series bold
td
\family default
\series default
, may be specified directly (as td=10ns, for example).
Alternatively, a frequency
\family typewriter
\series bold
f
\family default
\series default
may be given, together with
\family typewriter
\series bold
nl
\family default
\series default
, the normalized electrical length of the transmission line with respect
to the wavelength in the line at the frequency `f'.
If a frequency is specified but
\family typewriter
\series bold
nl
\family default
\series default
is omitted, 0.25 is assumed (that is, the frequency is assumed to be the
quarter-wave frequency).
Note that although both forms for expressing the line length are indicated
as optional, one of the two must be specified.
\end_layout
\begin_layout Standard
Note that this element models only one propagating mode.
If all four nodes are distinct in the actual circuit, then two modes may
be excited.
To simulate such a situation, two transmission-line elements are required.
(see the example in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Transmission-Line-Inverter"
\end_inset
for further clarification.) The (optional) initial condition specification
consists of the voltage and current at each of the transmission line ports.
Note that the initial conditions (if any) apply
\emph on
only
\emph default
if the
\family typewriter
\series bold
UIC
\family default
\series default
option is specified on the
\family typewriter
.TRAN
\family default
control line.
\end_layout
\begin_layout Standard
Note that a lossy transmission line (see below) with zero loss may be more
accurate than the lossless transmission line due to implementation details.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Lossy-Transmission-Lines"
\end_inset
Lossy Transmission Lines
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
OXXXXXXX n1 n2 n3 n4 mname
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
O23 1 0 2 0 LOSSYMOD
\end_layout
\begin_layout Plain Layout
OCONNECT 10 5 20 5 INTERCONNECT
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
This is a two-port convolution model for single conductor lossy transmission
lines.
\family typewriter
\series bold
n1
\family default
\series default
and
\family typewriter
\series bold
n2
\family default
\series default
are the nodes at port 1;
\family typewriter
\series bold
n3
\family default
\series default
and
\family typewriter
\series bold
n4
\family default
\series default
are the nodes at port 2.
Note that a lossy transmission line with zero loss may be more accurate
than the lossless transmission line due to implementation details.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Lossy-Transmission-Line"
\end_inset
Lossy Transmission Line Model (LTRA)
\end_layout
\begin_layout Standard
The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA
model henceforth) models a uniform constant-parameter distributed transmission
line.
The RC and LC cases may also be modeled using the URC and TRA models; however,
the newer LTRA model is usually faster and more accurate than the others.
The operation of the LTRA model is based on the convolution of the transmission
line's impulse responses with its inputs (see [8]).
The LTRA model takes a number of parameters, some of which must be given
and some of which are optional.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units/Type
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
R
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
resistance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
L
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
inductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{H}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
9.13e-9
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
G
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
conductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{mhos}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
C
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
capacitance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.65e-12
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LEN
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
length of line
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $unit$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
no default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
REL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
breakpoint control
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
arbitrary unit
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ABS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
breakpoint control
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NOSTEPLIMIT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
don't limit time-step to less than line delay
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NO CONTROL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
don't do complex time-step control
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LININTERP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
use linear interpolation
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MIXEDINTERP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
use linear when quadratic seems bad
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
COMPACTREL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
special reltol for history compaction
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RELTOL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
COMPACTABS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
special abstol for history compaction
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ABSTOL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-9
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRUNCNR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
use Newton-Raphson method for time-step control
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRUNCDONTCUT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
don't limit time-step to keep impulse-response errors low
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
not set
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
set
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
The following types of lines have been implemented so far:
\end_layout
\begin_layout Itemize
RLC (uniform transmission line with series loss only),
\end_layout
\begin_layout Itemize
RC (uniform RC line),
\end_layout
\begin_layout Itemize
LC (lossless transmission line),
\end_layout
\begin_layout Itemize
RG (distributed series resistance and parallel conductance only).
\end_layout
\begin_layout Standard
Any other combination will yield erroneous results and should not be tried.
The length
\family typewriter
\series bold
LEN
\family default
\series default
of the line must be specified.
\family typewriter
\series bold
NOSTEPLIMIT
\family default
\series default
is a flag that will remove the default restriction of limiting time-steps
to less than the line delay in the RLC case.
\family typewriter
\series bold
NO CONTROL
\family default
\series default
is a flag that prevents the default limiting of the time-step based on
convolution error criteria in the RLC and RC cases.
This speeds up simulation but may in some cases reduce the accuracy of
results.
\family typewriter
\series bold
LININTERP
\family default
\series default
is a flag that, when specified, will use linear interpolation instead of
the default quadratic interpolation for calculating delayed signals.
\family typewriter
\series bold
MIXEDINTERP
\family default
\series default
is a flag that, when specified, uses a metric for judging whether quadratic
interpolation is not applicable and if so uses linear interpolation; otherwise
it uses the default quadratic interpolation.
\family typewriter
\series bold
TRUNCDONTCUT
\family default
\series default
is a flag that removes the default cutting of the time-step to limit errors
in the actual calculation of impulse-response related quantities.
\family typewriter
\series bold
COMPACTREL
\family default
\series default
and
\family typewriter
\series bold
COMPACTABS
\family default
\series default
are quantities that control the compaction of the past history of values
stored for convolution.
Larger values of these lower accuracy but usually increase simulation speed.
These are to be used with the
\family typewriter
\series bold
TRYTOCOMPACT
\family default
\series default
option, described in the .
\family typewriter
\series bold
OPTIONS
\family default
\series default
section.
\family typewriter
\series bold
TRUNCNR
\family default
\series default
is a flag that turns on the use of Newton-Raphson iterations to determine
an appropriate time-step in the time-step control routines.
The default is a trial and error procedure by cutting the previous time-step
in half.
\family typewriter
\series bold
REL
\family default
\series default
and
\family typewriter
\series bold
ABS
\family default
\series default
are quantities that control the setting of breakpoints.
\end_layout
\begin_layout Standard
The option most worth experimenting with for increasing the speed of simulation
is
\family typewriter
\series bold
REL
\family default
\series default
.
The default value of 1 is usually safe from the point of view of accuracy
but occasionally increases computation time.
A value greater than 2 eliminates all breakpoints and may be worth trying
depending on the nature of the rest of the circuit, keeping in mind that
it might not be safe from the viewpoint of accuracy.
\end_layout
\begin_layout Standard
Breakpoints may usually be entirely eliminated if it is expected the circuit
will not display sharp discontinuities.
Values between 0 and 1 are usually not required but may be used for setting
many breakpoints.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
COMPACTREL
\family default
\series default
may also be experimented with when the option
\family typewriter
\series bold
TRYTOCOMPACT
\family default
\series default
is specified in a
\family typewriter
.OPTIONS
\family default
card.
The legal range is between 0 and 1.
Larger values usually decrease the accuracy of the simulation but in some
cases improve speed.
If
\family typewriter
\series bold
TRYTOCOMPACT
\family default
\series default
is not specified on a
\family typewriter
.OPTIONS
\family default
card, history compaction is not attempted and accuracy is high.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
NO CONTROL
\family default
\series default
,
\family typewriter
\series bold
TRUNCDONTCUT
\family default
\series default
and
\family typewriter
\series bold
NOSTEPLIMIT
\family default
\series default
also tend to increase speed at the expense of accuracy.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Uniform-Distributed-RC"
\end_inset
Uniform Distributed RC Lines
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
UXXXXXXX n1 n2 n3 mname l=len
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
U1 1 2 0 URCMOD L=50U
\end_layout
\begin_layout Plain Layout
URC2 1 12 2 UMODL l=1MIL N=6
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n1
\family default
\series default
and
\family typewriter
\series bold
n2
\family default
\series default
are the two element nodes the RC line connects, while
\family typewriter
\series bold
n3
\family default
\series default
is the node the capacitances are connected to.
\family typewriter
\series bold
mname
\family default
\series default
is the model name,
\family typewriter
\series bold
len
\family default
\series default
is the length of the RC line in meters.
\family typewriter
\series bold
lumps
\family default
\series default
, if specified, is the number of lumped segments to use in modeling the
RC line (see the model description for the action taken if this parameter
is omitted).
\end_layout
\begin_layout Subsection
Uniform Distributed RC Model (URC)
\end_layout
\begin_layout Standard
The URC model is derived from a model proposed by L.
Gertzberg in 1974.
The model is accomplished by a subcircuit type expansion of the URC line
into a network of lumped RC segments with internally generated nodes.
The RC segments are in a geometric progression, increasing toward the middle
of the URC line, with
\begin_inset Formula $K$
\end_inset
as a proportionality constant.
The number of lumped segments used, if not specified for the URC line device,
is determined by the following formula:
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
N=\frac{\log\left|F_{{\rm max}}\frac{R}{L}\frac{C}{L}2\pi L^{2}\left|\frac{(K-1)}{K}\right|^{2}\right|}{\log K}
\end{equation}
\end_inset
The URC line is made up strictly of resistor and capacitor segments unless
the
\family typewriter
\series bold
ISPERL
\family default
\series default
parameter is given a nonzero value, in which case the capacitors are replaced
with reverse biased diodes with a zero-bias junction capacitance equivalent
to the capacitance replaced, and with a saturation current of
\family typewriter
\series bold
ISPERL
\family default
\series default
amps per meter of transmission line and an optional series resistance equivalen
t to
\family typewriter
\series bold
RSPERL
\family default
\series default
ohms per meter.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
K
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Propagation Constant
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FMAX
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Maximum Frequency of interest
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $Hz$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0 G
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
6.5 Meg
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RPERL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Resistance per unit length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1000
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CPERL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Capacitance per unit length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10e-15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1 p
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ISPERL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Saturation Current per unit length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{A}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RSPERL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Diode Resistance per unit length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Section
KSPICE Lossy Transmission Lines
\end_layout
\begin_layout Standard
Unlike SPICE3, which uses the state-based approach to simulate lossy transmissio
n lines, KSPICE simulates lossy transmission lines and coupled multiconductor
line systems using the recursive convolution method.
The impulse response of an arbitrary transfer function can be determined
by deriving a recursive convolution from the Pade approximations of the
function.
NGSPICE is using this approach for simulating each transmission line's
characteristics and each multiconductor line's modal functions.
This method of lossy transmission line simulation has shown to give a speedup
of one to two orders of magnitude over SPICE3E.
Please note that the following two models will support only
\series bold
transient simulation
\series default
, no ac.
\end_layout
\begin_layout Standard
Additional Documentation Available:
\end_layout
\begin_layout Itemize
S.
Lin and E.
S.
Kuh, `Pade Approximation Applied to Transient Simulation of Lossy Coupled
Transmission Lines,' Proc.
IEEE Multi-Chip Module Conference, 1992, pp.
52-55.
\end_layout
\begin_layout Itemize
S.
Lin, M.
Marek-Sadowska, and E.
S.
Kuh, `SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS
VLSI Circuits,' European Design Automation Conf., February 1991, pp.
142-148.
\end_layout
\begin_layout Itemize
S.
Lin and E.
S.
Kuh, `Transient Simulation of Lossy Interconnect,' Proc.
Design Automation Conference, Anaheim, CA, June 1992, pp.
81-86.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Single-Lossy-Transmission"
\end_inset
Single Lossy Transmission Line (TXL)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
YXXXXXXX N1 0 N2 0 mname
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Y1 1 0 2 0 ymod LEN=2
\end_layout
\begin_layout Plain Layout
.MODEL ymod txl R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
n1
\family default
\series default
and
\family typewriter
\series bold
n2
\family default
\series default
are the nodes of the two ports.
The optional instance parameter
\family typewriter
\series bold
len
\family default
\series default
is the length of the line and may be expressed in multiples of [
\begin_inset Formula $unit$
\end_inset
].
Typically
\begin_inset Formula $unit$
\end_inset
is given in meters.
\family typewriter
\series bold
len
\family default
\series default
will override the model parameter
\family typewriter
\series bold
length
\family default
\series default
for the specific instance only.
\end_layout
\begin_layout Standard
The TXL model takes a number of parameters:
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units/Type
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
R
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
resistance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
L
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
inductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{H}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
9.13e-9
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
G
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
conductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{mhos}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
C
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
capacitance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.65e-12
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LENGTH
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
length of line
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $unit$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
no default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
Model parameter
\family typewriter
\series bold
length
\family default
\series default
must be specified as a multiple of
\begin_inset Formula $unit$
\end_inset
.
Typically
\begin_inset Formula $unit$
\end_inset
is given in [m].
For transient simulation only.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Coupled-Multiconductor-Line"
\end_inset
Coupled Multiconductor Line (CPL)
\end_layout
\begin_layout Standard
The CPL multiconductor line model is in theory similar to the RLGC model,
but without frequency dependent loss (neither skin effect nor frequency-depende
nt dielectric loss).
Up to 8 coupled lines are supported in NGSPICE.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
PXXXXXXX NI1 NI2...NIX GND1 NO1 NO2...NOX GND2 mname
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
P1 in1 in2 0 b1 b2 0 PLINE
\end_layout
\begin_layout Plain Layout
.model PLINE CPL length={Len}
\end_layout
\begin_layout Plain Layout
+R=1 0 1
\end_layout
\begin_layout Plain Layout
+L={L11} {L12} {L22}
\end_layout
\begin_layout Plain Layout
+G=0 0 0
\end_layout
\begin_layout Plain Layout
+C={C11} {C12} {C22}
\end_layout
\begin_layout Plain Layout
.param Len=1 Rs=0
\end_layout
\begin_layout Plain Layout
+ C11=9.143579E-11 C12=-9.78265E-12 C22=9.143578E-11
\end_layout
\begin_layout Plain Layout
+ L11=3.83572E-7 L12=8.26253E-8 L22=3.83572E-7
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
ni1
\family default
\series default
...
\family typewriter
\series bold
nix
\family default
\series default
are the nodes at port 1 with gnd1;
\family typewriter
\series bold
no1
\family default
\series default
...
\family typewriter
\series bold
nox
\family default
\series default
are the nodes at port 2 with gnd2.
The optional instance parameter
\family typewriter
\series bold
len
\family default
\series default
is the length of the line and may be expressed in multiples of [
\begin_inset Formula $unit$
\end_inset
].
Typically
\begin_inset Formula $unit$
\end_inset
is given in meters.
\family typewriter
\series bold
len
\family default
\series default
will override the model parameter
\family typewriter
\series bold
length
\family default
\series default
for the specific instance only.
\end_layout
\begin_layout Standard
The CPL model takes a number of parameters:
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units/Type
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
R
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
resistance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
L
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
inductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{H}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
9.13e-9
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
G
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
conductance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{mhos}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
C
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
capacitance/length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{unit}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.65e-12
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LENGTH
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
length of line
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $unit$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
no default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
All RLGC parameters are given in Maxwell matrix form.
For the R and G matrices the diagonal elements must be specified, for L
and C matrices the lower or upper triangular elements must specified.
The parameter LENGTH is a scalar and is mandatory.
For transient simulation only.
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "cha:DIODEs"
\end_inset
Diodes
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Junction-Diodes"
\end_inset
Junction Diodes
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
DXXXXXXX n+ n- mname
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
DBRIDGE 2 10 DIODE1
\end_layout
\begin_layout Plain Layout
DCLMP 3 7 DMOD AREA=3.0 IC=0.2
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The pn junction (diode) implemented in ngspice expands the one found in
SPICE3f5.
Perimeter effects and high injection level have been introduced into the
original model and temperature dependence of some parameters has been added.
\family typewriter
\series bold
n+
\family default
\series default
and
\family typewriter
\series bold
n-
\family default
\series default
are the positive and negative nodes, respectively.
\family typewriter
\series bold
mname
\family default
\series default
is the model name.
Instance parameters may follow, dedicated to only the diode described on
the respective line.
\family typewriter
\series bold
area
\family default
\series default
is the area scale factor, which may scale the saturation current given
by the model parameters (and others, see table below).
\family typewriter
\series bold
pj
\family default
\series default
is the perimeter scale factor, scaling the sidewall saturation current
and its associated capacitance.
\family typewriter
\series bold
m
\family default
\series default
is a multiplier of area and perimeter, and
\family typewriter
\series bold
off
\family default
\series default
indicates an (optional) starting condition on the device for dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition specification using
\family typewriter
\series bold
ic
\family default
\series default
is intended for use with the
\family typewriter
\series bold
uic
\family default
\series default
option on the
\family typewriter
.tran
\family default
control line, when a transient analysis is desired starting from other
than the quiescent operating point.
You should supply the initial voltage across the diode there.
The (optional)
\family typewriter
\series bold
temp
\family default
\series default
value is the temperature at which this device is to operate, and overrides
the temperature specification on the
\family typewriter
.option
\family default
control line.
The temperature of each instance can be specified as an offset to the circuit
temperature with the
\family typewriter
\series bold
dtemp
\family default
\series default
option.
\end_layout
\begin_layout Section
Diode Model (D)
\end_layout
\begin_layout Standard
The dc characteristics of the diode are determined by the parameters
\family typewriter
\series bold
is
\family default
\series default
and
\family typewriter
\series bold
n
\family default
\series default
.
An ohmic resistance,
\family typewriter
\series bold
rs
\family default
\series default
, is included.
Charge storage effects are modeled by a transit time,
\family typewriter
\series bold
tt
\family default
\series default
, and a nonlinear depletion layer capacitance that is determined by the
parameters
\family typewriter
\series bold
cjo
\family default
\series default
,
\family typewriter
\series bold
vj
\family default
\series default
, and
\family typewriter
\series bold
m
\family default
\series default
.
The temperature dependence of the saturation current is defined by the
parameters
\family typewriter
\series bold
eg
\family default
\series default
, the energy, and
\family typewriter
\series bold
xti
\family default
\series default
, the saturation current temperature exponent.
The nominal temperature where these parameters were measured is
\family typewriter
\series bold
tnom
\family default
\series default
, which defaults to the circuit-wide value specified on the
\family typewriter
.options
\family default
control line.
Reverse breakdown is modeled by an exponential increase in the reverse
diode current and is determined by the parameters
\family typewriter
\series bold
bv
\family default
\series default
and
\family typewriter
\series bold
ibv
\family default
\series default
(both of which are positive numbers).
\end_layout
\begin_layout Subsubsection*
Junction DC parameters
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Scale factor
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BV
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Reverse breakdown voltage
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
40
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IBV
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Current at breakdown voltage
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IK (IKF)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Forward knee current
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IKR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Reverse knee current
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IS (JS)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Saturation current
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-14
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-16
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
JSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sidewall saturation current
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-14
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
perimeter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
N
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Emission coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Ohmic resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{area}$
\end_inset
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Subsubsection*
Junction capacitance parameters
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Scale factor
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJO (CJ0)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias junction bottom-wall capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJP (CJSW)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias junction sidewall capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
.1pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
perimeter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Coefficient for forward-bias depletion bottom-wall capacitance formula
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FCS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Coefficient for forward-bias depletion sidewall capacitance formula
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
M (MJ)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Area junction grading coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Periphery junction grading coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.33
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VJ (PB)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Junction potential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Periphery junction potential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Transit-time
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
sec
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1ns
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Subsubsection*
Temperature effects
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
EG
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Activation energy
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $eV$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.11
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\begin{array}{cc}
1.11 & \mathrm{Si}\\
0.69 & \mathrm{Sbd}\\
0.67 & \mathrm{Ge}
\end{array}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TM1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order tempco for MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TM2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order tempco for MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNOM (TREF)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter measurement temperature
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $°C$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
27
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
50
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRS1 (TRS)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order tempco for RS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRS2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order tempco for RS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TM1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order tempco for MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TM2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order tempco for MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TTT1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order tempco for TT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TTT2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order tempco for TT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XTI
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Saturation current temperature exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\begin{array}{cc}
3.0 & \mathrm{pn}\\
2.0 & \mathrm{Sbd}
\end{array}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TLEV
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Diode temperature equation selector
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TLEVC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Diode capac.
temperature equation selector
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CTA (CTC)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Area junct.
cap.
temperature coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CTP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Perimeter junct.
cap.
temperature coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TCV
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Breakdown voltage temperature coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Subsubsection*
Noise modeling
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
\shape italic
Scale factor
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
KF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
AF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
Diode models may be described in the input file (or an file included by
.inc) according to the following example:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.model mname type(pname1=pval1 pname2=pval2 ...
)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.model DMOD D (bf=50 is=1e-13 vbf=50)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section
Diode Equations
\end_layout
\begin_layout Standard
The junction diode is the basic semiconductor device and the simplest one
in ngspice, but its model is quite complex, even when not all the physical
phenomena affecting a pn junction are handled.
The diode is modeled in three different regions:
\end_layout
\begin_layout Itemize
\emph on
Forward bias
\emph default
: the anode is more positive than the cathode, the diode is `on' and can
conduct large currents.
To avoid convergence problems and unrealistic high current, it is prudent
to specify a series resistance to limit current with the
\family typewriter
\series bold
rs
\family default
\series default
model parameter.
\end_layout
\begin_layout Itemize
\emph on
Reverse bias
\emph default
: the cathode is more positive than the anode and the diode is `off'.
A reverse bias diode conducts a small leakage current.
\end_layout
\begin_layout Itemize
\emph on
Breakdown
\emph default
: the breakdown region is modeled only if the
\family typewriter
\series bold
bv
\family default
\series default
model parameter is given.
When a diode enters breakdown the current increases exponentially (remember
to limit it);
\family typewriter
\series bold
bv
\family default
\series default
is a positive value.
\end_layout
\begin_layout Subsubsection*
Parameters Scaling
\end_layout
\begin_layout Standard
Model parameters are scaled using the unit-less parameters
\family typewriter
\series bold
area
\family default
\series default
and
\family typewriter
\series bold
pj
\family default
\series default
and the multiplier
\family typewriter
\series bold
m
\family default
\series default
as depicted below:
\end_layout
\begin_layout Standard
\begin_inset Formula $AREA_{eff}={\rm AREA}\:m$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $PJ_{eff}={\rm PJ}\:m$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $IS_{eff}={\rm IS}\:AREA_{eff}+{\rm JSW}\:PJ_{eff}$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $IBV_{eff}={\rm IBV}\:AREA_{eff}$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $IK_{eff}={\rm IK}\:AREA_{eff}$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $IKR_{eff}={\rm IKR}\:AREA_{eff}$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $CJ_{eff}={\rm CJ0}\:AREA_{eff}$
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula $CJP_{eff}={\rm CJP}\:PJ_{eff}$
\end_inset
\end_layout
\begin_layout Subsubsection*
Diode DC, Transient and AC model equations
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
I_{D}=\begin{cases}
IS_{eff}(e^{\frac{qV_{D}}{NkT}}-1)+V_{D}\cdot GMIN, & \mathrm{if}\;V_{D}\geq-3\frac{NkT}{q}\\
-IS_{eff}[1+(\frac{3NkT}{qV_{D}e})^{3}]+V_{D}\cdot GMIN, & \mathrm{if}\;-BV_{eff} mname
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Q23 10 24 13 QMOD IC=0.6, 5.0
\end_layout
\begin_layout Plain Layout
Q50A 11 26 4 20 MOD1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
nc
\family default
\series default
,
\family typewriter
\series bold
nb
\family default
\series default
, and
\family typewriter
\series bold
ne
\family default
\series default
are the collector, base, and emitter nodes, respectively.
\family typewriter
\series bold
ns
\family default
\series default
is the (optional) substrate node.
When unspecified, ground is used.
\family typewriter
\series bold
mname
\family default
\series default
is the model name,
\family typewriter
\series bold
area
\family default
\series default
,
\family typewriter
\series bold
areab
\family default
\series default
,
\family typewriter
\series bold
areac
\family default
\series default
are the area factors (emitter, base and collector respectively), and
\family typewriter
\series bold
off
\family default
\series default
indicates an (optional) initial condition on the device for the dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
\end_layout
\begin_layout Standard
The (optional) initial condition specification using
\family typewriter
\series bold
ic=vbe,vce
\family default
\series default
is intended for use with the
\family typewriter
\series bold
uic
\family default
\series default
option on a
\family typewriter
.tran
\family default
control line, when a transient analysis is desired to start from other
than the quiescent operating point.
See the
\family typewriter
.ic
\family default
control line description for a better way to set transient initial conditions.
The (optional)
\family typewriter
\series bold
temp
\family default
\series default
value is the temperature where this device is to operate, and overrides
the temperature specification on the
\family typewriter
.option
\family default
control line.
Using the
\family typewriter
\series bold
dtemp
\family default
\series default
option one can specify the instance's temperature relative to the circuit
temperature.
\end_layout
\begin_layout Section
BJT Models (NPN/PNP)
\end_layout
\begin_layout Standard
Ngspice provides three BJT device models, which are selected by the
\family typewriter
.model
\family default
card.
\end_layout
\begin_layout Standard
\family typewriter
.model QMOD1 BJT level=2
\end_layout
\begin_layout Standard
This is the minimal version, further optional parameters listed in the table
below may replace the ngspice default parameters.
The
\family typewriter
\series bold
level
\family default
\series default
keyword specifies the model to be used:
\end_layout
\begin_layout Itemize
level=1: This is the original SPICE BJT model, and it is the default model
if the
\family typewriter
\series bold
level
\family default
\series default
keyword is not specified on the
\family typewriter
.model
\family default
line.
\end_layout
\begin_layout Itemize
level=2: This is a modified version of the original SPICE BJT that models
both vertical and lateral devices and includes temperature corrections
of collector, emitter and base resistors.
\end_layout
\begin_layout Itemize
level=4: Advanced VBIC model (see
\begin_inset CommandInset href
LatexCommand href
target "http://www.designers-guide.org/VBIC/"
\end_inset
for details)
\end_layout
\begin_layout Standard
The bipolar junction transistor model in ngspice is an adaptation of the
integral charge control model of Gummel and Poon.
This modified Gummel-Poon model extends the original model to include several
effects at high bias levels.
The model automatically simplifies to the simpler Ebers-Moll model when
certain parameters are not specified.
The parameter names used in the modified Gummel-Poon model have been chosen
to be more easily understood by the user, and to reflect better both physical
and circuit design thinking.
\end_layout
\begin_layout Standard
The dc model is defined by the parameters
\family typewriter
\series bold
is
\family default
\series default
,
\family typewriter
\series bold
bf
\family default
\series default
,
\family typewriter
\series bold
nf
\family default
\series default
,
\family typewriter
\series bold
ise
\family default
\series default
,
\family typewriter
\series bold
ikf
\family default
\series default
, and
\family typewriter
\series bold
ne,
\family default
\series default
which determine the forward current gain characteristics,
\family typewriter
\series bold
is
\family default
\series default
,
\family typewriter
\series bold
br
\family default
\series default
,
\family typewriter
\series bold
nr
\family default
\series default
,
\family typewriter
\series bold
isc
\family default
\series default
,
\family typewriter
\series bold
ikr
\family default
\series default
, and
\family typewriter
\series bold
nc
\family default
\series default
, which determine the reverse current gain characteristics, and
\family typewriter
\series bold
vaf
\family default
\series default
and
\family typewriter
\series bold
var
\family default
\series default
, which determine the output conductance for forward and reverse regions.
\end_layout
\begin_layout Standard
The level 1 model has among the standard temperature parameters an extension
compatible with most foundry provided process design kits (see parameter
table below
\family typewriter
\series bold
tlev
\family default
\series default
).
\end_layout
\begin_layout Standard
The level 1 and 2 models include the substrate saturation current
\family typewriter
\series bold
iss
\family default
\series default
.
Three ohmic resistances
\family typewriter
\series bold
rb
\family default
\series default
,
\family typewriter
\series bold
rc
\family default
\series default
, and
\family typewriter
\series bold
re
\family default
\series default
are included, where
\family typewriter
\series bold
rb
\family default
\series default
can be high current dependent.
Base charge storage is modeled by forward and reverse transit times,
\family typewriter
\series bold
tf
\family default
\series default
and
\family typewriter
\series bold
tr
\family default
\series default
, where the forward transit time
\family typewriter
\series bold
tf
\family default
\series default
can be bias dependent if desired.
Nonlinear depletion layer capacitances are defined with
\family typewriter
\series bold
cje
\family default
\series default
,
\family typewriter
\series bold
vje
\family default
\series default
, and
\family typewriter
\series bold
nje
\family default
\series default
for the B-E junction,
\family typewriter
\series bold
cjc
\family default
\series default
,
\family typewriter
\series bold
vjc
\family default
\series default
, and
\family typewriter
\series bold
njc
\family default
\series default
for the B-C junction and
\family typewriter
\series bold
cjs
\family default
\series default
,
\family typewriter
\series bold
vjs
\family default
\series default
, and
\family typewriter
\series bold
mjs
\family default
\series default
for the C-S (collector-substrate) junction.
\end_layout
\begin_layout Standard
The level 1 and 2 model support a substrate capacitance that is connected
to the device's base or collector, to model lateral or vertical devices
dependent on the parameter
\family typewriter
\series bold
subs
\family default
\series default
.
The temperature dependence of the saturation currents,
\family typewriter
\series bold
is
\family default
\series default
and
\family typewriter
\series bold
iss
\family default
\series default
(for the level 2 model), is determined by the energy-gap,
\family typewriter
\series bold
eg
\family default
\series default
, and the saturation current temperature exponent,
\family typewriter
\series bold
xti
\family default
\series default
.
\end_layout
\begin_layout Standard
In the new model, additional base current temperature dependence is modeled
by the beta temperature exponent
\family typewriter
\series bold
xtb
\family default
\series default
.
The values specified are assumed to have been measured at the temperature
\family typewriter
\series bold
tnom
\family default
\series default
, which can be specified on the
\family typewriter
.options
\family default
control line or overridden by a specification on the
\family typewriter
.model
\family default
line.
\end_layout
\begin_layout Standard
The level 4 model (VBIC) has the following improvements beyond the GP models:
improved Early effect modeling, quasi-saturation modeling, parasitic substrate
transistor modeling, parasitic fixed (oxide) capacitance modeling, includes
an avalanche multiplication model, improved temperature modeling, base
current is decoupled from collector current, electrothermal modeling, smooth
and continuous mode.
\end_layout
\begin_layout Standard
The BJT parameters used in the modified Gummel-Poon model are listed below.
The parameter names used in earlier versions of SPICE2 are still accepted.
\end_layout
\begin_layout Subsubsection*
Gummel-Poon BJT Parameters (incl.
model extensions)
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameters
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Scale factor
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
SUBS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Substrate connection: for vertical geometry, -1 for lateral geometry (level
2 only).
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Transport saturation current.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-16
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ISS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Reverse saturation current, substrate-to-collector for vertical device or
substrate-to-base for lateral (level 2 only).
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-16
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Ideal maximum forward beta.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Forward current emission coefficient.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VAF (VA)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Forward Early voltage.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
200
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IKF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Corner for forward beta current roll-off.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.01
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
NKF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
High current Beta rolloff exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.58
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ISE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-E leakage saturation current.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-13
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-E leakage emission coefficient.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Ideal maximum reverse beta.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Reverse current emission coefficient.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VAR (VB)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Reverse Early voltage.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
200
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IKR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Corner for reverse beta high current roll-off.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.01
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ISC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-C leakage saturation current (area is `areab' for vertical devices and
`areac' for lateral).
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-13
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-C leakage emission coefficient.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero bias base resistance.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IRB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Current where base resistance falls halfway to its min value.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RBM
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Minimum base resistance at high currents.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Emitter resistance.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Collector resistance.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-E zero-bias depletion capacitance.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VJE (PE)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-E built-in potential.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.75
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJE (ME)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-E junction exponential factor.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.33
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.33
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Ideal forward transit time.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
sec
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1ns
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XTF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Coefficient for bias dependence of TF.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VTF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Voltage describing VBC dependence of TF.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\infty$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ITF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
High-current parameter for effect on TF.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PTF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Excess phase at freq=
\begin_inset Formula $\dfrac{1}{2\pi TF}$
\end_inset
Hz.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
deg
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-C zero-bias depletion capacitance (area is `areab' for vertical devices
and `areac' for lateral).
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VJC (PC)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-C built-in potential.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.75
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B-C junction exponential factor.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.33
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XCJC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Fraction of B-C depletion capacitance connected to internal base node.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Ideal reverse transit time.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
sec
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10ns
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias collector-substrate capacitance (area is `areac' for vertical
devices and `areab' for lateral).
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VJS (PS)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Substrate junction built-in potential.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.75
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJS (MS)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Substrate junction exponential factor.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XTB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Forward and reverse beta temperature exponent.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
EG
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\begin_inset Text
\begin_layout Plain Layout
Energy gap for temperature effect on IS.
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $eV$
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\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1.11
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
XTI
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\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Temperature exponent for effect on IS.
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
3
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
KF
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\begin_inset Text
\begin_layout Plain Layout
Flicker-noise coefficient.
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
0
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
AF
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\begin_inset Text
\begin_layout Plain Layout
Flicker-noise exponent.
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Coefficient for forward-bias depletion capacitance formula.
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
TNOM (TREF)
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
Parameter measurement temperature.
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $°C$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
27
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
50
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TLEV
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
BJT temperature equation selector
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TLEVC
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
BJT capac.
temperature equation selector
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TRE1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for RE.
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TRE2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for RE.
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TRC1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for RC .
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRC2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for RC.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRB1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for RB.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRB2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for RB.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRBM1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for RBM
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TRBM2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for RBM
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TBF1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for BF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TBF2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for BF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TBR1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for BR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TBR2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for BR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TIKF1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for IKF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TIKF2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for IKF
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TIKR1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for IKR
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TIKR2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for IKR
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
TIRB1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for IRB
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TIRB2
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for IRB
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNC1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for NC
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNC2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for NC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNE1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for NE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNE2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for NE
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNF1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for NF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNF2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for NF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNR1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for IKF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNR2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for IKF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TVAF1
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for VAF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TVAF2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2nd order temperature coefficient for VAF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TVAR1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1st order temperature coefficient for VAR
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
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TVAR2
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\begin_layout Plain Layout
2nd order temperature coefficient for VAR
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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CTC
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\begin_layout Plain Layout
1st order temperature coefficient for CJC
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{°C}$
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0.0
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CTE
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1st order temperature coefficient for CJE
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\begin_inset Formula $\nicefrac{1}{°C}$
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CTS
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1st order temperature coefficient for CJS
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\begin_inset Formula $\nicefrac{1}{°C}$
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TVJC
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1st order temperature coefficient for VJC
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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TVJE
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1st order temperature coefficient for VJE
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\begin_inset Formula $\nicefrac{1}{°C}$
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TITF1
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1st order temperature coefficient for ITF
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\begin_inset Formula $\nicefrac{1}{°C}$
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TITF2
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2nd order temperature coefficient for ITF
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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TTF1
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1st order temperature coefficient for TF
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\begin_inset Formula $\nicefrac{1}{°C}$
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2nd order temperature coefficient for TF
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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TTR1
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1st order temperature coefficient for TR
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\begin_inset Formula $\nicefrac{1}{°C}$
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2nd order temperature coefficient for TR
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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1st order temperature coefficient for MJE
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\begin_inset Formula $\nicefrac{1}{°C}$
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TMJE2
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2nd order temperature coefficient for MJE
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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TMJC1
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1st order temperature coefficient for MJC
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\begin_inset Formula $\nicefrac{1}{°C}$
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TMJC2
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2nd order temperature coefficient for MJC
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\begin_inset Formula $\nicefrac{1}{°C^{2}}$
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\end_inset
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "cha:JFETs"
\end_inset
JFETs
\end_layout
\begin_layout Section
Junction Field-Effect Transistors (JFETs)
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
JXXXXXXX nd ng ns mname
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
J1 7 2 3 JM1 OFF
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
nd
\family default
\series default
,
\family typewriter
\series bold
ng
\family default
\series default
, and
\family typewriter
\series bold
ns
\family default
\series default
are the drain, gate, and source nodes, respectively.
\family typewriter
\series bold
mname
\family default
\series default
is the model name,
\family typewriter
\series bold
area
\family default
\series default
is the area factor, and
\family typewriter
\series bold
off
\family default
\series default
indicates an (optional) initial condition on the device for dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition specification, using
\family typewriter
\series bold
ic=VDS,VGS
\family default
\series default
is intended for use with the
\family typewriter
\series bold
uic
\family default
\series default
option on the
\family typewriter
.TRAN
\family default
control line, when a transient analysis is desired starting from other
than the quiescent operating point.
See the
\family typewriter
.ic
\family default
control line for a better way to set initial conditions.
The (optional)
\family typewriter
temp
\family default
value is the temperature where this device is to operate, and overrides
the temperature specification on the
\family typewriter
.option
\family default
control line.
\end_layout
\begin_layout Section
JFET Models (NJF/PJF)
\end_layout
\begin_layout Subsection
JFET level 1 model with Parker Skellern modification
\end_layout
\begin_layout Standard
The
\series bold
level 1
\series default
JFET model is derived from the FET model of Shichman and Hodges.
The dc characteristics are defined by the parameters VTO and BETA, which
determine the variation of drain current with gate voltage, LAMBDA, which
determines the output conductance, and IS, the saturation current of the
two gate junctions.
Two ohmic resistances, RD and RS, are included.
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
vgst=vgs-VTO
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
\beta_{p}=BETA\:(1+LAMBDA\:vds)
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
bfac=\frac{1-B}{PB-VTO}
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
I_{Drain}=\begin{cases}
vds\cdot GMIN, & \mathrm{if}\;vgst\leq0\\
\beta_{p}\:vds\:(vds\:(bfac\:vds-B)\:vgst\:(2B+3bfac\:(vgst-vds)))+vds\cdot GMIN, & \mathrm{if}\;vgst\geq vds\\
\beta_{p}\:vgst^{2}\:(B+vgst\:bfac)+vds\cdot GMIN, & \mathrm{if}\;vgst
\begin_inset Text
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Name
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Parameter
\end_layout
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Units
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Default
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\begin_layout Plain Layout
Example
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Scaling factor
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\end_inset
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\begin_inset Text
\begin_layout Plain Layout
VTO
\end_layout
\end_inset
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\begin_layout Plain Layout
Threshold voltage
\begin_inset Formula $V_{T0}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
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-2.0
\end_layout
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-2.0
\end_layout
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\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
BETA
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Transconductance parameter (
\begin_inset Formula $\beta$
\end_inset
)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{A}{V^{"}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-4
\end_layout
\end_inset
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\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LAMBDA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Channel-length modulation parameter (
\begin_inset Formula $\lambda$
\end_inset
)
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
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0
\end_layout
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1.0e-4
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
RD
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Drain ohmic resistance
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
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0
\end_layout
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100
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area
\end_layout
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RS
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Source ohmic resistance
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
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0
\end_layout
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100
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area
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
CGS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias G-S junction capacitance
\begin_inset Formula $C_{gs}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
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\begin_inset Text
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5pF
\end_layout
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\begin_inset Text
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area
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
CGD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias G-D junction capacitance
\begin_inset Formula $C_{gd}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
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0
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1pF
\end_layout
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area
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
PB
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
Gate junction potential
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
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|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
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\end_layout
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\begin_layout Plain Layout
IS
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
Gate saturation current
\begin_inset Formula $I_{S}$
\end_inset
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
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|
\begin_inset Text
\begin_layout Plain Layout
1.0e-14
\end_layout
\end_inset
|
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1.0e-14
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
area
\end_layout
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
B
\end_layout
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\begin_inset Text
\begin_layout Plain Layout
Doping tail parameter
\end_layout
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\begin_inset Text
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-
\end_layout
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1
\end_layout
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1.1
\end_layout
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\begin_layout Plain Layout
KF
\end_layout
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Flicker noise coefficient
\end_layout
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Flicker noise exponent
\end_layout
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\begin_inset Text
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1
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\end_layout
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\begin_inset Text
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-
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GDSNOI
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\begin_inset Text
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Channel noise coefficient for nlev=3
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1.0
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2.0
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FC
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Coefficient for forward-bias depletion capacitance formula
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0.5
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\begin_layout Plain Layout
TNOM
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\begin_layout Plain Layout
Parameter measurement temperature
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\begin_layout Plain Layout
\begin_inset Formula $°C$
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\begin_layout Plain Layout
27
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\begin_layout Plain Layout
50
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\begin_layout Plain Layout
\end_layout
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\begin_layout Plain Layout
TCV
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\begin_layout Plain Layout
Threshold voltage temperature coefficient
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{\text{°}C}$
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0.0
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0.1
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\begin_layout Plain Layout
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\begin_layout Plain Layout
BEX
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Mobility temperature exponent
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-
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0.0
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1.1
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\begin_layout Plain Layout
\end_layout
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\end_inset
\end_layout
\begin_layout Standard
Additional to the standard thermal and flicker noise model an alternative
thermal channel noise model is implemented and is selectable by setting
NLEV parameter to 3.
This follows in a correct channel thermal noise in the linear region.
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
S_{noise}=\frac{2}{3}\:4kT\cdot BETA\cdot Vgst\:\frac{(1+\text{\alpha}+\alpha^{2})}{1+\alpha}GDSNOI
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
with
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
\alpha=\begin{cases}
1-\frac{vds}{vgs-VTO}, & \mathrm{if}\;vgs-VTO\geq vds\\
0, & \mathrm{else}
\end{cases}
\end{equation}
\end_inset
\end_layout
\begin_layout Subsection
JFET level 2 Parker Skellern model
\end_layout
\begin_layout Standard
The level 2 model is an improvement to level 1.
Details are available from
\begin_inset CommandInset href
LatexCommand href
name "Macquarie University"
target "http://www.engineering.mq.edu.au/research/groups/cnerf/psmodel/index.htm"
\end_inset
.
Some important items are:
\end_layout
\begin_layout Itemize
The description maintains strict continuity in its high-order derivatives,
which is essential for prediction of distortion and intermodulation.
\end_layout
\begin_layout Itemize
Frequency dependence of output conductance and transconductance is described
as a function of bias.
\end_layout
\begin_layout Itemize
Both drain-gate and source-gate potentials modulate the pinch-off potential,
which is consistent with S-parameter and pulsed-bias measurements.
\end_layout
\begin_layout Itemize
Self-heating varies with frequency.
\end_layout
\begin_layout Itemize
Extreme operating regions - subthreshold, forward gate bias, controlled
resistance, and breakdown regions - are included.
\end_layout
\begin_layout Itemize
Parameters provide independent fitting to all operating regions.
It is not necessary to compromise one region in favor of another.
\end_layout
\begin_layout Itemize
Strict drain-source symmetry is maintained.
The transition during drain-source potential reversal is smooth and continuous.
\end_layout
\begin_layout Standard
The model equations are described in this
\begin_inset CommandInset href
LatexCommand href
name "pdf document"
target "http://www.engineering.mq.edu.au/research/groups/cnerf/psfet.pdf"
\end_inset
and in
\begin_inset CommandInset citation
LatexCommand cite
key "key-19"
\end_inset
.
\end_layout
\begin_layout Standard
\begin_inset Tabular
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Name
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Description
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Unit Type
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Default
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ID
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Device IDText
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Text
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\begin_layout Plain Layout
PF1
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\begin_layout Plain Layout
ACGAM
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\begin_layout Plain Layout
Capacitance modulation
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None
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0
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BETA
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Linear-region transconductance scale
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\begin_layout Plain Layout
None
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\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $10^{−4}$
\end_inset
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\begin_inset Text
\begin_layout Plain Layout
CGD
\end_layout
\end_inset
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\begin_layout Plain Layout
Zero-bias gate-source capacitance
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Capacitance
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0 F
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CGS
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Zero-bias gate-drain capacitance
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Capacitance
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0 F
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DELTA
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Thermal reduction coefficient
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None
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0 W
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FC
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Forward bias capacitance parameter
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None
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0.5
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HFETA
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High-frequency VGS feedback parameter
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None
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0
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HFE1
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HFGAM modulation by VGD
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None
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\begin_inset Formula $0V^{−1}$
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HFE2
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HFGAM modulation by VGS
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None
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0 V−1
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HFGAM
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High-frequency VGD feedback parameter
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None
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0
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HFG1
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HFGAM modulation by VSG
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None
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0 V−1
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HFG2
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HFGAM modulation by VDG
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None
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0 V−1
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IBD
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Gate-junction breakdown current
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Current
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0 A
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IS
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Gate-junction saturation current
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Current
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10−14A
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LFGAM
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Low-frequency feedback parameter
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None
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0
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LFG1
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LFGAM modulation by VSG
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None
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0 V−1
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LFG2
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LFGAM modulation by VDG
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None
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0 V−1
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MVST
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Subthreshold modulation
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None
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0 V−1
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N
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Gate-junction ideality factor
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P
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Q
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Saturated-region power-law exponent
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RS
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Source ohmic resistance
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Resistance
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0 Ohm
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RD
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Drain ohmic resistance
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Resistance
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0 Ohm
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TAUD
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Relaxation time for thermal reduction
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Gate-junction breakdown potential
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VTO
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Capacitance pinch-off reduction factor
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1000
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Z
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Knee transition parameter
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RG
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Gate ohmic resistance
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Source inductance
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Fixed Drain-source capacitance
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TNOM
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Nominal Temperature (Not implemented)
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\begin_layout Chapter
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name "cha:MESFETs"
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MESFETs
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\begin_layout Section
MESFETs
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Z1 7 2 3 ZM1 OFF
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\end_layout
\begin_layout Section
MESFET Models (NMF/PMF)
\end_layout
\begin_layout Subsection
Model by Statz e.a.
\end_layout
\begin_layout Standard
The MESFET model
\series bold
level 1
\series default
is derived from the GaAs FET model of Statz et al.
as described in
\begin_inset CommandInset citation
LatexCommand cite
key "key-11"
\end_inset
.
The dc characteristics are defined by the parameters VTO, B, and BETA,
which determine the variation of drain current with gate voltage, ALPHA,
which determines saturation voltage, and LAMBDA, which determines the output
conductance.
The formula are given by:
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
I_{d}=\begin{cases}
\frac{B(V_{gs}-V_{T})^{2}}{1+b(V_{gs}-V_{T})}\left|1-\left|1-A\frac{V_{ds}}{3}\right|^{3}\right|(1+LV_{ds}) & \mathrm{for\;}0\frac{3}{A}
\end{cases}
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
Two ohmic resistances,
\family typewriter
\series bold
rd
\family default
\series default
and
\family typewriter
\series bold
rs
\family default
\series default
, are included.
Charge storage is modeled by total gate charge as a function of gate-drain
and gate-source voltages and is defined by the parameters
\family typewriter
\series bold
cgs
\family default
\series default
,
\family typewriter
\series bold
cgd
\family default
\series default
, and
\family typewriter
\series bold
pb
\family default
\series default
.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VTO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Pinch-off voltage
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-2.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-2.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BETA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Transconductance parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{A}{V^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
B
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Doping tail extending parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ALPHA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Saturation voltage parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LAMBDA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Channel-length modulation parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Drain ohmic resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source ohmic resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
100
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias G-S junction capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
5pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias G-D junction capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1pF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate junction potential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
KF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
AF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Coefficient for forward-bias depletion capacitance formula
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Device instance:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
z1 2 3 0 mesmod area=1.4
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Model:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.model mesmod nmf level=1 rd=46 rs=46 vt0=-1.3
\end_layout
\begin_layout Plain Layout
+ lambda=0.03 alpha=3 beta=1.4e-3
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Subsection
Model by Ytterdal e.a.
\end_layout
\begin_layout Standard
\series bold
level 2
\series default
(and levels 3,4) Copyright 1993: T.
Ytterdal, K.
Lee, M.
Shur and T.
A.
Fjeldly
\end_layout
\begin_layout Standard
to be written
\end_layout
\begin_layout Standard
M.
Shur, T.A.
Fjeldly, T.
Ytterdal, K.
Lee, "Unified GaAs MESFET Model for Circuit Simulation", Int.
Journal of High Speed Electronics, vol.
3, no.
2, pp.
201-233, 1992
\end_layout
\begin_layout Subsection
hfet1
\end_layout
\begin_layout Standard
\series bold
level 5
\end_layout
\begin_layout Standard
to be written
\end_layout
\begin_layout Standard
no documentation available
\end_layout
\begin_layout Subsection
hfet2
\end_layout
\begin_layout Standard
\series bold
level6
\end_layout
\begin_layout Standard
to be written
\end_layout
\begin_layout Standard
no documentation available
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "cha:MOSFETs"
\end_inset
MOSFETs
\end_layout
\begin_layout Standard
Ngspice supports all the original mosfet models present in SPICE3f5 and
almost all the newer ones that have been published and made open-source.
Both bulk and SOI (Silicon on Insulator) models are available.
When compiled with the cider option, ngspice implements the four terminals
numerical model that can be used to simulate a MOSFET (please refer to
numerical modeling documentation for additional information and examples).
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:MOSFET-devices"
\end_inset
MOSFET devices
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
MXXXXXXX nd ng ns nb mname
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
M1 24 2 0 20 TYPE1
\end_layout
\begin_layout Plain Layout
M31 2 17 6 10 MOSN L=5U W=2U
\end_layout
\begin_layout Plain Layout
M1 2 9 3 0 MOSP L=10U W=5U AD=100P AS=100P PD=40U PS=40U
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Note the suffixes in the example: the suffix `u' specifies microns (1e-6
\begin_inset Formula $\mathrm{m}$
\end_inset
) and `p' sq-microns (1e-12
\begin_inset Formula $\mathrm{m^{2}}$
\end_inset
).
\end_layout
\begin_layout Standard
The instance card for MOS devices starts with the letter '
\family typewriter
\series bold
M
\family default
\series default
'.
\family typewriter
\series bold
nd
\family default
\series default
,
\family typewriter
\series bold
ng
\family default
\series default
,
\family typewriter
\series bold
ns
\family default
\series default
, and
\family typewriter
\series bold
nb
\family default
\series default
are the drain, gate, source, and bulk (substrate) nodes, respectively.
\family typewriter
\series bold
mname
\family default
\series default
is the model name and
\family typewriter
\series bold
m
\family default
\series default
is the multiplicity parameter, which simulates `
\family typewriter
m
\family default
' paralleled devices.
All MOS models support the `
\family typewriter
\series bold
m
\family default
\series default
' multiplier parameter.
Instance parameters
\family typewriter
\series bold
l
\family default
\series default
and
\family typewriter
\series bold
w
\family default
\series default
, channel length and width respectively, are expressed in meters.
The areas of drain and source diffusions:
\family typewriter
\series bold
ad
\family default
\series default
and
\family typewriter
\series bold
as
\family default
\series default
, in squared meters (
\begin_inset Formula $\mathrm{m^{2}}$
\end_inset
).
\end_layout
\begin_layout Standard
If any of
\family typewriter
\series bold
l
\family default
\series default
,
\family typewriter
\series bold
w
\family default
\series default
,
\family typewriter
\series bold
ad
\family default
\series default
, or
\family typewriter
\series bold
as
\family default
\series default
are not specified, default values are used.
The use of defaults simplifies input file preparation, as well as the editing
required if device geometries are to be changed.
\family typewriter
\series bold
pd
\family default
\series default
and
\family typewriter
\series bold
ps
\family default
\series default
are the perimeters of the drain and source junctions, in meters.
\family typewriter
\series bold
nrd
\family default
\series default
and
\family typewriter
\series bold
nrs
\family default
\series default
designate the equivalent number of squares of the drain and source diffusions;
these values multiply the sheet resistance
\family typewriter
\series bold
rsh
\family default
\series default
specified on the
\family typewriter
.model
\family default
control line for an accurate representation of the parasitic series drain
and source resistance of each transistor.
\family typewriter
\series bold
pd
\family default
\series default
and
\family typewriter
\series bold
ps
\family default
\series default
default to 0.0 while
\family typewriter
\series bold
nrd
\family default
\series default
and
\family typewriter
\series bold
nrs
\family default
\series default
to 1.0.
\family typewriter
\series bold
off
\family default
\series default
indicates an (optional) initial condition on the device for dc analysis.
The (optional) initial condition specification using
\family typewriter
\series bold
ic=vds,vgs,vbs
\family default
\series default
is intended for use with the
\family typewriter
\series bold
uic
\family default
\series default
option on the
\family typewriter
.tran
\family default
control line, when a transient analysis is desired starting from other
than the quiescent operating point.
See the
\family typewriter
.ic
\family default
control line for a better and more convenient way to specify transient
initial conditions.
The (optional)
\family typewriter
\series bold
temp
\family default
\series default
value is the temperature at which this device is to operate, and overrides
the temperature specification on the
\family typewriter
.option
\family default
control line.
\end_layout
\begin_layout Standard
The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs,
not for level 4 or 5 (BSIM) devices.
\end_layout
\begin_layout Standard
BSIM3 (v3.2 and v3.3.0), BSIM4 (v4.7 and v4.8) and BSIMSOI models are also supporting
the instance parameter
\family typewriter
\series bold
delvto
\family default
\series default
and
\family typewriter
\series bold
mulu0
\family default
\series default
for local mismatch and NBTI (negative bias temperature instability) modeling:
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Default
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Example
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
delvto (delvt0)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Threshold voltage shift
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.07
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
mulu0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Low-field mobility multiplier (U0)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.9
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Section
MOSFET models (NMOS/PMOS)
\end_layout
\begin_layout Standard
MOSFET models are the central part of ngspice, probably because they are
the most widely used devices in the electronics world.
Ngspice provides all the MOSFETs implemented in the original Spice3f and
adds several models developed by
\begin_inset CommandInset href
LatexCommand href
name "UC Berkeley's Device Group"
target "http://www-device.eecs.berkeley.edu/bsim/"
\end_inset
and other independent groups.
\end_layout
\begin_layout Standard
Each model is invoked with a
\family typewriter
.model
\family default
card.
A minimal version is:
\end_layout
\begin_layout Standard
\family typewriter
.model MOSN NMOS level=8 version=3.3.0
\end_layout
\begin_layout Standard
The model name MOSN corresponds to the model name in the instance card (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:MOSFET-devices"
\end_inset
).
Parameter NMOS selects an n-channel device, PMOS would point to a p-channel
transistor.
The
\family typewriter
\series bold
level
\family default
\series default
and
\family typewriter
\series bold
version
\family default
\series default
parameters select the specific model.
Further model parameters are optional and replace ngspice default values.
Due to the large number of parameters (more than 100 for modern models),
model cards may be stored in extra files and loaded into the netlist by
the .include (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:.INCLUDE"
\end_inset
) command.
Model cards are specific for a an IC manufacturing process and are typically
provided by the IC foundry.
Some generic parameter sets, not linked to a specific process, are made
available by the model developers, e.g.
\begin_inset CommandInset href
LatexCommand href
name "UC Berkeley's Device Group"
target "http://www-device.eecs.berkeley.edu/bsim/"
\end_inset
for BSIM4 and BSIMSOI.
\end_layout
\begin_layout Standard
Ngspice provides several MOSFET device models, which differ in the formulation
of the I-V characteristic, and are of varying complexity.
Models available are listed in table
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:MOSFET-model-summary"
\end_inset
.
Current models for IC design are BSIM3 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM3-model"
\end_inset
, down to channel length of 0.25 µm), BSIM4 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM4-model"
\end_inset
, below 0.25 µm), BSIMSOI (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIMSOI-models"
\end_inset
, silicon-on-insulator devices), HiSIM2 and HiSIM_HV (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:HiSIM-models-of"
\end_inset
, surface potential models for standard and high voltage/high power MOS
devices).
\end_layout
\begin_layout Standard
\begin_inset Float table
wide false
sideways false
status open
\begin_layout Plain Layout
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
Level
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Model
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Version
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Developer
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
References
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Notes
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
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\begin_inset Caption Standard
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\begin_inset CommandInset label
LatexCommand label
name "tab:MOSFET-model-summary"
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MOSFET model summary
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\begin_layout Subsection
MOS Level 1
\end_layout
\begin_layout Standard
This model is also known as the `Shichman-Hodges' model.
This is the first model written and the one often described in the introductory
textbooks for electronics.
This model is applicable only to long channel devices.
The use of Meyer's model for the C-V part makes it non charge conserving.
\end_layout
\begin_layout Subsection
MOS Level 2
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\begin_layout Standard
This model tries to overcome the limitations of the Level 1 model addressing
several short-channel effects, like velocity saturation.
The implementation of this model is complicated and this leads to many
convergence problems.
C-V calculations can be done with the original Meyer model (non charge
conserving).
\end_layout
\begin_layout Subsection
MOS Level 3
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\begin_layout Standard
This is a semi-empirical model derived from the Level 2 model.
In the 80s this model has often been used for digital design and, over
the years, has proved to be robust.
A discontinuity in the model with respect to the KAPPA parameter has been
detected (see [10]).
The supplied fix has been implemented in Spice3f2 and later.
Since this fix may affect parameter fitting, the option
\family typewriter
\series bold
badmos3
\family default
\series default
may be set to use the old implementation (see the section on simulation
variables and the
\family typewriter
.options
\family default
line).
Ngspice level 3 implementation takes into account length and width mask
adjustments (
\family typewriter
\series bold
xl
\family default
\series default
and
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xw
\family default
\series default
) and device width narrowing due to diffusion (
\family typewriter
\series bold
wd
\family default
\series default
).
\end_layout
\begin_layout Subsection
MOS Level 6
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\begin_layout Standard
This model is described in
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
\end_inset
.
The model can express the current characteristics of short-channel MOSFETs
at least down to 0.25
\begin_inset Formula $\mu m$
\end_inset
channel-length, GaAs FET, and resistance inserted MOSFETs.
The model evaluation time is about 1/3 of the evaluation time of the SPICE3
mos level 3 model.
The model also enables analytical treatments of circuits in short-channel
region and makes up for a missing link between a complicated MOSFET current
characteristics and circuit behaviors in the deep submicron region.
\end_layout
\begin_layout Subsection
Notes on Level 1-6 models
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\begin_layout Standard
The dc characteristics of the level 1 through level 3 MOSFETs are defined
by the device parameters
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vto
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,
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kp
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,
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lambda
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\series default
,
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phi
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\series default
and
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gamma
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.
These parameters are computed by ngspice if process parameters (
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nsub
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,
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tox
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, ...) are given, but users specified values always override.
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vto
\family default
\series default
is positive (negative) for enhancement mode and negative (positive) for
depletion mode N-channel (P-channel) devices.
\end_layout
\begin_layout Standard
Charge storage is modeled by three constant capacitors,
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cgso
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,
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cgdo
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, and
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cgbo
\family default
\series default
, which represent overlap capacitances, by the nonlinear thin-oxide capacitance
that is distributed among the gate, source, drain, and bulk regions, and
by the nonlinear depletion-layer capacitances for both substrate junctions
divided into bottom and periphery, which vary as the
\family typewriter
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mj
\family default
\series default
and
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mjsw
\family default
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power of junction voltage respectively, and are determined by the parameters
\family typewriter
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cbd
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,
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cbs
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,
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cj
\family default
\series default
,
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cjsw
\family default
\series default
,
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mj
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\series default
,
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mjsw
\family default
\series default
and
\family typewriter
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pb
\family default
\series default
.
\end_layout
\begin_layout Standard
Charge storage effects are modeled by the piecewise linear voltages-dependent
capacitance model proposed by Meyer.
The thin-oxide charge-storage effects are treated slightly different for
the level 1 model.
These voltage-dependent capacitances are included only if
\family typewriter
\series bold
tox
\family default
\series default
is specified in the input description and they are represented using Meyer's
formulation.
\end_layout
\begin_layout Standard
There is some overlap among the parameters describing the junctions, e.g.
the reverse current can be input either as
\family typewriter
\series bold
is
\family default
\series default
(in A) or as
\family typewriter
\series bold
js
\family default
\series default
(in
\begin_inset Formula $\nicefrac{A}{m^{2}}$
\end_inset
).
Whereas the first is an absolute value the second is multiplied by
\family typewriter
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ad
\family default
\series default
and
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\series bold
as
\family default
\series default
to give the reverse current of the drain and source junctions respectively.
\end_layout
\begin_layout Standard
This methodology has been chosen since there is no sense in relating always
junction characteristics with
\family typewriter
\series bold
ad
\family default
\series default
and
\family typewriter
\series bold
as
\family default
\series default
entered on the device line; the areas can be defaulted.
The same idea applies also to the zero-bias junction capacitances
\family typewriter
\series bold
cbd
\family default
\series default
and
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cbs
\family default
\series default
(in F) on one hand, and
\family typewriter
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cj
\family default
\series default
(in
\begin_inset Formula $\nicefrac{F}{m^{2}}$
\end_inset
) on the other.
\end_layout
\begin_layout Standard
The parasitic drain and source series resistance can be expressed as either
\family typewriter
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rd
\family default
\series default
and
\family typewriter
\series bold
rs
\family default
\series default
(in ohms) or
\family typewriter
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rsh
\family default
\series default
(in ohms/sq.), the latter being multiplied by the number of squares
\family typewriter
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nrd
\family default
\series default
and
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nrs
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input on the device line.
\end_layout
\begin_layout Subsubsection*
\noindent
NGSPICE level 1, 2, 3 and 6 parameters
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\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LEVEL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Model index
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VTO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias threshold voltage (
\begin_inset Formula $V_{T0})$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
KP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Transconductance parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{A}{V^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2.0e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.1e-5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
GAMMA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk threshold parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\sqrt{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.37
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHI
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Surface potential (U)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.6
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.65
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LAMBDA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Channel length modulation (MOS1 and MOS2 only) (
\begin_inset Formula $\lambda)$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.02
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Drain ohmic resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source ohmic resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\Omega$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CBD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias B-D junction capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
20fF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CBS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias B-S junction capacitance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $F$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
20fF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
IS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk junction saturation current (
\begin_inset Formula $I_{S}$
\end_inset
)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $A$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-14
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk junction potential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.8
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.87
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGSO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-source overlap capacitance per meter channel width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.0e-11
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGDO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-drain overlap capacitance per meter channel width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.0e-11
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGBO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-bulk overlap capacitance per meter channel width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2.0e-11
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RSH
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Drain and source diffusion sheet resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{\square}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias bulk junction bottom cap.
per sq-meter of junction area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
2.0e-4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk junction bottom grading coeff.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias bulk junction sidewall cap.
per meter of junction perimeter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-9
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk junction sidewall grading coeff.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\begin{array}{cc}
0.50 & \mathrm{(level}1)\\
0.33 & \mathrm{(level}2,3)
\end{array}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
JS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Bulk junction saturation current
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TOX
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Oxide thickness
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-7
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-7
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NSUB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Substrate doping
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $cm^{-3}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.0e15
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NSS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Surface state density
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $cm^{-2}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NFS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Fast surface state density
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $cm^{-2}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e10
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TPG
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Type of gate material: +1 opp.
to substrate, -1 same as substrate, 0 Al gate
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Metallurgical junction depth
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1M
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
LD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Lateral diffusion
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.8M
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
UO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Surface mobility
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
600
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
700
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
UCRIT
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Critical field for mobility degradation (MOS2 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{V}{cm}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
UEXP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Critical field exponent in mobility degradation (MOS2 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
UTRA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Transverse field coeff.
(mobility) (deleted for MOS2)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VMAX
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Maximum drift velocity of carriers
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{m}{s}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
5.0e4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NEFF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Total channel-charge (fixed and mobile) coefficient (MOS2 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
5.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
KF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0e-26
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
AF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flicker noise exponent
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
FC
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Coefficient for forward-bias depletion capacitance formula
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
DELTA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Width effect on threshold voltage (MOS2 and MOS3)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
THETA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Mobility modulation (MOS3 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ETA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Static feedback (MOS3 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
KAPPA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Saturation field factor (MOS3 only)
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
0.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TNOM
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parameter measurement temperature
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $°C$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
27
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
50
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Subsection
MOS Level 9
\end_layout
\begin_layout Standard
Documentation is not available..
\end_layout
\begin_layout Subsection
BSIM Models
\end_layout
\begin_layout Standard
Ngspice implements many of the BSIM models developed by
\begin_inset CommandInset href
LatexCommand href
name "Berkeley's BSIM group"
target "http://bsim.berkeley.edu/"
\end_inset
.
BSIM stands for Berkeley Short-Channel IGFET Model and groups a class of
models that is continuously updated.
BSIM3 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM3-model"
\end_inset
) and BSIM4 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM4-model"
\end_inset
) are industry standards for CMOS processes down to 0.15 µm (BSIM3) and below
(BSIM4), are very stable and are supported by model parameter sets from
foundries all over the world.
BSIM1 and BSIM2 are obsolete today.
\end_layout
\begin_layout Standard
In general, all parameters of BSIM models are obtained from process characteriza
tion, in particular level 4 and level 5 (BSIM1 and BSIM2) parameters can
be generated automatically.
J.
Pierret [4] describes a means of generating a `process' file, and the program
\family typewriter
ngproc2mod
\family default
provided with ngspice converts this file into a sequence of BSIM1
\family typewriter
.model
\family default
lines suitable for inclusion in an ngspice input file.
\end_layout
\begin_layout Standard
Parameters marked below with an
\family typewriter
*
\family default
in the
\family typewriter
l/w
\family default
column also have corresponding parameters with a length and width dependency.
For example,
\family typewriter
\series bold
vfb
\family default
\series default
is the basic parameter with units of Volts, and
\family typewriter
\series bold
lvfb
\family default
\series default
and
\family typewriter
\series bold
wvfb
\family default
\series default
also exist and have units of Volt-meter.
\end_layout
\begin_layout Standard
The formula
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
P=P_{0}+\frac{P_{L}}{L_{{\rm effective}}}+\frac{P_{W}}{W_{{\rm effective}}}
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
is used to evaluate the parameter for the actual device specified with
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
L_{{\rm effective}}=L_{{\rm input}}-DL
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Formula
\begin{equation}
W_{{\rm effective}}=W_{{\rm input}}-DW
\end{equation}
\end_inset
\end_layout
\begin_layout Standard
Note that unlike the other models in ngspice, the BSIM models are designed
for use with a process characterization system that provides all the parameters
, thus there are no defaults for the parameters, and leaving one out is
considered an error.
For an example set of parameters and the format of a process file, see
the SPICE2 implementation notes [3].
For more information on BSIM2, see reference [5].
BSIM3 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM3-model"
\end_inset
) and BSIM4 (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:BSIM4-model"
\end_inset
) represent state of the art for submicron and deep submicron IC design.
\end_layout
\begin_layout Subsection
BSIM1 model (level 4)
\end_layout
\begin_layout Standard
BSIM1 model (the first is a long series) is an empirical model.
Developers placed less emphasis on device physics and based the model on
parametrical polynomial equations to model the various physical effects.
This approach pays in terms of circuit simulation behavior but the accuracy
degrades in the submicron region.
A known problem of this model is the negative output conductance and the
convergence problems, both related to poor behavior of the polynomial equations.
\end_layout
\begin_layout Subsubsection*
Ngspice BSIM (level 4) parameters
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
Name
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Parameter
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Units
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
l/w
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VFB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Flat-band voltage
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PHI
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Surface inversion potential
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
K1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Body effect coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\sqrt{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
K2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Drain/source depletion charge-sharing coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ETA
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias drain-induced barrier-lowering coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MUZ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias mobility
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
DL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Shortening of channel
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\mu m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
DW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Narrowing of channel
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\mu m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
U0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias transverse-field mobility degradation coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
U1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias velocity saturation coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\mu}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X2MZ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of mobility to substrate bias at v=0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V^{2}\cdot sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X2E
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of drain-induced barrier lowering effect to substrate bias
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X3E
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of drain-induced barrier lowering effect to drain bias at
\begin_inset Formula $V_{ds}=V_{dd}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X2U0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of transverse field mobility degradation effect to substrate bias
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{1}{V^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X2U1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of velocity saturation effect to substrate bias
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\mu m}{V^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MUS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Mobility at zero substrate bias and at
\begin_inset Formula $V_{ds}=V_{dd}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X2MS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of mobility to substrate bias at
\begin_inset Formula $V_{ds}=V_{dd}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X3MS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of mobility to drain bias at
\begin_inset Formula $V_{ds}=V_{dd}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
X3U1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of velocity saturation effect on drain bias at Vds=Vdd
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\mu m}{V^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TOX
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate oxide thickness
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\mu m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
TEMP
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Temperature where parameters were measured
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $°C$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
VDD
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Measurement bias range
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGDO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-drain overlap capacitance per meter channel width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGSO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-source overlap capacitance per meter channel width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CGBO
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-bulk overlap capacitance per meter channel length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
XPART
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Gate-oxide capacitance-charge model flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
N0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Zero-bias subthreshold slope coefficient
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
NB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of subthreshold slope to substrate bias
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
ND
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Sens.
of subthreshold slope to drain bias
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
RSH
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Drain and source diffusion sheet resistance
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{\Omega}{\square}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
JS
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source drain junction current density
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{A}{m^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PB
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Built in potential of source drain junction
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Grading coefficient of source drain junction
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
PBSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Built in potential of source, drain junction sidewall
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $V$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
MJSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Grading coefficient of source drain junction sidewall
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
-
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJ
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source drain junction capacitance per unit area
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m^{2}}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
CJSW
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
source drain junction sidewall capacitance per unit length
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $\nicefrac{F}{m}$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
WDF
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source drain junction default width
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
DELL
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Source drain junction length reduction
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\begin_inset Formula $m$
\end_inset
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
xpart
\family default
\series default
= 0 selects a 40/60 drain/source charge partition in saturation, while
\family typewriter
\series bold
xpart
\family default
\series default
=1 selects a 0/100 drain/source charge partition.
\family typewriter
\series bold
nd
\family default
\series default
,
\family typewriter
\series bold
ng
\family default
\series default
, and
\family typewriter
\series bold
ns
\family default
\series default
are the drain, gate, and source nodes, respectively.
\family typewriter
\series bold
mname
\family default
\series default
is the model name,
\family typewriter
\series bold
area
\family default
\series default
is the area factor, and
\family typewriter
\series bold
off
\family default
\series default
indicates an (optional) initial condition on the device for dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition specification, using
\family typewriter
\series bold
ic=vds,vgs
\family default
\series default
is intended for use with the
\family typewriter
\series bold
uic
\family default
\series default
option on the
\family typewriter
.tran
\family default
control line, when a transient analysis is desired starting from other
than the quiescent operating point.
See the
\family typewriter
.ic
\family default
control line for a better way to set initial conditions.
\end_layout
\begin_layout Subsection
BSIM2 model (level 5)
\end_layout
\begin_layout Standard
This model contains many improvements over BSIM1 and is suitable for analog
simulation.
Nevertheless, even BSIM2 breaks transistor operation into several distinct
regions and this leads to discontinuities in the first derivative in C-V
and I-V characteristics that can cause numerical problems during simulation.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:BSIM3-model"
\end_inset
BSIM3 model (levels 8, 49)
\end_layout
\begin_layout Standard
BSIM3 solves the numerical problems of previous models with the introduction
of smoothing functions.
It adopts a single equation to describe device characteristics in the operating
regions.
This approach eliminates the discontinuities in the I-V and C-V characteristics.
The original model,
\begin_inset CommandInset href
LatexCommand href
name "BSIM3"
target "http://bsim.berkeley.edu/models/bsim3/"
\end_inset
evolved through three versions: BSIM3v1, BSIM3v2 and BSIM3v3.
Both BSIM3v1 and BSIM3v2 had suffered from many mathematical problems and
were replaced by BSIM3v3.
The latter is the only surviving release and has itself a long revision
history.
\end_layout
\begin_layout Standard
The following table summarizes the story of this model:
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
Release
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Date
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Notes
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Version flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM3v3.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10/30/1995
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM3v3.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
12/09/1996
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM3v3.2
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
06/16/1998
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Revisions available: BSIM3v3.2.2, BSIM3v3.2.3, and BSIM3v3.2.4
\end_layout
\begin_layout Plain Layout
Parallel processing with OpenMP is available for BSIM3v3.2.4.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.2, 3.2.2, 3.2.3, 3.2.4
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM3v3.3
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
07/29/2005
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Parallel processing with OpenMP is available for this model.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
3.3.0
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
BSIM3v2 and 3v3 models has proved for accurate use in 0.18
\begin_inset Formula $\mu m$
\end_inset
technologies.
The model is publicly available as
\begin_inset CommandInset href
LatexCommand href
name "source code"
target "http://bsim.berkeley.edu/BSIM4/BSIM3/ftpv330.zip"
\end_inset
form from University of California, Berkeley.
\end_layout
\begin_layout Standard
A detailed description is given in the user's manual available from
\begin_inset CommandInset href
LatexCommand href
name "here"
target "http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf"
\end_inset
.
\end_layout
\begin_layout Standard
We recommend that you use only the most recent BSIM3 models (version 3.3.0),
because it contains corrections to all known bugs.
To achieve that, change the version parameter in your modelcard files to
\end_layout
\begin_layout Standard
\family typewriter
VERSION = 3.3.0
\family default
.
\end_layout
\begin_layout Standard
If no version number is given in the
\family typewriter
.model
\family default
card, this (newest) version is selected as the default.
\end_layout
\begin_layout Standard
BSIM3v3.2.4 supports the extra model parameter
\family typewriter
lmlt
\family default
on channel length scaling and is still used by many foundries today.
\end_layout
\begin_layout Standard
The older models will not be supported, they are made available for reference
only.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:BSIM4-model"
\end_inset
BSIM4 model (levels 14, 54)
\end_layout
\begin_layout Standard
This is the newest class of the BSIM family and introduces noise modeling
and extrinsic parasitics.
BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects
into sub-100nm regime.
It is a physics-based, accurate, scalable, robust and predictive MOSFET
SPICE model for circuit simulation and CMOS technology development.
It is developed by the BSIM Research Group in the Department of Electrical
Engineering and Computer Sciences (EECS) at the University of California,
Berkeley (see
\begin_inset CommandInset href
LatexCommand href
name "BSIM4 home page"
target "http://bsim.berkeley.edu/models/bsim4/"
\end_inset
).
BSIM4 has a long revision history, which is summarized below.
\end_layout
\begin_layout Standard
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\series bold
Release
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Date
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Notes
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\series bold
Version flag
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.0.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
03/24/2000
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.1.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10/11/2000
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.2.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
04/06/2001
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.2.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
10/05/2001
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.2.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.3.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
05/09/2003
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.3.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.4.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
03/04/2004
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
*
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.4.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.5.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
07/29/2005
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
* **
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.5.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.6.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
12/13/2006
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
...
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.6.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
09/09/2009
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
* **
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.6.5
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.7.0
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
04/08/2011
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
* **
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.7
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
BSIM4.8.1
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
15/02/2017
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
* **
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
4.8
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Standard
*) supported in ngspice, using e.g.
the
\family typewriter
version=
\family default
flag in the parameter file.
\end_layout
\begin_layout Standard
**) Parallel processing using OpenMP support is available for this model.
\end_layout
\begin_layout Standard
Details of any revision are to be found in the Berkeley user's manuals,
a pdf download of the most recent edition is to be found
\begin_inset CommandInset href
LatexCommand href
name "here"
target "http://ngspice.sourceforge.net/external-documents/models/BSIM480_Manual.pdf"
\end_inset
.
\end_layout
\begin_layout Standard
We recommend that you use only the most recent BSIM4 model (version 4.8.1),
because it contains corrections to all known bugs.
To achieve that, change the version parameter in your modelcard files to
\end_layout
\begin_layout Standard
\family typewriter
VERSION = 4.8
\family default
.
\end_layout
\begin_layout Standard
If no version number is given in the
\family typewriter
.model
\family default
card, this (newest) version is selected as the default.
The older models will typically not be supported, they are made available
for reference only.
\end_layout
\begin_layout Subsection
EKV model
\end_layout
\begin_layout Standard
Level 44 model (EKV) is not available in the standard distribution since
it is not released in source form by the EKV group.
To obtain the code please refer to the (
\begin_inset CommandInset href
LatexCommand href
name "EKV model home page"
target "http://ekv.epfl.ch/"
\end_inset
, EKV group home page).
A verilog-A version is available contributed by Ivan Riis Nielsen 11/2006.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:BSIMSOI-models"
\end_inset
BSIMSOI models (levels 10, 58, 55, 56, 57)
\end_layout
\begin_layout Standard
BSIMSOI is a SPICE compact model for SOI (Silicon-On-Insulator) circuit
design, created by
\begin_inset CommandInset href
LatexCommand href
name "University of California at Berkeley"
target "http://bsim.berkeley.edu/models/bsimsoi/"
\end_inset
.
This model is formulated on top of the BSIM3 framework.
It shares the same basic equations with the bulk model so that the physical
nature and smoothness of BSIM3v3 are retained.
Four models are supported in ngspice, those based on BSIM3 and modeling
fully depleted (FD, level 55), partially depleted (PD, level 57) and both
(DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10,
58).
Detailed descriptions are beyond the scope of this manual, but see e.g.
\begin_inset CommandInset href
LatexCommand href
name "BSIMSOIv4.4 User Manual"
target "http://ngspice.sourceforge.net/external-documents/models/BSIMSOIv4.4_UsersManual.pdf"
\end_inset
for a very extensive description of the recent model version.
OpenMP support is available for levels 10, 58, version 4.4.
\end_layout
\begin_layout Subsection
SOI3 model (level 60)
\end_layout
\begin_layout Standard
see literature citation [18] for a description.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:HiSIM-models-of"
\end_inset
HiSIM models of the University of Hiroshima
\end_layout
\begin_layout Standard
There are two model implementations available - see also
\begin_inset CommandInset href
LatexCommand href
name "HiSIM Research Center"
target "https://www.hisim.hiroshima-u.ac.jp/index.php?id=87"
\end_inset
:
\end_layout
\begin_layout Enumerate
HiSIM2 model: Surface-Potential-Based MOSFET Model for Circuit Simulation
version 2.8.0 - level 68 (see
\begin_inset CommandInset href
LatexCommand href
name "link to HiSIM2"
target "http://home.hiroshima-u.ac.jp/usdl/HiSIM2/HiSIM_2.5.1_Release_20110407.zip"
\end_inset
for source code and manual).
\end_layout
\begin_layout Enumerate
HiSIM_HV model: Surface-Potential-Based HV/LD-MOSFET Model for Circuit Simulatio
n version 1.2.4 and 2.2.0 - level 73 (see
\begin_inset CommandInset href
LatexCommand href
name "link to HiSIM_HV"
target "http://home.hiroshima-u.ac.jp/usdl/HiSIM_HV/C-Code/HiSIM_HV_1.2.2_Release_20110629.zip"
\end_inset
for source code and manual).
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "cha:Behavioral-Modeling"
\end_inset
Mixed-Mode and Behavioral Modeling with XSPICE
\end_layout
\begin_layout Standard
Ngspice implements XSPICE extensions for behavioral and mixed-mode (analog
and digital) modeling.
In the XSPICE framework this is referred to as code level modeling.
Behavioral modeling may benefit dramatically because XSPICE offers a means
to add analog functionality programmed in C.
Many examples (amplifiers, oscillators, filters ...) are presented in the
following.
Even more flexibility is available because you may define your own models
and use them in addition and in combination with all the already existing
ngspice functionality.
Digital and mixed mode simulation is speeded up significantly by simulating
the digital part in an event driven manner, in that state equations use
only a few allowed states and are evaluated only during switching, and
not continuously in time and signal as in a pure analog simulator.
\end_layout
\begin_layout Standard
This chapter describes the predefined models available in ngspice, stemming
from the original XSPICE simulator or being added to enhance the usability.
The instructions for writing new code models are given in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Code-Models-and"
\end_inset
.
\end_layout
\begin_layout Standard
To make use of the XSPICE extensions, you need to compile them in.
Linux, CYGWIN, MINGW and other users may add the flag
\family typewriter
--enable-xspice
\family default
to their
\family typewriter
./configure
\family default
command and then recompile.
The pre-built ngspice for Windows distribution has XSPICE already enabled.
For detailed compiling instructions see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Ngspice-Installation-under"
\end_inset
.
\end_layout
\begin_layout Section
Code Model Element & .MODEL Cards
\end_layout
\begin_layout Subsection
Syntax
\end_layout
\begin_layout Standard
Ngspice includes a library of predefined `Code Models' that can be placed
within any circuit description in a manner similar to that used to place
standard device models.
Code model instance cards always begin with the letter `A', and always
make use of a
\family typewriter
.MODEL
\family default
card to describe the code model desired.
Section
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Code-Models-and"
\end_inset
of this document goes into greater detail as to how a code model similar
to the predefined models may be developed, but once any model is created
and linked into the simulator it may be placed using one instance card
and one
\family typewriter
.MODEL
\family default
card (note here we conform to the SPICE custom of referring to a single
logical line of information as a `card').
As an example, the following uses a predefined `gain' code model taking
as an input some value on node 1, multiplies it by a gain of 5.0, and outputs
the new value to node 2.
Note that, by convention, input ports are specified first on code models.
Output ports follow the inputs.
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
a1 1 2 amp
\end_layout
\begin_layout Plain Layout
.model amp gain(gain=5.0)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
In this example the numerical values picked up from single-ended (i.e.
ground referenced) input node 1 and output to single-ended output node
2 will be voltages, since in the Interface Specification File for this
code model (i.e., gain), the default port type is specified as a voltage
(more on this later).
However, if you didn't know this, the following modifications to the instance
card could be used to insure it:
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
a1 %v(1) %v(2) amp
\end_layout
\begin_layout Plain Layout
.model amp gain(gain=5.0)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The specification
\family typewriter
%v
\family default
preceding the input and output node numbers of the instance card indicate
to the simulator that the inputs to the model should be single-ended voltage
values.
Other possibilities exist, as described later.
\end_layout
\begin_layout Standard
Some of the other features of the instance and
\family typewriter
.MODEL
\family default
cards are worth noting.
Of particular interest is the portion of the
\family typewriter
.MODEL
\family default
card that specifies
\family typewriter
gain=5.0
\family default
.
This portion of the card assigns a value to a parameter of the `gain' model.
There are other parameters that can be assigned values for this model,
and in general code models will have several.
In addition to numeric values, code model parameters can take non-numeric
values (such as TRUE and FALSE), and even vector values.
All of these topics will be discussed at length in the following pages.
In general, however, the instance and
\family typewriter
.MODEL
\family default
cards that define a code model will follow the abstract form described
below.
This form illustrates that the number of inputs and outputs and the number
of parameters that can be specified is relatively open-ended and can be
interpreted in a variety of ways (note that angle-brackets `
\family typewriter
<
\family default
' and `
\family typewriter
>
\family default
' enclose optional inputs):
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
AXXXXXXX <%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d>
\end_layout
\begin_layout Plain Layout
+ <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d>
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+ <~>... >
\end_layout
\begin_layout Plain Layout
+ <%v,%i,%vd,%id,%g,%gd,%h,%hd,%d or %vnam>
\end_layout
\begin_layout Plain Layout
+ <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd,
\end_layout
\begin_layout Plain Layout
or %d>
\end_layout
\begin_layout Plain Layout
+ <~>...>
\end_layout
\begin_layout Plain Layout
+ MODELNAME
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.MODEL MODELNAME MODELTYPE
\end_layout
\begin_layout Plain Layout
+ <( PARAMNAME1= <[> VAL1 > PARAMNAME2..>)>
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Square brackets ([ ]) are used to enclose vector input nodes.
In addition, these brackets are used to delineate vectors of parameters.
\end_layout
\begin_layout Standard
The literal string `null', when included in a node list, is interpreted
as no connection at that input to the model.
`Null' is not allowed as the name of a model's input or output if the model
only has one input or one output.
Also, `null' should only be used to indicate a missing connection for a
code model; use on other XSPICE component is not interpreted as a missing
connection, but will be interpreted as an actual node name.
\end_layout
\begin_layout Standard
The tilde, `
\family typewriter
~
\family default
', when prepended to a digital node name, specifies that the logical value
of that node be inverted prior to being passed to the code model.
This allows for simple inversion of input and output polarities of a digital
model in order to handle logically equivalent cases and others that frequently
arise in digital system design.
The following example defines a NAND gate, one input of which is inverted:
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
a1 [~1 2] 3 nand1
\end_layout
\begin_layout Plain Layout
.model nand1 d_nand (rise_delay=0.1 fall_delay=0.2)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The optional symbols %v, %i, %vd, etc.
specify the type of port the simulator is to expect for the subsequent
port or port vector.
The meaning of each symbol is given in Table
\begin_inset CommandInset ref
LatexCommand ref
reference "cap:Port-Type-Modifiers"
\end_inset
.
\end_layout
\begin_layout Standard
\begin_inset Float table
wide false
sideways false
status open
\begin_layout Plain Layout
\begin_inset Tabular
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
Port Type Modifiers
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Modifier
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
Interpretation
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%v
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a single-ended voltage port - one node name or number is expected
for each port.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%i
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a single-ended current port - one node name or number
\family default
\series default
\shape default
\size default
\emph default
\bar default
\noun default
\color inherit
is expected for each port.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%g
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a single-ended voltage-input, current-output (VCCS) port - one
node name or number is expected for each port.
This type of port is automatically an input/output.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%h
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a single-ended current-input, voltage-output (CCVS) port - one
node name or number is expected for each port.
This type of port is automatically an input/output.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%d
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a digital port - one node name or number is expected for each
port.
This type of port may be either an input or an output.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%vnam
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents the name of a voltage source, the current through which is taken
as an input.
This notation is provided primarily in order to allow models defined using
SPICE2G6 syntax to operate properly in XSPICE.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%vd
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a differential voltage port - two node names or numbers are expected
for each port.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%id
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a differential current port - two node names or numbers are expected
for each port.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%gd
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a differential VCCS port - two node names or numbers are expected
for each port.
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
%hd
\end_layout
\end_inset
|
\begin_inset Text
\begin_layout Plain Layout
\family roman
\series medium
\shape up
\size normal
\emph off
\bar no
\noun off
\color none
represents a differential CCVS port - two node names or numbers
\family default
\series default
\shape default
\size default
\emph default
\bar default
\noun default
\color inherit
are expected for each port.
\end_layout
\end_inset
|
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
\begin_inset CommandInset label
LatexCommand label
name "cap:Port-Type-Modifiers"
\end_inset
Port Type Modifiers
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The symbols described in Table
\begin_inset CommandInset ref
LatexCommand ref
reference "cap:Port-Type-Modifiers"
\end_inset
may be omitted if the default port type for the model is desired.
Note that non-default port types for multi-input or multi-output (vector)
ports must be specified by placing one of the symbols in front of EACH
vector port.
On the other hand, if all ports of a vector port are to be declared as
having the same non-default type, then a symbol may be specified immediately
prior to the opening bracket of the vector.
The following examples should make this clear:
\end_layout
\begin_layout LyX-Code
Example 1: - Specifies two differential voltage connections, one
\end_layout
\begin_layout LyX-Code
to nodes 1 & 2, and one to nodes 3 & 4.
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace defskip
\end_inset
\end_layout
\begin_layout LyX-Code
%vd [1 2 3 4]
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout LyX-Code
Example 2: - Specifies two single-ended connections to node 1 and
\end_layout
\begin_layout LyX-Code
at node 2, and one differential connection to
\end_layout
\begin_layout LyX-Code
nodes 3 & 4.
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace defskip
\end_inset
\end_layout
\begin_layout LyX-Code
%v [1 2 %vd 3 4]
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout LyX-Code
Example 3: - Identical to the previous example...parenthesis
\end_layout
\begin_layout LyX-Code
are added for additional clarity.
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace defskip
\end_inset
\end_layout
\begin_layout LyX-Code
%v [1 2 %vd(3 4)]
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout LyX-Code
Example 4: - Specifies that the node numbers are to be treated in the
\end_layout
\begin_layout LyX-Code
default fashion for the particular model.
\end_layout
\begin_layout LyX-Code
If this model had `%v'' as a default for this
\end_layout
\begin_layout LyX-Code
port, then this notation would represent four single-ended
\end_layout
\begin_layout LyX-Code
voltage connections.
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace defskip
\end_inset
\end_layout
\begin_layout LyX-Code
[1 2 3 4]
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout Standard
The parameter names listed on the
\family typewriter
.MODEL
\family default
card must be identical to those named in the code model itself.
The parameters for each predefined code model are described in detail in
Sections
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:XSPICE-Analog-Models"
\end_inset
(analog),
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:XSPICE-Hybrid-Models"
\end_inset
(Hybrid, A/D) and
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:XSPICE-Digital-Models"
\end_inset
(digital) .
The steps required in order to specify parameters for user-defined models
are described in Chapter
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Code-Models-and"
\end_inset
.
\end_layout
\begin_layout Subsection
Examples
\end_layout
\begin_layout Standard
The following is a list of instance card and associated
\family typewriter
.MODEL
\family default
card examples showing use of predefined models within an XSPICE deck:
\end_layout
\begin_layout LyX-Code
a1 1 2 amp
\end_layout
\begin_layout LyX-Code
.model amp gain(in_offset=0.1 gain=5.0 out_offset=-0.01)
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout LyX-Code
a2 %i[1 2] 3 sum1
\end_layout
\begin_layout LyX-Code
.model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0]
\end_layout
\begin_layout LyX-Code
+ out_gain=5.0 out_offset=-0.01)
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout LyX-Code
a21 %i[1 %vd(2 5) 7 10] 3 sum2
\end_layout
\begin_layout LyX-Code
.model sum2 summer(out_gain=10.0)
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout LyX-Code
a5 1 2 limit5
\end_layout
\begin_layout LyX-Code
.model limit5 limit(in_offset=0.1 gain=2.5
\end_layout
\begin_layout LyX-Code
+ out_lower.limit=-5.0 out_upper_limit=5.0 limit_domain=0.10
\end_layout
\begin_layout LyX-Code
+ fraction=FALSE)
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout LyX-Code
a7 2 %id(4 7) xfer.cntl1
\end_layout
\begin_layout LyX-Code
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
\end_layout
\begin_layout LyX-Code
+ y_array=[-0.2 -0.2 0.1 2.0 10.0]
\end_layout
\begin_layout LyX-Code
+ input_domain=0.05 fraction=TRUE)
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout LyX-Code
a8 3 %gd(6 7) switch3
\end_layout
\begin_layout LyX-Code
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
\end_layout
\begin_layout LyX-Code
+ r_on=10.0 log=TRUE)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Search-path-for"
\end_inset
Search path for file input
\end_layout
\begin_layout Standard
Several code models (
\family typewriter
filesource
\family default
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Filesource"
\end_inset
,
\family typewriter
d_source
\family default
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Digital-Source"
\end_inset
,
\family typewriter
d_state
\family default
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:State-Machine"
\end_inset
) call additional files for supply of input data.
A call to
\family typewriter
file="path/filename"
\family default
(or input_file=, state_file=) in the
\family typewriter
.model
\family default
card will start a search sequence for finding the file.
\family typewriter
path
\family default
may be an absolute path.
If
\family typewriter
path
\family default
is omitted or is a relative path,
\family typewriter
filename
\family default
is looked for according to the following search list:
\end_layout
\begin_layout Labeling
\labelwidthstring 00.00.0000
\family typewriter
Infile_Path/
\family default
(Infile_Path is the path of the input file
\family sans
*.sp
\family default
containing the netlist)
\end_layout
\begin_layout Labeling
\labelwidthstring 00.00.0000
\family typewriter
NGSPICE_INPUT_DIR/
\family default
(where an additional path is set by the environmental variable)
\end_layout
\begin_layout Labeling
\labelwidthstring 00.00.0000
\family typewriter
\family default
(where the search is relative to the current directory (OS dependent))
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:XSPICE-Analog-Models"
\end_inset
Analog Models
\end_layout
\begin_layout Standard
The following analog models are supplied with XSPICE.
The descriptions included consist of the model Interface Specification
File and a description of the model's operation.
This is followed by an example of a simulator-deck placement of the model,
including the
\family typewriter
.MODEL
\family default
card and the specification of all available parameters.
\end_layout
\begin_layout Subsection
Gain
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_gain
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: gain
\end_layout
\begin_layout LyX-Code
Description: "A simple gain block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector.Bounds: - -
\end_layout
\begin_layout LyX-Code
Null.Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - - -
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes yes
\end_layout
\begin_layout Description
Description: This function is a simple gain block with optional offsets
on the input and the output.
The input offset is added to the input, the sum is then multiplied by the
gain, and the result is produced by adding the output offset.
This model will operate in DC, AC, and Transient analysis modes.
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
a1 1 2 amp
\end_layout
\begin_layout Plain Layout
.model amp gain(in_offset=0.1 gain=5.0
\end_layout
\begin_layout Plain Layout
+ out_offset=-0.01)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Subsection
Summer
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_summer
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: summer
\end_layout
\begin_layout LyX-Code
Description: "A summer block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input vector" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset in_gain
\end_layout
\begin_layout LyX-Code
Description: "input offset vector" "input gain vector"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: in in
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "output gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: This function is a summer block with 2-to-N input ports.
Individual gains and offsets can be applied to each input and to the output.
Each input is added to its respective offset and then multiplied by its
gain.
The results are then summed, multiplied by the output gain and added to
the output offset.
This model will operate in DC, AC, and Transient analysis modes.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example usage:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
a2 [1 2] 3 sum1
\end_layout
\begin_layout Plain Layout
.model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0]
\end_layout
\begin_layout Plain Layout
+ out_gain=5.0 out_offset=-0.01)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Subsection
Multiplier
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_mult
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: mult
\end_layout
\begin_layout LyX-Code
Description: "multiplier block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input vector" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset in_gain
\end_layout
\begin_layout LyX-Code
Description: "input offset vector" "input gain vector"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: in in
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "output gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: This function is a multiplier block with 2-to-N input ports.
Individual gains and offsets can be applied to each input and to the output.
Each input is added to its respective offset and then multiplied by its
gain.
The results are multiplied along with the output gain and are added to
the output offset.
This model will operate in DC, AC, and Transient analysis modes.
However, in ac analysis it is important to remember that results are invalid
unless only
\emph on
one
\emph default
input of the multiplier is connected to a node that i connected to an AC
signal (this is exemplified by the use of a multiplier to perform a potentiomet
er function: one input is DC, the other carries the AC signal).
\end_layout
\begin_layout LyX-Code
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
a3 [1 2 3] 4 sigmult
\end_layout
\begin_layout Plain Layout
.model sigmult mult(in_offset=[0.1 0.1 -0.1]
\end_layout
\begin_layout Plain Layout
+ in_gain=[10.0 10.0 10.0] out_gain=5.0 out_offset=0.05)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Subsection
Divider
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_divide
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: divide
\end_layout
\begin_layout LyX-Code
Description: "divider block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: num den out
\end_layout
\begin_layout LyX-Code
Description: "numerator" "denominator" "output"
\end_layout
\begin_layout LyX-Code
Direction: in in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: num_offset num_gain
\end_layout
\begin_layout LyX-Code
Description: "numerator offset" "numerator gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: den_offset den_gain
\end_layout
\begin_layout LyX-Code
Description: "denominator offset" "denominator gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: den_lower_limit
\end_layout
\begin_layout LyX-Code
Description: "denominator lower limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-10
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: den_domain
\end_layout
\begin_layout LyX-Code
Description: "denominator smoothing domain"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-10
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fraction
\end_layout
\begin_layout LyX-Code
Description: "smoothing fraction/absolute value switch"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: false
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "output gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: This function is a two-quadrant divider.
It takes two inputs; num (numerator) and den (denominator).
Divide offsets its inputs, multiplies them by their respective gains, divides
the results, multiplies the quotient by the output gain, and offsets the
result.
The denominator is limited to a value above zero via a user specified lower
limit.
This limit is approached through a quadratic smoothing function, the domain
of which may be specified as a fraction of the lower limit value (default),
or as an absolute value.
This model will operate in DC, AC and Transient analysis modes.
However, in ac analysis it is important to remember that results are invalid
unless only
\emph on
one
\emph default
input of the divider is connected to a node that is connected to an ac
signal (this is exemplified by the use of the divider to perform a potentiomete
r function: one input is dc, the other carries the ac signal).
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 1 2 4 divider
\end_layout
\begin_layout LyX-Code
.model divider divide(num_offset=0.1 num_gain=2.5 den_offset=-0.1
\end_layout
\begin_layout LyX-Code
+ den_gain=5.0 den_lower.limit=1e-5 den_domain=1e-6
\end_layout
\begin_layout LyX-Code
+ fraction=FALSE out_gain=1.0 out_offset=0.0)
\end_layout
\begin_layout Subsection
Limiter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_limit
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: limit
\end_layout
\begin_layout LyX-Code
Description: "limit block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_lower_limit out_upper_limit
\end_layout
\begin_layout LyX-Code
Description: "output lower limit" "output upper limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: limit_range
\end_layout
\begin_layout LyX-Code
Description: "upper & lower smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-6
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fraction
\end_layout
\begin_layout LyX-Code
Description: "smoothing fraction/absolute value switch"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: FALSE
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Limiter is a single input, single output function similar
to the Gain Block.
However, the output of the Limiter function is restricted to the range
specified by the output lower and upper limits.
This model will operate in DC, AC and Transient analysis modes.
Note that the limit range is the value
\emph on
below the upper limit and above the lower limit
\emph default
at which smoothing of the output begins.
For this model, then, the limit range represents the delta
\emph on
with respect to the output level
\emph default
at which smoothing occurs.
Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the
output will begin to smooth out at
\begin_inset Formula $\pm$
\end_inset
0.9 volts, which occurs when the input value is at
\begin_inset Formula $\pm$
\end_inset
0.4.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a5 1 2 limit5
\end_layout
\begin_layout LyX-Code
.model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=-5.0
\end_layout
\begin_layout LyX-Code
+ out_upper_limit=5.0 limit_range=0.10 fraction=FALSE)
\end_layout
\begin_layout Subsection
Controlled Limiter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_climit
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: climit
\end_layout
\begin_layout LyX-Code
Description: "controlled limiter block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in cntl_upper
\end_layout
\begin_layout LyX-Code
Description: "input" "upper lim.
control input"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: cntl_lower out
\end_layout
\begin_layout LyX-Code
Description: "lower limit control input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: upper_delta lower_delta
\end_layout
\begin_layout LyX-Code
Description: "output upper delta" "output lower delta"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: limit_range fraction
\end_layout
\begin_layout LyX-Code
Description: "upper & lower sm.
range" "smoothing %/abs switch"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-6 FALSE
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The Controlled Limiter is a single input, single output function
similar to the Gain Block.
However, the output of the Limiter function is restricted to the range
specified by the output lower and upper limits.
This model will operate in DC, AC, and Transient analysis modes.
Note that the limit range is the value
\emph on
below the
\begin_inset Formula $cntl\_upper$
\end_inset
limit and above the
\begin_inset Formula $cntl\_lower$
\end_inset
limit
\emph default
at which smoothing of the output begins (minimum positive value of voltage
must exist between the
\emph on
\begin_inset Formula $cntl\_upper$
\end_inset
\emph default
input and the
\emph on
\begin_inset Formula $cntl\_lower$
\end_inset
\emph default
input at all times).
For this model, then, the limit range represents the delta
\emph on
with respect to the output level
\emph default
at which smoothing occurs.
Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the
output will begin to smooth out at
\begin_inset Formula $\pm$
\end_inset
0.9 volts, which occurs when the input value is at
\begin_inset Formula $\pm$
\end_inset
0.4.
Note also that the Controlled Limiter code tests the input values of
\begin_inset Formula $cntl\_upper$
\end_inset
and
\begin_inset Formula $cntl\_lower$
\end_inset
to make sure that they are spaced far enough apart to guarantee the existence
of a linear range between them.
The range is calculated as the difference between (
\begin_inset Formula $cntl\_upper-upper\_delta-limit\_range$
\end_inset
) and (
\begin_inset Formula $cntl\_lower+lower\_delta+limit\_range$
\end_inset
) and must be greater than or equal to zero.
Note that when the limit range is specified as a fractional value, the
limit range used in the above is taken as the calculated fraction of the
difference between
\begin_inset Formula $cntl\_upper$
\end_inset
and
\begin_inset Formula $cntl\_lower$
\end_inset
.
Still, the potential exists for too great a limit range value to be specified
for proper operation, in which case the model will return an error message.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
a6 3 6 8 4 varlimit
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0
\end_layout
\begin_layout LyX-Code
+ lower_delta=0.0 limit_range=0.10 fraction=FALSE)
\end_layout
\begin_layout Subsection
PWL Controlled Source
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_pwl
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: pwl
\end_layout
\begin_layout LyX-Code
Description: "piecewise linear controlled source"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: x_array y_array
\end_layout
\begin_layout LyX-Code
Description: "x-element array" "y-element array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] [2 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_domain fraction
\end_layout
\begin_layout LyX-Code
Description: "input sm.
domain" "smoothing %/abs switch"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 0.01 TRUE
\end_layout
\begin_layout LyX-Code
Limits: [1e-12 0.5] -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
STATIC_VAR_TABLE:
\end_layout
\begin_layout LyX-Code
Static_Var_Name: last_x_value
\end_layout
\begin_layout LyX-Code
Data_Type: pointer
\end_layout
\begin_layout LyX-Code
Description: "iteration holding variable for limiting"
\end_layout
\begin_layout Description
Description: The Piece-Wise Linear Controlled Source is a single input,
single output function similar to the Gain Block.
However, the output of the PWL Source is not necessarily linear for all
values of input.
Instead, it follows an I/O relationship specified by you via the
\family typewriter
x_array
\family default
and
\family typewriter
y_array
\family default
coordinates.
This is detailed below.
\begin_inset Newline newline
\end_inset
The
\family typewriter
x_array
\family default
and
\family typewriter
y_array
\family default
values represent vectors of coordinate points on the x and y axes, respectively.
The
\family typewriter
x_array
\family default
values are progressively increasing input coordinate points, and the associated
\family typewriter
y_array
\family default
values represent the outputs at those points.
There may be as few as two (
\family typewriter
x_array
\family default
[n],
\family typewriter
y_array
\family default
[n]) pairs specified, or as many as memory and simulation speed allow.
This permits you to very finely approximate a non-linear function by capturing
multiple input-output coordinate points.
\begin_inset Newline newline
\end_inset
Two aspects of the PWL Controlled Source warrant special attention.
These are the handling of endpoints and the smoothing of the described
transfer function near coordinate points.
\begin_inset Newline newline
\end_inset
In order to fully specify outputs for values of
\family typewriter
in
\family default
outside of the bounds of the PWL function (i.e., less than
\family typewriter
x_array
\family default
[0] or greater than
\family typewriter
x_array
\family default
[n], where n is the largest user-specified coordinate index), the PWL Controlled
Source model extends the slope found between the lowest two coordinate
pairs and the highest two coordinate pairs.
This has the effect of making the transfer function completely linear for
\family typewriter
in
\family default
less than
\family typewriter
x_array
\family default
[0] and
\family typewriter
in
\family default
greater than
\family typewriter
x_array
\family default
[n].
It also has the potentially subtle effect of unrealistically causing an
output to reach a very large or small value for large inputs.
You should thus keep in mind that the PWL Source does not inherently provide
a limiting capability.
\begin_inset Newline newline
\end_inset
In order to diminish the potential for non-convergence of simulations when
using the PWL block, a form of smoothing around the
\family typewriter
x_array
\family default
,
\family typewriter
y_array
\family default
coordinate points is necessary.
This is due to the iterative nature of the simulator and its reliance on
smooth first derivatives of transfer functions in order to arrive at a
matrix solution.
Consequently, the
\family typewriter
input_domain
\family default
and
\family typewriter
fraction
\family default
parameters are included to allow you some control over the amount and nature
of the smoothing performed.
\begin_inset Newline newline
\end_inset
\family typewriter
Fraction
\family default
is a switch that is either TRUE or FALSE.
When TRUE (the default setting), the simulator assumes that the specified
input domain value is to be interpreted as a fractional figure.
Otherwise, it is interpreted as an absolute value.
Thus, if
\family typewriter
fraction
\family default
=TRUE and
\family typewriter
input_domain=
\family default
0.10, The simulator assumes that the smoothing radius about each coordinate
point is to be set equal to 10% of the length of either the
\family typewriter
x_array
\family default
segment above each coordinate point, or the
\family typewriter
x_array
\family default
segment below each coordinate point.
The specific segment length chosen will be the smallest of these two for
each coordinate point.
\begin_inset Newline newline
\end_inset
On the other hand, if
\family typewriter
fraction
\family default
=FALSE and
\family typewriter
input
\family default
=0.10, then the simulator will begin smoothing the transfer function at 0.10
volts (or amperes) below each
\family typewriter
x_array
\family default
coordinate and will continue the smoothing process for another 0.10 volts
(or amperes) above each
\family typewriter
x_array
\family default
coordinate point.
Since the overlap of smoothing domains is not allowed, checking is done
by the model to ensure that the specified input domain value is not excessive.
\begin_inset Newline newline
\end_inset
One subtle consequence of the use of the
\family typewriter
fraction
\family default
=TRUE feature of the PWL Controlled Source is that, in certain cases, you
may inadvertently create extreme smoothing of functions by choosing inappropria
te coordinate value points.
This can be demonstrated by considering a function described by three coordinat
e pairs, such as (-1,-1), (1,1), and (2,1).
In this case, with a 10%
\family typewriter
input_domain
\family default
value specified (
\family typewriter
fraction
\family default
=TRUE,
\family typewriter
input_domain
\family default
=0.10), you would expect to see rounding occur between
\family typewriter
in
\family default
=0.9 and
\family typewriter
in
\family default
=1.1, and nowhere else.
On the other hand, if you were to specify the same function using the coordinat
e pairs (-100,-100), (1,1) and (201,1), you would find that rounding occurs
between
\family typewriter
in
\family default
=-19 and
\family typewriter
in
\family default
=21.
Clearly in the latter case the smoothing might cause an excessive divergence
from the intended linearity above and below
\family typewriter
in
\family default
=1.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a7 2 4 xfer_cntl1
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
\end_layout
\begin_layout LyX-Code
+ y_array=[-0.2 -0.2 0.1 2.0 10.0]
\end_layout
\begin_layout LyX-Code
+ input_domain=0.05 fraction=TRUE)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Filesource"
\end_inset
Filesource
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_filesource
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: filesource
\end_layout
\begin_layout LyX-Code
Description: "File Source"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Port_Name: out
\end_layout
\begin_layout LyX-Code
Description: "output"
\end_layout
\begin_layout LyX-Code
Direction: out
\end_layout
\begin_layout LyX-Code
Default_Type: v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Parameter_Name: timeoffset timescale
\end_layout
\begin_layout LyX-Code
Description: "time offset" "timescale"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Parameter_Name: timerelative amplstep
\end_layout
\begin_layout LyX-Code
Description: "relative time" "step amplitude"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean boolean
\end_layout
\begin_layout LyX-Code
Default_Value: FALSE FALSE
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Parameter_Name: amploffset amplscale
\end_layout
\begin_layout LyX-Code
Description: "ampl offset" "amplscale"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -] [1 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Parameter_Name: file
\end_layout
\begin_layout LyX-Code
Description: "file name"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "filesource.txt"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Description
Description: The File Source is similar to the Piece-Wise Linear Source,
except that the waveform data is read from a file instead of being taken
from parameter vectors.
The file format is line oriented ASCII.
`
\family typewriter
#
\family default
' and `
\family typewriter
;
\family default
' are comment characters; all characters from a comment character until
the end of the line are ignored.
Each line consists of two or more real values.
The first value is the time; subsequent values correspond to the outputs.
Values are separated by spaces.
Time values are absolute and must be monotonically increasing, unless
\family sans
timerelative
\family default
is set to TRUE, in which case the values specify the interval between two
samples and must be positive.
Waveforms may be scaled and shifted in the time dimension by setting
\family sans
timescale
\family default
and
\family sans
timeoffset
\family default
.
\begin_inset Newline newline
\end_inset
Amplitudes can also be scaled and shifted using
\family sans
amplscale
\family default
and
\family sans
amploffset
\family default
.
Amplitudes are normally interpolated between two samples, unless
\family sans
amplstep
\family default
is set to TRUE.
\begin_inset Newline newline
\end_inset
\end_layout
\begin_layout Description
Note: The file named by the parameter
\family typewriter
filename
\family default
in
\family typewriter
file=
\family default
"
\family typewriter
filename
\family default
" is sought after according to a search list described in
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Search-path-for"
\end_inset
.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a8 %vd([1 0 2 0]) filesrc
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1]
\end_layout
\begin_layout LyX-Code
+ timeoffset=0 timescale=1
\end_layout
\begin_layout LyX-Code
+ timerelative=false amplstep=false)
\end_layout
\begin_layout LyX-Code
\begin_inset VSpace 1cm
\end_inset
\end_layout
\begin_layout LyX-Code
Example input file:
\end_layout
\begin_layout LyX-Code
# name: sine.m
\end_layout
\begin_layout LyX-Code
# two output ports
\end_layout
\begin_layout LyX-Code
# column 1: time
\end_layout
\begin_layout LyX-Code
# columns 2, 3: values
\end_layout
\begin_layout LyX-Code
0 0 1
\end_layout
\begin_layout LyX-Code
3.90625e-09 0.02454122852291229 0.9996988186962042
\end_layout
\begin_layout LyX-Code
7.8125e-09 0.04906767432741801 0.9987954562051724
\end_layout
\begin_layout LyX-Code
1.171875e-08 0.07356456359966743 0.9972904566786902
\end_layout
\begin_layout LyX-Code
...
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Subsection
multi_input_pwl block
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_multi_input_pwl
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: multi_input_pwl
\end_layout
\begin_layout LyX-Code
Description: "multi_input_pwl block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input array" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: vd vd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [vd,id] [vd,id]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: x y
\end_layout
\begin_layout LyX-Code
Description: "x array" "y array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] [2 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: model
\end_layout
\begin_layout LyX-Code
Description: "model type"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "and"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: Multi-input gate voltage controlled voltage source that supports
\series bold
and
\series default
or
\series bold
or
\series default
gating.
The x's and y's represent the piecewise linear variation of output (y)
as a function of input (x).
The type of gate is selectable by the parameter
\family typewriter
model
\family default
.
In case the model is
\series bold
and
\series default
, the smallest input determines the output value (i.e.
the
\family typewriter
and
\family default
function).
In case the model is
\series bold
or
\series default
, the largest input determines the output value (i.e.
the
\family typewriter
or
\family default
function).
The inverse of these functions (i.e.
\family typewriter
nand
\family default
and
\family typewriter
nor
\family default
) is constructed by complementing the y array.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
a82 [1 0 2 0 3 0] 7 0 pwlm
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model pwlm multi_input_pwl((x=[-2.0 -1.0 2.0 4.0 5.0]
\end_layout
\begin_layout LyX-Code
+ y=[-0.2 -0.2 0.1 2.0 10.0]
\end_layout
\begin_layout LyX-Code
+ model="and")
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Subsection
Analog Switch
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_aswitch
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: aswitch
\end_layout
\begin_layout LyX-Code
Description: "analog switch"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: cntl_in out
\end_layout
\begin_layout LyX-Code
Description: "input" "resistive output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v gd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [gd]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_off cntl_on
\end_layout
\begin_layout LyX-Code
Description: "control `off' value" "control `on' value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: r_off log
\end_layout
\begin_layout LyX-Code
Description: "off resistance" "log/linear switch"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e12 TRUE
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: r_on
\end_layout
\begin_layout LyX-Code
Description: "on resistance"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Analog Switch is a resistor that varies either logarithmically
or linearly between specified values of a controlling input voltage or
current.
Note that the input is not internally limited.
Therefore, if the controlling signal exceeds the specified OFF state or
ON state value, the resistance may become excessively large or excessively
small (in the case of logarithmic dependence), or may become negative (in
the case of linear dependence).
For the experienced user, these excursions may prove valuable for modeling
certain devices, but in most cases you are advised to add limiting of the
controlling input if the possibility of excessive control value variation
exists.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
a8 3 %gd(6 7) switch3
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
\end_layout
\begin_layout LyX-Code
+ r_on=10.0 log=TRUE)
\end_layout
\begin_layout Subsection
Zener Diode
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_zener
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: zener
\end_layout
\begin_layout LyX-Code
Description: "zener diode"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: z
\end_layout
\begin_layout LyX-Code
Description: "zener"
\end_layout
\begin_layout LyX-Code
Direction: inout
\end_layout
\begin_layout LyX-Code
Default_Type: gd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [gd]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: v_breakdown i_breakdown
\end_layout
\begin_layout LyX-Code
Description: "breakdown voltage" "breakdown current"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - 2.0e-2
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-6 1.0e6] [1.0e-9 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: i_sat n_forward
\end_layout
\begin_layout LyX-Code
Description: "saturation current" "forward emission coefficient"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-15 -] [0.1 10]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: limit_switch
\end_layout
\begin_layout LyX-Code
Description: "switch for on-board limiting (convergence aid)"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: FALSE
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
STATIC_VAR_TABLE:
\end_layout
\begin_layout LyX-Code
Static_Var_Name: previous_voltage
\end_layout
\begin_layout LyX-Code
Data_Type: pointer
\end_layout
\begin_layout LyX-Code
Description: "iteration holding variable for limiting"
\end_layout
\begin_layout Description
Description: The Zener Diode models the DC characteristics of most zeners.
This model differs from the Diode/Rectifier by providing a user-defined
dynamic resistance in the reverse breakdown region.
The forward characteristic is defined by only a single point, since most
data sheets for zener diodes do not give detailed characteristics in the
forward region.
\begin_inset Newline newline
\end_inset
The first three parameters define the DC characteristics of the zener in
the breakdown region and are usually explicitly given on the data sheet.
\begin_inset Newline newline
\end_inset
The saturation current refers to the relatively constant reverse current
that is produced when the voltage across the zener is negative, but breakdown
has not been reached.
The reverse leakage current determines the slight increase in reverse current
as the voltage across the zener becomes more negative.
It is modeled as a resistance parallel to the zener with value v breakdown
/ i rev.
\begin_inset Newline newline
\end_inset
Note that the limit switch parameter engages an internal limiting function
for the zener.
This can, in some cases, prevent the simulator from converging to an unrealisti
c solution if the voltage across or current into the device is excessive.
If use of this feature fails to yield acceptable results, the convlimit
option should be tried (add the following statement to the SPICE input
deck:
\family typewriter
.options
\family default
convlimit)
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a9 3 4 vref10
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model vref10 zener(v_breakdown=10.0 i_breakdown=0.02
\end_layout
\begin_layout LyX-Code
+ r_breakdown=1.0 i_rev=1e-6 i_sat=1e-12)
\end_layout
\begin_layout Subsection
Current Limiter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_ilimit
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: ilimit
\end_layout
\begin_layout LyX-Code
Description: "current limiter block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in pos_pwr
\end_layout
\begin_layout LyX-Code
Description: "input" "positive power supply"
\end_layout
\begin_layout LyX-Code
Direction: in inout
\end_layout
\begin_layout LyX-Code
Default_Type: v g
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd] [g,gd]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: neg_pwr out
\end_layout
\begin_layout LyX-Code
Description: "negative power supply" "output"
\end_layout
\begin_layout LyX-Code
Direction: inout inout
\end_layout
\begin_layout LyX-Code
Default_Type: g g
\end_layout
\begin_layout LyX-Code
Allowed_Types: [g,gd] [g,gd]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: r_out_source r_out_sink
\end_layout
\begin_layout LyX-Code
Description: "sourcing resistance" "sinking resistance"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-9 1.0e9] [1.0e-9 1.0e9]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: i_limit_source
\end_layout
\begin_layout LyX-Code
Description: "current sourcing limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: -
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: i_limit_sink
\end_layout
\begin_layout LyX-Code
Description: "current sinking limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: -
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: v_pwr_range i_source_range
\end_layout
\begin_layout LyX-Code
Description: "upper & lower power "sourcing current
\end_layout
\begin_layout LyX-Code
supply smoothing range" smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-6 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-15 -] [1.0e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: i_sink_range
\end_layout
\begin_layout LyX-Code
Description: "sinking current smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: r_out_domain
\end_layout
\begin_layout LyX-Code
Description: "internal/external voltage delta smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Current Limiter models the behavior of an operational amplifier
or comparator device at a high level of abstraction.
All of its pins act as inputs; three of the four also act as outputs.
The model takes as input a voltage value from the
\family typewriter
in
\family default
connector.
It then applies an offset and a gain, and derives from it an equivalent
internal voltage (
\emph on
veq
\emph default
), which it limits to fall between
\family typewriter
pos_pwr
\family default
and
\family typewriter
neg_pwr
\family default
.
If
\emph on
veq
\emph default
is greater than the output voltage seen on the
\family typewriter
out
\family default
connector, a sourcing current will flow from the output pin.
Conversely, if the voltage is less than
\emph on
vout
\emph default
, a sinking current will flow into the output pin.
\begin_inset Newline newline
\end_inset
Depending on the polarity of the current flow, either a sourcing or a sinking
resistance value (
\family typewriter
r_out_source
\family default
,
\family typewriter
r_out_sink
\family default
) is applied to govern the
\family typewriter
vout/i_out
\family default
relationship.
The chosen resistance will continue to control the output current until
it reaches a maximum value specified by either
\family typewriter
i_limit_source
\family default
or
\family typewriter
i_limit_sink
\family default
.
The latter mimics the current limiting behavior of many operational amplifier
output stages.
\begin_inset Newline newline
\end_inset
During all operation, the output current is reflected either in the
\family typewriter
pos_pwr
\family default
connector current or the
\family typewriter
neg_pwr
\family default
current, depending on the polarity of
\family typewriter
i_out
\family default
.
Thus, realistic power consumption as seen in the supply rails is included
in the model.
\begin_inset Newline newline
\end_inset
The user-specified smoothing parameters relate to model operation as follows:
\family typewriter
v_pwr_range
\family default
controls the voltage below
\family typewriter
vpos_pwr
\family default
and above
\family typewriter
vneg_pwr
\family default
inputs beyond which
\begin_inset Formula $veq=gain\:(vin+v_{offset})$
\end_inset
is smoothed;
\family typewriter
i_source_range
\family default
specifies the current below
\family typewriter
i_limit_source
\family default
at which smoothing begins, as well as specifying the current increment
above
\family typewriter
i_out
\family default
=0.0 at which
\family typewriter
i_pos_pwr
\family default
begins to transition to zero;
\family typewriter
i_sink_range
\family default
serves the same purpose with respect to
\family typewriter
i_limit_sink
\family default
and
\family typewriter
i_neg_pwr
\family default
that
\family typewriter
i_source_range
\family default
serves for
\family typewriter
i_limit_source
\family default
and
\family typewriter
i_pos_pwr
\family default
;
\family typewriter
r_out_domain
\family default
specifies the incremental value above and below (
\family typewriter
veq-vout
\family default
)=0.0 at which
\family typewriter
r_out
\family default
will be set to
\family typewriter
r_out_source
\family default
and
\family typewriter
r_out_sink
\family default
, respectively.
For values of (
\family typewriter
veq-vout
\family default
) less than
\family typewriter
r_out_domain
\family default
and greater than
\family typewriter
-r_out_domain
\family default
,
\family typewriter
r_out
\family default
is interpolated smoothly between
\family typewriter
r_out_source
\family default
and
\family typewriter
r_out_sink
\family default
.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a10 3 10 20 4 amp3
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0
\end_layout
\begin_layout LyX-Code
+ r_out_sink=1.0 i_limit_source=1e-3
\end_layout
\begin_layout LyX-Code
+ i_limit_sink=10e-3 v_pwr_range=0.2
\end_layout
\begin_layout LyX-Code
+ i_source_range=1e-6 i_sink_range=1e-6
\end_layout
\begin_layout LyX-Code
+ r_out_domain=1e-6)
\end_layout
\begin_layout Subsection
Hysteresis Block
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_hyst
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: hyst
\end_layout
\begin_layout LyX-Code
Description: "hysteresis block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_low in_high
\end_layout
\begin_layout LyX-Code
Description: "input low value" "input high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: hyst out_lower_limit
\end_layout
\begin_layout LyX-Code
Description: "hysteresis" "output lower limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.1 0.0
\end_layout
\begin_layout LyX-Code
Limits: [0.0 -] -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_upper_limit input_domain
\end_layout
\begin_layout LyX-Code
Description: "output upper limit" "input smoothing domain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 0.01
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fraction
\end_layout
\begin_layout LyX-Code
Description: "smoothing fraction/absolute value switch"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: TRUE
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Hysteresis block is a simple buffer stage that provides
hysteresis of the output with respect to the input.
The in low and in high parameter values specify the center voltage or current
inputs about which the hysteresis effect operates.
The output values are limited to out lower limit and out upper limit.
The value of
\family typewriter
hyst
\family default
is added to the in low and in high points in order to specify the points
at which the slope of the hysteresis function would normally change abruptly
as the input transitions from a low to a high value.
Likewise, the value of
\family typewriter
hyst
\family default
is subtracted from the in high and in low values in order to specify the
points at which the slope of the hysteresis function would normally change
abruptly as the input transitions from a high to a low value.
In fact, the slope of the hysteresis function is never allowed to change
abruptly but is smoothly varied whenever the input domain smoothing parameter
is set greater than zero.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a11 1 2 schmitt1
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5
\end_layout
\begin_layout LyX-Code
+ out_lower_limit=0.5 out_upper_limit=3.0
\end_layout
\begin_layout LyX-Code
+ input_domain=0.01 fraction=TRUE)
\end_layout
\begin_layout Subsection
Differentiator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_dt
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_dt
\end_layout
\begin_layout LyX-Code
Description: "time-derivative block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_lower_limit out_upper_limit
\end_layout
\begin_layout LyX-Code
Description: "output lower limit" "output upper limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: limit_range
\end_layout
\begin_layout LyX-Code
Description: "upper & lower limit smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-6
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Differentiator block is a simple derivative stage that
approximates the time derivative of an input signal by calculating the
incremental slope of that signal since the previous time point.
The block also includes gain and output offset parameters to allow for
tailoring of the required signal, and output upper and lower limits to
prevent convergence errors resulting from excessively large output values.
The incremental value of output below the output upper limit and above
the output lower limit at which smoothing begins is specified via the limit
range parameter.
In AC analysis, the value returned is equal to the radian frequency of
analysis multiplied by the gain.
\begin_inset Newline newline
\end_inset
Note that since truncation error checking is not included in the d_dt block,
it is not recommended that the model be used to provide an integration
function through the use of a feedback loop.
Such an arrangement could produce erroneous results.
Instead, you should make use of the "integrate" model, which does include
truncation error checking for enhanced accuracy.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a12 7 12 slope_gen
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model slope_gen d_dt(out_offset=0.0 gain=1.0
\end_layout
\begin_layout LyX-Code
+ out_lower_limit=1e-12 out_upper_limit=1e12
\end_layout
\begin_layout LyX-Code
+ limit_range=1e-9)
\end_layout
\begin_layout Subsection
Integrator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_int
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: int
\end_layout
\begin_layout LyX-Code
Description: "time-integration block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_lower_limit out_upper_limit
\end_layout
\begin_layout LyX-Code
Description: "output lower limit" "output upper limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: limit_range
\end_layout
\begin_layout LyX-Code
Description: "upper & lower limit smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-6
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_ic
\end_layout
\begin_layout LyX-Code
Description: "output initial condition"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The Integrator block is a simple integration stage that approximate
s the integral with respect to time of an input signal.
The block also includes gain and input offset parameters to allow for tailoring
of the required signal, and output upper and lower limits to prevent convergenc
e errors resulting from excessively large output values.
Note that these limits specify integrator behavior similar to that found
in an operational amplifier-based integration stage, in that once a limit
is reached, additional storage does not occur.
Thus, the input of a negative value to an integrator that is currently
driving at the out upper limit level will immediately cause a drop in the
output, regardless of how long the integrator was previously summing positive
inputs.
The incremental value of output below the output upper limit and above
the output lower limit at which smoothing begins is specified via the limit
range parameter.
In AC analysis, the value returned is equal to the gain divided by the
radian frequency of analysis.
\begin_inset Newline newline
\end_inset
Note that truncation error checking is included in the
\family typewriter
int
\family default
block.
This should provide for a more accurate simulation of the time integration
function, since the model will inherently request smaller time increments
between simulation points if truncation errors would otherwise be excessive.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a13 7 12 time_count
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model time_count int(in_offset=0.0 gain=1.0
\end_layout
\begin_layout LyX-Code
+ out_lower_limit=-1e12 out_upper_limit=1e12
\end_layout
\begin_layout LyX-Code
+ limit_range=1e-9 out_ic=0.0)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:S-Domain-Transfer-Function"
\end_inset
S-Domain Transfer Function
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_s_xfer
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: s_xfer
\end_layout
\begin_layout LyX-Code
Description: "s-domain transfer function"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: num_coeff
\end_layout
\begin_layout LyX-Code
Description: "numerator polynomial coefficients"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: -
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: den_coeff
\end_layout
\begin_layout LyX-Code
Description: "denominator polynomial coefficients"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: -
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: int_ic
\end_layout
\begin_layout LyX-Code
Description: "integrator stage initial conditions"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: den_coeff
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: denormalized_freq
\end_layout
\begin_layout LyX-Code
Description: "denorm.
corner freq.(radians) for 1 rad/s coeffs"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The s-domain transfer function is a single input, single output
transfer function in the Laplace transform variable `
\family typewriter
s
\family default
' that allows for flexible modulation of the frequency domain characteristics
of a signal.
Ac and transient simulations are supported.
The code model may be configured to produce an arbitrary s-domain transfer
function with the following restrictions:
\end_layout
\begin_layout LyX-Code
1.
The degree of the numerator polynomial cannot exceed that
\end_layout
\begin_layout LyX-Code
of the denominator polynomial in the variable "s".
\end_layout
\begin_layout LyX-Code
2.
The coefficients for a polynomial must be stated
\end_layout
\begin_layout LyX-Code
explicitly.
That is, if a coefficient is zero, it must be
\end_layout
\begin_layout LyX-Code
included as an input to the num coeff or den coeff vector.
\end_layout
\begin_layout Standard
The order of the coefficient parameters is from that associated with the
highest-powered term decreasing to that of the lowest.
Thus, for the coefficient parameters specified below, the equation in `
\family typewriter
s
\family default
' is shown:
\end_layout
\begin_layout LyX-Code
.model filter s_xfer(gain=0.139713
\end_layout
\begin_layout LyX-Code
+ num_coeff=[1.0 0.0 0.7464102]
\end_layout
\begin_layout LyX-Code
+ den_coeff=[1.0 0.998942 0.001170077]
\end_layout
\begin_layout LyX-Code
+ int_ic=[0 0])
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
...specifies a transfer function of the form...
\end_layout
\begin_layout Standard
\align center
\begin_inset Formula $N(s)=0.139713\cdot\frac{s^{2}+0.7464102}{s^{2}+0.998942s+0.00117077}$
\end_inset
\end_layout
\begin_layout Standard
The s-domain transfer function includes
\series bold
gain
\series default
and
\series bold
in_offset
\series default
(input offset) parameters to allow for tailoring of the required signal.
There are no limits on the internal signal values or on the output value
of the s-domain transfer function, so you are cautioned to specify gain
and coefficient values that will not cause the model to produce excessively
large values.
In AC analysis, the value returned is equal to the real and imaginary component
s of the total s-domain transfer function at each frequency of interest.
\end_layout
\begin_layout Standard
The
\series bold
denormalized_freq
\series default
term allows you to specify coefficients for a normalized filter (i.e.
one in which the frequency of interest is 1 rad/s).
Once these coefficients are included, specifying the denormalized frequency
value `shifts' the corner frequency to the actual one of interest.
As an example, the following transfer function describes a Chebyshev low-pass
filter with a corner (pass-band) frequency of 1 rad/s:
\end_layout
\begin_layout Standard
\align center
\begin_inset Formula $N(s)=0.139713\cdot\frac{1.0}{s^{2}+1.09773s+1.10251}$
\end_inset
\end_layout
\begin_layout Standard
In order to define an s_xfer model for the above, but with the corner frequency
equal to 1500 rad/s (9425 Hz), the following instance and model lines would
be needed:
\end_layout
\begin_layout LyX-Code
a12 node1 node2 cheby1
\end_layout
\begin_layout LyX-Code
.model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251]
\end_layout
\begin_layout LyX-Code
+ int_ic=[0 0] denormalized_freq=1500)
\end_layout
\begin_layout Standard
In the above, you add the normalized coefficients and scale the filter through
the use of the denormalized freq parameter.
Similar results could have been achieved by performing the denormalization
prior to specification of the coefficients, and setting denormalized freq
to the value 1.0 (or not specifying the frequency, as the default is 1.0
rad/s) Note in the above that frequencies are
\emph on
always specified as radians/second
\emph default
.
\end_layout
\begin_layout Standard
Truncation error checking is included in the s-domain transfer block.
This should provide for more accurate simulations, since the model will
inherently request smaller time increments between simulation points if
truncation errors would otherwise be excessive.
\end_layout
\begin_layout Standard
The
\series bold
int_ic
\series default
parameter is an array that must be of size one less as the array of values
specified for the
\series bold
den_coeff
\series default
parameter.
Even if a 0 start value is required, you have to add the specific int_ic
vector to the set of coefficients (see the examples above and below).
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a14 9 22 cheby_LP_3kHz
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.
\end_layout
\begin_layout LyX-Code
.model cheby_LP_3kHz s_xfer(in_offset=0.0 gain=1.0 int_ic=[0 0]
\end_layout
\begin_layout LyX-Code
+ num_coeff=[1.0]
\end_layout
\begin_layout LyX-Code
+ den_coeff=[1.0 1.42562 1.51620])
\end_layout
\begin_layout Subsection
Slew Rate Block
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_slew
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: slew
\end_layout
\begin_layout LyX-Code
Description: "A simple slew rate follower block"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_slope
\end_layout
\begin_layout LyX-Code
Description: "maximum rising slope value"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e9
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fall_slope
\end_layout
\begin_layout LyX-Code
Description: "maximum falling slope value"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e9
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: range
\end_layout
\begin_layout LyX-Code
Description: "smoothing range"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.1
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a simple slew rate block that limits the absolute
slope of the output with respect to time to some maximum or value.
The actual slew rate effects of over-driving an amplifier circuit can thus
be accurately modeled by cascading the amplifier with this model.
The units used to describe the maximum rising and falling slope values
are expressed in volts or amperes per second.
Thus a desired slew rate of 0.5 V/
\begin_inset Formula $\mu s$
\end_inset
will be expressed as 0.5e+6, etc.
\begin_inset Newline newline
\end_inset
The slew rate block will continue to raise or lower its output until the
difference between the input and the output values is zero.
Thereafter, it will resume following the input signal, unless the slope
again exceeds its rise or fall slope limits.
The range input specifies a smoothing region above or below the input value.
Whenever the model is slewing and the output comes to within the input
+ or - the range value, the partial derivative of the output with respect
to the input will begin to smoothly transition from 0.0 to 1.0.
When the model is no longer slewing (output = input), dout/din will equal
1.0.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a15 1 2 slew1
\end_layout
\begin_layout LyX-Code
.model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6)
\end_layout
\begin_layout Subsection
Inductive Coupling
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_lcouple
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: lcouple
\end_layout
\begin_layout LyX-Code
Description: "inductive coupling (for use with 'core' model)"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: l mmf_out
\end_layout
\begin_layout LyX-Code
Description: "inductor" "mmf output (in ampere-turns)"
\end_layout
\begin_layout LyX-Code
Direction: inout inout
\end_layout
\begin_layout LyX-Code
Default_Type: hd hd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [h,hd] [hd]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: num_turns
\end_layout
\begin_layout LyX-Code
Description: "number of inductor turns"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a conceptual model that is used as a building
block to create a wide variety of inductive and magnetic circuit models.
This function is normally used in conjunction with the
\family typewriter
core
\family default
model, but can also be used with resistors, hysteresis blocks, etc.
to build up systems that mock the behavior of linear and nonlinear components.
\begin_inset Newline newline
\end_inset
The
\family typewriter
lcouple
\family default
takes as an input (on the `
\family typewriter
l
\family default
' port), a current.
This current value is multiplied by the
\family typewriter
num_turns
\family default
value,
\family typewriter
N
\family default
, to produce an output value (a voltage value that appears on the
\family typewriter
mmf_out
\family default
port).
The mmf_out acts similar to a magnetomotive force in a magnetic circuit;
when the lcouple is connected to the
\family typewriter
core
\family default
model, or to some other resistive device, a current will flow.
This current value (which is modulated by whatever the lcouple is connected
to) is then used by the
\family typewriter
lcouple
\family default
to calculate a voltage `seen' at the
\family typewriter
l
\family default
port.
The voltage is a function of the derivative with respect to time of the
current value seen at
\family typewriter
mmf_out
\family default
.
\begin_inset Newline newline
\end_inset
The most common use for
\family typewriter
lcouple
\family default
s will be as a building block in the construction of transformer models.
To create a transformer with a single input and a single output, you would
require two
\family typewriter
lcouple
\family default
models plus one
\family typewriter
core
\family default
model.
The process of building up such a transformer is described under the descriptio
n of the
\family typewriter
core
\family default
model, below.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
a150 (7 0) (9 10) lcouple1
\end_layout
\begin_layout LyX-Code
.model lcouple1 lcouple(num_turns=10.0)
\end_layout
\begin_layout Subsection
Magnetic Core
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_core
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: core
\end_layout
\begin_layout LyX-Code
Description: "magnetic core"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: mc
\end_layout
\begin_layout LyX-Code
Description: "magnetic core"
\end_layout
\begin_layout LyX-Code
Direction: inout
\end_layout
\begin_layout LyX-Code
Default_Type: gd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [g,gd]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: H_array B_array
\end_layout
\begin_layout LyX-Code
Description: "magnetic field array" "flux density array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] [2 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: area length
\end_layout
\begin_layout LyX-Code
Description: "cross-sectional area" "core length"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: - -
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_domain
\end_layout
\begin_layout LyX-Code
Description: "input sm.
domain"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.01
\end_layout
\begin_layout LyX-Code
Limits: [1e-12 0.5]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fraction
\end_layout
\begin_layout LyX-Code
Description: "smoothing fraction/abs switch"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: TRUE
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: mode
\end_layout
\begin_layout LyX-Code
Description: "mode switch (1 = pwl, 2 = hyst)"
\end_layout
\begin_layout LyX-Code
Data_Type: int
\end_layout
\begin_layout LyX-Code
Default_Value: 1
\end_layout
\begin_layout LyX-Code
Limits: [1 2]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_low in_high
\end_layout
\begin_layout LyX-Code
Description: "input low value" "input high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: hyst out_lower_limit
\end_layout
\begin_layout LyX-Code
Description: "hysteresis" "output lower limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.1 0.0
\end_layout
\begin_layout LyX-Code
Limits: [0 -] -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_upper_limit
\end_layout
\begin_layout LyX-Code
Description: "output upper limit"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a conceptual model that is used as a building
block to create a wide variety of inductive and magnetic circuit models.
This function is almost always expected to be used in conjunction with
the
\family typewriter
lcouple
\family default
model to build up systems that mock the behavior of linear and nonlinear
magnetic components.
There are two fundamental modes of operation for the core model.
These are the pwl mode (which is the default, and which is the most likely
to be of use to you) and the hysteresis mode.
These are detailed below.
\end_layout
\begin_layout Standard
\align center
PWL Mode (mode = 1)
\end_layout
\begin_layout Standard
The core model in PWL mode takes as input a voltage that it treats as a
magnetomotive force (mmf) value.
This value is divided by the total effective length of the core to produce
a value for the Magnetic Field Intensity, H.
This value of H is then used to find the corresponding Flux Density, B,
using the piecewise linear relationship described by you in the H array
/ B array coordinate pairs.
B is then multiplied by the cross-sectional area of the core to find the
Flux value, which is output as a current.
The pertinent mathematical equations are listed below:
\end_layout
\begin_layout Standard
\align center
H = mmf =L, where L = Length
\end_layout
\begin_layout Standard
Here H, the Magnetic Field Intensity, is expressed in ampere-turns/meter.
\end_layout
\begin_layout Standard
\align center
B = f (H)
\end_layout
\begin_layout Standard
The B value is derived from a piecewise linear transfer function described
to the model via the (H_array[],B_array[]) parameter coordinate pairs.
This transfer function does not include hysteretic effects; for that, you
would need to substitute a HYST model for the core.
\end_layout
\begin_layout Standard
\align center
\begin_inset Formula $\phi$
\end_inset
= BA, where A = Area
\end_layout
\begin_layout Standard
The final current allowed to flow through the core is equal to
\begin_inset Formula $\phi$
\end_inset
.
This value in turn is used by the "lcouple" code model to obtain a value
for the voltage reflected back across its terminals to the driving electrical
circuit.
\end_layout
\begin_layout Standard
The following example code shows the use of two
\family typewriter
lcouple
\family default
models and one core model to produce a simple primary/secondary transformer.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a1 (2 0) (3 0) primary
\end_layout
\begin_layout LyX-Code
.model primary lcouple (num_turns = 155)
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a2 (3 4) iron_core
\end_layout
\begin_layout LyX-Code
.model iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0
\end_layout
\begin_layout LyX-Code
+ 63 125 188 250 375 500 1000]
\end_layout
\begin_layout LyX-Code
+ B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3
\end_layout
\begin_layout LyX-Code
+ -1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4
\end_layout
\begin_layout LyX-Code
+ 6.25e-4 1.5e-3 1.93e-3 2.33e-3
\end_layout
\begin_layout LyX-Code
+ 2.63e-3 3.13e-3]
\end_layout
\begin_layout LyX-Code
+ area = 0.01 length = 0.01)
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a3 (5 0) (4 0) secondary
\end_layout
\begin_layout LyX-Code
.model secondary lcouple (num_turns = 310)
\end_layout
\begin_layout Standard
\align center
HYSTERESIS Mode (mode = 2)
\end_layout
\begin_layout Standard
The core model in HYSTERESIS mode takes as input a voltage that it treats
as a magnetomotive force (mmf) value.
This value is used as input to the equivalent of a hysteresis code model
block.
The parameters defining the input low and high values, the output low and
high values, and the amount of hysteresis are as in that model.
The output from this mode, as in PWL mode, is a current value that is seen
across the mc port.
An example of the core model used in this fashion is shown below:
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a1 (2 0) (3 0) primary
\end_layout
\begin_layout LyX-Code
.model primary lcouple (num_turns = 155)
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a2 (3 4) iron_core
\end_layout
\begin_layout LyX-Code
.model iron_core core (mode = 2 in_low=-7.0 in_high=7.0
\end_layout
\begin_layout LyX-Code
+ out_lower_limit=-2.5e-4 out_upper_limit=2.5e-4
\end_layout
\begin_layout LyX-Code
+ hyst = 2.3 )
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a3 (5 0) (4 0) secondary
\end_layout
\begin_layout LyX-Code
.model secondary lcouple (num_turns = 310)
\end_layout
\begin_layout Standard
\emph on
One final note to be made about the two core model nodes is that certain
parameters are available in one mode, but not in the other
\emph default
.
In particular, the in_low, in_high, out_lower_limit, out_upper_limit, and
hysteresis parameters are not available in PWL mode.
Likewise, the H_array, B_array, area, and length values are unavailable
in HYSTERESIS mode.
The input domain and fraction parameters are common to both modes (though
their behavior is somewhat different; for explanation of the input domain
and fraction values for the HYSTERESIS mode, you should refer to the hysteresis
code model discussion).
\end_layout
\begin_layout Subsection
Controlled Sine Wave Oscillator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_sine
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: sine
\end_layout
\begin_layout LyX-Code
Description: "controlled sine wave oscillator"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: cntl_in out
\end_layout
\begin_layout LyX-Code
Description: "control input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_array freq_array
\end_layout
\begin_layout LyX-Code
Description: "control array" "frequency array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0e3
\end_layout
\begin_layout LyX-Code
Limits: - [0 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] cntl_array
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_low out_high
\end_layout
\begin_layout LyX-Code
Description: "output peak low value" "output peak high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: -1.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: This function is a controlled sine wave oscillator with parametriza
ble values of low and high peak output.
It takes an input voltage or current value.
This value is used as the independent variable in the piecewise linear
curve described by the coordinate points of the cntl array and freq array
pairs.
From the curve, a frequency value is determined, and the oscillator will
output a sine wave at that frequency.
From the above, it is easy to see that array sizes of 2 for both the cntl
array and the freq array will yield a linear variation of the frequency
with respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic.
For more detail, refer to the description of the piecewise linear controlled
source, which uses a similar method to derive an output value given a control
input.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
asine 1 2 in_sine
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
.model in_sine sine(cntl_array = [-1 0 5 6]
\end_layout
\begin_layout LyX-Code
+ freq_array=[10 10 1000 1000] out_low = -5.0
\end_layout
\begin_layout LyX-Code
+ out_high = 5.0)
\end_layout
\begin_layout Subsection
Controlled Triangle Wave Oscillator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_triangle
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: triangle
\end_layout
\begin_layout LyX-Code
Description: "controlled triangle wave oscillator"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: cntl_in out
\end_layout
\begin_layout LyX-Code
Description: "control input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_array freq_array
\end_layout
\begin_layout LyX-Code
Description: "control array" "frequency array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0e3
\end_layout
\begin_layout LyX-Code
Limits: - [0 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] cntl_array
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_low out_high
\end_layout
\begin_layout LyX-Code
Description: "output peak low value" "output peak high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: -1.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: duty_cycle
\end_layout
\begin_layout LyX-Code
Description: "rise time duty cycle"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.5
\end_layout
\begin_layout LyX-Code
Limits: [1e-10 0.999999999]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a controlled triangle/ramp wave oscillator
with parametrizable values of low and high peak output and rise time duty
cycle.
It takes an input voltage or current value.
This value is used as the independent variable in the piecewise linear
curve described by the coordinate points of the cntl_array and freq_array
pairs.
\begin_inset Newline newline
\end_inset
From the curve, a frequency value is determined, and the oscillator will
output a triangle wave at that frequency.
From the above, it is easy to see that array sizes of 2 for both the cntl_array
and the freq_array will yield a linear variation of the frequency with
respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic.
For more detail, refer to the description of the piecewise linear controlled
source, which uses a similar method to derive an output value given a control
input.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
ain 1 2 ramp1
\end_layout
\begin_layout LyX-Code
.model ramp1 triangle(cntl_array = [-1 0 5 6]
\end_layout
\begin_layout LyX-Code
+ freq_array=[10 10 1000 1000] out_low = -5.0
\end_layout
\begin_layout LyX-Code
+ out_high = 5.0 duty_cycle = 0.9)
\end_layout
\begin_layout Subsection
Controlled Square Wave Oscillator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_square
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: square
\end_layout
\begin_layout LyX-Code
Description: "controlled square wave oscillator"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: cntl_in out
\end_layout
\begin_layout LyX-Code
Description: "control input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_array freq_array
\end_layout
\begin_layout LyX-Code
Description: "control array" "frequency array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0e3
\end_layout
\begin_layout LyX-Code
Limits: - [0 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] cntl_array
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_low out_high
\end_layout
\begin_layout LyX-Code
Description: "output peak low value" "output peak high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: -1.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER.TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: duty_cycle rise_time
\end_layout
\begin_layout LyX-Code
Description: "duty cycle" "output rise time"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.5 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1e-6 0.999999] -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fall_time
\end_layout
\begin_layout LyX-Code
Description: "output fall time"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a controlled square wave oscillator with parametri
zable values of low and high peak output, duty cycle, rise time, and fall
time.
It takes an input voltage or current value.
This value is used as the independent variable in the piecewise linear
curve described by the coordinate points of the cntl_array and freq_array
pairs.
From the curve, a frequency value is determined, and the oscillator will
output a square wave at that frequency.
\begin_inset Newline newline
\end_inset
From the above, it is easy to see that array sizes of 2 for both the cntl_array
and the freq_array will yield a linear variation of the frequency with
respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic.
For more detail, refer to the description of the piecewise linear controlled
source, which uses a similar method to derive an output value given a control
input.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
ain 1 2 pulse1
\end_layout
\begin_layout LyX-Code
.model pulse1 square(cntl_array = [-1 0 5 6]
\end_layout
\begin_layout LyX-Code
+ freq_array=[10 10 1000 1000] out_low = 0.0
\end_layout
\begin_layout LyX-Code
+ out_high = 4.5 duty_cycle = 0.2
\end_layout
\begin_layout LyX-Code
+ rise_time = 1e-6 fall_time = 2e-6)
\end_layout
\begin_layout Subsection
Controlled One-Shot
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_oneshot
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: oneshot
\end_layout
\begin_layout LyX-Code
Description: "controlled one-shot"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: clk cntl_in
\end_layout
\begin_layout LyX-Code
Description: "clock input" "control input"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: clear out
\end_layout
\begin_layout LyX-Code
Description: "clear signal" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_trig retrig
\end_layout
\begin_layout LyX-Code
Description: "clock trigger value" "retrigger switch"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 0.5 FALSE
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: pos_edge_trig
\end_layout
\begin_layout LyX-Code
Description: "positive/negative edge trigger switch"
\end_layout
\begin_layout LyX-Code
Data_Type: boolean
\end_layout
\begin_layout LyX-Code
Default_Value: TRUE
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_array pw_array
\end_layout
\begin_layout LyX-Code
Description: "control array" "pulse width array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0e-6
\end_layout
\begin_layout LyX-Code
Limits: - [0.00 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - cntl_array
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_low out_high
\end_layout
\begin_layout LyX-Code
Description: "output low value" "output high value"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fall_time rise_time
\end_layout
\begin_layout LyX-Code
Description: "output fall time" "output rise time"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay
\end_layout
\begin_layout LyX-Code
Description: "output delay from trigger"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: fall_delay
\end_layout
\begin_layout LyX-Code
Description: "output delay from pw"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: This function is a controlled oneshot with parametrizable values
of low and high peak output, input trigger value level, delay, and output
rise and fall times.
It takes an input voltage or current value.
This value is used as the independent variable in the piecewise linear
curve described by the coordinate points of the cntl_array and pw_array
pairs.
From the curve, a pulse width value is determined.
The one-shot will output a pulse of that width, triggered by the clock
signal (rising or falling edge), delayed by the delay value, and with specified
rise and fall times.
A positive slope on the clear input will immediately terminate the pulse,
which resets with its fall time.
\begin_inset Newline newline
\end_inset
From the above, it is easy to see that array sizes of 2 for both the cntl_array
and the pw_array will yield a linear variation of the pulse width with
respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic.
For more detail, refer to the description of the piecewise linear controlled
source, which uses a similar method to derive an output value given a control
input.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
ain 1 2 3 4 pulse2
\end_layout
\begin_layout LyX-Code
.model pulse2 oneshot(cntl_array = [-1 0 10 11]
\end_layout
\begin_layout LyX-Code
+ pw_array=[1e-6 1e-6 1e-4 1e-4]
\end_layout
\begin_layout LyX-Code
+ clk_trig = 0.9 pos_edge_trig = FALSE
\end_layout
\begin_layout LyX-Code
+ out_low = 0.0 out_high = 4.5
\end_layout
\begin_layout LyX-Code
+ rise_delay = 20.0-9 fall_delay = 35.0e-9)
\end_layout
\begin_layout Subsection
Capacitance Meter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_cmeter
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: cmeter
\end_layout
\begin_layout LyX-Code
Description: "capacitance meter"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: gain
\end_layout
\begin_layout LyX-Code
Description: "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The capacitance meter is a sensing device that is attached
to a circuit node and produces as an output a scaled value equal to the
total capacitance seen on its input multiplied by the gain parameter.
This model is primarily intended as a building block for other models that
must sense a capacitance value and alter their behavior based upon it.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
atest1 1 2 ctest
\end_layout
\begin_layout LyX-Code
.model ctest cmeter(gain=1.0e12)
\end_layout
\begin_layout Subsection
Inductance Meter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_lmeter
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: lmeter
\end_layout
\begin_layout LyX-Code
Description: "inductance meter"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: gain
\end_layout
\begin_layout LyX-Code
Description: "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The inductance meter is a sensing device that is attached to
a circuit node and produces as an output a scaled value equal to the total
inductance seen on its input multiplied by the gain parameter.
This model is primarily intended as a building block for other models that
must sense an inductance value and alter their behavior based upon it.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
atest2 1 2 ltest
\end_layout
\begin_layout LyX-Code
.model ltest lmeter(gain=1.0e6)
\end_layout
\begin_layout Subsection
Memristor
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_memristor
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: memristor
\end_layout
\begin_layout LyX-Code
Description: "Memristor Interface"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: memris
\end_layout
\begin_layout LyX-Code
Description: "memristor terminals"
\end_layout
\begin_layout LyX-Code
Direction: inout
\end_layout
\begin_layout LyX-Code
Default_Type: gd
\end_layout
\begin_layout LyX-Code
Allowed_Types: [gd]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rmin rmax
\end_layout
\begin_layout LyX-Code
Description: "minimum resistance" "maximum resistance"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 10.0 10000.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rinit vt
\end_layout
\begin_layout LyX-Code
Description: "initial resistance" "threshold"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 7000.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: alpha beta
\end_layout
\begin_layout LyX-Code
Description: "model parameter 1" "model parameter 2"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Description
Description: The memristor is a two-terminal resistor with memory, whose
resistance depends on the time integral of the voltage across its terminals.
rmin and rmax provide the lower and upper limits of the resistance, rinit
is its starting value (no voltage applied so far).
The voltage has to be above a threshold vt to become effective in changing
the resistance.
alpha and beta are two model parameters.
The memristor code model is derived from a SPICE subcircuit published in
\begin_inset CommandInset citation
LatexCommand cite
key "key-23"
\end_inset
.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
amen 1 2 memr
\end_layout
\begin_layout LyX-Code
.model memr memristor (rmin=1k rmax=10k rinit=7k
\end_layout
\begin_layout LyX-Code
+ alpha=0 beta=2e13 vt=1.6)
\end_layout
\begin_layout Subsection
2D table model
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_table2D
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: table2D
\end_layout
\begin_layout LyX-Code
Description: "2D table model"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: inx iny out
\end_layout
\begin_layout LyX-Code
Description: "inputx" "inputy" "output"
\end_layout
\begin_layout LyX-Code
Direction: in in out
\end_layout
\begin_layout LyX-Code
Default_Type: v v i
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: order verbose
\end_layout
\begin_layout LyX-Code
Description: "order" "verbose"
\end_layout
\begin_layout LyX-Code
Data_Type: int int
\end_layout
\begin_layout LyX-Code
Default_Value: 3 0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: offset gain
\end_layout
\begin_layout LyX-Code
Description: "offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: file
\end_layout
\begin_layout LyX-Code
Description: "file name"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "2D-table-model.txt"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Description
Description: The 2D table model reads a matrix from file "
\family typewriter
file name
\family default
" (default 2D-table-model.txt) which has x columns and y rows.
Each x,y pair, addressed by inx and iny, yields an output value
\family typewriter
out
\family default
.
Linear interpolation is used for
\family typewriter
out
\family default
, eno (essentially non oscillating) interpolation for its derivatives.
Parameters
\family typewriter
offset
\family default
(default 0) and
\family typewriter
gain
\family default
(default 1) modify the output table values according to
\begin_inset Formula $offset+gain\;out$
\end_inset
.
Parameter
\family typewriter
order
\family default
(default 3) influences the calculation of the derivatives.
Parameter
\family typewriter
verbose
\family default
(default 0) yields test outputs, if set to 1 or 2.
The table format is shown below.
Be careful to include the data point inx = 0, iny = 0 into your table,
because ngspice uses these during
\family typewriter
.OP
\family default
computations.
The x horizontal and y vertical address values have to increase monotonically.
The usage example consists of two input voltages referenced to ground and
a current source output with two floating nodes.
\end_layout
\begin_layout LyX-Code
Table Example:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* table source
\end_layout
\begin_layout LyX-Code
* number of columns (x)
\end_layout
\begin_layout LyX-Code
8
\end_layout
\begin_layout LyX-Code
* number of rows (y)
\end_layout
\begin_layout LyX-Code
9
\end_layout
\begin_layout LyX-Code
* x horizontal (column) address values (real numbers)
\end_layout
\begin_layout LyX-Code
-1 0 1 2 3 4 5 6
\end_layout
\begin_layout LyX-Code
* y vertical (row) address values (real numbers)
\end_layout
\begin_layout LyX-Code
-0.6 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2
\end_layout
\begin_layout LyX-Code
* table with output data (horizontally addressed by x, vertically by y)
\end_layout
\begin_layout LyX-Code
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
\end_layout
\begin_layout LyX-Code
1 1 1 1 1 1 1 1
\end_layout
\begin_layout LyX-Code
1 1.2 1.4 1.6 1.8 2 2.2 2.4
\end_layout
\begin_layout LyX-Code
1 1.5 2 2.5 3 3.5 4 4.5
\end_layout
\begin_layout LyX-Code
1 2 3 4 5 6 7 8
\end_layout
\begin_layout LyX-Code
1 2.5 4 5.5 7 8.5 10 11.5
\end_layout
\begin_layout LyX-Code
1 3 5 7 9 11 13 15
\end_layout
\begin_layout LyX-Code
1 3.5 6 8.5 11 13.5 16 18.5
\end_layout
\begin_layout LyX-Code
1 4 7 10 13 16 19 22
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
atab inx iny %id(out1 out2) tabmod
\end_layout
\begin_layout LyX-Code
.model tabmod table2d (offset=0.0 gain=1 order=3 file="table-simple.txt")
\end_layout
\begin_layout Subsection
3D table model
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_table3D
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: table3D
\end_layout
\begin_layout LyX-Code
Description: "3D table model"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: inx iny inz
\end_layout
\begin_layout LyX-Code
Description: "inputx" "inputy" "inputz"
\end_layout
\begin_layout LyX-Code
Direction: in in in
\end_layout
\begin_layout LyX-Code
Default_Type: v v v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id,vnam]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: out
\end_layout
\begin_layout LyX-Code
Description: "output"
\end_layout
\begin_layout LyX-Code
Direction: out
\end_layout
\begin_layout LyX-Code
Default_Type: i
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: order verbose
\end_layout
\begin_layout LyX-Code
Description: "order" "verbose"
\end_layout
\begin_layout LyX-Code
Data_Type: int int
\end_layout
\begin_layout LyX-Code
Default_Value: 3 0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: offset gain
\end_layout
\begin_layout LyX-Code
Description: "offset" "gain"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: file
\end_layout
\begin_layout LyX-Code
Description: "file name"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "3D-table-model.txt"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Description
Description: The 3D table model reads a matrix from file
\family typewriter
"file name"
\family default
(default 3D-table-model.txt) which has x columns, y rows per table and z
tables.
Each x,y,z triple, addressed by inx, iny, and inz, yields an output value
\family typewriter
out
\family default
.
Linear interpolation is used for
\family typewriter
out
\family default
, eno (essentially non oscillating) interpolation for its derivatives.
Parameters
\family typewriter
offset
\family default
(default 0) and
\family typewriter
gain
\family default
(default 1) modify the output table values according to
\begin_inset Formula $offset+gain\;out$
\end_inset
.
Parameter
\family typewriter
order
\family default
(default 3) influences the calculation of the derivatives.
Parameter
\family typewriter
verbose
\family default
(default 0) yields test outputs, if set to 1 or 2.
The table format is shown below.
Be careful to include the data point inx = 0, iny = 0, inz = 0 into your
table, because ngspice needs these to for the
\family typewriter
.OP
\family default
calculation.
The x horizontal, y vertical, and z table address values have to increase
monotonically.
The usage example simulates a NMOS transistor with independent drain, gate
and bulk nodes, referenced to source.
Parameter
\emph on
gain
\emph default
may be used to emulate transistor width, with respect to the table transistor.
\end_layout
\begin_layout LyX-Code
Table Example:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* 3D table for nmos bsim 4, W=10um, L=0.13um
\end_layout
\begin_layout LyX-Code
*x
\end_layout
\begin_layout LyX-Code
39
\end_layout
\begin_layout LyX-Code
*y
\end_layout
\begin_layout LyX-Code
39
\end_layout
\begin_layout LyX-Code
*z
\end_layout
\begin_layout LyX-Code
11
\end_layout
\begin_layout LyX-Code
*x (drain voltage)
\end_layout
\begin_layout LyX-Code
-0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 ...
\end_layout
\begin_layout LyX-Code
*y (gate voltage)
\end_layout
\begin_layout LyX-Code
-0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 ...
\end_layout
\begin_layout LyX-Code
*z (substrate voltage)
\end_layout
\begin_layout LyX-Code
-1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2
\end_layout
\begin_layout LyX-Code
*table -1.8
\end_layout
\begin_layout LyX-Code
-4.50688E-10 -4.50613E-10 -4.50601E-10 -4.50599E-10 ...
\end_layout
\begin_layout LyX-Code
-4.49622E-10 -4.49267E-10 -4.4921E-10 -4.49202E-10 ...
\end_layout
\begin_layout LyX-Code
-4.50672E-10 -4.49099E-10 -4.48838E-10 -4.48795E-10 ...
\end_layout
\begin_layout LyX-Code
-4.55575E-10 -4.4953E-10 -4.48435E-10 -4.48217E-10 ...
\end_layout
\begin_layout LyX-Code
...
\end_layout
\begin_layout LyX-Code
*table -1.6
\end_layout
\begin_layout LyX-Code
-3.10015E-10 -3.09767E-10 -3.0973E-10 -3.09724E-10 ...
\end_layout
\begin_layout LyX-Code
-3.09748E-10 -3.08524E-10 -3.08339E-10 -3.08312E-10 ...
\end_layout
\begin_layout LyX-Code
...
\end_layout
\begin_layout LyX-Code
*table -1.4
\end_layout
\begin_layout LyX-Code
-2.04848E-10 -2.04008E-10 -2.03882E-10 ...
\end_layout
\begin_layout LyX-Code
-2.07275E-10 -2.03117E-10 -2.02491E-10 ...
\end_layout
\begin_layout LyX-Code
...
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
amos1 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable1
\end_layout
\begin_layout LyX-Code
.model mostable1 table3d (offset=0.0 gain=0.5 order=3
\end_layout
\begin_layout LyX-Code
+ verbose=1 file="table-3D-bsim4n.txt")
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:XSPICE-Hybrid-Models"
\end_inset
Hybrid Models
\end_layout
\begin_layout Standard
The following hybrid models are supplied with XSPICE.
The descriptions included below consist of the model Interface Specification
File and a description of the model's operation.
This is followed by an example of a simulator-deck placement of the model,
including the
\family typewriter
.MODEL
\family default
card and the specification of all available parameters.
\end_layout
\begin_layout Standard
A note should be made with respect to the use of hybrid models for other
than simple digital-to-analog and analog-to-digital translations.
The hybrid models represented in this section address that specific need,
but in the development of user-defined nodes you may find a need to translate
not only between digital and analog nodes, but also between real and digital,
real and int, etc.
In most cases such translations will not need to be as involved or as detailed
as shown in the following.
\end_layout
\begin_layout Subsection
Digital-to-Analog Node Bridge
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_dac_bridge
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: dac_bridge
\end_layout
\begin_layout LyX-Code
Description: "digital-to-analog node bridge"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [v,vd,i,id,d]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_low
\end_layout
\begin_layout LyX-Code
Description: "0-valued analog output"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_high
\end_layout
\begin_layout LyX-Code
Description: "1-valued analog output"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: out_undef input_load
\end_layout
\begin_layout LyX-Code
Description: "U-valued analog output" "input load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.5 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: t_rise t_fall
\end_layout
\begin_layout LyX-Code
Description: "rise time 0->1" "fall time 1->0"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The
\family typewriter
dac_bridge
\family default
is the first of two node bridge devices designed to allow for the ready
transfer of digital information to analog values and back again.
The second device is the
\family typewriter
adc_bridge
\family default
(which takes an analog value and maps it to a digital one).The
\family typewriter
dac_bridge
\family default
takes as input a digital value from a digital node.
This value by definition may take on only one of the values `
\family typewriter
\series medium
0
\family default
\series default
', `1' or `U'.
The
\family typewriter
dac_bridge
\family default
then outputs the value
\family typewriter
out_low
\family default
,
\family typewriter
out_high
\family default
or
\family typewriter
out_undef
\family default
, or ramps linearly toward one of these `final' values from its current
analog output level.
The speed at which this ramping occurs depends on the values of
\family typewriter
t_rise
\family default
and
\family typewriter
t_fall
\family default
.
These parameters are interpreted by the model such that the rise or fall
slope generated is always constant.
\emph on
Note that the
\family typewriter
\emph default
dac_bridge
\family default
\emph on
includes test code in its cfunc.mod file for determining the presence of
the out_undef parameter.
If this parameter is not specified by you, and if
\family typewriter
\emph default
out_high
\family default
\emph on
and
\family typewriter
\emph default
out_low
\family default
\emph on
values are specified, then out_undef is assigned the value of the arithmetic
mean of
\family typewriter
\emph default
out_high
\family default
\emph on
and
\family typewriter
\emph default
out_low
\family default
\series bold
.
\series default
This simplifies coding of output buffers, where typically a logic family
will include an
\family typewriter
out_low
\family default
and
\family typewriter
out_high
\family default
voltage, but not an
\family typewriter
out_undef
\family default
value.
This model also posts an input load value (in farads) based on the parameter
input load.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
abridge1 [7] [2] dac1
\end_layout
\begin_layout LyX-Code
.model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2
\end_layout
\begin_layout LyX-Code
+ input_load = 5.0e-12 t_rise = 50e-9
\end_layout
\begin_layout LyX-Code
+ t_fall = 20e-9)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Analog-to-Digital-Node-Bridge"
\end_inset
Analog-to-Digital Node Bridge
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_adc_bridge
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: adc_bridge
\end_layout
\begin_layout LyX-Code
Description: "analog-to-digital node bridge"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id,d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_low
\end_layout
\begin_layout LyX-Code
Description: "maximum 0-valued analog input"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_high
\end_layout
\begin_layout LyX-Code
Description: "minimum 1-valued analog input"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 2.0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The
\family typewriter
adc_bridge
\family default
is one of two node bridge devices designed to allow for the ready transfer
of analog information to digital values and back again.
The second device is the
\family typewriter
dac_bridge
\family default
(which takes a digital value and maps it to an analog one).
The
\family typewriter
adc_bridge
\family default
takes as input an analog value from an analog node.
This value by definition may be in the form of a voltage, or a current.
If the input value is less than or equal to in_low, then a digital output
value of `
\family typewriter
\series medium
0
\family default
\series default
' is generated.
If the input is greater than or equal to in_high, a digital output value
of `1' is generated.
If neither of these is true, then a digital `UNKNOWN' value is output.
Note that unlike the case of the
\family typewriter
dac_bridge
\family default
, no ramping time or delay is associated with the
\family typewriter
adc_bridge
\family default
.
Rather, the continuous ramping of the input value provides for any associated
delays in the digitized signal.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
abridge2 [1] [8] adc_buff
\end_layout
\begin_layout LyX-Code
.model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Controlled-Digital-Oscillator"
\end_inset
Controlled Digital Oscillator
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_osc
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_osc
\end_layout
\begin_layout LyX-Code
Description: "controlled digital oscillator"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: cntl_in out
\end_layout
\begin_layout LyX-Code
Description: "control input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: v d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [v,vd,i,id] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: cntl_array freq_array
\end_layout
\begin_layout LyX-Code
Description: "control array" "frequency array"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0e6
\end_layout
\begin_layout LyX-Code
Limits: - [0 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] cntl_array
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: duty_cycle init_phase
\end_layout
\begin_layout LyX-Code
Description: "duty cycle" "initial phase of output"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.5 0
\end_layout
\begin_layout LyX-Code
Limits: [1e-6 0.999999] [-180.0 +360.0]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1e-9 1e-9
\end_layout
\begin_layout LyX-Code
Limits: [0 -] [0 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital oscillator is a hybrid model that accepts as input
a voltage or current.
This input is compared to the voltage-to-frequency transfer characteristic
specified by the
\family typewriter
cntl_array/freq_array
\family default
coordinate pairs, and a frequency is obtained that represents a linear
interpolation or extrapolation based on those pairs.
A digital time-varying signal is then produced with this fundamental frequency.
\begin_inset Newline newline
\end_inset
The output waveform, which is the equivalent of a digital clock signal,
has rise and fall delays that can be specified independently.
In addition, the duty cycle and the phase of the waveform are also variable
and can be set by you.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a5 1 8 var_clock
\end_layout
\begin_layout LyX-Code
.model var_clock d_osc(cntl_array = [-2 -1 1 2]
\end_layout
\begin_layout LyX-Code
+ freq_array = [1e3 1e3 10e3 10e3]
\end_layout
\begin_layout LyX-Code
+ duty_cycle = 0.4 init_phase = 180.0
\end_layout
\begin_layout LyX-Code
+ rise_delay = 10e-9 fall_delay=8e-9)
\end_layout
\begin_layout Subsection
Node bridge from digital to real with enable
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_to_real
\end_layout
\begin_layout LyX-Code
C_Function_Name: ucm_d_to_real
\end_layout
\begin_layout LyX-Code
Description: "Node bridge from digital to real with enable"
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in enable out
\end_layout
\begin_layout LyX-Code
Description: "input" "enable" "output"
\end_layout
\begin_layout LyX-Code
Direction: in in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d real
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d] [real]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no yes no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: zero one delay
\end_layout
\begin_layout LyX-Code
Description: "value for 0" "value for 1" "delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0 1e-9
\end_layout
\begin_layout LyX-Code
Limits: - - [1e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes yes
\end_layout
\begin_layout Subsection
A Z**-1 block working on real data
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: real_delay
\end_layout
\begin_layout LyX-Code
C_Function_Name: ucm_real_delay
\end_layout
\begin_layout LyX-Code
Description: "A Z ** -1 block working on real data"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in clk out
\end_layout
\begin_layout LyX-Code
Description: "input" "clock" "output"
\end_layout
\begin_layout LyX-Code
Direction: in in out
\end_layout
\begin_layout LyX-Code
Default_Type: real d real
\end_layout
\begin_layout LyX-Code
Allowed_Types: [real] [d] [real]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: delay
\end_layout
\begin_layout LyX-Code
Description: "delay from clk to out"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1e-9
\end_layout
\begin_layout LyX-Code
Limits: [1e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Subsection
A gain block for event-driven real data
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: real_gain
\end_layout
\begin_layout LyX-Code
C_Function_Name: ucm_real_gain
\end_layout
\begin_layout LyX-Code
Description: "A gain block for event-driven real data"
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: real real
\end_layout
\begin_layout LyX-Code
Allowed_Types: [real] [real]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: in_offset gain out_offset
\end_layout
\begin_layout LyX-Code
Description: "input offset" "gain" "output offset"
\end_layout
\begin_layout LyX-Code
Data_Type: real real real
\end_layout
\begin_layout LyX-Code
Default_Value: 0.0 1.0 0.0
\end_layout
\begin_layout LyX-Code
Limits: - - -
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes yes
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay" "initial condition"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Subsection
Node bridge from real to analog voltage
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: real_to_v
\end_layout
\begin_layout LyX-Code
C_Function_Name: ucm_real_to_v
\end_layout
\begin_layout LyX-Code
Description: "Node bridge from real to analog voltage"
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: real v
\end_layout
\begin_layout LyX-Code
Allowed_Types: [real] [v, vd, i, id]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: gain transition_time
\end_layout
\begin_layout LyX-Code
Description: "gain" "output transition time"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0 1e-9
\end_layout
\begin_layout LyX-Code
Limits: - [1e-15 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:XSPICE-Digital-Models"
\end_inset
Digital Models
\end_layout
\begin_layout Standard
The following digital models are supplied with XSPICE.
The descriptions included below consist of an example model Interface Specifica
tion File and a description of the model's operation.
This is followed by an example of a simulator-deck placement of the model,
including the
\family typewriter
.MODEL
\family default
card and the specification of all available parameters.
Note that these models have not been finalized at this time.
\end_layout
\begin_layout Standard
Some information common to all digital models and/or digital nodes is included
here.
The following are general rules that should make working with digital nodes
and models more straightforward:
\end_layout
\begin_layout Enumerate
All digital nodes are initialized to ZERO at the start of a simulation (i.e.,
when INIT=TRUE).
This means that a model need not post an explicit value to an output node
upon initialization if its output would normally be a ZERO (although posting
such would certainly cause no harm).
\end_layout
\begin_layout Enumerate
Digital nodes may have one out of twelve possible node values.
See
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Digital-Node-Type"
\end_inset
for details.
\end_layout
\begin_layout Enumerate
Digital models typically have defined their rise and fall delays for their
output signals.
A capacitive input load value may be defined as well to determine a load-depend
ent delay, but is currently not used in any code model (see
\begin_inset CommandInset ref
LatexCommand ref
reference "TOTAL_LOAD(a)"
\end_inset
).
\end_layout
\begin_layout Enumerate
Several commands are available for outputting data, e.g.
eprint, edisplay, and eprvcd.
Digital inputs may be read from files.
Please see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:(Digital)-Input/Output"
\end_inset
for more details.
\end_layout
\begin_layout Enumerate
Hybrid models (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:XSPICE-Hybrid-Models"
\end_inset
) provide an interface between the digital event driven world and the analog
world of ngspice to enable true mixed mode simulation.
\end_layout
\begin_layout Subsection
Buffer
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_buffer
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_buffer
\end_layout
\begin_layout LyX-Code
Description: "digital one-bit-wide buffer"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The buffer is a single-input, single-output digital buffer
that produces as output a time-delayed copy of its input.
The delays associated with an output rise and those associated with an
output fall may be different.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a6 1 8 buff1
\end_layout
\begin_layout LyX-Code
.model buff1 d_buffer(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Inverter
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_inverter
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_inverter
\end_layout
\begin_layout LyX-Code
Description: "digital one-bit-wide inverter"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The inverter is a single-input, single-output digital inverter
that produces as output an inverted, time-delayed copy of its input.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a6 1 8 inv1
\end_layout
\begin_layout LyX-Code
.model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
And
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_and
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_and
\end_layout
\begin_layout LyX-Code
Description: "digital `and' gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
and
\family default
gate is an n-input, single-output
\family typewriter
and
\family default
gate that produces an active `
\family typewriter
1
\family default
' value if, and only if, all of its inputs are also `
\family typewriter
1
\family default
' values.
If ANY of the inputs is a `
\family typewriter
\series medium
0
\family default
\series default
', the output will also be a `
\family typewriter
0
\family default
'; if neither of these conditions holds, the output will be unknown.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a6 [1 2] 8 and1
\end_layout
\begin_layout LyX-Code
.model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Nand
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_nand
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_nand
\end_layout
\begin_layout LyX-Code
Description: "digital `nand' gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
nand
\family default
gate is an n-input, single-output
\family typewriter
nand
\family default
gate that produces an active `
\family typewriter
\series medium
0
\family default
\series default
' value if and only if all of its inputs are `
\family typewriter
\series medium
1
\family default
\series default
' values.
If ANY of the inputs is a `
\family typewriter
\series medium
0
\family default
\series default
', the output will be a `
\family typewriter
\series medium
1
\family default
\series default
'; if neither of these conditions holds, the output will be unknown.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a6 [1 2 3] 8 nand1
\end_layout
\begin_layout LyX-Code
.model nand1 d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Or
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_or
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_or
\end_layout
\begin_layout LyX-Code
Description: "digital `or' gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
or
\family default
gate is an n-input, single-output
\family typewriter
or
\family default
gate that produces an active `
\family typewriter
\series medium
1
\family default
\series default
' value if at least one of its inputs is a `
\family typewriter
\series medium
1
\family default
\series default
' value.
The gate produces a `
\family typewriter
\series medium
0
\family default
\series default
' value if all inputs are `
\family typewriter
\series medium
0
\family default
\series default
'; if neither of these two conditions holds, the output is unknown.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a6 [1 2 3] 8 or1
\end_layout
\begin_layout LyX-Code
.model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Nor
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_nor
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_nor
\end_layout
\begin_layout LyX-Code
Description: "digital `nor' gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
nor
\family default
gate is an n-input, single-output
\family typewriter
nor
\family default
gate that produces an active `
\family typewriter
\series medium
0
\family default
\series default
' value if at least one of its inputs is a `
\family typewriter
\series medium
1
\family default
\series default
' value.
The gate produces a `
\family typewriter
\series medium
0
\family default
\series default
' value if all inputs are `
\family typewriter
\series medium
0
\family default
\series default
'; if neither of these two conditions holds, the output is unknown.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
anor12 [1 2 3 4] 8 nor12
\end_layout
\begin_layout LyX-Code
.model nor12 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Xor
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_xor
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_xor
\end_layout
\begin_layout LyX-Code
Description: "digital exclusive-or gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
xor
\family default
gate is an n-input, single-output
\family typewriter
xor
\family default
gate that produces an active `
\family typewriter
\series medium
1
\family default
\series default
' value if an odd number of its inputs are also `
\family typewriter
\series medium
1
\family default
\series default
' values.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
\begin_inset Newline newline
\end_inset
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
Note also that to maintain the technology-independence of the model, any
UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a9 [1 2] 8 xor3
\end_layout
\begin_layout LyX-Code
.model xor3 d_xor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Xnor
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_xnor
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_xnor
\end_layout
\begin_layout LyX-Code
Description: "digital exclusive-nor gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [2 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital
\family typewriter
xnor
\family default
gate is an n-input, single-output
\family typewriter
xnor
\family default
gate that produces an active `
\family typewriter
\series medium
0
\family default
\series default
' value if an odd number of its inputs are also `
\family typewriter
\series medium
1
\family default
\series default
' values.
It produces a `
\family typewriter
\series medium
1
\family default
\series default
' output when an even number of `
\family typewriter
\series medium
1
\family default
\series default
' values occurs on its inputs.
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
input load.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the specified delays.
Note also that to maintain the technology-independence of the model, any
UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a9 [1 2] 8 xnor3
\end_layout
\begin_layout LyX-Code
.model xnor3 d_xnor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
\end_layout
\begin_layout LyX-Code
+ input_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Tristate
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_tristate
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_tristate
\end_layout
\begin_layout LyX-Code
Description: "digital tristate buffer"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in enable out
\end_layout
\begin_layout LyX-Code
Description: "input" "enable" "output"
\end_layout
\begin_layout LyX-Code
Direction: in in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: delay
\end_layout
\begin_layout LyX-Code
Description: "delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: enable_load
\end_layout
\begin_layout LyX-Code
Description: "enable load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital tristate is a simple tristate gate that can be
configured to allow for open-collector behavior, as well as standard tristate
behavior.
The state seen on the input line is reflected in the output.
The state seen on the enable line determines the strength of the output.
Thus, a ONE forces the output to its state with a STRONG strength.
A ZERO forces the output to go to a HI_IMPEDANCE strength.
The delays associated with an output state or strength change cannot be
specified independently, nor may they be specified independently for rise
or fall conditions; other gate models may be used to provide such delays
if needed.
The model posts input and enable load values (in farads) based on the parameter
s input load and enable.
The output of this model does
\emph on
not
\emph default
, however, respond to the total loading it sees on its output; it will always
drive the output with the specified delay.
Note also that to maintain the technology-independence of the model, any
UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
Likewise, any UNKNOWN input on the enable line causes the output to go
to an UNDETERMINED strength value.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a9 1 2 8 tri7
\end_layout
\begin_layout LyX-Code
.model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12
\end_layout
\begin_layout LyX-Code
+ enable_load = 0.5e-12)
\end_layout
\begin_layout Subsection
Pullup
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_pullup
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_pullup
\end_layout
\begin_layout LyX-Code
Description: "digital pullup resistor"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out
\end_layout
\begin_layout LyX-Code
Description: "output"
\end_layout
\begin_layout LyX-Code
Direction: out
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: load
\end_layout
\begin_layout LyX-Code
Description: "load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital pullup resistor is a device that emulates the behavior
of an analog resistance value tied to a high voltage level.
The pullup may be used in conjunction with tristate buffers to provide
open-collector wired
\family typewriter
or
\family default
constructs, or any other logical constructs that rely on a resistive pullup
common to many tristated output devices.
The model posts an input load value (in farads) based on the parameter
\family sans
load
\family default
.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a2 9 pullup1
\end_layout
\begin_layout LyX-Code
.model pullup1 d_pullup(load = 20.0e-12)
\end_layout
\begin_layout Subsection
Pulldown
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_pulldown
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_pulldown
\end_layout
\begin_layout LyX-Code
Description: "digital pulldown resistor"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out
\end_layout
\begin_layout LyX-Code
Description: "output"
\end_layout
\begin_layout LyX-Code
Direction: out
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: load
\end_layout
\begin_layout LyX-Code
Description: "load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital pulldown resistor is a device that emulates the
behavior of an analog resistance value tied to a low voltage level.
The pulldown may be used in conjunction with tristate buffers to provide
open-collector wired
\family typewriter
or
\family default
constructs, or any other logical constructs that rely on a resistive pulldown
common to many tristated output devices.
The model posts an input load value (in farads) based on the parameter
\family typewriter
load
\family default
.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 9 pulldown1
\end_layout
\begin_layout LyX-Code
.model pulldown1 d_pulldown(load = 20.0e-12)
\end_layout
\begin_layout Subsection
D Flip Flop
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_dff
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_dff
\end_layout
\begin_layout LyX-Code
Description: "digital d-type flip flop"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: data clk
\end_layout
\begin_layout LyX-Code
Description: "input data" "clock"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "asynch.
set" "asynch.
reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverted data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from clk" "delay from set"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from reset" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real int
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [0 2]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: data_load clk_load
\end_layout
\begin_layout LyX-Code
Description: "data load value (F)" "clk load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector.Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital d-type flip flop is a one-bit, edge-triggered storage
element that will store data whenever the clk input line transitions from
low to high (ZERO to ONE).
In addition, asynchronous set and reset signals exist, and each of the
three methods of changing the stored output of the d_dff have separate
load values and delays associated with them.
Additionally, you may specify separate rise and fall delay values that
are added to those specified for the input lines; these allow for more
faithful reproduction of the output characteristics of different IC fabrication
technologies.
\begin_inset Newline newline
\end_inset
Note that any UNKNOWN input on the set or reset lines immediately results
in an UNKNOWN output.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a7 1 2 3 4 5 6 flop1
\end_layout
\begin_layout LyX-Code
.model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
\end_layout
\begin_layout LyX-Code
+ fall_delay = 3e-9)
\end_layout
\begin_layout Subsection
JK Flip Flop
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_jkff
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_jkff
\end_layout
\begin_layout LyX-Code
Description: "digital jk-type flip flop"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: j k
\end_layout
\begin_layout LyX-Code
Description: "j input" "k input"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: clk
\end_layout
\begin_layout LyX-Code
Description: "clock"
\end_layout
\begin_layout LyX-Code
Direction: in
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "asynchronous set" "asynchronous reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverted data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from clk" "delay from set"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from reset" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real int
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [0 2]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: jk_load clk_load
\end_layout
\begin_layout LyX-Code
Description: "j,k load values (F)" "clk load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital jk-type flip flop is a one-bit, edge-triggered
storage element that will store data whenever the clk input line transitions
from low to high (ZERO to ONE).
In addition, asynchronous set and reset signals exist, and each of the
three methods of changing the stored output of the d_jkff have separate
load values and delays associated with them.
Additionally, you may specify separate rise and fall delay values that
are added to those specified for the input lines; these allow for more
faithful reproduction of the output characteristics of different IC fabrication
technologies.
\begin_inset Newline newline
\end_inset
Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN
automatically.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a8 1 2 3 4 5 6 7 flop2
\end_layout
\begin_layout LyX-Code
.model flop2 d_jkff(clk_delay = 13.0e-9 set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
\end_layout
\begin_layout LyX-Code
+ fall_delay = 3e-9)
\end_layout
\begin_layout Subsection
Toggle Flip Flop
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_tff
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_tff
\end_layout
\begin_layout LyX-Code
Description: "digital toggle flip flop"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: t clk
\end_layout
\begin_layout LyX-Code
Description: "toggle input" "clock"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "set" "reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT.TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverted data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from clk" "delay from set"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from reset" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real int
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [0 2]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: t_load clk_load
\end_layout
\begin_layout LyX-Code
Description: "toggle load value (F)" "clk load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default.Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital toggle-type flip flop is a one-bit, edge-triggered
storage element that will toggle its current state whenever the clk input
line transitions from low to high (ZERO to ONE).
In addition, asynchronous set and reset signals exist, and each of the
three methods of changing the stored output of the d_tff have separate
load values and delays associated with them.
Additionally, you may specify separate rise and fall delay values that
are added to those specified for the input lines; these allow for more
faithful reproduction of the output characteristics of different IC fabrication
technologies.
\begin_inset Newline newline
\end_inset
Note that any UNKNOWN inputs other than t immediately cause the output to
go UNKNOWN.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a8 2 12 4 5 6 3 flop3
\end_layout
\begin_layout LyX-Code
.model flop3 d_tff(clk_delay = 13.0e-9 set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
\end_layout
\begin_layout LyX-Code
+ fall_delay = 3e-9 t_load = 0.2e-12)
\end_layout
\begin_layout Subsection
Set-Reset Flip Flop
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_srff
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_srff
\end_layout
\begin_layout LyX-Code
Description: "digital set-reset flip flop"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: s r
\end_layout
\begin_layout LyX-Code
Description: "set input" "reset input"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: clk
\end_layout
\begin_layout LyX-Code
Description: "clock"
\end_layout
\begin_layout LyX-Code
Direction: in
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "asynchronous set" "asynchronous reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverted data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from clk" "delay from set"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from reset" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real int
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [0 2]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: sr_load clk_load
\end_layout
\begin_layout LyX-Code
Description: "set/reset loads (F)" "clk load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital sr-type flip flop is a one-bit, edge-triggered
storage element that will store data whenever the clk input line transitions
from low to high (ZERO to ONE).
The value stored (i.e., the
\family typewriter
out
\family default
value) will depend on the s and r input pin values, and will be:
\end_layout
\begin_layout LyX-Code
out=ONE if s=ONE and r=ZERO;
\end_layout
\begin_layout LyX-Code
out=ZERO if s=ZERO and r=ONE;
\end_layout
\begin_layout LyX-Code
out=previous value if s=ZERO and r=ZERO;
\end_layout
\begin_layout LyX-Code
out=UNKNOWN if s=ONE and r=ONE;
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Standard
In addition, asynchronous set and reset signals exist, and each of the three
methods of changing the stored output of the d_srff have separate load
values and delays associated with them.
You may also specify separate rise and fall delay values that are added
to those specified for the input lines; these allow for more faithful reproduct
ion of the output characteristics of different IC fabrication technologies.
\end_layout
\begin_layout Standard
Note that any UNKNOWN inputs other than s and r immediately cause the output
to go UNKNOWN.
\end_layout
\begin_layout Standard
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a8 2 12 4 5 6 3 14 flop7
\end_layout
\begin_layout LyX-Code
.model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
\end_layout
\begin_layout LyX-Code
+ fall_delay = 3e-9)
\end_layout
\begin_layout Subsection
D Latch
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_dlatch
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_dlatch
\end_layout
\begin_layout LyX-Code
Description: "digital d-type latch"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: data enable
\end_layout
\begin_layout LyX-Code
Description: "input data" "enable input"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "set" "reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverter data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: data_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from data"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: enable_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from enable" "delay from SET"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from RESET" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: data_load enable_load
\end_layout
\begin_layout LyX-Code
Description: "data load (F)" "enable load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital d-type latch is a one-bit, level-sensitive storage
element that will output the value on the data line whenever the enable
input line is high (ONE).
The value on the data line is stored (i.e., held on the out line) whenever
the enable line is low (ZERO).
\begin_inset Newline newline
\end_inset
In addition, asynchronous set and reset signals exist, and each of the four
methods of changing the stored output of the d_dlatch (i.e., data changing
with enable=ONE, enable changing to ONE from ZERO with a new value on data,
raising set and raising reset) have separate delays associated with them.
You may also specify separate rise and fall delay values that are added
to those specified for the input lines; these allow for more faithful reproduct
ion of the output characteristics of different IC fabrication technologies.
\begin_inset Newline newline
\end_inset
Note that any UNKNOWN inputs other than on the data line when enable=ZERO
immediately cause the output to go UNKNOWN.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 12 4 5 6 3 14 latch1
\end_layout
\begin_layout LyX-Code
.model latch1 d_dlatch(data_delay = 13.0e-9 enable_delay = 22.0e-9
\end_layout
\begin_layout LyX-Code
+ set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2
\end_layout
\begin_layout LyX-Code
+ rise_delay = 10.0e-9 fall_delay = 3e-9)
\end_layout
\begin_layout Subsection
Set-Reset Latch
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_srlatch
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_srlatch
\end_layout
\begin_layout LyX-Code
Description: "digital sr-type latch"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: s r
\end_layout
\begin_layout LyX-Code
Description: "set" "reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: enable
\end_layout
\begin_layout LyX-Code
Description: "enable"
\end_layout
\begin_layout LyX-Code
Direction: in
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: set reset
\end_layout
\begin_layout LyX-Code
Description: "set" "reset"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out Nout
\end_layout
\begin_layout LyX-Code
Description: "data output" "inverted data output"
\end_layout
\begin_layout LyX-Code
Direction: out out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: sr_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from s or r input change"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: enable_delay set_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from enable" "delay from SET"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_delay ic
\end_layout
\begin_layout LyX-Code
Description: "delay from RESET" "output initial state"
\end_layout
\begin_layout LyX-Code
Data_Type: real boolean
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 0
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: sr_load enable_load
\end_layout
\begin_layout LyX-Code
Description: "s & r input loads (F)" "enable load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: set_load reset_load
\end_layout
\begin_layout LyX-Code
Description: "set load value (F)" "reset load (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout Description
Description: The digital sr-type latch is a one-bit, level-sensitive storage
element that will output the value dictated by the state of the s and r
pins whenever the enable input line is high (ONE).
This value is stored (i.e., held on the out line) whenever the enable line
is low (ZERO).
The particular value chosen is as shown below:
\end_layout
\begin_layout LyX-Code
s=ZERO, r=ZERO => out=current value (i.e., not change in output)
\end_layout
\begin_layout LyX-Code
s=ZERO, r=ONE => out=ZERO
\end_layout
\begin_layout LyX-Code
s=ONE, r=ZERO => out=ONE
\end_layout
\begin_layout LyX-Code
s=ONE, r=ONE => out=UNKNOWN
\end_layout
\begin_layout Standard
Asynchronous set and reset signals exist, and each of the four methods of
changing the stored output of the d srlatch (i.e., s/r combination changing
with enable=ONE, enable changing to ONE from ZERO with an output-changing
combination of s and r, raising set and raising reset) have separate delays
associated with them.
You may also specify separate rise and fall delay values that are added
to those specified for the input lines; these allow for more faithful reproduct
ion of the output characteristics of different IC fabrication technologies.
\end_layout
\begin_layout Standard
Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO
immediately cause the output to go UNKNOWN.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 12 4 5 6 3 14 16 latch2
\end_layout
\begin_layout LyX-Code
.model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9
\end_layout
\begin_layout LyX-Code
+ set_delay = 25.0e-9
\end_layout
\begin_layout LyX-Code
+ reset_delay = 27.0e-9 ic = 2
\end_layout
\begin_layout LyX-Code
+ rise_delay = 10.0e-9 fall_delay = 3e-9)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:State-Machine"
\end_inset
State Machine
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_state
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_state
\end_layout
\begin_layout LyX-Code
Description: "digital state machine"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: in clk
\end_layout
\begin_layout LyX-Code
Description: "input" "clock"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: reset out
\end_layout
\begin_layout LyX-Code
Description: "reset" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - [1 -]
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_delay reset_delay
\end_layout
\begin_layout LyX-Code
Description: "delay from CLK" "delay from RESET"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE: Parameter_Name: state_file
\end_layout
\begin_layout LyX-Code
Description: "state transition specification file name"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "state.txt"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_state
\end_layout
\begin_layout LyX-Code
Description: "default state on RESET & at DC"
\end_layout
\begin_layout LyX-Code
Data_Type: int
\end_layout
\begin_layout LyX-Code
Default_Value: 0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input loading capacitance (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: clk_load
\end_layout
\begin_layout LyX-Code
Description: "clock loading capacitance (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: reset_load
\end_layout
\begin_layout LyX-Code
Description: "reset loading capacitance (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital state machine provides for straightforward descriptions
of clocked
\series medium
combinational
\series default
logic blocks with a variable number of inputs and outputs and with an unlimited
number of possible states.
The model can be configured to behave as virtually any type of counter
or clocked
\series medium
combinational
\series default
logic block and can be used to replace very large digital circuit schematics
with an identically functional but faster representation.
\begin_inset Newline newline
\end_inset
The d state model is configured through the use of a state definition file
(state.in) that resides in a directory of your choosing.
The file defines all states to be understood by the model, plus input bit
combinations that trigger changes in state.
An example state.in file is shown below:
\end_layout
\begin_layout LyX-Code
----------- begin file -------------
\end_layout
\begin_layout LyX-Code
* This is an example state.in file.
This file
\end_layout
\begin_layout LyX-Code
* defines a simple 2-bit counter with one input.
The
\end_layout
\begin_layout LyX-Code
* value of this input determines whether the counter counts
\end_layout
\begin_layout LyX-Code
* up (in = 1) or down (in = 0).
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
0 0s 0s 0 -> 3
\end_layout
\begin_layout LyX-Code
1 -> 1
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
1 0s 1z 0 -> 0
\end_layout
\begin_layout LyX-Code
1 -> 2
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
2 1z 0s 0 -> 1
\end_layout
\begin_layout LyX-Code
1 -> 3
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
3 1z 1z 0 -> 2
\end_layout
\begin_layout LyX-Code
3 1z 1z 1 -> 0
\end_layout
\begin_layout LyX-Code
------------------ end file ---------------
\end_layout
\begin_layout Standard
Several attributes of the above file structure should be noted.
First,
\emph on
all lines in the file must be one of four types
\emph default
.
These are:
\end_layout
\begin_layout Enumerate
A comment, beginning with a `
\family typewriter
*
\family default
' in the first column.
\end_layout
\begin_layout Enumerate
A header line, which is a complete description of the current state, the
outputs corresponding to that state, an input value, and the state that
the model will assume should that input be encountered.
The first line of a state definition must
\emph on
always
\emph default
be a header line.
\end_layout
\begin_layout Enumerate
A continuation line, which is a partial description of a state, consisting
of an input value and the state that the model will assume should that
input be encountered.
Note that continuation lines may only be used after the initial header
line definition for a state.
\end_layout
\begin_layout Enumerate
A line containing nothing but white-spaces (space, form-feed, newline, carriage
return, tab, vertical tab).
\end_layout
\begin_layout Standard
A line that is not one of the above will cause a file-loading error.
Note that in the example shown, whitespace (any combination of blanks,
tabs, commas) is used to separate values, and that the character
\family typewriter
->
\family default
is used to underline the state transition implied by the input preceding
it.
This particular character is not critical in of itself, and can be replaced
with any other character or non-broken combination of characters that you
prefer (e.g.
\family typewriter
==>
\family default
,
\family typewriter
>>
\family default
, `
\family typewriter
:
\family default
',
\family typewriter
resolves_to
\family default
, etc.)
\end_layout
\begin_layout Standard
The order of the output and input bits in the file is important; the first
column is always interpreted to refer to the `zeroth' bit of input and
output.
Thus, in the file above, the output from state 1 sets
\family typewriter
out
\family default
[0] to
\family typewriter
0s
\family default
, and
\family typewriter
out
\family default
[1] to
\family typewriter
1z
\family default
.
\end_layout
\begin_layout Standard
The state numbers need not be in any particular order, but a state definition
(which consists of the sum total of all lines that define the state, its
outputs, and all methods by which a state can be exited) must be made on
contiguous line numbers; a state definition cannot be broken into sub-blocks
and distributed randomly throughout the file.
On the other hand, the state definition can be broken up by as many comment
lines as you desire.
\end_layout
\begin_layout Standard
Header files may be used throughout the
\family sans
state.in
\family default
file, and continuation lines can be discarded completely if you so choose:
continuation lines are primarily provided as a convenience.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1
\end_layout
\begin_layout LyX-Code
.model state1 d_state(clk_delay = 13.0e-9 reset_delay = 27.0e-9
\end_layout
\begin_layout LyX-Code
+ state_file = "newstate.txt" reset_state = 2)
\end_layout
\begin_layout Description
Note: The file named by the parameter
\family typewriter
filename
\family default
in
\family typewriter
state_file=
\family default
"
\family typewriter
filename
\family default
" is sought after according to a search list described in
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Search-path-for"
\end_inset
.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Frequency-Divider"
\end_inset
Frequency Divider
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_fdiv
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_fdiv
\end_layout
\begin_layout LyX-Code
Description: "digital frequency divider"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: freq_in freq_out
\end_layout
\begin_layout LyX-Code
Description: "frequency input" "frequency output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: div_factor high_cycles
\end_layout
\begin_layout LyX-Code
Description: "divide factor" "# of cycles for high out"
\end_layout
\begin_layout LyX-Code
Data_Type: int int
\end_layout
\begin_layout LyX-Code
Default_Value: 2 1
\end_layout
\begin_layout LyX-Code
Limits: [1 -] [1 div_factor-1]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: i_count
\end_layout
\begin_layout LyX-Code
Description: "divider initial count value"
\end_layout
\begin_layout LyX-Code
Data_Type: int
\end_layout
\begin_layout LyX-Code
Default_Value: 0
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: in in
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: freq_in_load
\end_layout
\begin_layout LyX-Code
Description: "freq_in load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital frequency divider is a programmable step-down divider
that accepts an arbitrary divisor (div_factor), a duty-cycle term (high_cycles)
, and an initial count value (i_count).
The generated output is synchronized to the rising edges of the input signal.
Rise delay and fall delay on the outputs may also be specified independently.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 3 7 divider
\end_layout
\begin_layout LyX-Code
.model divider d_fdiv(div_factor = 5 high_cycles = 3
\end_layout
\begin_layout LyX-Code
+ i_count = 4 rise_delay = 23e-9
\end_layout
\begin_layout LyX-Code
+ fall_delay = 9e-9)
\end_layout
\begin_layout Subsection
RAM
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_ram
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_ram
\end_layout
\begin_layout LyX-Code
Description: "digital random-access memory"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: data_in data_out
\end_layout
\begin_layout LyX-Code
Description: "data input line(s)" "data output line(s)"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -] data_in
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: address write_en
\end_layout
\begin_layout LyX-Code
Description: "address input line(s)" "write enable line"
\end_layout
\begin_layout LyX-Code
Direction: in in
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: select
\end_layout
\begin_layout LyX-Code
Description: "chip select line(s)"
\end_layout
\begin_layout LyX-Code
Direction: in
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 16]
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: select_value
\end_layout
\begin_layout LyX-Code
Description: "decimal active value for select line comparison"
\end_layout
\begin_layout LyX-Code
Data_Type: int
\end_layout
\begin_layout LyX-Code
Default_Value: 1
\end_layout
\begin_layout LyX-Code
Limits: [0 32767]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: ic
\end_layout
\begin_layout LyX-Code
Description: "initial bit state @ dc"
\end_layout
\begin_layout LyX-Code
Data_Type: int
\end_layout
\begin_layout LyX-Code
Default_Value: 2
\end_layout
\begin_layout LyX-Code
Limits: [0 2]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: read_delay
\end_layout
\begin_layout LyX-Code
Description: "read delay from address/select/write.en active"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 100.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: data_load address_load
\end_layout
\begin_layout LyX-Code
Description: "data_in load value (F)" "addr.
load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: select_load
\end_layout
\begin_layout LyX-Code
Description: "select load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: enable_load
\end_layout
\begin_layout LyX-Code
Description: "enable line load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout Description
Description: The digital RAM is an M-wide, N-deep random access memory element
with programmable select lines, tristated data out lines, and a single
write/~read line.
The width of the RAM words (M) is set through the use of the word width
parameter.
The depth of the RAM (N) is set by the number of address lines input to
the device.
The value of N is related to the number of address input lines (P) by the
following equation:
\begin_inset Formula
\[
2^{P}=N
\]
\end_inset
There is no reset line into the device.
However, an initial value for all bits may be specified by setting the
ic parameter to either 0 or 1.
In reading a word from the ram, the read delay value is invoked, and output
will not appear until that delay has been satisfied.
Separate rise and fall delays are not supported for this device.
\begin_inset Newline newline
\end_inset
Note that UNKNOWN inputs on the address lines are not allowed during a write.
In the event that an address line does indeed go unknown during a write,
\emph on
the entire contents of the ram will be set to unknown
\emph default
.
This is in contrast to the data in lines being set to unknown during a
write; in that case, only the selected word will be corrupted, and this
is corrected once the data lines settle back to a known value.
Note that protection is added to the write en line such that extended UNKNOWN
values on that line are interpreted as ZERO values.
This is the equivalent of a read operation and will not corrupt the contents
of the RAM.
A similar mechanism exists for the select lines.
If they are unknown, then it is assumed that the chip is not selected.
\begin_inset Newline newline
\end_inset
Detailed timing-checking routines are not provided in this model, other
than for the enable delay and select delay restrictions on read operations.
You are advised, therefore, to carefully check the timing into and out
of the RAM for correct read and write cycle times, setup and hold times,
etc.
for the particular device they are attempting to model.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2
\end_layout
\begin_layout LyX-Code
.model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9)
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Digital-Source"
\end_inset
Digital Source
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_source
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_source
\end_layout
\begin_layout LyX-Code
Description: "digital signal source"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port Name: out
\end_layout
\begin_layout LyX-Code
Description: "output"
\end_layout
\begin_layout LyX-Code
Direction: out
\end_layout
\begin_layout LyX-Code
Default_Type: d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d]
\end_layout
\begin_layout LyX-Code
Vector: yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_file
\end_layout
\begin_layout LyX-Code
Description: "digital input vector filename"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "source.txt"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input loading capacitance (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout Description
Description: The digital source provides for straightforward descriptions
of digital signal vectors in a tabular format.
The model reads input from the input file and, at the times specified in
the file, generates the inputs along with the strengths listed.
The format of the input file is as shown below.
Note that comment lines are delineated through the use of a single `
\family typewriter
*
\family default
' character in the first column of a line.
This is similar to the way the SPICE program handles comments.
\end_layout
\begin_layout LyX-Code
* T c n n n .
.
.
\end_layout
\begin_layout LyX-Code
* i l o o o .
.
.
\end_layout
\begin_layout LyX-Code
* m o d d d .
.
.
\end_layout
\begin_layout LyX-Code
* e c e e e .
.
.
\end_layout
\begin_layout LyX-Code
* k a b c .
.
.
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
0.0000 Uu Uu Us Uu .
.
.
\end_layout
\begin_layout LyX-Code
1.234e-9 0s 1s 1s 0z .
.
.
\end_layout
\begin_layout LyX-Code
1.376e-9 0s 0s 1s 0z .
.
.
\end_layout
\begin_layout LyX-Code
2.5e-7 1s 0s 1s 0z .
.
.
\end_layout
\begin_layout LyX-Code
2.5006e-7 1s 1s 1s 0z .
.
.
\end_layout
\begin_layout LyX-Code
5.0e-7 0s 1s 1s 0z .
.
.
\end_layout
\begin_layout Standard
Note that in the example shown, whitespace (any combination of blanks, tabs,
commas) is used to separate the time and state/strength tokens.
The order of the input columns is important; the first column is always
interpreted to mean `time'.
The second through the N'th columns map to the
\family typewriter
out
\family default
[0] through
\family typewriter
out
\family default
[N-2] output nodes.
A non-commented line that does not contain enough tokens to completely
define all outputs for the digital source will cause an error.
Also, time values must increase monotonically or an error will result in
reading the source file.
\end_layout
\begin_layout Standard
Errors will also occur if a line exists in
\family sans
source.txt
\family default
that is neither a comment nor vector line.
The only exception to this is in the case of a line that is completely
blank; this is treated as a comment (note that such lines often occur at
the end of text within a file; ignoring these in particular prevents nuisance
errors on the part of the simulator).
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector
\end_layout
\begin_layout LyX-Code
.model input_vector d_source(input_file = "source_simple.text")
\end_layout
\begin_layout Description
Note: The file named by the parameter
\family typewriter
filename
\family default
in
\family typewriter
input_file=
\family default
"
\family typewriter
filename
\family default
" is sought after according to a search list described in
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Search-path-for"
\end_inset
.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:LUT"
\end_inset
LUT
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_lut
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_lut
\end_layout
\begin_layout LyX-Code
Description: "digital n-input look-up table gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: [1 -] -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: no no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)"
\end_layout
\begin_layout LyX-Code
Data_Type: real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: table_values
\end_layout
\begin_layout LyX-Code
Description: "lookup table values"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "0"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout Subsubsection*
Description:
\series medium
The lookup table provides a way to map any arbitrary n-input, 1-output combinati
onal logic block to XSPICE.
The inputs are mapped to the output using a string of length 2^n.
The string may contain values "0", "1" or "X", corresponding to an output
of low, high, or unknown, respectively.
The outputs are only mapped for inputs which are valid logic levels.
Any unknown bit in the input vector will always produce an unknown output.
The first character of the string
\family typewriter
table_values
\family default
corresponds to all inputs value zero, and the last (2^n) character corresponds
to all inputs value one, with the first signal in the input vector being
the least significant bit.
For example, a 2-input lookup table representing the function
\family typewriter
(A * B)
\family default
(that is,
\family typewriter
A AND B
\family default
), with input vector
\family typewriter
[A B]
\family default
can be constructed with a
\family typewriter
table_values
\family default
string of "0001"; function
\family typewriter
(~A * B)
\family default
with input vector
\family typewriter
[A B]
\family default
can be constructed with a
\family typewriter
table_values
\family default
string of "0010".
The delays associated with an output rise and those associated with an
output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter
\family typewriter
input_load
\family default
.
The output of this model does not respond to the total loading it sees
on the output; it will always drive the output strongly with the specified
delays.
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* LUT encoding 3-bit parity function
\end_layout
\begin_layout LyX-Code
a4 [1 2 3] 5 lut_pty3_1
\end_layout
\begin_layout LyX-Code
.model lut_pty3_1 d_lut(table_values = "01101001"
\end_layout
\begin_layout LyX-Code
+ input_load 2.0e-12)
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:GENLUT"
\end_inset
General LUT
\end_layout
\begin_layout LyX-Code
NAME_TABLE:
\end_layout
\begin_layout LyX-Code
C_Function_Name: cm_d_genlut
\end_layout
\begin_layout LyX-Code
Spice_Model_Name: d_genlut
\end_layout
\begin_layout LyX-Code
Description: "digital n-input x m-output look-up table gate"
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PORT_TABLE:
\end_layout
\begin_layout LyX-Code
Port_Name: in out
\end_layout
\begin_layout LyX-Code
Description: "input" "output"
\end_layout
\begin_layout LyX-Code
Direction: in out
\end_layout
\begin_layout LyX-Code
Default_Type: d d
\end_layout
\begin_layout LyX-Code
Allowed_Types: [d] [d]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no no
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: rise_delay fall_delay
\end_layout
\begin_layout LyX-Code
Description: "rise delay" "fall delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-9 1.0e-9
\end_layout
\begin_layout LyX-Code
Limits: [1.0e-12 -] [1.0e-12 -]
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: input_load input_delay
\end_layout
\begin_layout LyX-Code
Description: "input load value (F)" "input delay"
\end_layout
\begin_layout LyX-Code
Data_Type: real real
\end_layout
\begin_layout LyX-Code
Default_Value: 1.0e-12 0.0
\end_layout
\begin_layout LyX-Code
Limits: - -
\end_layout
\begin_layout LyX-Code
Vector: yes yes
\end_layout
\begin_layout LyX-Code
Vector_Bounds: - -
\end_layout
\begin_layout LyX-Code
Null_Allowed: yes yes
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
PARAMETER_TABLE:
\end_layout
\begin_layout LyX-Code
Parameter_Name: table_values
\end_layout
\begin_layout LyX-Code
Description: "lookup table values"
\end_layout
\begin_layout LyX-Code
Data_Type: string
\end_layout
\begin_layout LyX-Code
Default_Value: "0"
\end_layout
\begin_layout LyX-Code
Limits: -
\end_layout
\begin_layout LyX-Code
Vector: no
\end_layout
\begin_layout LyX-Code
Vector_Bounds: -
\end_layout
\begin_layout LyX-Code
Null_Allowed: no
\end_layout
\begin_layout Subsubsection*
Description:
\series medium
The lookup table provides a way to map any arbitrary n-input, m-output combinati
onal logic block to XSPICE.
The inputs are mapped to the output using a string of length m * (2^n).
The string may contain values "0", "1", "X", or "Z", corresponding to an
output of low, high, unknown, or high-impedance, respectively.
The outputs are only mapped for inputs which are valid logic levels.
Any unknown bit in the input vector will always produce an unknown output.
The character string is in groups of (2^n) characters, one group corresponding
to each output pin, in order.
The first character of a group in the string
\family typewriter
table_values
\family default
corresponds to all inputs value zero, and the last (2^n) character in the
group corresponds to all inputs value one, with the first signal in the
input vector being the least significant bit.
For example, a 2-input lookup table representing the function
\family typewriter
(A * B)
\family default
(that is,
\family typewriter
A AND B
\family default
), with input vector
\family typewriter
[A B]
\family default
can be constructed with a
\family typewriter
table_values
\family default
string of "0001"; function
\family typewriter
(~A * B)
\family default
with input vector
\family typewriter
[A B]
\family default
can be constructed with a "table_values" string of "0010".
The delays associated with each output pin's rise and those associated
with each output pin's fall may be specified independently.
The model also posts independent input load values per input pin (in farads)
based on the parameter
\family typewriter
input_load
\family default
.
The parameter
\family typewriter
input_delay
\family default
provides a way to specify additional delay between each input pin and the
output.
This delay is added to the rise- or fall-time of the output.
The output of this model does not respond to the total loading it sees
on the output; it will always drive the output strongly with the specified
delays.
\series default
\end_layout
\begin_layout LyX-Code
Example SPICE Usage:
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* LUT encoding 3-bit parity function
\end_layout
\begin_layout LyX-Code
a4 [1 2 3] [5] lut_pty3_1
\end_layout
\begin_layout LyX-Code
.model lut_pty3_1 d_genlut(table_values = "01101001"
\end_layout
\begin_layout LyX-Code
+ input_load [2.0e-12])
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* LUT encoding a tristate inverter function (en in out)
\end_layout
\begin_layout LyX-Code
a2 [1 2] [3] lut_triinv_1
\end_layout
\begin_layout LyX-Code
.model lut_triinv_1 d_genlut(table_values = "Z1Z0")
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout LyX-Code
* LUT encoding a half-adder function (A B Carry Sum)
\end_layout
\begin_layout LyX-Code
a8 [1 2] [3 4] lut_halfadd_1
\end_layout
\begin_layout LyX-Code
.model lut_halfadd_1 d_genlut(table_values = "00010110"
\end_layout
\begin_layout LyX-Code
+ rise_delay [ 1.5e-9 1.0e-9 ] fall_delay [ 1.5e-9 1.0e-9 ])
\end_layout
\begin_layout Section
Predefined Node Types for event driven simulation
\end_layout
\begin_layout Standard
The following pre-written node types are included with the XSPICE simulator.
These should provide you not only with valuable event-driven modeling capabilit
ies, but also with examples to use for guidance in creating new UDN (user
defined node) types.
You may access these node data by the
\family typewriter
plot
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Plot:-Plot-values"
\end_inset
) or
\family typewriter
eprint
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Eprint*:-Print-an"
\end_inset
) commands.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Digital-Node-Type"
\end_inset
Digital Node Type
\end_layout
\begin_layout Standard
The `digital' node type is directly built into the simulator.
12 digital node values are available.
They are described by a two character string (the state/strength token).
The first character (0, 1, or U) gives the state of the node (logic zero,
logic one, or unknown logic state).
The second character (s, r, z, u) gives the "strength" of the logic state
(strong, resistive, hi-impedance, or undetermined).
So these are the values we have: 0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u,
1u, Uu.
\end_layout
\begin_layout Subsection
Real Node Type
\end_layout
\begin_layout Standard
The `real' node type provides for event-driven simulation with double-precision
floating point data.
This type is useful for evaluating sampled-data filters and systems.
The type implements all optional functions for User-Defined Nodes, including
inversion and node resolution.
For inversion, the sign of the value is reversed.
For node resolution, the resultant value at a node is the sum of all values
output to that node.
The node is implemented as a user defined node in
\family sans
ngspice/src/xspice/icm/xtraevt/real
\family default
.
\end_layout
\begin_layout Subsection
Int Node Type
\end_layout
\begin_layout Standard
The `int' node type provides for event-driven simulation with integer data.
This type is useful for evaluating round-off error effects in sampled-data
systems.
The type implements all optional functions for User-Defined Nodes, including
inversion and node resolution.
For inversion, the sign of the integer value is reversed.
For node resolution, the resultant value at a node is the sum of all values
output to that node.
The node is implemented as a user defined node in
\family sans
ngspice/src/xspice/icm/xtraevt/int
\family default
.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:(Digital)-Input/Output"
\end_inset
(Digital) Input/Output
\end_layout
\begin_layout Standard
The analog code models use the standard (analog) nodes provided by ngspice
and thus are using all the commands for sourcing, storing, printing, and
plotting data.
\end_layout
\begin_layout Standard
I/O for event nodes (digital, real, int, and UDNs) is offered by the following
tools: For output you may use the
\family typewriter
plot
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Plot:-Plot-values"
\end_inset
) or
\family typewriter
eprint
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Eprint*:-Print-an"
\end_inset
) commands, as well as
\family typewriter
edisplay
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Edisplay*"
\end_inset
) and
\family typewriter
eprvcd
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Edisplay*-1"
\end_inset
).
The latter writes all node data to a
\begin_inset CommandInset href
LatexCommand href
name "VCD"
target "http://en.wikipedia.org/wiki/Value_change_dump"
\end_inset
file (a digital standard interface) that may be analysed by viewers like
\begin_inset CommandInset href
LatexCommand href
name "gtkwave"
target "http://gtkwave.sourceforge.net/"
\end_inset
.
For input, you may create a test bench with existing code models (oscillator
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Controlled-Digital-Oscillator"
\end_inset
), frequency divider (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Frequency-Divider"
\end_inset
), state machine (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:State-Machine"
\end_inset
) etc.).
Reading data from a file is offered by d_source (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Digital-Source"
\end_inset
).
Some
\begin_inset CommandInset href
LatexCommand href
name "comments and hints"
target "https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/3e193172/"
\end_inset
have been provided by Sdaau.
You may also use the analog input from file, (filesource
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Filesource"
\end_inset
) and convert its analog input to the digital type by the
\family typewriter
adc_bridge
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Analog-to-Digital-Node-Bridge"
\end_inset
).
If you want reading data from a
\begin_inset CommandInset href
LatexCommand href
name "VCD"
target "http://en.wikipedia.org/wiki/Value_change_dump"
\end_inset
file, please have a look at
\begin_inset CommandInset href
LatexCommand href
name "ngspice tips and examples forum"
target "https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/635bb14a/"
\end_inset
and apply a python script provided by Sdaau to translate the VCD data to
d_source or filesource input.
\end_layout
\begin_layout Chapter
Verilog A Device models
\end_layout
\begin_layout Section
Introduction
\end_layout
\begin_layout Standard
The ngspice-adms interface will implement extra HICUM level0 and level2
(
\begin_inset CommandInset href
LatexCommand href
name "HICUM model web page"
target "http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html"
\end_inset
), MEXTRAM(
\begin_inset CommandInset href
LatexCommand href
name "MEXTRAM model web page"
target "http://mextram.ewi.tudelft.nl/"
\end_inset
), EKV(
\begin_inset CommandInset href
LatexCommand href
name "EKV model web page"
target "http://ekv.epfl.ch/"
\end_inset
) and PSP(
\begin_inset CommandInset href
LatexCommand href
name "NXP MOS model 9 web page"
target "http://www.nxp.com/models/mos_models/model9/index.html"
\end_inset
) models written in Verilog-A behavior language.
\end_layout
\begin_layout Section
adms
\end_layout
\begin_layout Standard
To compile Verilog-A compact models into ngspice-ready C models the the
program admsXml is required.
Details of this software are described in
\begin_inset CommandInset href
LatexCommand href
name "adms home page"
target "http://mot-adms.sourceforge.net"
\end_inset
.
\end_layout
\begin_layout Section
How to integrate a Verilog-A model into ngspice
\end_layout
\begin_layout Subsection
How to setup a *.va model for ngspice
\end_layout
\begin_layout Standard
The root entry for new Verilog-A models is
\family sans
\backslash
src
\backslash
spicelib
\backslash
devices
\backslash
adms
\family default
.
Below the modelname entry the Verilog-A code should reside in folder admsva
\begin_inset Newline newline
\end_inset
(e.g.:
\family sans
ngspice
\backslash
src
\backslash
spicelib
\backslash
devices
\backslash
adms
\backslash
ekv
\backslash
admsva
\backslash
ekv.va
\family default
).
The file extension is fixed to .va.
\end_layout
\begin_layout Standard
Certain files must modified to create the interface to ngspice - see the
guideline
\family sans
README.adms
\family default
in the ngspice root.
\end_layout
\begin_layout Subsection
Adding admsXml to your build environment
\end_layout
\begin_layout Standard
To facilitate the installation of adms, a source code package has been assembled
for use with ngspice, available as a zip file for
\begin_inset CommandInset href
LatexCommand href
name "download"
target "http://ngspice.sourceforge.net/adms2/adms-svn-ngspice-src.zip"
\end_inset
.
It is based on adms source code from the subversion repository downloaded
on August 1st, 2010, and has been slightly modified (see ChangeLog).
\end_layout
\begin_layout Standard
Under OS Linux (tested with SUSE 11.2, 64 bit) you may expand the zip file
and run
\begin_inset Newline newline
\end_inset
\family typewriter
./autogen_lin.sh
\family default
, followed by '
\family typewriter
make
\family default
' and '
\family typewriter
make install
\family default
'.
\end_layout
\begin_layout Standard
Under OS CYGWIN (tested with actual CYGWIN on MS Windows 7, 64 bit), please
use
\family typewriter
./autogen_cyg.sh
\family default
, followed by '
\family typewriter
make
\family default
' and '
\family typewriter
make install
\family default
'.
\end_layout
\begin_layout Standard
Under OS MINGW, a direct compilation would require the additional installation
of perl module XML-LibXML, which is not as straightforward as it should
be.
However you may start with a CYGWIN compile as described above.
If you then go to your MSYS window, cd to the adms top directory and start
\family typewriter
./mingw-compile.sh
\family default
, you will obtain
\family sans
admsXml.exe
\family default
, copied to MSYS
\family sans
/bin
\family default
, and you are ready to go.
To facilitate installation under MS Windows, a
\family sans
admsXml.exe
\family default
\begin_inset CommandInset href
LatexCommand href
name "zipped binary"
target "http://ngspice.sourceforge.net/adms2/adms-admsXml-Win32-bin.zip"
\end_inset
is available.
Just copy it to MSYS
\family sans
/bin
\family default
directory and start working on your verilog models.
\end_layout
\begin_layout Standard
A short test of a successful installation is:
\end_layout
\begin_layout Standard
\family typewriter
$ admsXml -v
\end_layout
\begin_layout Standard
\family typewriter
$ [usage..] release name="admsXml" version="2.3.0" date="Aug 4 2010"
\begin_inset Newline newline
\end_inset
time="10:24:18"
\end_layout
\begin_layout Standard
Compilation of admsXml with MS Visual Studio is not possible, because the
source code has variable declarations not only at the top of a block, but
deliberately also in the following lines.
This is ok by the C99 standard, but not supported by MS Visual Studio.
\end_layout
\begin_layout Chapter
Mixed-Level Simulation (ngspice with TCAD)
\end_layout
\begin_layout Section
Cider
\end_layout
\begin_layout Standard
Ngspice implements mixed-level simulation through the merging of its code
with CIDER (details see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:CIDER-User’s-Manual"
\end_inset
).
\end_layout
\begin_layout Standard
CIDER is a mixed-level circuit and device simulator that provides a direct
link between technology parameters and circuit performance.
A mixed-level circuit and device simulator can provide greater simulation
accuracy than a stand-alone circuit or device simulator by numerically
modeling the critical devices in a circuit.
Compact models can be used for noncritical devices.
\end_layout
\begin_layout Standard
CIDER couples the latest version of SPICE3 (version 3F.2) [JOHN92] to a internal
C-based device simulator, DSIM.
SPICE3 provides circuit analyses, compact models for semiconductor devices,
and an interactive user interface.
DSIM provides accurate, one- and two-dimensional numerical device models
based on the solution of Poisson's equation, and the electron and hole
current-continuity equations.
DSIM incorporates many of the same basic physical models found in the the
Stanford two-dimensional device simulator PISCES [PINT85].
Input to CIDER consists of a SPICE-like description of the circuit and
its compact models, and PISCES-like descriptions of the structures of numerical
ly modeled devices.
As a result, CIDER should seem familiar to designers already accustomed
to these two tools.
For example, SPICE3F.2 input files should run without modification, producing
identical results.
\end_layout
\begin_layout Standard
CIDER is based on the mixed-level circuit and device simulator CODECS [MAYA88]
and is a replacement for this program.
The basic algorithms of the two programs are the same.
Some of the differences between CIDER and CODECS are described below.
The CIDER input format has greater flexibility and allows increased access
to physical model parameters.
New physical models have been added to allow simulation of state-of-the-art
devices.
These include transverse field mobility degradation [GATE90] that is important
in scaled-down MOSFETs and a polysilicon model for poly-emitter bipolar
transistors.
Temperature dependence has been included for most physical models over
the range from -50°C to 150°C.
The numerical models can be used to simulate all the basic types of semiconduct
or devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs.
BJTs and JFETs can be modeled with or without a substrate contact.
Support has been added for the management of device internal states.
Post-processing of device states can be performed using the NUTMEG user
interface of SPICE3.
Previously computed states can be loaded into the program to provide accurate
initial guesses for subsequent analyses.
Finally, numerous small bugs have been discovered and fixed, and the program
has been ported to a wider variety of computing platforms.
\end_layout
\begin_layout Standard
Berkeley tradition calls for the naming of new versions of programs by affixing
a (number, letter, number) triplet to the end of the program name.
Under this scheme, CIDER should instead be named CODECS2A.l.
However, tradition has been broken in this case because major incompatibilities
exist between the two programs and because it was observed that the acronym
CODECS is already used in the analog design community to refer to coder-decoder
circuits.
\end_layout
\begin_layout Standard
Details of the basic semiconductor equations and the physical models used
by CIDER are not provided in this manual.
Unfortunately, no other single source exists that describes all of the
relevant background material.
Comprehensive reviews of device simulation can be found in [PINT90] and
the book [SELB84].
CODECS and its inversion-layer mobility model are described in [MAYA88]
and LGATE90], respectively.
PISCES and its models are described in [PINT85].
Temperature dependencies for the PISCES models used by CIDER are available
in [SOLL90].
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:GSS,-Genius"
\end_inset
GSS, Genius
\end_layout
\begin_layout Standard
For Linux users the cooperation of the TCAD software GSS with ngspice might
be of interest, see
\begin_inset CommandInset href
LatexCommand href
target "http://ngspice.sourceforge.net/gss.html"
\end_inset
.
This project is no longer maintained however, but has moved into the Genius
simulator, still available as open source
\begin_inset CommandInset href
LatexCommand href
name "cogenda genius"
target "http://www.cogenda.com/article/download"
\end_inset
.
\end_layout
\begin_layout Chapter
\begin_inset CommandInset label
LatexCommand label
name "chap:Analyses-and-Output"
\end_inset
Analyses and Output Control (batch mode)
\end_layout
\begin_layout Standard
The command lines described in this chapter are specifying analyses and
outputs within the circuit description file.
They start with a `
\family typewriter
.
\family default
' (dot commands).
Specifying analyses and plots (or tables) in the input file with dot commands
is used with batch runs.
Batch mode is entered when either the
\family typewriter
\series bold
-b
\family default
\series default
option is given upon starting ngspice
\end_layout
\begin_layout Standard
\family typewriter
ngspice -b -r rawfile.raw circuitfile.cir
\end_layout
\begin_layout Standard
or when the default input source is redirected from a file (see also Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Batch-mode"
\end_inset
).
\end_layout
\begin_layout Standard
\family typewriter
ngspice < circuitfile.cir
\end_layout
\begin_layout Standard
In batch mode, the analyses specified by the control lines in the input
file (e.g.
\family typewriter
.ac
\family default
,
\family typewriter
.tran
\family default
, etc.) are immediately executed.
If the
\family typewriter
\series bold
-r
\family default
\series default
rawfile option is given then all data generated is written to a ngspice
rawfile.
The rawfile may later be read by the interactive mode of ngspice using
the
\family sans
load
\family default
command (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Load:-Load-rawfile"
\end_inset
).
In this case, the
\family typewriter
.save
\family default
line (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Batch-Output"
\end_inset
) may be used to record the value of internal device variables (see Appendix,
Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "cha:Model-and-Device"
\end_inset
).
\end_layout
\begin_layout Standard
If a rawfile is not specified, then output plots (in `line-printer' form)
and tables can be printed according to the
\family typewriter
.print
\family default
,
\family typewriter
.plot
\family default
, and
\family typewriter
.four
\family default
control lines, described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Batch-Output"
\end_inset
.
\end_layout
\begin_layout Standard
If ngspice is started in interactive mode (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Interactive-mode"
\end_inset
), like
\end_layout
\begin_layout Standard
\family typewriter
ngspice circuitfile.cir
\end_layout
\begin_layout Standard
and no control section (
\family typewriter
.control
\family default
...
\family typewriter
.endc
\family default
, see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Interactive-mode-with"
\end_inset
) is provided in the circuit file, the dot commands are not executed immediately
, but are waiting for manually receiving the command
\family sans
run
\family default
.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Simulator-Variables"
\end_inset
Simulator Variables (.options)
\end_layout
\begin_layout Standard
Various parameters of the simulations available in Ngspice can be altered
to control the accuracy, speed, or default values for some devices.
These parameters may be changed via the
\family sans
option
\family default
command (described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Option*:"
\end_inset
) or via the
\family typewriter
.options
\family default
line:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.options opt1 opt2 ...
(or opt=optval ...)
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.options reltol=.005 trtol=8
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The options line allows the user to reset program control and user options
for specific simulation purposes.
Options specified to Ngspice via the
\family typewriter
\series bold
option
\family default
\series default
command (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Option*:"
\end_inset
) are also passed on as if specified on a
\family typewriter
.options
\family default
line.
Any combination of the following options may be included, in any order.
`x' (below) represents some positive number.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:General-Options"
\end_inset
General Options
\end_layout
\begin_layout Description
ACCT causes accounting and run time statistics to be printed.
\end_layout
\begin_layout Description
NOACCT no printing of statistics, no printing of the Initial Transient Solution.
\end_layout
\begin_layout Description
NOINIT suppresses only printing of the Initial Transient Solution, maybe
combined with ACCT.
\end_layout
\begin_layout Description
LIST causes the summary listing of the input data to be printed.
\end_layout
\begin_layout Description
NOMOD suppresses the printout of the model parameters.
\end_layout
\begin_layout Description
NOPAGE suppresses page ejects.
\end_layout
\begin_layout Description
NODE causes the printing of the node table.
\end_layout
\begin_layout Description
OPTS causes the option values to be printed.
\end_layout
\begin_layout Description
TEMP=x Resets the operating temperature of the circuit.
The default value is 27
\begin_inset Formula $°C$
\end_inset
(300K).
TEMP can be overridden per device by a temperature specification on any
temperature dependent instance.
May also be generally overridden by a .TEMP card (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:.temp"
\end_inset
).
\end_layout
\begin_layout Description
TNOM=x resets the nominal temperature at which device parameters are measured.
The default value is 27
\begin_inset Formula $°C$
\end_inset
(300 deg K).
TNOM can be overridden by a specification on any temperature dependent
device model.
\end_layout
\begin_layout Description
WARN=1|0 enables or turns of SOA (Safe Operating Area) voltage warning messages
(default: 0).
\end_layout
\begin_layout Description
MAXWARNS=x specifies the maximum number of SOA (Safe Operating Area) warning
messages per model (default: 5).
\end_layout
\begin_layout Description
SAVECURRENTS save currents through all terminals of the following devices:
M, J, Q, D, R, C, L, B, F, G, W, S, I (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Circuit-elements-(device"
\end_inset
).
Recommended only for small circuits, because otherwise memory requirements
explode and simulation speed suffers.
See
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Measuring-current-in"
\end_inset
for more details.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:DC-Solution-Options"
\end_inset
DC Solution Options
\end_layout
\begin_layout Standard
The following options controls properties pertaining to DC analysis and
algorithms.
Since transient analysis is based on DC many of the options affect the
latter one.
\end_layout
\begin_layout Description
ABSTOL=x resets the absolute current error tolerance of the program.
The default value is 1 pA.
\end_layout
\begin_layout Description
GMIN=x resets the value of GMIN, the minimum conductance allowed by the
program.
The default value is 1.0e-12.
\end_layout
\begin_layout Description
ITL1=x resets the dc iteration limit.
The default is 100.
\end_layout
\begin_layout Description
ITL2=x resets the dc transfer curve iteration limit.
The default is 50.
\end_layout
\begin_layout Description
KEEPOPINFO Retain the operating point information when either an AC, Distortion,
or Pole-Zero analysis is run.
This is particularly useful if the circuit is large and you do not want
to run a (redundant)
\family typewriter
.OP
\family default
analysis.
\end_layout
\begin_layout Description
PIVREL=x resets the relative ratio between the largest column entry and
an acceptable pivot value.
The default value is 1.0e-3.
In the numerical pivoting algorithm the allowed minimum pivot value is
determined by
\begin_inset Formula $\mathtt{EPSREL}=\mathtt{AMAX1}(\mathtt{PIVREL}\cdot\mathtt{MAXVAL},\:\mathtt{PIVTOL})$
\end_inset
where MAXVAL is the maximum element in the column where a pivot is sought
(partial pivoting).
\end_layout
\begin_layout Description
PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted
as a pivot.
The default value is 1.0e-13.
\end_layout
\begin_layout Description
RELTOL=x resets the relative error tolerance of the program.
The default value is 0.001 (0.1%).
\end_layout
\begin_layout Description
RSHUNT=x introduces a resistor from each analog node to ground.
The value of the resistor should be high enough to not interfere with circuit
operations.
The XSPICE option has to be enabled (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Advanced-Install"
\end_inset
) .
\end_layout
\begin_layout Description
VNTOL=x resets the absolute voltage error tolerance of the program.
The default value is 1
\begin_inset Formula $\mu V$
\end_inset
.
\end_layout
\begin_layout Subsubsection
Matrix Conditioning info
\end_layout
\begin_layout Standard
In most SPICE-based simulators, problems can arise with certain circuit
topologies.
One of the most common problems is the absence of a DC path to ground at
some node.
This may happen, for example, when two capacitors are connected in series
with no other connection at the common node or when certain code models
are cascaded.
The result is an ill-conditioned or nearly singular matrix that prevents
the simulation from completing.
The XSPICE option introduces the
\family typewriter
rshunt
\family default
option to help eliminate this problem.
When used, this option inserts resistors to ground at all the analog nodes
in the circuit.
In general, the value of
\family typewriter
rshunt
\family default
should be set to some very high resistance (e.g.
1000 Meg Ohms or greater) so that the operation of the circuit is essentially
unaffected, but the matrix problems are corrected.
If you should encounter a `no DC path to ground' or a `matrix is nearly
singular' error message with your circuit, you should try adding the following
\family typewriter
.option
\family default
card to your circuit description deck.
\end_layout
\begin_layout LyX-Code
.option rshunt = 1.0e12
\end_layout
\begin_layout Standard
Usually a value of 1.0e12 is sufficient to correct the matrix problems.
However, if you still have problems, you may wish to try lowering this
value to 1.0e10 or 1.0e9.
\end_layout
\begin_layout Standard
Another matrix conditioning problem might occur if you try to place an inductor
in parallel to a voltage source.
An ac simulation will fail, because it is preceded by an op analysis.
Option noopac (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:AC-Solution-Options"
\end_inset
) will help if the circuit is linear.
If the circuit is non-linear, you will need the op analysis.
Then adding a small resistor (e.g.
1e-4 Ohms) in series to the inductor will help to obtain convergence.
\end_layout
\begin_layout LyX-Code
.option rseries = 1.0e-4
\end_layout
\begin_layout Standard
will add a series resistor to each inductor in the circuit.
Be careful if you use behavioral inductors (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Inductors,-dependent-on"
\end_inset
), because the result may become unpredictable.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:AC-Solution-Options"
\end_inset
AC Solution Options
\end_layout
\begin_layout Description
NOOPAC Do not do an operating point (OP) analysis before the AC analysis.
To become valid, this option requires that the circuit is linear, thus
consists only of R, L, and C devices, independent V, I sources and linear
dependent E, G, H, and F sources (without poly statement, non-behavioral).
If a non-linear device is detected, the OP analysis will be executed automatica
lly.
This option is of interest for example in nested LC circuits, where there
is no series resistance for the L device given, which during OP analysis
may result in an ill formed matrix, yields an error message and aborts
the simulation.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Transient-Analysis-Options"
\end_inset
Transient Analysis Options
\end_layout
\begin_layout Description
AUTOSTOP stops a transient analysis after successfully calculating all measure
functions (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.MEAS"
\end_inset
) specified with the dot command
\family typewriter
.meas
\family default
.
Autostop is not available with
\family typewriter
meas
\family default
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Meas*:-Mesurements-on"
\end_inset
) used in control mode.
\end_layout
\begin_layout Description
CHGTOL=x resets the charge tolerance of the program.
The default value is 1.0e-14.
\end_layout
\begin_layout Description
CONVSTEP=x relative step limit applied to code models.
\end_layout
\begin_layout Description
CONVABSSTEP=x absolute step limit applied to code models.
\end_layout
\begin_layout Description
GMINSTEPS=x [*] sets number of Gmin steps to be attempted.
If the value is set to zero, the gmin stepping algorithm is disabled.
In such case the source stepping algorithm becomes the standard when the
standard procedure fails to converge to a solution.
\end_layout
\begin_layout Description
INTERP interpolates output data onto fixed time steps, detemined by TSTEP
(
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.TRAN:-Transient-Analysis"
\end_inset
).
Uses linear interpolation between previous and next time value.
Simulation itself is not influenced by this option.
May be used in all simulation modes (batch, control or interactive,
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Starting-options"
\end_inset
).
This option may drastically reduce memory requirements in control mode
or file size in batch mode, but be careful not to choose a too large TSTEP
value, otherwise your output data may be corrupted by undersampling.
See command 'linearize' (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Linearize*:-Interpolate-to"
\end_inset
) in control or interactive mode to achieve similar outputs by post-processing
of data.
See
\family sans
ngspice/examples/xspice/delta-sigma/delta-sigma-1.cir
\family default
how INTERP will reduce memory requirements and speeds up plotting.
\end_layout
\begin_layout Description
ITL3=x resets the lower transient analysis iteration limit.
the default value is 4.
(Note: not implemented in Spice3).
\end_layout
\begin_layout Description
ITL4=x resets the transient analysis time-point iteration limit.
the default is 10.
\end_layout
\begin_layout Description
ITL5=x resets the transient analysis total iteration limit.
the default is 5000.
Set ITL5=0 to omit this test.
(Note: not implemented in Spice3).
\end_layout
\begin_layout Description
ITL6=x [*] synonym for SRCSTEPS.
\end_layout
\begin_layout Description
MAXEVITER=x sets the number of event iterations that are allowed at an analysis
point
\end_layout
\begin_layout Description
MAXOPALTER=x specifies the maximum number of analog/event alternations that
the simulator can use in solving a hybrid circuit.
\end_layout
\begin_layout Description
MAXORD=x [*] specifies the maximum order for the numerical integration method
used by SPICE.
Possible values for the Gear method are from 2 (the default) to 6.
Using the value 1 with the trapezoidal method specifies backward Euler
integration.
\end_layout
\begin_layout Description
METHOD=name sets the numerical integration method used by SPICE.
Possible names are `Gear' or `trapezoidal' (or just `trap').
The default is trapezoidal.
\end_layout
\begin_layout Description
NOOPALTER=TRUE|FALSE if set to false alternations between analog/event are
enabled.
\end_layout
\begin_layout Description
RAMPTIME=x this options sets the rate of change of independent supplies
and code model inductors and capacitors with initial conditions specified.
\end_layout
\begin_layout Description
SRCSTEPS=x [*] a non-zero value causes SPICE to use a source-stepping method
to find the DC operating point.
Its value specifies the number of steps.
\end_layout
\begin_layout Description
\begin_inset CommandInset label
LatexCommand label
name "des:TRTOL"
\end_inset
TRTOL=x resets the transient error tolerance.
The default value is 7.
This parameter is an estimate of the factor by which ngspice overestimates
the actual truncation error.
If XSPICE is enabled and 'A' devices included, the value is internally
set to 1 for higher precision.
This will cost a factor of two in CPU time during transient analysis.
\end_layout
\begin_layout Description
XMU=x sets a damping factor for trapezoidal integration.
The default value is
\family typewriter
XMU
\family default
=0.5.
A value
\family typewriter
<
\family default
0.5 may be chosen.
Even a small reduction, e.g.
to 0.495, may suppress trap ringing.
The reduction has to be set carefully in order not to excessively damp
circuits that are prone to ringing, and lead the simulation (and the user)
to believe that the circuit is stable.
\end_layout
\begin_layout Subsection
ELEMENT Specific options
\end_layout
\begin_layout Description
BADMOS3 Use the older version of the MOS3 model with the `kappa' discontinuity.
\end_layout
\begin_layout Description
DEFAD=x resets the value for MOS drain diffusion area; the default is 0.0.
\end_layout
\begin_layout Description
DEFAS=x resets the value for MOS source diffusion area; the default is 0.0.
\end_layout
\begin_layout Description
DEFL=x resets the value for MOS channel length; the default is 100.0
\begin_inset Formula $\mu m$
\end_inset
.
\end_layout
\begin_layout Description
DEFW=x resets the value for MOS channel width; the default is 100.0
\begin_inset Formula $\mu m$
\end_inset
.
\end_layout
\begin_layout Description
SCALE=x set the element scaling factor for geometric element parameters
whose default unit is meters.
As an example: scale=1u and a MOSFET instance parameter W=10 will result
in a width of 10
\begin_inset Formula $\mu m$
\end_inset
for this device.
An area parameter AD=20 will result in 20e-12 m
\begin_inset script superscript
\begin_layout Plain Layout
2
\end_layout
\end_inset
.
Following instance parameters are scaled:
\end_layout
\begin_layout Itemize
Resistors and Capacitors: W, L
\end_layout
\begin_layout Itemize
Diodes: W, L, Area
\end_layout
\begin_layout Itemize
JFET, MESFET: W, L, Area
\end_layout
\begin_layout Itemize
MOSFET: W, L, AS, AD, PS, PD, SA, SB, SC, SD
\end_layout
\begin_layout Subsection
Transmission Lines Specific Options
\end_layout
\begin_layout Description
TRYTOCOMPACT Applicable only to the LTRA model (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Lossy-Transmission-Line"
\end_inset
).
When specified, the simulator tries to condense LTRA transmission line's
past history of input voltages and currents.
\end_layout
\begin_layout Subsection
Precedence of option and .options commands
\end_layout
\begin_layout Standard
There are various ways to set the above mentioned options in Ngspice.
If no
\family typewriter
option
\family default
or
\family typewriter
.options
\family default
lines are set by the user, internal default values are given for each of
the simulator variables.
\end_layout
\begin_layout Standard
You may set options in the init files
\family sans
spinit
\family default
or
\family sans
.spiceinit
\family default
via the
\family typewriter
option
\family default
command (see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Option*:"
\end_inset
).
The values given here will supersede the default values.
If you set options via the
\family typewriter
.options
\family default
line in your input file, their values will supersede the default and init
file data.
Finally if you set options inside a
\family typewriter
.control
\family default
...
\family typewriter
.endc
\family default
section, these values will supersede any values of the respective simulator
variables given so far.
\end_layout
\begin_layout Section
Initial Conditions
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.NODESET"
\end_inset
.NODESET: Specify Initial Node Voltage Guesses
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.NODESET V(NODNUM)=VAL V(NODNUM)=VAL ...
\end_layout
\begin_layout Plain Layout
.NODESET ALL=VAL
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.NODESET V(12)=4.5 V(4)=2.23
\end_layout
\begin_layout Plain Layout
.NODESET ALL=1.5
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.nodeset
\family default
line helps the program find the dc or initial transient solution by making
a preliminary pass with the specified nodes held to the given voltages.
The restriction is then released and the iteration continues to the true
solution.
The
\family typewriter
.nodeset
\family default
line may be necessary for convergence on bistable or a-stable circuits.
\family typewriter
.nodeset all=val
\family default
allows to set all starting node voltages (except for the ground node) in
a single line.
In general, the
\family typewriter
.nodeset
\family default
line should not be necessary.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.IC:-Set-Initial"
\end_inset
.IC: Set Initial Conditions
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.ic v(nodnum)=val v(nodnum)=val ...
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.ic v(11)=5 v(4)=-5 v(2)=2.2
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.ic
\family default
line is for setting transient initial conditions.
It has two different interpretations, depending on whether the
\family typewriter
\series bold
uic
\family default
\series default
parameter is specified on the
\family typewriter
.tran
\family default
control line.
Also, one should not confuse this line with the
\family typewriter
.nodeset
\family default
line.
The
\family typewriter
.nodeset
\family default
line is only to help dc convergence, and does not affect the final bias
solution (except for multi-stable circuits).
The two interpretations of this line are as follows:
\end_layout
\begin_layout Enumerate
When the
\family typewriter
\series bold
uic
\family default
\series default
parameter is specified on the
\family typewriter
.tran
\family default
line, then the node voltages specified on the
\family typewriter
.ic
\family default
control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET
initial conditions.
This is equivalent to specifying the
\family typewriter
\series bold
ic=...
\family default
\series default
parameter on each device line, but is much more convenient.
The
\family typewriter
\series bold
ic=...
\family default
\series default
parameter can still be specified and takes precedence over the
\family typewriter
.ic
\family default
values.
Since no dc bias (initial transient) solution is computed before the transient
analysis, one should take care to specify all dc source voltages on the
\family typewriter
.ic
\family default
control line if they are to be used to compute device initial conditions.
\end_layout
\begin_layout Enumerate
When the
\family typewriter
\series bold
uic
\family default
\series default
parameter is not specified on the
\family typewriter
.tran
\family default
control line, the dc bias (initial transient) solution is computed before
the transient analysis.
In this case, the node voltages specified on the
\family typewriter
.ic
\family default
control lines are forced to the desired initial values during the bias
solution.
During transient analysis, the constraint on these node voltages is removed.
This is the preferred method since it allows ngspice to compute a consistent
dc solution.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sec:Analyses"
\end_inset
Analyses
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.AC:-Small-Signal-AC"
\end_inset
.AC: Small-Signal AC Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.ac dec nd fstart fstop
\end_layout
\begin_layout Plain Layout
.ac oct no fstart fstop
\end_layout
\begin_layout Plain Layout
.ac lin np fstart fstop
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.ac dec 10 1 10K
\end_layout
\begin_layout Plain Layout
.ac dec 10 1K 100MEG
\end_layout
\begin_layout Plain Layout
.ac lin 100 1 100HZ
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
dec
\family default
\series default
stands for decade variation, and
\family typewriter
\series bold
nd
\family default
\series default
is the number of points per decade.
\family typewriter
\series bold
oct
\family default
\series default
stands for octave variation, and
\family typewriter
\series bold
no
\family default
\series default
is the number of points per octave.
\family typewriter
\series bold
lin
\family default
\series default
stands for linear variation, and
\family typewriter
\series bold
np
\family default
\series default
is the number of points.
\family typewriter
\series bold
fstart
\family default
\series default
is the starting frequency, and
\family typewriter
\series bold
fstop
\family default
\series default
is the final frequency.
If this line is included in the input file, ngspice performs an AC analysis
of the circuit over the specified frequency range.
Note that in order for this analysis to be meaningful, at least one independent
source must have been specified with an ac value.
Typically it does not make much sense to specify more than one ac source.
If you do, the result will be a superposition of all sources, thus difficult
to interpret.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
Basic RC circuit
\end_layout
\begin_layout Plain Layout
r 1 2 1.0
\end_layout
\begin_layout Plain Layout
c 2 0 1.0
\end_layout
\begin_layout Plain Layout
vin 1 0 dc 0 ac 1 $ <--- the ac source
\end_layout
\begin_layout Plain Layout
.options noacct
\end_layout
\begin_layout Plain Layout
.ac dec 10 .01 10
\end_layout
\begin_layout Plain Layout
.plot ac vdb(2) xlog
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
In this ac (or 'small signal') analysis all non-linear devices are linearized
around their actual dc operating point.
All Ls and Cs get their imaginary value, depending on the actual frequency
step.
Each output vector will be calculated relative to the input voltage (current)
given by the ac value (Vin equals to 1 in the example above).
The resulting node voltages (and branch currents) are complex vectors.
Therefore you have to be careful using the
\family typewriter
plot
\family default
command.
Especially you may use the variants of vxx(node) described in Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.PRINT-Lines"
\end_inset
like
\family typewriter
vdb(2)
\family default
(see example above).
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.DC:-DC-Transfer"
\end_inset
.DC: DC Transfer Function
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.dc srcnam vstart vstop vincr [src2 start2 stop2 incr2]
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.dc VIN 0.25 5.0 0.25
\end_layout
\begin_layout Plain Layout
.dc VDS 0 10 .5 VGS 0 5 1
\end_layout
\begin_layout Plain Layout
.dc VCE 0 10 .25 IB 0 10u 1u
\end_layout
\begin_layout Plain Layout
.dc RLoad 1k 2k 100
\end_layout
\begin_layout Plain Layout
.dc TEMP -15 75 5
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.dc
\family default
line defines the dc transfer curve source and sweep limits (again with
capacitors open and inductors shorted).
\family typewriter
\series bold
srcnam
\family default
\series default
is the name of an independent voltage or current source, a resistor or
the circuit temperature.
\family typewriter
\series bold
vstart
\family default
\series default
,
\family typewriter
\series bold
vstop
\family default
\series default
, and
\family typewriter
\series bold
vincr
\family default
\series default
are the starting, final, and incrementing values respectively.
The first example causes the value of the voltage source VIN to be swept
from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts.
A second source (
\family typewriter
\series bold
src2
\family default
\series default
) may optionally be specified with associated sweep parameters.
In this case, the first source is swept over its range for each value of
the second source.
This option can be useful for obtaining semiconductor device output characteris
tics.
See the example circuit description on transistor characteristics (
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:MOSFET-Characterization"
\end_inset
).
\end_layout
\begin_layout Subsection
.DISTO: Distortion Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.disto dec nd fstart fstop
\end_layout
\begin_layout Plain Layout
.disto oct no fstart fstop
\end_layout
\begin_layout Plain Layout
.disto lin np fstart fstop
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.disto dec 10 1kHz 100MEG
\end_layout
\begin_layout Plain Layout
.disto dec 10 1kHz 100MEG 0.9
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.disto
\family default
line does a small-signal distortion analysis of the circuit.
A multi-dimensional Volterra series analysis is done using multi-dimensional
Taylor series to represent the nonlinearities at the operating point.
Terms of up to third order are used in the series expansions.
\end_layout
\begin_layout Standard
If the optional parameter
\family typewriter
\series bold
f2overf1
\family default
\series default
is not specified,
\family typewriter
.disto
\family default
does a harmonic analysis - i.e., it analyses distortion in the circuit using
only a single input frequency
\begin_inset Formula $F_{1}$
\end_inset
, which is swept as specified by arguments of the
\family typewriter
.disto
\family default
command exactly as in the
\family typewriter
.ac
\family default
command.
Inputs at this frequency may be present at more than one input source,
and their magnitudes and phases are specified by the arguments of the
\family typewriter
\series bold
distof1
\family default
\series default
keyword in the input file lines for the input sources (see the description
for independent sources).
(The arguments of the
\family typewriter
\series bold
distof2
\family default
\series default
keyword are not relevant in this case).
\end_layout
\begin_layout Standard
The analysis produces information about the AC values of all node voltages
and branch currents at the harmonic frequencies
\begin_inset Formula $2F_{1}$
\end_inset
and , vs.
the input frequency
\begin_inset Formula $F_{1}$
\end_inset
as it is swept.
(A value of 1 (as a complex distortion output) signifies
\begin_inset Formula $\cos(2\pi(2F_{1})t)$
\end_inset
at
\begin_inset Formula $2F_{1}$
\end_inset
and
\begin_inset Formula $\cos(2\pi(3F_{1})t)$
\end_inset
at
\begin_inset Formula $3F_{1}$
\end_inset
, using the convention that 1 at the input fundamental frequency is equivalent
to
\begin_inset Formula $\cos(2\pi F_{1}t)$
\end_inset
.) The distortion component desired (
\begin_inset Formula $2F_{1}$
\end_inset
or
\begin_inset Formula $3F_{1}$
\end_inset
) can be selected using commands in ngnutmeg, and then printed or plotted.
(Normally, one is interested primarily in the magnitude of the harmonic
components, so the magnitude of the AC distortion value is looked at).
It should be noted that these are the AC values of the actual harmonic
components, and are not equal to HD2 and HD3.
To obtain HD2 and HD3, one must divide by the corresponding AC values at
\begin_inset Formula $F_{1}$
\end_inset
, obtained from an
\family typewriter
.ac
\family default
line.
This division can be done using ngnutmeg commands.
\end_layout
\begin_layout Standard
If the optional
\family typewriter
\series bold
f2overf1
\family default
\series default
parameter is specified, it should be a real number between (and not equal
to) 0.0 and 1.0; in this case,
\family typewriter
.disto
\family default
does a spectral analysis.
It considers the circuit with sinusoidal inputs at two different frequencies
\begin_inset Formula $F_{1}$
\end_inset
and
\begin_inset Formula $F_{2}$
\end_inset
.
\begin_inset Formula $F_{1}$
\end_inset
is swept according to the
\family typewriter
.disto
\family default
control line options exactly as in the
\family typewriter
.ac
\family default
control line.
\begin_inset Formula $F_{2}$
\end_inset
is kept fixed at a single frequency as
\begin_inset Formula $F_{1}$
\end_inset
sweeps - the value at which it is kept fixed is equal to
\family typewriter
f2overf1
\family default
times
\family typewriter
fstart
\family default
.
Each independent source in the circuit may potentially have two (superimposed)
sinusoidal inputs for distortion, at the frequencies
\begin_inset Formula $F_{1}$
\end_inset
and
\begin_inset Formula $F_{2}$
\end_inset
.
The magnitude and phase of the
\begin_inset Formula $F_{1}$
\end_inset
component are specified by the arguments of the
\family typewriter
\series bold
distof1
\family default
\series default
keyword in the source's input line (see the description of independent
sources); the magnitude and phase of the
\begin_inset Formula $F_{2}$
\end_inset
component are specified by the arguments of the
\family typewriter
\series bold
distof2
\family default
\series default
keyword.
The analysis produces plots of all node voltages/branch currents at the
intermodulation product frequencies
\begin_inset Formula $F_{1}+F_{2}$
\end_inset
,
\begin_inset Formula $F_{1}-F_{2}$
\end_inset
, and
\begin_inset Formula $(2F_{1})-F_{2}$
\end_inset
, vs the swept frequency
\begin_inset Formula $F_{1}$
\end_inset
.
The IM product of interest may be selected using the
\family sans
setplot
\family default
command, and displayed with the
\family typewriter
print
\family default
and
\family typewriter
plot
\family default
commands.
It is to be noted as in the harmonic analysis case, the results are the
actual AC voltages and currents at the intermodulation frequencies, and
need to be normalized with respect to
\family typewriter
.ac
\family default
values to obtain the IM parameters.
\end_layout
\begin_layout Standard
If the
\family typewriter
\series bold
distof1
\family default
\series default
or
\family typewriter
\series bold
distof2
\family default
\series default
keywords are missing from the description of an independent source, then
that source is assumed to have no input at the corresponding frequency.
The default values of the magnitude and phase are 1.0 and 0.0 respectively.
The phase should be specified in degrees.
\end_layout
\begin_layout Standard
It should be carefully noted that the number
\family typewriter
\series bold
f2overf1
\family default
\series default
should ideally be an irrational number, and that since this is not possible
in practice, efforts should be made to keep the denominator in its fractional
representation as large as possible, certainly above 3, for accurate results
(i.e., if
\family typewriter
\series bold
f2overf1
\family default
\series default
is represented as a fraction
\begin_inset Formula $\nicefrac{A}{B}$
\end_inset
, where
\begin_inset Formula $A$
\end_inset
and
\begin_inset Formula $B$
\end_inset
are integers with no common factors,
\begin_inset Formula $B$
\end_inset
should be as large as possible; note that
\begin_inset Formula $A49/100$
\end_inset
\begin_inset Formula $F_{1}=F_{2}$
\end_inset
.
In this case, there are two very closely spaced frequency components at
\begin_inset Formula $F_{2}$
\end_inset
and
\begin_inset Formula $F_{1}-F_{2}$
\end_inset
.
One of the advantages of the Volterra series technique is that it computes
distortions at mix frequencies expressed symbolically (i.e.
\begin_inset Formula $nF_{1}+mF_{2}$
\end_inset
), therefore one is able to obtain the strengths of distortion components
accurately even if the separation between them is very small, as opposed
to transient analysis for example.
The disadvantage is of course that if two of the mix frequencies coincide,
the results are not merged together and presented (though this could presumably
be done as a postprocessing step).
Currently, the interested user should keep track of the mix frequencies
himself or herself and add the distortions at coinciding mix frequencies
together should it be necessary.
\end_layout
\begin_layout Standard
Only a subset of the ngspice nonlinear device models supports distortion
analysis.
These are
\end_layout
\begin_layout Itemize
Diodes (DIO),
\end_layout
\begin_layout Itemize
BJT,
\end_layout
\begin_layout Itemize
JFET (level 1),
\end_layout
\begin_layout Itemize
MOSFETs (levels 1, 2, 3, 9, and BSIM1),
\end_layout
\begin_layout Itemize
MESFET (level 1).
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.NOISE:-Noise-Analysis"
\end_inset
.NOISE: Noise Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.noise v(output <,ref>) src ( dec | lin | oct ) pts fstart fstop
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.noise v(5) VIN dec 10 1kHz 100MEG
\end_layout
\begin_layout Plain Layout
.noise v(5,3) V1 oct 8 1.0 1.0e6 1
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.noise
\family default
line does a noise analysis of the circuit.
\family typewriter
\series bold
output
\family default
\series default
is the node at which the total output noise is desired; if
\family typewriter
\series bold
ref
\family default
\series default
is specified, then the noise voltage
\family typewriter
\series bold
v(output) - v(ref)
\family default
\series default
is calculated.
By default,
\family typewriter
\series bold
ref
\family default
\series default
is assumed to be ground.
\family typewriter
\series bold
src
\family default
\series default
is the name of an independent source to which input noise is referred.
\family typewriter
\series bold
pts
\family default
\series default
,
\family typewriter
\series bold
fstart
\family default
\series default
and
\family typewriter
\series bold
fstop
\family default
\series default
are
\family typewriter
.ac
\family default
type parameters that specify the frequency range over which plots are desired.
\family typewriter
\series bold
pts_per_summary
\family default
\series default
is an optional integer; if specified, the noise contributions of each noise
generator is produced every
\family typewriter
\series bold
pts_per_summary
\family default
\series default
frequency points.
The
\family typewriter
.noise
\family default
control line produces two plots:
\end_layout
\begin_layout Enumerate
one for the Noise Spectral Density (in
\begin_inset Formula $\nicefrac{V}{\sqrt{Hz}}$
\end_inset
or
\begin_inset Formula $\nicefrac{A}{\sqrt{Hz}}$
\end_inset
) curves and
\end_layout
\begin_layout Enumerate
one for the total Integrated Noise (in
\begin_inset Formula $V$
\end_inset
or
\begin_inset Formula $A$
\end_inset
) over the specified frequency range.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.OP:-Operating-Point"
\end_inset
.OP: Operating Point Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.op
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The inclusion of this line in an input file directs ngspice to determine
the dc operating point of the circuit with inductors shorted and capacitors
opened.
\end_layout
\begin_layout Standard
Note: a DC analysis is automatically performed prior to a transient analysis
to determine the transient initial conditions, and prior to an AC small-signal,
Noise, and Pole-Zero analysis to determine the linearized, small-signal
models for nonlinear devices (see the
\family typewriter
KEEPOPINFO
\family default
variable
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:DC-Solution-Options"
\end_inset
).
\end_layout
\begin_layout LyX-Code
\end_layout
\begin_layout Subsection
.PZ: Pole-Zero Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.pz node1 node2 node3 node4 cur pol
\end_layout
\begin_layout Plain Layout
.pz node1 node2 node3 node4 cur zer
\end_layout
\begin_layout Plain Layout
.pz node1 node2 node3 node4 cur pz
\end_layout
\begin_layout Plain Layout
.pz node1 node2 node3 node4 vol pol
\end_layout
\begin_layout Plain Layout
.pz node1 node2 NODE3 node4 vol zer
\end_layout
\begin_layout Plain Layout
.pz node1 node2 node3 node4 vol pz
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.pz 1 0 3 0 cur pol
\end_layout
\begin_layout Plain Layout
.pz 2 3 5 0 vol zer
\end_layout
\begin_layout Plain Layout
.pz 4 1 4 1 cur pz
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
cur
\family default
\series default
stands for a transfer function of the type (output voltage)/(input current)
while
\family typewriter
\series bold
vol
\family default
\series default
stands for a transfer function of the type (output voltage)/(input voltage).
\family typewriter
\series bold
pol
\family default
\series default
stands for pole analysis only,
\family typewriter
\series bold
zer
\family default
\series default
for zero analysis only and
\family typewriter
\series bold
pz
\family default
\series default
for both.
This feature is provided mainly because if there is a non-convergence in
finding poles or zeros, then, at least the other can be found.
Finally,
\family typewriter
\series bold
node1
\family default
\series default
and
\family typewriter
\series bold
node2
\family default
\series default
are the two input nodes and
\family typewriter
\series bold
node3
\family default
\series default
and
\family typewriter
\series bold
node4
\family default
\series default
are the two output nodes.
Thus, there is complete freedom regarding the output and input ports and
the type of transfer function.
\end_layout
\begin_layout Standard
In interactive mode, the command syntax is the same except that the first
field is
\family sans
pz
\family default
instead of
\family typewriter
.pz
\family default
.
To print the results, one should use the command
\family sans
print all
\family default
.
\end_layout
\begin_layout Subsection
.SENS: DC or Small-Signal AC Sensitivity Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.SENS OUTVAR
\end_layout
\begin_layout Plain Layout
.SENS OUTVAR AC DEC ND FSTART FSTOP
\end_layout
\begin_layout Plain Layout
.SENS OUTVAR AC OCT NO FSTART FSTOP
\end_layout
\begin_layout Plain Layout
.SENS OUTVAR AC LIN NP FSTART FSTOP
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.SENS V(1,OUT)
\end_layout
\begin_layout Plain Layout
.SENS V(OUT) AC DEC 10 100 100k
\end_layout
\begin_layout Plain Layout
.SENS I(VTEST)
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The sensitivity of OUTVAR to all non-zero device parameters is calculated
when the SENS analysis is specified.
OUTVAR is a circuit variable (node voltage or voltage-source branch current).
The first form calculates sensitivity of the DC operating-point value of
OUTVAR.
The second form calculates sensitivity of the AC values of OUTVAR.
The parameters listed for AC sensitivity are the same as in an AC analysis
(see
\family typewriter
.AC
\family default
above).
The output values are in dimensions of change in output per unit change
of input (as opposed to percent change in output or per percent change
of input).
\end_layout
\begin_layout Subsection
.TF: Transfer Function Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.tf outvar insrc
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.tf v(5, 3) VIN
\end_layout
\begin_layout Plain Layout
.tf i(VLOAD) VIN
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The
\family typewriter
.tf
\family default
line defines the small-signal output and input for the dc small-signal
analysis.
\family typewriter
\series bold
outvar
\family default
\series default
is the small signal output variable and
\family typewriter
\series bold
insrc
\family default
\series default
is the small-signal input source.
If this line is included, ngspice computes the dc small-signal value of
the transfer function (output/input), input resistance, and output resistance.
For the first example, ngspice would compute the ratio of V(5, 3) to VIN,
the small-signal input resistance at VIN, and the small signal output resistanc
e measured across nodes 5 and 3.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.TRAN:-Transient-Analysis"
\end_inset
.TRAN: Transient Analysis
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.tran tstep tstop >
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.tran 1ns 100ns
\end_layout
\begin_layout Plain Layout
.tran 1ns 1000ns 500ns
\end_layout
\begin_layout Plain Layout
.tran 10ns 1us
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
tstep
\family default
\series default
is the printing or plotting increment for line-printer output.
For use with the post-processor,
\family typewriter
\series bold
tstep
\family default
\series default
is the suggested computing increment.
\family typewriter
\series bold
tstop
\family default
\series default
is the final time, and
\family typewriter
\series bold
tstart
\family default
\series default
is the initial time.
If
\family typewriter
\series bold
tstart
\family default
\series default
is omitted, it is assumed to be zero.
The transient analysis always begins at time zero.
In the interval , the circuit is analyzed (to reach a steady state), but no outputs are
stored.
In the interval <
\family typewriter
\series bold
tstart
\family default
\series default
,
\family typewriter
\series bold
tstop
\family default
\series default
>, the circuit is analyzed and outputs are stored.
\family typewriter
\series bold
tmax
\family default
\series default
is the maximum stepsize that ngspice uses; for default, the program chooses
either
\family typewriter
\series bold
tstep
\family default
\series default
or (
\family typewriter
\series bold
tstop
\family default
\series default
-
\family typewriter
\series bold
tstart
\family default
\series default
)/50.0, whichever is smaller.
\family typewriter
\series bold
tmax
\family default
\series default
is useful when one wishes to guarantee a computing interval that is smaller
than the printer increment,
\family typewriter
\series bold
tstep
\family default
\series default
.
\end_layout
\begin_layout Standard
An initial transient operating point at time zero is calculated according
to the following procedure: all independent voltages and currents are applied
with their time zero values, all capacitances are opened, inductances are
shorted, the non linear device equations are solved iteratively.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
uic
\family default
\series default
(use initial conditions) is an optional keyword that indicates that the
user does not want ngspice to solve for the quiescent operating point before
beginning the transient analysis.
If this keyword is specified, ngspice uses the values specified using IC=...
on the various elements as the initial transient condition and proceeds
with the analysis.
If the
\family typewriter
.ic
\family default
control line has been specified (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.IC:-Set-Initial"
\end_inset
), then the node voltages on the
\family typewriter
.ic
\family default
line are used to compute the initial conditions for the devices.
IC=...
will take precedence over the values given in the
\family typewriter
.ic
\family default
control line.
If neither IC=...
nor the
\family typewriter
.ic
\family default
control line is given for a specific node, node voltage zero is assumed.
\end_layout
\begin_layout Standard
Look at the description on the
\family typewriter
.ic
\family default
control line (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.IC:-Set-Initial"
\end_inset
) for its interpretation when
\family typewriter
\series bold
uic
\family default
\series default
is not specified.
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:Transient-noise-analysis"
\end_inset
Transient noise analysis (at low frequency)
\end_layout
\begin_layout Standard
In contrast to the analysis types described above the transient noise simulation
(noise current or voltage versus time) is not implemented as a dot command,
but is integrated with the independent voltage source
\family typewriter
vsrc
\family default
(
\family typewriter
isrc
\family default
not yet available) (see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Transient-noise-source"
\end_inset
) and used in combination with the
\family typewriter
.tran
\family default
transient analysis (
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.TRAN:-Transient-Analysis"
\end_inset
).
\end_layout
\begin_layout Standard
Transient noise analysis deals with noise currents or voltages added to
your circuits as a time dependent signal of randomly generated voltage
excursion on top of a fixed dc voltage.
The sequence of voltage values has random amplitude, but equidistant time
intervals, selectable by the user (parameter
\family typewriter
NT
\family default
).
The resulting voltage waveform is differentiable and thus does not require
any modifications of the matrix solving algorithms.
\end_layout
\begin_layout Standard
White noise is generated by the ngspice random number generator, applying
the Box-Muller transform.
Values are generated on the fly, each time when a breakpoint is hit.
\end_layout
\begin_layout Standard
The 1/f noise is generated with an algorithm provided by N.
J.
Kasdin (`
\shape italic
Discrete simulation of colored noise and stochastic processes and
\begin_inset Formula $1/f^{a}$
\end_inset
power law noise generation
\shape default
', Proceedings of the IEEE, Volume 83, Issue 5, May 1995 Page(s):802--827).
The noise sequence (one for each voltage/current source with 1/f selected)
is generated upon start up of the simulator and stored for later use.
The number of points is determined by the total simulation time divided
by
\family typewriter
NT
\family default
, rounded up the the nearest power of 2.
Each time a breakpoint (
\begin_inset Formula $n\star NT$
\end_inset
, relevant to the noise signal) is hit, the next value is retrieved from
the sequence.
\end_layout
\begin_layout Standard
If you want a random, but reproducible sequence, you may select a seed value
for the random number generator by adding
\end_layout
\begin_layout Standard
\family typewriter
set rndseed=nn
\end_layout
\begin_layout Standard
to the
\family sans
spinit
\family default
or
\family sans
.spiceinit
\family default
file,
\family typewriter
nn
\family default
being a positive integer number.
\end_layout
\begin_layout Standard
The transient noise analysis will allow the simulation of the three most
important noise sources.
Thermal noise is described by the Gaussian white noise.
Flicker noise (pink noise or 1 over f noise) with an exponent between 0
and 2 is provided as well.
Shot noise is dependent on the current flowing through a device and may
be simulated by applying a non-linear source as demonstrated in the following
example:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
* Shot noise test with B source, diode
\end_layout
\begin_layout Plain Layout
* voltage on device (diode, forward)
\end_layout
\begin_layout Plain Layout
Vdev out 0 DC 0 PULSE(0.4 0.45 10u)
\end_layout
\begin_layout Plain Layout
* diode, forward direction, to be modeled with noise
\end_layout
\begin_layout Plain Layout
D1 mess 0 DMOD
\end_layout
\begin_layout Plain Layout
.model DMOD D IS=1e-14 N=1
\end_layout
\begin_layout Plain Layout
X1 0 mess out ishot
\end_layout
\begin_layout Plain Layout
* device between 1 and 2
\end_layout
\begin_layout Plain Layout
* new output terminals of device including noise: 1 and 3
\end_layout
\begin_layout Plain Layout
.subckt ishot 1 2 3
\end_layout
\begin_layout Plain Layout
* white noise source with rms 1V
\end_layout
\begin_layout Plain Layout
* 20000 sample points
\end_layout
\begin_layout Plain Layout
VNG 0 11 DC 0 TRNOISE(1 1n 0 0)
\end_layout
\begin_layout Plain Layout
*measure the current i(v1)
\end_layout
\begin_layout Plain Layout
V1 2 3 DC 0
\end_layout
\begin_layout Plain Layout
* calculate the shot noise
\end_layout
\begin_layout Plain Layout
* sqrt(2*current*q*bandwidth)
\end_layout
\begin_layout Plain Layout
BI 1 3 I=sqrt(2*abs(i(v1))*1.6e-19*1e7)*v(11)
\end_layout
\begin_layout Plain Layout
.ends ishot
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.tran 1n 20u
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
run
\end_layout
\begin_layout Plain Layout
plot (-1)*i(vdev)
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\begin_layout Plain Layout
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
The selection of the delta time step (
\family typewriter
NT
\family default
) is worth discussing.
Gaussian white noise has unlimited bandwidth and thus unlimited energy
content.
This is unrealistic.
The bandwidth of real noise is limited, but it is still called `White'
if it is the same level throughout the frequency range of interest, e.g.
the bandwidth of your system.
Thus you may select
\family typewriter
NT
\family default
to be a factor of 10 smaller than the frequency limit of your circuit.
A thorough analysis is still needed to clarify the appropriate factor.
The transient method is probably most suited to circuits including switches,
which are not amenable to the small signal
\family typewriter
.NOISE
\family default
analysis (Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:.NOISE:-Noise-Analysis"
\end_inset
).
\end_layout
\begin_layout Standard
There is a price you have to pay for transient noise analysis: the number
of required time steps, and thus the simulation time, increases.
\end_layout
\begin_layout Standard
In addition to white and 1/f noise the independent voltage and current sources
offer a random telegraph signal (
\family typewriter
RTS
\family default
) noise source, also known as burst noise or popcorn noise, again for transient
analysis.
For each voltage (current) source offering
\family typewriter
RTS
\family default
noise an individual noise amplitude is required for input, as well as a
mean capture time and a mean emission time.
The amplitude resembles the influence of a single trap on the current or
voltage.
The capture and emission times emulate the filling and emptying of the
trap, typically following a Poisson process.
They are generated from an random exponential distribution with respective
mean values given by the user.
To simulate an ensemble of traps, you may combine several current or voltage
sources with different parameters.
\end_layout
\begin_layout Standard
All three sources (white, 1/f, and
\family typewriter
RTS
\family default
) may be combined in a single command line.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
RTS noise example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
* white noise, 1/f noise, RTS noise
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* voltage source
\end_layout
\begin_layout Plain Layout
VRTS2 13 12 DC 0 trnoise(0 0 0 0 5m 18u 30u)
\end_layout
\begin_layout Plain Layout
VRTS3 11 0 DC 0 trnoise(0 0 0 0 10m 20u 40u)
\end_layout
\begin_layout Plain Layout
VALL 12 11 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
VW1of 21 0 DC trnoise(1m 1u 1.0 0.1m)
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* current source
\end_layout
\begin_layout Plain Layout
IRTS2 10 0 DC 0 trnoise(0 0 0 0 5m 18u 30u)
\end_layout
\begin_layout Plain Layout
IRTS3 10 0 DC 0 trnoise(0 0 0 0 10m 20u 40u)
\end_layout
\begin_layout Plain Layout
IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u)
\end_layout
\begin_layout Plain Layout
R10 10 0 1
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
IW1of 9 0 DC trnoise(1m 1u 1.0 0.1m)
\end_layout
\begin_layout Plain Layout
Rall 9 0 1
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
* sample points
\end_layout
\begin_layout Plain Layout
.tran 1u 500u
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
run
\end_layout
\begin_layout Plain Layout
plot v(13) v(21)
\end_layout
\begin_layout Plain Layout
plot v(10) v(9)
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\begin_layout Plain Layout
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Some details on
\family typewriter
RTS
\family default
noise modeling are available in a recent article
\begin_inset CommandInset citation
LatexCommand cite
key "key-20"
\end_inset
, available
\begin_inset CommandInset href
LatexCommand href
name "here"
target "http://www.see.ed.ac.uk/~tbt/iscas09.pdf"
\end_inset
.
\end_layout
\begin_layout Standard
\emph on
This transient noise feature is still experimental.
\emph default
\end_layout
\begin_layout Standard
The following questions (among others) are to be solved:
\end_layout
\begin_layout Itemize
clarify the theoretical background
\end_layout
\begin_layout Itemize
noise limit of plain ngspice (numerical solver, fft etc.)
\end_layout
\begin_layout Itemize
time step (
\family typewriter
NT
\family default
) selection
\end_layout
\begin_layout Itemize
calibration of noise spectral density
\end_layout
\begin_layout Itemize
how to generate noise from a transistor model
\end_layout
\begin_layout Itemize
application benefits and limits
\end_layout
\begin_layout Subsection
\begin_inset CommandInset label
LatexCommand label
name "sub:.PSS:-Periodic_Steady_State-Analysis"
\end_inset
.PSS: Periodic Steady State Analysis
\end_layout
\begin_layout Standard
\emph on
Experimental code, not yet made publicly available.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.pss gfreq tstab oscnob psspoints harms sciter steadycoeff
\end_layout
\end_inset
\end_layout
\begin_layout Plain Layout
Examples:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
.pss 150 200e-3 2 1024 11 50 5e-3 uic
\end_layout
\begin_layout Plain Layout
.pss 624e6 1u v_plus 1024 10 150 5e-3 uic
\end_layout
\begin_layout Plain Layout
.pss 624e6 500n bout 1024 10 100 5e-3 uic
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
\family typewriter
\series bold
gfreq
\family default
\series default
is guessed frequency of fundamental suggested by user.
When performing transient analysis the PSS algorithm tries to infer a new
rough guess
\family typewriter
\series bold
rgfreq
\family default
\series default
on the fundamental.
If
\family typewriter
\series bold
gfreq
\family default
\series default
is out of
\begin_inset Formula $\pm$
\end_inset
10% with respect to
\family typewriter
\series bold
rgfreq
\family default
\series default
then
\family typewriter
\series bold
gfreq
\family default
\series default
is discarded.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
tstab
\family default
\series default
is stabilization time before the shooting begin to search for the PSS.
It has to be noticed that this parameter heavily influence the possibility
to reach the PSS.
Thus is a good practice to ensure a circuit to have a right
\family typewriter
\series bold
tstab
\family default
\series default
, e.g.
performing a separate TRAN analysis before to run PSS analysis.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
oscnob
\family default
\series default
is the node or branch where the oscillation dynamic is expected.
PSS analysis will give a brief report of harmonic content at this node
or branch.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
psspoints
\family default
\series default
is number of step in evaluating predicted period after convergence is reached.
It is useful only in Time Domain plots.
However this number should be higher than 2 times the requested
\family typewriter
\series bold
harms
\family default
\series default
.
Otherwise the PSS analysis will properly adjust it.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
harms
\family default
\series default
number of harmonics to be calculated as requested by the user.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
sciter
\family default
\series default
number of allowed shooting cycle iterations.
Default is 50.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
steady_coeff
\family default
\series default
is the weighting coefficient for calculating the Global Convergence Error
(GCE), which is the reference value in order to infer is convergence is
reached.
The lower
\family typewriter
\series bold
steady_coeff
\family default
\series default
is set, the higher the accuracy of predicted frequency can be reached but
at longer analysis time and
\family typewriter
\series bold
sciter
\family default
\series default
number.
Default is 1e-3.
\end_layout
\begin_layout Standard
\family typewriter
\series bold
uic
\family default
\series default
(use initial conditions) is an optional keyword that indicates that the
user does not want ngspice to solve for the quiescent operating point before
beginning the transient analysis.
If this keyword is specified, ngspice uses the values specified using IC=...
on the various elements as the initial transient condition and proceeds
with the analysis.
If the
\family typewriter
.ic
\family default
control line has been specified, then the node voltages on the
\family typewriter
.ic
\family default
line are used to compute the initial conditions for the devices.
Look at the description on the
\family typewriter
.ic
\family default
control line for its interpretation when
\family typewriter
\series bold
uic
\family default
\series default
is not specified.
\end_layout
\begin_layout Section
\begin_inset CommandInset label
LatexCommand label
name "sub:.MEAS"
\end_inset
Measurements after AC, DC and Transient Analysis
\end_layout
\begin_layout Subsection
.meas(ure)
\end_layout
\begin_layout Standard
The
\series bold
.meas
\series default
or
\series bold
.measure
\series default
statement (and its equivalent
\series bold
meas
\series default
command, see Chapt.
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Meas*:-Mesurements-on"
\end_inset
) are used to analyze the output data of a tran, ac, or dc simulation.
The command is executed immediately after the simulation has finished.
\end_layout
\begin_layout Subsection
batch versus interactive mode
\end_layout
\begin_layout Standard
\family typewriter
.meas
\family default
analysis may not be used in batch mode (
\family typewriter
\series bold
-b
\family default
\series default
command line option), if an output file (rawfile) is given at the same
time (
\family typewriter
\series bold
-r
\series default
rawfile
\family default
command line option).
In this batch mode ngspice will write its simulation output data directly
to the output file.
The data is not kept in memory, thus is no longer available for further
analysis.
This is made to allow a very large output stream with only a relatively
small memory usage.
For
\family typewriter
.meas
\family default
to be active you need to run the batch mode with a
\family typewriter
.plot
\family default
or
\family typewriter
.print
\family default
command.
A better alternative may be to start ngspice in interactive mode.
\end_layout
\begin_layout Standard
If you need batch like operation, you may add a
\family typewriter
.control ...
.endc
\family default
section to the input file:
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Example:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
inline false
status open
\begin_layout Plain Layout
*input file
\end_layout
\begin_layout Plain Layout
...
\end_layout
\begin_layout Plain Layout
.tran 1ns 1000ns
\end_layout
\begin_layout Plain Layout
...
\end_layout
\begin_layout Plain Layout
*********************************
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
run
\end_layout
\begin_layout Plain Layout
write outputfile data
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
*********************************
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
and start ngspice in interactive mode, e.g.
by running the command
\end_layout
\begin_layout Standard
\family typewriter
ngspice inputfile
\family default
.
\end_layout
\begin_layout Standard
\family typewriter
.meas
\family default
then prints its user-defined data analysis to the standard output.
The analysis includes propagation, delay, rise time, fall time, peak-to-peak
voltage, minimum or maximum voltage, the integral or derivative over a
specified period and several other user defined values.
\end_layout
\begin_layout Subsection
General remarks
\end_layout
\begin_layout Standard
The measure type
\family typewriter
{DC|AC|TRAN|SP}
\family default
depends on the data that is to be evaluated, either originating from a
dc analysis, an ac analysis, or a transient simulation.
The type
\family typewriter
SP
\family default
to analyze a spectrum from the
\family typewriter
spec
\family default
or
\family typewriter
fft
\family default
commands is only available when executed in a
\family typewriter
meas
\family default
command, see
\begin_inset CommandInset ref
LatexCommand ref
reference "sub:Meas*:-Mesurements-on"
\end_inset
.
\end_layout
\begin_layout Standard
\series bold
result
\series default
will be a vector containing the result of the measurement.
\family typewriter
trig_variable
\family default
,
\family typewriter
targ_variable
\family default
, and
\family typewriter
out_variable
\family default
are vectors stemming from the simulation, e.g.
a voltage vector v(out).
\end_layout
\begin_layout Standard
\family typewriter
VAL
\family default
\series bold
=
\family typewriter
\series default
val
\family default
expects a real number val.
It may be as well a parameter delimited by
\family typewriter
'' or {}
\family default
expanding to a real number.
\end_layout
\begin_layout Standard
\family typewriter
TD
\family default
\series bold
=
\family typewriter
\series default
td
\family default
and
\family typewriter
AT
\family default
\series bold
=
\family typewriter
\series default
time
\family default
expect a time value if measure type is
\family typewriter
tran
\family default
.
For
\family typewriter
ac
\family default
and
\family typewriter
sp
\family default
\family typewriter
AT
\family default
will be a frequency value,
\family typewriter
TD
\family default
is ignored.
For
\family typewriter
dc
\family default
analysis
\family typewriter
AT
\family default
is a voltage (or current),
\family typewriter
TD
\family default
is ignored as well.
\end_layout
\begin_layout Standard
\family typewriter
CROSS
\family default
\series bold
=#
\series default
requires an integer number #.
\family typewriter
CROSS
\family default
\series bold
=
\family typewriter
\series default
LAST
\family default
is possible as well.
The same is expected by
\family typewriter
RISE
\family default
and
\family typewriter
FALL
\family default
.
\end_layout
\begin_layout Standard
Frequency and time values may start at 0 and extend to positive real numbers.
Voltage (or current) inputs for the independent (scale) axis in a dc analysis
may start or end at arbitrary real valued numbers.
\end_layout
\begin_layout Standard
Please note that not all of the
\family typewriter
.measure
\family default
commands have been implemented.
\end_layout
\begin_layout Subsection
Input
\end_layout
\begin_layout Standard
In the following lines you will get some explanation on the
\family typewriter
.measure
\family default
commands.
A simple simulation file with two sines of different frequencies may serve
as an example.
The transient simulation delivers time as the independent variable and
two voltages as output (dependent variables).
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
Input file:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
File: simple-meas-tran.sp
\end_layout
\begin_layout Plain Layout
* Simple .measure examples
\end_layout
\begin_layout Plain Layout
* transient simulation of two sine
\end_layout
\begin_layout Plain Layout
* signals with different frequencies
\end_layout
\begin_layout Plain Layout
vac1 1 0 DC 0 sin(0 1 1k 0 0)
\end_layout
\begin_layout Plain Layout
vac2 2 0 DC 0 sin(0 1.2 0.9k 0 0)
\end_layout
\begin_layout Plain Layout
.tran 10u 5m
\end_layout
\begin_layout Plain Layout
*
\end_layout
\begin_layout Plain Layout
.measure tran ...
$ for the different inputs see below!
\end_layout
\begin_layout Plain Layout
*
\end_layout
\begin_layout Plain Layout
.control
\end_layout
\begin_layout Plain Layout
run
\end_layout
\begin_layout Plain Layout
plot v(1) v(2)
\end_layout
\begin_layout Plain Layout
.endc
\end_layout
\begin_layout Plain Layout
.end
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
After displaying the general syntax of the
\family typewriter
.measure
\family default
statement, some examples are posted, referring to the input file given
above.
\end_layout
\begin_layout Subsection
Trig Targ
\end_layout
\begin_layout Standard
\family typewriter
.measure
\family default
according to general form 1 measures the difference in dc voltage, frequency
or time between two points selected from one or two output vectors.
The current examples all are using transient simulation.
Measurements for
\family typewriter
tran
\family default
analysis start after a delay time td.
If you run other examples with
\family typewriter
ac
\family default
simulation or
\family typewriter
sp
\family default
ectrum analysis, time may be replaced by frequency, after a
\family typewriter
dc
\family default
simulation the independent variable may become a voltage or current.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form 1:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
.MEASURE {DC|AC|TRAN|SP} result TRIG trig_variable VAL=val
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+ TARG targ_variable
\end_layout
\begin_layout Plain Layout
+ VAL=val
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Measure statement example (for use in the input file given above):
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2
\end_layout
\begin_layout Standard
measures the time difference between v(1) reaching 0.5 V for the first time
on its first rising slope (TRIG) versus reaching 0.5 V again on its second
rising slope (TARG), i.e.
it measures the signal period.
\end_layout
\begin_layout Standard
Output:
\end_layout
\begin_layout Standard
\family typewriter
tdiff = 1.000000e-003 targ= 1.083343e-003 trig= 8.334295e-005
\end_layout
\begin_layout Standard
Measure statement example:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3
\end_layout
\begin_layout Standard
measures the time difference between v(1) reaching 0.5 V for the first time
on its rising slope versus reaching 0.5 V on its rising slope for the third
time (i.e.
two periods).
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1
\end_layout
\begin_layout Standard
measures the time difference between v(1) reaching 0.5V for the first time
on its rising slope versus reaching 0.5 V on its first falling slope.
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3
\end_layout
\begin_layout Standard
measures the time difference between v(1) reaching 0V its third falling
slope versus v(2) reaching 0 V on its third falling slope.
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1
\end_layout
\begin_layout Standard
measures the time difference between v(1) crossing -0.6 V for the first time
(any slope) versus v(2) crossing -0.8 V for the first time (any slope).
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3
\end_layout
\begin_layout Standard
measures the time difference between the time point 1ms versus the time
when v(2) crosses -0.8 V for the third time (any slope).
\end_layout
\begin_layout Subsection
Find ...
When
\end_layout
\begin_layout Standard
The
\family typewriter
FIND
\family default
and
\family typewriter
WHEN
\family default
functions allow to measure any dependent or independent time, frequency,
or dc parameter, when two signals cross each other or a signal crosses
a given value.
Measurements start after a delay
\family typewriter
TD
\family default
and may be restricted to a range between
\family typewriter
FROM
\family default
and
\family typewriter
TO
\family default
.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form 2:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
.MEASURE {DC|AC|TRAN|SP} result WHEN out_variable=val
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran teval WHEN v(2)=0.7 CROSS=LAST
\end_layout
\begin_layout Standard
measures the time point when v(2) crosses 0.7 V for the last time (any slope).
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form 3:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
.MEASURE {DC|AC|TRAN|SP} result
\end_layout
\begin_layout Plain Layout
+ WHEN out_variable=out_variable2
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran teval WHEN v(2)=v(1) RISE=LAST
\end_layout
\begin_layout Standard
measures the time point when v(2) and v(1) are equal, v(2) rising for the
last time.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form 4:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
.MEASURE {DC|AC|TRAN|SP} result FIND out_variable
\end_layout
\begin_layout Plain Layout
+ WHEN out_variable2=val
\end_layout
\begin_layout Plain Layout
+
\end_layout
\begin_layout Plain Layout
+
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Measure statement:
\end_layout
\begin_layout Standard
\family typewriter
.measure tran yeval FIND v(2) WHEN v(1)=-0.4 FALL=LAST
\end_layout
\begin_layout Standard
returns the dependent (y) variable drawn from v(2) at the time point when
v(1) equals a value of -0.4, v(1) falling for the last time.
\end_layout
\begin_layout Standard
\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 0
use_makebox 0
width "100col%"
special "none"
height "1in"
height_special "totalheight"
status open
\begin_layout Plain Layout
General form 5:
\end_layout
\begin_layout LyX-Code
\begin_inset listings
lstparams "breaklines=true"
inline false
status open
\begin_layout Plain Layout
.MEASURE {DC|AC|TRAN|SP} result FIND out_variable
\end_layout
\begin_layout Plain Layout
+ WHEN out_variable2=out_variable3
\end_layout
\begin_layout Plain Layout
+ | | | | | | | |